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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
db18b6a6 | 40 | #include "intel_dsi.h" |
e5510fac | 41 | #include "i915_trace.h" |
319c1d42 | 42 | #include <drm/drm_atomic.h> |
c196e1d6 | 43 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
44 | #include <drm/drm_dp_helper.h> |
45 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
46 | #include <drm/drm_plane_helper.h> |
47 | #include <drm/drm_rect.h> | |
c0f372b3 | 48 | #include <linux/dma_remapping.h> |
fd8e058a | 49 | #include <linux/reservation.h> |
79e53945 | 50 | |
5a21b665 DV |
51 | static bool is_mmio_work(struct intel_flip_work *work) |
52 | { | |
53 | return work->mmio_work.func; | |
54 | } | |
55 | ||
465c120c | 56 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 57 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
465c120c | 60 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 61 | DRM_FORMAT_XRGB8888, |
465c120c MR |
62 | }; |
63 | ||
64 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 65 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
66 | DRM_FORMAT_C8, |
67 | DRM_FORMAT_RGB565, | |
68 | DRM_FORMAT_XRGB8888, | |
69 | DRM_FORMAT_XBGR8888, | |
70 | DRM_FORMAT_XRGB2101010, | |
71 | DRM_FORMAT_XBGR2101010, | |
72 | }; | |
73 | ||
74 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
75 | DRM_FORMAT_C8, |
76 | DRM_FORMAT_RGB565, | |
77 | DRM_FORMAT_XRGB8888, | |
465c120c | 78 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 79 | DRM_FORMAT_ARGB8888, |
465c120c MR |
80 | DRM_FORMAT_ABGR8888, |
81 | DRM_FORMAT_XRGB2101010, | |
465c120c | 82 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
83 | DRM_FORMAT_YUYV, |
84 | DRM_FORMAT_YVYU, | |
85 | DRM_FORMAT_UYVY, | |
86 | DRM_FORMAT_VYUY, | |
465c120c MR |
87 | }; |
88 | ||
3d7d6510 MR |
89 | /* Cursor formats */ |
90 | static const uint32_t intel_cursor_formats[] = { | |
91 | DRM_FORMAT_ARGB8888, | |
92 | }; | |
93 | ||
f1f644dc | 94 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 95 | struct intel_crtc_state *pipe_config); |
18442d08 | 96 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 97 | struct intel_crtc_state *pipe_config); |
f1f644dc | 98 | |
eb1bfe80 JB |
99 | static int intel_framebuffer_init(struct drm_device *dev, |
100 | struct intel_framebuffer *ifb, | |
101 | struct drm_mode_fb_cmd2 *mode_cmd, | |
102 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
65edccce VS |
118 | static void skl_init_scalers(struct drm_i915_private *dev_priv, |
119 | struct intel_crtc *crtc, | |
120 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
121 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
122 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
123 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 124 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 125 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 126 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
89b3c3c7 | 127 | static int glk_calc_cdclk(int max_pixclk); |
324513c0 | 128 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 129 | |
d4906093 | 130 | struct intel_limit { |
4c5def93 ACO |
131 | struct { |
132 | int min, max; | |
133 | } dot, vco, n, m, m1, m2, p, p1; | |
134 | ||
135 | struct { | |
136 | int dot_limit; | |
137 | int p2_slow, p2_fast; | |
138 | } p2; | |
d4906093 | 139 | }; |
79e53945 | 140 | |
bfa7df01 VS |
141 | /* returns HPLL frequency in kHz */ |
142 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
143 | { | |
144 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
145 | ||
146 | /* Obtain SKU information */ | |
147 | mutex_lock(&dev_priv->sb_lock); | |
148 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
149 | CCK_FUSE_HPLL_FREQ_MASK; | |
150 | mutex_unlock(&dev_priv->sb_lock); | |
151 | ||
152 | return vco_freq[hpll_freq] * 1000; | |
153 | } | |
154 | ||
c30fec65 VS |
155 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
156 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
157 | { |
158 | u32 val; | |
159 | int divider; | |
160 | ||
bfa7df01 VS |
161 | mutex_lock(&dev_priv->sb_lock); |
162 | val = vlv_cck_read(dev_priv, reg); | |
163 | mutex_unlock(&dev_priv->sb_lock); | |
164 | ||
165 | divider = val & CCK_FREQUENCY_VALUES; | |
166 | ||
167 | WARN((val & CCK_FREQUENCY_STATUS) != | |
168 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
169 | "%s change in progress\n", name); | |
170 | ||
c30fec65 VS |
171 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
172 | } | |
173 | ||
174 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
175 | const char *name, u32 reg) | |
176 | { | |
177 | if (dev_priv->hpll_freq == 0) | |
178 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
179 | ||
180 | return vlv_get_cck_clock(dev_priv, name, reg, | |
181 | dev_priv->hpll_freq); | |
bfa7df01 VS |
182 | } |
183 | ||
e7dc33f3 VS |
184 | static int |
185 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 186 | { |
e7dc33f3 VS |
187 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
188 | } | |
d2acd215 | 189 | |
e7dc33f3 VS |
190 | static int |
191 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
192 | { | |
19ab4ed3 | 193 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
194 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
195 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
196 | } |
197 | ||
e7dc33f3 VS |
198 | static int |
199 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 200 | { |
79e50a4f JN |
201 | uint32_t clkcfg; |
202 | ||
e7dc33f3 | 203 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
204 | clkcfg = I915_READ(CLKCFG); |
205 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
206 | case CLKCFG_FSB_400: | |
e7dc33f3 | 207 | return 100000; |
79e50a4f | 208 | case CLKCFG_FSB_533: |
e7dc33f3 | 209 | return 133333; |
79e50a4f | 210 | case CLKCFG_FSB_667: |
e7dc33f3 | 211 | return 166667; |
79e50a4f | 212 | case CLKCFG_FSB_800: |
e7dc33f3 | 213 | return 200000; |
79e50a4f | 214 | case CLKCFG_FSB_1067: |
e7dc33f3 | 215 | return 266667; |
79e50a4f | 216 | case CLKCFG_FSB_1333: |
e7dc33f3 | 217 | return 333333; |
79e50a4f JN |
218 | /* these two are just a guess; one of them might be right */ |
219 | case CLKCFG_FSB_1600: | |
220 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 221 | return 400000; |
79e50a4f | 222 | default: |
e7dc33f3 | 223 | return 133333; |
79e50a4f JN |
224 | } |
225 | } | |
226 | ||
19ab4ed3 | 227 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
228 | { |
229 | if (HAS_PCH_SPLIT(dev_priv)) | |
230 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
231 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
232 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
233 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
234 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
235 | else | |
236 | return; /* no rawclk on other platforms, or no need to know it */ | |
237 | ||
238 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
239 | } | |
240 | ||
bfa7df01 VS |
241 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
242 | { | |
666a4537 | 243 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
244 | return; |
245 | ||
246 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
247 | CCK_CZ_CLOCK_CONTROL); | |
248 | ||
249 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
250 | } | |
251 | ||
021357ac | 252 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
253 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
254 | const struct intel_crtc_state *pipe_config) | |
021357ac | 255 | { |
21a727b3 VS |
256 | if (HAS_DDI(dev_priv)) |
257 | return pipe_config->port_clock; /* SPLL */ | |
258 | else if (IS_GEN5(dev_priv)) | |
259 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 260 | else |
21a727b3 | 261 | return 270000; |
021357ac CW |
262 | } |
263 | ||
1b6f4958 | 264 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 265 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 266 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 267 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
268 | .m = { .min = 96, .max = 140 }, |
269 | .m1 = { .min = 18, .max = 26 }, | |
270 | .m2 = { .min = 6, .max = 16 }, | |
271 | .p = { .min = 4, .max = 128 }, | |
272 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
273 | .p2 = { .dot_limit = 165000, |
274 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
275 | }; |
276 | ||
1b6f4958 | 277 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 278 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 279 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 280 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
281 | .m = { .min = 96, .max = 140 }, |
282 | .m1 = { .min = 18, .max = 26 }, | |
283 | .m2 = { .min = 6, .max = 16 }, | |
284 | .p = { .min = 4, .max = 128 }, | |
285 | .p1 = { .min = 2, .max = 33 }, | |
286 | .p2 = { .dot_limit = 165000, | |
287 | .p2_slow = 4, .p2_fast = 4 }, | |
288 | }; | |
289 | ||
1b6f4958 | 290 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 291 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 292 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 293 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
294 | .m = { .min = 96, .max = 140 }, |
295 | .m1 = { .min = 18, .max = 26 }, | |
296 | .m2 = { .min = 6, .max = 16 }, | |
297 | .p = { .min = 4, .max = 128 }, | |
298 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
299 | .p2 = { .dot_limit = 165000, |
300 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 301 | }; |
273e27ca | 302 | |
1b6f4958 | 303 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
304 | .dot = { .min = 20000, .max = 400000 }, |
305 | .vco = { .min = 1400000, .max = 2800000 }, | |
306 | .n = { .min = 1, .max = 6 }, | |
307 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
308 | .m1 = { .min = 8, .max = 18 }, |
309 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
310 | .p = { .min = 5, .max = 80 }, |
311 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
312 | .p2 = { .dot_limit = 200000, |
313 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
314 | }; |
315 | ||
1b6f4958 | 316 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
317 | .dot = { .min = 20000, .max = 400000 }, |
318 | .vco = { .min = 1400000, .max = 2800000 }, | |
319 | .n = { .min = 1, .max = 6 }, | |
320 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
321 | .m1 = { .min = 8, .max = 18 }, |
322 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
323 | .p = { .min = 7, .max = 98 }, |
324 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
325 | .p2 = { .dot_limit = 112000, |
326 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
327 | }; |
328 | ||
273e27ca | 329 | |
1b6f4958 | 330 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
331 | .dot = { .min = 25000, .max = 270000 }, |
332 | .vco = { .min = 1750000, .max = 3500000}, | |
333 | .n = { .min = 1, .max = 4 }, | |
334 | .m = { .min = 104, .max = 138 }, | |
335 | .m1 = { .min = 17, .max = 23 }, | |
336 | .m2 = { .min = 5, .max = 11 }, | |
337 | .p = { .min = 10, .max = 30 }, | |
338 | .p1 = { .min = 1, .max = 3}, | |
339 | .p2 = { .dot_limit = 270000, | |
340 | .p2_slow = 10, | |
341 | .p2_fast = 10 | |
044c7c41 | 342 | }, |
e4b36699 KP |
343 | }; |
344 | ||
1b6f4958 | 345 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
346 | .dot = { .min = 22000, .max = 400000 }, |
347 | .vco = { .min = 1750000, .max = 3500000}, | |
348 | .n = { .min = 1, .max = 4 }, | |
349 | .m = { .min = 104, .max = 138 }, | |
350 | .m1 = { .min = 16, .max = 23 }, | |
351 | .m2 = { .min = 5, .max = 11 }, | |
352 | .p = { .min = 5, .max = 80 }, | |
353 | .p1 = { .min = 1, .max = 8}, | |
354 | .p2 = { .dot_limit = 165000, | |
355 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
356 | }; |
357 | ||
1b6f4958 | 358 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
359 | .dot = { .min = 20000, .max = 115000 }, |
360 | .vco = { .min = 1750000, .max = 3500000 }, | |
361 | .n = { .min = 1, .max = 3 }, | |
362 | .m = { .min = 104, .max = 138 }, | |
363 | .m1 = { .min = 17, .max = 23 }, | |
364 | .m2 = { .min = 5, .max = 11 }, | |
365 | .p = { .min = 28, .max = 112 }, | |
366 | .p1 = { .min = 2, .max = 8 }, | |
367 | .p2 = { .dot_limit = 0, | |
368 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 369 | }, |
e4b36699 KP |
370 | }; |
371 | ||
1b6f4958 | 372 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
373 | .dot = { .min = 80000, .max = 224000 }, |
374 | .vco = { .min = 1750000, .max = 3500000 }, | |
375 | .n = { .min = 1, .max = 3 }, | |
376 | .m = { .min = 104, .max = 138 }, | |
377 | .m1 = { .min = 17, .max = 23 }, | |
378 | .m2 = { .min = 5, .max = 11 }, | |
379 | .p = { .min = 14, .max = 42 }, | |
380 | .p1 = { .min = 2, .max = 6 }, | |
381 | .p2 = { .dot_limit = 0, | |
382 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 383 | }, |
e4b36699 KP |
384 | }; |
385 | ||
1b6f4958 | 386 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
387 | .dot = { .min = 20000, .max = 400000}, |
388 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 389 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
390 | .n = { .min = 3, .max = 6 }, |
391 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 392 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
393 | .m1 = { .min = 0, .max = 0 }, |
394 | .m2 = { .min = 0, .max = 254 }, | |
395 | .p = { .min = 5, .max = 80 }, | |
396 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
397 | .p2 = { .dot_limit = 200000, |
398 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
399 | }; |
400 | ||
1b6f4958 | 401 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
402 | .dot = { .min = 20000, .max = 400000 }, |
403 | .vco = { .min = 1700000, .max = 3500000 }, | |
404 | .n = { .min = 3, .max = 6 }, | |
405 | .m = { .min = 2, .max = 256 }, | |
406 | .m1 = { .min = 0, .max = 0 }, | |
407 | .m2 = { .min = 0, .max = 254 }, | |
408 | .p = { .min = 7, .max = 112 }, | |
409 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
410 | .p2 = { .dot_limit = 112000, |
411 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
412 | }; |
413 | ||
273e27ca EA |
414 | /* Ironlake / Sandybridge |
415 | * | |
416 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
417 | * the range value for them is (actual_value - 2). | |
418 | */ | |
1b6f4958 | 419 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
420 | .dot = { .min = 25000, .max = 350000 }, |
421 | .vco = { .min = 1760000, .max = 3510000 }, | |
422 | .n = { .min = 1, .max = 5 }, | |
423 | .m = { .min = 79, .max = 127 }, | |
424 | .m1 = { .min = 12, .max = 22 }, | |
425 | .m2 = { .min = 5, .max = 9 }, | |
426 | .p = { .min = 5, .max = 80 }, | |
427 | .p1 = { .min = 1, .max = 8 }, | |
428 | .p2 = { .dot_limit = 225000, | |
429 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
430 | }; |
431 | ||
1b6f4958 | 432 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
433 | .dot = { .min = 25000, .max = 350000 }, |
434 | .vco = { .min = 1760000, .max = 3510000 }, | |
435 | .n = { .min = 1, .max = 3 }, | |
436 | .m = { .min = 79, .max = 118 }, | |
437 | .m1 = { .min = 12, .max = 22 }, | |
438 | .m2 = { .min = 5, .max = 9 }, | |
439 | .p = { .min = 28, .max = 112 }, | |
440 | .p1 = { .min = 2, .max = 8 }, | |
441 | .p2 = { .dot_limit = 225000, | |
442 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
443 | }; |
444 | ||
1b6f4958 | 445 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
446 | .dot = { .min = 25000, .max = 350000 }, |
447 | .vco = { .min = 1760000, .max = 3510000 }, | |
448 | .n = { .min = 1, .max = 3 }, | |
449 | .m = { .min = 79, .max = 127 }, | |
450 | .m1 = { .min = 12, .max = 22 }, | |
451 | .m2 = { .min = 5, .max = 9 }, | |
452 | .p = { .min = 14, .max = 56 }, | |
453 | .p1 = { .min = 2, .max = 8 }, | |
454 | .p2 = { .dot_limit = 225000, | |
455 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
456 | }; |
457 | ||
273e27ca | 458 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 459 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
460 | .dot = { .min = 25000, .max = 350000 }, |
461 | .vco = { .min = 1760000, .max = 3510000 }, | |
462 | .n = { .min = 1, .max = 2 }, | |
463 | .m = { .min = 79, .max = 126 }, | |
464 | .m1 = { .min = 12, .max = 22 }, | |
465 | .m2 = { .min = 5, .max = 9 }, | |
466 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 467 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
468 | .p2 = { .dot_limit = 225000, |
469 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
470 | }; |
471 | ||
1b6f4958 | 472 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
473 | .dot = { .min = 25000, .max = 350000 }, |
474 | .vco = { .min = 1760000, .max = 3510000 }, | |
475 | .n = { .min = 1, .max = 3 }, | |
476 | .m = { .min = 79, .max = 126 }, | |
477 | .m1 = { .min = 12, .max = 22 }, | |
478 | .m2 = { .min = 5, .max = 9 }, | |
479 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 480 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
481 | .p2 = { .dot_limit = 225000, |
482 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
483 | }; |
484 | ||
1b6f4958 | 485 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
486 | /* |
487 | * These are the data rate limits (measured in fast clocks) | |
488 | * since those are the strictest limits we have. The fast | |
489 | * clock and actual rate limits are more relaxed, so checking | |
490 | * them would make no difference. | |
491 | */ | |
492 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 493 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 494 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
495 | .m1 = { .min = 2, .max = 3 }, |
496 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 497 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 498 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
499 | }; |
500 | ||
1b6f4958 | 501 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
502 | /* |
503 | * These are the data rate limits (measured in fast clocks) | |
504 | * since those are the strictest limits we have. The fast | |
505 | * clock and actual rate limits are more relaxed, so checking | |
506 | * them would make no difference. | |
507 | */ | |
508 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 509 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
510 | .n = { .min = 1, .max = 1 }, |
511 | .m1 = { .min = 2, .max = 2 }, | |
512 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
513 | .p1 = { .min = 2, .max = 4 }, | |
514 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
515 | }; | |
516 | ||
1b6f4958 | 517 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
518 | /* FIXME: find real dot limits */ |
519 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 520 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
521 | .n = { .min = 1, .max = 1 }, |
522 | .m1 = { .min = 2, .max = 2 }, | |
523 | /* FIXME: find real m2 limits */ | |
524 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
525 | .p1 = { .min = 2, .max = 4 }, | |
526 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
527 | }; | |
528 | ||
cdba954e ACO |
529 | static bool |
530 | needs_modeset(struct drm_crtc_state *state) | |
531 | { | |
fc596660 | 532 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
533 | } |
534 | ||
dccbea3b ID |
535 | /* |
536 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
537 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
538 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
539 | * The helpers' return value is the rate of the clock that is fed to the | |
540 | * display engine's pipe which can be the above fast dot clock rate or a | |
541 | * divided-down version of it. | |
542 | */ | |
f2b115e6 | 543 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 544 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 545 | { |
2177832f SL |
546 | clock->m = clock->m2 + 2; |
547 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 548 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 549 | return 0; |
fb03ac01 VS |
550 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
551 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
552 | |
553 | return clock->dot; | |
2177832f SL |
554 | } |
555 | ||
7429e9d4 DV |
556 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
557 | { | |
558 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
559 | } | |
560 | ||
9e2c8475 | 561 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 562 | { |
7429e9d4 | 563 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 564 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 565 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 566 | return 0; |
fb03ac01 VS |
567 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
568 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
569 | |
570 | return clock->dot; | |
79e53945 JB |
571 | } |
572 | ||
9e2c8475 | 573 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
574 | { |
575 | clock->m = clock->m1 * clock->m2; | |
576 | clock->p = clock->p1 * clock->p2; | |
577 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 578 | return 0; |
589eca67 ID |
579 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
580 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
581 | |
582 | return clock->dot / 5; | |
589eca67 ID |
583 | } |
584 | ||
9e2c8475 | 585 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
586 | { |
587 | clock->m = clock->m1 * clock->m2; | |
588 | clock->p = clock->p1 * clock->p2; | |
589 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 590 | return 0; |
ef9348c8 CML |
591 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
592 | clock->n << 22); | |
593 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
594 | |
595 | return clock->dot / 5; | |
ef9348c8 CML |
596 | } |
597 | ||
7c04d1d9 | 598 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
599 | /** |
600 | * Returns whether the given set of divisors are valid for a given refclk with | |
601 | * the given connectors. | |
602 | */ | |
603 | ||
e2d214ae | 604 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 605 | const struct intel_limit *limit, |
9e2c8475 | 606 | const struct dpll *clock) |
79e53945 | 607 | { |
f01b7962 VS |
608 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
609 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 610 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 611 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 612 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 613 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 614 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 615 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 616 | |
e2d214ae | 617 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 618 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
619 | if (clock->m1 <= clock->m2) |
620 | INTELPllInvalid("m1 <= m2\n"); | |
621 | ||
e2d214ae | 622 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 623 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
624 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
625 | INTELPllInvalid("p out of range\n"); | |
626 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
627 | INTELPllInvalid("m out of range\n"); | |
628 | } | |
629 | ||
79e53945 | 630 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 631 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
632 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
633 | * connector, etc., rather than just a single range. | |
634 | */ | |
635 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 636 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
637 | |
638 | return true; | |
639 | } | |
640 | ||
3b1429d9 | 641 | static int |
1b6f4958 | 642 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
643 | const struct intel_crtc_state *crtc_state, |
644 | int target) | |
79e53945 | 645 | { |
3b1429d9 | 646 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 647 | |
2d84d2b3 | 648 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 649 | /* |
a210b028 DV |
650 | * For LVDS just rely on its current settings for dual-channel. |
651 | * We haven't figured out how to reliably set up different | |
652 | * single/dual channel state, if we even can. | |
79e53945 | 653 | */ |
1974cad0 | 654 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 655 | return limit->p2.p2_fast; |
79e53945 | 656 | else |
3b1429d9 | 657 | return limit->p2.p2_slow; |
79e53945 JB |
658 | } else { |
659 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 660 | return limit->p2.p2_slow; |
79e53945 | 661 | else |
3b1429d9 | 662 | return limit->p2.p2_fast; |
79e53945 | 663 | } |
3b1429d9 VS |
664 | } |
665 | ||
70e8aa21 ACO |
666 | /* |
667 | * Returns a set of divisors for the desired target clock with the given | |
668 | * refclk, or FALSE. The returned values represent the clock equation: | |
669 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
670 | * | |
671 | * Target and reference clocks are specified in kHz. | |
672 | * | |
673 | * If match_clock is provided, then best_clock P divider must match the P | |
674 | * divider from @match_clock used for LVDS downclocking. | |
675 | */ | |
3b1429d9 | 676 | static bool |
1b6f4958 | 677 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 678 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
679 | int target, int refclk, struct dpll *match_clock, |
680 | struct dpll *best_clock) | |
3b1429d9 VS |
681 | { |
682 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 683 | struct dpll clock; |
3b1429d9 | 684 | int err = target; |
79e53945 | 685 | |
0206e353 | 686 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 687 | |
3b1429d9 VS |
688 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
689 | ||
42158660 ZY |
690 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
691 | clock.m1++) { | |
692 | for (clock.m2 = limit->m2.min; | |
693 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 694 | if (clock.m2 >= clock.m1) |
42158660 ZY |
695 | break; |
696 | for (clock.n = limit->n.min; | |
697 | clock.n <= limit->n.max; clock.n++) { | |
698 | for (clock.p1 = limit->p1.min; | |
699 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
700 | int this_err; |
701 | ||
dccbea3b | 702 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
703 | if (!intel_PLL_is_valid(to_i915(dev), |
704 | limit, | |
ac58c3f0 DV |
705 | &clock)) |
706 | continue; | |
707 | if (match_clock && | |
708 | clock.p != match_clock->p) | |
709 | continue; | |
710 | ||
711 | this_err = abs(clock.dot - target); | |
712 | if (this_err < err) { | |
713 | *best_clock = clock; | |
714 | err = this_err; | |
715 | } | |
716 | } | |
717 | } | |
718 | } | |
719 | } | |
720 | ||
721 | return (err != target); | |
722 | } | |
723 | ||
70e8aa21 ACO |
724 | /* |
725 | * Returns a set of divisors for the desired target clock with the given | |
726 | * refclk, or FALSE. The returned values represent the clock equation: | |
727 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
728 | * | |
729 | * Target and reference clocks are specified in kHz. | |
730 | * | |
731 | * If match_clock is provided, then best_clock P divider must match the P | |
732 | * divider from @match_clock used for LVDS downclocking. | |
733 | */ | |
ac58c3f0 | 734 | static bool |
1b6f4958 | 735 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 736 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
737 | int target, int refclk, struct dpll *match_clock, |
738 | struct dpll *best_clock) | |
79e53945 | 739 | { |
3b1429d9 | 740 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 741 | struct dpll clock; |
79e53945 JB |
742 | int err = target; |
743 | ||
0206e353 | 744 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 745 | |
3b1429d9 VS |
746 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
747 | ||
42158660 ZY |
748 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
749 | clock.m1++) { | |
750 | for (clock.m2 = limit->m2.min; | |
751 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
752 | for (clock.n = limit->n.min; |
753 | clock.n <= limit->n.max; clock.n++) { | |
754 | for (clock.p1 = limit->p1.min; | |
755 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
756 | int this_err; |
757 | ||
dccbea3b | 758 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
759 | if (!intel_PLL_is_valid(to_i915(dev), |
760 | limit, | |
1b894b59 | 761 | &clock)) |
79e53945 | 762 | continue; |
cec2f356 SP |
763 | if (match_clock && |
764 | clock.p != match_clock->p) | |
765 | continue; | |
79e53945 JB |
766 | |
767 | this_err = abs(clock.dot - target); | |
768 | if (this_err < err) { | |
769 | *best_clock = clock; | |
770 | err = this_err; | |
771 | } | |
772 | } | |
773 | } | |
774 | } | |
775 | } | |
776 | ||
777 | return (err != target); | |
778 | } | |
779 | ||
997c030c ACO |
780 | /* |
781 | * Returns a set of divisors for the desired target clock with the given | |
782 | * refclk, or FALSE. The returned values represent the clock equation: | |
783 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
784 | * |
785 | * Target and reference clocks are specified in kHz. | |
786 | * | |
787 | * If match_clock is provided, then best_clock P divider must match the P | |
788 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 789 | */ |
d4906093 | 790 | static bool |
1b6f4958 | 791 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 792 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
793 | int target, int refclk, struct dpll *match_clock, |
794 | struct dpll *best_clock) | |
d4906093 | 795 | { |
3b1429d9 | 796 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 797 | struct dpll clock; |
d4906093 | 798 | int max_n; |
3b1429d9 | 799 | bool found = false; |
6ba770dc AJ |
800 | /* approximately equals target * 0.00585 */ |
801 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
802 | |
803 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
804 | |
805 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
806 | ||
d4906093 | 807 | max_n = limit->n.max; |
f77f13e2 | 808 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 809 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 810 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
811 | for (clock.m1 = limit->m1.max; |
812 | clock.m1 >= limit->m1.min; clock.m1--) { | |
813 | for (clock.m2 = limit->m2.max; | |
814 | clock.m2 >= limit->m2.min; clock.m2--) { | |
815 | for (clock.p1 = limit->p1.max; | |
816 | clock.p1 >= limit->p1.min; clock.p1--) { | |
817 | int this_err; | |
818 | ||
dccbea3b | 819 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
820 | if (!intel_PLL_is_valid(to_i915(dev), |
821 | limit, | |
1b894b59 | 822 | &clock)) |
d4906093 | 823 | continue; |
1b894b59 CW |
824 | |
825 | this_err = abs(clock.dot - target); | |
d4906093 ML |
826 | if (this_err < err_most) { |
827 | *best_clock = clock; | |
828 | err_most = this_err; | |
829 | max_n = clock.n; | |
830 | found = true; | |
831 | } | |
832 | } | |
833 | } | |
834 | } | |
835 | } | |
2c07245f ZW |
836 | return found; |
837 | } | |
838 | ||
d5dd62bd ID |
839 | /* |
840 | * Check if the calculated PLL configuration is more optimal compared to the | |
841 | * best configuration and error found so far. Return the calculated error. | |
842 | */ | |
843 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
844 | const struct dpll *calculated_clock, |
845 | const struct dpll *best_clock, | |
d5dd62bd ID |
846 | unsigned int best_error_ppm, |
847 | unsigned int *error_ppm) | |
848 | { | |
9ca3ba01 ID |
849 | /* |
850 | * For CHV ignore the error and consider only the P value. | |
851 | * Prefer a bigger P value based on HW requirements. | |
852 | */ | |
920a14b2 | 853 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
854 | *error_ppm = 0; |
855 | ||
856 | return calculated_clock->p > best_clock->p; | |
857 | } | |
858 | ||
24be4e46 ID |
859 | if (WARN_ON_ONCE(!target_freq)) |
860 | return false; | |
861 | ||
d5dd62bd ID |
862 | *error_ppm = div_u64(1000000ULL * |
863 | abs(target_freq - calculated_clock->dot), | |
864 | target_freq); | |
865 | /* | |
866 | * Prefer a better P value over a better (smaller) error if the error | |
867 | * is small. Ensure this preference for future configurations too by | |
868 | * setting the error to 0. | |
869 | */ | |
870 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
871 | *error_ppm = 0; | |
872 | ||
873 | return true; | |
874 | } | |
875 | ||
876 | return *error_ppm + 10 < best_error_ppm; | |
877 | } | |
878 | ||
65b3d6a9 ACO |
879 | /* |
880 | * Returns a set of divisors for the desired target clock with the given | |
881 | * refclk, or FALSE. The returned values represent the clock equation: | |
882 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
883 | */ | |
a0c4da24 | 884 | static bool |
1b6f4958 | 885 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 886 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
887 | int target, int refclk, struct dpll *match_clock, |
888 | struct dpll *best_clock) | |
a0c4da24 | 889 | { |
a93e255f | 890 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 891 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 892 | struct dpll clock; |
69e4f900 | 893 | unsigned int bestppm = 1000000; |
27e639bf VS |
894 | /* min update 19.2 MHz */ |
895 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 896 | bool found = false; |
a0c4da24 | 897 | |
6b4bf1c4 VS |
898 | target *= 5; /* fast clock */ |
899 | ||
900 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
901 | |
902 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 903 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 904 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 905 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 906 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 907 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 908 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 909 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 910 | unsigned int ppm; |
69e4f900 | 911 | |
6b4bf1c4 VS |
912 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
913 | refclk * clock.m1); | |
914 | ||
dccbea3b | 915 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 916 | |
e2d214ae TU |
917 | if (!intel_PLL_is_valid(to_i915(dev), |
918 | limit, | |
f01b7962 | 919 | &clock)) |
43b0ac53 VS |
920 | continue; |
921 | ||
d5dd62bd ID |
922 | if (!vlv_PLL_is_optimal(dev, target, |
923 | &clock, | |
924 | best_clock, | |
925 | bestppm, &ppm)) | |
926 | continue; | |
6b4bf1c4 | 927 | |
d5dd62bd ID |
928 | *best_clock = clock; |
929 | bestppm = ppm; | |
930 | found = true; | |
a0c4da24 JB |
931 | } |
932 | } | |
933 | } | |
934 | } | |
a0c4da24 | 935 | |
49e497ef | 936 | return found; |
a0c4da24 | 937 | } |
a4fc5ed6 | 938 | |
65b3d6a9 ACO |
939 | /* |
940 | * Returns a set of divisors for the desired target clock with the given | |
941 | * refclk, or FALSE. The returned values represent the clock equation: | |
942 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
943 | */ | |
ef9348c8 | 944 | static bool |
1b6f4958 | 945 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 946 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
947 | int target, int refclk, struct dpll *match_clock, |
948 | struct dpll *best_clock) | |
ef9348c8 | 949 | { |
a93e255f | 950 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 951 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 952 | unsigned int best_error_ppm; |
9e2c8475 | 953 | struct dpll clock; |
ef9348c8 CML |
954 | uint64_t m2; |
955 | int found = false; | |
956 | ||
957 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 958 | best_error_ppm = 1000000; |
ef9348c8 CML |
959 | |
960 | /* | |
961 | * Based on hardware doc, the n always set to 1, and m1 always | |
962 | * set to 2. If requires to support 200Mhz refclk, we need to | |
963 | * revisit this because n may not 1 anymore. | |
964 | */ | |
965 | clock.n = 1, clock.m1 = 2; | |
966 | target *= 5; /* fast clock */ | |
967 | ||
968 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
969 | for (clock.p2 = limit->p2.p2_fast; | |
970 | clock.p2 >= limit->p2.p2_slow; | |
971 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 972 | unsigned int error_ppm; |
ef9348c8 CML |
973 | |
974 | clock.p = clock.p1 * clock.p2; | |
975 | ||
976 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
977 | clock.n) << 22, refclk * clock.m1); | |
978 | ||
979 | if (m2 > INT_MAX/clock.m1) | |
980 | continue; | |
981 | ||
982 | clock.m2 = m2; | |
983 | ||
dccbea3b | 984 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 985 | |
e2d214ae | 986 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
987 | continue; |
988 | ||
9ca3ba01 ID |
989 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
990 | best_error_ppm, &error_ppm)) | |
991 | continue; | |
992 | ||
993 | *best_clock = clock; | |
994 | best_error_ppm = error_ppm; | |
995 | found = true; | |
ef9348c8 CML |
996 | } |
997 | } | |
998 | ||
999 | return found; | |
1000 | } | |
1001 | ||
5ab7b0b7 | 1002 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 1003 | struct dpll *best_clock) |
5ab7b0b7 | 1004 | { |
65b3d6a9 | 1005 | int refclk = 100000; |
1b6f4958 | 1006 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1007 | |
65b3d6a9 | 1008 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1009 | target_clock, refclk, NULL, best_clock); |
1010 | } | |
1011 | ||
525b9311 | 1012 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 1013 | { |
20ddf665 VS |
1014 | /* Be paranoid as we can arrive here with only partial |
1015 | * state retrieved from the hardware during setup. | |
1016 | * | |
241bfc38 | 1017 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1018 | * as Haswell has gained clock readout/fastboot support. |
1019 | * | |
66e514c1 | 1020 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1021 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1022 | * |
1023 | * FIXME: The intel_crtc->active here should be switched to | |
1024 | * crtc->state->active once we have proper CRTC states wired up | |
1025 | * for atomic. | |
20ddf665 | 1026 | */ |
525b9311 VS |
1027 | return crtc->active && crtc->base.primary->state->fb && |
1028 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
1029 | } |
1030 | ||
a5c961d1 PZ |
1031 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1032 | enum pipe pipe) | |
1033 | { | |
98187836 | 1034 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 1035 | |
e2af48c6 | 1036 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1037 | } |
1038 | ||
6315b5d3 | 1039 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 1040 | { |
f0f59a00 | 1041 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1042 | u32 line1, line2; |
1043 | u32 line_mask; | |
1044 | ||
5db94019 | 1045 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
1046 | line_mask = DSL_LINEMASK_GEN2; |
1047 | else | |
1048 | line_mask = DSL_LINEMASK_GEN3; | |
1049 | ||
1050 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1051 | msleep(5); |
fbf49ea2 VS |
1052 | line2 = I915_READ(reg) & line_mask; |
1053 | ||
1054 | return line1 == line2; | |
1055 | } | |
1056 | ||
ab7ad7f6 KP |
1057 | /* |
1058 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1059 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1060 | * |
1061 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1062 | * spinning on the vblank interrupt status bit, since we won't actually | |
1063 | * see an interrupt when the pipe is disabled. | |
1064 | * | |
ab7ad7f6 KP |
1065 | * On Gen4 and above: |
1066 | * wait for the pipe register state bit to turn off | |
1067 | * | |
1068 | * Otherwise: | |
1069 | * wait for the display line value to settle (it usually | |
1070 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1071 | * |
9d0498a2 | 1072 | */ |
575f7ab7 | 1073 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1074 | { |
6315b5d3 | 1075 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1076 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1077 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1078 | |
6315b5d3 | 1079 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1080 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1081 | |
1082 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1083 | if (intel_wait_for_register(dev_priv, |
1084 | reg, I965_PIPECONF_ACTIVE, 0, | |
1085 | 100)) | |
284637d9 | 1086 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1087 | } else { |
ab7ad7f6 | 1088 | /* Wait for the display line to settle */ |
6315b5d3 | 1089 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1090 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1091 | } |
79e53945 JB |
1092 | } |
1093 | ||
b24e7179 | 1094 | /* Only for pre-ILK configs */ |
55607e8a DV |
1095 | void assert_pll(struct drm_i915_private *dev_priv, |
1096 | enum pipe pipe, bool state) | |
b24e7179 | 1097 | { |
b24e7179 JB |
1098 | u32 val; |
1099 | bool cur_state; | |
1100 | ||
649636ef | 1101 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1102 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1103 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1104 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1105 | onoff(state), onoff(cur_state)); |
b24e7179 | 1106 | } |
b24e7179 | 1107 | |
23538ef1 | 1108 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1109 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1110 | { |
1111 | u32 val; | |
1112 | bool cur_state; | |
1113 | ||
a580516d | 1114 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1115 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1116 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1117 | |
1118 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1119 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1120 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1121 | onoff(state), onoff(cur_state)); |
23538ef1 | 1122 | } |
23538ef1 | 1123 | |
040484af JB |
1124 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1125 | enum pipe pipe, bool state) | |
1126 | { | |
040484af | 1127 | bool cur_state; |
ad80a810 PZ |
1128 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1129 | pipe); | |
040484af | 1130 | |
2d1fe073 | 1131 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1132 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1133 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1134 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1135 | } else { |
649636ef | 1136 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1137 | cur_state = !!(val & FDI_TX_ENABLE); |
1138 | } | |
e2c719b7 | 1139 | I915_STATE_WARN(cur_state != state, |
040484af | 1140 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1141 | onoff(state), onoff(cur_state)); |
040484af JB |
1142 | } |
1143 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1144 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1145 | ||
1146 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1147 | enum pipe pipe, bool state) | |
1148 | { | |
040484af JB |
1149 | u32 val; |
1150 | bool cur_state; | |
1151 | ||
649636ef | 1152 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1153 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1154 | I915_STATE_WARN(cur_state != state, |
040484af | 1155 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1156 | onoff(state), onoff(cur_state)); |
040484af JB |
1157 | } |
1158 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1159 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1160 | ||
1161 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1162 | enum pipe pipe) | |
1163 | { | |
040484af JB |
1164 | u32 val; |
1165 | ||
1166 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1167 | if (IS_GEN5(dev_priv)) |
040484af JB |
1168 | return; |
1169 | ||
bf507ef7 | 1170 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1171 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1172 | return; |
1173 | ||
649636ef | 1174 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1175 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1176 | } |
1177 | ||
55607e8a DV |
1178 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1179 | enum pipe pipe, bool state) | |
040484af | 1180 | { |
040484af | 1181 | u32 val; |
55607e8a | 1182 | bool cur_state; |
040484af | 1183 | |
649636ef | 1184 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1185 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1186 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1187 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1188 | onoff(state), onoff(cur_state)); |
040484af JB |
1189 | } |
1190 | ||
4f8036a2 | 1191 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1192 | { |
f0f59a00 | 1193 | i915_reg_t pp_reg; |
ea0760cf JB |
1194 | u32 val; |
1195 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1196 | bool locked = true; |
ea0760cf | 1197 | |
4f8036a2 | 1198 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1199 | return; |
1200 | ||
4f8036a2 | 1201 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1202 | u32 port_sel; |
1203 | ||
44cb734c ID |
1204 | pp_reg = PP_CONTROL(0); |
1205 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1206 | |
1207 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1208 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1209 | panel_pipe = PIPE_B; | |
1210 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1211 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1212 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1213 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1214 | panel_pipe = pipe; |
ea0760cf | 1215 | } else { |
44cb734c | 1216 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1217 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1218 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1219 | } |
1220 | ||
1221 | val = I915_READ(pp_reg); | |
1222 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1223 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1224 | locked = false; |
1225 | ||
e2c719b7 | 1226 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1227 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1228 | pipe_name(pipe)); |
ea0760cf JB |
1229 | } |
1230 | ||
93ce0ba6 JN |
1231 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1232 | enum pipe pipe, bool state) | |
1233 | { | |
93ce0ba6 JN |
1234 | bool cur_state; |
1235 | ||
2a307c2e | 1236 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1237 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1238 | else |
5efb3e28 | 1239 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1240 | |
e2c719b7 | 1241 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1242 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1243 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1244 | } |
1245 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1246 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1247 | ||
b840d907 JB |
1248 | void assert_pipe(struct drm_i915_private *dev_priv, |
1249 | enum pipe pipe, bool state) | |
b24e7179 | 1250 | { |
63d7bbe9 | 1251 | bool cur_state; |
702e7a56 PZ |
1252 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1253 | pipe); | |
4feed0eb | 1254 | enum intel_display_power_domain power_domain; |
b24e7179 | 1255 | |
b6b5d049 VS |
1256 | /* if we need the pipe quirk it must be always on */ |
1257 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1258 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1259 | state = true; |
1260 | ||
4feed0eb ID |
1261 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1262 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1263 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1264 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1265 | |
1266 | intel_display_power_put(dev_priv, power_domain); | |
1267 | } else { | |
1268 | cur_state = false; | |
69310161 PZ |
1269 | } |
1270 | ||
e2c719b7 | 1271 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1272 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1273 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1274 | } |
1275 | ||
931872fc CW |
1276 | static void assert_plane(struct drm_i915_private *dev_priv, |
1277 | enum plane plane, bool state) | |
b24e7179 | 1278 | { |
b24e7179 | 1279 | u32 val; |
931872fc | 1280 | bool cur_state; |
b24e7179 | 1281 | |
649636ef | 1282 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1283 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1284 | I915_STATE_WARN(cur_state != state, |
931872fc | 1285 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1286 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1287 | } |
1288 | ||
931872fc CW |
1289 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1290 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1291 | ||
b24e7179 JB |
1292 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1293 | enum pipe pipe) | |
1294 | { | |
649636ef | 1295 | int i; |
b24e7179 | 1296 | |
653e1026 | 1297 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1298 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1299 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1300 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1301 | "plane %c assertion failure, should be disabled but not\n", |
1302 | plane_name(pipe)); | |
19ec1358 | 1303 | return; |
28c05794 | 1304 | } |
19ec1358 | 1305 | |
b24e7179 | 1306 | /* Need to check both planes against the pipe */ |
055e393f | 1307 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1308 | u32 val = I915_READ(DSPCNTR(i)); |
1309 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1310 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1311 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1312 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1313 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1314 | } |
1315 | } | |
1316 | ||
19332d7a JB |
1317 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1318 | enum pipe pipe) | |
1319 | { | |
649636ef | 1320 | int sprite; |
19332d7a | 1321 | |
6315b5d3 | 1322 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1323 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1324 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1325 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1326 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1327 | sprite, pipe_name(pipe)); | |
1328 | } | |
920a14b2 | 1329 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1330 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1331 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1332 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1333 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1334 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1335 | } |
6315b5d3 | 1336 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1337 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1338 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1339 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1340 | plane_name(pipe), pipe_name(pipe)); |
6315b5d3 | 1341 | } else if (INTEL_GEN(dev_priv) >= 5) { |
649636ef | 1342 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1343 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1344 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1345 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1346 | } |
1347 | } | |
1348 | ||
08c71e5e VS |
1349 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1350 | { | |
e2c719b7 | 1351 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1352 | drm_crtc_vblank_put(crtc); |
1353 | } | |
1354 | ||
7abd4b35 ACO |
1355 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1356 | enum pipe pipe) | |
92f2584a | 1357 | { |
92f2584a JB |
1358 | u32 val; |
1359 | bool enabled; | |
1360 | ||
649636ef | 1361 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1362 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1363 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1364 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1365 | pipe_name(pipe)); | |
92f2584a JB |
1366 | } |
1367 | ||
4e634389 KP |
1368 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1369 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1370 | { |
1371 | if ((val & DP_PORT_EN) == 0) | |
1372 | return false; | |
1373 | ||
2d1fe073 | 1374 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1375 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1376 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1377 | return false; | |
2d1fe073 | 1378 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1379 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1380 | return false; | |
f0575e92 KP |
1381 | } else { |
1382 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1383 | return false; | |
1384 | } | |
1385 | return true; | |
1386 | } | |
1387 | ||
1519b995 KP |
1388 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1389 | enum pipe pipe, u32 val) | |
1390 | { | |
dc0fa718 | 1391 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1392 | return false; |
1393 | ||
2d1fe073 | 1394 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1395 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1396 | return false; |
2d1fe073 | 1397 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1398 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1399 | return false; | |
1519b995 | 1400 | } else { |
dc0fa718 | 1401 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1402 | return false; |
1403 | } | |
1404 | return true; | |
1405 | } | |
1406 | ||
1407 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1408 | enum pipe pipe, u32 val) | |
1409 | { | |
1410 | if ((val & LVDS_PORT_EN) == 0) | |
1411 | return false; | |
1412 | ||
2d1fe073 | 1413 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1414 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1415 | return false; | |
1416 | } else { | |
1417 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1418 | return false; | |
1419 | } | |
1420 | return true; | |
1421 | } | |
1422 | ||
1423 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1424 | enum pipe pipe, u32 val) | |
1425 | { | |
1426 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1427 | return false; | |
2d1fe073 | 1428 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1429 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1430 | return false; | |
1431 | } else { | |
1432 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1433 | return false; | |
1434 | } | |
1435 | return true; | |
1436 | } | |
1437 | ||
291906f1 | 1438 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1439 | enum pipe pipe, i915_reg_t reg, |
1440 | u32 port_sel) | |
291906f1 | 1441 | { |
47a05eca | 1442 | u32 val = I915_READ(reg); |
e2c719b7 | 1443 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1444 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1445 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1446 | |
2d1fe073 | 1447 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1448 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1449 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1450 | } |
1451 | ||
1452 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1453 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1454 | { |
47a05eca | 1455 | u32 val = I915_READ(reg); |
e2c719b7 | 1456 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1457 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1458 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1459 | |
2d1fe073 | 1460 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1461 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1462 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1463 | } |
1464 | ||
1465 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1466 | enum pipe pipe) | |
1467 | { | |
291906f1 | 1468 | u32 val; |
291906f1 | 1469 | |
f0575e92 KP |
1470 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1471 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1472 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1473 | |
649636ef | 1474 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1475 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1476 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1477 | pipe_name(pipe)); |
291906f1 | 1478 | |
649636ef | 1479 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1480 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1481 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1482 | pipe_name(pipe)); |
291906f1 | 1483 | |
e2debe91 PZ |
1484 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1485 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1486 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1487 | } |
1488 | ||
cd2d34d9 VS |
1489 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1490 | const struct intel_crtc_state *pipe_config) | |
1491 | { | |
1492 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1493 | enum pipe pipe = crtc->pipe; | |
1494 | ||
1495 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1496 | POSTING_READ(DPLL(pipe)); | |
1497 | udelay(150); | |
1498 | ||
2c30b43b CW |
1499 | if (intel_wait_for_register(dev_priv, |
1500 | DPLL(pipe), | |
1501 | DPLL_LOCK_VLV, | |
1502 | DPLL_LOCK_VLV, | |
1503 | 1)) | |
cd2d34d9 VS |
1504 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1505 | } | |
1506 | ||
d288f65f | 1507 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1508 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1509 | { |
cd2d34d9 | 1510 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1511 | enum pipe pipe = crtc->pipe; |
87442f73 | 1512 | |
8bd3f301 | 1513 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1514 | |
87442f73 | 1515 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1516 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1517 | |
cd2d34d9 VS |
1518 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1519 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1520 | |
8bd3f301 VS |
1521 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1522 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1523 | } |
1524 | ||
cd2d34d9 VS |
1525 | |
1526 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1527 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1528 | { |
cd2d34d9 | 1529 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1530 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1531 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1532 | u32 tmp; |
1533 | ||
a580516d | 1534 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1535 | |
1536 | /* Enable back the 10bit clock to display controller */ | |
1537 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1538 | tmp |= DPIO_DCLKP_EN; | |
1539 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1540 | ||
54433e91 VS |
1541 | mutex_unlock(&dev_priv->sb_lock); |
1542 | ||
9d556c99 CML |
1543 | /* |
1544 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1545 | */ | |
1546 | udelay(1); | |
1547 | ||
1548 | /* Enable PLL */ | |
d288f65f | 1549 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1550 | |
1551 | /* Check PLL is locked */ | |
6b18826a CW |
1552 | if (intel_wait_for_register(dev_priv, |
1553 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1554 | 1)) | |
9d556c99 | 1555 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1556 | } |
1557 | ||
1558 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1559 | const struct intel_crtc_state *pipe_config) | |
1560 | { | |
1561 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1562 | enum pipe pipe = crtc->pipe; | |
1563 | ||
1564 | assert_pipe_disabled(dev_priv, pipe); | |
1565 | ||
1566 | /* PLL is protected by panel, make sure we can write it */ | |
1567 | assert_panel_unlocked(dev_priv, pipe); | |
1568 | ||
1569 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1570 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1571 | |
c231775c VS |
1572 | if (pipe != PIPE_A) { |
1573 | /* | |
1574 | * WaPixelRepeatModeFixForC0:chv | |
1575 | * | |
1576 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1577 | * the value from DPLLBMD to either pipe B or C. | |
1578 | */ | |
1579 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1580 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1581 | I915_WRITE(CBR4_VLV, 0); | |
1582 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1583 | ||
1584 | /* | |
1585 | * DPLLB VGA mode also seems to cause problems. | |
1586 | * We should always have it disabled. | |
1587 | */ | |
1588 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1589 | } else { | |
1590 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1591 | POSTING_READ(DPLL_MD(pipe)); | |
1592 | } | |
9d556c99 CML |
1593 | } |
1594 | ||
6315b5d3 | 1595 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1596 | { |
1597 | struct intel_crtc *crtc; | |
1598 | int count = 0; | |
1599 | ||
6315b5d3 | 1600 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1601 | count += crtc->base.state->active && |
2d84d2b3 VS |
1602 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1603 | } | |
1c4e0274 VS |
1604 | |
1605 | return count; | |
1606 | } | |
1607 | ||
66e3d5c0 | 1608 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1609 | { |
6315b5d3 | 1610 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1611 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1612 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1613 | |
66e3d5c0 | 1614 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1615 | |
63d7bbe9 | 1616 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1617 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1618 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1619 | |
1c4e0274 | 1620 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1621 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1622 | /* |
1623 | * It appears to be important that we don't enable this | |
1624 | * for the current pipe before otherwise configuring the | |
1625 | * PLL. No idea how this should be handled if multiple | |
1626 | * DVO outputs are enabled simultaneosly. | |
1627 | */ | |
1628 | dpll |= DPLL_DVO_2X_MODE; | |
1629 | I915_WRITE(DPLL(!crtc->pipe), | |
1630 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1631 | } | |
66e3d5c0 | 1632 | |
c2b63374 VS |
1633 | /* |
1634 | * Apparently we need to have VGA mode enabled prior to changing | |
1635 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1636 | * dividers, even though the register value does change. | |
1637 | */ | |
1638 | I915_WRITE(reg, 0); | |
1639 | ||
8e7a65aa VS |
1640 | I915_WRITE(reg, dpll); |
1641 | ||
66e3d5c0 DV |
1642 | /* Wait for the clocks to stabilize. */ |
1643 | POSTING_READ(reg); | |
1644 | udelay(150); | |
1645 | ||
6315b5d3 | 1646 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1647 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1648 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1649 | } else { |
1650 | /* The pixel multiplier can only be updated once the | |
1651 | * DPLL is enabled and the clocks are stable. | |
1652 | * | |
1653 | * So write it again. | |
1654 | */ | |
1655 | I915_WRITE(reg, dpll); | |
1656 | } | |
63d7bbe9 JB |
1657 | |
1658 | /* We do this three times for luck */ | |
66e3d5c0 | 1659 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1660 | POSTING_READ(reg); |
1661 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1662 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1663 | POSTING_READ(reg); |
1664 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1665 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1666 | POSTING_READ(reg); |
1667 | udelay(150); /* wait for warmup */ | |
1668 | } | |
1669 | ||
1670 | /** | |
50b44a44 | 1671 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1672 | * @dev_priv: i915 private structure |
1673 | * @pipe: pipe PLL to disable | |
1674 | * | |
1675 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1676 | * | |
1677 | * Note! This is for pre-ILK only. | |
1678 | */ | |
1c4e0274 | 1679 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1680 | { |
6315b5d3 | 1681 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1682 | enum pipe pipe = crtc->pipe; |
1683 | ||
1684 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1685 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1686 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1687 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1688 | I915_WRITE(DPLL(PIPE_B), |
1689 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1690 | I915_WRITE(DPLL(PIPE_A), | |
1691 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1692 | } | |
1693 | ||
b6b5d049 VS |
1694 | /* Don't disable pipe or pipe PLLs if needed */ |
1695 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1696 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1697 | return; |
1698 | ||
1699 | /* Make sure the pipe isn't still relying on us */ | |
1700 | assert_pipe_disabled(dev_priv, pipe); | |
1701 | ||
b8afb911 | 1702 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1703 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1704 | } |
1705 | ||
f6071166 JB |
1706 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1707 | { | |
b8afb911 | 1708 | u32 val; |
f6071166 JB |
1709 | |
1710 | /* Make sure the pipe isn't still relying on us */ | |
1711 | assert_pipe_disabled(dev_priv, pipe); | |
1712 | ||
03ed5cbf VS |
1713 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1714 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1715 | if (pipe != PIPE_A) | |
1716 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1717 | ||
f6071166 JB |
1718 | I915_WRITE(DPLL(pipe), val); |
1719 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1720 | } |
1721 | ||
1722 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1723 | { | |
d752048d | 1724 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1725 | u32 val; |
1726 | ||
a11b0703 VS |
1727 | /* Make sure the pipe isn't still relying on us */ |
1728 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1729 | |
60bfe44f VS |
1730 | val = DPLL_SSC_REF_CLK_CHV | |
1731 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1732 | if (pipe != PIPE_A) |
1733 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1734 | |
a11b0703 VS |
1735 | I915_WRITE(DPLL(pipe), val); |
1736 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1737 | |
a580516d | 1738 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1739 | |
1740 | /* Disable 10bit clock to display controller */ | |
1741 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1742 | val &= ~DPIO_DCLKP_EN; | |
1743 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1744 | ||
a580516d | 1745 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1746 | } |
1747 | ||
e4607fcf | 1748 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1749 | struct intel_digital_port *dport, |
1750 | unsigned int expected_mask) | |
89b667f8 JB |
1751 | { |
1752 | u32 port_mask; | |
f0f59a00 | 1753 | i915_reg_t dpll_reg; |
89b667f8 | 1754 | |
e4607fcf CML |
1755 | switch (dport->port) { |
1756 | case PORT_B: | |
89b667f8 | 1757 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1758 | dpll_reg = DPLL(0); |
e4607fcf CML |
1759 | break; |
1760 | case PORT_C: | |
89b667f8 | 1761 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1762 | dpll_reg = DPLL(0); |
9b6de0a1 | 1763 | expected_mask <<= 4; |
00fc31b7 CML |
1764 | break; |
1765 | case PORT_D: | |
1766 | port_mask = DPLL_PORTD_READY_MASK; | |
1767 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1768 | break; |
1769 | default: | |
1770 | BUG(); | |
1771 | } | |
89b667f8 | 1772 | |
370004d3 CW |
1773 | if (intel_wait_for_register(dev_priv, |
1774 | dpll_reg, port_mask, expected_mask, | |
1775 | 1000)) | |
9b6de0a1 VS |
1776 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1777 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1778 | } |
1779 | ||
b8a4f404 PZ |
1780 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1781 | enum pipe pipe) | |
040484af | 1782 | { |
98187836 VS |
1783 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1784 | pipe); | |
f0f59a00 VS |
1785 | i915_reg_t reg; |
1786 | uint32_t val, pipeconf_val; | |
040484af | 1787 | |
040484af | 1788 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1789 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1790 | |
1791 | /* FDI must be feeding us bits for PCH ports */ | |
1792 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1793 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1794 | ||
6e266956 | 1795 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1796 | /* Workaround: Set the timing override bit before enabling the |
1797 | * pch transcoder. */ | |
1798 | reg = TRANS_CHICKEN2(pipe); | |
1799 | val = I915_READ(reg); | |
1800 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1801 | I915_WRITE(reg, val); | |
59c859d6 | 1802 | } |
23670b32 | 1803 | |
ab9412ba | 1804 | reg = PCH_TRANSCONF(pipe); |
040484af | 1805 | val = I915_READ(reg); |
5f7f726d | 1806 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1807 | |
2d1fe073 | 1808 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1809 | /* |
c5de7c6f VS |
1810 | * Make the BPC in transcoder be consistent with |
1811 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1812 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1813 | */ |
dfd07d72 | 1814 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1815 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1816 | val |= PIPECONF_8BPC; |
1817 | else | |
1818 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1819 | } |
5f7f726d PZ |
1820 | |
1821 | val &= ~TRANS_INTERLACE_MASK; | |
1822 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1823 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1824 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1825 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1826 | else | |
1827 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1828 | else |
1829 | val |= TRANS_PROGRESSIVE; | |
1830 | ||
040484af | 1831 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1832 | if (intel_wait_for_register(dev_priv, |
1833 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1834 | 100)) | |
4bb6f1f3 | 1835 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1836 | } |
1837 | ||
8fb033d7 | 1838 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1839 | enum transcoder cpu_transcoder) |
040484af | 1840 | { |
8fb033d7 | 1841 | u32 val, pipeconf_val; |
8fb033d7 | 1842 | |
8fb033d7 | 1843 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1844 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1845 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1846 | |
223a6fdf | 1847 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1848 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1849 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1850 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1851 | |
25f3ef11 | 1852 | val = TRANS_ENABLE; |
937bb610 | 1853 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1854 | |
9a76b1c6 PZ |
1855 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1856 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1857 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1858 | else |
1859 | val |= TRANS_PROGRESSIVE; | |
1860 | ||
ab9412ba | 1861 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1862 | if (intel_wait_for_register(dev_priv, |
1863 | LPT_TRANSCONF, | |
1864 | TRANS_STATE_ENABLE, | |
1865 | TRANS_STATE_ENABLE, | |
1866 | 100)) | |
937bb610 | 1867 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1868 | } |
1869 | ||
b8a4f404 PZ |
1870 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1871 | enum pipe pipe) | |
040484af | 1872 | { |
f0f59a00 VS |
1873 | i915_reg_t reg; |
1874 | uint32_t val; | |
040484af JB |
1875 | |
1876 | /* FDI relies on the transcoder */ | |
1877 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1878 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1879 | ||
291906f1 JB |
1880 | /* Ports must be off as well */ |
1881 | assert_pch_ports_disabled(dev_priv, pipe); | |
1882 | ||
ab9412ba | 1883 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1884 | val = I915_READ(reg); |
1885 | val &= ~TRANS_ENABLE; | |
1886 | I915_WRITE(reg, val); | |
1887 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1888 | if (intel_wait_for_register(dev_priv, |
1889 | reg, TRANS_STATE_ENABLE, 0, | |
1890 | 50)) | |
4bb6f1f3 | 1891 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1892 | |
6e266956 | 1893 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1894 | /* Workaround: Clear the timing override chicken bit again. */ |
1895 | reg = TRANS_CHICKEN2(pipe); | |
1896 | val = I915_READ(reg); | |
1897 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1898 | I915_WRITE(reg, val); | |
1899 | } | |
040484af JB |
1900 | } |
1901 | ||
b7076546 | 1902 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1903 | { |
8fb033d7 PZ |
1904 | u32 val; |
1905 | ||
ab9412ba | 1906 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1907 | val &= ~TRANS_ENABLE; |
ab9412ba | 1908 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1909 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1910 | if (intel_wait_for_register(dev_priv, |
1911 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1912 | 50)) | |
8a52fd9f | 1913 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1914 | |
1915 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1916 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1917 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1918 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1919 | } |
1920 | ||
65f2130c VS |
1921 | enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
1922 | { | |
1923 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1924 | ||
1925 | WARN_ON(!crtc->config->has_pch_encoder); | |
1926 | ||
1927 | if (HAS_PCH_LPT(dev_priv)) | |
1928 | return TRANSCODER_A; | |
1929 | else | |
1930 | return (enum transcoder) crtc->pipe; | |
1931 | } | |
1932 | ||
b24e7179 | 1933 | /** |
309cfea8 | 1934 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1935 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1936 | * |
0372264a | 1937 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1938 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1939 | */ |
e1fdc473 | 1940 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1941 | { |
0372264a | 1942 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1943 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1944 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1945 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1946 | i915_reg_t reg; |
b24e7179 JB |
1947 | u32 val; |
1948 | ||
9e2ee2dd VS |
1949 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1950 | ||
58c6eaa2 | 1951 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1952 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1953 | assert_sprites_disabled(dev_priv, pipe); |
1954 | ||
b24e7179 JB |
1955 | /* |
1956 | * A pipe without a PLL won't actually be able to drive bits from | |
1957 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1958 | * need the check. | |
1959 | */ | |
09fa8bb9 | 1960 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1961 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1962 | assert_dsi_pll_enabled(dev_priv); |
1963 | else | |
1964 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1965 | } else { |
6e3c9717 | 1966 | if (crtc->config->has_pch_encoder) { |
040484af | 1967 | /* if driving the PCH, we need FDI enabled */ |
65f2130c VS |
1968 | assert_fdi_rx_pll_enabled(dev_priv, |
1969 | (enum pipe) intel_crtc_pch_transcoder(crtc)); | |
1a240d4d DV |
1970 | assert_fdi_tx_pll_enabled(dev_priv, |
1971 | (enum pipe) cpu_transcoder); | |
040484af JB |
1972 | } |
1973 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1974 | } | |
b24e7179 | 1975 | |
702e7a56 | 1976 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1977 | val = I915_READ(reg); |
7ad25d48 | 1978 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1979 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1980 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1981 | return; |
7ad25d48 | 1982 | } |
00d70b15 CW |
1983 | |
1984 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1985 | POSTING_READ(reg); |
b7792d8b VS |
1986 | |
1987 | /* | |
1988 | * Until the pipe starts DSL will read as 0, which would cause | |
1989 | * an apparent vblank timestamp jump, which messes up also the | |
1990 | * frame count when it's derived from the timestamps. So let's | |
1991 | * wait for the pipe to start properly before we call | |
1992 | * drm_crtc_vblank_on() | |
1993 | */ | |
1994 | if (dev->max_vblank_count == 0 && | |
1995 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1996 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1997 | } |
1998 | ||
1999 | /** | |
309cfea8 | 2000 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2001 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2002 | * |
575f7ab7 VS |
2003 | * Disable the pipe of @crtc, making sure that various hardware |
2004 | * specific requirements are met, if applicable, e.g. plane | |
2005 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2006 | * |
2007 | * Will wait until the pipe has shut down before returning. | |
2008 | */ | |
575f7ab7 | 2009 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2010 | { |
fac5e23e | 2011 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 2012 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2013 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2014 | i915_reg_t reg; |
b24e7179 JB |
2015 | u32 val; |
2016 | ||
9e2ee2dd VS |
2017 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2018 | ||
b24e7179 JB |
2019 | /* |
2020 | * Make sure planes won't keep trying to pump pixels to us, | |
2021 | * or we might hang the display. | |
2022 | */ | |
2023 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2024 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2025 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2026 | |
702e7a56 | 2027 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2028 | val = I915_READ(reg); |
00d70b15 CW |
2029 | if ((val & PIPECONF_ENABLE) == 0) |
2030 | return; | |
2031 | ||
67adc644 VS |
2032 | /* |
2033 | * Double wide has implications for planes | |
2034 | * so best keep it disabled when not needed. | |
2035 | */ | |
6e3c9717 | 2036 | if (crtc->config->double_wide) |
67adc644 VS |
2037 | val &= ~PIPECONF_DOUBLE_WIDE; |
2038 | ||
2039 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2040 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2041 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2042 | val &= ~PIPECONF_ENABLE; |
2043 | ||
2044 | I915_WRITE(reg, val); | |
2045 | if ((val & PIPECONF_ENABLE) == 0) | |
2046 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2047 | } |
2048 | ||
832be82f VS |
2049 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2050 | { | |
2051 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2052 | } | |
2053 | ||
27ba3910 VS |
2054 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2055 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2056 | { |
2057 | switch (fb_modifier) { | |
2058 | case DRM_FORMAT_MOD_NONE: | |
2059 | return cpp; | |
2060 | case I915_FORMAT_MOD_X_TILED: | |
2061 | if (IS_GEN2(dev_priv)) | |
2062 | return 128; | |
2063 | else | |
2064 | return 512; | |
2065 | case I915_FORMAT_MOD_Y_TILED: | |
2066 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2067 | return 128; | |
2068 | else | |
2069 | return 512; | |
2070 | case I915_FORMAT_MOD_Yf_TILED: | |
2071 | switch (cpp) { | |
2072 | case 1: | |
2073 | return 64; | |
2074 | case 2: | |
2075 | case 4: | |
2076 | return 128; | |
2077 | case 8: | |
2078 | case 16: | |
2079 | return 256; | |
2080 | default: | |
2081 | MISSING_CASE(cpp); | |
2082 | return cpp; | |
2083 | } | |
2084 | break; | |
2085 | default: | |
2086 | MISSING_CASE(fb_modifier); | |
2087 | return cpp; | |
2088 | } | |
2089 | } | |
2090 | ||
832be82f VS |
2091 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2092 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2093 | { |
832be82f VS |
2094 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2095 | return 1; | |
2096 | else | |
2097 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2098 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2099 | } |
2100 | ||
8d0deca8 VS |
2101 | /* Return the tile dimensions in pixel units */ |
2102 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2103 | unsigned int *tile_width, | |
2104 | unsigned int *tile_height, | |
2105 | uint64_t fb_modifier, | |
2106 | unsigned int cpp) | |
2107 | { | |
2108 | unsigned int tile_width_bytes = | |
2109 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2110 | ||
2111 | *tile_width = tile_width_bytes / cpp; | |
2112 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2113 | } | |
2114 | ||
6761dd31 TU |
2115 | unsigned int |
2116 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2117 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2118 | { |
832be82f VS |
2119 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2120 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2121 | ||
2122 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2123 | } |
2124 | ||
1663b9d6 VS |
2125 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2126 | { | |
2127 | unsigned int size = 0; | |
2128 | int i; | |
2129 | ||
2130 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2131 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2132 | ||
2133 | return size; | |
2134 | } | |
2135 | ||
75c82a53 | 2136 | static void |
3465c580 VS |
2137 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2138 | const struct drm_framebuffer *fb, | |
2139 | unsigned int rotation) | |
f64b98cd | 2140 | { |
bd2ef25d | 2141 | if (drm_rotation_90_or_270(rotation)) { |
2d7a215f VS |
2142 | *view = i915_ggtt_view_rotated; |
2143 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2144 | } else { | |
2145 | *view = i915_ggtt_view_normal; | |
2146 | } | |
2147 | } | |
50470bb0 | 2148 | |
603525d7 | 2149 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2150 | { |
2151 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2152 | return 256 * 1024; | |
c0f86832 | 2153 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2154 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2155 | return 128 * 1024; |
2156 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2157 | return 4 * 1024; | |
2158 | else | |
44c5905e | 2159 | return 0; |
4e9a86b6 VS |
2160 | } |
2161 | ||
603525d7 VS |
2162 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2163 | uint64_t fb_modifier) | |
2164 | { | |
2165 | switch (fb_modifier) { | |
2166 | case DRM_FORMAT_MOD_NONE: | |
2167 | return intel_linear_alignment(dev_priv); | |
2168 | case I915_FORMAT_MOD_X_TILED: | |
2169 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2170 | return 256 * 1024; | |
2171 | return 0; | |
2172 | case I915_FORMAT_MOD_Y_TILED: | |
2173 | case I915_FORMAT_MOD_Yf_TILED: | |
2174 | return 1 * 1024 * 1024; | |
2175 | default: | |
2176 | MISSING_CASE(fb_modifier); | |
2177 | return 0; | |
2178 | } | |
2179 | } | |
2180 | ||
058d88c4 CW |
2181 | struct i915_vma * |
2182 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2183 | { |
850c4cdc | 2184 | struct drm_device *dev = fb->dev; |
fac5e23e | 2185 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2186 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2187 | struct i915_ggtt_view view; |
058d88c4 | 2188 | struct i915_vma *vma; |
6b95a207 | 2189 | u32 alignment; |
6b95a207 | 2190 | |
ebcdd39e MR |
2191 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2192 | ||
bae781b2 | 2193 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
6b95a207 | 2194 | |
3465c580 | 2195 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2196 | |
693db184 CW |
2197 | /* Note that the w/a also requires 64 PTE of padding following the |
2198 | * bo. We currently fill all unused PTE with the shadow page and so | |
2199 | * we should always have valid PTE following the scanout preventing | |
2200 | * the VT-d warning. | |
2201 | */ | |
48f112fe | 2202 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2203 | alignment = 256 * 1024; |
2204 | ||
d6dd6843 PZ |
2205 | /* |
2206 | * Global gtt pte registers are special registers which actually forward | |
2207 | * writes to a chunk of system memory. Which means that there is no risk | |
2208 | * that the register values disappear as soon as we call | |
2209 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2210 | * pin/unpin/fence and not more. | |
2211 | */ | |
2212 | intel_runtime_pm_get(dev_priv); | |
2213 | ||
058d88c4 | 2214 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2215 | if (IS_ERR(vma)) |
2216 | goto err; | |
6b95a207 | 2217 | |
05a20d09 | 2218 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2219 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2220 | * fence, whereas 965+ only requires a fence if using | |
2221 | * framebuffer compression. For simplicity, we always, when | |
2222 | * possible, install a fence as the cost is not that onerous. | |
2223 | * | |
2224 | * If we fail to fence the tiled scanout, then either the | |
2225 | * modeset will reject the change (which is highly unlikely as | |
2226 | * the affected systems, all but one, do not have unmappable | |
2227 | * space) or we will not be able to enable full powersaving | |
2228 | * techniques (also likely not to apply due to various limits | |
2229 | * FBC and the like impose on the size of the buffer, which | |
2230 | * presumably we violated anyway with this unmappable buffer). | |
2231 | * Anyway, it is presumably better to stumble onwards with | |
2232 | * something and try to run the system in a "less than optimal" | |
2233 | * mode that matches the user configuration. | |
2234 | */ | |
2235 | if (i915_vma_get_fence(vma) == 0) | |
2236 | i915_vma_pin_fence(vma); | |
9807216f | 2237 | } |
6b95a207 | 2238 | |
49ef5294 | 2239 | err: |
d6dd6843 | 2240 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2241 | return vma; |
6b95a207 KH |
2242 | } |
2243 | ||
fb4b8ce1 | 2244 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2245 | { |
82bc3b2d | 2246 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2247 | struct i915_ggtt_view view; |
058d88c4 | 2248 | struct i915_vma *vma; |
82bc3b2d | 2249 | |
ebcdd39e MR |
2250 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2251 | ||
3465c580 | 2252 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
05a20d09 | 2253 | vma = i915_gem_object_to_ggtt(obj, &view); |
f64b98cd | 2254 | |
49ef5294 | 2255 | i915_vma_unpin_fence(vma); |
058d88c4 | 2256 | i915_gem_object_unpin_from_display_plane(vma); |
1690e1eb CW |
2257 | } |
2258 | ||
ef78ec94 VS |
2259 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2260 | unsigned int rotation) | |
2261 | { | |
bd2ef25d | 2262 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2263 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2264 | else | |
2265 | return fb->pitches[plane]; | |
2266 | } | |
2267 | ||
6687c906 VS |
2268 | /* |
2269 | * Convert the x/y offsets into a linear offset. | |
2270 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2271 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2272 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2273 | */ | |
2274 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2275 | const struct intel_plane_state *state, |
2276 | int plane) | |
6687c906 | 2277 | { |
2949056c | 2278 | const struct drm_framebuffer *fb = state->base.fb; |
6687c906 VS |
2279 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
2280 | unsigned int pitch = fb->pitches[plane]; | |
2281 | ||
2282 | return y * pitch + x * cpp; | |
2283 | } | |
2284 | ||
2285 | /* | |
2286 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2287 | * specified plane src x/y offsets. The resulting x/y offsets | |
2288 | * specify the start of scanout from the beginning of the gtt mapping. | |
2289 | */ | |
2290 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2291 | const struct intel_plane_state *state, |
2292 | int plane) | |
6687c906 VS |
2293 | |
2294 | { | |
2949056c VS |
2295 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2296 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2297 | |
bd2ef25d | 2298 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2299 | *x += intel_fb->rotated[plane].x; |
2300 | *y += intel_fb->rotated[plane].y; | |
2301 | } else { | |
2302 | *x += intel_fb->normal[plane].x; | |
2303 | *y += intel_fb->normal[plane].y; | |
2304 | } | |
2305 | } | |
2306 | ||
29cf9491 | 2307 | /* |
29cf9491 VS |
2308 | * Input tile dimensions and pitch must already be |
2309 | * rotated to match x and y, and in pixel units. | |
2310 | */ | |
66a2d927 VS |
2311 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2312 | unsigned int tile_width, | |
2313 | unsigned int tile_height, | |
2314 | unsigned int tile_size, | |
2315 | unsigned int pitch_tiles, | |
2316 | u32 old_offset, | |
2317 | u32 new_offset) | |
29cf9491 | 2318 | { |
b9b24038 | 2319 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2320 | unsigned int tiles; |
2321 | ||
2322 | WARN_ON(old_offset & (tile_size - 1)); | |
2323 | WARN_ON(new_offset & (tile_size - 1)); | |
2324 | WARN_ON(new_offset > old_offset); | |
2325 | ||
2326 | tiles = (old_offset - new_offset) / tile_size; | |
2327 | ||
2328 | *y += tiles / pitch_tiles * tile_height; | |
2329 | *x += tiles % pitch_tiles * tile_width; | |
2330 | ||
b9b24038 VS |
2331 | /* minimize x in case it got needlessly big */ |
2332 | *y += *x / pitch_pixels * tile_height; | |
2333 | *x %= pitch_pixels; | |
2334 | ||
29cf9491 VS |
2335 | return new_offset; |
2336 | } | |
2337 | ||
66a2d927 VS |
2338 | /* |
2339 | * Adjust the tile offset by moving the difference into | |
2340 | * the x/y offsets. | |
2341 | */ | |
2342 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2343 | const struct intel_plane_state *state, int plane, | |
2344 | u32 old_offset, u32 new_offset) | |
2345 | { | |
2346 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2347 | const struct drm_framebuffer *fb = state->base.fb; | |
2348 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2349 | unsigned int rotation = state->base.rotation; | |
2350 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2351 | ||
2352 | WARN_ON(new_offset > old_offset); | |
2353 | ||
bae781b2 | 2354 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
66a2d927 VS |
2355 | unsigned int tile_size, tile_width, tile_height; |
2356 | unsigned int pitch_tiles; | |
2357 | ||
2358 | tile_size = intel_tile_size(dev_priv); | |
2359 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
bae781b2 | 2360 | fb->modifier, cpp); |
66a2d927 | 2361 | |
bd2ef25d | 2362 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2363 | pitch_tiles = pitch / tile_height; |
2364 | swap(tile_width, tile_height); | |
2365 | } else { | |
2366 | pitch_tiles = pitch / (tile_width * cpp); | |
2367 | } | |
2368 | ||
2369 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2370 | tile_size, pitch_tiles, | |
2371 | old_offset, new_offset); | |
2372 | } else { | |
2373 | old_offset += *y * pitch + *x * cpp; | |
2374 | ||
2375 | *y = (old_offset - new_offset) / pitch; | |
2376 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2377 | } | |
2378 | ||
2379 | return new_offset; | |
2380 | } | |
2381 | ||
8d0deca8 VS |
2382 | /* |
2383 | * Computes the linear offset to the base tile and adjusts | |
2384 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2385 | * | |
2386 | * In the 90/270 rotated case, x and y are assumed | |
2387 | * to be already rotated to match the rotated GTT view, and | |
2388 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2389 | * |
2390 | * This function is used when computing the derived information | |
2391 | * under intel_framebuffer, so using any of that information | |
2392 | * here is not allowed. Anything under drm_framebuffer can be | |
2393 | * used. This is why the user has to pass in the pitch since it | |
2394 | * is specified in the rotated orientation. | |
8d0deca8 | 2395 | */ |
6687c906 VS |
2396 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2397 | int *x, int *y, | |
2398 | const struct drm_framebuffer *fb, int plane, | |
2399 | unsigned int pitch, | |
2400 | unsigned int rotation, | |
2401 | u32 alignment) | |
c2c75131 | 2402 | { |
bae781b2 | 2403 | uint64_t fb_modifier = fb->modifier; |
4f2d9934 | 2404 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
6687c906 | 2405 | u32 offset, offset_aligned; |
29cf9491 | 2406 | |
29cf9491 VS |
2407 | if (alignment) |
2408 | alignment--; | |
2409 | ||
b5c65338 | 2410 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2411 | unsigned int tile_size, tile_width, tile_height; |
2412 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2413 | |
d843310d | 2414 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2415 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2416 | fb_modifier, cpp); | |
2417 | ||
bd2ef25d | 2418 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2419 | pitch_tiles = pitch / tile_height; |
2420 | swap(tile_width, tile_height); | |
2421 | } else { | |
2422 | pitch_tiles = pitch / (tile_width * cpp); | |
2423 | } | |
d843310d VS |
2424 | |
2425 | tile_rows = *y / tile_height; | |
2426 | *y %= tile_height; | |
c2c75131 | 2427 | |
8d0deca8 VS |
2428 | tiles = *x / tile_width; |
2429 | *x %= tile_width; | |
bc752862 | 2430 | |
29cf9491 VS |
2431 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2432 | offset_aligned = offset & ~alignment; | |
bc752862 | 2433 | |
66a2d927 VS |
2434 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2435 | tile_size, pitch_tiles, | |
2436 | offset, offset_aligned); | |
29cf9491 | 2437 | } else { |
bc752862 | 2438 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2439 | offset_aligned = offset & ~alignment; |
2440 | ||
4e9a86b6 VS |
2441 | *y = (offset & alignment) / pitch; |
2442 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2443 | } |
29cf9491 VS |
2444 | |
2445 | return offset_aligned; | |
c2c75131 DV |
2446 | } |
2447 | ||
6687c906 | 2448 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2449 | const struct intel_plane_state *state, |
2450 | int plane) | |
6687c906 | 2451 | { |
2949056c VS |
2452 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
2453 | const struct drm_framebuffer *fb = state->base.fb; | |
2454 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2455 | int pitch = intel_fb_pitch(fb, plane, rotation); |
8d970654 VS |
2456 | u32 alignment; |
2457 | ||
2458 | /* AUX_DIST needs only 4K alignment */ | |
2459 | if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1) | |
2460 | alignment = 4096; | |
2461 | else | |
bae781b2 | 2462 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
6687c906 VS |
2463 | |
2464 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2465 | rotation, alignment); | |
2466 | } | |
2467 | ||
2468 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2469 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2470 | const struct drm_framebuffer *fb, int plane) | |
2471 | { | |
2472 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2473 | unsigned int pitch = fb->pitches[plane]; | |
2474 | u32 linear_offset = fb->offsets[plane]; | |
2475 | ||
2476 | *y = linear_offset / pitch; | |
2477 | *x = linear_offset % pitch / cpp; | |
2478 | } | |
2479 | ||
72618ebf VS |
2480 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2481 | { | |
2482 | switch (fb_modifier) { | |
2483 | case I915_FORMAT_MOD_X_TILED: | |
2484 | return I915_TILING_X; | |
2485 | case I915_FORMAT_MOD_Y_TILED: | |
2486 | return I915_TILING_Y; | |
2487 | default: | |
2488 | return I915_TILING_NONE; | |
2489 | } | |
2490 | } | |
2491 | ||
6687c906 VS |
2492 | static int |
2493 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2494 | struct drm_framebuffer *fb) | |
2495 | { | |
2496 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2497 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2498 | u32 gtt_offset_rotated = 0; | |
2499 | unsigned int max_size = 0; | |
2500 | uint32_t format = fb->pixel_format; | |
2501 | int i, num_planes = drm_format_num_planes(format); | |
2502 | unsigned int tile_size = intel_tile_size(dev_priv); | |
2503 | ||
2504 | for (i = 0; i < num_planes; i++) { | |
2505 | unsigned int width, height; | |
2506 | unsigned int cpp, size; | |
2507 | u32 offset; | |
2508 | int x, y; | |
2509 | ||
2510 | cpp = drm_format_plane_cpp(format, i); | |
2511 | width = drm_format_plane_width(fb->width, format, i); | |
2512 | height = drm_format_plane_height(fb->height, format, i); | |
2513 | ||
2514 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2515 | ||
60d5f2a4 VS |
2516 | /* |
2517 | * The fence (if used) is aligned to the start of the object | |
2518 | * so having the framebuffer wrap around across the edge of the | |
2519 | * fenced region doesn't really work. We have no API to configure | |
2520 | * the fence start offset within the object (nor could we probably | |
2521 | * on gen2/3). So it's just easier if we just require that the | |
2522 | * fb layout agrees with the fence layout. We already check that the | |
2523 | * fb stride matches the fence stride elsewhere. | |
2524 | */ | |
2525 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2526 | (x + width) * cpp > fb->pitches[i]) { | |
2527 | DRM_DEBUG("bad fb plane %d offset: 0x%x\n", | |
2528 | i, fb->offsets[i]); | |
2529 | return -EINVAL; | |
2530 | } | |
2531 | ||
6687c906 VS |
2532 | /* |
2533 | * First pixel of the framebuffer from | |
2534 | * the start of the normal gtt mapping. | |
2535 | */ | |
2536 | intel_fb->normal[i].x = x; | |
2537 | intel_fb->normal[i].y = y; | |
2538 | ||
2539 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
2540 | fb, 0, fb->pitches[i], | |
cc926387 | 2541 | DRM_ROTATE_0, tile_size); |
6687c906 VS |
2542 | offset /= tile_size; |
2543 | ||
bae781b2 | 2544 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
6687c906 VS |
2545 | unsigned int tile_width, tile_height; |
2546 | unsigned int pitch_tiles; | |
2547 | struct drm_rect r; | |
2548 | ||
2549 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
bae781b2 | 2550 | fb->modifier, cpp); |
6687c906 VS |
2551 | |
2552 | rot_info->plane[i].offset = offset; | |
2553 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2554 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2555 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2556 | ||
2557 | intel_fb->rotated[i].pitch = | |
2558 | rot_info->plane[i].height * tile_height; | |
2559 | ||
2560 | /* how many tiles does this plane need */ | |
2561 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2562 | /* | |
2563 | * If the plane isn't horizontally tile aligned, | |
2564 | * we need one more tile. | |
2565 | */ | |
2566 | if (x != 0) | |
2567 | size++; | |
2568 | ||
2569 | /* rotate the x/y offsets to match the GTT view */ | |
2570 | r.x1 = x; | |
2571 | r.y1 = y; | |
2572 | r.x2 = x + width; | |
2573 | r.y2 = y + height; | |
2574 | drm_rect_rotate(&r, | |
2575 | rot_info->plane[i].width * tile_width, | |
2576 | rot_info->plane[i].height * tile_height, | |
cc926387 | 2577 | DRM_ROTATE_270); |
6687c906 VS |
2578 | x = r.x1; |
2579 | y = r.y1; | |
2580 | ||
2581 | /* rotate the tile dimensions to match the GTT view */ | |
2582 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2583 | swap(tile_width, tile_height); | |
2584 | ||
2585 | /* | |
2586 | * We only keep the x/y offsets, so push all of the | |
2587 | * gtt offset into the x/y offsets. | |
2588 | */ | |
66a2d927 VS |
2589 | _intel_adjust_tile_offset(&x, &y, tile_size, |
2590 | tile_width, tile_height, pitch_tiles, | |
2591 | gtt_offset_rotated * tile_size, 0); | |
6687c906 VS |
2592 | |
2593 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2594 | ||
2595 | /* | |
2596 | * First pixel of the framebuffer from | |
2597 | * the start of the rotated gtt mapping. | |
2598 | */ | |
2599 | intel_fb->rotated[i].x = x; | |
2600 | intel_fb->rotated[i].y = y; | |
2601 | } else { | |
2602 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2603 | x * cpp, tile_size); | |
2604 | } | |
2605 | ||
2606 | /* how many tiles in total needed in the bo */ | |
2607 | max_size = max(max_size, offset + size); | |
2608 | } | |
2609 | ||
2610 | if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { | |
2611 | DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2612 | max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); | |
2613 | return -EINVAL; | |
2614 | } | |
2615 | ||
2616 | return 0; | |
2617 | } | |
2618 | ||
b35d63fa | 2619 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2620 | { |
2621 | switch (format) { | |
2622 | case DISPPLANE_8BPP: | |
2623 | return DRM_FORMAT_C8; | |
2624 | case DISPPLANE_BGRX555: | |
2625 | return DRM_FORMAT_XRGB1555; | |
2626 | case DISPPLANE_BGRX565: | |
2627 | return DRM_FORMAT_RGB565; | |
2628 | default: | |
2629 | case DISPPLANE_BGRX888: | |
2630 | return DRM_FORMAT_XRGB8888; | |
2631 | case DISPPLANE_RGBX888: | |
2632 | return DRM_FORMAT_XBGR8888; | |
2633 | case DISPPLANE_BGRX101010: | |
2634 | return DRM_FORMAT_XRGB2101010; | |
2635 | case DISPPLANE_RGBX101010: | |
2636 | return DRM_FORMAT_XBGR2101010; | |
2637 | } | |
2638 | } | |
2639 | ||
bc8d7dff DL |
2640 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2641 | { | |
2642 | switch (format) { | |
2643 | case PLANE_CTL_FORMAT_RGB_565: | |
2644 | return DRM_FORMAT_RGB565; | |
2645 | default: | |
2646 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2647 | if (rgb_order) { | |
2648 | if (alpha) | |
2649 | return DRM_FORMAT_ABGR8888; | |
2650 | else | |
2651 | return DRM_FORMAT_XBGR8888; | |
2652 | } else { | |
2653 | if (alpha) | |
2654 | return DRM_FORMAT_ARGB8888; | |
2655 | else | |
2656 | return DRM_FORMAT_XRGB8888; | |
2657 | } | |
2658 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2659 | if (rgb_order) | |
2660 | return DRM_FORMAT_XBGR2101010; | |
2661 | else | |
2662 | return DRM_FORMAT_XRGB2101010; | |
2663 | } | |
2664 | } | |
2665 | ||
5724dbd1 | 2666 | static bool |
f6936e29 DV |
2667 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2668 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2669 | { |
2670 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2671 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2672 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2673 | struct drm_i915_gem_object *obj = NULL; |
2674 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2675 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2676 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2677 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2678 | PAGE_SIZE); | |
2679 | ||
2680 | size_aligned -= base_aligned; | |
46f297fb | 2681 | |
ff2652ea CW |
2682 | if (plane_config->size == 0) |
2683 | return false; | |
2684 | ||
3badb49f PZ |
2685 | /* If the FB is too big, just don't use it since fbdev is not very |
2686 | * important and we should probably use that space with FBC or other | |
2687 | * features. */ | |
72e96d64 | 2688 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2689 | return false; |
2690 | ||
12c83d99 TU |
2691 | mutex_lock(&dev->struct_mutex); |
2692 | ||
187685cb | 2693 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2694 | base_aligned, |
2695 | base_aligned, | |
2696 | size_aligned); | |
12c83d99 TU |
2697 | if (!obj) { |
2698 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2699 | return false; |
12c83d99 | 2700 | } |
46f297fb | 2701 | |
3e510a8e CW |
2702 | if (plane_config->tiling == I915_TILING_X) |
2703 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2704 | |
6bf129df DL |
2705 | mode_cmd.pixel_format = fb->pixel_format; |
2706 | mode_cmd.width = fb->width; | |
2707 | mode_cmd.height = fb->height; | |
2708 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2709 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2710 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2711 | |
6bf129df | 2712 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2713 | &mode_cmd, obj)) { |
46f297fb JB |
2714 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2715 | goto out_unref_obj; | |
2716 | } | |
12c83d99 | 2717 | |
46f297fb | 2718 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2719 | |
f6936e29 | 2720 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2721 | return true; |
46f297fb JB |
2722 | |
2723 | out_unref_obj: | |
f8c417cd | 2724 | i915_gem_object_put(obj); |
46f297fb | 2725 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2726 | return false; |
2727 | } | |
2728 | ||
5a21b665 DV |
2729 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2730 | static void | |
2731 | update_state_fb(struct drm_plane *plane) | |
2732 | { | |
2733 | if (plane->fb == plane->state->fb) | |
2734 | return; | |
2735 | ||
2736 | if (plane->state->fb) | |
2737 | drm_framebuffer_unreference(plane->state->fb); | |
2738 | plane->state->fb = plane->fb; | |
2739 | if (plane->state->fb) | |
2740 | drm_framebuffer_reference(plane->state->fb); | |
2741 | } | |
2742 | ||
5724dbd1 | 2743 | static void |
f6936e29 DV |
2744 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2745 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2746 | { |
2747 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2748 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd JB |
2749 | struct drm_crtc *c; |
2750 | struct intel_crtc *i; | |
2ff8fde1 | 2751 | struct drm_i915_gem_object *obj; |
88595ac9 | 2752 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2753 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2754 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2755 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2756 | struct intel_plane_state *intel_state = |
2757 | to_intel_plane_state(plane_state); | |
88595ac9 | 2758 | struct drm_framebuffer *fb; |
484b41dd | 2759 | |
2d14030b | 2760 | if (!plane_config->fb) |
484b41dd JB |
2761 | return; |
2762 | ||
f6936e29 | 2763 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2764 | fb = &plane_config->fb->base; |
2765 | goto valid_fb; | |
f55548b5 | 2766 | } |
484b41dd | 2767 | |
2d14030b | 2768 | kfree(plane_config->fb); |
484b41dd JB |
2769 | |
2770 | /* | |
2771 | * Failed to alloc the obj, check to see if we should share | |
2772 | * an fb with another CRTC instead | |
2773 | */ | |
70e1e0ec | 2774 | for_each_crtc(dev, c) { |
484b41dd JB |
2775 | i = to_intel_crtc(c); |
2776 | ||
2777 | if (c == &intel_crtc->base) | |
2778 | continue; | |
2779 | ||
2ff8fde1 MR |
2780 | if (!i->active) |
2781 | continue; | |
2782 | ||
88595ac9 DV |
2783 | fb = c->primary->fb; |
2784 | if (!fb) | |
484b41dd JB |
2785 | continue; |
2786 | ||
88595ac9 | 2787 | obj = intel_fb_obj(fb); |
058d88c4 | 2788 | if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) { |
88595ac9 DV |
2789 | drm_framebuffer_reference(fb); |
2790 | goto valid_fb; | |
484b41dd JB |
2791 | } |
2792 | } | |
88595ac9 | 2793 | |
200757f5 MR |
2794 | /* |
2795 | * We've failed to reconstruct the BIOS FB. Current display state | |
2796 | * indicates that the primary plane is visible, but has a NULL FB, | |
2797 | * which will lead to problems later if we don't fix it up. The | |
2798 | * simplest solution is to just disable the primary plane now and | |
2799 | * pretend the BIOS never had it enabled. | |
2800 | */ | |
936e71e3 | 2801 | to_intel_plane_state(plane_state)->base.visible = false; |
200757f5 | 2802 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); |
2622a081 | 2803 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2804 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2805 | ||
88595ac9 DV |
2806 | return; |
2807 | ||
2808 | valid_fb: | |
f44e2659 VS |
2809 | plane_state->src_x = 0; |
2810 | plane_state->src_y = 0; | |
be5651f2 ML |
2811 | plane_state->src_w = fb->width << 16; |
2812 | plane_state->src_h = fb->height << 16; | |
2813 | ||
f44e2659 VS |
2814 | plane_state->crtc_x = 0; |
2815 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2816 | plane_state->crtc_w = fb->width; |
2817 | plane_state->crtc_h = fb->height; | |
2818 | ||
1638d30c RC |
2819 | intel_state->base.src = drm_plane_state_src(plane_state); |
2820 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2821 | |
88595ac9 | 2822 | obj = intel_fb_obj(fb); |
3e510a8e | 2823 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2824 | dev_priv->preserve_bios_swizzle = true; |
2825 | ||
be5651f2 ML |
2826 | drm_framebuffer_reference(fb); |
2827 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2828 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2829 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
faf5bf0a CW |
2830 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2831 | &obj->frontbuffer_bits); | |
46f297fb JB |
2832 | } |
2833 | ||
b63a16f6 VS |
2834 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2835 | unsigned int rotation) | |
2836 | { | |
2837 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2838 | ||
bae781b2 | 2839 | switch (fb->modifier) { |
b63a16f6 VS |
2840 | case DRM_FORMAT_MOD_NONE: |
2841 | case I915_FORMAT_MOD_X_TILED: | |
2842 | switch (cpp) { | |
2843 | case 8: | |
2844 | return 4096; | |
2845 | case 4: | |
2846 | case 2: | |
2847 | case 1: | |
2848 | return 8192; | |
2849 | default: | |
2850 | MISSING_CASE(cpp); | |
2851 | break; | |
2852 | } | |
2853 | break; | |
2854 | case I915_FORMAT_MOD_Y_TILED: | |
2855 | case I915_FORMAT_MOD_Yf_TILED: | |
2856 | switch (cpp) { | |
2857 | case 8: | |
2858 | return 2048; | |
2859 | case 4: | |
2860 | return 4096; | |
2861 | case 2: | |
2862 | case 1: | |
2863 | return 8192; | |
2864 | default: | |
2865 | MISSING_CASE(cpp); | |
2866 | break; | |
2867 | } | |
2868 | break; | |
2869 | default: | |
bae781b2 | 2870 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2871 | } |
2872 | ||
2873 | return 2048; | |
2874 | } | |
2875 | ||
2876 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2877 | { | |
2878 | const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); | |
2879 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2880 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2881 | int x = plane_state->base.src.x1 >> 16; |
2882 | int y = plane_state->base.src.y1 >> 16; | |
2883 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2884 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2885 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2886 | int max_height = 4096; | |
8d970654 | 2887 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2888 | |
2889 | if (w > max_width || h > max_height) { | |
2890 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2891 | w, h, max_width, max_height); | |
2892 | return -EINVAL; | |
2893 | } | |
2894 | ||
2895 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2896 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
2897 | ||
bae781b2 | 2898 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
b63a16f6 | 2899 | |
8d970654 VS |
2900 | /* |
2901 | * AUX surface offset is specified as the distance from the | |
2902 | * main surface offset, and it must be non-negative. Make | |
2903 | * sure that is what we will get. | |
2904 | */ | |
2905 | if (offset > aux_offset) | |
2906 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2907 | offset, aux_offset & ~(alignment - 1)); | |
2908 | ||
b63a16f6 VS |
2909 | /* |
2910 | * When using an X-tiled surface, the plane blows up | |
2911 | * if the x offset + width exceed the stride. | |
2912 | * | |
2913 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2914 | */ | |
bae781b2 | 2915 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
b63a16f6 VS |
2916 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
2917 | ||
2918 | while ((x + w) * cpp > fb->pitches[0]) { | |
2919 | if (offset == 0) { | |
2920 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2921 | return -EINVAL; | |
2922 | } | |
2923 | ||
2924 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2925 | offset, offset - alignment); | |
2926 | } | |
2927 | } | |
2928 | ||
2929 | plane_state->main.offset = offset; | |
2930 | plane_state->main.x = x; | |
2931 | plane_state->main.y = y; | |
2932 | ||
2933 | return 0; | |
2934 | } | |
2935 | ||
8d970654 VS |
2936 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2937 | { | |
2938 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2939 | unsigned int rotation = plane_state->base.rotation; | |
2940 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2941 | int max_height = 4096; | |
cc926387 DV |
2942 | int x = plane_state->base.src.x1 >> 17; |
2943 | int y = plane_state->base.src.y1 >> 17; | |
2944 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2945 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2946 | u32 offset; |
2947 | ||
2948 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2949 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2950 | ||
2951 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2952 | if (w > max_width || h > max_height) { | |
2953 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2954 | w, h, max_width, max_height); | |
2955 | return -EINVAL; | |
2956 | } | |
2957 | ||
2958 | plane_state->aux.offset = offset; | |
2959 | plane_state->aux.x = x; | |
2960 | plane_state->aux.y = y; | |
2961 | ||
2962 | return 0; | |
2963 | } | |
2964 | ||
b63a16f6 VS |
2965 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2966 | { | |
2967 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2968 | unsigned int rotation = plane_state->base.rotation; | |
2969 | int ret; | |
2970 | ||
2971 | /* Rotate src coordinates to match rotated GTT view */ | |
bd2ef25d | 2972 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 2973 | drm_rect_rotate(&plane_state->base.src, |
da064b47 VS |
2974 | fb->width << 16, fb->height << 16, |
2975 | DRM_ROTATE_270); | |
b63a16f6 | 2976 | |
8d970654 VS |
2977 | /* |
2978 | * Handle the AUX surface first since | |
2979 | * the main surface setup depends on it. | |
2980 | */ | |
2981 | if (fb->pixel_format == DRM_FORMAT_NV12) { | |
2982 | ret = skl_check_nv12_aux_surface(plane_state); | |
2983 | if (ret) | |
2984 | return ret; | |
2985 | } else { | |
2986 | plane_state->aux.offset = ~0xfff; | |
2987 | plane_state->aux.x = 0; | |
2988 | plane_state->aux.y = 0; | |
2989 | } | |
2990 | ||
b63a16f6 VS |
2991 | ret = skl_check_main_surface(plane_state); |
2992 | if (ret) | |
2993 | return ret; | |
2994 | ||
2995 | return 0; | |
2996 | } | |
2997 | ||
a8d201af ML |
2998 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2999 | const struct intel_crtc_state *crtc_state, | |
3000 | const struct intel_plane_state *plane_state) | |
81255565 | 3001 | { |
6315b5d3 | 3002 | struct drm_i915_private *dev_priv = to_i915(primary->dev); |
a8d201af ML |
3003 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3004 | struct drm_framebuffer *fb = plane_state->base.fb; | |
81255565 | 3005 | int plane = intel_crtc->plane; |
54ea9da8 | 3006 | u32 linear_offset; |
81255565 | 3007 | u32 dspcntr; |
f0f59a00 | 3008 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 3009 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3010 | int x = plane_state->base.src.x1 >> 16; |
3011 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3012 | |
f45651ba VS |
3013 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
3014 | ||
fdd508a6 | 3015 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 3016 | |
6315b5d3 | 3017 | if (INTEL_GEN(dev_priv) < 4) { |
f45651ba VS |
3018 | if (intel_crtc->pipe == PIPE_B) |
3019 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
3020 | ||
3021 | /* pipesrc and dspsize control the size that is scaled from, | |
3022 | * which should always be the user's requested size. | |
3023 | */ | |
3024 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
3025 | ((crtc_state->pipe_src_h - 1) << 16) | |
3026 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 3027 | I915_WRITE(DSPPOS(plane), 0); |
920a14b2 | 3028 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
c14b0485 | 3029 | I915_WRITE(PRIMSIZE(plane), |
a8d201af ML |
3030 | ((crtc_state->pipe_src_h - 1) << 16) | |
3031 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
3032 | I915_WRITE(PRIMPOS(plane), 0); |
3033 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 3034 | } |
81255565 | 3035 | |
57779d06 VS |
3036 | switch (fb->pixel_format) { |
3037 | case DRM_FORMAT_C8: | |
81255565 JB |
3038 | dspcntr |= DISPPLANE_8BPP; |
3039 | break; | |
57779d06 | 3040 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3041 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3042 | break; |
57779d06 VS |
3043 | case DRM_FORMAT_RGB565: |
3044 | dspcntr |= DISPPLANE_BGRX565; | |
3045 | break; | |
3046 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3047 | dspcntr |= DISPPLANE_BGRX888; |
3048 | break; | |
3049 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3050 | dspcntr |= DISPPLANE_RGBX888; |
3051 | break; | |
3052 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3053 | dspcntr |= DISPPLANE_BGRX101010; |
3054 | break; | |
3055 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3056 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3057 | break; |
3058 | default: | |
baba133a | 3059 | BUG(); |
81255565 | 3060 | } |
57779d06 | 3061 | |
72618ebf | 3062 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3063 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3064 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3065 | |
df0cd455 VS |
3066 | if (rotation & DRM_ROTATE_180) |
3067 | dspcntr |= DISPPLANE_ROTATE_180; | |
3068 | ||
4ea7be2b VS |
3069 | if (rotation & DRM_REFLECT_X) |
3070 | dspcntr |= DISPPLANE_MIRROR; | |
3071 | ||
9beb5fea | 3072 | if (IS_G4X(dev_priv)) |
de1aa629 VS |
3073 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
3074 | ||
2949056c | 3075 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
81255565 | 3076 | |
6315b5d3 | 3077 | if (INTEL_GEN(dev_priv) >= 4) |
c2c75131 | 3078 | intel_crtc->dspaddr_offset = |
2949056c | 3079 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
e506a0c6 | 3080 | |
f22aa143 | 3081 | if (rotation & DRM_ROTATE_180) { |
df0cd455 VS |
3082 | x += crtc_state->pipe_src_w - 1; |
3083 | y += crtc_state->pipe_src_h - 1; | |
4ea7be2b VS |
3084 | } else if (rotation & DRM_REFLECT_X) { |
3085 | x += crtc_state->pipe_src_w - 1; | |
48404c1e SJ |
3086 | } |
3087 | ||
2949056c | 3088 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3089 | |
6315b5d3 | 3090 | if (INTEL_GEN(dev_priv) < 4) |
6687c906 VS |
3091 | intel_crtc->dspaddr_offset = linear_offset; |
3092 | ||
2db3366b PZ |
3093 | intel_crtc->adjusted_x = x; |
3094 | intel_crtc->adjusted_y = y; | |
3095 | ||
48404c1e SJ |
3096 | I915_WRITE(reg, dspcntr); |
3097 | ||
01f2c773 | 3098 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
6315b5d3 | 3099 | if (INTEL_GEN(dev_priv) >= 4) { |
85ba7b7d | 3100 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3101 | intel_fb_gtt_offset(fb, rotation) + |
3102 | intel_crtc->dspaddr_offset); | |
5eddb70b | 3103 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 3104 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
bfb81049 VS |
3105 | } else { |
3106 | I915_WRITE(DSPADDR(plane), | |
3107 | intel_fb_gtt_offset(fb, rotation) + | |
3108 | intel_crtc->dspaddr_offset); | |
3109 | } | |
5eddb70b | 3110 | POSTING_READ(reg); |
17638cd6 JB |
3111 | } |
3112 | ||
a8d201af ML |
3113 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
3114 | struct drm_crtc *crtc) | |
17638cd6 JB |
3115 | { |
3116 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3117 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 3118 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 3119 | int plane = intel_crtc->plane; |
f45651ba | 3120 | |
a8d201af ML |
3121 | I915_WRITE(DSPCNTR(plane), 0); |
3122 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 3123 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
3124 | else |
3125 | I915_WRITE(DSPADDR(plane), 0); | |
3126 | POSTING_READ(DSPCNTR(plane)); | |
3127 | } | |
c9ba6fad | 3128 | |
a8d201af ML |
3129 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
3130 | const struct intel_crtc_state *crtc_state, | |
3131 | const struct intel_plane_state *plane_state) | |
3132 | { | |
3133 | struct drm_device *dev = primary->dev; | |
fac5e23e | 3134 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3135 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3136 | struct drm_framebuffer *fb = plane_state->base.fb; | |
a8d201af | 3137 | int plane = intel_crtc->plane; |
54ea9da8 | 3138 | u32 linear_offset; |
a8d201af ML |
3139 | u32 dspcntr; |
3140 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 3141 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3142 | int x = plane_state->base.src.x1 >> 16; |
3143 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3144 | |
f45651ba | 3145 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 3146 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 3147 | |
8652744b | 3148 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f45651ba | 3149 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
17638cd6 | 3150 | |
57779d06 VS |
3151 | switch (fb->pixel_format) { |
3152 | case DRM_FORMAT_C8: | |
17638cd6 JB |
3153 | dspcntr |= DISPPLANE_8BPP; |
3154 | break; | |
57779d06 VS |
3155 | case DRM_FORMAT_RGB565: |
3156 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 3157 | break; |
57779d06 | 3158 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
3159 | dspcntr |= DISPPLANE_BGRX888; |
3160 | break; | |
3161 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3162 | dspcntr |= DISPPLANE_RGBX888; |
3163 | break; | |
3164 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3165 | dspcntr |= DISPPLANE_BGRX101010; |
3166 | break; | |
3167 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3168 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
3169 | break; |
3170 | default: | |
baba133a | 3171 | BUG(); |
17638cd6 JB |
3172 | } |
3173 | ||
bae781b2 | 3174 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
17638cd6 | 3175 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 3176 | |
df0cd455 VS |
3177 | if (rotation & DRM_ROTATE_180) |
3178 | dspcntr |= DISPPLANE_ROTATE_180; | |
3179 | ||
8652744b | 3180 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) |
1f5d76db | 3181 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 3182 | |
2949056c | 3183 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
6687c906 | 3184 | |
c2c75131 | 3185 | intel_crtc->dspaddr_offset = |
2949056c | 3186 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
6687c906 | 3187 | |
df0cd455 VS |
3188 | /* HSW+ does this automagically in hardware */ |
3189 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) && | |
3190 | rotation & DRM_ROTATE_180) { | |
3191 | x += crtc_state->pipe_src_w - 1; | |
3192 | y += crtc_state->pipe_src_h - 1; | |
48404c1e SJ |
3193 | } |
3194 | ||
2949056c | 3195 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3196 | |
2db3366b PZ |
3197 | intel_crtc->adjusted_x = x; |
3198 | intel_crtc->adjusted_y = y; | |
3199 | ||
48404c1e | 3200 | I915_WRITE(reg, dspcntr); |
17638cd6 | 3201 | |
01f2c773 | 3202 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d | 3203 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3204 | intel_fb_gtt_offset(fb, rotation) + |
3205 | intel_crtc->dspaddr_offset); | |
8652744b | 3206 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
bc1c91eb DL |
3207 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
3208 | } else { | |
3209 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
3210 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
3211 | } | |
17638cd6 | 3212 | POSTING_READ(reg); |
17638cd6 JB |
3213 | } |
3214 | ||
7b49f948 VS |
3215 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
3216 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 3217 | { |
7b49f948 | 3218 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 3219 | return 64; |
7b49f948 VS |
3220 | } else { |
3221 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
3222 | ||
27ba3910 | 3223 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
3224 | } |
3225 | } | |
3226 | ||
6687c906 VS |
3227 | u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, |
3228 | unsigned int rotation) | |
121920fa | 3229 | { |
6687c906 | 3230 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ce7f1728 | 3231 | struct i915_ggtt_view view; |
058d88c4 | 3232 | struct i915_vma *vma; |
121920fa | 3233 | |
6687c906 | 3234 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
dedf278c | 3235 | |
058d88c4 CW |
3236 | vma = i915_gem_object_to_ggtt(obj, &view); |
3237 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", | |
3238 | view.type)) | |
3239 | return -1; | |
3240 | ||
bde13ebd | 3241 | return i915_ggtt_offset(vma); |
121920fa TU |
3242 | } |
3243 | ||
e435d6e5 ML |
3244 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3245 | { | |
3246 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3247 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3248 | |
3249 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3250 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3251 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3252 | } |
3253 | ||
a1b2278e CK |
3254 | /* |
3255 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3256 | */ | |
0583236e | 3257 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3258 | { |
a1b2278e CK |
3259 | struct intel_crtc_scaler_state *scaler_state; |
3260 | int i; | |
3261 | ||
a1b2278e CK |
3262 | scaler_state = &intel_crtc->config->scaler_state; |
3263 | ||
3264 | /* loop through and disable scalers that aren't in use */ | |
3265 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3266 | if (!scaler_state->scalers[i].in_use) |
3267 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3268 | } |
3269 | } | |
3270 | ||
d2196774 VS |
3271 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3272 | unsigned int rotation) | |
3273 | { | |
3274 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
3275 | u32 stride = intel_fb_pitch(fb, plane, rotation); | |
3276 | ||
3277 | /* | |
3278 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3279 | * linear buffers or in number of tiles for tiled buffers. | |
3280 | */ | |
bd2ef25d | 3281 | if (drm_rotation_90_or_270(rotation)) { |
d2196774 VS |
3282 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
3283 | ||
bae781b2 | 3284 | stride /= intel_tile_height(dev_priv, fb->modifier, cpp); |
d2196774 | 3285 | } else { |
bae781b2 | 3286 | stride /= intel_fb_stride_alignment(dev_priv, fb->modifier, |
d2196774 VS |
3287 | fb->pixel_format); |
3288 | } | |
3289 | ||
3290 | return stride; | |
3291 | } | |
3292 | ||
6156a456 | 3293 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3294 | { |
6156a456 | 3295 | switch (pixel_format) { |
d161cf7a | 3296 | case DRM_FORMAT_C8: |
c34ce3d1 | 3297 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3298 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3299 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3300 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3301 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3302 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3303 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3304 | /* |
3305 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3306 | * to be already pre-multiplied. We need to add a knob (or a different | |
3307 | * DRM_FORMAT) for user-space to configure that. | |
3308 | */ | |
f75fb42a | 3309 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3310 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3311 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3312 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3313 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3314 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3315 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3316 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3317 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3318 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3319 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3320 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3321 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3322 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3323 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3324 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3325 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3326 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3327 | default: |
4249eeef | 3328 | MISSING_CASE(pixel_format); |
70d21f0e | 3329 | } |
8cfcba41 | 3330 | |
c34ce3d1 | 3331 | return 0; |
6156a456 | 3332 | } |
70d21f0e | 3333 | |
6156a456 CK |
3334 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3335 | { | |
6156a456 | 3336 | switch (fb_modifier) { |
30af77c4 | 3337 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3338 | break; |
30af77c4 | 3339 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3340 | return PLANE_CTL_TILED_X; |
b321803d | 3341 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3342 | return PLANE_CTL_TILED_Y; |
b321803d | 3343 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3344 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3345 | default: |
6156a456 | 3346 | MISSING_CASE(fb_modifier); |
70d21f0e | 3347 | } |
8cfcba41 | 3348 | |
c34ce3d1 | 3349 | return 0; |
6156a456 | 3350 | } |
70d21f0e | 3351 | |
6156a456 CK |
3352 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3353 | { | |
3b7a5119 | 3354 | switch (rotation) { |
31ad61e4 | 3355 | case DRM_ROTATE_0: |
6156a456 | 3356 | break; |
1e8df167 SJ |
3357 | /* |
3358 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3359 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3360 | */ | |
31ad61e4 | 3361 | case DRM_ROTATE_90: |
1e8df167 | 3362 | return PLANE_CTL_ROTATE_270; |
31ad61e4 | 3363 | case DRM_ROTATE_180: |
c34ce3d1 | 3364 | return PLANE_CTL_ROTATE_180; |
31ad61e4 | 3365 | case DRM_ROTATE_270: |
1e8df167 | 3366 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3367 | default: |
3368 | MISSING_CASE(rotation); | |
3369 | } | |
3370 | ||
c34ce3d1 | 3371 | return 0; |
6156a456 CK |
3372 | } |
3373 | ||
a8d201af ML |
3374 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3375 | const struct intel_crtc_state *crtc_state, | |
3376 | const struct intel_plane_state *plane_state) | |
6156a456 | 3377 | { |
a8d201af | 3378 | struct drm_device *dev = plane->dev; |
fac5e23e | 3379 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3381 | struct drm_framebuffer *fb = plane_state->base.fb; | |
8e816bb4 VS |
3382 | enum plane_id plane_id = to_intel_plane(plane)->id; |
3383 | enum pipe pipe = to_intel_plane(plane)->pipe; | |
d2196774 | 3384 | u32 plane_ctl; |
a8d201af | 3385 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3386 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3387 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3388 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3389 | int src_x = plane_state->main.x; |
3390 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3391 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3392 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3393 | int dst_x = plane_state->base.dst.x1; | |
3394 | int dst_y = plane_state->base.dst.y1; | |
3395 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3396 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
70d21f0e | 3397 | |
6156a456 CK |
3398 | plane_ctl = PLANE_CTL_ENABLE | |
3399 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3400 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3401 | ||
3402 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
bae781b2 | 3403 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); |
6156a456 | 3404 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; |
6156a456 CK |
3405 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3406 | ||
6687c906 VS |
3407 | /* Sizes are 0 based */ |
3408 | src_w--; | |
3409 | src_h--; | |
3410 | dst_w--; | |
3411 | dst_h--; | |
3412 | ||
4c0b8a8b PZ |
3413 | intel_crtc->dspaddr_offset = surf_addr; |
3414 | ||
6687c906 VS |
3415 | intel_crtc->adjusted_x = src_x; |
3416 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3417 | |
8e816bb4 VS |
3418 | I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl); |
3419 | I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3420 | I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride); | |
3421 | I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
6156a456 CK |
3422 | |
3423 | if (scaler_id >= 0) { | |
3424 | uint32_t ps_ctrl = 0; | |
3425 | ||
3426 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3427 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 CK |
3428 | crtc_state->scaler_state.scalers[scaler_id].mode; |
3429 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3430 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3431 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3432 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
8e816bb4 | 3433 | I915_WRITE(PLANE_POS(pipe, plane_id), 0); |
6156a456 | 3434 | } else { |
8e816bb4 | 3435 | I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3436 | } |
3437 | ||
8e816bb4 | 3438 | I915_WRITE(PLANE_SURF(pipe, plane_id), |
6687c906 | 3439 | intel_fb_gtt_offset(fb, rotation) + surf_addr); |
70d21f0e | 3440 | |
8e816bb4 | 3441 | POSTING_READ(PLANE_SURF(pipe, plane_id)); |
70d21f0e DL |
3442 | } |
3443 | ||
a8d201af ML |
3444 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3445 | struct drm_crtc *crtc) | |
17638cd6 JB |
3446 | { |
3447 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3448 | struct drm_i915_private *dev_priv = to_i915(dev); |
8e816bb4 VS |
3449 | enum plane_id plane_id = to_intel_plane(primary)->id; |
3450 | enum pipe pipe = to_intel_plane(primary)->pipe; | |
62e0fb88 | 3451 | |
8e816bb4 VS |
3452 | I915_WRITE(PLANE_CTL(pipe, plane_id), 0); |
3453 | I915_WRITE(PLANE_SURF(pipe, plane_id), 0); | |
3454 | POSTING_READ(PLANE_SURF(pipe, plane_id)); | |
a8d201af | 3455 | } |
29b9bde6 | 3456 | |
a8d201af ML |
3457 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3458 | static int | |
3459 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3460 | int x, int y, enum mode_set_atomic state) | |
3461 | { | |
3462 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3463 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3464 | ||
3465 | return -ENODEV; | |
81255565 JB |
3466 | } |
3467 | ||
5a21b665 DV |
3468 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3469 | { | |
3470 | struct intel_crtc *crtc; | |
3471 | ||
91c8a326 | 3472 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3473 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3474 | } | |
3475 | ||
7514747d VS |
3476 | static void intel_update_primary_planes(struct drm_device *dev) |
3477 | { | |
7514747d | 3478 | struct drm_crtc *crtc; |
96a02917 | 3479 | |
70e1e0ec | 3480 | for_each_crtc(dev, crtc) { |
11c22da6 | 3481 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3482 | struct intel_plane_state *plane_state = |
3483 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3484 | |
936e71e3 | 3485 | if (plane_state->base.visible) |
a8d201af ML |
3486 | plane->update_plane(&plane->base, |
3487 | to_intel_crtc_state(crtc->state), | |
3488 | plane_state); | |
73974893 ML |
3489 | } |
3490 | } | |
3491 | ||
3492 | static int | |
3493 | __intel_display_resume(struct drm_device *dev, | |
3494 | struct drm_atomic_state *state) | |
3495 | { | |
3496 | struct drm_crtc_state *crtc_state; | |
3497 | struct drm_crtc *crtc; | |
3498 | int i, ret; | |
11c22da6 | 3499 | |
73974893 | 3500 | intel_modeset_setup_hw_state(dev); |
29b74b7f | 3501 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3502 | |
3503 | if (!state) | |
3504 | return 0; | |
3505 | ||
3506 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3507 | /* | |
3508 | * Force recalculation even if we restore | |
3509 | * current state. With fast modeset this may not result | |
3510 | * in a modeset when the state is compatible. | |
3511 | */ | |
3512 | crtc_state->mode_changed = true; | |
96a02917 | 3513 | } |
73974893 ML |
3514 | |
3515 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
3516 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
3517 | ||
3518 | ret = drm_atomic_commit(state); | |
3519 | ||
3520 | WARN_ON(ret == -EDEADLK); | |
3521 | return ret; | |
96a02917 VS |
3522 | } |
3523 | ||
4ac2ba2f VS |
3524 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3525 | { | |
ae98104b VS |
3526 | return intel_has_gpu_reset(dev_priv) && |
3527 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3528 | } |
3529 | ||
c033666a | 3530 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3531 | { |
73974893 ML |
3532 | struct drm_device *dev = &dev_priv->drm; |
3533 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3534 | struct drm_atomic_state *state; | |
3535 | int ret; | |
3536 | ||
73974893 ML |
3537 | /* |
3538 | * Need mode_config.mutex so that we don't | |
3539 | * trample ongoing ->detect() and whatnot. | |
3540 | */ | |
3541 | mutex_lock(&dev->mode_config.mutex); | |
3542 | drm_modeset_acquire_init(ctx, 0); | |
3543 | while (1) { | |
3544 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3545 | if (ret != -EDEADLK) | |
3546 | break; | |
3547 | ||
3548 | drm_modeset_backoff(ctx); | |
3549 | } | |
3550 | ||
3551 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3552 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3553 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3554 | return; |
3555 | ||
f98ce92f VS |
3556 | /* |
3557 | * Disabling the crtcs gracefully seems nicer. Also the | |
3558 | * g33 docs say we should at least disable all the planes. | |
3559 | */ | |
73974893 ML |
3560 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3561 | if (IS_ERR(state)) { | |
3562 | ret = PTR_ERR(state); | |
3563 | state = NULL; | |
3564 | DRM_ERROR("Duplicating state failed with %i\n", ret); | |
3565 | goto err; | |
3566 | } | |
3567 | ||
3568 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3569 | if (ret) { | |
3570 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
3571 | goto err; | |
3572 | } | |
3573 | ||
3574 | dev_priv->modeset_restore_state = state; | |
3575 | state->acquire_ctx = ctx; | |
3576 | return; | |
3577 | ||
3578 | err: | |
0853695c | 3579 | drm_atomic_state_put(state); |
7514747d VS |
3580 | } |
3581 | ||
c033666a | 3582 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3583 | { |
73974893 ML |
3584 | struct drm_device *dev = &dev_priv->drm; |
3585 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3586 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3587 | int ret; | |
3588 | ||
5a21b665 DV |
3589 | /* |
3590 | * Flips in the rings will be nuked by the reset, | |
3591 | * so complete all pending flips so that user space | |
3592 | * will get its events and not get stuck. | |
3593 | */ | |
3594 | intel_complete_page_flips(dev_priv); | |
3595 | ||
73974893 ML |
3596 | dev_priv->modeset_restore_state = NULL; |
3597 | ||
7514747d | 3598 | /* reset doesn't touch the display */ |
4ac2ba2f | 3599 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3600 | if (!state) { |
3601 | /* | |
3602 | * Flips in the rings have been nuked by the reset, | |
3603 | * so update the base address of all primary | |
3604 | * planes to the the last fb to make sure we're | |
3605 | * showing the correct fb after a reset. | |
3606 | * | |
3607 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3608 | * CS-based flips (which might get lost in gpu resets) any more. | |
3609 | */ | |
3610 | intel_update_primary_planes(dev); | |
3611 | } else { | |
3612 | ret = __intel_display_resume(dev, state); | |
3613 | if (ret) | |
3614 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3615 | } | |
73974893 ML |
3616 | } else { |
3617 | /* | |
3618 | * The display has been reset as well, | |
3619 | * so need a full re-initialization. | |
3620 | */ | |
3621 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3622 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3623 | |
51f59205 | 3624 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3625 | intel_modeset_init_hw(dev); |
7514747d | 3626 | |
73974893 ML |
3627 | spin_lock_irq(&dev_priv->irq_lock); |
3628 | if (dev_priv->display.hpd_irq_setup) | |
3629 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3630 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3631 | |
73974893 ML |
3632 | ret = __intel_display_resume(dev, state); |
3633 | if (ret) | |
3634 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3635 | |
73974893 ML |
3636 | intel_hpd_init(dev_priv); |
3637 | } | |
7514747d | 3638 | |
0853695c CW |
3639 | if (state) |
3640 | drm_atomic_state_put(state); | |
73974893 ML |
3641 | drm_modeset_drop_locks(ctx); |
3642 | drm_modeset_acquire_fini(ctx); | |
3643 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3644 | } |
3645 | ||
8af29b0c CW |
3646 | static bool abort_flip_on_reset(struct intel_crtc *crtc) |
3647 | { | |
3648 | struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; | |
3649 | ||
3650 | if (i915_reset_in_progress(error)) | |
3651 | return true; | |
3652 | ||
3653 | if (crtc->reset_count != i915_reset_count(error)) | |
3654 | return true; | |
3655 | ||
3656 | return false; | |
3657 | } | |
3658 | ||
7d5e3799 CW |
3659 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3660 | { | |
5a21b665 DV |
3661 | struct drm_device *dev = crtc->dev; |
3662 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5a21b665 DV |
3663 | bool pending; |
3664 | ||
8af29b0c | 3665 | if (abort_flip_on_reset(intel_crtc)) |
5a21b665 DV |
3666 | return false; |
3667 | ||
3668 | spin_lock_irq(&dev->event_lock); | |
3669 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3670 | spin_unlock_irq(&dev->event_lock); | |
3671 | ||
3672 | return pending; | |
7d5e3799 CW |
3673 | } |
3674 | ||
bfd16b2a ML |
3675 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3676 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3677 | { |
6315b5d3 | 3678 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3679 | struct intel_crtc_state *pipe_config = |
3680 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3681 | |
bfd16b2a ML |
3682 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3683 | crtc->base.mode = crtc->base.state->mode; | |
3684 | ||
3685 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3686 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3687 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3688 | |
3689 | /* | |
3690 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3691 | * that in compute_mode_changes we check the native mode (not the pfit | |
3692 | * mode) to see if we can flip rather than do a full mode set. In the | |
3693 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3694 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3695 | * sized surface. | |
e30e8f75 GP |
3696 | */ |
3697 | ||
e30e8f75 | 3698 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3699 | ((pipe_config->pipe_src_w - 1) << 16) | |
3700 | (pipe_config->pipe_src_h - 1)); | |
3701 | ||
3702 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3703 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3704 | skl_detach_scalers(crtc); |
3705 | ||
3706 | if (pipe_config->pch_pfit.enabled) | |
3707 | skylake_pfit_enable(crtc); | |
6e266956 | 3708 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3709 | if (pipe_config->pch_pfit.enabled) |
3710 | ironlake_pfit_enable(crtc); | |
3711 | else if (old_crtc_state->pch_pfit.enabled) | |
3712 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3713 | } |
e30e8f75 GP |
3714 | } |
3715 | ||
5e84e1a4 ZW |
3716 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3717 | { | |
3718 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3719 | struct drm_i915_private *dev_priv = to_i915(dev); |
5e84e1a4 ZW |
3720 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3721 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3722 | i915_reg_t reg; |
3723 | u32 temp; | |
5e84e1a4 ZW |
3724 | |
3725 | /* enable normal train */ | |
3726 | reg = FDI_TX_CTL(pipe); | |
3727 | temp = I915_READ(reg); | |
fd6b8f43 | 3728 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3729 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3730 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3731 | } else { |
3732 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3733 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3734 | } |
5e84e1a4 ZW |
3735 | I915_WRITE(reg, temp); |
3736 | ||
3737 | reg = FDI_RX_CTL(pipe); | |
3738 | temp = I915_READ(reg); | |
6e266956 | 3739 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3740 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3741 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3742 | } else { | |
3743 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3744 | temp |= FDI_LINK_TRAIN_NONE; | |
3745 | } | |
3746 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3747 | ||
3748 | /* wait one idle pattern time */ | |
3749 | POSTING_READ(reg); | |
3750 | udelay(1000); | |
357555c0 JB |
3751 | |
3752 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3753 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3754 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3755 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3756 | } |
3757 | ||
8db9d77b ZW |
3758 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3759 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3760 | { | |
3761 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3762 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3763 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3764 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3765 | i915_reg_t reg; |
3766 | u32 temp, tries; | |
8db9d77b | 3767 | |
1c8562f6 | 3768 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3769 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3770 | |
e1a44743 AJ |
3771 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3772 | for train result */ | |
5eddb70b CW |
3773 | reg = FDI_RX_IMR(pipe); |
3774 | temp = I915_READ(reg); | |
e1a44743 AJ |
3775 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3776 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3777 | I915_WRITE(reg, temp); |
3778 | I915_READ(reg); | |
e1a44743 AJ |
3779 | udelay(150); |
3780 | ||
8db9d77b | 3781 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3782 | reg = FDI_TX_CTL(pipe); |
3783 | temp = I915_READ(reg); | |
627eb5a3 | 3784 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3785 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3786 | temp &= ~FDI_LINK_TRAIN_NONE; |
3787 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3788 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3789 | |
5eddb70b CW |
3790 | reg = FDI_RX_CTL(pipe); |
3791 | temp = I915_READ(reg); | |
8db9d77b ZW |
3792 | temp &= ~FDI_LINK_TRAIN_NONE; |
3793 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3794 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3795 | ||
3796 | POSTING_READ(reg); | |
8db9d77b ZW |
3797 | udelay(150); |
3798 | ||
5b2adf89 | 3799 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3800 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3801 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3802 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3803 | |
5eddb70b | 3804 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3805 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3806 | temp = I915_READ(reg); |
8db9d77b ZW |
3807 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3808 | ||
3809 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3810 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3811 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3812 | break; |
3813 | } | |
8db9d77b | 3814 | } |
e1a44743 | 3815 | if (tries == 5) |
5eddb70b | 3816 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3817 | |
3818 | /* Train 2 */ | |
5eddb70b CW |
3819 | reg = FDI_TX_CTL(pipe); |
3820 | temp = I915_READ(reg); | |
8db9d77b ZW |
3821 | temp &= ~FDI_LINK_TRAIN_NONE; |
3822 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3823 | I915_WRITE(reg, temp); |
8db9d77b | 3824 | |
5eddb70b CW |
3825 | reg = FDI_RX_CTL(pipe); |
3826 | temp = I915_READ(reg); | |
8db9d77b ZW |
3827 | temp &= ~FDI_LINK_TRAIN_NONE; |
3828 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3829 | I915_WRITE(reg, temp); |
8db9d77b | 3830 | |
5eddb70b CW |
3831 | POSTING_READ(reg); |
3832 | udelay(150); | |
8db9d77b | 3833 | |
5eddb70b | 3834 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3835 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3836 | temp = I915_READ(reg); |
8db9d77b ZW |
3837 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3838 | ||
3839 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3840 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3841 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3842 | break; | |
3843 | } | |
8db9d77b | 3844 | } |
e1a44743 | 3845 | if (tries == 5) |
5eddb70b | 3846 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3847 | |
3848 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3849 | |
8db9d77b ZW |
3850 | } |
3851 | ||
0206e353 | 3852 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3853 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3854 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3855 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3856 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3857 | }; | |
3858 | ||
3859 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3860 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3861 | { | |
3862 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3863 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3864 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3865 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3866 | i915_reg_t reg; |
3867 | u32 temp, i, retry; | |
8db9d77b | 3868 | |
e1a44743 AJ |
3869 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3870 | for train result */ | |
5eddb70b CW |
3871 | reg = FDI_RX_IMR(pipe); |
3872 | temp = I915_READ(reg); | |
e1a44743 AJ |
3873 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3874 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3875 | I915_WRITE(reg, temp); |
3876 | ||
3877 | POSTING_READ(reg); | |
e1a44743 AJ |
3878 | udelay(150); |
3879 | ||
8db9d77b | 3880 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3881 | reg = FDI_TX_CTL(pipe); |
3882 | temp = I915_READ(reg); | |
627eb5a3 | 3883 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3884 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3885 | temp &= ~FDI_LINK_TRAIN_NONE; |
3886 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3887 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3888 | /* SNB-B */ | |
3889 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3890 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3891 | |
d74cf324 DV |
3892 | I915_WRITE(FDI_RX_MISC(pipe), |
3893 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3894 | ||
5eddb70b CW |
3895 | reg = FDI_RX_CTL(pipe); |
3896 | temp = I915_READ(reg); | |
6e266956 | 3897 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3898 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3899 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3900 | } else { | |
3901 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3902 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3903 | } | |
5eddb70b CW |
3904 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3905 | ||
3906 | POSTING_READ(reg); | |
8db9d77b ZW |
3907 | udelay(150); |
3908 | ||
0206e353 | 3909 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3910 | reg = FDI_TX_CTL(pipe); |
3911 | temp = I915_READ(reg); | |
8db9d77b ZW |
3912 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3913 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3914 | I915_WRITE(reg, temp); |
3915 | ||
3916 | POSTING_READ(reg); | |
8db9d77b ZW |
3917 | udelay(500); |
3918 | ||
fa37d39e SP |
3919 | for (retry = 0; retry < 5; retry++) { |
3920 | reg = FDI_RX_IIR(pipe); | |
3921 | temp = I915_READ(reg); | |
3922 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3923 | if (temp & FDI_RX_BIT_LOCK) { | |
3924 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3925 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3926 | break; | |
3927 | } | |
3928 | udelay(50); | |
8db9d77b | 3929 | } |
fa37d39e SP |
3930 | if (retry < 5) |
3931 | break; | |
8db9d77b ZW |
3932 | } |
3933 | if (i == 4) | |
5eddb70b | 3934 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3935 | |
3936 | /* Train 2 */ | |
5eddb70b CW |
3937 | reg = FDI_TX_CTL(pipe); |
3938 | temp = I915_READ(reg); | |
8db9d77b ZW |
3939 | temp &= ~FDI_LINK_TRAIN_NONE; |
3940 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3941 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3942 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3943 | /* SNB-B */ | |
3944 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3945 | } | |
5eddb70b | 3946 | I915_WRITE(reg, temp); |
8db9d77b | 3947 | |
5eddb70b CW |
3948 | reg = FDI_RX_CTL(pipe); |
3949 | temp = I915_READ(reg); | |
6e266956 | 3950 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3951 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3952 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3953 | } else { | |
3954 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3955 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3956 | } | |
5eddb70b CW |
3957 | I915_WRITE(reg, temp); |
3958 | ||
3959 | POSTING_READ(reg); | |
8db9d77b ZW |
3960 | udelay(150); |
3961 | ||
0206e353 | 3962 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3963 | reg = FDI_TX_CTL(pipe); |
3964 | temp = I915_READ(reg); | |
8db9d77b ZW |
3965 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3966 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3967 | I915_WRITE(reg, temp); |
3968 | ||
3969 | POSTING_READ(reg); | |
8db9d77b ZW |
3970 | udelay(500); |
3971 | ||
fa37d39e SP |
3972 | for (retry = 0; retry < 5; retry++) { |
3973 | reg = FDI_RX_IIR(pipe); | |
3974 | temp = I915_READ(reg); | |
3975 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3976 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3977 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3978 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3979 | break; | |
3980 | } | |
3981 | udelay(50); | |
8db9d77b | 3982 | } |
fa37d39e SP |
3983 | if (retry < 5) |
3984 | break; | |
8db9d77b ZW |
3985 | } |
3986 | if (i == 4) | |
5eddb70b | 3987 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3988 | |
3989 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3990 | } | |
3991 | ||
357555c0 JB |
3992 | /* Manual link training for Ivy Bridge A0 parts */ |
3993 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3994 | { | |
3995 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3996 | struct drm_i915_private *dev_priv = to_i915(dev); |
357555c0 JB |
3997 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3998 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3999 | i915_reg_t reg; |
4000 | u32 temp, i, j; | |
357555c0 JB |
4001 | |
4002 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
4003 | for train result */ | |
4004 | reg = FDI_RX_IMR(pipe); | |
4005 | temp = I915_READ(reg); | |
4006 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
4007 | temp &= ~FDI_RX_BIT_LOCK; | |
4008 | I915_WRITE(reg, temp); | |
4009 | ||
4010 | POSTING_READ(reg); | |
4011 | udelay(150); | |
4012 | ||
01a415fd DV |
4013 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
4014 | I915_READ(FDI_RX_IIR(pipe))); | |
4015 | ||
139ccd3f JB |
4016 | /* Try each vswing and preemphasis setting twice before moving on */ |
4017 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
4018 | /* disable first in case we need to retry */ | |
4019 | reg = FDI_TX_CTL(pipe); | |
4020 | temp = I915_READ(reg); | |
4021 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
4022 | temp &= ~FDI_TX_ENABLE; | |
4023 | I915_WRITE(reg, temp); | |
357555c0 | 4024 | |
139ccd3f JB |
4025 | reg = FDI_RX_CTL(pipe); |
4026 | temp = I915_READ(reg); | |
4027 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
4028 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4029 | temp &= ~FDI_RX_ENABLE; | |
4030 | I915_WRITE(reg, temp); | |
357555c0 | 4031 | |
139ccd3f | 4032 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
4033 | reg = FDI_TX_CTL(pipe); |
4034 | temp = I915_READ(reg); | |
139ccd3f | 4035 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 4036 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 4037 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 4038 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4039 | temp |= snb_b_fdi_train_param[j/2]; |
4040 | temp |= FDI_COMPOSITE_SYNC; | |
4041 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4042 | |
139ccd3f JB |
4043 | I915_WRITE(FDI_RX_MISC(pipe), |
4044 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4045 | |
139ccd3f | 4046 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4047 | temp = I915_READ(reg); |
139ccd3f JB |
4048 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4049 | temp |= FDI_COMPOSITE_SYNC; | |
4050 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4051 | |
139ccd3f JB |
4052 | POSTING_READ(reg); |
4053 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4054 | |
139ccd3f JB |
4055 | for (i = 0; i < 4; i++) { |
4056 | reg = FDI_RX_IIR(pipe); | |
4057 | temp = I915_READ(reg); | |
4058 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4059 | |
139ccd3f JB |
4060 | if (temp & FDI_RX_BIT_LOCK || |
4061 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4062 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4063 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4064 | i); | |
4065 | break; | |
4066 | } | |
4067 | udelay(1); /* should be 0.5us */ | |
4068 | } | |
4069 | if (i == 4) { | |
4070 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4071 | continue; | |
4072 | } | |
357555c0 | 4073 | |
139ccd3f | 4074 | /* Train 2 */ |
357555c0 JB |
4075 | reg = FDI_TX_CTL(pipe); |
4076 | temp = I915_READ(reg); | |
139ccd3f JB |
4077 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4078 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4079 | I915_WRITE(reg, temp); | |
4080 | ||
4081 | reg = FDI_RX_CTL(pipe); | |
4082 | temp = I915_READ(reg); | |
4083 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4084 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4085 | I915_WRITE(reg, temp); |
4086 | ||
4087 | POSTING_READ(reg); | |
139ccd3f | 4088 | udelay(2); /* should be 1.5us */ |
357555c0 | 4089 | |
139ccd3f JB |
4090 | for (i = 0; i < 4; i++) { |
4091 | reg = FDI_RX_IIR(pipe); | |
4092 | temp = I915_READ(reg); | |
4093 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4094 | |
139ccd3f JB |
4095 | if (temp & FDI_RX_SYMBOL_LOCK || |
4096 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4097 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4098 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4099 | i); | |
4100 | goto train_done; | |
4101 | } | |
4102 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4103 | } |
139ccd3f JB |
4104 | if (i == 4) |
4105 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4106 | } |
357555c0 | 4107 | |
139ccd3f | 4108 | train_done: |
357555c0 JB |
4109 | DRM_DEBUG_KMS("FDI train done.\n"); |
4110 | } | |
4111 | ||
88cefb6c | 4112 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4113 | { |
88cefb6c | 4114 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4115 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4116 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4117 | i915_reg_t reg; |
4118 | u32 temp; | |
c64e311e | 4119 | |
c98e9dcf | 4120 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4121 | reg = FDI_RX_CTL(pipe); |
4122 | temp = I915_READ(reg); | |
627eb5a3 | 4123 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4124 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4125 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4126 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4127 | ||
4128 | POSTING_READ(reg); | |
c98e9dcf JB |
4129 | udelay(200); |
4130 | ||
4131 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4132 | temp = I915_READ(reg); |
4133 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4134 | ||
4135 | POSTING_READ(reg); | |
c98e9dcf JB |
4136 | udelay(200); |
4137 | ||
20749730 PZ |
4138 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4139 | reg = FDI_TX_CTL(pipe); | |
4140 | temp = I915_READ(reg); | |
4141 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4142 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4143 | |
20749730 PZ |
4144 | POSTING_READ(reg); |
4145 | udelay(100); | |
6be4a607 | 4146 | } |
0e23b99d JB |
4147 | } |
4148 | ||
88cefb6c DV |
4149 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4150 | { | |
4151 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4152 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4153 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4154 | i915_reg_t reg; |
4155 | u32 temp; | |
88cefb6c DV |
4156 | |
4157 | /* Switch from PCDclk to Rawclk */ | |
4158 | reg = FDI_RX_CTL(pipe); | |
4159 | temp = I915_READ(reg); | |
4160 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4161 | ||
4162 | /* Disable CPU FDI TX PLL */ | |
4163 | reg = FDI_TX_CTL(pipe); | |
4164 | temp = I915_READ(reg); | |
4165 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4166 | ||
4167 | POSTING_READ(reg); | |
4168 | udelay(100); | |
4169 | ||
4170 | reg = FDI_RX_CTL(pipe); | |
4171 | temp = I915_READ(reg); | |
4172 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4173 | ||
4174 | /* Wait for the clocks to turn off. */ | |
4175 | POSTING_READ(reg); | |
4176 | udelay(100); | |
4177 | } | |
4178 | ||
0fc932b8 JB |
4179 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4180 | { | |
4181 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4182 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4184 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4185 | i915_reg_t reg; |
4186 | u32 temp; | |
0fc932b8 JB |
4187 | |
4188 | /* disable CPU FDI tx and PCH FDI rx */ | |
4189 | reg = FDI_TX_CTL(pipe); | |
4190 | temp = I915_READ(reg); | |
4191 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4192 | POSTING_READ(reg); | |
4193 | ||
4194 | reg = FDI_RX_CTL(pipe); | |
4195 | temp = I915_READ(reg); | |
4196 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4197 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4198 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4199 | ||
4200 | POSTING_READ(reg); | |
4201 | udelay(100); | |
4202 | ||
4203 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4204 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4205 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4206 | |
4207 | /* still set train pattern 1 */ | |
4208 | reg = FDI_TX_CTL(pipe); | |
4209 | temp = I915_READ(reg); | |
4210 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4211 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4212 | I915_WRITE(reg, temp); | |
4213 | ||
4214 | reg = FDI_RX_CTL(pipe); | |
4215 | temp = I915_READ(reg); | |
6e266956 | 4216 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4217 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4218 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4219 | } else { | |
4220 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4221 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4222 | } | |
4223 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4224 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4225 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4226 | I915_WRITE(reg, temp); |
4227 | ||
4228 | POSTING_READ(reg); | |
4229 | udelay(100); | |
4230 | } | |
4231 | ||
49d73912 | 4232 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 CW |
4233 | { |
4234 | struct intel_crtc *crtc; | |
4235 | ||
4236 | /* Note that we don't need to be called with mode_config.lock here | |
4237 | * as our list of CRTC objects is static for the lifetime of the | |
4238 | * device and so cannot disappear as we iterate. Similarly, we can | |
4239 | * happily treat the predicates as racy, atomic checks as userspace | |
4240 | * cannot claim and pin a new fb without at least acquring the | |
4241 | * struct_mutex and so serialising with us. | |
4242 | */ | |
49d73912 | 4243 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
5dce5b93 CW |
4244 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4245 | continue; | |
4246 | ||
5a21b665 | 4247 | if (crtc->flip_work) |
0f0f74bc | 4248 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
5dce5b93 CW |
4249 | |
4250 | return true; | |
4251 | } | |
4252 | ||
4253 | return false; | |
4254 | } | |
4255 | ||
5a21b665 | 4256 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4257 | { |
4258 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4259 | struct intel_flip_work *work = intel_crtc->flip_work; |
4260 | ||
4261 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4262 | |
4263 | if (work->event) | |
560ce1dc | 4264 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4265 | |
4266 | drm_crtc_vblank_put(&intel_crtc->base); | |
4267 | ||
5a21b665 | 4268 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 4269 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
4270 | |
4271 | trace_i915_flip_complete(intel_crtc->plane, | |
4272 | work->pending_flip_obj); | |
d6bbafa1 CW |
4273 | } |
4274 | ||
5008e874 | 4275 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4276 | { |
0f91128d | 4277 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4278 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4279 | long ret; |
e6c3a2a6 | 4280 | |
2c10d571 | 4281 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4282 | |
4283 | ret = wait_event_interruptible_timeout( | |
4284 | dev_priv->pending_flip_queue, | |
4285 | !intel_crtc_has_pending_flip(crtc), | |
4286 | 60*HZ); | |
4287 | ||
4288 | if (ret < 0) | |
4289 | return ret; | |
4290 | ||
5a21b665 DV |
4291 | if (ret == 0) { |
4292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4293 | struct intel_flip_work *work; | |
4294 | ||
4295 | spin_lock_irq(&dev->event_lock); | |
4296 | work = intel_crtc->flip_work; | |
4297 | if (work && !is_mmio_work(work)) { | |
4298 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4299 | page_flip_completed(intel_crtc); | |
4300 | } | |
4301 | spin_unlock_irq(&dev->event_lock); | |
4302 | } | |
5bb61643 | 4303 | |
5008e874 | 4304 | return 0; |
e6c3a2a6 CW |
4305 | } |
4306 | ||
b7076546 | 4307 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4308 | { |
4309 | u32 temp; | |
4310 | ||
4311 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4312 | ||
4313 | mutex_lock(&dev_priv->sb_lock); | |
4314 | ||
4315 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4316 | temp |= SBI_SSCCTL_DISABLE; | |
4317 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4318 | ||
4319 | mutex_unlock(&dev_priv->sb_lock); | |
4320 | } | |
4321 | ||
e615efe4 ED |
4322 | /* Program iCLKIP clock to the desired frequency */ |
4323 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
4324 | { | |
64b46a06 | 4325 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 4326 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
4327 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4328 | u32 temp; | |
4329 | ||
060f02d8 | 4330 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4331 | |
64b46a06 VS |
4332 | /* The iCLK virtual clock root frequency is in MHz, |
4333 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4334 | * divisors, it is necessary to divide one by another, so we | |
4335 | * convert the virtual clock precision to KHz here for higher | |
4336 | * precision. | |
4337 | */ | |
4338 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4339 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4340 | u32 iclk_pi_range = 64; | |
64b46a06 | 4341 | u32 desired_divisor; |
e615efe4 | 4342 | |
64b46a06 VS |
4343 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4344 | clock << auxdiv); | |
4345 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4346 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4347 | |
64b46a06 VS |
4348 | /* |
4349 | * Near 20MHz is a corner case which is | |
4350 | * out of range for the 7-bit divisor | |
4351 | */ | |
4352 | if (divsel <= 0x7f) | |
4353 | break; | |
e615efe4 ED |
4354 | } |
4355 | ||
4356 | /* This should not happen with any sane values */ | |
4357 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4358 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4359 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4360 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4361 | ||
4362 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4363 | clock, |
e615efe4 ED |
4364 | auxdiv, |
4365 | divsel, | |
4366 | phasedir, | |
4367 | phaseinc); | |
4368 | ||
060f02d8 VS |
4369 | mutex_lock(&dev_priv->sb_lock); |
4370 | ||
e615efe4 | 4371 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4372 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4373 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4374 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4375 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4376 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4377 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4378 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4379 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4380 | |
4381 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4382 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4383 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4384 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4385 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4386 | |
4387 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4388 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4389 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4390 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4391 | |
060f02d8 VS |
4392 | mutex_unlock(&dev_priv->sb_lock); |
4393 | ||
e615efe4 ED |
4394 | /* Wait for initialization time */ |
4395 | udelay(24); | |
4396 | ||
4397 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4398 | } | |
4399 | ||
8802e5b6 VS |
4400 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4401 | { | |
4402 | u32 divsel, phaseinc, auxdiv; | |
4403 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4404 | u32 iclk_pi_range = 64; | |
4405 | u32 desired_divisor; | |
4406 | u32 temp; | |
4407 | ||
4408 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4409 | return 0; | |
4410 | ||
4411 | mutex_lock(&dev_priv->sb_lock); | |
4412 | ||
4413 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4414 | if (temp & SBI_SSCCTL_DISABLE) { | |
4415 | mutex_unlock(&dev_priv->sb_lock); | |
4416 | return 0; | |
4417 | } | |
4418 | ||
4419 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4420 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4421 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4422 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4423 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4424 | ||
4425 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4426 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4427 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4428 | ||
4429 | mutex_unlock(&dev_priv->sb_lock); | |
4430 | ||
4431 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4432 | ||
4433 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4434 | desired_divisor << auxdiv); | |
4435 | } | |
4436 | ||
275f01b2 DV |
4437 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4438 | enum pipe pch_transcoder) | |
4439 | { | |
4440 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4441 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4442 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4443 | |
4444 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4445 | I915_READ(HTOTAL(cpu_transcoder))); | |
4446 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4447 | I915_READ(HBLANK(cpu_transcoder))); | |
4448 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4449 | I915_READ(HSYNC(cpu_transcoder))); | |
4450 | ||
4451 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4452 | I915_READ(VTOTAL(cpu_transcoder))); | |
4453 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4454 | I915_READ(VBLANK(cpu_transcoder))); | |
4455 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4456 | I915_READ(VSYNC(cpu_transcoder))); | |
4457 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4458 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4459 | } | |
4460 | ||
003632d9 | 4461 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4462 | { |
fac5e23e | 4463 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4464 | uint32_t temp; |
4465 | ||
4466 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4467 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4468 | return; |
4469 | ||
4470 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4471 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4472 | ||
003632d9 ACO |
4473 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4474 | if (enable) | |
4475 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4476 | ||
4477 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4478 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4479 | POSTING_READ(SOUTH_CHICKEN1); | |
4480 | } | |
4481 | ||
4482 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4483 | { | |
4484 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4485 | |
4486 | switch (intel_crtc->pipe) { | |
4487 | case PIPE_A: | |
4488 | break; | |
4489 | case PIPE_B: | |
6e3c9717 | 4490 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4491 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4492 | else |
003632d9 | 4493 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4494 | |
4495 | break; | |
4496 | case PIPE_C: | |
003632d9 | 4497 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4498 | |
4499 | break; | |
4500 | default: | |
4501 | BUG(); | |
4502 | } | |
4503 | } | |
4504 | ||
c48b5305 VS |
4505 | /* Return which DP Port should be selected for Transcoder DP control */ |
4506 | static enum port | |
4507 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4508 | { | |
4509 | struct drm_device *dev = crtc->dev; | |
4510 | struct intel_encoder *encoder; | |
4511 | ||
4512 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
cca0502b | 4513 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4514 | encoder->type == INTEL_OUTPUT_EDP) |
4515 | return enc_to_dig_port(&encoder->base)->port; | |
4516 | } | |
4517 | ||
4518 | return -1; | |
4519 | } | |
4520 | ||
f67a559d JB |
4521 | /* |
4522 | * Enable PCH resources required for PCH ports: | |
4523 | * - PCH PLLs | |
4524 | * - FDI training & RX/TX | |
4525 | * - update transcoder timings | |
4526 | * - DP transcoding bits | |
4527 | * - transcoder | |
4528 | */ | |
4529 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4530 | { |
4531 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4532 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e23b99d JB |
4533 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4534 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4535 | u32 temp; |
2c07245f | 4536 | |
ab9412ba | 4537 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4538 | |
fd6b8f43 | 4539 | if (IS_IVYBRIDGE(dev_priv)) |
1fbc0d78 DV |
4540 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
4541 | ||
cd986abb DV |
4542 | /* Write the TU size bits before fdi link training, so that error |
4543 | * detection works. */ | |
4544 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4545 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4546 | ||
c98e9dcf | 4547 | /* For PCH output, training FDI link */ |
674cf967 | 4548 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4549 | |
3ad8a208 DV |
4550 | /* We need to program the right clock selection before writing the pixel |
4551 | * mutliplier into the DPLL. */ | |
6e266956 | 4552 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4553 | u32 sel; |
4b645f14 | 4554 | |
c98e9dcf | 4555 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4556 | temp |= TRANS_DPLL_ENABLE(pipe); |
4557 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4558 | if (intel_crtc->config->shared_dpll == |
4559 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4560 | temp |= sel; |
4561 | else | |
4562 | temp &= ~sel; | |
c98e9dcf | 4563 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4564 | } |
5eddb70b | 4565 | |
3ad8a208 DV |
4566 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4567 | * transcoder, and we actually should do this to not upset any PCH | |
4568 | * transcoder that already use the clock when we share it. | |
4569 | * | |
4570 | * Note that enable_shared_dpll tries to do the right thing, but | |
4571 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4572 | * the right LVDS enable sequence. */ | |
85b3894f | 4573 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4574 | |
d9b6cb56 JB |
4575 | /* set transcoder timing, panel must allow it */ |
4576 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4577 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4578 | |
303b81e0 | 4579 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4580 | |
c98e9dcf | 4581 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 TU |
4582 | if (HAS_PCH_CPT(dev_priv) && |
4583 | intel_crtc_has_dp_encoder(intel_crtc->config)) { | |
9c4edaee VS |
4584 | const struct drm_display_mode *adjusted_mode = |
4585 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4586 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4587 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4588 | temp = I915_READ(reg); |
4589 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4590 | TRANS_DP_SYNC_MASK | |
4591 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4592 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4593 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4594 | |
9c4edaee | 4595 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4596 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4597 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4598 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4599 | |
4600 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4601 | case PORT_B: |
5eddb70b | 4602 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4603 | break; |
c48b5305 | 4604 | case PORT_C: |
5eddb70b | 4605 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4606 | break; |
c48b5305 | 4607 | case PORT_D: |
5eddb70b | 4608 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4609 | break; |
4610 | default: | |
e95d41e1 | 4611 | BUG(); |
32f9d658 | 4612 | } |
2c07245f | 4613 | |
5eddb70b | 4614 | I915_WRITE(reg, temp); |
6be4a607 | 4615 | } |
b52eb4dc | 4616 | |
b8a4f404 | 4617 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4618 | } |
4619 | ||
1507e5bd PZ |
4620 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4621 | { | |
4622 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4623 | struct drm_i915_private *dev_priv = to_i915(dev); |
1507e5bd | 4624 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 4625 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4626 | |
ab9412ba | 4627 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4628 | |
8c52b5e8 | 4629 | lpt_program_iclkip(crtc); |
1507e5bd | 4630 | |
0540e488 | 4631 | /* Set transcoder timing. */ |
275f01b2 | 4632 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4633 | |
937bb610 | 4634 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4635 | } |
4636 | ||
a1520318 | 4637 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4638 | { |
fac5e23e | 4639 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4640 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4641 | u32 temp; |
4642 | ||
4643 | temp = I915_READ(dslreg); | |
4644 | udelay(500); | |
4645 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4646 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4647 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4648 | } |
4649 | } | |
4650 | ||
86adf9d7 ML |
4651 | static int |
4652 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4653 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4654 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4655 | { |
86adf9d7 ML |
4656 | struct intel_crtc_scaler_state *scaler_state = |
4657 | &crtc_state->scaler_state; | |
4658 | struct intel_crtc *intel_crtc = | |
4659 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4660 | int need_scaling; |
6156a456 | 4661 | |
bd2ef25d | 4662 | need_scaling = drm_rotation_90_or_270(rotation) ? |
6156a456 CK |
4663 | (src_h != dst_w || src_w != dst_h): |
4664 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4665 | |
4666 | /* | |
4667 | * if plane is being disabled or scaler is no more required or force detach | |
4668 | * - free scaler binded to this plane/crtc | |
4669 | * - in order to do this, update crtc->scaler_usage | |
4670 | * | |
4671 | * Here scaler state in crtc_state is set free so that | |
4672 | * scaler can be assigned to other user. Actual register | |
4673 | * update to free the scaler is done in plane/panel-fit programming. | |
4674 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4675 | */ | |
86adf9d7 | 4676 | if (force_detach || !need_scaling) { |
a1b2278e | 4677 | if (*scaler_id >= 0) { |
86adf9d7 | 4678 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4679 | scaler_state->scalers[*scaler_id].in_use = 0; |
4680 | ||
86adf9d7 ML |
4681 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4682 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4683 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4684 | scaler_state->scaler_users); |
4685 | *scaler_id = -1; | |
4686 | } | |
4687 | return 0; | |
4688 | } | |
4689 | ||
4690 | /* range checks */ | |
4691 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4692 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4693 | ||
4694 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4695 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4696 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4697 | "size is out of scaler range\n", |
86adf9d7 | 4698 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4699 | return -EINVAL; |
4700 | } | |
4701 | ||
86adf9d7 ML |
4702 | /* mark this plane as a scaler user in crtc_state */ |
4703 | scaler_state->scaler_users |= (1 << scaler_user); | |
4704 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4705 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4706 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4707 | scaler_state->scaler_users); | |
4708 | ||
4709 | return 0; | |
4710 | } | |
4711 | ||
4712 | /** | |
4713 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4714 | * | |
4715 | * @state: crtc's scaler state | |
86adf9d7 ML |
4716 | * |
4717 | * Return | |
4718 | * 0 - scaler_usage updated successfully | |
4719 | * error - requested scaling cannot be supported or other error condition | |
4720 | */ | |
e435d6e5 | 4721 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4722 | { |
7c5f93b0 | 4723 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4724 | |
e435d6e5 | 4725 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
31ad61e4 | 4726 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
86adf9d7 | 4727 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4728 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4729 | } |
4730 | ||
4731 | /** | |
4732 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4733 | * | |
4734 | * @state: crtc's scaler state | |
86adf9d7 ML |
4735 | * @plane_state: atomic plane state to update |
4736 | * | |
4737 | * Return | |
4738 | * 0 - scaler_usage updated successfully | |
4739 | * error - requested scaling cannot be supported or other error condition | |
4740 | */ | |
da20eabd ML |
4741 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4742 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4743 | { |
4744 | ||
da20eabd ML |
4745 | struct intel_plane *intel_plane = |
4746 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4747 | struct drm_framebuffer *fb = plane_state->base.fb; |
4748 | int ret; | |
4749 | ||
936e71e3 | 4750 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4751 | |
86adf9d7 ML |
4752 | ret = skl_update_scaler(crtc_state, force_detach, |
4753 | drm_plane_index(&intel_plane->base), | |
4754 | &plane_state->scaler_id, | |
4755 | plane_state->base.rotation, | |
936e71e3 VS |
4756 | drm_rect_width(&plane_state->base.src) >> 16, |
4757 | drm_rect_height(&plane_state->base.src) >> 16, | |
4758 | drm_rect_width(&plane_state->base.dst), | |
4759 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4760 | |
4761 | if (ret || plane_state->scaler_id < 0) | |
4762 | return ret; | |
4763 | ||
a1b2278e | 4764 | /* check colorkey */ |
818ed961 | 4765 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4766 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4767 | intel_plane->base.base.id, | |
4768 | intel_plane->base.name); | |
a1b2278e CK |
4769 | return -EINVAL; |
4770 | } | |
4771 | ||
4772 | /* Check src format */ | |
86adf9d7 ML |
4773 | switch (fb->pixel_format) { |
4774 | case DRM_FORMAT_RGB565: | |
4775 | case DRM_FORMAT_XBGR8888: | |
4776 | case DRM_FORMAT_XRGB8888: | |
4777 | case DRM_FORMAT_ABGR8888: | |
4778 | case DRM_FORMAT_ARGB8888: | |
4779 | case DRM_FORMAT_XRGB2101010: | |
4780 | case DRM_FORMAT_XBGR2101010: | |
4781 | case DRM_FORMAT_YUYV: | |
4782 | case DRM_FORMAT_YVYU: | |
4783 | case DRM_FORMAT_UYVY: | |
4784 | case DRM_FORMAT_VYUY: | |
4785 | break; | |
4786 | default: | |
72660ce0 VS |
4787 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4788 | intel_plane->base.base.id, intel_plane->base.name, | |
4789 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4790 | return -EINVAL; |
a1b2278e CK |
4791 | } |
4792 | ||
a1b2278e CK |
4793 | return 0; |
4794 | } | |
4795 | ||
e435d6e5 ML |
4796 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4797 | { | |
4798 | int i; | |
4799 | ||
4800 | for (i = 0; i < crtc->num_scalers; i++) | |
4801 | skl_detach_scaler(crtc, i); | |
4802 | } | |
4803 | ||
4804 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4805 | { |
4806 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4807 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4808 | int pipe = crtc->pipe; |
a1b2278e CK |
4809 | struct intel_crtc_scaler_state *scaler_state = |
4810 | &crtc->config->scaler_state; | |
4811 | ||
4812 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4813 | ||
6e3c9717 | 4814 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4815 | int id; |
4816 | ||
4817 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4818 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4819 | return; | |
4820 | } | |
4821 | ||
4822 | id = scaler_state->scaler_id; | |
4823 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4824 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4825 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4826 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4827 | ||
4828 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4829 | } |
4830 | } | |
4831 | ||
b074cec8 JB |
4832 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4833 | { | |
4834 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4835 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4836 | int pipe = crtc->pipe; |
4837 | ||
6e3c9717 | 4838 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4839 | /* Force use of hard-coded filter coefficients |
4840 | * as some pre-programmed values are broken, | |
4841 | * e.g. x201. | |
4842 | */ | |
fd6b8f43 | 4843 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4844 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4845 | PF_PIPE_SEL_IVB(pipe)); | |
4846 | else | |
4847 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4848 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4849 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4850 | } |
4851 | } | |
4852 | ||
20bc8673 | 4853 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4854 | { |
cea165c3 | 4855 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4856 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4857 | |
6e3c9717 | 4858 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4859 | return; |
4860 | ||
307e4498 ML |
4861 | /* |
4862 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4863 | * This function is called from post_plane_update, which is run after | |
4864 | * a vblank wait. | |
4865 | */ | |
cea165c3 | 4866 | |
d77e4531 | 4867 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4868 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4869 | mutex_lock(&dev_priv->rps.hw_lock); |
4870 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4871 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4872 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4873 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4874 | * mailbox." Moreover, the mailbox may return a bogus state, |
4875 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4876 | */ |
4877 | } else { | |
4878 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4879 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4880 | * is essentially intel_wait_for_vblank. If we don't have this | |
4881 | * and don't wait for vblanks until the end of crtc_enable, then | |
4882 | * the HW state readout code will complain that the expected | |
4883 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4884 | if (intel_wait_for_register(dev_priv, |
4885 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4886 | 50)) | |
2a114cc1 BW |
4887 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4888 | } | |
d77e4531 PZ |
4889 | } |
4890 | ||
20bc8673 | 4891 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4892 | { |
4893 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4894 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4895 | |
6e3c9717 | 4896 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4897 | return; |
4898 | ||
4899 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4900 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4901 | mutex_lock(&dev_priv->rps.hw_lock); |
4902 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4903 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4904 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4905 | if (intel_wait_for_register(dev_priv, |
4906 | IPS_CTL, IPS_ENABLE, 0, | |
4907 | 42)) | |
23d0b130 | 4908 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4909 | } else { |
2a114cc1 | 4910 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4911 | POSTING_READ(IPS_CTL); |
4912 | } | |
d77e4531 PZ |
4913 | |
4914 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4915 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4916 | } |
4917 | ||
7cac945f | 4918 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4919 | { |
7cac945f | 4920 | if (intel_crtc->overlay) { |
d3eedb1a | 4921 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4922 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4923 | |
4924 | mutex_lock(&dev->struct_mutex); | |
4925 | dev_priv->mm.interruptible = false; | |
4926 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4927 | dev_priv->mm.interruptible = true; | |
4928 | mutex_unlock(&dev->struct_mutex); | |
4929 | } | |
4930 | ||
4931 | /* Let userspace switch the overlay on again. In most cases userspace | |
4932 | * has to recompute where to put it anyway. | |
4933 | */ | |
4934 | } | |
4935 | ||
87d4300a ML |
4936 | /** |
4937 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4938 | * @crtc: the CRTC whose primary plane was just enabled | |
4939 | * | |
4940 | * Performs potentially sleeping operations that must be done after the primary | |
4941 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4942 | * called due to an explicit primary plane update, or due to an implicit | |
4943 | * re-enable that is caused when a sprite plane is updated to no longer | |
4944 | * completely hide the primary plane. | |
4945 | */ | |
4946 | static void | |
4947 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4948 | { |
4949 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4950 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4951 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4952 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4953 | |
87d4300a ML |
4954 | /* |
4955 | * FIXME IPS should be fine as long as one plane is | |
4956 | * enabled, but in practice it seems to have problems | |
4957 | * when going from primary only to sprite only and vice | |
4958 | * versa. | |
4959 | */ | |
a5c4d7bc VS |
4960 | hsw_enable_ips(intel_crtc); |
4961 | ||
f99d7069 | 4962 | /* |
87d4300a ML |
4963 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4964 | * So don't enable underrun reporting before at least some planes | |
4965 | * are enabled. | |
4966 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4967 | * but leave the pipe running. | |
f99d7069 | 4968 | */ |
5db94019 | 4969 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4970 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4971 | ||
aca7b684 VS |
4972 | /* Underruns don't always raise interrupts, so check manually. */ |
4973 | intel_check_cpu_fifo_underruns(dev_priv); | |
4974 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4975 | } |
4976 | ||
2622a081 | 4977 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4978 | static void |
4979 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4980 | { |
4981 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4982 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4983 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4984 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4985 | |
87d4300a ML |
4986 | /* |
4987 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4988 | * So diasble underrun reporting before all the planes get disabled. | |
4989 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4990 | * but leave the pipe running. | |
4991 | */ | |
5db94019 | 4992 | if (IS_GEN2(dev_priv)) |
87d4300a | 4993 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 4994 | |
2622a081 VS |
4995 | /* |
4996 | * FIXME IPS should be fine as long as one plane is | |
4997 | * enabled, but in practice it seems to have problems | |
4998 | * when going from primary only to sprite only and vice | |
4999 | * versa. | |
5000 | */ | |
5001 | hsw_disable_ips(intel_crtc); | |
5002 | } | |
5003 | ||
5004 | /* FIXME get rid of this and use pre_plane_update */ | |
5005 | static void | |
5006 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
5007 | { | |
5008 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5009 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
5010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5011 | int pipe = intel_crtc->pipe; | |
5012 | ||
5013 | intel_pre_disable_primary(crtc); | |
5014 | ||
87d4300a ML |
5015 | /* |
5016 | * Vblank time updates from the shadow to live plane control register | |
5017 | * are blocked if the memory self-refresh mode is active at that | |
5018 | * moment. So to make sure the plane gets truly disabled, disable | |
5019 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5020 | * will be checked/applied by the HW only at the next frame start | |
5021 | * event which is after the vblank start event, so we need to have a | |
5022 | * wait-for-vblank between disabling the plane and the pipe. | |
5023 | */ | |
11a85d6a VS |
5024 | if (HAS_GMCH_DISPLAY(dev_priv) && |
5025 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 5026 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
5027 | } |
5028 | ||
5a21b665 DV |
5029 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
5030 | { | |
5031 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
5032 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
5033 | struct intel_crtc_state *pipe_config = | |
5034 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
5035 | struct drm_plane *primary = crtc->base.primary; |
5036 | struct drm_plane_state *old_pri_state = | |
5037 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5038 | ||
5748b6a1 | 5039 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 DV |
5040 | |
5041 | crtc->wm.cxsr_allowed = true; | |
5042 | ||
5043 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
432081bc | 5044 | intel_update_watermarks(crtc); |
5a21b665 DV |
5045 | |
5046 | if (old_pri_state) { | |
5047 | struct intel_plane_state *primary_state = | |
5048 | to_intel_plane_state(primary->state); | |
5049 | struct intel_plane_state *old_primary_state = | |
5050 | to_intel_plane_state(old_pri_state); | |
5051 | ||
5052 | intel_fbc_post_update(crtc); | |
5053 | ||
936e71e3 | 5054 | if (primary_state->base.visible && |
5a21b665 | 5055 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5056 | !old_primary_state->base.visible)) |
5a21b665 DV |
5057 | intel_post_enable_primary(&crtc->base); |
5058 | } | |
5059 | } | |
5060 | ||
5c74cd73 | 5061 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 5062 | { |
5c74cd73 | 5063 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5064 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5065 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
5066 | struct intel_crtc_state *pipe_config = |
5067 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
5068 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5069 | struct drm_plane *primary = crtc->base.primary; | |
5070 | struct drm_plane_state *old_pri_state = | |
5071 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5072 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5073 | struct intel_atomic_state *old_intel_state = |
5074 | to_intel_atomic_state(old_state); | |
ac21b225 | 5075 | |
5c74cd73 ML |
5076 | if (old_pri_state) { |
5077 | struct intel_plane_state *primary_state = | |
5078 | to_intel_plane_state(primary->state); | |
5079 | struct intel_plane_state *old_primary_state = | |
5080 | to_intel_plane_state(old_pri_state); | |
5081 | ||
faf68d92 | 5082 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5083 | |
936e71e3 VS |
5084 | if (old_primary_state->base.visible && |
5085 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5086 | intel_pre_disable_primary(&crtc->base); |
5087 | } | |
852eb00d | 5088 | |
49cff963 | 5089 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) { |
852eb00d | 5090 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 5091 | |
2622a081 VS |
5092 | /* |
5093 | * Vblank time updates from the shadow to live plane control register | |
5094 | * are blocked if the memory self-refresh mode is active at that | |
5095 | * moment. So to make sure the plane gets truly disabled, disable | |
5096 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5097 | * will be checked/applied by the HW only at the next frame start | |
5098 | * event which is after the vblank start event, so we need to have a | |
5099 | * wait-for-vblank between disabling the plane and the pipe. | |
5100 | */ | |
11a85d6a VS |
5101 | if (old_crtc_state->base.active && |
5102 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 5103 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
852eb00d | 5104 | } |
92826fcd | 5105 | |
ed4a6a7c MR |
5106 | /* |
5107 | * IVB workaround: must disable low power watermarks for at least | |
5108 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5109 | * when scaling is disabled. | |
5110 | * | |
5111 | * WaCxSRDisabledForSpriteScaling:ivb | |
5112 | */ | |
ddd2b792 | 5113 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5114 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5115 | |
5116 | /* | |
5117 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5118 | * watermark programming here. | |
5119 | */ | |
5120 | if (needs_modeset(&pipe_config->base)) | |
5121 | return; | |
5122 | ||
5123 | /* | |
5124 | * For platforms that support atomic watermarks, program the | |
5125 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5126 | * will be the intermediate values that are safe for both pre- and | |
5127 | * post- vblank; when vblank happens, the 'active' values will be set | |
5128 | * to the final 'target' values and we'll do this again to get the | |
5129 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5130 | * will be the final target values which will get automatically latched | |
5131 | * at vblank time; no further programming will be necessary. | |
5132 | * | |
5133 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5134 | * we'll continue to update watermarks the old way, if flags tell | |
5135 | * us to. | |
5136 | */ | |
5137 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5138 | dev_priv->display.initial_watermarks(old_intel_state, |
5139 | pipe_config); | |
caed361d | 5140 | else if (pipe_config->update_wm_pre) |
432081bc | 5141 | intel_update_watermarks(crtc); |
ac21b225 ML |
5142 | } |
5143 | ||
d032ffa0 | 5144 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5145 | { |
5146 | struct drm_device *dev = crtc->dev; | |
5147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5148 | struct drm_plane *p; |
87d4300a ML |
5149 | int pipe = intel_crtc->pipe; |
5150 | ||
7cac945f | 5151 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5152 | |
d032ffa0 ML |
5153 | drm_for_each_plane_mask(p, dev, plane_mask) |
5154 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5155 | |
f99d7069 DV |
5156 | /* |
5157 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5158 | * to compute the mask of flip planes precisely. For the time being | |
5159 | * consider this a flip to a NULL plane. | |
5160 | */ | |
5748b6a1 | 5161 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5162 | } |
5163 | ||
fb1c98b1 | 5164 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5165 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5166 | struct drm_atomic_state *old_state) |
5167 | { | |
5168 | struct drm_connector_state *old_conn_state; | |
5169 | struct drm_connector *conn; | |
5170 | int i; | |
5171 | ||
5172 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5173 | struct drm_connector_state *conn_state = conn->state; | |
5174 | struct intel_encoder *encoder = | |
5175 | to_intel_encoder(conn_state->best_encoder); | |
5176 | ||
5177 | if (conn_state->crtc != crtc) | |
5178 | continue; | |
5179 | ||
5180 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5181 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5182 | } |
5183 | } | |
5184 | ||
5185 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5186 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5187 | struct drm_atomic_state *old_state) |
5188 | { | |
5189 | struct drm_connector_state *old_conn_state; | |
5190 | struct drm_connector *conn; | |
5191 | int i; | |
5192 | ||
5193 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5194 | struct drm_connector_state *conn_state = conn->state; | |
5195 | struct intel_encoder *encoder = | |
5196 | to_intel_encoder(conn_state->best_encoder); | |
5197 | ||
5198 | if (conn_state->crtc != crtc) | |
5199 | continue; | |
5200 | ||
5201 | if (encoder->pre_enable) | |
fd6bbda9 | 5202 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5203 | } |
5204 | } | |
5205 | ||
5206 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5207 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5208 | struct drm_atomic_state *old_state) |
5209 | { | |
5210 | struct drm_connector_state *old_conn_state; | |
5211 | struct drm_connector *conn; | |
5212 | int i; | |
5213 | ||
5214 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5215 | struct drm_connector_state *conn_state = conn->state; | |
5216 | struct intel_encoder *encoder = | |
5217 | to_intel_encoder(conn_state->best_encoder); | |
5218 | ||
5219 | if (conn_state->crtc != crtc) | |
5220 | continue; | |
5221 | ||
fd6bbda9 | 5222 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5223 | intel_opregion_notify_encoder(encoder, true); |
5224 | } | |
5225 | } | |
5226 | ||
5227 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5228 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5229 | struct drm_atomic_state *old_state) |
5230 | { | |
5231 | struct drm_connector_state *old_conn_state; | |
5232 | struct drm_connector *conn; | |
5233 | int i; | |
5234 | ||
5235 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5236 | struct intel_encoder *encoder = | |
5237 | to_intel_encoder(old_conn_state->best_encoder); | |
5238 | ||
5239 | if (old_conn_state->crtc != crtc) | |
5240 | continue; | |
5241 | ||
5242 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5243 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5244 | } |
5245 | } | |
5246 | ||
5247 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5248 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5249 | struct drm_atomic_state *old_state) |
5250 | { | |
5251 | struct drm_connector_state *old_conn_state; | |
5252 | struct drm_connector *conn; | |
5253 | int i; | |
5254 | ||
5255 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5256 | struct intel_encoder *encoder = | |
5257 | to_intel_encoder(old_conn_state->best_encoder); | |
5258 | ||
5259 | if (old_conn_state->crtc != crtc) | |
5260 | continue; | |
5261 | ||
5262 | if (encoder->post_disable) | |
fd6bbda9 | 5263 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5264 | } |
5265 | } | |
5266 | ||
5267 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5268 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5269 | struct drm_atomic_state *old_state) |
5270 | { | |
5271 | struct drm_connector_state *old_conn_state; | |
5272 | struct drm_connector *conn; | |
5273 | int i; | |
5274 | ||
5275 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5276 | struct intel_encoder *encoder = | |
5277 | to_intel_encoder(old_conn_state->best_encoder); | |
5278 | ||
5279 | if (old_conn_state->crtc != crtc) | |
5280 | continue; | |
5281 | ||
5282 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5283 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5284 | } |
5285 | } | |
5286 | ||
4a806558 ML |
5287 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5288 | struct drm_atomic_state *old_state) | |
f67a559d | 5289 | { |
4a806558 | 5290 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5291 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5292 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5293 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5294 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5295 | struct intel_atomic_state *old_intel_state = |
5296 | to_intel_atomic_state(old_state); | |
f67a559d | 5297 | |
53d9f4e9 | 5298 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5299 | return; |
5300 | ||
b2c0593a VS |
5301 | /* |
5302 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5303 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5304 | * | |
5305 | * On ILK we get an occasional spurious CPU pipe underruns | |
5306 | * between eDP port A enable and vdd enable. Also PCH port | |
5307 | * enable seems to result in the occasional CPU pipe underrun. | |
5308 | * | |
5309 | * Spurious PCH underruns also occur during PCH enabling. | |
5310 | */ | |
5311 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5312 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5313 | if (intel_crtc->config->has_pch_encoder) |
5314 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5315 | ||
6e3c9717 | 5316 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5317 | intel_prepare_shared_dpll(intel_crtc); |
5318 | ||
37a5650b | 5319 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5320 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5321 | |
5322 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5323 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5324 | |
6e3c9717 | 5325 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5326 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5327 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5328 | } |
5329 | ||
5330 | ironlake_set_pipeconf(crtc); | |
5331 | ||
f67a559d | 5332 | intel_crtc->active = true; |
8664281b | 5333 | |
fd6bbda9 | 5334 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5335 | |
6e3c9717 | 5336 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5337 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5338 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5339 | * enabling. */ | |
88cefb6c | 5340 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5341 | } else { |
5342 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5343 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5344 | } | |
f67a559d | 5345 | |
b074cec8 | 5346 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5347 | |
9c54c0dd JB |
5348 | /* |
5349 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5350 | * clocks enabled | |
5351 | */ | |
b95c5321 | 5352 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5353 | |
1d5bf5d9 | 5354 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5355 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5356 | intel_enable_pipe(intel_crtc); |
f67a559d | 5357 | |
6e3c9717 | 5358 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 5359 | ironlake_pch_enable(crtc); |
c98e9dcf | 5360 | |
f9b61ff6 DV |
5361 | assert_vblank_disabled(crtc); |
5362 | drm_crtc_vblank_on(crtc); | |
5363 | ||
fd6bbda9 | 5364 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5365 | |
6e266956 | 5366 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5367 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5368 | |
5369 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5370 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5371 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5372 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5373 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5374 | } |
5375 | ||
42db64ef PZ |
5376 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5377 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5378 | { | |
50a0bc90 | 5379 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5380 | } |
5381 | ||
4a806558 ML |
5382 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5383 | struct drm_atomic_state *old_state) | |
4f771f10 | 5384 | { |
4a806558 | 5385 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5386 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5387 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5388 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5389 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5390 | struct intel_atomic_state *old_intel_state = |
5391 | to_intel_atomic_state(old_state); | |
4f771f10 | 5392 | |
53d9f4e9 | 5393 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5394 | return; |
5395 | ||
81b088ca VS |
5396 | if (intel_crtc->config->has_pch_encoder) |
5397 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5398 | false); | |
5399 | ||
fd6bbda9 | 5400 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5401 | |
8106ddbd | 5402 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5403 | intel_enable_shared_dpll(intel_crtc); |
5404 | ||
37a5650b | 5405 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5406 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5407 | |
d7edc4e5 | 5408 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5409 | intel_set_pipe_timings(intel_crtc); |
5410 | ||
bc58be60 | 5411 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5412 | |
4d1de975 JN |
5413 | if (cpu_transcoder != TRANSCODER_EDP && |
5414 | !transcoder_is_dsi(cpu_transcoder)) { | |
5415 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5416 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5417 | } |
5418 | ||
6e3c9717 | 5419 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5420 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5421 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5422 | } |
5423 | ||
d7edc4e5 | 5424 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5425 | haswell_set_pipeconf(crtc); |
5426 | ||
391bf048 | 5427 | haswell_set_pipemisc(crtc); |
229fca97 | 5428 | |
b95c5321 | 5429 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5430 | |
4f771f10 | 5431 | intel_crtc->active = true; |
8664281b | 5432 | |
6b698516 DV |
5433 | if (intel_crtc->config->has_pch_encoder) |
5434 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5435 | else | |
5436 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5437 | ||
fd6bbda9 | 5438 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5439 | |
d2d65408 | 5440 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5441 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5442 | |
d7edc4e5 | 5443 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5444 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5445 | |
6315b5d3 | 5446 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5447 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5448 | else |
1c132b44 | 5449 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5450 | |
5451 | /* | |
5452 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5453 | * clocks enabled | |
5454 | */ | |
b95c5321 | 5455 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5456 | |
1f544388 | 5457 | intel_ddi_set_pipe_settings(crtc); |
d7edc4e5 | 5458 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5459 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5460 | |
1d5bf5d9 | 5461 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5462 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5463 | |
5464 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5465 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5466 | intel_enable_pipe(intel_crtc); |
42db64ef | 5467 | |
6e3c9717 | 5468 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5469 | lpt_pch_enable(crtc); |
4f771f10 | 5470 | |
0037071d | 5471 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
0e32b39c DA |
5472 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5473 | ||
f9b61ff6 DV |
5474 | assert_vblank_disabled(crtc); |
5475 | drm_crtc_vblank_on(crtc); | |
5476 | ||
fd6bbda9 | 5477 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5478 | |
6b698516 | 5479 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5480 | intel_wait_for_vblank(dev_priv, pipe); |
5481 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5482 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
d2d65408 VS |
5483 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5484 | true); | |
6b698516 | 5485 | } |
d2d65408 | 5486 | |
e4916946 PZ |
5487 | /* If we change the relative order between pipe/planes enabling, we need |
5488 | * to change the workaround. */ | |
99d736a2 | 5489 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5490 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5491 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5492 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5493 | } |
4f771f10 PZ |
5494 | } |
5495 | ||
bfd16b2a | 5496 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5497 | { |
5498 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5499 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5500 | int pipe = crtc->pipe; |
5501 | ||
5502 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5503 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5504 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5505 | I915_WRITE(PF_CTL(pipe), 0); |
5506 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5507 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5508 | } | |
5509 | } | |
5510 | ||
4a806558 ML |
5511 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5512 | struct drm_atomic_state *old_state) | |
6be4a607 | 5513 | { |
4a806558 | 5514 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5515 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5516 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5517 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5518 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5519 | |
b2c0593a VS |
5520 | /* |
5521 | * Sometimes spurious CPU pipe underruns happen when the | |
5522 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5523 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5524 | */ | |
5525 | if (intel_crtc->config->has_pch_encoder) { | |
5526 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5527 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5528 | } |
37ca8d4c | 5529 | |
fd6bbda9 | 5530 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5531 | |
f9b61ff6 DV |
5532 | drm_crtc_vblank_off(crtc); |
5533 | assert_vblank_disabled(crtc); | |
5534 | ||
575f7ab7 | 5535 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5536 | |
bfd16b2a | 5537 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5538 | |
b2c0593a | 5539 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5540 | ironlake_fdi_disable(crtc); |
5541 | ||
fd6bbda9 | 5542 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5543 | |
6e3c9717 | 5544 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5545 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5546 | |
6e266956 | 5547 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5548 | i915_reg_t reg; |
5549 | u32 temp; | |
5550 | ||
d925c59a DV |
5551 | /* disable TRANS_DP_CTL */ |
5552 | reg = TRANS_DP_CTL(pipe); | |
5553 | temp = I915_READ(reg); | |
5554 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5555 | TRANS_DP_PORT_SEL_MASK); | |
5556 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5557 | I915_WRITE(reg, temp); | |
5558 | ||
5559 | /* disable DPLL_SEL */ | |
5560 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5561 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5562 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5563 | } |
e3421a18 | 5564 | |
d925c59a DV |
5565 | ironlake_fdi_pll_disable(intel_crtc); |
5566 | } | |
81b088ca | 5567 | |
b2c0593a | 5568 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5569 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5570 | } |
1b3c7a47 | 5571 | |
4a806558 ML |
5572 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5573 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5574 | { |
4a806558 | 5575 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5576 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5577 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5578 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5579 | |
d2d65408 VS |
5580 | if (intel_crtc->config->has_pch_encoder) |
5581 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5582 | false); | |
5583 | ||
fd6bbda9 | 5584 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5585 | |
f9b61ff6 DV |
5586 | drm_crtc_vblank_off(crtc); |
5587 | assert_vblank_disabled(crtc); | |
5588 | ||
4d1de975 | 5589 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5590 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5591 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5592 | |
0037071d | 5593 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
a4bf214f VS |
5594 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5595 | ||
d7edc4e5 | 5596 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5597 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5598 | |
6315b5d3 | 5599 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5600 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5601 | else |
bfd16b2a | 5602 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5603 | |
d7edc4e5 | 5604 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5605 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5606 | |
fd6bbda9 | 5607 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5608 | |
b7076546 | 5609 | if (old_crtc_state->has_pch_encoder) |
81b088ca VS |
5610 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5611 | true); | |
4f771f10 PZ |
5612 | } |
5613 | ||
2dd24552 JB |
5614 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5615 | { | |
5616 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5617 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5618 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5619 | |
681a8504 | 5620 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5621 | return; |
5622 | ||
2dd24552 | 5623 | /* |
c0b03411 DV |
5624 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5625 | * according to register description and PRM. | |
2dd24552 | 5626 | */ |
c0b03411 DV |
5627 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5628 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5629 | |
b074cec8 JB |
5630 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5631 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5632 | |
5633 | /* Border color in case we don't scale up to the full screen. Black by | |
5634 | * default, change to something else for debugging. */ | |
5635 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5636 | } |
5637 | ||
d05410f9 DA |
5638 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5639 | { | |
5640 | switch (port) { | |
5641 | case PORT_A: | |
6331a704 | 5642 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5643 | case PORT_B: |
6331a704 | 5644 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5645 | case PORT_C: |
6331a704 | 5646 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5647 | case PORT_D: |
6331a704 | 5648 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5649 | case PORT_E: |
6331a704 | 5650 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5651 | default: |
b9fec167 | 5652 | MISSING_CASE(port); |
d05410f9 DA |
5653 | return POWER_DOMAIN_PORT_OTHER; |
5654 | } | |
5655 | } | |
5656 | ||
25f78f58 VS |
5657 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5658 | { | |
5659 | switch (port) { | |
5660 | case PORT_A: | |
5661 | return POWER_DOMAIN_AUX_A; | |
5662 | case PORT_B: | |
5663 | return POWER_DOMAIN_AUX_B; | |
5664 | case PORT_C: | |
5665 | return POWER_DOMAIN_AUX_C; | |
5666 | case PORT_D: | |
5667 | return POWER_DOMAIN_AUX_D; | |
5668 | case PORT_E: | |
5669 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5670 | return POWER_DOMAIN_AUX_D; | |
5671 | default: | |
b9fec167 | 5672 | MISSING_CASE(port); |
25f78f58 VS |
5673 | return POWER_DOMAIN_AUX_A; |
5674 | } | |
5675 | } | |
5676 | ||
319be8ae ID |
5677 | enum intel_display_power_domain |
5678 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5679 | { | |
4f8036a2 | 5680 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
319be8ae ID |
5681 | struct intel_digital_port *intel_dig_port; |
5682 | ||
5683 | switch (intel_encoder->type) { | |
5684 | case INTEL_OUTPUT_UNKNOWN: | |
5685 | /* Only DDI platforms should ever use this output type */ | |
4f8036a2 | 5686 | WARN_ON_ONCE(!HAS_DDI(dev_priv)); |
cca0502b | 5687 | case INTEL_OUTPUT_DP: |
319be8ae ID |
5688 | case INTEL_OUTPUT_HDMI: |
5689 | case INTEL_OUTPUT_EDP: | |
5690 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5691 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5692 | case INTEL_OUTPUT_DP_MST: |
5693 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5694 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5695 | case INTEL_OUTPUT_ANALOG: |
5696 | return POWER_DOMAIN_PORT_CRT; | |
5697 | case INTEL_OUTPUT_DSI: | |
5698 | return POWER_DOMAIN_PORT_DSI; | |
5699 | default: | |
5700 | return POWER_DOMAIN_PORT_OTHER; | |
5701 | } | |
5702 | } | |
5703 | ||
25f78f58 VS |
5704 | enum intel_display_power_domain |
5705 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5706 | { | |
4f8036a2 | 5707 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
25f78f58 VS |
5708 | struct intel_digital_port *intel_dig_port; |
5709 | ||
5710 | switch (intel_encoder->type) { | |
5711 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5712 | case INTEL_OUTPUT_HDMI: |
5713 | /* | |
5714 | * Only DDI platforms should ever use these output types. | |
5715 | * We can get here after the HDMI detect code has already set | |
5716 | * the type of the shared encoder. Since we can't be sure | |
5717 | * what's the status of the given connectors, play safe and | |
5718 | * run the DP detection too. | |
5719 | */ | |
4f8036a2 | 5720 | WARN_ON_ONCE(!HAS_DDI(dev_priv)); |
cca0502b | 5721 | case INTEL_OUTPUT_DP: |
25f78f58 VS |
5722 | case INTEL_OUTPUT_EDP: |
5723 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5724 | return port_to_aux_power_domain(intel_dig_port->port); | |
5725 | case INTEL_OUTPUT_DP_MST: | |
5726 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5727 | return port_to_aux_power_domain(intel_dig_port->port); | |
5728 | default: | |
b9fec167 | 5729 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5730 | return POWER_DOMAIN_AUX_A; |
5731 | } | |
5732 | } | |
5733 | ||
74bff5f9 ML |
5734 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5735 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5736 | { |
319be8ae | 5737 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5738 | struct drm_encoder *encoder; |
319be8ae ID |
5739 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5740 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5741 | unsigned long mask; |
74bff5f9 | 5742 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5743 | |
74bff5f9 | 5744 | if (!crtc_state->base.active) |
292b990e ML |
5745 | return 0; |
5746 | ||
77d22dca ID |
5747 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5748 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5749 | if (crtc_state->pch_pfit.enabled || |
5750 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5751 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5752 | ||
74bff5f9 ML |
5753 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5754 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5755 | ||
319be8ae | 5756 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5757 | } |
319be8ae | 5758 | |
15e7ec29 ML |
5759 | if (crtc_state->shared_dpll) |
5760 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5761 | ||
77d22dca ID |
5762 | return mask; |
5763 | } | |
5764 | ||
74bff5f9 ML |
5765 | static unsigned long |
5766 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5767 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5768 | { |
fac5e23e | 5769 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5770 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5771 | enum intel_display_power_domain domain; | |
5a21b665 | 5772 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5773 | |
292b990e | 5774 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5775 | intel_crtc->enabled_power_domains = new_domains = |
5776 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5777 | |
5a21b665 | 5778 | domains = new_domains & ~old_domains; |
292b990e ML |
5779 | |
5780 | for_each_power_domain(domain, domains) | |
5781 | intel_display_power_get(dev_priv, domain); | |
5782 | ||
5a21b665 | 5783 | return old_domains & ~new_domains; |
292b990e ML |
5784 | } |
5785 | ||
5786 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5787 | unsigned long domains) | |
5788 | { | |
5789 | enum intel_display_power_domain domain; | |
5790 | ||
5791 | for_each_power_domain(domain, domains) | |
5792 | intel_display_power_put(dev_priv, domain); | |
5793 | } | |
77d22dca | 5794 | |
adafdc6f MK |
5795 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5796 | { | |
5797 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5798 | ||
09d09386 ACO |
5799 | if (IS_GEMINILAKE(dev_priv)) |
5800 | return 2 * max_cdclk_freq; | |
5801 | else if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5802 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
adafdc6f MK |
5803 | return max_cdclk_freq; |
5804 | else if (IS_CHERRYVIEW(dev_priv)) | |
5805 | return max_cdclk_freq*95/100; | |
5806 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5807 | return 2*max_cdclk_freq*90/100; | |
5808 | else | |
5809 | return max_cdclk_freq*90/100; | |
5810 | } | |
5811 | ||
b2045352 VS |
5812 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5813 | ||
4c75b940 | 5814 | static void intel_update_max_cdclk(struct drm_i915_private *dev_priv) |
560a7ae4 | 5815 | { |
0853723b | 5816 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
560a7ae4 | 5817 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5818 | int max_cdclk, vco; |
5819 | ||
5820 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5821 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5822 | |
b2045352 VS |
5823 | /* |
5824 | * Use the lower (vco 8640) cdclk values as a | |
5825 | * first guess. skl_calc_cdclk() will correct it | |
5826 | * if the preferred vco is 8100 instead. | |
5827 | */ | |
560a7ae4 | 5828 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5829 | max_cdclk = 617143; |
560a7ae4 | 5830 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5831 | max_cdclk = 540000; |
560a7ae4 | 5832 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5833 | max_cdclk = 432000; |
560a7ae4 | 5834 | else |
487ed2e4 | 5835 | max_cdclk = 308571; |
b2045352 VS |
5836 | |
5837 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
89b3c3c7 ACO |
5838 | } else if (IS_GEMINILAKE(dev_priv)) { |
5839 | dev_priv->max_cdclk_freq = 316800; | |
e2d214ae | 5840 | } else if (IS_BROXTON(dev_priv)) { |
281c114f | 5841 | dev_priv->max_cdclk_freq = 624000; |
8652744b | 5842 | } else if (IS_BROADWELL(dev_priv)) { |
560a7ae4 DL |
5843 | /* |
5844 | * FIXME with extra cooling we can allow | |
5845 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5846 | * How can we know if extra cooling is | |
5847 | * available? PCI ID, VTB, something else? | |
5848 | */ | |
5849 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5850 | dev_priv->max_cdclk_freq = 450000; | |
50a0bc90 | 5851 | else if (IS_BDW_ULX(dev_priv)) |
560a7ae4 | 5852 | dev_priv->max_cdclk_freq = 450000; |
50a0bc90 | 5853 | else if (IS_BDW_ULT(dev_priv)) |
560a7ae4 DL |
5854 | dev_priv->max_cdclk_freq = 540000; |
5855 | else | |
5856 | dev_priv->max_cdclk_freq = 675000; | |
920a14b2 | 5857 | } else if (IS_CHERRYVIEW(dev_priv)) { |
0904deaf | 5858 | dev_priv->max_cdclk_freq = 320000; |
11a914c2 | 5859 | } else if (IS_VALLEYVIEW(dev_priv)) { |
560a7ae4 DL |
5860 | dev_priv->max_cdclk_freq = 400000; |
5861 | } else { | |
5862 | /* otherwise assume cdclk is fixed */ | |
5863 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5864 | } | |
5865 | ||
adafdc6f MK |
5866 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5867 | ||
560a7ae4 DL |
5868 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5869 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5870 | |
5871 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5872 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5873 | } |
5874 | ||
4c75b940 | 5875 | static void intel_update_cdclk(struct drm_i915_private *dev_priv) |
560a7ae4 | 5876 | { |
1353c4fb | 5877 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv); |
2f2a121a | 5878 | |
83d7c81f | 5879 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5880 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5881 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5882 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5883 | else |
5884 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5885 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5886 | |
5887 | /* | |
b5d99ff9 VS |
5888 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5889 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5890 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5891 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5892 | */ |
b5d99ff9 | 5893 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5894 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5895 | } |
5896 | ||
92891e45 VS |
5897 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5898 | static int skl_cdclk_decimal(int cdclk) | |
5899 | { | |
5900 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5901 | } | |
5902 | ||
5f199dfa VS |
5903 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5904 | { | |
5905 | int ratio; | |
5906 | ||
5907 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5908 | return 0; | |
5909 | ||
5910 | switch (cdclk) { | |
5911 | default: | |
5912 | MISSING_CASE(cdclk); | |
5913 | case 144000: | |
5914 | case 288000: | |
5915 | case 384000: | |
5916 | case 576000: | |
5917 | ratio = 60; | |
5918 | break; | |
5919 | case 624000: | |
5920 | ratio = 65; | |
5921 | break; | |
5922 | } | |
5923 | ||
5924 | return dev_priv->cdclk_pll.ref * ratio; | |
5925 | } | |
5926 | ||
89b3c3c7 ACO |
5927 | static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5928 | { | |
5929 | int ratio; | |
5930 | ||
5931 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5932 | return 0; | |
5933 | ||
5934 | switch (cdclk) { | |
5935 | default: | |
5936 | MISSING_CASE(cdclk); | |
5937 | case 79200: | |
5938 | case 158400: | |
5939 | case 316800: | |
5940 | ratio = 33; | |
5941 | break; | |
5942 | } | |
5943 | ||
5944 | return dev_priv->cdclk_pll.ref * ratio; | |
5945 | } | |
5946 | ||
2b73001e VS |
5947 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5948 | { | |
5949 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5950 | ||
5951 | /* Timeout 200us */ | |
95cac283 CW |
5952 | if (intel_wait_for_register(dev_priv, |
5953 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
5954 | 1)) | |
2b73001e | 5955 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
83d7c81f VS |
5956 | |
5957 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5958 | } |
5959 | ||
5f199dfa | 5960 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5961 | { |
5f199dfa | 5962 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5963 | u32 val; |
5964 | ||
5965 | val = I915_READ(BXT_DE_PLL_CTL); | |
5966 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5967 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5968 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5969 | ||
5970 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5971 | ||
5972 | /* Timeout 200us */ | |
e084e1b9 CW |
5973 | if (intel_wait_for_register(dev_priv, |
5974 | BXT_DE_PLL_ENABLE, | |
5975 | BXT_DE_PLL_LOCK, | |
5976 | BXT_DE_PLL_LOCK, | |
5977 | 1)) | |
2b73001e | 5978 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
83d7c81f | 5979 | |
5f199dfa | 5980 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5981 | } |
5982 | ||
324513c0 | 5983 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5984 | { |
5f199dfa VS |
5985 | u32 val, divider; |
5986 | int vco, ret; | |
f8437dd1 | 5987 | |
89b3c3c7 ACO |
5988 | if (IS_GEMINILAKE(dev_priv)) |
5989 | vco = glk_de_pll_vco(dev_priv, cdclk); | |
5990 | else | |
5991 | vco = bxt_de_pll_vco(dev_priv, cdclk); | |
5f199dfa VS |
5992 | |
5993 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5994 | ||
5995 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5996 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5997 | case 8: | |
f8437dd1 | 5998 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5999 | break; |
5f199dfa | 6000 | case 4: |
f8437dd1 | 6001 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 6002 | break; |
5f199dfa | 6003 | case 3: |
89b3c3c7 | 6004 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); |
f8437dd1 | 6005 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 6006 | break; |
5f199dfa | 6007 | case 2: |
f8437dd1 | 6008 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
6009 | break; |
6010 | default: | |
5f199dfa VS |
6011 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
6012 | WARN_ON(vco != 0); | |
f8437dd1 | 6013 | |
5f199dfa VS |
6014 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
6015 | break; | |
f8437dd1 VK |
6016 | } |
6017 | ||
f8437dd1 | 6018 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 6019 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
6020 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
6021 | 0x80000000); | |
6022 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6023 | ||
6024 | if (ret) { | |
6025 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 6026 | ret, cdclk); |
f8437dd1 VK |
6027 | return; |
6028 | } | |
6029 | ||
5f199dfa VS |
6030 | if (dev_priv->cdclk_pll.vco != 0 && |
6031 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 6032 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 6033 | |
5f199dfa VS |
6034 | if (dev_priv->cdclk_pll.vco != vco) |
6035 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 6036 | |
5f199dfa VS |
6037 | val = divider | skl_cdclk_decimal(cdclk); |
6038 | /* | |
6039 | * FIXME if only the cd2x divider needs changing, it could be done | |
6040 | * without shutting off the pipe (if only one pipe is active). | |
6041 | */ | |
6042 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
6043 | /* | |
6044 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
6045 | * enable otherwise. | |
6046 | */ | |
6047 | if (cdclk >= 500000) | |
6048 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
6049 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
6050 | |
6051 | mutex_lock(&dev_priv->rps.hw_lock); | |
6052 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 6053 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
6054 | mutex_unlock(&dev_priv->rps.hw_lock); |
6055 | ||
6056 | if (ret) { | |
6057 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 6058 | ret, cdclk); |
f8437dd1 VK |
6059 | return; |
6060 | } | |
6061 | ||
4c75b940 | 6062 | intel_update_cdclk(dev_priv); |
f8437dd1 VK |
6063 | } |
6064 | ||
d66a2194 | 6065 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 6066 | { |
d66a2194 ID |
6067 | u32 cdctl, expected; |
6068 | ||
4c75b940 | 6069 | intel_update_cdclk(dev_priv); |
f8437dd1 | 6070 | |
d66a2194 ID |
6071 | if (dev_priv->cdclk_pll.vco == 0 || |
6072 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
6073 | goto sanitize; | |
6074 | ||
6075 | /* DPLL okay; verify the cdclock | |
6076 | * | |
6077 | * Some BIOS versions leave an incorrect decimal frequency value and | |
6078 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
6079 | * so sanitize this register. | |
6080 | */ | |
6081 | cdctl = I915_READ(CDCLK_CTL); | |
6082 | /* | |
6083 | * Let's ignore the pipe field, since BIOS could have configured the | |
6084 | * dividers both synching to an active pipe, or asynchronously | |
6085 | * (PIPE_NONE). | |
6086 | */ | |
6087 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
6088 | ||
6089 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
6090 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6091 | /* | |
6092 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
6093 | * enable otherwise. | |
6094 | */ | |
6095 | if (dev_priv->cdclk_freq >= 500000) | |
6096 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
6097 | ||
6098 | if (cdctl == expected) | |
6099 | /* All well; nothing to sanitize */ | |
6100 | return; | |
6101 | ||
6102 | sanitize: | |
6103 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
6104 | ||
6105 | /* force cdclk programming */ | |
6106 | dev_priv->cdclk_freq = 0; | |
6107 | ||
6108 | /* force full PLL disable + enable */ | |
6109 | dev_priv->cdclk_pll.vco = -1; | |
6110 | } | |
6111 | ||
324513c0 | 6112 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 | 6113 | { |
89b3c3c7 ACO |
6114 | int cdclk; |
6115 | ||
d66a2194 ID |
6116 | bxt_sanitize_cdclk(dev_priv); |
6117 | ||
6118 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 6119 | return; |
c2e001ef | 6120 | |
f8437dd1 VK |
6121 | /* |
6122 | * FIXME: | |
6123 | * - The initial CDCLK needs to be read from VBT. | |
6124 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 6125 | */ |
89b3c3c7 ACO |
6126 | if (IS_GEMINILAKE(dev_priv)) |
6127 | cdclk = glk_calc_cdclk(0); | |
6128 | else | |
6129 | cdclk = bxt_calc_cdclk(0); | |
6130 | ||
6131 | bxt_set_cdclk(dev_priv, cdclk); | |
f8437dd1 VK |
6132 | } |
6133 | ||
324513c0 | 6134 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 6135 | { |
324513c0 | 6136 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
6137 | } |
6138 | ||
a8ca4934 VS |
6139 | static int skl_calc_cdclk(int max_pixclk, int vco) |
6140 | { | |
63911d72 | 6141 | if (vco == 8640000) { |
a8ca4934 | 6142 | if (max_pixclk > 540000) |
487ed2e4 | 6143 | return 617143; |
a8ca4934 VS |
6144 | else if (max_pixclk > 432000) |
6145 | return 540000; | |
487ed2e4 | 6146 | else if (max_pixclk > 308571) |
a8ca4934 VS |
6147 | return 432000; |
6148 | else | |
487ed2e4 | 6149 | return 308571; |
a8ca4934 | 6150 | } else { |
a8ca4934 VS |
6151 | if (max_pixclk > 540000) |
6152 | return 675000; | |
6153 | else if (max_pixclk > 450000) | |
6154 | return 540000; | |
6155 | else if (max_pixclk > 337500) | |
6156 | return 450000; | |
6157 | else | |
6158 | return 337500; | |
6159 | } | |
6160 | } | |
6161 | ||
ea61791e VS |
6162 | static void |
6163 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 6164 | { |
ea61791e | 6165 | u32 val; |
5d96d8af | 6166 | |
709e05c3 | 6167 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 6168 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 6169 | |
ea61791e | 6170 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 6171 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 6172 | return; |
5d96d8af | 6173 | |
1c3f7700 ID |
6174 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
6175 | return; | |
9f7eb31a | 6176 | |
ea61791e VS |
6177 | val = I915_READ(DPLL_CTRL1); |
6178 | ||
1c3f7700 ID |
6179 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
6180 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6181 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
6182 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
6183 | return; | |
9f7eb31a | 6184 | |
ea61791e VS |
6185 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
6186 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
6187 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
6188 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
6189 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 6190 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
6191 | break; |
6192 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
6193 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 6194 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
6195 | break; |
6196 | default: | |
6197 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
6198 | break; |
6199 | } | |
5d96d8af DL |
6200 | } |
6201 | ||
b2045352 VS |
6202 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
6203 | { | |
6204 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
6205 | ||
6206 | dev_priv->skl_preferred_vco_freq = vco; | |
6207 | ||
6208 | if (changed) | |
4c75b940 | 6209 | intel_update_max_cdclk(dev_priv); |
b2045352 VS |
6210 | } |
6211 | ||
5d96d8af | 6212 | static void |
3861fc60 | 6213 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 6214 | { |
a8ca4934 | 6215 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
6216 | u32 val; |
6217 | ||
63911d72 | 6218 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 6219 | |
5d96d8af | 6220 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 6221 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
6222 | I915_WRITE(CDCLK_CTL, val); |
6223 | POSTING_READ(CDCLK_CTL); | |
6224 | ||
6225 | /* | |
6226 | * We always enable DPLL0 with the lowest link rate possible, but still | |
6227 | * taking into account the VCO required to operate the eDP panel at the | |
6228 | * desired frequency. The usual DP link rates operate with a VCO of | |
6229 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
6230 | * The modeset code is responsible for the selection of the exact link | |
6231 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 6232 | * works with vco. |
5d96d8af DL |
6233 | */ |
6234 | val = I915_READ(DPLL_CTRL1); | |
6235 | ||
6236 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6237 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
6238 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 6239 | if (vco == 8640000) |
5d96d8af DL |
6240 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
6241 | SKL_DPLL0); | |
6242 | else | |
6243 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
6244 | SKL_DPLL0); | |
6245 | ||
6246 | I915_WRITE(DPLL_CTRL1, val); | |
6247 | POSTING_READ(DPLL_CTRL1); | |
6248 | ||
6249 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
6250 | ||
e24ca054 CW |
6251 | if (intel_wait_for_register(dev_priv, |
6252 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
6253 | 5)) | |
5d96d8af | 6254 | DRM_ERROR("DPLL0 not locked\n"); |
1cd593e0 | 6255 | |
63911d72 | 6256 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
6257 | |
6258 | /* We'll want to keep using the current vco from now on. */ | |
6259 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
6260 | } |
6261 | ||
430e05de VS |
6262 | static void |
6263 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
6264 | { | |
6265 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
8ad32a05 CW |
6266 | if (intel_wait_for_register(dev_priv, |
6267 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
6268 | 1)) | |
430e05de | 6269 | DRM_ERROR("Couldn't disable DPLL0\n"); |
1cd593e0 | 6270 | |
63911d72 | 6271 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
6272 | } |
6273 | ||
1cd593e0 | 6274 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af DL |
6275 | { |
6276 | u32 freq_select, pcu_ack; | |
a0b8a1fe | 6277 | int ret; |
5d96d8af | 6278 | |
1cd593e0 VS |
6279 | WARN_ON((cdclk == 24000) != (vco == 0)); |
6280 | ||
63911d72 | 6281 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af | 6282 | |
a0b8a1fe ID |
6283 | mutex_lock(&dev_priv->rps.hw_lock); |
6284 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, | |
6285 | SKL_CDCLK_PREPARE_FOR_CHANGE, | |
6286 | SKL_CDCLK_READY_FOR_CHANGE, | |
6287 | SKL_CDCLK_READY_FOR_CHANGE, 3); | |
6288 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6289 | if (ret) { | |
6290 | DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", | |
6291 | ret); | |
5d96d8af DL |
6292 | return; |
6293 | } | |
6294 | ||
6295 | /* set CDCLK_CTL */ | |
9ef56154 | 6296 | switch (cdclk) { |
5d96d8af DL |
6297 | case 450000: |
6298 | case 432000: | |
6299 | freq_select = CDCLK_FREQ_450_432; | |
6300 | pcu_ack = 1; | |
6301 | break; | |
6302 | case 540000: | |
6303 | freq_select = CDCLK_FREQ_540; | |
6304 | pcu_ack = 2; | |
6305 | break; | |
487ed2e4 | 6306 | case 308571: |
5d96d8af DL |
6307 | case 337500: |
6308 | default: | |
6309 | freq_select = CDCLK_FREQ_337_308; | |
6310 | pcu_ack = 0; | |
6311 | break; | |
487ed2e4 | 6312 | case 617143: |
5d96d8af DL |
6313 | case 675000: |
6314 | freq_select = CDCLK_FREQ_675_617; | |
6315 | pcu_ack = 3; | |
6316 | break; | |
6317 | } | |
6318 | ||
63911d72 VS |
6319 | if (dev_priv->cdclk_pll.vco != 0 && |
6320 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
6321 | skl_dpll0_disable(dev_priv); |
6322 | ||
63911d72 | 6323 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
6324 | skl_dpll0_enable(dev_priv, vco); |
6325 | ||
9ef56154 | 6326 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
6327 | POSTING_READ(CDCLK_CTL); |
6328 | ||
6329 | /* inform PCU of the change */ | |
6330 | mutex_lock(&dev_priv->rps.hw_lock); | |
6331 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
6332 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 | 6333 | |
4c75b940 | 6334 | intel_update_cdclk(dev_priv); |
5d96d8af DL |
6335 | } |
6336 | ||
9f7eb31a VS |
6337 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
6338 | ||
5d96d8af DL |
6339 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
6340 | { | |
709e05c3 | 6341 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
6342 | } |
6343 | ||
6344 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
6345 | { | |
9f7eb31a VS |
6346 | int cdclk, vco; |
6347 | ||
6348 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 6349 | |
63911d72 | 6350 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
6351 | /* |
6352 | * Use the current vco as our initial | |
6353 | * guess as to what the preferred vco is. | |
6354 | */ | |
6355 | if (dev_priv->skl_preferred_vco_freq == 0) | |
6356 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 6357 | dev_priv->cdclk_pll.vco); |
70c2c184 | 6358 | return; |
1cd593e0 | 6359 | } |
5d96d8af | 6360 | |
70c2c184 VS |
6361 | vco = dev_priv->skl_preferred_vco_freq; |
6362 | if (vco == 0) | |
63911d72 | 6363 | vco = 8100000; |
70c2c184 | 6364 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 6365 | |
70c2c184 | 6366 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
6367 | } |
6368 | ||
9f7eb31a | 6369 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 6370 | { |
09492498 | 6371 | uint32_t cdctl, expected; |
c73666f3 | 6372 | |
f1b391a5 SK |
6373 | /* |
6374 | * check if the pre-os intialized the display | |
6375 | * There is SWF18 scratchpad register defined which is set by the | |
6376 | * pre-os which can be used by the OS drivers to check the status | |
6377 | */ | |
6378 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
6379 | goto sanitize; | |
6380 | ||
4c75b940 | 6381 | intel_update_cdclk(dev_priv); |
c73666f3 | 6382 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
6383 | if (dev_priv->cdclk_pll.vco == 0 || |
6384 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
6385 | goto sanitize; |
6386 | ||
6387 | /* DPLL okay; verify the cdclock | |
6388 | * | |
6389 | * Noticed in some instances that the freq selection is correct but | |
6390 | * decimal part is programmed wrong from BIOS where pre-os does not | |
6391 | * enable display. Verify the same as well. | |
6392 | */ | |
09492498 VS |
6393 | cdctl = I915_READ(CDCLK_CTL); |
6394 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
6395 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6396 | if (cdctl == expected) | |
c73666f3 | 6397 | /* All well; nothing to sanitize */ |
9f7eb31a | 6398 | return; |
c89e39f3 | 6399 | |
9f7eb31a VS |
6400 | sanitize: |
6401 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 6402 | |
9f7eb31a VS |
6403 | /* force cdclk programming */ |
6404 | dev_priv->cdclk_freq = 0; | |
6405 | /* force full PLL disable + enable */ | |
63911d72 | 6406 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
6407 | } |
6408 | ||
30a970c6 JB |
6409 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
6410 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
6411 | { | |
fac5e23e | 6412 | struct drm_i915_private *dev_priv = to_i915(dev); |
30a970c6 JB |
6413 | u32 val, cmd; |
6414 | ||
1353c4fb | 6415 | WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) |
164dfd28 | 6416 | != dev_priv->cdclk_freq); |
d60c4473 | 6417 | |
dfcab17e | 6418 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 6419 | cmd = 2; |
dfcab17e | 6420 | else if (cdclk == 266667) |
30a970c6 JB |
6421 | cmd = 1; |
6422 | else | |
6423 | cmd = 0; | |
6424 | ||
6425 | mutex_lock(&dev_priv->rps.hw_lock); | |
6426 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6427 | val &= ~DSPFREQGUAR_MASK; | |
6428 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
6429 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6430 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6431 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
6432 | 50)) { | |
6433 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6434 | } | |
6435 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6436 | ||
54433e91 VS |
6437 | mutex_lock(&dev_priv->sb_lock); |
6438 | ||
dfcab17e | 6439 | if (cdclk == 400000) { |
6bcda4f0 | 6440 | u32 divider; |
30a970c6 | 6441 | |
6bcda4f0 | 6442 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 6443 | |
30a970c6 JB |
6444 | /* adjust cdclk divider */ |
6445 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 6446 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
6447 | val |= divider; |
6448 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
6449 | |
6450 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 6451 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
6452 | 50)) |
6453 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
6454 | } |
6455 | ||
30a970c6 JB |
6456 | /* adjust self-refresh exit latency value */ |
6457 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
6458 | val &= ~0x7f; | |
6459 | ||
6460 | /* | |
6461 | * For high bandwidth configs, we set a higher latency in the bunit | |
6462 | * so that the core display fetch happens in time to avoid underruns. | |
6463 | */ | |
dfcab17e | 6464 | if (cdclk == 400000) |
30a970c6 JB |
6465 | val |= 4500 / 250; /* 4.5 usec */ |
6466 | else | |
6467 | val |= 3000 / 250; /* 3.0 usec */ | |
6468 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 6469 | |
a580516d | 6470 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 6471 | |
4c75b940 | 6472 | intel_update_cdclk(dev_priv); |
30a970c6 JB |
6473 | } |
6474 | ||
383c5a6a VS |
6475 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
6476 | { | |
fac5e23e | 6477 | struct drm_i915_private *dev_priv = to_i915(dev); |
383c5a6a VS |
6478 | u32 val, cmd; |
6479 | ||
1353c4fb | 6480 | WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) |
164dfd28 | 6481 | != dev_priv->cdclk_freq); |
383c5a6a VS |
6482 | |
6483 | switch (cdclk) { | |
383c5a6a VS |
6484 | case 333333: |
6485 | case 320000: | |
383c5a6a | 6486 | case 266667: |
383c5a6a | 6487 | case 200000: |
383c5a6a VS |
6488 | break; |
6489 | default: | |
5f77eeb0 | 6490 | MISSING_CASE(cdclk); |
383c5a6a VS |
6491 | return; |
6492 | } | |
6493 | ||
9d0d3fda VS |
6494 | /* |
6495 | * Specs are full of misinformation, but testing on actual | |
6496 | * hardware has shown that we just need to write the desired | |
6497 | * CCK divider into the Punit register. | |
6498 | */ | |
6499 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6500 | ||
383c5a6a VS |
6501 | mutex_lock(&dev_priv->rps.hw_lock); |
6502 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6503 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6504 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6505 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6506 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6507 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6508 | 50)) { | |
6509 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6510 | } | |
6511 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6512 | ||
4c75b940 | 6513 | intel_update_cdclk(dev_priv); |
383c5a6a VS |
6514 | } |
6515 | ||
30a970c6 JB |
6516 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6517 | int max_pixclk) | |
6518 | { | |
6bcda4f0 | 6519 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6520 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6521 | |
30a970c6 JB |
6522 | /* |
6523 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6524 | * 200MHz | |
6525 | * 267MHz | |
29dc7ef3 | 6526 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6527 | * 400MHz (VLV only) |
6528 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6529 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6530 | * |
6531 | * We seem to get an unstable or solid color picture at 200MHz. | |
6532 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6533 | * are off. | |
30a970c6 | 6534 | */ |
6cca3195 VS |
6535 | if (!IS_CHERRYVIEW(dev_priv) && |
6536 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6537 | return 400000; |
6cca3195 | 6538 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6539 | return freq_320; |
e37c67a1 | 6540 | else if (max_pixclk > 0) |
dfcab17e | 6541 | return 266667; |
e37c67a1 VS |
6542 | else |
6543 | return 200000; | |
30a970c6 JB |
6544 | } |
6545 | ||
89b3c3c7 ACO |
6546 | static int glk_calc_cdclk(int max_pixclk) |
6547 | { | |
09d09386 | 6548 | if (max_pixclk > 2 * 158400) |
89b3c3c7 | 6549 | return 316800; |
09d09386 | 6550 | else if (max_pixclk > 2 * 79200) |
89b3c3c7 ACO |
6551 | return 158400; |
6552 | else | |
6553 | return 79200; | |
6554 | } | |
6555 | ||
324513c0 | 6556 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 6557 | { |
760e1477 | 6558 | if (max_pixclk > 576000) |
f8437dd1 | 6559 | return 624000; |
760e1477 | 6560 | else if (max_pixclk > 384000) |
f8437dd1 | 6561 | return 576000; |
760e1477 | 6562 | else if (max_pixclk > 288000) |
f8437dd1 | 6563 | return 384000; |
760e1477 | 6564 | else if (max_pixclk > 144000) |
f8437dd1 VK |
6565 | return 288000; |
6566 | else | |
6567 | return 144000; | |
6568 | } | |
6569 | ||
e8788cbc | 6570 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6571 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6572 | struct drm_atomic_state *state) | |
30a970c6 | 6573 | { |
565602d7 | 6574 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 6575 | struct drm_i915_private *dev_priv = to_i915(dev); |
565602d7 ML |
6576 | struct drm_crtc *crtc; |
6577 | struct drm_crtc_state *crtc_state; | |
6578 | unsigned max_pixclk = 0, i; | |
6579 | enum pipe pipe; | |
30a970c6 | 6580 | |
565602d7 ML |
6581 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6582 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6583 | |
565602d7 ML |
6584 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6585 | int pixclk = 0; | |
6586 | ||
6587 | if (crtc_state->enable) | |
6588 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6589 | |
565602d7 | 6590 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6591 | } |
6592 | ||
565602d7 ML |
6593 | for_each_pipe(dev_priv, pipe) |
6594 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6595 | ||
30a970c6 JB |
6596 | return max_pixclk; |
6597 | } | |
6598 | ||
27c329ed | 6599 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6600 | { |
27c329ed | 6601 | struct drm_device *dev = state->dev; |
fac5e23e | 6602 | struct drm_i915_private *dev_priv = to_i915(dev); |
27c329ed | 6603 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
6604 | struct intel_atomic_state *intel_state = |
6605 | to_intel_atomic_state(state); | |
30a970c6 | 6606 | |
1a617b77 | 6607 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6608 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6609 | |
1a617b77 ML |
6610 | if (!intel_state->active_crtcs) |
6611 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6612 | ||
27c329ed ML |
6613 | return 0; |
6614 | } | |
304603f4 | 6615 | |
324513c0 | 6616 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6617 | { |
89b3c3c7 | 6618 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4e5ca60f | 6619 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6620 | struct intel_atomic_state *intel_state = |
6621 | to_intel_atomic_state(state); | |
89b3c3c7 | 6622 | int cdclk; |
85a96e7a | 6623 | |
89b3c3c7 ACO |
6624 | if (IS_GEMINILAKE(dev_priv)) |
6625 | cdclk = glk_calc_cdclk(max_pixclk); | |
6626 | else | |
6627 | cdclk = bxt_calc_cdclk(max_pixclk); | |
85a96e7a | 6628 | |
89b3c3c7 ACO |
6629 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
6630 | ||
6631 | if (!intel_state->active_crtcs) { | |
6632 | if (IS_GEMINILAKE(dev_priv)) | |
6633 | cdclk = glk_calc_cdclk(0); | |
6634 | else | |
6635 | cdclk = bxt_calc_cdclk(0); | |
6636 | ||
6637 | intel_state->dev_cdclk = cdclk; | |
6638 | } | |
1a617b77 | 6639 | |
27c329ed | 6640 | return 0; |
30a970c6 JB |
6641 | } |
6642 | ||
1e69cd74 VS |
6643 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6644 | { | |
6645 | unsigned int credits, default_credits; | |
6646 | ||
6647 | if (IS_CHERRYVIEW(dev_priv)) | |
6648 | default_credits = PFI_CREDIT(12); | |
6649 | else | |
6650 | default_credits = PFI_CREDIT(8); | |
6651 | ||
bfa7df01 | 6652 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6653 | /* CHV suggested value is 31 or 63 */ |
6654 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6655 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6656 | else |
6657 | credits = PFI_CREDIT(15); | |
6658 | } else { | |
6659 | credits = default_credits; | |
6660 | } | |
6661 | ||
6662 | /* | |
6663 | * WA - write default credits before re-programming | |
6664 | * FIXME: should we also set the resend bit here? | |
6665 | */ | |
6666 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6667 | default_credits); | |
6668 | ||
6669 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6670 | credits | PFI_CREDIT_RESEND); | |
6671 | ||
6672 | /* | |
6673 | * FIXME is this guaranteed to clear | |
6674 | * immediately or should we poll for it? | |
6675 | */ | |
6676 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6677 | } | |
6678 | ||
27c329ed | 6679 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6680 | { |
a821fc46 | 6681 | struct drm_device *dev = old_state->dev; |
fac5e23e | 6682 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 ML |
6683 | struct intel_atomic_state *old_intel_state = |
6684 | to_intel_atomic_state(old_state); | |
6685 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6686 | |
27c329ed ML |
6687 | /* |
6688 | * FIXME: We can end up here with all power domains off, yet | |
6689 | * with a CDCLK frequency other than the minimum. To account | |
6690 | * for this take the PIPE-A power domain, which covers the HW | |
6691 | * blocks needed for the following programming. This can be | |
6692 | * removed once it's guaranteed that we get here either with | |
6693 | * the minimum CDCLK set, or the required power domains | |
6694 | * enabled. | |
6695 | */ | |
6696 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6697 | |
920a14b2 | 6698 | if (IS_CHERRYVIEW(dev_priv)) |
27c329ed ML |
6699 | cherryview_set_cdclk(dev, req_cdclk); |
6700 | else | |
6701 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6702 | |
27c329ed | 6703 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6704 | |
27c329ed | 6705 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6706 | } |
6707 | ||
4a806558 ML |
6708 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
6709 | struct drm_atomic_state *old_state) | |
89b667f8 | 6710 | { |
4a806558 | 6711 | struct drm_crtc *crtc = pipe_config->base.crtc; |
89b667f8 | 6712 | struct drm_device *dev = crtc->dev; |
a72e4c9f | 6713 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 | 6714 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
89b667f8 | 6715 | int pipe = intel_crtc->pipe; |
89b667f8 | 6716 | |
53d9f4e9 | 6717 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6718 | return; |
6719 | ||
37a5650b | 6720 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6721 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6722 | |
6723 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6724 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6725 | |
920a14b2 | 6726 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
fac5e23e | 6727 | struct drm_i915_private *dev_priv = to_i915(dev); |
c14b0485 VS |
6728 | |
6729 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6730 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6731 | } | |
6732 | ||
5b18e57c DV |
6733 | i9xx_set_pipeconf(intel_crtc); |
6734 | ||
89b667f8 | 6735 | intel_crtc->active = true; |
89b667f8 | 6736 | |
a72e4c9f | 6737 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6738 | |
fd6bbda9 | 6739 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
89b667f8 | 6740 | |
920a14b2 | 6741 | if (IS_CHERRYVIEW(dev_priv)) { |
cd2d34d9 VS |
6742 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
6743 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6744 | } else { | |
6745 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6746 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6747 | } |
89b667f8 | 6748 | |
fd6bbda9 | 6749 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
89b667f8 | 6750 | |
2dd24552 JB |
6751 | i9xx_pfit_enable(intel_crtc); |
6752 | ||
b95c5321 | 6753 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6754 | |
432081bc | 6755 | intel_update_watermarks(intel_crtc); |
e1fdc473 | 6756 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6757 | |
4b3a9526 VS |
6758 | assert_vblank_disabled(crtc); |
6759 | drm_crtc_vblank_on(crtc); | |
6760 | ||
fd6bbda9 | 6761 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b667f8 JB |
6762 | } |
6763 | ||
f13c2ef3 DV |
6764 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6765 | { | |
6766 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6767 | struct drm_i915_private *dev_priv = to_i915(dev); |
f13c2ef3 | 6768 | |
6e3c9717 ACO |
6769 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6770 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6771 | } |
6772 | ||
4a806558 ML |
6773 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
6774 | struct drm_atomic_state *old_state) | |
79e53945 | 6775 | { |
4a806558 | 6776 | struct drm_crtc *crtc = pipe_config->base.crtc; |
79e53945 | 6777 | struct drm_device *dev = crtc->dev; |
a72e4c9f | 6778 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6779 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cd2d34d9 | 6780 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6781 | |
53d9f4e9 | 6782 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6783 | return; |
6784 | ||
f13c2ef3 DV |
6785 | i9xx_set_pll_dividers(intel_crtc); |
6786 | ||
37a5650b | 6787 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6788 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6789 | |
6790 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6791 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6792 | |
5b18e57c DV |
6793 | i9xx_set_pipeconf(intel_crtc); |
6794 | ||
f7abfe8b | 6795 | intel_crtc->active = true; |
6b383a7f | 6796 | |
5db94019 | 6797 | if (!IS_GEN2(dev_priv)) |
a72e4c9f | 6798 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6799 | |
fd6bbda9 | 6800 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
9d6d9f19 | 6801 | |
f6736a1a DV |
6802 | i9xx_enable_pll(intel_crtc); |
6803 | ||
2dd24552 JB |
6804 | i9xx_pfit_enable(intel_crtc); |
6805 | ||
b95c5321 | 6806 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6807 | |
432081bc | 6808 | intel_update_watermarks(intel_crtc); |
e1fdc473 | 6809 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6810 | |
4b3a9526 VS |
6811 | assert_vblank_disabled(crtc); |
6812 | drm_crtc_vblank_on(crtc); | |
6813 | ||
fd6bbda9 | 6814 | intel_encoders_enable(crtc, pipe_config, old_state); |
0b8765c6 | 6815 | } |
79e53945 | 6816 | |
87476d63 DV |
6817 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6818 | { | |
6819 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6820 | struct drm_i915_private *dev_priv = to_i915(dev); |
87476d63 | 6821 | |
6e3c9717 | 6822 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6823 | return; |
87476d63 | 6824 | |
328d8e82 | 6825 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6826 | |
328d8e82 DV |
6827 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6828 | I915_READ(PFIT_CONTROL)); | |
6829 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6830 | } |
6831 | ||
4a806558 ML |
6832 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
6833 | struct drm_atomic_state *old_state) | |
0b8765c6 | 6834 | { |
4a806558 | 6835 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
0b8765c6 | 6836 | struct drm_device *dev = crtc->dev; |
fac5e23e | 6837 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b8765c6 JB |
6838 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6839 | int pipe = intel_crtc->pipe; | |
ef9c3aee | 6840 | |
6304cd91 VS |
6841 | /* |
6842 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6843 | * wait for planes to fully turn off before disabling the pipe. | |
6844 | */ | |
5db94019 | 6845 | if (IS_GEN2(dev_priv)) |
0f0f74bc | 6846 | intel_wait_for_vblank(dev_priv, pipe); |
6304cd91 | 6847 | |
fd6bbda9 | 6848 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4b3a9526 | 6849 | |
f9b61ff6 DV |
6850 | drm_crtc_vblank_off(crtc); |
6851 | assert_vblank_disabled(crtc); | |
6852 | ||
575f7ab7 | 6853 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6854 | |
87476d63 | 6855 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6856 | |
fd6bbda9 | 6857 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
89b667f8 | 6858 | |
d7edc4e5 | 6859 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
920a14b2 | 6860 | if (IS_CHERRYVIEW(dev_priv)) |
076ed3b2 | 6861 | chv_disable_pll(dev_priv, pipe); |
11a914c2 | 6862 | else if (IS_VALLEYVIEW(dev_priv)) |
076ed3b2 CML |
6863 | vlv_disable_pll(dev_priv, pipe); |
6864 | else | |
1c4e0274 | 6865 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6866 | } |
0b8765c6 | 6867 | |
fd6bbda9 | 6868 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
d6db995f | 6869 | |
5db94019 | 6870 | if (!IS_GEN2(dev_priv)) |
a72e4c9f | 6871 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6872 | } |
6873 | ||
b17d48e2 ML |
6874 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6875 | { | |
842e0307 | 6876 | struct intel_encoder *encoder; |
b17d48e2 ML |
6877 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6878 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6879 | enum intel_display_power_domain domain; | |
6880 | unsigned long domains; | |
4a806558 ML |
6881 | struct drm_atomic_state *state; |
6882 | struct intel_crtc_state *crtc_state; | |
6883 | int ret; | |
b17d48e2 ML |
6884 | |
6885 | if (!intel_crtc->active) | |
6886 | return; | |
6887 | ||
936e71e3 | 6888 | if (to_intel_plane_state(crtc->primary->state)->base.visible) { |
5a21b665 | 6889 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6890 | |
2622a081 | 6891 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6892 | |
6893 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
936e71e3 | 6894 | to_intel_plane_state(crtc->primary->state)->base.visible = false; |
a539205a ML |
6895 | } |
6896 | ||
4a806558 ML |
6897 | state = drm_atomic_state_alloc(crtc->dev); |
6898 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; | |
6899 | ||
6900 | /* Everything's already locked, -EDEADLK can't happen. */ | |
6901 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
6902 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
6903 | ||
6904 | WARN_ON(IS_ERR(crtc_state) || ret); | |
6905 | ||
6906 | dev_priv->display.crtc_disable(crtc_state, state); | |
6907 | ||
0853695c | 6908 | drm_atomic_state_put(state); |
842e0307 | 6909 | |
78108b7c VS |
6910 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6911 | crtc->base.id, crtc->name); | |
842e0307 ML |
6912 | |
6913 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6914 | crtc->state->active = false; | |
37d9078b | 6915 | intel_crtc->active = false; |
842e0307 ML |
6916 | crtc->enabled = false; |
6917 | crtc->state->connector_mask = 0; | |
6918 | crtc->state->encoder_mask = 0; | |
6919 | ||
6920 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6921 | encoder->base.crtc = NULL; | |
6922 | ||
58f9c0bc | 6923 | intel_fbc_disable(intel_crtc); |
432081bc | 6924 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 6925 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6926 | |
6927 | domains = intel_crtc->enabled_power_domains; | |
6928 | for_each_power_domain(domain, domains) | |
6929 | intel_display_power_put(dev_priv, domain); | |
6930 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6931 | |
6932 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6933 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6934 | } |
6935 | ||
6b72d486 ML |
6936 | /* |
6937 | * turn all crtc's off, but do not adjust state | |
6938 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6939 | */ | |
70e0bd74 | 6940 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6941 | { |
e2c8b870 | 6942 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6943 | struct drm_atomic_state *state; |
e2c8b870 | 6944 | int ret; |
70e0bd74 | 6945 | |
e2c8b870 ML |
6946 | state = drm_atomic_helper_suspend(dev); |
6947 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6948 | if (ret) |
6949 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6950 | else |
6951 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6952 | return ret; |
ee7b9f93 JB |
6953 | } |
6954 | ||
ea5b213a | 6955 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6956 | { |
4ef69c7a | 6957 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6958 | |
ea5b213a CW |
6959 | drm_encoder_cleanup(encoder); |
6960 | kfree(intel_encoder); | |
7e7d76c3 JB |
6961 | } |
6962 | ||
0a91ca29 DV |
6963 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6964 | * internal consistency). */ | |
5a21b665 | 6965 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6966 | { |
5a21b665 | 6967 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6968 | |
6969 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6970 | connector->base.base.id, | |
6971 | connector->base.name); | |
6972 | ||
0a91ca29 | 6973 | if (connector->get_hw_state(connector)) { |
e85376cb | 6974 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6975 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6976 | |
35dd3c64 ML |
6977 | I915_STATE_WARN(!crtc, |
6978 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6979 | |
35dd3c64 ML |
6980 | if (!crtc) |
6981 | return; | |
6982 | ||
6983 | I915_STATE_WARN(!crtc->state->active, | |
6984 | "connector is active, but attached crtc isn't\n"); | |
6985 | ||
e85376cb | 6986 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6987 | return; |
6988 | ||
e85376cb | 6989 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6990 | "atomic encoder doesn't match attached encoder\n"); |
6991 | ||
e85376cb | 6992 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6993 | "attached encoder crtc differs from connector crtc\n"); |
6994 | } else { | |
4d688a2a ML |
6995 | I915_STATE_WARN(crtc && crtc->state->active, |
6996 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 6997 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 6998 | "best encoder set without crtc!\n"); |
0a91ca29 | 6999 | } |
79e53945 JB |
7000 | } |
7001 | ||
08d9bc92 ACO |
7002 | int intel_connector_init(struct intel_connector *connector) |
7003 | { | |
5350a031 | 7004 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 7005 | |
5350a031 | 7006 | if (!connector->base.state) |
08d9bc92 ACO |
7007 | return -ENOMEM; |
7008 | ||
08d9bc92 ACO |
7009 | return 0; |
7010 | } | |
7011 | ||
7012 | struct intel_connector *intel_connector_alloc(void) | |
7013 | { | |
7014 | struct intel_connector *connector; | |
7015 | ||
7016 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
7017 | if (!connector) | |
7018 | return NULL; | |
7019 | ||
7020 | if (intel_connector_init(connector) < 0) { | |
7021 | kfree(connector); | |
7022 | return NULL; | |
7023 | } | |
7024 | ||
7025 | return connector; | |
7026 | } | |
7027 | ||
f0947c37 DV |
7028 | /* Simple connector->get_hw_state implementation for encoders that support only |
7029 | * one connector and no cloning and hence the encoder state determines the state | |
7030 | * of the connector. */ | |
7031 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 7032 | { |
24929352 | 7033 | enum pipe pipe = 0; |
f0947c37 | 7034 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 7035 | |
f0947c37 | 7036 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
7037 | } |
7038 | ||
6d293983 | 7039 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 7040 | { |
6d293983 ACO |
7041 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
7042 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
7043 | |
7044 | return 0; | |
7045 | } | |
7046 | ||
6d293983 | 7047 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 7048 | struct intel_crtc_state *pipe_config) |
1857e1da | 7049 | { |
8652744b | 7050 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
7051 | struct drm_atomic_state *state = pipe_config->base.state; |
7052 | struct intel_crtc *other_crtc; | |
7053 | struct intel_crtc_state *other_crtc_state; | |
7054 | ||
1857e1da DV |
7055 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
7056 | pipe_name(pipe), pipe_config->fdi_lanes); | |
7057 | if (pipe_config->fdi_lanes > 4) { | |
7058 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
7059 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7060 | return -EINVAL; |
1857e1da DV |
7061 | } |
7062 | ||
8652744b | 7063 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
7064 | if (pipe_config->fdi_lanes > 2) { |
7065 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
7066 | pipe_config->fdi_lanes); | |
6d293983 | 7067 | return -EINVAL; |
1857e1da | 7068 | } else { |
6d293983 | 7069 | return 0; |
1857e1da DV |
7070 | } |
7071 | } | |
7072 | ||
b7f05d4a | 7073 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 7074 | return 0; |
1857e1da DV |
7075 | |
7076 | /* Ivybridge 3 pipe is really complicated */ | |
7077 | switch (pipe) { | |
7078 | case PIPE_A: | |
6d293983 | 7079 | return 0; |
1857e1da | 7080 | case PIPE_B: |
6d293983 ACO |
7081 | if (pipe_config->fdi_lanes <= 2) |
7082 | return 0; | |
7083 | ||
b91eb5cc | 7084 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
7085 | other_crtc_state = |
7086 | intel_atomic_get_crtc_state(state, other_crtc); | |
7087 | if (IS_ERR(other_crtc_state)) | |
7088 | return PTR_ERR(other_crtc_state); | |
7089 | ||
7090 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
7091 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
7092 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7093 | return -EINVAL; |
1857e1da | 7094 | } |
6d293983 | 7095 | return 0; |
1857e1da | 7096 | case PIPE_C: |
251cc67c VS |
7097 | if (pipe_config->fdi_lanes > 2) { |
7098 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
7099 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7100 | return -EINVAL; |
251cc67c | 7101 | } |
6d293983 | 7102 | |
b91eb5cc | 7103 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
7104 | other_crtc_state = |
7105 | intel_atomic_get_crtc_state(state, other_crtc); | |
7106 | if (IS_ERR(other_crtc_state)) | |
7107 | return PTR_ERR(other_crtc_state); | |
7108 | ||
7109 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 7110 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 7111 | return -EINVAL; |
1857e1da | 7112 | } |
6d293983 | 7113 | return 0; |
1857e1da DV |
7114 | default: |
7115 | BUG(); | |
7116 | } | |
7117 | } | |
7118 | ||
e29c22c0 DV |
7119 | #define RETRY 1 |
7120 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 7121 | struct intel_crtc_state *pipe_config) |
877d48d5 | 7122 | { |
1857e1da | 7123 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 7124 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
7125 | int lane, link_bw, fdi_dotclock, ret; |
7126 | bool needs_recompute = false; | |
877d48d5 | 7127 | |
e29c22c0 | 7128 | retry: |
877d48d5 DV |
7129 | /* FDI is a binary signal running at ~2.7GHz, encoding |
7130 | * each output octet as 10 bits. The actual frequency | |
7131 | * is stored as a divider into a 100MHz clock, and the | |
7132 | * mode pixel clock is stored in units of 1KHz. | |
7133 | * Hence the bw of each lane in terms of the mode signal | |
7134 | * is: | |
7135 | */ | |
21a727b3 | 7136 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 7137 | |
241bfc38 | 7138 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 7139 | |
2bd89a07 | 7140 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
7141 | pipe_config->pipe_bpp); |
7142 | ||
7143 | pipe_config->fdi_lanes = lane; | |
7144 | ||
2bd89a07 | 7145 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 7146 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 7147 | |
e3b247da | 7148 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 7149 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
7150 | pipe_config->pipe_bpp -= 2*3; |
7151 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
7152 | pipe_config->pipe_bpp); | |
7153 | needs_recompute = true; | |
7154 | pipe_config->bw_constrained = true; | |
7155 | ||
7156 | goto retry; | |
7157 | } | |
7158 | ||
7159 | if (needs_recompute) | |
7160 | return RETRY; | |
7161 | ||
6d293983 | 7162 | return ret; |
877d48d5 DV |
7163 | } |
7164 | ||
8cfb3407 VS |
7165 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
7166 | struct intel_crtc_state *pipe_config) | |
7167 | { | |
7168 | if (pipe_config->pipe_bpp > 24) | |
7169 | return false; | |
7170 | ||
7171 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 7172 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
7173 | return true; |
7174 | ||
7175 | /* | |
b432e5cf VS |
7176 | * We compare against max which means we must take |
7177 | * the increased cdclk requirement into account when | |
7178 | * calculating the new cdclk. | |
7179 | * | |
7180 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
7181 | */ |
7182 | return ilk_pipe_pixel_rate(pipe_config) <= | |
7183 | dev_priv->max_cdclk_freq * 95 / 100; | |
7184 | } | |
7185 | ||
42db64ef | 7186 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 7187 | struct intel_crtc_state *pipe_config) |
42db64ef | 7188 | { |
8cfb3407 | 7189 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7190 | struct drm_i915_private *dev_priv = to_i915(dev); |
8cfb3407 | 7191 | |
d330a953 | 7192 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
7193 | hsw_crtc_supports_ips(crtc) && |
7194 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
7195 | } |
7196 | ||
39acb4aa VS |
7197 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
7198 | { | |
7199 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7200 | ||
7201 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
7202 | return INTEL_INFO(dev_priv)->gen < 4 && | |
7203 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
7204 | } | |
7205 | ||
a43f6e0f | 7206 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 7207 | struct intel_crtc_state *pipe_config) |
79e53945 | 7208 | { |
a43f6e0f | 7209 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7210 | struct drm_i915_private *dev_priv = to_i915(dev); |
7c5f93b0 | 7211 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 7212 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 7213 | |
6315b5d3 | 7214 | if (INTEL_GEN(dev_priv) < 4) { |
f3261156 | 7215 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
7216 | |
7217 | /* | |
39acb4aa | 7218 | * Enable double wide mode when the dot clock |
cf532bb2 | 7219 | * is > 90% of the (display) core speed. |
cf532bb2 | 7220 | */ |
39acb4aa VS |
7221 | if (intel_crtc_supports_double_wide(crtc) && |
7222 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 7223 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 7224 | pipe_config->double_wide = true; |
ad3a4479 | 7225 | } |
f3261156 | 7226 | } |
ad3a4479 | 7227 | |
f3261156 VS |
7228 | if (adjusted_mode->crtc_clock > clock_limit) { |
7229 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
7230 | adjusted_mode->crtc_clock, clock_limit, | |
7231 | yesno(pipe_config->double_wide)); | |
7232 | return -EINVAL; | |
2c07245f | 7233 | } |
89749350 | 7234 | |
1d1d0e27 VS |
7235 | /* |
7236 | * Pipe horizontal size must be even in: | |
7237 | * - DVO ganged mode | |
7238 | * - LVDS dual channel mode | |
7239 | * - Double wide pipe | |
7240 | */ | |
2d84d2b3 | 7241 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
7242 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
7243 | pipe_config->pipe_src_w &= ~1; | |
7244 | ||
8693a824 DL |
7245 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
7246 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 | 7247 | */ |
9beb5fea | 7248 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && |
aad941d5 | 7249 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 7250 | return -EINVAL; |
44f46b42 | 7251 | |
50a0bc90 | 7252 | if (HAS_IPS(dev_priv)) |
a43f6e0f DV |
7253 | hsw_compute_ips_config(crtc, pipe_config); |
7254 | ||
877d48d5 | 7255 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 7256 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 7257 | |
cf5a15be | 7258 | return 0; |
79e53945 JB |
7259 | } |
7260 | ||
1353c4fb | 7261 | static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7262 | { |
1353c4fb | 7263 | u32 cdctl; |
1652d19e | 7264 | |
ea61791e | 7265 | skl_dpll0_update(dev_priv); |
1652d19e | 7266 | |
63911d72 | 7267 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 7268 | return dev_priv->cdclk_pll.ref; |
1652d19e | 7269 | |
ea61791e | 7270 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 7271 | |
63911d72 | 7272 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
7273 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7274 | case CDCLK_FREQ_450_432: | |
7275 | return 432000; | |
7276 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 7277 | return 308571; |
ea61791e VS |
7278 | case CDCLK_FREQ_540: |
7279 | return 540000; | |
1652d19e | 7280 | case CDCLK_FREQ_675_617: |
487ed2e4 | 7281 | return 617143; |
1652d19e | 7282 | default: |
ea61791e | 7283 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7284 | } |
7285 | } else { | |
1652d19e VS |
7286 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7287 | case CDCLK_FREQ_450_432: | |
7288 | return 450000; | |
7289 | case CDCLK_FREQ_337_308: | |
7290 | return 337500; | |
ea61791e VS |
7291 | case CDCLK_FREQ_540: |
7292 | return 540000; | |
1652d19e VS |
7293 | case CDCLK_FREQ_675_617: |
7294 | return 675000; | |
7295 | default: | |
ea61791e | 7296 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7297 | } |
7298 | } | |
7299 | ||
709e05c3 | 7300 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
7301 | } |
7302 | ||
83d7c81f VS |
7303 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
7304 | { | |
7305 | u32 val; | |
7306 | ||
7307 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 7308 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
7309 | |
7310 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 7311 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 7312 | return; |
83d7c81f | 7313 | |
1c3f7700 ID |
7314 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
7315 | return; | |
83d7c81f VS |
7316 | |
7317 | val = I915_READ(BXT_DE_PLL_CTL); | |
7318 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
7319 | dev_priv->cdclk_pll.ref; | |
7320 | } | |
7321 | ||
1353c4fb | 7322 | static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv) |
acd3f3d3 | 7323 | { |
f5986242 VS |
7324 | u32 divider; |
7325 | int div, vco; | |
acd3f3d3 | 7326 | |
83d7c81f VS |
7327 | bxt_de_pll_update(dev_priv); |
7328 | ||
f5986242 VS |
7329 | vco = dev_priv->cdclk_pll.vco; |
7330 | if (vco == 0) | |
7331 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 7332 | |
f5986242 | 7333 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 7334 | |
f5986242 | 7335 | switch (divider) { |
acd3f3d3 | 7336 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
7337 | div = 2; |
7338 | break; | |
acd3f3d3 | 7339 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
89b3c3c7 | 7340 | WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); |
f5986242 VS |
7341 | div = 3; |
7342 | break; | |
acd3f3d3 | 7343 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
7344 | div = 4; |
7345 | break; | |
acd3f3d3 | 7346 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
7347 | div = 8; |
7348 | break; | |
7349 | default: | |
7350 | MISSING_CASE(divider); | |
7351 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
7352 | } |
7353 | ||
f5986242 | 7354 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
7355 | } |
7356 | ||
1353c4fb | 7357 | static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7358 | { |
1652d19e VS |
7359 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7360 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7361 | ||
7362 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7363 | return 800000; | |
7364 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7365 | return 450000; | |
7366 | else if (freq == LCPLL_CLK_FREQ_450) | |
7367 | return 450000; | |
7368 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
7369 | return 540000; | |
7370 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
7371 | return 337500; | |
7372 | else | |
7373 | return 675000; | |
7374 | } | |
7375 | ||
1353c4fb | 7376 | static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7377 | { |
1652d19e VS |
7378 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7379 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7380 | ||
7381 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7382 | return 800000; | |
7383 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7384 | return 450000; | |
7385 | else if (freq == LCPLL_CLK_FREQ_450) | |
7386 | return 450000; | |
50a0bc90 | 7387 | else if (IS_HSW_ULT(dev_priv)) |
1652d19e VS |
7388 | return 337500; |
7389 | else | |
7390 | return 540000; | |
79e53945 JB |
7391 | } |
7392 | ||
1353c4fb | 7393 | static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv) |
25eb05fc | 7394 | { |
1353c4fb | 7395 | return vlv_get_cck_clock_hpll(dev_priv, "cdclk", |
bfa7df01 | 7396 | CCK_DISPLAY_CLOCK_CONTROL); |
25eb05fc JB |
7397 | } |
7398 | ||
1353c4fb | 7399 | static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv) |
b37a6434 VS |
7400 | { |
7401 | return 450000; | |
7402 | } | |
7403 | ||
1353c4fb | 7404 | static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 JB |
7405 | { |
7406 | return 400000; | |
7407 | } | |
79e53945 | 7408 | |
1353c4fb | 7409 | static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv) |
79e53945 | 7410 | { |
e907f170 | 7411 | return 333333; |
e70236a8 | 7412 | } |
79e53945 | 7413 | |
1353c4fb | 7414 | static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 JB |
7415 | { |
7416 | return 200000; | |
7417 | } | |
79e53945 | 7418 | |
1353c4fb | 7419 | static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv) |
257a7ffc | 7420 | { |
1353c4fb | 7421 | struct pci_dev *pdev = dev_priv->drm.pdev; |
257a7ffc DV |
7422 | u16 gcfgc = 0; |
7423 | ||
52a05c30 | 7424 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
257a7ffc DV |
7425 | |
7426 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7427 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 7428 | return 266667; |
257a7ffc | 7429 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 7430 | return 333333; |
257a7ffc | 7431 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 7432 | return 444444; |
257a7ffc DV |
7433 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
7434 | return 200000; | |
7435 | default: | |
7436 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
7437 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 7438 | return 133333; |
257a7ffc | 7439 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 7440 | return 166667; |
257a7ffc DV |
7441 | } |
7442 | } | |
7443 | ||
1353c4fb | 7444 | static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7445 | { |
1353c4fb | 7446 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e70236a8 | 7447 | u16 gcfgc = 0; |
79e53945 | 7448 | |
52a05c30 | 7449 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
e70236a8 JB |
7450 | |
7451 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 7452 | return 133333; |
e70236a8 JB |
7453 | else { |
7454 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7455 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 7456 | return 333333; |
e70236a8 JB |
7457 | default: |
7458 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
7459 | return 190000; | |
79e53945 | 7460 | } |
e70236a8 JB |
7461 | } |
7462 | } | |
7463 | ||
1353c4fb | 7464 | static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7465 | { |
e907f170 | 7466 | return 266667; |
e70236a8 JB |
7467 | } |
7468 | ||
1353c4fb | 7469 | static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7470 | { |
1353c4fb | 7471 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e70236a8 | 7472 | u16 hpllcc = 0; |
1b1d2716 | 7473 | |
65cd2b3f VS |
7474 | /* |
7475 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
7476 | * encoding is different :( | |
7477 | * FIXME is this the right way to detect 852GM/852GMV? | |
7478 | */ | |
52a05c30 | 7479 | if (pdev->revision == 0x1) |
65cd2b3f VS |
7480 | return 133333; |
7481 | ||
52a05c30 | 7482 | pci_bus_read_config_word(pdev->bus, |
1b1d2716 VS |
7483 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); |
7484 | ||
e70236a8 JB |
7485 | /* Assume that the hardware is in the high speed state. This |
7486 | * should be the default. | |
7487 | */ | |
7488 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
7489 | case GC_CLOCK_133_200: | |
1b1d2716 | 7490 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
7491 | case GC_CLOCK_100_200: |
7492 | return 200000; | |
7493 | case GC_CLOCK_166_250: | |
7494 | return 250000; | |
7495 | case GC_CLOCK_100_133: | |
e907f170 | 7496 | return 133333; |
1b1d2716 VS |
7497 | case GC_CLOCK_133_266: |
7498 | case GC_CLOCK_133_266_2: | |
7499 | case GC_CLOCK_166_266: | |
7500 | return 266667; | |
e70236a8 | 7501 | } |
79e53945 | 7502 | |
e70236a8 JB |
7503 | /* Shouldn't happen */ |
7504 | return 0; | |
7505 | } | |
79e53945 | 7506 | |
1353c4fb | 7507 | static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7508 | { |
e907f170 | 7509 | return 133333; |
79e53945 JB |
7510 | } |
7511 | ||
1353c4fb | 7512 | static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) |
34edce2f | 7513 | { |
34edce2f VS |
7514 | static const unsigned int blb_vco[8] = { |
7515 | [0] = 3200000, | |
7516 | [1] = 4000000, | |
7517 | [2] = 5333333, | |
7518 | [3] = 4800000, | |
7519 | [4] = 6400000, | |
7520 | }; | |
7521 | static const unsigned int pnv_vco[8] = { | |
7522 | [0] = 3200000, | |
7523 | [1] = 4000000, | |
7524 | [2] = 5333333, | |
7525 | [3] = 4800000, | |
7526 | [4] = 2666667, | |
7527 | }; | |
7528 | static const unsigned int cl_vco[8] = { | |
7529 | [0] = 3200000, | |
7530 | [1] = 4000000, | |
7531 | [2] = 5333333, | |
7532 | [3] = 6400000, | |
7533 | [4] = 3333333, | |
7534 | [5] = 3566667, | |
7535 | [6] = 4266667, | |
7536 | }; | |
7537 | static const unsigned int elk_vco[8] = { | |
7538 | [0] = 3200000, | |
7539 | [1] = 4000000, | |
7540 | [2] = 5333333, | |
7541 | [3] = 4800000, | |
7542 | }; | |
7543 | static const unsigned int ctg_vco[8] = { | |
7544 | [0] = 3200000, | |
7545 | [1] = 4000000, | |
7546 | [2] = 5333333, | |
7547 | [3] = 6400000, | |
7548 | [4] = 2666667, | |
7549 | [5] = 4266667, | |
7550 | }; | |
7551 | const unsigned int *vco_table; | |
7552 | unsigned int vco; | |
7553 | uint8_t tmp = 0; | |
7554 | ||
7555 | /* FIXME other chipsets? */ | |
50a0bc90 | 7556 | if (IS_GM45(dev_priv)) |
34edce2f | 7557 | vco_table = ctg_vco; |
9beb5fea | 7558 | else if (IS_G4X(dev_priv)) |
34edce2f | 7559 | vco_table = elk_vco; |
c0f86832 | 7560 | else if (IS_I965GM(dev_priv)) |
34edce2f | 7561 | vco_table = cl_vco; |
1353c4fb | 7562 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f | 7563 | vco_table = pnv_vco; |
1353c4fb | 7564 | else if (IS_G33(dev_priv)) |
34edce2f VS |
7565 | vco_table = blb_vco; |
7566 | else | |
7567 | return 0; | |
7568 | ||
1353c4fb | 7569 | tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); |
34edce2f VS |
7570 | |
7571 | vco = vco_table[tmp & 0x7]; | |
7572 | if (vco == 0) | |
7573 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7574 | else | |
7575 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7576 | ||
7577 | return vco; | |
7578 | } | |
7579 | ||
1353c4fb | 7580 | static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7581 | { |
1353c4fb VS |
7582 | struct pci_dev *pdev = dev_priv->drm.pdev; |
7583 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); | |
34edce2f VS |
7584 | uint16_t tmp = 0; |
7585 | ||
52a05c30 | 7586 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7587 | |
7588 | cdclk_sel = (tmp >> 12) & 0x1; | |
7589 | ||
7590 | switch (vco) { | |
7591 | case 2666667: | |
7592 | case 4000000: | |
7593 | case 5333333: | |
7594 | return cdclk_sel ? 333333 : 222222; | |
7595 | case 3200000: | |
7596 | return cdclk_sel ? 320000 : 228571; | |
7597 | default: | |
7598 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7599 | return 222222; | |
7600 | } | |
7601 | } | |
7602 | ||
1353c4fb | 7603 | static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7604 | { |
1353c4fb | 7605 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34edce2f VS |
7606 | static const uint8_t div_3200[] = { 16, 10, 8 }; |
7607 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7608 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7609 | const uint8_t *div_table; | |
1353c4fb | 7610 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); |
34edce2f VS |
7611 | uint16_t tmp = 0; |
7612 | ||
52a05c30 | 7613 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7614 | |
7615 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7616 | ||
7617 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7618 | goto fail; | |
7619 | ||
7620 | switch (vco) { | |
7621 | case 3200000: | |
7622 | div_table = div_3200; | |
7623 | break; | |
7624 | case 4000000: | |
7625 | div_table = div_4000; | |
7626 | break; | |
7627 | case 5333333: | |
7628 | div_table = div_5333; | |
7629 | break; | |
7630 | default: | |
7631 | goto fail; | |
7632 | } | |
7633 | ||
7634 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7635 | ||
caf4e252 | 7636 | fail: |
34edce2f VS |
7637 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7638 | return 200000; | |
7639 | } | |
7640 | ||
1353c4fb | 7641 | static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7642 | { |
1353c4fb | 7643 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34edce2f VS |
7644 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; |
7645 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7646 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7647 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7648 | const uint8_t *div_table; | |
1353c4fb | 7649 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); |
34edce2f VS |
7650 | uint16_t tmp = 0; |
7651 | ||
52a05c30 | 7652 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7653 | |
7654 | cdclk_sel = (tmp >> 4) & 0x7; | |
7655 | ||
7656 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7657 | goto fail; | |
7658 | ||
7659 | switch (vco) { | |
7660 | case 3200000: | |
7661 | div_table = div_3200; | |
7662 | break; | |
7663 | case 4000000: | |
7664 | div_table = div_4000; | |
7665 | break; | |
7666 | case 4800000: | |
7667 | div_table = div_4800; | |
7668 | break; | |
7669 | case 5333333: | |
7670 | div_table = div_5333; | |
7671 | break; | |
7672 | default: | |
7673 | goto fail; | |
7674 | } | |
7675 | ||
7676 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7677 | ||
caf4e252 | 7678 | fail: |
34edce2f VS |
7679 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7680 | return 190476; | |
7681 | } | |
7682 | ||
2c07245f | 7683 | static void |
a65851af | 7684 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7685 | { |
a65851af VS |
7686 | while (*num > DATA_LINK_M_N_MASK || |
7687 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7688 | *num >>= 1; |
7689 | *den >>= 1; | |
7690 | } | |
7691 | } | |
7692 | ||
a65851af VS |
7693 | static void compute_m_n(unsigned int m, unsigned int n, |
7694 | uint32_t *ret_m, uint32_t *ret_n) | |
7695 | { | |
7696 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7697 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7698 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7699 | } | |
7700 | ||
e69d0bc1 DV |
7701 | void |
7702 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7703 | int pixel_clock, int link_clock, | |
7704 | struct intel_link_m_n *m_n) | |
2c07245f | 7705 | { |
e69d0bc1 | 7706 | m_n->tu = 64; |
a65851af VS |
7707 | |
7708 | compute_m_n(bits_per_pixel * pixel_clock, | |
7709 | link_clock * nlanes * 8, | |
7710 | &m_n->gmch_m, &m_n->gmch_n); | |
7711 | ||
7712 | compute_m_n(pixel_clock, link_clock, | |
7713 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7714 | } |
7715 | ||
a7615030 CW |
7716 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7717 | { | |
d330a953 JN |
7718 | if (i915.panel_use_ssc >= 0) |
7719 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7720 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7721 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7722 | } |
7723 | ||
7429e9d4 | 7724 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7725 | { |
7df00d7a | 7726 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7727 | } |
f47709a9 | 7728 | |
7429e9d4 DV |
7729 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7730 | { | |
7731 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7732 | } |
7733 | ||
f47709a9 | 7734 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7735 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7736 | struct dpll *reduced_clock) |
a7516a05 | 7737 | { |
9b1e14f4 | 7738 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
7739 | u32 fp, fp2 = 0; |
7740 | ||
9b1e14f4 | 7741 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 7742 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7743 | if (reduced_clock) |
7429e9d4 | 7744 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7745 | } else { |
190f68c5 | 7746 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7747 | if (reduced_clock) |
7429e9d4 | 7748 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7749 | } |
7750 | ||
190f68c5 | 7751 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7752 | |
f47709a9 | 7753 | crtc->lowfreq_avail = false; |
2d84d2b3 | 7754 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7755 | reduced_clock) { |
190f68c5 | 7756 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7757 | crtc->lowfreq_avail = true; |
a7516a05 | 7758 | } else { |
190f68c5 | 7759 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7760 | } |
7761 | } | |
7762 | ||
5e69f97f CML |
7763 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7764 | pipe) | |
89b667f8 JB |
7765 | { |
7766 | u32 reg_val; | |
7767 | ||
7768 | /* | |
7769 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7770 | * and set it to a reasonable value instead. | |
7771 | */ | |
ab3c759a | 7772 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7773 | reg_val &= 0xffffff00; |
7774 | reg_val |= 0x00000030; | |
ab3c759a | 7775 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7776 | |
ab3c759a | 7777 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7778 | reg_val &= 0x8cffffff; |
7779 | reg_val = 0x8c000000; | |
ab3c759a | 7780 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7781 | |
ab3c759a | 7782 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7783 | reg_val &= 0xffffff00; |
ab3c759a | 7784 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7785 | |
ab3c759a | 7786 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7787 | reg_val &= 0x00ffffff; |
7788 | reg_val |= 0xb0000000; | |
ab3c759a | 7789 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7790 | } |
7791 | ||
b551842d DV |
7792 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7793 | struct intel_link_m_n *m_n) | |
7794 | { | |
7795 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7796 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
7797 | int pipe = crtc->pipe; |
7798 | ||
e3b95f1e DV |
7799 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7800 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7801 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7802 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7803 | } |
7804 | ||
7805 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7806 | struct intel_link_m_n *m_n, |
7807 | struct intel_link_m_n *m2_n2) | |
b551842d | 7808 | { |
6315b5d3 | 7809 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 7810 | int pipe = crtc->pipe; |
6e3c9717 | 7811 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 7812 | |
6315b5d3 | 7813 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
7814 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7815 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7816 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7817 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7818 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7819 | * for gen < 8) and if DRRS is supported (to make sure the | |
7820 | * registers are not unnecessarily accessed). | |
7821 | */ | |
920a14b2 TU |
7822 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
7823 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
7824 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7825 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7826 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7827 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7828 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7829 | } | |
b551842d | 7830 | } else { |
e3b95f1e DV |
7831 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7832 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7833 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7834 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7835 | } |
7836 | } | |
7837 | ||
fe3cd48d | 7838 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7839 | { |
fe3cd48d R |
7840 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7841 | ||
7842 | if (m_n == M1_N1) { | |
7843 | dp_m_n = &crtc->config->dp_m_n; | |
7844 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7845 | } else if (m_n == M2_N2) { | |
7846 | ||
7847 | /* | |
7848 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7849 | * needs to be programmed into M1_N1. | |
7850 | */ | |
7851 | dp_m_n = &crtc->config->dp_m2_n2; | |
7852 | } else { | |
7853 | DRM_ERROR("Unsupported divider value\n"); | |
7854 | return; | |
7855 | } | |
7856 | ||
6e3c9717 ACO |
7857 | if (crtc->config->has_pch_encoder) |
7858 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7859 | else |
fe3cd48d | 7860 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7861 | } |
7862 | ||
251ac862 DV |
7863 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7864 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7865 | { |
03ed5cbf | 7866 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7867 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7868 | if (crtc->pipe != PIPE_A) |
7869 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7870 | |
cd2d34d9 | 7871 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7872 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7873 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7874 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7875 | ||
03ed5cbf VS |
7876 | pipe_config->dpll_hw_state.dpll_md = |
7877 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7878 | } | |
bdd4b6a6 | 7879 | |
03ed5cbf VS |
7880 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7881 | struct intel_crtc_state *pipe_config) | |
7882 | { | |
7883 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7884 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7885 | if (crtc->pipe != PIPE_A) |
7886 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7887 | ||
cd2d34d9 | 7888 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7889 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7890 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7891 | ||
03ed5cbf VS |
7892 | pipe_config->dpll_hw_state.dpll_md = |
7893 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7894 | } |
7895 | ||
d288f65f | 7896 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7897 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7898 | { |
f47709a9 | 7899 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7900 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7901 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7902 | u32 mdiv; |
a0c4da24 | 7903 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7904 | u32 coreclk, reg_val; |
a0c4da24 | 7905 | |
cd2d34d9 VS |
7906 | /* Enable Refclk */ |
7907 | I915_WRITE(DPLL(pipe), | |
7908 | pipe_config->dpll_hw_state.dpll & | |
7909 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7910 | ||
7911 | /* No need to actually set up the DPLL with DSI */ | |
7912 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7913 | return; | |
7914 | ||
a580516d | 7915 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7916 | |
d288f65f VS |
7917 | bestn = pipe_config->dpll.n; |
7918 | bestm1 = pipe_config->dpll.m1; | |
7919 | bestm2 = pipe_config->dpll.m2; | |
7920 | bestp1 = pipe_config->dpll.p1; | |
7921 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7922 | |
89b667f8 JB |
7923 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7924 | ||
7925 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7926 | if (pipe == PIPE_B) |
5e69f97f | 7927 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7928 | |
7929 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7930 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7931 | |
7932 | /* Disable target IRef on PLL */ | |
ab3c759a | 7933 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7934 | reg_val &= 0x00ffffff; |
ab3c759a | 7935 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7936 | |
7937 | /* Disable fast lock */ | |
ab3c759a | 7938 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7939 | |
7940 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7941 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7942 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7943 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7944 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7945 | |
7946 | /* | |
7947 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7948 | * but we don't support that). | |
7949 | * Note: don't use the DAC post divider as it seems unstable. | |
7950 | */ | |
7951 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7952 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7953 | |
a0c4da24 | 7954 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7955 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7956 | |
89b667f8 | 7957 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7958 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
7959 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
7960 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7961 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7962 | 0x009f0003); |
89b667f8 | 7963 | else |
ab3c759a | 7964 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7965 | 0x00d0000f); |
7966 | ||
37a5650b | 7967 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 7968 | /* Use SSC source */ |
bdd4b6a6 | 7969 | if (pipe == PIPE_A) |
ab3c759a | 7970 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7971 | 0x0df40000); |
7972 | else | |
ab3c759a | 7973 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7974 | 0x0df70000); |
7975 | } else { /* HDMI or VGA */ | |
7976 | /* Use bend source */ | |
bdd4b6a6 | 7977 | if (pipe == PIPE_A) |
ab3c759a | 7978 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7979 | 0x0df70000); |
7980 | else | |
ab3c759a | 7981 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7982 | 0x0df40000); |
7983 | } | |
a0c4da24 | 7984 | |
ab3c759a | 7985 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7986 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 7987 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 7988 | coreclk |= 0x01000000; |
ab3c759a | 7989 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7990 | |
ab3c759a | 7991 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7992 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7993 | } |
7994 | ||
d288f65f | 7995 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7996 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7997 | { |
7998 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7999 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 8000 | enum pipe pipe = crtc->pipe; |
9d556c99 | 8001 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 8002 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 8003 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 8004 | u32 dpio_val; |
9cbe40c1 | 8005 | int vco; |
9d556c99 | 8006 | |
cd2d34d9 VS |
8007 | /* Enable Refclk and SSC */ |
8008 | I915_WRITE(DPLL(pipe), | |
8009 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
8010 | ||
8011 | /* No need to actually set up the DPLL with DSI */ | |
8012 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8013 | return; | |
8014 | ||
d288f65f VS |
8015 | bestn = pipe_config->dpll.n; |
8016 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
8017 | bestm1 = pipe_config->dpll.m1; | |
8018 | bestm2 = pipe_config->dpll.m2 >> 22; | |
8019 | bestp1 = pipe_config->dpll.p1; | |
8020 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 8021 | vco = pipe_config->dpll.vco; |
a945ce7e | 8022 | dpio_val = 0; |
9cbe40c1 | 8023 | loopfilter = 0; |
9d556c99 | 8024 | |
a580516d | 8025 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 8026 | |
9d556c99 CML |
8027 | /* p1 and p2 divider */ |
8028 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
8029 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
8030 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
8031 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
8032 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
8033 | ||
8034 | /* Feedback post-divider - m2 */ | |
8035 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
8036 | ||
8037 | /* Feedback refclk divider - n and m1 */ | |
8038 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
8039 | DPIO_CHV_M1_DIV_BY_2 | | |
8040 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
8041 | ||
8042 | /* M2 fraction division */ | |
25a25dfc | 8043 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
8044 | |
8045 | /* M2 fraction division enable */ | |
a945ce7e VP |
8046 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
8047 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
8048 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
8049 | if (bestm2_frac) | |
8050 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
8051 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 8052 | |
de3a0fde VP |
8053 | /* Program digital lock detect threshold */ |
8054 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
8055 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
8056 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
8057 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
8058 | if (!bestm2_frac) | |
8059 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
8060 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
8061 | ||
9d556c99 | 8062 | /* Loop filter */ |
9cbe40c1 VP |
8063 | if (vco == 5400000) { |
8064 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8065 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
8066 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8067 | tribuf_calcntr = 0x9; | |
8068 | } else if (vco <= 6200000) { | |
8069 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8070 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
8071 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8072 | tribuf_calcntr = 0x9; | |
8073 | } else if (vco <= 6480000) { | |
8074 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8075 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8076 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8077 | tribuf_calcntr = 0x8; | |
8078 | } else { | |
8079 | /* Not supported. Apply the same limits as in the max case */ | |
8080 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8081 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8082 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8083 | tribuf_calcntr = 0; | |
8084 | } | |
9d556c99 CML |
8085 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
8086 | ||
968040b2 | 8087 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
8088 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
8089 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
8090 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
8091 | ||
9d556c99 CML |
8092 | /* AFC Recal */ |
8093 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
8094 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
8095 | DPIO_AFC_RECAL); | |
8096 | ||
a580516d | 8097 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
8098 | } |
8099 | ||
d288f65f VS |
8100 | /** |
8101 | * vlv_force_pll_on - forcibly enable just the PLL | |
8102 | * @dev_priv: i915 private structure | |
8103 | * @pipe: pipe PLL to enable | |
8104 | * @dpll: PLL configuration | |
8105 | * | |
8106 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
8107 | * in cases where we need the PLL enabled even when @pipe is not going to | |
8108 | * be enabled. | |
8109 | */ | |
30ad9814 | 8110 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 8111 | const struct dpll *dpll) |
d288f65f | 8112 | { |
b91eb5cc | 8113 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
8114 | struct intel_crtc_state *pipe_config; |
8115 | ||
8116 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
8117 | if (!pipe_config) | |
8118 | return -ENOMEM; | |
8119 | ||
8120 | pipe_config->base.crtc = &crtc->base; | |
8121 | pipe_config->pixel_multiplier = 1; | |
8122 | pipe_config->dpll = *dpll; | |
d288f65f | 8123 | |
30ad9814 | 8124 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
8125 | chv_compute_dpll(crtc, pipe_config); |
8126 | chv_prepare_pll(crtc, pipe_config); | |
8127 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 8128 | } else { |
3f36b937 TU |
8129 | vlv_compute_dpll(crtc, pipe_config); |
8130 | vlv_prepare_pll(crtc, pipe_config); | |
8131 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 8132 | } |
3f36b937 TU |
8133 | |
8134 | kfree(pipe_config); | |
8135 | ||
8136 | return 0; | |
d288f65f VS |
8137 | } |
8138 | ||
8139 | /** | |
8140 | * vlv_force_pll_off - forcibly disable just the PLL | |
8141 | * @dev_priv: i915 private structure | |
8142 | * @pipe: pipe PLL to disable | |
8143 | * | |
8144 | * Disable the PLL for @pipe. To be used in cases where we need | |
8145 | * the PLL enabled even when @pipe is not going to be enabled. | |
8146 | */ | |
30ad9814 | 8147 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 8148 | { |
30ad9814 VS |
8149 | if (IS_CHERRYVIEW(dev_priv)) |
8150 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 8151 | else |
30ad9814 | 8152 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
8153 | } |
8154 | ||
251ac862 DV |
8155 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
8156 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8157 | struct dpll *reduced_clock) |
eb1cbe48 | 8158 | { |
9b1e14f4 | 8159 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 8160 | u32 dpll; |
190f68c5 | 8161 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8162 | |
190f68c5 | 8163 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8164 | |
eb1cbe48 DV |
8165 | dpll = DPLL_VGA_MODE_DIS; |
8166 | ||
2d84d2b3 | 8167 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
8168 | dpll |= DPLLB_MODE_LVDS; |
8169 | else | |
8170 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 8171 | |
73f67aa8 JN |
8172 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
8173 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 8174 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 8175 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 8176 | } |
198a037f | 8177 | |
3d6e9ee0 VS |
8178 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8179 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8180 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 8181 | |
37a5650b | 8182 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8183 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
8184 | |
8185 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 8186 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
8187 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
8188 | else { | |
8189 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 8190 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
8191 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
8192 | } | |
8193 | switch (clock->p2) { | |
8194 | case 5: | |
8195 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8196 | break; | |
8197 | case 7: | |
8198 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8199 | break; | |
8200 | case 10: | |
8201 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8202 | break; | |
8203 | case 14: | |
8204 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8205 | break; | |
8206 | } | |
9b1e14f4 | 8207 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
8208 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
8209 | ||
190f68c5 | 8210 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 8211 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 8212 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8213 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8214 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8215 | else | |
8216 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8217 | ||
8218 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8219 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 8220 | |
9b1e14f4 | 8221 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 8222 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8223 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 8224 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
8225 | } |
8226 | } | |
8227 | ||
251ac862 DV |
8228 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
8229 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8230 | struct dpll *reduced_clock) |
eb1cbe48 | 8231 | { |
f47709a9 | 8232 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8233 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 8234 | u32 dpll; |
190f68c5 | 8235 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8236 | |
190f68c5 | 8237 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8238 | |
eb1cbe48 DV |
8239 | dpll = DPLL_VGA_MODE_DIS; |
8240 | ||
2d84d2b3 | 8241 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
8242 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
8243 | } else { | |
8244 | if (clock->p1 == 2) | |
8245 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
8246 | else | |
8247 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
8248 | if (clock->p2 == 4) | |
8249 | dpll |= PLL_P2_DIVIDE_BY_4; | |
8250 | } | |
8251 | ||
50a0bc90 TU |
8252 | if (!IS_I830(dev_priv) && |
8253 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
8254 | dpll |= DPLL_DVO_2X_MODE; |
8255 | ||
2d84d2b3 | 8256 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8257 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8258 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8259 | else | |
8260 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8261 | ||
8262 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8263 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
8264 | } |
8265 | ||
8a654f3b | 8266 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 8267 | { |
6315b5d3 | 8268 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 8269 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8270 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 8271 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
8272 | uint32_t crtc_vtotal, crtc_vblank_end; |
8273 | int vsyncshift = 0; | |
4d8a62ea DV |
8274 | |
8275 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
8276 | * the hw state checker will get angry at the mismatch. */ | |
8277 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
8278 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 8279 | |
609aeaca | 8280 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 8281 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
8282 | crtc_vtotal -= 1; |
8283 | crtc_vblank_end -= 1; | |
609aeaca | 8284 | |
2d84d2b3 | 8285 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
8286 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
8287 | else | |
8288 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
8289 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
8290 | if (vsyncshift < 0) |
8291 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
8292 | } |
8293 | ||
6315b5d3 | 8294 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 8295 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 8296 | |
fe2b8f9d | 8297 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
8298 | (adjusted_mode->crtc_hdisplay - 1) | |
8299 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 8300 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
8301 | (adjusted_mode->crtc_hblank_start - 1) | |
8302 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 8303 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
8304 | (adjusted_mode->crtc_hsync_start - 1) | |
8305 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
8306 | ||
fe2b8f9d | 8307 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 8308 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 8309 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 8310 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 8311 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 8312 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 8313 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
8314 | (adjusted_mode->crtc_vsync_start - 1) | |
8315 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
8316 | ||
b5e508d4 PZ |
8317 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
8318 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
8319 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
8320 | * bits. */ | |
772c2a51 | 8321 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
8322 | (pipe == PIPE_B || pipe == PIPE_C)) |
8323 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
8324 | ||
bc58be60 JN |
8325 | } |
8326 | ||
8327 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
8328 | { | |
8329 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8330 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
8331 | enum pipe pipe = intel_crtc->pipe; |
8332 | ||
b0e77b9c PZ |
8333 | /* pipesrc controls the size that is scaled from, which should |
8334 | * always be the user's requested size. | |
8335 | */ | |
8336 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
8337 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
8338 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
8339 | } |
8340 | ||
1bd1bd80 | 8341 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 8342 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
8343 | { |
8344 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8345 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
8346 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
8347 | uint32_t tmp; | |
8348 | ||
8349 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8350 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
8351 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8352 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
8353 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
8354 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8355 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
8356 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
8357 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8358 | |
8359 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8360 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
8361 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8362 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
8363 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
8364 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8365 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
8366 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
8367 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8368 | |
8369 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
8370 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
8371 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
8372 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 8373 | } |
bc58be60 JN |
8374 | } |
8375 | ||
8376 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
8377 | struct intel_crtc_state *pipe_config) | |
8378 | { | |
8379 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8380 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 8381 | u32 tmp; |
1bd1bd80 DV |
8382 | |
8383 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
8384 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
8385 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
8386 | ||
2d112de7 ACO |
8387 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
8388 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
8389 | } |
8390 | ||
f6a83288 | 8391 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 8392 | struct intel_crtc_state *pipe_config) |
babea61d | 8393 | { |
2d112de7 ACO |
8394 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
8395 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
8396 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
8397 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 8398 | |
2d112de7 ACO |
8399 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
8400 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
8401 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
8402 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 8403 | |
2d112de7 | 8404 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 8405 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 8406 | |
2d112de7 ACO |
8407 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
8408 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
8409 | |
8410 | mode->hsync = drm_mode_hsync(mode); | |
8411 | mode->vrefresh = drm_mode_vrefresh(mode); | |
8412 | drm_mode_set_name(mode); | |
babea61d JB |
8413 | } |
8414 | ||
84b046f3 DV |
8415 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
8416 | { | |
6315b5d3 | 8417 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
8418 | uint32_t pipeconf; |
8419 | ||
9f11a9e4 | 8420 | pipeconf = 0; |
84b046f3 | 8421 | |
b6b5d049 VS |
8422 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
8423 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8424 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 8425 | |
6e3c9717 | 8426 | if (intel_crtc->config->double_wide) |
cf532bb2 | 8427 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 8428 | |
ff9ce46e | 8429 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
8430 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
8431 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 8432 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 8433 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 8434 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 8435 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 8436 | |
6e3c9717 | 8437 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
8438 | case 18: |
8439 | pipeconf |= PIPECONF_6BPC; | |
8440 | break; | |
8441 | case 24: | |
8442 | pipeconf |= PIPECONF_8BPC; | |
8443 | break; | |
8444 | case 30: | |
8445 | pipeconf |= PIPECONF_10BPC; | |
8446 | break; | |
8447 | default: | |
8448 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
8449 | BUG(); | |
84b046f3 DV |
8450 | } |
8451 | } | |
8452 | ||
56b857a5 | 8453 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
8454 | if (intel_crtc->lowfreq_avail) { |
8455 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
8456 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
8457 | } else { | |
8458 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
8459 | } |
8460 | } | |
8461 | ||
6e3c9717 | 8462 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 8463 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 8464 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
8465 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
8466 | else | |
8467 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
8468 | } else | |
84b046f3 DV |
8469 | pipeconf |= PIPECONF_PROGRESSIVE; |
8470 | ||
920a14b2 | 8471 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 8472 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 8473 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 8474 | |
84b046f3 DV |
8475 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
8476 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
8477 | } | |
8478 | ||
81c97f52 ACO |
8479 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
8480 | struct intel_crtc_state *crtc_state) | |
8481 | { | |
8482 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8483 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8484 | const struct intel_limit *limit; |
81c97f52 ACO |
8485 | int refclk = 48000; |
8486 | ||
8487 | memset(&crtc_state->dpll_hw_state, 0, | |
8488 | sizeof(crtc_state->dpll_hw_state)); | |
8489 | ||
2d84d2b3 | 8490 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
8491 | if (intel_panel_use_ssc(dev_priv)) { |
8492 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8493 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8494 | } | |
8495 | ||
8496 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 8497 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
8498 | limit = &intel_limits_i8xx_dvo; |
8499 | } else { | |
8500 | limit = &intel_limits_i8xx_dac; | |
8501 | } | |
8502 | ||
8503 | if (!crtc_state->clock_set && | |
8504 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8505 | refclk, NULL, &crtc_state->dpll)) { | |
8506 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8507 | return -EINVAL; | |
8508 | } | |
8509 | ||
8510 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
8511 | ||
8512 | return 0; | |
8513 | } | |
8514 | ||
19ec6693 ACO |
8515 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
8516 | struct intel_crtc_state *crtc_state) | |
8517 | { | |
8518 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8519 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8520 | const struct intel_limit *limit; |
19ec6693 ACO |
8521 | int refclk = 96000; |
8522 | ||
8523 | memset(&crtc_state->dpll_hw_state, 0, | |
8524 | sizeof(crtc_state->dpll_hw_state)); | |
8525 | ||
2d84d2b3 | 8526 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
8527 | if (intel_panel_use_ssc(dev_priv)) { |
8528 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8529 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8530 | } | |
8531 | ||
8532 | if (intel_is_dual_link_lvds(dev)) | |
8533 | limit = &intel_limits_g4x_dual_channel_lvds; | |
8534 | else | |
8535 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
8536 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
8537 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 8538 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 8539 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
8540 | limit = &intel_limits_g4x_sdvo; |
8541 | } else { | |
8542 | /* The option is for other outputs */ | |
8543 | limit = &intel_limits_i9xx_sdvo; | |
8544 | } | |
8545 | ||
8546 | if (!crtc_state->clock_set && | |
8547 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8548 | refclk, NULL, &crtc_state->dpll)) { | |
8549 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8550 | return -EINVAL; | |
8551 | } | |
8552 | ||
8553 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8554 | ||
8555 | return 0; | |
8556 | } | |
8557 | ||
70e8aa21 ACO |
8558 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
8559 | struct intel_crtc_state *crtc_state) | |
8560 | { | |
8561 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8562 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8563 | const struct intel_limit *limit; |
70e8aa21 ACO |
8564 | int refclk = 96000; |
8565 | ||
8566 | memset(&crtc_state->dpll_hw_state, 0, | |
8567 | sizeof(crtc_state->dpll_hw_state)); | |
8568 | ||
2d84d2b3 | 8569 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8570 | if (intel_panel_use_ssc(dev_priv)) { |
8571 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8572 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8573 | } | |
8574 | ||
8575 | limit = &intel_limits_pineview_lvds; | |
8576 | } else { | |
8577 | limit = &intel_limits_pineview_sdvo; | |
8578 | } | |
8579 | ||
8580 | if (!crtc_state->clock_set && | |
8581 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8582 | refclk, NULL, &crtc_state->dpll)) { | |
8583 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8584 | return -EINVAL; | |
8585 | } | |
8586 | ||
8587 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8588 | ||
8589 | return 0; | |
8590 | } | |
8591 | ||
190f68c5 ACO |
8592 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8593 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8594 | { |
c7653199 | 8595 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8596 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8597 | const struct intel_limit *limit; |
81c97f52 | 8598 | int refclk = 96000; |
79e53945 | 8599 | |
dd3cd74a ACO |
8600 | memset(&crtc_state->dpll_hw_state, 0, |
8601 | sizeof(crtc_state->dpll_hw_state)); | |
8602 | ||
2d84d2b3 | 8603 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8604 | if (intel_panel_use_ssc(dev_priv)) { |
8605 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8606 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8607 | } | |
43565a06 | 8608 | |
70e8aa21 ACO |
8609 | limit = &intel_limits_i9xx_lvds; |
8610 | } else { | |
8611 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8612 | } |
79e53945 | 8613 | |
70e8aa21 ACO |
8614 | if (!crtc_state->clock_set && |
8615 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8616 | refclk, NULL, &crtc_state->dpll)) { | |
8617 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8618 | return -EINVAL; | |
f47709a9 | 8619 | } |
7026d4ac | 8620 | |
81c97f52 | 8621 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8622 | |
c8f7a0db | 8623 | return 0; |
f564048e EA |
8624 | } |
8625 | ||
65b3d6a9 ACO |
8626 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8627 | struct intel_crtc_state *crtc_state) | |
8628 | { | |
8629 | int refclk = 100000; | |
1b6f4958 | 8630 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8631 | |
8632 | memset(&crtc_state->dpll_hw_state, 0, | |
8633 | sizeof(crtc_state->dpll_hw_state)); | |
8634 | ||
65b3d6a9 ACO |
8635 | if (!crtc_state->clock_set && |
8636 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8637 | refclk, NULL, &crtc_state->dpll)) { | |
8638 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8639 | return -EINVAL; | |
8640 | } | |
8641 | ||
8642 | chv_compute_dpll(crtc, crtc_state); | |
8643 | ||
8644 | return 0; | |
8645 | } | |
8646 | ||
8647 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8648 | struct intel_crtc_state *crtc_state) | |
8649 | { | |
8650 | int refclk = 100000; | |
1b6f4958 | 8651 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8652 | |
8653 | memset(&crtc_state->dpll_hw_state, 0, | |
8654 | sizeof(crtc_state->dpll_hw_state)); | |
8655 | ||
65b3d6a9 ACO |
8656 | if (!crtc_state->clock_set && |
8657 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8658 | refclk, NULL, &crtc_state->dpll)) { | |
8659 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8660 | return -EINVAL; | |
8661 | } | |
8662 | ||
8663 | vlv_compute_dpll(crtc, crtc_state); | |
8664 | ||
8665 | return 0; | |
8666 | } | |
8667 | ||
2fa2fe9a | 8668 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8669 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 8670 | { |
6315b5d3 | 8671 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
8672 | uint32_t tmp; |
8673 | ||
50a0bc90 TU |
8674 | if (INTEL_GEN(dev_priv) <= 3 && |
8675 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
8676 | return; |
8677 | ||
2fa2fe9a | 8678 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8679 | if (!(tmp & PFIT_ENABLE)) |
8680 | return; | |
2fa2fe9a | 8681 | |
06922821 | 8682 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 8683 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
8684 | if (crtc->pipe != PIPE_B) |
8685 | return; | |
2fa2fe9a DV |
8686 | } else { |
8687 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8688 | return; | |
8689 | } | |
8690 | ||
06922821 | 8691 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8692 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8693 | } |
8694 | ||
acbec814 | 8695 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8696 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8697 | { |
8698 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8699 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 8700 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 8701 | struct dpll clock; |
acbec814 | 8702 | u32 mdiv; |
662c6ecb | 8703 | int refclk = 100000; |
acbec814 | 8704 | |
b521973b VS |
8705 | /* In case of DSI, DPLL will not be used */ |
8706 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8707 | return; |
8708 | ||
a580516d | 8709 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8710 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8711 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8712 | |
8713 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8714 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8715 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8716 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8717 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8718 | ||
dccbea3b | 8719 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8720 | } |
8721 | ||
5724dbd1 DL |
8722 | static void |
8723 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8724 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8725 | { |
8726 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8727 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
8728 | u32 val, base, offset; |
8729 | int pipe = crtc->pipe, plane = crtc->plane; | |
8730 | int fourcc, pixel_format; | |
6761dd31 | 8731 | unsigned int aligned_height; |
b113d5ee | 8732 | struct drm_framebuffer *fb; |
1b842c89 | 8733 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8734 | |
42a7b088 DL |
8735 | val = I915_READ(DSPCNTR(plane)); |
8736 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8737 | return; | |
8738 | ||
d9806c9f | 8739 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8740 | if (!intel_fb) { |
1ad292b5 JB |
8741 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8742 | return; | |
8743 | } | |
8744 | ||
1b842c89 DL |
8745 | fb = &intel_fb->base; |
8746 | ||
6315b5d3 | 8747 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8748 | if (val & DISPPLANE_TILED) { |
49af449b | 8749 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8750 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8751 | } |
8752 | } | |
1ad292b5 JB |
8753 | |
8754 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8755 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8756 | fb->pixel_format = fourcc; |
8757 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 | 8758 | |
6315b5d3 | 8759 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 8760 | if (plane_config->tiling) |
1ad292b5 JB |
8761 | offset = I915_READ(DSPTILEOFF(plane)); |
8762 | else | |
8763 | offset = I915_READ(DSPLINOFF(plane)); | |
8764 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8765 | } else { | |
8766 | base = I915_READ(DSPADDR(plane)); | |
8767 | } | |
8768 | plane_config->base = base; | |
8769 | ||
8770 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8771 | fb->width = ((val >> 16) & 0xfff) + 1; |
8772 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8773 | |
8774 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8775 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8776 | |
b113d5ee | 8777 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb | 8778 | fb->pixel_format, |
bae781b2 | 8779 | fb->modifier); |
1ad292b5 | 8780 | |
f37b5c2b | 8781 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8782 | |
2844a921 DL |
8783 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8784 | pipe_name(pipe), plane, fb->width, fb->height, | |
8785 | fb->bits_per_pixel, base, fb->pitches[0], | |
8786 | plane_config->size); | |
1ad292b5 | 8787 | |
2d14030b | 8788 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8789 | } |
8790 | ||
70b23a98 | 8791 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8792 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8793 | { |
8794 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8795 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
8796 | int pipe = pipe_config->cpu_transcoder; |
8797 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8798 | struct dpll clock; |
0d7b6b11 | 8799 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8800 | int refclk = 100000; |
8801 | ||
b521973b VS |
8802 | /* In case of DSI, DPLL will not be used */ |
8803 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8804 | return; | |
8805 | ||
a580516d | 8806 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8807 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8808 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8809 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8810 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8811 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8812 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8813 | |
8814 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8815 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8816 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8817 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8818 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8819 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8820 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8821 | ||
dccbea3b | 8822 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8823 | } |
8824 | ||
0e8ffe1b | 8825 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8826 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 8827 | { |
6315b5d3 | 8828 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 8829 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8830 | uint32_t tmp; |
1729050e | 8831 | bool ret; |
0e8ffe1b | 8832 | |
1729050e ID |
8833 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8834 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8835 | return false; |
8836 | ||
e143a21c | 8837 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8838 | pipe_config->shared_dpll = NULL; |
eccb140b | 8839 | |
1729050e ID |
8840 | ret = false; |
8841 | ||
0e8ffe1b DV |
8842 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8843 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8844 | goto out; |
0e8ffe1b | 8845 | |
9beb5fea TU |
8846 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
8847 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
8848 | switch (tmp & PIPECONF_BPC_MASK) { |
8849 | case PIPECONF_6BPC: | |
8850 | pipe_config->pipe_bpp = 18; | |
8851 | break; | |
8852 | case PIPECONF_8BPC: | |
8853 | pipe_config->pipe_bpp = 24; | |
8854 | break; | |
8855 | case PIPECONF_10BPC: | |
8856 | pipe_config->pipe_bpp = 30; | |
8857 | break; | |
8858 | default: | |
8859 | break; | |
8860 | } | |
8861 | } | |
8862 | ||
920a14b2 | 8863 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 8864 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
8865 | pipe_config->limited_color_range = true; |
8866 | ||
6315b5d3 | 8867 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
8868 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
8869 | ||
1bd1bd80 | 8870 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8871 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8872 | |
2fa2fe9a DV |
8873 | i9xx_get_pfit_config(crtc, pipe_config); |
8874 | ||
6315b5d3 | 8875 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 8876 | /* No way to read it out on pipes B and C */ |
920a14b2 | 8877 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
8878 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
8879 | else | |
8880 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8881 | pipe_config->pixel_multiplier = |
8882 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8883 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8884 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 8885 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 8886 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
8887 | tmp = I915_READ(DPLL(crtc->pipe)); |
8888 | pipe_config->pixel_multiplier = | |
8889 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8890 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8891 | } else { | |
8892 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8893 | * port and will be fixed up in the encoder->get_config | |
8894 | * function. */ | |
8895 | pipe_config->pixel_multiplier = 1; | |
8896 | } | |
8bcc2795 | 8897 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 8898 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
8899 | /* |
8900 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8901 | * on 830. Filter it out here so that we don't | |
8902 | * report errors due to that. | |
8903 | */ | |
50a0bc90 | 8904 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
8905 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
8906 | ||
8bcc2795 DV |
8907 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8908 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8909 | } else { |
8910 | /* Mask out read-only status bits. */ | |
8911 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8912 | DPLL_PORTC_READY_MASK | | |
8913 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8914 | } |
6c49f241 | 8915 | |
920a14b2 | 8916 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 8917 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 8918 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
8919 | vlv_crtc_clock_get(crtc, pipe_config); |
8920 | else | |
8921 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8922 | |
0f64614d VS |
8923 | /* |
8924 | * Normally the dotclock is filled in by the encoder .get_config() | |
8925 | * but in case the pipe is enabled w/o any ports we need a sane | |
8926 | * default. | |
8927 | */ | |
8928 | pipe_config->base.adjusted_mode.crtc_clock = | |
8929 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8930 | ||
1729050e ID |
8931 | ret = true; |
8932 | ||
8933 | out: | |
8934 | intel_display_power_put(dev_priv, power_domain); | |
8935 | ||
8936 | return ret; | |
0e8ffe1b DV |
8937 | } |
8938 | ||
c39055b0 | 8939 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 8940 | { |
13d83a67 | 8941 | struct intel_encoder *encoder; |
1c1a24d2 | 8942 | int i; |
74cfd7ac | 8943 | u32 val, final; |
13d83a67 | 8944 | bool has_lvds = false; |
199e5d79 | 8945 | bool has_cpu_edp = false; |
199e5d79 | 8946 | bool has_panel = false; |
99eb6a01 KP |
8947 | bool has_ck505 = false; |
8948 | bool can_ssc = false; | |
1c1a24d2 | 8949 | bool using_ssc_source = false; |
13d83a67 JB |
8950 | |
8951 | /* We need to take the global config into account */ | |
c39055b0 | 8952 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
8953 | switch (encoder->type) { |
8954 | case INTEL_OUTPUT_LVDS: | |
8955 | has_panel = true; | |
8956 | has_lvds = true; | |
8957 | break; | |
8958 | case INTEL_OUTPUT_EDP: | |
8959 | has_panel = true; | |
2de6905f | 8960 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8961 | has_cpu_edp = true; |
8962 | break; | |
6847d71b PZ |
8963 | default: |
8964 | break; | |
13d83a67 JB |
8965 | } |
8966 | } | |
8967 | ||
6e266956 | 8968 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 8969 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8970 | can_ssc = has_ck505; |
8971 | } else { | |
8972 | has_ck505 = false; | |
8973 | can_ssc = true; | |
8974 | } | |
8975 | ||
1c1a24d2 L |
8976 | /* Check if any DPLLs are using the SSC source */ |
8977 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8978 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8979 | ||
8980 | if (!(temp & DPLL_VCO_ENABLE)) | |
8981 | continue; | |
8982 | ||
8983 | if ((temp & PLL_REF_INPUT_MASK) == | |
8984 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8985 | using_ssc_source = true; | |
8986 | break; | |
8987 | } | |
8988 | } | |
8989 | ||
8990 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
8991 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
8992 | |
8993 | /* Ironlake: try to setup display ref clock before DPLL | |
8994 | * enabling. This is only under driver's control after | |
8995 | * PCH B stepping, previous chipset stepping should be | |
8996 | * ignoring this setting. | |
8997 | */ | |
74cfd7ac CW |
8998 | val = I915_READ(PCH_DREF_CONTROL); |
8999 | ||
9000 | /* As we must carefully and slowly disable/enable each source in turn, | |
9001 | * compute the final state we want first and check if we need to | |
9002 | * make any changes at all. | |
9003 | */ | |
9004 | final = val; | |
9005 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
9006 | if (has_ck505) | |
9007 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
9008 | else | |
9009 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
9010 | ||
8c07eb68 | 9011 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 9012 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 9013 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
9014 | |
9015 | if (has_panel) { | |
9016 | final |= DREF_SSC_SOURCE_ENABLE; | |
9017 | ||
9018 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9019 | final |= DREF_SSC1_ENABLE; | |
9020 | ||
9021 | if (has_cpu_edp) { | |
9022 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9023 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
9024 | else | |
9025 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
9026 | } else | |
9027 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
9028 | } else if (using_ssc_source) { |
9029 | final |= DREF_SSC_SOURCE_ENABLE; | |
9030 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
9031 | } |
9032 | ||
9033 | if (final == val) | |
9034 | return; | |
9035 | ||
13d83a67 | 9036 | /* Always enable nonspread source */ |
74cfd7ac | 9037 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 9038 | |
99eb6a01 | 9039 | if (has_ck505) |
74cfd7ac | 9040 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 9041 | else |
74cfd7ac | 9042 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 9043 | |
199e5d79 | 9044 | if (has_panel) { |
74cfd7ac CW |
9045 | val &= ~DREF_SSC_SOURCE_MASK; |
9046 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 9047 | |
199e5d79 | 9048 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 9049 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 9050 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 9051 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 9052 | } else |
74cfd7ac | 9053 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
9054 | |
9055 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 9056 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9057 | POSTING_READ(PCH_DREF_CONTROL); |
9058 | udelay(200); | |
9059 | ||
74cfd7ac | 9060 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
9061 | |
9062 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 9063 | if (has_cpu_edp) { |
99eb6a01 | 9064 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 9065 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 9066 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 9067 | } else |
74cfd7ac | 9068 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 9069 | } else |
74cfd7ac | 9070 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9071 | |
74cfd7ac | 9072 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9073 | POSTING_READ(PCH_DREF_CONTROL); |
9074 | udelay(200); | |
9075 | } else { | |
1c1a24d2 | 9076 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 9077 | |
74cfd7ac | 9078 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
9079 | |
9080 | /* Turn off CPU output */ | |
74cfd7ac | 9081 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9082 | |
74cfd7ac | 9083 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9084 | POSTING_READ(PCH_DREF_CONTROL); |
9085 | udelay(200); | |
9086 | ||
1c1a24d2 L |
9087 | if (!using_ssc_source) { |
9088 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 9089 | |
1c1a24d2 L |
9090 | /* Turn off the SSC source */ |
9091 | val &= ~DREF_SSC_SOURCE_MASK; | |
9092 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 9093 | |
1c1a24d2 L |
9094 | /* Turn off SSC1 */ |
9095 | val &= ~DREF_SSC1_ENABLE; | |
9096 | ||
9097 | I915_WRITE(PCH_DREF_CONTROL, val); | |
9098 | POSTING_READ(PCH_DREF_CONTROL); | |
9099 | udelay(200); | |
9100 | } | |
13d83a67 | 9101 | } |
74cfd7ac CW |
9102 | |
9103 | BUG_ON(val != final); | |
13d83a67 JB |
9104 | } |
9105 | ||
f31f2d55 | 9106 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 9107 | { |
f31f2d55 | 9108 | uint32_t tmp; |
dde86e2d | 9109 | |
0ff066a9 PZ |
9110 | tmp = I915_READ(SOUTH_CHICKEN2); |
9111 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
9112 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 9113 | |
cf3598c2 ID |
9114 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
9115 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 9116 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 9117 | |
0ff066a9 PZ |
9118 | tmp = I915_READ(SOUTH_CHICKEN2); |
9119 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
9120 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 9121 | |
cf3598c2 ID |
9122 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
9123 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 9124 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
9125 | } |
9126 | ||
9127 | /* WaMPhyProgramming:hsw */ | |
9128 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
9129 | { | |
9130 | uint32_t tmp; | |
dde86e2d PZ |
9131 | |
9132 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
9133 | tmp &= ~(0xFF << 24); | |
9134 | tmp |= (0x12 << 24); | |
9135 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
9136 | ||
dde86e2d PZ |
9137 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
9138 | tmp |= (1 << 11); | |
9139 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
9140 | ||
9141 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
9142 | tmp |= (1 << 11); | |
9143 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
9144 | ||
dde86e2d PZ |
9145 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
9146 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9147 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
9148 | ||
9149 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
9150 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9151 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
9152 | ||
0ff066a9 PZ |
9153 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
9154 | tmp &= ~(7 << 13); | |
9155 | tmp |= (5 << 13); | |
9156 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 9157 | |
0ff066a9 PZ |
9158 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
9159 | tmp &= ~(7 << 13); | |
9160 | tmp |= (5 << 13); | |
9161 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
9162 | |
9163 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
9164 | tmp &= ~0xFF; | |
9165 | tmp |= 0x1C; | |
9166 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
9167 | ||
9168 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
9169 | tmp &= ~0xFF; | |
9170 | tmp |= 0x1C; | |
9171 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
9172 | ||
9173 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
9174 | tmp &= ~(0xFF << 16); | |
9175 | tmp |= (0x1C << 16); | |
9176 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
9177 | ||
9178 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
9179 | tmp &= ~(0xFF << 16); | |
9180 | tmp |= (0x1C << 16); | |
9181 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
9182 | ||
0ff066a9 PZ |
9183 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
9184 | tmp |= (1 << 27); | |
9185 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 9186 | |
0ff066a9 PZ |
9187 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
9188 | tmp |= (1 << 27); | |
9189 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 9190 | |
0ff066a9 PZ |
9191 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
9192 | tmp &= ~(0xF << 28); | |
9193 | tmp |= (4 << 28); | |
9194 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 9195 | |
0ff066a9 PZ |
9196 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
9197 | tmp &= ~(0xF << 28); | |
9198 | tmp |= (4 << 28); | |
9199 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
9200 | } |
9201 | ||
2fa86a1f PZ |
9202 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
9203 | * Programming" based on the parameters passed: | |
9204 | * - Sequence to enable CLKOUT_DP | |
9205 | * - Sequence to enable CLKOUT_DP without spread | |
9206 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
9207 | */ | |
c39055b0 ACO |
9208 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
9209 | bool with_spread, bool with_fdi) | |
f31f2d55 | 9210 | { |
2fa86a1f PZ |
9211 | uint32_t reg, tmp; |
9212 | ||
9213 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
9214 | with_spread = true; | |
4f8036a2 TU |
9215 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
9216 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 9217 | with_fdi = false; |
f31f2d55 | 9218 | |
a580516d | 9219 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
9220 | |
9221 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9222 | tmp &= ~SBI_SSCCTL_DISABLE; | |
9223 | tmp |= SBI_SSCCTL_PATHALT; | |
9224 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9225 | ||
9226 | udelay(24); | |
9227 | ||
2fa86a1f PZ |
9228 | if (with_spread) { |
9229 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9230 | tmp &= ~SBI_SSCCTL_PATHALT; | |
9231 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 9232 | |
2fa86a1f PZ |
9233 | if (with_fdi) { |
9234 | lpt_reset_fdi_mphy(dev_priv); | |
9235 | lpt_program_fdi_mphy(dev_priv); | |
9236 | } | |
9237 | } | |
dde86e2d | 9238 | |
4f8036a2 | 9239 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
9240 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9241 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9242 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 9243 | |
a580516d | 9244 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
9245 | } |
9246 | ||
47701c3b | 9247 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 9248 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 9249 | { |
47701c3b PZ |
9250 | uint32_t reg, tmp; |
9251 | ||
a580516d | 9252 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 9253 | |
4f8036a2 | 9254 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
9255 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9256 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9257 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
9258 | ||
9259 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9260 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
9261 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
9262 | tmp |= SBI_SSCCTL_PATHALT; | |
9263 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9264 | udelay(32); | |
9265 | } | |
9266 | tmp |= SBI_SSCCTL_DISABLE; | |
9267 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9268 | } | |
9269 | ||
a580516d | 9270 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
9271 | } |
9272 | ||
f7be2c21 VS |
9273 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
9274 | ||
9275 | static const uint16_t sscdivintphase[] = { | |
9276 | [BEND_IDX( 50)] = 0x3B23, | |
9277 | [BEND_IDX( 45)] = 0x3B23, | |
9278 | [BEND_IDX( 40)] = 0x3C23, | |
9279 | [BEND_IDX( 35)] = 0x3C23, | |
9280 | [BEND_IDX( 30)] = 0x3D23, | |
9281 | [BEND_IDX( 25)] = 0x3D23, | |
9282 | [BEND_IDX( 20)] = 0x3E23, | |
9283 | [BEND_IDX( 15)] = 0x3E23, | |
9284 | [BEND_IDX( 10)] = 0x3F23, | |
9285 | [BEND_IDX( 5)] = 0x3F23, | |
9286 | [BEND_IDX( 0)] = 0x0025, | |
9287 | [BEND_IDX( -5)] = 0x0025, | |
9288 | [BEND_IDX(-10)] = 0x0125, | |
9289 | [BEND_IDX(-15)] = 0x0125, | |
9290 | [BEND_IDX(-20)] = 0x0225, | |
9291 | [BEND_IDX(-25)] = 0x0225, | |
9292 | [BEND_IDX(-30)] = 0x0325, | |
9293 | [BEND_IDX(-35)] = 0x0325, | |
9294 | [BEND_IDX(-40)] = 0x0425, | |
9295 | [BEND_IDX(-45)] = 0x0425, | |
9296 | [BEND_IDX(-50)] = 0x0525, | |
9297 | }; | |
9298 | ||
9299 | /* | |
9300 | * Bend CLKOUT_DP | |
9301 | * steps -50 to 50 inclusive, in steps of 5 | |
9302 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
9303 | * change in clock period = -(steps / 10) * 5.787 ps | |
9304 | */ | |
9305 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
9306 | { | |
9307 | uint32_t tmp; | |
9308 | int idx = BEND_IDX(steps); | |
9309 | ||
9310 | if (WARN_ON(steps % 5 != 0)) | |
9311 | return; | |
9312 | ||
9313 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
9314 | return; | |
9315 | ||
9316 | mutex_lock(&dev_priv->sb_lock); | |
9317 | ||
9318 | if (steps % 10 != 0) | |
9319 | tmp = 0xAAAAAAAB; | |
9320 | else | |
9321 | tmp = 0x00000000; | |
9322 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
9323 | ||
9324 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
9325 | tmp &= 0xffff0000; | |
9326 | tmp |= sscdivintphase[idx]; | |
9327 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
9328 | ||
9329 | mutex_unlock(&dev_priv->sb_lock); | |
9330 | } | |
9331 | ||
9332 | #undef BEND_IDX | |
9333 | ||
c39055b0 | 9334 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 9335 | { |
bf8fa3d3 PZ |
9336 | struct intel_encoder *encoder; |
9337 | bool has_vga = false; | |
9338 | ||
c39055b0 | 9339 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
9340 | switch (encoder->type) { |
9341 | case INTEL_OUTPUT_ANALOG: | |
9342 | has_vga = true; | |
9343 | break; | |
6847d71b PZ |
9344 | default: |
9345 | break; | |
bf8fa3d3 PZ |
9346 | } |
9347 | } | |
9348 | ||
f7be2c21 | 9349 | if (has_vga) { |
c39055b0 ACO |
9350 | lpt_bend_clkout_dp(dev_priv, 0); |
9351 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 9352 | } else { |
c39055b0 | 9353 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 9354 | } |
bf8fa3d3 PZ |
9355 | } |
9356 | ||
dde86e2d PZ |
9357 | /* |
9358 | * Initialize reference clocks when the driver loads | |
9359 | */ | |
c39055b0 | 9360 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 9361 | { |
6e266956 | 9362 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 9363 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 9364 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 9365 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
9366 | } |
9367 | ||
6ff93609 | 9368 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 9369 | { |
fac5e23e | 9370 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
9371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9372 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
9373 | uint32_t val; |
9374 | ||
78114071 | 9375 | val = 0; |
c8203565 | 9376 | |
6e3c9717 | 9377 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 9378 | case 18: |
dfd07d72 | 9379 | val |= PIPECONF_6BPC; |
c8203565 PZ |
9380 | break; |
9381 | case 24: | |
dfd07d72 | 9382 | val |= PIPECONF_8BPC; |
c8203565 PZ |
9383 | break; |
9384 | case 30: | |
dfd07d72 | 9385 | val |= PIPECONF_10BPC; |
c8203565 PZ |
9386 | break; |
9387 | case 36: | |
dfd07d72 | 9388 | val |= PIPECONF_12BPC; |
c8203565 PZ |
9389 | break; |
9390 | default: | |
cc769b62 PZ |
9391 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
9392 | BUG(); | |
c8203565 PZ |
9393 | } |
9394 | ||
6e3c9717 | 9395 | if (intel_crtc->config->dither) |
c8203565 PZ |
9396 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9397 | ||
6e3c9717 | 9398 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
9399 | val |= PIPECONF_INTERLACED_ILK; |
9400 | else | |
9401 | val |= PIPECONF_PROGRESSIVE; | |
9402 | ||
6e3c9717 | 9403 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 9404 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 9405 | |
c8203565 PZ |
9406 | I915_WRITE(PIPECONF(pipe), val); |
9407 | POSTING_READ(PIPECONF(pipe)); | |
9408 | } | |
9409 | ||
6ff93609 | 9410 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 9411 | { |
fac5e23e | 9412 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 9413 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9414 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 9415 | u32 val = 0; |
ee2b0b38 | 9416 | |
391bf048 | 9417 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
9418 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9419 | ||
6e3c9717 | 9420 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
9421 | val |= PIPECONF_INTERLACED_ILK; |
9422 | else | |
9423 | val |= PIPECONF_PROGRESSIVE; | |
9424 | ||
702e7a56 PZ |
9425 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
9426 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
9427 | } |
9428 | ||
391bf048 JN |
9429 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
9430 | { | |
fac5e23e | 9431 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 9432 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 9433 | |
391bf048 JN |
9434 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
9435 | u32 val = 0; | |
756f85cf | 9436 | |
6e3c9717 | 9437 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
9438 | case 18: |
9439 | val |= PIPEMISC_DITHER_6_BPC; | |
9440 | break; | |
9441 | case 24: | |
9442 | val |= PIPEMISC_DITHER_8_BPC; | |
9443 | break; | |
9444 | case 30: | |
9445 | val |= PIPEMISC_DITHER_10_BPC; | |
9446 | break; | |
9447 | case 36: | |
9448 | val |= PIPEMISC_DITHER_12_BPC; | |
9449 | break; | |
9450 | default: | |
9451 | /* Case prevented by pipe_config_set_bpp. */ | |
9452 | BUG(); | |
9453 | } | |
9454 | ||
6e3c9717 | 9455 | if (intel_crtc->config->dither) |
756f85cf PZ |
9456 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
9457 | ||
391bf048 | 9458 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 9459 | } |
ee2b0b38 PZ |
9460 | } |
9461 | ||
d4b1931c PZ |
9462 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
9463 | { | |
9464 | /* | |
9465 | * Account for spread spectrum to avoid | |
9466 | * oversubscribing the link. Max center spread | |
9467 | * is 2.5%; use 5% for safety's sake. | |
9468 | */ | |
9469 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 9470 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
9471 | } |
9472 | ||
7429e9d4 | 9473 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 9474 | { |
7429e9d4 | 9475 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
9476 | } |
9477 | ||
b75ca6f6 ACO |
9478 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
9479 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 9480 | struct dpll *reduced_clock) |
79e53945 | 9481 | { |
de13a2e3 | 9482 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 9483 | struct drm_device *dev = crtc->dev; |
fac5e23e | 9484 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 9485 | u32 dpll, fp, fp2; |
3d6e9ee0 | 9486 | int factor; |
79e53945 | 9487 | |
c1858123 | 9488 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 9489 | factor = 21; |
3d6e9ee0 | 9490 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 9491 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 9492 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 9493 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 9494 | factor = 25; |
190f68c5 | 9495 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 9496 | factor = 20; |
c1858123 | 9497 | |
b75ca6f6 ACO |
9498 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
9499 | ||
190f68c5 | 9500 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
9501 | fp |= FP_CB_TUNE; |
9502 | ||
9503 | if (reduced_clock) { | |
9504 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 9505 | |
b75ca6f6 ACO |
9506 | if (reduced_clock->m < factor * reduced_clock->n) |
9507 | fp2 |= FP_CB_TUNE; | |
9508 | } else { | |
9509 | fp2 = fp; | |
9510 | } | |
9a7c7890 | 9511 | |
5eddb70b | 9512 | dpll = 0; |
2c07245f | 9513 | |
3d6e9ee0 | 9514 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
9515 | dpll |= DPLLB_MODE_LVDS; |
9516 | else | |
9517 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9518 | |
190f68c5 | 9519 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9520 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 9521 | |
3d6e9ee0 VS |
9522 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
9523 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 9524 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 9525 | |
37a5650b | 9526 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 9527 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9528 | |
7d7f8633 VS |
9529 | /* |
9530 | * The high speed IO clock is only really required for | |
9531 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
9532 | * possible to share the DPLL between CRT and HDMI. Enabling | |
9533 | * the clock needlessly does no real harm, except use up a | |
9534 | * bit of power potentially. | |
9535 | * | |
9536 | * We'll limit this to IVB with 3 pipes, since it has only two | |
9537 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
9538 | * driving PCH ports at the same time. On SNB we could do this, | |
9539 | * and potentially avoid enabling the second DPLL, but it's not | |
9540 | * clear if it''s a win or loss power wise. No point in doing | |
9541 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
9542 | */ | |
9543 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
9544 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
9545 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
9546 | ||
a07d6787 | 9547 | /* compute bitmask from p1 value */ |
190f68c5 | 9548 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9549 | /* also FPA1 */ |
190f68c5 | 9550 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9551 | |
190f68c5 | 9552 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9553 | case 5: |
9554 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9555 | break; | |
9556 | case 7: | |
9557 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9558 | break; | |
9559 | case 10: | |
9560 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9561 | break; | |
9562 | case 14: | |
9563 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9564 | break; | |
79e53945 JB |
9565 | } |
9566 | ||
3d6e9ee0 VS |
9567 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
9568 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 9569 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9570 | else |
9571 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9572 | ||
b75ca6f6 ACO |
9573 | dpll |= DPLL_VCO_ENABLE; |
9574 | ||
9575 | crtc_state->dpll_hw_state.dpll = dpll; | |
9576 | crtc_state->dpll_hw_state.fp0 = fp; | |
9577 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
9578 | } |
9579 | ||
190f68c5 ACO |
9580 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9581 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9582 | { |
997c030c | 9583 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9584 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 9585 | struct dpll reduced_clock; |
7ed9f894 | 9586 | bool has_reduced_clock = false; |
e2b78267 | 9587 | struct intel_shared_dpll *pll; |
1b6f4958 | 9588 | const struct intel_limit *limit; |
997c030c | 9589 | int refclk = 120000; |
de13a2e3 | 9590 | |
dd3cd74a ACO |
9591 | memset(&crtc_state->dpll_hw_state, 0, |
9592 | sizeof(crtc_state->dpll_hw_state)); | |
9593 | ||
ded220e2 ACO |
9594 | crtc->lowfreq_avail = false; |
9595 | ||
9596 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
9597 | if (!crtc_state->has_pch_encoder) | |
9598 | return 0; | |
79e53945 | 9599 | |
2d84d2b3 | 9600 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
9601 | if (intel_panel_use_ssc(dev_priv)) { |
9602 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
9603 | dev_priv->vbt.lvds_ssc_freq); | |
9604 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
9605 | } | |
9606 | ||
9607 | if (intel_is_dual_link_lvds(dev)) { | |
9608 | if (refclk == 100000) | |
9609 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
9610 | else | |
9611 | limit = &intel_limits_ironlake_dual_lvds; | |
9612 | } else { | |
9613 | if (refclk == 100000) | |
9614 | limit = &intel_limits_ironlake_single_lvds_100m; | |
9615 | else | |
9616 | limit = &intel_limits_ironlake_single_lvds; | |
9617 | } | |
9618 | } else { | |
9619 | limit = &intel_limits_ironlake_dac; | |
9620 | } | |
9621 | ||
364ee29d | 9622 | if (!crtc_state->clock_set && |
997c030c ACO |
9623 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9624 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9625 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9626 | return -EINVAL; | |
f47709a9 | 9627 | } |
79e53945 | 9628 | |
b75ca6f6 ACO |
9629 | ironlake_compute_dpll(crtc, crtc_state, |
9630 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9631 | |
ded220e2 ACO |
9632 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9633 | if (pll == NULL) { | |
9634 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9635 | pipe_name(crtc->pipe)); | |
9636 | return -EINVAL; | |
3fb37703 | 9637 | } |
79e53945 | 9638 | |
2d84d2b3 | 9639 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 9640 | has_reduced_clock) |
c7653199 | 9641 | crtc->lowfreq_avail = true; |
e2b78267 | 9642 | |
c8f7a0db | 9643 | return 0; |
79e53945 JB |
9644 | } |
9645 | ||
eb14cb74 VS |
9646 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9647 | struct intel_link_m_n *m_n) | |
9648 | { | |
9649 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9650 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
9651 | enum pipe pipe = crtc->pipe; |
9652 | ||
9653 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9654 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9655 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9656 | & ~TU_SIZE_MASK; | |
9657 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9658 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9659 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9660 | } | |
9661 | ||
9662 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9663 | enum transcoder transcoder, | |
b95af8be VK |
9664 | struct intel_link_m_n *m_n, |
9665 | struct intel_link_m_n *m2_n2) | |
72419203 | 9666 | { |
6315b5d3 | 9667 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 9668 | enum pipe pipe = crtc->pipe; |
72419203 | 9669 | |
6315b5d3 | 9670 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
9671 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
9672 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9673 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9674 | & ~TU_SIZE_MASK; | |
9675 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9676 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9677 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9678 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9679 | * gen < 8) and if DRRS is supported (to make sure the | |
9680 | * registers are not unnecessarily read). | |
9681 | */ | |
6315b5d3 | 9682 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 9683 | crtc->config->has_drrs) { |
b95af8be VK |
9684 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9685 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9686 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9687 | & ~TU_SIZE_MASK; | |
9688 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9689 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9690 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9691 | } | |
eb14cb74 VS |
9692 | } else { |
9693 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9694 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9695 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9696 | & ~TU_SIZE_MASK; | |
9697 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9698 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9699 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9700 | } | |
9701 | } | |
9702 | ||
9703 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9704 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9705 | { |
681a8504 | 9706 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9707 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9708 | else | |
9709 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9710 | &pipe_config->dp_m_n, |
9711 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9712 | } |
72419203 | 9713 | |
eb14cb74 | 9714 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9715 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9716 | { |
9717 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9718 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9719 | } |
9720 | ||
bd2e244f | 9721 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9722 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9723 | { |
9724 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9725 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
9726 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9727 | uint32_t ps_ctrl = 0; | |
9728 | int id = -1; | |
9729 | int i; | |
bd2e244f | 9730 | |
a1b2278e CK |
9731 | /* find scaler attached to this pipe */ |
9732 | for (i = 0; i < crtc->num_scalers; i++) { | |
9733 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9734 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9735 | id = i; | |
9736 | pipe_config->pch_pfit.enabled = true; | |
9737 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9738 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9739 | break; | |
9740 | } | |
9741 | } | |
bd2e244f | 9742 | |
a1b2278e CK |
9743 | scaler_state->scaler_id = id; |
9744 | if (id >= 0) { | |
9745 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9746 | } else { | |
9747 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9748 | } |
9749 | } | |
9750 | ||
5724dbd1 DL |
9751 | static void |
9752 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9753 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9754 | { |
9755 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9756 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 9757 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9758 | int pipe = crtc->pipe; |
9759 | int fourcc, pixel_format; | |
6761dd31 | 9760 | unsigned int aligned_height; |
bc8d7dff | 9761 | struct drm_framebuffer *fb; |
1b842c89 | 9762 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9763 | |
d9806c9f | 9764 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9765 | if (!intel_fb) { |
bc8d7dff DL |
9766 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9767 | return; | |
9768 | } | |
9769 | ||
1b842c89 DL |
9770 | fb = &intel_fb->base; |
9771 | ||
bc8d7dff | 9772 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9773 | if (!(val & PLANE_CTL_ENABLE)) |
9774 | goto error; | |
9775 | ||
bc8d7dff DL |
9776 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9777 | fourcc = skl_format_to_fourcc(pixel_format, | |
9778 | val & PLANE_CTL_ORDER_RGBX, | |
9779 | val & PLANE_CTL_ALPHA_MASK); | |
9780 | fb->pixel_format = fourcc; | |
9781 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9782 | ||
40f46283 DL |
9783 | tiling = val & PLANE_CTL_TILED_MASK; |
9784 | switch (tiling) { | |
9785 | case PLANE_CTL_TILED_LINEAR: | |
bae781b2 | 9786 | fb->modifier = DRM_FORMAT_MOD_NONE; |
40f46283 DL |
9787 | break; |
9788 | case PLANE_CTL_TILED_X: | |
9789 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 9790 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
9791 | break; |
9792 | case PLANE_CTL_TILED_Y: | |
bae781b2 | 9793 | fb->modifier = I915_FORMAT_MOD_Y_TILED; |
40f46283 DL |
9794 | break; |
9795 | case PLANE_CTL_TILED_YF: | |
bae781b2 | 9796 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; |
40f46283 DL |
9797 | break; |
9798 | default: | |
9799 | MISSING_CASE(tiling); | |
9800 | goto error; | |
9801 | } | |
9802 | ||
bc8d7dff DL |
9803 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9804 | plane_config->base = base; | |
9805 | ||
9806 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9807 | ||
9808 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9809 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9810 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9811 | ||
9812 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
bae781b2 | 9813 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier, |
40f46283 | 9814 | fb->pixel_format); |
bc8d7dff DL |
9815 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9816 | ||
9817 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb | 9818 | fb->pixel_format, |
bae781b2 | 9819 | fb->modifier); |
bc8d7dff | 9820 | |
f37b5c2b | 9821 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9822 | |
9823 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9824 | pipe_name(pipe), fb->width, fb->height, | |
9825 | fb->bits_per_pixel, base, fb->pitches[0], | |
9826 | plane_config->size); | |
9827 | ||
2d14030b | 9828 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9829 | return; |
9830 | ||
9831 | error: | |
d1a3a036 | 9832 | kfree(intel_fb); |
bc8d7dff DL |
9833 | } |
9834 | ||
2fa2fe9a | 9835 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9836 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9837 | { |
9838 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9839 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
9840 | uint32_t tmp; |
9841 | ||
9842 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9843 | ||
9844 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9845 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9846 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9847 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9848 | |
9849 | /* We currently do not free assignements of panel fitters on | |
9850 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9851 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 9852 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
9853 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
9854 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9855 | } | |
2fa2fe9a | 9856 | } |
79e53945 JB |
9857 | } |
9858 | ||
5724dbd1 DL |
9859 | static void |
9860 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9861 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9862 | { |
9863 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9864 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 9865 | u32 val, base, offset; |
aeee5a49 | 9866 | int pipe = crtc->pipe; |
4c6baa59 | 9867 | int fourcc, pixel_format; |
6761dd31 | 9868 | unsigned int aligned_height; |
b113d5ee | 9869 | struct drm_framebuffer *fb; |
1b842c89 | 9870 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9871 | |
42a7b088 DL |
9872 | val = I915_READ(DSPCNTR(pipe)); |
9873 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9874 | return; | |
9875 | ||
d9806c9f | 9876 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9877 | if (!intel_fb) { |
4c6baa59 JB |
9878 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9879 | return; | |
9880 | } | |
9881 | ||
1b842c89 DL |
9882 | fb = &intel_fb->base; |
9883 | ||
6315b5d3 | 9884 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 9885 | if (val & DISPPLANE_TILED) { |
49af449b | 9886 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 9887 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
9888 | } |
9889 | } | |
4c6baa59 JB |
9890 | |
9891 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9892 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9893 | fb->pixel_format = fourcc; |
9894 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9895 | |
aeee5a49 | 9896 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 9897 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 9898 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9899 | } else { |
49af449b | 9900 | if (plane_config->tiling) |
aeee5a49 | 9901 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9902 | else |
aeee5a49 | 9903 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9904 | } |
9905 | plane_config->base = base; | |
9906 | ||
9907 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9908 | fb->width = ((val >> 16) & 0xfff) + 1; |
9909 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9910 | |
9911 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9912 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9913 | |
b113d5ee | 9914 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb | 9915 | fb->pixel_format, |
bae781b2 | 9916 | fb->modifier); |
4c6baa59 | 9917 | |
f37b5c2b | 9918 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9919 | |
2844a921 DL |
9920 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9921 | pipe_name(pipe), fb->width, fb->height, | |
9922 | fb->bits_per_pixel, base, fb->pitches[0], | |
9923 | plane_config->size); | |
b113d5ee | 9924 | |
2d14030b | 9925 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9926 | } |
9927 | ||
0e8ffe1b | 9928 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9929 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9930 | { |
9931 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9932 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 9933 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9934 | uint32_t tmp; |
1729050e | 9935 | bool ret; |
0e8ffe1b | 9936 | |
1729050e ID |
9937 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9938 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9939 | return false; |
9940 | ||
e143a21c | 9941 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9942 | pipe_config->shared_dpll = NULL; |
eccb140b | 9943 | |
1729050e | 9944 | ret = false; |
0e8ffe1b DV |
9945 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9946 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9947 | goto out; |
0e8ffe1b | 9948 | |
42571aef VS |
9949 | switch (tmp & PIPECONF_BPC_MASK) { |
9950 | case PIPECONF_6BPC: | |
9951 | pipe_config->pipe_bpp = 18; | |
9952 | break; | |
9953 | case PIPECONF_8BPC: | |
9954 | pipe_config->pipe_bpp = 24; | |
9955 | break; | |
9956 | case PIPECONF_10BPC: | |
9957 | pipe_config->pipe_bpp = 30; | |
9958 | break; | |
9959 | case PIPECONF_12BPC: | |
9960 | pipe_config->pipe_bpp = 36; | |
9961 | break; | |
9962 | default: | |
9963 | break; | |
9964 | } | |
9965 | ||
b5a9fa09 DV |
9966 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9967 | pipe_config->limited_color_range = true; | |
9968 | ||
ab9412ba | 9969 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9970 | struct intel_shared_dpll *pll; |
8106ddbd | 9971 | enum intel_dpll_id pll_id; |
66e985c0 | 9972 | |
88adfff1 DV |
9973 | pipe_config->has_pch_encoder = true; |
9974 | ||
627eb5a3 DV |
9975 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9976 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9977 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9978 | |
9979 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9980 | |
2d1fe073 | 9981 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9982 | /* |
9983 | * The pipe->pch transcoder and pch transcoder->pll | |
9984 | * mapping is fixed. | |
9985 | */ | |
8106ddbd | 9986 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9987 | } else { |
9988 | tmp = I915_READ(PCH_DPLL_SEL); | |
9989 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9990 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9991 | else |
8106ddbd | 9992 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9993 | } |
66e985c0 | 9994 | |
8106ddbd ACO |
9995 | pipe_config->shared_dpll = |
9996 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9997 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9998 | |
2edd6443 ACO |
9999 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10000 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
10001 | |
10002 | tmp = pipe_config->dpll_hw_state.dpll; | |
10003 | pipe_config->pixel_multiplier = | |
10004 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
10005 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
10006 | |
10007 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
10008 | } else { |
10009 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
10010 | } |
10011 | ||
1bd1bd80 | 10012 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 10013 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10014 | |
2fa2fe9a DV |
10015 | ironlake_get_pfit_config(crtc, pipe_config); |
10016 | ||
1729050e ID |
10017 | ret = true; |
10018 | ||
10019 | out: | |
10020 | intel_display_power_put(dev_priv, power_domain); | |
10021 | ||
10022 | return ret; | |
0e8ffe1b DV |
10023 | } |
10024 | ||
be256dc7 PZ |
10025 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
10026 | { | |
91c8a326 | 10027 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 10028 | struct intel_crtc *crtc; |
be256dc7 | 10029 | |
d3fcc808 | 10030 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 10031 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
10032 | pipe_name(crtc->pipe)); |
10033 | ||
e2c719b7 RC |
10034 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
10035 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
10036 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
10037 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 10038 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 10039 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 10040 | "CPU PWM1 enabled\n"); |
772c2a51 | 10041 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 10042 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 10043 | "CPU PWM2 enabled\n"); |
e2c719b7 | 10044 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 10045 | "PCH PWM1 enabled\n"); |
e2c719b7 | 10046 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 10047 | "Utility pin enabled\n"); |
e2c719b7 | 10048 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 10049 | |
9926ada1 PZ |
10050 | /* |
10051 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
10052 | * interrupts remain enabled. We used to check for that, but since it's | |
10053 | * gen-specific and since we only disable LCPLL after we fully disable | |
10054 | * the interrupts, the check below should be enough. | |
10055 | */ | |
e2c719b7 | 10056 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
10057 | } |
10058 | ||
9ccd5aeb PZ |
10059 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
10060 | { | |
772c2a51 | 10061 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
10062 | return I915_READ(D_COMP_HSW); |
10063 | else | |
10064 | return I915_READ(D_COMP_BDW); | |
10065 | } | |
10066 | ||
3c4c9b81 PZ |
10067 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
10068 | { | |
772c2a51 | 10069 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
10070 | mutex_lock(&dev_priv->rps.hw_lock); |
10071 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
10072 | val)) | |
79cf219a | 10073 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
10074 | mutex_unlock(&dev_priv->rps.hw_lock); |
10075 | } else { | |
9ccd5aeb PZ |
10076 | I915_WRITE(D_COMP_BDW, val); |
10077 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 10078 | } |
be256dc7 PZ |
10079 | } |
10080 | ||
10081 | /* | |
10082 | * This function implements pieces of two sequences from BSpec: | |
10083 | * - Sequence for display software to disable LCPLL | |
10084 | * - Sequence for display software to allow package C8+ | |
10085 | * The steps implemented here are just the steps that actually touch the LCPLL | |
10086 | * register. Callers should take care of disabling all the display engine | |
10087 | * functions, doing the mode unset, fixing interrupts, etc. | |
10088 | */ | |
6ff58d53 PZ |
10089 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
10090 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
10091 | { |
10092 | uint32_t val; | |
10093 | ||
10094 | assert_can_disable_lcpll(dev_priv); | |
10095 | ||
10096 | val = I915_READ(LCPLL_CTL); | |
10097 | ||
10098 | if (switch_to_fclk) { | |
10099 | val |= LCPLL_CD_SOURCE_FCLK; | |
10100 | I915_WRITE(LCPLL_CTL, val); | |
10101 | ||
f53dd63f ID |
10102 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
10103 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
10104 | DRM_ERROR("Switching to FCLK failed\n"); |
10105 | ||
10106 | val = I915_READ(LCPLL_CTL); | |
10107 | } | |
10108 | ||
10109 | val |= LCPLL_PLL_DISABLE; | |
10110 | I915_WRITE(LCPLL_CTL, val); | |
10111 | POSTING_READ(LCPLL_CTL); | |
10112 | ||
24d8441d | 10113 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
10114 | DRM_ERROR("LCPLL still locked\n"); |
10115 | ||
9ccd5aeb | 10116 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 10117 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 10118 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
10119 | ndelay(100); |
10120 | ||
9ccd5aeb PZ |
10121 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
10122 | 1)) | |
be256dc7 PZ |
10123 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
10124 | ||
10125 | if (allow_power_down) { | |
10126 | val = I915_READ(LCPLL_CTL); | |
10127 | val |= LCPLL_POWER_DOWN_ALLOW; | |
10128 | I915_WRITE(LCPLL_CTL, val); | |
10129 | POSTING_READ(LCPLL_CTL); | |
10130 | } | |
10131 | } | |
10132 | ||
10133 | /* | |
10134 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
10135 | * source. | |
10136 | */ | |
6ff58d53 | 10137 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
10138 | { |
10139 | uint32_t val; | |
10140 | ||
10141 | val = I915_READ(LCPLL_CTL); | |
10142 | ||
10143 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
10144 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
10145 | return; | |
10146 | ||
a8a8bd54 PZ |
10147 | /* |
10148 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
10149 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 10150 | */ |
59bad947 | 10151 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 10152 | |
be256dc7 PZ |
10153 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
10154 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
10155 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 10156 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
10157 | } |
10158 | ||
9ccd5aeb | 10159 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
10160 | val |= D_COMP_COMP_FORCE; |
10161 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 10162 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
10163 | |
10164 | val = I915_READ(LCPLL_CTL); | |
10165 | val &= ~LCPLL_PLL_DISABLE; | |
10166 | I915_WRITE(LCPLL_CTL, val); | |
10167 | ||
93220c08 CW |
10168 | if (intel_wait_for_register(dev_priv, |
10169 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
10170 | 5)) | |
be256dc7 PZ |
10171 | DRM_ERROR("LCPLL not locked yet\n"); |
10172 | ||
10173 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
10174 | val = I915_READ(LCPLL_CTL); | |
10175 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10176 | I915_WRITE(LCPLL_CTL, val); | |
10177 | ||
f53dd63f ID |
10178 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10179 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
10180 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10181 | } | |
215733fa | 10182 | |
59bad947 | 10183 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 10184 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
10185 | } |
10186 | ||
765dab67 PZ |
10187 | /* |
10188 | * Package states C8 and deeper are really deep PC states that can only be | |
10189 | * reached when all the devices on the system allow it, so even if the graphics | |
10190 | * device allows PC8+, it doesn't mean the system will actually get to these | |
10191 | * states. Our driver only allows PC8+ when going into runtime PM. | |
10192 | * | |
10193 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
10194 | * well is disabled and most interrupts are disabled, and these are also | |
10195 | * requirements for runtime PM. When these conditions are met, we manually do | |
10196 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
10197 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
10198 | * hang the machine. | |
10199 | * | |
10200 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
10201 | * the state of some registers, so when we come back from PC8+ we need to | |
10202 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
10203 | * need to take care of the registers kept by RC6. Notice that this happens even | |
10204 | * if we don't put the device in PCI D3 state (which is what currently happens | |
10205 | * because of the runtime PM support). | |
10206 | * | |
10207 | * For more, read "Display Sequences for Package C8" on the hardware | |
10208 | * documentation. | |
10209 | */ | |
a14cb6fc | 10210 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10211 | { |
c67a470b PZ |
10212 | uint32_t val; |
10213 | ||
c67a470b PZ |
10214 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
10215 | ||
4f8036a2 | 10216 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
10217 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10218 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
10219 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10220 | } | |
10221 | ||
c39055b0 | 10222 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
10223 | hsw_disable_lcpll(dev_priv, true, true); |
10224 | } | |
10225 | ||
a14cb6fc | 10226 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10227 | { |
c67a470b PZ |
10228 | uint32_t val; |
10229 | ||
c67a470b PZ |
10230 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
10231 | ||
10232 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 10233 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 10234 | |
4f8036a2 | 10235 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
10236 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10237 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
10238 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10239 | } | |
c67a470b PZ |
10240 | } |
10241 | ||
324513c0 | 10242 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 10243 | { |
a821fc46 | 10244 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10245 | struct intel_atomic_state *old_intel_state = |
10246 | to_intel_atomic_state(old_state); | |
10247 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 10248 | |
324513c0 | 10249 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
10250 | } |
10251 | ||
b30ce9e0 DP |
10252 | static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, |
10253 | int pixel_rate) | |
10254 | { | |
9c754024 DP |
10255 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
10256 | ||
b30ce9e0 | 10257 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
9c754024 | 10258 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b30ce9e0 DP |
10259 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
10260 | ||
10261 | /* BSpec says "Do not use DisplayPort with CDCLK less than | |
10262 | * 432 MHz, audio enabled, port width x4, and link rate | |
10263 | * HBR2 (5.4 GHz), or else there may be audio corruption or | |
10264 | * screen corruption." | |
10265 | */ | |
10266 | if (intel_crtc_has_dp_encoder(crtc_state) && | |
10267 | crtc_state->has_audio && | |
10268 | crtc_state->port_clock >= 540000 && | |
10269 | crtc_state->lane_count == 4) | |
10270 | pixel_rate = max(432000, pixel_rate); | |
10271 | ||
10272 | return pixel_rate; | |
10273 | } | |
10274 | ||
b432e5cf | 10275 | /* compute the max rate for new configuration */ |
27c329ed | 10276 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 10277 | { |
565602d7 | 10278 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 10279 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
10280 | struct drm_crtc *crtc; |
10281 | struct drm_crtc_state *cstate; | |
27c329ed | 10282 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
10283 | unsigned max_pixel_rate = 0, i; |
10284 | enum pipe pipe; | |
b432e5cf | 10285 | |
565602d7 ML |
10286 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
10287 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 10288 | |
565602d7 ML |
10289 | for_each_crtc_in_state(state, crtc, cstate, i) { |
10290 | int pixel_rate; | |
27c329ed | 10291 | |
565602d7 ML |
10292 | crtc_state = to_intel_crtc_state(cstate); |
10293 | if (!crtc_state->base.enable) { | |
10294 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 10295 | continue; |
565602d7 | 10296 | } |
b432e5cf | 10297 | |
27c329ed | 10298 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf | 10299 | |
9c754024 | 10300 | if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) |
b30ce9e0 DP |
10301 | pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, |
10302 | pixel_rate); | |
b432e5cf | 10303 | |
565602d7 | 10304 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
10305 | } |
10306 | ||
565602d7 ML |
10307 | for_each_pipe(dev_priv, pipe) |
10308 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
10309 | ||
b432e5cf VS |
10310 | return max_pixel_rate; |
10311 | } | |
10312 | ||
10313 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
10314 | { | |
fac5e23e | 10315 | struct drm_i915_private *dev_priv = to_i915(dev); |
b432e5cf VS |
10316 | uint32_t val, data; |
10317 | int ret; | |
10318 | ||
10319 | if (WARN((I915_READ(LCPLL_CTL) & | |
10320 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
10321 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
10322 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
10323 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
10324 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
10325 | return; | |
10326 | ||
10327 | mutex_lock(&dev_priv->rps.hw_lock); | |
10328 | ret = sandybridge_pcode_write(dev_priv, | |
10329 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
10330 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10331 | if (ret) { | |
10332 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
10333 | return; | |
10334 | } | |
10335 | ||
10336 | val = I915_READ(LCPLL_CTL); | |
10337 | val |= LCPLL_CD_SOURCE_FCLK; | |
10338 | I915_WRITE(LCPLL_CTL, val); | |
10339 | ||
5ba00178 TU |
10340 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
10341 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
10342 | DRM_ERROR("Switching to FCLK failed\n"); |
10343 | ||
10344 | val = I915_READ(LCPLL_CTL); | |
10345 | val &= ~LCPLL_CLK_FREQ_MASK; | |
10346 | ||
10347 | switch (cdclk) { | |
10348 | case 450000: | |
10349 | val |= LCPLL_CLK_FREQ_450; | |
10350 | data = 0; | |
10351 | break; | |
10352 | case 540000: | |
10353 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
10354 | data = 1; | |
10355 | break; | |
10356 | case 337500: | |
10357 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
10358 | data = 2; | |
10359 | break; | |
10360 | case 675000: | |
10361 | val |= LCPLL_CLK_FREQ_675_BDW; | |
10362 | data = 3; | |
10363 | break; | |
10364 | default: | |
10365 | WARN(1, "invalid cdclk frequency\n"); | |
10366 | return; | |
10367 | } | |
10368 | ||
10369 | I915_WRITE(LCPLL_CTL, val); | |
10370 | ||
10371 | val = I915_READ(LCPLL_CTL); | |
10372 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10373 | I915_WRITE(LCPLL_CTL, val); | |
10374 | ||
5ba00178 TU |
10375 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10376 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
10377 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10378 | ||
10379 | mutex_lock(&dev_priv->rps.hw_lock); | |
10380 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
10381 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10382 | ||
7f1052a8 VS |
10383 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
10384 | ||
4c75b940 | 10385 | intel_update_cdclk(dev_priv); |
b432e5cf VS |
10386 | |
10387 | WARN(cdclk != dev_priv->cdclk_freq, | |
10388 | "cdclk requested %d kHz but got %d kHz\n", | |
10389 | cdclk, dev_priv->cdclk_freq); | |
10390 | } | |
10391 | ||
587c7914 VS |
10392 | static int broadwell_calc_cdclk(int max_pixclk) |
10393 | { | |
10394 | if (max_pixclk > 540000) | |
10395 | return 675000; | |
10396 | else if (max_pixclk > 450000) | |
10397 | return 540000; | |
10398 | else if (max_pixclk > 337500) | |
10399 | return 450000; | |
10400 | else | |
10401 | return 337500; | |
10402 | } | |
10403 | ||
27c329ed | 10404 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 10405 | { |
27c329ed | 10406 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 10407 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 10408 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
10409 | int cdclk; |
10410 | ||
10411 | /* | |
10412 | * FIXME should also account for plane ratio | |
10413 | * once 64bpp pixel formats are supported. | |
10414 | */ | |
587c7914 | 10415 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 10416 | |
b432e5cf | 10417 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
10418 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
10419 | cdclk, dev_priv->max_cdclk_freq); | |
10420 | return -EINVAL; | |
b432e5cf VS |
10421 | } |
10422 | ||
1a617b77 ML |
10423 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
10424 | if (!intel_state->active_crtcs) | |
587c7914 | 10425 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
10426 | |
10427 | return 0; | |
10428 | } | |
10429 | ||
27c329ed | 10430 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 10431 | { |
27c329ed | 10432 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10433 | struct intel_atomic_state *old_intel_state = |
10434 | to_intel_atomic_state(old_state); | |
10435 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 10436 | |
27c329ed | 10437 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
10438 | } |
10439 | ||
c89e39f3 CT |
10440 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
10441 | { | |
10442 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
10443 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
10444 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 10445 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
10446 | int cdclk; |
10447 | ||
10448 | /* | |
10449 | * FIXME should also account for plane ratio | |
10450 | * once 64bpp pixel formats are supported. | |
10451 | */ | |
a8ca4934 | 10452 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
10453 | |
10454 | /* | |
10455 | * FIXME move the cdclk caclulation to | |
10456 | * compute_config() so we can fail gracegully. | |
10457 | */ | |
10458 | if (cdclk > dev_priv->max_cdclk_freq) { | |
10459 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
10460 | cdclk, dev_priv->max_cdclk_freq); | |
10461 | cdclk = dev_priv->max_cdclk_freq; | |
10462 | } | |
10463 | ||
10464 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
10465 | if (!intel_state->active_crtcs) | |
a8ca4934 | 10466 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
10467 | |
10468 | return 0; | |
10469 | } | |
10470 | ||
10471 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
10472 | { | |
1cd593e0 VS |
10473 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
10474 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
10475 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
10476 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 10477 | |
1cd593e0 | 10478 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
10479 | } |
10480 | ||
190f68c5 ACO |
10481 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
10482 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 10483 | { |
d7edc4e5 | 10484 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
10485 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
10486 | return -EINVAL; | |
10487 | } | |
716c2e55 | 10488 | |
c7653199 | 10489 | crtc->lowfreq_avail = false; |
644cef34 | 10490 | |
c8f7a0db | 10491 | return 0; |
79e53945 JB |
10492 | } |
10493 | ||
3760b59c S |
10494 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
10495 | enum port port, | |
10496 | struct intel_crtc_state *pipe_config) | |
10497 | { | |
8106ddbd ACO |
10498 | enum intel_dpll_id id; |
10499 | ||
3760b59c S |
10500 | switch (port) { |
10501 | case PORT_A: | |
08250c4b | 10502 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
10503 | break; |
10504 | case PORT_B: | |
08250c4b | 10505 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
10506 | break; |
10507 | case PORT_C: | |
08250c4b | 10508 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
10509 | break; |
10510 | default: | |
10511 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 10512 | return; |
3760b59c | 10513 | } |
8106ddbd ACO |
10514 | |
10515 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
10516 | } |
10517 | ||
96b7dfb7 S |
10518 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
10519 | enum port port, | |
5cec258b | 10520 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 10521 | { |
8106ddbd | 10522 | enum intel_dpll_id id; |
a3c988ea | 10523 | u32 temp; |
96b7dfb7 S |
10524 | |
10525 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 10526 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 10527 | |
c856052a | 10528 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 10529 | return; |
8106ddbd ACO |
10530 | |
10531 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
10532 | } |
10533 | ||
7d2c8175 DL |
10534 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
10535 | enum port port, | |
5cec258b | 10536 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 10537 | { |
8106ddbd | 10538 | enum intel_dpll_id id; |
c856052a | 10539 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 10540 | |
c856052a | 10541 | switch (ddi_pll_sel) { |
7d2c8175 | 10542 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 10543 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
10544 | break; |
10545 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 10546 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 10547 | break; |
00490c22 | 10548 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 10549 | id = DPLL_ID_SPLL; |
79bd23da | 10550 | break; |
9d16da65 ACO |
10551 | case PORT_CLK_SEL_LCPLL_810: |
10552 | id = DPLL_ID_LCPLL_810; | |
10553 | break; | |
10554 | case PORT_CLK_SEL_LCPLL_1350: | |
10555 | id = DPLL_ID_LCPLL_1350; | |
10556 | break; | |
10557 | case PORT_CLK_SEL_LCPLL_2700: | |
10558 | id = DPLL_ID_LCPLL_2700; | |
10559 | break; | |
8106ddbd | 10560 | default: |
c856052a | 10561 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
10562 | /* fall through */ |
10563 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 10564 | return; |
7d2c8175 | 10565 | } |
8106ddbd ACO |
10566 | |
10567 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
10568 | } |
10569 | ||
cf30429e JN |
10570 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
10571 | struct intel_crtc_state *pipe_config, | |
10572 | unsigned long *power_domain_mask) | |
10573 | { | |
10574 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10575 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
10576 | enum intel_display_power_domain power_domain; |
10577 | u32 tmp; | |
10578 | ||
d9a7bc67 ID |
10579 | /* |
10580 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
10581 | * transcoder handled below. | |
10582 | */ | |
cf30429e JN |
10583 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
10584 | ||
10585 | /* | |
10586 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
10587 | * consistency and less surprising code; it's in always on power). | |
10588 | */ | |
10589 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
10590 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10591 | enum pipe trans_edp_pipe; | |
10592 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10593 | default: | |
10594 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10595 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10596 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10597 | trans_edp_pipe = PIPE_A; | |
10598 | break; | |
10599 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10600 | trans_edp_pipe = PIPE_B; | |
10601 | break; | |
10602 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10603 | trans_edp_pipe = PIPE_C; | |
10604 | break; | |
10605 | } | |
10606 | ||
10607 | if (trans_edp_pipe == crtc->pipe) | |
10608 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10609 | } | |
10610 | ||
10611 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
10612 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10613 | return false; | |
10614 | *power_domain_mask |= BIT(power_domain); | |
10615 | ||
10616 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
10617 | ||
10618 | return tmp & PIPECONF_ENABLE; | |
10619 | } | |
10620 | ||
4d1de975 JN |
10621 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10622 | struct intel_crtc_state *pipe_config, | |
10623 | unsigned long *power_domain_mask) | |
10624 | { | |
10625 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10626 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
10627 | enum intel_display_power_domain power_domain; |
10628 | enum port port; | |
10629 | enum transcoder cpu_transcoder; | |
10630 | u32 tmp; | |
10631 | ||
4d1de975 JN |
10632 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
10633 | if (port == PORT_A) | |
10634 | cpu_transcoder = TRANSCODER_DSI_A; | |
10635 | else | |
10636 | cpu_transcoder = TRANSCODER_DSI_C; | |
10637 | ||
10638 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10639 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10640 | continue; | |
10641 | *power_domain_mask |= BIT(power_domain); | |
10642 | ||
db18b6a6 ID |
10643 | /* |
10644 | * The PLL needs to be enabled with a valid divider | |
10645 | * configuration, otherwise accessing DSI registers will hang | |
10646 | * the machine. See BSpec North Display Engine | |
10647 | * registers/MIPI[BXT]. We can break out here early, since we | |
10648 | * need the same DSI PLL to be enabled for both DSI ports. | |
10649 | */ | |
10650 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10651 | break; | |
10652 | ||
4d1de975 JN |
10653 | /* XXX: this works for video mode only */ |
10654 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10655 | if (!(tmp & DPI_ENABLE)) | |
10656 | continue; | |
10657 | ||
10658 | tmp = I915_READ(MIPI_CTRL(port)); | |
10659 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10660 | continue; | |
10661 | ||
10662 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
10663 | break; |
10664 | } | |
10665 | ||
d7edc4e5 | 10666 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
10667 | } |
10668 | ||
26804afd | 10669 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10670 | struct intel_crtc_state *pipe_config) |
26804afd | 10671 | { |
6315b5d3 | 10672 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 10673 | struct intel_shared_dpll *pll; |
26804afd DV |
10674 | enum port port; |
10675 | uint32_t tmp; | |
10676 | ||
10677 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10678 | ||
10679 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10680 | ||
0853723b | 10681 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
96b7dfb7 | 10682 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 10683 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 10684 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
10685 | else |
10686 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10687 | |
8106ddbd ACO |
10688 | pll = pipe_config->shared_dpll; |
10689 | if (pll) { | |
2edd6443 ACO |
10690 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10691 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10692 | } |
10693 | ||
26804afd DV |
10694 | /* |
10695 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10696 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10697 | * the PCH transcoder is on. | |
10698 | */ | |
6315b5d3 | 10699 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 10700 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
10701 | pipe_config->has_pch_encoder = true; |
10702 | ||
10703 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10704 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10705 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10706 | ||
10707 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10708 | } | |
10709 | } | |
10710 | ||
0e8ffe1b | 10711 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10712 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 10713 | { |
6315b5d3 | 10714 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e ID |
10715 | enum intel_display_power_domain power_domain; |
10716 | unsigned long power_domain_mask; | |
cf30429e | 10717 | bool active; |
0e8ffe1b | 10718 | |
1729050e ID |
10719 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10720 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10721 | return false; |
1729050e ID |
10722 | power_domain_mask = BIT(power_domain); |
10723 | ||
8106ddbd | 10724 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10725 | |
cf30429e | 10726 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10727 | |
cc3f90f0 | 10728 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
10729 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
10730 | WARN_ON(active); | |
10731 | active = true; | |
4d1de975 JN |
10732 | } |
10733 | ||
cf30429e | 10734 | if (!active) |
1729050e | 10735 | goto out; |
0e8ffe1b | 10736 | |
d7edc4e5 | 10737 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
10738 | haswell_get_ddi_port_state(crtc, pipe_config); |
10739 | intel_get_pipe_timings(crtc, pipe_config); | |
10740 | } | |
627eb5a3 | 10741 | |
bc58be60 | 10742 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10743 | |
05dc698c LL |
10744 | pipe_config->gamma_mode = |
10745 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10746 | ||
6315b5d3 | 10747 | if (INTEL_GEN(dev_priv) >= 9) { |
65edccce | 10748 | skl_init_scalers(dev_priv, crtc, pipe_config); |
a1b2278e | 10749 | |
af99ceda CK |
10750 | pipe_config->scaler_state.scaler_id = -1; |
10751 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10752 | } | |
10753 | ||
1729050e ID |
10754 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10755 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10756 | power_domain_mask |= BIT(power_domain); | |
6315b5d3 | 10757 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 10758 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10759 | else |
1c132b44 | 10760 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10761 | } |
88adfff1 | 10762 | |
772c2a51 | 10763 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
10764 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
10765 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10766 | |
4d1de975 JN |
10767 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10768 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10769 | pipe_config->pixel_multiplier = |
10770 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10771 | } else { | |
10772 | pipe_config->pixel_multiplier = 1; | |
10773 | } | |
6c49f241 | 10774 | |
1729050e ID |
10775 | out: |
10776 | for_each_power_domain(power_domain, power_domain_mask) | |
10777 | intel_display_power_put(dev_priv, power_domain); | |
10778 | ||
cf30429e | 10779 | return active; |
0e8ffe1b DV |
10780 | } |
10781 | ||
55a08b3f ML |
10782 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10783 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10784 | { |
10785 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10786 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 10787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 10788 | uint32_t cntl = 0, size = 0; |
560b85bb | 10789 | |
936e71e3 | 10790 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
10791 | unsigned int width = plane_state->base.crtc_w; |
10792 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10793 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10794 | ||
10795 | switch (stride) { | |
10796 | default: | |
10797 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10798 | width, stride); | |
10799 | stride = 256; | |
10800 | /* fallthrough */ | |
10801 | case 256: | |
10802 | case 512: | |
10803 | case 1024: | |
10804 | case 2048: | |
10805 | break; | |
4b0e333e CW |
10806 | } |
10807 | ||
dc41c154 VS |
10808 | cntl |= CURSOR_ENABLE | |
10809 | CURSOR_GAMMA_ENABLE | | |
10810 | CURSOR_FORMAT_ARGB | | |
10811 | CURSOR_STRIDE(stride); | |
10812 | ||
10813 | size = (height << 12) | width; | |
4b0e333e | 10814 | } |
560b85bb | 10815 | |
dc41c154 VS |
10816 | if (intel_crtc->cursor_cntl != 0 && |
10817 | (intel_crtc->cursor_base != base || | |
10818 | intel_crtc->cursor_size != size || | |
10819 | intel_crtc->cursor_cntl != cntl)) { | |
10820 | /* On these chipsets we can only modify the base/size/stride | |
10821 | * whilst the cursor is disabled. | |
10822 | */ | |
0b87c24e VS |
10823 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10824 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10825 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10826 | } |
560b85bb | 10827 | |
99d1f387 | 10828 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10829 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10830 | intel_crtc->cursor_base = base; |
10831 | } | |
4726e0b0 | 10832 | |
dc41c154 VS |
10833 | if (intel_crtc->cursor_size != size) { |
10834 | I915_WRITE(CURSIZE, size); | |
10835 | intel_crtc->cursor_size = size; | |
4b0e333e | 10836 | } |
560b85bb | 10837 | |
4b0e333e | 10838 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10839 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10840 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10841 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10842 | } |
560b85bb CW |
10843 | } |
10844 | ||
55a08b3f ML |
10845 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10846 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10847 | { |
10848 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10849 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
10850 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10851 | int pipe = intel_crtc->pipe; | |
663f3122 | 10852 | uint32_t cntl = 0; |
4b0e333e | 10853 | |
936e71e3 | 10854 | if (plane_state && plane_state->base.visible) { |
4b0e333e | 10855 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10856 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10857 | case 64: |
10858 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10859 | break; | |
10860 | case 128: | |
10861 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10862 | break; | |
10863 | case 256: | |
10864 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10865 | break; | |
10866 | default: | |
55a08b3f | 10867 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10868 | return; |
65a21cd6 | 10869 | } |
4b0e333e | 10870 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10871 | |
4f8036a2 | 10872 | if (HAS_DDI(dev_priv)) |
47bf17a7 | 10873 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10874 | |
f22aa143 | 10875 | if (plane_state->base.rotation & DRM_ROTATE_180) |
55a08b3f ML |
10876 | cntl |= CURSOR_ROTATE_180; |
10877 | } | |
4398ad45 | 10878 | |
4b0e333e CW |
10879 | if (intel_crtc->cursor_cntl != cntl) { |
10880 | I915_WRITE(CURCNTR(pipe), cntl); | |
10881 | POSTING_READ(CURCNTR(pipe)); | |
10882 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10883 | } |
4b0e333e | 10884 | |
65a21cd6 | 10885 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10886 | I915_WRITE(CURBASE(pipe), base); |
10887 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10888 | |
10889 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10890 | } |
10891 | ||
cda4b7d3 | 10892 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10893 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10894 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10895 | { |
10896 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10897 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
10898 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10899 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10900 | u32 base = intel_crtc->cursor_addr; |
10901 | u32 pos = 0; | |
cda4b7d3 | 10902 | |
55a08b3f ML |
10903 | if (plane_state) { |
10904 | int x = plane_state->base.crtc_x; | |
10905 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10906 | |
55a08b3f ML |
10907 | if (x < 0) { |
10908 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10909 | x = -x; | |
10910 | } | |
10911 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10912 | |
55a08b3f ML |
10913 | if (y < 0) { |
10914 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10915 | y = -y; | |
10916 | } | |
10917 | pos |= y << CURSOR_Y_SHIFT; | |
10918 | ||
10919 | /* ILK+ do this automagically */ | |
49cff963 | 10920 | if (HAS_GMCH_DISPLAY(dev_priv) && |
f22aa143 | 10921 | plane_state->base.rotation & DRM_ROTATE_180) { |
55a08b3f ML |
10922 | base += (plane_state->base.crtc_h * |
10923 | plane_state->base.crtc_w - 1) * 4; | |
10924 | } | |
cda4b7d3 | 10925 | } |
cda4b7d3 | 10926 | |
5efb3e28 VS |
10927 | I915_WRITE(CURPOS(pipe), pos); |
10928 | ||
2a307c2e | 10929 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
55a08b3f | 10930 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10931 | else |
55a08b3f | 10932 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10933 | } |
10934 | ||
50a0bc90 | 10935 | static bool cursor_size_ok(struct drm_i915_private *dev_priv, |
dc41c154 VS |
10936 | uint32_t width, uint32_t height) |
10937 | { | |
10938 | if (width == 0 || height == 0) | |
10939 | return false; | |
10940 | ||
10941 | /* | |
10942 | * 845g/865g are special in that they are only limited by | |
10943 | * the width of their cursors, the height is arbitrary up to | |
10944 | * the precision of the register. Everything else requires | |
10945 | * square cursors, limited to a few power-of-two sizes. | |
10946 | */ | |
2a307c2e | 10947 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
dc41c154 VS |
10948 | if ((width & 63) != 0) |
10949 | return false; | |
10950 | ||
2a307c2e | 10951 | if (width > (IS_I845G(dev_priv) ? 64 : 512)) |
dc41c154 VS |
10952 | return false; |
10953 | ||
10954 | if (height > 1023) | |
10955 | return false; | |
10956 | } else { | |
10957 | switch (width | height) { | |
10958 | case 256: | |
10959 | case 128: | |
50a0bc90 | 10960 | if (IS_GEN2(dev_priv)) |
dc41c154 VS |
10961 | return false; |
10962 | case 64: | |
10963 | break; | |
10964 | default: | |
10965 | return false; | |
10966 | } | |
10967 | } | |
10968 | ||
10969 | return true; | |
10970 | } | |
10971 | ||
79e53945 JB |
10972 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10973 | static struct drm_display_mode load_detect_mode = { | |
10974 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10975 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10976 | }; | |
10977 | ||
a8bb6818 DV |
10978 | struct drm_framebuffer * |
10979 | __intel_framebuffer_create(struct drm_device *dev, | |
10980 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10981 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10982 | { |
10983 | struct intel_framebuffer *intel_fb; | |
10984 | int ret; | |
10985 | ||
10986 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10987 | if (!intel_fb) |
d2dff872 | 10988 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10989 | |
10990 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10991 | if (ret) |
10992 | goto err; | |
d2dff872 CW |
10993 | |
10994 | return &intel_fb->base; | |
dcb1394e | 10995 | |
dd4916c5 | 10996 | err: |
dd4916c5 | 10997 | kfree(intel_fb); |
dd4916c5 | 10998 | return ERR_PTR(ret); |
d2dff872 CW |
10999 | } |
11000 | ||
b5ea642a | 11001 | static struct drm_framebuffer * |
a8bb6818 DV |
11002 | intel_framebuffer_create(struct drm_device *dev, |
11003 | struct drm_mode_fb_cmd2 *mode_cmd, | |
11004 | struct drm_i915_gem_object *obj) | |
11005 | { | |
11006 | struct drm_framebuffer *fb; | |
11007 | int ret; | |
11008 | ||
11009 | ret = i915_mutex_lock_interruptible(dev); | |
11010 | if (ret) | |
11011 | return ERR_PTR(ret); | |
11012 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
11013 | mutex_unlock(&dev->struct_mutex); | |
11014 | ||
11015 | return fb; | |
11016 | } | |
11017 | ||
d2dff872 CW |
11018 | static u32 |
11019 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
11020 | { | |
11021 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
11022 | return ALIGN(pitch, 64); | |
11023 | } | |
11024 | ||
11025 | static u32 | |
11026 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
11027 | { | |
11028 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 11029 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
11030 | } |
11031 | ||
11032 | static struct drm_framebuffer * | |
11033 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
11034 | struct drm_display_mode *mode, | |
11035 | int depth, int bpp) | |
11036 | { | |
dcb1394e | 11037 | struct drm_framebuffer *fb; |
d2dff872 | 11038 | struct drm_i915_gem_object *obj; |
0fed39bd | 11039 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 11040 | |
12d79d78 | 11041 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 11042 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
11043 | if (IS_ERR(obj)) |
11044 | return ERR_CAST(obj); | |
d2dff872 CW |
11045 | |
11046 | mode_cmd.width = mode->hdisplay; | |
11047 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
11048 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
11049 | bpp); | |
5ca0c34a | 11050 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 11051 | |
dcb1394e LW |
11052 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
11053 | if (IS_ERR(fb)) | |
f0cd5182 | 11054 | i915_gem_object_put(obj); |
dcb1394e LW |
11055 | |
11056 | return fb; | |
d2dff872 CW |
11057 | } |
11058 | ||
11059 | static struct drm_framebuffer * | |
11060 | mode_fits_in_fbdev(struct drm_device *dev, | |
11061 | struct drm_display_mode *mode) | |
11062 | { | |
0695726e | 11063 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 11064 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
11065 | struct drm_i915_gem_object *obj; |
11066 | struct drm_framebuffer *fb; | |
11067 | ||
4c0e5528 | 11068 | if (!dev_priv->fbdev) |
d2dff872 CW |
11069 | return NULL; |
11070 | ||
4c0e5528 | 11071 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
11072 | return NULL; |
11073 | ||
4c0e5528 DV |
11074 | obj = dev_priv->fbdev->fb->obj; |
11075 | BUG_ON(!obj); | |
11076 | ||
8bcd4553 | 11077 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
11078 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
11079 | fb->bits_per_pixel)) | |
d2dff872 CW |
11080 | return NULL; |
11081 | ||
01f2c773 | 11082 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
11083 | return NULL; |
11084 | ||
edde3617 | 11085 | drm_framebuffer_reference(fb); |
d2dff872 | 11086 | return fb; |
4520f53a DV |
11087 | #else |
11088 | return NULL; | |
11089 | #endif | |
d2dff872 CW |
11090 | } |
11091 | ||
d3a40d1b ACO |
11092 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
11093 | struct drm_crtc *crtc, | |
11094 | struct drm_display_mode *mode, | |
11095 | struct drm_framebuffer *fb, | |
11096 | int x, int y) | |
11097 | { | |
11098 | struct drm_plane_state *plane_state; | |
11099 | int hdisplay, vdisplay; | |
11100 | int ret; | |
11101 | ||
11102 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
11103 | if (IS_ERR(plane_state)) | |
11104 | return PTR_ERR(plane_state); | |
11105 | ||
11106 | if (mode) | |
11107 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
11108 | else | |
11109 | hdisplay = vdisplay = 0; | |
11110 | ||
11111 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
11112 | if (ret) | |
11113 | return ret; | |
11114 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11115 | plane_state->crtc_x = 0; | |
11116 | plane_state->crtc_y = 0; | |
11117 | plane_state->crtc_w = hdisplay; | |
11118 | plane_state->crtc_h = vdisplay; | |
11119 | plane_state->src_x = x << 16; | |
11120 | plane_state->src_y = y << 16; | |
11121 | plane_state->src_w = hdisplay << 16; | |
11122 | plane_state->src_h = vdisplay << 16; | |
11123 | ||
11124 | return 0; | |
11125 | } | |
11126 | ||
d2434ab7 | 11127 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 11128 | struct drm_display_mode *mode, |
51fd371b RC |
11129 | struct intel_load_detect_pipe *old, |
11130 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
11131 | { |
11132 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
11133 | struct intel_encoder *intel_encoder = |
11134 | intel_attached_encoder(connector); | |
79e53945 | 11135 | struct drm_crtc *possible_crtc; |
4ef69c7a | 11136 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
11137 | struct drm_crtc *crtc = NULL; |
11138 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 11139 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 11140 | struct drm_framebuffer *fb; |
51fd371b | 11141 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 11142 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 11143 | struct drm_connector_state *connector_state; |
4be07317 | 11144 | struct intel_crtc_state *crtc_state; |
51fd371b | 11145 | int ret, i = -1; |
79e53945 | 11146 | |
d2dff872 | 11147 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 11148 | connector->base.id, connector->name, |
8e329a03 | 11149 | encoder->base.id, encoder->name); |
d2dff872 | 11150 | |
edde3617 ML |
11151 | old->restore_state = NULL; |
11152 | ||
51fd371b RC |
11153 | retry: |
11154 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
11155 | if (ret) | |
ad3c558f | 11156 | goto fail; |
6e9f798d | 11157 | |
79e53945 JB |
11158 | /* |
11159 | * Algorithm gets a little messy: | |
7a5e4805 | 11160 | * |
79e53945 JB |
11161 | * - if the connector already has an assigned crtc, use it (but make |
11162 | * sure it's on first) | |
7a5e4805 | 11163 | * |
79e53945 JB |
11164 | * - try to find the first unused crtc that can drive this connector, |
11165 | * and use that if we find one | |
79e53945 JB |
11166 | */ |
11167 | ||
11168 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
11169 | if (connector->state->crtc) { |
11170 | crtc = connector->state->crtc; | |
8261b191 | 11171 | |
51fd371b | 11172 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 11173 | if (ret) |
ad3c558f | 11174 | goto fail; |
8261b191 CW |
11175 | |
11176 | /* Make sure the crtc and connector are running */ | |
edde3617 | 11177 | goto found; |
79e53945 JB |
11178 | } |
11179 | ||
11180 | /* Find an unused one (if possible) */ | |
70e1e0ec | 11181 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
11182 | i++; |
11183 | if (!(encoder->possible_crtcs & (1 << i))) | |
11184 | continue; | |
edde3617 ML |
11185 | |
11186 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
11187 | if (ret) | |
11188 | goto fail; | |
11189 | ||
11190 | if (possible_crtc->state->enable) { | |
11191 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 11192 | continue; |
edde3617 | 11193 | } |
a459249c VS |
11194 | |
11195 | crtc = possible_crtc; | |
11196 | break; | |
79e53945 JB |
11197 | } |
11198 | ||
11199 | /* | |
11200 | * If we didn't find an unused CRTC, don't use any. | |
11201 | */ | |
11202 | if (!crtc) { | |
7173188d | 11203 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 11204 | goto fail; |
79e53945 JB |
11205 | } |
11206 | ||
edde3617 ML |
11207 | found: |
11208 | intel_crtc = to_intel_crtc(crtc); | |
11209 | ||
4d02e2de DV |
11210 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
11211 | if (ret) | |
ad3c558f | 11212 | goto fail; |
79e53945 | 11213 | |
83a57153 | 11214 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
11215 | restore_state = drm_atomic_state_alloc(dev); |
11216 | if (!state || !restore_state) { | |
11217 | ret = -ENOMEM; | |
11218 | goto fail; | |
11219 | } | |
83a57153 ACO |
11220 | |
11221 | state->acquire_ctx = ctx; | |
edde3617 | 11222 | restore_state->acquire_ctx = ctx; |
83a57153 | 11223 | |
944b0c76 ACO |
11224 | connector_state = drm_atomic_get_connector_state(state, connector); |
11225 | if (IS_ERR(connector_state)) { | |
11226 | ret = PTR_ERR(connector_state); | |
11227 | goto fail; | |
11228 | } | |
11229 | ||
edde3617 ML |
11230 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
11231 | if (ret) | |
11232 | goto fail; | |
944b0c76 | 11233 | |
4be07317 ACO |
11234 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
11235 | if (IS_ERR(crtc_state)) { | |
11236 | ret = PTR_ERR(crtc_state); | |
11237 | goto fail; | |
11238 | } | |
11239 | ||
49d6fa21 | 11240 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 11241 | |
6492711d CW |
11242 | if (!mode) |
11243 | mode = &load_detect_mode; | |
79e53945 | 11244 | |
d2dff872 CW |
11245 | /* We need a framebuffer large enough to accommodate all accesses |
11246 | * that the plane may generate whilst we perform load detection. | |
11247 | * We can not rely on the fbcon either being present (we get called | |
11248 | * during its initialisation to detect all boot displays, or it may | |
11249 | * not even exist) or that it is large enough to satisfy the | |
11250 | * requested mode. | |
11251 | */ | |
94352cf9 DV |
11252 | fb = mode_fits_in_fbdev(dev, mode); |
11253 | if (fb == NULL) { | |
d2dff872 | 11254 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 11255 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
11256 | } else |
11257 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 11258 | if (IS_ERR(fb)) { |
d2dff872 | 11259 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 11260 | goto fail; |
79e53945 | 11261 | } |
79e53945 | 11262 | |
d3a40d1b ACO |
11263 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
11264 | if (ret) | |
11265 | goto fail; | |
11266 | ||
edde3617 ML |
11267 | drm_framebuffer_unreference(fb); |
11268 | ||
11269 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
11270 | if (ret) | |
11271 | goto fail; | |
11272 | ||
11273 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
11274 | if (!ret) | |
11275 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
11276 | if (!ret) | |
11277 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
11278 | if (ret) { | |
11279 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
11280 | goto fail; | |
11281 | } | |
8c7b5ccb | 11282 | |
3ba86073 ML |
11283 | ret = drm_atomic_commit(state); |
11284 | if (ret) { | |
6492711d | 11285 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 11286 | goto fail; |
79e53945 | 11287 | } |
edde3617 ML |
11288 | |
11289 | old->restore_state = restore_state; | |
7173188d | 11290 | |
79e53945 | 11291 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 11292 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 11293 | return true; |
412b61d8 | 11294 | |
ad3c558f | 11295 | fail: |
7fb71c8f CW |
11296 | if (state) { |
11297 | drm_atomic_state_put(state); | |
11298 | state = NULL; | |
11299 | } | |
11300 | if (restore_state) { | |
11301 | drm_atomic_state_put(restore_state); | |
11302 | restore_state = NULL; | |
11303 | } | |
83a57153 | 11304 | |
51fd371b RC |
11305 | if (ret == -EDEADLK) { |
11306 | drm_modeset_backoff(ctx); | |
11307 | goto retry; | |
11308 | } | |
11309 | ||
412b61d8 | 11310 | return false; |
79e53945 JB |
11311 | } |
11312 | ||
d2434ab7 | 11313 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
11314 | struct intel_load_detect_pipe *old, |
11315 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 11316 | { |
d2434ab7 DV |
11317 | struct intel_encoder *intel_encoder = |
11318 | intel_attached_encoder(connector); | |
4ef69c7a | 11319 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 11320 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 11321 | int ret; |
79e53945 | 11322 | |
d2dff872 | 11323 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 11324 | connector->base.id, connector->name, |
8e329a03 | 11325 | encoder->base.id, encoder->name); |
d2dff872 | 11326 | |
edde3617 | 11327 | if (!state) |
0622a53c | 11328 | return; |
79e53945 | 11329 | |
edde3617 | 11330 | ret = drm_atomic_commit(state); |
0853695c | 11331 | if (ret) |
edde3617 | 11332 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 11333 | drm_atomic_state_put(state); |
79e53945 JB |
11334 | } |
11335 | ||
da4a1efa | 11336 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 11337 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 11338 | { |
fac5e23e | 11339 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
11340 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
11341 | ||
11342 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 11343 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 11344 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 11345 | return 120000; |
5db94019 | 11346 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
11347 | return 96000; |
11348 | else | |
11349 | return 48000; | |
11350 | } | |
11351 | ||
79e53945 | 11352 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 11353 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 11354 | struct intel_crtc_state *pipe_config) |
79e53945 | 11355 | { |
f1f644dc | 11356 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 11357 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 11358 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 11359 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 11360 | u32 fp; |
9e2c8475 | 11361 | struct dpll clock; |
dccbea3b | 11362 | int port_clock; |
da4a1efa | 11363 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
11364 | |
11365 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 11366 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 11367 | else |
293623f7 | 11368 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
11369 | |
11370 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 11371 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
11372 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
11373 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
11374 | } else { |
11375 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
11376 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
11377 | } | |
11378 | ||
5db94019 | 11379 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 11380 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
11381 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
11382 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
11383 | else |
11384 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
11385 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
11386 | ||
11387 | switch (dpll & DPLL_MODE_MASK) { | |
11388 | case DPLLB_MODE_DAC_SERIAL: | |
11389 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
11390 | 5 : 10; | |
11391 | break; | |
11392 | case DPLLB_MODE_LVDS: | |
11393 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
11394 | 7 : 14; | |
11395 | break; | |
11396 | default: | |
28c97730 | 11397 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 11398 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 11399 | return; |
79e53945 JB |
11400 | } |
11401 | ||
9b1e14f4 | 11402 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 11403 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 11404 | else |
dccbea3b | 11405 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 11406 | } else { |
50a0bc90 | 11407 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 11408 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
11409 | |
11410 | if (is_lvds) { | |
11411 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
11412 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
11413 | |
11414 | if (lvds & LVDS_CLKB_POWER_UP) | |
11415 | clock.p2 = 7; | |
11416 | else | |
11417 | clock.p2 = 14; | |
79e53945 JB |
11418 | } else { |
11419 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
11420 | clock.p1 = 2; | |
11421 | else { | |
11422 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
11423 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
11424 | } | |
11425 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
11426 | clock.p2 = 4; | |
11427 | else | |
11428 | clock.p2 = 2; | |
79e53945 | 11429 | } |
da4a1efa | 11430 | |
dccbea3b | 11431 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
11432 | } |
11433 | ||
18442d08 VS |
11434 | /* |
11435 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 11436 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
11437 | * encoder's get_config() function. |
11438 | */ | |
dccbea3b | 11439 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
11440 | } |
11441 | ||
6878da05 VS |
11442 | int intel_dotclock_calculate(int link_freq, |
11443 | const struct intel_link_m_n *m_n) | |
f1f644dc | 11444 | { |
f1f644dc JB |
11445 | /* |
11446 | * The calculation for the data clock is: | |
1041a02f | 11447 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 11448 | * But we want to avoid losing precison if possible, so: |
1041a02f | 11449 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
11450 | * |
11451 | * and the link clock is simpler: | |
1041a02f | 11452 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
11453 | */ |
11454 | ||
6878da05 VS |
11455 | if (!m_n->link_n) |
11456 | return 0; | |
f1f644dc | 11457 | |
6878da05 VS |
11458 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
11459 | } | |
f1f644dc | 11460 | |
18442d08 | 11461 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 11462 | struct intel_crtc_state *pipe_config) |
6878da05 | 11463 | { |
e3b247da | 11464 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 11465 | |
18442d08 VS |
11466 | /* read out port_clock from the DPLL */ |
11467 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 11468 | |
f1f644dc | 11469 | /* |
e3b247da VS |
11470 | * In case there is an active pipe without active ports, |
11471 | * we may need some idea for the dotclock anyway. | |
11472 | * Calculate one based on the FDI configuration. | |
79e53945 | 11473 | */ |
2d112de7 | 11474 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 11475 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 11476 | &pipe_config->fdi_m_n); |
79e53945 JB |
11477 | } |
11478 | ||
11479 | /** Returns the currently programmed mode of the given pipe. */ | |
11480 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
11481 | struct drm_crtc *crtc) | |
11482 | { | |
fac5e23e | 11483 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 11484 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 11485 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 11486 | struct drm_display_mode *mode; |
3f36b937 | 11487 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
11488 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
11489 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11490 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
11491 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 11492 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
11493 | |
11494 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
11495 | if (!mode) | |
11496 | return NULL; | |
11497 | ||
3f36b937 TU |
11498 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
11499 | if (!pipe_config) { | |
11500 | kfree(mode); | |
11501 | return NULL; | |
11502 | } | |
11503 | ||
f1f644dc JB |
11504 | /* |
11505 | * Construct a pipe_config sufficient for getting the clock info | |
11506 | * back out of crtc_clock_get. | |
11507 | * | |
11508 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
11509 | * to use a real value here instead. | |
11510 | */ | |
3f36b937 TU |
11511 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
11512 | pipe_config->pixel_multiplier = 1; | |
11513 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
11514 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
11515 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
11516 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
11517 | ||
11518 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
11519 | mode->hdisplay = (htot & 0xffff) + 1; |
11520 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
11521 | mode->hsync_start = (hsync & 0xffff) + 1; | |
11522 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
11523 | mode->vdisplay = (vtot & 0xffff) + 1; | |
11524 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
11525 | mode->vsync_start = (vsync & 0xffff) + 1; | |
11526 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
11527 | ||
11528 | drm_mode_set_name(mode); | |
79e53945 | 11529 | |
3f36b937 TU |
11530 | kfree(pipe_config); |
11531 | ||
79e53945 JB |
11532 | return mode; |
11533 | } | |
11534 | ||
11535 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
11536 | { | |
11537 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 11538 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 11539 | struct intel_flip_work *work; |
67e77c5a | 11540 | |
5e2d7afc | 11541 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
11542 | work = intel_crtc->flip_work; |
11543 | intel_crtc->flip_work = NULL; | |
11544 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 11545 | |
5a21b665 | 11546 | if (work) { |
51cbaf01 ML |
11547 | cancel_work_sync(&work->mmio_work); |
11548 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 11549 | kfree(work); |
67e77c5a | 11550 | } |
79e53945 JB |
11551 | |
11552 | drm_crtc_cleanup(crtc); | |
67e77c5a | 11553 | |
79e53945 JB |
11554 | kfree(intel_crtc); |
11555 | } | |
11556 | ||
6b95a207 KH |
11557 | static void intel_unpin_work_fn(struct work_struct *__work) |
11558 | { | |
51cbaf01 ML |
11559 | struct intel_flip_work *work = |
11560 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
11561 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
11562 | struct drm_device *dev = crtc->base.dev; | |
11563 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 11564 | |
5a21b665 DV |
11565 | if (is_mmio_work(work)) |
11566 | flush_work(&work->mmio_work); | |
03f476e1 | 11567 | |
5a21b665 DV |
11568 | mutex_lock(&dev->struct_mutex); |
11569 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
f8c417cd | 11570 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 11571 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 11572 | |
e8a261ea CW |
11573 | i915_gem_request_put(work->flip_queued_req); |
11574 | ||
5748b6a1 CW |
11575 | intel_frontbuffer_flip_complete(to_i915(dev), |
11576 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
11577 | intel_fbc_post_update(crtc); |
11578 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 11579 | |
5a21b665 DV |
11580 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11581 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 11582 | |
5a21b665 DV |
11583 | kfree(work); |
11584 | } | |
d9e86c0e | 11585 | |
5a21b665 DV |
11586 | /* Is 'a' after or equal to 'b'? */ |
11587 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11588 | { | |
11589 | return !((a - b) & 0x80000000); | |
11590 | } | |
143f73b3 | 11591 | |
5a21b665 DV |
11592 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
11593 | struct intel_flip_work *work) | |
11594 | { | |
11595 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11596 | struct drm_i915_private *dev_priv = to_i915(dev); |
143f73b3 | 11597 | |
8af29b0c | 11598 | if (abort_flip_on_reset(crtc)) |
5a21b665 | 11599 | return true; |
143f73b3 | 11600 | |
5a21b665 DV |
11601 | /* |
11602 | * The relevant registers doen't exist on pre-ctg. | |
11603 | * As the flip done interrupt doesn't trigger for mmio | |
11604 | * flips on gmch platforms, a flip count check isn't | |
11605 | * really needed there. But since ctg has the registers, | |
11606 | * include it in the check anyway. | |
11607 | */ | |
9beb5fea | 11608 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
5a21b665 | 11609 | return true; |
b4a98e57 | 11610 | |
5a21b665 DV |
11611 | /* |
11612 | * BDW signals flip done immediately if the plane | |
11613 | * is disabled, even if the plane enable is already | |
11614 | * armed to occur at the next vblank :( | |
11615 | */ | |
f99d7069 | 11616 | |
5a21b665 DV |
11617 | /* |
11618 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11619 | * used the same base address. In that case the mmio flip might | |
11620 | * have completed, but the CS hasn't even executed the flip yet. | |
11621 | * | |
11622 | * A flip count check isn't enough as the CS might have updated | |
11623 | * the base address just after start of vblank, but before we | |
11624 | * managed to process the interrupt. This means we'd complete the | |
11625 | * CS flip too soon. | |
11626 | * | |
11627 | * Combining both checks should get us a good enough result. It may | |
11628 | * still happen that the CS flip has been executed, but has not | |
11629 | * yet actually completed. But in case the base address is the same | |
11630 | * anyway, we don't really care. | |
11631 | */ | |
11632 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11633 | crtc->flip_work->gtt_offset && | |
11634 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11635 | crtc->flip_work->flip_count); | |
11636 | } | |
b4a98e57 | 11637 | |
5a21b665 DV |
11638 | static bool |
11639 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11640 | struct intel_flip_work *work) | |
11641 | { | |
11642 | /* | |
11643 | * MMIO work completes when vblank is different from | |
11644 | * flip_queued_vblank. | |
11645 | * | |
11646 | * Reset counter value doesn't matter, this is handled by | |
11647 | * i915_wait_request finishing early, so no need to handle | |
11648 | * reset here. | |
11649 | */ | |
11650 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11651 | } |
11652 | ||
51cbaf01 ML |
11653 | |
11654 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11655 | struct intel_flip_work *work) | |
11656 | { | |
11657 | if (!atomic_read(&work->pending)) | |
11658 | return false; | |
11659 | ||
11660 | smp_rmb(); | |
11661 | ||
5a21b665 DV |
11662 | if (is_mmio_work(work)) |
11663 | return __pageflip_finished_mmio(crtc, work); | |
11664 | else | |
11665 | return __pageflip_finished_cs(crtc, work); | |
11666 | } | |
11667 | ||
11668 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11669 | { | |
91c8a326 | 11670 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 11671 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
11672 | struct intel_flip_work *work; |
11673 | unsigned long flags; | |
11674 | ||
11675 | /* Ignore early vblank irqs */ | |
11676 | if (!crtc) | |
11677 | return; | |
11678 | ||
51cbaf01 | 11679 | /* |
5a21b665 DV |
11680 | * This is called both by irq handlers and the reset code (to complete |
11681 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11682 | */ |
5a21b665 | 11683 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 11684 | work = crtc->flip_work; |
5a21b665 DV |
11685 | |
11686 | if (work != NULL && | |
11687 | !is_mmio_work(work) && | |
e2af48c6 VS |
11688 | pageflip_finished(crtc, work)) |
11689 | page_flip_completed(crtc); | |
5a21b665 DV |
11690 | |
11691 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11692 | } |
11693 | ||
51cbaf01 | 11694 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11695 | { |
91c8a326 | 11696 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 11697 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
51cbaf01 | 11698 | struct intel_flip_work *work; |
6b95a207 KH |
11699 | unsigned long flags; |
11700 | ||
5251f04e ML |
11701 | /* Ignore early vblank irqs */ |
11702 | if (!crtc) | |
11703 | return; | |
f326038a DV |
11704 | |
11705 | /* | |
11706 | * This is called both by irq handlers and the reset code (to complete | |
11707 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11708 | */ |
6b95a207 | 11709 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 11710 | work = crtc->flip_work; |
5251f04e | 11711 | |
5a21b665 DV |
11712 | if (work != NULL && |
11713 | is_mmio_work(work) && | |
e2af48c6 VS |
11714 | pageflip_finished(crtc, work)) |
11715 | page_flip_completed(crtc); | |
5251f04e | 11716 | |
6b95a207 KH |
11717 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11718 | } | |
11719 | ||
5a21b665 DV |
11720 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11721 | struct intel_flip_work *work) | |
84c33a64 | 11722 | { |
5a21b665 | 11723 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11724 | |
5a21b665 DV |
11725 | /* Ensure that the work item is consistent when activating it ... */ |
11726 | smp_mb__before_atomic(); | |
11727 | atomic_set(&work->pending, 1); | |
11728 | } | |
a6747b73 | 11729 | |
5a21b665 DV |
11730 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11731 | struct drm_crtc *crtc, | |
11732 | struct drm_framebuffer *fb, | |
11733 | struct drm_i915_gem_object *obj, | |
11734 | struct drm_i915_gem_request *req, | |
11735 | uint32_t flags) | |
11736 | { | |
7e37f889 | 11737 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11739 | u32 flip_mask; | |
11740 | int ret; | |
143f73b3 | 11741 | |
5a21b665 DV |
11742 | ret = intel_ring_begin(req, 6); |
11743 | if (ret) | |
11744 | return ret; | |
143f73b3 | 11745 | |
5a21b665 DV |
11746 | /* Can't queue multiple flips, so wait for the previous |
11747 | * one to finish before executing the next. | |
11748 | */ | |
11749 | if (intel_crtc->plane) | |
11750 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11751 | else | |
11752 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11753 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11754 | intel_ring_emit(ring, MI_NOOP); | |
11755 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
5a21b665 | 11756 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11757 | intel_ring_emit(ring, fb->pitches[0]); |
11758 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11759 | intel_ring_emit(ring, 0); /* aux display base address, unused */ | |
143f73b3 | 11760 | |
5a21b665 DV |
11761 | return 0; |
11762 | } | |
84c33a64 | 11763 | |
5a21b665 DV |
11764 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11765 | struct drm_crtc *crtc, | |
11766 | struct drm_framebuffer *fb, | |
11767 | struct drm_i915_gem_object *obj, | |
11768 | struct drm_i915_gem_request *req, | |
11769 | uint32_t flags) | |
11770 | { | |
7e37f889 | 11771 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11773 | u32 flip_mask; | |
11774 | int ret; | |
d55dbd06 | 11775 | |
5a21b665 DV |
11776 | ret = intel_ring_begin(req, 6); |
11777 | if (ret) | |
11778 | return ret; | |
d55dbd06 | 11779 | |
5a21b665 DV |
11780 | if (intel_crtc->plane) |
11781 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11782 | else | |
11783 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11784 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11785 | intel_ring_emit(ring, MI_NOOP); | |
11786 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
5a21b665 | 11787 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11788 | intel_ring_emit(ring, fb->pitches[0]); |
11789 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11790 | intel_ring_emit(ring, MI_NOOP); | |
fd8e058a | 11791 | |
5a21b665 DV |
11792 | return 0; |
11793 | } | |
84c33a64 | 11794 | |
5a21b665 DV |
11795 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11796 | struct drm_crtc *crtc, | |
11797 | struct drm_framebuffer *fb, | |
11798 | struct drm_i915_gem_object *obj, | |
11799 | struct drm_i915_gem_request *req, | |
11800 | uint32_t flags) | |
11801 | { | |
7e37f889 | 11802 | struct intel_ring *ring = req->ring; |
fac5e23e | 11803 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11804 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11805 | uint32_t pf, pipesrc; | |
11806 | int ret; | |
143f73b3 | 11807 | |
5a21b665 DV |
11808 | ret = intel_ring_begin(req, 4); |
11809 | if (ret) | |
11810 | return ret; | |
143f73b3 | 11811 | |
5a21b665 DV |
11812 | /* i965+ uses the linear or tiled offsets from the |
11813 | * Display Registers (which do not change across a page-flip) | |
11814 | * so we need only reprogram the base address. | |
11815 | */ | |
b5321f30 | 11816 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11817 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11818 | intel_ring_emit(ring, fb->pitches[0]); |
11819 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset | | |
bae781b2 | 11820 | intel_fb_modifier_to_tiling(fb->modifier)); |
5a21b665 DV |
11821 | |
11822 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11823 | * untested on non-native modes, so ignore it for now. | |
11824 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11825 | */ | |
11826 | pf = 0; | |
11827 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11828 | intel_ring_emit(ring, pf | pipesrc); |
143f73b3 | 11829 | |
5a21b665 | 11830 | return 0; |
8c9f3aaf JB |
11831 | } |
11832 | ||
5a21b665 DV |
11833 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11834 | struct drm_crtc *crtc, | |
11835 | struct drm_framebuffer *fb, | |
11836 | struct drm_i915_gem_object *obj, | |
11837 | struct drm_i915_gem_request *req, | |
11838 | uint32_t flags) | |
da20eabd | 11839 | { |
7e37f889 | 11840 | struct intel_ring *ring = req->ring; |
fac5e23e | 11841 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11843 | uint32_t pf, pipesrc; | |
11844 | int ret; | |
d21fbe87 | 11845 | |
5a21b665 DV |
11846 | ret = intel_ring_begin(req, 4); |
11847 | if (ret) | |
11848 | return ret; | |
92826fcd | 11849 | |
b5321f30 | 11850 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11851 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
72618ebf | 11852 | intel_ring_emit(ring, fb->pitches[0] | |
bae781b2 | 11853 | intel_fb_modifier_to_tiling(fb->modifier)); |
b5321f30 | 11854 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
92826fcd | 11855 | |
5a21b665 DV |
11856 | /* Contrary to the suggestions in the documentation, |
11857 | * "Enable Panel Fitter" does not seem to be required when page | |
11858 | * flipping with a non-native mode, and worse causes a normal | |
11859 | * modeset to fail. | |
11860 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11861 | */ | |
11862 | pf = 0; | |
11863 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11864 | intel_ring_emit(ring, pf | pipesrc); |
7809e5ae | 11865 | |
5a21b665 | 11866 | return 0; |
7809e5ae MR |
11867 | } |
11868 | ||
5a21b665 DV |
11869 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11870 | struct drm_crtc *crtc, | |
11871 | struct drm_framebuffer *fb, | |
11872 | struct drm_i915_gem_object *obj, | |
11873 | struct drm_i915_gem_request *req, | |
11874 | uint32_t flags) | |
d21fbe87 | 11875 | { |
5db94019 | 11876 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e37f889 | 11877 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11878 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11879 | uint32_t plane_bit = 0; | |
11880 | int len, ret; | |
d21fbe87 | 11881 | |
5a21b665 DV |
11882 | switch (intel_crtc->plane) { |
11883 | case PLANE_A: | |
11884 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11885 | break; | |
11886 | case PLANE_B: | |
11887 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11888 | break; | |
11889 | case PLANE_C: | |
11890 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11891 | break; | |
11892 | default: | |
11893 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11894 | return -ENODEV; | |
11895 | } | |
11896 | ||
11897 | len = 4; | |
b5321f30 | 11898 | if (req->engine->id == RCS) { |
5a21b665 DV |
11899 | len += 6; |
11900 | /* | |
11901 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11902 | * 48bits addresses, and we need a NOOP for the batch size to | |
11903 | * stay even. | |
11904 | */ | |
5db94019 | 11905 | if (IS_GEN8(dev_priv)) |
5a21b665 DV |
11906 | len += 2; |
11907 | } | |
11908 | ||
11909 | /* | |
11910 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11911 | * "The full packet must be contained within the same cache line." | |
11912 | * | |
11913 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11914 | * cacheline, if we ever start emitting more commands before | |
11915 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11916 | * then do the cacheline alignment, and finally emit the | |
11917 | * MI_DISPLAY_FLIP. | |
11918 | */ | |
11919 | ret = intel_ring_cacheline_align(req); | |
11920 | if (ret) | |
11921 | return ret; | |
11922 | ||
11923 | ret = intel_ring_begin(req, len); | |
11924 | if (ret) | |
11925 | return ret; | |
11926 | ||
11927 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11928 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11929 | * more than one flip event at any time (or ensure that one flip message | |
11930 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11931 | * Experimentation says that BCS works despite DERRMR masking all | |
11932 | * flip-done completion events and that unmasking all planes at once | |
11933 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11934 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11935 | */ | |
b5321f30 CW |
11936 | if (req->engine->id == RCS) { |
11937 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11938 | intel_ring_emit_reg(ring, DERRMR); | |
11939 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
5a21b665 DV |
11940 | DERRMR_PIPEB_PRI_FLIP_DONE | |
11941 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
5db94019 | 11942 | if (IS_GEN8(dev_priv)) |
b5321f30 | 11943 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
5a21b665 DV |
11944 | MI_SRM_LRM_GLOBAL_GTT); |
11945 | else | |
b5321f30 | 11946 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
5a21b665 | 11947 | MI_SRM_LRM_GLOBAL_GTT); |
b5321f30 | 11948 | intel_ring_emit_reg(ring, DERRMR); |
bde13ebd CW |
11949 | intel_ring_emit(ring, |
11950 | i915_ggtt_offset(req->engine->scratch) + 256); | |
5db94019 | 11951 | if (IS_GEN8(dev_priv)) { |
b5321f30 CW |
11952 | intel_ring_emit(ring, 0); |
11953 | intel_ring_emit(ring, MI_NOOP); | |
5a21b665 DV |
11954 | } |
11955 | } | |
11956 | ||
b5321f30 | 11957 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
72618ebf | 11958 | intel_ring_emit(ring, fb->pitches[0] | |
bae781b2 | 11959 | intel_fb_modifier_to_tiling(fb->modifier)); |
b5321f30 CW |
11960 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
11961 | intel_ring_emit(ring, (MI_NOOP)); | |
5a21b665 DV |
11962 | |
11963 | return 0; | |
11964 | } | |
11965 | ||
11966 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11967 | struct drm_i915_gem_object *obj) | |
11968 | { | |
11969 | /* | |
11970 | * This is not being used for older platforms, because | |
11971 | * non-availability of flip done interrupt forces us to use | |
11972 | * CS flips. Older platforms derive flip done using some clever | |
11973 | * tricks involving the flip_pending status bits and vblank irqs. | |
11974 | * So using MMIO flips there would disrupt this mechanism. | |
11975 | */ | |
11976 | ||
11977 | if (engine == NULL) | |
11978 | return true; | |
11979 | ||
11980 | if (INTEL_GEN(engine->i915) < 5) | |
11981 | return false; | |
11982 | ||
11983 | if (i915.use_mmio_flip < 0) | |
11984 | return false; | |
11985 | else if (i915.use_mmio_flip > 0) | |
11986 | return true; | |
11987 | else if (i915.enable_execlists) | |
11988 | return true; | |
c37efb99 | 11989 | |
d07f0e59 | 11990 | return engine != i915_gem_object_last_write_engine(obj); |
5a21b665 DV |
11991 | } |
11992 | ||
11993 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11994 | unsigned int rotation, | |
11995 | struct intel_flip_work *work) | |
11996 | { | |
11997 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11998 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11999 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
12000 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 12001 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
12002 | |
12003 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
12004 | ctl &= ~PLANE_CTL_TILED_MASK; | |
bae781b2 | 12005 | switch (fb->modifier) { |
5a21b665 DV |
12006 | case DRM_FORMAT_MOD_NONE: |
12007 | break; | |
12008 | case I915_FORMAT_MOD_X_TILED: | |
12009 | ctl |= PLANE_CTL_TILED_X; | |
12010 | break; | |
12011 | case I915_FORMAT_MOD_Y_TILED: | |
12012 | ctl |= PLANE_CTL_TILED_Y; | |
12013 | break; | |
12014 | case I915_FORMAT_MOD_Yf_TILED: | |
12015 | ctl |= PLANE_CTL_TILED_YF; | |
12016 | break; | |
12017 | default: | |
bae781b2 | 12018 | MISSING_CASE(fb->modifier); |
5a21b665 DV |
12019 | } |
12020 | ||
5a21b665 DV |
12021 | /* |
12022 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
12023 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
12024 | */ | |
12025 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
12026 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
12027 | ||
12028 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
12029 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
12030 | } | |
12031 | ||
12032 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
12033 | struct intel_flip_work *work) | |
12034 | { | |
12035 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 12036 | struct drm_i915_private *dev_priv = to_i915(dev); |
72618ebf | 12037 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
5a21b665 DV |
12038 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
12039 | u32 dspcntr; | |
12040 | ||
12041 | dspcntr = I915_READ(reg); | |
12042 | ||
bae781b2 | 12043 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
5a21b665 DV |
12044 | dspcntr |= DISPPLANE_TILED; |
12045 | else | |
12046 | dspcntr &= ~DISPPLANE_TILED; | |
12047 | ||
12048 | I915_WRITE(reg, dspcntr); | |
12049 | ||
12050 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
12051 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
12052 | } | |
12053 | ||
12054 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
12055 | { | |
12056 | struct intel_flip_work *work = | |
12057 | container_of(w, struct intel_flip_work, mmio_work); | |
12058 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
12059 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
12060 | struct intel_framebuffer *intel_fb = | |
12061 | to_intel_framebuffer(crtc->base.primary->fb); | |
12062 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
12063 | ||
d07f0e59 | 12064 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); |
5a21b665 DV |
12065 | |
12066 | intel_pipe_update_start(crtc); | |
12067 | ||
12068 | if (INTEL_GEN(dev_priv) >= 9) | |
12069 | skl_do_mmio_flip(crtc, work->rotation, work); | |
12070 | else | |
12071 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
12072 | ilk_do_mmio_flip(crtc, work); | |
12073 | ||
12074 | intel_pipe_update_end(crtc, work); | |
12075 | } | |
12076 | ||
12077 | static int intel_default_queue_flip(struct drm_device *dev, | |
12078 | struct drm_crtc *crtc, | |
12079 | struct drm_framebuffer *fb, | |
12080 | struct drm_i915_gem_object *obj, | |
12081 | struct drm_i915_gem_request *req, | |
12082 | uint32_t flags) | |
12083 | { | |
12084 | return -ENODEV; | |
12085 | } | |
12086 | ||
12087 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
12088 | struct intel_crtc *intel_crtc, | |
12089 | struct intel_flip_work *work) | |
12090 | { | |
12091 | u32 addr, vblank; | |
12092 | ||
12093 | if (!atomic_read(&work->pending)) | |
12094 | return false; | |
12095 | ||
12096 | smp_rmb(); | |
12097 | ||
12098 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
12099 | if (work->flip_ready_vblank == 0) { | |
12100 | if (work->flip_queued_req && | |
f69a02c9 | 12101 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
12102 | return false; |
12103 | ||
12104 | work->flip_ready_vblank = vblank; | |
12105 | } | |
12106 | ||
12107 | if (vblank - work->flip_ready_vblank < 3) | |
12108 | return false; | |
12109 | ||
12110 | /* Potential stall - if we see that the flip has happened, | |
12111 | * assume a missed interrupt. */ | |
12112 | if (INTEL_GEN(dev_priv) >= 4) | |
12113 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
12114 | else | |
12115 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
12116 | ||
12117 | /* There is a potential issue here with a false positive after a flip | |
12118 | * to the same address. We could address this by checking for a | |
12119 | * non-incrementing frame counter. | |
12120 | */ | |
12121 | return addr == work->gtt_offset; | |
12122 | } | |
12123 | ||
12124 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
12125 | { | |
91c8a326 | 12126 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 12127 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
12128 | struct intel_flip_work *work; |
12129 | ||
12130 | WARN_ON(!in_interrupt()); | |
12131 | ||
12132 | if (crtc == NULL) | |
12133 | return; | |
12134 | ||
12135 | spin_lock(&dev->event_lock); | |
e2af48c6 | 12136 | work = crtc->flip_work; |
5a21b665 DV |
12137 | |
12138 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 12139 | __pageflip_stall_check_cs(dev_priv, crtc, work)) { |
5a21b665 DV |
12140 | WARN_ONCE(1, |
12141 | "Kicking stuck page flip: queued at %d, now %d\n", | |
e2af48c6 VS |
12142 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); |
12143 | page_flip_completed(crtc); | |
5a21b665 DV |
12144 | work = NULL; |
12145 | } | |
12146 | ||
12147 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 12148 | intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) |
5a21b665 DV |
12149 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
12150 | spin_unlock(&dev->event_lock); | |
12151 | } | |
12152 | ||
12153 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
12154 | struct drm_framebuffer *fb, | |
12155 | struct drm_pending_vblank_event *event, | |
12156 | uint32_t page_flip_flags) | |
12157 | { | |
12158 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 12159 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
12160 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
12161 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12162 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12163 | struct drm_plane *primary = crtc->primary; | |
12164 | enum pipe pipe = intel_crtc->pipe; | |
12165 | struct intel_flip_work *work; | |
12166 | struct intel_engine_cs *engine; | |
12167 | bool mmio_flip; | |
8e637178 | 12168 | struct drm_i915_gem_request *request; |
058d88c4 | 12169 | struct i915_vma *vma; |
5a21b665 DV |
12170 | int ret; |
12171 | ||
12172 | /* | |
12173 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
12174 | * check to be safe. In the future we may enable pageflipping from | |
12175 | * a disabled primary plane. | |
12176 | */ | |
12177 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
12178 | return -EBUSY; | |
12179 | ||
12180 | /* Can't change pixel format via MI display flips. */ | |
12181 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
12182 | return -EINVAL; | |
12183 | ||
12184 | /* | |
12185 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
12186 | * Note that pitch changes could also affect these register. | |
12187 | */ | |
6315b5d3 | 12188 | if (INTEL_GEN(dev_priv) > 3 && |
5a21b665 DV |
12189 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
12190 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
12191 | return -EINVAL; | |
12192 | ||
12193 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
12194 | goto out_hang; | |
12195 | ||
12196 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
12197 | if (work == NULL) | |
12198 | return -ENOMEM; | |
12199 | ||
12200 | work->event = event; | |
12201 | work->crtc = crtc; | |
12202 | work->old_fb = old_fb; | |
12203 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
12204 | ||
12205 | ret = drm_crtc_vblank_get(crtc); | |
12206 | if (ret) | |
12207 | goto free_work; | |
12208 | ||
12209 | /* We borrow the event spin lock for protecting flip_work */ | |
12210 | spin_lock_irq(&dev->event_lock); | |
12211 | if (intel_crtc->flip_work) { | |
12212 | /* Before declaring the flip queue wedged, check if | |
12213 | * the hardware completed the operation behind our backs. | |
12214 | */ | |
12215 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
12216 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
12217 | page_flip_completed(intel_crtc); | |
12218 | } else { | |
12219 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
12220 | spin_unlock_irq(&dev->event_lock); | |
12221 | ||
12222 | drm_crtc_vblank_put(crtc); | |
12223 | kfree(work); | |
12224 | return -EBUSY; | |
12225 | } | |
12226 | } | |
12227 | intel_crtc->flip_work = work; | |
12228 | spin_unlock_irq(&dev->event_lock); | |
12229 | ||
12230 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
12231 | flush_workqueue(dev_priv->wq); | |
12232 | ||
12233 | /* Reference the objects for the scheduled work. */ | |
12234 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
12235 | |
12236 | crtc->primary->fb = fb; | |
12237 | update_state_fb(crtc->primary); | |
faf68d92 | 12238 | |
25dc556a | 12239 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
12240 | |
12241 | ret = i915_mutex_lock_interruptible(dev); | |
12242 | if (ret) | |
12243 | goto cleanup; | |
12244 | ||
8af29b0c CW |
12245 | intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); |
12246 | if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) { | |
5a21b665 | 12247 | ret = -EIO; |
ddbb271a | 12248 | goto unlock; |
5a21b665 DV |
12249 | } |
12250 | ||
12251 | atomic_inc(&intel_crtc->unpin_work_count); | |
12252 | ||
9beb5fea | 12253 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
5a21b665 DV |
12254 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
12255 | ||
920a14b2 | 12256 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3b3f1650 | 12257 | engine = dev_priv->engine[BCS]; |
bae781b2 | 12258 | if (fb->modifier != old_fb->modifier) |
5a21b665 DV |
12259 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
12260 | engine = NULL; | |
fd6b8f43 | 12261 | } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { |
3b3f1650 | 12262 | engine = dev_priv->engine[BCS]; |
6315b5d3 | 12263 | } else if (INTEL_GEN(dev_priv) >= 7) { |
d07f0e59 | 12264 | engine = i915_gem_object_last_write_engine(obj); |
5a21b665 | 12265 | if (engine == NULL || engine->id != RCS) |
3b3f1650 | 12266 | engine = dev_priv->engine[BCS]; |
5a21b665 | 12267 | } else { |
3b3f1650 | 12268 | engine = dev_priv->engine[RCS]; |
5a21b665 DV |
12269 | } |
12270 | ||
12271 | mmio_flip = use_mmio_flip(engine, obj); | |
12272 | ||
058d88c4 CW |
12273 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
12274 | if (IS_ERR(vma)) { | |
12275 | ret = PTR_ERR(vma); | |
5a21b665 | 12276 | goto cleanup_pending; |
058d88c4 | 12277 | } |
5a21b665 | 12278 | |
6687c906 | 12279 | work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation); |
5a21b665 DV |
12280 | work->gtt_offset += intel_crtc->dspaddr_offset; |
12281 | work->rotation = crtc->primary->state->rotation; | |
12282 | ||
1f061316 PZ |
12283 | /* |
12284 | * There's the potential that the next frame will not be compatible with | |
12285 | * FBC, so we want to call pre_update() before the actual page flip. | |
12286 | * The problem is that pre_update() caches some information about the fb | |
12287 | * object, so we want to do this only after the object is pinned. Let's | |
12288 | * be on the safe side and do this immediately before scheduling the | |
12289 | * flip. | |
12290 | */ | |
12291 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
12292 | to_intel_plane_state(primary->state)); | |
12293 | ||
5a21b665 DV |
12294 | if (mmio_flip) { |
12295 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
6277c8d0 | 12296 | queue_work(system_unbound_wq, &work->mmio_work); |
5a21b665 | 12297 | } else { |
e8a9c58f CW |
12298 | request = i915_gem_request_alloc(engine, |
12299 | dev_priv->kernel_context); | |
8e637178 CW |
12300 | if (IS_ERR(request)) { |
12301 | ret = PTR_ERR(request); | |
12302 | goto cleanup_unpin; | |
12303 | } | |
12304 | ||
a2bc4695 | 12305 | ret = i915_gem_request_await_object(request, obj, false); |
8e637178 CW |
12306 | if (ret) |
12307 | goto cleanup_request; | |
12308 | ||
5a21b665 DV |
12309 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
12310 | page_flip_flags); | |
12311 | if (ret) | |
8e637178 | 12312 | goto cleanup_request; |
5a21b665 DV |
12313 | |
12314 | intel_mark_page_flip_active(intel_crtc, work); | |
12315 | ||
8e637178 | 12316 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
12317 | i915_add_request_no_flush(request); |
12318 | } | |
12319 | ||
92117f0b | 12320 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); |
5a21b665 DV |
12321 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, |
12322 | to_intel_plane(primary)->frontbuffer_bit); | |
12323 | mutex_unlock(&dev->struct_mutex); | |
12324 | ||
5748b6a1 | 12325 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
12326 | to_intel_plane(primary)->frontbuffer_bit); |
12327 | ||
12328 | trace_i915_flip_request(intel_crtc->plane, obj); | |
12329 | ||
12330 | return 0; | |
12331 | ||
8e637178 CW |
12332 | cleanup_request: |
12333 | i915_add_request_no_flush(request); | |
5a21b665 DV |
12334 | cleanup_unpin: |
12335 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
12336 | cleanup_pending: | |
5a21b665 | 12337 | atomic_dec(&intel_crtc->unpin_work_count); |
ddbb271a | 12338 | unlock: |
5a21b665 DV |
12339 | mutex_unlock(&dev->struct_mutex); |
12340 | cleanup: | |
12341 | crtc->primary->fb = old_fb; | |
12342 | update_state_fb(crtc->primary); | |
12343 | ||
f0cd5182 | 12344 | i915_gem_object_put(obj); |
5a21b665 DV |
12345 | drm_framebuffer_unreference(work->old_fb); |
12346 | ||
12347 | spin_lock_irq(&dev->event_lock); | |
12348 | intel_crtc->flip_work = NULL; | |
12349 | spin_unlock_irq(&dev->event_lock); | |
12350 | ||
12351 | drm_crtc_vblank_put(crtc); | |
12352 | free_work: | |
12353 | kfree(work); | |
12354 | ||
12355 | if (ret == -EIO) { | |
12356 | struct drm_atomic_state *state; | |
12357 | struct drm_plane_state *plane_state; | |
12358 | ||
12359 | out_hang: | |
12360 | state = drm_atomic_state_alloc(dev); | |
12361 | if (!state) | |
12362 | return -ENOMEM; | |
12363 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
12364 | ||
12365 | retry: | |
12366 | plane_state = drm_atomic_get_plane_state(state, primary); | |
12367 | ret = PTR_ERR_OR_ZERO(plane_state); | |
12368 | if (!ret) { | |
12369 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
12370 | ||
12371 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
12372 | if (!ret) | |
12373 | ret = drm_atomic_commit(state); | |
12374 | } | |
12375 | ||
12376 | if (ret == -EDEADLK) { | |
12377 | drm_modeset_backoff(state->acquire_ctx); | |
12378 | drm_atomic_state_clear(state); | |
12379 | goto retry; | |
12380 | } | |
12381 | ||
0853695c | 12382 | drm_atomic_state_put(state); |
5a21b665 DV |
12383 | |
12384 | if (ret == 0 && event) { | |
12385 | spin_lock_irq(&dev->event_lock); | |
12386 | drm_crtc_send_vblank_event(crtc, event); | |
12387 | spin_unlock_irq(&dev->event_lock); | |
12388 | } | |
12389 | } | |
12390 | return ret; | |
12391 | } | |
12392 | ||
12393 | ||
12394 | /** | |
12395 | * intel_wm_need_update - Check whether watermarks need updating | |
12396 | * @plane: drm plane | |
12397 | * @state: new plane state | |
12398 | * | |
12399 | * Check current plane state versus the new one to determine whether | |
12400 | * watermarks need to be recalculated. | |
12401 | * | |
12402 | * Returns true or false. | |
12403 | */ | |
12404 | static bool intel_wm_need_update(struct drm_plane *plane, | |
12405 | struct drm_plane_state *state) | |
12406 | { | |
12407 | struct intel_plane_state *new = to_intel_plane_state(state); | |
12408 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
12409 | ||
12410 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 12411 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
12412 | return true; |
12413 | ||
12414 | if (!cur->base.fb || !new->base.fb) | |
12415 | return false; | |
12416 | ||
bae781b2 | 12417 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 12418 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
12419 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
12420 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
12421 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
12422 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
12423 | return true; |
12424 | ||
12425 | return false; | |
12426 | } | |
12427 | ||
12428 | static bool needs_scaling(struct intel_plane_state *state) | |
12429 | { | |
936e71e3 VS |
12430 | int src_w = drm_rect_width(&state->base.src) >> 16; |
12431 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
12432 | int dst_w = drm_rect_width(&state->base.dst); | |
12433 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
12434 | |
12435 | return (src_w != dst_w || src_h != dst_h); | |
12436 | } | |
d21fbe87 | 12437 | |
da20eabd ML |
12438 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
12439 | struct drm_plane_state *plane_state) | |
12440 | { | |
ab1d3a0e | 12441 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
12442 | struct drm_crtc *crtc = crtc_state->crtc; |
12443 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12444 | struct drm_plane *plane = plane_state->plane; | |
12445 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 12446 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
12447 | struct intel_plane_state *old_plane_state = |
12448 | to_intel_plane_state(plane->state); | |
da20eabd ML |
12449 | bool mode_changed = needs_modeset(crtc_state); |
12450 | bool was_crtc_enabled = crtc->state->active; | |
12451 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
12452 | bool turn_off, turn_on, visible, was_visible; |
12453 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 12454 | int ret; |
da20eabd | 12455 | |
55b8f2a7 | 12456 | if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
12457 | ret = skl_update_scaler_plane( |
12458 | to_intel_crtc_state(crtc_state), | |
12459 | to_intel_plane_state(plane_state)); | |
12460 | if (ret) | |
12461 | return ret; | |
12462 | } | |
12463 | ||
936e71e3 VS |
12464 | was_visible = old_plane_state->base.visible; |
12465 | visible = to_intel_plane_state(plane_state)->base.visible; | |
da20eabd ML |
12466 | |
12467 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
12468 | was_visible = false; | |
12469 | ||
35c08f43 ML |
12470 | /* |
12471 | * Visibility is calculated as if the crtc was on, but | |
12472 | * after scaler setup everything depends on it being off | |
12473 | * when the crtc isn't active. | |
f818ffea VS |
12474 | * |
12475 | * FIXME this is wrong for watermarks. Watermarks should also | |
12476 | * be computed as if the pipe would be active. Perhaps move | |
12477 | * per-plane wm computation to the .check_plane() hook, and | |
12478 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
12479 | */ |
12480 | if (!is_crtc_enabled) | |
936e71e3 | 12481 | to_intel_plane_state(plane_state)->base.visible = visible = false; |
da20eabd ML |
12482 | |
12483 | if (!was_visible && !visible) | |
12484 | return 0; | |
12485 | ||
e8861675 ML |
12486 | if (fb != old_plane_state->base.fb) |
12487 | pipe_config->fb_changed = true; | |
12488 | ||
da20eabd ML |
12489 | turn_off = was_visible && (!visible || mode_changed); |
12490 | turn_on = visible && (!was_visible || mode_changed); | |
12491 | ||
72660ce0 | 12492 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
12493 | intel_crtc->base.base.id, |
12494 | intel_crtc->base.name, | |
72660ce0 VS |
12495 | plane->base.id, plane->name, |
12496 | fb ? fb->base.id : -1); | |
da20eabd | 12497 | |
72660ce0 VS |
12498 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
12499 | plane->base.id, plane->name, | |
12500 | was_visible, visible, | |
da20eabd ML |
12501 | turn_off, turn_on, mode_changed); |
12502 | ||
caed361d VS |
12503 | if (turn_on) { |
12504 | pipe_config->update_wm_pre = true; | |
12505 | ||
12506 | /* must disable cxsr around plane enable/disable */ | |
12507 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
12508 | pipe_config->disable_cxsr = true; | |
12509 | } else if (turn_off) { | |
12510 | pipe_config->update_wm_post = true; | |
92826fcd | 12511 | |
852eb00d | 12512 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 12513 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 12514 | pipe_config->disable_cxsr = true; |
852eb00d | 12515 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
12516 | /* FIXME bollocks */ |
12517 | pipe_config->update_wm_pre = true; | |
12518 | pipe_config->update_wm_post = true; | |
852eb00d | 12519 | } |
da20eabd | 12520 | |
ed4a6a7c | 12521 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d | 12522 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
6315b5d3 | 12523 | INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks) |
ed4a6a7c MR |
12524 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
12525 | ||
8be6ca85 | 12526 | if (visible || was_visible) |
cd202f69 | 12527 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 12528 | |
31ae71fc ML |
12529 | /* |
12530 | * WaCxSRDisabledForSpriteScaling:ivb | |
12531 | * | |
12532 | * cstate->update_wm was already set above, so this flag will | |
12533 | * take effect when we commit and program watermarks. | |
12534 | */ | |
fd6b8f43 | 12535 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
12536 | needs_scaling(to_intel_plane_state(plane_state)) && |
12537 | !needs_scaling(old_plane_state)) | |
12538 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 12539 | |
da20eabd ML |
12540 | return 0; |
12541 | } | |
12542 | ||
6d3a1ce7 ML |
12543 | static bool encoders_cloneable(const struct intel_encoder *a, |
12544 | const struct intel_encoder *b) | |
12545 | { | |
12546 | /* masks could be asymmetric, so check both ways */ | |
12547 | return a == b || (a->cloneable & (1 << b->type) && | |
12548 | b->cloneable & (1 << a->type)); | |
12549 | } | |
12550 | ||
12551 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12552 | struct intel_crtc *crtc, | |
12553 | struct intel_encoder *encoder) | |
12554 | { | |
12555 | struct intel_encoder *source_encoder; | |
12556 | struct drm_connector *connector; | |
12557 | struct drm_connector_state *connector_state; | |
12558 | int i; | |
12559 | ||
12560 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12561 | if (connector_state->crtc != &crtc->base) | |
12562 | continue; | |
12563 | ||
12564 | source_encoder = | |
12565 | to_intel_encoder(connector_state->best_encoder); | |
12566 | if (!encoders_cloneable(encoder, source_encoder)) | |
12567 | return false; | |
12568 | } | |
12569 | ||
12570 | return true; | |
12571 | } | |
12572 | ||
6d3a1ce7 ML |
12573 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
12574 | struct drm_crtc_state *crtc_state) | |
12575 | { | |
cf5a15be | 12576 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12577 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 12578 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12579 | struct intel_crtc_state *pipe_config = |
12580 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12581 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12582 | int ret; |
6d3a1ce7 ML |
12583 | bool mode_changed = needs_modeset(crtc_state); |
12584 | ||
852eb00d | 12585 | if (mode_changed && !crtc_state->active) |
caed361d | 12586 | pipe_config->update_wm_post = true; |
eddfcbcd | 12587 | |
ad421372 ML |
12588 | if (mode_changed && crtc_state->enable && |
12589 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 12590 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
12591 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12592 | pipe_config); | |
12593 | if (ret) | |
12594 | return ret; | |
12595 | } | |
12596 | ||
82cf435b LL |
12597 | if (crtc_state->color_mgmt_changed) { |
12598 | ret = intel_color_check(crtc, crtc_state); | |
12599 | if (ret) | |
12600 | return ret; | |
e7852a4b LL |
12601 | |
12602 | /* | |
12603 | * Changing color management on Intel hardware is | |
12604 | * handled as part of planes update. | |
12605 | */ | |
12606 | crtc_state->planes_changed = true; | |
82cf435b LL |
12607 | } |
12608 | ||
e435d6e5 | 12609 | ret = 0; |
86c8bbbe | 12610 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12611 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12612 | if (ret) { |
12613 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12614 | return ret; | |
12615 | } | |
12616 | } | |
12617 | ||
12618 | if (dev_priv->display.compute_intermediate_wm && | |
12619 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12620 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12621 | return 0; | |
12622 | ||
12623 | /* | |
12624 | * Calculate 'intermediate' watermarks that satisfy both the | |
12625 | * old state and the new state. We can program these | |
12626 | * immediately. | |
12627 | */ | |
6315b5d3 | 12628 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
12629 | intel_crtc, |
12630 | pipe_config); | |
12631 | if (ret) { | |
12632 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12633 | return ret; |
ed4a6a7c | 12634 | } |
e3d5457c VS |
12635 | } else if (dev_priv->display.compute_intermediate_wm) { |
12636 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12637 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12638 | } |
12639 | ||
6315b5d3 | 12640 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
12641 | if (mode_changed) |
12642 | ret = skl_update_scaler_crtc(pipe_config); | |
12643 | ||
12644 | if (!ret) | |
12645 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12646 | pipe_config); | |
12647 | } | |
12648 | ||
12649 | return ret; | |
6d3a1ce7 ML |
12650 | } |
12651 | ||
65b38e0d | 12652 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12653 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12654 | .atomic_begin = intel_begin_crtc_commit, |
12655 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12656 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12657 | }; |
12658 | ||
d29b2f9d ACO |
12659 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12660 | { | |
12661 | struct intel_connector *connector; | |
12662 | ||
12663 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12664 | if (connector->base.state->crtc) |
12665 | drm_connector_unreference(&connector->base); | |
12666 | ||
d29b2f9d ACO |
12667 | if (connector->base.encoder) { |
12668 | connector->base.state->best_encoder = | |
12669 | connector->base.encoder; | |
12670 | connector->base.state->crtc = | |
12671 | connector->base.encoder->crtc; | |
8863dc7f DV |
12672 | |
12673 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12674 | } else { |
12675 | connector->base.state->best_encoder = NULL; | |
12676 | connector->base.state->crtc = NULL; | |
12677 | } | |
12678 | } | |
12679 | } | |
12680 | ||
050f7aeb | 12681 | static void |
eba905b2 | 12682 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12683 | struct intel_crtc_state *pipe_config) |
050f7aeb | 12684 | { |
6a2a5c5d | 12685 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
12686 | int bpp = pipe_config->pipe_bpp; |
12687 | ||
12688 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
12689 | connector->base.base.id, |
12690 | connector->base.name); | |
050f7aeb DV |
12691 | |
12692 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 12693 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 12694 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
12695 | bpp, info->bpc * 3); |
12696 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
12697 | } |
12698 | ||
196f954e | 12699 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 12700 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
12701 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
12702 | bpp); | |
12703 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
12704 | } |
12705 | } | |
12706 | ||
4e53c2e0 | 12707 | static int |
050f7aeb | 12708 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12709 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12710 | { |
9beb5fea | 12711 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 12712 | struct drm_atomic_state *state; |
da3ced29 ACO |
12713 | struct drm_connector *connector; |
12714 | struct drm_connector_state *connector_state; | |
1486017f | 12715 | int bpp, i; |
4e53c2e0 | 12716 | |
9beb5fea TU |
12717 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
12718 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 12719 | bpp = 10*3; |
9beb5fea | 12720 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
12721 | bpp = 12*3; |
12722 | else | |
12723 | bpp = 8*3; | |
12724 | ||
4e53c2e0 | 12725 | |
4e53c2e0 DV |
12726 | pipe_config->pipe_bpp = bpp; |
12727 | ||
1486017f ACO |
12728 | state = pipe_config->base.state; |
12729 | ||
4e53c2e0 | 12730 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12731 | for_each_connector_in_state(state, connector, connector_state, i) { |
12732 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12733 | continue; |
12734 | ||
da3ced29 ACO |
12735 | connected_sink_compute_bpp(to_intel_connector(connector), |
12736 | pipe_config); | |
4e53c2e0 DV |
12737 | } |
12738 | ||
12739 | return bpp; | |
12740 | } | |
12741 | ||
644db711 DV |
12742 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12743 | { | |
12744 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12745 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12746 | mode->crtc_clock, |
644db711 DV |
12747 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12748 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12749 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12750 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12751 | } | |
12752 | ||
f6982332 TU |
12753 | static inline void |
12754 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 12755 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 12756 | { |
a4309657 TU |
12757 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
12758 | id, lane_count, | |
f6982332 TU |
12759 | m_n->gmch_m, m_n->gmch_n, |
12760 | m_n->link_m, m_n->link_n, m_n->tu); | |
12761 | } | |
12762 | ||
c0b03411 | 12763 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12764 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12765 | const char *context) |
12766 | { | |
6a60cd87 | 12767 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 12768 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
12769 | struct drm_plane *plane; |
12770 | struct intel_plane *intel_plane; | |
12771 | struct intel_plane_state *state; | |
12772 | struct drm_framebuffer *fb; | |
12773 | ||
66766e4f TU |
12774 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
12775 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 12776 | |
2c89429e TU |
12777 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
12778 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 12779 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
12780 | |
12781 | if (pipe_config->has_pch_encoder) | |
12782 | intel_dump_m_n_config(pipe_config, "fdi", | |
12783 | pipe_config->fdi_lanes, | |
12784 | &pipe_config->fdi_m_n); | |
f6982332 TU |
12785 | |
12786 | if (intel_crtc_has_dp_encoder(pipe_config)) { | |
a4309657 TU |
12787 | intel_dump_m_n_config(pipe_config, "dp m_n", |
12788 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
12789 | if (pipe_config->has_drrs) |
12790 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
12791 | pipe_config->lane_count, | |
12792 | &pipe_config->dp_m2_n2); | |
f6982332 | 12793 | } |
b95af8be | 12794 | |
55072d19 | 12795 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 12796 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 12797 | |
c0b03411 | 12798 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12799 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12800 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12801 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12802 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
2c89429e TU |
12803 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n", |
12804 | pipe_config->port_clock, | |
37327abd | 12805 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
dd2f616d TU |
12806 | |
12807 | if (INTEL_GEN(dev_priv) >= 9) | |
12808 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
12809 | crtc->num_scalers, | |
12810 | pipe_config->scaler_state.scaler_users, | |
12811 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
12812 | |
12813 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
12814 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
12815 | pipe_config->gmch_pfit.control, | |
12816 | pipe_config->gmch_pfit.pgm_ratios, | |
12817 | pipe_config->gmch_pfit.lvds_border_bits); | |
12818 | else | |
12819 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
12820 | pipe_config->pch_pfit.pos, | |
12821 | pipe_config->pch_pfit.size, | |
08c4d7fc | 12822 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 12823 | |
2c89429e TU |
12824 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
12825 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 12826 | |
cc3f90f0 | 12827 | if (IS_GEN9_LP(dev_priv)) { |
c856052a | 12828 | DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12829 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12830 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 | 12831 | pipe_config->dpll_hw_state.ebb0, |
05712c15 | 12832 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12833 | pipe_config->dpll_hw_state.pll0, |
12834 | pipe_config->dpll_hw_state.pll1, | |
12835 | pipe_config->dpll_hw_state.pll2, | |
12836 | pipe_config->dpll_hw_state.pll3, | |
12837 | pipe_config->dpll_hw_state.pll6, | |
12838 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12839 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12840 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12841 | pipe_config->dpll_hw_state.pcsdw12); |
0853723b | 12842 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
c856052a | 12843 | DRM_DEBUG_KMS("dpll_hw_state: " |
415ff0f6 | 12844 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", |
415ff0f6 TU |
12845 | pipe_config->dpll_hw_state.ctrl1, |
12846 | pipe_config->dpll_hw_state.cfgcr1, | |
12847 | pipe_config->dpll_hw_state.cfgcr2); | |
4f8036a2 | 12848 | } else if (HAS_DDI(dev_priv)) { |
c856052a | 12849 | DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
00490c22 ML |
12850 | pipe_config->dpll_hw_state.wrpll, |
12851 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12852 | } else { |
12853 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12854 | "fp0: 0x%x, fp1: 0x%x\n", | |
12855 | pipe_config->dpll_hw_state.dpll, | |
12856 | pipe_config->dpll_hw_state.dpll_md, | |
12857 | pipe_config->dpll_hw_state.fp0, | |
12858 | pipe_config->dpll_hw_state.fp1); | |
12859 | } | |
12860 | ||
6a60cd87 CK |
12861 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12862 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 12863 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
12864 | intel_plane = to_intel_plane(plane); |
12865 | if (intel_plane->pipe != crtc->pipe) | |
12866 | continue; | |
12867 | ||
12868 | state = to_intel_plane_state(plane->state); | |
12869 | fb = state->base.fb; | |
12870 | if (!fb) { | |
1d577e02 VS |
12871 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12872 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12873 | continue; |
12874 | } | |
12875 | ||
dd2f616d TU |
12876 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
12877 | plane->base.id, plane->name, | |
b3c11ac2 EE |
12878 | fb->base.id, fb->width, fb->height, |
12879 | drm_get_format_name(fb->pixel_format, &format_name)); | |
dd2f616d TU |
12880 | if (INTEL_GEN(dev_priv) >= 9) |
12881 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
12882 | state->scaler_id, | |
12883 | state->base.src.x1 >> 16, | |
12884 | state->base.src.y1 >> 16, | |
12885 | drm_rect_width(&state->base.src) >> 16, | |
12886 | drm_rect_height(&state->base.src) >> 16, | |
12887 | state->base.dst.x1, state->base.dst.y1, | |
12888 | drm_rect_width(&state->base.dst), | |
12889 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 12890 | } |
c0b03411 DV |
12891 | } |
12892 | ||
5448a00d | 12893 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12894 | { |
5448a00d | 12895 | struct drm_device *dev = state->dev; |
da3ced29 | 12896 | struct drm_connector *connector; |
00f0b378 | 12897 | unsigned int used_ports = 0; |
477321e0 | 12898 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
12899 | |
12900 | /* | |
12901 | * Walk the connector list instead of the encoder | |
12902 | * list to detect the problem on ddi platforms | |
12903 | * where there's just one encoder per digital port. | |
12904 | */ | |
0bff4858 VS |
12905 | drm_for_each_connector(connector, dev) { |
12906 | struct drm_connector_state *connector_state; | |
12907 | struct intel_encoder *encoder; | |
12908 | ||
12909 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12910 | if (!connector_state) | |
12911 | connector_state = connector->state; | |
12912 | ||
5448a00d | 12913 | if (!connector_state->best_encoder) |
00f0b378 VS |
12914 | continue; |
12915 | ||
5448a00d ACO |
12916 | encoder = to_intel_encoder(connector_state->best_encoder); |
12917 | ||
12918 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12919 | |
12920 | switch (encoder->type) { | |
12921 | unsigned int port_mask; | |
12922 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 12923 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 12924 | break; |
cca0502b | 12925 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
12926 | case INTEL_OUTPUT_HDMI: |
12927 | case INTEL_OUTPUT_EDP: | |
12928 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12929 | ||
12930 | /* the same port mustn't appear more than once */ | |
12931 | if (used_ports & port_mask) | |
12932 | return false; | |
12933 | ||
12934 | used_ports |= port_mask; | |
477321e0 VS |
12935 | break; |
12936 | case INTEL_OUTPUT_DP_MST: | |
12937 | used_mst_ports |= | |
12938 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
12939 | break; | |
00f0b378 VS |
12940 | default: |
12941 | break; | |
12942 | } | |
12943 | } | |
12944 | ||
477321e0 VS |
12945 | /* can't mix MST and SST/HDMI on the same port */ |
12946 | if (used_ports & used_mst_ports) | |
12947 | return false; | |
12948 | ||
00f0b378 VS |
12949 | return true; |
12950 | } | |
12951 | ||
83a57153 ACO |
12952 | static void |
12953 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12954 | { | |
12955 | struct drm_crtc_state tmp_state; | |
663a3640 | 12956 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12957 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12958 | struct intel_shared_dpll *shared_dpll; |
c4e2d043 | 12959 | bool force_thru; |
83a57153 | 12960 | |
7546a384 ACO |
12961 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12962 | * kzalloc'd. Code that depends on any field being zero should be | |
12963 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12964 | * only fields that are know to not cause problems are preserved. */ | |
12965 | ||
83a57153 | 12966 | tmp_state = crtc_state->base; |
663a3640 | 12967 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12968 | shared_dpll = crtc_state->shared_dpll; |
12969 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 12970 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12971 | |
83a57153 | 12972 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12973 | |
83a57153 | 12974 | crtc_state->base = tmp_state; |
663a3640 | 12975 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12976 | crtc_state->shared_dpll = shared_dpll; |
12977 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 12978 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12979 | } |
12980 | ||
548ee15b | 12981 | static int |
b8cecdf5 | 12982 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12983 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12984 | { |
b359283a | 12985 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12986 | struct intel_encoder *encoder; |
da3ced29 | 12987 | struct drm_connector *connector; |
0b901879 | 12988 | struct drm_connector_state *connector_state; |
d328c9d7 | 12989 | int base_bpp, ret = -EINVAL; |
0b901879 | 12990 | int i; |
e29c22c0 | 12991 | bool retry = true; |
ee7b9f93 | 12992 | |
83a57153 | 12993 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12994 | |
e143a21c DV |
12995 | pipe_config->cpu_transcoder = |
12996 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12997 | |
2960bc9c ID |
12998 | /* |
12999 | * Sanitize sync polarity flags based on requested ones. If neither | |
13000 | * positive or negative polarity is requested, treat this as meaning | |
13001 | * negative polarity. | |
13002 | */ | |
2d112de7 | 13003 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 13004 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 13005 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 13006 | |
2d112de7 | 13007 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 13008 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 13009 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 13010 | |
d328c9d7 DV |
13011 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
13012 | pipe_config); | |
13013 | if (base_bpp < 0) | |
4e53c2e0 DV |
13014 | goto fail; |
13015 | ||
e41a56be VS |
13016 | /* |
13017 | * Determine the real pipe dimensions. Note that stereo modes can | |
13018 | * increase the actual pipe size due to the frame doubling and | |
13019 | * insertion of additional space for blanks between the frame. This | |
13020 | * is stored in the crtc timings. We use the requested mode to do this | |
13021 | * computation to clearly distinguish it from the adjusted mode, which | |
13022 | * can be changed by the connectors in the below retry loop. | |
13023 | */ | |
2d112de7 | 13024 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
13025 | &pipe_config->pipe_src_w, |
13026 | &pipe_config->pipe_src_h); | |
e41a56be | 13027 | |
253c84c8 VS |
13028 | for_each_connector_in_state(state, connector, connector_state, i) { |
13029 | if (connector_state->crtc != crtc) | |
13030 | continue; | |
13031 | ||
13032 | encoder = to_intel_encoder(connector_state->best_encoder); | |
13033 | ||
e25148d0 VS |
13034 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
13035 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
13036 | goto fail; | |
13037 | } | |
13038 | ||
253c84c8 VS |
13039 | /* |
13040 | * Determine output_types before calling the .compute_config() | |
13041 | * hooks so that the hooks can use this information safely. | |
13042 | */ | |
13043 | pipe_config->output_types |= 1 << encoder->type; | |
13044 | } | |
13045 | ||
e29c22c0 | 13046 | encoder_retry: |
ef1b460d | 13047 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 13048 | pipe_config->port_clock = 0; |
ef1b460d | 13049 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 13050 | |
135c81b8 | 13051 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
13052 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
13053 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 13054 | |
7758a113 DV |
13055 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
13056 | * adjust it according to limitations or connector properties, and also | |
13057 | * a chance to reject the mode entirely. | |
47f1c6c9 | 13058 | */ |
da3ced29 | 13059 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 13060 | if (connector_state->crtc != crtc) |
7758a113 | 13061 | continue; |
7ae89233 | 13062 | |
0b901879 ACO |
13063 | encoder = to_intel_encoder(connector_state->best_encoder); |
13064 | ||
0a478c27 | 13065 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 13066 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
13067 | goto fail; |
13068 | } | |
ee7b9f93 | 13069 | } |
47f1c6c9 | 13070 | |
ff9a6750 DV |
13071 | /* Set default port clock if not overwritten by the encoder. Needs to be |
13072 | * done afterwards in case the encoder adjusts the mode. */ | |
13073 | if (!pipe_config->port_clock) | |
2d112de7 | 13074 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 13075 | * pipe_config->pixel_multiplier; |
ff9a6750 | 13076 | |
a43f6e0f | 13077 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 13078 | if (ret < 0) { |
7758a113 DV |
13079 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
13080 | goto fail; | |
ee7b9f93 | 13081 | } |
e29c22c0 DV |
13082 | |
13083 | if (ret == RETRY) { | |
13084 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
13085 | ret = -EINVAL; | |
13086 | goto fail; | |
13087 | } | |
13088 | ||
13089 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
13090 | retry = false; | |
13091 | goto encoder_retry; | |
13092 | } | |
13093 | ||
e8fa4270 DV |
13094 | /* Dithering seems to not pass-through bits correctly when it should, so |
13095 | * only enable it on 6bpc panels. */ | |
13096 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 13097 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 13098 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 13099 | |
7758a113 | 13100 | fail: |
548ee15b | 13101 | return ret; |
ee7b9f93 | 13102 | } |
47f1c6c9 | 13103 | |
ea9d758d | 13104 | static void |
4740b0f2 | 13105 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 13106 | { |
0a9ab303 ACO |
13107 | struct drm_crtc *crtc; |
13108 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 13109 | int i; |
ea9d758d | 13110 | |
7668851f | 13111 | /* Double check state. */ |
8a75d157 | 13112 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 13113 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
13114 | |
13115 | /* Update hwmode for vblank functions */ | |
13116 | if (crtc->state->active) | |
13117 | crtc->hwmode = crtc->state->adjusted_mode; | |
13118 | else | |
13119 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
13120 | |
13121 | /* | |
13122 | * Update legacy state to satisfy fbc code. This can | |
13123 | * be removed when fbc uses the atomic state. | |
13124 | */ | |
13125 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
13126 | struct drm_plane_state *plane_state = crtc->primary->state; | |
13127 | ||
13128 | crtc->primary->fb = plane_state->fb; | |
13129 | crtc->x = plane_state->src_x >> 16; | |
13130 | crtc->y = plane_state->src_y >> 16; | |
13131 | } | |
ea9d758d | 13132 | } |
ea9d758d DV |
13133 | } |
13134 | ||
3bd26263 | 13135 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 13136 | { |
3bd26263 | 13137 | int diff; |
f1f644dc JB |
13138 | |
13139 | if (clock1 == clock2) | |
13140 | return true; | |
13141 | ||
13142 | if (!clock1 || !clock2) | |
13143 | return false; | |
13144 | ||
13145 | diff = abs(clock1 - clock2); | |
13146 | ||
13147 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
13148 | return true; | |
13149 | ||
13150 | return false; | |
13151 | } | |
13152 | ||
cfb23ed6 ML |
13153 | static bool |
13154 | intel_compare_m_n(unsigned int m, unsigned int n, | |
13155 | unsigned int m2, unsigned int n2, | |
13156 | bool exact) | |
13157 | { | |
13158 | if (m == m2 && n == n2) | |
13159 | return true; | |
13160 | ||
13161 | if (exact || !m || !n || !m2 || !n2) | |
13162 | return false; | |
13163 | ||
13164 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
13165 | ||
31d10b57 ML |
13166 | if (n > n2) { |
13167 | while (n > n2) { | |
cfb23ed6 ML |
13168 | m2 <<= 1; |
13169 | n2 <<= 1; | |
13170 | } | |
31d10b57 ML |
13171 | } else if (n < n2) { |
13172 | while (n < n2) { | |
cfb23ed6 ML |
13173 | m <<= 1; |
13174 | n <<= 1; | |
13175 | } | |
13176 | } | |
13177 | ||
31d10b57 ML |
13178 | if (n != n2) |
13179 | return false; | |
13180 | ||
13181 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
13182 | } |
13183 | ||
13184 | static bool | |
13185 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
13186 | struct intel_link_m_n *m2_n2, | |
13187 | bool adjust) | |
13188 | { | |
13189 | if (m_n->tu == m2_n2->tu && | |
13190 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
13191 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
13192 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
13193 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
13194 | if (adjust) | |
13195 | *m2_n2 = *m_n; | |
13196 | ||
13197 | return true; | |
13198 | } | |
13199 | ||
13200 | return false; | |
13201 | } | |
13202 | ||
4e8048f8 TU |
13203 | static void __printf(3, 4) |
13204 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
13205 | { | |
13206 | char *level; | |
13207 | unsigned int category; | |
13208 | struct va_format vaf; | |
13209 | va_list args; | |
13210 | ||
13211 | if (adjust) { | |
13212 | level = KERN_DEBUG; | |
13213 | category = DRM_UT_KMS; | |
13214 | } else { | |
13215 | level = KERN_ERR; | |
13216 | category = DRM_UT_NONE; | |
13217 | } | |
13218 | ||
13219 | va_start(args, format); | |
13220 | vaf.fmt = format; | |
13221 | vaf.va = &args; | |
13222 | ||
13223 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
13224 | ||
13225 | va_end(args); | |
13226 | } | |
13227 | ||
0e8ffe1b | 13228 | static bool |
6315b5d3 | 13229 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 13230 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
13231 | struct intel_crtc_state *pipe_config, |
13232 | bool adjust) | |
0e8ffe1b | 13233 | { |
cfb23ed6 ML |
13234 | bool ret = true; |
13235 | ||
66e985c0 DV |
13236 | #define PIPE_CONF_CHECK_X(name) \ |
13237 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 13238 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
13239 | "(expected 0x%08x, found 0x%08x)\n", \ |
13240 | current_config->name, \ | |
13241 | pipe_config->name); \ | |
cfb23ed6 | 13242 | ret = false; \ |
66e985c0 DV |
13243 | } |
13244 | ||
08a24034 DV |
13245 | #define PIPE_CONF_CHECK_I(name) \ |
13246 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 13247 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
13248 | "(expected %i, found %i)\n", \ |
13249 | current_config->name, \ | |
13250 | pipe_config->name); \ | |
cfb23ed6 ML |
13251 | ret = false; \ |
13252 | } | |
13253 | ||
8106ddbd ACO |
13254 | #define PIPE_CONF_CHECK_P(name) \ |
13255 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 13256 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
13257 | "(expected %p, found %p)\n", \ |
13258 | current_config->name, \ | |
13259 | pipe_config->name); \ | |
13260 | ret = false; \ | |
13261 | } | |
13262 | ||
cfb23ed6 ML |
13263 | #define PIPE_CONF_CHECK_M_N(name) \ |
13264 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13265 | &pipe_config->name,\ | |
13266 | adjust)) { \ | |
4e8048f8 | 13267 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
13268 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
13269 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13270 | current_config->name.tu, \ | |
13271 | current_config->name.gmch_m, \ | |
13272 | current_config->name.gmch_n, \ | |
13273 | current_config->name.link_m, \ | |
13274 | current_config->name.link_n, \ | |
13275 | pipe_config->name.tu, \ | |
13276 | pipe_config->name.gmch_m, \ | |
13277 | pipe_config->name.gmch_n, \ | |
13278 | pipe_config->name.link_m, \ | |
13279 | pipe_config->name.link_n); \ | |
13280 | ret = false; \ | |
13281 | } | |
13282 | ||
55c561a7 DV |
13283 | /* This is required for BDW+ where there is only one set of registers for |
13284 | * switching between high and low RR. | |
13285 | * This macro can be used whenever a comparison has to be made between one | |
13286 | * hw state and multiple sw state variables. | |
13287 | */ | |
cfb23ed6 ML |
13288 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
13289 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13290 | &pipe_config->name, adjust) && \ | |
13291 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
13292 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 13293 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
13294 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
13295 | "or tu %i gmch %i/%i link %i/%i, " \ | |
13296 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13297 | current_config->name.tu, \ | |
13298 | current_config->name.gmch_m, \ | |
13299 | current_config->name.gmch_n, \ | |
13300 | current_config->name.link_m, \ | |
13301 | current_config->name.link_n, \ | |
13302 | current_config->alt_name.tu, \ | |
13303 | current_config->alt_name.gmch_m, \ | |
13304 | current_config->alt_name.gmch_n, \ | |
13305 | current_config->alt_name.link_m, \ | |
13306 | current_config->alt_name.link_n, \ | |
13307 | pipe_config->name.tu, \ | |
13308 | pipe_config->name.gmch_m, \ | |
13309 | pipe_config->name.gmch_n, \ | |
13310 | pipe_config->name.link_m, \ | |
13311 | pipe_config->name.link_n); \ | |
13312 | ret = false; \ | |
88adfff1 DV |
13313 | } |
13314 | ||
1bd1bd80 DV |
13315 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
13316 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
13317 | pipe_config_err(adjust, __stringify(name), \ |
13318 | "(%x) (expected %i, found %i)\n", \ | |
13319 | (mask), \ | |
1bd1bd80 DV |
13320 | current_config->name & (mask), \ |
13321 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 13322 | ret = false; \ |
1bd1bd80 DV |
13323 | } |
13324 | ||
5e550656 VS |
13325 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
13326 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 13327 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
13328 | "(expected %i, found %i)\n", \ |
13329 | current_config->name, \ | |
13330 | pipe_config->name); \ | |
cfb23ed6 | 13331 | ret = false; \ |
5e550656 VS |
13332 | } |
13333 | ||
bb760063 DV |
13334 | #define PIPE_CONF_QUIRK(quirk) \ |
13335 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
13336 | ||
eccb140b DV |
13337 | PIPE_CONF_CHECK_I(cpu_transcoder); |
13338 | ||
08a24034 DV |
13339 | PIPE_CONF_CHECK_I(has_pch_encoder); |
13340 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 13341 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 13342 | |
90a6b7b0 | 13343 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 13344 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 13345 | |
6315b5d3 | 13346 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
13347 | PIPE_CONF_CHECK_M_N(dp_m_n); |
13348 | ||
cfb23ed6 ML |
13349 | if (current_config->has_drrs) |
13350 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
13351 | } else | |
13352 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 13353 | |
253c84c8 | 13354 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 13355 | |
2d112de7 ACO |
13356 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
13357 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
13358 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
13359 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
13360 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
13361 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 13362 | |
2d112de7 ACO |
13363 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
13364 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
13365 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
13366 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
13367 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
13368 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 13369 | |
c93f54cf | 13370 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 13371 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 13372 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 13373 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 13374 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 13375 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 13376 | |
9ed109a7 DV |
13377 | PIPE_CONF_CHECK_I(has_audio); |
13378 | ||
2d112de7 | 13379 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
13380 | DRM_MODE_FLAG_INTERLACE); |
13381 | ||
bb760063 | 13382 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 13383 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13384 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 13385 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13386 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 13387 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13388 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 13389 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
13390 | DRM_MODE_FLAG_NVSYNC); |
13391 | } | |
045ac3b5 | 13392 | |
333b8ca8 | 13393 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 13394 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 13395 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 13396 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 13397 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 13398 | |
bfd16b2a ML |
13399 | if (!adjust) { |
13400 | PIPE_CONF_CHECK_I(pipe_src_w); | |
13401 | PIPE_CONF_CHECK_I(pipe_src_h); | |
13402 | ||
13403 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
13404 | if (current_config->pch_pfit.enabled) { | |
13405 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
13406 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
13407 | } | |
2fa2fe9a | 13408 | |
7aefe2b5 ML |
13409 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
13410 | } | |
a1b2278e | 13411 | |
e59150dc | 13412 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 13413 | if (IS_HASWELL(dev_priv)) |
e59150dc | 13414 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 13415 | |
282740f7 VS |
13416 | PIPE_CONF_CHECK_I(double_wide); |
13417 | ||
8106ddbd | 13418 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 13419 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 13420 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
13421 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
13422 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 13423 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 13424 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
13425 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
13426 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
13427 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 13428 | |
47eacbab VS |
13429 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
13430 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
13431 | ||
9beb5fea | 13432 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
13433 | PIPE_CONF_CHECK_I(pipe_bpp); |
13434 | ||
2d112de7 | 13435 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 13436 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 13437 | |
66e985c0 | 13438 | #undef PIPE_CONF_CHECK_X |
08a24034 | 13439 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 13440 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 13441 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 13442 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 13443 | #undef PIPE_CONF_QUIRK |
88adfff1 | 13444 | |
cfb23ed6 | 13445 | return ret; |
0e8ffe1b DV |
13446 | } |
13447 | ||
e3b247da VS |
13448 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
13449 | const struct intel_crtc_state *pipe_config) | |
13450 | { | |
13451 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 13452 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
13453 | &pipe_config->fdi_m_n); |
13454 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
13455 | ||
13456 | /* | |
13457 | * FDI already provided one idea for the dotclock. | |
13458 | * Yell if the encoder disagrees. | |
13459 | */ | |
13460 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
13461 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
13462 | fdi_dotclock, dotclock); | |
13463 | } | |
13464 | } | |
13465 | ||
c0ead703 ML |
13466 | static void verify_wm_state(struct drm_crtc *crtc, |
13467 | struct drm_crtc_state *new_state) | |
08db6652 | 13468 | { |
6315b5d3 | 13469 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 13470 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 13471 | struct skl_pipe_wm hw_wm, *sw_wm; |
13472 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
13473 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
13474 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13475 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 13476 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 13477 | |
6315b5d3 | 13478 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
13479 | return; |
13480 | ||
3de8a14c | 13481 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 13482 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 13483 | |
08db6652 DL |
13484 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
13485 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
13486 | ||
e7c84544 | 13487 | /* planes */ |
8b364b41 | 13488 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 13489 | hw_plane_wm = &hw_wm.planes[plane]; |
13490 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 13491 | |
3de8a14c | 13492 | /* Watermarks */ |
13493 | for (level = 0; level <= max_level; level++) { | |
13494 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
13495 | &sw_plane_wm->wm[level])) | |
13496 | continue; | |
13497 | ||
13498 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13499 | pipe_name(pipe), plane + 1, level, | |
13500 | sw_plane_wm->wm[level].plane_en, | |
13501 | sw_plane_wm->wm[level].plane_res_b, | |
13502 | sw_plane_wm->wm[level].plane_res_l, | |
13503 | hw_plane_wm->wm[level].plane_en, | |
13504 | hw_plane_wm->wm[level].plane_res_b, | |
13505 | hw_plane_wm->wm[level].plane_res_l); | |
13506 | } | |
08db6652 | 13507 | |
3de8a14c | 13508 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
13509 | &sw_plane_wm->trans_wm)) { | |
13510 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13511 | pipe_name(pipe), plane + 1, | |
13512 | sw_plane_wm->trans_wm.plane_en, | |
13513 | sw_plane_wm->trans_wm.plane_res_b, | |
13514 | sw_plane_wm->trans_wm.plane_res_l, | |
13515 | hw_plane_wm->trans_wm.plane_en, | |
13516 | hw_plane_wm->trans_wm.plane_res_b, | |
13517 | hw_plane_wm->trans_wm.plane_res_l); | |
13518 | } | |
13519 | ||
13520 | /* DDB */ | |
13521 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
13522 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
13523 | ||
13524 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 13525 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 13526 | pipe_name(pipe), plane + 1, |
13527 | sw_ddb_entry->start, sw_ddb_entry->end, | |
13528 | hw_ddb_entry->start, hw_ddb_entry->end); | |
13529 | } | |
e7c84544 | 13530 | } |
08db6652 | 13531 | |
27082493 L |
13532 | /* |
13533 | * cursor | |
13534 | * If the cursor plane isn't active, we may not have updated it's ddb | |
13535 | * allocation. In that case since the ddb allocation will be updated | |
13536 | * once the plane becomes visible, we can skip this check | |
13537 | */ | |
13538 | if (intel_crtc->cursor_addr) { | |
3de8a14c | 13539 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
13540 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
13541 | ||
13542 | /* Watermarks */ | |
13543 | for (level = 0; level <= max_level; level++) { | |
13544 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
13545 | &sw_plane_wm->wm[level])) | |
13546 | continue; | |
13547 | ||
13548 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13549 | pipe_name(pipe), level, | |
13550 | sw_plane_wm->wm[level].plane_en, | |
13551 | sw_plane_wm->wm[level].plane_res_b, | |
13552 | sw_plane_wm->wm[level].plane_res_l, | |
13553 | hw_plane_wm->wm[level].plane_en, | |
13554 | hw_plane_wm->wm[level].plane_res_b, | |
13555 | hw_plane_wm->wm[level].plane_res_l); | |
13556 | } | |
13557 | ||
13558 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
13559 | &sw_plane_wm->trans_wm)) { | |
13560 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13561 | pipe_name(pipe), | |
13562 | sw_plane_wm->trans_wm.plane_en, | |
13563 | sw_plane_wm->trans_wm.plane_res_b, | |
13564 | sw_plane_wm->trans_wm.plane_res_l, | |
13565 | hw_plane_wm->trans_wm.plane_en, | |
13566 | hw_plane_wm->trans_wm.plane_res_b, | |
13567 | hw_plane_wm->trans_wm.plane_res_l); | |
13568 | } | |
13569 | ||
13570 | /* DDB */ | |
13571 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
13572 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 13573 | |
3de8a14c | 13574 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 13575 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 13576 | pipe_name(pipe), |
3de8a14c | 13577 | sw_ddb_entry->start, sw_ddb_entry->end, |
13578 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 13579 | } |
08db6652 DL |
13580 | } |
13581 | } | |
13582 | ||
91d1b4bd | 13583 | static void |
677100ce ML |
13584 | verify_connector_state(struct drm_device *dev, |
13585 | struct drm_atomic_state *state, | |
13586 | struct drm_crtc *crtc) | |
8af6cf88 | 13587 | { |
35dd3c64 | 13588 | struct drm_connector *connector; |
677100ce ML |
13589 | struct drm_connector_state *old_conn_state; |
13590 | int i; | |
8af6cf88 | 13591 | |
677100ce | 13592 | for_each_connector_in_state(state, connector, old_conn_state, i) { |
35dd3c64 ML |
13593 | struct drm_encoder *encoder = connector->encoder; |
13594 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 13595 | |
e7c84544 ML |
13596 | if (state->crtc != crtc) |
13597 | continue; | |
13598 | ||
5a21b665 | 13599 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 13600 | |
ad3c558f | 13601 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 13602 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 13603 | } |
91d1b4bd DV |
13604 | } |
13605 | ||
13606 | static void | |
c0ead703 | 13607 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
13608 | { |
13609 | struct intel_encoder *encoder; | |
13610 | struct intel_connector *connector; | |
8af6cf88 | 13611 | |
b2784e15 | 13612 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13613 | bool enabled = false; |
4d20cd86 | 13614 | enum pipe pipe; |
8af6cf88 DV |
13615 | |
13616 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13617 | encoder->base.base.id, | |
8e329a03 | 13618 | encoder->base.name); |
8af6cf88 | 13619 | |
3a3371ff | 13620 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13621 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13622 | continue; |
13623 | enabled = true; | |
ad3c558f ML |
13624 | |
13625 | I915_STATE_WARN(connector->base.state->crtc != | |
13626 | encoder->base.crtc, | |
13627 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13628 | } |
0e32b39c | 13629 | |
e2c719b7 | 13630 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13631 | "encoder's enabled state mismatch " |
13632 | "(expected %i, found %i)\n", | |
13633 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13634 | |
13635 | if (!encoder->base.crtc) { | |
4d20cd86 | 13636 | bool active; |
7c60d198 | 13637 | |
4d20cd86 ML |
13638 | active = encoder->get_hw_state(encoder, &pipe); |
13639 | I915_STATE_WARN(active, | |
13640 | "encoder detached but still enabled on pipe %c.\n", | |
13641 | pipe_name(pipe)); | |
7c60d198 | 13642 | } |
8af6cf88 | 13643 | } |
91d1b4bd DV |
13644 | } |
13645 | ||
13646 | static void | |
c0ead703 ML |
13647 | verify_crtc_state(struct drm_crtc *crtc, |
13648 | struct drm_crtc_state *old_crtc_state, | |
13649 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 13650 | { |
e7c84544 | 13651 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13652 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 13653 | struct intel_encoder *encoder; |
e7c84544 ML |
13654 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13655 | struct intel_crtc_state *pipe_config, *sw_config; | |
13656 | struct drm_atomic_state *old_state; | |
13657 | bool active; | |
045ac3b5 | 13658 | |
e7c84544 | 13659 | old_state = old_crtc_state->state; |
ec2dc6a0 | 13660 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
13661 | pipe_config = to_intel_crtc_state(old_crtc_state); |
13662 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13663 | pipe_config->base.crtc = crtc; | |
13664 | pipe_config->base.state = old_state; | |
8af6cf88 | 13665 | |
78108b7c | 13666 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 13667 | |
e7c84544 | 13668 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 13669 | |
e7c84544 ML |
13670 | /* hw state is inconsistent with the pipe quirk */ |
13671 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
13672 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13673 | active = new_crtc_state->active; | |
6c49f241 | 13674 | |
e7c84544 ML |
13675 | I915_STATE_WARN(new_crtc_state->active != active, |
13676 | "crtc active state doesn't match with hw state " | |
13677 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 13678 | |
e7c84544 ML |
13679 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
13680 | "transitional active state does not match atomic hw state " | |
13681 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13682 | |
e7c84544 ML |
13683 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13684 | enum pipe pipe; | |
4d20cd86 | 13685 | |
e7c84544 ML |
13686 | active = encoder->get_hw_state(encoder, &pipe); |
13687 | I915_STATE_WARN(active != new_crtc_state->active, | |
13688 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13689 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13690 | |
e7c84544 ML |
13691 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13692 | "Encoder connected to wrong pipe %c\n", | |
13693 | pipe_name(pipe)); | |
4d20cd86 | 13694 | |
253c84c8 VS |
13695 | if (active) { |
13696 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 13697 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 13698 | } |
e7c84544 | 13699 | } |
53d9f4e9 | 13700 | |
e7c84544 ML |
13701 | if (!new_crtc_state->active) |
13702 | return; | |
cfb23ed6 | 13703 | |
e7c84544 | 13704 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13705 | |
e7c84544 | 13706 | sw_config = to_intel_crtc_state(crtc->state); |
6315b5d3 | 13707 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
13708 | pipe_config, false)) { |
13709 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13710 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13711 | "[hw state]"); | |
13712 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13713 | "[sw state]"); | |
8af6cf88 DV |
13714 | } |
13715 | } | |
13716 | ||
91d1b4bd | 13717 | static void |
c0ead703 ML |
13718 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13719 | struct intel_shared_dpll *pll, | |
13720 | struct drm_crtc *crtc, | |
13721 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13722 | { |
91d1b4bd | 13723 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13724 | unsigned crtc_mask; |
13725 | bool active; | |
5358901f | 13726 | |
e7c84544 | 13727 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13728 | |
e7c84544 | 13729 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13730 | |
e7c84544 | 13731 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13732 | |
e7c84544 ML |
13733 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13734 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13735 | "pll in active use but not on in sw tracking\n"); | |
13736 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13737 | "pll is on but not used by any active crtc\n"); | |
13738 | I915_STATE_WARN(pll->on != active, | |
13739 | "pll on state mismatch (expected %i, found %i)\n", | |
13740 | pll->on, active); | |
13741 | } | |
5358901f | 13742 | |
e7c84544 | 13743 | if (!crtc) { |
2dd66ebd | 13744 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13745 | "more active pll users than references: %x vs %x\n", |
13746 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13747 | |
e7c84544 ML |
13748 | return; |
13749 | } | |
13750 | ||
13751 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13752 | ||
13753 | if (new_state->active) | |
13754 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13755 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13756 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13757 | else | |
13758 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13759 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13760 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13761 | |
e7c84544 ML |
13762 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13763 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13764 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13765 | |
e7c84544 ML |
13766 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13767 | &dpll_hw_state, | |
13768 | sizeof(dpll_hw_state)), | |
13769 | "pll hw state mismatch\n"); | |
13770 | } | |
13771 | ||
13772 | static void | |
c0ead703 ML |
13773 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13774 | struct drm_crtc_state *old_crtc_state, | |
13775 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 13776 | { |
fac5e23e | 13777 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13778 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
13779 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13780 | ||
13781 | if (new_state->shared_dpll) | |
c0ead703 | 13782 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13783 | |
13784 | if (old_state->shared_dpll && | |
13785 | old_state->shared_dpll != new_state->shared_dpll) { | |
13786 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13787 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13788 | ||
13789 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13790 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13791 | pipe_name(drm_crtc_index(crtc))); | |
13792 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13793 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13794 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13795 | } |
8af6cf88 DV |
13796 | } |
13797 | ||
e7c84544 | 13798 | static void |
c0ead703 | 13799 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
13800 | struct drm_atomic_state *state, |
13801 | struct drm_crtc_state *old_state, | |
13802 | struct drm_crtc_state *new_state) | |
e7c84544 | 13803 | { |
5a21b665 DV |
13804 | if (!needs_modeset(new_state) && |
13805 | !to_intel_crtc_state(new_state)->update_pipe) | |
13806 | return; | |
13807 | ||
c0ead703 | 13808 | verify_wm_state(crtc, new_state); |
677100ce | 13809 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
13810 | verify_crtc_state(crtc, old_state, new_state); |
13811 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13812 | } |
13813 | ||
13814 | static void | |
c0ead703 | 13815 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 13816 | { |
fac5e23e | 13817 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13818 | int i; |
13819 | ||
13820 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13821 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13822 | } |
13823 | ||
13824 | static void | |
677100ce ML |
13825 | intel_modeset_verify_disabled(struct drm_device *dev, |
13826 | struct drm_atomic_state *state) | |
e7c84544 | 13827 | { |
c0ead703 | 13828 | verify_encoder_state(dev); |
677100ce | 13829 | verify_connector_state(dev, state, NULL); |
c0ead703 | 13830 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
13831 | } |
13832 | ||
80715b2f VS |
13833 | static void update_scanline_offset(struct intel_crtc *crtc) |
13834 | { | |
4f8036a2 | 13835 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
13836 | |
13837 | /* | |
13838 | * The scanline counter increments at the leading edge of hsync. | |
13839 | * | |
13840 | * On most platforms it starts counting from vtotal-1 on the | |
13841 | * first active line. That means the scanline counter value is | |
13842 | * always one less than what we would expect. Ie. just after | |
13843 | * start of vblank, which also occurs at start of hsync (on the | |
13844 | * last active line), the scanline counter will read vblank_start-1. | |
13845 | * | |
13846 | * On gen2 the scanline counter starts counting from 1 instead | |
13847 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13848 | * to keep the value positive), instead of adding one. | |
13849 | * | |
13850 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13851 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13852 | * there's an extra 1 line difference. So we need to add two instead of | |
13853 | * one to the value. | |
13854 | */ | |
4f8036a2 | 13855 | if (IS_GEN2(dev_priv)) { |
124abe07 | 13856 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13857 | int vtotal; |
13858 | ||
124abe07 VS |
13859 | vtotal = adjusted_mode->crtc_vtotal; |
13860 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13861 | vtotal /= 2; |
13862 | ||
13863 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 13864 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 13865 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13866 | crtc->scanline_offset = 2; |
13867 | } else | |
13868 | crtc->scanline_offset = 1; | |
13869 | } | |
13870 | ||
ad421372 | 13871 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13872 | { |
225da59b | 13873 | struct drm_device *dev = state->dev; |
ed6739ef | 13874 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13875 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13876 | struct drm_crtc *crtc; |
13877 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13878 | int i; |
ed6739ef ACO |
13879 | |
13880 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13881 | return; |
ed6739ef | 13882 | |
0a9ab303 | 13883 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13884 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13885 | struct intel_shared_dpll *old_dpll = |
13886 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13887 | |
fb1a38a9 | 13888 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13889 | continue; |
13890 | ||
8106ddbd | 13891 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13892 | |
8106ddbd | 13893 | if (!old_dpll) |
fb1a38a9 | 13894 | continue; |
0a9ab303 | 13895 | |
ad421372 ML |
13896 | if (!shared_dpll) |
13897 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13898 | |
8106ddbd | 13899 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13900 | } |
ed6739ef ACO |
13901 | } |
13902 | ||
99d736a2 ML |
13903 | /* |
13904 | * This implements the workaround described in the "notes" section of the mode | |
13905 | * set sequence documentation. When going from no pipes or single pipe to | |
13906 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13907 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13908 | */ | |
13909 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13910 | { | |
13911 | struct drm_crtc_state *crtc_state; | |
13912 | struct intel_crtc *intel_crtc; | |
13913 | struct drm_crtc *crtc; | |
13914 | struct intel_crtc_state *first_crtc_state = NULL; | |
13915 | struct intel_crtc_state *other_crtc_state = NULL; | |
13916 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13917 | int i; | |
13918 | ||
13919 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13920 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13921 | intel_crtc = to_intel_crtc(crtc); | |
13922 | ||
13923 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13924 | continue; | |
13925 | ||
13926 | if (first_crtc_state) { | |
13927 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13928 | break; | |
13929 | } else { | |
13930 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13931 | first_pipe = intel_crtc->pipe; | |
13932 | } | |
13933 | } | |
13934 | ||
13935 | /* No workaround needed? */ | |
13936 | if (!first_crtc_state) | |
13937 | return 0; | |
13938 | ||
13939 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13940 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13941 | struct intel_crtc_state *pipe_config; | |
13942 | ||
13943 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13944 | if (IS_ERR(pipe_config)) | |
13945 | return PTR_ERR(pipe_config); | |
13946 | ||
13947 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13948 | ||
13949 | if (!pipe_config->base.active || | |
13950 | needs_modeset(&pipe_config->base)) | |
13951 | continue; | |
13952 | ||
13953 | /* 2 or more enabled crtcs means no need for w/a */ | |
13954 | if (enabled_pipe != INVALID_PIPE) | |
13955 | return 0; | |
13956 | ||
13957 | enabled_pipe = intel_crtc->pipe; | |
13958 | } | |
13959 | ||
13960 | if (enabled_pipe != INVALID_PIPE) | |
13961 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13962 | else if (other_crtc_state) | |
13963 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13964 | ||
13965 | return 0; | |
13966 | } | |
13967 | ||
8d96561a VS |
13968 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
13969 | { | |
13970 | struct drm_crtc *crtc; | |
13971 | ||
13972 | /* Add all pipes to the state */ | |
13973 | for_each_crtc(state->dev, crtc) { | |
13974 | struct drm_crtc_state *crtc_state; | |
13975 | ||
13976 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13977 | if (IS_ERR(crtc_state)) | |
13978 | return PTR_ERR(crtc_state); | |
13979 | } | |
13980 | ||
13981 | return 0; | |
13982 | } | |
13983 | ||
27c329ed ML |
13984 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13985 | { | |
13986 | struct drm_crtc *crtc; | |
27c329ed | 13987 | |
8d96561a VS |
13988 | /* |
13989 | * Add all pipes to the state, and force | |
13990 | * a modeset on all the active ones. | |
13991 | */ | |
27c329ed | 13992 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
13993 | struct drm_crtc_state *crtc_state; |
13994 | int ret; | |
13995 | ||
27c329ed ML |
13996 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
13997 | if (IS_ERR(crtc_state)) | |
13998 | return PTR_ERR(crtc_state); | |
13999 | ||
14000 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
14001 | continue; | |
14002 | ||
14003 | crtc_state->mode_changed = true; | |
14004 | ||
14005 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
14006 | if (ret) | |
9780aad5 | 14007 | return ret; |
27c329ed ML |
14008 | |
14009 | ret = drm_atomic_add_affected_planes(state, crtc); | |
14010 | if (ret) | |
9780aad5 | 14011 | return ret; |
27c329ed ML |
14012 | } |
14013 | ||
9780aad5 | 14014 | return 0; |
27c329ed ML |
14015 | } |
14016 | ||
c347a676 | 14017 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 14018 | { |
565602d7 | 14019 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 14020 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
14021 | struct drm_crtc *crtc; |
14022 | struct drm_crtc_state *crtc_state; | |
14023 | int ret = 0, i; | |
054518dd | 14024 | |
b359283a ML |
14025 | if (!check_digital_port_conflicts(state)) { |
14026 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
14027 | return -EINVAL; | |
14028 | } | |
14029 | ||
565602d7 ML |
14030 | intel_state->modeset = true; |
14031 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
14032 | ||
14033 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
14034 | if (crtc_state->active) | |
14035 | intel_state->active_crtcs |= 1 << i; | |
14036 | else | |
14037 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
14038 | |
14039 | if (crtc_state->active != crtc->state->active) | |
14040 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
14041 | } |
14042 | ||
054518dd ACO |
14043 | /* |
14044 | * See if the config requires any additional preparation, e.g. | |
14045 | * to adjust global state with pipes off. We need to do this | |
14046 | * here so we can get the modeset_pipe updated config for the new | |
14047 | * mode set on this crtc. For other crtcs we need to use the | |
14048 | * adjusted_mode bits in the crtc directly. | |
14049 | */ | |
27c329ed | 14050 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 14051 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 14052 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
14053 | if (!intel_state->cdclk_pll_vco) |
14054 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 14055 | |
27c329ed | 14056 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
14057 | if (ret < 0) |
14058 | return ret; | |
27c329ed | 14059 | |
8d96561a VS |
14060 | /* |
14061 | * Writes to dev_priv->atomic_cdclk_freq must protected by | |
14062 | * holding all the crtc locks, even if we don't end up | |
14063 | * touching the hardware | |
14064 | */ | |
14065 | if (intel_state->cdclk != dev_priv->atomic_cdclk_freq) { | |
14066 | ret = intel_lock_all_pipes(state); | |
14067 | if (ret < 0) | |
14068 | return ret; | |
14069 | } | |
14070 | ||
14071 | /* All pipes must be switched off while we change the cdclk. */ | |
c89e39f3 | 14072 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
8d96561a | 14073 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) { |
27c329ed | 14074 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
14075 | if (ret < 0) |
14076 | return ret; | |
14077 | } | |
e8788cbc ML |
14078 | |
14079 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
14080 | intel_state->cdclk, intel_state->dev_cdclk); | |
e0ca7a6b | 14081 | } else { |
1a617b77 | 14082 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
e0ca7a6b | 14083 | } |
054518dd | 14084 | |
ad421372 | 14085 | intel_modeset_clear_plls(state); |
054518dd | 14086 | |
565602d7 | 14087 | if (IS_HASWELL(dev_priv)) |
ad421372 | 14088 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 14089 | |
ad421372 | 14090 | return 0; |
c347a676 ACO |
14091 | } |
14092 | ||
aa363136 MR |
14093 | /* |
14094 | * Handle calculation of various watermark data at the end of the atomic check | |
14095 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
14096 | * handlers to ensure that all derived state has been updated. | |
14097 | */ | |
55994c2c | 14098 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
14099 | { |
14100 | struct drm_device *dev = state->dev; | |
98d39494 | 14101 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
14102 | |
14103 | /* Is there platform-specific watermark information to calculate? */ | |
14104 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
14105 | return dev_priv->display.compute_global_watermarks(state); |
14106 | ||
14107 | return 0; | |
aa363136 MR |
14108 | } |
14109 | ||
74c090b1 ML |
14110 | /** |
14111 | * intel_atomic_check - validate state object | |
14112 | * @dev: drm device | |
14113 | * @state: state to validate | |
14114 | */ | |
14115 | static int intel_atomic_check(struct drm_device *dev, | |
14116 | struct drm_atomic_state *state) | |
c347a676 | 14117 | { |
dd8b3bdb | 14118 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 14119 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
14120 | struct drm_crtc *crtc; |
14121 | struct drm_crtc_state *crtc_state; | |
14122 | int ret, i; | |
61333b60 | 14123 | bool any_ms = false; |
c347a676 | 14124 | |
74c090b1 | 14125 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
14126 | if (ret) |
14127 | return ret; | |
14128 | ||
c347a676 | 14129 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
14130 | struct intel_crtc_state *pipe_config = |
14131 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
14132 | |
14133 | /* Catch I915_MODE_FLAG_INHERITED */ | |
14134 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
14135 | crtc_state->mode_changed = true; | |
cfb23ed6 | 14136 | |
af4a879e | 14137 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
14138 | continue; |
14139 | ||
af4a879e DV |
14140 | if (!crtc_state->enable) { |
14141 | any_ms = true; | |
cfb23ed6 | 14142 | continue; |
af4a879e | 14143 | } |
cfb23ed6 | 14144 | |
26495481 DV |
14145 | /* FIXME: For only active_changed we shouldn't need to do any |
14146 | * state recomputation at all. */ | |
14147 | ||
1ed51de9 DV |
14148 | ret = drm_atomic_add_affected_connectors(state, crtc); |
14149 | if (ret) | |
14150 | return ret; | |
b359283a | 14151 | |
cfb23ed6 | 14152 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
14153 | if (ret) { |
14154 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
14155 | pipe_config, "[failed]"); | |
c347a676 | 14156 | return ret; |
25aa1c39 | 14157 | } |
c347a676 | 14158 | |
73831236 | 14159 | if (i915.fastboot && |
6315b5d3 | 14160 | intel_pipe_config_compare(dev_priv, |
cfb23ed6 | 14161 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 14162 | pipe_config, true)) { |
26495481 | 14163 | crtc_state->mode_changed = false; |
bfd16b2a | 14164 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
14165 | } |
14166 | ||
af4a879e | 14167 | if (needs_modeset(crtc_state)) |
26495481 | 14168 | any_ms = true; |
cfb23ed6 | 14169 | |
af4a879e DV |
14170 | ret = drm_atomic_add_affected_planes(state, crtc); |
14171 | if (ret) | |
14172 | return ret; | |
61333b60 | 14173 | |
26495481 DV |
14174 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
14175 | needs_modeset(crtc_state) ? | |
14176 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
14177 | } |
14178 | ||
61333b60 ML |
14179 | if (any_ms) { |
14180 | ret = intel_modeset_checks(state); | |
14181 | ||
14182 | if (ret) | |
14183 | return ret; | |
e0ca7a6b VS |
14184 | } else { |
14185 | intel_state->cdclk = dev_priv->atomic_cdclk_freq; | |
14186 | } | |
76305b1a | 14187 | |
dd8b3bdb | 14188 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
14189 | if (ret) |
14190 | return ret; | |
14191 | ||
f51be2e0 | 14192 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 14193 | return calc_watermark_data(state); |
054518dd ACO |
14194 | } |
14195 | ||
5008e874 | 14196 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 14197 | struct drm_atomic_state *state) |
5008e874 | 14198 | { |
fac5e23e | 14199 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 ML |
14200 | struct drm_crtc_state *crtc_state; |
14201 | struct drm_crtc *crtc; | |
14202 | int i, ret; | |
14203 | ||
5a21b665 DV |
14204 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
14205 | if (state->legacy_cursor_update) | |
a6747b73 ML |
14206 | continue; |
14207 | ||
5a21b665 DV |
14208 | ret = intel_crtc_wait_for_pending_flips(crtc); |
14209 | if (ret) | |
14210 | return ret; | |
5008e874 | 14211 | |
5a21b665 DV |
14212 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
14213 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
14214 | } |
14215 | ||
f935675f ML |
14216 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
14217 | if (ret) | |
14218 | return ret; | |
14219 | ||
5008e874 | 14220 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 14221 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 14222 | |
5008e874 ML |
14223 | return ret; |
14224 | } | |
14225 | ||
a2991414 ML |
14226 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
14227 | { | |
14228 | struct drm_device *dev = crtc->base.dev; | |
14229 | ||
14230 | if (!dev->max_vblank_count) | |
14231 | return drm_accurate_vblank_count(&crtc->base); | |
14232 | ||
14233 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
14234 | } | |
14235 | ||
5a21b665 DV |
14236 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
14237 | struct drm_i915_private *dev_priv, | |
14238 | unsigned crtc_mask) | |
e8861675 | 14239 | { |
5a21b665 DV |
14240 | unsigned last_vblank_count[I915_MAX_PIPES]; |
14241 | enum pipe pipe; | |
14242 | int ret; | |
e8861675 | 14243 | |
5a21b665 DV |
14244 | if (!crtc_mask) |
14245 | return; | |
e8861675 | 14246 | |
5a21b665 | 14247 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
14248 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
14249 | pipe); | |
e8861675 | 14250 | |
5a21b665 | 14251 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
14252 | continue; |
14253 | ||
e2af48c6 | 14254 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
14255 | if (WARN_ON(ret != 0)) { |
14256 | crtc_mask &= ~(1 << pipe); | |
14257 | continue; | |
e8861675 ML |
14258 | } |
14259 | ||
e2af48c6 | 14260 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
14261 | } |
14262 | ||
5a21b665 | 14263 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
14264 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
14265 | pipe); | |
5a21b665 | 14266 | long lret; |
e8861675 | 14267 | |
5a21b665 DV |
14268 | if (!((1 << pipe) & crtc_mask)) |
14269 | continue; | |
d55dbd06 | 14270 | |
5a21b665 DV |
14271 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
14272 | last_vblank_count[pipe] != | |
e2af48c6 | 14273 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 14274 | msecs_to_jiffies(50)); |
d55dbd06 | 14275 | |
5a21b665 | 14276 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 14277 | |
e2af48c6 | 14278 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
14279 | } |
14280 | } | |
14281 | ||
5a21b665 | 14282 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 14283 | { |
5a21b665 DV |
14284 | /* fb updated, need to unpin old fb */ |
14285 | if (crtc_state->fb_changed) | |
14286 | return true; | |
a6747b73 | 14287 | |
5a21b665 DV |
14288 | /* wm changes, need vblank before final wm's */ |
14289 | if (crtc_state->update_wm_post) | |
14290 | return true; | |
a6747b73 | 14291 | |
5a21b665 DV |
14292 | /* |
14293 | * cxsr is re-enabled after vblank. | |
14294 | * This is already handled by crtc_state->update_wm_post, | |
14295 | * but added for clarity. | |
14296 | */ | |
14297 | if (crtc_state->disable_cxsr) | |
14298 | return true; | |
a6747b73 | 14299 | |
5a21b665 | 14300 | return false; |
e8861675 ML |
14301 | } |
14302 | ||
896e5bb0 L |
14303 | static void intel_update_crtc(struct drm_crtc *crtc, |
14304 | struct drm_atomic_state *state, | |
14305 | struct drm_crtc_state *old_crtc_state, | |
14306 | unsigned int *crtc_vblank_mask) | |
14307 | { | |
14308 | struct drm_device *dev = crtc->dev; | |
14309 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14311 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state); | |
14312 | bool modeset = needs_modeset(crtc->state); | |
14313 | ||
14314 | if (modeset) { | |
14315 | update_scanline_offset(intel_crtc); | |
14316 | dev_priv->display.crtc_enable(pipe_config, state); | |
14317 | } else { | |
14318 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); | |
14319 | } | |
14320 | ||
14321 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
14322 | intel_fbc_enable( | |
14323 | intel_crtc, pipe_config, | |
14324 | to_intel_plane_state(crtc->primary->state)); | |
14325 | } | |
14326 | ||
14327 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
14328 | ||
14329 | if (needs_vblank_wait(pipe_config)) | |
14330 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
14331 | } | |
14332 | ||
14333 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
14334 | unsigned int *crtc_vblank_mask) | |
14335 | { | |
14336 | struct drm_crtc *crtc; | |
14337 | struct drm_crtc_state *old_crtc_state; | |
14338 | int i; | |
14339 | ||
14340 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14341 | if (!crtc->state->active) | |
14342 | continue; | |
14343 | ||
14344 | intel_update_crtc(crtc, state, old_crtc_state, | |
14345 | crtc_vblank_mask); | |
14346 | } | |
14347 | } | |
14348 | ||
27082493 L |
14349 | static void skl_update_crtcs(struct drm_atomic_state *state, |
14350 | unsigned int *crtc_vblank_mask) | |
14351 | { | |
0f0f74bc | 14352 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
14353 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
14354 | struct drm_crtc *crtc; | |
ce0ba283 | 14355 | struct intel_crtc *intel_crtc; |
27082493 | 14356 | struct drm_crtc_state *old_crtc_state; |
ce0ba283 | 14357 | struct intel_crtc_state *cstate; |
27082493 L |
14358 | unsigned int updated = 0; |
14359 | bool progress; | |
14360 | enum pipe pipe; | |
5eff503b ML |
14361 | int i; |
14362 | ||
14363 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
14364 | ||
14365 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) | |
14366 | /* ignore allocations for crtc's that have been turned off. */ | |
14367 | if (crtc->state->active) | |
14368 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; | |
27082493 L |
14369 | |
14370 | /* | |
14371 | * Whenever the number of active pipes changes, we need to make sure we | |
14372 | * update the pipes in the right order so that their ddb allocations | |
14373 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
14374 | * cause pipe underruns and other bad stuff. | |
14375 | */ | |
14376 | do { | |
27082493 L |
14377 | progress = false; |
14378 | ||
14379 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14380 | bool vbl_wait = false; | |
14381 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
14382 | |
14383 | intel_crtc = to_intel_crtc(crtc); | |
14384 | cstate = to_intel_crtc_state(crtc->state); | |
14385 | pipe = intel_crtc->pipe; | |
27082493 | 14386 | |
5eff503b | 14387 | if (updated & cmask || !cstate->base.active) |
27082493 | 14388 | continue; |
5eff503b ML |
14389 | |
14390 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
14391 | continue; |
14392 | ||
14393 | updated |= cmask; | |
5eff503b | 14394 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
14395 | |
14396 | /* | |
14397 | * If this is an already active pipe, it's DDB changed, | |
14398 | * and this isn't the last pipe that needs updating | |
14399 | * then we need to wait for a vblank to pass for the | |
14400 | * new ddb allocation to take effect. | |
14401 | */ | |
ce0ba283 | 14402 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 14403 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
27082493 L |
14404 | !crtc->state->active_changed && |
14405 | intel_state->wm_results.dirty_pipes != updated) | |
14406 | vbl_wait = true; | |
14407 | ||
14408 | intel_update_crtc(crtc, state, old_crtc_state, | |
14409 | crtc_vblank_mask); | |
14410 | ||
14411 | if (vbl_wait) | |
0f0f74bc | 14412 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
14413 | |
14414 | progress = true; | |
14415 | } | |
14416 | } while (progress); | |
14417 | } | |
14418 | ||
94f05024 | 14419 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 14420 | { |
94f05024 | 14421 | struct drm_device *dev = state->dev; |
565602d7 | 14422 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 14423 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 14424 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 14425 | struct drm_crtc *crtc; |
5a21b665 | 14426 | struct intel_crtc_state *intel_cstate; |
5a21b665 DV |
14427 | bool hw_check = intel_state->modeset; |
14428 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
14429 | unsigned crtc_vblank_mask = 0; | |
e95433c7 | 14430 | int i; |
a6778b3c | 14431 | |
ea0000f0 DV |
14432 | drm_atomic_helper_wait_for_dependencies(state); |
14433 | ||
c3b32658 | 14434 | if (intel_state->modeset) |
5a21b665 | 14435 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 14436 | |
29ceb0e6 | 14437 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
14438 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14439 | ||
5a21b665 DV |
14440 | if (needs_modeset(crtc->state) || |
14441 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
14442 | hw_check = true; | |
14443 | ||
14444 | put_domains[to_intel_crtc(crtc)->pipe] = | |
14445 | modeset_get_crtc_power_domains(crtc, | |
14446 | to_intel_crtc_state(crtc->state)); | |
14447 | } | |
14448 | ||
61333b60 ML |
14449 | if (!needs_modeset(crtc->state)) |
14450 | continue; | |
14451 | ||
29ceb0e6 | 14452 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 14453 | |
29ceb0e6 VS |
14454 | if (old_crtc_state->active) { |
14455 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 14456 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 14457 | intel_crtc->active = false; |
58f9c0bc | 14458 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 14459 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
14460 | |
14461 | /* | |
14462 | * Underruns don't always raise | |
14463 | * interrupts, so check manually. | |
14464 | */ | |
14465 | intel_check_cpu_fifo_underruns(dev_priv); | |
14466 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 14467 | |
e62929b3 ML |
14468 | if (!crtc->state->active) { |
14469 | /* | |
14470 | * Make sure we don't call initial_watermarks | |
14471 | * for ILK-style watermark updates. | |
14472 | */ | |
14473 | if (dev_priv->display.atomic_update_watermarks) | |
14474 | dev_priv->display.initial_watermarks(intel_state, | |
14475 | to_intel_crtc_state(crtc->state)); | |
14476 | else | |
14477 | intel_update_watermarks(intel_crtc); | |
14478 | } | |
a539205a | 14479 | } |
b8cecdf5 | 14480 | } |
7758a113 | 14481 | |
ea9d758d DV |
14482 | /* Only after disabling all output pipelines that will be changed can we |
14483 | * update the the output configuration. */ | |
4740b0f2 | 14484 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 14485 | |
565602d7 | 14486 | if (intel_state->modeset) { |
4740b0f2 | 14487 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
14488 | |
14489 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 14490 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 14491 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 14492 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 14493 | |
656d1b89 L |
14494 | /* |
14495 | * SKL workaround: bspec recommends we disable the SAGV when we | |
14496 | * have more then one pipe enabled | |
14497 | */ | |
56feca91 | 14498 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 14499 | intel_disable_sagv(dev_priv); |
656d1b89 | 14500 | |
677100ce | 14501 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 14502 | } |
47fab737 | 14503 | |
896e5bb0 | 14504 | /* Complete the events for pipes that have now been disabled */ |
29ceb0e6 | 14505 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a | 14506 | bool modeset = needs_modeset(crtc->state); |
80715b2f | 14507 | |
1f7528c4 DV |
14508 | /* Complete events for now disable pipes here. */ |
14509 | if (modeset && !crtc->state->active && crtc->state->event) { | |
14510 | spin_lock_irq(&dev->event_lock); | |
14511 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
14512 | spin_unlock_irq(&dev->event_lock); | |
14513 | ||
14514 | crtc->state->event = NULL; | |
14515 | } | |
177246a8 MR |
14516 | } |
14517 | ||
896e5bb0 L |
14518 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
14519 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
14520 | ||
94f05024 DV |
14521 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
14522 | * already, but still need the state for the delayed optimization. To | |
14523 | * fix this: | |
14524 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
14525 | * - schedule that vblank worker _before_ calling hw_done | |
14526 | * - at the start of commit_tail, cancel it _synchrously | |
14527 | * - switch over to the vblank wait helper in the core after that since | |
14528 | * we don't need out special handling any more. | |
14529 | */ | |
5a21b665 DV |
14530 | if (!state->legacy_cursor_update) |
14531 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
14532 | ||
14533 | /* | |
14534 | * Now that the vblank has passed, we can go ahead and program the | |
14535 | * optimal watermarks on platforms that need two-step watermark | |
14536 | * programming. | |
14537 | * | |
14538 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
14539 | */ | |
14540 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14541 | intel_cstate = to_intel_crtc_state(crtc->state); | |
14542 | ||
14543 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
14544 | dev_priv->display.optimize_watermarks(intel_state, |
14545 | intel_cstate); | |
5a21b665 DV |
14546 | } |
14547 | ||
14548 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14549 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
14550 | ||
14551 | if (put_domains[i]) | |
14552 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
14553 | ||
677100ce | 14554 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state); |
5a21b665 DV |
14555 | } |
14556 | ||
56feca91 | 14557 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 14558 | intel_enable_sagv(dev_priv); |
656d1b89 | 14559 | |
94f05024 DV |
14560 | drm_atomic_helper_commit_hw_done(state); |
14561 | ||
5a21b665 DV |
14562 | if (intel_state->modeset) |
14563 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
14564 | ||
14565 | mutex_lock(&dev->struct_mutex); | |
14566 | drm_atomic_helper_cleanup_planes(dev, state); | |
14567 | mutex_unlock(&dev->struct_mutex); | |
14568 | ||
ea0000f0 DV |
14569 | drm_atomic_helper_commit_cleanup_done(state); |
14570 | ||
0853695c | 14571 | drm_atomic_state_put(state); |
f30da187 | 14572 | |
75714940 MK |
14573 | /* As one of the primary mmio accessors, KMS has a high likelihood |
14574 | * of triggering bugs in unclaimed access. After we finish | |
14575 | * modesetting, see if an error has been flagged, and if so | |
14576 | * enable debugging for the next modeset - and hope we catch | |
14577 | * the culprit. | |
14578 | * | |
14579 | * XXX note that we assume display power is on at this point. | |
14580 | * This might hold true now but we need to add pm helper to check | |
14581 | * unclaimed only when the hardware is on, as atomic commits | |
14582 | * can happen also when the device is completely off. | |
14583 | */ | |
14584 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
14585 | } |
14586 | ||
14587 | static void intel_atomic_commit_work(struct work_struct *work) | |
14588 | { | |
c004a90b CW |
14589 | struct drm_atomic_state *state = |
14590 | container_of(work, struct drm_atomic_state, commit_work); | |
14591 | ||
94f05024 DV |
14592 | intel_atomic_commit_tail(state); |
14593 | } | |
14594 | ||
c004a90b CW |
14595 | static int __i915_sw_fence_call |
14596 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
14597 | enum i915_sw_fence_notify notify) | |
14598 | { | |
14599 | struct intel_atomic_state *state = | |
14600 | container_of(fence, struct intel_atomic_state, commit_ready); | |
14601 | ||
14602 | switch (notify) { | |
14603 | case FENCE_COMPLETE: | |
14604 | if (state->base.commit_work.func) | |
14605 | queue_work(system_unbound_wq, &state->base.commit_work); | |
14606 | break; | |
14607 | ||
14608 | case FENCE_FREE: | |
14609 | drm_atomic_state_put(&state->base); | |
14610 | break; | |
14611 | } | |
14612 | ||
14613 | return NOTIFY_DONE; | |
14614 | } | |
14615 | ||
6c9c1b38 DV |
14616 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
14617 | { | |
14618 | struct drm_plane_state *old_plane_state; | |
14619 | struct drm_plane *plane; | |
6c9c1b38 DV |
14620 | int i; |
14621 | ||
faf5bf0a CW |
14622 | for_each_plane_in_state(state, plane, old_plane_state, i) |
14623 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
14624 | intel_fb_obj(plane->state->fb), | |
14625 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
14626 | } |
14627 | ||
94f05024 DV |
14628 | /** |
14629 | * intel_atomic_commit - commit validated state object | |
14630 | * @dev: DRM device | |
14631 | * @state: the top-level driver state object | |
14632 | * @nonblock: nonblocking commit | |
14633 | * | |
14634 | * This function commits a top-level state object that has been validated | |
14635 | * with drm_atomic_helper_check(). | |
14636 | * | |
94f05024 DV |
14637 | * RETURNS |
14638 | * Zero for success or -errno. | |
14639 | */ | |
14640 | static int intel_atomic_commit(struct drm_device *dev, | |
14641 | struct drm_atomic_state *state, | |
14642 | bool nonblock) | |
14643 | { | |
14644 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 14645 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
14646 | int ret = 0; |
14647 | ||
94f05024 DV |
14648 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
14649 | if (ret) | |
14650 | return ret; | |
14651 | ||
c004a90b CW |
14652 | drm_atomic_state_get(state); |
14653 | i915_sw_fence_init(&intel_state->commit_ready, | |
14654 | intel_atomic_commit_ready); | |
94f05024 | 14655 | |
d07f0e59 | 14656 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
14657 | if (ret) { |
14658 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 14659 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
14660 | return ret; |
14661 | } | |
14662 | ||
14663 | drm_atomic_helper_swap_state(state, true); | |
14664 | dev_priv->wm.distrust_bios_wm = false; | |
94f05024 | 14665 | intel_shared_dpll_commit(state); |
6c9c1b38 | 14666 | intel_atomic_track_fbs(state); |
94f05024 | 14667 | |
c3b32658 ML |
14668 | if (intel_state->modeset) { |
14669 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
14670 | sizeof(intel_state->min_pixclk)); | |
14671 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
14672 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; | |
14673 | } | |
14674 | ||
0853695c | 14675 | drm_atomic_state_get(state); |
c004a90b CW |
14676 | INIT_WORK(&state->commit_work, |
14677 | nonblock ? intel_atomic_commit_work : NULL); | |
14678 | ||
14679 | i915_sw_fence_commit(&intel_state->commit_ready); | |
14680 | if (!nonblock) { | |
14681 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 14682 | intel_atomic_commit_tail(state); |
c004a90b | 14683 | } |
75714940 | 14684 | |
74c090b1 | 14685 | return 0; |
7f27126e JB |
14686 | } |
14687 | ||
c0c36b94 CW |
14688 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
14689 | { | |
83a57153 ACO |
14690 | struct drm_device *dev = crtc->dev; |
14691 | struct drm_atomic_state *state; | |
e694eb02 | 14692 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 14693 | int ret; |
83a57153 ACO |
14694 | |
14695 | state = drm_atomic_state_alloc(dev); | |
14696 | if (!state) { | |
78108b7c VS |
14697 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
14698 | crtc->base.id, crtc->name); | |
83a57153 ACO |
14699 | return; |
14700 | } | |
14701 | ||
e694eb02 | 14702 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 14703 | |
e694eb02 ML |
14704 | retry: |
14705 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
14706 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
14707 | if (!ret) { | |
14708 | if (!crtc_state->active) | |
14709 | goto out; | |
83a57153 | 14710 | |
e694eb02 | 14711 | crtc_state->mode_changed = true; |
74c090b1 | 14712 | ret = drm_atomic_commit(state); |
83a57153 ACO |
14713 | } |
14714 | ||
e694eb02 ML |
14715 | if (ret == -EDEADLK) { |
14716 | drm_atomic_state_clear(state); | |
14717 | drm_modeset_backoff(state->acquire_ctx); | |
14718 | goto retry; | |
4ed9fb37 | 14719 | } |
4be07317 | 14720 | |
e694eb02 | 14721 | out: |
0853695c | 14722 | drm_atomic_state_put(state); |
c0c36b94 CW |
14723 | } |
14724 | ||
a8784875 BP |
14725 | /* |
14726 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
14727 | * drm_atomic_helper_legacy_gamma_set() directly. | |
14728 | */ | |
14729 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
14730 | u16 *red, u16 *green, u16 *blue, | |
14731 | uint32_t size) | |
14732 | { | |
14733 | struct drm_device *dev = crtc->dev; | |
14734 | struct drm_mode_config *config = &dev->mode_config; | |
14735 | struct drm_crtc_state *state; | |
14736 | int ret; | |
14737 | ||
14738 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
14739 | if (ret) | |
14740 | return ret; | |
14741 | ||
14742 | /* | |
14743 | * Make sure we update the legacy properties so this works when | |
14744 | * atomic is not enabled. | |
14745 | */ | |
14746 | ||
14747 | state = crtc->state; | |
14748 | ||
14749 | drm_object_property_set_value(&crtc->base, | |
14750 | config->degamma_lut_property, | |
14751 | (state->degamma_lut) ? | |
14752 | state->degamma_lut->base.id : 0); | |
14753 | ||
14754 | drm_object_property_set_value(&crtc->base, | |
14755 | config->ctm_property, | |
14756 | (state->ctm) ? | |
14757 | state->ctm->base.id : 0); | |
14758 | ||
14759 | drm_object_property_set_value(&crtc->base, | |
14760 | config->gamma_lut_property, | |
14761 | (state->gamma_lut) ? | |
14762 | state->gamma_lut->base.id : 0); | |
14763 | ||
14764 | return 0; | |
14765 | } | |
14766 | ||
f6e5b160 | 14767 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 14768 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 14769 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 14770 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 14771 | .destroy = intel_crtc_destroy, |
527b6abe | 14772 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
14773 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
14774 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
14775 | }; |
14776 | ||
6beb8c23 MR |
14777 | /** |
14778 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
14779 | * @plane: drm plane to prepare for | |
14780 | * @fb: framebuffer to prepare for presentation | |
14781 | * | |
14782 | * Prepares a framebuffer for usage on a display plane. Generally this | |
14783 | * involves pinning the underlying object and updating the frontbuffer tracking | |
14784 | * bits. Some older platforms need special physical address handling for | |
14785 | * cursor planes. | |
14786 | * | |
f935675f ML |
14787 | * Must be called with struct_mutex held. |
14788 | * | |
6beb8c23 MR |
14789 | * Returns 0 on success, negative error code on failure. |
14790 | */ | |
14791 | int | |
14792 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 14793 | struct drm_plane_state *new_state) |
465c120c | 14794 | { |
c004a90b CW |
14795 | struct intel_atomic_state *intel_state = |
14796 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 14797 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 14798 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 14799 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14800 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 14801 | int ret; |
465c120c | 14802 | |
1ee49399 | 14803 | if (!obj && !old_obj) |
465c120c MR |
14804 | return 0; |
14805 | ||
5008e874 ML |
14806 | if (old_obj) { |
14807 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
14808 | drm_atomic_get_existing_crtc_state(new_state->state, |
14809 | plane->state->crtc); | |
5008e874 ML |
14810 | |
14811 | /* Big Hammer, we also need to ensure that any pending | |
14812 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14813 | * current scanout is retired before unpinning the old | |
14814 | * framebuffer. Note that we rely on userspace rendering | |
14815 | * into the buffer attached to the pipe they are waiting | |
14816 | * on. If not, userspace generates a GPU hang with IPEHR | |
14817 | * point to the MI_WAIT_FOR_EVENT. | |
14818 | * | |
14819 | * This should only fail upon a hung GPU, in which case we | |
14820 | * can safely continue. | |
14821 | */ | |
c004a90b CW |
14822 | if (needs_modeset(crtc_state)) { |
14823 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
14824 | old_obj->resv, NULL, | |
14825 | false, 0, | |
14826 | GFP_KERNEL); | |
14827 | if (ret < 0) | |
14828 | return ret; | |
f4457ae7 | 14829 | } |
5008e874 ML |
14830 | } |
14831 | ||
c004a90b CW |
14832 | if (new_state->fence) { /* explicit fencing */ |
14833 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
14834 | new_state->fence, | |
14835 | I915_FENCE_TIMEOUT, | |
14836 | GFP_KERNEL); | |
14837 | if (ret < 0) | |
14838 | return ret; | |
14839 | } | |
14840 | ||
c37efb99 CW |
14841 | if (!obj) |
14842 | return 0; | |
14843 | ||
c004a90b CW |
14844 | if (!new_state->fence) { /* implicit fencing */ |
14845 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
14846 | obj->resv, NULL, | |
14847 | false, I915_FENCE_TIMEOUT, | |
14848 | GFP_KERNEL); | |
14849 | if (ret < 0) | |
14850 | return ret; | |
6b5e90f5 CW |
14851 | |
14852 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
c004a90b | 14853 | } |
5a21b665 | 14854 | |
c37efb99 | 14855 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
b7f05d4a | 14856 | INTEL_INFO(dev_priv)->cursor_needs_physical) { |
50a0bc90 | 14857 | int align = IS_I830(dev_priv) ? 16 * 1024 : 256; |
6beb8c23 | 14858 | ret = i915_gem_object_attach_phys(obj, align); |
d07f0e59 | 14859 | if (ret) { |
6beb8c23 | 14860 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
d07f0e59 CW |
14861 | return ret; |
14862 | } | |
6beb8c23 | 14863 | } else { |
058d88c4 CW |
14864 | struct i915_vma *vma; |
14865 | ||
14866 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
d07f0e59 CW |
14867 | if (IS_ERR(vma)) { |
14868 | DRM_DEBUG_KMS("failed to pin object\n"); | |
14869 | return PTR_ERR(vma); | |
14870 | } | |
7580d774 | 14871 | } |
fdd508a6 | 14872 | |
d07f0e59 | 14873 | return 0; |
6beb8c23 MR |
14874 | } |
14875 | ||
38f3ce3a MR |
14876 | /** |
14877 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14878 | * @plane: drm plane to clean up for | |
14879 | * @fb: old framebuffer that was on plane | |
14880 | * | |
14881 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14882 | * |
14883 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14884 | */ |
14885 | void | |
14886 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 14887 | struct drm_plane_state *old_state) |
38f3ce3a | 14888 | { |
b7f05d4a | 14889 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
7580d774 | 14890 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
14891 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14892 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14893 | |
7580d774 ML |
14894 | old_intel_state = to_intel_plane_state(old_state); |
14895 | ||
1ee49399 | 14896 | if (!obj && !old_obj) |
38f3ce3a MR |
14897 | return; |
14898 | ||
1ee49399 | 14899 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
b7f05d4a | 14900 | !INTEL_INFO(dev_priv)->cursor_needs_physical)) |
3465c580 | 14901 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
465c120c MR |
14902 | } |
14903 | ||
6156a456 CK |
14904 | int |
14905 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14906 | { | |
14907 | int max_scale; | |
6156a456 CK |
14908 | int crtc_clock, cdclk; |
14909 | ||
bf8a0af0 | 14910 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14911 | return DRM_PLANE_HELPER_NO_SCALING; |
14912 | ||
6156a456 | 14913 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
27c329ed | 14914 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14915 | |
54bf1ce6 | 14916 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14917 | return DRM_PLANE_HELPER_NO_SCALING; |
14918 | ||
14919 | /* | |
14920 | * skl max scale is lower of: | |
14921 | * close to 3 but not 3, -1 is for that purpose | |
14922 | * or | |
14923 | * cdclk/crtc_clock | |
14924 | */ | |
14925 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14926 | ||
14927 | return max_scale; | |
14928 | } | |
14929 | ||
465c120c | 14930 | static int |
3c692a41 | 14931 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14932 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14933 | struct intel_plane_state *state) |
14934 | { | |
b63a16f6 | 14935 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 14936 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 14937 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14938 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14939 | bool can_position = false; | |
b63a16f6 | 14940 | int ret; |
465c120c | 14941 | |
b63a16f6 | 14942 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
14943 | /* use scaler when colorkey is not required */ |
14944 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14945 | min_scale = 1; | |
14946 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14947 | } | |
d8106366 | 14948 | can_position = true; |
6156a456 | 14949 | } |
d8106366 | 14950 | |
cc926387 DV |
14951 | ret = drm_plane_helper_check_state(&state->base, |
14952 | &state->clip, | |
14953 | min_scale, max_scale, | |
14954 | can_position, true); | |
b63a16f6 VS |
14955 | if (ret) |
14956 | return ret; | |
14957 | ||
cc926387 | 14958 | if (!state->base.fb) |
b63a16f6 VS |
14959 | return 0; |
14960 | ||
14961 | if (INTEL_GEN(dev_priv) >= 9) { | |
14962 | ret = skl_check_plane_surface(state); | |
14963 | if (ret) | |
14964 | return ret; | |
14965 | } | |
14966 | ||
14967 | return 0; | |
14af293f GP |
14968 | } |
14969 | ||
5a21b665 DV |
14970 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14971 | struct drm_crtc_state *old_crtc_state) | |
14972 | { | |
14973 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 14974 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 14975 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
14976 | struct intel_crtc_state *intel_cstate = |
14977 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 14978 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 14979 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
14980 | struct intel_atomic_state *old_intel_state = |
14981 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
14982 | bool modeset = needs_modeset(crtc->state); |
14983 | ||
14984 | /* Perform vblank evasion around commit operation */ | |
14985 | intel_pipe_update_start(intel_crtc); | |
14986 | ||
14987 | if (modeset) | |
e62929b3 | 14988 | goto out; |
5a21b665 DV |
14989 | |
14990 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14991 | intel_color_set_csc(crtc->state); | |
14992 | intel_color_load_luts(crtc->state); | |
14993 | } | |
14994 | ||
ccf010fb ML |
14995 | if (intel_cstate->update_pipe) |
14996 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
14997 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 14998 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 14999 | |
e62929b3 | 15000 | out: |
ccf010fb ML |
15001 | if (dev_priv->display.atomic_update_watermarks) |
15002 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
15003 | intel_cstate); | |
5a21b665 DV |
15004 | } |
15005 | ||
15006 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
15007 | struct drm_crtc_state *old_crtc_state) | |
15008 | { | |
15009 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
15010 | ||
15011 | intel_pipe_update_end(intel_crtc, NULL); | |
15012 | } | |
15013 | ||
cf4c7c12 | 15014 | /** |
4a3b8769 MR |
15015 | * intel_plane_destroy - destroy a plane |
15016 | * @plane: plane to destroy | |
cf4c7c12 | 15017 | * |
4a3b8769 MR |
15018 | * Common destruction function for all types of planes (primary, cursor, |
15019 | * sprite). | |
cf4c7c12 | 15020 | */ |
4a3b8769 | 15021 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 15022 | { |
465c120c | 15023 | drm_plane_cleanup(plane); |
69ae561f | 15024 | kfree(to_intel_plane(plane)); |
465c120c MR |
15025 | } |
15026 | ||
65a3fea0 | 15027 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
15028 | .update_plane = drm_atomic_helper_update_plane, |
15029 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 15030 | .destroy = intel_plane_destroy, |
c196e1d6 | 15031 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
15032 | .atomic_get_property = intel_plane_atomic_get_property, |
15033 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
15034 | .atomic_duplicate_state = intel_plane_duplicate_state, |
15035 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
15036 | }; |
15037 | ||
b079bd17 | 15038 | static struct intel_plane * |
580503c7 | 15039 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 15040 | { |
fca0ce2a VS |
15041 | struct intel_plane *primary = NULL; |
15042 | struct intel_plane_state *state = NULL; | |
465c120c | 15043 | const uint32_t *intel_primary_formats; |
93ca7e00 | 15044 | unsigned int supported_rotations; |
45e3743a | 15045 | unsigned int num_formats; |
fca0ce2a | 15046 | int ret; |
465c120c MR |
15047 | |
15048 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
15049 | if (!primary) { |
15050 | ret = -ENOMEM; | |
fca0ce2a | 15051 | goto fail; |
b079bd17 | 15052 | } |
465c120c | 15053 | |
8e7d688b | 15054 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
15055 | if (!state) { |
15056 | ret = -ENOMEM; | |
fca0ce2a | 15057 | goto fail; |
b079bd17 VS |
15058 | } |
15059 | ||
8e7d688b | 15060 | primary->base.state = &state->base; |
ea2c67bb | 15061 | |
465c120c MR |
15062 | primary->can_scale = false; |
15063 | primary->max_downscale = 1; | |
580503c7 | 15064 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 15065 | primary->can_scale = true; |
af99ceda | 15066 | state->scaler_id = -1; |
6156a456 | 15067 | } |
465c120c | 15068 | primary->pipe = pipe; |
e3c566df VS |
15069 | /* |
15070 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
15071 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
15072 | */ | |
15073 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
15074 | primary->plane = (enum plane) !pipe; | |
15075 | else | |
15076 | primary->plane = (enum plane) pipe; | |
b14e5848 | 15077 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 15078 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 15079 | primary->check_plane = intel_check_primary_plane; |
465c120c | 15080 | |
580503c7 | 15081 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
15082 | intel_primary_formats = skl_primary_formats; |
15083 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
15084 | |
15085 | primary->update_plane = skylake_update_primary_plane; | |
15086 | primary->disable_plane = skylake_disable_primary_plane; | |
6e266956 | 15087 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
a8d201af ML |
15088 | intel_primary_formats = i965_primary_formats; |
15089 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
15090 | ||
15091 | primary->update_plane = ironlake_update_primary_plane; | |
15092 | primary->disable_plane = i9xx_disable_primary_plane; | |
580503c7 | 15093 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
15094 | intel_primary_formats = i965_primary_formats; |
15095 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
15096 | |
15097 | primary->update_plane = i9xx_update_primary_plane; | |
15098 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
15099 | } else { |
15100 | intel_primary_formats = i8xx_primary_formats; | |
15101 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
15102 | |
15103 | primary->update_plane = i9xx_update_primary_plane; | |
15104 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
15105 | } |
15106 | ||
580503c7 VS |
15107 | if (INTEL_GEN(dev_priv) >= 9) |
15108 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
15109 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15110 | intel_primary_formats, num_formats, |
15111 | DRM_PLANE_TYPE_PRIMARY, | |
15112 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 15113 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
15114 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
15115 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15116 | intel_primary_formats, num_formats, |
15117 | DRM_PLANE_TYPE_PRIMARY, | |
15118 | "primary %c", pipe_name(pipe)); | |
15119 | else | |
580503c7 VS |
15120 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
15121 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15122 | intel_primary_formats, num_formats, |
15123 | DRM_PLANE_TYPE_PRIMARY, | |
15124 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
15125 | if (ret) |
15126 | goto fail; | |
48404c1e | 15127 | |
5481e27f | 15128 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 VS |
15129 | supported_rotations = |
15130 | DRM_ROTATE_0 | DRM_ROTATE_90 | | |
15131 | DRM_ROTATE_180 | DRM_ROTATE_270; | |
4ea7be2b VS |
15132 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
15133 | supported_rotations = | |
15134 | DRM_ROTATE_0 | DRM_ROTATE_180 | | |
15135 | DRM_REFLECT_X; | |
5481e27f | 15136 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 VS |
15137 | supported_rotations = |
15138 | DRM_ROTATE_0 | DRM_ROTATE_180; | |
15139 | } else { | |
15140 | supported_rotations = DRM_ROTATE_0; | |
15141 | } | |
15142 | ||
5481e27f | 15143 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
15144 | drm_plane_create_rotation_property(&primary->base, |
15145 | DRM_ROTATE_0, | |
15146 | supported_rotations); | |
48404c1e | 15147 | |
ea2c67bb MR |
15148 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
15149 | ||
b079bd17 | 15150 | return primary; |
fca0ce2a VS |
15151 | |
15152 | fail: | |
15153 | kfree(state); | |
15154 | kfree(primary); | |
15155 | ||
b079bd17 | 15156 | return ERR_PTR(ret); |
465c120c MR |
15157 | } |
15158 | ||
3d7d6510 | 15159 | static int |
852e787c | 15160 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 15161 | struct intel_crtc_state *crtc_state, |
852e787c | 15162 | struct intel_plane_state *state) |
3d7d6510 | 15163 | { |
2b875c22 | 15164 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 15165 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 15166 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
15167 | unsigned stride; |
15168 | int ret; | |
3d7d6510 | 15169 | |
f8856a44 VS |
15170 | ret = drm_plane_helper_check_state(&state->base, |
15171 | &state->clip, | |
15172 | DRM_PLANE_HELPER_NO_SCALING, | |
15173 | DRM_PLANE_HELPER_NO_SCALING, | |
15174 | true, true); | |
757f9a3e GP |
15175 | if (ret) |
15176 | return ret; | |
15177 | ||
757f9a3e GP |
15178 | /* if we want to turn off the cursor ignore width and height */ |
15179 | if (!obj) | |
da20eabd | 15180 | return 0; |
757f9a3e | 15181 | |
757f9a3e | 15182 | /* Check for which cursor types we support */ |
50a0bc90 TU |
15183 | if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w, |
15184 | state->base.crtc_h)) { | |
ea2c67bb MR |
15185 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
15186 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
15187 | return -EINVAL; |
15188 | } | |
15189 | ||
ea2c67bb MR |
15190 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
15191 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
15192 | DRM_DEBUG_KMS("buffer is too small\n"); |
15193 | return -ENOMEM; | |
15194 | } | |
15195 | ||
bae781b2 | 15196 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 15197 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 15198 | return -EINVAL; |
32b7eeec MR |
15199 | } |
15200 | ||
b29ec92c VS |
15201 | /* |
15202 | * There's something wrong with the cursor on CHV pipe C. | |
15203 | * If it straddles the left edge of the screen then | |
15204 | * moving it away from the edge or disabling it often | |
15205 | * results in a pipe underrun, and often that can lead to | |
15206 | * dead pipe (constant underrun reported, and it scans | |
15207 | * out just a solid color). To recover from that, the | |
15208 | * display power well must be turned off and on again. | |
15209 | * Refuse the put the cursor into that compromised position. | |
15210 | */ | |
920a14b2 | 15211 | if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C && |
936e71e3 | 15212 | state->base.visible && state->base.crtc_x < 0) { |
b29ec92c VS |
15213 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
15214 | return -EINVAL; | |
15215 | } | |
15216 | ||
da20eabd | 15217 | return 0; |
852e787c | 15218 | } |
3d7d6510 | 15219 | |
a8ad0d8e ML |
15220 | static void |
15221 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 15222 | struct drm_crtc *crtc) |
a8ad0d8e | 15223 | { |
f2858021 ML |
15224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
15225 | ||
15226 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 15227 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
15228 | } |
15229 | ||
f4a2cf29 | 15230 | static void |
55a08b3f ML |
15231 | intel_update_cursor_plane(struct drm_plane *plane, |
15232 | const struct intel_crtc_state *crtc_state, | |
15233 | const struct intel_plane_state *state) | |
852e787c | 15234 | { |
55a08b3f ML |
15235 | struct drm_crtc *crtc = crtc_state->base.crtc; |
15236 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b7f05d4a | 15237 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 15238 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 15239 | uint32_t addr; |
852e787c | 15240 | |
f4a2cf29 | 15241 | if (!obj) |
a912f12f | 15242 | addr = 0; |
b7f05d4a | 15243 | else if (!INTEL_INFO(dev_priv)->cursor_needs_physical) |
058d88c4 | 15244 | addr = i915_gem_object_ggtt_offset(obj, NULL); |
f4a2cf29 | 15245 | else |
a912f12f | 15246 | addr = obj->phys_handle->busaddr; |
852e787c | 15247 | |
a912f12f | 15248 | intel_crtc->cursor_addr = addr; |
55a08b3f | 15249 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
15250 | } |
15251 | ||
b079bd17 | 15252 | static struct intel_plane * |
580503c7 | 15253 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
3d7d6510 | 15254 | { |
fca0ce2a VS |
15255 | struct intel_plane *cursor = NULL; |
15256 | struct intel_plane_state *state = NULL; | |
15257 | int ret; | |
3d7d6510 MR |
15258 | |
15259 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
15260 | if (!cursor) { |
15261 | ret = -ENOMEM; | |
fca0ce2a | 15262 | goto fail; |
b079bd17 | 15263 | } |
3d7d6510 | 15264 | |
8e7d688b | 15265 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
15266 | if (!state) { |
15267 | ret = -ENOMEM; | |
fca0ce2a | 15268 | goto fail; |
b079bd17 VS |
15269 | } |
15270 | ||
8e7d688b | 15271 | cursor->base.state = &state->base; |
ea2c67bb | 15272 | |
3d7d6510 MR |
15273 | cursor->can_scale = false; |
15274 | cursor->max_downscale = 1; | |
15275 | cursor->pipe = pipe; | |
15276 | cursor->plane = pipe; | |
b14e5848 | 15277 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 15278 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 15279 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 15280 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 15281 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 15282 | |
580503c7 VS |
15283 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
15284 | 0, &intel_plane_funcs, | |
fca0ce2a VS |
15285 | intel_cursor_formats, |
15286 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
15287 | DRM_PLANE_TYPE_CURSOR, |
15288 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
15289 | if (ret) |
15290 | goto fail; | |
4398ad45 | 15291 | |
5481e27f | 15292 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
15293 | drm_plane_create_rotation_property(&cursor->base, |
15294 | DRM_ROTATE_0, | |
15295 | DRM_ROTATE_0 | | |
15296 | DRM_ROTATE_180); | |
4398ad45 | 15297 | |
580503c7 | 15298 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
15299 | state->scaler_id = -1; |
15300 | ||
ea2c67bb MR |
15301 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
15302 | ||
b079bd17 | 15303 | return cursor; |
fca0ce2a VS |
15304 | |
15305 | fail: | |
15306 | kfree(state); | |
15307 | kfree(cursor); | |
15308 | ||
b079bd17 | 15309 | return ERR_PTR(ret); |
3d7d6510 MR |
15310 | } |
15311 | ||
65edccce VS |
15312 | static void skl_init_scalers(struct drm_i915_private *dev_priv, |
15313 | struct intel_crtc *crtc, | |
15314 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 15315 | { |
65edccce VS |
15316 | struct intel_crtc_scaler_state *scaler_state = |
15317 | &crtc_state->scaler_state; | |
549e2bfb | 15318 | int i; |
549e2bfb | 15319 | |
65edccce VS |
15320 | for (i = 0; i < crtc->num_scalers; i++) { |
15321 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
15322 | ||
15323 | scaler->in_use = 0; | |
15324 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
15325 | } |
15326 | ||
15327 | scaler_state->scaler_id = -1; | |
15328 | } | |
15329 | ||
5ab0d85b | 15330 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
15331 | { |
15332 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 15333 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
15334 | struct intel_plane *primary = NULL; |
15335 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 15336 | int sprite, ret; |
79e53945 | 15337 | |
955382f3 | 15338 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
15339 | if (!intel_crtc) |
15340 | return -ENOMEM; | |
79e53945 | 15341 | |
f5de6e07 | 15342 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
15343 | if (!crtc_state) { |
15344 | ret = -ENOMEM; | |
f5de6e07 | 15345 | goto fail; |
b079bd17 | 15346 | } |
550acefd ACO |
15347 | intel_crtc->config = crtc_state; |
15348 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 15349 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 15350 | |
549e2bfb | 15351 | /* initialize shared scalers */ |
5ab0d85b | 15352 | if (INTEL_GEN(dev_priv) >= 9) { |
549e2bfb CK |
15353 | if (pipe == PIPE_C) |
15354 | intel_crtc->num_scalers = 1; | |
15355 | else | |
15356 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
15357 | ||
65edccce | 15358 | skl_init_scalers(dev_priv, intel_crtc, crtc_state); |
549e2bfb CK |
15359 | } |
15360 | ||
580503c7 | 15361 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
15362 | if (IS_ERR(primary)) { |
15363 | ret = PTR_ERR(primary); | |
3d7d6510 | 15364 | goto fail; |
b079bd17 | 15365 | } |
d97d7b48 | 15366 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 15367 | |
a81d6fa0 | 15368 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
15369 | struct intel_plane *plane; |
15370 | ||
580503c7 | 15371 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 15372 | if (IS_ERR(plane)) { |
b079bd17 VS |
15373 | ret = PTR_ERR(plane); |
15374 | goto fail; | |
15375 | } | |
d97d7b48 | 15376 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
15377 | } |
15378 | ||
580503c7 | 15379 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 15380 | if (IS_ERR(cursor)) { |
b079bd17 | 15381 | ret = PTR_ERR(cursor); |
3d7d6510 | 15382 | goto fail; |
b079bd17 | 15383 | } |
d97d7b48 | 15384 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 15385 | |
5ab0d85b | 15386 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
15387 | &primary->base, &cursor->base, |
15388 | &intel_crtc_funcs, | |
4d5d72b7 | 15389 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
15390 | if (ret) |
15391 | goto fail; | |
79e53945 | 15392 | |
80824003 | 15393 | intel_crtc->pipe = pipe; |
e3c566df | 15394 | intel_crtc->plane = primary->plane; |
80824003 | 15395 | |
4b0e333e CW |
15396 | intel_crtc->cursor_base = ~0; |
15397 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 15398 | intel_crtc->cursor_size = ~0; |
8d7849db | 15399 | |
852eb00d VS |
15400 | intel_crtc->wm.cxsr_allowed = true; |
15401 | ||
22fd0fab JB |
15402 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
15403 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
15404 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
15405 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 15406 | |
79e53945 | 15407 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 15408 | |
8563b1e8 LL |
15409 | intel_color_init(&intel_crtc->base); |
15410 | ||
87b6b101 | 15411 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
15412 | |
15413 | return 0; | |
3d7d6510 MR |
15414 | |
15415 | fail: | |
b079bd17 VS |
15416 | /* |
15417 | * drm_mode_config_cleanup() will free up any | |
15418 | * crtcs/planes already initialized. | |
15419 | */ | |
f5de6e07 | 15420 | kfree(crtc_state); |
3d7d6510 | 15421 | kfree(intel_crtc); |
b079bd17 VS |
15422 | |
15423 | return ret; | |
79e53945 JB |
15424 | } |
15425 | ||
752aa88a JB |
15426 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
15427 | { | |
15428 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 15429 | struct drm_device *dev = connector->base.dev; |
752aa88a | 15430 | |
51fd371b | 15431 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 15432 | |
d3babd3f | 15433 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
15434 | return INVALID_PIPE; |
15435 | ||
15436 | return to_intel_crtc(encoder->crtc)->pipe; | |
15437 | } | |
15438 | ||
08d7b3d1 | 15439 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 15440 | struct drm_file *file) |
08d7b3d1 | 15441 | { |
08d7b3d1 | 15442 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 15443 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 15444 | struct intel_crtc *crtc; |
08d7b3d1 | 15445 | |
7707e653 | 15446 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 15447 | if (!drmmode_crtc) |
3f2c2057 | 15448 | return -ENOENT; |
08d7b3d1 | 15449 | |
7707e653 | 15450 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 15451 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 15452 | |
c05422d5 | 15453 | return 0; |
08d7b3d1 CW |
15454 | } |
15455 | ||
66a9278e | 15456 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 15457 | { |
66a9278e DV |
15458 | struct drm_device *dev = encoder->base.dev; |
15459 | struct intel_encoder *source_encoder; | |
79e53945 | 15460 | int index_mask = 0; |
79e53945 JB |
15461 | int entry = 0; |
15462 | ||
b2784e15 | 15463 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 15464 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
15465 | index_mask |= (1 << entry); |
15466 | ||
79e53945 JB |
15467 | entry++; |
15468 | } | |
4ef69c7a | 15469 | |
79e53945 JB |
15470 | return index_mask; |
15471 | } | |
15472 | ||
646d5772 | 15473 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 15474 | { |
646d5772 | 15475 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
15476 | return false; |
15477 | ||
15478 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
15479 | return false; | |
15480 | ||
5db94019 | 15481 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
15482 | return false; |
15483 | ||
15484 | return true; | |
15485 | } | |
15486 | ||
6315b5d3 | 15487 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 15488 | { |
6315b5d3 | 15489 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
15490 | return false; |
15491 | ||
50a0bc90 | 15492 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
15493 | return false; |
15494 | ||
920a14b2 | 15495 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
15496 | return false; |
15497 | ||
4f8036a2 TU |
15498 | if (HAS_PCH_LPT_H(dev_priv) && |
15499 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
15500 | return false; |
15501 | ||
70ac54d0 | 15502 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 15503 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
15504 | return false; |
15505 | ||
e4abb733 | 15506 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
15507 | return false; |
15508 | ||
15509 | return true; | |
15510 | } | |
15511 | ||
8090ba8c ID |
15512 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
15513 | { | |
15514 | int pps_num; | |
15515 | int pps_idx; | |
15516 | ||
15517 | if (HAS_DDI(dev_priv)) | |
15518 | return; | |
15519 | /* | |
15520 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
15521 | * everywhere where registers can be write protected. | |
15522 | */ | |
15523 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15524 | pps_num = 2; | |
15525 | else | |
15526 | pps_num = 1; | |
15527 | ||
15528 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
15529 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
15530 | ||
15531 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
15532 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
15533 | } | |
15534 | } | |
15535 | ||
44cb734c ID |
15536 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
15537 | { | |
cc3f90f0 | 15538 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
15539 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
15540 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15541 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
15542 | else | |
15543 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
15544 | |
15545 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
15546 | } |
15547 | ||
c39055b0 | 15548 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 15549 | { |
4ef69c7a | 15550 | struct intel_encoder *encoder; |
cb0953d7 | 15551 | bool dpd_is_edp = false; |
79e53945 | 15552 | |
44cb734c ID |
15553 | intel_pps_init(dev_priv); |
15554 | ||
97a824e1 ID |
15555 | /* |
15556 | * intel_edp_init_connector() depends on this completing first, to | |
15557 | * prevent the registeration of both eDP and LVDS and the incorrect | |
15558 | * sharing of the PPS. | |
15559 | */ | |
c39055b0 | 15560 | intel_lvds_init(dev_priv); |
79e53945 | 15561 | |
6315b5d3 | 15562 | if (intel_crt_present(dev_priv)) |
c39055b0 | 15563 | intel_crt_init(dev_priv); |
cb0953d7 | 15564 | |
cc3f90f0 | 15565 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
15566 | /* |
15567 | * FIXME: Broxton doesn't support port detection via the | |
15568 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
15569 | * detect the ports. | |
15570 | */ | |
c39055b0 ACO |
15571 | intel_ddi_init(dev_priv, PORT_A); |
15572 | intel_ddi_init(dev_priv, PORT_B); | |
15573 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 15574 | |
c39055b0 | 15575 | intel_dsi_init(dev_priv); |
4f8036a2 | 15576 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
15577 | int found; |
15578 | ||
de31facd JB |
15579 | /* |
15580 | * Haswell uses DDI functions to detect digital outputs. | |
15581 | * On SKL pre-D0 the strap isn't connected, so we assume | |
15582 | * it's there. | |
15583 | */ | |
77179400 | 15584 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 15585 | /* WaIgnoreDDIAStrap: skl */ |
0853723b | 15586 | if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
c39055b0 | 15587 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
15588 | |
15589 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
15590 | * register */ | |
15591 | found = I915_READ(SFUSE_STRAP); | |
15592 | ||
15593 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 15594 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 15595 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 15596 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 15597 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 15598 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
15599 | /* |
15600 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
15601 | */ | |
0853723b | 15602 | if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && |
2800e4c2 RV |
15603 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
15604 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
15605 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 15606 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 15607 | |
6e266956 | 15608 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 15609 | int found; |
dd11bc10 | 15610 | dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); |
270b3042 | 15611 | |
646d5772 | 15612 | if (has_edp_a(dev_priv)) |
c39055b0 | 15613 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 15614 | |
dc0fa718 | 15615 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 15616 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 15617 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 15618 | if (!found) |
c39055b0 | 15619 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 15620 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 15621 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
15622 | } |
15623 | ||
dc0fa718 | 15624 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 15625 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 15626 | |
dc0fa718 | 15627 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 15628 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 15629 | |
5eb08b69 | 15630 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 15631 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 15632 | |
270b3042 | 15633 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 15634 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 15635 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 15636 | bool has_edp, has_port; |
457c52d8 | 15637 | |
e17ac6db VS |
15638 | /* |
15639 | * The DP_DETECTED bit is the latched state of the DDC | |
15640 | * SDA pin at boot. However since eDP doesn't require DDC | |
15641 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
15642 | * eDP ports may have been muxed to an alternate function. | |
15643 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
15644 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
15645 | * detect eDP ports. | |
22f35042 VS |
15646 | * |
15647 | * Sadly the straps seem to be missing sometimes even for HDMI | |
15648 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
15649 | * and VBT for the presence of the port. Additionally we can't | |
15650 | * trust the port type the VBT declares as we've seen at least | |
15651 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 15652 | */ |
dd11bc10 | 15653 | has_edp = intel_dp_is_edp(dev_priv, PORT_B); |
22f35042 VS |
15654 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
15655 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 15656 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 15657 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 15658 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 15659 | |
dd11bc10 | 15660 | has_edp = intel_dp_is_edp(dev_priv, PORT_C); |
22f35042 VS |
15661 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
15662 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 15663 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 15664 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 15665 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 15666 | |
920a14b2 | 15667 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
15668 | /* |
15669 | * eDP not supported on port D, | |
15670 | * so no need to worry about it | |
15671 | */ | |
15672 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
15673 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 15674 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 15675 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 15676 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
15677 | } |
15678 | ||
c39055b0 | 15679 | intel_dsi_init(dev_priv); |
5db94019 | 15680 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 15681 | bool found = false; |
7d57382e | 15682 | |
e2debe91 | 15683 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15684 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 15685 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 15686 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 15687 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 15688 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 15689 | } |
27185ae1 | 15690 | |
9beb5fea | 15691 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 15692 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 15693 | } |
13520b05 KH |
15694 | |
15695 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 15696 | |
e2debe91 | 15697 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15698 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 15699 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 15700 | } |
27185ae1 | 15701 | |
e2debe91 | 15702 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 15703 | |
9beb5fea | 15704 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 15705 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 15706 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 15707 | } |
9beb5fea | 15708 | if (IS_G4X(dev_priv)) |
c39055b0 | 15709 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 15710 | } |
27185ae1 | 15711 | |
9beb5fea | 15712 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 15713 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 15714 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 15715 | intel_dvo_init(dev_priv); |
79e53945 | 15716 | |
56b857a5 | 15717 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 15718 | intel_tv_init(dev_priv); |
79e53945 | 15719 | |
c39055b0 | 15720 | intel_psr_init(dev_priv); |
7c8f8a70 | 15721 | |
c39055b0 | 15722 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
15723 | encoder->base.possible_crtcs = encoder->crtc_mask; |
15724 | encoder->base.possible_clones = | |
66a9278e | 15725 | intel_encoder_clones(encoder); |
79e53945 | 15726 | } |
47356eb6 | 15727 | |
c39055b0 | 15728 | intel_init_pch_refclk(dev_priv); |
270b3042 | 15729 | |
c39055b0 | 15730 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
15731 | } |
15732 | ||
15733 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
15734 | { | |
60a5ca01 | 15735 | struct drm_device *dev = fb->dev; |
79e53945 | 15736 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 15737 | |
ef2d633e | 15738 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 15739 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 15740 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
f8c417cd | 15741 | i915_gem_object_put(intel_fb->obj); |
60a5ca01 | 15742 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
15743 | kfree(intel_fb); |
15744 | } | |
15745 | ||
15746 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 15747 | struct drm_file *file, |
79e53945 JB |
15748 | unsigned int *handle) |
15749 | { | |
15750 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 15751 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 15752 | |
cc917ab4 CW |
15753 | if (obj->userptr.mm) { |
15754 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
15755 | return -EINVAL; | |
15756 | } | |
15757 | ||
05394f39 | 15758 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
15759 | } |
15760 | ||
86c98588 RV |
15761 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
15762 | struct drm_file *file, | |
15763 | unsigned flags, unsigned color, | |
15764 | struct drm_clip_rect *clips, | |
15765 | unsigned num_clips) | |
15766 | { | |
15767 | struct drm_device *dev = fb->dev; | |
15768 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
15769 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
15770 | ||
15771 | mutex_lock(&dev->struct_mutex); | |
a6a7cc4b CW |
15772 | if (obj->pin_display && obj->cache_dirty) |
15773 | i915_gem_clflush_object(obj, true); | |
74b4ea1e | 15774 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
15775 | mutex_unlock(&dev->struct_mutex); |
15776 | ||
15777 | return 0; | |
15778 | } | |
15779 | ||
79e53945 JB |
15780 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
15781 | .destroy = intel_user_framebuffer_destroy, | |
15782 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 15783 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
15784 | }; |
15785 | ||
b321803d | 15786 | static |
920a14b2 TU |
15787 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
15788 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 15789 | { |
920a14b2 | 15790 | u32 gen = INTEL_INFO(dev_priv)->gen; |
b321803d DL |
15791 | |
15792 | if (gen >= 9) { | |
ac484963 VS |
15793 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
15794 | ||
b321803d DL |
15795 | /* "The stride in bytes must not exceed the of the size of 8K |
15796 | * pixels and 32K bytes." | |
15797 | */ | |
ac484963 | 15798 | return min(8192 * cpp, 32768); |
920a14b2 TU |
15799 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) && |
15800 | !IS_CHERRYVIEW(dev_priv)) { | |
b321803d DL |
15801 | return 32*1024; |
15802 | } else if (gen >= 4) { | |
15803 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15804 | return 16*1024; | |
15805 | else | |
15806 | return 32*1024; | |
15807 | } else if (gen >= 3) { | |
15808 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15809 | return 8*1024; | |
15810 | else | |
15811 | return 16*1024; | |
15812 | } else { | |
15813 | /* XXX DSPC is limited to 4k tiled */ | |
15814 | return 8*1024; | |
15815 | } | |
15816 | } | |
15817 | ||
b5ea642a DV |
15818 | static int intel_framebuffer_init(struct drm_device *dev, |
15819 | struct intel_framebuffer *intel_fb, | |
15820 | struct drm_mode_fb_cmd2 *mode_cmd, | |
15821 | struct drm_i915_gem_object *obj) | |
79e53945 | 15822 | { |
7b49f948 | 15823 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2ff7370 | 15824 | unsigned int tiling = i915_gem_object_get_tiling(obj); |
79e53945 | 15825 | int ret; |
b321803d | 15826 | u32 pitch_limit, stride_alignment; |
b3c11ac2 | 15827 | struct drm_format_name_buf format_name; |
79e53945 | 15828 | |
dd4916c5 DV |
15829 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
15830 | ||
2a80eada | 15831 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
15832 | /* |
15833 | * If there's a fence, enforce that | |
15834 | * the fb modifier and tiling mode match. | |
15835 | */ | |
15836 | if (tiling != I915_TILING_NONE && | |
15837 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
2a80eada DV |
15838 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
15839 | return -EINVAL; | |
15840 | } | |
15841 | } else { | |
c2ff7370 | 15842 | if (tiling == I915_TILING_X) { |
2a80eada | 15843 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 15844 | } else if (tiling == I915_TILING_Y) { |
2a80eada DV |
15845 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
15846 | return -EINVAL; | |
15847 | } | |
15848 | } | |
15849 | ||
9a8f0a12 TU |
15850 | /* Passed in modifier sanity checking. */ |
15851 | switch (mode_cmd->modifier[0]) { | |
15852 | case I915_FORMAT_MOD_Y_TILED: | |
15853 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 15854 | if (INTEL_GEN(dev_priv) < 9) { |
9a8f0a12 TU |
15855 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", |
15856 | mode_cmd->modifier[0]); | |
15857 | return -EINVAL; | |
15858 | } | |
15859 | case DRM_FORMAT_MOD_NONE: | |
15860 | case I915_FORMAT_MOD_X_TILED: | |
15861 | break; | |
15862 | default: | |
c0f40428 JB |
15863 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
15864 | mode_cmd->modifier[0]); | |
57cd6508 | 15865 | return -EINVAL; |
c16ed4be | 15866 | } |
57cd6508 | 15867 | |
c2ff7370 VS |
15868 | /* |
15869 | * gen2/3 display engine uses the fence if present, | |
15870 | * so the tiling mode must match the fb modifier exactly. | |
15871 | */ | |
15872 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
15873 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
15874 | DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n"); | |
15875 | return -EINVAL; | |
15876 | } | |
15877 | ||
7b49f948 VS |
15878 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
15879 | mode_cmd->modifier[0], | |
b321803d DL |
15880 | mode_cmd->pixel_format); |
15881 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
15882 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
15883 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 15884 | return -EINVAL; |
c16ed4be | 15885 | } |
57cd6508 | 15886 | |
920a14b2 | 15887 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 15888 | mode_cmd->pixel_format); |
a35cdaa0 | 15889 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
15890 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
15891 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 15892 | "tiled" : "linear", |
a35cdaa0 | 15893 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 15894 | return -EINVAL; |
c16ed4be | 15895 | } |
5d7bd705 | 15896 | |
c2ff7370 VS |
15897 | /* |
15898 | * If there's a fence, enforce that | |
15899 | * the fb pitch and fence stride match. | |
15900 | */ | |
15901 | if (tiling != I915_TILING_NONE && | |
3e510a8e | 15902 | mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) { |
c16ed4be | 15903 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
3e510a8e CW |
15904 | mode_cmd->pitches[0], |
15905 | i915_gem_object_get_stride(obj)); | |
5d7bd705 | 15906 | return -EINVAL; |
c16ed4be | 15907 | } |
5d7bd705 | 15908 | |
57779d06 | 15909 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 15910 | switch (mode_cmd->pixel_format) { |
57779d06 | 15911 | case DRM_FORMAT_C8: |
04b3924d VS |
15912 | case DRM_FORMAT_RGB565: |
15913 | case DRM_FORMAT_XRGB8888: | |
15914 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
15915 | break; |
15916 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 15917 | if (INTEL_GEN(dev_priv) > 3) { |
b3c11ac2 EE |
15918 | DRM_DEBUG("unsupported pixel format: %s\n", |
15919 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57779d06 | 15920 | return -EINVAL; |
c16ed4be | 15921 | } |
57779d06 | 15922 | break; |
57779d06 | 15923 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 15924 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 15925 | INTEL_GEN(dev_priv) < 9) { |
b3c11ac2 EE |
15926 | DRM_DEBUG("unsupported pixel format: %s\n", |
15927 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
6c0fd451 DL |
15928 | return -EINVAL; |
15929 | } | |
15930 | break; | |
15931 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15932 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15933 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 15934 | if (INTEL_GEN(dev_priv) < 4) { |
b3c11ac2 EE |
15935 | DRM_DEBUG("unsupported pixel format: %s\n", |
15936 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57779d06 | 15937 | return -EINVAL; |
c16ed4be | 15938 | } |
b5626747 | 15939 | break; |
7531208b | 15940 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 15941 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
b3c11ac2 EE |
15942 | DRM_DEBUG("unsupported pixel format: %s\n", |
15943 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
7531208b DL |
15944 | return -EINVAL; |
15945 | } | |
15946 | break; | |
04b3924d VS |
15947 | case DRM_FORMAT_YUYV: |
15948 | case DRM_FORMAT_UYVY: | |
15949 | case DRM_FORMAT_YVYU: | |
15950 | case DRM_FORMAT_VYUY: | |
6315b5d3 | 15951 | if (INTEL_GEN(dev_priv) < 5) { |
b3c11ac2 EE |
15952 | DRM_DEBUG("unsupported pixel format: %s\n", |
15953 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57779d06 | 15954 | return -EINVAL; |
c16ed4be | 15955 | } |
57cd6508 CW |
15956 | break; |
15957 | default: | |
b3c11ac2 EE |
15958 | DRM_DEBUG("unsupported pixel format: %s\n", |
15959 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57cd6508 CW |
15960 | return -EINVAL; |
15961 | } | |
15962 | ||
90f9a336 VS |
15963 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15964 | if (mode_cmd->offsets[0] != 0) | |
15965 | return -EINVAL; | |
15966 | ||
c7d73f6a DV |
15967 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15968 | intel_fb->obj = obj; | |
15969 | ||
6687c906 VS |
15970 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
15971 | if (ret) | |
15972 | return ret; | |
2d7a215f | 15973 | |
79e53945 JB |
15974 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15975 | if (ret) { | |
15976 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15977 | return ret; | |
15978 | } | |
15979 | ||
0b05e1e0 VS |
15980 | intel_fb->obj->framebuffer_references++; |
15981 | ||
79e53945 JB |
15982 | return 0; |
15983 | } | |
15984 | ||
79e53945 JB |
15985 | static struct drm_framebuffer * |
15986 | intel_user_framebuffer_create(struct drm_device *dev, | |
15987 | struct drm_file *filp, | |
1eb83451 | 15988 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15989 | { |
dcb1394e | 15990 | struct drm_framebuffer *fb; |
05394f39 | 15991 | struct drm_i915_gem_object *obj; |
76dc3769 | 15992 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15993 | |
03ac0642 CW |
15994 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
15995 | if (!obj) | |
cce13ff7 | 15996 | return ERR_PTR(-ENOENT); |
79e53945 | 15997 | |
92907cbb | 15998 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e | 15999 | if (IS_ERR(fb)) |
f0cd5182 | 16000 | i915_gem_object_put(obj); |
dcb1394e LW |
16001 | |
16002 | return fb; | |
79e53945 JB |
16003 | } |
16004 | ||
778e23a9 CW |
16005 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
16006 | { | |
16007 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
16008 | ||
16009 | drm_atomic_state_default_release(state); | |
16010 | ||
16011 | i915_sw_fence_fini(&intel_state->commit_ready); | |
16012 | ||
16013 | kfree(state); | |
16014 | } | |
16015 | ||
79e53945 | 16016 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 16017 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 16018 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
16019 | .atomic_check = intel_atomic_check, |
16020 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
16021 | .atomic_state_alloc = intel_atomic_state_alloc, |
16022 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 16023 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
16024 | }; |
16025 | ||
88212941 ID |
16026 | /** |
16027 | * intel_init_display_hooks - initialize the display modesetting hooks | |
16028 | * @dev_priv: device private | |
16029 | */ | |
16030 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 16031 | { |
88212941 | 16032 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 16033 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
16034 | dev_priv->display.get_initial_plane_config = |
16035 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
16036 | dev_priv->display.crtc_compute_clock = |
16037 | haswell_crtc_compute_clock; | |
16038 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
16039 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 16040 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 16041 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
16042 | dev_priv->display.get_initial_plane_config = |
16043 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
16044 | dev_priv->display.crtc_compute_clock = |
16045 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
16046 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
16047 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 16048 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 16049 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
16050 | dev_priv->display.get_initial_plane_config = |
16051 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
16052 | dev_priv->display.crtc_compute_clock = |
16053 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
16054 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
16055 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 16056 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 16057 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
16058 | dev_priv->display.get_initial_plane_config = |
16059 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
16060 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
16061 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
16062 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
16063 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
16064 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16065 | dev_priv->display.get_initial_plane_config = | |
16066 | i9xx_get_initial_plane_config; | |
16067 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
16068 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
16069 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
16070 | } else if (IS_G4X(dev_priv)) { |
16071 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16072 | dev_priv->display.get_initial_plane_config = | |
16073 | i9xx_get_initial_plane_config; | |
16074 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
16075 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
16076 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
16077 | } else if (IS_PINEVIEW(dev_priv)) { |
16078 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16079 | dev_priv->display.get_initial_plane_config = | |
16080 | i9xx_get_initial_plane_config; | |
16081 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
16082 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
16083 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 16084 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 16085 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
16086 | dev_priv->display.get_initial_plane_config = |
16087 | i9xx_get_initial_plane_config; | |
d6dfee7a | 16088 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
16089 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
16090 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
16091 | } else { |
16092 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16093 | dev_priv->display.get_initial_plane_config = | |
16094 | i9xx_get_initial_plane_config; | |
16095 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
16096 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
16097 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 16098 | } |
e70236a8 | 16099 | |
e70236a8 | 16100 | /* Returns the core display clock speed */ |
88212941 | 16101 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
16102 | dev_priv->display.get_display_clock_speed = |
16103 | skylake_get_display_clock_speed; | |
89b3c3c7 | 16104 | else if (IS_GEN9_LP(dev_priv)) |
acd3f3d3 BP |
16105 | dev_priv->display.get_display_clock_speed = |
16106 | broxton_get_display_clock_speed; | |
88212941 | 16107 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
16108 | dev_priv->display.get_display_clock_speed = |
16109 | broadwell_get_display_clock_speed; | |
88212941 | 16110 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
16111 | dev_priv->display.get_display_clock_speed = |
16112 | haswell_get_display_clock_speed; | |
88212941 | 16113 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
16114 | dev_priv->display.get_display_clock_speed = |
16115 | valleyview_get_display_clock_speed; | |
88212941 | 16116 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
16117 | dev_priv->display.get_display_clock_speed = |
16118 | ilk_get_display_clock_speed; | |
c0f86832 | 16119 | else if (IS_I945G(dev_priv) || IS_I965G(dev_priv) || |
88212941 | 16120 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) |
e70236a8 JB |
16121 | dev_priv->display.get_display_clock_speed = |
16122 | i945_get_display_clock_speed; | |
88212941 | 16123 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
16124 | dev_priv->display.get_display_clock_speed = |
16125 | gm45_get_display_clock_speed; | |
c0f86832 | 16126 | else if (IS_I965GM(dev_priv)) |
34edce2f VS |
16127 | dev_priv->display.get_display_clock_speed = |
16128 | i965gm_get_display_clock_speed; | |
88212941 | 16129 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
16130 | dev_priv->display.get_display_clock_speed = |
16131 | pnv_get_display_clock_speed; | |
88212941 | 16132 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
16133 | dev_priv->display.get_display_clock_speed = |
16134 | g33_get_display_clock_speed; | |
88212941 | 16135 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
16136 | dev_priv->display.get_display_clock_speed = |
16137 | i915_get_display_clock_speed; | |
2a307c2e | 16138 | else if (IS_I945GM(dev_priv) || IS_I845G(dev_priv)) |
e70236a8 JB |
16139 | dev_priv->display.get_display_clock_speed = |
16140 | i9xx_misc_get_display_clock_speed; | |
88212941 | 16141 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
16142 | dev_priv->display.get_display_clock_speed = |
16143 | i915gm_get_display_clock_speed; | |
88212941 | 16144 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
16145 | dev_priv->display.get_display_clock_speed = |
16146 | i865_get_display_clock_speed; | |
88212941 | 16147 | else if (IS_I85X(dev_priv)) |
e70236a8 | 16148 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 16149 | i85x_get_display_clock_speed; |
623e01e5 | 16150 | else { /* 830 */ |
88212941 | 16151 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
16152 | dev_priv->display.get_display_clock_speed = |
16153 | i830_get_display_clock_speed; | |
623e01e5 | 16154 | } |
e70236a8 | 16155 | |
88212941 | 16156 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 16157 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 16158 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 16159 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 16160 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
16161 | /* FIXME: detect B0+ stepping and use auto training */ |
16162 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 16163 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 16164 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
16165 | } |
16166 | ||
16167 | if (IS_BROADWELL(dev_priv)) { | |
16168 | dev_priv->display.modeset_commit_cdclk = | |
16169 | broadwell_modeset_commit_cdclk; | |
16170 | dev_priv->display.modeset_calc_cdclk = | |
16171 | broadwell_modeset_calc_cdclk; | |
88212941 | 16172 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
16173 | dev_priv->display.modeset_commit_cdclk = |
16174 | valleyview_modeset_commit_cdclk; | |
16175 | dev_priv->display.modeset_calc_cdclk = | |
16176 | valleyview_modeset_calc_cdclk; | |
89b3c3c7 | 16177 | } else if (IS_GEN9_LP(dev_priv)) { |
27c329ed | 16178 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 16179 | bxt_modeset_commit_cdclk; |
27c329ed | 16180 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 16181 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
16182 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
16183 | dev_priv->display.modeset_commit_cdclk = | |
16184 | skl_modeset_commit_cdclk; | |
16185 | dev_priv->display.modeset_calc_cdclk = | |
16186 | skl_modeset_calc_cdclk; | |
e70236a8 | 16187 | } |
5a21b665 | 16188 | |
27082493 L |
16189 | if (dev_priv->info.gen >= 9) |
16190 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
16191 | else | |
16192 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
16193 | ||
5a21b665 DV |
16194 | switch (INTEL_INFO(dev_priv)->gen) { |
16195 | case 2: | |
16196 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
16197 | break; | |
16198 | ||
16199 | case 3: | |
16200 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
16201 | break; | |
16202 | ||
16203 | case 4: | |
16204 | case 5: | |
16205 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
16206 | break; | |
16207 | ||
16208 | case 6: | |
16209 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
16210 | break; | |
16211 | case 7: | |
16212 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
16213 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
16214 | break; | |
16215 | case 9: | |
16216 | /* Drop through - unsupported since execlist only. */ | |
16217 | default: | |
16218 | /* Default just returns -ENODEV to indicate unsupported */ | |
16219 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
16220 | } | |
e70236a8 JB |
16221 | } |
16222 | ||
b690e96c JB |
16223 | /* |
16224 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
16225 | * resume, or other times. This quirk makes sure that's the case for | |
16226 | * affected systems. | |
16227 | */ | |
0206e353 | 16228 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 16229 | { |
fac5e23e | 16230 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
16231 | |
16232 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 16233 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
16234 | } |
16235 | ||
b6b5d049 VS |
16236 | static void quirk_pipeb_force(struct drm_device *dev) |
16237 | { | |
fac5e23e | 16238 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
16239 | |
16240 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
16241 | DRM_INFO("applying pipe b force quirk\n"); | |
16242 | } | |
16243 | ||
435793df KP |
16244 | /* |
16245 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
16246 | */ | |
16247 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
16248 | { | |
fac5e23e | 16249 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 16250 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 16251 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
16252 | } |
16253 | ||
4dca20ef | 16254 | /* |
5a15ab5b CE |
16255 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
16256 | * brightness value | |
4dca20ef CE |
16257 | */ |
16258 | static void quirk_invert_brightness(struct drm_device *dev) | |
16259 | { | |
fac5e23e | 16260 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 16261 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 16262 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
16263 | } |
16264 | ||
9c72cc6f SD |
16265 | /* Some VBT's incorrectly indicate no backlight is present */ |
16266 | static void quirk_backlight_present(struct drm_device *dev) | |
16267 | { | |
fac5e23e | 16268 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
16269 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
16270 | DRM_INFO("applying backlight present quirk\n"); | |
16271 | } | |
16272 | ||
b690e96c JB |
16273 | struct intel_quirk { |
16274 | int device; | |
16275 | int subsystem_vendor; | |
16276 | int subsystem_device; | |
16277 | void (*hook)(struct drm_device *dev); | |
16278 | }; | |
16279 | ||
5f85f176 EE |
16280 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
16281 | struct intel_dmi_quirk { | |
16282 | void (*hook)(struct drm_device *dev); | |
16283 | const struct dmi_system_id (*dmi_id_list)[]; | |
16284 | }; | |
16285 | ||
16286 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
16287 | { | |
16288 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
16289 | return 1; | |
16290 | } | |
16291 | ||
16292 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
16293 | { | |
16294 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
16295 | { | |
16296 | .callback = intel_dmi_reverse_brightness, | |
16297 | .ident = "NCR Corporation", | |
16298 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
16299 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
16300 | }, | |
16301 | }, | |
16302 | { } /* terminating entry */ | |
16303 | }, | |
16304 | .hook = quirk_invert_brightness, | |
16305 | }, | |
16306 | }; | |
16307 | ||
c43b5634 | 16308 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
16309 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
16310 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
16311 | ||
b690e96c JB |
16312 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
16313 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
16314 | ||
5f080c0f VS |
16315 | /* 830 needs to leave pipe A & dpll A up */ |
16316 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
16317 | ||
b6b5d049 VS |
16318 | /* 830 needs to leave pipe B & dpll B up */ |
16319 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
16320 | ||
435793df KP |
16321 | /* Lenovo U160 cannot use SSC on LVDS */ |
16322 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
16323 | |
16324 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
16325 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 16326 | |
be505f64 AH |
16327 | /* Acer Aspire 5734Z must invert backlight brightness */ |
16328 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
16329 | ||
16330 | /* Acer/eMachines G725 */ | |
16331 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
16332 | ||
16333 | /* Acer/eMachines e725 */ | |
16334 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
16335 | ||
16336 | /* Acer/Packard Bell NCL20 */ | |
16337 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
16338 | ||
16339 | /* Acer Aspire 4736Z */ | |
16340 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
16341 | |
16342 | /* Acer Aspire 5336 */ | |
16343 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
16344 | |
16345 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
16346 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 16347 | |
dfb3d47b SD |
16348 | /* Acer C720 Chromebook (Core i3 4005U) */ |
16349 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
16350 | ||
b2a9601c | 16351 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
16352 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
16353 | ||
1b9448b0 JN |
16354 | /* Apple Macbook 4,1 */ |
16355 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
16356 | ||
d4967d8c SD |
16357 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
16358 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
16359 | |
16360 | /* HP Chromebook 14 (Celeron 2955U) */ | |
16361 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
16362 | |
16363 | /* Dell Chromebook 11 */ | |
16364 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
16365 | |
16366 | /* Dell Chromebook 11 (2015 version) */ | |
16367 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
16368 | }; |
16369 | ||
16370 | static void intel_init_quirks(struct drm_device *dev) | |
16371 | { | |
16372 | struct pci_dev *d = dev->pdev; | |
16373 | int i; | |
16374 | ||
16375 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
16376 | struct intel_quirk *q = &intel_quirks[i]; | |
16377 | ||
16378 | if (d->device == q->device && | |
16379 | (d->subsystem_vendor == q->subsystem_vendor || | |
16380 | q->subsystem_vendor == PCI_ANY_ID) && | |
16381 | (d->subsystem_device == q->subsystem_device || | |
16382 | q->subsystem_device == PCI_ANY_ID)) | |
16383 | q->hook(dev); | |
16384 | } | |
5f85f176 EE |
16385 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
16386 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
16387 | intel_dmi_quirks[i].hook(dev); | |
16388 | } | |
b690e96c JB |
16389 | } |
16390 | ||
9cce37f4 | 16391 | /* Disable the VGA plane that we never use */ |
29b74b7f | 16392 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 16393 | { |
52a05c30 | 16394 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 16395 | u8 sr1; |
920a14b2 | 16396 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 16397 | |
2b37c616 | 16398 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 16399 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 16400 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
16401 | sr1 = inb(VGA_SR_DATA); |
16402 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 16403 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
16404 | udelay(300); |
16405 | ||
01f5a626 | 16406 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
16407 | POSTING_READ(vga_reg); |
16408 | } | |
16409 | ||
f817586c DV |
16410 | void intel_modeset_init_hw(struct drm_device *dev) |
16411 | { | |
fac5e23e | 16412 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 16413 | |
4c75b940 | 16414 | intel_update_cdclk(dev_priv); |
1a617b77 ML |
16415 | |
16416 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
16417 | ||
46f16e63 | 16418 | intel_init_clock_gating(dev_priv); |
f817586c DV |
16419 | } |
16420 | ||
d93c0372 MR |
16421 | /* |
16422 | * Calculate what we think the watermarks should be for the state we've read | |
16423 | * out of the hardware and then immediately program those watermarks so that | |
16424 | * we ensure the hardware settings match our internal state. | |
16425 | * | |
16426 | * We can calculate what we think WM's should be by creating a duplicate of the | |
16427 | * current state (which was constructed during hardware readout) and running it | |
16428 | * through the atomic check code to calculate new watermark values in the | |
16429 | * state object. | |
16430 | */ | |
16431 | static void sanitize_watermarks(struct drm_device *dev) | |
16432 | { | |
16433 | struct drm_i915_private *dev_priv = to_i915(dev); | |
16434 | struct drm_atomic_state *state; | |
ccf010fb | 16435 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
16436 | struct drm_crtc *crtc; |
16437 | struct drm_crtc_state *cstate; | |
16438 | struct drm_modeset_acquire_ctx ctx; | |
16439 | int ret; | |
16440 | int i; | |
16441 | ||
16442 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 16443 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
16444 | return; |
16445 | ||
16446 | /* | |
16447 | * We need to hold connection_mutex before calling duplicate_state so | |
16448 | * that the connector loop is protected. | |
16449 | */ | |
16450 | drm_modeset_acquire_init(&ctx, 0); | |
16451 | retry: | |
0cd1262d | 16452 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
16453 | if (ret == -EDEADLK) { |
16454 | drm_modeset_backoff(&ctx); | |
16455 | goto retry; | |
16456 | } else if (WARN_ON(ret)) { | |
0cd1262d | 16457 | goto fail; |
d93c0372 MR |
16458 | } |
16459 | ||
16460 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
16461 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 16462 | goto fail; |
d93c0372 | 16463 | |
ccf010fb ML |
16464 | intel_state = to_intel_atomic_state(state); |
16465 | ||
ed4a6a7c MR |
16466 | /* |
16467 | * Hardware readout is the only time we don't want to calculate | |
16468 | * intermediate watermarks (since we don't trust the current | |
16469 | * watermarks). | |
16470 | */ | |
ccf010fb | 16471 | intel_state->skip_intermediate_wm = true; |
ed4a6a7c | 16472 | |
d93c0372 MR |
16473 | ret = intel_atomic_check(dev, state); |
16474 | if (ret) { | |
16475 | /* | |
16476 | * If we fail here, it means that the hardware appears to be | |
16477 | * programmed in a way that shouldn't be possible, given our | |
16478 | * understanding of watermark requirements. This might mean a | |
16479 | * mistake in the hardware readout code or a mistake in the | |
16480 | * watermark calculations for a given platform. Raise a WARN | |
16481 | * so that this is noticeable. | |
16482 | * | |
16483 | * If this actually happens, we'll have to just leave the | |
16484 | * BIOS-programmed watermarks untouched and hope for the best. | |
16485 | */ | |
16486 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 16487 | goto put_state; |
d93c0372 MR |
16488 | } |
16489 | ||
16490 | /* Write calculated watermark values back */ | |
d93c0372 MR |
16491 | for_each_crtc_in_state(state, crtc, cstate, i) { |
16492 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
16493 | ||
ed4a6a7c | 16494 | cs->wm.need_postvbl_update = true; |
ccf010fb | 16495 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
16496 | } |
16497 | ||
b9a1b717 | 16498 | put_state: |
0853695c | 16499 | drm_atomic_state_put(state); |
0cd1262d | 16500 | fail: |
d93c0372 MR |
16501 | drm_modeset_drop_locks(&ctx); |
16502 | drm_modeset_acquire_fini(&ctx); | |
16503 | } | |
16504 | ||
b079bd17 | 16505 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 16506 | { |
72e96d64 JL |
16507 | struct drm_i915_private *dev_priv = to_i915(dev); |
16508 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 16509 | enum pipe pipe; |
46f297fb | 16510 | struct intel_crtc *crtc; |
79e53945 JB |
16511 | |
16512 | drm_mode_config_init(dev); | |
16513 | ||
16514 | dev->mode_config.min_width = 0; | |
16515 | dev->mode_config.min_height = 0; | |
16516 | ||
019d96cb DA |
16517 | dev->mode_config.preferred_depth = 24; |
16518 | dev->mode_config.prefer_shadow = 1; | |
16519 | ||
25bab385 TU |
16520 | dev->mode_config.allow_fb_modifiers = true; |
16521 | ||
e6ecefaa | 16522 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 16523 | |
b690e96c JB |
16524 | intel_init_quirks(dev); |
16525 | ||
62d75df7 | 16526 | intel_init_pm(dev_priv); |
1fa61106 | 16527 | |
b7f05d4a | 16528 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 16529 | return 0; |
e3c74757 | 16530 | |
69f92f67 LW |
16531 | /* |
16532 | * There may be no VBT; and if the BIOS enabled SSC we can | |
16533 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
16534 | * BIOS isn't using it, don't assume it will work even if the VBT | |
16535 | * indicates as much. | |
16536 | */ | |
6e266956 | 16537 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
16538 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
16539 | DREF_SSC1_ENABLE); | |
16540 | ||
16541 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
16542 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
16543 | bios_lvds_use_ssc ? "en" : "dis", | |
16544 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
16545 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
16546 | } | |
16547 | } | |
16548 | ||
5db94019 | 16549 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
16550 | dev->mode_config.max_width = 2048; |
16551 | dev->mode_config.max_height = 2048; | |
5db94019 | 16552 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
16553 | dev->mode_config.max_width = 4096; |
16554 | dev->mode_config.max_height = 4096; | |
79e53945 | 16555 | } else { |
a6c45cf0 CW |
16556 | dev->mode_config.max_width = 8192; |
16557 | dev->mode_config.max_height = 8192; | |
79e53945 | 16558 | } |
068be561 | 16559 | |
2a307c2e JN |
16560 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
16561 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 16562 | dev->mode_config.cursor_height = 1023; |
5db94019 | 16563 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
16564 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
16565 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
16566 | } else { | |
16567 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
16568 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
16569 | } | |
16570 | ||
72e96d64 | 16571 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 16572 | |
28c97730 | 16573 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
16574 | INTEL_INFO(dev_priv)->num_pipes, |
16575 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 16576 | |
055e393f | 16577 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
16578 | int ret; |
16579 | ||
5ab0d85b | 16580 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
16581 | if (ret) { |
16582 | drm_mode_config_cleanup(dev); | |
16583 | return ret; | |
16584 | } | |
79e53945 JB |
16585 | } |
16586 | ||
bfa7df01 | 16587 | intel_update_czclk(dev_priv); |
4c75b940 | 16588 | intel_update_cdclk(dev_priv); |
6a259b1f | 16589 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; |
bfa7df01 | 16590 | |
e72f9fbf | 16591 | intel_shared_dpll_init(dev); |
ee7b9f93 | 16592 | |
b2045352 | 16593 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 16594 | intel_update_max_cdclk(dev_priv); |
b2045352 | 16595 | |
9cce37f4 | 16596 | /* Just disable it once at startup */ |
29b74b7f | 16597 | i915_disable_vga(dev_priv); |
c39055b0 | 16598 | intel_setup_outputs(dev_priv); |
11be49eb | 16599 | |
6e9f798d | 16600 | drm_modeset_lock_all(dev); |
043e9bda | 16601 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 16602 | drm_modeset_unlock_all(dev); |
46f297fb | 16603 | |
d3fcc808 | 16604 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
16605 | struct intel_initial_plane_config plane_config = {}; |
16606 | ||
46f297fb JB |
16607 | if (!crtc->active) |
16608 | continue; | |
16609 | ||
46f297fb | 16610 | /* |
46f297fb JB |
16611 | * Note that reserving the BIOS fb up front prevents us |
16612 | * from stuffing other stolen allocations like the ring | |
16613 | * on top. This prevents some ugliness at boot time, and | |
16614 | * can even allow for smooth boot transitions if the BIOS | |
16615 | * fb is large enough for the active pipe configuration. | |
16616 | */ | |
eeebeac5 ML |
16617 | dev_priv->display.get_initial_plane_config(crtc, |
16618 | &plane_config); | |
16619 | ||
16620 | /* | |
16621 | * If the fb is shared between multiple heads, we'll | |
16622 | * just get the first one. | |
16623 | */ | |
16624 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 16625 | } |
d93c0372 MR |
16626 | |
16627 | /* | |
16628 | * Make sure hardware watermarks really match the state we read out. | |
16629 | * Note that we need to do this after reconstructing the BIOS fb's | |
16630 | * since the watermark calculation done here will use pstate->fb. | |
16631 | */ | |
16632 | sanitize_watermarks(dev); | |
b079bd17 VS |
16633 | |
16634 | return 0; | |
2c7111db CW |
16635 | } |
16636 | ||
7fad798e DV |
16637 | static void intel_enable_pipe_a(struct drm_device *dev) |
16638 | { | |
16639 | struct intel_connector *connector; | |
16640 | struct drm_connector *crt = NULL; | |
16641 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 16642 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
16643 | |
16644 | /* We can't just switch on the pipe A, we need to set things up with a | |
16645 | * proper mode and output configuration. As a gross hack, enable pipe A | |
16646 | * by enabling the load detect pipe once. */ | |
3a3371ff | 16647 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
16648 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
16649 | crt = &connector->base; | |
16650 | break; | |
16651 | } | |
16652 | } | |
16653 | ||
16654 | if (!crt) | |
16655 | return; | |
16656 | ||
208bf9fd | 16657 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 16658 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
16659 | } |
16660 | ||
fa555837 DV |
16661 | static bool |
16662 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
16663 | { | |
b7f05d4a | 16664 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 16665 | u32 val; |
fa555837 | 16666 | |
b7f05d4a | 16667 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
16668 | return true; |
16669 | ||
649636ef | 16670 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
16671 | |
16672 | if ((val & DISPLAY_PLANE_ENABLE) && | |
16673 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
16674 | return false; | |
16675 | ||
16676 | return true; | |
16677 | } | |
16678 | ||
02e93c35 VS |
16679 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
16680 | { | |
16681 | struct drm_device *dev = crtc->base.dev; | |
16682 | struct intel_encoder *encoder; | |
16683 | ||
16684 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
16685 | return true; | |
16686 | ||
16687 | return false; | |
16688 | } | |
16689 | ||
496b0fc3 ML |
16690 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
16691 | { | |
16692 | struct drm_device *dev = encoder->base.dev; | |
16693 | struct intel_connector *connector; | |
16694 | ||
16695 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
16696 | return connector; | |
16697 | ||
16698 | return NULL; | |
16699 | } | |
16700 | ||
a168f5b3 VS |
16701 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
16702 | enum transcoder pch_transcoder) | |
16703 | { | |
16704 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
16705 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
16706 | } | |
16707 | ||
24929352 DV |
16708 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
16709 | { | |
16710 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 16711 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 16712 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 16713 | |
24929352 | 16714 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
16715 | if (!transcoder_is_dsi(cpu_transcoder)) { |
16716 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
16717 | ||
16718 | I915_WRITE(reg, | |
16719 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
16720 | } | |
24929352 | 16721 | |
d3eaf884 | 16722 | /* restore vblank interrupts to correct state */ |
9625604c | 16723 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 16724 | if (crtc->active) { |
f9cd7b88 VS |
16725 | struct intel_plane *plane; |
16726 | ||
9625604c | 16727 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
16728 | |
16729 | /* Disable everything but the primary plane */ | |
16730 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
16731 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
16732 | continue; | |
16733 | ||
16734 | plane->disable_plane(&plane->base, &crtc->base); | |
16735 | } | |
9625604c | 16736 | } |
d3eaf884 | 16737 | |
24929352 | 16738 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
16739 | * disable the crtc (and hence change the state) if it is wrong. Note |
16740 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 16741 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
16742 | bool plane; |
16743 | ||
78108b7c VS |
16744 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
16745 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
16746 | |
16747 | /* Pipe has the wrong plane attached and the plane is active. | |
16748 | * Temporarily change the plane mapping and disable everything | |
16749 | * ... */ | |
16750 | plane = crtc->plane; | |
936e71e3 | 16751 | to_intel_plane_state(crtc->base.primary->state)->base.visible = true; |
24929352 | 16752 | crtc->plane = !plane; |
b17d48e2 | 16753 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16754 | crtc->plane = plane; |
24929352 | 16755 | } |
24929352 | 16756 | |
7fad798e DV |
16757 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
16758 | crtc->pipe == PIPE_A && !crtc->active) { | |
16759 | /* BIOS forgot to enable pipe A, this mostly happens after | |
16760 | * resume. Force-enable the pipe to fix this, the update_dpms | |
16761 | * call below we restore the pipe to the right state, but leave | |
16762 | * the required bits on. */ | |
16763 | intel_enable_pipe_a(dev); | |
16764 | } | |
16765 | ||
24929352 DV |
16766 | /* Adjust the state of the output pipe according to whether we |
16767 | * have active connectors/encoders. */ | |
842e0307 | 16768 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 16769 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16770 | |
49cff963 | 16771 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
16772 | /* |
16773 | * We start out with underrun reporting disabled to avoid races. | |
16774 | * For correct bookkeeping mark this on active crtcs. | |
16775 | * | |
c5ab3bc0 DV |
16776 | * Also on gmch platforms we dont have any hardware bits to |
16777 | * disable the underrun reporting. Which means we need to start | |
16778 | * out with underrun reporting disabled also on inactive pipes, | |
16779 | * since otherwise we'll complain about the garbage we read when | |
16780 | * e.g. coming up after runtime pm. | |
16781 | * | |
4cc31489 DV |
16782 | * No protection against concurrent access is required - at |
16783 | * worst a fifo underrun happens which also sets this to false. | |
16784 | */ | |
16785 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
16786 | /* |
16787 | * We track the PCH trancoder underrun reporting state | |
16788 | * within the crtc. With crtc for pipe A housing the underrun | |
16789 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
16790 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
16791 | * and marking underrun reporting as disabled for the non-existing | |
16792 | * PCH transcoders B and C would prevent enabling the south | |
16793 | * error interrupt (see cpt_can_enable_serr_int()). | |
16794 | */ | |
16795 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
16796 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 16797 | } |
24929352 DV |
16798 | } |
16799 | ||
16800 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
16801 | { | |
16802 | struct intel_connector *connector; | |
24929352 DV |
16803 | |
16804 | /* We need to check both for a crtc link (meaning that the | |
16805 | * encoder is active and trying to read from a pipe) and the | |
16806 | * pipe itself being active. */ | |
16807 | bool has_active_crtc = encoder->base.crtc && | |
16808 | to_intel_crtc(encoder->base.crtc)->active; | |
16809 | ||
496b0fc3 ML |
16810 | connector = intel_encoder_find_connector(encoder); |
16811 | if (connector && !has_active_crtc) { | |
24929352 DV |
16812 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
16813 | encoder->base.base.id, | |
8e329a03 | 16814 | encoder->base.name); |
24929352 DV |
16815 | |
16816 | /* Connector is active, but has no active pipe. This is | |
16817 | * fallout from our resume register restoring. Disable | |
16818 | * the encoder manually again. */ | |
16819 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
16820 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
16821 | ||
24929352 DV |
16822 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
16823 | encoder->base.base.id, | |
8e329a03 | 16824 | encoder->base.name); |
fd6bbda9 | 16825 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 16826 | if (encoder->post_disable) |
fd6bbda9 | 16827 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 16828 | } |
7f1950fb | 16829 | encoder->base.crtc = NULL; |
24929352 DV |
16830 | |
16831 | /* Inconsistent output/port/pipe state happens presumably due to | |
16832 | * a bug in one of the get_hw_state functions. Or someplace else | |
16833 | * in our code, like the register restore mess on resume. Clamp | |
16834 | * things to off as a safer default. */ | |
fd6bbda9 ML |
16835 | |
16836 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16837 | connector->base.encoder = NULL; | |
24929352 DV |
16838 | } |
16839 | /* Enabled encoders without active connectors will be fixed in | |
16840 | * the crtc fixup. */ | |
16841 | } | |
16842 | ||
29b74b7f | 16843 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 16844 | { |
920a14b2 | 16845 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 16846 | |
04098753 ID |
16847 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
16848 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 16849 | i915_disable_vga(dev_priv); |
04098753 ID |
16850 | } |
16851 | } | |
16852 | ||
29b74b7f | 16853 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 16854 | { |
8dc8a27c PZ |
16855 | /* This function can be called both from intel_modeset_setup_hw_state or |
16856 | * at a very early point in our resume sequence, where the power well | |
16857 | * structures are not yet restored. Since this function is at a very | |
16858 | * paranoid "someone might have enabled VGA while we were not looking" | |
16859 | * level, just check if the power well is enabled instead of trying to | |
16860 | * follow the "don't touch the power well if we don't need it" policy | |
16861 | * the rest of the driver uses. */ | |
6392f847 | 16862 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
16863 | return; |
16864 | ||
29b74b7f | 16865 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
16866 | |
16867 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
16868 | } |
16869 | ||
f9cd7b88 | 16870 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 16871 | { |
f9cd7b88 | 16872 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 16873 | |
f9cd7b88 | 16874 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
16875 | } |
16876 | ||
f9cd7b88 VS |
16877 | /* FIXME read out full plane state for all planes */ |
16878 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 16879 | { |
b26d3ea3 | 16880 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 16881 | struct intel_plane_state *plane_state = |
b26d3ea3 | 16882 | to_intel_plane_state(primary->state); |
d032ffa0 | 16883 | |
936e71e3 | 16884 | plane_state->base.visible = crtc->active && |
b26d3ea3 ML |
16885 | primary_get_hw_state(to_intel_plane(primary)); |
16886 | ||
936e71e3 | 16887 | if (plane_state->base.visible) |
b26d3ea3 | 16888 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); |
98ec7739 VS |
16889 | } |
16890 | ||
30e984df | 16891 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 16892 | { |
fac5e23e | 16893 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 16894 | enum pipe pipe; |
24929352 DV |
16895 | struct intel_crtc *crtc; |
16896 | struct intel_encoder *encoder; | |
16897 | struct intel_connector *connector; | |
5358901f | 16898 | int i; |
24929352 | 16899 | |
565602d7 ML |
16900 | dev_priv->active_crtcs = 0; |
16901 | ||
d3fcc808 | 16902 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
16903 | struct intel_crtc_state *crtc_state = crtc->config; |
16904 | int pixclk = 0; | |
3b117c8f | 16905 | |
ec2dc6a0 | 16906 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
16907 | memset(crtc_state, 0, sizeof(*crtc_state)); |
16908 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 16909 | |
565602d7 ML |
16910 | crtc_state->base.active = crtc_state->base.enable = |
16911 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
16912 | ||
16913 | crtc->base.enabled = crtc_state->base.enable; | |
16914 | crtc->active = crtc_state->base.active; | |
16915 | ||
16916 | if (crtc_state->base.active) { | |
16917 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
16918 | ||
c89e39f3 | 16919 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 16920 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 16921 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
16922 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
16923 | else | |
16924 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
16925 | |
16926 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
16927 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
16928 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
16929 | } |
16930 | ||
16931 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 16932 | |
f9cd7b88 | 16933 | readout_plane_state(crtc); |
24929352 | 16934 | |
78108b7c VS |
16935 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
16936 | crtc->base.base.id, crtc->base.name, | |
08c4d7fc | 16937 | enableddisabled(crtc->active)); |
24929352 DV |
16938 | } |
16939 | ||
5358901f DV |
16940 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16941 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16942 | ||
2edd6443 ACO |
16943 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16944 | &pll->config.hw_state); | |
3e369b76 | 16945 | pll->config.crtc_mask = 0; |
d3fcc808 | 16946 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16947 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16948 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16949 | } |
2dd66ebd | 16950 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16951 | |
1e6f2ddc | 16952 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16953 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16954 | } |
16955 | ||
b2784e15 | 16956 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16957 | pipe = 0; |
16958 | ||
16959 | if (encoder->get_hw_state(encoder, &pipe)) { | |
98187836 | 16960 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 16961 | |
045ac3b5 | 16962 | encoder->base.crtc = &crtc->base; |
253c84c8 | 16963 | crtc->config->output_types |= 1 << encoder->type; |
6e3c9717 | 16964 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16965 | } else { |
16966 | encoder->base.crtc = NULL; | |
16967 | } | |
16968 | ||
6f2bcceb | 16969 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
16970 | encoder->base.base.id, encoder->base.name, |
16971 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 16972 | pipe_name(pipe)); |
24929352 DV |
16973 | } |
16974 | ||
3a3371ff | 16975 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16976 | if (connector->get_hw_state(connector)) { |
16977 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16978 | |
16979 | encoder = connector->encoder; | |
16980 | connector->base.encoder = &encoder->base; | |
16981 | ||
16982 | if (encoder->base.crtc && | |
16983 | encoder->base.crtc->state->active) { | |
16984 | /* | |
16985 | * This has to be done during hardware readout | |
16986 | * because anything calling .crtc_disable may | |
16987 | * rely on the connector_mask being accurate. | |
16988 | */ | |
16989 | encoder->base.crtc->state->connector_mask |= | |
16990 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16991 | encoder->base.crtc->state->encoder_mask |= |
16992 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16993 | } |
16994 | ||
24929352 DV |
16995 | } else { |
16996 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16997 | connector->base.encoder = NULL; | |
16998 | } | |
16999 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
17000 | connector->base.base.id, connector->base.name, |
17001 | enableddisabled(connector->base.encoder)); | |
24929352 | 17002 | } |
7f4c6284 VS |
17003 | |
17004 | for_each_intel_crtc(dev, crtc) { | |
17005 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
17006 | ||
17007 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
17008 | if (crtc->base.state->active) { | |
17009 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
17010 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
17011 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
17012 | ||
17013 | /* | |
17014 | * The initial mode needs to be set in order to keep | |
17015 | * the atomic core happy. It wants a valid mode if the | |
17016 | * crtc's enabled, so we do the above call. | |
17017 | * | |
17018 | * At this point some state updated by the connectors | |
17019 | * in their ->detect() callback has not run yet, so | |
17020 | * no recalculation can be done yet. | |
17021 | * | |
17022 | * Even if we could do a recalculation and modeset | |
17023 | * right now it would cause a double modeset if | |
17024 | * fbdev or userspace chooses a different initial mode. | |
17025 | * | |
17026 | * If that happens, someone indicated they wanted a | |
17027 | * mode change, which means it's safe to do a full | |
17028 | * recalculation. | |
17029 | */ | |
17030 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
17031 | |
17032 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
17033 | update_scanline_offset(crtc); | |
7f4c6284 | 17034 | } |
e3b247da VS |
17035 | |
17036 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 17037 | } |
30e984df DV |
17038 | } |
17039 | ||
043e9bda ML |
17040 | /* Scan out the current hw modeset state, |
17041 | * and sanitizes it to the current state | |
17042 | */ | |
17043 | static void | |
17044 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 17045 | { |
fac5e23e | 17046 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 17047 | enum pipe pipe; |
30e984df DV |
17048 | struct intel_crtc *crtc; |
17049 | struct intel_encoder *encoder; | |
35c95375 | 17050 | int i; |
30e984df DV |
17051 | |
17052 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
17053 | |
17054 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 17055 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
17056 | intel_sanitize_encoder(encoder); |
17057 | } | |
17058 | ||
055e393f | 17059 | for_each_pipe(dev_priv, pipe) { |
98187836 | 17060 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 17061 | |
24929352 | 17062 | intel_sanitize_crtc(crtc); |
6e3c9717 ACO |
17063 | intel_dump_pipe_config(crtc, crtc->config, |
17064 | "[setup_hw_state]"); | |
24929352 | 17065 | } |
9a935856 | 17066 | |
d29b2f9d ACO |
17067 | intel_modeset_update_connector_atomic_state(dev); |
17068 | ||
35c95375 DV |
17069 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
17070 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
17071 | ||
2dd66ebd | 17072 | if (!pll->on || pll->active_mask) |
35c95375 DV |
17073 | continue; |
17074 | ||
17075 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
17076 | ||
2edd6443 | 17077 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
17078 | pll->on = false; |
17079 | } | |
17080 | ||
920a14b2 | 17081 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6eb1a681 | 17082 | vlv_wm_get_hw_state(dev); |
5db94019 | 17083 | else if (IS_GEN9(dev_priv)) |
3078999f | 17084 | skl_wm_get_hw_state(dev); |
6e266956 | 17085 | else if (HAS_PCH_SPLIT(dev_priv)) |
243e6a44 | 17086 | ilk_wm_get_hw_state(dev); |
292b990e ML |
17087 | |
17088 | for_each_intel_crtc(dev, crtc) { | |
17089 | unsigned long put_domains; | |
17090 | ||
74bff5f9 | 17091 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
17092 | if (WARN_ON(put_domains)) |
17093 | modeset_put_power_domains(dev_priv, put_domains); | |
17094 | } | |
17095 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
17096 | |
17097 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 17098 | } |
7d0bc1ea | 17099 | |
043e9bda ML |
17100 | void intel_display_resume(struct drm_device *dev) |
17101 | { | |
e2c8b870 ML |
17102 | struct drm_i915_private *dev_priv = to_i915(dev); |
17103 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
17104 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 17105 | int ret; |
f30da187 | 17106 | |
e2c8b870 | 17107 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
17108 | if (state) |
17109 | state->acquire_ctx = &ctx; | |
043e9bda | 17110 | |
ea49c9ac ML |
17111 | /* |
17112 | * This is a cludge because with real atomic modeset mode_config.mutex | |
17113 | * won't be taken. Unfortunately some probed state like | |
17114 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
17115 | * it here for now. | |
17116 | */ | |
17117 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 17118 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 17119 | |
73974893 ML |
17120 | while (1) { |
17121 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
17122 | if (ret != -EDEADLK) | |
17123 | break; | |
043e9bda | 17124 | |
e2c8b870 | 17125 | drm_modeset_backoff(&ctx); |
e2c8b870 | 17126 | } |
043e9bda | 17127 | |
73974893 ML |
17128 | if (!ret) |
17129 | ret = __intel_display_resume(dev, state); | |
17130 | ||
e2c8b870 ML |
17131 | drm_modeset_drop_locks(&ctx); |
17132 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 17133 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 17134 | |
0853695c | 17135 | if (ret) |
e2c8b870 | 17136 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
0853695c | 17137 | drm_atomic_state_put(state); |
2c7111db CW |
17138 | } |
17139 | ||
17140 | void intel_modeset_gem_init(struct drm_device *dev) | |
17141 | { | |
dc97997a | 17142 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 17143 | struct drm_crtc *c; |
2ff8fde1 | 17144 | struct drm_i915_gem_object *obj; |
484b41dd | 17145 | |
dc97997a | 17146 | intel_init_gt_powersave(dev_priv); |
ae48434c | 17147 | |
1833b134 | 17148 | intel_modeset_init_hw(dev); |
02e792fb | 17149 | |
1ee8da6d | 17150 | intel_setup_overlay(dev_priv); |
484b41dd JB |
17151 | |
17152 | /* | |
17153 | * Make sure any fbs we allocated at startup are properly | |
17154 | * pinned & fenced. When we do the allocation it's too early | |
17155 | * for this. | |
17156 | */ | |
70e1e0ec | 17157 | for_each_crtc(dev, c) { |
058d88c4 CW |
17158 | struct i915_vma *vma; |
17159 | ||
2ff8fde1 MR |
17160 | obj = intel_fb_obj(c->primary->fb); |
17161 | if (obj == NULL) | |
484b41dd JB |
17162 | continue; |
17163 | ||
e0d6149b | 17164 | mutex_lock(&dev->struct_mutex); |
058d88c4 | 17165 | vma = intel_pin_and_fence_fb_obj(c->primary->fb, |
3465c580 | 17166 | c->primary->state->rotation); |
e0d6149b | 17167 | mutex_unlock(&dev->struct_mutex); |
058d88c4 | 17168 | if (IS_ERR(vma)) { |
484b41dd JB |
17169 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
17170 | to_intel_crtc(c)->pipe); | |
66e514c1 | 17171 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 17172 | c->primary->fb = NULL; |
36750f28 | 17173 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 17174 | update_state_fb(c->primary); |
36750f28 | 17175 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
17176 | } |
17177 | } | |
1ebaa0b9 CW |
17178 | } |
17179 | ||
17180 | int intel_connector_register(struct drm_connector *connector) | |
17181 | { | |
17182 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
17183 | int ret; | |
17184 | ||
17185 | ret = intel_backlight_device_register(intel_connector); | |
17186 | if (ret) | |
17187 | goto err; | |
17188 | ||
17189 | return 0; | |
0962c3c9 | 17190 | |
1ebaa0b9 CW |
17191 | err: |
17192 | return ret; | |
79e53945 JB |
17193 | } |
17194 | ||
c191eca1 | 17195 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 17196 | { |
e63d87c0 | 17197 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 17198 | |
e63d87c0 | 17199 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 17200 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
17201 | } |
17202 | ||
79e53945 JB |
17203 | void intel_modeset_cleanup(struct drm_device *dev) |
17204 | { | |
fac5e23e | 17205 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 17206 | |
dc97997a | 17207 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 17208 | |
fd0c0642 DV |
17209 | /* |
17210 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 17211 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
17212 | * experience fancy races otherwise. |
17213 | */ | |
2aeb7d3a | 17214 | intel_irq_uninstall(dev_priv); |
eb21b92b | 17215 | |
fd0c0642 DV |
17216 | /* |
17217 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
17218 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
17219 | */ | |
f87ea761 | 17220 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 17221 | |
723bfd70 JB |
17222 | intel_unregister_dsm_handler(); |
17223 | ||
c937ab3e | 17224 | intel_fbc_global_disable(dev_priv); |
69341a5e | 17225 | |
1630fe75 CW |
17226 | /* flush any delayed tasks or pending work */ |
17227 | flush_scheduled_work(); | |
17228 | ||
79e53945 | 17229 | drm_mode_config_cleanup(dev); |
4d7bb011 | 17230 | |
1ee8da6d | 17231 | intel_cleanup_overlay(dev_priv); |
ae48434c | 17232 | |
dc97997a | 17233 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 17234 | |
40196446 | 17235 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
17236 | } |
17237 | ||
df0e9248 CW |
17238 | void intel_connector_attach_encoder(struct intel_connector *connector, |
17239 | struct intel_encoder *encoder) | |
17240 | { | |
17241 | connector->encoder = encoder; | |
17242 | drm_mode_connector_attach_encoder(&connector->base, | |
17243 | &encoder->base); | |
79e53945 | 17244 | } |
28d52043 DA |
17245 | |
17246 | /* | |
17247 | * set vga decode state - true == enable VGA decode | |
17248 | */ | |
6315b5d3 | 17249 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 17250 | { |
6315b5d3 | 17251 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
17252 | u16 gmch_ctrl; |
17253 | ||
75fa041d CW |
17254 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
17255 | DRM_ERROR("failed to read control word\n"); | |
17256 | return -EIO; | |
17257 | } | |
17258 | ||
c0cc8a55 CW |
17259 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
17260 | return 0; | |
17261 | ||
28d52043 DA |
17262 | if (state) |
17263 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
17264 | else | |
17265 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
17266 | |
17267 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
17268 | DRM_ERROR("failed to write control word\n"); | |
17269 | return -EIO; | |
17270 | } | |
17271 | ||
28d52043 DA |
17272 | return 0; |
17273 | } | |
c4a1d9e4 | 17274 | |
98a2f411 CW |
17275 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
17276 | ||
c4a1d9e4 | 17277 | struct intel_display_error_state { |
ff57f1b0 PZ |
17278 | |
17279 | u32 power_well_driver; | |
17280 | ||
63b66e5b CW |
17281 | int num_transcoders; |
17282 | ||
c4a1d9e4 CW |
17283 | struct intel_cursor_error_state { |
17284 | u32 control; | |
17285 | u32 position; | |
17286 | u32 base; | |
17287 | u32 size; | |
52331309 | 17288 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
17289 | |
17290 | struct intel_pipe_error_state { | |
ddf9c536 | 17291 | bool power_domain_on; |
c4a1d9e4 | 17292 | u32 source; |
f301b1e1 | 17293 | u32 stat; |
52331309 | 17294 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
17295 | |
17296 | struct intel_plane_error_state { | |
17297 | u32 control; | |
17298 | u32 stride; | |
17299 | u32 size; | |
17300 | u32 pos; | |
17301 | u32 addr; | |
17302 | u32 surface; | |
17303 | u32 tile_offset; | |
52331309 | 17304 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
17305 | |
17306 | struct intel_transcoder_error_state { | |
ddf9c536 | 17307 | bool power_domain_on; |
63b66e5b CW |
17308 | enum transcoder cpu_transcoder; |
17309 | ||
17310 | u32 conf; | |
17311 | ||
17312 | u32 htotal; | |
17313 | u32 hblank; | |
17314 | u32 hsync; | |
17315 | u32 vtotal; | |
17316 | u32 vblank; | |
17317 | u32 vsync; | |
17318 | } transcoder[4]; | |
c4a1d9e4 CW |
17319 | }; |
17320 | ||
17321 | struct intel_display_error_state * | |
c033666a | 17322 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 17323 | { |
c4a1d9e4 | 17324 | struct intel_display_error_state *error; |
63b66e5b CW |
17325 | int transcoders[] = { |
17326 | TRANSCODER_A, | |
17327 | TRANSCODER_B, | |
17328 | TRANSCODER_C, | |
17329 | TRANSCODER_EDP, | |
17330 | }; | |
c4a1d9e4 CW |
17331 | int i; |
17332 | ||
c033666a | 17333 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
17334 | return NULL; |
17335 | ||
9d1cb914 | 17336 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
17337 | if (error == NULL) |
17338 | return NULL; | |
17339 | ||
c033666a | 17340 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
17341 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
17342 | ||
055e393f | 17343 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 17344 | error->pipe[i].power_domain_on = |
f458ebbc DV |
17345 | __intel_display_power_is_enabled(dev_priv, |
17346 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 17347 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
17348 | continue; |
17349 | ||
5efb3e28 VS |
17350 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
17351 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
17352 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
17353 | |
17354 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
17355 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 17356 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 17357 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
17358 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
17359 | } | |
c033666a | 17360 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 17361 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 17362 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
17363 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
17364 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
17365 | } | |
17366 | ||
c4a1d9e4 | 17367 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 17368 | |
c033666a | 17369 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 17370 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
17371 | } |
17372 | ||
4d1de975 | 17373 | /* Note: this does not include DSI transcoders. */ |
c033666a | 17374 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 17375 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
17376 | error->num_transcoders++; /* Account for eDP. */ |
17377 | ||
17378 | for (i = 0; i < error->num_transcoders; i++) { | |
17379 | enum transcoder cpu_transcoder = transcoders[i]; | |
17380 | ||
ddf9c536 | 17381 | error->transcoder[i].power_domain_on = |
f458ebbc | 17382 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 17383 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 17384 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
17385 | continue; |
17386 | ||
63b66e5b CW |
17387 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
17388 | ||
17389 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
17390 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
17391 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
17392 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
17393 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
17394 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
17395 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
17396 | } |
17397 | ||
17398 | return error; | |
17399 | } | |
17400 | ||
edc3d884 MK |
17401 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
17402 | ||
c4a1d9e4 | 17403 | void |
edc3d884 | 17404 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
5f56d5f9 | 17405 | struct drm_i915_private *dev_priv, |
c4a1d9e4 CW |
17406 | struct intel_display_error_state *error) |
17407 | { | |
17408 | int i; | |
17409 | ||
63b66e5b CW |
17410 | if (!error) |
17411 | return; | |
17412 | ||
b7f05d4a | 17413 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 17414 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 17415 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 17416 | error->power_well_driver); |
055e393f | 17417 | for_each_pipe(dev_priv, i) { |
edc3d884 | 17418 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 17419 | err_printf(m, " Power: %s\n", |
87ad3212 | 17420 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 17421 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 17422 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
17423 | |
17424 | err_printf(m, "Plane [%d]:\n", i); | |
17425 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
17426 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 17427 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
17428 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
17429 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 17430 | } |
772c2a51 | 17431 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 17432 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 17433 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
17434 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
17435 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
17436 | } |
17437 | ||
edc3d884 MK |
17438 | err_printf(m, "Cursor [%d]:\n", i); |
17439 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
17440 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
17441 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 17442 | } |
63b66e5b CW |
17443 | |
17444 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 17445 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 17446 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 17447 | err_printf(m, " Power: %s\n", |
87ad3212 | 17448 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
17449 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
17450 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
17451 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
17452 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
17453 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
17454 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
17455 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
17456 | } | |
c4a1d9e4 | 17457 | } |
98a2f411 CW |
17458 | |
17459 | #endif |