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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
57822dc6 | 40 | #include "i915_gem_clflush.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
5a21b665 DV |
52 | static bool is_mmio_work(struct intel_flip_work *work) |
53 | { | |
54 | return work->mmio_work.func; | |
55 | } | |
56 | ||
465c120c | 57 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 58 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
59 | DRM_FORMAT_C8, |
60 | DRM_FORMAT_RGB565, | |
465c120c | 61 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 62 | DRM_FORMAT_XRGB8888, |
465c120c MR |
63 | }; |
64 | ||
65 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 66 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
70 | DRM_FORMAT_XBGR8888, | |
71 | DRM_FORMAT_XRGB2101010, | |
72 | DRM_FORMAT_XBGR2101010, | |
73 | }; | |
74 | ||
75 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
76 | DRM_FORMAT_C8, |
77 | DRM_FORMAT_RGB565, | |
78 | DRM_FORMAT_XRGB8888, | |
465c120c | 79 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 80 | DRM_FORMAT_ARGB8888, |
465c120c MR |
81 | DRM_FORMAT_ABGR8888, |
82 | DRM_FORMAT_XRGB2101010, | |
465c120c | 83 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
84 | DRM_FORMAT_YUYV, |
85 | DRM_FORMAT_YVYU, | |
86 | DRM_FORMAT_UYVY, | |
87 | DRM_FORMAT_VYUY, | |
465c120c MR |
88 | }; |
89 | ||
3d7d6510 MR |
90 | /* Cursor formats */ |
91 | static const uint32_t intel_cursor_formats[] = { | |
92 | DRM_FORMAT_ARGB8888, | |
93 | }; | |
94 | ||
f1f644dc | 95 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 96 | struct intel_crtc_state *pipe_config); |
18442d08 | 97 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 98 | struct intel_crtc_state *pipe_config); |
f1f644dc | 99 | |
24dbf51a CW |
100 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
101 | struct drm_i915_gem_object *obj, | |
102 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
1c74eeaf NM |
118 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
119 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
120 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
121 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
122 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 123 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 124 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 125 | |
d4906093 | 126 | struct intel_limit { |
4c5def93 ACO |
127 | struct { |
128 | int min, max; | |
129 | } dot, vco, n, m, m1, m2, p, p1; | |
130 | ||
131 | struct { | |
132 | int dot_limit; | |
133 | int p2_slow, p2_fast; | |
134 | } p2; | |
d4906093 | 135 | }; |
79e53945 | 136 | |
bfa7df01 | 137 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 138 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
139 | { |
140 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
141 | ||
142 | /* Obtain SKU information */ | |
143 | mutex_lock(&dev_priv->sb_lock); | |
144 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
145 | CCK_FUSE_HPLL_FREQ_MASK; | |
146 | mutex_unlock(&dev_priv->sb_lock); | |
147 | ||
148 | return vco_freq[hpll_freq] * 1000; | |
149 | } | |
150 | ||
c30fec65 VS |
151 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
152 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
153 | { |
154 | u32 val; | |
155 | int divider; | |
156 | ||
bfa7df01 VS |
157 | mutex_lock(&dev_priv->sb_lock); |
158 | val = vlv_cck_read(dev_priv, reg); | |
159 | mutex_unlock(&dev_priv->sb_lock); | |
160 | ||
161 | divider = val & CCK_FREQUENCY_VALUES; | |
162 | ||
163 | WARN((val & CCK_FREQUENCY_STATUS) != | |
164 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
165 | "%s change in progress\n", name); | |
166 | ||
c30fec65 VS |
167 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
168 | } | |
169 | ||
7ff89ca2 VS |
170 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
171 | const char *name, u32 reg) | |
c30fec65 VS |
172 | { |
173 | if (dev_priv->hpll_freq == 0) | |
49cd97a3 | 174 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 VS |
175 | |
176 | return vlv_get_cck_clock(dev_priv, name, reg, | |
177 | dev_priv->hpll_freq); | |
bfa7df01 VS |
178 | } |
179 | ||
bfa7df01 VS |
180 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
181 | { | |
666a4537 | 182 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
183 | return; |
184 | ||
185 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
186 | CCK_CZ_CLOCK_CONTROL); | |
187 | ||
188 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
189 | } | |
190 | ||
021357ac | 191 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
192 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
193 | const struct intel_crtc_state *pipe_config) | |
021357ac | 194 | { |
21a727b3 VS |
195 | if (HAS_DDI(dev_priv)) |
196 | return pipe_config->port_clock; /* SPLL */ | |
197 | else if (IS_GEN5(dev_priv)) | |
198 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 199 | else |
21a727b3 | 200 | return 270000; |
021357ac CW |
201 | } |
202 | ||
1b6f4958 | 203 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 204 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 205 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 206 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
207 | .m = { .min = 96, .max = 140 }, |
208 | .m1 = { .min = 18, .max = 26 }, | |
209 | .m2 = { .min = 6, .max = 16 }, | |
210 | .p = { .min = 4, .max = 128 }, | |
211 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
212 | .p2 = { .dot_limit = 165000, |
213 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
214 | }; |
215 | ||
1b6f4958 | 216 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 217 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 218 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 219 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
220 | .m = { .min = 96, .max = 140 }, |
221 | .m1 = { .min = 18, .max = 26 }, | |
222 | .m2 = { .min = 6, .max = 16 }, | |
223 | .p = { .min = 4, .max = 128 }, | |
224 | .p1 = { .min = 2, .max = 33 }, | |
225 | .p2 = { .dot_limit = 165000, | |
226 | .p2_slow = 4, .p2_fast = 4 }, | |
227 | }; | |
228 | ||
1b6f4958 | 229 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 230 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 231 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 232 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
233 | .m = { .min = 96, .max = 140 }, |
234 | .m1 = { .min = 18, .max = 26 }, | |
235 | .m2 = { .min = 6, .max = 16 }, | |
236 | .p = { .min = 4, .max = 128 }, | |
237 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
238 | .p2 = { .dot_limit = 165000, |
239 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 240 | }; |
273e27ca | 241 | |
1b6f4958 | 242 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
243 | .dot = { .min = 20000, .max = 400000 }, |
244 | .vco = { .min = 1400000, .max = 2800000 }, | |
245 | .n = { .min = 1, .max = 6 }, | |
246 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
247 | .m1 = { .min = 8, .max = 18 }, |
248 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
249 | .p = { .min = 5, .max = 80 }, |
250 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
251 | .p2 = { .dot_limit = 200000, |
252 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
253 | }; |
254 | ||
1b6f4958 | 255 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
256 | .dot = { .min = 20000, .max = 400000 }, |
257 | .vco = { .min = 1400000, .max = 2800000 }, | |
258 | .n = { .min = 1, .max = 6 }, | |
259 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
260 | .m1 = { .min = 8, .max = 18 }, |
261 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
262 | .p = { .min = 7, .max = 98 }, |
263 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
264 | .p2 = { .dot_limit = 112000, |
265 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
266 | }; |
267 | ||
273e27ca | 268 | |
1b6f4958 | 269 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
270 | .dot = { .min = 25000, .max = 270000 }, |
271 | .vco = { .min = 1750000, .max = 3500000}, | |
272 | .n = { .min = 1, .max = 4 }, | |
273 | .m = { .min = 104, .max = 138 }, | |
274 | .m1 = { .min = 17, .max = 23 }, | |
275 | .m2 = { .min = 5, .max = 11 }, | |
276 | .p = { .min = 10, .max = 30 }, | |
277 | .p1 = { .min = 1, .max = 3}, | |
278 | .p2 = { .dot_limit = 270000, | |
279 | .p2_slow = 10, | |
280 | .p2_fast = 10 | |
044c7c41 | 281 | }, |
e4b36699 KP |
282 | }; |
283 | ||
1b6f4958 | 284 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
285 | .dot = { .min = 22000, .max = 400000 }, |
286 | .vco = { .min = 1750000, .max = 3500000}, | |
287 | .n = { .min = 1, .max = 4 }, | |
288 | .m = { .min = 104, .max = 138 }, | |
289 | .m1 = { .min = 16, .max = 23 }, | |
290 | .m2 = { .min = 5, .max = 11 }, | |
291 | .p = { .min = 5, .max = 80 }, | |
292 | .p1 = { .min = 1, .max = 8}, | |
293 | .p2 = { .dot_limit = 165000, | |
294 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
295 | }; |
296 | ||
1b6f4958 | 297 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
298 | .dot = { .min = 20000, .max = 115000 }, |
299 | .vco = { .min = 1750000, .max = 3500000 }, | |
300 | .n = { .min = 1, .max = 3 }, | |
301 | .m = { .min = 104, .max = 138 }, | |
302 | .m1 = { .min = 17, .max = 23 }, | |
303 | .m2 = { .min = 5, .max = 11 }, | |
304 | .p = { .min = 28, .max = 112 }, | |
305 | .p1 = { .min = 2, .max = 8 }, | |
306 | .p2 = { .dot_limit = 0, | |
307 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 308 | }, |
e4b36699 KP |
309 | }; |
310 | ||
1b6f4958 | 311 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
312 | .dot = { .min = 80000, .max = 224000 }, |
313 | .vco = { .min = 1750000, .max = 3500000 }, | |
314 | .n = { .min = 1, .max = 3 }, | |
315 | .m = { .min = 104, .max = 138 }, | |
316 | .m1 = { .min = 17, .max = 23 }, | |
317 | .m2 = { .min = 5, .max = 11 }, | |
318 | .p = { .min = 14, .max = 42 }, | |
319 | .p1 = { .min = 2, .max = 6 }, | |
320 | .p2 = { .dot_limit = 0, | |
321 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 322 | }, |
e4b36699 KP |
323 | }; |
324 | ||
1b6f4958 | 325 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
326 | .dot = { .min = 20000, .max = 400000}, |
327 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 328 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
329 | .n = { .min = 3, .max = 6 }, |
330 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 331 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
332 | .m1 = { .min = 0, .max = 0 }, |
333 | .m2 = { .min = 0, .max = 254 }, | |
334 | .p = { .min = 5, .max = 80 }, | |
335 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
336 | .p2 = { .dot_limit = 200000, |
337 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
338 | }; |
339 | ||
1b6f4958 | 340 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
341 | .dot = { .min = 20000, .max = 400000 }, |
342 | .vco = { .min = 1700000, .max = 3500000 }, | |
343 | .n = { .min = 3, .max = 6 }, | |
344 | .m = { .min = 2, .max = 256 }, | |
345 | .m1 = { .min = 0, .max = 0 }, | |
346 | .m2 = { .min = 0, .max = 254 }, | |
347 | .p = { .min = 7, .max = 112 }, | |
348 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
349 | .p2 = { .dot_limit = 112000, |
350 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
351 | }; |
352 | ||
273e27ca EA |
353 | /* Ironlake / Sandybridge |
354 | * | |
355 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
356 | * the range value for them is (actual_value - 2). | |
357 | */ | |
1b6f4958 | 358 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
359 | .dot = { .min = 25000, .max = 350000 }, |
360 | .vco = { .min = 1760000, .max = 3510000 }, | |
361 | .n = { .min = 1, .max = 5 }, | |
362 | .m = { .min = 79, .max = 127 }, | |
363 | .m1 = { .min = 12, .max = 22 }, | |
364 | .m2 = { .min = 5, .max = 9 }, | |
365 | .p = { .min = 5, .max = 80 }, | |
366 | .p1 = { .min = 1, .max = 8 }, | |
367 | .p2 = { .dot_limit = 225000, | |
368 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
369 | }; |
370 | ||
1b6f4958 | 371 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
372 | .dot = { .min = 25000, .max = 350000 }, |
373 | .vco = { .min = 1760000, .max = 3510000 }, | |
374 | .n = { .min = 1, .max = 3 }, | |
375 | .m = { .min = 79, .max = 118 }, | |
376 | .m1 = { .min = 12, .max = 22 }, | |
377 | .m2 = { .min = 5, .max = 9 }, | |
378 | .p = { .min = 28, .max = 112 }, | |
379 | .p1 = { .min = 2, .max = 8 }, | |
380 | .p2 = { .dot_limit = 225000, | |
381 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
382 | }; |
383 | ||
1b6f4958 | 384 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
385 | .dot = { .min = 25000, .max = 350000 }, |
386 | .vco = { .min = 1760000, .max = 3510000 }, | |
387 | .n = { .min = 1, .max = 3 }, | |
388 | .m = { .min = 79, .max = 127 }, | |
389 | .m1 = { .min = 12, .max = 22 }, | |
390 | .m2 = { .min = 5, .max = 9 }, | |
391 | .p = { .min = 14, .max = 56 }, | |
392 | .p1 = { .min = 2, .max = 8 }, | |
393 | .p2 = { .dot_limit = 225000, | |
394 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
395 | }; |
396 | ||
273e27ca | 397 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 398 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
399 | .dot = { .min = 25000, .max = 350000 }, |
400 | .vco = { .min = 1760000, .max = 3510000 }, | |
401 | .n = { .min = 1, .max = 2 }, | |
402 | .m = { .min = 79, .max = 126 }, | |
403 | .m1 = { .min = 12, .max = 22 }, | |
404 | .m2 = { .min = 5, .max = 9 }, | |
405 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 406 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
407 | .p2 = { .dot_limit = 225000, |
408 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
409 | }; |
410 | ||
1b6f4958 | 411 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
412 | .dot = { .min = 25000, .max = 350000 }, |
413 | .vco = { .min = 1760000, .max = 3510000 }, | |
414 | .n = { .min = 1, .max = 3 }, | |
415 | .m = { .min = 79, .max = 126 }, | |
416 | .m1 = { .min = 12, .max = 22 }, | |
417 | .m2 = { .min = 5, .max = 9 }, | |
418 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 419 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
420 | .p2 = { .dot_limit = 225000, |
421 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
422 | }; |
423 | ||
1b6f4958 | 424 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
425 | /* |
426 | * These are the data rate limits (measured in fast clocks) | |
427 | * since those are the strictest limits we have. The fast | |
428 | * clock and actual rate limits are more relaxed, so checking | |
429 | * them would make no difference. | |
430 | */ | |
431 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 432 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 433 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
434 | .m1 = { .min = 2, .max = 3 }, |
435 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 436 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 437 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
438 | }; |
439 | ||
1b6f4958 | 440 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
441 | /* |
442 | * These are the data rate limits (measured in fast clocks) | |
443 | * since those are the strictest limits we have. The fast | |
444 | * clock and actual rate limits are more relaxed, so checking | |
445 | * them would make no difference. | |
446 | */ | |
447 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 448 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
449 | .n = { .min = 1, .max = 1 }, |
450 | .m1 = { .min = 2, .max = 2 }, | |
451 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
452 | .p1 = { .min = 2, .max = 4 }, | |
453 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
454 | }; | |
455 | ||
1b6f4958 | 456 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
457 | /* FIXME: find real dot limits */ |
458 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 459 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
460 | .n = { .min = 1, .max = 1 }, |
461 | .m1 = { .min = 2, .max = 2 }, | |
462 | /* FIXME: find real m2 limits */ | |
463 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
464 | .p1 = { .min = 2, .max = 4 }, | |
465 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
466 | }; | |
467 | ||
cdba954e ACO |
468 | static bool |
469 | needs_modeset(struct drm_crtc_state *state) | |
470 | { | |
fc596660 | 471 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
472 | } |
473 | ||
dccbea3b ID |
474 | /* |
475 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
476 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
477 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
478 | * The helpers' return value is the rate of the clock that is fed to the | |
479 | * display engine's pipe which can be the above fast dot clock rate or a | |
480 | * divided-down version of it. | |
481 | */ | |
f2b115e6 | 482 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 483 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 484 | { |
2177832f SL |
485 | clock->m = clock->m2 + 2; |
486 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 487 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 488 | return 0; |
fb03ac01 VS |
489 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
490 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
491 | |
492 | return clock->dot; | |
2177832f SL |
493 | } |
494 | ||
7429e9d4 DV |
495 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
496 | { | |
497 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
498 | } | |
499 | ||
9e2c8475 | 500 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 501 | { |
7429e9d4 | 502 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 503 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 504 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 505 | return 0; |
fb03ac01 VS |
506 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
507 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
508 | |
509 | return clock->dot; | |
79e53945 JB |
510 | } |
511 | ||
9e2c8475 | 512 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
513 | { |
514 | clock->m = clock->m1 * clock->m2; | |
515 | clock->p = clock->p1 * clock->p2; | |
516 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 517 | return 0; |
589eca67 ID |
518 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
519 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
520 | |
521 | return clock->dot / 5; | |
589eca67 ID |
522 | } |
523 | ||
9e2c8475 | 524 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
525 | { |
526 | clock->m = clock->m1 * clock->m2; | |
527 | clock->p = clock->p1 * clock->p2; | |
528 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 529 | return 0; |
ef9348c8 CML |
530 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
531 | clock->n << 22); | |
532 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
533 | |
534 | return clock->dot / 5; | |
ef9348c8 CML |
535 | } |
536 | ||
7c04d1d9 | 537 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
538 | /** |
539 | * Returns whether the given set of divisors are valid for a given refclk with | |
540 | * the given connectors. | |
541 | */ | |
542 | ||
e2d214ae | 543 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 544 | const struct intel_limit *limit, |
9e2c8475 | 545 | const struct dpll *clock) |
79e53945 | 546 | { |
f01b7962 VS |
547 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
548 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 549 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 550 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 551 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 552 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 553 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 554 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 555 | |
e2d214ae | 556 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 557 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
558 | if (clock->m1 <= clock->m2) |
559 | INTELPllInvalid("m1 <= m2\n"); | |
560 | ||
e2d214ae | 561 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 562 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
563 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
564 | INTELPllInvalid("p out of range\n"); | |
565 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
566 | INTELPllInvalid("m out of range\n"); | |
567 | } | |
568 | ||
79e53945 | 569 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 570 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
571 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
572 | * connector, etc., rather than just a single range. | |
573 | */ | |
574 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 575 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
576 | |
577 | return true; | |
578 | } | |
579 | ||
3b1429d9 | 580 | static int |
1b6f4958 | 581 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
582 | const struct intel_crtc_state *crtc_state, |
583 | int target) | |
79e53945 | 584 | { |
3b1429d9 | 585 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 586 | |
2d84d2b3 | 587 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 588 | /* |
a210b028 DV |
589 | * For LVDS just rely on its current settings for dual-channel. |
590 | * We haven't figured out how to reliably set up different | |
591 | * single/dual channel state, if we even can. | |
79e53945 | 592 | */ |
1974cad0 | 593 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 594 | return limit->p2.p2_fast; |
79e53945 | 595 | else |
3b1429d9 | 596 | return limit->p2.p2_slow; |
79e53945 JB |
597 | } else { |
598 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 599 | return limit->p2.p2_slow; |
79e53945 | 600 | else |
3b1429d9 | 601 | return limit->p2.p2_fast; |
79e53945 | 602 | } |
3b1429d9 VS |
603 | } |
604 | ||
70e8aa21 ACO |
605 | /* |
606 | * Returns a set of divisors for the desired target clock with the given | |
607 | * refclk, or FALSE. The returned values represent the clock equation: | |
608 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
609 | * | |
610 | * Target and reference clocks are specified in kHz. | |
611 | * | |
612 | * If match_clock is provided, then best_clock P divider must match the P | |
613 | * divider from @match_clock used for LVDS downclocking. | |
614 | */ | |
3b1429d9 | 615 | static bool |
1b6f4958 | 616 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 617 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
618 | int target, int refclk, struct dpll *match_clock, |
619 | struct dpll *best_clock) | |
3b1429d9 VS |
620 | { |
621 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 622 | struct dpll clock; |
3b1429d9 | 623 | int err = target; |
79e53945 | 624 | |
0206e353 | 625 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 626 | |
3b1429d9 VS |
627 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
628 | ||
42158660 ZY |
629 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
630 | clock.m1++) { | |
631 | for (clock.m2 = limit->m2.min; | |
632 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 633 | if (clock.m2 >= clock.m1) |
42158660 ZY |
634 | break; |
635 | for (clock.n = limit->n.min; | |
636 | clock.n <= limit->n.max; clock.n++) { | |
637 | for (clock.p1 = limit->p1.min; | |
638 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
639 | int this_err; |
640 | ||
dccbea3b | 641 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
642 | if (!intel_PLL_is_valid(to_i915(dev), |
643 | limit, | |
ac58c3f0 DV |
644 | &clock)) |
645 | continue; | |
646 | if (match_clock && | |
647 | clock.p != match_clock->p) | |
648 | continue; | |
649 | ||
650 | this_err = abs(clock.dot - target); | |
651 | if (this_err < err) { | |
652 | *best_clock = clock; | |
653 | err = this_err; | |
654 | } | |
655 | } | |
656 | } | |
657 | } | |
658 | } | |
659 | ||
660 | return (err != target); | |
661 | } | |
662 | ||
70e8aa21 ACO |
663 | /* |
664 | * Returns a set of divisors for the desired target clock with the given | |
665 | * refclk, or FALSE. The returned values represent the clock equation: | |
666 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
667 | * | |
668 | * Target and reference clocks are specified in kHz. | |
669 | * | |
670 | * If match_clock is provided, then best_clock P divider must match the P | |
671 | * divider from @match_clock used for LVDS downclocking. | |
672 | */ | |
ac58c3f0 | 673 | static bool |
1b6f4958 | 674 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 675 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
676 | int target, int refclk, struct dpll *match_clock, |
677 | struct dpll *best_clock) | |
79e53945 | 678 | { |
3b1429d9 | 679 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 680 | struct dpll clock; |
79e53945 JB |
681 | int err = target; |
682 | ||
0206e353 | 683 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 684 | |
3b1429d9 VS |
685 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
686 | ||
42158660 ZY |
687 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
688 | clock.m1++) { | |
689 | for (clock.m2 = limit->m2.min; | |
690 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
691 | for (clock.n = limit->n.min; |
692 | clock.n <= limit->n.max; clock.n++) { | |
693 | for (clock.p1 = limit->p1.min; | |
694 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
695 | int this_err; |
696 | ||
dccbea3b | 697 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
698 | if (!intel_PLL_is_valid(to_i915(dev), |
699 | limit, | |
1b894b59 | 700 | &clock)) |
79e53945 | 701 | continue; |
cec2f356 SP |
702 | if (match_clock && |
703 | clock.p != match_clock->p) | |
704 | continue; | |
79e53945 JB |
705 | |
706 | this_err = abs(clock.dot - target); | |
707 | if (this_err < err) { | |
708 | *best_clock = clock; | |
709 | err = this_err; | |
710 | } | |
711 | } | |
712 | } | |
713 | } | |
714 | } | |
715 | ||
716 | return (err != target); | |
717 | } | |
718 | ||
997c030c ACO |
719 | /* |
720 | * Returns a set of divisors for the desired target clock with the given | |
721 | * refclk, or FALSE. The returned values represent the clock equation: | |
722 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
723 | * |
724 | * Target and reference clocks are specified in kHz. | |
725 | * | |
726 | * If match_clock is provided, then best_clock P divider must match the P | |
727 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 728 | */ |
d4906093 | 729 | static bool |
1b6f4958 | 730 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 731 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
732 | int target, int refclk, struct dpll *match_clock, |
733 | struct dpll *best_clock) | |
d4906093 | 734 | { |
3b1429d9 | 735 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 736 | struct dpll clock; |
d4906093 | 737 | int max_n; |
3b1429d9 | 738 | bool found = false; |
6ba770dc AJ |
739 | /* approximately equals target * 0.00585 */ |
740 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
741 | |
742 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
743 | |
744 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
745 | ||
d4906093 | 746 | max_n = limit->n.max; |
f77f13e2 | 747 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 748 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 749 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
750 | for (clock.m1 = limit->m1.max; |
751 | clock.m1 >= limit->m1.min; clock.m1--) { | |
752 | for (clock.m2 = limit->m2.max; | |
753 | clock.m2 >= limit->m2.min; clock.m2--) { | |
754 | for (clock.p1 = limit->p1.max; | |
755 | clock.p1 >= limit->p1.min; clock.p1--) { | |
756 | int this_err; | |
757 | ||
dccbea3b | 758 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
759 | if (!intel_PLL_is_valid(to_i915(dev), |
760 | limit, | |
1b894b59 | 761 | &clock)) |
d4906093 | 762 | continue; |
1b894b59 CW |
763 | |
764 | this_err = abs(clock.dot - target); | |
d4906093 ML |
765 | if (this_err < err_most) { |
766 | *best_clock = clock; | |
767 | err_most = this_err; | |
768 | max_n = clock.n; | |
769 | found = true; | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
774 | } | |
2c07245f ZW |
775 | return found; |
776 | } | |
777 | ||
d5dd62bd ID |
778 | /* |
779 | * Check if the calculated PLL configuration is more optimal compared to the | |
780 | * best configuration and error found so far. Return the calculated error. | |
781 | */ | |
782 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
783 | const struct dpll *calculated_clock, |
784 | const struct dpll *best_clock, | |
d5dd62bd ID |
785 | unsigned int best_error_ppm, |
786 | unsigned int *error_ppm) | |
787 | { | |
9ca3ba01 ID |
788 | /* |
789 | * For CHV ignore the error and consider only the P value. | |
790 | * Prefer a bigger P value based on HW requirements. | |
791 | */ | |
920a14b2 | 792 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
793 | *error_ppm = 0; |
794 | ||
795 | return calculated_clock->p > best_clock->p; | |
796 | } | |
797 | ||
24be4e46 ID |
798 | if (WARN_ON_ONCE(!target_freq)) |
799 | return false; | |
800 | ||
d5dd62bd ID |
801 | *error_ppm = div_u64(1000000ULL * |
802 | abs(target_freq - calculated_clock->dot), | |
803 | target_freq); | |
804 | /* | |
805 | * Prefer a better P value over a better (smaller) error if the error | |
806 | * is small. Ensure this preference for future configurations too by | |
807 | * setting the error to 0. | |
808 | */ | |
809 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
810 | *error_ppm = 0; | |
811 | ||
812 | return true; | |
813 | } | |
814 | ||
815 | return *error_ppm + 10 < best_error_ppm; | |
816 | } | |
817 | ||
65b3d6a9 ACO |
818 | /* |
819 | * Returns a set of divisors for the desired target clock with the given | |
820 | * refclk, or FALSE. The returned values represent the clock equation: | |
821 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
822 | */ | |
a0c4da24 | 823 | static bool |
1b6f4958 | 824 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 825 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
826 | int target, int refclk, struct dpll *match_clock, |
827 | struct dpll *best_clock) | |
a0c4da24 | 828 | { |
a93e255f | 829 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 830 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 831 | struct dpll clock; |
69e4f900 | 832 | unsigned int bestppm = 1000000; |
27e639bf VS |
833 | /* min update 19.2 MHz */ |
834 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 835 | bool found = false; |
a0c4da24 | 836 | |
6b4bf1c4 VS |
837 | target *= 5; /* fast clock */ |
838 | ||
839 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
840 | |
841 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 842 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 843 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 844 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 845 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 846 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 847 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 848 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 849 | unsigned int ppm; |
69e4f900 | 850 | |
6b4bf1c4 VS |
851 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
852 | refclk * clock.m1); | |
853 | ||
dccbea3b | 854 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 855 | |
e2d214ae TU |
856 | if (!intel_PLL_is_valid(to_i915(dev), |
857 | limit, | |
f01b7962 | 858 | &clock)) |
43b0ac53 VS |
859 | continue; |
860 | ||
d5dd62bd ID |
861 | if (!vlv_PLL_is_optimal(dev, target, |
862 | &clock, | |
863 | best_clock, | |
864 | bestppm, &ppm)) | |
865 | continue; | |
6b4bf1c4 | 866 | |
d5dd62bd ID |
867 | *best_clock = clock; |
868 | bestppm = ppm; | |
869 | found = true; | |
a0c4da24 JB |
870 | } |
871 | } | |
872 | } | |
873 | } | |
a0c4da24 | 874 | |
49e497ef | 875 | return found; |
a0c4da24 | 876 | } |
a4fc5ed6 | 877 | |
65b3d6a9 ACO |
878 | /* |
879 | * Returns a set of divisors for the desired target clock with the given | |
880 | * refclk, or FALSE. The returned values represent the clock equation: | |
881 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
882 | */ | |
ef9348c8 | 883 | static bool |
1b6f4958 | 884 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 885 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
886 | int target, int refclk, struct dpll *match_clock, |
887 | struct dpll *best_clock) | |
ef9348c8 | 888 | { |
a93e255f | 889 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 890 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 891 | unsigned int best_error_ppm; |
9e2c8475 | 892 | struct dpll clock; |
ef9348c8 CML |
893 | uint64_t m2; |
894 | int found = false; | |
895 | ||
896 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 897 | best_error_ppm = 1000000; |
ef9348c8 CML |
898 | |
899 | /* | |
900 | * Based on hardware doc, the n always set to 1, and m1 always | |
901 | * set to 2. If requires to support 200Mhz refclk, we need to | |
902 | * revisit this because n may not 1 anymore. | |
903 | */ | |
904 | clock.n = 1, clock.m1 = 2; | |
905 | target *= 5; /* fast clock */ | |
906 | ||
907 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
908 | for (clock.p2 = limit->p2.p2_fast; | |
909 | clock.p2 >= limit->p2.p2_slow; | |
910 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 911 | unsigned int error_ppm; |
ef9348c8 CML |
912 | |
913 | clock.p = clock.p1 * clock.p2; | |
914 | ||
915 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
916 | clock.n) << 22, refclk * clock.m1); | |
917 | ||
918 | if (m2 > INT_MAX/clock.m1) | |
919 | continue; | |
920 | ||
921 | clock.m2 = m2; | |
922 | ||
dccbea3b | 923 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 924 | |
e2d214ae | 925 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
926 | continue; |
927 | ||
9ca3ba01 ID |
928 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
929 | best_error_ppm, &error_ppm)) | |
930 | continue; | |
931 | ||
932 | *best_clock = clock; | |
933 | best_error_ppm = error_ppm; | |
934 | found = true; | |
ef9348c8 CML |
935 | } |
936 | } | |
937 | ||
938 | return found; | |
939 | } | |
940 | ||
5ab7b0b7 | 941 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 942 | struct dpll *best_clock) |
5ab7b0b7 | 943 | { |
65b3d6a9 | 944 | int refclk = 100000; |
1b6f4958 | 945 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 946 | |
65b3d6a9 | 947 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
948 | target_clock, refclk, NULL, best_clock); |
949 | } | |
950 | ||
525b9311 | 951 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 952 | { |
20ddf665 VS |
953 | /* Be paranoid as we can arrive here with only partial |
954 | * state retrieved from the hardware during setup. | |
955 | * | |
241bfc38 | 956 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
957 | * as Haswell has gained clock readout/fastboot support. |
958 | * | |
66e514c1 | 959 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 960 | * properly reconstruct framebuffers. |
c3d1f436 MR |
961 | * |
962 | * FIXME: The intel_crtc->active here should be switched to | |
963 | * crtc->state->active once we have proper CRTC states wired up | |
964 | * for atomic. | |
20ddf665 | 965 | */ |
525b9311 VS |
966 | return crtc->active && crtc->base.primary->state->fb && |
967 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
968 | } |
969 | ||
a5c961d1 PZ |
970 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
971 | enum pipe pipe) | |
972 | { | |
98187836 | 973 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 974 | |
e2af48c6 | 975 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
976 | } |
977 | ||
6315b5d3 | 978 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 979 | { |
f0f59a00 | 980 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
981 | u32 line1, line2; |
982 | u32 line_mask; | |
983 | ||
5db94019 | 984 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
985 | line_mask = DSL_LINEMASK_GEN2; |
986 | else | |
987 | line_mask = DSL_LINEMASK_GEN3; | |
988 | ||
989 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 990 | msleep(5); |
fbf49ea2 VS |
991 | line2 = I915_READ(reg) & line_mask; |
992 | ||
993 | return line1 == line2; | |
994 | } | |
995 | ||
ab7ad7f6 KP |
996 | /* |
997 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 998 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
999 | * |
1000 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1001 | * spinning on the vblank interrupt status bit, since we won't actually | |
1002 | * see an interrupt when the pipe is disabled. | |
1003 | * | |
ab7ad7f6 KP |
1004 | * On Gen4 and above: |
1005 | * wait for the pipe register state bit to turn off | |
1006 | * | |
1007 | * Otherwise: | |
1008 | * wait for the display line value to settle (it usually | |
1009 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1010 | * |
9d0498a2 | 1011 | */ |
575f7ab7 | 1012 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1013 | { |
6315b5d3 | 1014 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1015 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1016 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1017 | |
6315b5d3 | 1018 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1019 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1020 | |
1021 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1022 | if (intel_wait_for_register(dev_priv, |
1023 | reg, I965_PIPECONF_ACTIVE, 0, | |
1024 | 100)) | |
284637d9 | 1025 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1026 | } else { |
ab7ad7f6 | 1027 | /* Wait for the display line to settle */ |
6315b5d3 | 1028 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1029 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1030 | } |
79e53945 JB |
1031 | } |
1032 | ||
b24e7179 | 1033 | /* Only for pre-ILK configs */ |
55607e8a DV |
1034 | void assert_pll(struct drm_i915_private *dev_priv, |
1035 | enum pipe pipe, bool state) | |
b24e7179 | 1036 | { |
b24e7179 JB |
1037 | u32 val; |
1038 | bool cur_state; | |
1039 | ||
649636ef | 1040 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1041 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1042 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1043 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1044 | onoff(state), onoff(cur_state)); |
b24e7179 | 1045 | } |
b24e7179 | 1046 | |
23538ef1 | 1047 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1048 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1049 | { |
1050 | u32 val; | |
1051 | bool cur_state; | |
1052 | ||
a580516d | 1053 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1054 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1055 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1056 | |
1057 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1058 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1059 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1060 | onoff(state), onoff(cur_state)); |
23538ef1 | 1061 | } |
23538ef1 | 1062 | |
040484af JB |
1063 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1064 | enum pipe pipe, bool state) | |
1065 | { | |
040484af | 1066 | bool cur_state; |
ad80a810 PZ |
1067 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1068 | pipe); | |
040484af | 1069 | |
2d1fe073 | 1070 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1071 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1072 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1073 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1074 | } else { |
649636ef | 1075 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1076 | cur_state = !!(val & FDI_TX_ENABLE); |
1077 | } | |
e2c719b7 | 1078 | I915_STATE_WARN(cur_state != state, |
040484af | 1079 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1080 | onoff(state), onoff(cur_state)); |
040484af JB |
1081 | } |
1082 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1083 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1084 | ||
1085 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1086 | enum pipe pipe, bool state) | |
1087 | { | |
040484af JB |
1088 | u32 val; |
1089 | bool cur_state; | |
1090 | ||
649636ef | 1091 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1092 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1093 | I915_STATE_WARN(cur_state != state, |
040484af | 1094 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1095 | onoff(state), onoff(cur_state)); |
040484af JB |
1096 | } |
1097 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1098 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1099 | ||
1100 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1101 | enum pipe pipe) | |
1102 | { | |
040484af JB |
1103 | u32 val; |
1104 | ||
1105 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1106 | if (IS_GEN5(dev_priv)) |
040484af JB |
1107 | return; |
1108 | ||
bf507ef7 | 1109 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1110 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1111 | return; |
1112 | ||
649636ef | 1113 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1114 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1115 | } |
1116 | ||
55607e8a DV |
1117 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1118 | enum pipe pipe, bool state) | |
040484af | 1119 | { |
040484af | 1120 | u32 val; |
55607e8a | 1121 | bool cur_state; |
040484af | 1122 | |
649636ef | 1123 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1124 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1125 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1126 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1127 | onoff(state), onoff(cur_state)); |
040484af JB |
1128 | } |
1129 | ||
4f8036a2 | 1130 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1131 | { |
f0f59a00 | 1132 | i915_reg_t pp_reg; |
ea0760cf JB |
1133 | u32 val; |
1134 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1135 | bool locked = true; |
ea0760cf | 1136 | |
4f8036a2 | 1137 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1138 | return; |
1139 | ||
4f8036a2 | 1140 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1141 | u32 port_sel; |
1142 | ||
44cb734c ID |
1143 | pp_reg = PP_CONTROL(0); |
1144 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1145 | |
1146 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1147 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1148 | panel_pipe = PIPE_B; | |
1149 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1150 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1151 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1152 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1153 | panel_pipe = pipe; |
ea0760cf | 1154 | } else { |
44cb734c | 1155 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1156 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1157 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1158 | } |
1159 | ||
1160 | val = I915_READ(pp_reg); | |
1161 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1162 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1163 | locked = false; |
1164 | ||
e2c719b7 | 1165 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1166 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1167 | pipe_name(pipe)); |
ea0760cf JB |
1168 | } |
1169 | ||
93ce0ba6 JN |
1170 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1171 | enum pipe pipe, bool state) | |
1172 | { | |
93ce0ba6 JN |
1173 | bool cur_state; |
1174 | ||
2a307c2e | 1175 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1176 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1177 | else |
5efb3e28 | 1178 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1179 | |
e2c719b7 | 1180 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1181 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1182 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1183 | } |
1184 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1185 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1186 | ||
b840d907 JB |
1187 | void assert_pipe(struct drm_i915_private *dev_priv, |
1188 | enum pipe pipe, bool state) | |
b24e7179 | 1189 | { |
63d7bbe9 | 1190 | bool cur_state; |
702e7a56 PZ |
1191 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1192 | pipe); | |
4feed0eb | 1193 | enum intel_display_power_domain power_domain; |
b24e7179 | 1194 | |
b6b5d049 VS |
1195 | /* if we need the pipe quirk it must be always on */ |
1196 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1197 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1198 | state = true; |
1199 | ||
4feed0eb ID |
1200 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1201 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1202 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1203 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1204 | |
1205 | intel_display_power_put(dev_priv, power_domain); | |
1206 | } else { | |
1207 | cur_state = false; | |
69310161 PZ |
1208 | } |
1209 | ||
e2c719b7 | 1210 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1211 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1212 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1213 | } |
1214 | ||
931872fc CW |
1215 | static void assert_plane(struct drm_i915_private *dev_priv, |
1216 | enum plane plane, bool state) | |
b24e7179 | 1217 | { |
b24e7179 | 1218 | u32 val; |
931872fc | 1219 | bool cur_state; |
b24e7179 | 1220 | |
649636ef | 1221 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1222 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1223 | I915_STATE_WARN(cur_state != state, |
931872fc | 1224 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1225 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1226 | } |
1227 | ||
931872fc CW |
1228 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1229 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1230 | ||
b24e7179 JB |
1231 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1232 | enum pipe pipe) | |
1233 | { | |
649636ef | 1234 | int i; |
b24e7179 | 1235 | |
653e1026 | 1236 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1237 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1238 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1239 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1240 | "plane %c assertion failure, should be disabled but not\n", |
1241 | plane_name(pipe)); | |
19ec1358 | 1242 | return; |
28c05794 | 1243 | } |
19ec1358 | 1244 | |
b24e7179 | 1245 | /* Need to check both planes against the pipe */ |
055e393f | 1246 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1247 | u32 val = I915_READ(DSPCNTR(i)); |
1248 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1249 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1250 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1251 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1252 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1253 | } |
1254 | } | |
1255 | ||
19332d7a JB |
1256 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1257 | enum pipe pipe) | |
1258 | { | |
649636ef | 1259 | int sprite; |
19332d7a | 1260 | |
6315b5d3 | 1261 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1262 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1263 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1264 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1265 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1266 | sprite, pipe_name(pipe)); | |
1267 | } | |
920a14b2 | 1268 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1269 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1270 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1271 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1272 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1273 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1274 | } |
6315b5d3 | 1275 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1276 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1277 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1278 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1279 | plane_name(pipe), pipe_name(pipe)); |
6315b5d3 | 1280 | } else if (INTEL_GEN(dev_priv) >= 5) { |
649636ef | 1281 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1282 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1283 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1284 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1285 | } |
1286 | } | |
1287 | ||
08c71e5e VS |
1288 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1289 | { | |
e2c719b7 | 1290 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1291 | drm_crtc_vblank_put(crtc); |
1292 | } | |
1293 | ||
7abd4b35 ACO |
1294 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe) | |
92f2584a | 1296 | { |
92f2584a JB |
1297 | u32 val; |
1298 | bool enabled; | |
1299 | ||
649636ef | 1300 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1301 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1302 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1303 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1304 | pipe_name(pipe)); | |
92f2584a JB |
1305 | } |
1306 | ||
4e634389 KP |
1307 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1308 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1309 | { |
1310 | if ((val & DP_PORT_EN) == 0) | |
1311 | return false; | |
1312 | ||
2d1fe073 | 1313 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1314 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1315 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1316 | return false; | |
2d1fe073 | 1317 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1318 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1319 | return false; | |
f0575e92 KP |
1320 | } else { |
1321 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1322 | return false; | |
1323 | } | |
1324 | return true; | |
1325 | } | |
1326 | ||
1519b995 KP |
1327 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1328 | enum pipe pipe, u32 val) | |
1329 | { | |
dc0fa718 | 1330 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1331 | return false; |
1332 | ||
2d1fe073 | 1333 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1334 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1335 | return false; |
2d1fe073 | 1336 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1337 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1338 | return false; | |
1519b995 | 1339 | } else { |
dc0fa718 | 1340 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1341 | return false; |
1342 | } | |
1343 | return true; | |
1344 | } | |
1345 | ||
1346 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1347 | enum pipe pipe, u32 val) | |
1348 | { | |
1349 | if ((val & LVDS_PORT_EN) == 0) | |
1350 | return false; | |
1351 | ||
2d1fe073 | 1352 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1353 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1354 | return false; | |
1355 | } else { | |
1356 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1357 | return false; | |
1358 | } | |
1359 | return true; | |
1360 | } | |
1361 | ||
1362 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1363 | enum pipe pipe, u32 val) | |
1364 | { | |
1365 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1366 | return false; | |
2d1fe073 | 1367 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1368 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1369 | return false; | |
1370 | } else { | |
1371 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1372 | return false; | |
1373 | } | |
1374 | return true; | |
1375 | } | |
1376 | ||
291906f1 | 1377 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1378 | enum pipe pipe, i915_reg_t reg, |
1379 | u32 port_sel) | |
291906f1 | 1380 | { |
47a05eca | 1381 | u32 val = I915_READ(reg); |
e2c719b7 | 1382 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1383 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1384 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1385 | |
2d1fe073 | 1386 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1387 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1388 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1389 | } |
1390 | ||
1391 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1392 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1393 | { |
47a05eca | 1394 | u32 val = I915_READ(reg); |
e2c719b7 | 1395 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1396 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1397 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1398 | |
2d1fe073 | 1399 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1400 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1401 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1402 | } |
1403 | ||
1404 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1405 | enum pipe pipe) | |
1406 | { | |
291906f1 | 1407 | u32 val; |
291906f1 | 1408 | |
f0575e92 KP |
1409 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1410 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1411 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1412 | |
649636ef | 1413 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1414 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1415 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1416 | pipe_name(pipe)); |
291906f1 | 1417 | |
649636ef | 1418 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1419 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1420 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1421 | pipe_name(pipe)); |
291906f1 | 1422 | |
e2debe91 PZ |
1423 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1424 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1425 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1426 | } |
1427 | ||
cd2d34d9 VS |
1428 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1429 | const struct intel_crtc_state *pipe_config) | |
1430 | { | |
1431 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1432 | enum pipe pipe = crtc->pipe; | |
1433 | ||
1434 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1435 | POSTING_READ(DPLL(pipe)); | |
1436 | udelay(150); | |
1437 | ||
2c30b43b CW |
1438 | if (intel_wait_for_register(dev_priv, |
1439 | DPLL(pipe), | |
1440 | DPLL_LOCK_VLV, | |
1441 | DPLL_LOCK_VLV, | |
1442 | 1)) | |
cd2d34d9 VS |
1443 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1444 | } | |
1445 | ||
d288f65f | 1446 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1447 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1448 | { |
cd2d34d9 | 1449 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1450 | enum pipe pipe = crtc->pipe; |
87442f73 | 1451 | |
8bd3f301 | 1452 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1453 | |
87442f73 | 1454 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1455 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1456 | |
cd2d34d9 VS |
1457 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1458 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1459 | |
8bd3f301 VS |
1460 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1461 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1462 | } |
1463 | ||
cd2d34d9 VS |
1464 | |
1465 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1466 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1467 | { |
cd2d34d9 | 1468 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1469 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1470 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1471 | u32 tmp; |
1472 | ||
a580516d | 1473 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1474 | |
1475 | /* Enable back the 10bit clock to display controller */ | |
1476 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1477 | tmp |= DPIO_DCLKP_EN; | |
1478 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1479 | ||
54433e91 VS |
1480 | mutex_unlock(&dev_priv->sb_lock); |
1481 | ||
9d556c99 CML |
1482 | /* |
1483 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1484 | */ | |
1485 | udelay(1); | |
1486 | ||
1487 | /* Enable PLL */ | |
d288f65f | 1488 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1489 | |
1490 | /* Check PLL is locked */ | |
6b18826a CW |
1491 | if (intel_wait_for_register(dev_priv, |
1492 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1493 | 1)) | |
9d556c99 | 1494 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1495 | } |
1496 | ||
1497 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1498 | const struct intel_crtc_state *pipe_config) | |
1499 | { | |
1500 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1501 | enum pipe pipe = crtc->pipe; | |
1502 | ||
1503 | assert_pipe_disabled(dev_priv, pipe); | |
1504 | ||
1505 | /* PLL is protected by panel, make sure we can write it */ | |
1506 | assert_panel_unlocked(dev_priv, pipe); | |
1507 | ||
1508 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1509 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1510 | |
c231775c VS |
1511 | if (pipe != PIPE_A) { |
1512 | /* | |
1513 | * WaPixelRepeatModeFixForC0:chv | |
1514 | * | |
1515 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1516 | * the value from DPLLBMD to either pipe B or C. | |
1517 | */ | |
1518 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1519 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1520 | I915_WRITE(CBR4_VLV, 0); | |
1521 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1522 | ||
1523 | /* | |
1524 | * DPLLB VGA mode also seems to cause problems. | |
1525 | * We should always have it disabled. | |
1526 | */ | |
1527 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1528 | } else { | |
1529 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1530 | POSTING_READ(DPLL_MD(pipe)); | |
1531 | } | |
9d556c99 CML |
1532 | } |
1533 | ||
6315b5d3 | 1534 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1535 | { |
1536 | struct intel_crtc *crtc; | |
1537 | int count = 0; | |
1538 | ||
6315b5d3 | 1539 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1540 | count += crtc->base.state->active && |
2d84d2b3 VS |
1541 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1542 | } | |
1c4e0274 VS |
1543 | |
1544 | return count; | |
1545 | } | |
1546 | ||
66e3d5c0 | 1547 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1548 | { |
6315b5d3 | 1549 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1550 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1551 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1552 | |
66e3d5c0 | 1553 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1554 | |
63d7bbe9 | 1555 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1556 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1557 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1558 | |
1c4e0274 | 1559 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1560 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1561 | /* |
1562 | * It appears to be important that we don't enable this | |
1563 | * for the current pipe before otherwise configuring the | |
1564 | * PLL. No idea how this should be handled if multiple | |
1565 | * DVO outputs are enabled simultaneosly. | |
1566 | */ | |
1567 | dpll |= DPLL_DVO_2X_MODE; | |
1568 | I915_WRITE(DPLL(!crtc->pipe), | |
1569 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1570 | } | |
66e3d5c0 | 1571 | |
c2b63374 VS |
1572 | /* |
1573 | * Apparently we need to have VGA mode enabled prior to changing | |
1574 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1575 | * dividers, even though the register value does change. | |
1576 | */ | |
1577 | I915_WRITE(reg, 0); | |
1578 | ||
8e7a65aa VS |
1579 | I915_WRITE(reg, dpll); |
1580 | ||
66e3d5c0 DV |
1581 | /* Wait for the clocks to stabilize. */ |
1582 | POSTING_READ(reg); | |
1583 | udelay(150); | |
1584 | ||
6315b5d3 | 1585 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1586 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1587 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1588 | } else { |
1589 | /* The pixel multiplier can only be updated once the | |
1590 | * DPLL is enabled and the clocks are stable. | |
1591 | * | |
1592 | * So write it again. | |
1593 | */ | |
1594 | I915_WRITE(reg, dpll); | |
1595 | } | |
63d7bbe9 JB |
1596 | |
1597 | /* We do this three times for luck */ | |
66e3d5c0 | 1598 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1599 | POSTING_READ(reg); |
1600 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1601 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1602 | POSTING_READ(reg); |
1603 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1604 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1605 | POSTING_READ(reg); |
1606 | udelay(150); /* wait for warmup */ | |
1607 | } | |
1608 | ||
1609 | /** | |
50b44a44 | 1610 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1611 | * @dev_priv: i915 private structure |
1612 | * @pipe: pipe PLL to disable | |
1613 | * | |
1614 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1615 | * | |
1616 | * Note! This is for pre-ILK only. | |
1617 | */ | |
1c4e0274 | 1618 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1619 | { |
6315b5d3 | 1620 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1621 | enum pipe pipe = crtc->pipe; |
1622 | ||
1623 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1624 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1625 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1626 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1627 | I915_WRITE(DPLL(PIPE_B), |
1628 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1629 | I915_WRITE(DPLL(PIPE_A), | |
1630 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1631 | } | |
1632 | ||
b6b5d049 VS |
1633 | /* Don't disable pipe or pipe PLLs if needed */ |
1634 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1635 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1636 | return; |
1637 | ||
1638 | /* Make sure the pipe isn't still relying on us */ | |
1639 | assert_pipe_disabled(dev_priv, pipe); | |
1640 | ||
b8afb911 | 1641 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1642 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1643 | } |
1644 | ||
f6071166 JB |
1645 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1646 | { | |
b8afb911 | 1647 | u32 val; |
f6071166 JB |
1648 | |
1649 | /* Make sure the pipe isn't still relying on us */ | |
1650 | assert_pipe_disabled(dev_priv, pipe); | |
1651 | ||
03ed5cbf VS |
1652 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1653 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1654 | if (pipe != PIPE_A) | |
1655 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1656 | ||
f6071166 JB |
1657 | I915_WRITE(DPLL(pipe), val); |
1658 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1659 | } |
1660 | ||
1661 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1662 | { | |
d752048d | 1663 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1664 | u32 val; |
1665 | ||
a11b0703 VS |
1666 | /* Make sure the pipe isn't still relying on us */ |
1667 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1668 | |
60bfe44f VS |
1669 | val = DPLL_SSC_REF_CLK_CHV | |
1670 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1671 | if (pipe != PIPE_A) |
1672 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1673 | |
a11b0703 VS |
1674 | I915_WRITE(DPLL(pipe), val); |
1675 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1676 | |
a580516d | 1677 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1678 | |
1679 | /* Disable 10bit clock to display controller */ | |
1680 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1681 | val &= ~DPIO_DCLKP_EN; | |
1682 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1683 | ||
a580516d | 1684 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1685 | } |
1686 | ||
e4607fcf | 1687 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1688 | struct intel_digital_port *dport, |
1689 | unsigned int expected_mask) | |
89b667f8 JB |
1690 | { |
1691 | u32 port_mask; | |
f0f59a00 | 1692 | i915_reg_t dpll_reg; |
89b667f8 | 1693 | |
e4607fcf CML |
1694 | switch (dport->port) { |
1695 | case PORT_B: | |
89b667f8 | 1696 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1697 | dpll_reg = DPLL(0); |
e4607fcf CML |
1698 | break; |
1699 | case PORT_C: | |
89b667f8 | 1700 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1701 | dpll_reg = DPLL(0); |
9b6de0a1 | 1702 | expected_mask <<= 4; |
00fc31b7 CML |
1703 | break; |
1704 | case PORT_D: | |
1705 | port_mask = DPLL_PORTD_READY_MASK; | |
1706 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1707 | break; |
1708 | default: | |
1709 | BUG(); | |
1710 | } | |
89b667f8 | 1711 | |
370004d3 CW |
1712 | if (intel_wait_for_register(dev_priv, |
1713 | dpll_reg, port_mask, expected_mask, | |
1714 | 1000)) | |
9b6de0a1 VS |
1715 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1716 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1717 | } |
1718 | ||
b8a4f404 PZ |
1719 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1720 | enum pipe pipe) | |
040484af | 1721 | { |
98187836 VS |
1722 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1723 | pipe); | |
f0f59a00 VS |
1724 | i915_reg_t reg; |
1725 | uint32_t val, pipeconf_val; | |
040484af | 1726 | |
040484af | 1727 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1728 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1729 | |
1730 | /* FDI must be feeding us bits for PCH ports */ | |
1731 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1732 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1733 | ||
6e266956 | 1734 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1735 | /* Workaround: Set the timing override bit before enabling the |
1736 | * pch transcoder. */ | |
1737 | reg = TRANS_CHICKEN2(pipe); | |
1738 | val = I915_READ(reg); | |
1739 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1740 | I915_WRITE(reg, val); | |
59c859d6 | 1741 | } |
23670b32 | 1742 | |
ab9412ba | 1743 | reg = PCH_TRANSCONF(pipe); |
040484af | 1744 | val = I915_READ(reg); |
5f7f726d | 1745 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1746 | |
2d1fe073 | 1747 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1748 | /* |
c5de7c6f VS |
1749 | * Make the BPC in transcoder be consistent with |
1750 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1751 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1752 | */ |
dfd07d72 | 1753 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1754 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1755 | val |= PIPECONF_8BPC; |
1756 | else | |
1757 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1758 | } |
5f7f726d PZ |
1759 | |
1760 | val &= ~TRANS_INTERLACE_MASK; | |
1761 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1762 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1763 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1764 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1765 | else | |
1766 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1767 | else |
1768 | val |= TRANS_PROGRESSIVE; | |
1769 | ||
040484af | 1770 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1771 | if (intel_wait_for_register(dev_priv, |
1772 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1773 | 100)) | |
4bb6f1f3 | 1774 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1775 | } |
1776 | ||
8fb033d7 | 1777 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1778 | enum transcoder cpu_transcoder) |
040484af | 1779 | { |
8fb033d7 | 1780 | u32 val, pipeconf_val; |
8fb033d7 | 1781 | |
8fb033d7 | 1782 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1783 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1784 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1785 | |
223a6fdf | 1786 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1787 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1788 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1789 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1790 | |
25f3ef11 | 1791 | val = TRANS_ENABLE; |
937bb610 | 1792 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1793 | |
9a76b1c6 PZ |
1794 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1795 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1796 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1797 | else |
1798 | val |= TRANS_PROGRESSIVE; | |
1799 | ||
ab9412ba | 1800 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1801 | if (intel_wait_for_register(dev_priv, |
1802 | LPT_TRANSCONF, | |
1803 | TRANS_STATE_ENABLE, | |
1804 | TRANS_STATE_ENABLE, | |
1805 | 100)) | |
937bb610 | 1806 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1807 | } |
1808 | ||
b8a4f404 PZ |
1809 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1810 | enum pipe pipe) | |
040484af | 1811 | { |
f0f59a00 VS |
1812 | i915_reg_t reg; |
1813 | uint32_t val; | |
040484af JB |
1814 | |
1815 | /* FDI relies on the transcoder */ | |
1816 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1817 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1818 | ||
291906f1 JB |
1819 | /* Ports must be off as well */ |
1820 | assert_pch_ports_disabled(dev_priv, pipe); | |
1821 | ||
ab9412ba | 1822 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1823 | val = I915_READ(reg); |
1824 | val &= ~TRANS_ENABLE; | |
1825 | I915_WRITE(reg, val); | |
1826 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1827 | if (intel_wait_for_register(dev_priv, |
1828 | reg, TRANS_STATE_ENABLE, 0, | |
1829 | 50)) | |
4bb6f1f3 | 1830 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1831 | |
6e266956 | 1832 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1833 | /* Workaround: Clear the timing override chicken bit again. */ |
1834 | reg = TRANS_CHICKEN2(pipe); | |
1835 | val = I915_READ(reg); | |
1836 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1837 | I915_WRITE(reg, val); | |
1838 | } | |
040484af JB |
1839 | } |
1840 | ||
b7076546 | 1841 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1842 | { |
8fb033d7 PZ |
1843 | u32 val; |
1844 | ||
ab9412ba | 1845 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1846 | val &= ~TRANS_ENABLE; |
ab9412ba | 1847 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1848 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1849 | if (intel_wait_for_register(dev_priv, |
1850 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1851 | 50)) | |
8a52fd9f | 1852 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1853 | |
1854 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1855 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1856 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1857 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1858 | } |
1859 | ||
65f2130c VS |
1860 | enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
1861 | { | |
1862 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1863 | ||
1864 | WARN_ON(!crtc->config->has_pch_encoder); | |
1865 | ||
1866 | if (HAS_PCH_LPT(dev_priv)) | |
1867 | return TRANSCODER_A; | |
1868 | else | |
1869 | return (enum transcoder) crtc->pipe; | |
1870 | } | |
1871 | ||
b24e7179 | 1872 | /** |
309cfea8 | 1873 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1874 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1875 | * |
0372264a | 1876 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1877 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1878 | */ |
e1fdc473 | 1879 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1880 | { |
0372264a | 1881 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1882 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1883 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1884 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1885 | i915_reg_t reg; |
b24e7179 JB |
1886 | u32 val; |
1887 | ||
9e2ee2dd VS |
1888 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1889 | ||
58c6eaa2 | 1890 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1891 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1892 | assert_sprites_disabled(dev_priv, pipe); |
1893 | ||
b24e7179 JB |
1894 | /* |
1895 | * A pipe without a PLL won't actually be able to drive bits from | |
1896 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1897 | * need the check. | |
1898 | */ | |
09fa8bb9 | 1899 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1900 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1901 | assert_dsi_pll_enabled(dev_priv); |
1902 | else | |
1903 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1904 | } else { |
6e3c9717 | 1905 | if (crtc->config->has_pch_encoder) { |
040484af | 1906 | /* if driving the PCH, we need FDI enabled */ |
65f2130c VS |
1907 | assert_fdi_rx_pll_enabled(dev_priv, |
1908 | (enum pipe) intel_crtc_pch_transcoder(crtc)); | |
1a240d4d DV |
1909 | assert_fdi_tx_pll_enabled(dev_priv, |
1910 | (enum pipe) cpu_transcoder); | |
040484af JB |
1911 | } |
1912 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1913 | } | |
b24e7179 | 1914 | |
702e7a56 | 1915 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1916 | val = I915_READ(reg); |
7ad25d48 | 1917 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1918 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1919 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1920 | return; |
7ad25d48 | 1921 | } |
00d70b15 CW |
1922 | |
1923 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1924 | POSTING_READ(reg); |
b7792d8b VS |
1925 | |
1926 | /* | |
1927 | * Until the pipe starts DSL will read as 0, which would cause | |
1928 | * an apparent vblank timestamp jump, which messes up also the | |
1929 | * frame count when it's derived from the timestamps. So let's | |
1930 | * wait for the pipe to start properly before we call | |
1931 | * drm_crtc_vblank_on() | |
1932 | */ | |
1933 | if (dev->max_vblank_count == 0 && | |
1934 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1935 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1936 | } |
1937 | ||
1938 | /** | |
309cfea8 | 1939 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 1940 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 1941 | * |
575f7ab7 VS |
1942 | * Disable the pipe of @crtc, making sure that various hardware |
1943 | * specific requirements are met, if applicable, e.g. plane | |
1944 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
1945 | * |
1946 | * Will wait until the pipe has shut down before returning. | |
1947 | */ | |
575f7ab7 | 1948 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1949 | { |
fac5e23e | 1950 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1951 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1952 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1953 | i915_reg_t reg; |
b24e7179 JB |
1954 | u32 val; |
1955 | ||
9e2ee2dd VS |
1956 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
1957 | ||
b24e7179 JB |
1958 | /* |
1959 | * Make sure planes won't keep trying to pump pixels to us, | |
1960 | * or we might hang the display. | |
1961 | */ | |
1962 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1963 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1964 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 1965 | |
702e7a56 | 1966 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1967 | val = I915_READ(reg); |
00d70b15 CW |
1968 | if ((val & PIPECONF_ENABLE) == 0) |
1969 | return; | |
1970 | ||
67adc644 VS |
1971 | /* |
1972 | * Double wide has implications for planes | |
1973 | * so best keep it disabled when not needed. | |
1974 | */ | |
6e3c9717 | 1975 | if (crtc->config->double_wide) |
67adc644 VS |
1976 | val &= ~PIPECONF_DOUBLE_WIDE; |
1977 | ||
1978 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
1979 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
1980 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
1981 | val &= ~PIPECONF_ENABLE; |
1982 | ||
1983 | I915_WRITE(reg, val); | |
1984 | if ((val & PIPECONF_ENABLE) == 0) | |
1985 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
1986 | } |
1987 | ||
832be82f VS |
1988 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
1989 | { | |
1990 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
1991 | } | |
1992 | ||
27ba3910 VS |
1993 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
1994 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
1995 | { |
1996 | switch (fb_modifier) { | |
1997 | case DRM_FORMAT_MOD_NONE: | |
1998 | return cpp; | |
1999 | case I915_FORMAT_MOD_X_TILED: | |
2000 | if (IS_GEN2(dev_priv)) | |
2001 | return 128; | |
2002 | else | |
2003 | return 512; | |
2004 | case I915_FORMAT_MOD_Y_TILED: | |
2005 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2006 | return 128; | |
2007 | else | |
2008 | return 512; | |
2009 | case I915_FORMAT_MOD_Yf_TILED: | |
2010 | switch (cpp) { | |
2011 | case 1: | |
2012 | return 64; | |
2013 | case 2: | |
2014 | case 4: | |
2015 | return 128; | |
2016 | case 8: | |
2017 | case 16: | |
2018 | return 256; | |
2019 | default: | |
2020 | MISSING_CASE(cpp); | |
2021 | return cpp; | |
2022 | } | |
2023 | break; | |
2024 | default: | |
2025 | MISSING_CASE(fb_modifier); | |
2026 | return cpp; | |
2027 | } | |
2028 | } | |
2029 | ||
832be82f VS |
2030 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2031 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2032 | { |
832be82f VS |
2033 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2034 | return 1; | |
2035 | else | |
2036 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2037 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2038 | } |
2039 | ||
8d0deca8 VS |
2040 | /* Return the tile dimensions in pixel units */ |
2041 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2042 | unsigned int *tile_width, | |
2043 | unsigned int *tile_height, | |
2044 | uint64_t fb_modifier, | |
2045 | unsigned int cpp) | |
2046 | { | |
2047 | unsigned int tile_width_bytes = | |
2048 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2049 | ||
2050 | *tile_width = tile_width_bytes / cpp; | |
2051 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2052 | } | |
2053 | ||
6761dd31 | 2054 | unsigned int |
24dbf51a CW |
2055 | intel_fb_align_height(struct drm_i915_private *dev_priv, |
2056 | unsigned int height, | |
2057 | uint32_t pixel_format, | |
2058 | uint64_t fb_modifier) | |
6761dd31 | 2059 | { |
832be82f | 2060 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
24dbf51a | 2061 | unsigned int tile_height = intel_tile_height(dev_priv, fb_modifier, cpp); |
832be82f VS |
2062 | |
2063 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2064 | } |
2065 | ||
1663b9d6 VS |
2066 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2067 | { | |
2068 | unsigned int size = 0; | |
2069 | int i; | |
2070 | ||
2071 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2072 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2073 | ||
2074 | return size; | |
2075 | } | |
2076 | ||
75c82a53 | 2077 | static void |
3465c580 VS |
2078 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2079 | const struct drm_framebuffer *fb, | |
2080 | unsigned int rotation) | |
f64b98cd | 2081 | { |
7b92c047 | 2082 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2083 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2084 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2085 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2086 | } |
2087 | } | |
50470bb0 | 2088 | |
603525d7 | 2089 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2090 | { |
2091 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2092 | return 256 * 1024; | |
c0f86832 | 2093 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2094 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2095 | return 128 * 1024; |
2096 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2097 | return 4 * 1024; | |
2098 | else | |
44c5905e | 2099 | return 0; |
4e9a86b6 VS |
2100 | } |
2101 | ||
603525d7 VS |
2102 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2103 | uint64_t fb_modifier) | |
2104 | { | |
2105 | switch (fb_modifier) { | |
2106 | case DRM_FORMAT_MOD_NONE: | |
2107 | return intel_linear_alignment(dev_priv); | |
2108 | case I915_FORMAT_MOD_X_TILED: | |
2109 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2110 | return 256 * 1024; | |
2111 | return 0; | |
2112 | case I915_FORMAT_MOD_Y_TILED: | |
2113 | case I915_FORMAT_MOD_Yf_TILED: | |
2114 | return 1 * 1024 * 1024; | |
2115 | default: | |
2116 | MISSING_CASE(fb_modifier); | |
2117 | return 0; | |
2118 | } | |
2119 | } | |
2120 | ||
058d88c4 CW |
2121 | struct i915_vma * |
2122 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2123 | { |
850c4cdc | 2124 | struct drm_device *dev = fb->dev; |
fac5e23e | 2125 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2126 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2127 | struct i915_ggtt_view view; |
058d88c4 | 2128 | struct i915_vma *vma; |
6b95a207 | 2129 | u32 alignment; |
6b95a207 | 2130 | |
ebcdd39e MR |
2131 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2132 | ||
bae781b2 | 2133 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
6b95a207 | 2134 | |
3465c580 | 2135 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2136 | |
693db184 CW |
2137 | /* Note that the w/a also requires 64 PTE of padding following the |
2138 | * bo. We currently fill all unused PTE with the shadow page and so | |
2139 | * we should always have valid PTE following the scanout preventing | |
2140 | * the VT-d warning. | |
2141 | */ | |
48f112fe | 2142 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2143 | alignment = 256 * 1024; |
2144 | ||
d6dd6843 PZ |
2145 | /* |
2146 | * Global gtt pte registers are special registers which actually forward | |
2147 | * writes to a chunk of system memory. Which means that there is no risk | |
2148 | * that the register values disappear as soon as we call | |
2149 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2150 | * pin/unpin/fence and not more. | |
2151 | */ | |
2152 | intel_runtime_pm_get(dev_priv); | |
2153 | ||
058d88c4 | 2154 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2155 | if (IS_ERR(vma)) |
2156 | goto err; | |
6b95a207 | 2157 | |
05a20d09 | 2158 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2159 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2160 | * fence, whereas 965+ only requires a fence if using | |
2161 | * framebuffer compression. For simplicity, we always, when | |
2162 | * possible, install a fence as the cost is not that onerous. | |
2163 | * | |
2164 | * If we fail to fence the tiled scanout, then either the | |
2165 | * modeset will reject the change (which is highly unlikely as | |
2166 | * the affected systems, all but one, do not have unmappable | |
2167 | * space) or we will not be able to enable full powersaving | |
2168 | * techniques (also likely not to apply due to various limits | |
2169 | * FBC and the like impose on the size of the buffer, which | |
2170 | * presumably we violated anyway with this unmappable buffer). | |
2171 | * Anyway, it is presumably better to stumble onwards with | |
2172 | * something and try to run the system in a "less than optimal" | |
2173 | * mode that matches the user configuration. | |
2174 | */ | |
2175 | if (i915_vma_get_fence(vma) == 0) | |
2176 | i915_vma_pin_fence(vma); | |
9807216f | 2177 | } |
6b95a207 | 2178 | |
be1e3415 | 2179 | i915_vma_get(vma); |
49ef5294 | 2180 | err: |
d6dd6843 | 2181 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2182 | return vma; |
6b95a207 KH |
2183 | } |
2184 | ||
be1e3415 | 2185 | void intel_unpin_fb_vma(struct i915_vma *vma) |
1690e1eb | 2186 | { |
be1e3415 | 2187 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
f64b98cd | 2188 | |
49ef5294 | 2189 | i915_vma_unpin_fence(vma); |
058d88c4 | 2190 | i915_gem_object_unpin_from_display_plane(vma); |
be1e3415 | 2191 | i915_vma_put(vma); |
1690e1eb CW |
2192 | } |
2193 | ||
ef78ec94 VS |
2194 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2195 | unsigned int rotation) | |
2196 | { | |
bd2ef25d | 2197 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2198 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2199 | else | |
2200 | return fb->pitches[plane]; | |
2201 | } | |
2202 | ||
6687c906 VS |
2203 | /* |
2204 | * Convert the x/y offsets into a linear offset. | |
2205 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2206 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2207 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2208 | */ | |
2209 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2210 | const struct intel_plane_state *state, |
2211 | int plane) | |
6687c906 | 2212 | { |
2949056c | 2213 | const struct drm_framebuffer *fb = state->base.fb; |
353c8598 | 2214 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2215 | unsigned int pitch = fb->pitches[plane]; |
2216 | ||
2217 | return y * pitch + x * cpp; | |
2218 | } | |
2219 | ||
2220 | /* | |
2221 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2222 | * specified plane src x/y offsets. The resulting x/y offsets | |
2223 | * specify the start of scanout from the beginning of the gtt mapping. | |
2224 | */ | |
2225 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2226 | const struct intel_plane_state *state, |
2227 | int plane) | |
6687c906 VS |
2228 | |
2229 | { | |
2949056c VS |
2230 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2231 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2232 | |
bd2ef25d | 2233 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2234 | *x += intel_fb->rotated[plane].x; |
2235 | *y += intel_fb->rotated[plane].y; | |
2236 | } else { | |
2237 | *x += intel_fb->normal[plane].x; | |
2238 | *y += intel_fb->normal[plane].y; | |
2239 | } | |
2240 | } | |
2241 | ||
29cf9491 | 2242 | /* |
29cf9491 VS |
2243 | * Input tile dimensions and pitch must already be |
2244 | * rotated to match x and y, and in pixel units. | |
2245 | */ | |
66a2d927 VS |
2246 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2247 | unsigned int tile_width, | |
2248 | unsigned int tile_height, | |
2249 | unsigned int tile_size, | |
2250 | unsigned int pitch_tiles, | |
2251 | u32 old_offset, | |
2252 | u32 new_offset) | |
29cf9491 | 2253 | { |
b9b24038 | 2254 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2255 | unsigned int tiles; |
2256 | ||
2257 | WARN_ON(old_offset & (tile_size - 1)); | |
2258 | WARN_ON(new_offset & (tile_size - 1)); | |
2259 | WARN_ON(new_offset > old_offset); | |
2260 | ||
2261 | tiles = (old_offset - new_offset) / tile_size; | |
2262 | ||
2263 | *y += tiles / pitch_tiles * tile_height; | |
2264 | *x += tiles % pitch_tiles * tile_width; | |
2265 | ||
b9b24038 VS |
2266 | /* minimize x in case it got needlessly big */ |
2267 | *y += *x / pitch_pixels * tile_height; | |
2268 | *x %= pitch_pixels; | |
2269 | ||
29cf9491 VS |
2270 | return new_offset; |
2271 | } | |
2272 | ||
66a2d927 VS |
2273 | /* |
2274 | * Adjust the tile offset by moving the difference into | |
2275 | * the x/y offsets. | |
2276 | */ | |
2277 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2278 | const struct intel_plane_state *state, int plane, | |
2279 | u32 old_offset, u32 new_offset) | |
2280 | { | |
2281 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2282 | const struct drm_framebuffer *fb = state->base.fb; | |
353c8598 | 2283 | unsigned int cpp = fb->format->cpp[plane]; |
66a2d927 VS |
2284 | unsigned int rotation = state->base.rotation; |
2285 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2286 | ||
2287 | WARN_ON(new_offset > old_offset); | |
2288 | ||
bae781b2 | 2289 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
66a2d927 VS |
2290 | unsigned int tile_size, tile_width, tile_height; |
2291 | unsigned int pitch_tiles; | |
2292 | ||
2293 | tile_size = intel_tile_size(dev_priv); | |
2294 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
bae781b2 | 2295 | fb->modifier, cpp); |
66a2d927 | 2296 | |
bd2ef25d | 2297 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2298 | pitch_tiles = pitch / tile_height; |
2299 | swap(tile_width, tile_height); | |
2300 | } else { | |
2301 | pitch_tiles = pitch / (tile_width * cpp); | |
2302 | } | |
2303 | ||
2304 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2305 | tile_size, pitch_tiles, | |
2306 | old_offset, new_offset); | |
2307 | } else { | |
2308 | old_offset += *y * pitch + *x * cpp; | |
2309 | ||
2310 | *y = (old_offset - new_offset) / pitch; | |
2311 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2312 | } | |
2313 | ||
2314 | return new_offset; | |
2315 | } | |
2316 | ||
8d0deca8 VS |
2317 | /* |
2318 | * Computes the linear offset to the base tile and adjusts | |
2319 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2320 | * | |
2321 | * In the 90/270 rotated case, x and y are assumed | |
2322 | * to be already rotated to match the rotated GTT view, and | |
2323 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2324 | * |
2325 | * This function is used when computing the derived information | |
2326 | * under intel_framebuffer, so using any of that information | |
2327 | * here is not allowed. Anything under drm_framebuffer can be | |
2328 | * used. This is why the user has to pass in the pitch since it | |
2329 | * is specified in the rotated orientation. | |
8d0deca8 | 2330 | */ |
6687c906 VS |
2331 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2332 | int *x, int *y, | |
2333 | const struct drm_framebuffer *fb, int plane, | |
2334 | unsigned int pitch, | |
2335 | unsigned int rotation, | |
2336 | u32 alignment) | |
c2c75131 | 2337 | { |
bae781b2 | 2338 | uint64_t fb_modifier = fb->modifier; |
353c8598 | 2339 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 | 2340 | u32 offset, offset_aligned; |
29cf9491 | 2341 | |
29cf9491 VS |
2342 | if (alignment) |
2343 | alignment--; | |
2344 | ||
b5c65338 | 2345 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2346 | unsigned int tile_size, tile_width, tile_height; |
2347 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2348 | |
d843310d | 2349 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2350 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2351 | fb_modifier, cpp); | |
2352 | ||
bd2ef25d | 2353 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2354 | pitch_tiles = pitch / tile_height; |
2355 | swap(tile_width, tile_height); | |
2356 | } else { | |
2357 | pitch_tiles = pitch / (tile_width * cpp); | |
2358 | } | |
d843310d VS |
2359 | |
2360 | tile_rows = *y / tile_height; | |
2361 | *y %= tile_height; | |
c2c75131 | 2362 | |
8d0deca8 VS |
2363 | tiles = *x / tile_width; |
2364 | *x %= tile_width; | |
bc752862 | 2365 | |
29cf9491 VS |
2366 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2367 | offset_aligned = offset & ~alignment; | |
bc752862 | 2368 | |
66a2d927 VS |
2369 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2370 | tile_size, pitch_tiles, | |
2371 | offset, offset_aligned); | |
29cf9491 | 2372 | } else { |
bc752862 | 2373 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2374 | offset_aligned = offset & ~alignment; |
2375 | ||
4e9a86b6 VS |
2376 | *y = (offset & alignment) / pitch; |
2377 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2378 | } |
29cf9491 VS |
2379 | |
2380 | return offset_aligned; | |
c2c75131 DV |
2381 | } |
2382 | ||
6687c906 | 2383 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2384 | const struct intel_plane_state *state, |
2385 | int plane) | |
6687c906 | 2386 | { |
2949056c VS |
2387 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
2388 | const struct drm_framebuffer *fb = state->base.fb; | |
2389 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2390 | int pitch = intel_fb_pitch(fb, plane, rotation); |
8d970654 VS |
2391 | u32 alignment; |
2392 | ||
2393 | /* AUX_DIST needs only 4K alignment */ | |
438b74a5 | 2394 | if (fb->format->format == DRM_FORMAT_NV12 && plane == 1) |
8d970654 VS |
2395 | alignment = 4096; |
2396 | else | |
bae781b2 | 2397 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
6687c906 VS |
2398 | |
2399 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2400 | rotation, alignment); | |
2401 | } | |
2402 | ||
2403 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2404 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2405 | const struct drm_framebuffer *fb, int plane) | |
2406 | { | |
353c8598 | 2407 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2408 | unsigned int pitch = fb->pitches[plane]; |
2409 | u32 linear_offset = fb->offsets[plane]; | |
2410 | ||
2411 | *y = linear_offset / pitch; | |
2412 | *x = linear_offset % pitch / cpp; | |
2413 | } | |
2414 | ||
72618ebf VS |
2415 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2416 | { | |
2417 | switch (fb_modifier) { | |
2418 | case I915_FORMAT_MOD_X_TILED: | |
2419 | return I915_TILING_X; | |
2420 | case I915_FORMAT_MOD_Y_TILED: | |
2421 | return I915_TILING_Y; | |
2422 | default: | |
2423 | return I915_TILING_NONE; | |
2424 | } | |
2425 | } | |
2426 | ||
6687c906 VS |
2427 | static int |
2428 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2429 | struct drm_framebuffer *fb) | |
2430 | { | |
2431 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2432 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2433 | u32 gtt_offset_rotated = 0; | |
2434 | unsigned int max_size = 0; | |
bcb0b461 | 2435 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
2436 | unsigned int tile_size = intel_tile_size(dev_priv); |
2437 | ||
2438 | for (i = 0; i < num_planes; i++) { | |
2439 | unsigned int width, height; | |
2440 | unsigned int cpp, size; | |
2441 | u32 offset; | |
2442 | int x, y; | |
2443 | ||
353c8598 | 2444 | cpp = fb->format->cpp[i]; |
145fcb11 VS |
2445 | width = drm_framebuffer_plane_width(fb->width, fb, i); |
2446 | height = drm_framebuffer_plane_height(fb->height, fb, i); | |
6687c906 VS |
2447 | |
2448 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2449 | ||
60d5f2a4 VS |
2450 | /* |
2451 | * The fence (if used) is aligned to the start of the object | |
2452 | * so having the framebuffer wrap around across the edge of the | |
2453 | * fenced region doesn't really work. We have no API to configure | |
2454 | * the fence start offset within the object (nor could we probably | |
2455 | * on gen2/3). So it's just easier if we just require that the | |
2456 | * fb layout agrees with the fence layout. We already check that the | |
2457 | * fb stride matches the fence stride elsewhere. | |
2458 | */ | |
2459 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2460 | (x + width) * cpp > fb->pitches[i]) { | |
2461 | DRM_DEBUG("bad fb plane %d offset: 0x%x\n", | |
2462 | i, fb->offsets[i]); | |
2463 | return -EINVAL; | |
2464 | } | |
2465 | ||
6687c906 VS |
2466 | /* |
2467 | * First pixel of the framebuffer from | |
2468 | * the start of the normal gtt mapping. | |
2469 | */ | |
2470 | intel_fb->normal[i].x = x; | |
2471 | intel_fb->normal[i].y = y; | |
2472 | ||
2473 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
2474 | fb, 0, fb->pitches[i], | |
cc926387 | 2475 | DRM_ROTATE_0, tile_size); |
6687c906 VS |
2476 | offset /= tile_size; |
2477 | ||
bae781b2 | 2478 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
6687c906 VS |
2479 | unsigned int tile_width, tile_height; |
2480 | unsigned int pitch_tiles; | |
2481 | struct drm_rect r; | |
2482 | ||
2483 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
bae781b2 | 2484 | fb->modifier, cpp); |
6687c906 VS |
2485 | |
2486 | rot_info->plane[i].offset = offset; | |
2487 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2488 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2489 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2490 | ||
2491 | intel_fb->rotated[i].pitch = | |
2492 | rot_info->plane[i].height * tile_height; | |
2493 | ||
2494 | /* how many tiles does this plane need */ | |
2495 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2496 | /* | |
2497 | * If the plane isn't horizontally tile aligned, | |
2498 | * we need one more tile. | |
2499 | */ | |
2500 | if (x != 0) | |
2501 | size++; | |
2502 | ||
2503 | /* rotate the x/y offsets to match the GTT view */ | |
2504 | r.x1 = x; | |
2505 | r.y1 = y; | |
2506 | r.x2 = x + width; | |
2507 | r.y2 = y + height; | |
2508 | drm_rect_rotate(&r, | |
2509 | rot_info->plane[i].width * tile_width, | |
2510 | rot_info->plane[i].height * tile_height, | |
cc926387 | 2511 | DRM_ROTATE_270); |
6687c906 VS |
2512 | x = r.x1; |
2513 | y = r.y1; | |
2514 | ||
2515 | /* rotate the tile dimensions to match the GTT view */ | |
2516 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2517 | swap(tile_width, tile_height); | |
2518 | ||
2519 | /* | |
2520 | * We only keep the x/y offsets, so push all of the | |
2521 | * gtt offset into the x/y offsets. | |
2522 | */ | |
46a1bd28 ACO |
2523 | _intel_adjust_tile_offset(&x, &y, |
2524 | tile_width, tile_height, | |
2525 | tile_size, pitch_tiles, | |
66a2d927 | 2526 | gtt_offset_rotated * tile_size, 0); |
6687c906 VS |
2527 | |
2528 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2529 | ||
2530 | /* | |
2531 | * First pixel of the framebuffer from | |
2532 | * the start of the rotated gtt mapping. | |
2533 | */ | |
2534 | intel_fb->rotated[i].x = x; | |
2535 | intel_fb->rotated[i].y = y; | |
2536 | } else { | |
2537 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2538 | x * cpp, tile_size); | |
2539 | } | |
2540 | ||
2541 | /* how many tiles in total needed in the bo */ | |
2542 | max_size = max(max_size, offset + size); | |
2543 | } | |
2544 | ||
2545 | if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { | |
2546 | DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2547 | max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); | |
2548 | return -EINVAL; | |
2549 | } | |
2550 | ||
2551 | return 0; | |
2552 | } | |
2553 | ||
b35d63fa | 2554 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2555 | { |
2556 | switch (format) { | |
2557 | case DISPPLANE_8BPP: | |
2558 | return DRM_FORMAT_C8; | |
2559 | case DISPPLANE_BGRX555: | |
2560 | return DRM_FORMAT_XRGB1555; | |
2561 | case DISPPLANE_BGRX565: | |
2562 | return DRM_FORMAT_RGB565; | |
2563 | default: | |
2564 | case DISPPLANE_BGRX888: | |
2565 | return DRM_FORMAT_XRGB8888; | |
2566 | case DISPPLANE_RGBX888: | |
2567 | return DRM_FORMAT_XBGR8888; | |
2568 | case DISPPLANE_BGRX101010: | |
2569 | return DRM_FORMAT_XRGB2101010; | |
2570 | case DISPPLANE_RGBX101010: | |
2571 | return DRM_FORMAT_XBGR2101010; | |
2572 | } | |
2573 | } | |
2574 | ||
bc8d7dff DL |
2575 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2576 | { | |
2577 | switch (format) { | |
2578 | case PLANE_CTL_FORMAT_RGB_565: | |
2579 | return DRM_FORMAT_RGB565; | |
2580 | default: | |
2581 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2582 | if (rgb_order) { | |
2583 | if (alpha) | |
2584 | return DRM_FORMAT_ABGR8888; | |
2585 | else | |
2586 | return DRM_FORMAT_XBGR8888; | |
2587 | } else { | |
2588 | if (alpha) | |
2589 | return DRM_FORMAT_ARGB8888; | |
2590 | else | |
2591 | return DRM_FORMAT_XRGB8888; | |
2592 | } | |
2593 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2594 | if (rgb_order) | |
2595 | return DRM_FORMAT_XBGR2101010; | |
2596 | else | |
2597 | return DRM_FORMAT_XRGB2101010; | |
2598 | } | |
2599 | } | |
2600 | ||
5724dbd1 | 2601 | static bool |
f6936e29 DV |
2602 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2603 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2604 | { |
2605 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2606 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2607 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2608 | struct drm_i915_gem_object *obj = NULL; |
2609 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2610 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2611 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2612 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2613 | PAGE_SIZE); | |
2614 | ||
2615 | size_aligned -= base_aligned; | |
46f297fb | 2616 | |
ff2652ea CW |
2617 | if (plane_config->size == 0) |
2618 | return false; | |
2619 | ||
3badb49f PZ |
2620 | /* If the FB is too big, just don't use it since fbdev is not very |
2621 | * important and we should probably use that space with FBC or other | |
2622 | * features. */ | |
72e96d64 | 2623 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2624 | return false; |
2625 | ||
12c83d99 | 2626 | mutex_lock(&dev->struct_mutex); |
187685cb | 2627 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2628 | base_aligned, |
2629 | base_aligned, | |
2630 | size_aligned); | |
24dbf51a CW |
2631 | mutex_unlock(&dev->struct_mutex); |
2632 | if (!obj) | |
484b41dd | 2633 | return false; |
46f297fb | 2634 | |
3e510a8e CW |
2635 | if (plane_config->tiling == I915_TILING_X) |
2636 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2637 | |
438b74a5 | 2638 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
2639 | mode_cmd.width = fb->width; |
2640 | mode_cmd.height = fb->height; | |
2641 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2642 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2643 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2644 | |
24dbf51a | 2645 | if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { |
46f297fb JB |
2646 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2647 | goto out_unref_obj; | |
2648 | } | |
12c83d99 | 2649 | |
484b41dd | 2650 | |
f6936e29 | 2651 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2652 | return true; |
46f297fb JB |
2653 | |
2654 | out_unref_obj: | |
f8c417cd | 2655 | i915_gem_object_put(obj); |
484b41dd JB |
2656 | return false; |
2657 | } | |
2658 | ||
5a21b665 DV |
2659 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2660 | static void | |
2661 | update_state_fb(struct drm_plane *plane) | |
2662 | { | |
2663 | if (plane->fb == plane->state->fb) | |
2664 | return; | |
2665 | ||
2666 | if (plane->state->fb) | |
2667 | drm_framebuffer_unreference(plane->state->fb); | |
2668 | plane->state->fb = plane->fb; | |
2669 | if (plane->state->fb) | |
2670 | drm_framebuffer_reference(plane->state->fb); | |
2671 | } | |
2672 | ||
e9728bd8 VS |
2673 | static void |
2674 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
2675 | struct intel_plane_state *plane_state, | |
2676 | bool visible) | |
2677 | { | |
2678 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
2679 | ||
2680 | plane_state->base.visible = visible; | |
2681 | ||
2682 | /* FIXME pre-g4x don't work like this */ | |
2683 | if (visible) { | |
2684 | crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); | |
2685 | crtc_state->active_planes |= BIT(plane->id); | |
2686 | } else { | |
2687 | crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); | |
2688 | crtc_state->active_planes &= ~BIT(plane->id); | |
2689 | } | |
2690 | ||
2691 | DRM_DEBUG_KMS("%s active planes 0x%x\n", | |
2692 | crtc_state->base.crtc->name, | |
2693 | crtc_state->active_planes); | |
2694 | } | |
2695 | ||
5724dbd1 | 2696 | static void |
f6936e29 DV |
2697 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2698 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2699 | { |
2700 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2701 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 2702 | struct drm_crtc *c; |
2ff8fde1 | 2703 | struct drm_i915_gem_object *obj; |
88595ac9 | 2704 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2705 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2706 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2707 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2708 | struct intel_plane_state *intel_state = |
2709 | to_intel_plane_state(plane_state); | |
88595ac9 | 2710 | struct drm_framebuffer *fb; |
484b41dd | 2711 | |
2d14030b | 2712 | if (!plane_config->fb) |
484b41dd JB |
2713 | return; |
2714 | ||
f6936e29 | 2715 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2716 | fb = &plane_config->fb->base; |
2717 | goto valid_fb; | |
f55548b5 | 2718 | } |
484b41dd | 2719 | |
2d14030b | 2720 | kfree(plane_config->fb); |
484b41dd JB |
2721 | |
2722 | /* | |
2723 | * Failed to alloc the obj, check to see if we should share | |
2724 | * an fb with another CRTC instead | |
2725 | */ | |
70e1e0ec | 2726 | for_each_crtc(dev, c) { |
be1e3415 | 2727 | struct intel_plane_state *state; |
484b41dd JB |
2728 | |
2729 | if (c == &intel_crtc->base) | |
2730 | continue; | |
2731 | ||
be1e3415 | 2732 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
2733 | continue; |
2734 | ||
be1e3415 CW |
2735 | state = to_intel_plane_state(c->primary->state); |
2736 | if (!state->vma) | |
484b41dd JB |
2737 | continue; |
2738 | ||
be1e3415 CW |
2739 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
2740 | fb = c->primary->fb; | |
88595ac9 DV |
2741 | drm_framebuffer_reference(fb); |
2742 | goto valid_fb; | |
484b41dd JB |
2743 | } |
2744 | } | |
88595ac9 | 2745 | |
200757f5 MR |
2746 | /* |
2747 | * We've failed to reconstruct the BIOS FB. Current display state | |
2748 | * indicates that the primary plane is visible, but has a NULL FB, | |
2749 | * which will lead to problems later if we don't fix it up. The | |
2750 | * simplest solution is to just disable the primary plane now and | |
2751 | * pretend the BIOS never had it enabled. | |
2752 | */ | |
e9728bd8 VS |
2753 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), |
2754 | to_intel_plane_state(plane_state), | |
2755 | false); | |
2622a081 | 2756 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2757 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2758 | ||
88595ac9 DV |
2759 | return; |
2760 | ||
2761 | valid_fb: | |
be1e3415 CW |
2762 | mutex_lock(&dev->struct_mutex); |
2763 | intel_state->vma = | |
2764 | intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
2765 | mutex_unlock(&dev->struct_mutex); | |
2766 | if (IS_ERR(intel_state->vma)) { | |
2767 | DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", | |
2768 | intel_crtc->pipe, PTR_ERR(intel_state->vma)); | |
2769 | ||
2770 | intel_state->vma = NULL; | |
2771 | drm_framebuffer_unreference(fb); | |
2772 | return; | |
2773 | } | |
2774 | ||
f44e2659 VS |
2775 | plane_state->src_x = 0; |
2776 | plane_state->src_y = 0; | |
be5651f2 ML |
2777 | plane_state->src_w = fb->width << 16; |
2778 | plane_state->src_h = fb->height << 16; | |
2779 | ||
f44e2659 VS |
2780 | plane_state->crtc_x = 0; |
2781 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2782 | plane_state->crtc_w = fb->width; |
2783 | plane_state->crtc_h = fb->height; | |
2784 | ||
1638d30c RC |
2785 | intel_state->base.src = drm_plane_state_src(plane_state); |
2786 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2787 | |
88595ac9 | 2788 | obj = intel_fb_obj(fb); |
3e510a8e | 2789 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2790 | dev_priv->preserve_bios_swizzle = true; |
2791 | ||
be5651f2 ML |
2792 | drm_framebuffer_reference(fb); |
2793 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2794 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
e9728bd8 VS |
2795 | |
2796 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), | |
2797 | to_intel_plane_state(plane_state), | |
2798 | true); | |
2799 | ||
faf5bf0a CW |
2800 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2801 | &obj->frontbuffer_bits); | |
46f297fb JB |
2802 | } |
2803 | ||
b63a16f6 VS |
2804 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2805 | unsigned int rotation) | |
2806 | { | |
353c8598 | 2807 | int cpp = fb->format->cpp[plane]; |
b63a16f6 | 2808 | |
bae781b2 | 2809 | switch (fb->modifier) { |
b63a16f6 VS |
2810 | case DRM_FORMAT_MOD_NONE: |
2811 | case I915_FORMAT_MOD_X_TILED: | |
2812 | switch (cpp) { | |
2813 | case 8: | |
2814 | return 4096; | |
2815 | case 4: | |
2816 | case 2: | |
2817 | case 1: | |
2818 | return 8192; | |
2819 | default: | |
2820 | MISSING_CASE(cpp); | |
2821 | break; | |
2822 | } | |
2823 | break; | |
2824 | case I915_FORMAT_MOD_Y_TILED: | |
2825 | case I915_FORMAT_MOD_Yf_TILED: | |
2826 | switch (cpp) { | |
2827 | case 8: | |
2828 | return 2048; | |
2829 | case 4: | |
2830 | return 4096; | |
2831 | case 2: | |
2832 | case 1: | |
2833 | return 8192; | |
2834 | default: | |
2835 | MISSING_CASE(cpp); | |
2836 | break; | |
2837 | } | |
2838 | break; | |
2839 | default: | |
bae781b2 | 2840 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2841 | } |
2842 | ||
2843 | return 2048; | |
2844 | } | |
2845 | ||
2846 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2847 | { | |
2848 | const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); | |
2849 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2850 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2851 | int x = plane_state->base.src.x1 >> 16; |
2852 | int y = plane_state->base.src.y1 >> 16; | |
2853 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2854 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2855 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2856 | int max_height = 4096; | |
8d970654 | 2857 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2858 | |
2859 | if (w > max_width || h > max_height) { | |
2860 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2861 | w, h, max_width, max_height); | |
2862 | return -EINVAL; | |
2863 | } | |
2864 | ||
2865 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2866 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
2867 | ||
bae781b2 | 2868 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
b63a16f6 | 2869 | |
8d970654 VS |
2870 | /* |
2871 | * AUX surface offset is specified as the distance from the | |
2872 | * main surface offset, and it must be non-negative. Make | |
2873 | * sure that is what we will get. | |
2874 | */ | |
2875 | if (offset > aux_offset) | |
2876 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2877 | offset, aux_offset & ~(alignment - 1)); | |
2878 | ||
b63a16f6 VS |
2879 | /* |
2880 | * When using an X-tiled surface, the plane blows up | |
2881 | * if the x offset + width exceed the stride. | |
2882 | * | |
2883 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2884 | */ | |
bae781b2 | 2885 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 2886 | int cpp = fb->format->cpp[0]; |
b63a16f6 VS |
2887 | |
2888 | while ((x + w) * cpp > fb->pitches[0]) { | |
2889 | if (offset == 0) { | |
2890 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2891 | return -EINVAL; | |
2892 | } | |
2893 | ||
2894 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2895 | offset, offset - alignment); | |
2896 | } | |
2897 | } | |
2898 | ||
2899 | plane_state->main.offset = offset; | |
2900 | plane_state->main.x = x; | |
2901 | plane_state->main.y = y; | |
2902 | ||
2903 | return 0; | |
2904 | } | |
2905 | ||
8d970654 VS |
2906 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2907 | { | |
2908 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2909 | unsigned int rotation = plane_state->base.rotation; | |
2910 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2911 | int max_height = 4096; | |
cc926387 DV |
2912 | int x = plane_state->base.src.x1 >> 17; |
2913 | int y = plane_state->base.src.y1 >> 17; | |
2914 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2915 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2916 | u32 offset; |
2917 | ||
2918 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2919 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2920 | ||
2921 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2922 | if (w > max_width || h > max_height) { | |
2923 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2924 | w, h, max_width, max_height); | |
2925 | return -EINVAL; | |
2926 | } | |
2927 | ||
2928 | plane_state->aux.offset = offset; | |
2929 | plane_state->aux.x = x; | |
2930 | plane_state->aux.y = y; | |
2931 | ||
2932 | return 0; | |
2933 | } | |
2934 | ||
b63a16f6 VS |
2935 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2936 | { | |
2937 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2938 | unsigned int rotation = plane_state->base.rotation; | |
2939 | int ret; | |
2940 | ||
a5e4c7d0 VS |
2941 | if (!plane_state->base.visible) |
2942 | return 0; | |
2943 | ||
b63a16f6 | 2944 | /* Rotate src coordinates to match rotated GTT view */ |
bd2ef25d | 2945 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 2946 | drm_rect_rotate(&plane_state->base.src, |
da064b47 VS |
2947 | fb->width << 16, fb->height << 16, |
2948 | DRM_ROTATE_270); | |
b63a16f6 | 2949 | |
8d970654 VS |
2950 | /* |
2951 | * Handle the AUX surface first since | |
2952 | * the main surface setup depends on it. | |
2953 | */ | |
438b74a5 | 2954 | if (fb->format->format == DRM_FORMAT_NV12) { |
8d970654 VS |
2955 | ret = skl_check_nv12_aux_surface(plane_state); |
2956 | if (ret) | |
2957 | return ret; | |
2958 | } else { | |
2959 | plane_state->aux.offset = ~0xfff; | |
2960 | plane_state->aux.x = 0; | |
2961 | plane_state->aux.y = 0; | |
2962 | } | |
2963 | ||
b63a16f6 VS |
2964 | ret = skl_check_main_surface(plane_state); |
2965 | if (ret) | |
2966 | return ret; | |
2967 | ||
2968 | return 0; | |
2969 | } | |
2970 | ||
a8d201af ML |
2971 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2972 | const struct intel_crtc_state *crtc_state, | |
2973 | const struct intel_plane_state *plane_state) | |
81255565 | 2974 | { |
6315b5d3 | 2975 | struct drm_i915_private *dev_priv = to_i915(primary->dev); |
a8d201af ML |
2976 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2977 | struct drm_framebuffer *fb = plane_state->base.fb; | |
81255565 | 2978 | int plane = intel_crtc->plane; |
54ea9da8 | 2979 | u32 linear_offset; |
81255565 | 2980 | u32 dspcntr; |
f0f59a00 | 2981 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2982 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
2983 | int x = plane_state->base.src.x1 >> 16; |
2984 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 2985 | |
f45651ba VS |
2986 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2987 | ||
fdd508a6 | 2988 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 2989 | |
6315b5d3 | 2990 | if (INTEL_GEN(dev_priv) < 4) { |
f45651ba VS |
2991 | if (intel_crtc->pipe == PIPE_B) |
2992 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2993 | ||
2994 | /* pipesrc and dspsize control the size that is scaled from, | |
2995 | * which should always be the user's requested size. | |
2996 | */ | |
2997 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2998 | ((crtc_state->pipe_src_h - 1) << 16) | |
2999 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 3000 | I915_WRITE(DSPPOS(plane), 0); |
920a14b2 | 3001 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
c14b0485 | 3002 | I915_WRITE(PRIMSIZE(plane), |
a8d201af ML |
3003 | ((crtc_state->pipe_src_h - 1) << 16) | |
3004 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
3005 | I915_WRITE(PRIMPOS(plane), 0); |
3006 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 3007 | } |
81255565 | 3008 | |
438b74a5 | 3009 | switch (fb->format->format) { |
57779d06 | 3010 | case DRM_FORMAT_C8: |
81255565 JB |
3011 | dspcntr |= DISPPLANE_8BPP; |
3012 | break; | |
57779d06 | 3013 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3014 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3015 | break; |
57779d06 VS |
3016 | case DRM_FORMAT_RGB565: |
3017 | dspcntr |= DISPPLANE_BGRX565; | |
3018 | break; | |
3019 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3020 | dspcntr |= DISPPLANE_BGRX888; |
3021 | break; | |
3022 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3023 | dspcntr |= DISPPLANE_RGBX888; |
3024 | break; | |
3025 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3026 | dspcntr |= DISPPLANE_BGRX101010; |
3027 | break; | |
3028 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3029 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3030 | break; |
3031 | default: | |
baba133a | 3032 | BUG(); |
81255565 | 3033 | } |
57779d06 | 3034 | |
72618ebf | 3035 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3036 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3037 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3038 | |
df0cd455 VS |
3039 | if (rotation & DRM_ROTATE_180) |
3040 | dspcntr |= DISPPLANE_ROTATE_180; | |
3041 | ||
4ea7be2b VS |
3042 | if (rotation & DRM_REFLECT_X) |
3043 | dspcntr |= DISPPLANE_MIRROR; | |
3044 | ||
9beb5fea | 3045 | if (IS_G4X(dev_priv)) |
de1aa629 VS |
3046 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
3047 | ||
2949056c | 3048 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
81255565 | 3049 | |
6315b5d3 | 3050 | if (INTEL_GEN(dev_priv) >= 4) |
c2c75131 | 3051 | intel_crtc->dspaddr_offset = |
2949056c | 3052 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
e506a0c6 | 3053 | |
f22aa143 | 3054 | if (rotation & DRM_ROTATE_180) { |
df0cd455 VS |
3055 | x += crtc_state->pipe_src_w - 1; |
3056 | y += crtc_state->pipe_src_h - 1; | |
4ea7be2b VS |
3057 | } else if (rotation & DRM_REFLECT_X) { |
3058 | x += crtc_state->pipe_src_w - 1; | |
48404c1e SJ |
3059 | } |
3060 | ||
2949056c | 3061 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3062 | |
6315b5d3 | 3063 | if (INTEL_GEN(dev_priv) < 4) |
6687c906 VS |
3064 | intel_crtc->dspaddr_offset = linear_offset; |
3065 | ||
2db3366b PZ |
3066 | intel_crtc->adjusted_x = x; |
3067 | intel_crtc->adjusted_y = y; | |
3068 | ||
48404c1e SJ |
3069 | I915_WRITE(reg, dspcntr); |
3070 | ||
01f2c773 | 3071 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
6315b5d3 | 3072 | if (INTEL_GEN(dev_priv) >= 4) { |
85ba7b7d | 3073 | I915_WRITE(DSPSURF(plane), |
be1e3415 | 3074 | intel_plane_ggtt_offset(plane_state) + |
6687c906 | 3075 | intel_crtc->dspaddr_offset); |
5eddb70b | 3076 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 3077 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
bfb81049 VS |
3078 | } else { |
3079 | I915_WRITE(DSPADDR(plane), | |
be1e3415 | 3080 | intel_plane_ggtt_offset(plane_state) + |
bfb81049 VS |
3081 | intel_crtc->dspaddr_offset); |
3082 | } | |
5eddb70b | 3083 | POSTING_READ(reg); |
17638cd6 JB |
3084 | } |
3085 | ||
a8d201af ML |
3086 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
3087 | struct drm_crtc *crtc) | |
17638cd6 JB |
3088 | { |
3089 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3090 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 3091 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 3092 | int plane = intel_crtc->plane; |
f45651ba | 3093 | |
a8d201af ML |
3094 | I915_WRITE(DSPCNTR(plane), 0); |
3095 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 3096 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
3097 | else |
3098 | I915_WRITE(DSPADDR(plane), 0); | |
3099 | POSTING_READ(DSPCNTR(plane)); | |
3100 | } | |
c9ba6fad | 3101 | |
a8d201af ML |
3102 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
3103 | const struct intel_crtc_state *crtc_state, | |
3104 | const struct intel_plane_state *plane_state) | |
3105 | { | |
3106 | struct drm_device *dev = primary->dev; | |
fac5e23e | 3107 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3108 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3109 | struct drm_framebuffer *fb = plane_state->base.fb; | |
a8d201af | 3110 | int plane = intel_crtc->plane; |
54ea9da8 | 3111 | u32 linear_offset; |
a8d201af ML |
3112 | u32 dspcntr; |
3113 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 3114 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3115 | int x = plane_state->base.src.x1 >> 16; |
3116 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3117 | |
f45651ba | 3118 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 3119 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 3120 | |
8652744b | 3121 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f45651ba | 3122 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
17638cd6 | 3123 | |
438b74a5 | 3124 | switch (fb->format->format) { |
57779d06 | 3125 | case DRM_FORMAT_C8: |
17638cd6 JB |
3126 | dspcntr |= DISPPLANE_8BPP; |
3127 | break; | |
57779d06 VS |
3128 | case DRM_FORMAT_RGB565: |
3129 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 3130 | break; |
57779d06 | 3131 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
3132 | dspcntr |= DISPPLANE_BGRX888; |
3133 | break; | |
3134 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3135 | dspcntr |= DISPPLANE_RGBX888; |
3136 | break; | |
3137 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3138 | dspcntr |= DISPPLANE_BGRX101010; |
3139 | break; | |
3140 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3141 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
3142 | break; |
3143 | default: | |
baba133a | 3144 | BUG(); |
17638cd6 JB |
3145 | } |
3146 | ||
bae781b2 | 3147 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
17638cd6 | 3148 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 3149 | |
df0cd455 VS |
3150 | if (rotation & DRM_ROTATE_180) |
3151 | dspcntr |= DISPPLANE_ROTATE_180; | |
3152 | ||
8652744b | 3153 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) |
1f5d76db | 3154 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 3155 | |
2949056c | 3156 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
6687c906 | 3157 | |
c2c75131 | 3158 | intel_crtc->dspaddr_offset = |
2949056c | 3159 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
6687c906 | 3160 | |
df0cd455 VS |
3161 | /* HSW+ does this automagically in hardware */ |
3162 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) && | |
3163 | rotation & DRM_ROTATE_180) { | |
3164 | x += crtc_state->pipe_src_w - 1; | |
3165 | y += crtc_state->pipe_src_h - 1; | |
48404c1e SJ |
3166 | } |
3167 | ||
2949056c | 3168 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3169 | |
2db3366b PZ |
3170 | intel_crtc->adjusted_x = x; |
3171 | intel_crtc->adjusted_y = y; | |
3172 | ||
48404c1e | 3173 | I915_WRITE(reg, dspcntr); |
17638cd6 | 3174 | |
01f2c773 | 3175 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d | 3176 | I915_WRITE(DSPSURF(plane), |
be1e3415 | 3177 | intel_plane_ggtt_offset(plane_state) + |
6687c906 | 3178 | intel_crtc->dspaddr_offset); |
8652744b | 3179 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
bc1c91eb DL |
3180 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
3181 | } else { | |
3182 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
3183 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
3184 | } | |
17638cd6 | 3185 | POSTING_READ(reg); |
17638cd6 JB |
3186 | } |
3187 | ||
7b49f948 VS |
3188 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
3189 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 3190 | { |
7b49f948 | 3191 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 3192 | return 64; |
7b49f948 VS |
3193 | } else { |
3194 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
3195 | ||
27ba3910 | 3196 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
3197 | } |
3198 | } | |
3199 | ||
e435d6e5 ML |
3200 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3201 | { | |
3202 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3203 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3204 | |
3205 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3206 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3207 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3208 | } |
3209 | ||
a1b2278e CK |
3210 | /* |
3211 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3212 | */ | |
0583236e | 3213 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3214 | { |
a1b2278e CK |
3215 | struct intel_crtc_scaler_state *scaler_state; |
3216 | int i; | |
3217 | ||
a1b2278e CK |
3218 | scaler_state = &intel_crtc->config->scaler_state; |
3219 | ||
3220 | /* loop through and disable scalers that aren't in use */ | |
3221 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3222 | if (!scaler_state->scalers[i].in_use) |
3223 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3224 | } |
3225 | } | |
3226 | ||
d2196774 VS |
3227 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3228 | unsigned int rotation) | |
3229 | { | |
3230 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
3231 | u32 stride = intel_fb_pitch(fb, plane, rotation); | |
3232 | ||
3233 | /* | |
3234 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3235 | * linear buffers or in number of tiles for tiled buffers. | |
3236 | */ | |
bd2ef25d | 3237 | if (drm_rotation_90_or_270(rotation)) { |
353c8598 | 3238 | int cpp = fb->format->cpp[plane]; |
d2196774 | 3239 | |
bae781b2 | 3240 | stride /= intel_tile_height(dev_priv, fb->modifier, cpp); |
d2196774 | 3241 | } else { |
bae781b2 | 3242 | stride /= intel_fb_stride_alignment(dev_priv, fb->modifier, |
438b74a5 | 3243 | fb->format->format); |
d2196774 VS |
3244 | } |
3245 | ||
3246 | return stride; | |
3247 | } | |
3248 | ||
6156a456 | 3249 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3250 | { |
6156a456 | 3251 | switch (pixel_format) { |
d161cf7a | 3252 | case DRM_FORMAT_C8: |
c34ce3d1 | 3253 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3254 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3255 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3256 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3257 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3258 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3259 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3260 | /* |
3261 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3262 | * to be already pre-multiplied. We need to add a knob (or a different | |
3263 | * DRM_FORMAT) for user-space to configure that. | |
3264 | */ | |
f75fb42a | 3265 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3266 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3267 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3268 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3269 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3270 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3271 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3272 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3273 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3274 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3275 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3276 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3277 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3278 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3279 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3280 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3281 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3282 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3283 | default: |
4249eeef | 3284 | MISSING_CASE(pixel_format); |
70d21f0e | 3285 | } |
8cfcba41 | 3286 | |
c34ce3d1 | 3287 | return 0; |
6156a456 | 3288 | } |
70d21f0e | 3289 | |
6156a456 CK |
3290 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3291 | { | |
6156a456 | 3292 | switch (fb_modifier) { |
30af77c4 | 3293 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3294 | break; |
30af77c4 | 3295 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3296 | return PLANE_CTL_TILED_X; |
b321803d | 3297 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3298 | return PLANE_CTL_TILED_Y; |
b321803d | 3299 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3300 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3301 | default: |
6156a456 | 3302 | MISSING_CASE(fb_modifier); |
70d21f0e | 3303 | } |
8cfcba41 | 3304 | |
c34ce3d1 | 3305 | return 0; |
6156a456 | 3306 | } |
70d21f0e | 3307 | |
6156a456 CK |
3308 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3309 | { | |
3b7a5119 | 3310 | switch (rotation) { |
31ad61e4 | 3311 | case DRM_ROTATE_0: |
6156a456 | 3312 | break; |
1e8df167 SJ |
3313 | /* |
3314 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3315 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3316 | */ | |
31ad61e4 | 3317 | case DRM_ROTATE_90: |
1e8df167 | 3318 | return PLANE_CTL_ROTATE_270; |
31ad61e4 | 3319 | case DRM_ROTATE_180: |
c34ce3d1 | 3320 | return PLANE_CTL_ROTATE_180; |
31ad61e4 | 3321 | case DRM_ROTATE_270: |
1e8df167 | 3322 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3323 | default: |
3324 | MISSING_CASE(rotation); | |
3325 | } | |
3326 | ||
c34ce3d1 | 3327 | return 0; |
6156a456 CK |
3328 | } |
3329 | ||
a8d201af ML |
3330 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3331 | const struct intel_crtc_state *crtc_state, | |
3332 | const struct intel_plane_state *plane_state) | |
6156a456 | 3333 | { |
a8d201af | 3334 | struct drm_device *dev = plane->dev; |
fac5e23e | 3335 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3336 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3337 | struct drm_framebuffer *fb = plane_state->base.fb; | |
8e816bb4 VS |
3338 | enum plane_id plane_id = to_intel_plane(plane)->id; |
3339 | enum pipe pipe = to_intel_plane(plane)->pipe; | |
d2196774 | 3340 | u32 plane_ctl; |
a8d201af | 3341 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3342 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3343 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3344 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3345 | int src_x = plane_state->main.x; |
3346 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3347 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3348 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3349 | int dst_x = plane_state->base.dst.x1; | |
3350 | int dst_y = plane_state->base.dst.y1; | |
3351 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3352 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
70d21f0e | 3353 | |
47f9ea8b ACO |
3354 | plane_ctl = PLANE_CTL_ENABLE; |
3355 | ||
3356 | if (IS_GEMINILAKE(dev_priv)) { | |
3357 | I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id), | |
3358 | PLANE_COLOR_PIPE_GAMMA_ENABLE | | |
3bb56da7 | 3359 | PLANE_COLOR_PIPE_CSC_ENABLE | |
47f9ea8b ACO |
3360 | PLANE_COLOR_PLANE_GAMMA_DISABLE); |
3361 | } else { | |
3362 | plane_ctl |= | |
3363 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3364 | PLANE_CTL_PIPE_CSC_ENABLE | | |
3365 | PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3366 | } | |
6156a456 | 3367 | |
438b74a5 | 3368 | plane_ctl |= skl_plane_ctl_format(fb->format->format); |
bae781b2 | 3369 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); |
6156a456 CK |
3370 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3371 | ||
6687c906 VS |
3372 | /* Sizes are 0 based */ |
3373 | src_w--; | |
3374 | src_h--; | |
3375 | dst_w--; | |
3376 | dst_h--; | |
3377 | ||
4c0b8a8b PZ |
3378 | intel_crtc->dspaddr_offset = surf_addr; |
3379 | ||
6687c906 VS |
3380 | intel_crtc->adjusted_x = src_x; |
3381 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3382 | |
8e816bb4 VS |
3383 | I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl); |
3384 | I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3385 | I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride); | |
3386 | I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
6156a456 CK |
3387 | |
3388 | if (scaler_id >= 0) { | |
3389 | uint32_t ps_ctrl = 0; | |
3390 | ||
3391 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3392 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 CK |
3393 | crtc_state->scaler_state.scalers[scaler_id].mode; |
3394 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3395 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3396 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3397 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
8e816bb4 | 3398 | I915_WRITE(PLANE_POS(pipe, plane_id), 0); |
6156a456 | 3399 | } else { |
8e816bb4 | 3400 | I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3401 | } |
3402 | ||
8e816bb4 | 3403 | I915_WRITE(PLANE_SURF(pipe, plane_id), |
be1e3415 | 3404 | intel_plane_ggtt_offset(plane_state) + surf_addr); |
70d21f0e | 3405 | |
8e816bb4 | 3406 | POSTING_READ(PLANE_SURF(pipe, plane_id)); |
70d21f0e DL |
3407 | } |
3408 | ||
a8d201af ML |
3409 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3410 | struct drm_crtc *crtc) | |
17638cd6 JB |
3411 | { |
3412 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3413 | struct drm_i915_private *dev_priv = to_i915(dev); |
8e816bb4 VS |
3414 | enum plane_id plane_id = to_intel_plane(primary)->id; |
3415 | enum pipe pipe = to_intel_plane(primary)->pipe; | |
62e0fb88 | 3416 | |
8e816bb4 VS |
3417 | I915_WRITE(PLANE_CTL(pipe, plane_id), 0); |
3418 | I915_WRITE(PLANE_SURF(pipe, plane_id), 0); | |
3419 | POSTING_READ(PLANE_SURF(pipe, plane_id)); | |
a8d201af | 3420 | } |
29b9bde6 | 3421 | |
a8d201af ML |
3422 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3423 | static int | |
3424 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3425 | int x, int y, enum mode_set_atomic state) | |
3426 | { | |
3427 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3428 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3429 | ||
3430 | return -ENODEV; | |
81255565 JB |
3431 | } |
3432 | ||
5a21b665 DV |
3433 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3434 | { | |
3435 | struct intel_crtc *crtc; | |
3436 | ||
91c8a326 | 3437 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3438 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3439 | } | |
3440 | ||
7514747d VS |
3441 | static void intel_update_primary_planes(struct drm_device *dev) |
3442 | { | |
7514747d | 3443 | struct drm_crtc *crtc; |
96a02917 | 3444 | |
70e1e0ec | 3445 | for_each_crtc(dev, crtc) { |
11c22da6 | 3446 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3447 | struct intel_plane_state *plane_state = |
3448 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3449 | |
936e71e3 | 3450 | if (plane_state->base.visible) |
a8d201af ML |
3451 | plane->update_plane(&plane->base, |
3452 | to_intel_crtc_state(crtc->state), | |
3453 | plane_state); | |
73974893 ML |
3454 | } |
3455 | } | |
3456 | ||
3457 | static int | |
3458 | __intel_display_resume(struct drm_device *dev, | |
3459 | struct drm_atomic_state *state) | |
3460 | { | |
3461 | struct drm_crtc_state *crtc_state; | |
3462 | struct drm_crtc *crtc; | |
3463 | int i, ret; | |
11c22da6 | 3464 | |
73974893 | 3465 | intel_modeset_setup_hw_state(dev); |
29b74b7f | 3466 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3467 | |
3468 | if (!state) | |
3469 | return 0; | |
3470 | ||
3471 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3472 | /* | |
3473 | * Force recalculation even if we restore | |
3474 | * current state. With fast modeset this may not result | |
3475 | * in a modeset when the state is compatible. | |
3476 | */ | |
3477 | crtc_state->mode_changed = true; | |
96a02917 | 3478 | } |
73974893 ML |
3479 | |
3480 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
602ae835 VS |
3481 | if (!HAS_GMCH_DISPLAY(to_i915(dev))) |
3482 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
73974893 ML |
3483 | |
3484 | ret = drm_atomic_commit(state); | |
3485 | ||
3486 | WARN_ON(ret == -EDEADLK); | |
3487 | return ret; | |
96a02917 VS |
3488 | } |
3489 | ||
4ac2ba2f VS |
3490 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3491 | { | |
ae98104b VS |
3492 | return intel_has_gpu_reset(dev_priv) && |
3493 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3494 | } |
3495 | ||
c033666a | 3496 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3497 | { |
73974893 ML |
3498 | struct drm_device *dev = &dev_priv->drm; |
3499 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3500 | struct drm_atomic_state *state; | |
3501 | int ret; | |
3502 | ||
73974893 ML |
3503 | /* |
3504 | * Need mode_config.mutex so that we don't | |
3505 | * trample ongoing ->detect() and whatnot. | |
3506 | */ | |
3507 | mutex_lock(&dev->mode_config.mutex); | |
3508 | drm_modeset_acquire_init(ctx, 0); | |
3509 | while (1) { | |
3510 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3511 | if (ret != -EDEADLK) | |
3512 | break; | |
3513 | ||
3514 | drm_modeset_backoff(ctx); | |
3515 | } | |
3516 | ||
3517 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3518 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3519 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3520 | return; |
3521 | ||
f98ce92f VS |
3522 | /* |
3523 | * Disabling the crtcs gracefully seems nicer. Also the | |
3524 | * g33 docs say we should at least disable all the planes. | |
3525 | */ | |
73974893 ML |
3526 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3527 | if (IS_ERR(state)) { | |
3528 | ret = PTR_ERR(state); | |
73974893 | 3529 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
1e5a15d6 | 3530 | return; |
73974893 ML |
3531 | } |
3532 | ||
3533 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3534 | if (ret) { | |
3535 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
1e5a15d6 ACO |
3536 | drm_atomic_state_put(state); |
3537 | return; | |
73974893 ML |
3538 | } |
3539 | ||
3540 | dev_priv->modeset_restore_state = state; | |
3541 | state->acquire_ctx = ctx; | |
7514747d VS |
3542 | } |
3543 | ||
c033666a | 3544 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3545 | { |
73974893 ML |
3546 | struct drm_device *dev = &dev_priv->drm; |
3547 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3548 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3549 | int ret; | |
3550 | ||
5a21b665 DV |
3551 | /* |
3552 | * Flips in the rings will be nuked by the reset, | |
3553 | * so complete all pending flips so that user space | |
3554 | * will get its events and not get stuck. | |
3555 | */ | |
3556 | intel_complete_page_flips(dev_priv); | |
3557 | ||
73974893 ML |
3558 | dev_priv->modeset_restore_state = NULL; |
3559 | ||
7514747d | 3560 | /* reset doesn't touch the display */ |
4ac2ba2f | 3561 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3562 | if (!state) { |
3563 | /* | |
3564 | * Flips in the rings have been nuked by the reset, | |
3565 | * so update the base address of all primary | |
3566 | * planes to the the last fb to make sure we're | |
3567 | * showing the correct fb after a reset. | |
3568 | * | |
3569 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3570 | * CS-based flips (which might get lost in gpu resets) any more. | |
3571 | */ | |
3572 | intel_update_primary_planes(dev); | |
3573 | } else { | |
3574 | ret = __intel_display_resume(dev, state); | |
3575 | if (ret) | |
3576 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3577 | } | |
73974893 ML |
3578 | } else { |
3579 | /* | |
3580 | * The display has been reset as well, | |
3581 | * so need a full re-initialization. | |
3582 | */ | |
3583 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3584 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3585 | |
51f59205 | 3586 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3587 | intel_modeset_init_hw(dev); |
7514747d | 3588 | |
73974893 ML |
3589 | spin_lock_irq(&dev_priv->irq_lock); |
3590 | if (dev_priv->display.hpd_irq_setup) | |
3591 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3592 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3593 | |
73974893 ML |
3594 | ret = __intel_display_resume(dev, state); |
3595 | if (ret) | |
3596 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3597 | |
73974893 ML |
3598 | intel_hpd_init(dev_priv); |
3599 | } | |
7514747d | 3600 | |
0853695c CW |
3601 | if (state) |
3602 | drm_atomic_state_put(state); | |
73974893 ML |
3603 | drm_modeset_drop_locks(ctx); |
3604 | drm_modeset_acquire_fini(ctx); | |
3605 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3606 | } |
3607 | ||
8af29b0c CW |
3608 | static bool abort_flip_on_reset(struct intel_crtc *crtc) |
3609 | { | |
3610 | struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; | |
3611 | ||
3612 | if (i915_reset_in_progress(error)) | |
3613 | return true; | |
3614 | ||
3615 | if (crtc->reset_count != i915_reset_count(error)) | |
3616 | return true; | |
3617 | ||
3618 | return false; | |
3619 | } | |
3620 | ||
7d5e3799 CW |
3621 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3622 | { | |
5a21b665 DV |
3623 | struct drm_device *dev = crtc->dev; |
3624 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5a21b665 DV |
3625 | bool pending; |
3626 | ||
8af29b0c | 3627 | if (abort_flip_on_reset(intel_crtc)) |
5a21b665 DV |
3628 | return false; |
3629 | ||
3630 | spin_lock_irq(&dev->event_lock); | |
3631 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3632 | spin_unlock_irq(&dev->event_lock); | |
3633 | ||
3634 | return pending; | |
7d5e3799 CW |
3635 | } |
3636 | ||
bfd16b2a ML |
3637 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3638 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3639 | { |
6315b5d3 | 3640 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3641 | struct intel_crtc_state *pipe_config = |
3642 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3643 | |
bfd16b2a ML |
3644 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3645 | crtc->base.mode = crtc->base.state->mode; | |
3646 | ||
3647 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3648 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3649 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3650 | |
3651 | /* | |
3652 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3653 | * that in compute_mode_changes we check the native mode (not the pfit | |
3654 | * mode) to see if we can flip rather than do a full mode set. In the | |
3655 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3656 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3657 | * sized surface. | |
e30e8f75 GP |
3658 | */ |
3659 | ||
e30e8f75 | 3660 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3661 | ((pipe_config->pipe_src_w - 1) << 16) | |
3662 | (pipe_config->pipe_src_h - 1)); | |
3663 | ||
3664 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3665 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3666 | skl_detach_scalers(crtc); |
3667 | ||
3668 | if (pipe_config->pch_pfit.enabled) | |
3669 | skylake_pfit_enable(crtc); | |
6e266956 | 3670 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3671 | if (pipe_config->pch_pfit.enabled) |
3672 | ironlake_pfit_enable(crtc); | |
3673 | else if (old_crtc_state->pch_pfit.enabled) | |
3674 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3675 | } |
e30e8f75 GP |
3676 | } |
3677 | ||
4cbe4b2b | 3678 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 3679 | { |
4cbe4b2b | 3680 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3681 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3682 | int pipe = crtc->pipe; |
f0f59a00 VS |
3683 | i915_reg_t reg; |
3684 | u32 temp; | |
5e84e1a4 ZW |
3685 | |
3686 | /* enable normal train */ | |
3687 | reg = FDI_TX_CTL(pipe); | |
3688 | temp = I915_READ(reg); | |
fd6b8f43 | 3689 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3690 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3691 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3692 | } else { |
3693 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3694 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3695 | } |
5e84e1a4 ZW |
3696 | I915_WRITE(reg, temp); |
3697 | ||
3698 | reg = FDI_RX_CTL(pipe); | |
3699 | temp = I915_READ(reg); | |
6e266956 | 3700 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3701 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3702 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3703 | } else { | |
3704 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3705 | temp |= FDI_LINK_TRAIN_NONE; | |
3706 | } | |
3707 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3708 | ||
3709 | /* wait one idle pattern time */ | |
3710 | POSTING_READ(reg); | |
3711 | udelay(1000); | |
357555c0 JB |
3712 | |
3713 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3714 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3715 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3716 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3717 | } |
3718 | ||
8db9d77b | 3719 | /* The FDI link training functions for ILK/Ibexpeak. */ |
dc4a1094 ACO |
3720 | static void ironlake_fdi_link_train(struct intel_crtc *crtc, |
3721 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3722 | { |
4cbe4b2b | 3723 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3724 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3725 | int pipe = crtc->pipe; |
f0f59a00 VS |
3726 | i915_reg_t reg; |
3727 | u32 temp, tries; | |
8db9d77b | 3728 | |
1c8562f6 | 3729 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3730 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3731 | |
e1a44743 AJ |
3732 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3733 | for train result */ | |
5eddb70b CW |
3734 | reg = FDI_RX_IMR(pipe); |
3735 | temp = I915_READ(reg); | |
e1a44743 AJ |
3736 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3737 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3738 | I915_WRITE(reg, temp); |
3739 | I915_READ(reg); | |
e1a44743 AJ |
3740 | udelay(150); |
3741 | ||
8db9d77b | 3742 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3743 | reg = FDI_TX_CTL(pipe); |
3744 | temp = I915_READ(reg); | |
627eb5a3 | 3745 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3746 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3747 | temp &= ~FDI_LINK_TRAIN_NONE; |
3748 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3749 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3750 | |
5eddb70b CW |
3751 | reg = FDI_RX_CTL(pipe); |
3752 | temp = I915_READ(reg); | |
8db9d77b ZW |
3753 | temp &= ~FDI_LINK_TRAIN_NONE; |
3754 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3755 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3756 | ||
3757 | POSTING_READ(reg); | |
8db9d77b ZW |
3758 | udelay(150); |
3759 | ||
5b2adf89 | 3760 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3761 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3762 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3763 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3764 | |
5eddb70b | 3765 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3766 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3767 | temp = I915_READ(reg); |
8db9d77b ZW |
3768 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3769 | ||
3770 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3771 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3772 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3773 | break; |
3774 | } | |
8db9d77b | 3775 | } |
e1a44743 | 3776 | if (tries == 5) |
5eddb70b | 3777 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3778 | |
3779 | /* Train 2 */ | |
5eddb70b CW |
3780 | reg = FDI_TX_CTL(pipe); |
3781 | temp = I915_READ(reg); | |
8db9d77b ZW |
3782 | temp &= ~FDI_LINK_TRAIN_NONE; |
3783 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3784 | I915_WRITE(reg, temp); |
8db9d77b | 3785 | |
5eddb70b CW |
3786 | reg = FDI_RX_CTL(pipe); |
3787 | temp = I915_READ(reg); | |
8db9d77b ZW |
3788 | temp &= ~FDI_LINK_TRAIN_NONE; |
3789 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3790 | I915_WRITE(reg, temp); |
8db9d77b | 3791 | |
5eddb70b CW |
3792 | POSTING_READ(reg); |
3793 | udelay(150); | |
8db9d77b | 3794 | |
5eddb70b | 3795 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3796 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3797 | temp = I915_READ(reg); |
8db9d77b ZW |
3798 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3799 | ||
3800 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3801 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3802 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3803 | break; | |
3804 | } | |
8db9d77b | 3805 | } |
e1a44743 | 3806 | if (tries == 5) |
5eddb70b | 3807 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3808 | |
3809 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3810 | |
8db9d77b ZW |
3811 | } |
3812 | ||
0206e353 | 3813 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3814 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3815 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3816 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3817 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3818 | }; | |
3819 | ||
3820 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
3821 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
3822 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3823 | { |
4cbe4b2b | 3824 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3825 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3826 | int pipe = crtc->pipe; |
f0f59a00 VS |
3827 | i915_reg_t reg; |
3828 | u32 temp, i, retry; | |
8db9d77b | 3829 | |
e1a44743 AJ |
3830 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3831 | for train result */ | |
5eddb70b CW |
3832 | reg = FDI_RX_IMR(pipe); |
3833 | temp = I915_READ(reg); | |
e1a44743 AJ |
3834 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3835 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3836 | I915_WRITE(reg, temp); |
3837 | ||
3838 | POSTING_READ(reg); | |
e1a44743 AJ |
3839 | udelay(150); |
3840 | ||
8db9d77b | 3841 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3842 | reg = FDI_TX_CTL(pipe); |
3843 | temp = I915_READ(reg); | |
627eb5a3 | 3844 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3845 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3846 | temp &= ~FDI_LINK_TRAIN_NONE; |
3847 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3848 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3849 | /* SNB-B */ | |
3850 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3851 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3852 | |
d74cf324 DV |
3853 | I915_WRITE(FDI_RX_MISC(pipe), |
3854 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3855 | ||
5eddb70b CW |
3856 | reg = FDI_RX_CTL(pipe); |
3857 | temp = I915_READ(reg); | |
6e266956 | 3858 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3859 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3860 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3861 | } else { | |
3862 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3863 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3864 | } | |
5eddb70b CW |
3865 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3866 | ||
3867 | POSTING_READ(reg); | |
8db9d77b ZW |
3868 | udelay(150); |
3869 | ||
0206e353 | 3870 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3871 | reg = FDI_TX_CTL(pipe); |
3872 | temp = I915_READ(reg); | |
8db9d77b ZW |
3873 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3874 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3875 | I915_WRITE(reg, temp); |
3876 | ||
3877 | POSTING_READ(reg); | |
8db9d77b ZW |
3878 | udelay(500); |
3879 | ||
fa37d39e SP |
3880 | for (retry = 0; retry < 5; retry++) { |
3881 | reg = FDI_RX_IIR(pipe); | |
3882 | temp = I915_READ(reg); | |
3883 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3884 | if (temp & FDI_RX_BIT_LOCK) { | |
3885 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3886 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3887 | break; | |
3888 | } | |
3889 | udelay(50); | |
8db9d77b | 3890 | } |
fa37d39e SP |
3891 | if (retry < 5) |
3892 | break; | |
8db9d77b ZW |
3893 | } |
3894 | if (i == 4) | |
5eddb70b | 3895 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3896 | |
3897 | /* Train 2 */ | |
5eddb70b CW |
3898 | reg = FDI_TX_CTL(pipe); |
3899 | temp = I915_READ(reg); | |
8db9d77b ZW |
3900 | temp &= ~FDI_LINK_TRAIN_NONE; |
3901 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3902 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3903 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3904 | /* SNB-B */ | |
3905 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3906 | } | |
5eddb70b | 3907 | I915_WRITE(reg, temp); |
8db9d77b | 3908 | |
5eddb70b CW |
3909 | reg = FDI_RX_CTL(pipe); |
3910 | temp = I915_READ(reg); | |
6e266956 | 3911 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3912 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3913 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3914 | } else { | |
3915 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3916 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3917 | } | |
5eddb70b CW |
3918 | I915_WRITE(reg, temp); |
3919 | ||
3920 | POSTING_READ(reg); | |
8db9d77b ZW |
3921 | udelay(150); |
3922 | ||
0206e353 | 3923 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3924 | reg = FDI_TX_CTL(pipe); |
3925 | temp = I915_READ(reg); | |
8db9d77b ZW |
3926 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3927 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3928 | I915_WRITE(reg, temp); |
3929 | ||
3930 | POSTING_READ(reg); | |
8db9d77b ZW |
3931 | udelay(500); |
3932 | ||
fa37d39e SP |
3933 | for (retry = 0; retry < 5; retry++) { |
3934 | reg = FDI_RX_IIR(pipe); | |
3935 | temp = I915_READ(reg); | |
3936 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3937 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3938 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3939 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3940 | break; | |
3941 | } | |
3942 | udelay(50); | |
8db9d77b | 3943 | } |
fa37d39e SP |
3944 | if (retry < 5) |
3945 | break; | |
8db9d77b ZW |
3946 | } |
3947 | if (i == 4) | |
5eddb70b | 3948 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3949 | |
3950 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3951 | } | |
3952 | ||
357555c0 | 3953 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
3954 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
3955 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 3956 | { |
4cbe4b2b | 3957 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3958 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3959 | int pipe = crtc->pipe; |
f0f59a00 VS |
3960 | i915_reg_t reg; |
3961 | u32 temp, i, j; | |
357555c0 JB |
3962 | |
3963 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3964 | for train result */ | |
3965 | reg = FDI_RX_IMR(pipe); | |
3966 | temp = I915_READ(reg); | |
3967 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3968 | temp &= ~FDI_RX_BIT_LOCK; | |
3969 | I915_WRITE(reg, temp); | |
3970 | ||
3971 | POSTING_READ(reg); | |
3972 | udelay(150); | |
3973 | ||
01a415fd DV |
3974 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3975 | I915_READ(FDI_RX_IIR(pipe))); | |
3976 | ||
139ccd3f JB |
3977 | /* Try each vswing and preemphasis setting twice before moving on */ |
3978 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3979 | /* disable first in case we need to retry */ | |
3980 | reg = FDI_TX_CTL(pipe); | |
3981 | temp = I915_READ(reg); | |
3982 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3983 | temp &= ~FDI_TX_ENABLE; | |
3984 | I915_WRITE(reg, temp); | |
357555c0 | 3985 | |
139ccd3f JB |
3986 | reg = FDI_RX_CTL(pipe); |
3987 | temp = I915_READ(reg); | |
3988 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3989 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3990 | temp &= ~FDI_RX_ENABLE; | |
3991 | I915_WRITE(reg, temp); | |
357555c0 | 3992 | |
139ccd3f | 3993 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3994 | reg = FDI_TX_CTL(pipe); |
3995 | temp = I915_READ(reg); | |
139ccd3f | 3996 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3997 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 3998 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3999 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4000 | temp |= snb_b_fdi_train_param[j/2]; |
4001 | temp |= FDI_COMPOSITE_SYNC; | |
4002 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4003 | |
139ccd3f JB |
4004 | I915_WRITE(FDI_RX_MISC(pipe), |
4005 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4006 | |
139ccd3f | 4007 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4008 | temp = I915_READ(reg); |
139ccd3f JB |
4009 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4010 | temp |= FDI_COMPOSITE_SYNC; | |
4011 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4012 | |
139ccd3f JB |
4013 | POSTING_READ(reg); |
4014 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4015 | |
139ccd3f JB |
4016 | for (i = 0; i < 4; i++) { |
4017 | reg = FDI_RX_IIR(pipe); | |
4018 | temp = I915_READ(reg); | |
4019 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4020 | |
139ccd3f JB |
4021 | if (temp & FDI_RX_BIT_LOCK || |
4022 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4023 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4024 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4025 | i); | |
4026 | break; | |
4027 | } | |
4028 | udelay(1); /* should be 0.5us */ | |
4029 | } | |
4030 | if (i == 4) { | |
4031 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4032 | continue; | |
4033 | } | |
357555c0 | 4034 | |
139ccd3f | 4035 | /* Train 2 */ |
357555c0 JB |
4036 | reg = FDI_TX_CTL(pipe); |
4037 | temp = I915_READ(reg); | |
139ccd3f JB |
4038 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4039 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4040 | I915_WRITE(reg, temp); | |
4041 | ||
4042 | reg = FDI_RX_CTL(pipe); | |
4043 | temp = I915_READ(reg); | |
4044 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4045 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4046 | I915_WRITE(reg, temp); |
4047 | ||
4048 | POSTING_READ(reg); | |
139ccd3f | 4049 | udelay(2); /* should be 1.5us */ |
357555c0 | 4050 | |
139ccd3f JB |
4051 | for (i = 0; i < 4; i++) { |
4052 | reg = FDI_RX_IIR(pipe); | |
4053 | temp = I915_READ(reg); | |
4054 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4055 | |
139ccd3f JB |
4056 | if (temp & FDI_RX_SYMBOL_LOCK || |
4057 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4058 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4059 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4060 | i); | |
4061 | goto train_done; | |
4062 | } | |
4063 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4064 | } |
139ccd3f JB |
4065 | if (i == 4) |
4066 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4067 | } |
357555c0 | 4068 | |
139ccd3f | 4069 | train_done: |
357555c0 JB |
4070 | DRM_DEBUG_KMS("FDI train done.\n"); |
4071 | } | |
4072 | ||
88cefb6c | 4073 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4074 | { |
88cefb6c | 4075 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4076 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4077 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4078 | i915_reg_t reg; |
4079 | u32 temp; | |
c64e311e | 4080 | |
c98e9dcf | 4081 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4082 | reg = FDI_RX_CTL(pipe); |
4083 | temp = I915_READ(reg); | |
627eb5a3 | 4084 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4085 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4086 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4087 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4088 | ||
4089 | POSTING_READ(reg); | |
c98e9dcf JB |
4090 | udelay(200); |
4091 | ||
4092 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4093 | temp = I915_READ(reg); |
4094 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4095 | ||
4096 | POSTING_READ(reg); | |
c98e9dcf JB |
4097 | udelay(200); |
4098 | ||
20749730 PZ |
4099 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4100 | reg = FDI_TX_CTL(pipe); | |
4101 | temp = I915_READ(reg); | |
4102 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4103 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4104 | |
20749730 PZ |
4105 | POSTING_READ(reg); |
4106 | udelay(100); | |
6be4a607 | 4107 | } |
0e23b99d JB |
4108 | } |
4109 | ||
88cefb6c DV |
4110 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4111 | { | |
4112 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4113 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4114 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4115 | i915_reg_t reg; |
4116 | u32 temp; | |
88cefb6c DV |
4117 | |
4118 | /* Switch from PCDclk to Rawclk */ | |
4119 | reg = FDI_RX_CTL(pipe); | |
4120 | temp = I915_READ(reg); | |
4121 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4122 | ||
4123 | /* Disable CPU FDI TX PLL */ | |
4124 | reg = FDI_TX_CTL(pipe); | |
4125 | temp = I915_READ(reg); | |
4126 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4127 | ||
4128 | POSTING_READ(reg); | |
4129 | udelay(100); | |
4130 | ||
4131 | reg = FDI_RX_CTL(pipe); | |
4132 | temp = I915_READ(reg); | |
4133 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4134 | ||
4135 | /* Wait for the clocks to turn off. */ | |
4136 | POSTING_READ(reg); | |
4137 | udelay(100); | |
4138 | } | |
4139 | ||
0fc932b8 JB |
4140 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4141 | { | |
4142 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4143 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4144 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4145 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4146 | i915_reg_t reg; |
4147 | u32 temp; | |
0fc932b8 JB |
4148 | |
4149 | /* disable CPU FDI tx and PCH FDI rx */ | |
4150 | reg = FDI_TX_CTL(pipe); | |
4151 | temp = I915_READ(reg); | |
4152 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4153 | POSTING_READ(reg); | |
4154 | ||
4155 | reg = FDI_RX_CTL(pipe); | |
4156 | temp = I915_READ(reg); | |
4157 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4158 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4159 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4160 | ||
4161 | POSTING_READ(reg); | |
4162 | udelay(100); | |
4163 | ||
4164 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4165 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4166 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4167 | |
4168 | /* still set train pattern 1 */ | |
4169 | reg = FDI_TX_CTL(pipe); | |
4170 | temp = I915_READ(reg); | |
4171 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4172 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4173 | I915_WRITE(reg, temp); | |
4174 | ||
4175 | reg = FDI_RX_CTL(pipe); | |
4176 | temp = I915_READ(reg); | |
6e266956 | 4177 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4178 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4179 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4180 | } else { | |
4181 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4182 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4183 | } | |
4184 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4185 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4186 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4187 | I915_WRITE(reg, temp); |
4188 | ||
4189 | POSTING_READ(reg); | |
4190 | udelay(100); | |
4191 | } | |
4192 | ||
49d73912 | 4193 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 CW |
4194 | { |
4195 | struct intel_crtc *crtc; | |
4196 | ||
4197 | /* Note that we don't need to be called with mode_config.lock here | |
4198 | * as our list of CRTC objects is static for the lifetime of the | |
4199 | * device and so cannot disappear as we iterate. Similarly, we can | |
4200 | * happily treat the predicates as racy, atomic checks as userspace | |
4201 | * cannot claim and pin a new fb without at least acquring the | |
4202 | * struct_mutex and so serialising with us. | |
4203 | */ | |
49d73912 | 4204 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
5dce5b93 CW |
4205 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4206 | continue; | |
4207 | ||
5a21b665 | 4208 | if (crtc->flip_work) |
0f0f74bc | 4209 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
5dce5b93 CW |
4210 | |
4211 | return true; | |
4212 | } | |
4213 | ||
4214 | return false; | |
4215 | } | |
4216 | ||
5a21b665 | 4217 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4218 | { |
4219 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4220 | struct intel_flip_work *work = intel_crtc->flip_work; |
4221 | ||
4222 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4223 | |
4224 | if (work->event) | |
560ce1dc | 4225 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4226 | |
4227 | drm_crtc_vblank_put(&intel_crtc->base); | |
4228 | ||
5a21b665 | 4229 | wake_up_all(&dev_priv->pending_flip_queue); |
5a21b665 DV |
4230 | trace_i915_flip_complete(intel_crtc->plane, |
4231 | work->pending_flip_obj); | |
05c41f92 AR |
4232 | |
4233 | queue_work(dev_priv->wq, &work->unpin_work); | |
d6bbafa1 CW |
4234 | } |
4235 | ||
5008e874 | 4236 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4237 | { |
0f91128d | 4238 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4239 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4240 | long ret; |
e6c3a2a6 | 4241 | |
2c10d571 | 4242 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4243 | |
4244 | ret = wait_event_interruptible_timeout( | |
4245 | dev_priv->pending_flip_queue, | |
4246 | !intel_crtc_has_pending_flip(crtc), | |
4247 | 60*HZ); | |
4248 | ||
4249 | if (ret < 0) | |
4250 | return ret; | |
4251 | ||
5a21b665 DV |
4252 | if (ret == 0) { |
4253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4254 | struct intel_flip_work *work; | |
4255 | ||
4256 | spin_lock_irq(&dev->event_lock); | |
4257 | work = intel_crtc->flip_work; | |
4258 | if (work && !is_mmio_work(work)) { | |
4259 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4260 | page_flip_completed(intel_crtc); | |
4261 | } | |
4262 | spin_unlock_irq(&dev->event_lock); | |
4263 | } | |
5bb61643 | 4264 | |
5008e874 | 4265 | return 0; |
e6c3a2a6 CW |
4266 | } |
4267 | ||
b7076546 | 4268 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4269 | { |
4270 | u32 temp; | |
4271 | ||
4272 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4273 | ||
4274 | mutex_lock(&dev_priv->sb_lock); | |
4275 | ||
4276 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4277 | temp |= SBI_SSCCTL_DISABLE; | |
4278 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4279 | ||
4280 | mutex_unlock(&dev_priv->sb_lock); | |
4281 | } | |
4282 | ||
e615efe4 | 4283 | /* Program iCLKIP clock to the desired frequency */ |
0dcdc382 | 4284 | static void lpt_program_iclkip(struct intel_crtc *crtc) |
e615efe4 | 4285 | { |
0dcdc382 ACO |
4286 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4287 | int clock = crtc->config->base.adjusted_mode.crtc_clock; | |
e615efe4 ED |
4288 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4289 | u32 temp; | |
4290 | ||
060f02d8 | 4291 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4292 | |
64b46a06 VS |
4293 | /* The iCLK virtual clock root frequency is in MHz, |
4294 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4295 | * divisors, it is necessary to divide one by another, so we | |
4296 | * convert the virtual clock precision to KHz here for higher | |
4297 | * precision. | |
4298 | */ | |
4299 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4300 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4301 | u32 iclk_pi_range = 64; | |
64b46a06 | 4302 | u32 desired_divisor; |
e615efe4 | 4303 | |
64b46a06 VS |
4304 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4305 | clock << auxdiv); | |
4306 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4307 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4308 | |
64b46a06 VS |
4309 | /* |
4310 | * Near 20MHz is a corner case which is | |
4311 | * out of range for the 7-bit divisor | |
4312 | */ | |
4313 | if (divsel <= 0x7f) | |
4314 | break; | |
e615efe4 ED |
4315 | } |
4316 | ||
4317 | /* This should not happen with any sane values */ | |
4318 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4319 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4320 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4321 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4322 | ||
4323 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4324 | clock, |
e615efe4 ED |
4325 | auxdiv, |
4326 | divsel, | |
4327 | phasedir, | |
4328 | phaseinc); | |
4329 | ||
060f02d8 VS |
4330 | mutex_lock(&dev_priv->sb_lock); |
4331 | ||
e615efe4 | 4332 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4333 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4334 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4335 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4336 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4337 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4338 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4339 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4340 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4341 | |
4342 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4343 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4344 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4345 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4346 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4347 | |
4348 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4349 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4350 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4351 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4352 | |
060f02d8 VS |
4353 | mutex_unlock(&dev_priv->sb_lock); |
4354 | ||
e615efe4 ED |
4355 | /* Wait for initialization time */ |
4356 | udelay(24); | |
4357 | ||
4358 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4359 | } | |
4360 | ||
8802e5b6 VS |
4361 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4362 | { | |
4363 | u32 divsel, phaseinc, auxdiv; | |
4364 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4365 | u32 iclk_pi_range = 64; | |
4366 | u32 desired_divisor; | |
4367 | u32 temp; | |
4368 | ||
4369 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4370 | return 0; | |
4371 | ||
4372 | mutex_lock(&dev_priv->sb_lock); | |
4373 | ||
4374 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4375 | if (temp & SBI_SSCCTL_DISABLE) { | |
4376 | mutex_unlock(&dev_priv->sb_lock); | |
4377 | return 0; | |
4378 | } | |
4379 | ||
4380 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4381 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4382 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4383 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4384 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4385 | ||
4386 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4387 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4388 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4389 | ||
4390 | mutex_unlock(&dev_priv->sb_lock); | |
4391 | ||
4392 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4393 | ||
4394 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4395 | desired_divisor << auxdiv); | |
4396 | } | |
4397 | ||
275f01b2 DV |
4398 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4399 | enum pipe pch_transcoder) | |
4400 | { | |
4401 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4402 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4403 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4404 | |
4405 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4406 | I915_READ(HTOTAL(cpu_transcoder))); | |
4407 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4408 | I915_READ(HBLANK(cpu_transcoder))); | |
4409 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4410 | I915_READ(HSYNC(cpu_transcoder))); | |
4411 | ||
4412 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4413 | I915_READ(VTOTAL(cpu_transcoder))); | |
4414 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4415 | I915_READ(VBLANK(cpu_transcoder))); | |
4416 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4417 | I915_READ(VSYNC(cpu_transcoder))); | |
4418 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4419 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4420 | } | |
4421 | ||
003632d9 | 4422 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4423 | { |
fac5e23e | 4424 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4425 | uint32_t temp; |
4426 | ||
4427 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4428 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4429 | return; |
4430 | ||
4431 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4432 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4433 | ||
003632d9 ACO |
4434 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4435 | if (enable) | |
4436 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4437 | ||
4438 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4439 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4440 | POSTING_READ(SOUTH_CHICKEN1); | |
4441 | } | |
4442 | ||
4443 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4444 | { | |
4445 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4446 | |
4447 | switch (intel_crtc->pipe) { | |
4448 | case PIPE_A: | |
4449 | break; | |
4450 | case PIPE_B: | |
6e3c9717 | 4451 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4452 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4453 | else |
003632d9 | 4454 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4455 | |
4456 | break; | |
4457 | case PIPE_C: | |
003632d9 | 4458 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4459 | |
4460 | break; | |
4461 | default: | |
4462 | BUG(); | |
4463 | } | |
4464 | } | |
4465 | ||
c48b5305 VS |
4466 | /* Return which DP Port should be selected for Transcoder DP control */ |
4467 | static enum port | |
4cbe4b2b | 4468 | intel_trans_dp_port_sel(struct intel_crtc *crtc) |
c48b5305 | 4469 | { |
4cbe4b2b | 4470 | struct drm_device *dev = crtc->base.dev; |
c48b5305 VS |
4471 | struct intel_encoder *encoder; |
4472 | ||
4cbe4b2b | 4473 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
cca0502b | 4474 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4475 | encoder->type == INTEL_OUTPUT_EDP) |
4476 | return enc_to_dig_port(&encoder->base)->port; | |
4477 | } | |
4478 | ||
4479 | return -1; | |
4480 | } | |
4481 | ||
f67a559d JB |
4482 | /* |
4483 | * Enable PCH resources required for PCH ports: | |
4484 | * - PCH PLLs | |
4485 | * - FDI training & RX/TX | |
4486 | * - update transcoder timings | |
4487 | * - DP transcoding bits | |
4488 | * - transcoder | |
4489 | */ | |
2ce42273 | 4490 | static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) |
0e23b99d | 4491 | { |
2ce42273 | 4492 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
4cbe4b2b | 4493 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4494 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4495 | int pipe = crtc->pipe; |
f0f59a00 | 4496 | u32 temp; |
2c07245f | 4497 | |
ab9412ba | 4498 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4499 | |
fd6b8f43 | 4500 | if (IS_IVYBRIDGE(dev_priv)) |
4cbe4b2b | 4501 | ivybridge_update_fdi_bc_bifurcation(crtc); |
1fbc0d78 | 4502 | |
cd986abb DV |
4503 | /* Write the TU size bits before fdi link training, so that error |
4504 | * detection works. */ | |
4505 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4506 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4507 | ||
c98e9dcf | 4508 | /* For PCH output, training FDI link */ |
dc4a1094 | 4509 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 4510 | |
3ad8a208 DV |
4511 | /* We need to program the right clock selection before writing the pixel |
4512 | * mutliplier into the DPLL. */ | |
6e266956 | 4513 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4514 | u32 sel; |
4b645f14 | 4515 | |
c98e9dcf | 4516 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4517 | temp |= TRANS_DPLL_ENABLE(pipe); |
4518 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 4519 | if (crtc_state->shared_dpll == |
8106ddbd | 4520 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
4521 | temp |= sel; |
4522 | else | |
4523 | temp &= ~sel; | |
c98e9dcf | 4524 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4525 | } |
5eddb70b | 4526 | |
3ad8a208 DV |
4527 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4528 | * transcoder, and we actually should do this to not upset any PCH | |
4529 | * transcoder that already use the clock when we share it. | |
4530 | * | |
4531 | * Note that enable_shared_dpll tries to do the right thing, but | |
4532 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4533 | * the right LVDS enable sequence. */ | |
4cbe4b2b | 4534 | intel_enable_shared_dpll(crtc); |
3ad8a208 | 4535 | |
d9b6cb56 JB |
4536 | /* set transcoder timing, panel must allow it */ |
4537 | assert_panel_unlocked(dev_priv, pipe); | |
4cbe4b2b | 4538 | ironlake_pch_transcoder_set_timings(crtc, pipe); |
8db9d77b | 4539 | |
303b81e0 | 4540 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4541 | |
c98e9dcf | 4542 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 4543 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 4544 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 4545 | const struct drm_display_mode *adjusted_mode = |
2ce42273 | 4546 | &crtc_state->base.adjusted_mode; |
dfd07d72 | 4547 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4548 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4549 | temp = I915_READ(reg); |
4550 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4551 | TRANS_DP_SYNC_MASK | |
4552 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4553 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4554 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4555 | |
9c4edaee | 4556 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4557 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4558 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4559 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4560 | |
4561 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4562 | case PORT_B: |
5eddb70b | 4563 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4564 | break; |
c48b5305 | 4565 | case PORT_C: |
5eddb70b | 4566 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4567 | break; |
c48b5305 | 4568 | case PORT_D: |
5eddb70b | 4569 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4570 | break; |
4571 | default: | |
e95d41e1 | 4572 | BUG(); |
32f9d658 | 4573 | } |
2c07245f | 4574 | |
5eddb70b | 4575 | I915_WRITE(reg, temp); |
6be4a607 | 4576 | } |
b52eb4dc | 4577 | |
b8a4f404 | 4578 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4579 | } |
4580 | ||
2ce42273 | 4581 | static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 4582 | { |
2ce42273 | 4583 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
0dcdc382 | 4584 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 4585 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 4586 | |
ab9412ba | 4587 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4588 | |
8c52b5e8 | 4589 | lpt_program_iclkip(crtc); |
1507e5bd | 4590 | |
0540e488 | 4591 | /* Set transcoder timing. */ |
0dcdc382 | 4592 | ironlake_pch_transcoder_set_timings(crtc, PIPE_A); |
1507e5bd | 4593 | |
937bb610 | 4594 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4595 | } |
4596 | ||
a1520318 | 4597 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4598 | { |
fac5e23e | 4599 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4600 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4601 | u32 temp; |
4602 | ||
4603 | temp = I915_READ(dslreg); | |
4604 | udelay(500); | |
4605 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4606 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4607 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4608 | } |
4609 | } | |
4610 | ||
86adf9d7 ML |
4611 | static int |
4612 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4613 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4614 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4615 | { |
86adf9d7 ML |
4616 | struct intel_crtc_scaler_state *scaler_state = |
4617 | &crtc_state->scaler_state; | |
4618 | struct intel_crtc *intel_crtc = | |
4619 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4620 | int need_scaling; |
6156a456 | 4621 | |
bd2ef25d | 4622 | need_scaling = drm_rotation_90_or_270(rotation) ? |
6156a456 CK |
4623 | (src_h != dst_w || src_w != dst_h): |
4624 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4625 | |
4626 | /* | |
4627 | * if plane is being disabled or scaler is no more required or force detach | |
4628 | * - free scaler binded to this plane/crtc | |
4629 | * - in order to do this, update crtc->scaler_usage | |
4630 | * | |
4631 | * Here scaler state in crtc_state is set free so that | |
4632 | * scaler can be assigned to other user. Actual register | |
4633 | * update to free the scaler is done in plane/panel-fit programming. | |
4634 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4635 | */ | |
86adf9d7 | 4636 | if (force_detach || !need_scaling) { |
a1b2278e | 4637 | if (*scaler_id >= 0) { |
86adf9d7 | 4638 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4639 | scaler_state->scalers[*scaler_id].in_use = 0; |
4640 | ||
86adf9d7 ML |
4641 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4642 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4643 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4644 | scaler_state->scaler_users); |
4645 | *scaler_id = -1; | |
4646 | } | |
4647 | return 0; | |
4648 | } | |
4649 | ||
4650 | /* range checks */ | |
4651 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4652 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4653 | ||
4654 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4655 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4656 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4657 | "size is out of scaler range\n", |
86adf9d7 | 4658 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4659 | return -EINVAL; |
4660 | } | |
4661 | ||
86adf9d7 ML |
4662 | /* mark this plane as a scaler user in crtc_state */ |
4663 | scaler_state->scaler_users |= (1 << scaler_user); | |
4664 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4665 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4666 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4667 | scaler_state->scaler_users); | |
4668 | ||
4669 | return 0; | |
4670 | } | |
4671 | ||
4672 | /** | |
4673 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4674 | * | |
4675 | * @state: crtc's scaler state | |
86adf9d7 ML |
4676 | * |
4677 | * Return | |
4678 | * 0 - scaler_usage updated successfully | |
4679 | * error - requested scaling cannot be supported or other error condition | |
4680 | */ | |
e435d6e5 | 4681 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4682 | { |
7c5f93b0 | 4683 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4684 | |
e435d6e5 | 4685 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
31ad61e4 | 4686 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
86adf9d7 | 4687 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4688 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4689 | } |
4690 | ||
4691 | /** | |
4692 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4693 | * | |
4694 | * @state: crtc's scaler state | |
86adf9d7 ML |
4695 | * @plane_state: atomic plane state to update |
4696 | * | |
4697 | * Return | |
4698 | * 0 - scaler_usage updated successfully | |
4699 | * error - requested scaling cannot be supported or other error condition | |
4700 | */ | |
da20eabd ML |
4701 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4702 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4703 | { |
4704 | ||
da20eabd ML |
4705 | struct intel_plane *intel_plane = |
4706 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4707 | struct drm_framebuffer *fb = plane_state->base.fb; |
4708 | int ret; | |
4709 | ||
936e71e3 | 4710 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4711 | |
86adf9d7 ML |
4712 | ret = skl_update_scaler(crtc_state, force_detach, |
4713 | drm_plane_index(&intel_plane->base), | |
4714 | &plane_state->scaler_id, | |
4715 | plane_state->base.rotation, | |
936e71e3 VS |
4716 | drm_rect_width(&plane_state->base.src) >> 16, |
4717 | drm_rect_height(&plane_state->base.src) >> 16, | |
4718 | drm_rect_width(&plane_state->base.dst), | |
4719 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4720 | |
4721 | if (ret || plane_state->scaler_id < 0) | |
4722 | return ret; | |
4723 | ||
a1b2278e | 4724 | /* check colorkey */ |
818ed961 | 4725 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4726 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4727 | intel_plane->base.base.id, | |
4728 | intel_plane->base.name); | |
a1b2278e CK |
4729 | return -EINVAL; |
4730 | } | |
4731 | ||
4732 | /* Check src format */ | |
438b74a5 | 4733 | switch (fb->format->format) { |
86adf9d7 ML |
4734 | case DRM_FORMAT_RGB565: |
4735 | case DRM_FORMAT_XBGR8888: | |
4736 | case DRM_FORMAT_XRGB8888: | |
4737 | case DRM_FORMAT_ABGR8888: | |
4738 | case DRM_FORMAT_ARGB8888: | |
4739 | case DRM_FORMAT_XRGB2101010: | |
4740 | case DRM_FORMAT_XBGR2101010: | |
4741 | case DRM_FORMAT_YUYV: | |
4742 | case DRM_FORMAT_YVYU: | |
4743 | case DRM_FORMAT_UYVY: | |
4744 | case DRM_FORMAT_VYUY: | |
4745 | break; | |
4746 | default: | |
72660ce0 VS |
4747 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4748 | intel_plane->base.base.id, intel_plane->base.name, | |
438b74a5 | 4749 | fb->base.id, fb->format->format); |
86adf9d7 | 4750 | return -EINVAL; |
a1b2278e CK |
4751 | } |
4752 | ||
a1b2278e CK |
4753 | return 0; |
4754 | } | |
4755 | ||
e435d6e5 ML |
4756 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4757 | { | |
4758 | int i; | |
4759 | ||
4760 | for (i = 0; i < crtc->num_scalers; i++) | |
4761 | skl_detach_scaler(crtc, i); | |
4762 | } | |
4763 | ||
4764 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4765 | { |
4766 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4767 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4768 | int pipe = crtc->pipe; |
a1b2278e CK |
4769 | struct intel_crtc_scaler_state *scaler_state = |
4770 | &crtc->config->scaler_state; | |
4771 | ||
4772 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4773 | ||
6e3c9717 | 4774 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4775 | int id; |
4776 | ||
4777 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4778 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4779 | return; | |
4780 | } | |
4781 | ||
4782 | id = scaler_state->scaler_id; | |
4783 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4784 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4785 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4786 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4787 | ||
4788 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4789 | } |
4790 | } | |
4791 | ||
b074cec8 JB |
4792 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4793 | { | |
4794 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4795 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4796 | int pipe = crtc->pipe; |
4797 | ||
6e3c9717 | 4798 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4799 | /* Force use of hard-coded filter coefficients |
4800 | * as some pre-programmed values are broken, | |
4801 | * e.g. x201. | |
4802 | */ | |
fd6b8f43 | 4803 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4804 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4805 | PF_PIPE_SEL_IVB(pipe)); | |
4806 | else | |
4807 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4808 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4809 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4810 | } |
4811 | } | |
4812 | ||
20bc8673 | 4813 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4814 | { |
cea165c3 | 4815 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4816 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4817 | |
6e3c9717 | 4818 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4819 | return; |
4820 | ||
307e4498 ML |
4821 | /* |
4822 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4823 | * This function is called from post_plane_update, which is run after | |
4824 | * a vblank wait. | |
4825 | */ | |
cea165c3 | 4826 | |
d77e4531 | 4827 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4828 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4829 | mutex_lock(&dev_priv->rps.hw_lock); |
4830 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4831 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4832 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4833 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4834 | * mailbox." Moreover, the mailbox may return a bogus state, |
4835 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4836 | */ |
4837 | } else { | |
4838 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4839 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4840 | * is essentially intel_wait_for_vblank. If we don't have this | |
4841 | * and don't wait for vblanks until the end of crtc_enable, then | |
4842 | * the HW state readout code will complain that the expected | |
4843 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4844 | if (intel_wait_for_register(dev_priv, |
4845 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4846 | 50)) | |
2a114cc1 BW |
4847 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4848 | } | |
d77e4531 PZ |
4849 | } |
4850 | ||
20bc8673 | 4851 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4852 | { |
4853 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4854 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4855 | |
6e3c9717 | 4856 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4857 | return; |
4858 | ||
4859 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4860 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4861 | mutex_lock(&dev_priv->rps.hw_lock); |
4862 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4863 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4864 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4865 | if (intel_wait_for_register(dev_priv, |
4866 | IPS_CTL, IPS_ENABLE, 0, | |
4867 | 42)) | |
23d0b130 | 4868 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4869 | } else { |
2a114cc1 | 4870 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4871 | POSTING_READ(IPS_CTL); |
4872 | } | |
d77e4531 PZ |
4873 | |
4874 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4875 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4876 | } |
4877 | ||
7cac945f | 4878 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4879 | { |
7cac945f | 4880 | if (intel_crtc->overlay) { |
d3eedb1a | 4881 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4882 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4883 | |
4884 | mutex_lock(&dev->struct_mutex); | |
4885 | dev_priv->mm.interruptible = false; | |
4886 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4887 | dev_priv->mm.interruptible = true; | |
4888 | mutex_unlock(&dev->struct_mutex); | |
4889 | } | |
4890 | ||
4891 | /* Let userspace switch the overlay on again. In most cases userspace | |
4892 | * has to recompute where to put it anyway. | |
4893 | */ | |
4894 | } | |
4895 | ||
87d4300a ML |
4896 | /** |
4897 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4898 | * @crtc: the CRTC whose primary plane was just enabled | |
4899 | * | |
4900 | * Performs potentially sleeping operations that must be done after the primary | |
4901 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4902 | * called due to an explicit primary plane update, or due to an implicit | |
4903 | * re-enable that is caused when a sprite plane is updated to no longer | |
4904 | * completely hide the primary plane. | |
4905 | */ | |
4906 | static void | |
4907 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4908 | { |
4909 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4910 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4911 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4912 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4913 | |
87d4300a ML |
4914 | /* |
4915 | * FIXME IPS should be fine as long as one plane is | |
4916 | * enabled, but in practice it seems to have problems | |
4917 | * when going from primary only to sprite only and vice | |
4918 | * versa. | |
4919 | */ | |
a5c4d7bc VS |
4920 | hsw_enable_ips(intel_crtc); |
4921 | ||
f99d7069 | 4922 | /* |
87d4300a ML |
4923 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4924 | * So don't enable underrun reporting before at least some planes | |
4925 | * are enabled. | |
4926 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4927 | * but leave the pipe running. | |
f99d7069 | 4928 | */ |
5db94019 | 4929 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4930 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4931 | ||
aca7b684 VS |
4932 | /* Underruns don't always raise interrupts, so check manually. */ |
4933 | intel_check_cpu_fifo_underruns(dev_priv); | |
4934 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4935 | } |
4936 | ||
2622a081 | 4937 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4938 | static void |
4939 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4940 | { |
4941 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4942 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4943 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4944 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4945 | |
87d4300a ML |
4946 | /* |
4947 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4948 | * So diasble underrun reporting before all the planes get disabled. | |
4949 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4950 | * but leave the pipe running. | |
4951 | */ | |
5db94019 | 4952 | if (IS_GEN2(dev_priv)) |
87d4300a | 4953 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 4954 | |
2622a081 VS |
4955 | /* |
4956 | * FIXME IPS should be fine as long as one plane is | |
4957 | * enabled, but in practice it seems to have problems | |
4958 | * when going from primary only to sprite only and vice | |
4959 | * versa. | |
4960 | */ | |
4961 | hsw_disable_ips(intel_crtc); | |
4962 | } | |
4963 | ||
4964 | /* FIXME get rid of this and use pre_plane_update */ | |
4965 | static void | |
4966 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4967 | { | |
4968 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4969 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4971 | int pipe = intel_crtc->pipe; | |
4972 | ||
4973 | intel_pre_disable_primary(crtc); | |
4974 | ||
87d4300a ML |
4975 | /* |
4976 | * Vblank time updates from the shadow to live plane control register | |
4977 | * are blocked if the memory self-refresh mode is active at that | |
4978 | * moment. So to make sure the plane gets truly disabled, disable | |
4979 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4980 | * will be checked/applied by the HW only at the next frame start | |
4981 | * event which is after the vblank start event, so we need to have a | |
4982 | * wait-for-vblank between disabling the plane and the pipe. | |
4983 | */ | |
11a85d6a VS |
4984 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4985 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 4986 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
4987 | } |
4988 | ||
5a21b665 DV |
4989 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4990 | { | |
4991 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4992 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4993 | struct intel_crtc_state *pipe_config = | |
4994 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
4995 | struct drm_plane *primary = crtc->base.primary; |
4996 | struct drm_plane_state *old_pri_state = | |
4997 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4998 | ||
5748b6a1 | 4999 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 | 5000 | |
5a21b665 | 5001 | if (pipe_config->update_wm_post && pipe_config->base.active) |
432081bc | 5002 | intel_update_watermarks(crtc); |
5a21b665 DV |
5003 | |
5004 | if (old_pri_state) { | |
5005 | struct intel_plane_state *primary_state = | |
5006 | to_intel_plane_state(primary->state); | |
5007 | struct intel_plane_state *old_primary_state = | |
5008 | to_intel_plane_state(old_pri_state); | |
5009 | ||
5010 | intel_fbc_post_update(crtc); | |
5011 | ||
936e71e3 | 5012 | if (primary_state->base.visible && |
5a21b665 | 5013 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5014 | !old_primary_state->base.visible)) |
5a21b665 DV |
5015 | intel_post_enable_primary(&crtc->base); |
5016 | } | |
5017 | } | |
5018 | ||
5c74cd73 | 5019 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 5020 | { |
5c74cd73 | 5021 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5022 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5023 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
5024 | struct intel_crtc_state *pipe_config = |
5025 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
5026 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5027 | struct drm_plane *primary = crtc->base.primary; | |
5028 | struct drm_plane_state *old_pri_state = | |
5029 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5030 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5031 | struct intel_atomic_state *old_intel_state = |
5032 | to_intel_atomic_state(old_state); | |
ac21b225 | 5033 | |
5c74cd73 ML |
5034 | if (old_pri_state) { |
5035 | struct intel_plane_state *primary_state = | |
5036 | to_intel_plane_state(primary->state); | |
5037 | struct intel_plane_state *old_primary_state = | |
5038 | to_intel_plane_state(old_pri_state); | |
5039 | ||
faf68d92 | 5040 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5041 | |
936e71e3 VS |
5042 | if (old_primary_state->base.visible && |
5043 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5044 | intel_pre_disable_primary(&crtc->base); |
5045 | } | |
852eb00d | 5046 | |
5eeb798b VS |
5047 | /* |
5048 | * Vblank time updates from the shadow to live plane control register | |
5049 | * are blocked if the memory self-refresh mode is active at that | |
5050 | * moment. So to make sure the plane gets truly disabled, disable | |
5051 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5052 | * will be checked/applied by the HW only at the next frame start | |
5053 | * event which is after the vblank start event, so we need to have a | |
5054 | * wait-for-vblank between disabling the plane and the pipe. | |
5055 | */ | |
5056 | if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active && | |
5057 | pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) | |
5058 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
92826fcd | 5059 | |
ed4a6a7c MR |
5060 | /* |
5061 | * IVB workaround: must disable low power watermarks for at least | |
5062 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5063 | * when scaling is disabled. | |
5064 | * | |
5065 | * WaCxSRDisabledForSpriteScaling:ivb | |
5066 | */ | |
ddd2b792 | 5067 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5068 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5069 | |
5070 | /* | |
5071 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5072 | * watermark programming here. | |
5073 | */ | |
5074 | if (needs_modeset(&pipe_config->base)) | |
5075 | return; | |
5076 | ||
5077 | /* | |
5078 | * For platforms that support atomic watermarks, program the | |
5079 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5080 | * will be the intermediate values that are safe for both pre- and | |
5081 | * post- vblank; when vblank happens, the 'active' values will be set | |
5082 | * to the final 'target' values and we'll do this again to get the | |
5083 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5084 | * will be the final target values which will get automatically latched | |
5085 | * at vblank time; no further programming will be necessary. | |
5086 | * | |
5087 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5088 | * we'll continue to update watermarks the old way, if flags tell | |
5089 | * us to. | |
5090 | */ | |
5091 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5092 | dev_priv->display.initial_watermarks(old_intel_state, |
5093 | pipe_config); | |
caed361d | 5094 | else if (pipe_config->update_wm_pre) |
432081bc | 5095 | intel_update_watermarks(crtc); |
ac21b225 ML |
5096 | } |
5097 | ||
d032ffa0 | 5098 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5099 | { |
5100 | struct drm_device *dev = crtc->dev; | |
5101 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5102 | struct drm_plane *p; |
87d4300a ML |
5103 | int pipe = intel_crtc->pipe; |
5104 | ||
7cac945f | 5105 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5106 | |
d032ffa0 ML |
5107 | drm_for_each_plane_mask(p, dev, plane_mask) |
5108 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5109 | |
f99d7069 DV |
5110 | /* |
5111 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5112 | * to compute the mask of flip planes precisely. For the time being | |
5113 | * consider this a flip to a NULL plane. | |
5114 | */ | |
5748b6a1 | 5115 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5116 | } |
5117 | ||
fb1c98b1 | 5118 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5119 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5120 | struct drm_atomic_state *old_state) |
5121 | { | |
5122 | struct drm_connector_state *old_conn_state; | |
5123 | struct drm_connector *conn; | |
5124 | int i; | |
5125 | ||
5126 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5127 | struct drm_connector_state *conn_state = conn->state; | |
5128 | struct intel_encoder *encoder = | |
5129 | to_intel_encoder(conn_state->best_encoder); | |
5130 | ||
5131 | if (conn_state->crtc != crtc) | |
5132 | continue; | |
5133 | ||
5134 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5135 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5136 | } |
5137 | } | |
5138 | ||
5139 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5140 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5141 | struct drm_atomic_state *old_state) |
5142 | { | |
5143 | struct drm_connector_state *old_conn_state; | |
5144 | struct drm_connector *conn; | |
5145 | int i; | |
5146 | ||
5147 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5148 | struct drm_connector_state *conn_state = conn->state; | |
5149 | struct intel_encoder *encoder = | |
5150 | to_intel_encoder(conn_state->best_encoder); | |
5151 | ||
5152 | if (conn_state->crtc != crtc) | |
5153 | continue; | |
5154 | ||
5155 | if (encoder->pre_enable) | |
fd6bbda9 | 5156 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5157 | } |
5158 | } | |
5159 | ||
5160 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5161 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5162 | struct drm_atomic_state *old_state) |
5163 | { | |
5164 | struct drm_connector_state *old_conn_state; | |
5165 | struct drm_connector *conn; | |
5166 | int i; | |
5167 | ||
5168 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5169 | struct drm_connector_state *conn_state = conn->state; | |
5170 | struct intel_encoder *encoder = | |
5171 | to_intel_encoder(conn_state->best_encoder); | |
5172 | ||
5173 | if (conn_state->crtc != crtc) | |
5174 | continue; | |
5175 | ||
fd6bbda9 | 5176 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5177 | intel_opregion_notify_encoder(encoder, true); |
5178 | } | |
5179 | } | |
5180 | ||
5181 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5182 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5183 | struct drm_atomic_state *old_state) |
5184 | { | |
5185 | struct drm_connector_state *old_conn_state; | |
5186 | struct drm_connector *conn; | |
5187 | int i; | |
5188 | ||
5189 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5190 | struct intel_encoder *encoder = | |
5191 | to_intel_encoder(old_conn_state->best_encoder); | |
5192 | ||
5193 | if (old_conn_state->crtc != crtc) | |
5194 | continue; | |
5195 | ||
5196 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5197 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5198 | } |
5199 | } | |
5200 | ||
5201 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5202 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5203 | struct drm_atomic_state *old_state) |
5204 | { | |
5205 | struct drm_connector_state *old_conn_state; | |
5206 | struct drm_connector *conn; | |
5207 | int i; | |
5208 | ||
5209 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5210 | struct intel_encoder *encoder = | |
5211 | to_intel_encoder(old_conn_state->best_encoder); | |
5212 | ||
5213 | if (old_conn_state->crtc != crtc) | |
5214 | continue; | |
5215 | ||
5216 | if (encoder->post_disable) | |
fd6bbda9 | 5217 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5218 | } |
5219 | } | |
5220 | ||
5221 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5222 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5223 | struct drm_atomic_state *old_state) |
5224 | { | |
5225 | struct drm_connector_state *old_conn_state; | |
5226 | struct drm_connector *conn; | |
5227 | int i; | |
5228 | ||
5229 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5230 | struct intel_encoder *encoder = | |
5231 | to_intel_encoder(old_conn_state->best_encoder); | |
5232 | ||
5233 | if (old_conn_state->crtc != crtc) | |
5234 | continue; | |
5235 | ||
5236 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5237 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5238 | } |
5239 | } | |
5240 | ||
4a806558 ML |
5241 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5242 | struct drm_atomic_state *old_state) | |
f67a559d | 5243 | { |
4a806558 | 5244 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5245 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5246 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5248 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5249 | struct intel_atomic_state *old_intel_state = |
5250 | to_intel_atomic_state(old_state); | |
f67a559d | 5251 | |
53d9f4e9 | 5252 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5253 | return; |
5254 | ||
b2c0593a VS |
5255 | /* |
5256 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5257 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5258 | * | |
5259 | * On ILK we get an occasional spurious CPU pipe underruns | |
5260 | * between eDP port A enable and vdd enable. Also PCH port | |
5261 | * enable seems to result in the occasional CPU pipe underrun. | |
5262 | * | |
5263 | * Spurious PCH underruns also occur during PCH enabling. | |
5264 | */ | |
5265 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5266 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5267 | if (intel_crtc->config->has_pch_encoder) |
5268 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5269 | ||
6e3c9717 | 5270 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5271 | intel_prepare_shared_dpll(intel_crtc); |
5272 | ||
37a5650b | 5273 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5274 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5275 | |
5276 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5277 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5278 | |
6e3c9717 | 5279 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5280 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5281 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5282 | } |
5283 | ||
5284 | ironlake_set_pipeconf(crtc); | |
5285 | ||
f67a559d | 5286 | intel_crtc->active = true; |
8664281b | 5287 | |
fd6bbda9 | 5288 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5289 | |
6e3c9717 | 5290 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5291 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5292 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5293 | * enabling. */ | |
88cefb6c | 5294 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5295 | } else { |
5296 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5297 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5298 | } | |
f67a559d | 5299 | |
b074cec8 | 5300 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5301 | |
9c54c0dd JB |
5302 | /* |
5303 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5304 | * clocks enabled | |
5305 | */ | |
b95c5321 | 5306 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5307 | |
1d5bf5d9 | 5308 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5309 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5310 | intel_enable_pipe(intel_crtc); |
f67a559d | 5311 | |
6e3c9717 | 5312 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5313 | ironlake_pch_enable(pipe_config); |
c98e9dcf | 5314 | |
f9b61ff6 DV |
5315 | assert_vblank_disabled(crtc); |
5316 | drm_crtc_vblank_on(crtc); | |
5317 | ||
fd6bbda9 | 5318 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5319 | |
6e266956 | 5320 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5321 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5322 | |
5323 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5324 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5325 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5326 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5327 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5328 | } |
5329 | ||
42db64ef PZ |
5330 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5331 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5332 | { | |
50a0bc90 | 5333 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5334 | } |
5335 | ||
4a806558 ML |
5336 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5337 | struct drm_atomic_state *old_state) | |
4f771f10 | 5338 | { |
4a806558 | 5339 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5340 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5341 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5342 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5343 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5344 | struct intel_atomic_state *old_intel_state = |
5345 | to_intel_atomic_state(old_state); | |
4f771f10 | 5346 | |
53d9f4e9 | 5347 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5348 | return; |
5349 | ||
81b088ca VS |
5350 | if (intel_crtc->config->has_pch_encoder) |
5351 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5352 | false); | |
5353 | ||
fd6bbda9 | 5354 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5355 | |
8106ddbd | 5356 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5357 | intel_enable_shared_dpll(intel_crtc); |
5358 | ||
37a5650b | 5359 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5360 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5361 | |
d7edc4e5 | 5362 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5363 | intel_set_pipe_timings(intel_crtc); |
5364 | ||
bc58be60 | 5365 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5366 | |
4d1de975 JN |
5367 | if (cpu_transcoder != TRANSCODER_EDP && |
5368 | !transcoder_is_dsi(cpu_transcoder)) { | |
5369 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5370 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5371 | } |
5372 | ||
6e3c9717 | 5373 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5374 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5375 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5376 | } |
5377 | ||
d7edc4e5 | 5378 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5379 | haswell_set_pipeconf(crtc); |
5380 | ||
391bf048 | 5381 | haswell_set_pipemisc(crtc); |
229fca97 | 5382 | |
b95c5321 | 5383 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5384 | |
4f771f10 | 5385 | intel_crtc->active = true; |
8664281b | 5386 | |
6b698516 DV |
5387 | if (intel_crtc->config->has_pch_encoder) |
5388 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5389 | else | |
5390 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5391 | ||
fd6bbda9 | 5392 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5393 | |
d2d65408 | 5394 | if (intel_crtc->config->has_pch_encoder) |
dc4a1094 | 5395 | dev_priv->display.fdi_link_train(intel_crtc, pipe_config); |
4fe9467d | 5396 | |
d7edc4e5 | 5397 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5398 | intel_ddi_enable_pipe_clock(pipe_config); |
4f771f10 | 5399 | |
6315b5d3 | 5400 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5401 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5402 | else |
1c132b44 | 5403 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5404 | |
5405 | /* | |
5406 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5407 | * clocks enabled | |
5408 | */ | |
b95c5321 | 5409 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5410 | |
3dc38eea | 5411 | intel_ddi_set_pipe_settings(pipe_config); |
d7edc4e5 | 5412 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5413 | intel_ddi_enable_transcoder_func(pipe_config); |
4f771f10 | 5414 | |
1d5bf5d9 | 5415 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5416 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5417 | |
5418 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5419 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5420 | intel_enable_pipe(intel_crtc); |
42db64ef | 5421 | |
6e3c9717 | 5422 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5423 | lpt_pch_enable(pipe_config); |
4f771f10 | 5424 | |
0037071d | 5425 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5426 | intel_ddi_set_vc_payload_alloc(pipe_config, true); |
0e32b39c | 5427 | |
f9b61ff6 DV |
5428 | assert_vblank_disabled(crtc); |
5429 | drm_crtc_vblank_on(crtc); | |
5430 | ||
fd6bbda9 | 5431 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5432 | |
6b698516 | 5433 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5434 | intel_wait_for_vblank(dev_priv, pipe); |
5435 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5436 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
d2d65408 VS |
5437 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5438 | true); | |
6b698516 | 5439 | } |
d2d65408 | 5440 | |
e4916946 PZ |
5441 | /* If we change the relative order between pipe/planes enabling, we need |
5442 | * to change the workaround. */ | |
99d736a2 | 5443 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5444 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5445 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5446 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5447 | } |
4f771f10 PZ |
5448 | } |
5449 | ||
bfd16b2a | 5450 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5451 | { |
5452 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5453 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5454 | int pipe = crtc->pipe; |
5455 | ||
5456 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5457 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5458 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5459 | I915_WRITE(PF_CTL(pipe), 0); |
5460 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5461 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5462 | } | |
5463 | } | |
5464 | ||
4a806558 ML |
5465 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5466 | struct drm_atomic_state *old_state) | |
6be4a607 | 5467 | { |
4a806558 | 5468 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5469 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5470 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5471 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5472 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5473 | |
b2c0593a VS |
5474 | /* |
5475 | * Sometimes spurious CPU pipe underruns happen when the | |
5476 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5477 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5478 | */ | |
5479 | if (intel_crtc->config->has_pch_encoder) { | |
5480 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5481 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5482 | } |
37ca8d4c | 5483 | |
fd6bbda9 | 5484 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5485 | |
f9b61ff6 DV |
5486 | drm_crtc_vblank_off(crtc); |
5487 | assert_vblank_disabled(crtc); | |
5488 | ||
575f7ab7 | 5489 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5490 | |
bfd16b2a | 5491 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5492 | |
b2c0593a | 5493 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5494 | ironlake_fdi_disable(crtc); |
5495 | ||
fd6bbda9 | 5496 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5497 | |
6e3c9717 | 5498 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5499 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5500 | |
6e266956 | 5501 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5502 | i915_reg_t reg; |
5503 | u32 temp; | |
5504 | ||
d925c59a DV |
5505 | /* disable TRANS_DP_CTL */ |
5506 | reg = TRANS_DP_CTL(pipe); | |
5507 | temp = I915_READ(reg); | |
5508 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5509 | TRANS_DP_PORT_SEL_MASK); | |
5510 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5511 | I915_WRITE(reg, temp); | |
5512 | ||
5513 | /* disable DPLL_SEL */ | |
5514 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5515 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5516 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5517 | } |
e3421a18 | 5518 | |
d925c59a DV |
5519 | ironlake_fdi_pll_disable(intel_crtc); |
5520 | } | |
81b088ca | 5521 | |
b2c0593a | 5522 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5523 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5524 | } |
1b3c7a47 | 5525 | |
4a806558 ML |
5526 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5527 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5528 | { |
4a806558 | 5529 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5530 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5531 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5532 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5533 | |
d2d65408 VS |
5534 | if (intel_crtc->config->has_pch_encoder) |
5535 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5536 | false); | |
5537 | ||
fd6bbda9 | 5538 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5539 | |
f9b61ff6 DV |
5540 | drm_crtc_vblank_off(crtc); |
5541 | assert_vblank_disabled(crtc); | |
5542 | ||
4d1de975 | 5543 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5544 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5545 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5546 | |
0037071d | 5547 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5548 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); |
a4bf214f | 5549 | |
d7edc4e5 | 5550 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5551 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5552 | |
6315b5d3 | 5553 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5554 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5555 | else |
bfd16b2a | 5556 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5557 | |
d7edc4e5 | 5558 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5559 | intel_ddi_disable_pipe_clock(intel_crtc->config); |
4f771f10 | 5560 | |
fd6bbda9 | 5561 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5562 | |
b7076546 | 5563 | if (old_crtc_state->has_pch_encoder) |
81b088ca VS |
5564 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5565 | true); | |
4f771f10 PZ |
5566 | } |
5567 | ||
2dd24552 JB |
5568 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5569 | { | |
5570 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5571 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5572 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5573 | |
681a8504 | 5574 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5575 | return; |
5576 | ||
2dd24552 | 5577 | /* |
c0b03411 DV |
5578 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5579 | * according to register description and PRM. | |
2dd24552 | 5580 | */ |
c0b03411 DV |
5581 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5582 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5583 | |
b074cec8 JB |
5584 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5585 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5586 | |
5587 | /* Border color in case we don't scale up to the full screen. Black by | |
5588 | * default, change to something else for debugging. */ | |
5589 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5590 | } |
5591 | ||
79f255a0 | 5592 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
5593 | { |
5594 | switch (port) { | |
5595 | case PORT_A: | |
6331a704 | 5596 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5597 | case PORT_B: |
6331a704 | 5598 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5599 | case PORT_C: |
6331a704 | 5600 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5601 | case PORT_D: |
6331a704 | 5602 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5603 | case PORT_E: |
6331a704 | 5604 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5605 | default: |
b9fec167 | 5606 | MISSING_CASE(port); |
d05410f9 DA |
5607 | return POWER_DOMAIN_PORT_OTHER; |
5608 | } | |
5609 | } | |
5610 | ||
d8fc70b7 ACO |
5611 | static u64 get_crtc_power_domains(struct drm_crtc *crtc, |
5612 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5613 | { |
319be8ae | 5614 | struct drm_device *dev = crtc->dev; |
37255d8d | 5615 | struct drm_i915_private *dev_priv = to_i915(dev); |
74bff5f9 | 5616 | struct drm_encoder *encoder; |
319be8ae ID |
5617 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5618 | enum pipe pipe = intel_crtc->pipe; | |
d8fc70b7 | 5619 | u64 mask; |
74bff5f9 | 5620 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5621 | |
74bff5f9 | 5622 | if (!crtc_state->base.active) |
292b990e ML |
5623 | return 0; |
5624 | ||
77d22dca ID |
5625 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5626 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5627 | if (crtc_state->pch_pfit.enabled || |
5628 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 5629 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 5630 | |
74bff5f9 ML |
5631 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5632 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5633 | ||
79f255a0 | 5634 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 5635 | } |
319be8ae | 5636 | |
37255d8d ML |
5637 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
5638 | mask |= BIT(POWER_DOMAIN_AUDIO); | |
5639 | ||
15e7ec29 | 5640 | if (crtc_state->shared_dpll) |
d8fc70b7 | 5641 | mask |= BIT_ULL(POWER_DOMAIN_PLLS); |
15e7ec29 | 5642 | |
77d22dca ID |
5643 | return mask; |
5644 | } | |
5645 | ||
d2d15016 | 5646 | static u64 |
74bff5f9 ML |
5647 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
5648 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5649 | { |
fac5e23e | 5650 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5651 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5652 | enum intel_display_power_domain domain; | |
d8fc70b7 | 5653 | u64 domains, new_domains, old_domains; |
77d22dca | 5654 | |
292b990e | 5655 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5656 | intel_crtc->enabled_power_domains = new_domains = |
5657 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5658 | |
5a21b665 | 5659 | domains = new_domains & ~old_domains; |
292b990e ML |
5660 | |
5661 | for_each_power_domain(domain, domains) | |
5662 | intel_display_power_get(dev_priv, domain); | |
5663 | ||
5a21b665 | 5664 | return old_domains & ~new_domains; |
292b990e ML |
5665 | } |
5666 | ||
5667 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 5668 | u64 domains) |
292b990e ML |
5669 | { |
5670 | enum intel_display_power_domain domain; | |
5671 | ||
5672 | for_each_power_domain(domain, domains) | |
5673 | intel_display_power_put(dev_priv, domain); | |
5674 | } | |
77d22dca | 5675 | |
7ff89ca2 VS |
5676 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
5677 | struct drm_atomic_state *old_state) | |
adafdc6f | 5678 | { |
ff32c54e VS |
5679 | struct intel_atomic_state *old_intel_state = |
5680 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5681 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5682 | struct drm_device *dev = crtc->dev; | |
5683 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5684 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5685 | int pipe = intel_crtc->pipe; | |
adafdc6f | 5686 | |
7ff89ca2 VS |
5687 | if (WARN_ON(intel_crtc->active)) |
5688 | return; | |
adafdc6f | 5689 | |
7ff89ca2 VS |
5690 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5691 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
b2045352 | 5692 | |
7ff89ca2 VS |
5693 | intel_set_pipe_timings(intel_crtc); |
5694 | intel_set_pipe_src_size(intel_crtc); | |
b2045352 | 5695 | |
7ff89ca2 VS |
5696 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
5697 | struct drm_i915_private *dev_priv = to_i915(dev); | |
560a7ae4 | 5698 | |
7ff89ca2 VS |
5699 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
5700 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
5701 | } |
5702 | ||
7ff89ca2 | 5703 | i9xx_set_pipeconf(intel_crtc); |
560a7ae4 | 5704 | |
7ff89ca2 | 5705 | intel_crtc->active = true; |
92891e45 | 5706 | |
7ff89ca2 | 5707 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 5708 | |
7ff89ca2 | 5709 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
5f199dfa | 5710 | |
7ff89ca2 VS |
5711 | if (IS_CHERRYVIEW(dev_priv)) { |
5712 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
5713 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
5714 | } else { | |
5715 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
5716 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
5f199dfa VS |
5717 | } |
5718 | ||
7ff89ca2 | 5719 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
5f199dfa | 5720 | |
7ff89ca2 | 5721 | i9xx_pfit_enable(intel_crtc); |
89b3c3c7 | 5722 | |
7ff89ca2 | 5723 | intel_color_load_luts(&pipe_config->base); |
89b3c3c7 | 5724 | |
ff32c54e VS |
5725 | dev_priv->display.initial_watermarks(old_intel_state, |
5726 | pipe_config); | |
7ff89ca2 VS |
5727 | intel_enable_pipe(intel_crtc); |
5728 | ||
5729 | assert_vblank_disabled(crtc); | |
5730 | drm_crtc_vblank_on(crtc); | |
89b3c3c7 | 5731 | |
7ff89ca2 | 5732 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b3c3c7 ACO |
5733 | } |
5734 | ||
7ff89ca2 | 5735 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
2b73001e | 5736 | { |
7ff89ca2 VS |
5737 | struct drm_device *dev = crtc->base.dev; |
5738 | struct drm_i915_private *dev_priv = to_i915(dev); | |
83d7c81f | 5739 | |
7ff89ca2 VS |
5740 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5741 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
2b73001e VS |
5742 | } |
5743 | ||
7ff89ca2 VS |
5744 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
5745 | struct drm_atomic_state *old_state) | |
2b73001e | 5746 | { |
7ff89ca2 VS |
5747 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5748 | struct drm_device *dev = crtc->dev; | |
5749 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5750 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5751 | enum pipe pipe = intel_crtc->pipe; | |
2b73001e | 5752 | |
7ff89ca2 VS |
5753 | if (WARN_ON(intel_crtc->active)) |
5754 | return; | |
2b73001e | 5755 | |
7ff89ca2 | 5756 | i9xx_set_pll_dividers(intel_crtc); |
2b73001e | 5757 | |
7ff89ca2 VS |
5758 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5759 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
83d7c81f | 5760 | |
7ff89ca2 VS |
5761 | intel_set_pipe_timings(intel_crtc); |
5762 | intel_set_pipe_src_size(intel_crtc); | |
2b73001e | 5763 | |
7ff89ca2 | 5764 | i9xx_set_pipeconf(intel_crtc); |
f8437dd1 | 5765 | |
7ff89ca2 | 5766 | intel_crtc->active = true; |
5f199dfa | 5767 | |
7ff89ca2 VS |
5768 | if (!IS_GEN2(dev_priv)) |
5769 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5f199dfa | 5770 | |
7ff89ca2 | 5771 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f8437dd1 | 5772 | |
7ff89ca2 | 5773 | i9xx_enable_pll(intel_crtc); |
f8437dd1 | 5774 | |
7ff89ca2 | 5775 | i9xx_pfit_enable(intel_crtc); |
f8437dd1 | 5776 | |
7ff89ca2 | 5777 | intel_color_load_luts(&pipe_config->base); |
f8437dd1 | 5778 | |
7ff89ca2 VS |
5779 | intel_update_watermarks(intel_crtc); |
5780 | intel_enable_pipe(intel_crtc); | |
f8437dd1 | 5781 | |
7ff89ca2 VS |
5782 | assert_vblank_disabled(crtc); |
5783 | drm_crtc_vblank_on(crtc); | |
f8437dd1 | 5784 | |
7ff89ca2 VS |
5785 | intel_encoders_enable(crtc, pipe_config, old_state); |
5786 | } | |
f8437dd1 | 5787 | |
7ff89ca2 VS |
5788 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5789 | { | |
5790 | struct drm_device *dev = crtc->base.dev; | |
5791 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f8437dd1 | 5792 | |
7ff89ca2 | 5793 | if (!crtc->config->gmch_pfit.control) |
f8437dd1 | 5794 | return; |
f8437dd1 | 5795 | |
7ff89ca2 VS |
5796 | assert_pipe_disabled(dev_priv, crtc->pipe); |
5797 | ||
5798 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
5799 | I915_READ(PFIT_CONTROL)); | |
5800 | I915_WRITE(PFIT_CONTROL, 0); | |
f8437dd1 VK |
5801 | } |
5802 | ||
7ff89ca2 VS |
5803 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5804 | struct drm_atomic_state *old_state) | |
f8437dd1 | 5805 | { |
7ff89ca2 VS |
5806 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
5807 | struct drm_device *dev = crtc->dev; | |
5808 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5809 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5810 | int pipe = intel_crtc->pipe; | |
d66a2194 | 5811 | |
d66a2194 | 5812 | /* |
7ff89ca2 VS |
5813 | * On gen2 planes are double buffered but the pipe isn't, so we must |
5814 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 5815 | */ |
7ff89ca2 VS |
5816 | if (IS_GEN2(dev_priv)) |
5817 | intel_wait_for_vblank(dev_priv, pipe); | |
d66a2194 | 5818 | |
7ff89ca2 | 5819 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5820 | |
7ff89ca2 VS |
5821 | drm_crtc_vblank_off(crtc); |
5822 | assert_vblank_disabled(crtc); | |
d66a2194 | 5823 | |
7ff89ca2 | 5824 | intel_disable_pipe(intel_crtc); |
d66a2194 | 5825 | |
7ff89ca2 | 5826 | i9xx_pfit_disable(intel_crtc); |
89b3c3c7 | 5827 | |
7ff89ca2 | 5828 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5829 | |
7ff89ca2 VS |
5830 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
5831 | if (IS_CHERRYVIEW(dev_priv)) | |
5832 | chv_disable_pll(dev_priv, pipe); | |
5833 | else if (IS_VALLEYVIEW(dev_priv)) | |
5834 | vlv_disable_pll(dev_priv, pipe); | |
5835 | else | |
5836 | i9xx_disable_pll(intel_crtc); | |
5837 | } | |
c2e001ef | 5838 | |
7ff89ca2 | 5839 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
89b3c3c7 | 5840 | |
7ff89ca2 VS |
5841 | if (!IS_GEN2(dev_priv)) |
5842 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
ff32c54e VS |
5843 | |
5844 | if (!dev_priv->display.initial_watermarks) | |
5845 | intel_update_watermarks(intel_crtc); | |
f8437dd1 VK |
5846 | } |
5847 | ||
7ff89ca2 | 5848 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
f8437dd1 | 5849 | { |
7ff89ca2 VS |
5850 | struct intel_encoder *encoder; |
5851 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5852 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
5853 | enum intel_display_power_domain domain; | |
d2d15016 | 5854 | u64 domains; |
7ff89ca2 VS |
5855 | struct drm_atomic_state *state; |
5856 | struct intel_crtc_state *crtc_state; | |
5857 | int ret; | |
f8437dd1 | 5858 | |
7ff89ca2 VS |
5859 | if (!intel_crtc->active) |
5860 | return; | |
a8ca4934 | 5861 | |
7ff89ca2 VS |
5862 | if (crtc->primary->state->visible) { |
5863 | WARN_ON(intel_crtc->flip_work); | |
5d96d8af | 5864 | |
7ff89ca2 | 5865 | intel_pre_disable_primary_noatomic(crtc); |
709e05c3 | 5866 | |
7ff89ca2 VS |
5867 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
5868 | crtc->primary->state->visible = false; | |
5869 | } | |
5d96d8af | 5870 | |
7ff89ca2 VS |
5871 | state = drm_atomic_state_alloc(crtc->dev); |
5872 | if (!state) { | |
5873 | DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", | |
5874 | crtc->base.id, crtc->name); | |
1c3f7700 | 5875 | return; |
7ff89ca2 | 5876 | } |
9f7eb31a | 5877 | |
7ff89ca2 | 5878 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; |
ea61791e | 5879 | |
7ff89ca2 VS |
5880 | /* Everything's already locked, -EDEADLK can't happen. */ |
5881 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
5882 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
9f7eb31a | 5883 | |
7ff89ca2 | 5884 | WARN_ON(IS_ERR(crtc_state) || ret); |
5d96d8af | 5885 | |
7ff89ca2 | 5886 | dev_priv->display.crtc_disable(crtc_state, state); |
4a806558 | 5887 | |
0853695c | 5888 | drm_atomic_state_put(state); |
842e0307 | 5889 | |
78108b7c VS |
5890 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
5891 | crtc->base.id, crtc->name); | |
842e0307 ML |
5892 | |
5893 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
5894 | crtc->state->active = false; | |
37d9078b | 5895 | intel_crtc->active = false; |
842e0307 ML |
5896 | crtc->enabled = false; |
5897 | crtc->state->connector_mask = 0; | |
5898 | crtc->state->encoder_mask = 0; | |
5899 | ||
5900 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
5901 | encoder->base.crtc = NULL; | |
5902 | ||
58f9c0bc | 5903 | intel_fbc_disable(intel_crtc); |
432081bc | 5904 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 5905 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
5906 | |
5907 | domains = intel_crtc->enabled_power_domains; | |
5908 | for_each_power_domain(domain, domains) | |
5909 | intel_display_power_put(dev_priv, domain); | |
5910 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
5911 | |
5912 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
5913 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
5914 | } |
5915 | ||
6b72d486 ML |
5916 | /* |
5917 | * turn all crtc's off, but do not adjust state | |
5918 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
5919 | */ | |
70e0bd74 | 5920 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 5921 | { |
e2c8b870 | 5922 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 5923 | struct drm_atomic_state *state; |
e2c8b870 | 5924 | int ret; |
70e0bd74 | 5925 | |
e2c8b870 ML |
5926 | state = drm_atomic_helper_suspend(dev); |
5927 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
5928 | if (ret) |
5929 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
5930 | else |
5931 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 5932 | return ret; |
ee7b9f93 JB |
5933 | } |
5934 | ||
ea5b213a | 5935 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5936 | { |
4ef69c7a | 5937 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5938 | |
ea5b213a CW |
5939 | drm_encoder_cleanup(encoder); |
5940 | kfree(intel_encoder); | |
7e7d76c3 JB |
5941 | } |
5942 | ||
0a91ca29 DV |
5943 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5944 | * internal consistency). */ | |
5a21b665 | 5945 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 5946 | { |
5a21b665 | 5947 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
5948 | |
5949 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5950 | connector->base.base.id, | |
5951 | connector->base.name); | |
5952 | ||
0a91ca29 | 5953 | if (connector->get_hw_state(connector)) { |
e85376cb | 5954 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 5955 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 5956 | |
35dd3c64 ML |
5957 | I915_STATE_WARN(!crtc, |
5958 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 5959 | |
35dd3c64 ML |
5960 | if (!crtc) |
5961 | return; | |
5962 | ||
5963 | I915_STATE_WARN(!crtc->state->active, | |
5964 | "connector is active, but attached crtc isn't\n"); | |
5965 | ||
e85376cb | 5966 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
5967 | return; |
5968 | ||
e85376cb | 5969 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
5970 | "atomic encoder doesn't match attached encoder\n"); |
5971 | ||
e85376cb | 5972 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
5973 | "attached encoder crtc differs from connector crtc\n"); |
5974 | } else { | |
4d688a2a ML |
5975 | I915_STATE_WARN(crtc && crtc->state->active, |
5976 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 5977 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 5978 | "best encoder set without crtc!\n"); |
0a91ca29 | 5979 | } |
79e53945 JB |
5980 | } |
5981 | ||
08d9bc92 ACO |
5982 | int intel_connector_init(struct intel_connector *connector) |
5983 | { | |
5350a031 | 5984 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 5985 | |
5350a031 | 5986 | if (!connector->base.state) |
08d9bc92 ACO |
5987 | return -ENOMEM; |
5988 | ||
08d9bc92 ACO |
5989 | return 0; |
5990 | } | |
5991 | ||
5992 | struct intel_connector *intel_connector_alloc(void) | |
5993 | { | |
5994 | struct intel_connector *connector; | |
5995 | ||
5996 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
5997 | if (!connector) | |
5998 | return NULL; | |
5999 | ||
6000 | if (intel_connector_init(connector) < 0) { | |
6001 | kfree(connector); | |
6002 | return NULL; | |
6003 | } | |
6004 | ||
6005 | return connector; | |
6006 | } | |
6007 | ||
f0947c37 DV |
6008 | /* Simple connector->get_hw_state implementation for encoders that support only |
6009 | * one connector and no cloning and hence the encoder state determines the state | |
6010 | * of the connector. */ | |
6011 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6012 | { |
24929352 | 6013 | enum pipe pipe = 0; |
f0947c37 | 6014 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6015 | |
f0947c37 | 6016 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6017 | } |
6018 | ||
6d293983 | 6019 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6020 | { |
6d293983 ACO |
6021 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6022 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6023 | |
6024 | return 0; | |
6025 | } | |
6026 | ||
6d293983 | 6027 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6028 | struct intel_crtc_state *pipe_config) |
1857e1da | 6029 | { |
8652744b | 6030 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
6031 | struct drm_atomic_state *state = pipe_config->base.state; |
6032 | struct intel_crtc *other_crtc; | |
6033 | struct intel_crtc_state *other_crtc_state; | |
6034 | ||
1857e1da DV |
6035 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6036 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6037 | if (pipe_config->fdi_lanes > 4) { | |
6038 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6039 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6040 | return -EINVAL; |
1857e1da DV |
6041 | } |
6042 | ||
8652744b | 6043 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
6044 | if (pipe_config->fdi_lanes > 2) { |
6045 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6046 | pipe_config->fdi_lanes); | |
6d293983 | 6047 | return -EINVAL; |
1857e1da | 6048 | } else { |
6d293983 | 6049 | return 0; |
1857e1da DV |
6050 | } |
6051 | } | |
6052 | ||
b7f05d4a | 6053 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 6054 | return 0; |
1857e1da DV |
6055 | |
6056 | /* Ivybridge 3 pipe is really complicated */ | |
6057 | switch (pipe) { | |
6058 | case PIPE_A: | |
6d293983 | 6059 | return 0; |
1857e1da | 6060 | case PIPE_B: |
6d293983 ACO |
6061 | if (pipe_config->fdi_lanes <= 2) |
6062 | return 0; | |
6063 | ||
b91eb5cc | 6064 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
6065 | other_crtc_state = |
6066 | intel_atomic_get_crtc_state(state, other_crtc); | |
6067 | if (IS_ERR(other_crtc_state)) | |
6068 | return PTR_ERR(other_crtc_state); | |
6069 | ||
6070 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6071 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6072 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6073 | return -EINVAL; |
1857e1da | 6074 | } |
6d293983 | 6075 | return 0; |
1857e1da | 6076 | case PIPE_C: |
251cc67c VS |
6077 | if (pipe_config->fdi_lanes > 2) { |
6078 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6079 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6080 | return -EINVAL; |
251cc67c | 6081 | } |
6d293983 | 6082 | |
b91eb5cc | 6083 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
6084 | other_crtc_state = |
6085 | intel_atomic_get_crtc_state(state, other_crtc); | |
6086 | if (IS_ERR(other_crtc_state)) | |
6087 | return PTR_ERR(other_crtc_state); | |
6088 | ||
6089 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6090 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6091 | return -EINVAL; |
1857e1da | 6092 | } |
6d293983 | 6093 | return 0; |
1857e1da DV |
6094 | default: |
6095 | BUG(); | |
6096 | } | |
6097 | } | |
6098 | ||
e29c22c0 DV |
6099 | #define RETRY 1 |
6100 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6101 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6102 | { |
1857e1da | 6103 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6104 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6105 | int lane, link_bw, fdi_dotclock, ret; |
6106 | bool needs_recompute = false; | |
877d48d5 | 6107 | |
e29c22c0 | 6108 | retry: |
877d48d5 DV |
6109 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6110 | * each output octet as 10 bits. The actual frequency | |
6111 | * is stored as a divider into a 100MHz clock, and the | |
6112 | * mode pixel clock is stored in units of 1KHz. | |
6113 | * Hence the bw of each lane in terms of the mode signal | |
6114 | * is: | |
6115 | */ | |
21a727b3 | 6116 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6117 | |
241bfc38 | 6118 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6119 | |
2bd89a07 | 6120 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6121 | pipe_config->pipe_bpp); |
6122 | ||
6123 | pipe_config->fdi_lanes = lane; | |
6124 | ||
2bd89a07 | 6125 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6126 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6127 | |
e3b247da | 6128 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6129 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 6130 | pipe_config->pipe_bpp -= 2*3; |
7ff89ca2 VS |
6131 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
6132 | pipe_config->pipe_bpp); | |
6133 | needs_recompute = true; | |
6134 | pipe_config->bw_constrained = true; | |
257a7ffc | 6135 | |
7ff89ca2 | 6136 | goto retry; |
257a7ffc | 6137 | } |
79e53945 | 6138 | |
7ff89ca2 VS |
6139 | if (needs_recompute) |
6140 | return RETRY; | |
e70236a8 | 6141 | |
7ff89ca2 | 6142 | return ret; |
e70236a8 JB |
6143 | } |
6144 | ||
7ff89ca2 VS |
6145 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6146 | struct intel_crtc_state *pipe_config) | |
e70236a8 | 6147 | { |
7ff89ca2 VS |
6148 | if (pipe_config->pipe_bpp > 24) |
6149 | return false; | |
e70236a8 | 6150 | |
7ff89ca2 VS |
6151 | /* HSW can handle pixel rate up to cdclk? */ |
6152 | if (IS_HASWELL(dev_priv)) | |
6153 | return true; | |
1b1d2716 | 6154 | |
65cd2b3f | 6155 | /* |
7ff89ca2 VS |
6156 | * We compare against max which means we must take |
6157 | * the increased cdclk requirement into account when | |
6158 | * calculating the new cdclk. | |
6159 | * | |
6160 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 6161 | */ |
7ff89ca2 VS |
6162 | return pipe_config->pixel_rate <= |
6163 | dev_priv->max_cdclk_freq * 95 / 100; | |
e70236a8 | 6164 | } |
79e53945 | 6165 | |
7ff89ca2 VS |
6166 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
6167 | struct intel_crtc_state *pipe_config) | |
6168 | { | |
6169 | struct drm_device *dev = crtc->base.dev; | |
6170 | struct drm_i915_private *dev_priv = to_i915(dev); | |
34edce2f | 6171 | |
7ff89ca2 VS |
6172 | pipe_config->ips_enabled = i915.enable_ips && |
6173 | hsw_crtc_supports_ips(crtc) && | |
6174 | pipe_config_supports_ips(dev_priv, pipe_config); | |
34edce2f VS |
6175 | } |
6176 | ||
7ff89ca2 | 6177 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 6178 | { |
7ff89ca2 | 6179 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 6180 | |
7ff89ca2 VS |
6181 | /* GDG double wide on either pipe, otherwise pipe A only */ |
6182 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6183 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
34edce2f VS |
6184 | } |
6185 | ||
ceb99320 VS |
6186 | static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
6187 | { | |
6188 | uint32_t pixel_rate; | |
6189 | ||
6190 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; | |
6191 | ||
6192 | /* | |
6193 | * We only use IF-ID interlacing. If we ever use | |
6194 | * PF-ID we'll need to adjust the pixel_rate here. | |
6195 | */ | |
6196 | ||
6197 | if (pipe_config->pch_pfit.enabled) { | |
6198 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
6199 | uint32_t pfit_size = pipe_config->pch_pfit.size; | |
6200 | ||
6201 | pipe_w = pipe_config->pipe_src_w; | |
6202 | pipe_h = pipe_config->pipe_src_h; | |
6203 | ||
6204 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
6205 | pfit_h = pfit_size & 0xFFFF; | |
6206 | if (pipe_w < pfit_w) | |
6207 | pipe_w = pfit_w; | |
6208 | if (pipe_h < pfit_h) | |
6209 | pipe_h = pfit_h; | |
6210 | ||
6211 | if (WARN_ON(!pfit_w || !pfit_h)) | |
6212 | return pixel_rate; | |
6213 | ||
6214 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
6215 | pfit_w * pfit_h); | |
6216 | } | |
6217 | ||
6218 | return pixel_rate; | |
6219 | } | |
6220 | ||
7ff89ca2 | 6221 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 6222 | { |
7ff89ca2 | 6223 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
34edce2f | 6224 | |
7ff89ca2 VS |
6225 | if (HAS_GMCH_DISPLAY(dev_priv)) |
6226 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ | |
6227 | crtc_state->pixel_rate = | |
6228 | crtc_state->base.adjusted_mode.crtc_clock; | |
6229 | else | |
6230 | crtc_state->pixel_rate = | |
6231 | ilk_pipe_pixel_rate(crtc_state); | |
6232 | } | |
34edce2f | 6233 | |
7ff89ca2 VS |
6234 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6235 | struct intel_crtc_state *pipe_config) | |
6236 | { | |
6237 | struct drm_device *dev = crtc->base.dev; | |
6238 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6239 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6240 | int clock_limit = dev_priv->max_dotclk_freq; | |
34edce2f | 6241 | |
7ff89ca2 VS |
6242 | if (INTEL_GEN(dev_priv) < 4) { |
6243 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 6244 | |
7ff89ca2 VS |
6245 | /* |
6246 | * Enable double wide mode when the dot clock | |
6247 | * is > 90% of the (display) core speed. | |
6248 | */ | |
6249 | if (intel_crtc_supports_double_wide(crtc) && | |
6250 | adjusted_mode->crtc_clock > clock_limit) { | |
6251 | clock_limit = dev_priv->max_dotclk_freq; | |
6252 | pipe_config->double_wide = true; | |
6253 | } | |
34edce2f VS |
6254 | } |
6255 | ||
7ff89ca2 VS |
6256 | if (adjusted_mode->crtc_clock > clock_limit) { |
6257 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6258 | adjusted_mode->crtc_clock, clock_limit, | |
6259 | yesno(pipe_config->double_wide)); | |
6260 | return -EINVAL; | |
6261 | } | |
34edce2f | 6262 | |
7ff89ca2 VS |
6263 | /* |
6264 | * Pipe horizontal size must be even in: | |
6265 | * - DVO ganged mode | |
6266 | * - LVDS dual channel mode | |
6267 | * - Double wide pipe | |
6268 | */ | |
6269 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6270 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6271 | pipe_config->pipe_src_w &= ~1; | |
34edce2f | 6272 | |
7ff89ca2 VS |
6273 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6274 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6275 | */ | |
6276 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
6277 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6278 | return -EINVAL; | |
34edce2f | 6279 | |
7ff89ca2 | 6280 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 6281 | |
7ff89ca2 VS |
6282 | if (HAS_IPS(dev_priv)) |
6283 | hsw_compute_ips_config(crtc, pipe_config); | |
34edce2f | 6284 | |
7ff89ca2 VS |
6285 | if (pipe_config->has_pch_encoder) |
6286 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
34edce2f | 6287 | |
7ff89ca2 | 6288 | return 0; |
34edce2f VS |
6289 | } |
6290 | ||
2c07245f | 6291 | static void |
a65851af | 6292 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6293 | { |
a65851af VS |
6294 | while (*num > DATA_LINK_M_N_MASK || |
6295 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6296 | *num >>= 1; |
6297 | *den >>= 1; | |
6298 | } | |
6299 | } | |
6300 | ||
a65851af VS |
6301 | static void compute_m_n(unsigned int m, unsigned int n, |
6302 | uint32_t *ret_m, uint32_t *ret_n) | |
6303 | { | |
6304 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6305 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6306 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6307 | } | |
6308 | ||
e69d0bc1 DV |
6309 | void |
6310 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6311 | int pixel_clock, int link_clock, | |
6312 | struct intel_link_m_n *m_n) | |
2c07245f | 6313 | { |
e69d0bc1 | 6314 | m_n->tu = 64; |
a65851af VS |
6315 | |
6316 | compute_m_n(bits_per_pixel * pixel_clock, | |
6317 | link_clock * nlanes * 8, | |
6318 | &m_n->gmch_m, &m_n->gmch_n); | |
6319 | ||
6320 | compute_m_n(pixel_clock, link_clock, | |
6321 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6322 | } |
6323 | ||
a7615030 CW |
6324 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6325 | { | |
d330a953 JN |
6326 | if (i915.panel_use_ssc >= 0) |
6327 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6328 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6329 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6330 | } |
6331 | ||
7429e9d4 | 6332 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6333 | { |
7df00d7a | 6334 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6335 | } |
f47709a9 | 6336 | |
7429e9d4 DV |
6337 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6338 | { | |
6339 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6340 | } |
6341 | ||
f47709a9 | 6342 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6343 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 6344 | struct dpll *reduced_clock) |
a7516a05 | 6345 | { |
9b1e14f4 | 6346 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
6347 | u32 fp, fp2 = 0; |
6348 | ||
9b1e14f4 | 6349 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 6350 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6351 | if (reduced_clock) |
7429e9d4 | 6352 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6353 | } else { |
190f68c5 | 6354 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6355 | if (reduced_clock) |
7429e9d4 | 6356 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6357 | } |
6358 | ||
190f68c5 | 6359 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6360 | |
f47709a9 | 6361 | crtc->lowfreq_avail = false; |
2d84d2b3 | 6362 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6363 | reduced_clock) { |
190f68c5 | 6364 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6365 | crtc->lowfreq_avail = true; |
a7516a05 | 6366 | } else { |
190f68c5 | 6367 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6368 | } |
6369 | } | |
6370 | ||
5e69f97f CML |
6371 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6372 | pipe) | |
89b667f8 JB |
6373 | { |
6374 | u32 reg_val; | |
6375 | ||
6376 | /* | |
6377 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6378 | * and set it to a reasonable value instead. | |
6379 | */ | |
ab3c759a | 6380 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6381 | reg_val &= 0xffffff00; |
6382 | reg_val |= 0x00000030; | |
ab3c759a | 6383 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6384 | |
ab3c759a | 6385 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6386 | reg_val &= 0x8cffffff; |
6387 | reg_val = 0x8c000000; | |
ab3c759a | 6388 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6389 | |
ab3c759a | 6390 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6391 | reg_val &= 0xffffff00; |
ab3c759a | 6392 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6393 | |
ab3c759a | 6394 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6395 | reg_val &= 0x00ffffff; |
6396 | reg_val |= 0xb0000000; | |
ab3c759a | 6397 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6398 | } |
6399 | ||
b551842d DV |
6400 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6401 | struct intel_link_m_n *m_n) | |
6402 | { | |
6403 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6404 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
6405 | int pipe = crtc->pipe; |
6406 | ||
e3b95f1e DV |
6407 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6408 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6409 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6410 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6411 | } |
6412 | ||
6413 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6414 | struct intel_link_m_n *m_n, |
6415 | struct intel_link_m_n *m2_n2) | |
b551842d | 6416 | { |
6315b5d3 | 6417 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 6418 | int pipe = crtc->pipe; |
6e3c9717 | 6419 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 6420 | |
6315b5d3 | 6421 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
6422 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6423 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6424 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6425 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6426 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6427 | * for gen < 8) and if DRRS is supported (to make sure the | |
6428 | * registers are not unnecessarily accessed). | |
6429 | */ | |
920a14b2 TU |
6430 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
6431 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
6432 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6433 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6434 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6435 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6436 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6437 | } | |
b551842d | 6438 | } else { |
e3b95f1e DV |
6439 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6440 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6441 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6442 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6443 | } |
6444 | } | |
6445 | ||
fe3cd48d | 6446 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6447 | { |
fe3cd48d R |
6448 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6449 | ||
6450 | if (m_n == M1_N1) { | |
6451 | dp_m_n = &crtc->config->dp_m_n; | |
6452 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6453 | } else if (m_n == M2_N2) { | |
6454 | ||
6455 | /* | |
6456 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6457 | * needs to be programmed into M1_N1. | |
6458 | */ | |
6459 | dp_m_n = &crtc->config->dp_m2_n2; | |
6460 | } else { | |
6461 | DRM_ERROR("Unsupported divider value\n"); | |
6462 | return; | |
6463 | } | |
6464 | ||
6e3c9717 ACO |
6465 | if (crtc->config->has_pch_encoder) |
6466 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6467 | else |
fe3cd48d | 6468 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6469 | } |
6470 | ||
251ac862 DV |
6471 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
6472 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 6473 | { |
03ed5cbf | 6474 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 6475 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6476 | if (crtc->pipe != PIPE_A) |
6477 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 6478 | |
cd2d34d9 | 6479 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6480 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6481 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
6482 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
6483 | ||
03ed5cbf VS |
6484 | pipe_config->dpll_hw_state.dpll_md = |
6485 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6486 | } | |
bdd4b6a6 | 6487 | |
03ed5cbf VS |
6488 | static void chv_compute_dpll(struct intel_crtc *crtc, |
6489 | struct intel_crtc_state *pipe_config) | |
6490 | { | |
6491 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 6492 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6493 | if (crtc->pipe != PIPE_A) |
6494 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6495 | ||
cd2d34d9 | 6496 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6497 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6498 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
6499 | ||
03ed5cbf VS |
6500 | pipe_config->dpll_hw_state.dpll_md = |
6501 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
6502 | } |
6503 | ||
d288f65f | 6504 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6505 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6506 | { |
f47709a9 | 6507 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6508 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6509 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 6510 | u32 mdiv; |
a0c4da24 | 6511 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6512 | u32 coreclk, reg_val; |
a0c4da24 | 6513 | |
cd2d34d9 VS |
6514 | /* Enable Refclk */ |
6515 | I915_WRITE(DPLL(pipe), | |
6516 | pipe_config->dpll_hw_state.dpll & | |
6517 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
6518 | ||
6519 | /* No need to actually set up the DPLL with DSI */ | |
6520 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6521 | return; | |
6522 | ||
a580516d | 6523 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 6524 | |
d288f65f VS |
6525 | bestn = pipe_config->dpll.n; |
6526 | bestm1 = pipe_config->dpll.m1; | |
6527 | bestm2 = pipe_config->dpll.m2; | |
6528 | bestp1 = pipe_config->dpll.p1; | |
6529 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6530 | |
89b667f8 JB |
6531 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6532 | ||
6533 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6534 | if (pipe == PIPE_B) |
5e69f97f | 6535 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6536 | |
6537 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6538 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6539 | |
6540 | /* Disable target IRef on PLL */ | |
ab3c759a | 6541 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6542 | reg_val &= 0x00ffffff; |
ab3c759a | 6543 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6544 | |
6545 | /* Disable fast lock */ | |
ab3c759a | 6546 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6547 | |
6548 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6549 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6550 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6551 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6552 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6553 | |
6554 | /* | |
6555 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6556 | * but we don't support that). | |
6557 | * Note: don't use the DAC post divider as it seems unstable. | |
6558 | */ | |
6559 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6560 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6561 | |
a0c4da24 | 6562 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6563 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6564 | |
89b667f8 | 6565 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6566 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
6567 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
6568 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6569 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6570 | 0x009f0003); |
89b667f8 | 6571 | else |
ab3c759a | 6572 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6573 | 0x00d0000f); |
6574 | ||
37a5650b | 6575 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 6576 | /* Use SSC source */ |
bdd4b6a6 | 6577 | if (pipe == PIPE_A) |
ab3c759a | 6578 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6579 | 0x0df40000); |
6580 | else | |
ab3c759a | 6581 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6582 | 0x0df70000); |
6583 | } else { /* HDMI or VGA */ | |
6584 | /* Use bend source */ | |
bdd4b6a6 | 6585 | if (pipe == PIPE_A) |
ab3c759a | 6586 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6587 | 0x0df70000); |
6588 | else | |
ab3c759a | 6589 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6590 | 0x0df40000); |
6591 | } | |
a0c4da24 | 6592 | |
ab3c759a | 6593 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6594 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 6595 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 6596 | coreclk |= 0x01000000; |
ab3c759a | 6597 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6598 | |
ab3c759a | 6599 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 6600 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
6601 | } |
6602 | ||
d288f65f | 6603 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6604 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6605 | { |
6606 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6607 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6608 | enum pipe pipe = crtc->pipe; |
9d556c99 | 6609 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 6610 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6611 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6612 | u32 dpio_val; |
9cbe40c1 | 6613 | int vco; |
9d556c99 | 6614 | |
cd2d34d9 VS |
6615 | /* Enable Refclk and SSC */ |
6616 | I915_WRITE(DPLL(pipe), | |
6617 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
6618 | ||
6619 | /* No need to actually set up the DPLL with DSI */ | |
6620 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6621 | return; | |
6622 | ||
d288f65f VS |
6623 | bestn = pipe_config->dpll.n; |
6624 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6625 | bestm1 = pipe_config->dpll.m1; | |
6626 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6627 | bestp1 = pipe_config->dpll.p1; | |
6628 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6629 | vco = pipe_config->dpll.vco; |
a945ce7e | 6630 | dpio_val = 0; |
9cbe40c1 | 6631 | loopfilter = 0; |
9d556c99 | 6632 | |
a580516d | 6633 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 6634 | |
9d556c99 CML |
6635 | /* p1 and p2 divider */ |
6636 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6637 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6638 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6639 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6640 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6641 | ||
6642 | /* Feedback post-divider - m2 */ | |
6643 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6644 | ||
6645 | /* Feedback refclk divider - n and m1 */ | |
6646 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6647 | DPIO_CHV_M1_DIV_BY_2 | | |
6648 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6649 | ||
6650 | /* M2 fraction division */ | |
25a25dfc | 6651 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
6652 | |
6653 | /* M2 fraction division enable */ | |
a945ce7e VP |
6654 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6655 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6656 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6657 | if (bestm2_frac) | |
6658 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6659 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6660 | |
de3a0fde VP |
6661 | /* Program digital lock detect threshold */ |
6662 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6663 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6664 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6665 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6666 | if (!bestm2_frac) | |
6667 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6668 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6669 | ||
9d556c99 | 6670 | /* Loop filter */ |
9cbe40c1 VP |
6671 | if (vco == 5400000) { |
6672 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6673 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6674 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6675 | tribuf_calcntr = 0x9; | |
6676 | } else if (vco <= 6200000) { | |
6677 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6678 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6679 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6680 | tribuf_calcntr = 0x9; | |
6681 | } else if (vco <= 6480000) { | |
6682 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6683 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6684 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6685 | tribuf_calcntr = 0x8; | |
6686 | } else { | |
6687 | /* Not supported. Apply the same limits as in the max case */ | |
6688 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6689 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6690 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6691 | tribuf_calcntr = 0; | |
6692 | } | |
9d556c99 CML |
6693 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6694 | ||
968040b2 | 6695 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6696 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6697 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6698 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6699 | ||
9d556c99 CML |
6700 | /* AFC Recal */ |
6701 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6702 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6703 | DPIO_AFC_RECAL); | |
6704 | ||
a580516d | 6705 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
6706 | } |
6707 | ||
d288f65f VS |
6708 | /** |
6709 | * vlv_force_pll_on - forcibly enable just the PLL | |
6710 | * @dev_priv: i915 private structure | |
6711 | * @pipe: pipe PLL to enable | |
6712 | * @dpll: PLL configuration | |
6713 | * | |
6714 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6715 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6716 | * be enabled. | |
6717 | */ | |
30ad9814 | 6718 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 6719 | const struct dpll *dpll) |
d288f65f | 6720 | { |
b91eb5cc | 6721 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
6722 | struct intel_crtc_state *pipe_config; |
6723 | ||
6724 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
6725 | if (!pipe_config) | |
6726 | return -ENOMEM; | |
6727 | ||
6728 | pipe_config->base.crtc = &crtc->base; | |
6729 | pipe_config->pixel_multiplier = 1; | |
6730 | pipe_config->dpll = *dpll; | |
d288f65f | 6731 | |
30ad9814 | 6732 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
6733 | chv_compute_dpll(crtc, pipe_config); |
6734 | chv_prepare_pll(crtc, pipe_config); | |
6735 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 6736 | } else { |
3f36b937 TU |
6737 | vlv_compute_dpll(crtc, pipe_config); |
6738 | vlv_prepare_pll(crtc, pipe_config); | |
6739 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 6740 | } |
3f36b937 TU |
6741 | |
6742 | kfree(pipe_config); | |
6743 | ||
6744 | return 0; | |
d288f65f VS |
6745 | } |
6746 | ||
6747 | /** | |
6748 | * vlv_force_pll_off - forcibly disable just the PLL | |
6749 | * @dev_priv: i915 private structure | |
6750 | * @pipe: pipe PLL to disable | |
6751 | * | |
6752 | * Disable the PLL for @pipe. To be used in cases where we need | |
6753 | * the PLL enabled even when @pipe is not going to be enabled. | |
6754 | */ | |
30ad9814 | 6755 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 6756 | { |
30ad9814 VS |
6757 | if (IS_CHERRYVIEW(dev_priv)) |
6758 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 6759 | else |
30ad9814 | 6760 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
6761 | } |
6762 | ||
251ac862 DV |
6763 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
6764 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6765 | struct dpll *reduced_clock) |
eb1cbe48 | 6766 | { |
9b1e14f4 | 6767 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 6768 | u32 dpll; |
190f68c5 | 6769 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6770 | |
190f68c5 | 6771 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6772 | |
eb1cbe48 DV |
6773 | dpll = DPLL_VGA_MODE_DIS; |
6774 | ||
2d84d2b3 | 6775 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6776 | dpll |= DPLLB_MODE_LVDS; |
6777 | else | |
6778 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6779 | |
73f67aa8 JN |
6780 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
6781 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 6782 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6783 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6784 | } |
198a037f | 6785 | |
3d6e9ee0 VS |
6786 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6787 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 6788 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6789 | |
37a5650b | 6790 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 6791 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6792 | |
6793 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 6794 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
6795 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
6796 | else { | |
6797 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 6798 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
6799 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6800 | } | |
6801 | switch (clock->p2) { | |
6802 | case 5: | |
6803 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6804 | break; | |
6805 | case 7: | |
6806 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6807 | break; | |
6808 | case 10: | |
6809 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6810 | break; | |
6811 | case 14: | |
6812 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6813 | break; | |
6814 | } | |
9b1e14f4 | 6815 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
6816 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
6817 | ||
190f68c5 | 6818 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6819 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 6820 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6821 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6822 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6823 | else | |
6824 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6825 | ||
6826 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6827 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6828 | |
9b1e14f4 | 6829 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 6830 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6831 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6832 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6833 | } |
6834 | } | |
6835 | ||
251ac862 DV |
6836 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
6837 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6838 | struct dpll *reduced_clock) |
eb1cbe48 | 6839 | { |
f47709a9 | 6840 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6841 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 6842 | u32 dpll; |
190f68c5 | 6843 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6844 | |
190f68c5 | 6845 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6846 | |
eb1cbe48 DV |
6847 | dpll = DPLL_VGA_MODE_DIS; |
6848 | ||
2d84d2b3 | 6849 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6850 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6851 | } else { | |
6852 | if (clock->p1 == 2) | |
6853 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6854 | else | |
6855 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6856 | if (clock->p2 == 4) | |
6857 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6858 | } | |
6859 | ||
50a0bc90 TU |
6860 | if (!IS_I830(dev_priv) && |
6861 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
6862 | dpll |= DPLL_DVO_2X_MODE; |
6863 | ||
2d84d2b3 | 6864 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6865 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6866 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6867 | else | |
6868 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6869 | ||
6870 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6871 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6872 | } |
6873 | ||
8a654f3b | 6874 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 6875 | { |
6315b5d3 | 6876 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 6877 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 6878 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 6879 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6880 | uint32_t crtc_vtotal, crtc_vblank_end; |
6881 | int vsyncshift = 0; | |
4d8a62ea DV |
6882 | |
6883 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6884 | * the hw state checker will get angry at the mismatch. */ | |
6885 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6886 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6887 | |
609aeaca | 6888 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6889 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6890 | crtc_vtotal -= 1; |
6891 | crtc_vblank_end -= 1; | |
609aeaca | 6892 | |
2d84d2b3 | 6893 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6894 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6895 | else | |
6896 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6897 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6898 | if (vsyncshift < 0) |
6899 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6900 | } |
6901 | ||
6315b5d3 | 6902 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 6903 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6904 | |
fe2b8f9d | 6905 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6906 | (adjusted_mode->crtc_hdisplay - 1) | |
6907 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6908 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6909 | (adjusted_mode->crtc_hblank_start - 1) | |
6910 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6911 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6912 | (adjusted_mode->crtc_hsync_start - 1) | |
6913 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6914 | ||
fe2b8f9d | 6915 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6916 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6917 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6918 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6919 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6920 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6921 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6922 | (adjusted_mode->crtc_vsync_start - 1) | |
6923 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6924 | ||
b5e508d4 PZ |
6925 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6926 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6927 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6928 | * bits. */ | |
772c2a51 | 6929 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
6930 | (pipe == PIPE_B || pipe == PIPE_C)) |
6931 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6932 | ||
bc58be60 JN |
6933 | } |
6934 | ||
6935 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
6936 | { | |
6937 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 6938 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
6939 | enum pipe pipe = intel_crtc->pipe; |
6940 | ||
b0e77b9c PZ |
6941 | /* pipesrc controls the size that is scaled from, which should |
6942 | * always be the user's requested size. | |
6943 | */ | |
6944 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6945 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6946 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6947 | } |
6948 | ||
1bd1bd80 | 6949 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6950 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6951 | { |
6952 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6953 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
6954 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
6955 | uint32_t tmp; | |
6956 | ||
6957 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6958 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6959 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6960 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6961 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6962 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6963 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6964 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6965 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6966 | |
6967 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6968 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6969 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6970 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6971 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6972 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6973 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6974 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6975 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6976 | |
6977 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6978 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6979 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6980 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 6981 | } |
bc58be60 JN |
6982 | } |
6983 | ||
6984 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
6985 | struct intel_crtc_state *pipe_config) | |
6986 | { | |
6987 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6988 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 6989 | u32 tmp; |
1bd1bd80 DV |
6990 | |
6991 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6992 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6993 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6994 | ||
2d112de7 ACO |
6995 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
6996 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6997 | } |
6998 | ||
f6a83288 | 6999 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7000 | struct intel_crtc_state *pipe_config) |
babea61d | 7001 | { |
2d112de7 ACO |
7002 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7003 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7004 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7005 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7006 | |
2d112de7 ACO |
7007 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7008 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7009 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7010 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7011 | |
2d112de7 | 7012 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7013 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7014 | |
2d112de7 | 7015 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
cd13f5ab ML |
7016 | |
7017 | mode->hsync = drm_mode_hsync(mode); | |
7018 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7019 | drm_mode_set_name(mode); | |
babea61d JB |
7020 | } |
7021 | ||
84b046f3 DV |
7022 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7023 | { | |
6315b5d3 | 7024 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
7025 | uint32_t pipeconf; |
7026 | ||
9f11a9e4 | 7027 | pipeconf = 0; |
84b046f3 | 7028 | |
b6b5d049 VS |
7029 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7030 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7031 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7032 | |
6e3c9717 | 7033 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7034 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7035 | |
ff9ce46e | 7036 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
7037 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7038 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 7039 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7040 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7041 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7042 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7043 | |
6e3c9717 | 7044 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7045 | case 18: |
7046 | pipeconf |= PIPECONF_6BPC; | |
7047 | break; | |
7048 | case 24: | |
7049 | pipeconf |= PIPECONF_8BPC; | |
7050 | break; | |
7051 | case 30: | |
7052 | pipeconf |= PIPECONF_10BPC; | |
7053 | break; | |
7054 | default: | |
7055 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7056 | BUG(); | |
84b046f3 DV |
7057 | } |
7058 | } | |
7059 | ||
56b857a5 | 7060 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
7061 | if (intel_crtc->lowfreq_avail) { |
7062 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7063 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7064 | } else { | |
7065 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7066 | } |
7067 | } | |
7068 | ||
6e3c9717 | 7069 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 7070 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 7071 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7072 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7073 | else | |
7074 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7075 | } else | |
84b046f3 DV |
7076 | pipeconf |= PIPECONF_PROGRESSIVE; |
7077 | ||
920a14b2 | 7078 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7079 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 7080 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7081 | |
84b046f3 DV |
7082 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7083 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7084 | } | |
7085 | ||
81c97f52 ACO |
7086 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7087 | struct intel_crtc_state *crtc_state) | |
7088 | { | |
7089 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7090 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7091 | const struct intel_limit *limit; |
81c97f52 ACO |
7092 | int refclk = 48000; |
7093 | ||
7094 | memset(&crtc_state->dpll_hw_state, 0, | |
7095 | sizeof(crtc_state->dpll_hw_state)); | |
7096 | ||
2d84d2b3 | 7097 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7098 | if (intel_panel_use_ssc(dev_priv)) { |
7099 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7100 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7101 | } | |
7102 | ||
7103 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7104 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7105 | limit = &intel_limits_i8xx_dvo; |
7106 | } else { | |
7107 | limit = &intel_limits_i8xx_dac; | |
7108 | } | |
7109 | ||
7110 | if (!crtc_state->clock_set && | |
7111 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7112 | refclk, NULL, &crtc_state->dpll)) { | |
7113 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7114 | return -EINVAL; | |
7115 | } | |
7116 | ||
7117 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7118 | ||
7119 | return 0; | |
7120 | } | |
7121 | ||
19ec6693 ACO |
7122 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7123 | struct intel_crtc_state *crtc_state) | |
7124 | { | |
7125 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7126 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7127 | const struct intel_limit *limit; |
19ec6693 ACO |
7128 | int refclk = 96000; |
7129 | ||
7130 | memset(&crtc_state->dpll_hw_state, 0, | |
7131 | sizeof(crtc_state->dpll_hw_state)); | |
7132 | ||
2d84d2b3 | 7133 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7134 | if (intel_panel_use_ssc(dev_priv)) { |
7135 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7136 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7137 | } | |
7138 | ||
7139 | if (intel_is_dual_link_lvds(dev)) | |
7140 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7141 | else | |
7142 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7143 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7144 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7145 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7146 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7147 | limit = &intel_limits_g4x_sdvo; |
7148 | } else { | |
7149 | /* The option is for other outputs */ | |
7150 | limit = &intel_limits_i9xx_sdvo; | |
7151 | } | |
7152 | ||
7153 | if (!crtc_state->clock_set && | |
7154 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7155 | refclk, NULL, &crtc_state->dpll)) { | |
7156 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7157 | return -EINVAL; | |
7158 | } | |
7159 | ||
7160 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7161 | ||
7162 | return 0; | |
7163 | } | |
7164 | ||
70e8aa21 ACO |
7165 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7166 | struct intel_crtc_state *crtc_state) | |
7167 | { | |
7168 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7169 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7170 | const struct intel_limit *limit; |
70e8aa21 ACO |
7171 | int refclk = 96000; |
7172 | ||
7173 | memset(&crtc_state->dpll_hw_state, 0, | |
7174 | sizeof(crtc_state->dpll_hw_state)); | |
7175 | ||
2d84d2b3 | 7176 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7177 | if (intel_panel_use_ssc(dev_priv)) { |
7178 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7179 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7180 | } | |
7181 | ||
7182 | limit = &intel_limits_pineview_lvds; | |
7183 | } else { | |
7184 | limit = &intel_limits_pineview_sdvo; | |
7185 | } | |
7186 | ||
7187 | if (!crtc_state->clock_set && | |
7188 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7189 | refclk, NULL, &crtc_state->dpll)) { | |
7190 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7191 | return -EINVAL; | |
7192 | } | |
7193 | ||
7194 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7195 | ||
7196 | return 0; | |
7197 | } | |
7198 | ||
190f68c5 ACO |
7199 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7200 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7201 | { |
c7653199 | 7202 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7203 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7204 | const struct intel_limit *limit; |
81c97f52 | 7205 | int refclk = 96000; |
79e53945 | 7206 | |
dd3cd74a ACO |
7207 | memset(&crtc_state->dpll_hw_state, 0, |
7208 | sizeof(crtc_state->dpll_hw_state)); | |
7209 | ||
2d84d2b3 | 7210 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7211 | if (intel_panel_use_ssc(dev_priv)) { |
7212 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7213 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7214 | } | |
43565a06 | 7215 | |
70e8aa21 ACO |
7216 | limit = &intel_limits_i9xx_lvds; |
7217 | } else { | |
7218 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7219 | } |
79e53945 | 7220 | |
70e8aa21 ACO |
7221 | if (!crtc_state->clock_set && |
7222 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7223 | refclk, NULL, &crtc_state->dpll)) { | |
7224 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7225 | return -EINVAL; | |
f47709a9 | 7226 | } |
7026d4ac | 7227 | |
81c97f52 | 7228 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7229 | |
c8f7a0db | 7230 | return 0; |
f564048e EA |
7231 | } |
7232 | ||
65b3d6a9 ACO |
7233 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7234 | struct intel_crtc_state *crtc_state) | |
7235 | { | |
7236 | int refclk = 100000; | |
1b6f4958 | 7237 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7238 | |
7239 | memset(&crtc_state->dpll_hw_state, 0, | |
7240 | sizeof(crtc_state->dpll_hw_state)); | |
7241 | ||
65b3d6a9 ACO |
7242 | if (!crtc_state->clock_set && |
7243 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7244 | refclk, NULL, &crtc_state->dpll)) { | |
7245 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7246 | return -EINVAL; | |
7247 | } | |
7248 | ||
7249 | chv_compute_dpll(crtc, crtc_state); | |
7250 | ||
7251 | return 0; | |
7252 | } | |
7253 | ||
7254 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7255 | struct intel_crtc_state *crtc_state) | |
7256 | { | |
7257 | int refclk = 100000; | |
1b6f4958 | 7258 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7259 | |
7260 | memset(&crtc_state->dpll_hw_state, 0, | |
7261 | sizeof(crtc_state->dpll_hw_state)); | |
7262 | ||
65b3d6a9 ACO |
7263 | if (!crtc_state->clock_set && |
7264 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7265 | refclk, NULL, &crtc_state->dpll)) { | |
7266 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7267 | return -EINVAL; | |
7268 | } | |
7269 | ||
7270 | vlv_compute_dpll(crtc, crtc_state); | |
7271 | ||
7272 | return 0; | |
7273 | } | |
7274 | ||
2fa2fe9a | 7275 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7276 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 7277 | { |
6315b5d3 | 7278 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
7279 | uint32_t tmp; |
7280 | ||
50a0bc90 TU |
7281 | if (INTEL_GEN(dev_priv) <= 3 && |
7282 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
7283 | return; |
7284 | ||
2fa2fe9a | 7285 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7286 | if (!(tmp & PFIT_ENABLE)) |
7287 | return; | |
2fa2fe9a | 7288 | |
06922821 | 7289 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 7290 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
7291 | if (crtc->pipe != PIPE_B) |
7292 | return; | |
2fa2fe9a DV |
7293 | } else { |
7294 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7295 | return; | |
7296 | } | |
7297 | ||
06922821 | 7298 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7299 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7300 | } |
7301 | ||
acbec814 | 7302 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7303 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7304 | { |
7305 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7306 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 7307 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 7308 | struct dpll clock; |
acbec814 | 7309 | u32 mdiv; |
662c6ecb | 7310 | int refclk = 100000; |
acbec814 | 7311 | |
b521973b VS |
7312 | /* In case of DSI, DPLL will not be used */ |
7313 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
7314 | return; |
7315 | ||
a580516d | 7316 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7317 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7318 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7319 | |
7320 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7321 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7322 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7323 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7324 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7325 | ||
dccbea3b | 7326 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7327 | } |
7328 | ||
5724dbd1 DL |
7329 | static void |
7330 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7331 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7332 | { |
7333 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7334 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
7335 | u32 val, base, offset; |
7336 | int pipe = crtc->pipe, plane = crtc->plane; | |
7337 | int fourcc, pixel_format; | |
6761dd31 | 7338 | unsigned int aligned_height; |
b113d5ee | 7339 | struct drm_framebuffer *fb; |
1b842c89 | 7340 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7341 | |
42a7b088 DL |
7342 | val = I915_READ(DSPCNTR(plane)); |
7343 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7344 | return; | |
7345 | ||
d9806c9f | 7346 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7347 | if (!intel_fb) { |
1ad292b5 JB |
7348 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7349 | return; | |
7350 | } | |
7351 | ||
1b842c89 DL |
7352 | fb = &intel_fb->base; |
7353 | ||
d2e9f5fc VS |
7354 | fb->dev = dev; |
7355 | ||
6315b5d3 | 7356 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 7357 | if (val & DISPPLANE_TILED) { |
49af449b | 7358 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 7359 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
7360 | } |
7361 | } | |
1ad292b5 JB |
7362 | |
7363 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7364 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 7365 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 7366 | |
6315b5d3 | 7367 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 7368 | if (plane_config->tiling) |
1ad292b5 JB |
7369 | offset = I915_READ(DSPTILEOFF(plane)); |
7370 | else | |
7371 | offset = I915_READ(DSPLINOFF(plane)); | |
7372 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7373 | } else { | |
7374 | base = I915_READ(DSPADDR(plane)); | |
7375 | } | |
7376 | plane_config->base = base; | |
7377 | ||
7378 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7379 | fb->width = ((val >> 16) & 0xfff) + 1; |
7380 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7381 | |
7382 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7383 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7384 | |
24dbf51a CW |
7385 | aligned_height = intel_fb_align_height(dev_priv, |
7386 | fb->height, | |
438b74a5 | 7387 | fb->format->format, |
bae781b2 | 7388 | fb->modifier); |
1ad292b5 | 7389 | |
f37b5c2b | 7390 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7391 | |
2844a921 DL |
7392 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7393 | pipe_name(pipe), plane, fb->width, fb->height, | |
272725c7 | 7394 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 7395 | plane_config->size); |
1ad292b5 | 7396 | |
2d14030b | 7397 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7398 | } |
7399 | ||
70b23a98 | 7400 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7401 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7402 | { |
7403 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7404 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
7405 | int pipe = pipe_config->cpu_transcoder; |
7406 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 7407 | struct dpll clock; |
0d7b6b11 | 7408 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
7409 | int refclk = 100000; |
7410 | ||
b521973b VS |
7411 | /* In case of DSI, DPLL will not be used */ |
7412 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7413 | return; | |
7414 | ||
a580516d | 7415 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7416 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7417 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7418 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7419 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 7420 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 7421 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7422 | |
7423 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
7424 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7425 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
7426 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
7427 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7428 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7429 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7430 | ||
dccbea3b | 7431 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
7432 | } |
7433 | ||
0e8ffe1b | 7434 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7435 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 7436 | { |
6315b5d3 | 7437 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 7438 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 7439 | uint32_t tmp; |
1729050e | 7440 | bool ret; |
0e8ffe1b | 7441 | |
1729050e ID |
7442 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
7443 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
7444 | return false; |
7445 | ||
e143a21c | 7446 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 7447 | pipe_config->shared_dpll = NULL; |
eccb140b | 7448 | |
1729050e ID |
7449 | ret = false; |
7450 | ||
0e8ffe1b DV |
7451 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7452 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 7453 | goto out; |
0e8ffe1b | 7454 | |
9beb5fea TU |
7455 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7456 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
7457 | switch (tmp & PIPECONF_BPC_MASK) { |
7458 | case PIPECONF_6BPC: | |
7459 | pipe_config->pipe_bpp = 18; | |
7460 | break; | |
7461 | case PIPECONF_8BPC: | |
7462 | pipe_config->pipe_bpp = 24; | |
7463 | break; | |
7464 | case PIPECONF_10BPC: | |
7465 | pipe_config->pipe_bpp = 30; | |
7466 | break; | |
7467 | default: | |
7468 | break; | |
7469 | } | |
7470 | } | |
7471 | ||
920a14b2 | 7472 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7473 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
7474 | pipe_config->limited_color_range = true; |
7475 | ||
6315b5d3 | 7476 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
7477 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
7478 | ||
1bd1bd80 | 7479 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 7480 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 7481 | |
2fa2fe9a DV |
7482 | i9xx_get_pfit_config(crtc, pipe_config); |
7483 | ||
6315b5d3 | 7484 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 7485 | /* No way to read it out on pipes B and C */ |
920a14b2 | 7486 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
7487 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
7488 | else | |
7489 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
7490 | pipe_config->pixel_multiplier = |
7491 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7492 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7493 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 7494 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 7495 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
7496 | tmp = I915_READ(DPLL(crtc->pipe)); |
7497 | pipe_config->pixel_multiplier = | |
7498 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7499 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7500 | } else { | |
7501 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7502 | * port and will be fixed up in the encoder->get_config | |
7503 | * function. */ | |
7504 | pipe_config->pixel_multiplier = 1; | |
7505 | } | |
8bcc2795 | 7506 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 7507 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
7508 | /* |
7509 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7510 | * on 830. Filter it out here so that we don't | |
7511 | * report errors due to that. | |
7512 | */ | |
50a0bc90 | 7513 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
7514 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
7515 | ||
8bcc2795 DV |
7516 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7517 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7518 | } else { |
7519 | /* Mask out read-only status bits. */ | |
7520 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7521 | DPLL_PORTC_READY_MASK | | |
7522 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7523 | } |
6c49f241 | 7524 | |
920a14b2 | 7525 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 7526 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 7527 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
7528 | vlv_crtc_clock_get(crtc, pipe_config); |
7529 | else | |
7530 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7531 | |
0f64614d VS |
7532 | /* |
7533 | * Normally the dotclock is filled in by the encoder .get_config() | |
7534 | * but in case the pipe is enabled w/o any ports we need a sane | |
7535 | * default. | |
7536 | */ | |
7537 | pipe_config->base.adjusted_mode.crtc_clock = | |
7538 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
7539 | ||
1729050e ID |
7540 | ret = true; |
7541 | ||
7542 | out: | |
7543 | intel_display_power_put(dev_priv, power_domain); | |
7544 | ||
7545 | return ret; | |
0e8ffe1b DV |
7546 | } |
7547 | ||
c39055b0 | 7548 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 7549 | { |
13d83a67 | 7550 | struct intel_encoder *encoder; |
1c1a24d2 | 7551 | int i; |
74cfd7ac | 7552 | u32 val, final; |
13d83a67 | 7553 | bool has_lvds = false; |
199e5d79 | 7554 | bool has_cpu_edp = false; |
199e5d79 | 7555 | bool has_panel = false; |
99eb6a01 KP |
7556 | bool has_ck505 = false; |
7557 | bool can_ssc = false; | |
1c1a24d2 | 7558 | bool using_ssc_source = false; |
13d83a67 JB |
7559 | |
7560 | /* We need to take the global config into account */ | |
c39055b0 | 7561 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
7562 | switch (encoder->type) { |
7563 | case INTEL_OUTPUT_LVDS: | |
7564 | has_panel = true; | |
7565 | has_lvds = true; | |
7566 | break; | |
7567 | case INTEL_OUTPUT_EDP: | |
7568 | has_panel = true; | |
2de6905f | 7569 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7570 | has_cpu_edp = true; |
7571 | break; | |
6847d71b PZ |
7572 | default: |
7573 | break; | |
13d83a67 JB |
7574 | } |
7575 | } | |
7576 | ||
6e266956 | 7577 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 7578 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7579 | can_ssc = has_ck505; |
7580 | } else { | |
7581 | has_ck505 = false; | |
7582 | can_ssc = true; | |
7583 | } | |
7584 | ||
1c1a24d2 L |
7585 | /* Check if any DPLLs are using the SSC source */ |
7586 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
7587 | u32 temp = I915_READ(PCH_DPLL(i)); | |
7588 | ||
7589 | if (!(temp & DPLL_VCO_ENABLE)) | |
7590 | continue; | |
7591 | ||
7592 | if ((temp & PLL_REF_INPUT_MASK) == | |
7593 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7594 | using_ssc_source = true; | |
7595 | break; | |
7596 | } | |
7597 | } | |
7598 | ||
7599 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
7600 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
7601 | |
7602 | /* Ironlake: try to setup display ref clock before DPLL | |
7603 | * enabling. This is only under driver's control after | |
7604 | * PCH B stepping, previous chipset stepping should be | |
7605 | * ignoring this setting. | |
7606 | */ | |
74cfd7ac CW |
7607 | val = I915_READ(PCH_DREF_CONTROL); |
7608 | ||
7609 | /* As we must carefully and slowly disable/enable each source in turn, | |
7610 | * compute the final state we want first and check if we need to | |
7611 | * make any changes at all. | |
7612 | */ | |
7613 | final = val; | |
7614 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7615 | if (has_ck505) | |
7616 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7617 | else | |
7618 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7619 | ||
8c07eb68 | 7620 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 7621 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 7622 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
7623 | |
7624 | if (has_panel) { | |
7625 | final |= DREF_SSC_SOURCE_ENABLE; | |
7626 | ||
7627 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7628 | final |= DREF_SSC1_ENABLE; | |
7629 | ||
7630 | if (has_cpu_edp) { | |
7631 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7632 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7633 | else | |
7634 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7635 | } else | |
7636 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
7637 | } else if (using_ssc_source) { |
7638 | final |= DREF_SSC_SOURCE_ENABLE; | |
7639 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
7640 | } |
7641 | ||
7642 | if (final == val) | |
7643 | return; | |
7644 | ||
13d83a67 | 7645 | /* Always enable nonspread source */ |
74cfd7ac | 7646 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7647 | |
99eb6a01 | 7648 | if (has_ck505) |
74cfd7ac | 7649 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7650 | else |
74cfd7ac | 7651 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7652 | |
199e5d79 | 7653 | if (has_panel) { |
74cfd7ac CW |
7654 | val &= ~DREF_SSC_SOURCE_MASK; |
7655 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7656 | |
199e5d79 | 7657 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7658 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7659 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7660 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7661 | } else |
74cfd7ac | 7662 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7663 | |
7664 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7665 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7666 | POSTING_READ(PCH_DREF_CONTROL); |
7667 | udelay(200); | |
7668 | ||
74cfd7ac | 7669 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7670 | |
7671 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7672 | if (has_cpu_edp) { |
99eb6a01 | 7673 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7674 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7675 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7676 | } else |
74cfd7ac | 7677 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7678 | } else |
74cfd7ac | 7679 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7680 | |
74cfd7ac | 7681 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7682 | POSTING_READ(PCH_DREF_CONTROL); |
7683 | udelay(200); | |
7684 | } else { | |
1c1a24d2 | 7685 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 7686 | |
74cfd7ac | 7687 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7688 | |
7689 | /* Turn off CPU output */ | |
74cfd7ac | 7690 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7691 | |
74cfd7ac | 7692 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7693 | POSTING_READ(PCH_DREF_CONTROL); |
7694 | udelay(200); | |
7695 | ||
1c1a24d2 L |
7696 | if (!using_ssc_source) { |
7697 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 7698 | |
1c1a24d2 L |
7699 | /* Turn off the SSC source */ |
7700 | val &= ~DREF_SSC_SOURCE_MASK; | |
7701 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 7702 | |
1c1a24d2 L |
7703 | /* Turn off SSC1 */ |
7704 | val &= ~DREF_SSC1_ENABLE; | |
7705 | ||
7706 | I915_WRITE(PCH_DREF_CONTROL, val); | |
7707 | POSTING_READ(PCH_DREF_CONTROL); | |
7708 | udelay(200); | |
7709 | } | |
13d83a67 | 7710 | } |
74cfd7ac CW |
7711 | |
7712 | BUG_ON(val != final); | |
13d83a67 JB |
7713 | } |
7714 | ||
f31f2d55 | 7715 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7716 | { |
f31f2d55 | 7717 | uint32_t tmp; |
dde86e2d | 7718 | |
0ff066a9 PZ |
7719 | tmp = I915_READ(SOUTH_CHICKEN2); |
7720 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7721 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7722 | |
cf3598c2 ID |
7723 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
7724 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 7725 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 7726 | |
0ff066a9 PZ |
7727 | tmp = I915_READ(SOUTH_CHICKEN2); |
7728 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7729 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7730 | |
cf3598c2 ID |
7731 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
7732 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 7733 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
7734 | } |
7735 | ||
7736 | /* WaMPhyProgramming:hsw */ | |
7737 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7738 | { | |
7739 | uint32_t tmp; | |
dde86e2d PZ |
7740 | |
7741 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7742 | tmp &= ~(0xFF << 24); | |
7743 | tmp |= (0x12 << 24); | |
7744 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7745 | ||
dde86e2d PZ |
7746 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7747 | tmp |= (1 << 11); | |
7748 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7749 | ||
7750 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7751 | tmp |= (1 << 11); | |
7752 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7753 | ||
dde86e2d PZ |
7754 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7755 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7756 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7757 | ||
7758 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7759 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7760 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7761 | ||
0ff066a9 PZ |
7762 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7763 | tmp &= ~(7 << 13); | |
7764 | tmp |= (5 << 13); | |
7765 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7766 | |
0ff066a9 PZ |
7767 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7768 | tmp &= ~(7 << 13); | |
7769 | tmp |= (5 << 13); | |
7770 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7771 | |
7772 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7773 | tmp &= ~0xFF; | |
7774 | tmp |= 0x1C; | |
7775 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7776 | ||
7777 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7778 | tmp &= ~0xFF; | |
7779 | tmp |= 0x1C; | |
7780 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7781 | ||
7782 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7783 | tmp &= ~(0xFF << 16); | |
7784 | tmp |= (0x1C << 16); | |
7785 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7786 | ||
7787 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7788 | tmp &= ~(0xFF << 16); | |
7789 | tmp |= (0x1C << 16); | |
7790 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7791 | ||
0ff066a9 PZ |
7792 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7793 | tmp |= (1 << 27); | |
7794 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7795 | |
0ff066a9 PZ |
7796 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7797 | tmp |= (1 << 27); | |
7798 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7799 | |
0ff066a9 PZ |
7800 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7801 | tmp &= ~(0xF << 28); | |
7802 | tmp |= (4 << 28); | |
7803 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7804 | |
0ff066a9 PZ |
7805 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7806 | tmp &= ~(0xF << 28); | |
7807 | tmp |= (4 << 28); | |
7808 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7809 | } |
7810 | ||
2fa86a1f PZ |
7811 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7812 | * Programming" based on the parameters passed: | |
7813 | * - Sequence to enable CLKOUT_DP | |
7814 | * - Sequence to enable CLKOUT_DP without spread | |
7815 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7816 | */ | |
c39055b0 ACO |
7817 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
7818 | bool with_spread, bool with_fdi) | |
f31f2d55 | 7819 | { |
2fa86a1f PZ |
7820 | uint32_t reg, tmp; |
7821 | ||
7822 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7823 | with_spread = true; | |
4f8036a2 TU |
7824 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
7825 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 7826 | with_fdi = false; |
f31f2d55 | 7827 | |
a580516d | 7828 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
7829 | |
7830 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7831 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7832 | tmp |= SBI_SSCCTL_PATHALT; | |
7833 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7834 | ||
7835 | udelay(24); | |
7836 | ||
2fa86a1f PZ |
7837 | if (with_spread) { |
7838 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7839 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7840 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7841 | |
2fa86a1f PZ |
7842 | if (with_fdi) { |
7843 | lpt_reset_fdi_mphy(dev_priv); | |
7844 | lpt_program_fdi_mphy(dev_priv); | |
7845 | } | |
7846 | } | |
dde86e2d | 7847 | |
4f8036a2 | 7848 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
7849 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7850 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7851 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 7852 | |
a580516d | 7853 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
7854 | } |
7855 | ||
47701c3b | 7856 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 7857 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 7858 | { |
47701c3b PZ |
7859 | uint32_t reg, tmp; |
7860 | ||
a580516d | 7861 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 7862 | |
4f8036a2 | 7863 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
7864 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7865 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7866 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7867 | ||
7868 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7869 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7870 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7871 | tmp |= SBI_SSCCTL_PATHALT; | |
7872 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7873 | udelay(32); | |
7874 | } | |
7875 | tmp |= SBI_SSCCTL_DISABLE; | |
7876 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7877 | } | |
7878 | ||
a580516d | 7879 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
7880 | } |
7881 | ||
f7be2c21 VS |
7882 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
7883 | ||
7884 | static const uint16_t sscdivintphase[] = { | |
7885 | [BEND_IDX( 50)] = 0x3B23, | |
7886 | [BEND_IDX( 45)] = 0x3B23, | |
7887 | [BEND_IDX( 40)] = 0x3C23, | |
7888 | [BEND_IDX( 35)] = 0x3C23, | |
7889 | [BEND_IDX( 30)] = 0x3D23, | |
7890 | [BEND_IDX( 25)] = 0x3D23, | |
7891 | [BEND_IDX( 20)] = 0x3E23, | |
7892 | [BEND_IDX( 15)] = 0x3E23, | |
7893 | [BEND_IDX( 10)] = 0x3F23, | |
7894 | [BEND_IDX( 5)] = 0x3F23, | |
7895 | [BEND_IDX( 0)] = 0x0025, | |
7896 | [BEND_IDX( -5)] = 0x0025, | |
7897 | [BEND_IDX(-10)] = 0x0125, | |
7898 | [BEND_IDX(-15)] = 0x0125, | |
7899 | [BEND_IDX(-20)] = 0x0225, | |
7900 | [BEND_IDX(-25)] = 0x0225, | |
7901 | [BEND_IDX(-30)] = 0x0325, | |
7902 | [BEND_IDX(-35)] = 0x0325, | |
7903 | [BEND_IDX(-40)] = 0x0425, | |
7904 | [BEND_IDX(-45)] = 0x0425, | |
7905 | [BEND_IDX(-50)] = 0x0525, | |
7906 | }; | |
7907 | ||
7908 | /* | |
7909 | * Bend CLKOUT_DP | |
7910 | * steps -50 to 50 inclusive, in steps of 5 | |
7911 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
7912 | * change in clock period = -(steps / 10) * 5.787 ps | |
7913 | */ | |
7914 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
7915 | { | |
7916 | uint32_t tmp; | |
7917 | int idx = BEND_IDX(steps); | |
7918 | ||
7919 | if (WARN_ON(steps % 5 != 0)) | |
7920 | return; | |
7921 | ||
7922 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
7923 | return; | |
7924 | ||
7925 | mutex_lock(&dev_priv->sb_lock); | |
7926 | ||
7927 | if (steps % 10 != 0) | |
7928 | tmp = 0xAAAAAAAB; | |
7929 | else | |
7930 | tmp = 0x00000000; | |
7931 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
7932 | ||
7933 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
7934 | tmp &= 0xffff0000; | |
7935 | tmp |= sscdivintphase[idx]; | |
7936 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
7937 | ||
7938 | mutex_unlock(&dev_priv->sb_lock); | |
7939 | } | |
7940 | ||
7941 | #undef BEND_IDX | |
7942 | ||
c39055b0 | 7943 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 7944 | { |
bf8fa3d3 PZ |
7945 | struct intel_encoder *encoder; |
7946 | bool has_vga = false; | |
7947 | ||
c39055b0 | 7948 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
7949 | switch (encoder->type) { |
7950 | case INTEL_OUTPUT_ANALOG: | |
7951 | has_vga = true; | |
7952 | break; | |
6847d71b PZ |
7953 | default: |
7954 | break; | |
bf8fa3d3 PZ |
7955 | } |
7956 | } | |
7957 | ||
f7be2c21 | 7958 | if (has_vga) { |
c39055b0 ACO |
7959 | lpt_bend_clkout_dp(dev_priv, 0); |
7960 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 7961 | } else { |
c39055b0 | 7962 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 7963 | } |
bf8fa3d3 PZ |
7964 | } |
7965 | ||
dde86e2d PZ |
7966 | /* |
7967 | * Initialize reference clocks when the driver loads | |
7968 | */ | |
c39055b0 | 7969 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 7970 | { |
6e266956 | 7971 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 7972 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 7973 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 7974 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
7975 | } |
7976 | ||
6ff93609 | 7977 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7978 | { |
fac5e23e | 7979 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
7980 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7981 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7982 | uint32_t val; |
7983 | ||
78114071 | 7984 | val = 0; |
c8203565 | 7985 | |
6e3c9717 | 7986 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7987 | case 18: |
dfd07d72 | 7988 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7989 | break; |
7990 | case 24: | |
dfd07d72 | 7991 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7992 | break; |
7993 | case 30: | |
dfd07d72 | 7994 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7995 | break; |
7996 | case 36: | |
dfd07d72 | 7997 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7998 | break; |
7999 | default: | |
cc769b62 PZ |
8000 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8001 | BUG(); | |
c8203565 PZ |
8002 | } |
8003 | ||
6e3c9717 | 8004 | if (intel_crtc->config->dither) |
c8203565 PZ |
8005 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8006 | ||
6e3c9717 | 8007 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8008 | val |= PIPECONF_INTERLACED_ILK; |
8009 | else | |
8010 | val |= PIPECONF_PROGRESSIVE; | |
8011 | ||
6e3c9717 | 8012 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8013 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8014 | |
c8203565 PZ |
8015 | I915_WRITE(PIPECONF(pipe), val); |
8016 | POSTING_READ(PIPECONF(pipe)); | |
8017 | } | |
8018 | ||
6ff93609 | 8019 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8020 | { |
fac5e23e | 8021 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8022 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8023 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8024 | u32 val = 0; |
ee2b0b38 | 8025 | |
391bf048 | 8026 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8027 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8028 | ||
6e3c9717 | 8029 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8030 | val |= PIPECONF_INTERLACED_ILK; |
8031 | else | |
8032 | val |= PIPECONF_PROGRESSIVE; | |
8033 | ||
702e7a56 PZ |
8034 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8035 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8036 | } |
8037 | ||
391bf048 JN |
8038 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8039 | { | |
fac5e23e | 8040 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8041 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8042 | |
391bf048 JN |
8043 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8044 | u32 val = 0; | |
756f85cf | 8045 | |
6e3c9717 | 8046 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8047 | case 18: |
8048 | val |= PIPEMISC_DITHER_6_BPC; | |
8049 | break; | |
8050 | case 24: | |
8051 | val |= PIPEMISC_DITHER_8_BPC; | |
8052 | break; | |
8053 | case 30: | |
8054 | val |= PIPEMISC_DITHER_10_BPC; | |
8055 | break; | |
8056 | case 36: | |
8057 | val |= PIPEMISC_DITHER_12_BPC; | |
8058 | break; | |
8059 | default: | |
8060 | /* Case prevented by pipe_config_set_bpp. */ | |
8061 | BUG(); | |
8062 | } | |
8063 | ||
6e3c9717 | 8064 | if (intel_crtc->config->dither) |
756f85cf PZ |
8065 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8066 | ||
391bf048 | 8067 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8068 | } |
ee2b0b38 PZ |
8069 | } |
8070 | ||
d4b1931c PZ |
8071 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8072 | { | |
8073 | /* | |
8074 | * Account for spread spectrum to avoid | |
8075 | * oversubscribing the link. Max center spread | |
8076 | * is 2.5%; use 5% for safety's sake. | |
8077 | */ | |
8078 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8079 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8080 | } |
8081 | ||
7429e9d4 | 8082 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8083 | { |
7429e9d4 | 8084 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8085 | } |
8086 | ||
b75ca6f6 ACO |
8087 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8088 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8089 | struct dpll *reduced_clock) |
79e53945 | 8090 | { |
de13a2e3 | 8091 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8092 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8093 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8094 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8095 | int factor; |
79e53945 | 8096 | |
c1858123 | 8097 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8098 | factor = 21; |
3d6e9ee0 | 8099 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8100 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8101 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 8102 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8103 | factor = 25; |
190f68c5 | 8104 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8105 | factor = 20; |
c1858123 | 8106 | |
b75ca6f6 ACO |
8107 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8108 | ||
190f68c5 | 8109 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8110 | fp |= FP_CB_TUNE; |
8111 | ||
8112 | if (reduced_clock) { | |
8113 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8114 | |
b75ca6f6 ACO |
8115 | if (reduced_clock->m < factor * reduced_clock->n) |
8116 | fp2 |= FP_CB_TUNE; | |
8117 | } else { | |
8118 | fp2 = fp; | |
8119 | } | |
9a7c7890 | 8120 | |
5eddb70b | 8121 | dpll = 0; |
2c07245f | 8122 | |
3d6e9ee0 | 8123 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8124 | dpll |= DPLLB_MODE_LVDS; |
8125 | else | |
8126 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8127 | |
190f68c5 | 8128 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8129 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8130 | |
3d6e9ee0 VS |
8131 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8132 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8133 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8134 | |
37a5650b | 8135 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8136 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8137 | |
7d7f8633 VS |
8138 | /* |
8139 | * The high speed IO clock is only really required for | |
8140 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
8141 | * possible to share the DPLL between CRT and HDMI. Enabling | |
8142 | * the clock needlessly does no real harm, except use up a | |
8143 | * bit of power potentially. | |
8144 | * | |
8145 | * We'll limit this to IVB with 3 pipes, since it has only two | |
8146 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
8147 | * driving PCH ports at the same time. On SNB we could do this, | |
8148 | * and potentially avoid enabling the second DPLL, but it's not | |
8149 | * clear if it''s a win or loss power wise. No point in doing | |
8150 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
8151 | */ | |
8152 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
8153 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
8154 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8155 | ||
a07d6787 | 8156 | /* compute bitmask from p1 value */ |
190f68c5 | 8157 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8158 | /* also FPA1 */ |
190f68c5 | 8159 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8160 | |
190f68c5 | 8161 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8162 | case 5: |
8163 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8164 | break; | |
8165 | case 7: | |
8166 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8167 | break; | |
8168 | case 10: | |
8169 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8170 | break; | |
8171 | case 14: | |
8172 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8173 | break; | |
79e53945 JB |
8174 | } |
8175 | ||
3d6e9ee0 VS |
8176 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8177 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8178 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8179 | else |
8180 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8181 | ||
b75ca6f6 ACO |
8182 | dpll |= DPLL_VCO_ENABLE; |
8183 | ||
8184 | crtc_state->dpll_hw_state.dpll = dpll; | |
8185 | crtc_state->dpll_hw_state.fp0 = fp; | |
8186 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8187 | } |
8188 | ||
190f68c5 ACO |
8189 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8190 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8191 | { |
997c030c | 8192 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8193 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 8194 | struct dpll reduced_clock; |
7ed9f894 | 8195 | bool has_reduced_clock = false; |
e2b78267 | 8196 | struct intel_shared_dpll *pll; |
1b6f4958 | 8197 | const struct intel_limit *limit; |
997c030c | 8198 | int refclk = 120000; |
de13a2e3 | 8199 | |
dd3cd74a ACO |
8200 | memset(&crtc_state->dpll_hw_state, 0, |
8201 | sizeof(crtc_state->dpll_hw_state)); | |
8202 | ||
ded220e2 ACO |
8203 | crtc->lowfreq_avail = false; |
8204 | ||
8205 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8206 | if (!crtc_state->has_pch_encoder) | |
8207 | return 0; | |
79e53945 | 8208 | |
2d84d2b3 | 8209 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8210 | if (intel_panel_use_ssc(dev_priv)) { |
8211 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8212 | dev_priv->vbt.lvds_ssc_freq); | |
8213 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8214 | } | |
8215 | ||
8216 | if (intel_is_dual_link_lvds(dev)) { | |
8217 | if (refclk == 100000) | |
8218 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8219 | else | |
8220 | limit = &intel_limits_ironlake_dual_lvds; | |
8221 | } else { | |
8222 | if (refclk == 100000) | |
8223 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8224 | else | |
8225 | limit = &intel_limits_ironlake_single_lvds; | |
8226 | } | |
8227 | } else { | |
8228 | limit = &intel_limits_ironlake_dac; | |
8229 | } | |
8230 | ||
364ee29d | 8231 | if (!crtc_state->clock_set && |
997c030c ACO |
8232 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8233 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8234 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8235 | return -EINVAL; | |
f47709a9 | 8236 | } |
79e53945 | 8237 | |
b75ca6f6 ACO |
8238 | ironlake_compute_dpll(crtc, crtc_state, |
8239 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 8240 | |
ded220e2 ACO |
8241 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
8242 | if (pll == NULL) { | |
8243 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8244 | pipe_name(crtc->pipe)); | |
8245 | return -EINVAL; | |
3fb37703 | 8246 | } |
79e53945 | 8247 | |
2d84d2b3 | 8248 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 8249 | has_reduced_clock) |
c7653199 | 8250 | crtc->lowfreq_avail = true; |
e2b78267 | 8251 | |
c8f7a0db | 8252 | return 0; |
79e53945 JB |
8253 | } |
8254 | ||
eb14cb74 VS |
8255 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8256 | struct intel_link_m_n *m_n) | |
8257 | { | |
8258 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8259 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
8260 | enum pipe pipe = crtc->pipe; |
8261 | ||
8262 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8263 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8264 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8265 | & ~TU_SIZE_MASK; | |
8266 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8267 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8268 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8269 | } | |
8270 | ||
8271 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8272 | enum transcoder transcoder, | |
b95af8be VK |
8273 | struct intel_link_m_n *m_n, |
8274 | struct intel_link_m_n *m2_n2) | |
72419203 | 8275 | { |
6315b5d3 | 8276 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 8277 | enum pipe pipe = crtc->pipe; |
72419203 | 8278 | |
6315b5d3 | 8279 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
8280 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
8281 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8282 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8283 | & ~TU_SIZE_MASK; | |
8284 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8285 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8286 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8287 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8288 | * gen < 8) and if DRRS is supported (to make sure the | |
8289 | * registers are not unnecessarily read). | |
8290 | */ | |
6315b5d3 | 8291 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 8292 | crtc->config->has_drrs) { |
b95af8be VK |
8293 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8294 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8295 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8296 | & ~TU_SIZE_MASK; | |
8297 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8298 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8299 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8300 | } | |
eb14cb74 VS |
8301 | } else { |
8302 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8303 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8304 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8305 | & ~TU_SIZE_MASK; | |
8306 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8307 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8308 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8309 | } | |
8310 | } | |
8311 | ||
8312 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8313 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8314 | { |
681a8504 | 8315 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8316 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8317 | else | |
8318 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8319 | &pipe_config->dp_m_n, |
8320 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8321 | } |
72419203 | 8322 | |
eb14cb74 | 8323 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8324 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8325 | { |
8326 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8327 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8328 | } |
8329 | ||
bd2e244f | 8330 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8331 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8332 | { |
8333 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8334 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
8335 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8336 | uint32_t ps_ctrl = 0; | |
8337 | int id = -1; | |
8338 | int i; | |
bd2e244f | 8339 | |
a1b2278e CK |
8340 | /* find scaler attached to this pipe */ |
8341 | for (i = 0; i < crtc->num_scalers; i++) { | |
8342 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8343 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8344 | id = i; | |
8345 | pipe_config->pch_pfit.enabled = true; | |
8346 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8347 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8348 | break; | |
8349 | } | |
8350 | } | |
bd2e244f | 8351 | |
a1b2278e CK |
8352 | scaler_state->scaler_id = id; |
8353 | if (id >= 0) { | |
8354 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8355 | } else { | |
8356 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8357 | } |
8358 | } | |
8359 | ||
5724dbd1 DL |
8360 | static void |
8361 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8362 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8363 | { |
8364 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8365 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 8366 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8367 | int pipe = crtc->pipe; |
8368 | int fourcc, pixel_format; | |
6761dd31 | 8369 | unsigned int aligned_height; |
bc8d7dff | 8370 | struct drm_framebuffer *fb; |
1b842c89 | 8371 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8372 | |
d9806c9f | 8373 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8374 | if (!intel_fb) { |
bc8d7dff DL |
8375 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8376 | return; | |
8377 | } | |
8378 | ||
1b842c89 DL |
8379 | fb = &intel_fb->base; |
8380 | ||
d2e9f5fc VS |
8381 | fb->dev = dev; |
8382 | ||
bc8d7dff | 8383 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8384 | if (!(val & PLANE_CTL_ENABLE)) |
8385 | goto error; | |
8386 | ||
bc8d7dff DL |
8387 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8388 | fourcc = skl_format_to_fourcc(pixel_format, | |
8389 | val & PLANE_CTL_ORDER_RGBX, | |
8390 | val & PLANE_CTL_ALPHA_MASK); | |
2f3f4763 | 8391 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 8392 | |
40f46283 DL |
8393 | tiling = val & PLANE_CTL_TILED_MASK; |
8394 | switch (tiling) { | |
8395 | case PLANE_CTL_TILED_LINEAR: | |
bae781b2 | 8396 | fb->modifier = DRM_FORMAT_MOD_NONE; |
40f46283 DL |
8397 | break; |
8398 | case PLANE_CTL_TILED_X: | |
8399 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 8400 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
8401 | break; |
8402 | case PLANE_CTL_TILED_Y: | |
bae781b2 | 8403 | fb->modifier = I915_FORMAT_MOD_Y_TILED; |
40f46283 DL |
8404 | break; |
8405 | case PLANE_CTL_TILED_YF: | |
bae781b2 | 8406 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; |
40f46283 DL |
8407 | break; |
8408 | default: | |
8409 | MISSING_CASE(tiling); | |
8410 | goto error; | |
8411 | } | |
8412 | ||
bc8d7dff DL |
8413 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8414 | plane_config->base = base; | |
8415 | ||
8416 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8417 | ||
8418 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8419 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8420 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8421 | ||
8422 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
bae781b2 | 8423 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier, |
438b74a5 | 8424 | fb->format->format); |
bc8d7dff DL |
8425 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8426 | ||
24dbf51a CW |
8427 | aligned_height = intel_fb_align_height(dev_priv, |
8428 | fb->height, | |
438b74a5 | 8429 | fb->format->format, |
bae781b2 | 8430 | fb->modifier); |
bc8d7dff | 8431 | |
f37b5c2b | 8432 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8433 | |
8434 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8435 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8436 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
bc8d7dff DL |
8437 | plane_config->size); |
8438 | ||
2d14030b | 8439 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8440 | return; |
8441 | ||
8442 | error: | |
d1a3a036 | 8443 | kfree(intel_fb); |
bc8d7dff DL |
8444 | } |
8445 | ||
2fa2fe9a | 8446 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8447 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8448 | { |
8449 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8450 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8451 | uint32_t tmp; |
8452 | ||
8453 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8454 | ||
8455 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8456 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8457 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8458 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8459 | |
8460 | /* We currently do not free assignements of panel fitters on | |
8461 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8462 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 8463 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
8464 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
8465 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8466 | } | |
2fa2fe9a | 8467 | } |
79e53945 JB |
8468 | } |
8469 | ||
5724dbd1 DL |
8470 | static void |
8471 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8472 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8473 | { |
8474 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8475 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 8476 | u32 val, base, offset; |
aeee5a49 | 8477 | int pipe = crtc->pipe; |
4c6baa59 | 8478 | int fourcc, pixel_format; |
6761dd31 | 8479 | unsigned int aligned_height; |
b113d5ee | 8480 | struct drm_framebuffer *fb; |
1b842c89 | 8481 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8482 | |
42a7b088 DL |
8483 | val = I915_READ(DSPCNTR(pipe)); |
8484 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8485 | return; | |
8486 | ||
d9806c9f | 8487 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8488 | if (!intel_fb) { |
4c6baa59 JB |
8489 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8490 | return; | |
8491 | } | |
8492 | ||
1b842c89 DL |
8493 | fb = &intel_fb->base; |
8494 | ||
d2e9f5fc VS |
8495 | fb->dev = dev; |
8496 | ||
6315b5d3 | 8497 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8498 | if (val & DISPPLANE_TILED) { |
49af449b | 8499 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8500 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8501 | } |
8502 | } | |
4c6baa59 JB |
8503 | |
8504 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8505 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 8506 | fb->format = drm_format_info(fourcc); |
4c6baa59 | 8507 | |
aeee5a49 | 8508 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 8509 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 8510 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8511 | } else { |
49af449b | 8512 | if (plane_config->tiling) |
aeee5a49 | 8513 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8514 | else |
aeee5a49 | 8515 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8516 | } |
8517 | plane_config->base = base; | |
8518 | ||
8519 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8520 | fb->width = ((val >> 16) & 0xfff) + 1; |
8521 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8522 | |
8523 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8524 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8525 | |
24dbf51a CW |
8526 | aligned_height = intel_fb_align_height(dev_priv, |
8527 | fb->height, | |
438b74a5 | 8528 | fb->format->format, |
bae781b2 | 8529 | fb->modifier); |
4c6baa59 | 8530 | |
f37b5c2b | 8531 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8532 | |
2844a921 DL |
8533 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8534 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8535 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 8536 | plane_config->size); |
b113d5ee | 8537 | |
2d14030b | 8538 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8539 | } |
8540 | ||
0e8ffe1b | 8541 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8542 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8543 | { |
8544 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8545 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8546 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8547 | uint32_t tmp; |
1729050e | 8548 | bool ret; |
0e8ffe1b | 8549 | |
1729050e ID |
8550 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8551 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
8552 | return false; |
8553 | ||
e143a21c | 8554 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8555 | pipe_config->shared_dpll = NULL; |
eccb140b | 8556 | |
1729050e | 8557 | ret = false; |
0e8ffe1b DV |
8558 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8559 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8560 | goto out; |
0e8ffe1b | 8561 | |
42571aef VS |
8562 | switch (tmp & PIPECONF_BPC_MASK) { |
8563 | case PIPECONF_6BPC: | |
8564 | pipe_config->pipe_bpp = 18; | |
8565 | break; | |
8566 | case PIPECONF_8BPC: | |
8567 | pipe_config->pipe_bpp = 24; | |
8568 | break; | |
8569 | case PIPECONF_10BPC: | |
8570 | pipe_config->pipe_bpp = 30; | |
8571 | break; | |
8572 | case PIPECONF_12BPC: | |
8573 | pipe_config->pipe_bpp = 36; | |
8574 | break; | |
8575 | default: | |
8576 | break; | |
8577 | } | |
8578 | ||
b5a9fa09 DV |
8579 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8580 | pipe_config->limited_color_range = true; | |
8581 | ||
ab9412ba | 8582 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 8583 | struct intel_shared_dpll *pll; |
8106ddbd | 8584 | enum intel_dpll_id pll_id; |
66e985c0 | 8585 | |
88adfff1 DV |
8586 | pipe_config->has_pch_encoder = true; |
8587 | ||
627eb5a3 DV |
8588 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8589 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8590 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8591 | |
8592 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8593 | |
2d1fe073 | 8594 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
8595 | /* |
8596 | * The pipe->pch transcoder and pch transcoder->pll | |
8597 | * mapping is fixed. | |
8598 | */ | |
8106ddbd | 8599 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
8600 | } else { |
8601 | tmp = I915_READ(PCH_DPLL_SEL); | |
8602 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 8603 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 8604 | else |
8106ddbd | 8605 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 8606 | } |
66e985c0 | 8607 | |
8106ddbd ACO |
8608 | pipe_config->shared_dpll = |
8609 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
8610 | pll = pipe_config->shared_dpll; | |
66e985c0 | 8611 | |
2edd6443 ACO |
8612 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8613 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8614 | |
8615 | tmp = pipe_config->dpll_hw_state.dpll; | |
8616 | pipe_config->pixel_multiplier = | |
8617 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8618 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8619 | |
8620 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8621 | } else { |
8622 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8623 | } |
8624 | ||
1bd1bd80 | 8625 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8626 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8627 | |
2fa2fe9a DV |
8628 | ironlake_get_pfit_config(crtc, pipe_config); |
8629 | ||
1729050e ID |
8630 | ret = true; |
8631 | ||
8632 | out: | |
8633 | intel_display_power_put(dev_priv, power_domain); | |
8634 | ||
8635 | return ret; | |
0e8ffe1b DV |
8636 | } |
8637 | ||
be256dc7 PZ |
8638 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8639 | { | |
91c8a326 | 8640 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 8641 | struct intel_crtc *crtc; |
be256dc7 | 8642 | |
d3fcc808 | 8643 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8644 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8645 | pipe_name(crtc->pipe)); |
8646 | ||
e2c719b7 RC |
8647 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8648 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
8649 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
8650 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 8651 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 8652 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 8653 | "CPU PWM1 enabled\n"); |
772c2a51 | 8654 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 8655 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8656 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8657 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8658 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8659 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8660 | "Utility pin enabled\n"); |
e2c719b7 | 8661 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8662 | |
9926ada1 PZ |
8663 | /* |
8664 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8665 | * interrupts remain enabled. We used to check for that, but since it's | |
8666 | * gen-specific and since we only disable LCPLL after we fully disable | |
8667 | * the interrupts, the check below should be enough. | |
8668 | */ | |
e2c719b7 | 8669 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8670 | } |
8671 | ||
9ccd5aeb PZ |
8672 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8673 | { | |
772c2a51 | 8674 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
8675 | return I915_READ(D_COMP_HSW); |
8676 | else | |
8677 | return I915_READ(D_COMP_BDW); | |
8678 | } | |
8679 | ||
3c4c9b81 PZ |
8680 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8681 | { | |
772c2a51 | 8682 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
8683 | mutex_lock(&dev_priv->rps.hw_lock); |
8684 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8685 | val)) | |
79cf219a | 8686 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8687 | mutex_unlock(&dev_priv->rps.hw_lock); |
8688 | } else { | |
9ccd5aeb PZ |
8689 | I915_WRITE(D_COMP_BDW, val); |
8690 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8691 | } |
be256dc7 PZ |
8692 | } |
8693 | ||
8694 | /* | |
8695 | * This function implements pieces of two sequences from BSpec: | |
8696 | * - Sequence for display software to disable LCPLL | |
8697 | * - Sequence for display software to allow package C8+ | |
8698 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8699 | * register. Callers should take care of disabling all the display engine | |
8700 | * functions, doing the mode unset, fixing interrupts, etc. | |
8701 | */ | |
6ff58d53 PZ |
8702 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8703 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8704 | { |
8705 | uint32_t val; | |
8706 | ||
8707 | assert_can_disable_lcpll(dev_priv); | |
8708 | ||
8709 | val = I915_READ(LCPLL_CTL); | |
8710 | ||
8711 | if (switch_to_fclk) { | |
8712 | val |= LCPLL_CD_SOURCE_FCLK; | |
8713 | I915_WRITE(LCPLL_CTL, val); | |
8714 | ||
f53dd63f ID |
8715 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
8716 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
8717 | DRM_ERROR("Switching to FCLK failed\n"); |
8718 | ||
8719 | val = I915_READ(LCPLL_CTL); | |
8720 | } | |
8721 | ||
8722 | val |= LCPLL_PLL_DISABLE; | |
8723 | I915_WRITE(LCPLL_CTL, val); | |
8724 | POSTING_READ(LCPLL_CTL); | |
8725 | ||
24d8441d | 8726 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
8727 | DRM_ERROR("LCPLL still locked\n"); |
8728 | ||
9ccd5aeb | 8729 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8730 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8731 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8732 | ndelay(100); |
8733 | ||
9ccd5aeb PZ |
8734 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8735 | 1)) | |
be256dc7 PZ |
8736 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8737 | ||
8738 | if (allow_power_down) { | |
8739 | val = I915_READ(LCPLL_CTL); | |
8740 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8741 | I915_WRITE(LCPLL_CTL, val); | |
8742 | POSTING_READ(LCPLL_CTL); | |
8743 | } | |
8744 | } | |
8745 | ||
8746 | /* | |
8747 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8748 | * source. | |
8749 | */ | |
6ff58d53 | 8750 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8751 | { |
8752 | uint32_t val; | |
8753 | ||
8754 | val = I915_READ(LCPLL_CTL); | |
8755 | ||
8756 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8757 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8758 | return; | |
8759 | ||
a8a8bd54 PZ |
8760 | /* |
8761 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8762 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8763 | */ |
59bad947 | 8764 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8765 | |
be256dc7 PZ |
8766 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8767 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8768 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8769 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8770 | } |
8771 | ||
9ccd5aeb | 8772 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8773 | val |= D_COMP_COMP_FORCE; |
8774 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8775 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8776 | |
8777 | val = I915_READ(LCPLL_CTL); | |
8778 | val &= ~LCPLL_PLL_DISABLE; | |
8779 | I915_WRITE(LCPLL_CTL, val); | |
8780 | ||
93220c08 CW |
8781 | if (intel_wait_for_register(dev_priv, |
8782 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
8783 | 5)) | |
be256dc7 PZ |
8784 | DRM_ERROR("LCPLL not locked yet\n"); |
8785 | ||
8786 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8787 | val = I915_READ(LCPLL_CTL); | |
8788 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8789 | I915_WRITE(LCPLL_CTL, val); | |
8790 | ||
f53dd63f ID |
8791 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
8792 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
8793 | DRM_ERROR("Switching back to LCPLL failed\n"); |
8794 | } | |
215733fa | 8795 | |
59bad947 | 8796 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 8797 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
8798 | } |
8799 | ||
765dab67 PZ |
8800 | /* |
8801 | * Package states C8 and deeper are really deep PC states that can only be | |
8802 | * reached when all the devices on the system allow it, so even if the graphics | |
8803 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8804 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8805 | * | |
8806 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8807 | * well is disabled and most interrupts are disabled, and these are also | |
8808 | * requirements for runtime PM. When these conditions are met, we manually do | |
8809 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8810 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8811 | * hang the machine. | |
8812 | * | |
8813 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8814 | * the state of some registers, so when we come back from PC8+ we need to | |
8815 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8816 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8817 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8818 | * because of the runtime PM support). | |
8819 | * | |
8820 | * For more, read "Display Sequences for Package C8" on the hardware | |
8821 | * documentation. | |
8822 | */ | |
a14cb6fc | 8823 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8824 | { |
c67a470b PZ |
8825 | uint32_t val; |
8826 | ||
c67a470b PZ |
8827 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8828 | ||
4f8036a2 | 8829 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8830 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8831 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8832 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8833 | } | |
8834 | ||
c39055b0 | 8835 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
8836 | hsw_disable_lcpll(dev_priv, true, true); |
8837 | } | |
8838 | ||
a14cb6fc | 8839 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8840 | { |
c67a470b PZ |
8841 | uint32_t val; |
8842 | ||
c67a470b PZ |
8843 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8844 | ||
8845 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 8846 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 8847 | |
4f8036a2 | 8848 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8849 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8850 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8851 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8852 | } | |
c67a470b PZ |
8853 | } |
8854 | ||
190f68c5 ACO |
8855 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8856 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8857 | { |
d7edc4e5 | 8858 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
8859 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
8860 | return -EINVAL; | |
8861 | } | |
716c2e55 | 8862 | |
c7653199 | 8863 | crtc->lowfreq_avail = false; |
644cef34 | 8864 | |
c8f7a0db | 8865 | return 0; |
79e53945 JB |
8866 | } |
8867 | ||
3760b59c S |
8868 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
8869 | enum port port, | |
8870 | struct intel_crtc_state *pipe_config) | |
8871 | { | |
8106ddbd ACO |
8872 | enum intel_dpll_id id; |
8873 | ||
3760b59c S |
8874 | switch (port) { |
8875 | case PORT_A: | |
08250c4b | 8876 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
8877 | break; |
8878 | case PORT_B: | |
08250c4b | 8879 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
8880 | break; |
8881 | case PORT_C: | |
08250c4b | 8882 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
8883 | break; |
8884 | default: | |
8885 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 8886 | return; |
3760b59c | 8887 | } |
8106ddbd ACO |
8888 | |
8889 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
8890 | } |
8891 | ||
96b7dfb7 S |
8892 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8893 | enum port port, | |
5cec258b | 8894 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8895 | { |
8106ddbd | 8896 | enum intel_dpll_id id; |
a3c988ea | 8897 | u32 temp; |
96b7dfb7 S |
8898 | |
8899 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 8900 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 8901 | |
c856052a | 8902 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 8903 | return; |
8106ddbd ACO |
8904 | |
8905 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
8906 | } |
8907 | ||
7d2c8175 DL |
8908 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8909 | enum port port, | |
5cec258b | 8910 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 8911 | { |
8106ddbd | 8912 | enum intel_dpll_id id; |
c856052a | 8913 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 8914 | |
c856052a | 8915 | switch (ddi_pll_sel) { |
7d2c8175 | 8916 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 8917 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
8918 | break; |
8919 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 8920 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 8921 | break; |
00490c22 | 8922 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 8923 | id = DPLL_ID_SPLL; |
79bd23da | 8924 | break; |
9d16da65 ACO |
8925 | case PORT_CLK_SEL_LCPLL_810: |
8926 | id = DPLL_ID_LCPLL_810; | |
8927 | break; | |
8928 | case PORT_CLK_SEL_LCPLL_1350: | |
8929 | id = DPLL_ID_LCPLL_1350; | |
8930 | break; | |
8931 | case PORT_CLK_SEL_LCPLL_2700: | |
8932 | id = DPLL_ID_LCPLL_2700; | |
8933 | break; | |
8106ddbd | 8934 | default: |
c856052a | 8935 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
8936 | /* fall through */ |
8937 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 8938 | return; |
7d2c8175 | 8939 | } |
8106ddbd ACO |
8940 | |
8941 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
8942 | } |
8943 | ||
cf30429e JN |
8944 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
8945 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8946 | u64 *power_domain_mask) |
cf30429e JN |
8947 | { |
8948 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8949 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
8950 | enum intel_display_power_domain power_domain; |
8951 | u32 tmp; | |
8952 | ||
d9a7bc67 ID |
8953 | /* |
8954 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
8955 | * transcoder handled below. | |
8956 | */ | |
cf30429e JN |
8957 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8958 | ||
8959 | /* | |
8960 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
8961 | * consistency and less surprising code; it's in always on power). | |
8962 | */ | |
8963 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
8964 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8965 | enum pipe trans_edp_pipe; | |
8966 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8967 | default: | |
8968 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8969 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8970 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8971 | trans_edp_pipe = PIPE_A; | |
8972 | break; | |
8973 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8974 | trans_edp_pipe = PIPE_B; | |
8975 | break; | |
8976 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8977 | trans_edp_pipe = PIPE_C; | |
8978 | break; | |
8979 | } | |
8980 | ||
8981 | if (trans_edp_pipe == crtc->pipe) | |
8982 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8983 | } | |
8984 | ||
8985 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
8986 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
8987 | return false; | |
d8fc70b7 | 8988 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e JN |
8989 | |
8990 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
8991 | ||
8992 | return tmp & PIPECONF_ENABLE; | |
8993 | } | |
8994 | ||
4d1de975 JN |
8995 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
8996 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8997 | u64 *power_domain_mask) |
4d1de975 JN |
8998 | { |
8999 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9000 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
9001 | enum intel_display_power_domain power_domain; |
9002 | enum port port; | |
9003 | enum transcoder cpu_transcoder; | |
9004 | u32 tmp; | |
9005 | ||
4d1de975 JN |
9006 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
9007 | if (port == PORT_A) | |
9008 | cpu_transcoder = TRANSCODER_DSI_A; | |
9009 | else | |
9010 | cpu_transcoder = TRANSCODER_DSI_C; | |
9011 | ||
9012 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9013 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9014 | continue; | |
d8fc70b7 | 9015 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 9016 | |
db18b6a6 ID |
9017 | /* |
9018 | * The PLL needs to be enabled with a valid divider | |
9019 | * configuration, otherwise accessing DSI registers will hang | |
9020 | * the machine. See BSpec North Display Engine | |
9021 | * registers/MIPI[BXT]. We can break out here early, since we | |
9022 | * need the same DSI PLL to be enabled for both DSI ports. | |
9023 | */ | |
9024 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9025 | break; | |
9026 | ||
4d1de975 JN |
9027 | /* XXX: this works for video mode only */ |
9028 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9029 | if (!(tmp & DPI_ENABLE)) | |
9030 | continue; | |
9031 | ||
9032 | tmp = I915_READ(MIPI_CTRL(port)); | |
9033 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9034 | continue; | |
9035 | ||
9036 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
9037 | break; |
9038 | } | |
9039 | ||
d7edc4e5 | 9040 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
9041 | } |
9042 | ||
26804afd | 9043 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9044 | struct intel_crtc_state *pipe_config) |
26804afd | 9045 | { |
6315b5d3 | 9046 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 9047 | struct intel_shared_dpll *pll; |
26804afd DV |
9048 | enum port port; |
9049 | uint32_t tmp; | |
9050 | ||
9051 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9052 | ||
9053 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9054 | ||
b976dc53 | 9055 | if (IS_GEN9_BC(dev_priv)) |
96b7dfb7 | 9056 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 9057 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 9058 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
9059 | else |
9060 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9061 | |
8106ddbd ACO |
9062 | pll = pipe_config->shared_dpll; |
9063 | if (pll) { | |
2edd6443 ACO |
9064 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9065 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9066 | } |
9067 | ||
26804afd DV |
9068 | /* |
9069 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9070 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9071 | * the PCH transcoder is on. | |
9072 | */ | |
6315b5d3 | 9073 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 9074 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
9075 | pipe_config->has_pch_encoder = true; |
9076 | ||
9077 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9078 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9079 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9080 | ||
9081 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9082 | } | |
9083 | } | |
9084 | ||
0e8ffe1b | 9085 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9086 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9087 | { |
6315b5d3 | 9088 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9089 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 9090 | u64 power_domain_mask; |
cf30429e | 9091 | bool active; |
0e8ffe1b | 9092 | |
1729050e ID |
9093 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9094 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9095 | return false; |
d8fc70b7 | 9096 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 9097 | |
8106ddbd | 9098 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9099 | |
cf30429e | 9100 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9101 | |
cc3f90f0 | 9102 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
9103 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
9104 | WARN_ON(active); | |
9105 | active = true; | |
4d1de975 JN |
9106 | } |
9107 | ||
cf30429e | 9108 | if (!active) |
1729050e | 9109 | goto out; |
0e8ffe1b | 9110 | |
d7edc4e5 | 9111 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
9112 | haswell_get_ddi_port_state(crtc, pipe_config); |
9113 | intel_get_pipe_timings(crtc, pipe_config); | |
9114 | } | |
627eb5a3 | 9115 | |
bc58be60 | 9116 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9117 | |
05dc698c LL |
9118 | pipe_config->gamma_mode = |
9119 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9120 | ||
6315b5d3 | 9121 | if (INTEL_GEN(dev_priv) >= 9) { |
1c74eeaf | 9122 | intel_crtc_init_scalers(crtc, pipe_config); |
a1b2278e | 9123 | |
af99ceda CK |
9124 | pipe_config->scaler_state.scaler_id = -1; |
9125 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9126 | } | |
9127 | ||
1729050e ID |
9128 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9129 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
d8fc70b7 | 9130 | power_domain_mask |= BIT_ULL(power_domain); |
6315b5d3 | 9131 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 9132 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9133 | else |
1c132b44 | 9134 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9135 | } |
88adfff1 | 9136 | |
772c2a51 | 9137 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
9138 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
9139 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9140 | |
4d1de975 JN |
9141 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9142 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9143 | pipe_config->pixel_multiplier = |
9144 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9145 | } else { | |
9146 | pipe_config->pixel_multiplier = 1; | |
9147 | } | |
6c49f241 | 9148 | |
1729050e ID |
9149 | out: |
9150 | for_each_power_domain(power_domain, power_domain_mask) | |
9151 | intel_display_power_put(dev_priv, power_domain); | |
9152 | ||
cf30429e | 9153 | return active; |
0e8ffe1b DV |
9154 | } |
9155 | ||
55a08b3f ML |
9156 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
9157 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
9158 | { |
9159 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9160 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 9161 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 9162 | uint32_t cntl = 0, size = 0; |
560b85bb | 9163 | |
936e71e3 | 9164 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
9165 | unsigned int width = plane_state->base.crtc_w; |
9166 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
9167 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9168 | ||
9169 | switch (stride) { | |
9170 | default: | |
9171 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9172 | width, stride); | |
9173 | stride = 256; | |
9174 | /* fallthrough */ | |
9175 | case 256: | |
9176 | case 512: | |
9177 | case 1024: | |
9178 | case 2048: | |
9179 | break; | |
4b0e333e CW |
9180 | } |
9181 | ||
dc41c154 VS |
9182 | cntl |= CURSOR_ENABLE | |
9183 | CURSOR_GAMMA_ENABLE | | |
9184 | CURSOR_FORMAT_ARGB | | |
9185 | CURSOR_STRIDE(stride); | |
9186 | ||
9187 | size = (height << 12) | width; | |
4b0e333e | 9188 | } |
560b85bb | 9189 | |
dc41c154 VS |
9190 | if (intel_crtc->cursor_cntl != 0 && |
9191 | (intel_crtc->cursor_base != base || | |
9192 | intel_crtc->cursor_size != size || | |
9193 | intel_crtc->cursor_cntl != cntl)) { | |
9194 | /* On these chipsets we can only modify the base/size/stride | |
9195 | * whilst the cursor is disabled. | |
9196 | */ | |
0b87c24e VS |
9197 | I915_WRITE(CURCNTR(PIPE_A), 0); |
9198 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 9199 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9200 | } |
560b85bb | 9201 | |
99d1f387 | 9202 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 9203 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
9204 | intel_crtc->cursor_base = base; |
9205 | } | |
4726e0b0 | 9206 | |
dc41c154 VS |
9207 | if (intel_crtc->cursor_size != size) { |
9208 | I915_WRITE(CURSIZE, size); | |
9209 | intel_crtc->cursor_size = size; | |
4b0e333e | 9210 | } |
560b85bb | 9211 | |
4b0e333e | 9212 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
9213 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
9214 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 9215 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9216 | } |
560b85bb CW |
9217 | } |
9218 | ||
55a08b3f ML |
9219 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
9220 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
9221 | { |
9222 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9223 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
9224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9225 | int pipe = intel_crtc->pipe; | |
663f3122 | 9226 | uint32_t cntl = 0; |
4b0e333e | 9227 | |
936e71e3 | 9228 | if (plane_state && plane_state->base.visible) { |
4b0e333e | 9229 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 9230 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
9231 | case 64: |
9232 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9233 | break; | |
9234 | case 128: | |
9235 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9236 | break; | |
9237 | case 256: | |
9238 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9239 | break; | |
9240 | default: | |
55a08b3f | 9241 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 9242 | return; |
65a21cd6 | 9243 | } |
4b0e333e | 9244 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 9245 | |
4f8036a2 | 9246 | if (HAS_DDI(dev_priv)) |
47bf17a7 | 9247 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 9248 | |
f22aa143 | 9249 | if (plane_state->base.rotation & DRM_ROTATE_180) |
55a08b3f ML |
9250 | cntl |= CURSOR_ROTATE_180; |
9251 | } | |
4398ad45 | 9252 | |
4b0e333e CW |
9253 | if (intel_crtc->cursor_cntl != cntl) { |
9254 | I915_WRITE(CURCNTR(pipe), cntl); | |
9255 | POSTING_READ(CURCNTR(pipe)); | |
9256 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9257 | } |
4b0e333e | 9258 | |
65a21cd6 | 9259 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9260 | I915_WRITE(CURBASE(pipe), base); |
9261 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9262 | |
9263 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9264 | } |
9265 | ||
cda4b7d3 | 9266 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 9267 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 9268 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
9269 | { |
9270 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9271 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
9272 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9273 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
9274 | u32 base = intel_crtc->cursor_addr; |
9275 | u32 pos = 0; | |
cda4b7d3 | 9276 | |
55a08b3f ML |
9277 | if (plane_state) { |
9278 | int x = plane_state->base.crtc_x; | |
9279 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 9280 | |
55a08b3f ML |
9281 | if (x < 0) { |
9282 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9283 | x = -x; | |
9284 | } | |
9285 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 9286 | |
55a08b3f ML |
9287 | if (y < 0) { |
9288 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9289 | y = -y; | |
9290 | } | |
9291 | pos |= y << CURSOR_Y_SHIFT; | |
9292 | ||
9293 | /* ILK+ do this automagically */ | |
49cff963 | 9294 | if (HAS_GMCH_DISPLAY(dev_priv) && |
f22aa143 | 9295 | plane_state->base.rotation & DRM_ROTATE_180) { |
55a08b3f ML |
9296 | base += (plane_state->base.crtc_h * |
9297 | plane_state->base.crtc_w - 1) * 4; | |
9298 | } | |
cda4b7d3 | 9299 | } |
cda4b7d3 | 9300 | |
5efb3e28 VS |
9301 | I915_WRITE(CURPOS(pipe), pos); |
9302 | ||
2a307c2e | 9303 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
55a08b3f | 9304 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 9305 | else |
55a08b3f | 9306 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
9307 | } |
9308 | ||
50a0bc90 | 9309 | static bool cursor_size_ok(struct drm_i915_private *dev_priv, |
dc41c154 VS |
9310 | uint32_t width, uint32_t height) |
9311 | { | |
9312 | if (width == 0 || height == 0) | |
9313 | return false; | |
9314 | ||
9315 | /* | |
9316 | * 845g/865g are special in that they are only limited by | |
9317 | * the width of their cursors, the height is arbitrary up to | |
9318 | * the precision of the register. Everything else requires | |
9319 | * square cursors, limited to a few power-of-two sizes. | |
9320 | */ | |
2a307c2e | 9321 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
dc41c154 VS |
9322 | if ((width & 63) != 0) |
9323 | return false; | |
9324 | ||
2a307c2e | 9325 | if (width > (IS_I845G(dev_priv) ? 64 : 512)) |
dc41c154 VS |
9326 | return false; |
9327 | ||
9328 | if (height > 1023) | |
9329 | return false; | |
9330 | } else { | |
9331 | switch (width | height) { | |
9332 | case 256: | |
9333 | case 128: | |
50a0bc90 | 9334 | if (IS_GEN2(dev_priv)) |
dc41c154 VS |
9335 | return false; |
9336 | case 64: | |
9337 | break; | |
9338 | default: | |
9339 | return false; | |
9340 | } | |
9341 | } | |
9342 | ||
9343 | return true; | |
9344 | } | |
9345 | ||
79e53945 JB |
9346 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9347 | static struct drm_display_mode load_detect_mode = { | |
9348 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9349 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9350 | }; | |
9351 | ||
a8bb6818 | 9352 | struct drm_framebuffer * |
24dbf51a CW |
9353 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
9354 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
9355 | { |
9356 | struct intel_framebuffer *intel_fb; | |
9357 | int ret; | |
9358 | ||
9359 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 9360 | if (!intel_fb) |
d2dff872 | 9361 | return ERR_PTR(-ENOMEM); |
d2dff872 | 9362 | |
24dbf51a | 9363 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
9364 | if (ret) |
9365 | goto err; | |
d2dff872 CW |
9366 | |
9367 | return &intel_fb->base; | |
dcb1394e | 9368 | |
dd4916c5 | 9369 | err: |
dd4916c5 | 9370 | kfree(intel_fb); |
dd4916c5 | 9371 | return ERR_PTR(ret); |
d2dff872 CW |
9372 | } |
9373 | ||
9374 | static u32 | |
9375 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9376 | { | |
9377 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9378 | return ALIGN(pitch, 64); | |
9379 | } | |
9380 | ||
9381 | static u32 | |
9382 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9383 | { | |
9384 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9385 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9386 | } |
9387 | ||
9388 | static struct drm_framebuffer * | |
9389 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9390 | struct drm_display_mode *mode, | |
9391 | int depth, int bpp) | |
9392 | { | |
dcb1394e | 9393 | struct drm_framebuffer *fb; |
d2dff872 | 9394 | struct drm_i915_gem_object *obj; |
0fed39bd | 9395 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 9396 | |
12d79d78 | 9397 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 9398 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
9399 | if (IS_ERR(obj)) |
9400 | return ERR_CAST(obj); | |
d2dff872 CW |
9401 | |
9402 | mode_cmd.width = mode->hdisplay; | |
9403 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9404 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9405 | bpp); | |
5ca0c34a | 9406 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 9407 | |
24dbf51a | 9408 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 9409 | if (IS_ERR(fb)) |
f0cd5182 | 9410 | i915_gem_object_put(obj); |
dcb1394e LW |
9411 | |
9412 | return fb; | |
d2dff872 CW |
9413 | } |
9414 | ||
9415 | static struct drm_framebuffer * | |
9416 | mode_fits_in_fbdev(struct drm_device *dev, | |
9417 | struct drm_display_mode *mode) | |
9418 | { | |
0695726e | 9419 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 9420 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
9421 | struct drm_i915_gem_object *obj; |
9422 | struct drm_framebuffer *fb; | |
9423 | ||
4c0e5528 | 9424 | if (!dev_priv->fbdev) |
d2dff872 CW |
9425 | return NULL; |
9426 | ||
4c0e5528 | 9427 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9428 | return NULL; |
9429 | ||
4c0e5528 DV |
9430 | obj = dev_priv->fbdev->fb->obj; |
9431 | BUG_ON(!obj); | |
9432 | ||
8bcd4553 | 9433 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 | 9434 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
272725c7 | 9435 | fb->format->cpp[0] * 8)) |
d2dff872 CW |
9436 | return NULL; |
9437 | ||
01f2c773 | 9438 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9439 | return NULL; |
9440 | ||
edde3617 | 9441 | drm_framebuffer_reference(fb); |
d2dff872 | 9442 | return fb; |
4520f53a DV |
9443 | #else |
9444 | return NULL; | |
9445 | #endif | |
d2dff872 CW |
9446 | } |
9447 | ||
d3a40d1b ACO |
9448 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9449 | struct drm_crtc *crtc, | |
9450 | struct drm_display_mode *mode, | |
9451 | struct drm_framebuffer *fb, | |
9452 | int x, int y) | |
9453 | { | |
9454 | struct drm_plane_state *plane_state; | |
9455 | int hdisplay, vdisplay; | |
9456 | int ret; | |
9457 | ||
9458 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9459 | if (IS_ERR(plane_state)) | |
9460 | return PTR_ERR(plane_state); | |
9461 | ||
9462 | if (mode) | |
196cd5d3 | 9463 | drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay); |
d3a40d1b ACO |
9464 | else |
9465 | hdisplay = vdisplay = 0; | |
9466 | ||
9467 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9468 | if (ret) | |
9469 | return ret; | |
9470 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9471 | plane_state->crtc_x = 0; | |
9472 | plane_state->crtc_y = 0; | |
9473 | plane_state->crtc_w = hdisplay; | |
9474 | plane_state->crtc_h = vdisplay; | |
9475 | plane_state->src_x = x << 16; | |
9476 | plane_state->src_y = y << 16; | |
9477 | plane_state->src_w = hdisplay << 16; | |
9478 | plane_state->src_h = vdisplay << 16; | |
9479 | ||
9480 | return 0; | |
9481 | } | |
9482 | ||
d2434ab7 | 9483 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9484 | struct drm_display_mode *mode, |
51fd371b RC |
9485 | struct intel_load_detect_pipe *old, |
9486 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9487 | { |
9488 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9489 | struct intel_encoder *intel_encoder = |
9490 | intel_attached_encoder(connector); | |
79e53945 | 9491 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9492 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9493 | struct drm_crtc *crtc = NULL; |
9494 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 9495 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 9496 | struct drm_framebuffer *fb; |
51fd371b | 9497 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 9498 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 9499 | struct drm_connector_state *connector_state; |
4be07317 | 9500 | struct intel_crtc_state *crtc_state; |
51fd371b | 9501 | int ret, i = -1; |
79e53945 | 9502 | |
d2dff872 | 9503 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9504 | connector->base.id, connector->name, |
8e329a03 | 9505 | encoder->base.id, encoder->name); |
d2dff872 | 9506 | |
edde3617 ML |
9507 | old->restore_state = NULL; |
9508 | ||
51fd371b RC |
9509 | retry: |
9510 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9511 | if (ret) | |
ad3c558f | 9512 | goto fail; |
6e9f798d | 9513 | |
79e53945 JB |
9514 | /* |
9515 | * Algorithm gets a little messy: | |
7a5e4805 | 9516 | * |
79e53945 JB |
9517 | * - if the connector already has an assigned crtc, use it (but make |
9518 | * sure it's on first) | |
7a5e4805 | 9519 | * |
79e53945 JB |
9520 | * - try to find the first unused crtc that can drive this connector, |
9521 | * and use that if we find one | |
79e53945 JB |
9522 | */ |
9523 | ||
9524 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
9525 | if (connector->state->crtc) { |
9526 | crtc = connector->state->crtc; | |
8261b191 | 9527 | |
51fd371b | 9528 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 9529 | if (ret) |
ad3c558f | 9530 | goto fail; |
8261b191 CW |
9531 | |
9532 | /* Make sure the crtc and connector are running */ | |
edde3617 | 9533 | goto found; |
79e53945 JB |
9534 | } |
9535 | ||
9536 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9537 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9538 | i++; |
9539 | if (!(encoder->possible_crtcs & (1 << i))) | |
9540 | continue; | |
edde3617 ML |
9541 | |
9542 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
9543 | if (ret) | |
9544 | goto fail; | |
9545 | ||
9546 | if (possible_crtc->state->enable) { | |
9547 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 9548 | continue; |
edde3617 | 9549 | } |
a459249c VS |
9550 | |
9551 | crtc = possible_crtc; | |
9552 | break; | |
79e53945 JB |
9553 | } |
9554 | ||
9555 | /* | |
9556 | * If we didn't find an unused CRTC, don't use any. | |
9557 | */ | |
9558 | if (!crtc) { | |
7173188d | 9559 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 9560 | goto fail; |
79e53945 JB |
9561 | } |
9562 | ||
edde3617 ML |
9563 | found: |
9564 | intel_crtc = to_intel_crtc(crtc); | |
9565 | ||
4d02e2de DV |
9566 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
9567 | if (ret) | |
ad3c558f | 9568 | goto fail; |
79e53945 | 9569 | |
83a57153 | 9570 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
9571 | restore_state = drm_atomic_state_alloc(dev); |
9572 | if (!state || !restore_state) { | |
9573 | ret = -ENOMEM; | |
9574 | goto fail; | |
9575 | } | |
83a57153 ACO |
9576 | |
9577 | state->acquire_ctx = ctx; | |
edde3617 | 9578 | restore_state->acquire_ctx = ctx; |
83a57153 | 9579 | |
944b0c76 ACO |
9580 | connector_state = drm_atomic_get_connector_state(state, connector); |
9581 | if (IS_ERR(connector_state)) { | |
9582 | ret = PTR_ERR(connector_state); | |
9583 | goto fail; | |
9584 | } | |
9585 | ||
edde3617 ML |
9586 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
9587 | if (ret) | |
9588 | goto fail; | |
944b0c76 | 9589 | |
4be07317 ACO |
9590 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9591 | if (IS_ERR(crtc_state)) { | |
9592 | ret = PTR_ERR(crtc_state); | |
9593 | goto fail; | |
9594 | } | |
9595 | ||
49d6fa21 | 9596 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 9597 | |
6492711d CW |
9598 | if (!mode) |
9599 | mode = &load_detect_mode; | |
79e53945 | 9600 | |
d2dff872 CW |
9601 | /* We need a framebuffer large enough to accommodate all accesses |
9602 | * that the plane may generate whilst we perform load detection. | |
9603 | * We can not rely on the fbcon either being present (we get called | |
9604 | * during its initialisation to detect all boot displays, or it may | |
9605 | * not even exist) or that it is large enough to satisfy the | |
9606 | * requested mode. | |
9607 | */ | |
94352cf9 DV |
9608 | fb = mode_fits_in_fbdev(dev, mode); |
9609 | if (fb == NULL) { | |
d2dff872 | 9610 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 9611 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
9612 | } else |
9613 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9614 | if (IS_ERR(fb)) { |
d2dff872 | 9615 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9616 | goto fail; |
79e53945 | 9617 | } |
79e53945 | 9618 | |
d3a40d1b ACO |
9619 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
9620 | if (ret) | |
9621 | goto fail; | |
9622 | ||
edde3617 ML |
9623 | drm_framebuffer_unreference(fb); |
9624 | ||
9625 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
9626 | if (ret) | |
9627 | goto fail; | |
9628 | ||
9629 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
9630 | if (!ret) | |
9631 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
9632 | if (!ret) | |
9633 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
9634 | if (ret) { | |
9635 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
9636 | goto fail; | |
9637 | } | |
8c7b5ccb | 9638 | |
3ba86073 ML |
9639 | ret = drm_atomic_commit(state); |
9640 | if (ret) { | |
6492711d | 9641 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 9642 | goto fail; |
79e53945 | 9643 | } |
edde3617 ML |
9644 | |
9645 | old->restore_state = restore_state; | |
7abbd11f | 9646 | drm_atomic_state_put(state); |
7173188d | 9647 | |
79e53945 | 9648 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 9649 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 9650 | return true; |
412b61d8 | 9651 | |
ad3c558f | 9652 | fail: |
7fb71c8f CW |
9653 | if (state) { |
9654 | drm_atomic_state_put(state); | |
9655 | state = NULL; | |
9656 | } | |
9657 | if (restore_state) { | |
9658 | drm_atomic_state_put(restore_state); | |
9659 | restore_state = NULL; | |
9660 | } | |
83a57153 | 9661 | |
51fd371b RC |
9662 | if (ret == -EDEADLK) { |
9663 | drm_modeset_backoff(ctx); | |
9664 | goto retry; | |
9665 | } | |
9666 | ||
412b61d8 | 9667 | return false; |
79e53945 JB |
9668 | } |
9669 | ||
d2434ab7 | 9670 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9671 | struct intel_load_detect_pipe *old, |
9672 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9673 | { |
d2434ab7 DV |
9674 | struct intel_encoder *intel_encoder = |
9675 | intel_attached_encoder(connector); | |
4ef69c7a | 9676 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 9677 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 9678 | int ret; |
79e53945 | 9679 | |
d2dff872 | 9680 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9681 | connector->base.id, connector->name, |
8e329a03 | 9682 | encoder->base.id, encoder->name); |
d2dff872 | 9683 | |
edde3617 | 9684 | if (!state) |
0622a53c | 9685 | return; |
79e53945 | 9686 | |
edde3617 | 9687 | ret = drm_atomic_commit(state); |
0853695c | 9688 | if (ret) |
edde3617 | 9689 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 9690 | drm_atomic_state_put(state); |
79e53945 JB |
9691 | } |
9692 | ||
da4a1efa | 9693 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9694 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 9695 | { |
fac5e23e | 9696 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
9697 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
9698 | ||
9699 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9700 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 9701 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 9702 | return 120000; |
5db94019 | 9703 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
9704 | return 96000; |
9705 | else | |
9706 | return 48000; | |
9707 | } | |
9708 | ||
79e53945 | 9709 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9710 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9711 | struct intel_crtc_state *pipe_config) |
79e53945 | 9712 | { |
f1f644dc | 9713 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9714 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 9715 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9716 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 9717 | u32 fp; |
9e2c8475 | 9718 | struct dpll clock; |
dccbea3b | 9719 | int port_clock; |
da4a1efa | 9720 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9721 | |
9722 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9723 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9724 | else |
293623f7 | 9725 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9726 | |
9727 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 9728 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
9729 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
9730 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9731 | } else { |
9732 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9733 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9734 | } | |
9735 | ||
5db94019 | 9736 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 9737 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
9738 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
9739 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9740 | else |
9741 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9742 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9743 | ||
9744 | switch (dpll & DPLL_MODE_MASK) { | |
9745 | case DPLLB_MODE_DAC_SERIAL: | |
9746 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9747 | 5 : 10; | |
9748 | break; | |
9749 | case DPLLB_MODE_LVDS: | |
9750 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9751 | 7 : 14; | |
9752 | break; | |
9753 | default: | |
28c97730 | 9754 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9755 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9756 | return; |
79e53945 JB |
9757 | } |
9758 | ||
9b1e14f4 | 9759 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 9760 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 9761 | else |
dccbea3b | 9762 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 9763 | } else { |
50a0bc90 | 9764 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9765 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9766 | |
9767 | if (is_lvds) { | |
9768 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9769 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9770 | |
9771 | if (lvds & LVDS_CLKB_POWER_UP) | |
9772 | clock.p2 = 7; | |
9773 | else | |
9774 | clock.p2 = 14; | |
79e53945 JB |
9775 | } else { |
9776 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9777 | clock.p1 = 2; | |
9778 | else { | |
9779 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9780 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9781 | } | |
9782 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9783 | clock.p2 = 4; | |
9784 | else | |
9785 | clock.p2 = 2; | |
79e53945 | 9786 | } |
da4a1efa | 9787 | |
dccbea3b | 9788 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
9789 | } |
9790 | ||
18442d08 VS |
9791 | /* |
9792 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9793 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9794 | * encoder's get_config() function. |
9795 | */ | |
dccbea3b | 9796 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
9797 | } |
9798 | ||
6878da05 VS |
9799 | int intel_dotclock_calculate(int link_freq, |
9800 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9801 | { |
f1f644dc JB |
9802 | /* |
9803 | * The calculation for the data clock is: | |
1041a02f | 9804 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9805 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9806 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9807 | * |
9808 | * and the link clock is simpler: | |
1041a02f | 9809 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9810 | */ |
9811 | ||
6878da05 VS |
9812 | if (!m_n->link_n) |
9813 | return 0; | |
f1f644dc | 9814 | |
6878da05 VS |
9815 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9816 | } | |
f1f644dc | 9817 | |
18442d08 | 9818 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9819 | struct intel_crtc_state *pipe_config) |
6878da05 | 9820 | { |
e3b247da | 9821 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 9822 | |
18442d08 VS |
9823 | /* read out port_clock from the DPLL */ |
9824 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9825 | |
f1f644dc | 9826 | /* |
e3b247da VS |
9827 | * In case there is an active pipe without active ports, |
9828 | * we may need some idea for the dotclock anyway. | |
9829 | * Calculate one based on the FDI configuration. | |
79e53945 | 9830 | */ |
2d112de7 | 9831 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 9832 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 9833 | &pipe_config->fdi_m_n); |
79e53945 JB |
9834 | } |
9835 | ||
9836 | /** Returns the currently programmed mode of the given pipe. */ | |
9837 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9838 | struct drm_crtc *crtc) | |
9839 | { | |
fac5e23e | 9840 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 9841 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9842 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9843 | struct drm_display_mode *mode; |
3f36b937 | 9844 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
9845 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9846 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9847 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9848 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9849 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9850 | |
9851 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9852 | if (!mode) | |
9853 | return NULL; | |
9854 | ||
3f36b937 TU |
9855 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9856 | if (!pipe_config) { | |
9857 | kfree(mode); | |
9858 | return NULL; | |
9859 | } | |
9860 | ||
f1f644dc JB |
9861 | /* |
9862 | * Construct a pipe_config sufficient for getting the clock info | |
9863 | * back out of crtc_clock_get. | |
9864 | * | |
9865 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9866 | * to use a real value here instead. | |
9867 | */ | |
3f36b937 TU |
9868 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
9869 | pipe_config->pixel_multiplier = 1; | |
9870 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
9871 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9872 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
9873 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
9874 | ||
9875 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
9876 | mode->hdisplay = (htot & 0xffff) + 1; |
9877 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9878 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9879 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9880 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9881 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9882 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9883 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9884 | ||
9885 | drm_mode_set_name(mode); | |
79e53945 | 9886 | |
3f36b937 TU |
9887 | kfree(pipe_config); |
9888 | ||
79e53945 JB |
9889 | return mode; |
9890 | } | |
9891 | ||
9892 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
9893 | { | |
9894 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 9895 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 9896 | struct intel_flip_work *work; |
67e77c5a | 9897 | |
5e2d7afc | 9898 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
9899 | work = intel_crtc->flip_work; |
9900 | intel_crtc->flip_work = NULL; | |
9901 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 9902 | |
5a21b665 | 9903 | if (work) { |
51cbaf01 ML |
9904 | cancel_work_sync(&work->mmio_work); |
9905 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 9906 | kfree(work); |
67e77c5a | 9907 | } |
79e53945 JB |
9908 | |
9909 | drm_crtc_cleanup(crtc); | |
67e77c5a | 9910 | |
79e53945 JB |
9911 | kfree(intel_crtc); |
9912 | } | |
9913 | ||
6b95a207 KH |
9914 | static void intel_unpin_work_fn(struct work_struct *__work) |
9915 | { | |
51cbaf01 ML |
9916 | struct intel_flip_work *work = |
9917 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
9918 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
9919 | struct drm_device *dev = crtc->base.dev; | |
9920 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 9921 | |
5a21b665 DV |
9922 | if (is_mmio_work(work)) |
9923 | flush_work(&work->mmio_work); | |
03f476e1 | 9924 | |
5a21b665 | 9925 | mutex_lock(&dev->struct_mutex); |
be1e3415 | 9926 | intel_unpin_fb_vma(work->old_vma); |
f8c417cd | 9927 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 9928 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 9929 | |
e8a261ea CW |
9930 | i915_gem_request_put(work->flip_queued_req); |
9931 | ||
5748b6a1 CW |
9932 | intel_frontbuffer_flip_complete(to_i915(dev), |
9933 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
9934 | intel_fbc_post_update(crtc); |
9935 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 9936 | |
5a21b665 DV |
9937 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
9938 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 9939 | |
5a21b665 DV |
9940 | kfree(work); |
9941 | } | |
d9e86c0e | 9942 | |
5a21b665 DV |
9943 | /* Is 'a' after or equal to 'b'? */ |
9944 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9945 | { | |
9946 | return !((a - b) & 0x80000000); | |
9947 | } | |
143f73b3 | 9948 | |
5a21b665 DV |
9949 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
9950 | struct intel_flip_work *work) | |
9951 | { | |
9952 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9953 | struct drm_i915_private *dev_priv = to_i915(dev); |
143f73b3 | 9954 | |
8af29b0c | 9955 | if (abort_flip_on_reset(crtc)) |
5a21b665 | 9956 | return true; |
143f73b3 | 9957 | |
5a21b665 DV |
9958 | /* |
9959 | * The relevant registers doen't exist on pre-ctg. | |
9960 | * As the flip done interrupt doesn't trigger for mmio | |
9961 | * flips on gmch platforms, a flip count check isn't | |
9962 | * really needed there. But since ctg has the registers, | |
9963 | * include it in the check anyway. | |
9964 | */ | |
9beb5fea | 9965 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
5a21b665 | 9966 | return true; |
b4a98e57 | 9967 | |
5a21b665 DV |
9968 | /* |
9969 | * BDW signals flip done immediately if the plane | |
9970 | * is disabled, even if the plane enable is already | |
9971 | * armed to occur at the next vblank :( | |
9972 | */ | |
f99d7069 | 9973 | |
5a21b665 DV |
9974 | /* |
9975 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9976 | * used the same base address. In that case the mmio flip might | |
9977 | * have completed, but the CS hasn't even executed the flip yet. | |
9978 | * | |
9979 | * A flip count check isn't enough as the CS might have updated | |
9980 | * the base address just after start of vblank, but before we | |
9981 | * managed to process the interrupt. This means we'd complete the | |
9982 | * CS flip too soon. | |
9983 | * | |
9984 | * Combining both checks should get us a good enough result. It may | |
9985 | * still happen that the CS flip has been executed, but has not | |
9986 | * yet actually completed. But in case the base address is the same | |
9987 | * anyway, we don't really care. | |
9988 | */ | |
9989 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9990 | crtc->flip_work->gtt_offset && | |
9991 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
9992 | crtc->flip_work->flip_count); | |
9993 | } | |
b4a98e57 | 9994 | |
5a21b665 DV |
9995 | static bool |
9996 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
9997 | struct intel_flip_work *work) | |
9998 | { | |
9999 | /* | |
10000 | * MMIO work completes when vblank is different from | |
10001 | * flip_queued_vblank. | |
10002 | * | |
10003 | * Reset counter value doesn't matter, this is handled by | |
10004 | * i915_wait_request finishing early, so no need to handle | |
10005 | * reset here. | |
10006 | */ | |
10007 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
10008 | } |
10009 | ||
51cbaf01 ML |
10010 | |
10011 | static bool pageflip_finished(struct intel_crtc *crtc, | |
10012 | struct intel_flip_work *work) | |
10013 | { | |
10014 | if (!atomic_read(&work->pending)) | |
10015 | return false; | |
10016 | ||
10017 | smp_rmb(); | |
10018 | ||
5a21b665 DV |
10019 | if (is_mmio_work(work)) |
10020 | return __pageflip_finished_mmio(crtc, work); | |
10021 | else | |
10022 | return __pageflip_finished_cs(crtc, work); | |
10023 | } | |
10024 | ||
10025 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
10026 | { | |
91c8a326 | 10027 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10028 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
10029 | struct intel_flip_work *work; |
10030 | unsigned long flags; | |
10031 | ||
10032 | /* Ignore early vblank irqs */ | |
10033 | if (!crtc) | |
10034 | return; | |
10035 | ||
51cbaf01 | 10036 | /* |
5a21b665 DV |
10037 | * This is called both by irq handlers and the reset code (to complete |
10038 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 10039 | */ |
5a21b665 | 10040 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 10041 | work = crtc->flip_work; |
5a21b665 DV |
10042 | |
10043 | if (work != NULL && | |
10044 | !is_mmio_work(work) && | |
e2af48c6 VS |
10045 | pageflip_finished(crtc, work)) |
10046 | page_flip_completed(crtc); | |
5a21b665 DV |
10047 | |
10048 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
10049 | } |
10050 | ||
51cbaf01 | 10051 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 10052 | { |
91c8a326 | 10053 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10054 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
51cbaf01 | 10055 | struct intel_flip_work *work; |
6b95a207 KH |
10056 | unsigned long flags; |
10057 | ||
5251f04e ML |
10058 | /* Ignore early vblank irqs */ |
10059 | if (!crtc) | |
10060 | return; | |
f326038a DV |
10061 | |
10062 | /* | |
10063 | * This is called both by irq handlers and the reset code (to complete | |
10064 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 10065 | */ |
6b95a207 | 10066 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 10067 | work = crtc->flip_work; |
5251f04e | 10068 | |
5a21b665 DV |
10069 | if (work != NULL && |
10070 | is_mmio_work(work) && | |
e2af48c6 VS |
10071 | pageflip_finished(crtc, work)) |
10072 | page_flip_completed(crtc); | |
5251f04e | 10073 | |
6b95a207 KH |
10074 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10075 | } | |
10076 | ||
5a21b665 DV |
10077 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
10078 | struct intel_flip_work *work) | |
84c33a64 | 10079 | { |
5a21b665 | 10080 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 10081 | |
5a21b665 DV |
10082 | /* Ensure that the work item is consistent when activating it ... */ |
10083 | smp_mb__before_atomic(); | |
10084 | atomic_set(&work->pending, 1); | |
10085 | } | |
a6747b73 | 10086 | |
5a21b665 DV |
10087 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10088 | struct drm_crtc *crtc, | |
10089 | struct drm_framebuffer *fb, | |
10090 | struct drm_i915_gem_object *obj, | |
10091 | struct drm_i915_gem_request *req, | |
10092 | uint32_t flags) | |
10093 | { | |
5a21b665 | 10094 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10095 | u32 flip_mask, *cs; |
143f73b3 | 10096 | |
73dec95e TU |
10097 | cs = intel_ring_begin(req, 6); |
10098 | if (IS_ERR(cs)) | |
10099 | return PTR_ERR(cs); | |
143f73b3 | 10100 | |
5a21b665 DV |
10101 | /* Can't queue multiple flips, so wait for the previous |
10102 | * one to finish before executing the next. | |
10103 | */ | |
10104 | if (intel_crtc->plane) | |
10105 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10106 | else | |
10107 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
73dec95e TU |
10108 | *cs++ = MI_WAIT_FOR_EVENT | flip_mask; |
10109 | *cs++ = MI_NOOP; | |
10110 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); | |
10111 | *cs++ = fb->pitches[0]; | |
10112 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10113 | *cs++ = 0; /* aux display base address, unused */ | |
143f73b3 | 10114 | |
5a21b665 DV |
10115 | return 0; |
10116 | } | |
84c33a64 | 10117 | |
5a21b665 DV |
10118 | static int intel_gen3_queue_flip(struct drm_device *dev, |
10119 | struct drm_crtc *crtc, | |
10120 | struct drm_framebuffer *fb, | |
10121 | struct drm_i915_gem_object *obj, | |
10122 | struct drm_i915_gem_request *req, | |
10123 | uint32_t flags) | |
10124 | { | |
5a21b665 | 10125 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10126 | u32 flip_mask, *cs; |
d55dbd06 | 10127 | |
73dec95e TU |
10128 | cs = intel_ring_begin(req, 6); |
10129 | if (IS_ERR(cs)) | |
10130 | return PTR_ERR(cs); | |
d55dbd06 | 10131 | |
5a21b665 DV |
10132 | if (intel_crtc->plane) |
10133 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10134 | else | |
10135 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
73dec95e TU |
10136 | *cs++ = MI_WAIT_FOR_EVENT | flip_mask; |
10137 | *cs++ = MI_NOOP; | |
10138 | *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); | |
10139 | *cs++ = fb->pitches[0]; | |
10140 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10141 | *cs++ = MI_NOOP; | |
fd8e058a | 10142 | |
5a21b665 DV |
10143 | return 0; |
10144 | } | |
84c33a64 | 10145 | |
5a21b665 DV |
10146 | static int intel_gen4_queue_flip(struct drm_device *dev, |
10147 | struct drm_crtc *crtc, | |
10148 | struct drm_framebuffer *fb, | |
10149 | struct drm_i915_gem_object *obj, | |
10150 | struct drm_i915_gem_request *req, | |
10151 | uint32_t flags) | |
10152 | { | |
fac5e23e | 10153 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10154 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10155 | u32 pf, pipesrc, *cs; |
143f73b3 | 10156 | |
73dec95e TU |
10157 | cs = intel_ring_begin(req, 4); |
10158 | if (IS_ERR(cs)) | |
10159 | return PTR_ERR(cs); | |
143f73b3 | 10160 | |
5a21b665 DV |
10161 | /* i965+ uses the linear or tiled offsets from the |
10162 | * Display Registers (which do not change across a page-flip) | |
10163 | * so we need only reprogram the base address. | |
10164 | */ | |
73dec95e TU |
10165 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); |
10166 | *cs++ = fb->pitches[0]; | |
10167 | *cs++ = intel_crtc->flip_work->gtt_offset | | |
10168 | intel_fb_modifier_to_tiling(fb->modifier); | |
5a21b665 DV |
10169 | |
10170 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10171 | * untested on non-native modes, so ignore it for now. | |
10172 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10173 | */ | |
10174 | pf = 0; | |
10175 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
73dec95e | 10176 | *cs++ = pf | pipesrc; |
143f73b3 | 10177 | |
5a21b665 | 10178 | return 0; |
8c9f3aaf JB |
10179 | } |
10180 | ||
5a21b665 DV |
10181 | static int intel_gen6_queue_flip(struct drm_device *dev, |
10182 | struct drm_crtc *crtc, | |
10183 | struct drm_framebuffer *fb, | |
10184 | struct drm_i915_gem_object *obj, | |
10185 | struct drm_i915_gem_request *req, | |
10186 | uint32_t flags) | |
da20eabd | 10187 | { |
fac5e23e | 10188 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10189 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10190 | u32 pf, pipesrc, *cs; |
d21fbe87 | 10191 | |
73dec95e TU |
10192 | cs = intel_ring_begin(req, 4); |
10193 | if (IS_ERR(cs)) | |
10194 | return PTR_ERR(cs); | |
92826fcd | 10195 | |
73dec95e TU |
10196 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); |
10197 | *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); | |
10198 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
92826fcd | 10199 | |
5a21b665 DV |
10200 | /* Contrary to the suggestions in the documentation, |
10201 | * "Enable Panel Fitter" does not seem to be required when page | |
10202 | * flipping with a non-native mode, and worse causes a normal | |
10203 | * modeset to fail. | |
10204 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10205 | */ | |
10206 | pf = 0; | |
10207 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
73dec95e | 10208 | *cs++ = pf | pipesrc; |
7809e5ae | 10209 | |
5a21b665 | 10210 | return 0; |
7809e5ae MR |
10211 | } |
10212 | ||
5a21b665 DV |
10213 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10214 | struct drm_crtc *crtc, | |
10215 | struct drm_framebuffer *fb, | |
10216 | struct drm_i915_gem_object *obj, | |
10217 | struct drm_i915_gem_request *req, | |
10218 | uint32_t flags) | |
d21fbe87 | 10219 | { |
5db94019 | 10220 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10222 | u32 *cs, plane_bit = 0; |
5a21b665 | 10223 | int len, ret; |
d21fbe87 | 10224 | |
5a21b665 DV |
10225 | switch (intel_crtc->plane) { |
10226 | case PLANE_A: | |
10227 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10228 | break; | |
10229 | case PLANE_B: | |
10230 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10231 | break; | |
10232 | case PLANE_C: | |
10233 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10234 | break; | |
10235 | default: | |
10236 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
10237 | return -ENODEV; | |
10238 | } | |
10239 | ||
10240 | len = 4; | |
b5321f30 | 10241 | if (req->engine->id == RCS) { |
5a21b665 DV |
10242 | len += 6; |
10243 | /* | |
10244 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10245 | * 48bits addresses, and we need a NOOP for the batch size to | |
10246 | * stay even. | |
10247 | */ | |
5db94019 | 10248 | if (IS_GEN8(dev_priv)) |
5a21b665 DV |
10249 | len += 2; |
10250 | } | |
10251 | ||
10252 | /* | |
10253 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10254 | * "The full packet must be contained within the same cache line." | |
10255 | * | |
10256 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10257 | * cacheline, if we ever start emitting more commands before | |
10258 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10259 | * then do the cacheline alignment, and finally emit the | |
10260 | * MI_DISPLAY_FLIP. | |
10261 | */ | |
10262 | ret = intel_ring_cacheline_align(req); | |
10263 | if (ret) | |
10264 | return ret; | |
10265 | ||
73dec95e TU |
10266 | cs = intel_ring_begin(req, len); |
10267 | if (IS_ERR(cs)) | |
10268 | return PTR_ERR(cs); | |
5a21b665 DV |
10269 | |
10270 | /* Unmask the flip-done completion message. Note that the bspec says that | |
10271 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10272 | * more than one flip event at any time (or ensure that one flip message | |
10273 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10274 | * Experimentation says that BCS works despite DERRMR masking all | |
10275 | * flip-done completion events and that unmasking all planes at once | |
10276 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10277 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10278 | */ | |
b5321f30 | 10279 | if (req->engine->id == RCS) { |
73dec95e TU |
10280 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
10281 | *cs++ = i915_mmio_reg_offset(DERRMR); | |
10282 | *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10283 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10284 | DERRMR_PIPEC_PRI_FLIP_DONE); | |
5db94019 | 10285 | if (IS_GEN8(dev_priv)) |
73dec95e TU |
10286 | *cs++ = MI_STORE_REGISTER_MEM_GEN8 | |
10287 | MI_SRM_LRM_GLOBAL_GTT; | |
5a21b665 | 10288 | else |
73dec95e TU |
10289 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; |
10290 | *cs++ = i915_mmio_reg_offset(DERRMR); | |
10291 | *cs++ = i915_ggtt_offset(req->engine->scratch) + 256; | |
5db94019 | 10292 | if (IS_GEN8(dev_priv)) { |
73dec95e TU |
10293 | *cs++ = 0; |
10294 | *cs++ = MI_NOOP; | |
5a21b665 DV |
10295 | } |
10296 | } | |
10297 | ||
73dec95e TU |
10298 | *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit; |
10299 | *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); | |
10300 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10301 | *cs++ = MI_NOOP; | |
5a21b665 DV |
10302 | |
10303 | return 0; | |
10304 | } | |
10305 | ||
10306 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
10307 | struct drm_i915_gem_object *obj) | |
10308 | { | |
10309 | /* | |
10310 | * This is not being used for older platforms, because | |
10311 | * non-availability of flip done interrupt forces us to use | |
10312 | * CS flips. Older platforms derive flip done using some clever | |
10313 | * tricks involving the flip_pending status bits and vblank irqs. | |
10314 | * So using MMIO flips there would disrupt this mechanism. | |
10315 | */ | |
10316 | ||
10317 | if (engine == NULL) | |
10318 | return true; | |
10319 | ||
10320 | if (INTEL_GEN(engine->i915) < 5) | |
10321 | return false; | |
10322 | ||
10323 | if (i915.use_mmio_flip < 0) | |
10324 | return false; | |
10325 | else if (i915.use_mmio_flip > 0) | |
10326 | return true; | |
10327 | else if (i915.enable_execlists) | |
10328 | return true; | |
c37efb99 | 10329 | |
d07f0e59 | 10330 | return engine != i915_gem_object_last_write_engine(obj); |
5a21b665 DV |
10331 | } |
10332 | ||
10333 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
10334 | unsigned int rotation, | |
10335 | struct intel_flip_work *work) | |
10336 | { | |
10337 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 10338 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
10339 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
10340 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 10341 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
10342 | |
10343 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10344 | ctl &= ~PLANE_CTL_TILED_MASK; | |
bae781b2 | 10345 | switch (fb->modifier) { |
5a21b665 DV |
10346 | case DRM_FORMAT_MOD_NONE: |
10347 | break; | |
10348 | case I915_FORMAT_MOD_X_TILED: | |
10349 | ctl |= PLANE_CTL_TILED_X; | |
10350 | break; | |
10351 | case I915_FORMAT_MOD_Y_TILED: | |
10352 | ctl |= PLANE_CTL_TILED_Y; | |
10353 | break; | |
10354 | case I915_FORMAT_MOD_Yf_TILED: | |
10355 | ctl |= PLANE_CTL_TILED_YF; | |
10356 | break; | |
10357 | default: | |
bae781b2 | 10358 | MISSING_CASE(fb->modifier); |
5a21b665 DV |
10359 | } |
10360 | ||
5a21b665 DV |
10361 | /* |
10362 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10363 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10364 | */ | |
10365 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10366 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10367 | ||
10368 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
10369 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10370 | } | |
10371 | ||
10372 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
10373 | struct intel_flip_work *work) | |
10374 | { | |
10375 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 10376 | struct drm_i915_private *dev_priv = to_i915(dev); |
72618ebf | 10377 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
5a21b665 DV |
10378 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
10379 | u32 dspcntr; | |
10380 | ||
10381 | dspcntr = I915_READ(reg); | |
10382 | ||
bae781b2 | 10383 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
5a21b665 DV |
10384 | dspcntr |= DISPPLANE_TILED; |
10385 | else | |
10386 | dspcntr &= ~DISPPLANE_TILED; | |
10387 | ||
10388 | I915_WRITE(reg, dspcntr); | |
10389 | ||
10390 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
10391 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
10392 | } | |
10393 | ||
10394 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
10395 | { | |
10396 | struct intel_flip_work *work = | |
10397 | container_of(w, struct intel_flip_work, mmio_work); | |
10398 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
10399 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
10400 | struct intel_framebuffer *intel_fb = | |
10401 | to_intel_framebuffer(crtc->base.primary->fb); | |
10402 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10403 | ||
d07f0e59 | 10404 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); |
5a21b665 DV |
10405 | |
10406 | intel_pipe_update_start(crtc); | |
10407 | ||
10408 | if (INTEL_GEN(dev_priv) >= 9) | |
10409 | skl_do_mmio_flip(crtc, work->rotation, work); | |
10410 | else | |
10411 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10412 | ilk_do_mmio_flip(crtc, work); | |
10413 | ||
10414 | intel_pipe_update_end(crtc, work); | |
10415 | } | |
10416 | ||
10417 | static int intel_default_queue_flip(struct drm_device *dev, | |
10418 | struct drm_crtc *crtc, | |
10419 | struct drm_framebuffer *fb, | |
10420 | struct drm_i915_gem_object *obj, | |
10421 | struct drm_i915_gem_request *req, | |
10422 | uint32_t flags) | |
10423 | { | |
10424 | return -ENODEV; | |
10425 | } | |
10426 | ||
10427 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
10428 | struct intel_crtc *intel_crtc, | |
10429 | struct intel_flip_work *work) | |
10430 | { | |
10431 | u32 addr, vblank; | |
10432 | ||
10433 | if (!atomic_read(&work->pending)) | |
10434 | return false; | |
10435 | ||
10436 | smp_rmb(); | |
10437 | ||
10438 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
10439 | if (work->flip_ready_vblank == 0) { | |
10440 | if (work->flip_queued_req && | |
f69a02c9 | 10441 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
10442 | return false; |
10443 | ||
10444 | work->flip_ready_vblank = vblank; | |
10445 | } | |
10446 | ||
10447 | if (vblank - work->flip_ready_vblank < 3) | |
10448 | return false; | |
10449 | ||
10450 | /* Potential stall - if we see that the flip has happened, | |
10451 | * assume a missed interrupt. */ | |
10452 | if (INTEL_GEN(dev_priv) >= 4) | |
10453 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10454 | else | |
10455 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10456 | ||
10457 | /* There is a potential issue here with a false positive after a flip | |
10458 | * to the same address. We could address this by checking for a | |
10459 | * non-incrementing frame counter. | |
10460 | */ | |
10461 | return addr == work->gtt_offset; | |
10462 | } | |
10463 | ||
10464 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
10465 | { | |
91c8a326 | 10466 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10467 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
10468 | struct intel_flip_work *work; |
10469 | ||
10470 | WARN_ON(!in_interrupt()); | |
10471 | ||
10472 | if (crtc == NULL) | |
10473 | return; | |
10474 | ||
10475 | spin_lock(&dev->event_lock); | |
e2af48c6 | 10476 | work = crtc->flip_work; |
5a21b665 DV |
10477 | |
10478 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 10479 | __pageflip_stall_check_cs(dev_priv, crtc, work)) { |
5a21b665 DV |
10480 | WARN_ONCE(1, |
10481 | "Kicking stuck page flip: queued at %d, now %d\n", | |
e2af48c6 VS |
10482 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); |
10483 | page_flip_completed(crtc); | |
5a21b665 DV |
10484 | work = NULL; |
10485 | } | |
10486 | ||
10487 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 10488 | intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) |
5a21b665 DV |
10489 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
10490 | spin_unlock(&dev->event_lock); | |
10491 | } | |
10492 | ||
4c01ded5 | 10493 | __maybe_unused |
5a21b665 DV |
10494 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10495 | struct drm_framebuffer *fb, | |
10496 | struct drm_pending_vblank_event *event, | |
10497 | uint32_t page_flip_flags) | |
10498 | { | |
10499 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10500 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
10501 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
10502 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
10503 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10504 | struct drm_plane *primary = crtc->primary; | |
10505 | enum pipe pipe = intel_crtc->pipe; | |
10506 | struct intel_flip_work *work; | |
10507 | struct intel_engine_cs *engine; | |
10508 | bool mmio_flip; | |
8e637178 | 10509 | struct drm_i915_gem_request *request; |
058d88c4 | 10510 | struct i915_vma *vma; |
5a21b665 DV |
10511 | int ret; |
10512 | ||
10513 | /* | |
10514 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10515 | * check to be safe. In the future we may enable pageflipping from | |
10516 | * a disabled primary plane. | |
10517 | */ | |
10518 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10519 | return -EBUSY; | |
10520 | ||
10521 | /* Can't change pixel format via MI display flips. */ | |
dbd4d576 | 10522 | if (fb->format != crtc->primary->fb->format) |
5a21b665 DV |
10523 | return -EINVAL; |
10524 | ||
10525 | /* | |
10526 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10527 | * Note that pitch changes could also affect these register. | |
10528 | */ | |
6315b5d3 | 10529 | if (INTEL_GEN(dev_priv) > 3 && |
5a21b665 DV |
10530 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10531 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
10532 | return -EINVAL; | |
10533 | ||
10534 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
10535 | goto out_hang; | |
10536 | ||
10537 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
10538 | if (work == NULL) | |
10539 | return -ENOMEM; | |
10540 | ||
10541 | work->event = event; | |
10542 | work->crtc = crtc; | |
10543 | work->old_fb = old_fb; | |
10544 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
10545 | ||
10546 | ret = drm_crtc_vblank_get(crtc); | |
10547 | if (ret) | |
10548 | goto free_work; | |
10549 | ||
10550 | /* We borrow the event spin lock for protecting flip_work */ | |
10551 | spin_lock_irq(&dev->event_lock); | |
10552 | if (intel_crtc->flip_work) { | |
10553 | /* Before declaring the flip queue wedged, check if | |
10554 | * the hardware completed the operation behind our backs. | |
10555 | */ | |
10556 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
10557 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10558 | page_flip_completed(intel_crtc); | |
10559 | } else { | |
10560 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
10561 | spin_unlock_irq(&dev->event_lock); | |
10562 | ||
10563 | drm_crtc_vblank_put(crtc); | |
10564 | kfree(work); | |
10565 | return -EBUSY; | |
10566 | } | |
10567 | } | |
10568 | intel_crtc->flip_work = work; | |
10569 | spin_unlock_irq(&dev->event_lock); | |
10570 | ||
10571 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
10572 | flush_workqueue(dev_priv->wq); | |
10573 | ||
10574 | /* Reference the objects for the scheduled work. */ | |
10575 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
10576 | |
10577 | crtc->primary->fb = fb; | |
10578 | update_state_fb(crtc->primary); | |
faf68d92 | 10579 | |
25dc556a | 10580 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
10581 | |
10582 | ret = i915_mutex_lock_interruptible(dev); | |
10583 | if (ret) | |
10584 | goto cleanup; | |
10585 | ||
8af29b0c CW |
10586 | intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); |
10587 | if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) { | |
5a21b665 | 10588 | ret = -EIO; |
ddbb271a | 10589 | goto unlock; |
5a21b665 DV |
10590 | } |
10591 | ||
10592 | atomic_inc(&intel_crtc->unpin_work_count); | |
10593 | ||
9beb5fea | 10594 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
5a21b665 DV |
10595 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
10596 | ||
920a14b2 | 10597 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3b3f1650 | 10598 | engine = dev_priv->engine[BCS]; |
bae781b2 | 10599 | if (fb->modifier != old_fb->modifier) |
5a21b665 DV |
10600 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10601 | engine = NULL; | |
fd6b8f43 | 10602 | } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { |
3b3f1650 | 10603 | engine = dev_priv->engine[BCS]; |
6315b5d3 | 10604 | } else if (INTEL_GEN(dev_priv) >= 7) { |
d07f0e59 | 10605 | engine = i915_gem_object_last_write_engine(obj); |
5a21b665 | 10606 | if (engine == NULL || engine->id != RCS) |
3b3f1650 | 10607 | engine = dev_priv->engine[BCS]; |
5a21b665 | 10608 | } else { |
3b3f1650 | 10609 | engine = dev_priv->engine[RCS]; |
5a21b665 DV |
10610 | } |
10611 | ||
10612 | mmio_flip = use_mmio_flip(engine, obj); | |
10613 | ||
058d88c4 CW |
10614 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
10615 | if (IS_ERR(vma)) { | |
10616 | ret = PTR_ERR(vma); | |
5a21b665 | 10617 | goto cleanup_pending; |
058d88c4 | 10618 | } |
5a21b665 | 10619 | |
be1e3415 CW |
10620 | work->old_vma = to_intel_plane_state(primary->state)->vma; |
10621 | to_intel_plane_state(primary->state)->vma = vma; | |
10622 | ||
10623 | work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset; | |
5a21b665 DV |
10624 | work->rotation = crtc->primary->state->rotation; |
10625 | ||
1f061316 PZ |
10626 | /* |
10627 | * There's the potential that the next frame will not be compatible with | |
10628 | * FBC, so we want to call pre_update() before the actual page flip. | |
10629 | * The problem is that pre_update() caches some information about the fb | |
10630 | * object, so we want to do this only after the object is pinned. Let's | |
10631 | * be on the safe side and do this immediately before scheduling the | |
10632 | * flip. | |
10633 | */ | |
10634 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
10635 | to_intel_plane_state(primary->state)); | |
10636 | ||
5a21b665 DV |
10637 | if (mmio_flip) { |
10638 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
6277c8d0 | 10639 | queue_work(system_unbound_wq, &work->mmio_work); |
5a21b665 | 10640 | } else { |
e8a9c58f CW |
10641 | request = i915_gem_request_alloc(engine, |
10642 | dev_priv->kernel_context); | |
8e637178 CW |
10643 | if (IS_ERR(request)) { |
10644 | ret = PTR_ERR(request); | |
10645 | goto cleanup_unpin; | |
10646 | } | |
10647 | ||
a2bc4695 | 10648 | ret = i915_gem_request_await_object(request, obj, false); |
8e637178 CW |
10649 | if (ret) |
10650 | goto cleanup_request; | |
10651 | ||
5a21b665 DV |
10652 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
10653 | page_flip_flags); | |
10654 | if (ret) | |
8e637178 | 10655 | goto cleanup_request; |
5a21b665 DV |
10656 | |
10657 | intel_mark_page_flip_active(intel_crtc, work); | |
10658 | ||
8e637178 | 10659 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
10660 | i915_add_request_no_flush(request); |
10661 | } | |
10662 | ||
92117f0b | 10663 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); |
5a21b665 DV |
10664 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, |
10665 | to_intel_plane(primary)->frontbuffer_bit); | |
10666 | mutex_unlock(&dev->struct_mutex); | |
10667 | ||
5748b6a1 | 10668 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
10669 | to_intel_plane(primary)->frontbuffer_bit); |
10670 | ||
10671 | trace_i915_flip_request(intel_crtc->plane, obj); | |
10672 | ||
10673 | return 0; | |
10674 | ||
8e637178 CW |
10675 | cleanup_request: |
10676 | i915_add_request_no_flush(request); | |
5a21b665 | 10677 | cleanup_unpin: |
be1e3415 CW |
10678 | to_intel_plane_state(primary->state)->vma = work->old_vma; |
10679 | intel_unpin_fb_vma(vma); | |
5a21b665 | 10680 | cleanup_pending: |
5a21b665 | 10681 | atomic_dec(&intel_crtc->unpin_work_count); |
ddbb271a | 10682 | unlock: |
5a21b665 DV |
10683 | mutex_unlock(&dev->struct_mutex); |
10684 | cleanup: | |
10685 | crtc->primary->fb = old_fb; | |
10686 | update_state_fb(crtc->primary); | |
10687 | ||
f0cd5182 | 10688 | i915_gem_object_put(obj); |
5a21b665 DV |
10689 | drm_framebuffer_unreference(work->old_fb); |
10690 | ||
10691 | spin_lock_irq(&dev->event_lock); | |
10692 | intel_crtc->flip_work = NULL; | |
10693 | spin_unlock_irq(&dev->event_lock); | |
10694 | ||
10695 | drm_crtc_vblank_put(crtc); | |
10696 | free_work: | |
10697 | kfree(work); | |
10698 | ||
10699 | if (ret == -EIO) { | |
10700 | struct drm_atomic_state *state; | |
10701 | struct drm_plane_state *plane_state; | |
10702 | ||
10703 | out_hang: | |
10704 | state = drm_atomic_state_alloc(dev); | |
10705 | if (!state) | |
10706 | return -ENOMEM; | |
10707 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
10708 | ||
10709 | retry: | |
10710 | plane_state = drm_atomic_get_plane_state(state, primary); | |
10711 | ret = PTR_ERR_OR_ZERO(plane_state); | |
10712 | if (!ret) { | |
10713 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10714 | ||
10715 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
10716 | if (!ret) | |
10717 | ret = drm_atomic_commit(state); | |
10718 | } | |
10719 | ||
10720 | if (ret == -EDEADLK) { | |
10721 | drm_modeset_backoff(state->acquire_ctx); | |
10722 | drm_atomic_state_clear(state); | |
10723 | goto retry; | |
10724 | } | |
10725 | ||
0853695c | 10726 | drm_atomic_state_put(state); |
5a21b665 DV |
10727 | |
10728 | if (ret == 0 && event) { | |
10729 | spin_lock_irq(&dev->event_lock); | |
10730 | drm_crtc_send_vblank_event(crtc, event); | |
10731 | spin_unlock_irq(&dev->event_lock); | |
10732 | } | |
10733 | } | |
10734 | return ret; | |
10735 | } | |
10736 | ||
10737 | ||
10738 | /** | |
10739 | * intel_wm_need_update - Check whether watermarks need updating | |
10740 | * @plane: drm plane | |
10741 | * @state: new plane state | |
10742 | * | |
10743 | * Check current plane state versus the new one to determine whether | |
10744 | * watermarks need to be recalculated. | |
10745 | * | |
10746 | * Returns true or false. | |
10747 | */ | |
10748 | static bool intel_wm_need_update(struct drm_plane *plane, | |
10749 | struct drm_plane_state *state) | |
10750 | { | |
10751 | struct intel_plane_state *new = to_intel_plane_state(state); | |
10752 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
10753 | ||
10754 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 10755 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
10756 | return true; |
10757 | ||
10758 | if (!cur->base.fb || !new->base.fb) | |
10759 | return false; | |
10760 | ||
bae781b2 | 10761 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 10762 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
10763 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
10764 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
10765 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
10766 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
10767 | return true; |
10768 | ||
10769 | return false; | |
10770 | } | |
10771 | ||
10772 | static bool needs_scaling(struct intel_plane_state *state) | |
10773 | { | |
936e71e3 VS |
10774 | int src_w = drm_rect_width(&state->base.src) >> 16; |
10775 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
10776 | int dst_w = drm_rect_width(&state->base.dst); | |
10777 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
10778 | |
10779 | return (src_w != dst_w || src_h != dst_h); | |
10780 | } | |
d21fbe87 | 10781 | |
da20eabd ML |
10782 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
10783 | struct drm_plane_state *plane_state) | |
10784 | { | |
ab1d3a0e | 10785 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
10786 | struct drm_crtc *crtc = crtc_state->crtc; |
10787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e9728bd8 | 10788 | struct intel_plane *plane = to_intel_plane(plane_state->plane); |
da20eabd | 10789 | struct drm_device *dev = crtc->dev; |
ed4a6a7c | 10790 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd | 10791 | struct intel_plane_state *old_plane_state = |
e9728bd8 | 10792 | to_intel_plane_state(plane->base.state); |
da20eabd ML |
10793 | bool mode_changed = needs_modeset(crtc_state); |
10794 | bool was_crtc_enabled = crtc->state->active; | |
10795 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
10796 | bool turn_off, turn_on, visible, was_visible; |
10797 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 10798 | int ret; |
da20eabd | 10799 | |
e9728bd8 | 10800 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
da20eabd ML |
10801 | ret = skl_update_scaler_plane( |
10802 | to_intel_crtc_state(crtc_state), | |
10803 | to_intel_plane_state(plane_state)); | |
10804 | if (ret) | |
10805 | return ret; | |
10806 | } | |
10807 | ||
936e71e3 | 10808 | was_visible = old_plane_state->base.visible; |
1d4258db | 10809 | visible = plane_state->visible; |
da20eabd ML |
10810 | |
10811 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
10812 | was_visible = false; | |
10813 | ||
35c08f43 ML |
10814 | /* |
10815 | * Visibility is calculated as if the crtc was on, but | |
10816 | * after scaler setup everything depends on it being off | |
10817 | * when the crtc isn't active. | |
f818ffea VS |
10818 | * |
10819 | * FIXME this is wrong for watermarks. Watermarks should also | |
10820 | * be computed as if the pipe would be active. Perhaps move | |
10821 | * per-plane wm computation to the .check_plane() hook, and | |
10822 | * only combine the results from all planes in the current place? | |
35c08f43 | 10823 | */ |
e9728bd8 | 10824 | if (!is_crtc_enabled) { |
1d4258db | 10825 | plane_state->visible = visible = false; |
e9728bd8 VS |
10826 | to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); |
10827 | } | |
da20eabd ML |
10828 | |
10829 | if (!was_visible && !visible) | |
10830 | return 0; | |
10831 | ||
e8861675 ML |
10832 | if (fb != old_plane_state->base.fb) |
10833 | pipe_config->fb_changed = true; | |
10834 | ||
da20eabd ML |
10835 | turn_off = was_visible && (!visible || mode_changed); |
10836 | turn_on = visible && (!was_visible || mode_changed); | |
10837 | ||
72660ce0 | 10838 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
e9728bd8 VS |
10839 | intel_crtc->base.base.id, intel_crtc->base.name, |
10840 | plane->base.base.id, plane->base.name, | |
72660ce0 | 10841 | fb ? fb->base.id : -1); |
da20eabd | 10842 | |
72660ce0 | 10843 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
e9728bd8 | 10844 | plane->base.base.id, plane->base.name, |
72660ce0 | 10845 | was_visible, visible, |
da20eabd ML |
10846 | turn_off, turn_on, mode_changed); |
10847 | ||
caed361d | 10848 | if (turn_on) { |
b4ede6df VS |
10849 | if (INTEL_GEN(dev_priv) < 5) |
10850 | pipe_config->update_wm_pre = true; | |
caed361d VS |
10851 | |
10852 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 10853 | if (plane->id != PLANE_CURSOR) |
caed361d VS |
10854 | pipe_config->disable_cxsr = true; |
10855 | } else if (turn_off) { | |
b4ede6df VS |
10856 | if (INTEL_GEN(dev_priv) < 5) |
10857 | pipe_config->update_wm_post = true; | |
92826fcd | 10858 | |
852eb00d | 10859 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 10860 | if (plane->id != PLANE_CURSOR) |
ab1d3a0e | 10861 | pipe_config->disable_cxsr = true; |
e9728bd8 | 10862 | } else if (intel_wm_need_update(&plane->base, plane_state)) { |
b4ede6df VS |
10863 | if (INTEL_GEN(dev_priv) < 5) { |
10864 | /* FIXME bollocks */ | |
10865 | pipe_config->update_wm_pre = true; | |
10866 | pipe_config->update_wm_post = true; | |
10867 | } | |
852eb00d | 10868 | } |
da20eabd | 10869 | |
8be6ca85 | 10870 | if (visible || was_visible) |
e9728bd8 | 10871 | pipe_config->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 10872 | |
31ae71fc ML |
10873 | /* |
10874 | * WaCxSRDisabledForSpriteScaling:ivb | |
10875 | * | |
10876 | * cstate->update_wm was already set above, so this flag will | |
10877 | * take effect when we commit and program watermarks. | |
10878 | */ | |
e9728bd8 | 10879 | if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
10880 | needs_scaling(to_intel_plane_state(plane_state)) && |
10881 | !needs_scaling(old_plane_state)) | |
10882 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 10883 | |
da20eabd ML |
10884 | return 0; |
10885 | } | |
10886 | ||
6d3a1ce7 ML |
10887 | static bool encoders_cloneable(const struct intel_encoder *a, |
10888 | const struct intel_encoder *b) | |
10889 | { | |
10890 | /* masks could be asymmetric, so check both ways */ | |
10891 | return a == b || (a->cloneable & (1 << b->type) && | |
10892 | b->cloneable & (1 << a->type)); | |
10893 | } | |
10894 | ||
10895 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
10896 | struct intel_crtc *crtc, | |
10897 | struct intel_encoder *encoder) | |
10898 | { | |
10899 | struct intel_encoder *source_encoder; | |
10900 | struct drm_connector *connector; | |
10901 | struct drm_connector_state *connector_state; | |
10902 | int i; | |
10903 | ||
10904 | for_each_connector_in_state(state, connector, connector_state, i) { | |
10905 | if (connector_state->crtc != &crtc->base) | |
10906 | continue; | |
10907 | ||
10908 | source_encoder = | |
10909 | to_intel_encoder(connector_state->best_encoder); | |
10910 | if (!encoders_cloneable(encoder, source_encoder)) | |
10911 | return false; | |
10912 | } | |
10913 | ||
10914 | return true; | |
10915 | } | |
10916 | ||
6d3a1ce7 ML |
10917 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
10918 | struct drm_crtc_state *crtc_state) | |
10919 | { | |
cf5a15be | 10920 | struct drm_device *dev = crtc->dev; |
fac5e23e | 10921 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 10922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
10923 | struct intel_crtc_state *pipe_config = |
10924 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 10925 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 10926 | int ret; |
6d3a1ce7 ML |
10927 | bool mode_changed = needs_modeset(crtc_state); |
10928 | ||
852eb00d | 10929 | if (mode_changed && !crtc_state->active) |
caed361d | 10930 | pipe_config->update_wm_post = true; |
eddfcbcd | 10931 | |
ad421372 ML |
10932 | if (mode_changed && crtc_state->enable && |
10933 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 10934 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
10935 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
10936 | pipe_config); | |
10937 | if (ret) | |
10938 | return ret; | |
10939 | } | |
10940 | ||
82cf435b LL |
10941 | if (crtc_state->color_mgmt_changed) { |
10942 | ret = intel_color_check(crtc, crtc_state); | |
10943 | if (ret) | |
10944 | return ret; | |
e7852a4b LL |
10945 | |
10946 | /* | |
10947 | * Changing color management on Intel hardware is | |
10948 | * handled as part of planes update. | |
10949 | */ | |
10950 | crtc_state->planes_changed = true; | |
82cf435b LL |
10951 | } |
10952 | ||
e435d6e5 | 10953 | ret = 0; |
86c8bbbe | 10954 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 10955 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
10956 | if (ret) { |
10957 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
10958 | return ret; | |
10959 | } | |
10960 | } | |
10961 | ||
10962 | if (dev_priv->display.compute_intermediate_wm && | |
10963 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
10964 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
10965 | return 0; | |
10966 | ||
10967 | /* | |
10968 | * Calculate 'intermediate' watermarks that satisfy both the | |
10969 | * old state and the new state. We can program these | |
10970 | * immediately. | |
10971 | */ | |
6315b5d3 | 10972 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
10973 | intel_crtc, |
10974 | pipe_config); | |
10975 | if (ret) { | |
10976 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 10977 | return ret; |
ed4a6a7c | 10978 | } |
e3d5457c VS |
10979 | } else if (dev_priv->display.compute_intermediate_wm) { |
10980 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
10981 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
10982 | } |
10983 | ||
6315b5d3 | 10984 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
10985 | if (mode_changed) |
10986 | ret = skl_update_scaler_crtc(pipe_config); | |
10987 | ||
10988 | if (!ret) | |
6ebc6923 | 10989 | ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, |
e435d6e5 ML |
10990 | pipe_config); |
10991 | } | |
10992 | ||
10993 | return ret; | |
6d3a1ce7 ML |
10994 | } |
10995 | ||
65b38e0d | 10996 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 10997 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
10998 | .atomic_begin = intel_begin_crtc_commit, |
10999 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11000 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11001 | }; |
11002 | ||
d29b2f9d ACO |
11003 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11004 | { | |
11005 | struct intel_connector *connector; | |
11006 | ||
11007 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
11008 | if (connector->base.state->crtc) |
11009 | drm_connector_unreference(&connector->base); | |
11010 | ||
d29b2f9d ACO |
11011 | if (connector->base.encoder) { |
11012 | connector->base.state->best_encoder = | |
11013 | connector->base.encoder; | |
11014 | connector->base.state->crtc = | |
11015 | connector->base.encoder->crtc; | |
8863dc7f DV |
11016 | |
11017 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
11018 | } else { |
11019 | connector->base.state->best_encoder = NULL; | |
11020 | connector->base.state->crtc = NULL; | |
11021 | } | |
11022 | } | |
11023 | } | |
11024 | ||
050f7aeb | 11025 | static void |
eba905b2 | 11026 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11027 | struct intel_crtc_state *pipe_config) |
050f7aeb | 11028 | { |
6a2a5c5d | 11029 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
11030 | int bpp = pipe_config->pipe_bpp; |
11031 | ||
11032 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
11033 | connector->base.base.id, |
11034 | connector->base.name); | |
050f7aeb DV |
11035 | |
11036 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 11037 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 11038 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
11039 | bpp, info->bpc * 3); |
11040 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
11041 | } |
11042 | ||
196f954e | 11043 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 11044 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
11045 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
11046 | bpp); | |
11047 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
11048 | } |
11049 | } | |
11050 | ||
4e53c2e0 | 11051 | static int |
050f7aeb | 11052 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11053 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11054 | { |
9beb5fea | 11055 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 11056 | struct drm_atomic_state *state; |
da3ced29 ACO |
11057 | struct drm_connector *connector; |
11058 | struct drm_connector_state *connector_state; | |
1486017f | 11059 | int bpp, i; |
4e53c2e0 | 11060 | |
9beb5fea TU |
11061 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
11062 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 11063 | bpp = 10*3; |
9beb5fea | 11064 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
11065 | bpp = 12*3; |
11066 | else | |
11067 | bpp = 8*3; | |
11068 | ||
4e53c2e0 | 11069 | |
4e53c2e0 DV |
11070 | pipe_config->pipe_bpp = bpp; |
11071 | ||
1486017f ACO |
11072 | state = pipe_config->base.state; |
11073 | ||
4e53c2e0 | 11074 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11075 | for_each_connector_in_state(state, connector, connector_state, i) { |
11076 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11077 | continue; |
11078 | ||
da3ced29 ACO |
11079 | connected_sink_compute_bpp(to_intel_connector(connector), |
11080 | pipe_config); | |
4e53c2e0 DV |
11081 | } |
11082 | ||
11083 | return bpp; | |
11084 | } | |
11085 | ||
644db711 DV |
11086 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11087 | { | |
11088 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11089 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11090 | mode->crtc_clock, |
644db711 DV |
11091 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11092 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11093 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11094 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11095 | } | |
11096 | ||
f6982332 TU |
11097 | static inline void |
11098 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 11099 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 11100 | { |
a4309657 TU |
11101 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11102 | id, lane_count, | |
f6982332 TU |
11103 | m_n->gmch_m, m_n->gmch_n, |
11104 | m_n->link_m, m_n->link_n, m_n->tu); | |
11105 | } | |
11106 | ||
c0b03411 | 11107 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11108 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11109 | const char *context) |
11110 | { | |
6a60cd87 | 11111 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 11112 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
11113 | struct drm_plane *plane; |
11114 | struct intel_plane *intel_plane; | |
11115 | struct intel_plane_state *state; | |
11116 | struct drm_framebuffer *fb; | |
11117 | ||
66766e4f TU |
11118 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
11119 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 11120 | |
2c89429e TU |
11121 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
11122 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 11123 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
11124 | |
11125 | if (pipe_config->has_pch_encoder) | |
11126 | intel_dump_m_n_config(pipe_config, "fdi", | |
11127 | pipe_config->fdi_lanes, | |
11128 | &pipe_config->fdi_m_n); | |
f6982332 TU |
11129 | |
11130 | if (intel_crtc_has_dp_encoder(pipe_config)) { | |
a4309657 TU |
11131 | intel_dump_m_n_config(pipe_config, "dp m_n", |
11132 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
11133 | if (pipe_config->has_drrs) |
11134 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
11135 | pipe_config->lane_count, | |
11136 | &pipe_config->dp_m2_n2); | |
f6982332 | 11137 | } |
b95af8be | 11138 | |
55072d19 | 11139 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 11140 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 11141 | |
c0b03411 | 11142 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11143 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11144 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11145 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11146 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
a7d1b3f4 | 11147 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", |
2c89429e | 11148 | pipe_config->port_clock, |
a7d1b3f4 VS |
11149 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
11150 | pipe_config->pixel_rate); | |
dd2f616d TU |
11151 | |
11152 | if (INTEL_GEN(dev_priv) >= 9) | |
11153 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
11154 | crtc->num_scalers, | |
11155 | pipe_config->scaler_state.scaler_users, | |
11156 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
11157 | |
11158 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
11159 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
11160 | pipe_config->gmch_pfit.control, | |
11161 | pipe_config->gmch_pfit.pgm_ratios, | |
11162 | pipe_config->gmch_pfit.lvds_border_bits); | |
11163 | else | |
11164 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
11165 | pipe_config->pch_pfit.pos, | |
11166 | pipe_config->pch_pfit.size, | |
08c4d7fc | 11167 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 11168 | |
2c89429e TU |
11169 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
11170 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 11171 | |
f50b79f0 | 11172 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 11173 | |
6a60cd87 CK |
11174 | DRM_DEBUG_KMS("planes on this crtc\n"); |
11175 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 11176 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
11177 | intel_plane = to_intel_plane(plane); |
11178 | if (intel_plane->pipe != crtc->pipe) | |
11179 | continue; | |
11180 | ||
11181 | state = to_intel_plane_state(plane->state); | |
11182 | fb = state->base.fb; | |
11183 | if (!fb) { | |
1d577e02 VS |
11184 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
11185 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
11186 | continue; |
11187 | } | |
11188 | ||
dd2f616d TU |
11189 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
11190 | plane->base.id, plane->name, | |
b3c11ac2 | 11191 | fb->base.id, fb->width, fb->height, |
438b74a5 | 11192 | drm_get_format_name(fb->format->format, &format_name)); |
dd2f616d TU |
11193 | if (INTEL_GEN(dev_priv) >= 9) |
11194 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
11195 | state->scaler_id, | |
11196 | state->base.src.x1 >> 16, | |
11197 | state->base.src.y1 >> 16, | |
11198 | drm_rect_width(&state->base.src) >> 16, | |
11199 | drm_rect_height(&state->base.src) >> 16, | |
11200 | state->base.dst.x1, state->base.dst.y1, | |
11201 | drm_rect_width(&state->base.dst), | |
11202 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 11203 | } |
c0b03411 DV |
11204 | } |
11205 | ||
5448a00d | 11206 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11207 | { |
5448a00d | 11208 | struct drm_device *dev = state->dev; |
da3ced29 | 11209 | struct drm_connector *connector; |
00f0b378 | 11210 | unsigned int used_ports = 0; |
477321e0 | 11211 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
11212 | |
11213 | /* | |
11214 | * Walk the connector list instead of the encoder | |
11215 | * list to detect the problem on ddi platforms | |
11216 | * where there's just one encoder per digital port. | |
11217 | */ | |
0bff4858 VS |
11218 | drm_for_each_connector(connector, dev) { |
11219 | struct drm_connector_state *connector_state; | |
11220 | struct intel_encoder *encoder; | |
11221 | ||
11222 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
11223 | if (!connector_state) | |
11224 | connector_state = connector->state; | |
11225 | ||
5448a00d | 11226 | if (!connector_state->best_encoder) |
00f0b378 VS |
11227 | continue; |
11228 | ||
5448a00d ACO |
11229 | encoder = to_intel_encoder(connector_state->best_encoder); |
11230 | ||
11231 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11232 | |
11233 | switch (encoder->type) { | |
11234 | unsigned int port_mask; | |
11235 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 11236 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 11237 | break; |
cca0502b | 11238 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
11239 | case INTEL_OUTPUT_HDMI: |
11240 | case INTEL_OUTPUT_EDP: | |
11241 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11242 | ||
11243 | /* the same port mustn't appear more than once */ | |
11244 | if (used_ports & port_mask) | |
11245 | return false; | |
11246 | ||
11247 | used_ports |= port_mask; | |
477321e0 VS |
11248 | break; |
11249 | case INTEL_OUTPUT_DP_MST: | |
11250 | used_mst_ports |= | |
11251 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
11252 | break; | |
00f0b378 VS |
11253 | default: |
11254 | break; | |
11255 | } | |
11256 | } | |
11257 | ||
477321e0 VS |
11258 | /* can't mix MST and SST/HDMI on the same port */ |
11259 | if (used_ports & used_mst_ports) | |
11260 | return false; | |
11261 | ||
00f0b378 VS |
11262 | return true; |
11263 | } | |
11264 | ||
83a57153 ACO |
11265 | static void |
11266 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11267 | { | |
ff32c54e VS |
11268 | struct drm_i915_private *dev_priv = |
11269 | to_i915(crtc_state->base.crtc->dev); | |
83a57153 | 11270 | struct drm_crtc_state tmp_state; |
663a3640 | 11271 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 11272 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 11273 | struct intel_shared_dpll *shared_dpll; |
ff32c54e | 11274 | struct intel_crtc_wm_state wm_state; |
c4e2d043 | 11275 | bool force_thru; |
83a57153 | 11276 | |
7546a384 ACO |
11277 | /* FIXME: before the switch to atomic started, a new pipe_config was |
11278 | * kzalloc'd. Code that depends on any field being zero should be | |
11279 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
11280 | * only fields that are know to not cause problems are preserved. */ | |
11281 | ||
83a57153 | 11282 | tmp_state = crtc_state->base; |
663a3640 | 11283 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
11284 | shared_dpll = crtc_state->shared_dpll; |
11285 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 11286 | force_thru = crtc_state->pch_pfit.force_thru; |
ff32c54e VS |
11287 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
11288 | wm_state = crtc_state->wm; | |
4978cc93 | 11289 | |
83a57153 | 11290 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 11291 | |
83a57153 | 11292 | crtc_state->base = tmp_state; |
663a3640 | 11293 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
11294 | crtc_state->shared_dpll = shared_dpll; |
11295 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 11296 | crtc_state->pch_pfit.force_thru = force_thru; |
ff32c54e VS |
11297 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
11298 | crtc_state->wm = wm_state; | |
83a57153 ACO |
11299 | } |
11300 | ||
548ee15b | 11301 | static int |
b8cecdf5 | 11302 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 11303 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 11304 | { |
b359283a | 11305 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 11306 | struct intel_encoder *encoder; |
da3ced29 | 11307 | struct drm_connector *connector; |
0b901879 | 11308 | struct drm_connector_state *connector_state; |
d328c9d7 | 11309 | int base_bpp, ret = -EINVAL; |
0b901879 | 11310 | int i; |
e29c22c0 | 11311 | bool retry = true; |
ee7b9f93 | 11312 | |
83a57153 | 11313 | clear_intel_crtc_state(pipe_config); |
7758a113 | 11314 | |
e143a21c DV |
11315 | pipe_config->cpu_transcoder = |
11316 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 11317 | |
2960bc9c ID |
11318 | /* |
11319 | * Sanitize sync polarity flags based on requested ones. If neither | |
11320 | * positive or negative polarity is requested, treat this as meaning | |
11321 | * negative polarity. | |
11322 | */ | |
2d112de7 | 11323 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11324 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11325 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11326 | |
2d112de7 | 11327 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11328 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11329 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11330 | |
d328c9d7 DV |
11331 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11332 | pipe_config); | |
11333 | if (base_bpp < 0) | |
4e53c2e0 DV |
11334 | goto fail; |
11335 | ||
e41a56be VS |
11336 | /* |
11337 | * Determine the real pipe dimensions. Note that stereo modes can | |
11338 | * increase the actual pipe size due to the frame doubling and | |
11339 | * insertion of additional space for blanks between the frame. This | |
11340 | * is stored in the crtc timings. We use the requested mode to do this | |
11341 | * computation to clearly distinguish it from the adjusted mode, which | |
11342 | * can be changed by the connectors in the below retry loop. | |
11343 | */ | |
196cd5d3 | 11344 | drm_mode_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11345 | &pipe_config->pipe_src_w, |
11346 | &pipe_config->pipe_src_h); | |
e41a56be | 11347 | |
253c84c8 VS |
11348 | for_each_connector_in_state(state, connector, connector_state, i) { |
11349 | if (connector_state->crtc != crtc) | |
11350 | continue; | |
11351 | ||
11352 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11353 | ||
e25148d0 VS |
11354 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
11355 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11356 | goto fail; | |
11357 | } | |
11358 | ||
253c84c8 VS |
11359 | /* |
11360 | * Determine output_types before calling the .compute_config() | |
11361 | * hooks so that the hooks can use this information safely. | |
11362 | */ | |
11363 | pipe_config->output_types |= 1 << encoder->type; | |
11364 | } | |
11365 | ||
e29c22c0 | 11366 | encoder_retry: |
ef1b460d | 11367 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11368 | pipe_config->port_clock = 0; |
ef1b460d | 11369 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11370 | |
135c81b8 | 11371 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11372 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11373 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11374 | |
7758a113 DV |
11375 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11376 | * adjust it according to limitations or connector properties, and also | |
11377 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11378 | */ |
da3ced29 | 11379 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 11380 | if (connector_state->crtc != crtc) |
7758a113 | 11381 | continue; |
7ae89233 | 11382 | |
0b901879 ACO |
11383 | encoder = to_intel_encoder(connector_state->best_encoder); |
11384 | ||
0a478c27 | 11385 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 11386 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
11387 | goto fail; |
11388 | } | |
ee7b9f93 | 11389 | } |
47f1c6c9 | 11390 | |
ff9a6750 DV |
11391 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11392 | * done afterwards in case the encoder adjusts the mode. */ | |
11393 | if (!pipe_config->port_clock) | |
2d112de7 | 11394 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11395 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11396 | |
a43f6e0f | 11397 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11398 | if (ret < 0) { |
7758a113 DV |
11399 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11400 | goto fail; | |
ee7b9f93 | 11401 | } |
e29c22c0 DV |
11402 | |
11403 | if (ret == RETRY) { | |
11404 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11405 | ret = -EINVAL; | |
11406 | goto fail; | |
11407 | } | |
11408 | ||
11409 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11410 | retry = false; | |
11411 | goto encoder_retry; | |
11412 | } | |
11413 | ||
e8fa4270 | 11414 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
11415 | * only enable it on 6bpc panels and when its not a compliance |
11416 | * test requesting 6bpc video pattern. | |
11417 | */ | |
11418 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
11419 | !pipe_config->dither_force_disable; | |
62f0ace5 | 11420 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11421 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11422 | |
7758a113 | 11423 | fail: |
548ee15b | 11424 | return ret; |
ee7b9f93 | 11425 | } |
47f1c6c9 | 11426 | |
ea9d758d | 11427 | static void |
4740b0f2 | 11428 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 11429 | { |
0a9ab303 ACO |
11430 | struct drm_crtc *crtc; |
11431 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 11432 | int i; |
ea9d758d | 11433 | |
7668851f | 11434 | /* Double check state. */ |
8a75d157 | 11435 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 11436 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
11437 | |
11438 | /* Update hwmode for vblank functions */ | |
11439 | if (crtc->state->active) | |
11440 | crtc->hwmode = crtc->state->adjusted_mode; | |
11441 | else | |
11442 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
11443 | |
11444 | /* | |
11445 | * Update legacy state to satisfy fbc code. This can | |
11446 | * be removed when fbc uses the atomic state. | |
11447 | */ | |
11448 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
11449 | struct drm_plane_state *plane_state = crtc->primary->state; | |
11450 | ||
11451 | crtc->primary->fb = plane_state->fb; | |
11452 | crtc->x = plane_state->src_x >> 16; | |
11453 | crtc->y = plane_state->src_y >> 16; | |
11454 | } | |
ea9d758d | 11455 | } |
ea9d758d DV |
11456 | } |
11457 | ||
3bd26263 | 11458 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11459 | { |
3bd26263 | 11460 | int diff; |
f1f644dc JB |
11461 | |
11462 | if (clock1 == clock2) | |
11463 | return true; | |
11464 | ||
11465 | if (!clock1 || !clock2) | |
11466 | return false; | |
11467 | ||
11468 | diff = abs(clock1 - clock2); | |
11469 | ||
11470 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11471 | return true; | |
11472 | ||
11473 | return false; | |
11474 | } | |
11475 | ||
cfb23ed6 ML |
11476 | static bool |
11477 | intel_compare_m_n(unsigned int m, unsigned int n, | |
11478 | unsigned int m2, unsigned int n2, | |
11479 | bool exact) | |
11480 | { | |
11481 | if (m == m2 && n == n2) | |
11482 | return true; | |
11483 | ||
11484 | if (exact || !m || !n || !m2 || !n2) | |
11485 | return false; | |
11486 | ||
11487 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
11488 | ||
31d10b57 ML |
11489 | if (n > n2) { |
11490 | while (n > n2) { | |
cfb23ed6 ML |
11491 | m2 <<= 1; |
11492 | n2 <<= 1; | |
11493 | } | |
31d10b57 ML |
11494 | } else if (n < n2) { |
11495 | while (n < n2) { | |
cfb23ed6 ML |
11496 | m <<= 1; |
11497 | n <<= 1; | |
11498 | } | |
11499 | } | |
11500 | ||
31d10b57 ML |
11501 | if (n != n2) |
11502 | return false; | |
11503 | ||
11504 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
11505 | } |
11506 | ||
11507 | static bool | |
11508 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
11509 | struct intel_link_m_n *m2_n2, | |
11510 | bool adjust) | |
11511 | { | |
11512 | if (m_n->tu == m2_n2->tu && | |
11513 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
11514 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
11515 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
11516 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
11517 | if (adjust) | |
11518 | *m2_n2 = *m_n; | |
11519 | ||
11520 | return true; | |
11521 | } | |
11522 | ||
11523 | return false; | |
11524 | } | |
11525 | ||
4e8048f8 TU |
11526 | static void __printf(3, 4) |
11527 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
11528 | { | |
11529 | char *level; | |
11530 | unsigned int category; | |
11531 | struct va_format vaf; | |
11532 | va_list args; | |
11533 | ||
11534 | if (adjust) { | |
11535 | level = KERN_DEBUG; | |
11536 | category = DRM_UT_KMS; | |
11537 | } else { | |
11538 | level = KERN_ERR; | |
11539 | category = DRM_UT_NONE; | |
11540 | } | |
11541 | ||
11542 | va_start(args, format); | |
11543 | vaf.fmt = format; | |
11544 | vaf.va = &args; | |
11545 | ||
11546 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
11547 | ||
11548 | va_end(args); | |
11549 | } | |
11550 | ||
0e8ffe1b | 11551 | static bool |
6315b5d3 | 11552 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 11553 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
11554 | struct intel_crtc_state *pipe_config, |
11555 | bool adjust) | |
0e8ffe1b | 11556 | { |
cfb23ed6 ML |
11557 | bool ret = true; |
11558 | ||
66e985c0 DV |
11559 | #define PIPE_CONF_CHECK_X(name) \ |
11560 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11561 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
11562 | "(expected 0x%08x, found 0x%08x)\n", \ |
11563 | current_config->name, \ | |
11564 | pipe_config->name); \ | |
cfb23ed6 | 11565 | ret = false; \ |
66e985c0 DV |
11566 | } |
11567 | ||
08a24034 DV |
11568 | #define PIPE_CONF_CHECK_I(name) \ |
11569 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11570 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
11571 | "(expected %i, found %i)\n", \ |
11572 | current_config->name, \ | |
11573 | pipe_config->name); \ | |
cfb23ed6 ML |
11574 | ret = false; \ |
11575 | } | |
11576 | ||
8106ddbd ACO |
11577 | #define PIPE_CONF_CHECK_P(name) \ |
11578 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11579 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
11580 | "(expected %p, found %p)\n", \ |
11581 | current_config->name, \ | |
11582 | pipe_config->name); \ | |
11583 | ret = false; \ | |
11584 | } | |
11585 | ||
cfb23ed6 ML |
11586 | #define PIPE_CONF_CHECK_M_N(name) \ |
11587 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11588 | &pipe_config->name,\ | |
11589 | adjust)) { \ | |
4e8048f8 | 11590 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11591 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11592 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11593 | current_config->name.tu, \ | |
11594 | current_config->name.gmch_m, \ | |
11595 | current_config->name.gmch_n, \ | |
11596 | current_config->name.link_m, \ | |
11597 | current_config->name.link_n, \ | |
11598 | pipe_config->name.tu, \ | |
11599 | pipe_config->name.gmch_m, \ | |
11600 | pipe_config->name.gmch_n, \ | |
11601 | pipe_config->name.link_m, \ | |
11602 | pipe_config->name.link_n); \ | |
11603 | ret = false; \ | |
11604 | } | |
11605 | ||
55c561a7 DV |
11606 | /* This is required for BDW+ where there is only one set of registers for |
11607 | * switching between high and low RR. | |
11608 | * This macro can be used whenever a comparison has to be made between one | |
11609 | * hw state and multiple sw state variables. | |
11610 | */ | |
cfb23ed6 ML |
11611 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
11612 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11613 | &pipe_config->name, adjust) && \ | |
11614 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
11615 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 11616 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11617 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11618 | "or tu %i gmch %i/%i link %i/%i, " \ | |
11619 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11620 | current_config->name.tu, \ | |
11621 | current_config->name.gmch_m, \ | |
11622 | current_config->name.gmch_n, \ | |
11623 | current_config->name.link_m, \ | |
11624 | current_config->name.link_n, \ | |
11625 | current_config->alt_name.tu, \ | |
11626 | current_config->alt_name.gmch_m, \ | |
11627 | current_config->alt_name.gmch_n, \ | |
11628 | current_config->alt_name.link_m, \ | |
11629 | current_config->alt_name.link_n, \ | |
11630 | pipe_config->name.tu, \ | |
11631 | pipe_config->name.gmch_m, \ | |
11632 | pipe_config->name.gmch_n, \ | |
11633 | pipe_config->name.link_m, \ | |
11634 | pipe_config->name.link_n); \ | |
11635 | ret = false; \ | |
88adfff1 DV |
11636 | } |
11637 | ||
1bd1bd80 DV |
11638 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11639 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
11640 | pipe_config_err(adjust, __stringify(name), \ |
11641 | "(%x) (expected %i, found %i)\n", \ | |
11642 | (mask), \ | |
1bd1bd80 DV |
11643 | current_config->name & (mask), \ |
11644 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 11645 | ret = false; \ |
1bd1bd80 DV |
11646 | } |
11647 | ||
5e550656 VS |
11648 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11649 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 11650 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
11651 | "(expected %i, found %i)\n", \ |
11652 | current_config->name, \ | |
11653 | pipe_config->name); \ | |
cfb23ed6 | 11654 | ret = false; \ |
5e550656 VS |
11655 | } |
11656 | ||
bb760063 DV |
11657 | #define PIPE_CONF_QUIRK(quirk) \ |
11658 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11659 | ||
eccb140b DV |
11660 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11661 | ||
08a24034 DV |
11662 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11663 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 11664 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 11665 | |
90a6b7b0 | 11666 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 11667 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 11668 | |
6315b5d3 | 11669 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
11670 | PIPE_CONF_CHECK_M_N(dp_m_n); |
11671 | ||
cfb23ed6 ML |
11672 | if (current_config->has_drrs) |
11673 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
11674 | } else | |
11675 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 11676 | |
253c84c8 | 11677 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 11678 | |
2d112de7 ACO |
11679 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11680 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11681 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11682 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11683 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11684 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11685 | |
2d112de7 ACO |
11686 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11687 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11688 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11689 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11690 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11691 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11692 | |
c93f54cf | 11693 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11694 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 11695 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 11696 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 11697 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 11698 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11699 | |
9ed109a7 DV |
11700 | PIPE_CONF_CHECK_I(has_audio); |
11701 | ||
2d112de7 | 11702 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11703 | DRM_MODE_FLAG_INTERLACE); |
11704 | ||
bb760063 | 11705 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11706 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11707 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11708 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11709 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11710 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11711 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11712 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11713 | DRM_MODE_FLAG_NVSYNC); |
11714 | } | |
045ac3b5 | 11715 | |
333b8ca8 | 11716 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 11717 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 11718 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 11719 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 11720 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 11721 | |
bfd16b2a ML |
11722 | if (!adjust) { |
11723 | PIPE_CONF_CHECK_I(pipe_src_w); | |
11724 | PIPE_CONF_CHECK_I(pipe_src_h); | |
11725 | ||
11726 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
11727 | if (current_config->pch_pfit.enabled) { | |
11728 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
11729 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
11730 | } | |
2fa2fe9a | 11731 | |
7aefe2b5 | 11732 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 11733 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
7aefe2b5 | 11734 | } |
a1b2278e | 11735 | |
e59150dc | 11736 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 11737 | if (IS_HASWELL(dev_priv)) |
e59150dc | 11738 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 11739 | |
282740f7 VS |
11740 | PIPE_CONF_CHECK_I(double_wide); |
11741 | ||
8106ddbd | 11742 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 11743 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11744 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11745 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11746 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11747 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 11748 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
11749 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11750 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11751 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11752 | |
47eacbab VS |
11753 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
11754 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
11755 | ||
9beb5fea | 11756 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
11757 | PIPE_CONF_CHECK_I(pipe_bpp); |
11758 | ||
2d112de7 | 11759 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11760 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11761 | |
66e985c0 | 11762 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11763 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 11764 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 11765 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11766 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11767 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11768 | |
cfb23ed6 | 11769 | return ret; |
0e8ffe1b DV |
11770 | } |
11771 | ||
e3b247da VS |
11772 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
11773 | const struct intel_crtc_state *pipe_config) | |
11774 | { | |
11775 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 11776 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
11777 | &pipe_config->fdi_m_n); |
11778 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
11779 | ||
11780 | /* | |
11781 | * FDI already provided one idea for the dotclock. | |
11782 | * Yell if the encoder disagrees. | |
11783 | */ | |
11784 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
11785 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
11786 | fdi_dotclock, dotclock); | |
11787 | } | |
11788 | } | |
11789 | ||
c0ead703 ML |
11790 | static void verify_wm_state(struct drm_crtc *crtc, |
11791 | struct drm_crtc_state *new_state) | |
08db6652 | 11792 | { |
6315b5d3 | 11793 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 11794 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 11795 | struct skl_pipe_wm hw_wm, *sw_wm; |
11796 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
11797 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
11798 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11799 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 11800 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 11801 | |
6315b5d3 | 11802 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
11803 | return; |
11804 | ||
3de8a14c | 11805 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 11806 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 11807 | |
08db6652 DL |
11808 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
11809 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11810 | ||
e7c84544 | 11811 | /* planes */ |
8b364b41 | 11812 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 11813 | hw_plane_wm = &hw_wm.planes[plane]; |
11814 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 11815 | |
3de8a14c | 11816 | /* Watermarks */ |
11817 | for (level = 0; level <= max_level; level++) { | |
11818 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11819 | &sw_plane_wm->wm[level])) | |
11820 | continue; | |
11821 | ||
11822 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11823 | pipe_name(pipe), plane + 1, level, | |
11824 | sw_plane_wm->wm[level].plane_en, | |
11825 | sw_plane_wm->wm[level].plane_res_b, | |
11826 | sw_plane_wm->wm[level].plane_res_l, | |
11827 | hw_plane_wm->wm[level].plane_en, | |
11828 | hw_plane_wm->wm[level].plane_res_b, | |
11829 | hw_plane_wm->wm[level].plane_res_l); | |
11830 | } | |
08db6652 | 11831 | |
3de8a14c | 11832 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
11833 | &sw_plane_wm->trans_wm)) { | |
11834 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11835 | pipe_name(pipe), plane + 1, | |
11836 | sw_plane_wm->trans_wm.plane_en, | |
11837 | sw_plane_wm->trans_wm.plane_res_b, | |
11838 | sw_plane_wm->trans_wm.plane_res_l, | |
11839 | hw_plane_wm->trans_wm.plane_en, | |
11840 | hw_plane_wm->trans_wm.plane_res_b, | |
11841 | hw_plane_wm->trans_wm.plane_res_l); | |
11842 | } | |
11843 | ||
11844 | /* DDB */ | |
11845 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
11846 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
11847 | ||
11848 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 11849 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 11850 | pipe_name(pipe), plane + 1, |
11851 | sw_ddb_entry->start, sw_ddb_entry->end, | |
11852 | hw_ddb_entry->start, hw_ddb_entry->end); | |
11853 | } | |
e7c84544 | 11854 | } |
08db6652 | 11855 | |
27082493 L |
11856 | /* |
11857 | * cursor | |
11858 | * If the cursor plane isn't active, we may not have updated it's ddb | |
11859 | * allocation. In that case since the ddb allocation will be updated | |
11860 | * once the plane becomes visible, we can skip this check | |
11861 | */ | |
11862 | if (intel_crtc->cursor_addr) { | |
3de8a14c | 11863 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
11864 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
11865 | ||
11866 | /* Watermarks */ | |
11867 | for (level = 0; level <= max_level; level++) { | |
11868 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11869 | &sw_plane_wm->wm[level])) | |
11870 | continue; | |
11871 | ||
11872 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11873 | pipe_name(pipe), level, | |
11874 | sw_plane_wm->wm[level].plane_en, | |
11875 | sw_plane_wm->wm[level].plane_res_b, | |
11876 | sw_plane_wm->wm[level].plane_res_l, | |
11877 | hw_plane_wm->wm[level].plane_en, | |
11878 | hw_plane_wm->wm[level].plane_res_b, | |
11879 | hw_plane_wm->wm[level].plane_res_l); | |
11880 | } | |
11881 | ||
11882 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
11883 | &sw_plane_wm->trans_wm)) { | |
11884 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11885 | pipe_name(pipe), | |
11886 | sw_plane_wm->trans_wm.plane_en, | |
11887 | sw_plane_wm->trans_wm.plane_res_b, | |
11888 | sw_plane_wm->trans_wm.plane_res_l, | |
11889 | hw_plane_wm->trans_wm.plane_en, | |
11890 | hw_plane_wm->trans_wm.plane_res_b, | |
11891 | hw_plane_wm->trans_wm.plane_res_l); | |
11892 | } | |
11893 | ||
11894 | /* DDB */ | |
11895 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
11896 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 11897 | |
3de8a14c | 11898 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 11899 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 11900 | pipe_name(pipe), |
3de8a14c | 11901 | sw_ddb_entry->start, sw_ddb_entry->end, |
11902 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 11903 | } |
08db6652 DL |
11904 | } |
11905 | } | |
11906 | ||
91d1b4bd | 11907 | static void |
677100ce ML |
11908 | verify_connector_state(struct drm_device *dev, |
11909 | struct drm_atomic_state *state, | |
11910 | struct drm_crtc *crtc) | |
8af6cf88 | 11911 | { |
35dd3c64 | 11912 | struct drm_connector *connector; |
677100ce ML |
11913 | struct drm_connector_state *old_conn_state; |
11914 | int i; | |
8af6cf88 | 11915 | |
677100ce | 11916 | for_each_connector_in_state(state, connector, old_conn_state, i) { |
35dd3c64 ML |
11917 | struct drm_encoder *encoder = connector->encoder; |
11918 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 11919 | |
e7c84544 ML |
11920 | if (state->crtc != crtc) |
11921 | continue; | |
11922 | ||
5a21b665 | 11923 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 11924 | |
ad3c558f | 11925 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 11926 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 11927 | } |
91d1b4bd DV |
11928 | } |
11929 | ||
11930 | static void | |
c0ead703 | 11931 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
11932 | { |
11933 | struct intel_encoder *encoder; | |
11934 | struct intel_connector *connector; | |
8af6cf88 | 11935 | |
b2784e15 | 11936 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 11937 | bool enabled = false; |
4d20cd86 | 11938 | enum pipe pipe; |
8af6cf88 DV |
11939 | |
11940 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11941 | encoder->base.base.id, | |
8e329a03 | 11942 | encoder->base.name); |
8af6cf88 | 11943 | |
3a3371ff | 11944 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 11945 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
11946 | continue; |
11947 | enabled = true; | |
ad3c558f ML |
11948 | |
11949 | I915_STATE_WARN(connector->base.state->crtc != | |
11950 | encoder->base.crtc, | |
11951 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 11952 | } |
0e32b39c | 11953 | |
e2c719b7 | 11954 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11955 | "encoder's enabled state mismatch " |
11956 | "(expected %i, found %i)\n", | |
11957 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
11958 | |
11959 | if (!encoder->base.crtc) { | |
4d20cd86 | 11960 | bool active; |
7c60d198 | 11961 | |
4d20cd86 ML |
11962 | active = encoder->get_hw_state(encoder, &pipe); |
11963 | I915_STATE_WARN(active, | |
11964 | "encoder detached but still enabled on pipe %c.\n", | |
11965 | pipe_name(pipe)); | |
7c60d198 | 11966 | } |
8af6cf88 | 11967 | } |
91d1b4bd DV |
11968 | } |
11969 | ||
11970 | static void | |
c0ead703 ML |
11971 | verify_crtc_state(struct drm_crtc *crtc, |
11972 | struct drm_crtc_state *old_crtc_state, | |
11973 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 11974 | { |
e7c84544 | 11975 | struct drm_device *dev = crtc->dev; |
fac5e23e | 11976 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 11977 | struct intel_encoder *encoder; |
e7c84544 ML |
11978 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11979 | struct intel_crtc_state *pipe_config, *sw_config; | |
11980 | struct drm_atomic_state *old_state; | |
11981 | bool active; | |
045ac3b5 | 11982 | |
e7c84544 | 11983 | old_state = old_crtc_state->state; |
ec2dc6a0 | 11984 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
11985 | pipe_config = to_intel_crtc_state(old_crtc_state); |
11986 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
11987 | pipe_config->base.crtc = crtc; | |
11988 | pipe_config->base.state = old_state; | |
8af6cf88 | 11989 | |
78108b7c | 11990 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 11991 | |
e7c84544 | 11992 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 11993 | |
e7c84544 ML |
11994 | /* hw state is inconsistent with the pipe quirk */ |
11995 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
11996 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
11997 | active = new_crtc_state->active; | |
6c49f241 | 11998 | |
e7c84544 ML |
11999 | I915_STATE_WARN(new_crtc_state->active != active, |
12000 | "crtc active state doesn't match with hw state " | |
12001 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 12002 | |
e7c84544 ML |
12003 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
12004 | "transitional active state does not match atomic hw state " | |
12005 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 12006 | |
e7c84544 ML |
12007 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
12008 | enum pipe pipe; | |
4d20cd86 | 12009 | |
e7c84544 ML |
12010 | active = encoder->get_hw_state(encoder, &pipe); |
12011 | I915_STATE_WARN(active != new_crtc_state->active, | |
12012 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12013 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 12014 | |
e7c84544 ML |
12015 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
12016 | "Encoder connected to wrong pipe %c\n", | |
12017 | pipe_name(pipe)); | |
4d20cd86 | 12018 | |
253c84c8 VS |
12019 | if (active) { |
12020 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 12021 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 12022 | } |
e7c84544 | 12023 | } |
53d9f4e9 | 12024 | |
a7d1b3f4 VS |
12025 | intel_crtc_compute_pixel_rate(pipe_config); |
12026 | ||
e7c84544 ML |
12027 | if (!new_crtc_state->active) |
12028 | return; | |
cfb23ed6 | 12029 | |
e7c84544 | 12030 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 12031 | |
e7c84544 | 12032 | sw_config = to_intel_crtc_state(crtc->state); |
6315b5d3 | 12033 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
12034 | pipe_config, false)) { |
12035 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
12036 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
12037 | "[hw state]"); | |
12038 | intel_dump_pipe_config(intel_crtc, sw_config, | |
12039 | "[sw state]"); | |
8af6cf88 DV |
12040 | } |
12041 | } | |
12042 | ||
91d1b4bd | 12043 | static void |
c0ead703 ML |
12044 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
12045 | struct intel_shared_dpll *pll, | |
12046 | struct drm_crtc *crtc, | |
12047 | struct drm_crtc_state *new_state) | |
91d1b4bd | 12048 | { |
91d1b4bd | 12049 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
12050 | unsigned crtc_mask; |
12051 | bool active; | |
5358901f | 12052 | |
e7c84544 | 12053 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 12054 | |
e7c84544 | 12055 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 12056 | |
e7c84544 | 12057 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12058 | |
e7c84544 ML |
12059 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
12060 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
12061 | "pll in active use but not on in sw tracking\n"); | |
12062 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12063 | "pll is on but not used by any active crtc\n"); | |
12064 | I915_STATE_WARN(pll->on != active, | |
12065 | "pll on state mismatch (expected %i, found %i)\n", | |
12066 | pll->on, active); | |
12067 | } | |
5358901f | 12068 | |
e7c84544 | 12069 | if (!crtc) { |
2c42e535 | 12070 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 12071 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 12072 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 12073 | |
e7c84544 ML |
12074 | return; |
12075 | } | |
12076 | ||
12077 | crtc_mask = 1 << drm_crtc_index(crtc); | |
12078 | ||
12079 | if (new_state->active) | |
12080 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
12081 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
12082 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
12083 | else | |
12084 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12085 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
12086 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 12087 | |
2c42e535 | 12088 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 12089 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 12090 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 12091 | |
2c42e535 | 12092 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
12093 | &dpll_hw_state, |
12094 | sizeof(dpll_hw_state)), | |
12095 | "pll hw state mismatch\n"); | |
12096 | } | |
12097 | ||
12098 | static void | |
c0ead703 ML |
12099 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
12100 | struct drm_crtc_state *old_crtc_state, | |
12101 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 12102 | { |
fac5e23e | 12103 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
12104 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
12105 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
12106 | ||
12107 | if (new_state->shared_dpll) | |
c0ead703 | 12108 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
12109 | |
12110 | if (old_state->shared_dpll && | |
12111 | old_state->shared_dpll != new_state->shared_dpll) { | |
12112 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
12113 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
12114 | ||
12115 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12116 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
12117 | pipe_name(drm_crtc_index(crtc))); | |
2c42e535 | 12118 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 ML |
12119 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
12120 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 12121 | } |
8af6cf88 DV |
12122 | } |
12123 | ||
e7c84544 | 12124 | static void |
c0ead703 | 12125 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
12126 | struct drm_atomic_state *state, |
12127 | struct drm_crtc_state *old_state, | |
12128 | struct drm_crtc_state *new_state) | |
e7c84544 | 12129 | { |
5a21b665 DV |
12130 | if (!needs_modeset(new_state) && |
12131 | !to_intel_crtc_state(new_state)->update_pipe) | |
12132 | return; | |
12133 | ||
c0ead703 | 12134 | verify_wm_state(crtc, new_state); |
677100ce | 12135 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
12136 | verify_crtc_state(crtc, old_state, new_state); |
12137 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
12138 | } |
12139 | ||
12140 | static void | |
c0ead703 | 12141 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 12142 | { |
fac5e23e | 12143 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
12144 | int i; |
12145 | ||
12146 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 12147 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
12148 | } |
12149 | ||
12150 | static void | |
677100ce ML |
12151 | intel_modeset_verify_disabled(struct drm_device *dev, |
12152 | struct drm_atomic_state *state) | |
e7c84544 | 12153 | { |
c0ead703 | 12154 | verify_encoder_state(dev); |
677100ce | 12155 | verify_connector_state(dev, state, NULL); |
c0ead703 | 12156 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
12157 | } |
12158 | ||
80715b2f VS |
12159 | static void update_scanline_offset(struct intel_crtc *crtc) |
12160 | { | |
4f8036a2 | 12161 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
12162 | |
12163 | /* | |
12164 | * The scanline counter increments at the leading edge of hsync. | |
12165 | * | |
12166 | * On most platforms it starts counting from vtotal-1 on the | |
12167 | * first active line. That means the scanline counter value is | |
12168 | * always one less than what we would expect. Ie. just after | |
12169 | * start of vblank, which also occurs at start of hsync (on the | |
12170 | * last active line), the scanline counter will read vblank_start-1. | |
12171 | * | |
12172 | * On gen2 the scanline counter starts counting from 1 instead | |
12173 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12174 | * to keep the value positive), instead of adding one. | |
12175 | * | |
12176 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12177 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12178 | * there's an extra 1 line difference. So we need to add two instead of | |
12179 | * one to the value. | |
12180 | */ | |
4f8036a2 | 12181 | if (IS_GEN2(dev_priv)) { |
124abe07 | 12182 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12183 | int vtotal; |
12184 | ||
124abe07 VS |
12185 | vtotal = adjusted_mode->crtc_vtotal; |
12186 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
12187 | vtotal /= 2; |
12188 | ||
12189 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 12190 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 12191 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12192 | crtc->scanline_offset = 2; |
12193 | } else | |
12194 | crtc->scanline_offset = 1; | |
12195 | } | |
12196 | ||
ad421372 | 12197 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12198 | { |
225da59b | 12199 | struct drm_device *dev = state->dev; |
ed6739ef | 12200 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 ACO |
12201 | struct drm_crtc *crtc; |
12202 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 12203 | int i; |
ed6739ef ACO |
12204 | |
12205 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12206 | return; |
ed6739ef | 12207 | |
0a9ab303 | 12208 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 12209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
12210 | struct intel_shared_dpll *old_dpll = |
12211 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 12212 | |
fb1a38a9 | 12213 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
12214 | continue; |
12215 | ||
8106ddbd | 12216 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 12217 | |
8106ddbd | 12218 | if (!old_dpll) |
fb1a38a9 | 12219 | continue; |
0a9ab303 | 12220 | |
a1c414ee | 12221 | intel_release_shared_dpll(old_dpll, intel_crtc, state); |
ad421372 | 12222 | } |
ed6739ef ACO |
12223 | } |
12224 | ||
99d736a2 ML |
12225 | /* |
12226 | * This implements the workaround described in the "notes" section of the mode | |
12227 | * set sequence documentation. When going from no pipes or single pipe to | |
12228 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12229 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12230 | */ | |
12231 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12232 | { | |
12233 | struct drm_crtc_state *crtc_state; | |
12234 | struct intel_crtc *intel_crtc; | |
12235 | struct drm_crtc *crtc; | |
12236 | struct intel_crtc_state *first_crtc_state = NULL; | |
12237 | struct intel_crtc_state *other_crtc_state = NULL; | |
12238 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12239 | int i; | |
12240 | ||
12241 | /* look at all crtc's that are going to be enabled in during modeset */ | |
12242 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12243 | intel_crtc = to_intel_crtc(crtc); | |
12244 | ||
12245 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12246 | continue; | |
12247 | ||
12248 | if (first_crtc_state) { | |
12249 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
12250 | break; | |
12251 | } else { | |
12252 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
12253 | first_pipe = intel_crtc->pipe; | |
12254 | } | |
12255 | } | |
12256 | ||
12257 | /* No workaround needed? */ | |
12258 | if (!first_crtc_state) | |
12259 | return 0; | |
12260 | ||
12261 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
12262 | for_each_intel_crtc(state->dev, intel_crtc) { | |
12263 | struct intel_crtc_state *pipe_config; | |
12264 | ||
12265 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12266 | if (IS_ERR(pipe_config)) | |
12267 | return PTR_ERR(pipe_config); | |
12268 | ||
12269 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
12270 | ||
12271 | if (!pipe_config->base.active || | |
12272 | needs_modeset(&pipe_config->base)) | |
12273 | continue; | |
12274 | ||
12275 | /* 2 or more enabled crtcs means no need for w/a */ | |
12276 | if (enabled_pipe != INVALID_PIPE) | |
12277 | return 0; | |
12278 | ||
12279 | enabled_pipe = intel_crtc->pipe; | |
12280 | } | |
12281 | ||
12282 | if (enabled_pipe != INVALID_PIPE) | |
12283 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
12284 | else if (other_crtc_state) | |
12285 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
12286 | ||
12287 | return 0; | |
12288 | } | |
12289 | ||
8d96561a VS |
12290 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
12291 | { | |
12292 | struct drm_crtc *crtc; | |
12293 | ||
12294 | /* Add all pipes to the state */ | |
12295 | for_each_crtc(state->dev, crtc) { | |
12296 | struct drm_crtc_state *crtc_state; | |
12297 | ||
12298 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
12299 | if (IS_ERR(crtc_state)) | |
12300 | return PTR_ERR(crtc_state); | |
12301 | } | |
12302 | ||
12303 | return 0; | |
12304 | } | |
12305 | ||
27c329ed ML |
12306 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
12307 | { | |
12308 | struct drm_crtc *crtc; | |
27c329ed | 12309 | |
8d96561a VS |
12310 | /* |
12311 | * Add all pipes to the state, and force | |
12312 | * a modeset on all the active ones. | |
12313 | */ | |
27c329ed | 12314 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
12315 | struct drm_crtc_state *crtc_state; |
12316 | int ret; | |
12317 | ||
27c329ed ML |
12318 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
12319 | if (IS_ERR(crtc_state)) | |
12320 | return PTR_ERR(crtc_state); | |
12321 | ||
12322 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
12323 | continue; | |
12324 | ||
12325 | crtc_state->mode_changed = true; | |
12326 | ||
12327 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12328 | if (ret) | |
9780aad5 | 12329 | return ret; |
27c329ed ML |
12330 | |
12331 | ret = drm_atomic_add_affected_planes(state, crtc); | |
12332 | if (ret) | |
9780aad5 | 12333 | return ret; |
27c329ed ML |
12334 | } |
12335 | ||
9780aad5 | 12336 | return 0; |
27c329ed ML |
12337 | } |
12338 | ||
c347a676 | 12339 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 12340 | { |
565602d7 | 12341 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12342 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
12343 | struct drm_crtc *crtc; |
12344 | struct drm_crtc_state *crtc_state; | |
12345 | int ret = 0, i; | |
054518dd | 12346 | |
b359283a ML |
12347 | if (!check_digital_port_conflicts(state)) { |
12348 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
12349 | return -EINVAL; | |
12350 | } | |
12351 | ||
565602d7 ML |
12352 | intel_state->modeset = true; |
12353 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
bb0f4aab VS |
12354 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
12355 | intel_state->cdclk.actual = dev_priv->cdclk.actual; | |
565602d7 ML |
12356 | |
12357 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12358 | if (crtc_state->active) | |
12359 | intel_state->active_crtcs |= 1 << i; | |
12360 | else | |
12361 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
12362 | |
12363 | if (crtc_state->active != crtc->state->active) | |
12364 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
12365 | } |
12366 | ||
054518dd ACO |
12367 | /* |
12368 | * See if the config requires any additional preparation, e.g. | |
12369 | * to adjust global state with pipes off. We need to do this | |
12370 | * here so we can get the modeset_pipe updated config for the new | |
12371 | * mode set on this crtc. For other crtcs we need to use the | |
12372 | * adjusted_mode bits in the crtc directly. | |
12373 | */ | |
27c329ed | 12374 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed | 12375 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
12376 | if (ret < 0) |
12377 | return ret; | |
27c329ed | 12378 | |
8d96561a | 12379 | /* |
bb0f4aab | 12380 | * Writes to dev_priv->cdclk.logical must protected by |
8d96561a VS |
12381 | * holding all the crtc locks, even if we don't end up |
12382 | * touching the hardware | |
12383 | */ | |
bb0f4aab VS |
12384 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical, |
12385 | &intel_state->cdclk.logical)) { | |
8d96561a VS |
12386 | ret = intel_lock_all_pipes(state); |
12387 | if (ret < 0) | |
12388 | return ret; | |
12389 | } | |
12390 | ||
12391 | /* All pipes must be switched off while we change the cdclk. */ | |
bb0f4aab VS |
12392 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual, |
12393 | &intel_state->cdclk.actual)) { | |
27c329ed | 12394 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
12395 | if (ret < 0) |
12396 | return ret; | |
12397 | } | |
e8788cbc | 12398 | |
bb0f4aab VS |
12399 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", |
12400 | intel_state->cdclk.logical.cdclk, | |
12401 | intel_state->cdclk.actual.cdclk); | |
e0ca7a6b | 12402 | } else { |
bb0f4aab | 12403 | to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12404 | } |
054518dd | 12405 | |
ad421372 | 12406 | intel_modeset_clear_plls(state); |
054518dd | 12407 | |
565602d7 | 12408 | if (IS_HASWELL(dev_priv)) |
ad421372 | 12409 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 12410 | |
ad421372 | 12411 | return 0; |
c347a676 ACO |
12412 | } |
12413 | ||
aa363136 MR |
12414 | /* |
12415 | * Handle calculation of various watermark data at the end of the atomic check | |
12416 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
12417 | * handlers to ensure that all derived state has been updated. | |
12418 | */ | |
55994c2c | 12419 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
12420 | { |
12421 | struct drm_device *dev = state->dev; | |
98d39494 | 12422 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
12423 | |
12424 | /* Is there platform-specific watermark information to calculate? */ | |
12425 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
12426 | return dev_priv->display.compute_global_watermarks(state); |
12427 | ||
12428 | return 0; | |
aa363136 MR |
12429 | } |
12430 | ||
74c090b1 ML |
12431 | /** |
12432 | * intel_atomic_check - validate state object | |
12433 | * @dev: drm device | |
12434 | * @state: state to validate | |
12435 | */ | |
12436 | static int intel_atomic_check(struct drm_device *dev, | |
12437 | struct drm_atomic_state *state) | |
c347a676 | 12438 | { |
dd8b3bdb | 12439 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 12440 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
12441 | struct drm_crtc *crtc; |
12442 | struct drm_crtc_state *crtc_state; | |
12443 | int ret, i; | |
61333b60 | 12444 | bool any_ms = false; |
c347a676 | 12445 | |
74c090b1 | 12446 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
12447 | if (ret) |
12448 | return ret; | |
12449 | ||
c347a676 | 12450 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
12451 | struct intel_crtc_state *pipe_config = |
12452 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
12453 | |
12454 | /* Catch I915_MODE_FLAG_INHERITED */ | |
12455 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
12456 | crtc_state->mode_changed = true; | |
cfb23ed6 | 12457 | |
af4a879e | 12458 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
12459 | continue; |
12460 | ||
af4a879e DV |
12461 | if (!crtc_state->enable) { |
12462 | any_ms = true; | |
cfb23ed6 | 12463 | continue; |
af4a879e | 12464 | } |
cfb23ed6 | 12465 | |
26495481 DV |
12466 | /* FIXME: For only active_changed we shouldn't need to do any |
12467 | * state recomputation at all. */ | |
12468 | ||
1ed51de9 DV |
12469 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12470 | if (ret) | |
12471 | return ret; | |
b359283a | 12472 | |
cfb23ed6 | 12473 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
12474 | if (ret) { |
12475 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12476 | pipe_config, "[failed]"); | |
c347a676 | 12477 | return ret; |
25aa1c39 | 12478 | } |
c347a676 | 12479 | |
73831236 | 12480 | if (i915.fastboot && |
6315b5d3 | 12481 | intel_pipe_config_compare(dev_priv, |
cfb23ed6 | 12482 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 12483 | pipe_config, true)) { |
26495481 | 12484 | crtc_state->mode_changed = false; |
bfd16b2a | 12485 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
12486 | } |
12487 | ||
af4a879e | 12488 | if (needs_modeset(crtc_state)) |
26495481 | 12489 | any_ms = true; |
cfb23ed6 | 12490 | |
af4a879e DV |
12491 | ret = drm_atomic_add_affected_planes(state, crtc); |
12492 | if (ret) | |
12493 | return ret; | |
61333b60 | 12494 | |
26495481 DV |
12495 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12496 | needs_modeset(crtc_state) ? | |
12497 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
12498 | } |
12499 | ||
61333b60 ML |
12500 | if (any_ms) { |
12501 | ret = intel_modeset_checks(state); | |
12502 | ||
12503 | if (ret) | |
12504 | return ret; | |
e0ca7a6b | 12505 | } else { |
bb0f4aab | 12506 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12507 | } |
76305b1a | 12508 | |
dd8b3bdb | 12509 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
12510 | if (ret) |
12511 | return ret; | |
12512 | ||
f51be2e0 | 12513 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 12514 | return calc_watermark_data(state); |
054518dd ACO |
12515 | } |
12516 | ||
5008e874 | 12517 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 12518 | struct drm_atomic_state *state) |
5008e874 | 12519 | { |
fac5e23e | 12520 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 ML |
12521 | struct drm_crtc_state *crtc_state; |
12522 | struct drm_crtc *crtc; | |
12523 | int i, ret; | |
12524 | ||
5a21b665 DV |
12525 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12526 | if (state->legacy_cursor_update) | |
a6747b73 ML |
12527 | continue; |
12528 | ||
5a21b665 DV |
12529 | ret = intel_crtc_wait_for_pending_flips(crtc); |
12530 | if (ret) | |
12531 | return ret; | |
5008e874 | 12532 | |
5a21b665 DV |
12533 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
12534 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
12535 | } |
12536 | ||
f935675f ML |
12537 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
12538 | if (ret) | |
12539 | return ret; | |
12540 | ||
5008e874 | 12541 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 12542 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 12543 | |
5008e874 ML |
12544 | return ret; |
12545 | } | |
12546 | ||
a2991414 ML |
12547 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
12548 | { | |
12549 | struct drm_device *dev = crtc->base.dev; | |
12550 | ||
12551 | if (!dev->max_vblank_count) | |
12552 | return drm_accurate_vblank_count(&crtc->base); | |
12553 | ||
12554 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
12555 | } | |
12556 | ||
5a21b665 DV |
12557 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
12558 | struct drm_i915_private *dev_priv, | |
12559 | unsigned crtc_mask) | |
e8861675 | 12560 | { |
5a21b665 DV |
12561 | unsigned last_vblank_count[I915_MAX_PIPES]; |
12562 | enum pipe pipe; | |
12563 | int ret; | |
e8861675 | 12564 | |
5a21b665 DV |
12565 | if (!crtc_mask) |
12566 | return; | |
e8861675 | 12567 | |
5a21b665 | 12568 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12569 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12570 | pipe); | |
e8861675 | 12571 | |
5a21b665 | 12572 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
12573 | continue; |
12574 | ||
e2af48c6 | 12575 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
12576 | if (WARN_ON(ret != 0)) { |
12577 | crtc_mask &= ~(1 << pipe); | |
12578 | continue; | |
e8861675 ML |
12579 | } |
12580 | ||
e2af48c6 | 12581 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
12582 | } |
12583 | ||
5a21b665 | 12584 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12585 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12586 | pipe); | |
5a21b665 | 12587 | long lret; |
e8861675 | 12588 | |
5a21b665 DV |
12589 | if (!((1 << pipe) & crtc_mask)) |
12590 | continue; | |
d55dbd06 | 12591 | |
5a21b665 DV |
12592 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
12593 | last_vblank_count[pipe] != | |
e2af48c6 | 12594 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 12595 | msecs_to_jiffies(50)); |
d55dbd06 | 12596 | |
5a21b665 | 12597 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 12598 | |
e2af48c6 | 12599 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
12600 | } |
12601 | } | |
12602 | ||
5a21b665 | 12603 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 12604 | { |
5a21b665 DV |
12605 | /* fb updated, need to unpin old fb */ |
12606 | if (crtc_state->fb_changed) | |
12607 | return true; | |
a6747b73 | 12608 | |
5a21b665 DV |
12609 | /* wm changes, need vblank before final wm's */ |
12610 | if (crtc_state->update_wm_post) | |
12611 | return true; | |
a6747b73 | 12612 | |
5eeb798b | 12613 | if (crtc_state->wm.need_postvbl_update) |
5a21b665 | 12614 | return true; |
a6747b73 | 12615 | |
5a21b665 | 12616 | return false; |
e8861675 ML |
12617 | } |
12618 | ||
896e5bb0 L |
12619 | static void intel_update_crtc(struct drm_crtc *crtc, |
12620 | struct drm_atomic_state *state, | |
12621 | struct drm_crtc_state *old_crtc_state, | |
12622 | unsigned int *crtc_vblank_mask) | |
12623 | { | |
12624 | struct drm_device *dev = crtc->dev; | |
12625 | struct drm_i915_private *dev_priv = to_i915(dev); | |
12626 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12627 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state); | |
12628 | bool modeset = needs_modeset(crtc->state); | |
12629 | ||
12630 | if (modeset) { | |
12631 | update_scanline_offset(intel_crtc); | |
12632 | dev_priv->display.crtc_enable(pipe_config, state); | |
12633 | } else { | |
12634 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); | |
12635 | } | |
12636 | ||
12637 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12638 | intel_fbc_enable( | |
12639 | intel_crtc, pipe_config, | |
12640 | to_intel_plane_state(crtc->primary->state)); | |
12641 | } | |
12642 | ||
12643 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
12644 | ||
12645 | if (needs_vblank_wait(pipe_config)) | |
12646 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
12647 | } | |
12648 | ||
12649 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
12650 | unsigned int *crtc_vblank_mask) | |
12651 | { | |
12652 | struct drm_crtc *crtc; | |
12653 | struct drm_crtc_state *old_crtc_state; | |
12654 | int i; | |
12655 | ||
12656 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12657 | if (!crtc->state->active) | |
12658 | continue; | |
12659 | ||
12660 | intel_update_crtc(crtc, state, old_crtc_state, | |
12661 | crtc_vblank_mask); | |
12662 | } | |
12663 | } | |
12664 | ||
27082493 L |
12665 | static void skl_update_crtcs(struct drm_atomic_state *state, |
12666 | unsigned int *crtc_vblank_mask) | |
12667 | { | |
0f0f74bc | 12668 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
12669 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
12670 | struct drm_crtc *crtc; | |
ce0ba283 | 12671 | struct intel_crtc *intel_crtc; |
27082493 | 12672 | struct drm_crtc_state *old_crtc_state; |
ce0ba283 | 12673 | struct intel_crtc_state *cstate; |
27082493 L |
12674 | unsigned int updated = 0; |
12675 | bool progress; | |
12676 | enum pipe pipe; | |
5eff503b ML |
12677 | int i; |
12678 | ||
12679 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
12680 | ||
12681 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) | |
12682 | /* ignore allocations for crtc's that have been turned off. */ | |
12683 | if (crtc->state->active) | |
12684 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; | |
27082493 L |
12685 | |
12686 | /* | |
12687 | * Whenever the number of active pipes changes, we need to make sure we | |
12688 | * update the pipes in the right order so that their ddb allocations | |
12689 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
12690 | * cause pipe underruns and other bad stuff. | |
12691 | */ | |
12692 | do { | |
27082493 L |
12693 | progress = false; |
12694 | ||
12695 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12696 | bool vbl_wait = false; | |
12697 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
12698 | |
12699 | intel_crtc = to_intel_crtc(crtc); | |
12700 | cstate = to_intel_crtc_state(crtc->state); | |
12701 | pipe = intel_crtc->pipe; | |
27082493 | 12702 | |
5eff503b | 12703 | if (updated & cmask || !cstate->base.active) |
27082493 | 12704 | continue; |
5eff503b ML |
12705 | |
12706 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
12707 | continue; |
12708 | ||
12709 | updated |= cmask; | |
5eff503b | 12710 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
12711 | |
12712 | /* | |
12713 | * If this is an already active pipe, it's DDB changed, | |
12714 | * and this isn't the last pipe that needs updating | |
12715 | * then we need to wait for a vblank to pass for the | |
12716 | * new ddb allocation to take effect. | |
12717 | */ | |
ce0ba283 | 12718 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 12719 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
27082493 L |
12720 | !crtc->state->active_changed && |
12721 | intel_state->wm_results.dirty_pipes != updated) | |
12722 | vbl_wait = true; | |
12723 | ||
12724 | intel_update_crtc(crtc, state, old_crtc_state, | |
12725 | crtc_vblank_mask); | |
12726 | ||
12727 | if (vbl_wait) | |
0f0f74bc | 12728 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
12729 | |
12730 | progress = true; | |
12731 | } | |
12732 | } while (progress); | |
12733 | } | |
12734 | ||
ba318c61 CW |
12735 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
12736 | { | |
12737 | struct intel_atomic_state *state, *next; | |
12738 | struct llist_node *freed; | |
12739 | ||
12740 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
12741 | llist_for_each_entry_safe(state, next, freed, freed) | |
12742 | drm_atomic_state_put(&state->base); | |
12743 | } | |
12744 | ||
12745 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
12746 | { | |
12747 | struct drm_i915_private *dev_priv = | |
12748 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
12749 | ||
12750 | intel_atomic_helper_free_state(dev_priv); | |
12751 | } | |
12752 | ||
94f05024 | 12753 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 12754 | { |
94f05024 | 12755 | struct drm_device *dev = state->dev; |
565602d7 | 12756 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12757 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 12758 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 12759 | struct drm_crtc *crtc; |
5a21b665 | 12760 | struct intel_crtc_state *intel_cstate; |
5a21b665 | 12761 | bool hw_check = intel_state->modeset; |
d8fc70b7 | 12762 | u64 put_domains[I915_MAX_PIPES] = {}; |
5a21b665 | 12763 | unsigned crtc_vblank_mask = 0; |
e95433c7 | 12764 | int i; |
a6778b3c | 12765 | |
ea0000f0 DV |
12766 | drm_atomic_helper_wait_for_dependencies(state); |
12767 | ||
c3b32658 | 12768 | if (intel_state->modeset) |
5a21b665 | 12769 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 12770 | |
29ceb0e6 | 12771 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
12772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12773 | ||
5a21b665 DV |
12774 | if (needs_modeset(crtc->state) || |
12775 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
12776 | hw_check = true; | |
12777 | ||
12778 | put_domains[to_intel_crtc(crtc)->pipe] = | |
12779 | modeset_get_crtc_power_domains(crtc, | |
12780 | to_intel_crtc_state(crtc->state)); | |
12781 | } | |
12782 | ||
61333b60 ML |
12783 | if (!needs_modeset(crtc->state)) |
12784 | continue; | |
12785 | ||
29ceb0e6 | 12786 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 12787 | |
29ceb0e6 VS |
12788 | if (old_crtc_state->active) { |
12789 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 12790 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 12791 | intel_crtc->active = false; |
58f9c0bc | 12792 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 12793 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
12794 | |
12795 | /* | |
12796 | * Underruns don't always raise | |
12797 | * interrupts, so check manually. | |
12798 | */ | |
12799 | intel_check_cpu_fifo_underruns(dev_priv); | |
12800 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 12801 | |
e62929b3 ML |
12802 | if (!crtc->state->active) { |
12803 | /* | |
12804 | * Make sure we don't call initial_watermarks | |
12805 | * for ILK-style watermark updates. | |
ff32c54e VS |
12806 | * |
12807 | * No clue what this is supposed to achieve. | |
e62929b3 | 12808 | */ |
ff32c54e | 12809 | if (INTEL_GEN(dev_priv) >= 9) |
e62929b3 ML |
12810 | dev_priv->display.initial_watermarks(intel_state, |
12811 | to_intel_crtc_state(crtc->state)); | |
e62929b3 | 12812 | } |
a539205a | 12813 | } |
b8cecdf5 | 12814 | } |
7758a113 | 12815 | |
ea9d758d DV |
12816 | /* Only after disabling all output pipelines that will be changed can we |
12817 | * update the the output configuration. */ | |
4740b0f2 | 12818 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 12819 | |
565602d7 | 12820 | if (intel_state->modeset) { |
4740b0f2 | 12821 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 | 12822 | |
b0587e4d | 12823 | intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
f6d1973d | 12824 | |
656d1b89 L |
12825 | /* |
12826 | * SKL workaround: bspec recommends we disable the SAGV when we | |
12827 | * have more then one pipe enabled | |
12828 | */ | |
56feca91 | 12829 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 12830 | intel_disable_sagv(dev_priv); |
656d1b89 | 12831 | |
677100ce | 12832 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 12833 | } |
47fab737 | 12834 | |
896e5bb0 | 12835 | /* Complete the events for pipes that have now been disabled */ |
29ceb0e6 | 12836 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a | 12837 | bool modeset = needs_modeset(crtc->state); |
80715b2f | 12838 | |
1f7528c4 DV |
12839 | /* Complete events for now disable pipes here. */ |
12840 | if (modeset && !crtc->state->active && crtc->state->event) { | |
12841 | spin_lock_irq(&dev->event_lock); | |
12842 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
12843 | spin_unlock_irq(&dev->event_lock); | |
12844 | ||
12845 | crtc->state->event = NULL; | |
12846 | } | |
177246a8 MR |
12847 | } |
12848 | ||
896e5bb0 L |
12849 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
12850 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
12851 | ||
94f05024 DV |
12852 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
12853 | * already, but still need the state for the delayed optimization. To | |
12854 | * fix this: | |
12855 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
12856 | * - schedule that vblank worker _before_ calling hw_done | |
12857 | * - at the start of commit_tail, cancel it _synchrously | |
12858 | * - switch over to the vblank wait helper in the core after that since | |
12859 | * we don't need out special handling any more. | |
12860 | */ | |
5a21b665 DV |
12861 | if (!state->legacy_cursor_update) |
12862 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
12863 | ||
12864 | /* | |
12865 | * Now that the vblank has passed, we can go ahead and program the | |
12866 | * optimal watermarks on platforms that need two-step watermark | |
12867 | * programming. | |
12868 | * | |
12869 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
12870 | */ | |
12871 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12872 | intel_cstate = to_intel_crtc_state(crtc->state); | |
12873 | ||
12874 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
12875 | dev_priv->display.optimize_watermarks(intel_state, |
12876 | intel_cstate); | |
5a21b665 DV |
12877 | } |
12878 | ||
12879 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12880 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
12881 | ||
12882 | if (put_domains[i]) | |
12883 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
12884 | ||
677100ce | 12885 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state); |
5a21b665 DV |
12886 | } |
12887 | ||
56feca91 | 12888 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 12889 | intel_enable_sagv(dev_priv); |
656d1b89 | 12890 | |
94f05024 DV |
12891 | drm_atomic_helper_commit_hw_done(state); |
12892 | ||
5a21b665 DV |
12893 | if (intel_state->modeset) |
12894 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
12895 | ||
12896 | mutex_lock(&dev->struct_mutex); | |
12897 | drm_atomic_helper_cleanup_planes(dev, state); | |
12898 | mutex_unlock(&dev->struct_mutex); | |
12899 | ||
ea0000f0 DV |
12900 | drm_atomic_helper_commit_cleanup_done(state); |
12901 | ||
0853695c | 12902 | drm_atomic_state_put(state); |
f30da187 | 12903 | |
75714940 MK |
12904 | /* As one of the primary mmio accessors, KMS has a high likelihood |
12905 | * of triggering bugs in unclaimed access. After we finish | |
12906 | * modesetting, see if an error has been flagged, and if so | |
12907 | * enable debugging for the next modeset - and hope we catch | |
12908 | * the culprit. | |
12909 | * | |
12910 | * XXX note that we assume display power is on at this point. | |
12911 | * This might hold true now but we need to add pm helper to check | |
12912 | * unclaimed only when the hardware is on, as atomic commits | |
12913 | * can happen also when the device is completely off. | |
12914 | */ | |
12915 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
ba318c61 CW |
12916 | |
12917 | intel_atomic_helper_free_state(dev_priv); | |
94f05024 DV |
12918 | } |
12919 | ||
12920 | static void intel_atomic_commit_work(struct work_struct *work) | |
12921 | { | |
c004a90b CW |
12922 | struct drm_atomic_state *state = |
12923 | container_of(work, struct drm_atomic_state, commit_work); | |
12924 | ||
94f05024 DV |
12925 | intel_atomic_commit_tail(state); |
12926 | } | |
12927 | ||
c004a90b CW |
12928 | static int __i915_sw_fence_call |
12929 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
12930 | enum i915_sw_fence_notify notify) | |
12931 | { | |
12932 | struct intel_atomic_state *state = | |
12933 | container_of(fence, struct intel_atomic_state, commit_ready); | |
12934 | ||
12935 | switch (notify) { | |
12936 | case FENCE_COMPLETE: | |
12937 | if (state->base.commit_work.func) | |
12938 | queue_work(system_unbound_wq, &state->base.commit_work); | |
12939 | break; | |
12940 | ||
12941 | case FENCE_FREE: | |
eb955eee CW |
12942 | { |
12943 | struct intel_atomic_helper *helper = | |
12944 | &to_i915(state->base.dev)->atomic_helper; | |
12945 | ||
12946 | if (llist_add(&state->freed, &helper->free_list)) | |
12947 | schedule_work(&helper->free_work); | |
12948 | break; | |
12949 | } | |
c004a90b CW |
12950 | } |
12951 | ||
12952 | return NOTIFY_DONE; | |
12953 | } | |
12954 | ||
6c9c1b38 DV |
12955 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
12956 | { | |
12957 | struct drm_plane_state *old_plane_state; | |
12958 | struct drm_plane *plane; | |
6c9c1b38 DV |
12959 | int i; |
12960 | ||
faf5bf0a CW |
12961 | for_each_plane_in_state(state, plane, old_plane_state, i) |
12962 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
12963 | intel_fb_obj(plane->state->fb), | |
12964 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
12965 | } |
12966 | ||
94f05024 DV |
12967 | /** |
12968 | * intel_atomic_commit - commit validated state object | |
12969 | * @dev: DRM device | |
12970 | * @state: the top-level driver state object | |
12971 | * @nonblock: nonblocking commit | |
12972 | * | |
12973 | * This function commits a top-level state object that has been validated | |
12974 | * with drm_atomic_helper_check(). | |
12975 | * | |
94f05024 DV |
12976 | * RETURNS |
12977 | * Zero for success or -errno. | |
12978 | */ | |
12979 | static int intel_atomic_commit(struct drm_device *dev, | |
12980 | struct drm_atomic_state *state, | |
12981 | bool nonblock) | |
12982 | { | |
12983 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 12984 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
12985 | int ret = 0; |
12986 | ||
a5509abd VS |
12987 | /* |
12988 | * The intel_legacy_cursor_update() fast path takes care | |
12989 | * of avoiding the vblank waits for simple cursor | |
12990 | * movement and flips. For cursor on/off and size changes, | |
12991 | * we want to perform the vblank waits so that watermark | |
12992 | * updates happen during the correct frames. Gen9+ have | |
12993 | * double buffered watermarks and so shouldn't need this. | |
12994 | */ | |
12995 | if (INTEL_GEN(dev_priv) < 9) | |
12996 | state->legacy_cursor_update = false; | |
12997 | ||
94f05024 DV |
12998 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
12999 | if (ret) | |
13000 | return ret; | |
13001 | ||
c004a90b CW |
13002 | drm_atomic_state_get(state); |
13003 | i915_sw_fence_init(&intel_state->commit_ready, | |
13004 | intel_atomic_commit_ready); | |
94f05024 | 13005 | |
d07f0e59 | 13006 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
13007 | if (ret) { |
13008 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 13009 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
13010 | return ret; |
13011 | } | |
13012 | ||
13013 | drm_atomic_helper_swap_state(state, true); | |
13014 | dev_priv->wm.distrust_bios_wm = false; | |
3c0fb588 | 13015 | intel_shared_dpll_swap_state(state); |
6c9c1b38 | 13016 | intel_atomic_track_fbs(state); |
94f05024 | 13017 | |
c3b32658 ML |
13018 | if (intel_state->modeset) { |
13019 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13020 | sizeof(intel_state->min_pixclk)); | |
13021 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
bb0f4aab VS |
13022 | dev_priv->cdclk.logical = intel_state->cdclk.logical; |
13023 | dev_priv->cdclk.actual = intel_state->cdclk.actual; | |
c3b32658 ML |
13024 | } |
13025 | ||
0853695c | 13026 | drm_atomic_state_get(state); |
c004a90b CW |
13027 | INIT_WORK(&state->commit_work, |
13028 | nonblock ? intel_atomic_commit_work : NULL); | |
13029 | ||
13030 | i915_sw_fence_commit(&intel_state->commit_ready); | |
13031 | if (!nonblock) { | |
13032 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 13033 | intel_atomic_commit_tail(state); |
c004a90b | 13034 | } |
75714940 | 13035 | |
74c090b1 | 13036 | return 0; |
7f27126e JB |
13037 | } |
13038 | ||
c0c36b94 CW |
13039 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13040 | { | |
83a57153 ACO |
13041 | struct drm_device *dev = crtc->dev; |
13042 | struct drm_atomic_state *state; | |
e694eb02 | 13043 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13044 | int ret; |
83a57153 ACO |
13045 | |
13046 | state = drm_atomic_state_alloc(dev); | |
13047 | if (!state) { | |
78108b7c VS |
13048 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
13049 | crtc->base.id, crtc->name); | |
83a57153 ACO |
13050 | return; |
13051 | } | |
13052 | ||
e694eb02 | 13053 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13054 | |
e694eb02 ML |
13055 | retry: |
13056 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13057 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13058 | if (!ret) { | |
13059 | if (!crtc_state->active) | |
13060 | goto out; | |
83a57153 | 13061 | |
e694eb02 | 13062 | crtc_state->mode_changed = true; |
74c090b1 | 13063 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13064 | } |
13065 | ||
e694eb02 ML |
13066 | if (ret == -EDEADLK) { |
13067 | drm_atomic_state_clear(state); | |
13068 | drm_modeset_backoff(state->acquire_ctx); | |
13069 | goto retry; | |
4ed9fb37 | 13070 | } |
4be07317 | 13071 | |
e694eb02 | 13072 | out: |
0853695c | 13073 | drm_atomic_state_put(state); |
c0c36b94 CW |
13074 | } |
13075 | ||
a8784875 BP |
13076 | /* |
13077 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
13078 | * drm_atomic_helper_legacy_gamma_set() directly. | |
13079 | */ | |
13080 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
13081 | u16 *red, u16 *green, u16 *blue, | |
13082 | uint32_t size) | |
13083 | { | |
13084 | struct drm_device *dev = crtc->dev; | |
13085 | struct drm_mode_config *config = &dev->mode_config; | |
13086 | struct drm_crtc_state *state; | |
13087 | int ret; | |
13088 | ||
13089 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
13090 | if (ret) | |
13091 | return ret; | |
13092 | ||
13093 | /* | |
13094 | * Make sure we update the legacy properties so this works when | |
13095 | * atomic is not enabled. | |
13096 | */ | |
13097 | ||
13098 | state = crtc->state; | |
13099 | ||
13100 | drm_object_property_set_value(&crtc->base, | |
13101 | config->degamma_lut_property, | |
13102 | (state->degamma_lut) ? | |
13103 | state->degamma_lut->base.id : 0); | |
13104 | ||
13105 | drm_object_property_set_value(&crtc->base, | |
13106 | config->ctm_property, | |
13107 | (state->ctm) ? | |
13108 | state->ctm->base.id : 0); | |
13109 | ||
13110 | drm_object_property_set_value(&crtc->base, | |
13111 | config->gamma_lut_property, | |
13112 | (state->gamma_lut) ? | |
13113 | state->gamma_lut->base.id : 0); | |
13114 | ||
13115 | return 0; | |
13116 | } | |
13117 | ||
f6e5b160 | 13118 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 13119 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 13120 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13121 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 13122 | .destroy = intel_crtc_destroy, |
4c01ded5 | 13123 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
13124 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13125 | .atomic_destroy_state = intel_crtc_destroy_state, | |
8c6b709d | 13126 | .set_crc_source = intel_crtc_set_crc_source, |
f6e5b160 CW |
13127 | }; |
13128 | ||
6beb8c23 MR |
13129 | /** |
13130 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13131 | * @plane: drm plane to prepare for | |
13132 | * @fb: framebuffer to prepare for presentation | |
13133 | * | |
13134 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13135 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13136 | * bits. Some older platforms need special physical address handling for | |
13137 | * cursor planes. | |
13138 | * | |
f935675f ML |
13139 | * Must be called with struct_mutex held. |
13140 | * | |
6beb8c23 MR |
13141 | * Returns 0 on success, negative error code on failure. |
13142 | */ | |
13143 | int | |
13144 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 13145 | struct drm_plane_state *new_state) |
465c120c | 13146 | { |
c004a90b CW |
13147 | struct intel_atomic_state *intel_state = |
13148 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 13149 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 13150 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13151 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13152 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 13153 | int ret; |
465c120c | 13154 | |
57822dc6 CW |
13155 | if (obj) { |
13156 | if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
13157 | INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
13158 | const int align = IS_I830(dev_priv) ? 16 * 1024 : 256; | |
13159 | ||
13160 | ret = i915_gem_object_attach_phys(obj, align); | |
13161 | if (ret) { | |
13162 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13163 | return ret; | |
13164 | } | |
13165 | } else { | |
13166 | struct i915_vma *vma; | |
13167 | ||
13168 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
13169 | if (IS_ERR(vma)) { | |
13170 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13171 | return PTR_ERR(vma); | |
13172 | } | |
13173 | ||
13174 | to_intel_plane_state(new_state)->vma = vma; | |
13175 | } | |
13176 | } | |
13177 | ||
1ee49399 | 13178 | if (!obj && !old_obj) |
465c120c MR |
13179 | return 0; |
13180 | ||
5008e874 ML |
13181 | if (old_obj) { |
13182 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
13183 | drm_atomic_get_existing_crtc_state(new_state->state, |
13184 | plane->state->crtc); | |
5008e874 ML |
13185 | |
13186 | /* Big Hammer, we also need to ensure that any pending | |
13187 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13188 | * current scanout is retired before unpinning the old | |
13189 | * framebuffer. Note that we rely on userspace rendering | |
13190 | * into the buffer attached to the pipe they are waiting | |
13191 | * on. If not, userspace generates a GPU hang with IPEHR | |
13192 | * point to the MI_WAIT_FOR_EVENT. | |
13193 | * | |
13194 | * This should only fail upon a hung GPU, in which case we | |
13195 | * can safely continue. | |
13196 | */ | |
c004a90b CW |
13197 | if (needs_modeset(crtc_state)) { |
13198 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
13199 | old_obj->resv, NULL, | |
13200 | false, 0, | |
13201 | GFP_KERNEL); | |
13202 | if (ret < 0) | |
13203 | return ret; | |
f4457ae7 | 13204 | } |
5008e874 ML |
13205 | } |
13206 | ||
c004a90b CW |
13207 | if (new_state->fence) { /* explicit fencing */ |
13208 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
13209 | new_state->fence, | |
13210 | I915_FENCE_TIMEOUT, | |
13211 | GFP_KERNEL); | |
13212 | if (ret < 0) | |
13213 | return ret; | |
13214 | } | |
13215 | ||
c37efb99 CW |
13216 | if (!obj) |
13217 | return 0; | |
13218 | ||
c004a90b CW |
13219 | if (!new_state->fence) { /* implicit fencing */ |
13220 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
13221 | obj->resv, NULL, | |
13222 | false, I915_FENCE_TIMEOUT, | |
13223 | GFP_KERNEL); | |
13224 | if (ret < 0) | |
13225 | return ret; | |
6b5e90f5 CW |
13226 | |
13227 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
c004a90b | 13228 | } |
5a21b665 | 13229 | |
d07f0e59 | 13230 | return 0; |
6beb8c23 MR |
13231 | } |
13232 | ||
38f3ce3a MR |
13233 | /** |
13234 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13235 | * @plane: drm plane to clean up for | |
13236 | * @fb: old framebuffer that was on plane | |
13237 | * | |
13238 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13239 | * |
13240 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13241 | */ |
13242 | void | |
13243 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 13244 | struct drm_plane_state *old_state) |
38f3ce3a | 13245 | { |
be1e3415 | 13246 | struct i915_vma *vma; |
38f3ce3a | 13247 | |
be1e3415 CW |
13248 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
13249 | vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); | |
13250 | if (vma) | |
13251 | intel_unpin_fb_vma(vma); | |
465c120c MR |
13252 | } |
13253 | ||
6156a456 CK |
13254 | int |
13255 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13256 | { | |
5b7280f0 | 13257 | struct drm_i915_private *dev_priv; |
6156a456 | 13258 | int max_scale; |
5b7280f0 | 13259 | int crtc_clock, max_dotclk; |
6156a456 | 13260 | |
bf8a0af0 | 13261 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13262 | return DRM_PLANE_HELPER_NO_SCALING; |
13263 | ||
5b7280f0 ACO |
13264 | dev_priv = to_i915(intel_crtc->base.dev); |
13265 | ||
6156a456 | 13266 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
5b7280f0 ACO |
13267 | max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; |
13268 | ||
13269 | if (IS_GEMINILAKE(dev_priv)) | |
13270 | max_dotclk *= 2; | |
6156a456 | 13271 | |
5b7280f0 | 13272 | if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) |
6156a456 CK |
13273 | return DRM_PLANE_HELPER_NO_SCALING; |
13274 | ||
13275 | /* | |
13276 | * skl max scale is lower of: | |
13277 | * close to 3 but not 3, -1 is for that purpose | |
13278 | * or | |
13279 | * cdclk/crtc_clock | |
13280 | */ | |
5b7280f0 ACO |
13281 | max_scale = min((1 << 16) * 3 - 1, |
13282 | (1 << 8) * ((max_dotclk << 8) / crtc_clock)); | |
6156a456 CK |
13283 | |
13284 | return max_scale; | |
13285 | } | |
13286 | ||
465c120c | 13287 | static int |
3c692a41 | 13288 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13289 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13290 | struct intel_plane_state *state) |
13291 | { | |
b63a16f6 | 13292 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 13293 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 13294 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13295 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13296 | bool can_position = false; | |
b63a16f6 | 13297 | int ret; |
465c120c | 13298 | |
b63a16f6 | 13299 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
13300 | /* use scaler when colorkey is not required */ |
13301 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13302 | min_scale = 1; | |
13303 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13304 | } | |
d8106366 | 13305 | can_position = true; |
6156a456 | 13306 | } |
d8106366 | 13307 | |
cc926387 DV |
13308 | ret = drm_plane_helper_check_state(&state->base, |
13309 | &state->clip, | |
13310 | min_scale, max_scale, | |
13311 | can_position, true); | |
b63a16f6 VS |
13312 | if (ret) |
13313 | return ret; | |
13314 | ||
cc926387 | 13315 | if (!state->base.fb) |
b63a16f6 VS |
13316 | return 0; |
13317 | ||
13318 | if (INTEL_GEN(dev_priv) >= 9) { | |
13319 | ret = skl_check_plane_surface(state); | |
13320 | if (ret) | |
13321 | return ret; | |
13322 | } | |
13323 | ||
13324 | return 0; | |
14af293f GP |
13325 | } |
13326 | ||
5a21b665 DV |
13327 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13328 | struct drm_crtc_state *old_crtc_state) | |
13329 | { | |
13330 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 13331 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 13332 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
13333 | struct intel_crtc_state *intel_cstate = |
13334 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 13335 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 13336 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
13337 | struct intel_atomic_state *old_intel_state = |
13338 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
13339 | bool modeset = needs_modeset(crtc->state); |
13340 | ||
13341 | /* Perform vblank evasion around commit operation */ | |
13342 | intel_pipe_update_start(intel_crtc); | |
13343 | ||
13344 | if (modeset) | |
e62929b3 | 13345 | goto out; |
5a21b665 DV |
13346 | |
13347 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
13348 | intel_color_set_csc(crtc->state); | |
13349 | intel_color_load_luts(crtc->state); | |
13350 | } | |
13351 | ||
ccf010fb ML |
13352 | if (intel_cstate->update_pipe) |
13353 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
13354 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 13355 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 13356 | |
e62929b3 | 13357 | out: |
ccf010fb ML |
13358 | if (dev_priv->display.atomic_update_watermarks) |
13359 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
13360 | intel_cstate); | |
5a21b665 DV |
13361 | } |
13362 | ||
13363 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
13364 | struct drm_crtc_state *old_crtc_state) | |
13365 | { | |
13366 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13367 | ||
13368 | intel_pipe_update_end(intel_crtc, NULL); | |
13369 | } | |
13370 | ||
cf4c7c12 | 13371 | /** |
4a3b8769 MR |
13372 | * intel_plane_destroy - destroy a plane |
13373 | * @plane: plane to destroy | |
cf4c7c12 | 13374 | * |
4a3b8769 MR |
13375 | * Common destruction function for all types of planes (primary, cursor, |
13376 | * sprite). | |
cf4c7c12 | 13377 | */ |
4a3b8769 | 13378 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 13379 | { |
465c120c | 13380 | drm_plane_cleanup(plane); |
69ae561f | 13381 | kfree(to_intel_plane(plane)); |
465c120c MR |
13382 | } |
13383 | ||
65a3fea0 | 13384 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13385 | .update_plane = drm_atomic_helper_update_plane, |
13386 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13387 | .destroy = intel_plane_destroy, |
c196e1d6 | 13388 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13389 | .atomic_get_property = intel_plane_atomic_get_property, |
13390 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13391 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13392 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
13393 | }; |
13394 | ||
f79f2692 ML |
13395 | static int |
13396 | intel_legacy_cursor_update(struct drm_plane *plane, | |
13397 | struct drm_crtc *crtc, | |
13398 | struct drm_framebuffer *fb, | |
13399 | int crtc_x, int crtc_y, | |
13400 | unsigned int crtc_w, unsigned int crtc_h, | |
13401 | uint32_t src_x, uint32_t src_y, | |
13402 | uint32_t src_w, uint32_t src_h) | |
13403 | { | |
13404 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
13405 | int ret; | |
13406 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
13407 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13408 | struct drm_framebuffer *old_fb; | |
13409 | struct drm_crtc_state *crtc_state = crtc->state; | |
be1e3415 | 13410 | struct i915_vma *old_vma; |
f79f2692 ML |
13411 | |
13412 | /* | |
13413 | * When crtc is inactive or there is a modeset pending, | |
13414 | * wait for it to complete in the slowpath | |
13415 | */ | |
13416 | if (!crtc_state->active || needs_modeset(crtc_state) || | |
13417 | to_intel_crtc_state(crtc_state)->update_pipe) | |
13418 | goto slow; | |
13419 | ||
13420 | old_plane_state = plane->state; | |
13421 | ||
13422 | /* | |
13423 | * If any parameters change that may affect watermarks, | |
13424 | * take the slowpath. Only changing fb or position should be | |
13425 | * in the fastpath. | |
13426 | */ | |
13427 | if (old_plane_state->crtc != crtc || | |
13428 | old_plane_state->src_w != src_w || | |
13429 | old_plane_state->src_h != src_h || | |
13430 | old_plane_state->crtc_w != crtc_w || | |
13431 | old_plane_state->crtc_h != crtc_h || | |
a5509abd | 13432 | !old_plane_state->fb != !fb) |
f79f2692 ML |
13433 | goto slow; |
13434 | ||
13435 | new_plane_state = intel_plane_duplicate_state(plane); | |
13436 | if (!new_plane_state) | |
13437 | return -ENOMEM; | |
13438 | ||
13439 | drm_atomic_set_fb_for_plane(new_plane_state, fb); | |
13440 | ||
13441 | new_plane_state->src_x = src_x; | |
13442 | new_plane_state->src_y = src_y; | |
13443 | new_plane_state->src_w = src_w; | |
13444 | new_plane_state->src_h = src_h; | |
13445 | new_plane_state->crtc_x = crtc_x; | |
13446 | new_plane_state->crtc_y = crtc_y; | |
13447 | new_plane_state->crtc_w = crtc_w; | |
13448 | new_plane_state->crtc_h = crtc_h; | |
13449 | ||
13450 | ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), | |
13451 | to_intel_plane_state(new_plane_state)); | |
13452 | if (ret) | |
13453 | goto out_free; | |
13454 | ||
f79f2692 ML |
13455 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
13456 | if (ret) | |
13457 | goto out_free; | |
13458 | ||
13459 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
13460 | int align = IS_I830(dev_priv) ? 16 * 1024 : 256; | |
13461 | ||
13462 | ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align); | |
13463 | if (ret) { | |
13464 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13465 | goto out_unlock; | |
13466 | } | |
13467 | } else { | |
13468 | struct i915_vma *vma; | |
13469 | ||
13470 | vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); | |
13471 | if (IS_ERR(vma)) { | |
13472 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13473 | ||
13474 | ret = PTR_ERR(vma); | |
13475 | goto out_unlock; | |
13476 | } | |
be1e3415 CW |
13477 | |
13478 | to_intel_plane_state(new_plane_state)->vma = vma; | |
f79f2692 ML |
13479 | } |
13480 | ||
13481 | old_fb = old_plane_state->fb; | |
be1e3415 | 13482 | old_vma = to_intel_plane_state(old_plane_state)->vma; |
f79f2692 ML |
13483 | |
13484 | i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), | |
13485 | intel_plane->frontbuffer_bit); | |
13486 | ||
13487 | /* Swap plane state */ | |
13488 | new_plane_state->fence = old_plane_state->fence; | |
13489 | *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state); | |
13490 | new_plane_state->fence = NULL; | |
13491 | new_plane_state->fb = old_fb; | |
be1e3415 | 13492 | to_intel_plane_state(new_plane_state)->vma = old_vma; |
f79f2692 | 13493 | |
a5509abd VS |
13494 | if (plane->state->visible) |
13495 | intel_plane->update_plane(plane, | |
13496 | to_intel_crtc_state(crtc->state), | |
13497 | to_intel_plane_state(plane->state)); | |
13498 | else | |
13499 | intel_plane->disable_plane(plane, crtc); | |
f79f2692 ML |
13500 | |
13501 | intel_cleanup_plane_fb(plane, new_plane_state); | |
13502 | ||
13503 | out_unlock: | |
13504 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
13505 | out_free: | |
13506 | intel_plane_destroy_state(plane, new_plane_state); | |
13507 | return ret; | |
13508 | ||
f79f2692 ML |
13509 | slow: |
13510 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
13511 | crtc_x, crtc_y, crtc_w, crtc_h, | |
13512 | src_x, src_y, src_w, src_h); | |
13513 | } | |
13514 | ||
13515 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
13516 | .update_plane = intel_legacy_cursor_update, | |
13517 | .disable_plane = drm_atomic_helper_disable_plane, | |
13518 | .destroy = intel_plane_destroy, | |
13519 | .set_property = drm_atomic_helper_plane_set_property, | |
13520 | .atomic_get_property = intel_plane_atomic_get_property, | |
13521 | .atomic_set_property = intel_plane_atomic_set_property, | |
13522 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
13523 | .atomic_destroy_state = intel_plane_destroy_state, | |
13524 | }; | |
13525 | ||
b079bd17 | 13526 | static struct intel_plane * |
580503c7 | 13527 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 13528 | { |
fca0ce2a VS |
13529 | struct intel_plane *primary = NULL; |
13530 | struct intel_plane_state *state = NULL; | |
465c120c | 13531 | const uint32_t *intel_primary_formats; |
93ca7e00 | 13532 | unsigned int supported_rotations; |
45e3743a | 13533 | unsigned int num_formats; |
fca0ce2a | 13534 | int ret; |
465c120c MR |
13535 | |
13536 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
13537 | if (!primary) { |
13538 | ret = -ENOMEM; | |
fca0ce2a | 13539 | goto fail; |
b079bd17 | 13540 | } |
465c120c | 13541 | |
8e7d688b | 13542 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
13543 | if (!state) { |
13544 | ret = -ENOMEM; | |
fca0ce2a | 13545 | goto fail; |
b079bd17 VS |
13546 | } |
13547 | ||
8e7d688b | 13548 | primary->base.state = &state->base; |
ea2c67bb | 13549 | |
465c120c MR |
13550 | primary->can_scale = false; |
13551 | primary->max_downscale = 1; | |
580503c7 | 13552 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 13553 | primary->can_scale = true; |
af99ceda | 13554 | state->scaler_id = -1; |
6156a456 | 13555 | } |
465c120c | 13556 | primary->pipe = pipe; |
e3c566df VS |
13557 | /* |
13558 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
13559 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
13560 | */ | |
13561 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
13562 | primary->plane = (enum plane) !pipe; | |
13563 | else | |
13564 | primary->plane = (enum plane) pipe; | |
b14e5848 | 13565 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 13566 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13567 | primary->check_plane = intel_check_primary_plane; |
465c120c | 13568 | |
580503c7 | 13569 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
13570 | intel_primary_formats = skl_primary_formats; |
13571 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
13572 | |
13573 | primary->update_plane = skylake_update_primary_plane; | |
13574 | primary->disable_plane = skylake_disable_primary_plane; | |
6e266956 | 13575 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
a8d201af ML |
13576 | intel_primary_formats = i965_primary_formats; |
13577 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
13578 | ||
13579 | primary->update_plane = ironlake_update_primary_plane; | |
13580 | primary->disable_plane = i9xx_disable_primary_plane; | |
580503c7 | 13581 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
13582 | intel_primary_formats = i965_primary_formats; |
13583 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
13584 | |
13585 | primary->update_plane = i9xx_update_primary_plane; | |
13586 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13587 | } else { |
13588 | intel_primary_formats = i8xx_primary_formats; | |
13589 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
13590 | |
13591 | primary->update_plane = i9xx_update_primary_plane; | |
13592 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13593 | } |
13594 | ||
580503c7 VS |
13595 | if (INTEL_GEN(dev_priv) >= 9) |
13596 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
13597 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13598 | intel_primary_formats, num_formats, |
13599 | DRM_PLANE_TYPE_PRIMARY, | |
13600 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 13601 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
13602 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13603 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13604 | intel_primary_formats, num_formats, |
13605 | DRM_PLANE_TYPE_PRIMARY, | |
13606 | "primary %c", pipe_name(pipe)); | |
13607 | else | |
580503c7 VS |
13608 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13609 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13610 | intel_primary_formats, num_formats, |
13611 | DRM_PLANE_TYPE_PRIMARY, | |
13612 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
13613 | if (ret) |
13614 | goto fail; | |
48404c1e | 13615 | |
5481e27f | 13616 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 VS |
13617 | supported_rotations = |
13618 | DRM_ROTATE_0 | DRM_ROTATE_90 | | |
13619 | DRM_ROTATE_180 | DRM_ROTATE_270; | |
4ea7be2b VS |
13620 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
13621 | supported_rotations = | |
13622 | DRM_ROTATE_0 | DRM_ROTATE_180 | | |
13623 | DRM_REFLECT_X; | |
5481e27f | 13624 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 VS |
13625 | supported_rotations = |
13626 | DRM_ROTATE_0 | DRM_ROTATE_180; | |
13627 | } else { | |
13628 | supported_rotations = DRM_ROTATE_0; | |
13629 | } | |
13630 | ||
5481e27f | 13631 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
13632 | drm_plane_create_rotation_property(&primary->base, |
13633 | DRM_ROTATE_0, | |
13634 | supported_rotations); | |
48404c1e | 13635 | |
ea2c67bb MR |
13636 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13637 | ||
b079bd17 | 13638 | return primary; |
fca0ce2a VS |
13639 | |
13640 | fail: | |
13641 | kfree(state); | |
13642 | kfree(primary); | |
13643 | ||
b079bd17 | 13644 | return ERR_PTR(ret); |
465c120c MR |
13645 | } |
13646 | ||
3d7d6510 | 13647 | static int |
852e787c | 13648 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13649 | struct intel_crtc_state *crtc_state, |
852e787c | 13650 | struct intel_plane_state *state) |
3d7d6510 | 13651 | { |
2b875c22 | 13652 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13653 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 13654 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
13655 | unsigned stride; |
13656 | int ret; | |
3d7d6510 | 13657 | |
f8856a44 VS |
13658 | ret = drm_plane_helper_check_state(&state->base, |
13659 | &state->clip, | |
13660 | DRM_PLANE_HELPER_NO_SCALING, | |
13661 | DRM_PLANE_HELPER_NO_SCALING, | |
13662 | true, true); | |
757f9a3e GP |
13663 | if (ret) |
13664 | return ret; | |
13665 | ||
757f9a3e GP |
13666 | /* if we want to turn off the cursor ignore width and height */ |
13667 | if (!obj) | |
da20eabd | 13668 | return 0; |
757f9a3e | 13669 | |
757f9a3e | 13670 | /* Check for which cursor types we support */ |
50a0bc90 TU |
13671 | if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w, |
13672 | state->base.crtc_h)) { | |
ea2c67bb MR |
13673 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
13674 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13675 | return -EINVAL; |
13676 | } | |
13677 | ||
ea2c67bb MR |
13678 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13679 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13680 | DRM_DEBUG_KMS("buffer is too small\n"); |
13681 | return -ENOMEM; | |
13682 | } | |
13683 | ||
bae781b2 | 13684 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 13685 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 13686 | return -EINVAL; |
32b7eeec MR |
13687 | } |
13688 | ||
b29ec92c VS |
13689 | /* |
13690 | * There's something wrong with the cursor on CHV pipe C. | |
13691 | * If it straddles the left edge of the screen then | |
13692 | * moving it away from the edge or disabling it often | |
13693 | * results in a pipe underrun, and often that can lead to | |
13694 | * dead pipe (constant underrun reported, and it scans | |
13695 | * out just a solid color). To recover from that, the | |
13696 | * display power well must be turned off and on again. | |
13697 | * Refuse the put the cursor into that compromised position. | |
13698 | */ | |
920a14b2 | 13699 | if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C && |
936e71e3 | 13700 | state->base.visible && state->base.crtc_x < 0) { |
b29ec92c VS |
13701 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
13702 | return -EINVAL; | |
13703 | } | |
13704 | ||
da20eabd | 13705 | return 0; |
852e787c | 13706 | } |
3d7d6510 | 13707 | |
a8ad0d8e ML |
13708 | static void |
13709 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 13710 | struct drm_crtc *crtc) |
a8ad0d8e | 13711 | { |
f2858021 ML |
13712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13713 | ||
13714 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 13715 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
13716 | } |
13717 | ||
f4a2cf29 | 13718 | static void |
55a08b3f ML |
13719 | intel_update_cursor_plane(struct drm_plane *plane, |
13720 | const struct intel_crtc_state *crtc_state, | |
13721 | const struct intel_plane_state *state) | |
852e787c | 13722 | { |
55a08b3f ML |
13723 | struct drm_crtc *crtc = crtc_state->base.crtc; |
13724 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b7f05d4a | 13725 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 13726 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13727 | uint32_t addr; |
852e787c | 13728 | |
f4a2cf29 | 13729 | if (!obj) |
a912f12f | 13730 | addr = 0; |
b7f05d4a | 13731 | else if (!INTEL_INFO(dev_priv)->cursor_needs_physical) |
be1e3415 | 13732 | addr = intel_plane_ggtt_offset(state); |
f4a2cf29 | 13733 | else |
a912f12f | 13734 | addr = obj->phys_handle->busaddr; |
852e787c | 13735 | |
a912f12f | 13736 | intel_crtc->cursor_addr = addr; |
55a08b3f | 13737 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
13738 | } |
13739 | ||
b079bd17 | 13740 | static struct intel_plane * |
580503c7 | 13741 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
3d7d6510 | 13742 | { |
fca0ce2a VS |
13743 | struct intel_plane *cursor = NULL; |
13744 | struct intel_plane_state *state = NULL; | |
13745 | int ret; | |
3d7d6510 MR |
13746 | |
13747 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
13748 | if (!cursor) { |
13749 | ret = -ENOMEM; | |
fca0ce2a | 13750 | goto fail; |
b079bd17 | 13751 | } |
3d7d6510 | 13752 | |
8e7d688b | 13753 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
13754 | if (!state) { |
13755 | ret = -ENOMEM; | |
fca0ce2a | 13756 | goto fail; |
b079bd17 VS |
13757 | } |
13758 | ||
8e7d688b | 13759 | cursor->base.state = &state->base; |
ea2c67bb | 13760 | |
3d7d6510 MR |
13761 | cursor->can_scale = false; |
13762 | cursor->max_downscale = 1; | |
13763 | cursor->pipe = pipe; | |
13764 | cursor->plane = pipe; | |
b14e5848 | 13765 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 13766 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 13767 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 13768 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 13769 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 13770 | |
580503c7 | 13771 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
f79f2692 | 13772 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
13773 | intel_cursor_formats, |
13774 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
13775 | DRM_PLANE_TYPE_CURSOR, |
13776 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
13777 | if (ret) |
13778 | goto fail; | |
4398ad45 | 13779 | |
5481e27f | 13780 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
13781 | drm_plane_create_rotation_property(&cursor->base, |
13782 | DRM_ROTATE_0, | |
13783 | DRM_ROTATE_0 | | |
13784 | DRM_ROTATE_180); | |
4398ad45 | 13785 | |
580503c7 | 13786 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
13787 | state->scaler_id = -1; |
13788 | ||
ea2c67bb MR |
13789 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13790 | ||
b079bd17 | 13791 | return cursor; |
fca0ce2a VS |
13792 | |
13793 | fail: | |
13794 | kfree(state); | |
13795 | kfree(cursor); | |
13796 | ||
b079bd17 | 13797 | return ERR_PTR(ret); |
3d7d6510 MR |
13798 | } |
13799 | ||
1c74eeaf NM |
13800 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
13801 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 13802 | { |
65edccce VS |
13803 | struct intel_crtc_scaler_state *scaler_state = |
13804 | &crtc_state->scaler_state; | |
1c74eeaf | 13805 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
549e2bfb | 13806 | int i; |
549e2bfb | 13807 | |
1c74eeaf NM |
13808 | crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; |
13809 | if (!crtc->num_scalers) | |
13810 | return; | |
13811 | ||
65edccce VS |
13812 | for (i = 0; i < crtc->num_scalers; i++) { |
13813 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
13814 | ||
13815 | scaler->in_use = 0; | |
13816 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
13817 | } |
13818 | ||
13819 | scaler_state->scaler_id = -1; | |
13820 | } | |
13821 | ||
5ab0d85b | 13822 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
13823 | { |
13824 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 13825 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
13826 | struct intel_plane *primary = NULL; |
13827 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 13828 | int sprite, ret; |
79e53945 | 13829 | |
955382f3 | 13830 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
13831 | if (!intel_crtc) |
13832 | return -ENOMEM; | |
79e53945 | 13833 | |
f5de6e07 | 13834 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
13835 | if (!crtc_state) { |
13836 | ret = -ENOMEM; | |
f5de6e07 | 13837 | goto fail; |
b079bd17 | 13838 | } |
550acefd ACO |
13839 | intel_crtc->config = crtc_state; |
13840 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13841 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13842 | |
580503c7 | 13843 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
13844 | if (IS_ERR(primary)) { |
13845 | ret = PTR_ERR(primary); | |
3d7d6510 | 13846 | goto fail; |
b079bd17 | 13847 | } |
d97d7b48 | 13848 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 13849 | |
a81d6fa0 | 13850 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
13851 | struct intel_plane *plane; |
13852 | ||
580503c7 | 13853 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 13854 | if (IS_ERR(plane)) { |
b079bd17 VS |
13855 | ret = PTR_ERR(plane); |
13856 | goto fail; | |
13857 | } | |
d97d7b48 | 13858 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
13859 | } |
13860 | ||
580503c7 | 13861 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 13862 | if (IS_ERR(cursor)) { |
b079bd17 | 13863 | ret = PTR_ERR(cursor); |
3d7d6510 | 13864 | goto fail; |
b079bd17 | 13865 | } |
d97d7b48 | 13866 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 13867 | |
5ab0d85b | 13868 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
13869 | &primary->base, &cursor->base, |
13870 | &intel_crtc_funcs, | |
4d5d72b7 | 13871 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
13872 | if (ret) |
13873 | goto fail; | |
79e53945 | 13874 | |
80824003 | 13875 | intel_crtc->pipe = pipe; |
e3c566df | 13876 | intel_crtc->plane = primary->plane; |
80824003 | 13877 | |
4b0e333e CW |
13878 | intel_crtc->cursor_base = ~0; |
13879 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13880 | intel_crtc->cursor_size = ~0; |
8d7849db | 13881 | |
1c74eeaf NM |
13882 | /* initialize shared scalers */ |
13883 | intel_crtc_init_scalers(intel_crtc, crtc_state); | |
13884 | ||
22fd0fab JB |
13885 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13886 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
13887 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
13888 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 13889 | |
79e53945 | 13890 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13891 | |
8563b1e8 LL |
13892 | intel_color_init(&intel_crtc->base); |
13893 | ||
87b6b101 | 13894 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
13895 | |
13896 | return 0; | |
3d7d6510 MR |
13897 | |
13898 | fail: | |
b079bd17 VS |
13899 | /* |
13900 | * drm_mode_config_cleanup() will free up any | |
13901 | * crtcs/planes already initialized. | |
13902 | */ | |
f5de6e07 | 13903 | kfree(crtc_state); |
3d7d6510 | 13904 | kfree(intel_crtc); |
b079bd17 VS |
13905 | |
13906 | return ret; | |
79e53945 JB |
13907 | } |
13908 | ||
752aa88a JB |
13909 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13910 | { | |
13911 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13912 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13913 | |
51fd371b | 13914 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13915 | |
d3babd3f | 13916 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13917 | return INVALID_PIPE; |
13918 | ||
13919 | return to_intel_crtc(encoder->crtc)->pipe; | |
13920 | } | |
13921 | ||
08d7b3d1 | 13922 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13923 | struct drm_file *file) |
08d7b3d1 | 13924 | { |
08d7b3d1 | 13925 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13926 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13927 | struct intel_crtc *crtc; |
08d7b3d1 | 13928 | |
7707e653 | 13929 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 13930 | if (!drmmode_crtc) |
3f2c2057 | 13931 | return -ENOENT; |
08d7b3d1 | 13932 | |
7707e653 | 13933 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13934 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13935 | |
c05422d5 | 13936 | return 0; |
08d7b3d1 CW |
13937 | } |
13938 | ||
66a9278e | 13939 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13940 | { |
66a9278e DV |
13941 | struct drm_device *dev = encoder->base.dev; |
13942 | struct intel_encoder *source_encoder; | |
79e53945 | 13943 | int index_mask = 0; |
79e53945 JB |
13944 | int entry = 0; |
13945 | ||
b2784e15 | 13946 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13947 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13948 | index_mask |= (1 << entry); |
13949 | ||
79e53945 JB |
13950 | entry++; |
13951 | } | |
4ef69c7a | 13952 | |
79e53945 JB |
13953 | return index_mask; |
13954 | } | |
13955 | ||
646d5772 | 13956 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 13957 | { |
646d5772 | 13958 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
13959 | return false; |
13960 | ||
13961 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13962 | return false; | |
13963 | ||
5db94019 | 13964 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13965 | return false; |
13966 | ||
13967 | return true; | |
13968 | } | |
13969 | ||
6315b5d3 | 13970 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 13971 | { |
6315b5d3 | 13972 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
13973 | return false; |
13974 | ||
50a0bc90 | 13975 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
13976 | return false; |
13977 | ||
920a14b2 | 13978 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
13979 | return false; |
13980 | ||
4f8036a2 TU |
13981 | if (HAS_PCH_LPT_H(dev_priv) && |
13982 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
13983 | return false; |
13984 | ||
70ac54d0 | 13985 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 13986 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
13987 | return false; |
13988 | ||
e4abb733 | 13989 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
13990 | return false; |
13991 | ||
13992 | return true; | |
13993 | } | |
13994 | ||
8090ba8c ID |
13995 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
13996 | { | |
13997 | int pps_num; | |
13998 | int pps_idx; | |
13999 | ||
14000 | if (HAS_DDI(dev_priv)) | |
14001 | return; | |
14002 | /* | |
14003 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
14004 | * everywhere where registers can be write protected. | |
14005 | */ | |
14006 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14007 | pps_num = 2; | |
14008 | else | |
14009 | pps_num = 1; | |
14010 | ||
14011 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
14012 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
14013 | ||
14014 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
14015 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
14016 | } | |
14017 | } | |
14018 | ||
44cb734c ID |
14019 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
14020 | { | |
cc3f90f0 | 14021 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
14022 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
14023 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14024 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
14025 | else | |
14026 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
14027 | |
14028 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
14029 | } |
14030 | ||
c39055b0 | 14031 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 14032 | { |
4ef69c7a | 14033 | struct intel_encoder *encoder; |
cb0953d7 | 14034 | bool dpd_is_edp = false; |
79e53945 | 14035 | |
44cb734c ID |
14036 | intel_pps_init(dev_priv); |
14037 | ||
97a824e1 ID |
14038 | /* |
14039 | * intel_edp_init_connector() depends on this completing first, to | |
14040 | * prevent the registeration of both eDP and LVDS and the incorrect | |
14041 | * sharing of the PPS. | |
14042 | */ | |
c39055b0 | 14043 | intel_lvds_init(dev_priv); |
79e53945 | 14044 | |
6315b5d3 | 14045 | if (intel_crt_present(dev_priv)) |
c39055b0 | 14046 | intel_crt_init(dev_priv); |
cb0953d7 | 14047 | |
cc3f90f0 | 14048 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
14049 | /* |
14050 | * FIXME: Broxton doesn't support port detection via the | |
14051 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14052 | * detect the ports. | |
14053 | */ | |
c39055b0 ACO |
14054 | intel_ddi_init(dev_priv, PORT_A); |
14055 | intel_ddi_init(dev_priv, PORT_B); | |
14056 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 14057 | |
c39055b0 | 14058 | intel_dsi_init(dev_priv); |
4f8036a2 | 14059 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
14060 | int found; |
14061 | ||
de31facd JB |
14062 | /* |
14063 | * Haswell uses DDI functions to detect digital outputs. | |
14064 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14065 | * it's there. | |
14066 | */ | |
77179400 | 14067 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14068 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 14069 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 14070 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
14071 | |
14072 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14073 | * register */ | |
14074 | found = I915_READ(SFUSE_STRAP); | |
14075 | ||
14076 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 14077 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 14078 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 14079 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 14080 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 14081 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
14082 | /* |
14083 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14084 | */ | |
b976dc53 | 14085 | if (IS_GEN9_BC(dev_priv) && |
2800e4c2 RV |
14086 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14087 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14088 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 14089 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 14090 | |
6e266956 | 14091 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 14092 | int found; |
dd11bc10 | 14093 | dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); |
270b3042 | 14094 | |
646d5772 | 14095 | if (has_edp_a(dev_priv)) |
c39055b0 | 14096 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 14097 | |
dc0fa718 | 14098 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14099 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 14100 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 14101 | if (!found) |
c39055b0 | 14102 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 14103 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 14104 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14105 | } |
14106 | ||
dc0fa718 | 14107 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 14108 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 14109 | |
dc0fa718 | 14110 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 14111 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 14112 | |
5eb08b69 | 14113 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 14114 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 14115 | |
270b3042 | 14116 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 14117 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 14118 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 14119 | bool has_edp, has_port; |
457c52d8 | 14120 | |
e17ac6db VS |
14121 | /* |
14122 | * The DP_DETECTED bit is the latched state of the DDC | |
14123 | * SDA pin at boot. However since eDP doesn't require DDC | |
14124 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14125 | * eDP ports may have been muxed to an alternate function. | |
14126 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14127 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14128 | * detect eDP ports. | |
22f35042 VS |
14129 | * |
14130 | * Sadly the straps seem to be missing sometimes even for HDMI | |
14131 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
14132 | * and VBT for the presence of the port. Additionally we can't | |
14133 | * trust the port type the VBT declares as we've seen at least | |
14134 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 14135 | */ |
dd11bc10 | 14136 | has_edp = intel_dp_is_edp(dev_priv, PORT_B); |
22f35042 VS |
14137 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
14138 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 14139 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 14140 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 14141 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 14142 | |
dd11bc10 | 14143 | has_edp = intel_dp_is_edp(dev_priv, PORT_C); |
22f35042 VS |
14144 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
14145 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 14146 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 14147 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 14148 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 14149 | |
920a14b2 | 14150 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
14151 | /* |
14152 | * eDP not supported on port D, | |
14153 | * so no need to worry about it | |
14154 | */ | |
14155 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
14156 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 14157 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 14158 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 14159 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
14160 | } |
14161 | ||
c39055b0 | 14162 | intel_dsi_init(dev_priv); |
5db94019 | 14163 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 14164 | bool found = false; |
7d57382e | 14165 | |
e2debe91 | 14166 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14167 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 14168 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 14169 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 14170 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 14171 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14172 | } |
27185ae1 | 14173 | |
9beb5fea | 14174 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 14175 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 14176 | } |
13520b05 KH |
14177 | |
14178 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14179 | |
e2debe91 | 14180 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14181 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 14182 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14183 | } |
27185ae1 | 14184 | |
e2debe91 | 14185 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14186 | |
9beb5fea | 14187 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 14188 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 14189 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14190 | } |
9beb5fea | 14191 | if (IS_G4X(dev_priv)) |
c39055b0 | 14192 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 14193 | } |
27185ae1 | 14194 | |
9beb5fea | 14195 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 14196 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 14197 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 14198 | intel_dvo_init(dev_priv); |
79e53945 | 14199 | |
56b857a5 | 14200 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 14201 | intel_tv_init(dev_priv); |
79e53945 | 14202 | |
c39055b0 | 14203 | intel_psr_init(dev_priv); |
7c8f8a70 | 14204 | |
c39055b0 | 14205 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
14206 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14207 | encoder->base.possible_clones = | |
66a9278e | 14208 | intel_encoder_clones(encoder); |
79e53945 | 14209 | } |
47356eb6 | 14210 | |
c39055b0 | 14211 | intel_init_pch_refclk(dev_priv); |
270b3042 | 14212 | |
c39055b0 | 14213 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
14214 | } |
14215 | ||
14216 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14217 | { | |
14218 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 14219 | |
ef2d633e | 14220 | drm_framebuffer_cleanup(fb); |
70001cd2 | 14221 | |
dd689287 CW |
14222 | i915_gem_object_lock(intel_fb->obj); |
14223 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
14224 | i915_gem_object_unlock(intel_fb->obj); | |
14225 | ||
f8c417cd | 14226 | i915_gem_object_put(intel_fb->obj); |
70001cd2 | 14227 | |
79e53945 JB |
14228 | kfree(intel_fb); |
14229 | } | |
14230 | ||
14231 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14232 | struct drm_file *file, |
79e53945 JB |
14233 | unsigned int *handle) |
14234 | { | |
14235 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14236 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14237 | |
cc917ab4 CW |
14238 | if (obj->userptr.mm) { |
14239 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14240 | return -EINVAL; | |
14241 | } | |
14242 | ||
05394f39 | 14243 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14244 | } |
14245 | ||
86c98588 RV |
14246 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14247 | struct drm_file *file, | |
14248 | unsigned flags, unsigned color, | |
14249 | struct drm_clip_rect *clips, | |
14250 | unsigned num_clips) | |
14251 | { | |
5a97bcc6 | 14252 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 14253 | |
5a97bcc6 | 14254 | i915_gem_object_flush_if_display(obj); |
d59b21ec | 14255 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
86c98588 RV |
14256 | |
14257 | return 0; | |
14258 | } | |
14259 | ||
79e53945 JB |
14260 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14261 | .destroy = intel_user_framebuffer_destroy, | |
14262 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14263 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14264 | }; |
14265 | ||
b321803d | 14266 | static |
920a14b2 TU |
14267 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
14268 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 14269 | { |
24dbf51a | 14270 | u32 gen = INTEL_GEN(dev_priv); |
b321803d DL |
14271 | |
14272 | if (gen >= 9) { | |
ac484963 VS |
14273 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14274 | ||
b321803d DL |
14275 | /* "The stride in bytes must not exceed the of the size of 8K |
14276 | * pixels and 32K bytes." | |
14277 | */ | |
ac484963 | 14278 | return min(8192 * cpp, 32768); |
6401c37d | 14279 | } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) { |
b321803d DL |
14280 | return 32*1024; |
14281 | } else if (gen >= 4) { | |
14282 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14283 | return 16*1024; | |
14284 | else | |
14285 | return 32*1024; | |
14286 | } else if (gen >= 3) { | |
14287 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14288 | return 8*1024; | |
14289 | else | |
14290 | return 16*1024; | |
14291 | } else { | |
14292 | /* XXX DSPC is limited to 4k tiled */ | |
14293 | return 8*1024; | |
14294 | } | |
14295 | } | |
14296 | ||
24dbf51a CW |
14297 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
14298 | struct drm_i915_gem_object *obj, | |
14299 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 14300 | { |
24dbf51a | 14301 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
b3c11ac2 | 14302 | struct drm_format_name_buf format_name; |
dd689287 CW |
14303 | u32 pitch_limit, stride_alignment; |
14304 | unsigned int tiling, stride; | |
24dbf51a | 14305 | int ret = -EINVAL; |
79e53945 | 14306 | |
dd689287 CW |
14307 | i915_gem_object_lock(obj); |
14308 | obj->framebuffer_references++; | |
14309 | tiling = i915_gem_object_get_tiling(obj); | |
14310 | stride = i915_gem_object_get_stride(obj); | |
14311 | i915_gem_object_unlock(obj); | |
dd4916c5 | 14312 | |
2a80eada | 14313 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
14314 | /* |
14315 | * If there's a fence, enforce that | |
14316 | * the fb modifier and tiling mode match. | |
14317 | */ | |
14318 | if (tiling != I915_TILING_NONE && | |
14319 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
2a80eada | 14320 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
24dbf51a | 14321 | goto err; |
2a80eada DV |
14322 | } |
14323 | } else { | |
c2ff7370 | 14324 | if (tiling == I915_TILING_X) { |
2a80eada | 14325 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 14326 | } else if (tiling == I915_TILING_Y) { |
2a80eada | 14327 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
24dbf51a | 14328 | goto err; |
2a80eada DV |
14329 | } |
14330 | } | |
14331 | ||
9a8f0a12 TU |
14332 | /* Passed in modifier sanity checking. */ |
14333 | switch (mode_cmd->modifier[0]) { | |
14334 | case I915_FORMAT_MOD_Y_TILED: | |
14335 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 14336 | if (INTEL_GEN(dev_priv) < 9) { |
9a8f0a12 TU |
14337 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", |
14338 | mode_cmd->modifier[0]); | |
24dbf51a | 14339 | goto err; |
9a8f0a12 TU |
14340 | } |
14341 | case DRM_FORMAT_MOD_NONE: | |
14342 | case I915_FORMAT_MOD_X_TILED: | |
14343 | break; | |
14344 | default: | |
c0f40428 JB |
14345 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14346 | mode_cmd->modifier[0]); | |
24dbf51a | 14347 | goto err; |
c16ed4be | 14348 | } |
57cd6508 | 14349 | |
c2ff7370 VS |
14350 | /* |
14351 | * gen2/3 display engine uses the fence if present, | |
14352 | * so the tiling mode must match the fb modifier exactly. | |
14353 | */ | |
14354 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
14355 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
14356 | DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n"); | |
9aceb5c1 | 14357 | goto err; |
c2ff7370 VS |
14358 | } |
14359 | ||
7b49f948 VS |
14360 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14361 | mode_cmd->modifier[0], | |
b321803d DL |
14362 | mode_cmd->pixel_format); |
14363 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14364 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14365 | mode_cmd->pitches[0], stride_alignment); | |
24dbf51a | 14366 | goto err; |
c16ed4be | 14367 | } |
57cd6508 | 14368 | |
920a14b2 | 14369 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 14370 | mode_cmd->pixel_format); |
a35cdaa0 | 14371 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14372 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14373 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14374 | "tiled" : "linear", |
a35cdaa0 | 14375 | mode_cmd->pitches[0], pitch_limit); |
24dbf51a | 14376 | goto err; |
c16ed4be | 14377 | } |
5d7bd705 | 14378 | |
c2ff7370 VS |
14379 | /* |
14380 | * If there's a fence, enforce that | |
14381 | * the fb pitch and fence stride match. | |
14382 | */ | |
dd689287 | 14383 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
c16ed4be | 14384 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
dd689287 | 14385 | mode_cmd->pitches[0], stride); |
24dbf51a | 14386 | goto err; |
c16ed4be | 14387 | } |
5d7bd705 | 14388 | |
57779d06 | 14389 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14390 | switch (mode_cmd->pixel_format) { |
57779d06 | 14391 | case DRM_FORMAT_C8: |
04b3924d VS |
14392 | case DRM_FORMAT_RGB565: |
14393 | case DRM_FORMAT_XRGB8888: | |
14394 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14395 | break; |
14396 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 14397 | if (INTEL_GEN(dev_priv) > 3) { |
b3c11ac2 EE |
14398 | DRM_DEBUG("unsupported pixel format: %s\n", |
14399 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14400 | goto err; |
c16ed4be | 14401 | } |
57779d06 | 14402 | break; |
57779d06 | 14403 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 14404 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 14405 | INTEL_GEN(dev_priv) < 9) { |
b3c11ac2 EE |
14406 | DRM_DEBUG("unsupported pixel format: %s\n", |
14407 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14408 | goto err; |
6c0fd451 DL |
14409 | } |
14410 | break; | |
14411 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14412 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14413 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 14414 | if (INTEL_GEN(dev_priv) < 4) { |
b3c11ac2 EE |
14415 | DRM_DEBUG("unsupported pixel format: %s\n", |
14416 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14417 | goto err; |
c16ed4be | 14418 | } |
b5626747 | 14419 | break; |
7531208b | 14420 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 14421 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
b3c11ac2 EE |
14422 | DRM_DEBUG("unsupported pixel format: %s\n", |
14423 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14424 | goto err; |
7531208b DL |
14425 | } |
14426 | break; | |
04b3924d VS |
14427 | case DRM_FORMAT_YUYV: |
14428 | case DRM_FORMAT_UYVY: | |
14429 | case DRM_FORMAT_YVYU: | |
14430 | case DRM_FORMAT_VYUY: | |
6315b5d3 | 14431 | if (INTEL_GEN(dev_priv) < 5) { |
b3c11ac2 EE |
14432 | DRM_DEBUG("unsupported pixel format: %s\n", |
14433 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14434 | goto err; |
c16ed4be | 14435 | } |
57cd6508 CW |
14436 | break; |
14437 | default: | |
b3c11ac2 EE |
14438 | DRM_DEBUG("unsupported pixel format: %s\n", |
14439 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14440 | goto err; |
57cd6508 CW |
14441 | } |
14442 | ||
90f9a336 VS |
14443 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14444 | if (mode_cmd->offsets[0] != 0) | |
24dbf51a | 14445 | goto err; |
90f9a336 | 14446 | |
24dbf51a CW |
14447 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, |
14448 | &intel_fb->base, mode_cmd); | |
c7d73f6a DV |
14449 | intel_fb->obj = obj; |
14450 | ||
6687c906 VS |
14451 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
14452 | if (ret) | |
9aceb5c1 | 14453 | goto err; |
2d7a215f | 14454 | |
24dbf51a CW |
14455 | ret = drm_framebuffer_init(obj->base.dev, |
14456 | &intel_fb->base, | |
14457 | &intel_fb_funcs); | |
79e53945 JB |
14458 | if (ret) { |
14459 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
24dbf51a | 14460 | goto err; |
79e53945 JB |
14461 | } |
14462 | ||
79e53945 | 14463 | return 0; |
24dbf51a CW |
14464 | |
14465 | err: | |
dd689287 CW |
14466 | i915_gem_object_lock(obj); |
14467 | obj->framebuffer_references--; | |
14468 | i915_gem_object_unlock(obj); | |
24dbf51a | 14469 | return ret; |
79e53945 JB |
14470 | } |
14471 | ||
79e53945 JB |
14472 | static struct drm_framebuffer * |
14473 | intel_user_framebuffer_create(struct drm_device *dev, | |
14474 | struct drm_file *filp, | |
1eb83451 | 14475 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14476 | { |
dcb1394e | 14477 | struct drm_framebuffer *fb; |
05394f39 | 14478 | struct drm_i915_gem_object *obj; |
76dc3769 | 14479 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14480 | |
03ac0642 CW |
14481 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
14482 | if (!obj) | |
cce13ff7 | 14483 | return ERR_PTR(-ENOENT); |
79e53945 | 14484 | |
24dbf51a | 14485 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 14486 | if (IS_ERR(fb)) |
f0cd5182 | 14487 | i915_gem_object_put(obj); |
dcb1394e LW |
14488 | |
14489 | return fb; | |
79e53945 JB |
14490 | } |
14491 | ||
778e23a9 CW |
14492 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
14493 | { | |
14494 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
14495 | ||
14496 | drm_atomic_state_default_release(state); | |
14497 | ||
14498 | i915_sw_fence_fini(&intel_state->commit_ready); | |
14499 | ||
14500 | kfree(state); | |
14501 | } | |
14502 | ||
79e53945 | 14503 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14504 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14505 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14506 | .atomic_check = intel_atomic_check, |
14507 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14508 | .atomic_state_alloc = intel_atomic_state_alloc, |
14509 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 14510 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
14511 | }; |
14512 | ||
88212941 ID |
14513 | /** |
14514 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14515 | * @dev_priv: device private | |
14516 | */ | |
14517 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14518 | { |
7ff89ca2 VS |
14519 | intel_init_cdclk_hooks(dev_priv); |
14520 | ||
88212941 | 14521 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14522 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14523 | dev_priv->display.get_initial_plane_config = |
14524 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14525 | dev_priv->display.crtc_compute_clock = |
14526 | haswell_crtc_compute_clock; | |
14527 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14528 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14529 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14530 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14531 | dev_priv->display.get_initial_plane_config = |
14532 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14533 | dev_priv->display.crtc_compute_clock = |
14534 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14535 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14536 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14537 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14538 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14539 | dev_priv->display.get_initial_plane_config = |
14540 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14541 | dev_priv->display.crtc_compute_clock = |
14542 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14543 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14544 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14545 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14546 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14547 | dev_priv->display.get_initial_plane_config = |
14548 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14549 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14550 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14551 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14552 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14553 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14554 | dev_priv->display.get_initial_plane_config = | |
14555 | i9xx_get_initial_plane_config; | |
14556 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14557 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14558 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14559 | } else if (IS_G4X(dev_priv)) { |
14560 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14561 | dev_priv->display.get_initial_plane_config = | |
14562 | i9xx_get_initial_plane_config; | |
14563 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14564 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14565 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14566 | } else if (IS_PINEVIEW(dev_priv)) { |
14567 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14568 | dev_priv->display.get_initial_plane_config = | |
14569 | i9xx_get_initial_plane_config; | |
14570 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14571 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14572 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14573 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14574 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14575 | dev_priv->display.get_initial_plane_config = |
14576 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14577 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14578 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14579 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14580 | } else { |
14581 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14582 | dev_priv->display.get_initial_plane_config = | |
14583 | i9xx_get_initial_plane_config; | |
14584 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14585 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14586 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14587 | } |
e70236a8 | 14588 | |
88212941 | 14589 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14590 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14591 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14592 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14593 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14594 | /* FIXME: detect B0+ stepping and use auto training */ |
14595 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14596 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14597 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14598 | } |
14599 | ||
27082493 L |
14600 | if (dev_priv->info.gen >= 9) |
14601 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
14602 | else | |
14603 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
14604 | ||
5a21b665 DV |
14605 | switch (INTEL_INFO(dev_priv)->gen) { |
14606 | case 2: | |
14607 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14608 | break; | |
14609 | ||
14610 | case 3: | |
14611 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14612 | break; | |
14613 | ||
14614 | case 4: | |
14615 | case 5: | |
14616 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14617 | break; | |
14618 | ||
14619 | case 6: | |
14620 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14621 | break; | |
14622 | case 7: | |
14623 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
14624 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
14625 | break; | |
14626 | case 9: | |
14627 | /* Drop through - unsupported since execlist only. */ | |
14628 | default: | |
14629 | /* Default just returns -ENODEV to indicate unsupported */ | |
14630 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
14631 | } | |
e70236a8 JB |
14632 | } |
14633 | ||
b690e96c JB |
14634 | /* |
14635 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14636 | * resume, or other times. This quirk makes sure that's the case for | |
14637 | * affected systems. | |
14638 | */ | |
0206e353 | 14639 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 14640 | { |
fac5e23e | 14641 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
14642 | |
14643 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14644 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14645 | } |
14646 | ||
b6b5d049 VS |
14647 | static void quirk_pipeb_force(struct drm_device *dev) |
14648 | { | |
fac5e23e | 14649 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
14650 | |
14651 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14652 | DRM_INFO("applying pipe b force quirk\n"); | |
14653 | } | |
14654 | ||
435793df KP |
14655 | /* |
14656 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14657 | */ | |
14658 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14659 | { | |
fac5e23e | 14660 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 14661 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 14662 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14663 | } |
14664 | ||
4dca20ef | 14665 | /* |
5a15ab5b CE |
14666 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14667 | * brightness value | |
4dca20ef CE |
14668 | */ |
14669 | static void quirk_invert_brightness(struct drm_device *dev) | |
14670 | { | |
fac5e23e | 14671 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 14672 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 14673 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14674 | } |
14675 | ||
9c72cc6f SD |
14676 | /* Some VBT's incorrectly indicate no backlight is present */ |
14677 | static void quirk_backlight_present(struct drm_device *dev) | |
14678 | { | |
fac5e23e | 14679 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
14680 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
14681 | DRM_INFO("applying backlight present quirk\n"); | |
14682 | } | |
14683 | ||
b690e96c JB |
14684 | struct intel_quirk { |
14685 | int device; | |
14686 | int subsystem_vendor; | |
14687 | int subsystem_device; | |
14688 | void (*hook)(struct drm_device *dev); | |
14689 | }; | |
14690 | ||
5f85f176 EE |
14691 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14692 | struct intel_dmi_quirk { | |
14693 | void (*hook)(struct drm_device *dev); | |
14694 | const struct dmi_system_id (*dmi_id_list)[]; | |
14695 | }; | |
14696 | ||
14697 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14698 | { | |
14699 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14700 | return 1; | |
14701 | } | |
14702 | ||
14703 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14704 | { | |
14705 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14706 | { | |
14707 | .callback = intel_dmi_reverse_brightness, | |
14708 | .ident = "NCR Corporation", | |
14709 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14710 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14711 | }, | |
14712 | }, | |
14713 | { } /* terminating entry */ | |
14714 | }, | |
14715 | .hook = quirk_invert_brightness, | |
14716 | }, | |
14717 | }; | |
14718 | ||
c43b5634 | 14719 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14720 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14721 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14722 | ||
b690e96c JB |
14723 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14724 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14725 | ||
5f080c0f VS |
14726 | /* 830 needs to leave pipe A & dpll A up */ |
14727 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14728 | ||
b6b5d049 VS |
14729 | /* 830 needs to leave pipe B & dpll B up */ |
14730 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14731 | ||
435793df KP |
14732 | /* Lenovo U160 cannot use SSC on LVDS */ |
14733 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14734 | |
14735 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14736 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14737 | |
be505f64 AH |
14738 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14739 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14740 | ||
14741 | /* Acer/eMachines G725 */ | |
14742 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14743 | ||
14744 | /* Acer/eMachines e725 */ | |
14745 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14746 | ||
14747 | /* Acer/Packard Bell NCL20 */ | |
14748 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14749 | ||
14750 | /* Acer Aspire 4736Z */ | |
14751 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14752 | |
14753 | /* Acer Aspire 5336 */ | |
14754 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14755 | |
14756 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14757 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14758 | |
dfb3d47b SD |
14759 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14760 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14761 | ||
b2a9601c | 14762 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14763 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14764 | ||
1b9448b0 JN |
14765 | /* Apple Macbook 4,1 */ |
14766 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
14767 | ||
d4967d8c SD |
14768 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14769 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14770 | |
14771 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14772 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14773 | |
14774 | /* Dell Chromebook 11 */ | |
14775 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
14776 | |
14777 | /* Dell Chromebook 11 (2015 version) */ | |
14778 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14779 | }; |
14780 | ||
14781 | static void intel_init_quirks(struct drm_device *dev) | |
14782 | { | |
14783 | struct pci_dev *d = dev->pdev; | |
14784 | int i; | |
14785 | ||
14786 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14787 | struct intel_quirk *q = &intel_quirks[i]; | |
14788 | ||
14789 | if (d->device == q->device && | |
14790 | (d->subsystem_vendor == q->subsystem_vendor || | |
14791 | q->subsystem_vendor == PCI_ANY_ID) && | |
14792 | (d->subsystem_device == q->subsystem_device || | |
14793 | q->subsystem_device == PCI_ANY_ID)) | |
14794 | q->hook(dev); | |
14795 | } | |
5f85f176 EE |
14796 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14797 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14798 | intel_dmi_quirks[i].hook(dev); | |
14799 | } | |
b690e96c JB |
14800 | } |
14801 | ||
9cce37f4 | 14802 | /* Disable the VGA plane that we never use */ |
29b74b7f | 14803 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 14804 | { |
52a05c30 | 14805 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 14806 | u8 sr1; |
920a14b2 | 14807 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 14808 | |
2b37c616 | 14809 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 14810 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14811 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14812 | sr1 = inb(VGA_SR_DATA); |
14813 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 14814 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
14815 | udelay(300); |
14816 | ||
01f5a626 | 14817 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14818 | POSTING_READ(vga_reg); |
14819 | } | |
14820 | ||
f817586c DV |
14821 | void intel_modeset_init_hw(struct drm_device *dev) |
14822 | { | |
fac5e23e | 14823 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 14824 | |
4c75b940 | 14825 | intel_update_cdclk(dev_priv); |
bb0f4aab | 14826 | dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; |
1a617b77 | 14827 | |
46f16e63 | 14828 | intel_init_clock_gating(dev_priv); |
f817586c DV |
14829 | } |
14830 | ||
d93c0372 MR |
14831 | /* |
14832 | * Calculate what we think the watermarks should be for the state we've read | |
14833 | * out of the hardware and then immediately program those watermarks so that | |
14834 | * we ensure the hardware settings match our internal state. | |
14835 | * | |
14836 | * We can calculate what we think WM's should be by creating a duplicate of the | |
14837 | * current state (which was constructed during hardware readout) and running it | |
14838 | * through the atomic check code to calculate new watermark values in the | |
14839 | * state object. | |
14840 | */ | |
14841 | static void sanitize_watermarks(struct drm_device *dev) | |
14842 | { | |
14843 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14844 | struct drm_atomic_state *state; | |
ccf010fb | 14845 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
14846 | struct drm_crtc *crtc; |
14847 | struct drm_crtc_state *cstate; | |
14848 | struct drm_modeset_acquire_ctx ctx; | |
14849 | int ret; | |
14850 | int i; | |
14851 | ||
14852 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 14853 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
14854 | return; |
14855 | ||
14856 | /* | |
14857 | * We need to hold connection_mutex before calling duplicate_state so | |
14858 | * that the connector loop is protected. | |
14859 | */ | |
14860 | drm_modeset_acquire_init(&ctx, 0); | |
14861 | retry: | |
0cd1262d | 14862 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
14863 | if (ret == -EDEADLK) { |
14864 | drm_modeset_backoff(&ctx); | |
14865 | goto retry; | |
14866 | } else if (WARN_ON(ret)) { | |
0cd1262d | 14867 | goto fail; |
d93c0372 MR |
14868 | } |
14869 | ||
14870 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
14871 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 14872 | goto fail; |
d93c0372 | 14873 | |
ccf010fb ML |
14874 | intel_state = to_intel_atomic_state(state); |
14875 | ||
ed4a6a7c MR |
14876 | /* |
14877 | * Hardware readout is the only time we don't want to calculate | |
14878 | * intermediate watermarks (since we don't trust the current | |
14879 | * watermarks). | |
14880 | */ | |
602ae835 VS |
14881 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14882 | intel_state->skip_intermediate_wm = true; | |
ed4a6a7c | 14883 | |
d93c0372 MR |
14884 | ret = intel_atomic_check(dev, state); |
14885 | if (ret) { | |
14886 | /* | |
14887 | * If we fail here, it means that the hardware appears to be | |
14888 | * programmed in a way that shouldn't be possible, given our | |
14889 | * understanding of watermark requirements. This might mean a | |
14890 | * mistake in the hardware readout code or a mistake in the | |
14891 | * watermark calculations for a given platform. Raise a WARN | |
14892 | * so that this is noticeable. | |
14893 | * | |
14894 | * If this actually happens, we'll have to just leave the | |
14895 | * BIOS-programmed watermarks untouched and hope for the best. | |
14896 | */ | |
14897 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 14898 | goto put_state; |
d93c0372 MR |
14899 | } |
14900 | ||
14901 | /* Write calculated watermark values back */ | |
d93c0372 MR |
14902 | for_each_crtc_in_state(state, crtc, cstate, i) { |
14903 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
14904 | ||
ed4a6a7c | 14905 | cs->wm.need_postvbl_update = true; |
ccf010fb | 14906 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
14907 | } |
14908 | ||
b9a1b717 | 14909 | put_state: |
0853695c | 14910 | drm_atomic_state_put(state); |
0cd1262d | 14911 | fail: |
d93c0372 MR |
14912 | drm_modeset_drop_locks(&ctx); |
14913 | drm_modeset_acquire_fini(&ctx); | |
14914 | } | |
14915 | ||
b079bd17 | 14916 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 14917 | { |
72e96d64 JL |
14918 | struct drm_i915_private *dev_priv = to_i915(dev); |
14919 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 14920 | enum pipe pipe; |
46f297fb | 14921 | struct intel_crtc *crtc; |
79e53945 JB |
14922 | |
14923 | drm_mode_config_init(dev); | |
14924 | ||
14925 | dev->mode_config.min_width = 0; | |
14926 | dev->mode_config.min_height = 0; | |
14927 | ||
019d96cb DA |
14928 | dev->mode_config.preferred_depth = 24; |
14929 | dev->mode_config.prefer_shadow = 1; | |
14930 | ||
25bab385 TU |
14931 | dev->mode_config.allow_fb_modifiers = true; |
14932 | ||
e6ecefaa | 14933 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14934 | |
eb955eee | 14935 | INIT_WORK(&dev_priv->atomic_helper.free_work, |
ba318c61 | 14936 | intel_atomic_helper_free_state_worker); |
eb955eee | 14937 | |
b690e96c JB |
14938 | intel_init_quirks(dev); |
14939 | ||
62d75df7 | 14940 | intel_init_pm(dev_priv); |
1fa61106 | 14941 | |
b7f05d4a | 14942 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 14943 | return 0; |
e3c74757 | 14944 | |
69f92f67 LW |
14945 | /* |
14946 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14947 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14948 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14949 | * indicates as much. | |
14950 | */ | |
6e266956 | 14951 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
14952 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
14953 | DREF_SSC1_ENABLE); | |
14954 | ||
14955 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14956 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14957 | bios_lvds_use_ssc ? "en" : "dis", | |
14958 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14959 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14960 | } | |
14961 | } | |
14962 | ||
5db94019 | 14963 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
14964 | dev->mode_config.max_width = 2048; |
14965 | dev->mode_config.max_height = 2048; | |
5db94019 | 14966 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
14967 | dev->mode_config.max_width = 4096; |
14968 | dev->mode_config.max_height = 4096; | |
79e53945 | 14969 | } else { |
a6c45cf0 CW |
14970 | dev->mode_config.max_width = 8192; |
14971 | dev->mode_config.max_height = 8192; | |
79e53945 | 14972 | } |
068be561 | 14973 | |
2a307c2e JN |
14974 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
14975 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 14976 | dev->mode_config.cursor_height = 1023; |
5db94019 | 14977 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
14978 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14979 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14980 | } else { | |
14981 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14982 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14983 | } | |
14984 | ||
72e96d64 | 14985 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 14986 | |
28c97730 | 14987 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
14988 | INTEL_INFO(dev_priv)->num_pipes, |
14989 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14990 | |
055e393f | 14991 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
14992 | int ret; |
14993 | ||
5ab0d85b | 14994 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
14995 | if (ret) { |
14996 | drm_mode_config_cleanup(dev); | |
14997 | return ret; | |
14998 | } | |
79e53945 JB |
14999 | } |
15000 | ||
e72f9fbf | 15001 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15002 | |
5be6e334 VS |
15003 | intel_update_czclk(dev_priv); |
15004 | intel_modeset_init_hw(dev); | |
15005 | ||
b2045352 | 15006 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 15007 | intel_update_max_cdclk(dev_priv); |
b2045352 | 15008 | |
9cce37f4 | 15009 | /* Just disable it once at startup */ |
29b74b7f | 15010 | i915_disable_vga(dev_priv); |
c39055b0 | 15011 | intel_setup_outputs(dev_priv); |
11be49eb | 15012 | |
6e9f798d | 15013 | drm_modeset_lock_all(dev); |
043e9bda | 15014 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15015 | drm_modeset_unlock_all(dev); |
46f297fb | 15016 | |
d3fcc808 | 15017 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15018 | struct intel_initial_plane_config plane_config = {}; |
15019 | ||
46f297fb JB |
15020 | if (!crtc->active) |
15021 | continue; | |
15022 | ||
46f297fb | 15023 | /* |
46f297fb JB |
15024 | * Note that reserving the BIOS fb up front prevents us |
15025 | * from stuffing other stolen allocations like the ring | |
15026 | * on top. This prevents some ugliness at boot time, and | |
15027 | * can even allow for smooth boot transitions if the BIOS | |
15028 | * fb is large enough for the active pipe configuration. | |
15029 | */ | |
eeebeac5 ML |
15030 | dev_priv->display.get_initial_plane_config(crtc, |
15031 | &plane_config); | |
15032 | ||
15033 | /* | |
15034 | * If the fb is shared between multiple heads, we'll | |
15035 | * just get the first one. | |
15036 | */ | |
15037 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15038 | } |
d93c0372 MR |
15039 | |
15040 | /* | |
15041 | * Make sure hardware watermarks really match the state we read out. | |
15042 | * Note that we need to do this after reconstructing the BIOS fb's | |
15043 | * since the watermark calculation done here will use pstate->fb. | |
15044 | */ | |
602ae835 VS |
15045 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
15046 | sanitize_watermarks(dev); | |
b079bd17 VS |
15047 | |
15048 | return 0; | |
2c7111db CW |
15049 | } |
15050 | ||
7fad798e DV |
15051 | static void intel_enable_pipe_a(struct drm_device *dev) |
15052 | { | |
15053 | struct intel_connector *connector; | |
15054 | struct drm_connector *crt = NULL; | |
15055 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15056 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15057 | |
15058 | /* We can't just switch on the pipe A, we need to set things up with a | |
15059 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15060 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15061 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15062 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15063 | crt = &connector->base; | |
15064 | break; | |
15065 | } | |
15066 | } | |
15067 | ||
15068 | if (!crt) | |
15069 | return; | |
15070 | ||
208bf9fd | 15071 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15072 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15073 | } |
15074 | ||
fa555837 DV |
15075 | static bool |
15076 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15077 | { | |
b7f05d4a | 15078 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 15079 | u32 val; |
fa555837 | 15080 | |
b7f05d4a | 15081 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
15082 | return true; |
15083 | ||
649636ef | 15084 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15085 | |
15086 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15087 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15088 | return false; | |
15089 | ||
15090 | return true; | |
15091 | } | |
15092 | ||
02e93c35 VS |
15093 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15094 | { | |
15095 | struct drm_device *dev = crtc->base.dev; | |
15096 | struct intel_encoder *encoder; | |
15097 | ||
15098 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15099 | return true; | |
15100 | ||
15101 | return false; | |
15102 | } | |
15103 | ||
496b0fc3 ML |
15104 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
15105 | { | |
15106 | struct drm_device *dev = encoder->base.dev; | |
15107 | struct intel_connector *connector; | |
15108 | ||
15109 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15110 | return connector; | |
15111 | ||
15112 | return NULL; | |
15113 | } | |
15114 | ||
a168f5b3 VS |
15115 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
15116 | enum transcoder pch_transcoder) | |
15117 | { | |
15118 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
15119 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
15120 | } | |
15121 | ||
24929352 DV |
15122 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15123 | { | |
15124 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 15125 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 15126 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15127 | |
24929352 | 15128 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15129 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15130 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15131 | ||
15132 | I915_WRITE(reg, | |
15133 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15134 | } | |
24929352 | 15135 | |
d3eaf884 | 15136 | /* restore vblank interrupts to correct state */ |
9625604c | 15137 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15138 | if (crtc->active) { |
f9cd7b88 VS |
15139 | struct intel_plane *plane; |
15140 | ||
9625604c | 15141 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15142 | |
15143 | /* Disable everything but the primary plane */ | |
15144 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15145 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15146 | continue; | |
15147 | ||
15148 | plane->disable_plane(&plane->base, &crtc->base); | |
15149 | } | |
9625604c | 15150 | } |
d3eaf884 | 15151 | |
24929352 | 15152 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15153 | * disable the crtc (and hence change the state) if it is wrong. Note |
15154 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 15155 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
15156 | bool plane; |
15157 | ||
78108b7c VS |
15158 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
15159 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
15160 | |
15161 | /* Pipe has the wrong plane attached and the plane is active. | |
15162 | * Temporarily change the plane mapping and disable everything | |
15163 | * ... */ | |
15164 | plane = crtc->plane; | |
1d4258db | 15165 | crtc->base.primary->state->visible = true; |
24929352 | 15166 | crtc->plane = !plane; |
b17d48e2 | 15167 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15168 | crtc->plane = plane; |
24929352 | 15169 | } |
24929352 | 15170 | |
7fad798e DV |
15171 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15172 | crtc->pipe == PIPE_A && !crtc->active) { | |
15173 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15174 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15175 | * call below we restore the pipe to the right state, but leave | |
15176 | * the required bits on. */ | |
15177 | intel_enable_pipe_a(dev); | |
15178 | } | |
15179 | ||
24929352 DV |
15180 | /* Adjust the state of the output pipe according to whether we |
15181 | * have active connectors/encoders. */ | |
842e0307 | 15182 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15183 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15184 | |
49cff963 | 15185 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
15186 | /* |
15187 | * We start out with underrun reporting disabled to avoid races. | |
15188 | * For correct bookkeeping mark this on active crtcs. | |
15189 | * | |
c5ab3bc0 DV |
15190 | * Also on gmch platforms we dont have any hardware bits to |
15191 | * disable the underrun reporting. Which means we need to start | |
15192 | * out with underrun reporting disabled also on inactive pipes, | |
15193 | * since otherwise we'll complain about the garbage we read when | |
15194 | * e.g. coming up after runtime pm. | |
15195 | * | |
4cc31489 DV |
15196 | * No protection against concurrent access is required - at |
15197 | * worst a fifo underrun happens which also sets this to false. | |
15198 | */ | |
15199 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
15200 | /* |
15201 | * We track the PCH trancoder underrun reporting state | |
15202 | * within the crtc. With crtc for pipe A housing the underrun | |
15203 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
15204 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
15205 | * and marking underrun reporting as disabled for the non-existing | |
15206 | * PCH transcoders B and C would prevent enabling the south | |
15207 | * error interrupt (see cpt_can_enable_serr_int()). | |
15208 | */ | |
15209 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
15210 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 15211 | } |
24929352 DV |
15212 | } |
15213 | ||
15214 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15215 | { | |
15216 | struct intel_connector *connector; | |
24929352 DV |
15217 | |
15218 | /* We need to check both for a crtc link (meaning that the | |
15219 | * encoder is active and trying to read from a pipe) and the | |
15220 | * pipe itself being active. */ | |
15221 | bool has_active_crtc = encoder->base.crtc && | |
15222 | to_intel_crtc(encoder->base.crtc)->active; | |
15223 | ||
496b0fc3 ML |
15224 | connector = intel_encoder_find_connector(encoder); |
15225 | if (connector && !has_active_crtc) { | |
24929352 DV |
15226 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15227 | encoder->base.base.id, | |
8e329a03 | 15228 | encoder->base.name); |
24929352 DV |
15229 | |
15230 | /* Connector is active, but has no active pipe. This is | |
15231 | * fallout from our resume register restoring. Disable | |
15232 | * the encoder manually again. */ | |
15233 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
15234 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
15235 | ||
24929352 DV |
15236 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
15237 | encoder->base.base.id, | |
8e329a03 | 15238 | encoder->base.name); |
fd6bbda9 | 15239 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 15240 | if (encoder->post_disable) |
fd6bbda9 | 15241 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 15242 | } |
7f1950fb | 15243 | encoder->base.crtc = NULL; |
24929352 DV |
15244 | |
15245 | /* Inconsistent output/port/pipe state happens presumably due to | |
15246 | * a bug in one of the get_hw_state functions. Or someplace else | |
15247 | * in our code, like the register restore mess on resume. Clamp | |
15248 | * things to off as a safer default. */ | |
fd6bbda9 ML |
15249 | |
15250 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15251 | connector->base.encoder = NULL; | |
24929352 DV |
15252 | } |
15253 | /* Enabled encoders without active connectors will be fixed in | |
15254 | * the crtc fixup. */ | |
15255 | } | |
15256 | ||
29b74b7f | 15257 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 15258 | { |
920a14b2 | 15259 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 15260 | |
04098753 ID |
15261 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15262 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 15263 | i915_disable_vga(dev_priv); |
04098753 ID |
15264 | } |
15265 | } | |
15266 | ||
29b74b7f | 15267 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 15268 | { |
8dc8a27c PZ |
15269 | /* This function can be called both from intel_modeset_setup_hw_state or |
15270 | * at a very early point in our resume sequence, where the power well | |
15271 | * structures are not yet restored. Since this function is at a very | |
15272 | * paranoid "someone might have enabled VGA while we were not looking" | |
15273 | * level, just check if the power well is enabled instead of trying to | |
15274 | * follow the "don't touch the power well if we don't need it" policy | |
15275 | * the rest of the driver uses. */ | |
6392f847 | 15276 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15277 | return; |
15278 | ||
29b74b7f | 15279 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
15280 | |
15281 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15282 | } |
15283 | ||
f9cd7b88 | 15284 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15285 | { |
f9cd7b88 | 15286 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15287 | |
f9cd7b88 | 15288 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15289 | } |
15290 | ||
f9cd7b88 VS |
15291 | /* FIXME read out full plane state for all planes */ |
15292 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15293 | { |
e9728bd8 VS |
15294 | struct intel_plane *primary = to_intel_plane(crtc->base.primary); |
15295 | bool visible; | |
d032ffa0 | 15296 | |
e9728bd8 | 15297 | visible = crtc->active && primary_get_hw_state(primary); |
b26d3ea3 | 15298 | |
e9728bd8 VS |
15299 | intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), |
15300 | to_intel_plane_state(primary->base.state), | |
15301 | visible); | |
98ec7739 VS |
15302 | } |
15303 | ||
30e984df | 15304 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 15305 | { |
fac5e23e | 15306 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 15307 | enum pipe pipe; |
24929352 DV |
15308 | struct intel_crtc *crtc; |
15309 | struct intel_encoder *encoder; | |
15310 | struct intel_connector *connector; | |
5358901f | 15311 | int i; |
24929352 | 15312 | |
565602d7 ML |
15313 | dev_priv->active_crtcs = 0; |
15314 | ||
d3fcc808 | 15315 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
15316 | struct intel_crtc_state *crtc_state = |
15317 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 15318 | |
ec2dc6a0 | 15319 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
15320 | memset(crtc_state, 0, sizeof(*crtc_state)); |
15321 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15322 | |
565602d7 ML |
15323 | crtc_state->base.active = crtc_state->base.enable = |
15324 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15325 | ||
15326 | crtc->base.enabled = crtc_state->base.enable; | |
15327 | crtc->active = crtc_state->base.active; | |
15328 | ||
aca1ebf4 | 15329 | if (crtc_state->base.active) |
565602d7 ML |
15330 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
15331 | ||
f9cd7b88 | 15332 | readout_plane_state(crtc); |
24929352 | 15333 | |
78108b7c VS |
15334 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
15335 | crtc->base.base.id, crtc->base.name, | |
a8cd6da0 | 15336 | enableddisabled(crtc_state->base.active)); |
24929352 DV |
15337 | } |
15338 | ||
5358901f DV |
15339 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15340 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15341 | ||
2edd6443 | 15342 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
2c42e535 ACO |
15343 | &pll->state.hw_state); |
15344 | pll->state.crtc_mask = 0; | |
d3fcc808 | 15345 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
15346 | struct intel_crtc_state *crtc_state = |
15347 | to_intel_crtc_state(crtc->base.state); | |
15348 | ||
15349 | if (crtc_state->base.active && | |
15350 | crtc_state->shared_dpll == pll) | |
2c42e535 | 15351 | pll->state.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15352 | } |
2c42e535 | 15353 | pll->active_mask = pll->state.crtc_mask; |
5358901f | 15354 | |
1e6f2ddc | 15355 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
2c42e535 | 15356 | pll->name, pll->state.crtc_mask, pll->on); |
5358901f DV |
15357 | } |
15358 | ||
b2784e15 | 15359 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15360 | pipe = 0; |
15361 | ||
15362 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
15363 | struct intel_crtc_state *crtc_state; |
15364 | ||
98187836 | 15365 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 15366 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 15367 | |
045ac3b5 | 15368 | encoder->base.crtc = &crtc->base; |
a8cd6da0 VS |
15369 | crtc_state->output_types |= 1 << encoder->type; |
15370 | encoder->get_config(encoder, crtc_state); | |
24929352 DV |
15371 | } else { |
15372 | encoder->base.crtc = NULL; | |
15373 | } | |
15374 | ||
6f2bcceb | 15375 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
15376 | encoder->base.base.id, encoder->base.name, |
15377 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 15378 | pipe_name(pipe)); |
24929352 DV |
15379 | } |
15380 | ||
3a3371ff | 15381 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15382 | if (connector->get_hw_state(connector)) { |
15383 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15384 | |
15385 | encoder = connector->encoder; | |
15386 | connector->base.encoder = &encoder->base; | |
15387 | ||
15388 | if (encoder->base.crtc && | |
15389 | encoder->base.crtc->state->active) { | |
15390 | /* | |
15391 | * This has to be done during hardware readout | |
15392 | * because anything calling .crtc_disable may | |
15393 | * rely on the connector_mask being accurate. | |
15394 | */ | |
15395 | encoder->base.crtc->state->connector_mask |= | |
15396 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15397 | encoder->base.crtc->state->encoder_mask |= |
15398 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15399 | } |
15400 | ||
24929352 DV |
15401 | } else { |
15402 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15403 | connector->base.encoder = NULL; | |
15404 | } | |
15405 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
15406 | connector->base.base.id, connector->base.name, |
15407 | enableddisabled(connector->base.encoder)); | |
24929352 | 15408 | } |
7f4c6284 VS |
15409 | |
15410 | for_each_intel_crtc(dev, crtc) { | |
a8cd6da0 VS |
15411 | struct intel_crtc_state *crtc_state = |
15412 | to_intel_crtc_state(crtc->base.state); | |
aca1ebf4 VS |
15413 | int pixclk = 0; |
15414 | ||
a8cd6da0 | 15415 | crtc->base.hwmode = crtc_state->base.adjusted_mode; |
7f4c6284 VS |
15416 | |
15417 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
a8cd6da0 VS |
15418 | if (crtc_state->base.active) { |
15419 | intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); | |
15420 | intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); | |
7f4c6284 VS |
15421 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
15422 | ||
15423 | /* | |
15424 | * The initial mode needs to be set in order to keep | |
15425 | * the atomic core happy. It wants a valid mode if the | |
15426 | * crtc's enabled, so we do the above call. | |
15427 | * | |
7800fb69 DV |
15428 | * But we don't set all the derived state fully, hence |
15429 | * set a flag to indicate that a full recalculation is | |
15430 | * needed on the next commit. | |
7f4c6284 | 15431 | */ |
a8cd6da0 | 15432 | crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; |
9eca6832 | 15433 | |
a7d1b3f4 VS |
15434 | intel_crtc_compute_pixel_rate(crtc_state); |
15435 | ||
15436 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || | |
15437 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15438 | pixclk = crtc_state->pixel_rate; | |
aca1ebf4 VS |
15439 | else |
15440 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15441 | ||
15442 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
a8cd6da0 | 15443 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
aca1ebf4 VS |
15444 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
15445 | ||
9eca6832 VS |
15446 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); |
15447 | update_scanline_offset(crtc); | |
7f4c6284 | 15448 | } |
e3b247da | 15449 | |
aca1ebf4 VS |
15450 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
15451 | ||
a8cd6da0 | 15452 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 15453 | } |
30e984df DV |
15454 | } |
15455 | ||
62b69566 ACO |
15456 | static void |
15457 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
15458 | { | |
15459 | struct intel_encoder *encoder; | |
15460 | ||
15461 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
15462 | u64 get_domains; | |
15463 | enum intel_display_power_domain domain; | |
15464 | ||
15465 | if (!encoder->get_power_domains) | |
15466 | continue; | |
15467 | ||
15468 | get_domains = encoder->get_power_domains(encoder); | |
15469 | for_each_power_domain(domain, get_domains) | |
15470 | intel_display_power_get(dev_priv, domain); | |
15471 | } | |
15472 | } | |
15473 | ||
043e9bda ML |
15474 | /* Scan out the current hw modeset state, |
15475 | * and sanitizes it to the current state | |
15476 | */ | |
15477 | static void | |
15478 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 15479 | { |
fac5e23e | 15480 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 15481 | enum pipe pipe; |
30e984df DV |
15482 | struct intel_crtc *crtc; |
15483 | struct intel_encoder *encoder; | |
35c95375 | 15484 | int i; |
30e984df DV |
15485 | |
15486 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15487 | |
15488 | /* HW state is read out, now we need to sanitize this mess. */ | |
62b69566 ACO |
15489 | get_encoder_power_domains(dev_priv); |
15490 | ||
b2784e15 | 15491 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15492 | intel_sanitize_encoder(encoder); |
15493 | } | |
15494 | ||
055e393f | 15495 | for_each_pipe(dev_priv, pipe) { |
98187836 | 15496 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 15497 | |
24929352 | 15498 | intel_sanitize_crtc(crtc); |
6e3c9717 ACO |
15499 | intel_dump_pipe_config(crtc, crtc->config, |
15500 | "[setup_hw_state]"); | |
24929352 | 15501 | } |
9a935856 | 15502 | |
d29b2f9d ACO |
15503 | intel_modeset_update_connector_atomic_state(dev); |
15504 | ||
35c95375 DV |
15505 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15506 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15507 | ||
2dd66ebd | 15508 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15509 | continue; |
15510 | ||
15511 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15512 | ||
2edd6443 | 15513 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15514 | pll->on = false; |
15515 | } | |
15516 | ||
602ae835 | 15517 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
6eb1a681 | 15518 | vlv_wm_get_hw_state(dev); |
602ae835 VS |
15519 | vlv_wm_sanitize(dev_priv); |
15520 | } else if (IS_GEN9(dev_priv)) { | |
3078999f | 15521 | skl_wm_get_hw_state(dev); |
602ae835 | 15522 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
243e6a44 | 15523 | ilk_wm_get_hw_state(dev); |
602ae835 | 15524 | } |
292b990e ML |
15525 | |
15526 | for_each_intel_crtc(dev, crtc) { | |
d8fc70b7 | 15527 | u64 put_domains; |
292b990e | 15528 | |
74bff5f9 | 15529 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15530 | if (WARN_ON(put_domains)) |
15531 | modeset_put_power_domains(dev_priv, put_domains); | |
15532 | } | |
15533 | intel_display_set_init_power(dev_priv, false); | |
010cf73d | 15534 | |
8d8c386c ID |
15535 | intel_power_domains_verify_state(dev_priv); |
15536 | ||
010cf73d | 15537 | intel_fbc_init_pipe_state(dev_priv); |
043e9bda | 15538 | } |
7d0bc1ea | 15539 | |
043e9bda ML |
15540 | void intel_display_resume(struct drm_device *dev) |
15541 | { | |
e2c8b870 ML |
15542 | struct drm_i915_private *dev_priv = to_i915(dev); |
15543 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15544 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15545 | int ret; |
f30da187 | 15546 | |
e2c8b870 | 15547 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
15548 | if (state) |
15549 | state->acquire_ctx = &ctx; | |
043e9bda | 15550 | |
ea49c9ac ML |
15551 | /* |
15552 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15553 | * won't be taken. Unfortunately some probed state like | |
15554 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15555 | * it here for now. | |
15556 | */ | |
15557 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 15558 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15559 | |
73974893 ML |
15560 | while (1) { |
15561 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
15562 | if (ret != -EDEADLK) | |
15563 | break; | |
043e9bda | 15564 | |
e2c8b870 | 15565 | drm_modeset_backoff(&ctx); |
e2c8b870 | 15566 | } |
043e9bda | 15567 | |
73974893 ML |
15568 | if (!ret) |
15569 | ret = __intel_display_resume(dev, state); | |
15570 | ||
e2c8b870 ML |
15571 | drm_modeset_drop_locks(&ctx); |
15572 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 15573 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 15574 | |
0853695c | 15575 | if (ret) |
e2c8b870 | 15576 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
3c5e37f1 CW |
15577 | if (state) |
15578 | drm_atomic_state_put(state); | |
2c7111db CW |
15579 | } |
15580 | ||
15581 | void intel_modeset_gem_init(struct drm_device *dev) | |
15582 | { | |
dc97997a | 15583 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15584 | |
dc97997a | 15585 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15586 | |
1ee8da6d | 15587 | intel_setup_overlay(dev_priv); |
1ebaa0b9 CW |
15588 | } |
15589 | ||
15590 | int intel_connector_register(struct drm_connector *connector) | |
15591 | { | |
15592 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
15593 | int ret; | |
15594 | ||
15595 | ret = intel_backlight_device_register(intel_connector); | |
15596 | if (ret) | |
15597 | goto err; | |
15598 | ||
15599 | return 0; | |
0962c3c9 | 15600 | |
1ebaa0b9 CW |
15601 | err: |
15602 | return ret; | |
79e53945 JB |
15603 | } |
15604 | ||
c191eca1 | 15605 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 15606 | { |
e63d87c0 | 15607 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 15608 | |
e63d87c0 | 15609 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 15610 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
15611 | } |
15612 | ||
79e53945 JB |
15613 | void intel_modeset_cleanup(struct drm_device *dev) |
15614 | { | |
fac5e23e | 15615 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 15616 | |
eb955eee CW |
15617 | flush_work(&dev_priv->atomic_helper.free_work); |
15618 | WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); | |
15619 | ||
dc97997a | 15620 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 15621 | |
fd0c0642 DV |
15622 | /* |
15623 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15624 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15625 | * experience fancy races otherwise. |
15626 | */ | |
2aeb7d3a | 15627 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15628 | |
fd0c0642 DV |
15629 | /* |
15630 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15631 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15632 | */ | |
f87ea761 | 15633 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15634 | |
723bfd70 JB |
15635 | intel_unregister_dsm_handler(); |
15636 | ||
c937ab3e | 15637 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15638 | |
1630fe75 CW |
15639 | /* flush any delayed tasks or pending work */ |
15640 | flush_scheduled_work(); | |
15641 | ||
79e53945 | 15642 | drm_mode_config_cleanup(dev); |
4d7bb011 | 15643 | |
1ee8da6d | 15644 | intel_cleanup_overlay(dev_priv); |
ae48434c | 15645 | |
dc97997a | 15646 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 15647 | |
40196446 | 15648 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
15649 | } |
15650 | ||
df0e9248 CW |
15651 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15652 | struct intel_encoder *encoder) | |
15653 | { | |
15654 | connector->encoder = encoder; | |
15655 | drm_mode_connector_attach_encoder(&connector->base, | |
15656 | &encoder->base); | |
79e53945 | 15657 | } |
28d52043 DA |
15658 | |
15659 | /* | |
15660 | * set vga decode state - true == enable VGA decode | |
15661 | */ | |
6315b5d3 | 15662 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 15663 | { |
6315b5d3 | 15664 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15665 | u16 gmch_ctrl; |
15666 | ||
75fa041d CW |
15667 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15668 | DRM_ERROR("failed to read control word\n"); | |
15669 | return -EIO; | |
15670 | } | |
15671 | ||
c0cc8a55 CW |
15672 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15673 | return 0; | |
15674 | ||
28d52043 DA |
15675 | if (state) |
15676 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15677 | else | |
15678 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15679 | |
15680 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15681 | DRM_ERROR("failed to write control word\n"); | |
15682 | return -EIO; | |
15683 | } | |
15684 | ||
28d52043 DA |
15685 | return 0; |
15686 | } | |
c4a1d9e4 | 15687 | |
98a2f411 CW |
15688 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
15689 | ||
c4a1d9e4 | 15690 | struct intel_display_error_state { |
ff57f1b0 PZ |
15691 | |
15692 | u32 power_well_driver; | |
15693 | ||
63b66e5b CW |
15694 | int num_transcoders; |
15695 | ||
c4a1d9e4 CW |
15696 | struct intel_cursor_error_state { |
15697 | u32 control; | |
15698 | u32 position; | |
15699 | u32 base; | |
15700 | u32 size; | |
52331309 | 15701 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15702 | |
15703 | struct intel_pipe_error_state { | |
ddf9c536 | 15704 | bool power_domain_on; |
c4a1d9e4 | 15705 | u32 source; |
f301b1e1 | 15706 | u32 stat; |
52331309 | 15707 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15708 | |
15709 | struct intel_plane_error_state { | |
15710 | u32 control; | |
15711 | u32 stride; | |
15712 | u32 size; | |
15713 | u32 pos; | |
15714 | u32 addr; | |
15715 | u32 surface; | |
15716 | u32 tile_offset; | |
52331309 | 15717 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15718 | |
15719 | struct intel_transcoder_error_state { | |
ddf9c536 | 15720 | bool power_domain_on; |
63b66e5b CW |
15721 | enum transcoder cpu_transcoder; |
15722 | ||
15723 | u32 conf; | |
15724 | ||
15725 | u32 htotal; | |
15726 | u32 hblank; | |
15727 | u32 hsync; | |
15728 | u32 vtotal; | |
15729 | u32 vblank; | |
15730 | u32 vsync; | |
15731 | } transcoder[4]; | |
c4a1d9e4 CW |
15732 | }; |
15733 | ||
15734 | struct intel_display_error_state * | |
c033666a | 15735 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 15736 | { |
c4a1d9e4 | 15737 | struct intel_display_error_state *error; |
63b66e5b CW |
15738 | int transcoders[] = { |
15739 | TRANSCODER_A, | |
15740 | TRANSCODER_B, | |
15741 | TRANSCODER_C, | |
15742 | TRANSCODER_EDP, | |
15743 | }; | |
c4a1d9e4 CW |
15744 | int i; |
15745 | ||
c033666a | 15746 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
15747 | return NULL; |
15748 | ||
9d1cb914 | 15749 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15750 | if (error == NULL) |
15751 | return NULL; | |
15752 | ||
c033666a | 15753 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
15754 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15755 | ||
055e393f | 15756 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15757 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15758 | __intel_display_power_is_enabled(dev_priv, |
15759 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15760 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15761 | continue; |
15762 | ||
5efb3e28 VS |
15763 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15764 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15765 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15766 | |
15767 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15768 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 15769 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 15770 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15771 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15772 | } | |
c033666a | 15773 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 15774 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 15775 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
15776 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
15777 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15778 | } | |
15779 | ||
c4a1d9e4 | 15780 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15781 | |
c033666a | 15782 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 15783 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15784 | } |
15785 | ||
4d1de975 | 15786 | /* Note: this does not include DSI transcoders. */ |
c033666a | 15787 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 15788 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
15789 | error->num_transcoders++; /* Account for eDP. */ |
15790 | ||
15791 | for (i = 0; i < error->num_transcoders; i++) { | |
15792 | enum transcoder cpu_transcoder = transcoders[i]; | |
15793 | ||
ddf9c536 | 15794 | error->transcoder[i].power_domain_on = |
f458ebbc | 15795 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15796 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15797 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15798 | continue; |
15799 | ||
63b66e5b CW |
15800 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15801 | ||
15802 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15803 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15804 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15805 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15806 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15807 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15808 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15809 | } |
15810 | ||
15811 | return error; | |
15812 | } | |
15813 | ||
edc3d884 MK |
15814 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15815 | ||
c4a1d9e4 | 15816 | void |
edc3d884 | 15817 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15818 | struct intel_display_error_state *error) |
15819 | { | |
5a4c6f1b | 15820 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
15821 | int i; |
15822 | ||
63b66e5b CW |
15823 | if (!error) |
15824 | return; | |
15825 | ||
b7f05d4a | 15826 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 15827 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 15828 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15829 | error->power_well_driver); |
055e393f | 15830 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15831 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 15832 | err_printf(m, " Power: %s\n", |
87ad3212 | 15833 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 15834 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15835 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15836 | |
15837 | err_printf(m, "Plane [%d]:\n", i); | |
15838 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15839 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 15840 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
15841 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15842 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15843 | } |
772c2a51 | 15844 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 15845 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 15846 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
15847 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15848 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15849 | } |
15850 | ||
edc3d884 MK |
15851 | err_printf(m, "Cursor [%d]:\n", i); |
15852 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15853 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15854 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15855 | } |
63b66e5b CW |
15856 | |
15857 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15858 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15859 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15860 | err_printf(m, " Power: %s\n", |
87ad3212 | 15861 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15862 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15863 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15864 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15865 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15866 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15867 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15868 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15869 | } | |
c4a1d9e4 | 15870 | } |
98a2f411 CW |
15871 | |
15872 | #endif |