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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
57822dc6 | 40 | #include "i915_gem_clflush.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
465c120c | 52 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 53 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
54 | DRM_FORMAT_C8, |
55 | DRM_FORMAT_RGB565, | |
465c120c | 56 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 57 | DRM_FORMAT_XRGB8888, |
465c120c MR |
58 | }; |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 61 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
62 | DRM_FORMAT_C8, |
63 | DRM_FORMAT_RGB565, | |
64 | DRM_FORMAT_XRGB8888, | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_XRGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | }; | |
69 | ||
70 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
71 | DRM_FORMAT_C8, |
72 | DRM_FORMAT_RGB565, | |
73 | DRM_FORMAT_XRGB8888, | |
465c120c | 74 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 75 | DRM_FORMAT_ARGB8888, |
465c120c MR |
76 | DRM_FORMAT_ABGR8888, |
77 | DRM_FORMAT_XRGB2101010, | |
465c120c | 78 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
79 | DRM_FORMAT_YUYV, |
80 | DRM_FORMAT_YVYU, | |
81 | DRM_FORMAT_UYVY, | |
82 | DRM_FORMAT_VYUY, | |
465c120c MR |
83 | }; |
84 | ||
3d7d6510 MR |
85 | /* Cursor formats */ |
86 | static const uint32_t intel_cursor_formats[] = { | |
87 | DRM_FORMAT_ARGB8888, | |
88 | }; | |
89 | ||
f1f644dc | 90 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
18442d08 | 92 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 93 | struct intel_crtc_state *pipe_config); |
f1f644dc | 94 | |
24dbf51a CW |
95 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
96 | struct drm_i915_gem_object *obj, | |
97 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5b18e57c DV |
98 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
99 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 100 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
102 | struct intel_link_m_n *m_n, |
103 | struct intel_link_m_n *m2_n2); | |
29407aab | 104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 106 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 107 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
d288f65f | 109 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 110 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
111 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
112 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
1c74eeaf NM |
113 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
114 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
aecd36b8 VS |
118 | static void intel_modeset_setup_hw_state(struct drm_device *dev, |
119 | struct drm_modeset_acquire_ctx *ctx); | |
2622a081 | 120 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 121 | |
d4906093 | 122 | struct intel_limit { |
4c5def93 ACO |
123 | struct { |
124 | int min, max; | |
125 | } dot, vco, n, m, m1, m2, p, p1; | |
126 | ||
127 | struct { | |
128 | int dot_limit; | |
129 | int p2_slow, p2_fast; | |
130 | } p2; | |
d4906093 | 131 | }; |
79e53945 | 132 | |
bfa7df01 | 133 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 134 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
135 | { |
136 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
137 | ||
138 | /* Obtain SKU information */ | |
139 | mutex_lock(&dev_priv->sb_lock); | |
140 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
141 | CCK_FUSE_HPLL_FREQ_MASK; | |
142 | mutex_unlock(&dev_priv->sb_lock); | |
143 | ||
144 | return vco_freq[hpll_freq] * 1000; | |
145 | } | |
146 | ||
c30fec65 VS |
147 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
148 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
149 | { |
150 | u32 val; | |
151 | int divider; | |
152 | ||
bfa7df01 VS |
153 | mutex_lock(&dev_priv->sb_lock); |
154 | val = vlv_cck_read(dev_priv, reg); | |
155 | mutex_unlock(&dev_priv->sb_lock); | |
156 | ||
157 | divider = val & CCK_FREQUENCY_VALUES; | |
158 | ||
159 | WARN((val & CCK_FREQUENCY_STATUS) != | |
160 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
161 | "%s change in progress\n", name); | |
162 | ||
c30fec65 VS |
163 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
164 | } | |
165 | ||
7ff89ca2 VS |
166 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
167 | const char *name, u32 reg) | |
c30fec65 VS |
168 | { |
169 | if (dev_priv->hpll_freq == 0) | |
49cd97a3 | 170 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 VS |
171 | |
172 | return vlv_get_cck_clock(dev_priv, name, reg, | |
173 | dev_priv->hpll_freq); | |
bfa7df01 VS |
174 | } |
175 | ||
bfa7df01 VS |
176 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
177 | { | |
666a4537 | 178 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
179 | return; |
180 | ||
181 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
182 | CCK_CZ_CLOCK_CONTROL); | |
183 | ||
184 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
185 | } | |
186 | ||
021357ac | 187 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
188 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
189 | const struct intel_crtc_state *pipe_config) | |
021357ac | 190 | { |
21a727b3 VS |
191 | if (HAS_DDI(dev_priv)) |
192 | return pipe_config->port_clock; /* SPLL */ | |
193 | else if (IS_GEN5(dev_priv)) | |
194 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 195 | else |
21a727b3 | 196 | return 270000; |
021357ac CW |
197 | } |
198 | ||
1b6f4958 | 199 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 200 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 201 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 202 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
203 | .m = { .min = 96, .max = 140 }, |
204 | .m1 = { .min = 18, .max = 26 }, | |
205 | .m2 = { .min = 6, .max = 16 }, | |
206 | .p = { .min = 4, .max = 128 }, | |
207 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
208 | .p2 = { .dot_limit = 165000, |
209 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
210 | }; |
211 | ||
1b6f4958 | 212 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 213 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 214 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 215 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
216 | .m = { .min = 96, .max = 140 }, |
217 | .m1 = { .min = 18, .max = 26 }, | |
218 | .m2 = { .min = 6, .max = 16 }, | |
219 | .p = { .min = 4, .max = 128 }, | |
220 | .p1 = { .min = 2, .max = 33 }, | |
221 | .p2 = { .dot_limit = 165000, | |
222 | .p2_slow = 4, .p2_fast = 4 }, | |
223 | }; | |
224 | ||
1b6f4958 | 225 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 226 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 227 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 228 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
229 | .m = { .min = 96, .max = 140 }, |
230 | .m1 = { .min = 18, .max = 26 }, | |
231 | .m2 = { .min = 6, .max = 16 }, | |
232 | .p = { .min = 4, .max = 128 }, | |
233 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
234 | .p2 = { .dot_limit = 165000, |
235 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 236 | }; |
273e27ca | 237 | |
1b6f4958 | 238 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
239 | .dot = { .min = 20000, .max = 400000 }, |
240 | .vco = { .min = 1400000, .max = 2800000 }, | |
241 | .n = { .min = 1, .max = 6 }, | |
242 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
243 | .m1 = { .min = 8, .max = 18 }, |
244 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
245 | .p = { .min = 5, .max = 80 }, |
246 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
247 | .p2 = { .dot_limit = 200000, |
248 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
249 | }; |
250 | ||
1b6f4958 | 251 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
252 | .dot = { .min = 20000, .max = 400000 }, |
253 | .vco = { .min = 1400000, .max = 2800000 }, | |
254 | .n = { .min = 1, .max = 6 }, | |
255 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
256 | .m1 = { .min = 8, .max = 18 }, |
257 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
258 | .p = { .min = 7, .max = 98 }, |
259 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
260 | .p2 = { .dot_limit = 112000, |
261 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
262 | }; |
263 | ||
273e27ca | 264 | |
1b6f4958 | 265 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
266 | .dot = { .min = 25000, .max = 270000 }, |
267 | .vco = { .min = 1750000, .max = 3500000}, | |
268 | .n = { .min = 1, .max = 4 }, | |
269 | .m = { .min = 104, .max = 138 }, | |
270 | .m1 = { .min = 17, .max = 23 }, | |
271 | .m2 = { .min = 5, .max = 11 }, | |
272 | .p = { .min = 10, .max = 30 }, | |
273 | .p1 = { .min = 1, .max = 3}, | |
274 | .p2 = { .dot_limit = 270000, | |
275 | .p2_slow = 10, | |
276 | .p2_fast = 10 | |
044c7c41 | 277 | }, |
e4b36699 KP |
278 | }; |
279 | ||
1b6f4958 | 280 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
281 | .dot = { .min = 22000, .max = 400000 }, |
282 | .vco = { .min = 1750000, .max = 3500000}, | |
283 | .n = { .min = 1, .max = 4 }, | |
284 | .m = { .min = 104, .max = 138 }, | |
285 | .m1 = { .min = 16, .max = 23 }, | |
286 | .m2 = { .min = 5, .max = 11 }, | |
287 | .p = { .min = 5, .max = 80 }, | |
288 | .p1 = { .min = 1, .max = 8}, | |
289 | .p2 = { .dot_limit = 165000, | |
290 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
291 | }; |
292 | ||
1b6f4958 | 293 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
294 | .dot = { .min = 20000, .max = 115000 }, |
295 | .vco = { .min = 1750000, .max = 3500000 }, | |
296 | .n = { .min = 1, .max = 3 }, | |
297 | .m = { .min = 104, .max = 138 }, | |
298 | .m1 = { .min = 17, .max = 23 }, | |
299 | .m2 = { .min = 5, .max = 11 }, | |
300 | .p = { .min = 28, .max = 112 }, | |
301 | .p1 = { .min = 2, .max = 8 }, | |
302 | .p2 = { .dot_limit = 0, | |
303 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 304 | }, |
e4b36699 KP |
305 | }; |
306 | ||
1b6f4958 | 307 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
308 | .dot = { .min = 80000, .max = 224000 }, |
309 | .vco = { .min = 1750000, .max = 3500000 }, | |
310 | .n = { .min = 1, .max = 3 }, | |
311 | .m = { .min = 104, .max = 138 }, | |
312 | .m1 = { .min = 17, .max = 23 }, | |
313 | .m2 = { .min = 5, .max = 11 }, | |
314 | .p = { .min = 14, .max = 42 }, | |
315 | .p1 = { .min = 2, .max = 6 }, | |
316 | .p2 = { .dot_limit = 0, | |
317 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 318 | }, |
e4b36699 KP |
319 | }; |
320 | ||
1b6f4958 | 321 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
322 | .dot = { .min = 20000, .max = 400000}, |
323 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 324 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
325 | .n = { .min = 3, .max = 6 }, |
326 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 327 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
328 | .m1 = { .min = 0, .max = 0 }, |
329 | .m2 = { .min = 0, .max = 254 }, | |
330 | .p = { .min = 5, .max = 80 }, | |
331 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
332 | .p2 = { .dot_limit = 200000, |
333 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
334 | }; |
335 | ||
1b6f4958 | 336 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
337 | .dot = { .min = 20000, .max = 400000 }, |
338 | .vco = { .min = 1700000, .max = 3500000 }, | |
339 | .n = { .min = 3, .max = 6 }, | |
340 | .m = { .min = 2, .max = 256 }, | |
341 | .m1 = { .min = 0, .max = 0 }, | |
342 | .m2 = { .min = 0, .max = 254 }, | |
343 | .p = { .min = 7, .max = 112 }, | |
344 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
345 | .p2 = { .dot_limit = 112000, |
346 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
347 | }; |
348 | ||
273e27ca EA |
349 | /* Ironlake / Sandybridge |
350 | * | |
351 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
352 | * the range value for them is (actual_value - 2). | |
353 | */ | |
1b6f4958 | 354 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
355 | .dot = { .min = 25000, .max = 350000 }, |
356 | .vco = { .min = 1760000, .max = 3510000 }, | |
357 | .n = { .min = 1, .max = 5 }, | |
358 | .m = { .min = 79, .max = 127 }, | |
359 | .m1 = { .min = 12, .max = 22 }, | |
360 | .m2 = { .min = 5, .max = 9 }, | |
361 | .p = { .min = 5, .max = 80 }, | |
362 | .p1 = { .min = 1, .max = 8 }, | |
363 | .p2 = { .dot_limit = 225000, | |
364 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
365 | }; |
366 | ||
1b6f4958 | 367 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
368 | .dot = { .min = 25000, .max = 350000 }, |
369 | .vco = { .min = 1760000, .max = 3510000 }, | |
370 | .n = { .min = 1, .max = 3 }, | |
371 | .m = { .min = 79, .max = 118 }, | |
372 | .m1 = { .min = 12, .max = 22 }, | |
373 | .m2 = { .min = 5, .max = 9 }, | |
374 | .p = { .min = 28, .max = 112 }, | |
375 | .p1 = { .min = 2, .max = 8 }, | |
376 | .p2 = { .dot_limit = 225000, | |
377 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
378 | }; |
379 | ||
1b6f4958 | 380 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
381 | .dot = { .min = 25000, .max = 350000 }, |
382 | .vco = { .min = 1760000, .max = 3510000 }, | |
383 | .n = { .min = 1, .max = 3 }, | |
384 | .m = { .min = 79, .max = 127 }, | |
385 | .m1 = { .min = 12, .max = 22 }, | |
386 | .m2 = { .min = 5, .max = 9 }, | |
387 | .p = { .min = 14, .max = 56 }, | |
388 | .p1 = { .min = 2, .max = 8 }, | |
389 | .p2 = { .dot_limit = 225000, | |
390 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
391 | }; |
392 | ||
273e27ca | 393 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 394 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
395 | .dot = { .min = 25000, .max = 350000 }, |
396 | .vco = { .min = 1760000, .max = 3510000 }, | |
397 | .n = { .min = 1, .max = 2 }, | |
398 | .m = { .min = 79, .max = 126 }, | |
399 | .m1 = { .min = 12, .max = 22 }, | |
400 | .m2 = { .min = 5, .max = 9 }, | |
401 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 402 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
403 | .p2 = { .dot_limit = 225000, |
404 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
405 | }; |
406 | ||
1b6f4958 | 407 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
408 | .dot = { .min = 25000, .max = 350000 }, |
409 | .vco = { .min = 1760000, .max = 3510000 }, | |
410 | .n = { .min = 1, .max = 3 }, | |
411 | .m = { .min = 79, .max = 126 }, | |
412 | .m1 = { .min = 12, .max = 22 }, | |
413 | .m2 = { .min = 5, .max = 9 }, | |
414 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 415 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
416 | .p2 = { .dot_limit = 225000, |
417 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
418 | }; |
419 | ||
1b6f4958 | 420 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
421 | /* |
422 | * These are the data rate limits (measured in fast clocks) | |
423 | * since those are the strictest limits we have. The fast | |
424 | * clock and actual rate limits are more relaxed, so checking | |
425 | * them would make no difference. | |
426 | */ | |
427 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 428 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 429 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
430 | .m1 = { .min = 2, .max = 3 }, |
431 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 432 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 433 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
434 | }; |
435 | ||
1b6f4958 | 436 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
437 | /* |
438 | * These are the data rate limits (measured in fast clocks) | |
439 | * since those are the strictest limits we have. The fast | |
440 | * clock and actual rate limits are more relaxed, so checking | |
441 | * them would make no difference. | |
442 | */ | |
443 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 444 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
445 | .n = { .min = 1, .max = 1 }, |
446 | .m1 = { .min = 2, .max = 2 }, | |
447 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
448 | .p1 = { .min = 2, .max = 4 }, | |
449 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
450 | }; | |
451 | ||
1b6f4958 | 452 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
453 | /* FIXME: find real dot limits */ |
454 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 455 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
456 | .n = { .min = 1, .max = 1 }, |
457 | .m1 = { .min = 2, .max = 2 }, | |
458 | /* FIXME: find real m2 limits */ | |
459 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
460 | .p1 = { .min = 2, .max = 4 }, | |
461 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
462 | }; | |
463 | ||
cdba954e ACO |
464 | static bool |
465 | needs_modeset(struct drm_crtc_state *state) | |
466 | { | |
fc596660 | 467 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
468 | } |
469 | ||
dccbea3b ID |
470 | /* |
471 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
472 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
473 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
474 | * The helpers' return value is the rate of the clock that is fed to the | |
475 | * display engine's pipe which can be the above fast dot clock rate or a | |
476 | * divided-down version of it. | |
477 | */ | |
f2b115e6 | 478 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 479 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 480 | { |
2177832f SL |
481 | clock->m = clock->m2 + 2; |
482 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 483 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 484 | return 0; |
fb03ac01 VS |
485 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
486 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
487 | |
488 | return clock->dot; | |
2177832f SL |
489 | } |
490 | ||
7429e9d4 DV |
491 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
492 | { | |
493 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
494 | } | |
495 | ||
9e2c8475 | 496 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 497 | { |
7429e9d4 | 498 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 499 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 500 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 501 | return 0; |
fb03ac01 VS |
502 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
503 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
504 | |
505 | return clock->dot; | |
79e53945 JB |
506 | } |
507 | ||
9e2c8475 | 508 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
509 | { |
510 | clock->m = clock->m1 * clock->m2; | |
511 | clock->p = clock->p1 * clock->p2; | |
512 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 513 | return 0; |
589eca67 ID |
514 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
515 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
516 | |
517 | return clock->dot / 5; | |
589eca67 ID |
518 | } |
519 | ||
9e2c8475 | 520 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
521 | { |
522 | clock->m = clock->m1 * clock->m2; | |
523 | clock->p = clock->p1 * clock->p2; | |
524 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 525 | return 0; |
ef9348c8 CML |
526 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
527 | clock->n << 22); | |
528 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
529 | |
530 | return clock->dot / 5; | |
ef9348c8 CML |
531 | } |
532 | ||
7c04d1d9 | 533 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
534 | /** |
535 | * Returns whether the given set of divisors are valid for a given refclk with | |
536 | * the given connectors. | |
537 | */ | |
538 | ||
e2d214ae | 539 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 540 | const struct intel_limit *limit, |
9e2c8475 | 541 | const struct dpll *clock) |
79e53945 | 542 | { |
f01b7962 VS |
543 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
544 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 545 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 546 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 547 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 548 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 549 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 550 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 551 | |
e2d214ae | 552 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 553 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
554 | if (clock->m1 <= clock->m2) |
555 | INTELPllInvalid("m1 <= m2\n"); | |
556 | ||
e2d214ae | 557 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 558 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
559 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
560 | INTELPllInvalid("p out of range\n"); | |
561 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
562 | INTELPllInvalid("m out of range\n"); | |
563 | } | |
564 | ||
79e53945 | 565 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 566 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
567 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
568 | * connector, etc., rather than just a single range. | |
569 | */ | |
570 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 571 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
572 | |
573 | return true; | |
574 | } | |
575 | ||
3b1429d9 | 576 | static int |
1b6f4958 | 577 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
578 | const struct intel_crtc_state *crtc_state, |
579 | int target) | |
79e53945 | 580 | { |
3b1429d9 | 581 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 582 | |
2d84d2b3 | 583 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 584 | /* |
a210b028 DV |
585 | * For LVDS just rely on its current settings for dual-channel. |
586 | * We haven't figured out how to reliably set up different | |
587 | * single/dual channel state, if we even can. | |
79e53945 | 588 | */ |
1974cad0 | 589 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 590 | return limit->p2.p2_fast; |
79e53945 | 591 | else |
3b1429d9 | 592 | return limit->p2.p2_slow; |
79e53945 JB |
593 | } else { |
594 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 595 | return limit->p2.p2_slow; |
79e53945 | 596 | else |
3b1429d9 | 597 | return limit->p2.p2_fast; |
79e53945 | 598 | } |
3b1429d9 VS |
599 | } |
600 | ||
70e8aa21 ACO |
601 | /* |
602 | * Returns a set of divisors for the desired target clock with the given | |
603 | * refclk, or FALSE. The returned values represent the clock equation: | |
604 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
605 | * | |
606 | * Target and reference clocks are specified in kHz. | |
607 | * | |
608 | * If match_clock is provided, then best_clock P divider must match the P | |
609 | * divider from @match_clock used for LVDS downclocking. | |
610 | */ | |
3b1429d9 | 611 | static bool |
1b6f4958 | 612 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 613 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
614 | int target, int refclk, struct dpll *match_clock, |
615 | struct dpll *best_clock) | |
3b1429d9 VS |
616 | { |
617 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 618 | struct dpll clock; |
3b1429d9 | 619 | int err = target; |
79e53945 | 620 | |
0206e353 | 621 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 622 | |
3b1429d9 VS |
623 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
624 | ||
42158660 ZY |
625 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
626 | clock.m1++) { | |
627 | for (clock.m2 = limit->m2.min; | |
628 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 629 | if (clock.m2 >= clock.m1) |
42158660 ZY |
630 | break; |
631 | for (clock.n = limit->n.min; | |
632 | clock.n <= limit->n.max; clock.n++) { | |
633 | for (clock.p1 = limit->p1.min; | |
634 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
635 | int this_err; |
636 | ||
dccbea3b | 637 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
638 | if (!intel_PLL_is_valid(to_i915(dev), |
639 | limit, | |
ac58c3f0 DV |
640 | &clock)) |
641 | continue; | |
642 | if (match_clock && | |
643 | clock.p != match_clock->p) | |
644 | continue; | |
645 | ||
646 | this_err = abs(clock.dot - target); | |
647 | if (this_err < err) { | |
648 | *best_clock = clock; | |
649 | err = this_err; | |
650 | } | |
651 | } | |
652 | } | |
653 | } | |
654 | } | |
655 | ||
656 | return (err != target); | |
657 | } | |
658 | ||
70e8aa21 ACO |
659 | /* |
660 | * Returns a set of divisors for the desired target clock with the given | |
661 | * refclk, or FALSE. The returned values represent the clock equation: | |
662 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
663 | * | |
664 | * Target and reference clocks are specified in kHz. | |
665 | * | |
666 | * If match_clock is provided, then best_clock P divider must match the P | |
667 | * divider from @match_clock used for LVDS downclocking. | |
668 | */ | |
ac58c3f0 | 669 | static bool |
1b6f4958 | 670 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 671 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
672 | int target, int refclk, struct dpll *match_clock, |
673 | struct dpll *best_clock) | |
79e53945 | 674 | { |
3b1429d9 | 675 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 676 | struct dpll clock; |
79e53945 JB |
677 | int err = target; |
678 | ||
0206e353 | 679 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 680 | |
3b1429d9 VS |
681 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
682 | ||
42158660 ZY |
683 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
684 | clock.m1++) { | |
685 | for (clock.m2 = limit->m2.min; | |
686 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
687 | for (clock.n = limit->n.min; |
688 | clock.n <= limit->n.max; clock.n++) { | |
689 | for (clock.p1 = limit->p1.min; | |
690 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
691 | int this_err; |
692 | ||
dccbea3b | 693 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
694 | if (!intel_PLL_is_valid(to_i915(dev), |
695 | limit, | |
1b894b59 | 696 | &clock)) |
79e53945 | 697 | continue; |
cec2f356 SP |
698 | if (match_clock && |
699 | clock.p != match_clock->p) | |
700 | continue; | |
79e53945 JB |
701 | |
702 | this_err = abs(clock.dot - target); | |
703 | if (this_err < err) { | |
704 | *best_clock = clock; | |
705 | err = this_err; | |
706 | } | |
707 | } | |
708 | } | |
709 | } | |
710 | } | |
711 | ||
712 | return (err != target); | |
713 | } | |
714 | ||
997c030c ACO |
715 | /* |
716 | * Returns a set of divisors for the desired target clock with the given | |
717 | * refclk, or FALSE. The returned values represent the clock equation: | |
718 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
719 | * |
720 | * Target and reference clocks are specified in kHz. | |
721 | * | |
722 | * If match_clock is provided, then best_clock P divider must match the P | |
723 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 724 | */ |
d4906093 | 725 | static bool |
1b6f4958 | 726 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 727 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
728 | int target, int refclk, struct dpll *match_clock, |
729 | struct dpll *best_clock) | |
d4906093 | 730 | { |
3b1429d9 | 731 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 732 | struct dpll clock; |
d4906093 | 733 | int max_n; |
3b1429d9 | 734 | bool found = false; |
6ba770dc AJ |
735 | /* approximately equals target * 0.00585 */ |
736 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
737 | |
738 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
739 | |
740 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
741 | ||
d4906093 | 742 | max_n = limit->n.max; |
f77f13e2 | 743 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 744 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 745 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
746 | for (clock.m1 = limit->m1.max; |
747 | clock.m1 >= limit->m1.min; clock.m1--) { | |
748 | for (clock.m2 = limit->m2.max; | |
749 | clock.m2 >= limit->m2.min; clock.m2--) { | |
750 | for (clock.p1 = limit->p1.max; | |
751 | clock.p1 >= limit->p1.min; clock.p1--) { | |
752 | int this_err; | |
753 | ||
dccbea3b | 754 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
755 | if (!intel_PLL_is_valid(to_i915(dev), |
756 | limit, | |
1b894b59 | 757 | &clock)) |
d4906093 | 758 | continue; |
1b894b59 CW |
759 | |
760 | this_err = abs(clock.dot - target); | |
d4906093 ML |
761 | if (this_err < err_most) { |
762 | *best_clock = clock; | |
763 | err_most = this_err; | |
764 | max_n = clock.n; | |
765 | found = true; | |
766 | } | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
2c07245f ZW |
771 | return found; |
772 | } | |
773 | ||
d5dd62bd ID |
774 | /* |
775 | * Check if the calculated PLL configuration is more optimal compared to the | |
776 | * best configuration and error found so far. Return the calculated error. | |
777 | */ | |
778 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
779 | const struct dpll *calculated_clock, |
780 | const struct dpll *best_clock, | |
d5dd62bd ID |
781 | unsigned int best_error_ppm, |
782 | unsigned int *error_ppm) | |
783 | { | |
9ca3ba01 ID |
784 | /* |
785 | * For CHV ignore the error and consider only the P value. | |
786 | * Prefer a bigger P value based on HW requirements. | |
787 | */ | |
920a14b2 | 788 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
789 | *error_ppm = 0; |
790 | ||
791 | return calculated_clock->p > best_clock->p; | |
792 | } | |
793 | ||
24be4e46 ID |
794 | if (WARN_ON_ONCE(!target_freq)) |
795 | return false; | |
796 | ||
d5dd62bd ID |
797 | *error_ppm = div_u64(1000000ULL * |
798 | abs(target_freq - calculated_clock->dot), | |
799 | target_freq); | |
800 | /* | |
801 | * Prefer a better P value over a better (smaller) error if the error | |
802 | * is small. Ensure this preference for future configurations too by | |
803 | * setting the error to 0. | |
804 | */ | |
805 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
806 | *error_ppm = 0; | |
807 | ||
808 | return true; | |
809 | } | |
810 | ||
811 | return *error_ppm + 10 < best_error_ppm; | |
812 | } | |
813 | ||
65b3d6a9 ACO |
814 | /* |
815 | * Returns a set of divisors for the desired target clock with the given | |
816 | * refclk, or FALSE. The returned values represent the clock equation: | |
817 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
818 | */ | |
a0c4da24 | 819 | static bool |
1b6f4958 | 820 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 821 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
822 | int target, int refclk, struct dpll *match_clock, |
823 | struct dpll *best_clock) | |
a0c4da24 | 824 | { |
a93e255f | 825 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 826 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 827 | struct dpll clock; |
69e4f900 | 828 | unsigned int bestppm = 1000000; |
27e639bf VS |
829 | /* min update 19.2 MHz */ |
830 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 831 | bool found = false; |
a0c4da24 | 832 | |
6b4bf1c4 VS |
833 | target *= 5; /* fast clock */ |
834 | ||
835 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
836 | |
837 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 838 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 839 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 840 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 841 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 842 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 843 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 844 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 845 | unsigned int ppm; |
69e4f900 | 846 | |
6b4bf1c4 VS |
847 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
848 | refclk * clock.m1); | |
849 | ||
dccbea3b | 850 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 851 | |
e2d214ae TU |
852 | if (!intel_PLL_is_valid(to_i915(dev), |
853 | limit, | |
f01b7962 | 854 | &clock)) |
43b0ac53 VS |
855 | continue; |
856 | ||
d5dd62bd ID |
857 | if (!vlv_PLL_is_optimal(dev, target, |
858 | &clock, | |
859 | best_clock, | |
860 | bestppm, &ppm)) | |
861 | continue; | |
6b4bf1c4 | 862 | |
d5dd62bd ID |
863 | *best_clock = clock; |
864 | bestppm = ppm; | |
865 | found = true; | |
a0c4da24 JB |
866 | } |
867 | } | |
868 | } | |
869 | } | |
a0c4da24 | 870 | |
49e497ef | 871 | return found; |
a0c4da24 | 872 | } |
a4fc5ed6 | 873 | |
65b3d6a9 ACO |
874 | /* |
875 | * Returns a set of divisors for the desired target clock with the given | |
876 | * refclk, or FALSE. The returned values represent the clock equation: | |
877 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
878 | */ | |
ef9348c8 | 879 | static bool |
1b6f4958 | 880 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 881 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
882 | int target, int refclk, struct dpll *match_clock, |
883 | struct dpll *best_clock) | |
ef9348c8 | 884 | { |
a93e255f | 885 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 886 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 887 | unsigned int best_error_ppm; |
9e2c8475 | 888 | struct dpll clock; |
ef9348c8 CML |
889 | uint64_t m2; |
890 | int found = false; | |
891 | ||
892 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 893 | best_error_ppm = 1000000; |
ef9348c8 CML |
894 | |
895 | /* | |
896 | * Based on hardware doc, the n always set to 1, and m1 always | |
897 | * set to 2. If requires to support 200Mhz refclk, we need to | |
898 | * revisit this because n may not 1 anymore. | |
899 | */ | |
900 | clock.n = 1, clock.m1 = 2; | |
901 | target *= 5; /* fast clock */ | |
902 | ||
903 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
904 | for (clock.p2 = limit->p2.p2_fast; | |
905 | clock.p2 >= limit->p2.p2_slow; | |
906 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 907 | unsigned int error_ppm; |
ef9348c8 CML |
908 | |
909 | clock.p = clock.p1 * clock.p2; | |
910 | ||
911 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
912 | clock.n) << 22, refclk * clock.m1); | |
913 | ||
914 | if (m2 > INT_MAX/clock.m1) | |
915 | continue; | |
916 | ||
917 | clock.m2 = m2; | |
918 | ||
dccbea3b | 919 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 920 | |
e2d214ae | 921 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
922 | continue; |
923 | ||
9ca3ba01 ID |
924 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
925 | best_error_ppm, &error_ppm)) | |
926 | continue; | |
927 | ||
928 | *best_clock = clock; | |
929 | best_error_ppm = error_ppm; | |
930 | found = true; | |
ef9348c8 CML |
931 | } |
932 | } | |
933 | ||
934 | return found; | |
935 | } | |
936 | ||
5ab7b0b7 | 937 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 938 | struct dpll *best_clock) |
5ab7b0b7 | 939 | { |
65b3d6a9 | 940 | int refclk = 100000; |
1b6f4958 | 941 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 942 | |
65b3d6a9 | 943 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
944 | target_clock, refclk, NULL, best_clock); |
945 | } | |
946 | ||
525b9311 | 947 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 948 | { |
20ddf665 VS |
949 | /* Be paranoid as we can arrive here with only partial |
950 | * state retrieved from the hardware during setup. | |
951 | * | |
241bfc38 | 952 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
953 | * as Haswell has gained clock readout/fastboot support. |
954 | * | |
66e514c1 | 955 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 956 | * properly reconstruct framebuffers. |
c3d1f436 MR |
957 | * |
958 | * FIXME: The intel_crtc->active here should be switched to | |
959 | * crtc->state->active once we have proper CRTC states wired up | |
960 | * for atomic. | |
20ddf665 | 961 | */ |
525b9311 VS |
962 | return crtc->active && crtc->base.primary->state->fb && |
963 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
964 | } |
965 | ||
a5c961d1 PZ |
966 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
967 | enum pipe pipe) | |
968 | { | |
98187836 | 969 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 970 | |
e2af48c6 | 971 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
972 | } |
973 | ||
6315b5d3 | 974 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 975 | { |
f0f59a00 | 976 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
977 | u32 line1, line2; |
978 | u32 line_mask; | |
979 | ||
5db94019 | 980 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
981 | line_mask = DSL_LINEMASK_GEN2; |
982 | else | |
983 | line_mask = DSL_LINEMASK_GEN3; | |
984 | ||
985 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 986 | msleep(5); |
fbf49ea2 VS |
987 | line2 = I915_READ(reg) & line_mask; |
988 | ||
989 | return line1 == line2; | |
990 | } | |
991 | ||
ab7ad7f6 KP |
992 | /* |
993 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 994 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
995 | * |
996 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
997 | * spinning on the vblank interrupt status bit, since we won't actually | |
998 | * see an interrupt when the pipe is disabled. | |
999 | * | |
ab7ad7f6 KP |
1000 | * On Gen4 and above: |
1001 | * wait for the pipe register state bit to turn off | |
1002 | * | |
1003 | * Otherwise: | |
1004 | * wait for the display line value to settle (it usually | |
1005 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1006 | * |
9d0498a2 | 1007 | */ |
575f7ab7 | 1008 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1009 | { |
6315b5d3 | 1010 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1011 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1012 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1013 | |
6315b5d3 | 1014 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1015 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1016 | |
1017 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1018 | if (intel_wait_for_register(dev_priv, |
1019 | reg, I965_PIPECONF_ACTIVE, 0, | |
1020 | 100)) | |
284637d9 | 1021 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1022 | } else { |
ab7ad7f6 | 1023 | /* Wait for the display line to settle */ |
6315b5d3 | 1024 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1025 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1026 | } |
79e53945 JB |
1027 | } |
1028 | ||
b24e7179 | 1029 | /* Only for pre-ILK configs */ |
55607e8a DV |
1030 | void assert_pll(struct drm_i915_private *dev_priv, |
1031 | enum pipe pipe, bool state) | |
b24e7179 | 1032 | { |
b24e7179 JB |
1033 | u32 val; |
1034 | bool cur_state; | |
1035 | ||
649636ef | 1036 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1037 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1038 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1039 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1040 | onoff(state), onoff(cur_state)); |
b24e7179 | 1041 | } |
b24e7179 | 1042 | |
23538ef1 | 1043 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1044 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1045 | { |
1046 | u32 val; | |
1047 | bool cur_state; | |
1048 | ||
a580516d | 1049 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1050 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1051 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1052 | |
1053 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1054 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1055 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1056 | onoff(state), onoff(cur_state)); |
23538ef1 | 1057 | } |
23538ef1 | 1058 | |
040484af JB |
1059 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1060 | enum pipe pipe, bool state) | |
1061 | { | |
040484af | 1062 | bool cur_state; |
ad80a810 PZ |
1063 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1064 | pipe); | |
040484af | 1065 | |
2d1fe073 | 1066 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1067 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1068 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1069 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1070 | } else { |
649636ef | 1071 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1072 | cur_state = !!(val & FDI_TX_ENABLE); |
1073 | } | |
e2c719b7 | 1074 | I915_STATE_WARN(cur_state != state, |
040484af | 1075 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1076 | onoff(state), onoff(cur_state)); |
040484af JB |
1077 | } |
1078 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1079 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1080 | ||
1081 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1082 | enum pipe pipe, bool state) | |
1083 | { | |
040484af JB |
1084 | u32 val; |
1085 | bool cur_state; | |
1086 | ||
649636ef | 1087 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1088 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1089 | I915_STATE_WARN(cur_state != state, |
040484af | 1090 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1091 | onoff(state), onoff(cur_state)); |
040484af JB |
1092 | } |
1093 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1094 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1095 | ||
1096 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1097 | enum pipe pipe) | |
1098 | { | |
040484af JB |
1099 | u32 val; |
1100 | ||
1101 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1102 | if (IS_GEN5(dev_priv)) |
040484af JB |
1103 | return; |
1104 | ||
bf507ef7 | 1105 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1106 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1107 | return; |
1108 | ||
649636ef | 1109 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1110 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1111 | } |
1112 | ||
55607e8a DV |
1113 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1114 | enum pipe pipe, bool state) | |
040484af | 1115 | { |
040484af | 1116 | u32 val; |
55607e8a | 1117 | bool cur_state; |
040484af | 1118 | |
649636ef | 1119 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1120 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1121 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1122 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1123 | onoff(state), onoff(cur_state)); |
040484af JB |
1124 | } |
1125 | ||
4f8036a2 | 1126 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1127 | { |
f0f59a00 | 1128 | i915_reg_t pp_reg; |
ea0760cf JB |
1129 | u32 val; |
1130 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1131 | bool locked = true; |
ea0760cf | 1132 | |
4f8036a2 | 1133 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1134 | return; |
1135 | ||
4f8036a2 | 1136 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1137 | u32 port_sel; |
1138 | ||
44cb734c ID |
1139 | pp_reg = PP_CONTROL(0); |
1140 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1141 | |
1142 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1143 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1144 | panel_pipe = PIPE_B; | |
1145 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1146 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1147 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1148 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1149 | panel_pipe = pipe; |
ea0760cf | 1150 | } else { |
44cb734c | 1151 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1152 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1153 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1154 | } |
1155 | ||
1156 | val = I915_READ(pp_reg); | |
1157 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1158 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1159 | locked = false; |
1160 | ||
e2c719b7 | 1161 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1162 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1163 | pipe_name(pipe)); |
ea0760cf JB |
1164 | } |
1165 | ||
93ce0ba6 JN |
1166 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1167 | enum pipe pipe, bool state) | |
1168 | { | |
93ce0ba6 JN |
1169 | bool cur_state; |
1170 | ||
2a307c2e | 1171 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1172 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1173 | else |
5efb3e28 | 1174 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1175 | |
e2c719b7 | 1176 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1177 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1178 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1179 | } |
1180 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1181 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1182 | ||
b840d907 JB |
1183 | void assert_pipe(struct drm_i915_private *dev_priv, |
1184 | enum pipe pipe, bool state) | |
b24e7179 | 1185 | { |
63d7bbe9 | 1186 | bool cur_state; |
702e7a56 PZ |
1187 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1188 | pipe); | |
4feed0eb | 1189 | enum intel_display_power_domain power_domain; |
b24e7179 | 1190 | |
e56134bc VS |
1191 | /* we keep both pipes enabled on 830 */ |
1192 | if (IS_I830(dev_priv)) | |
8e636784 DV |
1193 | state = true; |
1194 | ||
4feed0eb ID |
1195 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1196 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1197 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1198 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1199 | |
1200 | intel_display_power_put(dev_priv, power_domain); | |
1201 | } else { | |
1202 | cur_state = false; | |
69310161 PZ |
1203 | } |
1204 | ||
e2c719b7 | 1205 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1206 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1207 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1208 | } |
1209 | ||
931872fc CW |
1210 | static void assert_plane(struct drm_i915_private *dev_priv, |
1211 | enum plane plane, bool state) | |
b24e7179 | 1212 | { |
b24e7179 | 1213 | u32 val; |
931872fc | 1214 | bool cur_state; |
b24e7179 | 1215 | |
649636ef | 1216 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1217 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1218 | I915_STATE_WARN(cur_state != state, |
931872fc | 1219 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1220 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1221 | } |
1222 | ||
931872fc CW |
1223 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1224 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1225 | ||
b24e7179 JB |
1226 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1227 | enum pipe pipe) | |
1228 | { | |
649636ef | 1229 | int i; |
b24e7179 | 1230 | |
653e1026 | 1231 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1232 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1233 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1234 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1235 | "plane %c assertion failure, should be disabled but not\n", |
1236 | plane_name(pipe)); | |
19ec1358 | 1237 | return; |
28c05794 | 1238 | } |
19ec1358 | 1239 | |
b24e7179 | 1240 | /* Need to check both planes against the pipe */ |
055e393f | 1241 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1242 | u32 val = I915_READ(DSPCNTR(i)); |
1243 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1244 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1245 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1246 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1247 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1248 | } |
1249 | } | |
1250 | ||
19332d7a JB |
1251 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1252 | enum pipe pipe) | |
1253 | { | |
649636ef | 1254 | int sprite; |
19332d7a | 1255 | |
6315b5d3 | 1256 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1257 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1258 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1259 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1260 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1261 | sprite, pipe_name(pipe)); | |
1262 | } | |
920a14b2 | 1263 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1264 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1265 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1266 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1267 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1268 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1269 | } |
6315b5d3 | 1270 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1271 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1272 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1273 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1274 | plane_name(pipe), pipe_name(pipe)); |
ab33081a | 1275 | } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
649636ef | 1276 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1277 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1278 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1279 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1280 | } |
1281 | } | |
1282 | ||
08c71e5e VS |
1283 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1284 | { | |
e2c719b7 | 1285 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1286 | drm_crtc_vblank_put(crtc); |
1287 | } | |
1288 | ||
7abd4b35 ACO |
1289 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1290 | enum pipe pipe) | |
92f2584a | 1291 | { |
92f2584a JB |
1292 | u32 val; |
1293 | bool enabled; | |
1294 | ||
649636ef | 1295 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1296 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1297 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1298 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1299 | pipe_name(pipe)); | |
92f2584a JB |
1300 | } |
1301 | ||
4e634389 KP |
1302 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1303 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1304 | { |
1305 | if ((val & DP_PORT_EN) == 0) | |
1306 | return false; | |
1307 | ||
2d1fe073 | 1308 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1309 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1310 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1311 | return false; | |
2d1fe073 | 1312 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1313 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1314 | return false; | |
f0575e92 KP |
1315 | } else { |
1316 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1317 | return false; | |
1318 | } | |
1319 | return true; | |
1320 | } | |
1321 | ||
1519b995 KP |
1322 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1323 | enum pipe pipe, u32 val) | |
1324 | { | |
dc0fa718 | 1325 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1326 | return false; |
1327 | ||
2d1fe073 | 1328 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1329 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1330 | return false; |
2d1fe073 | 1331 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1332 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1333 | return false; | |
1519b995 | 1334 | } else { |
dc0fa718 | 1335 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1336 | return false; |
1337 | } | |
1338 | return true; | |
1339 | } | |
1340 | ||
1341 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1342 | enum pipe pipe, u32 val) | |
1343 | { | |
1344 | if ((val & LVDS_PORT_EN) == 0) | |
1345 | return false; | |
1346 | ||
2d1fe073 | 1347 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1348 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1349 | return false; | |
1350 | } else { | |
1351 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1352 | return false; | |
1353 | } | |
1354 | return true; | |
1355 | } | |
1356 | ||
1357 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1358 | enum pipe pipe, u32 val) | |
1359 | { | |
1360 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1361 | return false; | |
2d1fe073 | 1362 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1363 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1364 | return false; | |
1365 | } else { | |
1366 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1367 | return false; | |
1368 | } | |
1369 | return true; | |
1370 | } | |
1371 | ||
291906f1 | 1372 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1373 | enum pipe pipe, i915_reg_t reg, |
1374 | u32 port_sel) | |
291906f1 | 1375 | { |
47a05eca | 1376 | u32 val = I915_READ(reg); |
e2c719b7 | 1377 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1378 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1379 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1380 | |
2d1fe073 | 1381 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1382 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1383 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1384 | } |
1385 | ||
1386 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1387 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1388 | { |
47a05eca | 1389 | u32 val = I915_READ(reg); |
e2c719b7 | 1390 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1391 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1392 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1393 | |
2d1fe073 | 1394 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1395 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1396 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1397 | } |
1398 | ||
1399 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1400 | enum pipe pipe) | |
1401 | { | |
291906f1 | 1402 | u32 val; |
291906f1 | 1403 | |
f0575e92 KP |
1404 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1405 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1406 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1407 | |
649636ef | 1408 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1409 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1410 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1411 | pipe_name(pipe)); |
291906f1 | 1412 | |
649636ef | 1413 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1414 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1415 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1416 | pipe_name(pipe)); |
291906f1 | 1417 | |
e2debe91 PZ |
1418 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1419 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1420 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1421 | } |
1422 | ||
cd2d34d9 VS |
1423 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1424 | const struct intel_crtc_state *pipe_config) | |
1425 | { | |
1426 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1427 | enum pipe pipe = crtc->pipe; | |
1428 | ||
1429 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1430 | POSTING_READ(DPLL(pipe)); | |
1431 | udelay(150); | |
1432 | ||
2c30b43b CW |
1433 | if (intel_wait_for_register(dev_priv, |
1434 | DPLL(pipe), | |
1435 | DPLL_LOCK_VLV, | |
1436 | DPLL_LOCK_VLV, | |
1437 | 1)) | |
cd2d34d9 VS |
1438 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1439 | } | |
1440 | ||
d288f65f | 1441 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1442 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1443 | { |
cd2d34d9 | 1444 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1445 | enum pipe pipe = crtc->pipe; |
87442f73 | 1446 | |
8bd3f301 | 1447 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1448 | |
87442f73 | 1449 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1450 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1451 | |
cd2d34d9 VS |
1452 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1453 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1454 | |
8bd3f301 VS |
1455 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1456 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1457 | } |
1458 | ||
cd2d34d9 VS |
1459 | |
1460 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1461 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1462 | { |
cd2d34d9 | 1463 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1464 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1465 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1466 | u32 tmp; |
1467 | ||
a580516d | 1468 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1469 | |
1470 | /* Enable back the 10bit clock to display controller */ | |
1471 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1472 | tmp |= DPIO_DCLKP_EN; | |
1473 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1474 | ||
54433e91 VS |
1475 | mutex_unlock(&dev_priv->sb_lock); |
1476 | ||
9d556c99 CML |
1477 | /* |
1478 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1479 | */ | |
1480 | udelay(1); | |
1481 | ||
1482 | /* Enable PLL */ | |
d288f65f | 1483 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1484 | |
1485 | /* Check PLL is locked */ | |
6b18826a CW |
1486 | if (intel_wait_for_register(dev_priv, |
1487 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1488 | 1)) | |
9d556c99 | 1489 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1490 | } |
1491 | ||
1492 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1493 | const struct intel_crtc_state *pipe_config) | |
1494 | { | |
1495 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1496 | enum pipe pipe = crtc->pipe; | |
1497 | ||
1498 | assert_pipe_disabled(dev_priv, pipe); | |
1499 | ||
1500 | /* PLL is protected by panel, make sure we can write it */ | |
1501 | assert_panel_unlocked(dev_priv, pipe); | |
1502 | ||
1503 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1504 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1505 | |
c231775c VS |
1506 | if (pipe != PIPE_A) { |
1507 | /* | |
1508 | * WaPixelRepeatModeFixForC0:chv | |
1509 | * | |
1510 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1511 | * the value from DPLLBMD to either pipe B or C. | |
1512 | */ | |
1513 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1514 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1515 | I915_WRITE(CBR4_VLV, 0); | |
1516 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1517 | ||
1518 | /* | |
1519 | * DPLLB VGA mode also seems to cause problems. | |
1520 | * We should always have it disabled. | |
1521 | */ | |
1522 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1523 | } else { | |
1524 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1525 | POSTING_READ(DPLL_MD(pipe)); | |
1526 | } | |
9d556c99 CML |
1527 | } |
1528 | ||
6315b5d3 | 1529 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1530 | { |
1531 | struct intel_crtc *crtc; | |
1532 | int count = 0; | |
1533 | ||
6315b5d3 | 1534 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1535 | count += crtc->base.state->active && |
2d84d2b3 VS |
1536 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1537 | } | |
1c4e0274 VS |
1538 | |
1539 | return count; | |
1540 | } | |
1541 | ||
66e3d5c0 | 1542 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1543 | { |
6315b5d3 | 1544 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1545 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1546 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
bb408dd2 | 1547 | int i; |
63d7bbe9 | 1548 | |
66e3d5c0 | 1549 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1550 | |
63d7bbe9 | 1551 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1552 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1553 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1554 | |
1c4e0274 | 1555 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1556 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1557 | /* |
1558 | * It appears to be important that we don't enable this | |
1559 | * for the current pipe before otherwise configuring the | |
1560 | * PLL. No idea how this should be handled if multiple | |
1561 | * DVO outputs are enabled simultaneosly. | |
1562 | */ | |
1563 | dpll |= DPLL_DVO_2X_MODE; | |
1564 | I915_WRITE(DPLL(!crtc->pipe), | |
1565 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1566 | } | |
66e3d5c0 | 1567 | |
c2b63374 VS |
1568 | /* |
1569 | * Apparently we need to have VGA mode enabled prior to changing | |
1570 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1571 | * dividers, even though the register value does change. | |
1572 | */ | |
1573 | I915_WRITE(reg, 0); | |
1574 | ||
8e7a65aa VS |
1575 | I915_WRITE(reg, dpll); |
1576 | ||
66e3d5c0 DV |
1577 | /* Wait for the clocks to stabilize. */ |
1578 | POSTING_READ(reg); | |
1579 | udelay(150); | |
1580 | ||
6315b5d3 | 1581 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1582 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1583 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1584 | } else { |
1585 | /* The pixel multiplier can only be updated once the | |
1586 | * DPLL is enabled and the clocks are stable. | |
1587 | * | |
1588 | * So write it again. | |
1589 | */ | |
1590 | I915_WRITE(reg, dpll); | |
1591 | } | |
63d7bbe9 JB |
1592 | |
1593 | /* We do this three times for luck */ | |
bb408dd2 VS |
1594 | for (i = 0; i < 3; i++) { |
1595 | I915_WRITE(reg, dpll); | |
1596 | POSTING_READ(reg); | |
1597 | udelay(150); /* wait for warmup */ | |
1598 | } | |
63d7bbe9 JB |
1599 | } |
1600 | ||
1601 | /** | |
50b44a44 | 1602 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1603 | * @dev_priv: i915 private structure |
1604 | * @pipe: pipe PLL to disable | |
1605 | * | |
1606 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1607 | * | |
1608 | * Note! This is for pre-ILK only. | |
1609 | */ | |
1c4e0274 | 1610 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1611 | { |
6315b5d3 | 1612 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1613 | enum pipe pipe = crtc->pipe; |
1614 | ||
1615 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1616 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1617 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1618 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1619 | I915_WRITE(DPLL(PIPE_B), |
1620 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1621 | I915_WRITE(DPLL(PIPE_A), | |
1622 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1623 | } | |
1624 | ||
b6b5d049 | 1625 | /* Don't disable pipe or pipe PLLs if needed */ |
e56134bc | 1626 | if (IS_I830(dev_priv)) |
63d7bbe9 JB |
1627 | return; |
1628 | ||
1629 | /* Make sure the pipe isn't still relying on us */ | |
1630 | assert_pipe_disabled(dev_priv, pipe); | |
1631 | ||
b8afb911 | 1632 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1633 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1634 | } |
1635 | ||
f6071166 JB |
1636 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1637 | { | |
b8afb911 | 1638 | u32 val; |
f6071166 JB |
1639 | |
1640 | /* Make sure the pipe isn't still relying on us */ | |
1641 | assert_pipe_disabled(dev_priv, pipe); | |
1642 | ||
03ed5cbf VS |
1643 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1644 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1645 | if (pipe != PIPE_A) | |
1646 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1647 | ||
f6071166 JB |
1648 | I915_WRITE(DPLL(pipe), val); |
1649 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1650 | } |
1651 | ||
1652 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1653 | { | |
d752048d | 1654 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1655 | u32 val; |
1656 | ||
a11b0703 VS |
1657 | /* Make sure the pipe isn't still relying on us */ |
1658 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1659 | |
60bfe44f VS |
1660 | val = DPLL_SSC_REF_CLK_CHV | |
1661 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1662 | if (pipe != PIPE_A) |
1663 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1664 | |
a11b0703 VS |
1665 | I915_WRITE(DPLL(pipe), val); |
1666 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1667 | |
a580516d | 1668 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1669 | |
1670 | /* Disable 10bit clock to display controller */ | |
1671 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1672 | val &= ~DPIO_DCLKP_EN; | |
1673 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1674 | ||
a580516d | 1675 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1676 | } |
1677 | ||
e4607fcf | 1678 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1679 | struct intel_digital_port *dport, |
1680 | unsigned int expected_mask) | |
89b667f8 JB |
1681 | { |
1682 | u32 port_mask; | |
f0f59a00 | 1683 | i915_reg_t dpll_reg; |
89b667f8 | 1684 | |
e4607fcf CML |
1685 | switch (dport->port) { |
1686 | case PORT_B: | |
89b667f8 | 1687 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1688 | dpll_reg = DPLL(0); |
e4607fcf CML |
1689 | break; |
1690 | case PORT_C: | |
89b667f8 | 1691 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1692 | dpll_reg = DPLL(0); |
9b6de0a1 | 1693 | expected_mask <<= 4; |
00fc31b7 CML |
1694 | break; |
1695 | case PORT_D: | |
1696 | port_mask = DPLL_PORTD_READY_MASK; | |
1697 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1698 | break; |
1699 | default: | |
1700 | BUG(); | |
1701 | } | |
89b667f8 | 1702 | |
370004d3 CW |
1703 | if (intel_wait_for_register(dev_priv, |
1704 | dpll_reg, port_mask, expected_mask, | |
1705 | 1000)) | |
9b6de0a1 VS |
1706 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1707 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1708 | } |
1709 | ||
b8a4f404 PZ |
1710 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1711 | enum pipe pipe) | |
040484af | 1712 | { |
98187836 VS |
1713 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1714 | pipe); | |
f0f59a00 VS |
1715 | i915_reg_t reg; |
1716 | uint32_t val, pipeconf_val; | |
040484af | 1717 | |
040484af | 1718 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1719 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1720 | |
1721 | /* FDI must be feeding us bits for PCH ports */ | |
1722 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1723 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1724 | ||
6e266956 | 1725 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1726 | /* Workaround: Set the timing override bit before enabling the |
1727 | * pch transcoder. */ | |
1728 | reg = TRANS_CHICKEN2(pipe); | |
1729 | val = I915_READ(reg); | |
1730 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1731 | I915_WRITE(reg, val); | |
59c859d6 | 1732 | } |
23670b32 | 1733 | |
ab9412ba | 1734 | reg = PCH_TRANSCONF(pipe); |
040484af | 1735 | val = I915_READ(reg); |
5f7f726d | 1736 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1737 | |
2d1fe073 | 1738 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1739 | /* |
c5de7c6f VS |
1740 | * Make the BPC in transcoder be consistent with |
1741 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1742 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1743 | */ |
dfd07d72 | 1744 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1745 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1746 | val |= PIPECONF_8BPC; |
1747 | else | |
1748 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1749 | } |
5f7f726d PZ |
1750 | |
1751 | val &= ~TRANS_INTERLACE_MASK; | |
1752 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1753 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1754 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1755 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1756 | else | |
1757 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1758 | else |
1759 | val |= TRANS_PROGRESSIVE; | |
1760 | ||
040484af | 1761 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1762 | if (intel_wait_for_register(dev_priv, |
1763 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1764 | 100)) | |
4bb6f1f3 | 1765 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1766 | } |
1767 | ||
8fb033d7 | 1768 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1769 | enum transcoder cpu_transcoder) |
040484af | 1770 | { |
8fb033d7 | 1771 | u32 val, pipeconf_val; |
8fb033d7 | 1772 | |
8fb033d7 | 1773 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1774 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
a2196033 | 1775 | assert_fdi_rx_enabled(dev_priv, PIPE_A); |
8fb033d7 | 1776 | |
223a6fdf | 1777 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1778 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1779 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1780 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1781 | |
25f3ef11 | 1782 | val = TRANS_ENABLE; |
937bb610 | 1783 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1784 | |
9a76b1c6 PZ |
1785 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1786 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1787 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1788 | else |
1789 | val |= TRANS_PROGRESSIVE; | |
1790 | ||
ab9412ba | 1791 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1792 | if (intel_wait_for_register(dev_priv, |
1793 | LPT_TRANSCONF, | |
1794 | TRANS_STATE_ENABLE, | |
1795 | TRANS_STATE_ENABLE, | |
1796 | 100)) | |
937bb610 | 1797 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1798 | } |
1799 | ||
b8a4f404 PZ |
1800 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1801 | enum pipe pipe) | |
040484af | 1802 | { |
f0f59a00 VS |
1803 | i915_reg_t reg; |
1804 | uint32_t val; | |
040484af JB |
1805 | |
1806 | /* FDI relies on the transcoder */ | |
1807 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1808 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1809 | ||
291906f1 JB |
1810 | /* Ports must be off as well */ |
1811 | assert_pch_ports_disabled(dev_priv, pipe); | |
1812 | ||
ab9412ba | 1813 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1814 | val = I915_READ(reg); |
1815 | val &= ~TRANS_ENABLE; | |
1816 | I915_WRITE(reg, val); | |
1817 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1818 | if (intel_wait_for_register(dev_priv, |
1819 | reg, TRANS_STATE_ENABLE, 0, | |
1820 | 50)) | |
4bb6f1f3 | 1821 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1822 | |
6e266956 | 1823 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1824 | /* Workaround: Clear the timing override chicken bit again. */ |
1825 | reg = TRANS_CHICKEN2(pipe); | |
1826 | val = I915_READ(reg); | |
1827 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1828 | I915_WRITE(reg, val); | |
1829 | } | |
040484af JB |
1830 | } |
1831 | ||
b7076546 | 1832 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1833 | { |
8fb033d7 PZ |
1834 | u32 val; |
1835 | ||
ab9412ba | 1836 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1837 | val &= ~TRANS_ENABLE; |
ab9412ba | 1838 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1839 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1840 | if (intel_wait_for_register(dev_priv, |
1841 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1842 | 50)) | |
8a52fd9f | 1843 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1844 | |
1845 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1846 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1847 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1848 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1849 | } |
1850 | ||
a2196033 | 1851 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
65f2130c VS |
1852 | { |
1853 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1854 | ||
1855 | WARN_ON(!crtc->config->has_pch_encoder); | |
1856 | ||
1857 | if (HAS_PCH_LPT(dev_priv)) | |
a2196033 | 1858 | return PIPE_A; |
65f2130c | 1859 | else |
a2196033 | 1860 | return crtc->pipe; |
65f2130c VS |
1861 | } |
1862 | ||
b24e7179 | 1863 | /** |
309cfea8 | 1864 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1865 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1866 | * |
0372264a | 1867 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1868 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1869 | */ |
e1fdc473 | 1870 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1871 | { |
0372264a | 1872 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1873 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1874 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1875 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1876 | i915_reg_t reg; |
b24e7179 JB |
1877 | u32 val; |
1878 | ||
9e2ee2dd VS |
1879 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1880 | ||
58c6eaa2 | 1881 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1882 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1883 | assert_sprites_disabled(dev_priv, pipe); |
1884 | ||
b24e7179 JB |
1885 | /* |
1886 | * A pipe without a PLL won't actually be able to drive bits from | |
1887 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1888 | * need the check. | |
1889 | */ | |
09fa8bb9 | 1890 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1891 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1892 | assert_dsi_pll_enabled(dev_priv); |
1893 | else | |
1894 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1895 | } else { |
6e3c9717 | 1896 | if (crtc->config->has_pch_encoder) { |
040484af | 1897 | /* if driving the PCH, we need FDI enabled */ |
65f2130c | 1898 | assert_fdi_rx_pll_enabled(dev_priv, |
a2196033 | 1899 | intel_crtc_pch_transcoder(crtc)); |
1a240d4d DV |
1900 | assert_fdi_tx_pll_enabled(dev_priv, |
1901 | (enum pipe) cpu_transcoder); | |
040484af JB |
1902 | } |
1903 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1904 | } | |
b24e7179 | 1905 | |
702e7a56 | 1906 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1907 | val = I915_READ(reg); |
7ad25d48 | 1908 | if (val & PIPECONF_ENABLE) { |
e56134bc VS |
1909 | /* we keep both pipes enabled on 830 */ |
1910 | WARN_ON(!IS_I830(dev_priv)); | |
00d70b15 | 1911 | return; |
7ad25d48 | 1912 | } |
00d70b15 CW |
1913 | |
1914 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1915 | POSTING_READ(reg); |
b7792d8b VS |
1916 | |
1917 | /* | |
1918 | * Until the pipe starts DSL will read as 0, which would cause | |
1919 | * an apparent vblank timestamp jump, which messes up also the | |
1920 | * frame count when it's derived from the timestamps. So let's | |
1921 | * wait for the pipe to start properly before we call | |
1922 | * drm_crtc_vblank_on() | |
1923 | */ | |
1924 | if (dev->max_vblank_count == 0 && | |
1925 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1926 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1927 | } |
1928 | ||
1929 | /** | |
309cfea8 | 1930 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 1931 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 1932 | * |
575f7ab7 VS |
1933 | * Disable the pipe of @crtc, making sure that various hardware |
1934 | * specific requirements are met, if applicable, e.g. plane | |
1935 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
1936 | * |
1937 | * Will wait until the pipe has shut down before returning. | |
1938 | */ | |
575f7ab7 | 1939 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1940 | { |
fac5e23e | 1941 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1942 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1943 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1944 | i915_reg_t reg; |
b24e7179 JB |
1945 | u32 val; |
1946 | ||
9e2ee2dd VS |
1947 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
1948 | ||
b24e7179 JB |
1949 | /* |
1950 | * Make sure planes won't keep trying to pump pixels to us, | |
1951 | * or we might hang the display. | |
1952 | */ | |
1953 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1954 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1955 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 1956 | |
702e7a56 | 1957 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1958 | val = I915_READ(reg); |
00d70b15 CW |
1959 | if ((val & PIPECONF_ENABLE) == 0) |
1960 | return; | |
1961 | ||
67adc644 VS |
1962 | /* |
1963 | * Double wide has implications for planes | |
1964 | * so best keep it disabled when not needed. | |
1965 | */ | |
6e3c9717 | 1966 | if (crtc->config->double_wide) |
67adc644 VS |
1967 | val &= ~PIPECONF_DOUBLE_WIDE; |
1968 | ||
1969 | /* Don't disable pipe or pipe PLLs if needed */ | |
e56134bc | 1970 | if (!IS_I830(dev_priv)) |
67adc644 VS |
1971 | val &= ~PIPECONF_ENABLE; |
1972 | ||
1973 | I915_WRITE(reg, val); | |
1974 | if ((val & PIPECONF_ENABLE) == 0) | |
1975 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
1976 | } |
1977 | ||
832be82f VS |
1978 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
1979 | { | |
1980 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
1981 | } | |
1982 | ||
d88c4afd VS |
1983 | static unsigned int |
1984 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) | |
7b49f948 | 1985 | { |
d88c4afd VS |
1986 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
1987 | unsigned int cpp = fb->format->cpp[plane]; | |
1988 | ||
1989 | switch (fb->modifier) { | |
2f075565 | 1990 | case DRM_FORMAT_MOD_LINEAR: |
7b49f948 VS |
1991 | return cpp; |
1992 | case I915_FORMAT_MOD_X_TILED: | |
1993 | if (IS_GEN2(dev_priv)) | |
1994 | return 128; | |
1995 | else | |
1996 | return 512; | |
1997 | case I915_FORMAT_MOD_Y_TILED: | |
1998 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
1999 | return 128; | |
2000 | else | |
2001 | return 512; | |
2002 | case I915_FORMAT_MOD_Yf_TILED: | |
2003 | switch (cpp) { | |
2004 | case 1: | |
2005 | return 64; | |
2006 | case 2: | |
2007 | case 4: | |
2008 | return 128; | |
2009 | case 8: | |
2010 | case 16: | |
2011 | return 256; | |
2012 | default: | |
2013 | MISSING_CASE(cpp); | |
2014 | return cpp; | |
2015 | } | |
2016 | break; | |
2017 | default: | |
d88c4afd | 2018 | MISSING_CASE(fb->modifier); |
7b49f948 VS |
2019 | return cpp; |
2020 | } | |
2021 | } | |
2022 | ||
d88c4afd VS |
2023 | static unsigned int |
2024 | intel_tile_height(const struct drm_framebuffer *fb, int plane) | |
a57ce0b2 | 2025 | { |
2f075565 | 2026 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
832be82f VS |
2027 | return 1; |
2028 | else | |
d88c4afd VS |
2029 | return intel_tile_size(to_i915(fb->dev)) / |
2030 | intel_tile_width_bytes(fb, plane); | |
6761dd31 TU |
2031 | } |
2032 | ||
8d0deca8 | 2033 | /* Return the tile dimensions in pixel units */ |
d88c4afd | 2034 | static void intel_tile_dims(const struct drm_framebuffer *fb, int plane, |
8d0deca8 | 2035 | unsigned int *tile_width, |
d88c4afd | 2036 | unsigned int *tile_height) |
8d0deca8 | 2037 | { |
d88c4afd VS |
2038 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane); |
2039 | unsigned int cpp = fb->format->cpp[plane]; | |
8d0deca8 VS |
2040 | |
2041 | *tile_width = tile_width_bytes / cpp; | |
d88c4afd | 2042 | *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes; |
8d0deca8 VS |
2043 | } |
2044 | ||
6761dd31 | 2045 | unsigned int |
d88c4afd VS |
2046 | intel_fb_align_height(const struct drm_framebuffer *fb, |
2047 | int plane, unsigned int height) | |
6761dd31 | 2048 | { |
d88c4afd | 2049 | unsigned int tile_height = intel_tile_height(fb, plane); |
832be82f VS |
2050 | |
2051 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2052 | } |
2053 | ||
1663b9d6 VS |
2054 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2055 | { | |
2056 | unsigned int size = 0; | |
2057 | int i; | |
2058 | ||
2059 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2060 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2061 | ||
2062 | return size; | |
2063 | } | |
2064 | ||
75c82a53 | 2065 | static void |
3465c580 VS |
2066 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2067 | const struct drm_framebuffer *fb, | |
2068 | unsigned int rotation) | |
f64b98cd | 2069 | { |
7b92c047 | 2070 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2071 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2072 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2073 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2074 | } |
2075 | } | |
50470bb0 | 2076 | |
fabac484 VS |
2077 | static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv) |
2078 | { | |
2079 | if (IS_I830(dev_priv)) | |
2080 | return 16 * 1024; | |
2081 | else if (IS_I85X(dev_priv)) | |
2082 | return 256; | |
d9e1551e VS |
2083 | else if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
2084 | return 32; | |
fabac484 VS |
2085 | else |
2086 | return 4 * 1024; | |
2087 | } | |
2088 | ||
603525d7 | 2089 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2090 | { |
2091 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2092 | return 256 * 1024; | |
c0f86832 | 2093 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2094 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2095 | return 128 * 1024; |
2096 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2097 | return 4 * 1024; | |
2098 | else | |
44c5905e | 2099 | return 0; |
4e9a86b6 VS |
2100 | } |
2101 | ||
d88c4afd VS |
2102 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
2103 | int plane) | |
603525d7 | 2104 | { |
d88c4afd VS |
2105 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2106 | ||
b90c1ee1 VS |
2107 | /* AUX_DIST needs only 4K alignment */ |
2108 | if (fb->format->format == DRM_FORMAT_NV12 && plane == 1) | |
2109 | return 4096; | |
2110 | ||
d88c4afd | 2111 | switch (fb->modifier) { |
2f075565 | 2112 | case DRM_FORMAT_MOD_LINEAR: |
603525d7 VS |
2113 | return intel_linear_alignment(dev_priv); |
2114 | case I915_FORMAT_MOD_X_TILED: | |
d88c4afd | 2115 | if (INTEL_GEN(dev_priv) >= 9) |
603525d7 VS |
2116 | return 256 * 1024; |
2117 | return 0; | |
2118 | case I915_FORMAT_MOD_Y_TILED: | |
2119 | case I915_FORMAT_MOD_Yf_TILED: | |
2120 | return 1 * 1024 * 1024; | |
2121 | default: | |
d88c4afd | 2122 | MISSING_CASE(fb->modifier); |
603525d7 VS |
2123 | return 0; |
2124 | } | |
2125 | } | |
2126 | ||
058d88c4 CW |
2127 | struct i915_vma * |
2128 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2129 | { |
850c4cdc | 2130 | struct drm_device *dev = fb->dev; |
fac5e23e | 2131 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2132 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2133 | struct i915_ggtt_view view; |
058d88c4 | 2134 | struct i915_vma *vma; |
6b95a207 | 2135 | u32 alignment; |
6b95a207 | 2136 | |
ebcdd39e MR |
2137 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2138 | ||
d88c4afd | 2139 | alignment = intel_surf_alignment(fb, 0); |
6b95a207 | 2140 | |
3465c580 | 2141 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2142 | |
693db184 CW |
2143 | /* Note that the w/a also requires 64 PTE of padding following the |
2144 | * bo. We currently fill all unused PTE with the shadow page and so | |
2145 | * we should always have valid PTE following the scanout preventing | |
2146 | * the VT-d warning. | |
2147 | */ | |
48f112fe | 2148 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2149 | alignment = 256 * 1024; |
2150 | ||
d6dd6843 PZ |
2151 | /* |
2152 | * Global gtt pte registers are special registers which actually forward | |
2153 | * writes to a chunk of system memory. Which means that there is no risk | |
2154 | * that the register values disappear as soon as we call | |
2155 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2156 | * pin/unpin/fence and not more. | |
2157 | */ | |
2158 | intel_runtime_pm_get(dev_priv); | |
2159 | ||
058d88c4 | 2160 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2161 | if (IS_ERR(vma)) |
2162 | goto err; | |
6b95a207 | 2163 | |
05a20d09 | 2164 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2165 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2166 | * fence, whereas 965+ only requires a fence if using | |
2167 | * framebuffer compression. For simplicity, we always, when | |
2168 | * possible, install a fence as the cost is not that onerous. | |
2169 | * | |
2170 | * If we fail to fence the tiled scanout, then either the | |
2171 | * modeset will reject the change (which is highly unlikely as | |
2172 | * the affected systems, all but one, do not have unmappable | |
2173 | * space) or we will not be able to enable full powersaving | |
2174 | * techniques (also likely not to apply due to various limits | |
2175 | * FBC and the like impose on the size of the buffer, which | |
2176 | * presumably we violated anyway with this unmappable buffer). | |
2177 | * Anyway, it is presumably better to stumble onwards with | |
2178 | * something and try to run the system in a "less than optimal" | |
2179 | * mode that matches the user configuration. | |
2180 | */ | |
2181 | if (i915_vma_get_fence(vma) == 0) | |
2182 | i915_vma_pin_fence(vma); | |
9807216f | 2183 | } |
6b95a207 | 2184 | |
be1e3415 | 2185 | i915_vma_get(vma); |
49ef5294 | 2186 | err: |
d6dd6843 | 2187 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2188 | return vma; |
6b95a207 KH |
2189 | } |
2190 | ||
be1e3415 | 2191 | void intel_unpin_fb_vma(struct i915_vma *vma) |
1690e1eb | 2192 | { |
be1e3415 | 2193 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
f64b98cd | 2194 | |
49ef5294 | 2195 | i915_vma_unpin_fence(vma); |
058d88c4 | 2196 | i915_gem_object_unpin_from_display_plane(vma); |
be1e3415 | 2197 | i915_vma_put(vma); |
1690e1eb CW |
2198 | } |
2199 | ||
ef78ec94 VS |
2200 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2201 | unsigned int rotation) | |
2202 | { | |
bd2ef25d | 2203 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2204 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2205 | else | |
2206 | return fb->pitches[plane]; | |
2207 | } | |
2208 | ||
6687c906 VS |
2209 | /* |
2210 | * Convert the x/y offsets into a linear offset. | |
2211 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2212 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2213 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2214 | */ | |
2215 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2216 | const struct intel_plane_state *state, |
2217 | int plane) | |
6687c906 | 2218 | { |
2949056c | 2219 | const struct drm_framebuffer *fb = state->base.fb; |
353c8598 | 2220 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2221 | unsigned int pitch = fb->pitches[plane]; |
2222 | ||
2223 | return y * pitch + x * cpp; | |
2224 | } | |
2225 | ||
2226 | /* | |
2227 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2228 | * specified plane src x/y offsets. The resulting x/y offsets | |
2229 | * specify the start of scanout from the beginning of the gtt mapping. | |
2230 | */ | |
2231 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2232 | const struct intel_plane_state *state, |
2233 | int plane) | |
6687c906 VS |
2234 | |
2235 | { | |
2949056c VS |
2236 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2237 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2238 | |
bd2ef25d | 2239 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2240 | *x += intel_fb->rotated[plane].x; |
2241 | *y += intel_fb->rotated[plane].y; | |
2242 | } else { | |
2243 | *x += intel_fb->normal[plane].x; | |
2244 | *y += intel_fb->normal[plane].y; | |
2245 | } | |
2246 | } | |
2247 | ||
29cf9491 | 2248 | /* |
29cf9491 VS |
2249 | * Input tile dimensions and pitch must already be |
2250 | * rotated to match x and y, and in pixel units. | |
2251 | */ | |
66a2d927 VS |
2252 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2253 | unsigned int tile_width, | |
2254 | unsigned int tile_height, | |
2255 | unsigned int tile_size, | |
2256 | unsigned int pitch_tiles, | |
2257 | u32 old_offset, | |
2258 | u32 new_offset) | |
29cf9491 | 2259 | { |
b9b24038 | 2260 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2261 | unsigned int tiles; |
2262 | ||
2263 | WARN_ON(old_offset & (tile_size - 1)); | |
2264 | WARN_ON(new_offset & (tile_size - 1)); | |
2265 | WARN_ON(new_offset > old_offset); | |
2266 | ||
2267 | tiles = (old_offset - new_offset) / tile_size; | |
2268 | ||
2269 | *y += tiles / pitch_tiles * tile_height; | |
2270 | *x += tiles % pitch_tiles * tile_width; | |
2271 | ||
b9b24038 VS |
2272 | /* minimize x in case it got needlessly big */ |
2273 | *y += *x / pitch_pixels * tile_height; | |
2274 | *x %= pitch_pixels; | |
2275 | ||
29cf9491 VS |
2276 | return new_offset; |
2277 | } | |
2278 | ||
66a2d927 VS |
2279 | /* |
2280 | * Adjust the tile offset by moving the difference into | |
2281 | * the x/y offsets. | |
2282 | */ | |
2283 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2284 | const struct intel_plane_state *state, int plane, | |
2285 | u32 old_offset, u32 new_offset) | |
2286 | { | |
2287 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2288 | const struct drm_framebuffer *fb = state->base.fb; | |
353c8598 | 2289 | unsigned int cpp = fb->format->cpp[plane]; |
66a2d927 VS |
2290 | unsigned int rotation = state->base.rotation; |
2291 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2292 | ||
2293 | WARN_ON(new_offset > old_offset); | |
2294 | ||
2f075565 | 2295 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
66a2d927 VS |
2296 | unsigned int tile_size, tile_width, tile_height; |
2297 | unsigned int pitch_tiles; | |
2298 | ||
2299 | tile_size = intel_tile_size(dev_priv); | |
d88c4afd | 2300 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
66a2d927 | 2301 | |
bd2ef25d | 2302 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2303 | pitch_tiles = pitch / tile_height; |
2304 | swap(tile_width, tile_height); | |
2305 | } else { | |
2306 | pitch_tiles = pitch / (tile_width * cpp); | |
2307 | } | |
2308 | ||
2309 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2310 | tile_size, pitch_tiles, | |
2311 | old_offset, new_offset); | |
2312 | } else { | |
2313 | old_offset += *y * pitch + *x * cpp; | |
2314 | ||
2315 | *y = (old_offset - new_offset) / pitch; | |
2316 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2317 | } | |
2318 | ||
2319 | return new_offset; | |
2320 | } | |
2321 | ||
8d0deca8 VS |
2322 | /* |
2323 | * Computes the linear offset to the base tile and adjusts | |
2324 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2325 | * | |
2326 | * In the 90/270 rotated case, x and y are assumed | |
2327 | * to be already rotated to match the rotated GTT view, and | |
2328 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2329 | * |
2330 | * This function is used when computing the derived information | |
2331 | * under intel_framebuffer, so using any of that information | |
2332 | * here is not allowed. Anything under drm_framebuffer can be | |
2333 | * used. This is why the user has to pass in the pitch since it | |
2334 | * is specified in the rotated orientation. | |
8d0deca8 | 2335 | */ |
6687c906 VS |
2336 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2337 | int *x, int *y, | |
2338 | const struct drm_framebuffer *fb, int plane, | |
2339 | unsigned int pitch, | |
2340 | unsigned int rotation, | |
2341 | u32 alignment) | |
c2c75131 | 2342 | { |
bae781b2 | 2343 | uint64_t fb_modifier = fb->modifier; |
353c8598 | 2344 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 | 2345 | u32 offset, offset_aligned; |
29cf9491 | 2346 | |
29cf9491 VS |
2347 | if (alignment) |
2348 | alignment--; | |
2349 | ||
2f075565 | 2350 | if (fb_modifier != DRM_FORMAT_MOD_LINEAR) { |
8d0deca8 VS |
2351 | unsigned int tile_size, tile_width, tile_height; |
2352 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2353 | |
d843310d | 2354 | tile_size = intel_tile_size(dev_priv); |
d88c4afd | 2355 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
8d0deca8 | 2356 | |
bd2ef25d | 2357 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2358 | pitch_tiles = pitch / tile_height; |
2359 | swap(tile_width, tile_height); | |
2360 | } else { | |
2361 | pitch_tiles = pitch / (tile_width * cpp); | |
2362 | } | |
d843310d VS |
2363 | |
2364 | tile_rows = *y / tile_height; | |
2365 | *y %= tile_height; | |
c2c75131 | 2366 | |
8d0deca8 VS |
2367 | tiles = *x / tile_width; |
2368 | *x %= tile_width; | |
bc752862 | 2369 | |
29cf9491 VS |
2370 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2371 | offset_aligned = offset & ~alignment; | |
bc752862 | 2372 | |
66a2d927 VS |
2373 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2374 | tile_size, pitch_tiles, | |
2375 | offset, offset_aligned); | |
29cf9491 | 2376 | } else { |
bc752862 | 2377 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2378 | offset_aligned = offset & ~alignment; |
2379 | ||
4e9a86b6 VS |
2380 | *y = (offset & alignment) / pitch; |
2381 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2382 | } |
29cf9491 VS |
2383 | |
2384 | return offset_aligned; | |
c2c75131 DV |
2385 | } |
2386 | ||
6687c906 | 2387 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2388 | const struct intel_plane_state *state, |
2389 | int plane) | |
6687c906 | 2390 | { |
1e7b4fd8 VS |
2391 | struct intel_plane *intel_plane = to_intel_plane(state->base.plane); |
2392 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); | |
2949056c VS |
2393 | const struct drm_framebuffer *fb = state->base.fb; |
2394 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2395 | int pitch = intel_fb_pitch(fb, plane, rotation); |
1e7b4fd8 VS |
2396 | u32 alignment; |
2397 | ||
2398 | if (intel_plane->id == PLANE_CURSOR) | |
2399 | alignment = intel_cursor_alignment(dev_priv); | |
2400 | else | |
2401 | alignment = intel_surf_alignment(fb, plane); | |
6687c906 VS |
2402 | |
2403 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2404 | rotation, alignment); | |
2405 | } | |
2406 | ||
2407 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2408 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2409 | const struct drm_framebuffer *fb, int plane) | |
2410 | { | |
353c8598 | 2411 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2412 | unsigned int pitch = fb->pitches[plane]; |
2413 | u32 linear_offset = fb->offsets[plane]; | |
2414 | ||
2415 | *y = linear_offset / pitch; | |
2416 | *x = linear_offset % pitch / cpp; | |
2417 | } | |
2418 | ||
72618ebf VS |
2419 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2420 | { | |
2421 | switch (fb_modifier) { | |
2422 | case I915_FORMAT_MOD_X_TILED: | |
2423 | return I915_TILING_X; | |
2424 | case I915_FORMAT_MOD_Y_TILED: | |
2425 | return I915_TILING_Y; | |
2426 | default: | |
2427 | return I915_TILING_NONE; | |
2428 | } | |
2429 | } | |
2430 | ||
6687c906 VS |
2431 | static int |
2432 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2433 | struct drm_framebuffer *fb) | |
2434 | { | |
2435 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2436 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2437 | u32 gtt_offset_rotated = 0; | |
2438 | unsigned int max_size = 0; | |
bcb0b461 | 2439 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
2440 | unsigned int tile_size = intel_tile_size(dev_priv); |
2441 | ||
2442 | for (i = 0; i < num_planes; i++) { | |
2443 | unsigned int width, height; | |
2444 | unsigned int cpp, size; | |
2445 | u32 offset; | |
2446 | int x, y; | |
2447 | ||
353c8598 | 2448 | cpp = fb->format->cpp[i]; |
145fcb11 VS |
2449 | width = drm_framebuffer_plane_width(fb->width, fb, i); |
2450 | height = drm_framebuffer_plane_height(fb->height, fb, i); | |
6687c906 VS |
2451 | |
2452 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2453 | ||
60d5f2a4 VS |
2454 | /* |
2455 | * The fence (if used) is aligned to the start of the object | |
2456 | * so having the framebuffer wrap around across the edge of the | |
2457 | * fenced region doesn't really work. We have no API to configure | |
2458 | * the fence start offset within the object (nor could we probably | |
2459 | * on gen2/3). So it's just easier if we just require that the | |
2460 | * fb layout agrees with the fence layout. We already check that the | |
2461 | * fb stride matches the fence stride elsewhere. | |
2462 | */ | |
2463 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2464 | (x + width) * cpp > fb->pitches[i]) { | |
144cc143 VS |
2465 | DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", |
2466 | i, fb->offsets[i]); | |
60d5f2a4 VS |
2467 | return -EINVAL; |
2468 | } | |
2469 | ||
6687c906 VS |
2470 | /* |
2471 | * First pixel of the framebuffer from | |
2472 | * the start of the normal gtt mapping. | |
2473 | */ | |
2474 | intel_fb->normal[i].x = x; | |
2475 | intel_fb->normal[i].y = y; | |
2476 | ||
2477 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
3ca46c0a | 2478 | fb, i, fb->pitches[i], |
c2c446ad | 2479 | DRM_MODE_ROTATE_0, tile_size); |
6687c906 VS |
2480 | offset /= tile_size; |
2481 | ||
2f075565 | 2482 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
6687c906 VS |
2483 | unsigned int tile_width, tile_height; |
2484 | unsigned int pitch_tiles; | |
2485 | struct drm_rect r; | |
2486 | ||
d88c4afd | 2487 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
6687c906 VS |
2488 | |
2489 | rot_info->plane[i].offset = offset; | |
2490 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2491 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2492 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2493 | ||
2494 | intel_fb->rotated[i].pitch = | |
2495 | rot_info->plane[i].height * tile_height; | |
2496 | ||
2497 | /* how many tiles does this plane need */ | |
2498 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2499 | /* | |
2500 | * If the plane isn't horizontally tile aligned, | |
2501 | * we need one more tile. | |
2502 | */ | |
2503 | if (x != 0) | |
2504 | size++; | |
2505 | ||
2506 | /* rotate the x/y offsets to match the GTT view */ | |
2507 | r.x1 = x; | |
2508 | r.y1 = y; | |
2509 | r.x2 = x + width; | |
2510 | r.y2 = y + height; | |
2511 | drm_rect_rotate(&r, | |
2512 | rot_info->plane[i].width * tile_width, | |
2513 | rot_info->plane[i].height * tile_height, | |
c2c446ad | 2514 | DRM_MODE_ROTATE_270); |
6687c906 VS |
2515 | x = r.x1; |
2516 | y = r.y1; | |
2517 | ||
2518 | /* rotate the tile dimensions to match the GTT view */ | |
2519 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2520 | swap(tile_width, tile_height); | |
2521 | ||
2522 | /* | |
2523 | * We only keep the x/y offsets, so push all of the | |
2524 | * gtt offset into the x/y offsets. | |
2525 | */ | |
46a1bd28 ACO |
2526 | _intel_adjust_tile_offset(&x, &y, |
2527 | tile_width, tile_height, | |
2528 | tile_size, pitch_tiles, | |
66a2d927 | 2529 | gtt_offset_rotated * tile_size, 0); |
6687c906 VS |
2530 | |
2531 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2532 | ||
2533 | /* | |
2534 | * First pixel of the framebuffer from | |
2535 | * the start of the rotated gtt mapping. | |
2536 | */ | |
2537 | intel_fb->rotated[i].x = x; | |
2538 | intel_fb->rotated[i].y = y; | |
2539 | } else { | |
2540 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2541 | x * cpp, tile_size); | |
2542 | } | |
2543 | ||
2544 | /* how many tiles in total needed in the bo */ | |
2545 | max_size = max(max_size, offset + size); | |
2546 | } | |
2547 | ||
144cc143 VS |
2548 | if (max_size * tile_size > intel_fb->obj->base.size) { |
2549 | DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2550 | max_size * tile_size, intel_fb->obj->base.size); | |
6687c906 VS |
2551 | return -EINVAL; |
2552 | } | |
2553 | ||
2554 | return 0; | |
2555 | } | |
2556 | ||
b35d63fa | 2557 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2558 | { |
2559 | switch (format) { | |
2560 | case DISPPLANE_8BPP: | |
2561 | return DRM_FORMAT_C8; | |
2562 | case DISPPLANE_BGRX555: | |
2563 | return DRM_FORMAT_XRGB1555; | |
2564 | case DISPPLANE_BGRX565: | |
2565 | return DRM_FORMAT_RGB565; | |
2566 | default: | |
2567 | case DISPPLANE_BGRX888: | |
2568 | return DRM_FORMAT_XRGB8888; | |
2569 | case DISPPLANE_RGBX888: | |
2570 | return DRM_FORMAT_XBGR8888; | |
2571 | case DISPPLANE_BGRX101010: | |
2572 | return DRM_FORMAT_XRGB2101010; | |
2573 | case DISPPLANE_RGBX101010: | |
2574 | return DRM_FORMAT_XBGR2101010; | |
2575 | } | |
2576 | } | |
2577 | ||
bc8d7dff DL |
2578 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2579 | { | |
2580 | switch (format) { | |
2581 | case PLANE_CTL_FORMAT_RGB_565: | |
2582 | return DRM_FORMAT_RGB565; | |
2583 | default: | |
2584 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2585 | if (rgb_order) { | |
2586 | if (alpha) | |
2587 | return DRM_FORMAT_ABGR8888; | |
2588 | else | |
2589 | return DRM_FORMAT_XBGR8888; | |
2590 | } else { | |
2591 | if (alpha) | |
2592 | return DRM_FORMAT_ARGB8888; | |
2593 | else | |
2594 | return DRM_FORMAT_XRGB8888; | |
2595 | } | |
2596 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2597 | if (rgb_order) | |
2598 | return DRM_FORMAT_XBGR2101010; | |
2599 | else | |
2600 | return DRM_FORMAT_XRGB2101010; | |
2601 | } | |
2602 | } | |
2603 | ||
5724dbd1 | 2604 | static bool |
f6936e29 DV |
2605 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2606 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2607 | { |
2608 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2609 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2610 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2611 | struct drm_i915_gem_object *obj = NULL; |
2612 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2613 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2614 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2615 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2616 | PAGE_SIZE); | |
2617 | ||
2618 | size_aligned -= base_aligned; | |
46f297fb | 2619 | |
ff2652ea CW |
2620 | if (plane_config->size == 0) |
2621 | return false; | |
2622 | ||
3badb49f PZ |
2623 | /* If the FB is too big, just don't use it since fbdev is not very |
2624 | * important and we should probably use that space with FBC or other | |
2625 | * features. */ | |
72e96d64 | 2626 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2627 | return false; |
2628 | ||
12c83d99 | 2629 | mutex_lock(&dev->struct_mutex); |
187685cb | 2630 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2631 | base_aligned, |
2632 | base_aligned, | |
2633 | size_aligned); | |
24dbf51a CW |
2634 | mutex_unlock(&dev->struct_mutex); |
2635 | if (!obj) | |
484b41dd | 2636 | return false; |
46f297fb | 2637 | |
3e510a8e CW |
2638 | if (plane_config->tiling == I915_TILING_X) |
2639 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2640 | |
438b74a5 | 2641 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
2642 | mode_cmd.width = fb->width; |
2643 | mode_cmd.height = fb->height; | |
2644 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2645 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2646 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2647 | |
24dbf51a | 2648 | if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { |
46f297fb JB |
2649 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2650 | goto out_unref_obj; | |
2651 | } | |
12c83d99 | 2652 | |
484b41dd | 2653 | |
f6936e29 | 2654 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2655 | return true; |
46f297fb JB |
2656 | |
2657 | out_unref_obj: | |
f8c417cd | 2658 | i915_gem_object_put(obj); |
484b41dd JB |
2659 | return false; |
2660 | } | |
2661 | ||
e9728bd8 VS |
2662 | static void |
2663 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
2664 | struct intel_plane_state *plane_state, | |
2665 | bool visible) | |
2666 | { | |
2667 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
2668 | ||
2669 | plane_state->base.visible = visible; | |
2670 | ||
2671 | /* FIXME pre-g4x don't work like this */ | |
2672 | if (visible) { | |
2673 | crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); | |
2674 | crtc_state->active_planes |= BIT(plane->id); | |
2675 | } else { | |
2676 | crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); | |
2677 | crtc_state->active_planes &= ~BIT(plane->id); | |
2678 | } | |
2679 | ||
2680 | DRM_DEBUG_KMS("%s active planes 0x%x\n", | |
2681 | crtc_state->base.crtc->name, | |
2682 | crtc_state->active_planes); | |
2683 | } | |
2684 | ||
5724dbd1 | 2685 | static void |
f6936e29 DV |
2686 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2687 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2688 | { |
2689 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2690 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 2691 | struct drm_crtc *c; |
2ff8fde1 | 2692 | struct drm_i915_gem_object *obj; |
88595ac9 | 2693 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2694 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2695 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2696 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2697 | struct intel_plane_state *intel_state = |
2698 | to_intel_plane_state(plane_state); | |
88595ac9 | 2699 | struct drm_framebuffer *fb; |
484b41dd | 2700 | |
2d14030b | 2701 | if (!plane_config->fb) |
484b41dd JB |
2702 | return; |
2703 | ||
f6936e29 | 2704 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2705 | fb = &plane_config->fb->base; |
2706 | goto valid_fb; | |
f55548b5 | 2707 | } |
484b41dd | 2708 | |
2d14030b | 2709 | kfree(plane_config->fb); |
484b41dd JB |
2710 | |
2711 | /* | |
2712 | * Failed to alloc the obj, check to see if we should share | |
2713 | * an fb with another CRTC instead | |
2714 | */ | |
70e1e0ec | 2715 | for_each_crtc(dev, c) { |
be1e3415 | 2716 | struct intel_plane_state *state; |
484b41dd JB |
2717 | |
2718 | if (c == &intel_crtc->base) | |
2719 | continue; | |
2720 | ||
be1e3415 | 2721 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
2722 | continue; |
2723 | ||
be1e3415 CW |
2724 | state = to_intel_plane_state(c->primary->state); |
2725 | if (!state->vma) | |
484b41dd JB |
2726 | continue; |
2727 | ||
be1e3415 CW |
2728 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
2729 | fb = c->primary->fb; | |
88595ac9 DV |
2730 | drm_framebuffer_reference(fb); |
2731 | goto valid_fb; | |
484b41dd JB |
2732 | } |
2733 | } | |
88595ac9 | 2734 | |
200757f5 MR |
2735 | /* |
2736 | * We've failed to reconstruct the BIOS FB. Current display state | |
2737 | * indicates that the primary plane is visible, but has a NULL FB, | |
2738 | * which will lead to problems later if we don't fix it up. The | |
2739 | * simplest solution is to just disable the primary plane now and | |
2740 | * pretend the BIOS never had it enabled. | |
2741 | */ | |
e9728bd8 VS |
2742 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), |
2743 | to_intel_plane_state(plane_state), | |
2744 | false); | |
2622a081 | 2745 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
72259536 | 2746 | trace_intel_disable_plane(primary, intel_crtc); |
282dbf9b | 2747 | intel_plane->disable_plane(intel_plane, intel_crtc); |
200757f5 | 2748 | |
88595ac9 DV |
2749 | return; |
2750 | ||
2751 | valid_fb: | |
be1e3415 CW |
2752 | mutex_lock(&dev->struct_mutex); |
2753 | intel_state->vma = | |
2754 | intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
2755 | mutex_unlock(&dev->struct_mutex); | |
2756 | if (IS_ERR(intel_state->vma)) { | |
2757 | DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", | |
2758 | intel_crtc->pipe, PTR_ERR(intel_state->vma)); | |
2759 | ||
2760 | intel_state->vma = NULL; | |
2761 | drm_framebuffer_unreference(fb); | |
2762 | return; | |
2763 | } | |
2764 | ||
f44e2659 VS |
2765 | plane_state->src_x = 0; |
2766 | plane_state->src_y = 0; | |
be5651f2 ML |
2767 | plane_state->src_w = fb->width << 16; |
2768 | plane_state->src_h = fb->height << 16; | |
2769 | ||
f44e2659 VS |
2770 | plane_state->crtc_x = 0; |
2771 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2772 | plane_state->crtc_w = fb->width; |
2773 | plane_state->crtc_h = fb->height; | |
2774 | ||
1638d30c RC |
2775 | intel_state->base.src = drm_plane_state_src(plane_state); |
2776 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2777 | |
88595ac9 | 2778 | obj = intel_fb_obj(fb); |
3e510a8e | 2779 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2780 | dev_priv->preserve_bios_swizzle = true; |
2781 | ||
be5651f2 ML |
2782 | drm_framebuffer_reference(fb); |
2783 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2784 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
e9728bd8 VS |
2785 | |
2786 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), | |
2787 | to_intel_plane_state(plane_state), | |
2788 | true); | |
2789 | ||
faf5bf0a CW |
2790 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2791 | &obj->frontbuffer_bits); | |
46f297fb JB |
2792 | } |
2793 | ||
b63a16f6 VS |
2794 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2795 | unsigned int rotation) | |
2796 | { | |
353c8598 | 2797 | int cpp = fb->format->cpp[plane]; |
b63a16f6 | 2798 | |
bae781b2 | 2799 | switch (fb->modifier) { |
2f075565 | 2800 | case DRM_FORMAT_MOD_LINEAR: |
b63a16f6 VS |
2801 | case I915_FORMAT_MOD_X_TILED: |
2802 | switch (cpp) { | |
2803 | case 8: | |
2804 | return 4096; | |
2805 | case 4: | |
2806 | case 2: | |
2807 | case 1: | |
2808 | return 8192; | |
2809 | default: | |
2810 | MISSING_CASE(cpp); | |
2811 | break; | |
2812 | } | |
2813 | break; | |
2814 | case I915_FORMAT_MOD_Y_TILED: | |
2815 | case I915_FORMAT_MOD_Yf_TILED: | |
2816 | switch (cpp) { | |
2817 | case 8: | |
2818 | return 2048; | |
2819 | case 4: | |
2820 | return 4096; | |
2821 | case 2: | |
2822 | case 1: | |
2823 | return 8192; | |
2824 | default: | |
2825 | MISSING_CASE(cpp); | |
2826 | break; | |
2827 | } | |
2828 | break; | |
2829 | default: | |
bae781b2 | 2830 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2831 | } |
2832 | ||
2833 | return 2048; | |
2834 | } | |
2835 | ||
2836 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2837 | { | |
b63a16f6 VS |
2838 | const struct drm_framebuffer *fb = plane_state->base.fb; |
2839 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2840 | int x = plane_state->base.src.x1 >> 16; |
2841 | int y = plane_state->base.src.y1 >> 16; | |
2842 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2843 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2844 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2845 | int max_height = 4096; | |
8d970654 | 2846 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2847 | |
2848 | if (w > max_width || h > max_height) { | |
2849 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2850 | w, h, max_width, max_height); | |
2851 | return -EINVAL; | |
2852 | } | |
2853 | ||
2854 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2855 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
d88c4afd | 2856 | alignment = intel_surf_alignment(fb, 0); |
b63a16f6 | 2857 | |
8d970654 VS |
2858 | /* |
2859 | * AUX surface offset is specified as the distance from the | |
2860 | * main surface offset, and it must be non-negative. Make | |
2861 | * sure that is what we will get. | |
2862 | */ | |
2863 | if (offset > aux_offset) | |
2864 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2865 | offset, aux_offset & ~(alignment - 1)); | |
2866 | ||
b63a16f6 VS |
2867 | /* |
2868 | * When using an X-tiled surface, the plane blows up | |
2869 | * if the x offset + width exceed the stride. | |
2870 | * | |
2871 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2872 | */ | |
bae781b2 | 2873 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 2874 | int cpp = fb->format->cpp[0]; |
b63a16f6 VS |
2875 | |
2876 | while ((x + w) * cpp > fb->pitches[0]) { | |
2877 | if (offset == 0) { | |
2878 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2879 | return -EINVAL; | |
2880 | } | |
2881 | ||
2882 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2883 | offset, offset - alignment); | |
2884 | } | |
2885 | } | |
2886 | ||
2887 | plane_state->main.offset = offset; | |
2888 | plane_state->main.x = x; | |
2889 | plane_state->main.y = y; | |
2890 | ||
2891 | return 0; | |
2892 | } | |
2893 | ||
8d970654 VS |
2894 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2895 | { | |
2896 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2897 | unsigned int rotation = plane_state->base.rotation; | |
2898 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2899 | int max_height = 4096; | |
cc926387 DV |
2900 | int x = plane_state->base.src.x1 >> 17; |
2901 | int y = plane_state->base.src.y1 >> 17; | |
2902 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2903 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2904 | u32 offset; |
2905 | ||
2906 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2907 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2908 | ||
2909 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2910 | if (w > max_width || h > max_height) { | |
2911 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2912 | w, h, max_width, max_height); | |
2913 | return -EINVAL; | |
2914 | } | |
2915 | ||
2916 | plane_state->aux.offset = offset; | |
2917 | plane_state->aux.x = x; | |
2918 | plane_state->aux.y = y; | |
2919 | ||
2920 | return 0; | |
2921 | } | |
2922 | ||
b63a16f6 VS |
2923 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2924 | { | |
2925 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2926 | unsigned int rotation = plane_state->base.rotation; | |
2927 | int ret; | |
2928 | ||
a5e4c7d0 VS |
2929 | if (!plane_state->base.visible) |
2930 | return 0; | |
2931 | ||
b63a16f6 | 2932 | /* Rotate src coordinates to match rotated GTT view */ |
bd2ef25d | 2933 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 2934 | drm_rect_rotate(&plane_state->base.src, |
da064b47 | 2935 | fb->width << 16, fb->height << 16, |
c2c446ad | 2936 | DRM_MODE_ROTATE_270); |
b63a16f6 | 2937 | |
8d970654 VS |
2938 | /* |
2939 | * Handle the AUX surface first since | |
2940 | * the main surface setup depends on it. | |
2941 | */ | |
438b74a5 | 2942 | if (fb->format->format == DRM_FORMAT_NV12) { |
8d970654 VS |
2943 | ret = skl_check_nv12_aux_surface(plane_state); |
2944 | if (ret) | |
2945 | return ret; | |
2946 | } else { | |
2947 | plane_state->aux.offset = ~0xfff; | |
2948 | plane_state->aux.x = 0; | |
2949 | plane_state->aux.y = 0; | |
2950 | } | |
2951 | ||
b63a16f6 VS |
2952 | ret = skl_check_main_surface(plane_state); |
2953 | if (ret) | |
2954 | return ret; | |
2955 | ||
2956 | return 0; | |
2957 | } | |
2958 | ||
7145f60a VS |
2959 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
2960 | const struct intel_plane_state *plane_state) | |
81255565 | 2961 | { |
7145f60a VS |
2962 | struct drm_i915_private *dev_priv = |
2963 | to_i915(plane_state->base.plane->dev); | |
2964 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
2965 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
8d0deca8 | 2966 | unsigned int rotation = plane_state->base.rotation; |
7145f60a | 2967 | u32 dspcntr; |
c9ba6fad | 2968 | |
7145f60a | 2969 | dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; |
f45651ba | 2970 | |
6a4407a6 VS |
2971 | if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || |
2972 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
7145f60a | 2973 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
f45651ba | 2974 | |
6a4407a6 VS |
2975 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
2976 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
f45651ba | 2977 | |
d509e28b VS |
2978 | if (INTEL_GEN(dev_priv) < 4) |
2979 | dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); | |
81255565 | 2980 | |
438b74a5 | 2981 | switch (fb->format->format) { |
57779d06 | 2982 | case DRM_FORMAT_C8: |
81255565 JB |
2983 | dspcntr |= DISPPLANE_8BPP; |
2984 | break; | |
57779d06 | 2985 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2986 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2987 | break; |
57779d06 VS |
2988 | case DRM_FORMAT_RGB565: |
2989 | dspcntr |= DISPPLANE_BGRX565; | |
2990 | break; | |
2991 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2992 | dspcntr |= DISPPLANE_BGRX888; |
2993 | break; | |
2994 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2995 | dspcntr |= DISPPLANE_RGBX888; |
2996 | break; | |
2997 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2998 | dspcntr |= DISPPLANE_BGRX101010; |
2999 | break; | |
3000 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3001 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3002 | break; |
3003 | default: | |
7145f60a VS |
3004 | MISSING_CASE(fb->format->format); |
3005 | return 0; | |
81255565 | 3006 | } |
57779d06 | 3007 | |
72618ebf | 3008 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3009 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3010 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3011 | |
c2c446ad | 3012 | if (rotation & DRM_MODE_ROTATE_180) |
df0cd455 VS |
3013 | dspcntr |= DISPPLANE_ROTATE_180; |
3014 | ||
c2c446ad | 3015 | if (rotation & DRM_MODE_REFLECT_X) |
4ea7be2b VS |
3016 | dspcntr |= DISPPLANE_MIRROR; |
3017 | ||
7145f60a VS |
3018 | return dspcntr; |
3019 | } | |
de1aa629 | 3020 | |
f9407ae1 | 3021 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
5b7fcc44 VS |
3022 | { |
3023 | struct drm_i915_private *dev_priv = | |
3024 | to_i915(plane_state->base.plane->dev); | |
3025 | int src_x = plane_state->base.src.x1 >> 16; | |
3026 | int src_y = plane_state->base.src.y1 >> 16; | |
3027 | u32 offset; | |
81255565 | 3028 | |
5b7fcc44 | 3029 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
e506a0c6 | 3030 | |
5b7fcc44 VS |
3031 | if (INTEL_GEN(dev_priv) >= 4) |
3032 | offset = intel_compute_tile_offset(&src_x, &src_y, | |
3033 | plane_state, 0); | |
3034 | else | |
3035 | offset = 0; | |
3036 | ||
3037 | /* HSW/BDW do this automagically in hardware */ | |
3038 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { | |
3039 | unsigned int rotation = plane_state->base.rotation; | |
3040 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; | |
3041 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3042 | ||
c2c446ad | 3043 | if (rotation & DRM_MODE_ROTATE_180) { |
5b7fcc44 VS |
3044 | src_x += src_w - 1; |
3045 | src_y += src_h - 1; | |
c2c446ad | 3046 | } else if (rotation & DRM_MODE_REFLECT_X) { |
5b7fcc44 VS |
3047 | src_x += src_w - 1; |
3048 | } | |
48404c1e SJ |
3049 | } |
3050 | ||
5b7fcc44 VS |
3051 | plane_state->main.offset = offset; |
3052 | plane_state->main.x = src_x; | |
3053 | plane_state->main.y = src_y; | |
3054 | ||
3055 | return 0; | |
3056 | } | |
3057 | ||
282dbf9b | 3058 | static void i9xx_update_primary_plane(struct intel_plane *primary, |
7145f60a VS |
3059 | const struct intel_crtc_state *crtc_state, |
3060 | const struct intel_plane_state *plane_state) | |
3061 | { | |
282dbf9b VS |
3062 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3063 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3064 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3065 | enum plane plane = primary->plane; | |
7145f60a | 3066 | u32 linear_offset; |
a0864d59 | 3067 | u32 dspcntr = plane_state->ctl; |
7145f60a | 3068 | i915_reg_t reg = DSPCNTR(plane); |
5b7fcc44 VS |
3069 | int x = plane_state->main.x; |
3070 | int y = plane_state->main.y; | |
7145f60a VS |
3071 | unsigned long irqflags; |
3072 | ||
2949056c | 3073 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3074 | |
5b7fcc44 | 3075 | if (INTEL_GEN(dev_priv) >= 4) |
282dbf9b | 3076 | crtc->dspaddr_offset = plane_state->main.offset; |
5b7fcc44 | 3077 | else |
282dbf9b | 3078 | crtc->dspaddr_offset = linear_offset; |
6687c906 | 3079 | |
282dbf9b VS |
3080 | crtc->adjusted_x = x; |
3081 | crtc->adjusted_y = y; | |
2db3366b | 3082 | |
dd584fc0 VS |
3083 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3084 | ||
78587de2 VS |
3085 | if (INTEL_GEN(dev_priv) < 4) { |
3086 | /* pipesrc and dspsize control the size that is scaled from, | |
3087 | * which should always be the user's requested size. | |
3088 | */ | |
dd584fc0 VS |
3089 | I915_WRITE_FW(DSPSIZE(plane), |
3090 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3091 | (crtc_state->pipe_src_w - 1)); | |
3092 | I915_WRITE_FW(DSPPOS(plane), 0); | |
78587de2 | 3093 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
dd584fc0 VS |
3094 | I915_WRITE_FW(PRIMSIZE(plane), |
3095 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3096 | (crtc_state->pipe_src_w - 1)); | |
3097 | I915_WRITE_FW(PRIMPOS(plane), 0); | |
3098 | I915_WRITE_FW(PRIMCNSTALPHA(plane), 0); | |
78587de2 VS |
3099 | } |
3100 | ||
dd584fc0 | 3101 | I915_WRITE_FW(reg, dspcntr); |
48404c1e | 3102 | |
dd584fc0 | 3103 | I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]); |
3ba35e53 VS |
3104 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3105 | I915_WRITE_FW(DSPSURF(plane), | |
3106 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3107 | crtc->dspaddr_offset); |
3ba35e53 VS |
3108 | I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); |
3109 | } else if (INTEL_GEN(dev_priv) >= 4) { | |
dd584fc0 VS |
3110 | I915_WRITE_FW(DSPSURF(plane), |
3111 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3112 | crtc->dspaddr_offset); |
dd584fc0 VS |
3113 | I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); |
3114 | I915_WRITE_FW(DSPLINOFF(plane), linear_offset); | |
bfb81049 | 3115 | } else { |
dd584fc0 VS |
3116 | I915_WRITE_FW(DSPADDR(plane), |
3117 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3118 | crtc->dspaddr_offset); |
bfb81049 | 3119 | } |
dd584fc0 VS |
3120 | POSTING_READ_FW(reg); |
3121 | ||
3122 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
17638cd6 JB |
3123 | } |
3124 | ||
282dbf9b VS |
3125 | static void i9xx_disable_primary_plane(struct intel_plane *primary, |
3126 | struct intel_crtc *crtc) | |
17638cd6 | 3127 | { |
282dbf9b VS |
3128 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3129 | enum plane plane = primary->plane; | |
dd584fc0 VS |
3130 | unsigned long irqflags; |
3131 | ||
3132 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
f45651ba | 3133 | |
dd584fc0 | 3134 | I915_WRITE_FW(DSPCNTR(plane), 0); |
a8d201af | 3135 | if (INTEL_INFO(dev_priv)->gen >= 4) |
dd584fc0 | 3136 | I915_WRITE_FW(DSPSURF(plane), 0); |
a8d201af | 3137 | else |
dd584fc0 VS |
3138 | I915_WRITE_FW(DSPADDR(plane), 0); |
3139 | POSTING_READ_FW(DSPCNTR(plane)); | |
3140 | ||
3141 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3142 | } |
c9ba6fad | 3143 | |
d88c4afd VS |
3144 | static u32 |
3145 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane) | |
b321803d | 3146 | { |
2f075565 | 3147 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
b321803d | 3148 | return 64; |
d88c4afd VS |
3149 | else |
3150 | return intel_tile_width_bytes(fb, plane); | |
b321803d DL |
3151 | } |
3152 | ||
e435d6e5 ML |
3153 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3154 | { | |
3155 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3156 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3157 | |
3158 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3159 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3160 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3161 | } |
3162 | ||
a1b2278e CK |
3163 | /* |
3164 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3165 | */ | |
0583236e | 3166 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3167 | { |
a1b2278e CK |
3168 | struct intel_crtc_scaler_state *scaler_state; |
3169 | int i; | |
3170 | ||
a1b2278e CK |
3171 | scaler_state = &intel_crtc->config->scaler_state; |
3172 | ||
3173 | /* loop through and disable scalers that aren't in use */ | |
3174 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3175 | if (!scaler_state->scalers[i].in_use) |
3176 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3177 | } |
3178 | } | |
3179 | ||
d2196774 VS |
3180 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3181 | unsigned int rotation) | |
3182 | { | |
1b500535 VS |
3183 | u32 stride; |
3184 | ||
3185 | if (plane >= fb->format->num_planes) | |
3186 | return 0; | |
3187 | ||
3188 | stride = intel_fb_pitch(fb, plane, rotation); | |
d2196774 VS |
3189 | |
3190 | /* | |
3191 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3192 | * linear buffers or in number of tiles for tiled buffers. | |
3193 | */ | |
d88c4afd VS |
3194 | if (drm_rotation_90_or_270(rotation)) |
3195 | stride /= intel_tile_height(fb, plane); | |
3196 | else | |
3197 | stride /= intel_fb_stride_alignment(fb, plane); | |
d2196774 VS |
3198 | |
3199 | return stride; | |
3200 | } | |
3201 | ||
2e881264 | 3202 | static u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3203 | { |
6156a456 | 3204 | switch (pixel_format) { |
d161cf7a | 3205 | case DRM_FORMAT_C8: |
c34ce3d1 | 3206 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3207 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3208 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3209 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3210 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3211 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3212 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3213 | /* |
3214 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3215 | * to be already pre-multiplied. We need to add a knob (or a different | |
3216 | * DRM_FORMAT) for user-space to configure that. | |
3217 | */ | |
f75fb42a | 3218 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3219 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3220 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3221 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3222 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3223 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3224 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3225 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3226 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3227 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3228 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3229 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3230 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3231 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3232 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3233 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3234 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3235 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3236 | default: |
4249eeef | 3237 | MISSING_CASE(pixel_format); |
70d21f0e | 3238 | } |
8cfcba41 | 3239 | |
c34ce3d1 | 3240 | return 0; |
6156a456 | 3241 | } |
70d21f0e | 3242 | |
2e881264 | 3243 | static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
6156a456 | 3244 | { |
6156a456 | 3245 | switch (fb_modifier) { |
2f075565 | 3246 | case DRM_FORMAT_MOD_LINEAR: |
70d21f0e | 3247 | break; |
30af77c4 | 3248 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3249 | return PLANE_CTL_TILED_X; |
b321803d | 3250 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3251 | return PLANE_CTL_TILED_Y; |
b321803d | 3252 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3253 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3254 | default: |
6156a456 | 3255 | MISSING_CASE(fb_modifier); |
70d21f0e | 3256 | } |
8cfcba41 | 3257 | |
c34ce3d1 | 3258 | return 0; |
6156a456 | 3259 | } |
70d21f0e | 3260 | |
2e881264 | 3261 | static u32 skl_plane_ctl_rotation(unsigned int rotation) |
6156a456 | 3262 | { |
3b7a5119 | 3263 | switch (rotation) { |
c2c446ad | 3264 | case DRM_MODE_ROTATE_0: |
6156a456 | 3265 | break; |
1e8df167 | 3266 | /* |
c2c446ad | 3267 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr |
1e8df167 SJ |
3268 | * while i915 HW rotation is clockwise, thats why this swapping. |
3269 | */ | |
c2c446ad | 3270 | case DRM_MODE_ROTATE_90: |
1e8df167 | 3271 | return PLANE_CTL_ROTATE_270; |
c2c446ad | 3272 | case DRM_MODE_ROTATE_180: |
c34ce3d1 | 3273 | return PLANE_CTL_ROTATE_180; |
c2c446ad | 3274 | case DRM_MODE_ROTATE_270: |
1e8df167 | 3275 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3276 | default: |
3277 | MISSING_CASE(rotation); | |
3278 | } | |
3279 | ||
c34ce3d1 | 3280 | return 0; |
6156a456 CK |
3281 | } |
3282 | ||
2e881264 VS |
3283 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
3284 | const struct intel_plane_state *plane_state) | |
46f788ba VS |
3285 | { |
3286 | struct drm_i915_private *dev_priv = | |
3287 | to_i915(plane_state->base.plane->dev); | |
3288 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3289 | unsigned int rotation = plane_state->base.rotation; | |
2e881264 | 3290 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
46f788ba VS |
3291 | u32 plane_ctl; |
3292 | ||
3293 | plane_ctl = PLANE_CTL_ENABLE; | |
3294 | ||
6602be0e | 3295 | if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) { |
46f788ba VS |
3296 | plane_ctl |= |
3297 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3298 | PLANE_CTL_PIPE_CSC_ENABLE | | |
3299 | PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3300 | } | |
3301 | ||
3302 | plane_ctl |= skl_plane_ctl_format(fb->format->format); | |
3303 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); | |
3304 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3305 | ||
2e881264 VS |
3306 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
3307 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
3308 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
3309 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
3310 | ||
46f788ba VS |
3311 | return plane_ctl; |
3312 | } | |
3313 | ||
282dbf9b | 3314 | static void skylake_update_primary_plane(struct intel_plane *plane, |
a8d201af ML |
3315 | const struct intel_crtc_state *crtc_state, |
3316 | const struct intel_plane_state *plane_state) | |
6156a456 | 3317 | { |
282dbf9b VS |
3318 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
3319 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3320 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3321 | enum plane_id plane_id = plane->id; | |
3322 | enum pipe pipe = plane->pipe; | |
a0864d59 | 3323 | u32 plane_ctl = plane_state->ctl; |
a8d201af | 3324 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3325 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3326 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3327 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3328 | int src_x = plane_state->main.x; |
3329 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3330 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3331 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3332 | int dst_x = plane_state->base.dst.x1; | |
3333 | int dst_y = plane_state->base.dst.y1; | |
3334 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3335 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
dd584fc0 | 3336 | unsigned long irqflags; |
70d21f0e | 3337 | |
6687c906 VS |
3338 | /* Sizes are 0 based */ |
3339 | src_w--; | |
3340 | src_h--; | |
3341 | dst_w--; | |
3342 | dst_h--; | |
3343 | ||
282dbf9b | 3344 | crtc->dspaddr_offset = surf_addr; |
4c0b8a8b | 3345 | |
282dbf9b VS |
3346 | crtc->adjusted_x = src_x; |
3347 | crtc->adjusted_y = src_y; | |
2db3366b | 3348 | |
dd584fc0 VS |
3349 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3350 | ||
6602be0e | 3351 | if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
dd584fc0 VS |
3352 | I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), |
3353 | PLANE_COLOR_PIPE_GAMMA_ENABLE | | |
3354 | PLANE_COLOR_PIPE_CSC_ENABLE | | |
3355 | PLANE_COLOR_PLANE_GAMMA_DISABLE); | |
78587de2 VS |
3356 | } |
3357 | ||
dd584fc0 VS |
3358 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); |
3359 | I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3360 | I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); | |
3361 | I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
6156a456 CK |
3362 | |
3363 | if (scaler_id >= 0) { | |
3364 | uint32_t ps_ctrl = 0; | |
3365 | ||
3366 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3367 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 | 3368 | crtc_state->scaler_state.scalers[scaler_id].mode; |
dd584fc0 VS |
3369 | I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
3370 | I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3371 | I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3372 | I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3373 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0); | |
6156a456 | 3374 | } else { |
dd584fc0 | 3375 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3376 | } |
3377 | ||
dd584fc0 VS |
3378 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), |
3379 | intel_plane_ggtt_offset(plane_state) + surf_addr); | |
70d21f0e | 3380 | |
dd584fc0 VS |
3381 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); |
3382 | ||
3383 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
70d21f0e DL |
3384 | } |
3385 | ||
282dbf9b VS |
3386 | static void skylake_disable_primary_plane(struct intel_plane *primary, |
3387 | struct intel_crtc *crtc) | |
17638cd6 | 3388 | { |
282dbf9b VS |
3389 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3390 | enum plane_id plane_id = primary->id; | |
3391 | enum pipe pipe = primary->pipe; | |
dd584fc0 VS |
3392 | unsigned long irqflags; |
3393 | ||
3394 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
62e0fb88 | 3395 | |
dd584fc0 VS |
3396 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); |
3397 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); | |
3398 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); | |
3399 | ||
3400 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3401 | } |
29b9bde6 | 3402 | |
73974893 ML |
3403 | static int |
3404 | __intel_display_resume(struct drm_device *dev, | |
581e49fe ML |
3405 | struct drm_atomic_state *state, |
3406 | struct drm_modeset_acquire_ctx *ctx) | |
73974893 ML |
3407 | { |
3408 | struct drm_crtc_state *crtc_state; | |
3409 | struct drm_crtc *crtc; | |
3410 | int i, ret; | |
11c22da6 | 3411 | |
aecd36b8 | 3412 | intel_modeset_setup_hw_state(dev, ctx); |
29b74b7f | 3413 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3414 | |
3415 | if (!state) | |
3416 | return 0; | |
3417 | ||
aa5e9b47 ML |
3418 | /* |
3419 | * We've duplicated the state, pointers to the old state are invalid. | |
3420 | * | |
3421 | * Don't attempt to use the old state until we commit the duplicated state. | |
3422 | */ | |
3423 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { | |
73974893 ML |
3424 | /* |
3425 | * Force recalculation even if we restore | |
3426 | * current state. With fast modeset this may not result | |
3427 | * in a modeset when the state is compatible. | |
3428 | */ | |
3429 | crtc_state->mode_changed = true; | |
96a02917 | 3430 | } |
73974893 ML |
3431 | |
3432 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
602ae835 VS |
3433 | if (!HAS_GMCH_DISPLAY(to_i915(dev))) |
3434 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
73974893 | 3435 | |
581e49fe | 3436 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
73974893 ML |
3437 | |
3438 | WARN_ON(ret == -EDEADLK); | |
3439 | return ret; | |
96a02917 VS |
3440 | } |
3441 | ||
4ac2ba2f VS |
3442 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3443 | { | |
ae98104b VS |
3444 | return intel_has_gpu_reset(dev_priv) && |
3445 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3446 | } |
3447 | ||
c033666a | 3448 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3449 | { |
73974893 ML |
3450 | struct drm_device *dev = &dev_priv->drm; |
3451 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3452 | struct drm_atomic_state *state; | |
3453 | int ret; | |
3454 | ||
ce87ea15 DV |
3455 | |
3456 | /* reset doesn't touch the display */ | |
3457 | if (!i915.force_reset_modeset_test && | |
3458 | !gpu_reset_clobbers_display(dev_priv)) | |
3459 | return; | |
3460 | ||
73974893 ML |
3461 | /* |
3462 | * Need mode_config.mutex so that we don't | |
3463 | * trample ongoing ->detect() and whatnot. | |
3464 | */ | |
3465 | mutex_lock(&dev->mode_config.mutex); | |
3466 | drm_modeset_acquire_init(ctx, 0); | |
3467 | while (1) { | |
3468 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3469 | if (ret != -EDEADLK) | |
3470 | break; | |
3471 | ||
3472 | drm_modeset_backoff(ctx); | |
3473 | } | |
f98ce92f VS |
3474 | /* |
3475 | * Disabling the crtcs gracefully seems nicer. Also the | |
3476 | * g33 docs say we should at least disable all the planes. | |
3477 | */ | |
73974893 ML |
3478 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3479 | if (IS_ERR(state)) { | |
3480 | ret = PTR_ERR(state); | |
73974893 | 3481 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
1e5a15d6 | 3482 | return; |
73974893 ML |
3483 | } |
3484 | ||
3485 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3486 | if (ret) { | |
3487 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
1e5a15d6 ACO |
3488 | drm_atomic_state_put(state); |
3489 | return; | |
73974893 ML |
3490 | } |
3491 | ||
3492 | dev_priv->modeset_restore_state = state; | |
3493 | state->acquire_ctx = ctx; | |
7514747d VS |
3494 | } |
3495 | ||
c033666a | 3496 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3497 | { |
73974893 ML |
3498 | struct drm_device *dev = &dev_priv->drm; |
3499 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3500 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3501 | int ret; | |
3502 | ||
ce87ea15 DV |
3503 | /* reset doesn't touch the display */ |
3504 | if (!i915.force_reset_modeset_test && | |
3505 | !gpu_reset_clobbers_display(dev_priv)) | |
3506 | return; | |
3507 | ||
3508 | if (!state) | |
3509 | goto unlock; | |
3510 | ||
73974893 ML |
3511 | dev_priv->modeset_restore_state = NULL; |
3512 | ||
7514747d | 3513 | /* reset doesn't touch the display */ |
4ac2ba2f | 3514 | if (!gpu_reset_clobbers_display(dev_priv)) { |
ce87ea15 DV |
3515 | /* for testing only restore the display */ |
3516 | ret = __intel_display_resume(dev, state, ctx); | |
522a63de ML |
3517 | if (ret) |
3518 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
73974893 ML |
3519 | } else { |
3520 | /* | |
3521 | * The display has been reset as well, | |
3522 | * so need a full re-initialization. | |
3523 | */ | |
3524 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3525 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3526 | |
51f59205 | 3527 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3528 | intel_modeset_init_hw(dev); |
7514747d | 3529 | |
73974893 ML |
3530 | spin_lock_irq(&dev_priv->irq_lock); |
3531 | if (dev_priv->display.hpd_irq_setup) | |
3532 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3533 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3534 | |
581e49fe | 3535 | ret = __intel_display_resume(dev, state, ctx); |
73974893 ML |
3536 | if (ret) |
3537 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3538 | |
73974893 ML |
3539 | intel_hpd_init(dev_priv); |
3540 | } | |
7514747d | 3541 | |
ce87ea15 DV |
3542 | drm_atomic_state_put(state); |
3543 | unlock: | |
73974893 ML |
3544 | drm_modeset_drop_locks(ctx); |
3545 | drm_modeset_acquire_fini(ctx); | |
3546 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3547 | } |
3548 | ||
bfd16b2a ML |
3549 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3550 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3551 | { |
6315b5d3 | 3552 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3553 | struct intel_crtc_state *pipe_config = |
3554 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3555 | |
bfd16b2a ML |
3556 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3557 | crtc->base.mode = crtc->base.state->mode; | |
3558 | ||
e30e8f75 GP |
3559 | /* |
3560 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3561 | * that in compute_mode_changes we check the native mode (not the pfit | |
3562 | * mode) to see if we can flip rather than do a full mode set. In the | |
3563 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3564 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3565 | * sized surface. | |
e30e8f75 GP |
3566 | */ |
3567 | ||
e30e8f75 | 3568 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3569 | ((pipe_config->pipe_src_w - 1) << 16) | |
3570 | (pipe_config->pipe_src_h - 1)); | |
3571 | ||
3572 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3573 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3574 | skl_detach_scalers(crtc); |
3575 | ||
3576 | if (pipe_config->pch_pfit.enabled) | |
3577 | skylake_pfit_enable(crtc); | |
6e266956 | 3578 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3579 | if (pipe_config->pch_pfit.enabled) |
3580 | ironlake_pfit_enable(crtc); | |
3581 | else if (old_crtc_state->pch_pfit.enabled) | |
3582 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3583 | } |
e30e8f75 GP |
3584 | } |
3585 | ||
4cbe4b2b | 3586 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 3587 | { |
4cbe4b2b | 3588 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3589 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3590 | int pipe = crtc->pipe; |
f0f59a00 VS |
3591 | i915_reg_t reg; |
3592 | u32 temp; | |
5e84e1a4 ZW |
3593 | |
3594 | /* enable normal train */ | |
3595 | reg = FDI_TX_CTL(pipe); | |
3596 | temp = I915_READ(reg); | |
fd6b8f43 | 3597 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3598 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3599 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3600 | } else { |
3601 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3602 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3603 | } |
5e84e1a4 ZW |
3604 | I915_WRITE(reg, temp); |
3605 | ||
3606 | reg = FDI_RX_CTL(pipe); | |
3607 | temp = I915_READ(reg); | |
6e266956 | 3608 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3609 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3610 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3611 | } else { | |
3612 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3613 | temp |= FDI_LINK_TRAIN_NONE; | |
3614 | } | |
3615 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3616 | ||
3617 | /* wait one idle pattern time */ | |
3618 | POSTING_READ(reg); | |
3619 | udelay(1000); | |
357555c0 JB |
3620 | |
3621 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3622 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3623 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3624 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3625 | } |
3626 | ||
8db9d77b | 3627 | /* The FDI link training functions for ILK/Ibexpeak. */ |
dc4a1094 ACO |
3628 | static void ironlake_fdi_link_train(struct intel_crtc *crtc, |
3629 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3630 | { |
4cbe4b2b | 3631 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3632 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3633 | int pipe = crtc->pipe; |
f0f59a00 VS |
3634 | i915_reg_t reg; |
3635 | u32 temp, tries; | |
8db9d77b | 3636 | |
1c8562f6 | 3637 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3638 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3639 | |
e1a44743 AJ |
3640 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3641 | for train result */ | |
5eddb70b CW |
3642 | reg = FDI_RX_IMR(pipe); |
3643 | temp = I915_READ(reg); | |
e1a44743 AJ |
3644 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3645 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3646 | I915_WRITE(reg, temp); |
3647 | I915_READ(reg); | |
e1a44743 AJ |
3648 | udelay(150); |
3649 | ||
8db9d77b | 3650 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3651 | reg = FDI_TX_CTL(pipe); |
3652 | temp = I915_READ(reg); | |
627eb5a3 | 3653 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3654 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3655 | temp &= ~FDI_LINK_TRAIN_NONE; |
3656 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3657 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3658 | |
5eddb70b CW |
3659 | reg = FDI_RX_CTL(pipe); |
3660 | temp = I915_READ(reg); | |
8db9d77b ZW |
3661 | temp &= ~FDI_LINK_TRAIN_NONE; |
3662 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3663 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3664 | ||
3665 | POSTING_READ(reg); | |
8db9d77b ZW |
3666 | udelay(150); |
3667 | ||
5b2adf89 | 3668 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3669 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3670 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3671 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3672 | |
5eddb70b | 3673 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3674 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3675 | temp = I915_READ(reg); |
8db9d77b ZW |
3676 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3677 | ||
3678 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3679 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3680 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3681 | break; |
3682 | } | |
8db9d77b | 3683 | } |
e1a44743 | 3684 | if (tries == 5) |
5eddb70b | 3685 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3686 | |
3687 | /* Train 2 */ | |
5eddb70b CW |
3688 | reg = FDI_TX_CTL(pipe); |
3689 | temp = I915_READ(reg); | |
8db9d77b ZW |
3690 | temp &= ~FDI_LINK_TRAIN_NONE; |
3691 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3692 | I915_WRITE(reg, temp); |
8db9d77b | 3693 | |
5eddb70b CW |
3694 | reg = FDI_RX_CTL(pipe); |
3695 | temp = I915_READ(reg); | |
8db9d77b ZW |
3696 | temp &= ~FDI_LINK_TRAIN_NONE; |
3697 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3698 | I915_WRITE(reg, temp); |
8db9d77b | 3699 | |
5eddb70b CW |
3700 | POSTING_READ(reg); |
3701 | udelay(150); | |
8db9d77b | 3702 | |
5eddb70b | 3703 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3704 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3705 | temp = I915_READ(reg); |
8db9d77b ZW |
3706 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3707 | ||
3708 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3709 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3710 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3711 | break; | |
3712 | } | |
8db9d77b | 3713 | } |
e1a44743 | 3714 | if (tries == 5) |
5eddb70b | 3715 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3716 | |
3717 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3718 | |
8db9d77b ZW |
3719 | } |
3720 | ||
0206e353 | 3721 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3722 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3723 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3724 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3725 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3726 | }; | |
3727 | ||
3728 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
3729 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
3730 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3731 | { |
4cbe4b2b | 3732 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3733 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3734 | int pipe = crtc->pipe; |
f0f59a00 VS |
3735 | i915_reg_t reg; |
3736 | u32 temp, i, retry; | |
8db9d77b | 3737 | |
e1a44743 AJ |
3738 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3739 | for train result */ | |
5eddb70b CW |
3740 | reg = FDI_RX_IMR(pipe); |
3741 | temp = I915_READ(reg); | |
e1a44743 AJ |
3742 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3743 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3744 | I915_WRITE(reg, temp); |
3745 | ||
3746 | POSTING_READ(reg); | |
e1a44743 AJ |
3747 | udelay(150); |
3748 | ||
8db9d77b | 3749 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3750 | reg = FDI_TX_CTL(pipe); |
3751 | temp = I915_READ(reg); | |
627eb5a3 | 3752 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3753 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3754 | temp &= ~FDI_LINK_TRAIN_NONE; |
3755 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3756 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3757 | /* SNB-B */ | |
3758 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3759 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3760 | |
d74cf324 DV |
3761 | I915_WRITE(FDI_RX_MISC(pipe), |
3762 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3763 | ||
5eddb70b CW |
3764 | reg = FDI_RX_CTL(pipe); |
3765 | temp = I915_READ(reg); | |
6e266956 | 3766 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3767 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3768 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3769 | } else { | |
3770 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3771 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3772 | } | |
5eddb70b CW |
3773 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3774 | ||
3775 | POSTING_READ(reg); | |
8db9d77b ZW |
3776 | udelay(150); |
3777 | ||
0206e353 | 3778 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3779 | reg = FDI_TX_CTL(pipe); |
3780 | temp = I915_READ(reg); | |
8db9d77b ZW |
3781 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3782 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3783 | I915_WRITE(reg, temp); |
3784 | ||
3785 | POSTING_READ(reg); | |
8db9d77b ZW |
3786 | udelay(500); |
3787 | ||
fa37d39e SP |
3788 | for (retry = 0; retry < 5; retry++) { |
3789 | reg = FDI_RX_IIR(pipe); | |
3790 | temp = I915_READ(reg); | |
3791 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3792 | if (temp & FDI_RX_BIT_LOCK) { | |
3793 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3794 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3795 | break; | |
3796 | } | |
3797 | udelay(50); | |
8db9d77b | 3798 | } |
fa37d39e SP |
3799 | if (retry < 5) |
3800 | break; | |
8db9d77b ZW |
3801 | } |
3802 | if (i == 4) | |
5eddb70b | 3803 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3804 | |
3805 | /* Train 2 */ | |
5eddb70b CW |
3806 | reg = FDI_TX_CTL(pipe); |
3807 | temp = I915_READ(reg); | |
8db9d77b ZW |
3808 | temp &= ~FDI_LINK_TRAIN_NONE; |
3809 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3810 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3811 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3812 | /* SNB-B */ | |
3813 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3814 | } | |
5eddb70b | 3815 | I915_WRITE(reg, temp); |
8db9d77b | 3816 | |
5eddb70b CW |
3817 | reg = FDI_RX_CTL(pipe); |
3818 | temp = I915_READ(reg); | |
6e266956 | 3819 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3820 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3821 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3822 | } else { | |
3823 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3824 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3825 | } | |
5eddb70b CW |
3826 | I915_WRITE(reg, temp); |
3827 | ||
3828 | POSTING_READ(reg); | |
8db9d77b ZW |
3829 | udelay(150); |
3830 | ||
0206e353 | 3831 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3832 | reg = FDI_TX_CTL(pipe); |
3833 | temp = I915_READ(reg); | |
8db9d77b ZW |
3834 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3835 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3836 | I915_WRITE(reg, temp); |
3837 | ||
3838 | POSTING_READ(reg); | |
8db9d77b ZW |
3839 | udelay(500); |
3840 | ||
fa37d39e SP |
3841 | for (retry = 0; retry < 5; retry++) { |
3842 | reg = FDI_RX_IIR(pipe); | |
3843 | temp = I915_READ(reg); | |
3844 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3845 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3846 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3847 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3848 | break; | |
3849 | } | |
3850 | udelay(50); | |
8db9d77b | 3851 | } |
fa37d39e SP |
3852 | if (retry < 5) |
3853 | break; | |
8db9d77b ZW |
3854 | } |
3855 | if (i == 4) | |
5eddb70b | 3856 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3857 | |
3858 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3859 | } | |
3860 | ||
357555c0 | 3861 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
3862 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
3863 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 3864 | { |
4cbe4b2b | 3865 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3866 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3867 | int pipe = crtc->pipe; |
f0f59a00 VS |
3868 | i915_reg_t reg; |
3869 | u32 temp, i, j; | |
357555c0 JB |
3870 | |
3871 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3872 | for train result */ | |
3873 | reg = FDI_RX_IMR(pipe); | |
3874 | temp = I915_READ(reg); | |
3875 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3876 | temp &= ~FDI_RX_BIT_LOCK; | |
3877 | I915_WRITE(reg, temp); | |
3878 | ||
3879 | POSTING_READ(reg); | |
3880 | udelay(150); | |
3881 | ||
01a415fd DV |
3882 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3883 | I915_READ(FDI_RX_IIR(pipe))); | |
3884 | ||
139ccd3f JB |
3885 | /* Try each vswing and preemphasis setting twice before moving on */ |
3886 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3887 | /* disable first in case we need to retry */ | |
3888 | reg = FDI_TX_CTL(pipe); | |
3889 | temp = I915_READ(reg); | |
3890 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3891 | temp &= ~FDI_TX_ENABLE; | |
3892 | I915_WRITE(reg, temp); | |
357555c0 | 3893 | |
139ccd3f JB |
3894 | reg = FDI_RX_CTL(pipe); |
3895 | temp = I915_READ(reg); | |
3896 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3897 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3898 | temp &= ~FDI_RX_ENABLE; | |
3899 | I915_WRITE(reg, temp); | |
357555c0 | 3900 | |
139ccd3f | 3901 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3902 | reg = FDI_TX_CTL(pipe); |
3903 | temp = I915_READ(reg); | |
139ccd3f | 3904 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3905 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 3906 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3907 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3908 | temp |= snb_b_fdi_train_param[j/2]; |
3909 | temp |= FDI_COMPOSITE_SYNC; | |
3910 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3911 | |
139ccd3f JB |
3912 | I915_WRITE(FDI_RX_MISC(pipe), |
3913 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3914 | |
139ccd3f | 3915 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3916 | temp = I915_READ(reg); |
139ccd3f JB |
3917 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3918 | temp |= FDI_COMPOSITE_SYNC; | |
3919 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3920 | |
139ccd3f JB |
3921 | POSTING_READ(reg); |
3922 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3923 | |
139ccd3f JB |
3924 | for (i = 0; i < 4; i++) { |
3925 | reg = FDI_RX_IIR(pipe); | |
3926 | temp = I915_READ(reg); | |
3927 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3928 | |
139ccd3f JB |
3929 | if (temp & FDI_RX_BIT_LOCK || |
3930 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3931 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3932 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3933 | i); | |
3934 | break; | |
3935 | } | |
3936 | udelay(1); /* should be 0.5us */ | |
3937 | } | |
3938 | if (i == 4) { | |
3939 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3940 | continue; | |
3941 | } | |
357555c0 | 3942 | |
139ccd3f | 3943 | /* Train 2 */ |
357555c0 JB |
3944 | reg = FDI_TX_CTL(pipe); |
3945 | temp = I915_READ(reg); | |
139ccd3f JB |
3946 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3947 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3948 | I915_WRITE(reg, temp); | |
3949 | ||
3950 | reg = FDI_RX_CTL(pipe); | |
3951 | temp = I915_READ(reg); | |
3952 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3953 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3954 | I915_WRITE(reg, temp); |
3955 | ||
3956 | POSTING_READ(reg); | |
139ccd3f | 3957 | udelay(2); /* should be 1.5us */ |
357555c0 | 3958 | |
139ccd3f JB |
3959 | for (i = 0; i < 4; i++) { |
3960 | reg = FDI_RX_IIR(pipe); | |
3961 | temp = I915_READ(reg); | |
3962 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3963 | |
139ccd3f JB |
3964 | if (temp & FDI_RX_SYMBOL_LOCK || |
3965 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3966 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3967 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3968 | i); | |
3969 | goto train_done; | |
3970 | } | |
3971 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3972 | } |
139ccd3f JB |
3973 | if (i == 4) |
3974 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3975 | } |
357555c0 | 3976 | |
139ccd3f | 3977 | train_done: |
357555c0 JB |
3978 | DRM_DEBUG_KMS("FDI train done.\n"); |
3979 | } | |
3980 | ||
88cefb6c | 3981 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3982 | { |
88cefb6c | 3983 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 3984 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 3985 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3986 | i915_reg_t reg; |
3987 | u32 temp; | |
c64e311e | 3988 | |
c98e9dcf | 3989 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3990 | reg = FDI_RX_CTL(pipe); |
3991 | temp = I915_READ(reg); | |
627eb5a3 | 3992 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3993 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3994 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3995 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3996 | ||
3997 | POSTING_READ(reg); | |
c98e9dcf JB |
3998 | udelay(200); |
3999 | ||
4000 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4001 | temp = I915_READ(reg); |
4002 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4003 | ||
4004 | POSTING_READ(reg); | |
c98e9dcf JB |
4005 | udelay(200); |
4006 | ||
20749730 PZ |
4007 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4008 | reg = FDI_TX_CTL(pipe); | |
4009 | temp = I915_READ(reg); | |
4010 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4011 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4012 | |
20749730 PZ |
4013 | POSTING_READ(reg); |
4014 | udelay(100); | |
6be4a607 | 4015 | } |
0e23b99d JB |
4016 | } |
4017 | ||
88cefb6c DV |
4018 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4019 | { | |
4020 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4021 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4022 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4023 | i915_reg_t reg; |
4024 | u32 temp; | |
88cefb6c DV |
4025 | |
4026 | /* Switch from PCDclk to Rawclk */ | |
4027 | reg = FDI_RX_CTL(pipe); | |
4028 | temp = I915_READ(reg); | |
4029 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4030 | ||
4031 | /* Disable CPU FDI TX PLL */ | |
4032 | reg = FDI_TX_CTL(pipe); | |
4033 | temp = I915_READ(reg); | |
4034 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4035 | ||
4036 | POSTING_READ(reg); | |
4037 | udelay(100); | |
4038 | ||
4039 | reg = FDI_RX_CTL(pipe); | |
4040 | temp = I915_READ(reg); | |
4041 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4042 | ||
4043 | /* Wait for the clocks to turn off. */ | |
4044 | POSTING_READ(reg); | |
4045 | udelay(100); | |
4046 | } | |
4047 | ||
0fc932b8 JB |
4048 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4049 | { | |
4050 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4051 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4052 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4053 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4054 | i915_reg_t reg; |
4055 | u32 temp; | |
0fc932b8 JB |
4056 | |
4057 | /* disable CPU FDI tx and PCH FDI rx */ | |
4058 | reg = FDI_TX_CTL(pipe); | |
4059 | temp = I915_READ(reg); | |
4060 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4061 | POSTING_READ(reg); | |
4062 | ||
4063 | reg = FDI_RX_CTL(pipe); | |
4064 | temp = I915_READ(reg); | |
4065 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4066 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4067 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4068 | ||
4069 | POSTING_READ(reg); | |
4070 | udelay(100); | |
4071 | ||
4072 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4073 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4074 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4075 | |
4076 | /* still set train pattern 1 */ | |
4077 | reg = FDI_TX_CTL(pipe); | |
4078 | temp = I915_READ(reg); | |
4079 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4080 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4081 | I915_WRITE(reg, temp); | |
4082 | ||
4083 | reg = FDI_RX_CTL(pipe); | |
4084 | temp = I915_READ(reg); | |
6e266956 | 4085 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4086 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4087 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4088 | } else { | |
4089 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4090 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4091 | } | |
4092 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4093 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4094 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4095 | I915_WRITE(reg, temp); |
4096 | ||
4097 | POSTING_READ(reg); | |
4098 | udelay(100); | |
4099 | } | |
4100 | ||
49d73912 | 4101 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 | 4102 | { |
fa05887a DV |
4103 | struct drm_crtc *crtc; |
4104 | bool cleanup_done; | |
4105 | ||
4106 | drm_for_each_crtc(crtc, &dev_priv->drm) { | |
4107 | struct drm_crtc_commit *commit; | |
4108 | spin_lock(&crtc->commit_lock); | |
4109 | commit = list_first_entry_or_null(&crtc->commit_list, | |
4110 | struct drm_crtc_commit, commit_entry); | |
4111 | cleanup_done = commit ? | |
4112 | try_wait_for_completion(&commit->cleanup_done) : true; | |
4113 | spin_unlock(&crtc->commit_lock); | |
4114 | ||
4115 | if (cleanup_done) | |
5dce5b93 CW |
4116 | continue; |
4117 | ||
fa05887a | 4118 | drm_crtc_wait_one_vblank(crtc); |
5dce5b93 CW |
4119 | |
4120 | return true; | |
4121 | } | |
4122 | ||
4123 | return false; | |
4124 | } | |
4125 | ||
b7076546 | 4126 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4127 | { |
4128 | u32 temp; | |
4129 | ||
4130 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4131 | ||
4132 | mutex_lock(&dev_priv->sb_lock); | |
4133 | ||
4134 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4135 | temp |= SBI_SSCCTL_DISABLE; | |
4136 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4137 | ||
4138 | mutex_unlock(&dev_priv->sb_lock); | |
4139 | } | |
4140 | ||
e615efe4 | 4141 | /* Program iCLKIP clock to the desired frequency */ |
0dcdc382 | 4142 | static void lpt_program_iclkip(struct intel_crtc *crtc) |
e615efe4 | 4143 | { |
0dcdc382 ACO |
4144 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4145 | int clock = crtc->config->base.adjusted_mode.crtc_clock; | |
e615efe4 ED |
4146 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4147 | u32 temp; | |
4148 | ||
060f02d8 | 4149 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4150 | |
64b46a06 VS |
4151 | /* The iCLK virtual clock root frequency is in MHz, |
4152 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4153 | * divisors, it is necessary to divide one by another, so we | |
4154 | * convert the virtual clock precision to KHz here for higher | |
4155 | * precision. | |
4156 | */ | |
4157 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4158 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4159 | u32 iclk_pi_range = 64; | |
64b46a06 | 4160 | u32 desired_divisor; |
e615efe4 | 4161 | |
64b46a06 VS |
4162 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4163 | clock << auxdiv); | |
4164 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4165 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4166 | |
64b46a06 VS |
4167 | /* |
4168 | * Near 20MHz is a corner case which is | |
4169 | * out of range for the 7-bit divisor | |
4170 | */ | |
4171 | if (divsel <= 0x7f) | |
4172 | break; | |
e615efe4 ED |
4173 | } |
4174 | ||
4175 | /* This should not happen with any sane values */ | |
4176 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4177 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4178 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4179 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4180 | ||
4181 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4182 | clock, |
e615efe4 ED |
4183 | auxdiv, |
4184 | divsel, | |
4185 | phasedir, | |
4186 | phaseinc); | |
4187 | ||
060f02d8 VS |
4188 | mutex_lock(&dev_priv->sb_lock); |
4189 | ||
e615efe4 | 4190 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4191 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4192 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4193 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4194 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4195 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4196 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4197 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4198 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4199 | |
4200 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4201 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4202 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4203 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4204 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4205 | |
4206 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4207 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4208 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4209 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4210 | |
060f02d8 VS |
4211 | mutex_unlock(&dev_priv->sb_lock); |
4212 | ||
e615efe4 ED |
4213 | /* Wait for initialization time */ |
4214 | udelay(24); | |
4215 | ||
4216 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4217 | } | |
4218 | ||
8802e5b6 VS |
4219 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4220 | { | |
4221 | u32 divsel, phaseinc, auxdiv; | |
4222 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4223 | u32 iclk_pi_range = 64; | |
4224 | u32 desired_divisor; | |
4225 | u32 temp; | |
4226 | ||
4227 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4228 | return 0; | |
4229 | ||
4230 | mutex_lock(&dev_priv->sb_lock); | |
4231 | ||
4232 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4233 | if (temp & SBI_SSCCTL_DISABLE) { | |
4234 | mutex_unlock(&dev_priv->sb_lock); | |
4235 | return 0; | |
4236 | } | |
4237 | ||
4238 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4239 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4240 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4241 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4242 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4243 | ||
4244 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4245 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4246 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4247 | ||
4248 | mutex_unlock(&dev_priv->sb_lock); | |
4249 | ||
4250 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4251 | ||
4252 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4253 | desired_divisor << auxdiv); | |
4254 | } | |
4255 | ||
275f01b2 DV |
4256 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4257 | enum pipe pch_transcoder) | |
4258 | { | |
4259 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4260 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4261 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4262 | |
4263 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4264 | I915_READ(HTOTAL(cpu_transcoder))); | |
4265 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4266 | I915_READ(HBLANK(cpu_transcoder))); | |
4267 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4268 | I915_READ(HSYNC(cpu_transcoder))); | |
4269 | ||
4270 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4271 | I915_READ(VTOTAL(cpu_transcoder))); | |
4272 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4273 | I915_READ(VBLANK(cpu_transcoder))); | |
4274 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4275 | I915_READ(VSYNC(cpu_transcoder))); | |
4276 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4277 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4278 | } | |
4279 | ||
003632d9 | 4280 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4281 | { |
fac5e23e | 4282 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4283 | uint32_t temp; |
4284 | ||
4285 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4286 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4287 | return; |
4288 | ||
4289 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4290 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4291 | ||
003632d9 ACO |
4292 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4293 | if (enable) | |
4294 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4295 | ||
4296 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4297 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4298 | POSTING_READ(SOUTH_CHICKEN1); | |
4299 | } | |
4300 | ||
4301 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4302 | { | |
4303 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4304 | |
4305 | switch (intel_crtc->pipe) { | |
4306 | case PIPE_A: | |
4307 | break; | |
4308 | case PIPE_B: | |
6e3c9717 | 4309 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4310 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4311 | else |
003632d9 | 4312 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4313 | |
4314 | break; | |
4315 | case PIPE_C: | |
003632d9 | 4316 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4317 | |
4318 | break; | |
4319 | default: | |
4320 | BUG(); | |
4321 | } | |
4322 | } | |
4323 | ||
c48b5305 VS |
4324 | /* Return which DP Port should be selected for Transcoder DP control */ |
4325 | static enum port | |
4cbe4b2b | 4326 | intel_trans_dp_port_sel(struct intel_crtc *crtc) |
c48b5305 | 4327 | { |
4cbe4b2b | 4328 | struct drm_device *dev = crtc->base.dev; |
c48b5305 VS |
4329 | struct intel_encoder *encoder; |
4330 | ||
4cbe4b2b | 4331 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
cca0502b | 4332 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4333 | encoder->type == INTEL_OUTPUT_EDP) |
4334 | return enc_to_dig_port(&encoder->base)->port; | |
4335 | } | |
4336 | ||
4337 | return -1; | |
4338 | } | |
4339 | ||
f67a559d JB |
4340 | /* |
4341 | * Enable PCH resources required for PCH ports: | |
4342 | * - PCH PLLs | |
4343 | * - FDI training & RX/TX | |
4344 | * - update transcoder timings | |
4345 | * - DP transcoding bits | |
4346 | * - transcoder | |
4347 | */ | |
2ce42273 | 4348 | static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) |
0e23b99d | 4349 | { |
2ce42273 | 4350 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
4cbe4b2b | 4351 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4352 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4353 | int pipe = crtc->pipe; |
f0f59a00 | 4354 | u32 temp; |
2c07245f | 4355 | |
ab9412ba | 4356 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4357 | |
fd6b8f43 | 4358 | if (IS_IVYBRIDGE(dev_priv)) |
4cbe4b2b | 4359 | ivybridge_update_fdi_bc_bifurcation(crtc); |
1fbc0d78 | 4360 | |
cd986abb DV |
4361 | /* Write the TU size bits before fdi link training, so that error |
4362 | * detection works. */ | |
4363 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4364 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4365 | ||
c98e9dcf | 4366 | /* For PCH output, training FDI link */ |
dc4a1094 | 4367 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 4368 | |
3ad8a208 DV |
4369 | /* We need to program the right clock selection before writing the pixel |
4370 | * mutliplier into the DPLL. */ | |
6e266956 | 4371 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4372 | u32 sel; |
4b645f14 | 4373 | |
c98e9dcf | 4374 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4375 | temp |= TRANS_DPLL_ENABLE(pipe); |
4376 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 4377 | if (crtc_state->shared_dpll == |
8106ddbd | 4378 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
4379 | temp |= sel; |
4380 | else | |
4381 | temp &= ~sel; | |
c98e9dcf | 4382 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4383 | } |
5eddb70b | 4384 | |
3ad8a208 DV |
4385 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4386 | * transcoder, and we actually should do this to not upset any PCH | |
4387 | * transcoder that already use the clock when we share it. | |
4388 | * | |
4389 | * Note that enable_shared_dpll tries to do the right thing, but | |
4390 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4391 | * the right LVDS enable sequence. */ | |
4cbe4b2b | 4392 | intel_enable_shared_dpll(crtc); |
3ad8a208 | 4393 | |
d9b6cb56 JB |
4394 | /* set transcoder timing, panel must allow it */ |
4395 | assert_panel_unlocked(dev_priv, pipe); | |
4cbe4b2b | 4396 | ironlake_pch_transcoder_set_timings(crtc, pipe); |
8db9d77b | 4397 | |
303b81e0 | 4398 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4399 | |
c98e9dcf | 4400 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 4401 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 4402 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 4403 | const struct drm_display_mode *adjusted_mode = |
2ce42273 | 4404 | &crtc_state->base.adjusted_mode; |
dfd07d72 | 4405 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4406 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4407 | temp = I915_READ(reg); |
4408 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4409 | TRANS_DP_SYNC_MASK | |
4410 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4411 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4412 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4413 | |
9c4edaee | 4414 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4415 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4416 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4417 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4418 | |
4419 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4420 | case PORT_B: |
5eddb70b | 4421 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4422 | break; |
c48b5305 | 4423 | case PORT_C: |
5eddb70b | 4424 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4425 | break; |
c48b5305 | 4426 | case PORT_D: |
5eddb70b | 4427 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4428 | break; |
4429 | default: | |
e95d41e1 | 4430 | BUG(); |
32f9d658 | 4431 | } |
2c07245f | 4432 | |
5eddb70b | 4433 | I915_WRITE(reg, temp); |
6be4a607 | 4434 | } |
b52eb4dc | 4435 | |
b8a4f404 | 4436 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4437 | } |
4438 | ||
2ce42273 | 4439 | static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 4440 | { |
2ce42273 | 4441 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
0dcdc382 | 4442 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 4443 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 4444 | |
a2196033 | 4445 | assert_pch_transcoder_disabled(dev_priv, PIPE_A); |
1507e5bd | 4446 | |
8c52b5e8 | 4447 | lpt_program_iclkip(crtc); |
1507e5bd | 4448 | |
0540e488 | 4449 | /* Set transcoder timing. */ |
0dcdc382 | 4450 | ironlake_pch_transcoder_set_timings(crtc, PIPE_A); |
1507e5bd | 4451 | |
937bb610 | 4452 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4453 | } |
4454 | ||
a1520318 | 4455 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4456 | { |
fac5e23e | 4457 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4458 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4459 | u32 temp; |
4460 | ||
4461 | temp = I915_READ(dslreg); | |
4462 | udelay(500); | |
4463 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4464 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4465 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4466 | } |
4467 | } | |
4468 | ||
86adf9d7 ML |
4469 | static int |
4470 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
d96a7d2a | 4471 | unsigned int scaler_user, int *scaler_id, |
86adf9d7 | 4472 | int src_w, int src_h, int dst_w, int dst_h) |
a1b2278e | 4473 | { |
86adf9d7 ML |
4474 | struct intel_crtc_scaler_state *scaler_state = |
4475 | &crtc_state->scaler_state; | |
4476 | struct intel_crtc *intel_crtc = | |
4477 | to_intel_crtc(crtc_state->base.crtc); | |
7f58cbb1 MK |
4478 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
4479 | const struct drm_display_mode *adjusted_mode = | |
4480 | &crtc_state->base.adjusted_mode; | |
a1b2278e | 4481 | int need_scaling; |
6156a456 | 4482 | |
d96a7d2a VS |
4483 | /* |
4484 | * Src coordinates are already rotated by 270 degrees for | |
4485 | * the 90/270 degree plane rotation cases (to match the | |
4486 | * GTT mapping), hence no need to account for rotation here. | |
4487 | */ | |
4488 | need_scaling = src_w != dst_w || src_h != dst_h; | |
a1b2278e | 4489 | |
7f58cbb1 MK |
4490 | /* |
4491 | * Scaling/fitting not supported in IF-ID mode in GEN9+ | |
4492 | * TODO: Interlace fetch mode doesn't support YUV420 planar formats. | |
4493 | * Once NV12 is enabled, handle it here while allocating scaler | |
4494 | * for NV12. | |
4495 | */ | |
4496 | if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && | |
4497 | need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4498 | DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n"); | |
4499 | return -EINVAL; | |
4500 | } | |
4501 | ||
a1b2278e CK |
4502 | /* |
4503 | * if plane is being disabled or scaler is no more required or force detach | |
4504 | * - free scaler binded to this plane/crtc | |
4505 | * - in order to do this, update crtc->scaler_usage | |
4506 | * | |
4507 | * Here scaler state in crtc_state is set free so that | |
4508 | * scaler can be assigned to other user. Actual register | |
4509 | * update to free the scaler is done in plane/panel-fit programming. | |
4510 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4511 | */ | |
86adf9d7 | 4512 | if (force_detach || !need_scaling) { |
a1b2278e | 4513 | if (*scaler_id >= 0) { |
86adf9d7 | 4514 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4515 | scaler_state->scalers[*scaler_id].in_use = 0; |
4516 | ||
86adf9d7 ML |
4517 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4518 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4519 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4520 | scaler_state->scaler_users); |
4521 | *scaler_id = -1; | |
4522 | } | |
4523 | return 0; | |
4524 | } | |
4525 | ||
4526 | /* range checks */ | |
4527 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4528 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4529 | ||
4530 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4531 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4532 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4533 | "size is out of scaler range\n", |
86adf9d7 | 4534 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4535 | return -EINVAL; |
4536 | } | |
4537 | ||
86adf9d7 ML |
4538 | /* mark this plane as a scaler user in crtc_state */ |
4539 | scaler_state->scaler_users |= (1 << scaler_user); | |
4540 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4541 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4542 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4543 | scaler_state->scaler_users); | |
4544 | ||
4545 | return 0; | |
4546 | } | |
4547 | ||
4548 | /** | |
4549 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4550 | * | |
4551 | * @state: crtc's scaler state | |
86adf9d7 ML |
4552 | * |
4553 | * Return | |
4554 | * 0 - scaler_usage updated successfully | |
4555 | * error - requested scaling cannot be supported or other error condition | |
4556 | */ | |
e435d6e5 | 4557 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4558 | { |
7c5f93b0 | 4559 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4560 | |
e435d6e5 | 4561 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
d96a7d2a | 4562 | &state->scaler_state.scaler_id, |
86adf9d7 | 4563 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4564 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4565 | } |
4566 | ||
4567 | /** | |
4568 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4569 | * | |
4570 | * @state: crtc's scaler state | |
86adf9d7 ML |
4571 | * @plane_state: atomic plane state to update |
4572 | * | |
4573 | * Return | |
4574 | * 0 - scaler_usage updated successfully | |
4575 | * error - requested scaling cannot be supported or other error condition | |
4576 | */ | |
da20eabd ML |
4577 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4578 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4579 | { |
4580 | ||
da20eabd ML |
4581 | struct intel_plane *intel_plane = |
4582 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4583 | struct drm_framebuffer *fb = plane_state->base.fb; |
4584 | int ret; | |
4585 | ||
936e71e3 | 4586 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4587 | |
86adf9d7 ML |
4588 | ret = skl_update_scaler(crtc_state, force_detach, |
4589 | drm_plane_index(&intel_plane->base), | |
4590 | &plane_state->scaler_id, | |
936e71e3 VS |
4591 | drm_rect_width(&plane_state->base.src) >> 16, |
4592 | drm_rect_height(&plane_state->base.src) >> 16, | |
4593 | drm_rect_width(&plane_state->base.dst), | |
4594 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4595 | |
4596 | if (ret || plane_state->scaler_id < 0) | |
4597 | return ret; | |
4598 | ||
a1b2278e | 4599 | /* check colorkey */ |
818ed961 | 4600 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4601 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4602 | intel_plane->base.base.id, | |
4603 | intel_plane->base.name); | |
a1b2278e CK |
4604 | return -EINVAL; |
4605 | } | |
4606 | ||
4607 | /* Check src format */ | |
438b74a5 | 4608 | switch (fb->format->format) { |
86adf9d7 ML |
4609 | case DRM_FORMAT_RGB565: |
4610 | case DRM_FORMAT_XBGR8888: | |
4611 | case DRM_FORMAT_XRGB8888: | |
4612 | case DRM_FORMAT_ABGR8888: | |
4613 | case DRM_FORMAT_ARGB8888: | |
4614 | case DRM_FORMAT_XRGB2101010: | |
4615 | case DRM_FORMAT_XBGR2101010: | |
4616 | case DRM_FORMAT_YUYV: | |
4617 | case DRM_FORMAT_YVYU: | |
4618 | case DRM_FORMAT_UYVY: | |
4619 | case DRM_FORMAT_VYUY: | |
4620 | break; | |
4621 | default: | |
72660ce0 VS |
4622 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4623 | intel_plane->base.base.id, intel_plane->base.name, | |
438b74a5 | 4624 | fb->base.id, fb->format->format); |
86adf9d7 | 4625 | return -EINVAL; |
a1b2278e CK |
4626 | } |
4627 | ||
a1b2278e CK |
4628 | return 0; |
4629 | } | |
4630 | ||
e435d6e5 ML |
4631 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4632 | { | |
4633 | int i; | |
4634 | ||
4635 | for (i = 0; i < crtc->num_scalers; i++) | |
4636 | skl_detach_scaler(crtc, i); | |
4637 | } | |
4638 | ||
4639 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4640 | { |
4641 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4642 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4643 | int pipe = crtc->pipe; |
a1b2278e CK |
4644 | struct intel_crtc_scaler_state *scaler_state = |
4645 | &crtc->config->scaler_state; | |
4646 | ||
6e3c9717 | 4647 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4648 | int id; |
4649 | ||
c3f8ad57 | 4650 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) |
a1b2278e | 4651 | return; |
a1b2278e CK |
4652 | |
4653 | id = scaler_state->scaler_id; | |
4654 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4655 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4656 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4657 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4658 | } |
4659 | } | |
4660 | ||
b074cec8 JB |
4661 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4662 | { | |
4663 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4664 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4665 | int pipe = crtc->pipe; |
4666 | ||
6e3c9717 | 4667 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4668 | /* Force use of hard-coded filter coefficients |
4669 | * as some pre-programmed values are broken, | |
4670 | * e.g. x201. | |
4671 | */ | |
fd6b8f43 | 4672 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4673 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4674 | PF_PIPE_SEL_IVB(pipe)); | |
4675 | else | |
4676 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4677 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4678 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4679 | } |
4680 | } | |
4681 | ||
20bc8673 | 4682 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4683 | { |
cea165c3 | 4684 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4685 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4686 | |
6e3c9717 | 4687 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4688 | return; |
4689 | ||
307e4498 ML |
4690 | /* |
4691 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4692 | * This function is called from post_plane_update, which is run after | |
4693 | * a vblank wait. | |
4694 | */ | |
cea165c3 | 4695 | |
d77e4531 | 4696 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4697 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4698 | mutex_lock(&dev_priv->rps.hw_lock); |
4699 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4700 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4701 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4702 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4703 | * mailbox." Moreover, the mailbox may return a bogus state, |
4704 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4705 | */ |
4706 | } else { | |
4707 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4708 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4709 | * is essentially intel_wait_for_vblank. If we don't have this | |
4710 | * and don't wait for vblanks until the end of crtc_enable, then | |
4711 | * the HW state readout code will complain that the expected | |
4712 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4713 | if (intel_wait_for_register(dev_priv, |
4714 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4715 | 50)) | |
2a114cc1 BW |
4716 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4717 | } | |
d77e4531 PZ |
4718 | } |
4719 | ||
20bc8673 | 4720 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4721 | { |
4722 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4723 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4724 | |
6e3c9717 | 4725 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4726 | return; |
4727 | ||
4728 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4729 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4730 | mutex_lock(&dev_priv->rps.hw_lock); |
4731 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4732 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4733 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4734 | if (intel_wait_for_register(dev_priv, |
4735 | IPS_CTL, IPS_ENABLE, 0, | |
4736 | 42)) | |
23d0b130 | 4737 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4738 | } else { |
2a114cc1 | 4739 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4740 | POSTING_READ(IPS_CTL); |
4741 | } | |
d77e4531 PZ |
4742 | |
4743 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4744 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4745 | } |
4746 | ||
7cac945f | 4747 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4748 | { |
7cac945f | 4749 | if (intel_crtc->overlay) { |
d3eedb1a | 4750 | struct drm_device *dev = intel_crtc->base.dev; |
d3eedb1a VS |
4751 | |
4752 | mutex_lock(&dev->struct_mutex); | |
d3eedb1a | 4753 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
d3eedb1a VS |
4754 | mutex_unlock(&dev->struct_mutex); |
4755 | } | |
4756 | ||
4757 | /* Let userspace switch the overlay on again. In most cases userspace | |
4758 | * has to recompute where to put it anyway. | |
4759 | */ | |
4760 | } | |
4761 | ||
87d4300a ML |
4762 | /** |
4763 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4764 | * @crtc: the CRTC whose primary plane was just enabled | |
4765 | * | |
4766 | * Performs potentially sleeping operations that must be done after the primary | |
4767 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4768 | * called due to an explicit primary plane update, or due to an implicit | |
4769 | * re-enable that is caused when a sprite plane is updated to no longer | |
4770 | * completely hide the primary plane. | |
4771 | */ | |
4772 | static void | |
4773 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4774 | { |
4775 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4776 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4778 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4779 | |
87d4300a ML |
4780 | /* |
4781 | * FIXME IPS should be fine as long as one plane is | |
4782 | * enabled, but in practice it seems to have problems | |
4783 | * when going from primary only to sprite only and vice | |
4784 | * versa. | |
4785 | */ | |
a5c4d7bc VS |
4786 | hsw_enable_ips(intel_crtc); |
4787 | ||
f99d7069 | 4788 | /* |
87d4300a ML |
4789 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4790 | * So don't enable underrun reporting before at least some planes | |
4791 | * are enabled. | |
4792 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4793 | * but leave the pipe running. | |
f99d7069 | 4794 | */ |
5db94019 | 4795 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4796 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4797 | ||
aca7b684 VS |
4798 | /* Underruns don't always raise interrupts, so check manually. */ |
4799 | intel_check_cpu_fifo_underruns(dev_priv); | |
4800 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4801 | } |
4802 | ||
2622a081 | 4803 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4804 | static void |
4805 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4806 | { |
4807 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4808 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4809 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4810 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4811 | |
87d4300a ML |
4812 | /* |
4813 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4814 | * So diasble underrun reporting before all the planes get disabled. | |
4815 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4816 | * but leave the pipe running. | |
4817 | */ | |
5db94019 | 4818 | if (IS_GEN2(dev_priv)) |
87d4300a | 4819 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 4820 | |
2622a081 VS |
4821 | /* |
4822 | * FIXME IPS should be fine as long as one plane is | |
4823 | * enabled, but in practice it seems to have problems | |
4824 | * when going from primary only to sprite only and vice | |
4825 | * versa. | |
4826 | */ | |
4827 | hsw_disable_ips(intel_crtc); | |
4828 | } | |
4829 | ||
4830 | /* FIXME get rid of this and use pre_plane_update */ | |
4831 | static void | |
4832 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4833 | { | |
4834 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4835 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4836 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4837 | int pipe = intel_crtc->pipe; | |
4838 | ||
4839 | intel_pre_disable_primary(crtc); | |
4840 | ||
87d4300a ML |
4841 | /* |
4842 | * Vblank time updates from the shadow to live plane control register | |
4843 | * are blocked if the memory self-refresh mode is active at that | |
4844 | * moment. So to make sure the plane gets truly disabled, disable | |
4845 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4846 | * will be checked/applied by the HW only at the next frame start | |
4847 | * event which is after the vblank start event, so we need to have a | |
4848 | * wait-for-vblank between disabling the plane and the pipe. | |
4849 | */ | |
11a85d6a VS |
4850 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4851 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 4852 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
4853 | } |
4854 | ||
5a21b665 DV |
4855 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4856 | { | |
4857 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4858 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4859 | struct intel_crtc_state *pipe_config = | |
4860 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
4861 | struct drm_plane *primary = crtc->base.primary; |
4862 | struct drm_plane_state *old_pri_state = | |
4863 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4864 | ||
5748b6a1 | 4865 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 | 4866 | |
5a21b665 | 4867 | if (pipe_config->update_wm_post && pipe_config->base.active) |
432081bc | 4868 | intel_update_watermarks(crtc); |
5a21b665 DV |
4869 | |
4870 | if (old_pri_state) { | |
4871 | struct intel_plane_state *primary_state = | |
4872 | to_intel_plane_state(primary->state); | |
4873 | struct intel_plane_state *old_primary_state = | |
4874 | to_intel_plane_state(old_pri_state); | |
4875 | ||
4876 | intel_fbc_post_update(crtc); | |
4877 | ||
936e71e3 | 4878 | if (primary_state->base.visible && |
5a21b665 | 4879 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 4880 | !old_primary_state->base.visible)) |
5a21b665 DV |
4881 | intel_post_enable_primary(&crtc->base); |
4882 | } | |
4883 | } | |
4884 | ||
aa5e9b47 ML |
4885 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, |
4886 | struct intel_crtc_state *pipe_config) | |
ac21b225 | 4887 | { |
5c74cd73 | 4888 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4889 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4890 | struct drm_i915_private *dev_priv = to_i915(dev); |
5c74cd73 ML |
4891 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4892 | struct drm_plane *primary = crtc->base.primary; | |
4893 | struct drm_plane_state *old_pri_state = | |
4894 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4895 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
4896 | struct intel_atomic_state *old_intel_state = |
4897 | to_intel_atomic_state(old_state); | |
ac21b225 | 4898 | |
5c74cd73 ML |
4899 | if (old_pri_state) { |
4900 | struct intel_plane_state *primary_state = | |
4901 | to_intel_plane_state(primary->state); | |
4902 | struct intel_plane_state *old_primary_state = | |
4903 | to_intel_plane_state(old_pri_state); | |
4904 | ||
faf68d92 | 4905 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 4906 | |
936e71e3 VS |
4907 | if (old_primary_state->base.visible && |
4908 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
4909 | intel_pre_disable_primary(&crtc->base); |
4910 | } | |
852eb00d | 4911 | |
5eeb798b VS |
4912 | /* |
4913 | * Vblank time updates from the shadow to live plane control register | |
4914 | * are blocked if the memory self-refresh mode is active at that | |
4915 | * moment. So to make sure the plane gets truly disabled, disable | |
4916 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4917 | * will be checked/applied by the HW only at the next frame start | |
4918 | * event which is after the vblank start event, so we need to have a | |
4919 | * wait-for-vblank between disabling the plane and the pipe. | |
4920 | */ | |
4921 | if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active && | |
4922 | pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) | |
4923 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
92826fcd | 4924 | |
ed4a6a7c MR |
4925 | /* |
4926 | * IVB workaround: must disable low power watermarks for at least | |
4927 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4928 | * when scaling is disabled. | |
4929 | * | |
4930 | * WaCxSRDisabledForSpriteScaling:ivb | |
4931 | */ | |
ddd2b792 | 4932 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 4933 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
4934 | |
4935 | /* | |
4936 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4937 | * watermark programming here. | |
4938 | */ | |
4939 | if (needs_modeset(&pipe_config->base)) | |
4940 | return; | |
4941 | ||
4942 | /* | |
4943 | * For platforms that support atomic watermarks, program the | |
4944 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4945 | * will be the intermediate values that are safe for both pre- and | |
4946 | * post- vblank; when vblank happens, the 'active' values will be set | |
4947 | * to the final 'target' values and we'll do this again to get the | |
4948 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4949 | * will be the final target values which will get automatically latched | |
4950 | * at vblank time; no further programming will be necessary. | |
4951 | * | |
4952 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4953 | * we'll continue to update watermarks the old way, if flags tell | |
4954 | * us to. | |
4955 | */ | |
4956 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
4957 | dev_priv->display.initial_watermarks(old_intel_state, |
4958 | pipe_config); | |
caed361d | 4959 | else if (pipe_config->update_wm_pre) |
432081bc | 4960 | intel_update_watermarks(crtc); |
ac21b225 ML |
4961 | } |
4962 | ||
d032ffa0 | 4963 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4964 | { |
4965 | struct drm_device *dev = crtc->dev; | |
4966 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4967 | struct drm_plane *p; |
87d4300a ML |
4968 | int pipe = intel_crtc->pipe; |
4969 | ||
7cac945f | 4970 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4971 | |
d032ffa0 | 4972 | drm_for_each_plane_mask(p, dev, plane_mask) |
282dbf9b | 4973 | to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc); |
f98551ae | 4974 | |
f99d7069 DV |
4975 | /* |
4976 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4977 | * to compute the mask of flip planes precisely. For the time being | |
4978 | * consider this a flip to a NULL plane. | |
4979 | */ | |
5748b6a1 | 4980 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
4981 | } |
4982 | ||
fb1c98b1 | 4983 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 4984 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
4985 | struct drm_atomic_state *old_state) |
4986 | { | |
aa5e9b47 | 4987 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
4988 | struct drm_connector *conn; |
4989 | int i; | |
4990 | ||
aa5e9b47 | 4991 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
4992 | struct intel_encoder *encoder = |
4993 | to_intel_encoder(conn_state->best_encoder); | |
4994 | ||
4995 | if (conn_state->crtc != crtc) | |
4996 | continue; | |
4997 | ||
4998 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 4999 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5000 | } |
5001 | } | |
5002 | ||
5003 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5004 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5005 | struct drm_atomic_state *old_state) |
5006 | { | |
aa5e9b47 | 5007 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5008 | struct drm_connector *conn; |
5009 | int i; | |
5010 | ||
aa5e9b47 | 5011 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5012 | struct intel_encoder *encoder = |
5013 | to_intel_encoder(conn_state->best_encoder); | |
5014 | ||
5015 | if (conn_state->crtc != crtc) | |
5016 | continue; | |
5017 | ||
5018 | if (encoder->pre_enable) | |
fd6bbda9 | 5019 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5020 | } |
5021 | } | |
5022 | ||
5023 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5024 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5025 | struct drm_atomic_state *old_state) |
5026 | { | |
aa5e9b47 | 5027 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5028 | struct drm_connector *conn; |
5029 | int i; | |
5030 | ||
aa5e9b47 | 5031 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5032 | struct intel_encoder *encoder = |
5033 | to_intel_encoder(conn_state->best_encoder); | |
5034 | ||
5035 | if (conn_state->crtc != crtc) | |
5036 | continue; | |
5037 | ||
fd6bbda9 | 5038 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5039 | intel_opregion_notify_encoder(encoder, true); |
5040 | } | |
5041 | } | |
5042 | ||
5043 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5044 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5045 | struct drm_atomic_state *old_state) |
5046 | { | |
5047 | struct drm_connector_state *old_conn_state; | |
5048 | struct drm_connector *conn; | |
5049 | int i; | |
5050 | ||
aa5e9b47 | 5051 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5052 | struct intel_encoder *encoder = |
5053 | to_intel_encoder(old_conn_state->best_encoder); | |
5054 | ||
5055 | if (old_conn_state->crtc != crtc) | |
5056 | continue; | |
5057 | ||
5058 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5059 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5060 | } |
5061 | } | |
5062 | ||
5063 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5064 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5065 | struct drm_atomic_state *old_state) |
5066 | { | |
5067 | struct drm_connector_state *old_conn_state; | |
5068 | struct drm_connector *conn; | |
5069 | int i; | |
5070 | ||
aa5e9b47 | 5071 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5072 | struct intel_encoder *encoder = |
5073 | to_intel_encoder(old_conn_state->best_encoder); | |
5074 | ||
5075 | if (old_conn_state->crtc != crtc) | |
5076 | continue; | |
5077 | ||
5078 | if (encoder->post_disable) | |
fd6bbda9 | 5079 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5080 | } |
5081 | } | |
5082 | ||
5083 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5084 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5085 | struct drm_atomic_state *old_state) |
5086 | { | |
5087 | struct drm_connector_state *old_conn_state; | |
5088 | struct drm_connector *conn; | |
5089 | int i; | |
5090 | ||
aa5e9b47 | 5091 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5092 | struct intel_encoder *encoder = |
5093 | to_intel_encoder(old_conn_state->best_encoder); | |
5094 | ||
5095 | if (old_conn_state->crtc != crtc) | |
5096 | continue; | |
5097 | ||
5098 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5099 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5100 | } |
5101 | } | |
5102 | ||
4a806558 ML |
5103 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5104 | struct drm_atomic_state *old_state) | |
f67a559d | 5105 | { |
4a806558 | 5106 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5107 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5108 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5109 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5110 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5111 | struct intel_atomic_state *old_intel_state = |
5112 | to_intel_atomic_state(old_state); | |
f67a559d | 5113 | |
53d9f4e9 | 5114 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5115 | return; |
5116 | ||
b2c0593a VS |
5117 | /* |
5118 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5119 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5120 | * | |
5121 | * On ILK we get an occasional spurious CPU pipe underruns | |
5122 | * between eDP port A enable and vdd enable. Also PCH port | |
5123 | * enable seems to result in the occasional CPU pipe underrun. | |
5124 | * | |
5125 | * Spurious PCH underruns also occur during PCH enabling. | |
5126 | */ | |
5127 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5128 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5129 | if (intel_crtc->config->has_pch_encoder) |
5130 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5131 | ||
6e3c9717 | 5132 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5133 | intel_prepare_shared_dpll(intel_crtc); |
5134 | ||
37a5650b | 5135 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5136 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5137 | |
5138 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5139 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5140 | |
6e3c9717 | 5141 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5142 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5143 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5144 | } |
5145 | ||
5146 | ironlake_set_pipeconf(crtc); | |
5147 | ||
f67a559d | 5148 | intel_crtc->active = true; |
8664281b | 5149 | |
fd6bbda9 | 5150 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5151 | |
6e3c9717 | 5152 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5153 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5154 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5155 | * enabling. */ | |
88cefb6c | 5156 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5157 | } else { |
5158 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5159 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5160 | } | |
f67a559d | 5161 | |
b074cec8 | 5162 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5163 | |
9c54c0dd JB |
5164 | /* |
5165 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5166 | * clocks enabled | |
5167 | */ | |
b95c5321 | 5168 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5169 | |
1d5bf5d9 | 5170 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5171 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5172 | intel_enable_pipe(intel_crtc); |
f67a559d | 5173 | |
6e3c9717 | 5174 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5175 | ironlake_pch_enable(pipe_config); |
c98e9dcf | 5176 | |
f9b61ff6 DV |
5177 | assert_vblank_disabled(crtc); |
5178 | drm_crtc_vblank_on(crtc); | |
5179 | ||
fd6bbda9 | 5180 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5181 | |
6e266956 | 5182 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5183 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5184 | |
5185 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5186 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5187 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5188 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5189 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5190 | } |
5191 | ||
42db64ef PZ |
5192 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5193 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5194 | { | |
50a0bc90 | 5195 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5196 | } |
5197 | ||
4a806558 ML |
5198 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5199 | struct drm_atomic_state *old_state) | |
4f771f10 | 5200 | { |
4a806558 | 5201 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5202 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5203 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5204 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5205 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5206 | struct intel_atomic_state *old_intel_state = |
5207 | to_intel_atomic_state(old_state); | |
4f771f10 | 5208 | |
53d9f4e9 | 5209 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5210 | return; |
5211 | ||
81b088ca | 5212 | if (intel_crtc->config->has_pch_encoder) |
29012159 | 5213 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
81b088ca | 5214 | |
fd6bbda9 | 5215 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5216 | |
8106ddbd | 5217 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5218 | intel_enable_shared_dpll(intel_crtc); |
5219 | ||
37a5650b | 5220 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5221 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5222 | |
d7edc4e5 | 5223 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5224 | intel_set_pipe_timings(intel_crtc); |
5225 | ||
bc58be60 | 5226 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5227 | |
4d1de975 JN |
5228 | if (cpu_transcoder != TRANSCODER_EDP && |
5229 | !transcoder_is_dsi(cpu_transcoder)) { | |
5230 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5231 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5232 | } |
5233 | ||
6e3c9717 | 5234 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5235 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5236 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5237 | } |
5238 | ||
d7edc4e5 | 5239 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5240 | haswell_set_pipeconf(crtc); |
5241 | ||
391bf048 | 5242 | haswell_set_pipemisc(crtc); |
229fca97 | 5243 | |
b95c5321 | 5244 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5245 | |
4f771f10 | 5246 | intel_crtc->active = true; |
8664281b | 5247 | |
6b698516 DV |
5248 | if (intel_crtc->config->has_pch_encoder) |
5249 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5250 | else | |
5251 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5252 | ||
fd6bbda9 | 5253 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5254 | |
d2d65408 | 5255 | if (intel_crtc->config->has_pch_encoder) |
dc4a1094 | 5256 | dev_priv->display.fdi_link_train(intel_crtc, pipe_config); |
4fe9467d | 5257 | |
d7edc4e5 | 5258 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5259 | intel_ddi_enable_pipe_clock(pipe_config); |
4f771f10 | 5260 | |
6315b5d3 | 5261 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5262 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5263 | else |
1c132b44 | 5264 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5265 | |
5266 | /* | |
5267 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5268 | * clocks enabled | |
5269 | */ | |
b95c5321 | 5270 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5271 | |
3dc38eea | 5272 | intel_ddi_set_pipe_settings(pipe_config); |
d7edc4e5 | 5273 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5274 | intel_ddi_enable_transcoder_func(pipe_config); |
4f771f10 | 5275 | |
1d5bf5d9 | 5276 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5277 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5278 | |
5279 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5280 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5281 | intel_enable_pipe(intel_crtc); |
42db64ef | 5282 | |
6e3c9717 | 5283 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5284 | lpt_pch_enable(pipe_config); |
4f771f10 | 5285 | |
0037071d | 5286 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5287 | intel_ddi_set_vc_payload_alloc(pipe_config, true); |
0e32b39c | 5288 | |
f9b61ff6 DV |
5289 | assert_vblank_disabled(crtc); |
5290 | drm_crtc_vblank_on(crtc); | |
5291 | ||
fd6bbda9 | 5292 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5293 | |
6b698516 | 5294 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5295 | intel_wait_for_vblank(dev_priv, pipe); |
5296 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5297 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
29012159 | 5298 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
6b698516 | 5299 | } |
d2d65408 | 5300 | |
e4916946 PZ |
5301 | /* If we change the relative order between pipe/planes enabling, we need |
5302 | * to change the workaround. */ | |
99d736a2 | 5303 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5304 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5305 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5306 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5307 | } |
4f771f10 PZ |
5308 | } |
5309 | ||
bfd16b2a | 5310 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5311 | { |
5312 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5313 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5314 | int pipe = crtc->pipe; |
5315 | ||
5316 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5317 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5318 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5319 | I915_WRITE(PF_CTL(pipe), 0); |
5320 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5321 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5322 | } | |
5323 | } | |
5324 | ||
4a806558 ML |
5325 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5326 | struct drm_atomic_state *old_state) | |
6be4a607 | 5327 | { |
4a806558 | 5328 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5329 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5330 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5331 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5332 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5333 | |
b2c0593a VS |
5334 | /* |
5335 | * Sometimes spurious CPU pipe underruns happen when the | |
5336 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5337 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5338 | */ | |
5339 | if (intel_crtc->config->has_pch_encoder) { | |
5340 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5341 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5342 | } |
37ca8d4c | 5343 | |
fd6bbda9 | 5344 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5345 | |
f9b61ff6 DV |
5346 | drm_crtc_vblank_off(crtc); |
5347 | assert_vblank_disabled(crtc); | |
5348 | ||
575f7ab7 | 5349 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5350 | |
bfd16b2a | 5351 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5352 | |
b2c0593a | 5353 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5354 | ironlake_fdi_disable(crtc); |
5355 | ||
fd6bbda9 | 5356 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5357 | |
6e3c9717 | 5358 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5359 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5360 | |
6e266956 | 5361 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5362 | i915_reg_t reg; |
5363 | u32 temp; | |
5364 | ||
d925c59a DV |
5365 | /* disable TRANS_DP_CTL */ |
5366 | reg = TRANS_DP_CTL(pipe); | |
5367 | temp = I915_READ(reg); | |
5368 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5369 | TRANS_DP_PORT_SEL_MASK); | |
5370 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5371 | I915_WRITE(reg, temp); | |
5372 | ||
5373 | /* disable DPLL_SEL */ | |
5374 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5375 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5376 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5377 | } |
e3421a18 | 5378 | |
d925c59a DV |
5379 | ironlake_fdi_pll_disable(intel_crtc); |
5380 | } | |
81b088ca | 5381 | |
b2c0593a | 5382 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5383 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5384 | } |
1b3c7a47 | 5385 | |
4a806558 ML |
5386 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5387 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5388 | { |
4a806558 | 5389 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5390 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5391 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5392 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5393 | |
d2d65408 | 5394 | if (intel_crtc->config->has_pch_encoder) |
29012159 | 5395 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
d2d65408 | 5396 | |
fd6bbda9 | 5397 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5398 | |
f9b61ff6 DV |
5399 | drm_crtc_vblank_off(crtc); |
5400 | assert_vblank_disabled(crtc); | |
5401 | ||
4d1de975 | 5402 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5403 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5404 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5405 | |
0037071d | 5406 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5407 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); |
a4bf214f | 5408 | |
d7edc4e5 | 5409 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5410 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5411 | |
6315b5d3 | 5412 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5413 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5414 | else |
bfd16b2a | 5415 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5416 | |
d7edc4e5 | 5417 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5418 | intel_ddi_disable_pipe_clock(intel_crtc->config); |
4f771f10 | 5419 | |
fd6bbda9 | 5420 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5421 | |
b7076546 | 5422 | if (old_crtc_state->has_pch_encoder) |
29012159 | 5423 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
4f771f10 PZ |
5424 | } |
5425 | ||
2dd24552 JB |
5426 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5427 | { | |
5428 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5429 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5430 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5431 | |
681a8504 | 5432 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5433 | return; |
5434 | ||
2dd24552 | 5435 | /* |
c0b03411 DV |
5436 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5437 | * according to register description and PRM. | |
2dd24552 | 5438 | */ |
c0b03411 DV |
5439 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5440 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5441 | |
b074cec8 JB |
5442 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5443 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5444 | |
5445 | /* Border color in case we don't scale up to the full screen. Black by | |
5446 | * default, change to something else for debugging. */ | |
5447 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5448 | } |
5449 | ||
79f255a0 | 5450 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
5451 | { |
5452 | switch (port) { | |
5453 | case PORT_A: | |
6331a704 | 5454 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5455 | case PORT_B: |
6331a704 | 5456 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5457 | case PORT_C: |
6331a704 | 5458 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5459 | case PORT_D: |
6331a704 | 5460 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5461 | case PORT_E: |
6331a704 | 5462 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5463 | default: |
b9fec167 | 5464 | MISSING_CASE(port); |
d05410f9 DA |
5465 | return POWER_DOMAIN_PORT_OTHER; |
5466 | } | |
5467 | } | |
5468 | ||
d8fc70b7 ACO |
5469 | static u64 get_crtc_power_domains(struct drm_crtc *crtc, |
5470 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5471 | { |
319be8ae | 5472 | struct drm_device *dev = crtc->dev; |
37255d8d | 5473 | struct drm_i915_private *dev_priv = to_i915(dev); |
74bff5f9 | 5474 | struct drm_encoder *encoder; |
319be8ae ID |
5475 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5476 | enum pipe pipe = intel_crtc->pipe; | |
d8fc70b7 | 5477 | u64 mask; |
74bff5f9 | 5478 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5479 | |
74bff5f9 | 5480 | if (!crtc_state->base.active) |
292b990e ML |
5481 | return 0; |
5482 | ||
77d22dca ID |
5483 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5484 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5485 | if (crtc_state->pch_pfit.enabled || |
5486 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 5487 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 5488 | |
74bff5f9 ML |
5489 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5490 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5491 | ||
79f255a0 | 5492 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 5493 | } |
319be8ae | 5494 | |
37255d8d ML |
5495 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
5496 | mask |= BIT(POWER_DOMAIN_AUDIO); | |
5497 | ||
15e7ec29 | 5498 | if (crtc_state->shared_dpll) |
d8fc70b7 | 5499 | mask |= BIT_ULL(POWER_DOMAIN_PLLS); |
15e7ec29 | 5500 | |
77d22dca ID |
5501 | return mask; |
5502 | } | |
5503 | ||
d2d15016 | 5504 | static u64 |
74bff5f9 ML |
5505 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
5506 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5507 | { |
fac5e23e | 5508 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5509 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5510 | enum intel_display_power_domain domain; | |
d8fc70b7 | 5511 | u64 domains, new_domains, old_domains; |
77d22dca | 5512 | |
292b990e | 5513 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5514 | intel_crtc->enabled_power_domains = new_domains = |
5515 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5516 | |
5a21b665 | 5517 | domains = new_domains & ~old_domains; |
292b990e ML |
5518 | |
5519 | for_each_power_domain(domain, domains) | |
5520 | intel_display_power_get(dev_priv, domain); | |
5521 | ||
5a21b665 | 5522 | return old_domains & ~new_domains; |
292b990e ML |
5523 | } |
5524 | ||
5525 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 5526 | u64 domains) |
292b990e ML |
5527 | { |
5528 | enum intel_display_power_domain domain; | |
5529 | ||
5530 | for_each_power_domain(domain, domains) | |
5531 | intel_display_power_put(dev_priv, domain); | |
5532 | } | |
77d22dca | 5533 | |
7ff89ca2 VS |
5534 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
5535 | struct drm_atomic_state *old_state) | |
adafdc6f | 5536 | { |
ff32c54e VS |
5537 | struct intel_atomic_state *old_intel_state = |
5538 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5539 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5540 | struct drm_device *dev = crtc->dev; | |
5541 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5542 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5543 | int pipe = intel_crtc->pipe; | |
adafdc6f | 5544 | |
7ff89ca2 VS |
5545 | if (WARN_ON(intel_crtc->active)) |
5546 | return; | |
adafdc6f | 5547 | |
7ff89ca2 VS |
5548 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5549 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
b2045352 | 5550 | |
7ff89ca2 VS |
5551 | intel_set_pipe_timings(intel_crtc); |
5552 | intel_set_pipe_src_size(intel_crtc); | |
b2045352 | 5553 | |
7ff89ca2 VS |
5554 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
5555 | struct drm_i915_private *dev_priv = to_i915(dev); | |
560a7ae4 | 5556 | |
7ff89ca2 VS |
5557 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
5558 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
5559 | } |
5560 | ||
7ff89ca2 | 5561 | i9xx_set_pipeconf(intel_crtc); |
560a7ae4 | 5562 | |
7ff89ca2 | 5563 | intel_crtc->active = true; |
92891e45 | 5564 | |
7ff89ca2 | 5565 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 5566 | |
7ff89ca2 | 5567 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
5f199dfa | 5568 | |
7ff89ca2 VS |
5569 | if (IS_CHERRYVIEW(dev_priv)) { |
5570 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
5571 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
5572 | } else { | |
5573 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
5574 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
5f199dfa VS |
5575 | } |
5576 | ||
7ff89ca2 | 5577 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
5f199dfa | 5578 | |
7ff89ca2 | 5579 | i9xx_pfit_enable(intel_crtc); |
89b3c3c7 | 5580 | |
7ff89ca2 | 5581 | intel_color_load_luts(&pipe_config->base); |
89b3c3c7 | 5582 | |
ff32c54e VS |
5583 | dev_priv->display.initial_watermarks(old_intel_state, |
5584 | pipe_config); | |
7ff89ca2 VS |
5585 | intel_enable_pipe(intel_crtc); |
5586 | ||
5587 | assert_vblank_disabled(crtc); | |
5588 | drm_crtc_vblank_on(crtc); | |
89b3c3c7 | 5589 | |
7ff89ca2 | 5590 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b3c3c7 ACO |
5591 | } |
5592 | ||
7ff89ca2 | 5593 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
2b73001e | 5594 | { |
7ff89ca2 VS |
5595 | struct drm_device *dev = crtc->base.dev; |
5596 | struct drm_i915_private *dev_priv = to_i915(dev); | |
83d7c81f | 5597 | |
7ff89ca2 VS |
5598 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5599 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
2b73001e VS |
5600 | } |
5601 | ||
7ff89ca2 VS |
5602 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
5603 | struct drm_atomic_state *old_state) | |
2b73001e | 5604 | { |
04548cba VS |
5605 | struct intel_atomic_state *old_intel_state = |
5606 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5607 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5608 | struct drm_device *dev = crtc->dev; | |
5609 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5610 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5611 | enum pipe pipe = intel_crtc->pipe; | |
2b73001e | 5612 | |
7ff89ca2 VS |
5613 | if (WARN_ON(intel_crtc->active)) |
5614 | return; | |
2b73001e | 5615 | |
7ff89ca2 | 5616 | i9xx_set_pll_dividers(intel_crtc); |
2b73001e | 5617 | |
7ff89ca2 VS |
5618 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5619 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
83d7c81f | 5620 | |
7ff89ca2 VS |
5621 | intel_set_pipe_timings(intel_crtc); |
5622 | intel_set_pipe_src_size(intel_crtc); | |
2b73001e | 5623 | |
7ff89ca2 | 5624 | i9xx_set_pipeconf(intel_crtc); |
f8437dd1 | 5625 | |
7ff89ca2 | 5626 | intel_crtc->active = true; |
5f199dfa | 5627 | |
7ff89ca2 VS |
5628 | if (!IS_GEN2(dev_priv)) |
5629 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5f199dfa | 5630 | |
7ff89ca2 | 5631 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f8437dd1 | 5632 | |
7ff89ca2 | 5633 | i9xx_enable_pll(intel_crtc); |
f8437dd1 | 5634 | |
7ff89ca2 | 5635 | i9xx_pfit_enable(intel_crtc); |
f8437dd1 | 5636 | |
7ff89ca2 | 5637 | intel_color_load_luts(&pipe_config->base); |
f8437dd1 | 5638 | |
04548cba VS |
5639 | if (dev_priv->display.initial_watermarks != NULL) |
5640 | dev_priv->display.initial_watermarks(old_intel_state, | |
5641 | intel_crtc->config); | |
5642 | else | |
5643 | intel_update_watermarks(intel_crtc); | |
7ff89ca2 | 5644 | intel_enable_pipe(intel_crtc); |
f8437dd1 | 5645 | |
7ff89ca2 VS |
5646 | assert_vblank_disabled(crtc); |
5647 | drm_crtc_vblank_on(crtc); | |
f8437dd1 | 5648 | |
7ff89ca2 VS |
5649 | intel_encoders_enable(crtc, pipe_config, old_state); |
5650 | } | |
f8437dd1 | 5651 | |
7ff89ca2 VS |
5652 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5653 | { | |
5654 | struct drm_device *dev = crtc->base.dev; | |
5655 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f8437dd1 | 5656 | |
7ff89ca2 | 5657 | if (!crtc->config->gmch_pfit.control) |
f8437dd1 | 5658 | return; |
f8437dd1 | 5659 | |
7ff89ca2 VS |
5660 | assert_pipe_disabled(dev_priv, crtc->pipe); |
5661 | ||
5662 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
5663 | I915_READ(PFIT_CONTROL)); | |
5664 | I915_WRITE(PFIT_CONTROL, 0); | |
f8437dd1 VK |
5665 | } |
5666 | ||
7ff89ca2 VS |
5667 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5668 | struct drm_atomic_state *old_state) | |
f8437dd1 | 5669 | { |
7ff89ca2 VS |
5670 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
5671 | struct drm_device *dev = crtc->dev; | |
5672 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5673 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5674 | int pipe = intel_crtc->pipe; | |
d66a2194 | 5675 | |
d66a2194 | 5676 | /* |
7ff89ca2 VS |
5677 | * On gen2 planes are double buffered but the pipe isn't, so we must |
5678 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 5679 | */ |
7ff89ca2 VS |
5680 | if (IS_GEN2(dev_priv)) |
5681 | intel_wait_for_vblank(dev_priv, pipe); | |
d66a2194 | 5682 | |
7ff89ca2 | 5683 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5684 | |
7ff89ca2 VS |
5685 | drm_crtc_vblank_off(crtc); |
5686 | assert_vblank_disabled(crtc); | |
d66a2194 | 5687 | |
7ff89ca2 | 5688 | intel_disable_pipe(intel_crtc); |
d66a2194 | 5689 | |
7ff89ca2 | 5690 | i9xx_pfit_disable(intel_crtc); |
89b3c3c7 | 5691 | |
7ff89ca2 | 5692 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5693 | |
7ff89ca2 VS |
5694 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
5695 | if (IS_CHERRYVIEW(dev_priv)) | |
5696 | chv_disable_pll(dev_priv, pipe); | |
5697 | else if (IS_VALLEYVIEW(dev_priv)) | |
5698 | vlv_disable_pll(dev_priv, pipe); | |
5699 | else | |
5700 | i9xx_disable_pll(intel_crtc); | |
5701 | } | |
c2e001ef | 5702 | |
7ff89ca2 | 5703 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
89b3c3c7 | 5704 | |
7ff89ca2 VS |
5705 | if (!IS_GEN2(dev_priv)) |
5706 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
ff32c54e VS |
5707 | |
5708 | if (!dev_priv->display.initial_watermarks) | |
5709 | intel_update_watermarks(intel_crtc); | |
2ee0da16 VS |
5710 | |
5711 | /* clock the pipe down to 640x480@60 to potentially save power */ | |
5712 | if (IS_I830(dev_priv)) | |
5713 | i830_enable_pipe(dev_priv, pipe); | |
f8437dd1 VK |
5714 | } |
5715 | ||
da1d0e26 VS |
5716 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, |
5717 | struct drm_modeset_acquire_ctx *ctx) | |
f8437dd1 | 5718 | { |
7ff89ca2 VS |
5719 | struct intel_encoder *encoder; |
5720 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5721 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
5722 | enum intel_display_power_domain domain; | |
d2d15016 | 5723 | u64 domains; |
7ff89ca2 VS |
5724 | struct drm_atomic_state *state; |
5725 | struct intel_crtc_state *crtc_state; | |
5726 | int ret; | |
f8437dd1 | 5727 | |
7ff89ca2 VS |
5728 | if (!intel_crtc->active) |
5729 | return; | |
a8ca4934 | 5730 | |
7ff89ca2 | 5731 | if (crtc->primary->state->visible) { |
7ff89ca2 | 5732 | intel_pre_disable_primary_noatomic(crtc); |
709e05c3 | 5733 | |
7ff89ca2 VS |
5734 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
5735 | crtc->primary->state->visible = false; | |
5736 | } | |
5d96d8af | 5737 | |
7ff89ca2 VS |
5738 | state = drm_atomic_state_alloc(crtc->dev); |
5739 | if (!state) { | |
5740 | DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", | |
5741 | crtc->base.id, crtc->name); | |
1c3f7700 | 5742 | return; |
7ff89ca2 | 5743 | } |
9f7eb31a | 5744 | |
da1d0e26 | 5745 | state->acquire_ctx = ctx; |
ea61791e | 5746 | |
7ff89ca2 VS |
5747 | /* Everything's already locked, -EDEADLK can't happen. */ |
5748 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
5749 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
9f7eb31a | 5750 | |
7ff89ca2 | 5751 | WARN_ON(IS_ERR(crtc_state) || ret); |
5d96d8af | 5752 | |
7ff89ca2 | 5753 | dev_priv->display.crtc_disable(crtc_state, state); |
4a806558 | 5754 | |
0853695c | 5755 | drm_atomic_state_put(state); |
842e0307 | 5756 | |
78108b7c VS |
5757 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
5758 | crtc->base.id, crtc->name); | |
842e0307 ML |
5759 | |
5760 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
5761 | crtc->state->active = false; | |
37d9078b | 5762 | intel_crtc->active = false; |
842e0307 ML |
5763 | crtc->enabled = false; |
5764 | crtc->state->connector_mask = 0; | |
5765 | crtc->state->encoder_mask = 0; | |
5766 | ||
5767 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
5768 | encoder->base.crtc = NULL; | |
5769 | ||
58f9c0bc | 5770 | intel_fbc_disable(intel_crtc); |
432081bc | 5771 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 5772 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
5773 | |
5774 | domains = intel_crtc->enabled_power_domains; | |
5775 | for_each_power_domain(domain, domains) | |
5776 | intel_display_power_put(dev_priv, domain); | |
5777 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
5778 | |
5779 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
5780 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
5781 | } |
5782 | ||
6b72d486 ML |
5783 | /* |
5784 | * turn all crtc's off, but do not adjust state | |
5785 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
5786 | */ | |
70e0bd74 | 5787 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 5788 | { |
e2c8b870 | 5789 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 5790 | struct drm_atomic_state *state; |
e2c8b870 | 5791 | int ret; |
70e0bd74 | 5792 | |
e2c8b870 ML |
5793 | state = drm_atomic_helper_suspend(dev); |
5794 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
5795 | if (ret) |
5796 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
5797 | else |
5798 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 5799 | return ret; |
ee7b9f93 JB |
5800 | } |
5801 | ||
ea5b213a | 5802 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5803 | { |
4ef69c7a | 5804 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5805 | |
ea5b213a CW |
5806 | drm_encoder_cleanup(encoder); |
5807 | kfree(intel_encoder); | |
7e7d76c3 JB |
5808 | } |
5809 | ||
0a91ca29 DV |
5810 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5811 | * internal consistency). */ | |
749d98b8 ML |
5812 | static void intel_connector_verify_state(struct drm_crtc_state *crtc_state, |
5813 | struct drm_connector_state *conn_state) | |
79e53945 | 5814 | { |
749d98b8 | 5815 | struct intel_connector *connector = to_intel_connector(conn_state->connector); |
35dd3c64 ML |
5816 | |
5817 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5818 | connector->base.base.id, | |
5819 | connector->base.name); | |
5820 | ||
0a91ca29 | 5821 | if (connector->get_hw_state(connector)) { |
e85376cb | 5822 | struct intel_encoder *encoder = connector->encoder; |
0a91ca29 | 5823 | |
749d98b8 | 5824 | I915_STATE_WARN(!crtc_state, |
35dd3c64 | 5825 | "connector enabled without attached crtc\n"); |
0a91ca29 | 5826 | |
749d98b8 | 5827 | if (!crtc_state) |
35dd3c64 ML |
5828 | return; |
5829 | ||
749d98b8 | 5830 | I915_STATE_WARN(!crtc_state->active, |
35dd3c64 ML |
5831 | "connector is active, but attached crtc isn't\n"); |
5832 | ||
e85376cb | 5833 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
5834 | return; |
5835 | ||
e85376cb | 5836 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
5837 | "atomic encoder doesn't match attached encoder\n"); |
5838 | ||
e85376cb | 5839 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
5840 | "attached encoder crtc differs from connector crtc\n"); |
5841 | } else { | |
749d98b8 | 5842 | I915_STATE_WARN(crtc_state && crtc_state->active, |
4d688a2a | 5843 | "attached crtc is active, but connector isn't\n"); |
749d98b8 | 5844 | I915_STATE_WARN(!crtc_state && conn_state->best_encoder, |
35dd3c64 | 5845 | "best encoder set without crtc!\n"); |
0a91ca29 | 5846 | } |
79e53945 JB |
5847 | } |
5848 | ||
08d9bc92 ACO |
5849 | int intel_connector_init(struct intel_connector *connector) |
5850 | { | |
11c1a9ec | 5851 | struct intel_digital_connector_state *conn_state; |
08d9bc92 | 5852 | |
11c1a9ec ML |
5853 | /* |
5854 | * Allocate enough memory to hold intel_digital_connector_state, | |
5855 | * This might be a few bytes too many, but for connectors that don't | |
5856 | * need it we'll free the state and allocate a smaller one on the first | |
5857 | * succesful commit anyway. | |
5858 | */ | |
5859 | conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); | |
5860 | if (!conn_state) | |
08d9bc92 ACO |
5861 | return -ENOMEM; |
5862 | ||
11c1a9ec ML |
5863 | __drm_atomic_helper_connector_reset(&connector->base, |
5864 | &conn_state->base); | |
5865 | ||
08d9bc92 ACO |
5866 | return 0; |
5867 | } | |
5868 | ||
5869 | struct intel_connector *intel_connector_alloc(void) | |
5870 | { | |
5871 | struct intel_connector *connector; | |
5872 | ||
5873 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
5874 | if (!connector) | |
5875 | return NULL; | |
5876 | ||
5877 | if (intel_connector_init(connector) < 0) { | |
5878 | kfree(connector); | |
5879 | return NULL; | |
5880 | } | |
5881 | ||
5882 | return connector; | |
5883 | } | |
5884 | ||
f0947c37 DV |
5885 | /* Simple connector->get_hw_state implementation for encoders that support only |
5886 | * one connector and no cloning and hence the encoder state determines the state | |
5887 | * of the connector. */ | |
5888 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5889 | { |
24929352 | 5890 | enum pipe pipe = 0; |
f0947c37 | 5891 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5892 | |
f0947c37 | 5893 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5894 | } |
5895 | ||
6d293983 | 5896 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 5897 | { |
6d293983 ACO |
5898 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
5899 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
5900 | |
5901 | return 0; | |
5902 | } | |
5903 | ||
6d293983 | 5904 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 5905 | struct intel_crtc_state *pipe_config) |
1857e1da | 5906 | { |
8652744b | 5907 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
5908 | struct drm_atomic_state *state = pipe_config->base.state; |
5909 | struct intel_crtc *other_crtc; | |
5910 | struct intel_crtc_state *other_crtc_state; | |
5911 | ||
1857e1da DV |
5912 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
5913 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5914 | if (pipe_config->fdi_lanes > 4) { | |
5915 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5916 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 5917 | return -EINVAL; |
1857e1da DV |
5918 | } |
5919 | ||
8652744b | 5920 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
5921 | if (pipe_config->fdi_lanes > 2) { |
5922 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5923 | pipe_config->fdi_lanes); | |
6d293983 | 5924 | return -EINVAL; |
1857e1da | 5925 | } else { |
6d293983 | 5926 | return 0; |
1857e1da DV |
5927 | } |
5928 | } | |
5929 | ||
b7f05d4a | 5930 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 5931 | return 0; |
1857e1da DV |
5932 | |
5933 | /* Ivybridge 3 pipe is really complicated */ | |
5934 | switch (pipe) { | |
5935 | case PIPE_A: | |
6d293983 | 5936 | return 0; |
1857e1da | 5937 | case PIPE_B: |
6d293983 ACO |
5938 | if (pipe_config->fdi_lanes <= 2) |
5939 | return 0; | |
5940 | ||
b91eb5cc | 5941 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
5942 | other_crtc_state = |
5943 | intel_atomic_get_crtc_state(state, other_crtc); | |
5944 | if (IS_ERR(other_crtc_state)) | |
5945 | return PTR_ERR(other_crtc_state); | |
5946 | ||
5947 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
5948 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
5949 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 5950 | return -EINVAL; |
1857e1da | 5951 | } |
6d293983 | 5952 | return 0; |
1857e1da | 5953 | case PIPE_C: |
251cc67c VS |
5954 | if (pipe_config->fdi_lanes > 2) { |
5955 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
5956 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 5957 | return -EINVAL; |
251cc67c | 5958 | } |
6d293983 | 5959 | |
b91eb5cc | 5960 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
5961 | other_crtc_state = |
5962 | intel_atomic_get_crtc_state(state, other_crtc); | |
5963 | if (IS_ERR(other_crtc_state)) | |
5964 | return PTR_ERR(other_crtc_state); | |
5965 | ||
5966 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 5967 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 5968 | return -EINVAL; |
1857e1da | 5969 | } |
6d293983 | 5970 | return 0; |
1857e1da DV |
5971 | default: |
5972 | BUG(); | |
5973 | } | |
5974 | } | |
5975 | ||
e29c22c0 DV |
5976 | #define RETRY 1 |
5977 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 5978 | struct intel_crtc_state *pipe_config) |
877d48d5 | 5979 | { |
1857e1da | 5980 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 5981 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
5982 | int lane, link_bw, fdi_dotclock, ret; |
5983 | bool needs_recompute = false; | |
877d48d5 | 5984 | |
e29c22c0 | 5985 | retry: |
877d48d5 DV |
5986 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5987 | * each output octet as 10 bits. The actual frequency | |
5988 | * is stored as a divider into a 100MHz clock, and the | |
5989 | * mode pixel clock is stored in units of 1KHz. | |
5990 | * Hence the bw of each lane in terms of the mode signal | |
5991 | * is: | |
5992 | */ | |
21a727b3 | 5993 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 5994 | |
241bfc38 | 5995 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5996 | |
2bd89a07 | 5997 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5998 | pipe_config->pipe_bpp); |
5999 | ||
6000 | pipe_config->fdi_lanes = lane; | |
6001 | ||
2bd89a07 | 6002 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
b31e85ed | 6003 | link_bw, &pipe_config->fdi_m_n, false); |
1857e1da | 6004 | |
e3b247da | 6005 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6006 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 6007 | pipe_config->pipe_bpp -= 2*3; |
7ff89ca2 VS |
6008 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
6009 | pipe_config->pipe_bpp); | |
6010 | needs_recompute = true; | |
6011 | pipe_config->bw_constrained = true; | |
257a7ffc | 6012 | |
7ff89ca2 | 6013 | goto retry; |
257a7ffc | 6014 | } |
79e53945 | 6015 | |
7ff89ca2 VS |
6016 | if (needs_recompute) |
6017 | return RETRY; | |
e70236a8 | 6018 | |
7ff89ca2 | 6019 | return ret; |
e70236a8 JB |
6020 | } |
6021 | ||
7ff89ca2 VS |
6022 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6023 | struct intel_crtc_state *pipe_config) | |
e70236a8 | 6024 | { |
7ff89ca2 VS |
6025 | if (pipe_config->pipe_bpp > 24) |
6026 | return false; | |
e70236a8 | 6027 | |
7ff89ca2 VS |
6028 | /* HSW can handle pixel rate up to cdclk? */ |
6029 | if (IS_HASWELL(dev_priv)) | |
6030 | return true; | |
1b1d2716 | 6031 | |
65cd2b3f | 6032 | /* |
7ff89ca2 VS |
6033 | * We compare against max which means we must take |
6034 | * the increased cdclk requirement into account when | |
6035 | * calculating the new cdclk. | |
6036 | * | |
6037 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 6038 | */ |
7ff89ca2 VS |
6039 | return pipe_config->pixel_rate <= |
6040 | dev_priv->max_cdclk_freq * 95 / 100; | |
e70236a8 | 6041 | } |
79e53945 | 6042 | |
7ff89ca2 VS |
6043 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
6044 | struct intel_crtc_state *pipe_config) | |
6045 | { | |
6046 | struct drm_device *dev = crtc->base.dev; | |
6047 | struct drm_i915_private *dev_priv = to_i915(dev); | |
34edce2f | 6048 | |
7ff89ca2 VS |
6049 | pipe_config->ips_enabled = i915.enable_ips && |
6050 | hsw_crtc_supports_ips(crtc) && | |
6051 | pipe_config_supports_ips(dev_priv, pipe_config); | |
34edce2f VS |
6052 | } |
6053 | ||
7ff89ca2 | 6054 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 6055 | { |
7ff89ca2 | 6056 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 6057 | |
7ff89ca2 VS |
6058 | /* GDG double wide on either pipe, otherwise pipe A only */ |
6059 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6060 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
34edce2f VS |
6061 | } |
6062 | ||
ceb99320 VS |
6063 | static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
6064 | { | |
6065 | uint32_t pixel_rate; | |
6066 | ||
6067 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; | |
6068 | ||
6069 | /* | |
6070 | * We only use IF-ID interlacing. If we ever use | |
6071 | * PF-ID we'll need to adjust the pixel_rate here. | |
6072 | */ | |
6073 | ||
6074 | if (pipe_config->pch_pfit.enabled) { | |
6075 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
6076 | uint32_t pfit_size = pipe_config->pch_pfit.size; | |
6077 | ||
6078 | pipe_w = pipe_config->pipe_src_w; | |
6079 | pipe_h = pipe_config->pipe_src_h; | |
6080 | ||
6081 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
6082 | pfit_h = pfit_size & 0xFFFF; | |
6083 | if (pipe_w < pfit_w) | |
6084 | pipe_w = pfit_w; | |
6085 | if (pipe_h < pfit_h) | |
6086 | pipe_h = pfit_h; | |
6087 | ||
6088 | if (WARN_ON(!pfit_w || !pfit_h)) | |
6089 | return pixel_rate; | |
6090 | ||
6091 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
6092 | pfit_w * pfit_h); | |
6093 | } | |
6094 | ||
6095 | return pixel_rate; | |
6096 | } | |
6097 | ||
7ff89ca2 | 6098 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 6099 | { |
7ff89ca2 | 6100 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
34edce2f | 6101 | |
7ff89ca2 VS |
6102 | if (HAS_GMCH_DISPLAY(dev_priv)) |
6103 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ | |
6104 | crtc_state->pixel_rate = | |
6105 | crtc_state->base.adjusted_mode.crtc_clock; | |
6106 | else | |
6107 | crtc_state->pixel_rate = | |
6108 | ilk_pipe_pixel_rate(crtc_state); | |
6109 | } | |
34edce2f | 6110 | |
7ff89ca2 VS |
6111 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6112 | struct intel_crtc_state *pipe_config) | |
6113 | { | |
6114 | struct drm_device *dev = crtc->base.dev; | |
6115 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6116 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6117 | int clock_limit = dev_priv->max_dotclk_freq; | |
34edce2f | 6118 | |
7ff89ca2 VS |
6119 | if (INTEL_GEN(dev_priv) < 4) { |
6120 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 6121 | |
7ff89ca2 VS |
6122 | /* |
6123 | * Enable double wide mode when the dot clock | |
6124 | * is > 90% of the (display) core speed. | |
6125 | */ | |
6126 | if (intel_crtc_supports_double_wide(crtc) && | |
6127 | adjusted_mode->crtc_clock > clock_limit) { | |
6128 | clock_limit = dev_priv->max_dotclk_freq; | |
6129 | pipe_config->double_wide = true; | |
6130 | } | |
34edce2f VS |
6131 | } |
6132 | ||
7ff89ca2 VS |
6133 | if (adjusted_mode->crtc_clock > clock_limit) { |
6134 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6135 | adjusted_mode->crtc_clock, clock_limit, | |
6136 | yesno(pipe_config->double_wide)); | |
6137 | return -EINVAL; | |
6138 | } | |
34edce2f | 6139 | |
7ff89ca2 VS |
6140 | /* |
6141 | * Pipe horizontal size must be even in: | |
6142 | * - DVO ganged mode | |
6143 | * - LVDS dual channel mode | |
6144 | * - Double wide pipe | |
6145 | */ | |
6146 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6147 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6148 | pipe_config->pipe_src_w &= ~1; | |
34edce2f | 6149 | |
7ff89ca2 VS |
6150 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6151 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6152 | */ | |
6153 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
6154 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6155 | return -EINVAL; | |
34edce2f | 6156 | |
7ff89ca2 | 6157 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 6158 | |
7ff89ca2 VS |
6159 | if (HAS_IPS(dev_priv)) |
6160 | hsw_compute_ips_config(crtc, pipe_config); | |
34edce2f | 6161 | |
7ff89ca2 VS |
6162 | if (pipe_config->has_pch_encoder) |
6163 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
34edce2f | 6164 | |
7ff89ca2 | 6165 | return 0; |
34edce2f VS |
6166 | } |
6167 | ||
2c07245f | 6168 | static void |
a65851af | 6169 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6170 | { |
a65851af VS |
6171 | while (*num > DATA_LINK_M_N_MASK || |
6172 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6173 | *num >>= 1; |
6174 | *den >>= 1; | |
6175 | } | |
6176 | } | |
6177 | ||
a65851af | 6178 | static void compute_m_n(unsigned int m, unsigned int n, |
b31e85ed JN |
6179 | uint32_t *ret_m, uint32_t *ret_n, |
6180 | bool reduce_m_n) | |
a65851af | 6181 | { |
9a86cda0 JN |
6182 | /* |
6183 | * Reduce M/N as much as possible without loss in precision. Several DP | |
6184 | * dongles in particular seem to be fussy about too large *link* M/N | |
6185 | * values. The passed in values are more likely to have the least | |
6186 | * significant bits zero than M after rounding below, so do this first. | |
6187 | */ | |
b31e85ed JN |
6188 | if (reduce_m_n) { |
6189 | while ((m & 1) == 0 && (n & 1) == 0) { | |
6190 | m >>= 1; | |
6191 | n >>= 1; | |
6192 | } | |
9a86cda0 JN |
6193 | } |
6194 | ||
a65851af VS |
6195 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
6196 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6197 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6198 | } | |
6199 | ||
e69d0bc1 DV |
6200 | void |
6201 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6202 | int pixel_clock, int link_clock, | |
b31e85ed JN |
6203 | struct intel_link_m_n *m_n, |
6204 | bool reduce_m_n) | |
2c07245f | 6205 | { |
e69d0bc1 | 6206 | m_n->tu = 64; |
a65851af VS |
6207 | |
6208 | compute_m_n(bits_per_pixel * pixel_clock, | |
6209 | link_clock * nlanes * 8, | |
b31e85ed JN |
6210 | &m_n->gmch_m, &m_n->gmch_n, |
6211 | reduce_m_n); | |
a65851af VS |
6212 | |
6213 | compute_m_n(pixel_clock, link_clock, | |
b31e85ed JN |
6214 | &m_n->link_m, &m_n->link_n, |
6215 | reduce_m_n); | |
2c07245f ZW |
6216 | } |
6217 | ||
a7615030 CW |
6218 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6219 | { | |
d330a953 JN |
6220 | if (i915.panel_use_ssc >= 0) |
6221 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6222 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6223 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6224 | } |
6225 | ||
7429e9d4 | 6226 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6227 | { |
7df00d7a | 6228 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6229 | } |
f47709a9 | 6230 | |
7429e9d4 DV |
6231 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6232 | { | |
6233 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6234 | } |
6235 | ||
f47709a9 | 6236 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6237 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 6238 | struct dpll *reduced_clock) |
a7516a05 | 6239 | { |
9b1e14f4 | 6240 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
6241 | u32 fp, fp2 = 0; |
6242 | ||
9b1e14f4 | 6243 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 6244 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6245 | if (reduced_clock) |
7429e9d4 | 6246 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6247 | } else { |
190f68c5 | 6248 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6249 | if (reduced_clock) |
7429e9d4 | 6250 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6251 | } |
6252 | ||
190f68c5 | 6253 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6254 | |
f47709a9 | 6255 | crtc->lowfreq_avail = false; |
2d84d2b3 | 6256 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6257 | reduced_clock) { |
190f68c5 | 6258 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6259 | crtc->lowfreq_avail = true; |
a7516a05 | 6260 | } else { |
190f68c5 | 6261 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6262 | } |
6263 | } | |
6264 | ||
5e69f97f CML |
6265 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6266 | pipe) | |
89b667f8 JB |
6267 | { |
6268 | u32 reg_val; | |
6269 | ||
6270 | /* | |
6271 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6272 | * and set it to a reasonable value instead. | |
6273 | */ | |
ab3c759a | 6274 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6275 | reg_val &= 0xffffff00; |
6276 | reg_val |= 0x00000030; | |
ab3c759a | 6277 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6278 | |
ab3c759a | 6279 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
ed58570f ID |
6280 | reg_val &= 0x00ffffff; |
6281 | reg_val |= 0x8c000000; | |
ab3c759a | 6282 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6283 | |
ab3c759a | 6284 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6285 | reg_val &= 0xffffff00; |
ab3c759a | 6286 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6287 | |
ab3c759a | 6288 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6289 | reg_val &= 0x00ffffff; |
6290 | reg_val |= 0xb0000000; | |
ab3c759a | 6291 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6292 | } |
6293 | ||
b551842d DV |
6294 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6295 | struct intel_link_m_n *m_n) | |
6296 | { | |
6297 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6298 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
6299 | int pipe = crtc->pipe; |
6300 | ||
e3b95f1e DV |
6301 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6302 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6303 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6304 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6305 | } |
6306 | ||
6307 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6308 | struct intel_link_m_n *m_n, |
6309 | struct intel_link_m_n *m2_n2) | |
b551842d | 6310 | { |
6315b5d3 | 6311 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 6312 | int pipe = crtc->pipe; |
6e3c9717 | 6313 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 6314 | |
6315b5d3 | 6315 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
6316 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6317 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6318 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6319 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6320 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6321 | * for gen < 8) and if DRRS is supported (to make sure the | |
6322 | * registers are not unnecessarily accessed). | |
6323 | */ | |
920a14b2 TU |
6324 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
6325 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
6326 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6327 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6328 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6329 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6330 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6331 | } | |
b551842d | 6332 | } else { |
e3b95f1e DV |
6333 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6334 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6335 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6336 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6337 | } |
6338 | } | |
6339 | ||
fe3cd48d | 6340 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6341 | { |
fe3cd48d R |
6342 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6343 | ||
6344 | if (m_n == M1_N1) { | |
6345 | dp_m_n = &crtc->config->dp_m_n; | |
6346 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6347 | } else if (m_n == M2_N2) { | |
6348 | ||
6349 | /* | |
6350 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6351 | * needs to be programmed into M1_N1. | |
6352 | */ | |
6353 | dp_m_n = &crtc->config->dp_m2_n2; | |
6354 | } else { | |
6355 | DRM_ERROR("Unsupported divider value\n"); | |
6356 | return; | |
6357 | } | |
6358 | ||
6e3c9717 ACO |
6359 | if (crtc->config->has_pch_encoder) |
6360 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6361 | else |
fe3cd48d | 6362 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6363 | } |
6364 | ||
251ac862 DV |
6365 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
6366 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 6367 | { |
03ed5cbf | 6368 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 6369 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6370 | if (crtc->pipe != PIPE_A) |
6371 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 6372 | |
cd2d34d9 | 6373 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6374 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6375 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
6376 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
6377 | ||
03ed5cbf VS |
6378 | pipe_config->dpll_hw_state.dpll_md = |
6379 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6380 | } | |
bdd4b6a6 | 6381 | |
03ed5cbf VS |
6382 | static void chv_compute_dpll(struct intel_crtc *crtc, |
6383 | struct intel_crtc_state *pipe_config) | |
6384 | { | |
6385 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 6386 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6387 | if (crtc->pipe != PIPE_A) |
6388 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6389 | ||
cd2d34d9 | 6390 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6391 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6392 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
6393 | ||
03ed5cbf VS |
6394 | pipe_config->dpll_hw_state.dpll_md = |
6395 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
6396 | } |
6397 | ||
d288f65f | 6398 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6399 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6400 | { |
f47709a9 | 6401 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6402 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6403 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 6404 | u32 mdiv; |
a0c4da24 | 6405 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6406 | u32 coreclk, reg_val; |
a0c4da24 | 6407 | |
cd2d34d9 VS |
6408 | /* Enable Refclk */ |
6409 | I915_WRITE(DPLL(pipe), | |
6410 | pipe_config->dpll_hw_state.dpll & | |
6411 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
6412 | ||
6413 | /* No need to actually set up the DPLL with DSI */ | |
6414 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6415 | return; | |
6416 | ||
a580516d | 6417 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 6418 | |
d288f65f VS |
6419 | bestn = pipe_config->dpll.n; |
6420 | bestm1 = pipe_config->dpll.m1; | |
6421 | bestm2 = pipe_config->dpll.m2; | |
6422 | bestp1 = pipe_config->dpll.p1; | |
6423 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6424 | |
89b667f8 JB |
6425 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6426 | ||
6427 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6428 | if (pipe == PIPE_B) |
5e69f97f | 6429 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6430 | |
6431 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6432 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6433 | |
6434 | /* Disable target IRef on PLL */ | |
ab3c759a | 6435 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6436 | reg_val &= 0x00ffffff; |
ab3c759a | 6437 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6438 | |
6439 | /* Disable fast lock */ | |
ab3c759a | 6440 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6441 | |
6442 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6443 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6444 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6445 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6446 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6447 | |
6448 | /* | |
6449 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6450 | * but we don't support that). | |
6451 | * Note: don't use the DAC post divider as it seems unstable. | |
6452 | */ | |
6453 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6454 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6455 | |
a0c4da24 | 6456 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6457 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6458 | |
89b667f8 | 6459 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6460 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
6461 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
6462 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6463 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6464 | 0x009f0003); |
89b667f8 | 6465 | else |
ab3c759a | 6466 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6467 | 0x00d0000f); |
6468 | ||
37a5650b | 6469 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 6470 | /* Use SSC source */ |
bdd4b6a6 | 6471 | if (pipe == PIPE_A) |
ab3c759a | 6472 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6473 | 0x0df40000); |
6474 | else | |
ab3c759a | 6475 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6476 | 0x0df70000); |
6477 | } else { /* HDMI or VGA */ | |
6478 | /* Use bend source */ | |
bdd4b6a6 | 6479 | if (pipe == PIPE_A) |
ab3c759a | 6480 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6481 | 0x0df70000); |
6482 | else | |
ab3c759a | 6483 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6484 | 0x0df40000); |
6485 | } | |
a0c4da24 | 6486 | |
ab3c759a | 6487 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6488 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 6489 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 6490 | coreclk |= 0x01000000; |
ab3c759a | 6491 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6492 | |
ab3c759a | 6493 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 6494 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
6495 | } |
6496 | ||
d288f65f | 6497 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6498 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6499 | { |
6500 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6501 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6502 | enum pipe pipe = crtc->pipe; |
9d556c99 | 6503 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 6504 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6505 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6506 | u32 dpio_val; |
9cbe40c1 | 6507 | int vco; |
9d556c99 | 6508 | |
cd2d34d9 VS |
6509 | /* Enable Refclk and SSC */ |
6510 | I915_WRITE(DPLL(pipe), | |
6511 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
6512 | ||
6513 | /* No need to actually set up the DPLL with DSI */ | |
6514 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6515 | return; | |
6516 | ||
d288f65f VS |
6517 | bestn = pipe_config->dpll.n; |
6518 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6519 | bestm1 = pipe_config->dpll.m1; | |
6520 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6521 | bestp1 = pipe_config->dpll.p1; | |
6522 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6523 | vco = pipe_config->dpll.vco; |
a945ce7e | 6524 | dpio_val = 0; |
9cbe40c1 | 6525 | loopfilter = 0; |
9d556c99 | 6526 | |
a580516d | 6527 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 6528 | |
9d556c99 CML |
6529 | /* p1 and p2 divider */ |
6530 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6531 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6532 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6533 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6534 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6535 | ||
6536 | /* Feedback post-divider - m2 */ | |
6537 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6538 | ||
6539 | /* Feedback refclk divider - n and m1 */ | |
6540 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6541 | DPIO_CHV_M1_DIV_BY_2 | | |
6542 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6543 | ||
6544 | /* M2 fraction division */ | |
25a25dfc | 6545 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
6546 | |
6547 | /* M2 fraction division enable */ | |
a945ce7e VP |
6548 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6549 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6550 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6551 | if (bestm2_frac) | |
6552 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6553 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6554 | |
de3a0fde VP |
6555 | /* Program digital lock detect threshold */ |
6556 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6557 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6558 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6559 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6560 | if (!bestm2_frac) | |
6561 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6562 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6563 | ||
9d556c99 | 6564 | /* Loop filter */ |
9cbe40c1 VP |
6565 | if (vco == 5400000) { |
6566 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6567 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6568 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6569 | tribuf_calcntr = 0x9; | |
6570 | } else if (vco <= 6200000) { | |
6571 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6572 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6573 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6574 | tribuf_calcntr = 0x9; | |
6575 | } else if (vco <= 6480000) { | |
6576 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6577 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6578 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6579 | tribuf_calcntr = 0x8; | |
6580 | } else { | |
6581 | /* Not supported. Apply the same limits as in the max case */ | |
6582 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6583 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6584 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6585 | tribuf_calcntr = 0; | |
6586 | } | |
9d556c99 CML |
6587 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6588 | ||
968040b2 | 6589 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6590 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6591 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6592 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6593 | ||
9d556c99 CML |
6594 | /* AFC Recal */ |
6595 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6596 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6597 | DPIO_AFC_RECAL); | |
6598 | ||
a580516d | 6599 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
6600 | } |
6601 | ||
d288f65f VS |
6602 | /** |
6603 | * vlv_force_pll_on - forcibly enable just the PLL | |
6604 | * @dev_priv: i915 private structure | |
6605 | * @pipe: pipe PLL to enable | |
6606 | * @dpll: PLL configuration | |
6607 | * | |
6608 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6609 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6610 | * be enabled. | |
6611 | */ | |
30ad9814 | 6612 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 6613 | const struct dpll *dpll) |
d288f65f | 6614 | { |
b91eb5cc | 6615 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
6616 | struct intel_crtc_state *pipe_config; |
6617 | ||
6618 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
6619 | if (!pipe_config) | |
6620 | return -ENOMEM; | |
6621 | ||
6622 | pipe_config->base.crtc = &crtc->base; | |
6623 | pipe_config->pixel_multiplier = 1; | |
6624 | pipe_config->dpll = *dpll; | |
d288f65f | 6625 | |
30ad9814 | 6626 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
6627 | chv_compute_dpll(crtc, pipe_config); |
6628 | chv_prepare_pll(crtc, pipe_config); | |
6629 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 6630 | } else { |
3f36b937 TU |
6631 | vlv_compute_dpll(crtc, pipe_config); |
6632 | vlv_prepare_pll(crtc, pipe_config); | |
6633 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 6634 | } |
3f36b937 TU |
6635 | |
6636 | kfree(pipe_config); | |
6637 | ||
6638 | return 0; | |
d288f65f VS |
6639 | } |
6640 | ||
6641 | /** | |
6642 | * vlv_force_pll_off - forcibly disable just the PLL | |
6643 | * @dev_priv: i915 private structure | |
6644 | * @pipe: pipe PLL to disable | |
6645 | * | |
6646 | * Disable the PLL for @pipe. To be used in cases where we need | |
6647 | * the PLL enabled even when @pipe is not going to be enabled. | |
6648 | */ | |
30ad9814 | 6649 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 6650 | { |
30ad9814 VS |
6651 | if (IS_CHERRYVIEW(dev_priv)) |
6652 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 6653 | else |
30ad9814 | 6654 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
6655 | } |
6656 | ||
251ac862 DV |
6657 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
6658 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6659 | struct dpll *reduced_clock) |
eb1cbe48 | 6660 | { |
9b1e14f4 | 6661 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 6662 | u32 dpll; |
190f68c5 | 6663 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6664 | |
190f68c5 | 6665 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6666 | |
eb1cbe48 DV |
6667 | dpll = DPLL_VGA_MODE_DIS; |
6668 | ||
2d84d2b3 | 6669 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6670 | dpll |= DPLLB_MODE_LVDS; |
6671 | else | |
6672 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6673 | |
73f67aa8 JN |
6674 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
6675 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 6676 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6677 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6678 | } |
198a037f | 6679 | |
3d6e9ee0 VS |
6680 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6681 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 6682 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6683 | |
37a5650b | 6684 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 6685 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6686 | |
6687 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 6688 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
6689 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
6690 | else { | |
6691 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 6692 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
6693 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6694 | } | |
6695 | switch (clock->p2) { | |
6696 | case 5: | |
6697 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6698 | break; | |
6699 | case 7: | |
6700 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6701 | break; | |
6702 | case 10: | |
6703 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6704 | break; | |
6705 | case 14: | |
6706 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6707 | break; | |
6708 | } | |
9b1e14f4 | 6709 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
6710 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
6711 | ||
190f68c5 | 6712 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6713 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 6714 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6715 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6716 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6717 | else | |
6718 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6719 | ||
6720 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6721 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6722 | |
9b1e14f4 | 6723 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 6724 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6725 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6726 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6727 | } |
6728 | } | |
6729 | ||
251ac862 DV |
6730 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
6731 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6732 | struct dpll *reduced_clock) |
eb1cbe48 | 6733 | { |
f47709a9 | 6734 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6735 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 6736 | u32 dpll; |
190f68c5 | 6737 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6738 | |
190f68c5 | 6739 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6740 | |
eb1cbe48 DV |
6741 | dpll = DPLL_VGA_MODE_DIS; |
6742 | ||
2d84d2b3 | 6743 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6744 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6745 | } else { | |
6746 | if (clock->p1 == 2) | |
6747 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6748 | else | |
6749 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6750 | if (clock->p2 == 4) | |
6751 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6752 | } | |
6753 | ||
50a0bc90 TU |
6754 | if (!IS_I830(dev_priv) && |
6755 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
6756 | dpll |= DPLL_DVO_2X_MODE; |
6757 | ||
2d84d2b3 | 6758 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6759 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6760 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6761 | else | |
6762 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6763 | ||
6764 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6765 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6766 | } |
6767 | ||
8a654f3b | 6768 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 6769 | { |
6315b5d3 | 6770 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 6771 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 6772 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 6773 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6774 | uint32_t crtc_vtotal, crtc_vblank_end; |
6775 | int vsyncshift = 0; | |
4d8a62ea DV |
6776 | |
6777 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6778 | * the hw state checker will get angry at the mismatch. */ | |
6779 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6780 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6781 | |
609aeaca | 6782 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6783 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6784 | crtc_vtotal -= 1; |
6785 | crtc_vblank_end -= 1; | |
609aeaca | 6786 | |
2d84d2b3 | 6787 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6788 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6789 | else | |
6790 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6791 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6792 | if (vsyncshift < 0) |
6793 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6794 | } |
6795 | ||
6315b5d3 | 6796 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 6797 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6798 | |
fe2b8f9d | 6799 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6800 | (adjusted_mode->crtc_hdisplay - 1) | |
6801 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6802 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6803 | (adjusted_mode->crtc_hblank_start - 1) | |
6804 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6805 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6806 | (adjusted_mode->crtc_hsync_start - 1) | |
6807 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6808 | ||
fe2b8f9d | 6809 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6810 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6811 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6812 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6813 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6814 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6815 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6816 | (adjusted_mode->crtc_vsync_start - 1) | |
6817 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6818 | ||
b5e508d4 PZ |
6819 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6820 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6821 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6822 | * bits. */ | |
772c2a51 | 6823 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
6824 | (pipe == PIPE_B || pipe == PIPE_C)) |
6825 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6826 | ||
bc58be60 JN |
6827 | } |
6828 | ||
6829 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
6830 | { | |
6831 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 6832 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
6833 | enum pipe pipe = intel_crtc->pipe; |
6834 | ||
b0e77b9c PZ |
6835 | /* pipesrc controls the size that is scaled from, which should |
6836 | * always be the user's requested size. | |
6837 | */ | |
6838 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6839 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6840 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6841 | } |
6842 | ||
1bd1bd80 | 6843 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6844 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6845 | { |
6846 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6847 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
6848 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
6849 | uint32_t tmp; | |
6850 | ||
6851 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6852 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6853 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6854 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6855 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6856 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6857 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6858 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6859 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6860 | |
6861 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6862 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6863 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6864 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6865 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6866 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6867 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6868 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6869 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6870 | |
6871 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6872 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6873 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6874 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 6875 | } |
bc58be60 JN |
6876 | } |
6877 | ||
6878 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
6879 | struct intel_crtc_state *pipe_config) | |
6880 | { | |
6881 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6882 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 6883 | u32 tmp; |
1bd1bd80 DV |
6884 | |
6885 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6886 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6887 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6888 | ||
2d112de7 ACO |
6889 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
6890 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6891 | } |
6892 | ||
f6a83288 | 6893 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 6894 | struct intel_crtc_state *pipe_config) |
babea61d | 6895 | { |
2d112de7 ACO |
6896 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
6897 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
6898 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
6899 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 6900 | |
2d112de7 ACO |
6901 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
6902 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
6903 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
6904 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 6905 | |
2d112de7 | 6906 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 6907 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 6908 | |
2d112de7 | 6909 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
cd13f5ab ML |
6910 | |
6911 | mode->hsync = drm_mode_hsync(mode); | |
6912 | mode->vrefresh = drm_mode_vrefresh(mode); | |
6913 | drm_mode_set_name(mode); | |
babea61d JB |
6914 | } |
6915 | ||
84b046f3 DV |
6916 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6917 | { | |
6315b5d3 | 6918 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
6919 | uint32_t pipeconf; |
6920 | ||
9f11a9e4 | 6921 | pipeconf = 0; |
84b046f3 | 6922 | |
e56134bc VS |
6923 | /* we keep both pipes enabled on 830 */ |
6924 | if (IS_I830(dev_priv)) | |
b6b5d049 | 6925 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; |
67c72a12 | 6926 | |
6e3c9717 | 6927 | if (intel_crtc->config->double_wide) |
cf532bb2 | 6928 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 6929 | |
ff9ce46e | 6930 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
6931 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
6932 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 6933 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 6934 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 6935 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 6936 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6937 | |
6e3c9717 | 6938 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
6939 | case 18: |
6940 | pipeconf |= PIPECONF_6BPC; | |
6941 | break; | |
6942 | case 24: | |
6943 | pipeconf |= PIPECONF_8BPC; | |
6944 | break; | |
6945 | case 30: | |
6946 | pipeconf |= PIPECONF_10BPC; | |
6947 | break; | |
6948 | default: | |
6949 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6950 | BUG(); | |
84b046f3 DV |
6951 | } |
6952 | } | |
6953 | ||
56b857a5 | 6954 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
6955 | if (intel_crtc->lowfreq_avail) { |
6956 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6957 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6958 | } else { | |
6959 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6960 | } |
6961 | } | |
6962 | ||
6e3c9717 | 6963 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 6964 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 6965 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
6966 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6967 | else | |
6968 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6969 | } else | |
84b046f3 DV |
6970 | pipeconf |= PIPECONF_PROGRESSIVE; |
6971 | ||
920a14b2 | 6972 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 6973 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 6974 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 6975 | |
84b046f3 DV |
6976 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6977 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6978 | } | |
6979 | ||
81c97f52 ACO |
6980 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
6981 | struct intel_crtc_state *crtc_state) | |
6982 | { | |
6983 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6984 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 6985 | const struct intel_limit *limit; |
81c97f52 ACO |
6986 | int refclk = 48000; |
6987 | ||
6988 | memset(&crtc_state->dpll_hw_state, 0, | |
6989 | sizeof(crtc_state->dpll_hw_state)); | |
6990 | ||
2d84d2b3 | 6991 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
6992 | if (intel_panel_use_ssc(dev_priv)) { |
6993 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
6994 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
6995 | } | |
6996 | ||
6997 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 6998 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
6999 | limit = &intel_limits_i8xx_dvo; |
7000 | } else { | |
7001 | limit = &intel_limits_i8xx_dac; | |
7002 | } | |
7003 | ||
7004 | if (!crtc_state->clock_set && | |
7005 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7006 | refclk, NULL, &crtc_state->dpll)) { | |
7007 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7008 | return -EINVAL; | |
7009 | } | |
7010 | ||
7011 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7012 | ||
7013 | return 0; | |
7014 | } | |
7015 | ||
19ec6693 ACO |
7016 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7017 | struct intel_crtc_state *crtc_state) | |
7018 | { | |
7019 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7020 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7021 | const struct intel_limit *limit; |
19ec6693 ACO |
7022 | int refclk = 96000; |
7023 | ||
7024 | memset(&crtc_state->dpll_hw_state, 0, | |
7025 | sizeof(crtc_state->dpll_hw_state)); | |
7026 | ||
2d84d2b3 | 7027 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7028 | if (intel_panel_use_ssc(dev_priv)) { |
7029 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7030 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7031 | } | |
7032 | ||
7033 | if (intel_is_dual_link_lvds(dev)) | |
7034 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7035 | else | |
7036 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7037 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7038 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7039 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7040 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7041 | limit = &intel_limits_g4x_sdvo; |
7042 | } else { | |
7043 | /* The option is for other outputs */ | |
7044 | limit = &intel_limits_i9xx_sdvo; | |
7045 | } | |
7046 | ||
7047 | if (!crtc_state->clock_set && | |
7048 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7049 | refclk, NULL, &crtc_state->dpll)) { | |
7050 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7051 | return -EINVAL; | |
7052 | } | |
7053 | ||
7054 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7055 | ||
7056 | return 0; | |
7057 | } | |
7058 | ||
70e8aa21 ACO |
7059 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7060 | struct intel_crtc_state *crtc_state) | |
7061 | { | |
7062 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7063 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7064 | const struct intel_limit *limit; |
70e8aa21 ACO |
7065 | int refclk = 96000; |
7066 | ||
7067 | memset(&crtc_state->dpll_hw_state, 0, | |
7068 | sizeof(crtc_state->dpll_hw_state)); | |
7069 | ||
2d84d2b3 | 7070 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7071 | if (intel_panel_use_ssc(dev_priv)) { |
7072 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7073 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7074 | } | |
7075 | ||
7076 | limit = &intel_limits_pineview_lvds; | |
7077 | } else { | |
7078 | limit = &intel_limits_pineview_sdvo; | |
7079 | } | |
7080 | ||
7081 | if (!crtc_state->clock_set && | |
7082 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7083 | refclk, NULL, &crtc_state->dpll)) { | |
7084 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7085 | return -EINVAL; | |
7086 | } | |
7087 | ||
7088 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7089 | ||
7090 | return 0; | |
7091 | } | |
7092 | ||
190f68c5 ACO |
7093 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7094 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7095 | { |
c7653199 | 7096 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7097 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7098 | const struct intel_limit *limit; |
81c97f52 | 7099 | int refclk = 96000; |
79e53945 | 7100 | |
dd3cd74a ACO |
7101 | memset(&crtc_state->dpll_hw_state, 0, |
7102 | sizeof(crtc_state->dpll_hw_state)); | |
7103 | ||
2d84d2b3 | 7104 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7105 | if (intel_panel_use_ssc(dev_priv)) { |
7106 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7107 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7108 | } | |
43565a06 | 7109 | |
70e8aa21 ACO |
7110 | limit = &intel_limits_i9xx_lvds; |
7111 | } else { | |
7112 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7113 | } |
79e53945 | 7114 | |
70e8aa21 ACO |
7115 | if (!crtc_state->clock_set && |
7116 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7117 | refclk, NULL, &crtc_state->dpll)) { | |
7118 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7119 | return -EINVAL; | |
f47709a9 | 7120 | } |
7026d4ac | 7121 | |
81c97f52 | 7122 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7123 | |
c8f7a0db | 7124 | return 0; |
f564048e EA |
7125 | } |
7126 | ||
65b3d6a9 ACO |
7127 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7128 | struct intel_crtc_state *crtc_state) | |
7129 | { | |
7130 | int refclk = 100000; | |
1b6f4958 | 7131 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7132 | |
7133 | memset(&crtc_state->dpll_hw_state, 0, | |
7134 | sizeof(crtc_state->dpll_hw_state)); | |
7135 | ||
65b3d6a9 ACO |
7136 | if (!crtc_state->clock_set && |
7137 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7138 | refclk, NULL, &crtc_state->dpll)) { | |
7139 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7140 | return -EINVAL; | |
7141 | } | |
7142 | ||
7143 | chv_compute_dpll(crtc, crtc_state); | |
7144 | ||
7145 | return 0; | |
7146 | } | |
7147 | ||
7148 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7149 | struct intel_crtc_state *crtc_state) | |
7150 | { | |
7151 | int refclk = 100000; | |
1b6f4958 | 7152 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7153 | |
7154 | memset(&crtc_state->dpll_hw_state, 0, | |
7155 | sizeof(crtc_state->dpll_hw_state)); | |
7156 | ||
65b3d6a9 ACO |
7157 | if (!crtc_state->clock_set && |
7158 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7159 | refclk, NULL, &crtc_state->dpll)) { | |
7160 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7161 | return -EINVAL; | |
7162 | } | |
7163 | ||
7164 | vlv_compute_dpll(crtc, crtc_state); | |
7165 | ||
7166 | return 0; | |
7167 | } | |
7168 | ||
2fa2fe9a | 7169 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7170 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 7171 | { |
6315b5d3 | 7172 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
7173 | uint32_t tmp; |
7174 | ||
50a0bc90 TU |
7175 | if (INTEL_GEN(dev_priv) <= 3 && |
7176 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
7177 | return; |
7178 | ||
2fa2fe9a | 7179 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7180 | if (!(tmp & PFIT_ENABLE)) |
7181 | return; | |
2fa2fe9a | 7182 | |
06922821 | 7183 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 7184 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
7185 | if (crtc->pipe != PIPE_B) |
7186 | return; | |
2fa2fe9a DV |
7187 | } else { |
7188 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7189 | return; | |
7190 | } | |
7191 | ||
06922821 | 7192 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7193 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7194 | } |
7195 | ||
acbec814 | 7196 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7197 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7198 | { |
7199 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7200 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 7201 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 7202 | struct dpll clock; |
acbec814 | 7203 | u32 mdiv; |
662c6ecb | 7204 | int refclk = 100000; |
acbec814 | 7205 | |
b521973b VS |
7206 | /* In case of DSI, DPLL will not be used */ |
7207 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
7208 | return; |
7209 | ||
a580516d | 7210 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7211 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7212 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7213 | |
7214 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7215 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7216 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7217 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7218 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7219 | ||
dccbea3b | 7220 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7221 | } |
7222 | ||
5724dbd1 DL |
7223 | static void |
7224 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7225 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7226 | { |
7227 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7228 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
7229 | u32 val, base, offset; |
7230 | int pipe = crtc->pipe, plane = crtc->plane; | |
7231 | int fourcc, pixel_format; | |
6761dd31 | 7232 | unsigned int aligned_height; |
b113d5ee | 7233 | struct drm_framebuffer *fb; |
1b842c89 | 7234 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7235 | |
42a7b088 DL |
7236 | val = I915_READ(DSPCNTR(plane)); |
7237 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7238 | return; | |
7239 | ||
d9806c9f | 7240 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7241 | if (!intel_fb) { |
1ad292b5 JB |
7242 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7243 | return; | |
7244 | } | |
7245 | ||
1b842c89 DL |
7246 | fb = &intel_fb->base; |
7247 | ||
d2e9f5fc VS |
7248 | fb->dev = dev; |
7249 | ||
6315b5d3 | 7250 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 7251 | if (val & DISPPLANE_TILED) { |
49af449b | 7252 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 7253 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
7254 | } |
7255 | } | |
1ad292b5 JB |
7256 | |
7257 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7258 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 7259 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 7260 | |
6315b5d3 | 7261 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 7262 | if (plane_config->tiling) |
1ad292b5 JB |
7263 | offset = I915_READ(DSPTILEOFF(plane)); |
7264 | else | |
7265 | offset = I915_READ(DSPLINOFF(plane)); | |
7266 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7267 | } else { | |
7268 | base = I915_READ(DSPADDR(plane)); | |
7269 | } | |
7270 | plane_config->base = base; | |
7271 | ||
7272 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7273 | fb->width = ((val >> 16) & 0xfff) + 1; |
7274 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7275 | |
7276 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7277 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7278 | |
d88c4afd | 7279 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1ad292b5 | 7280 | |
f37b5c2b | 7281 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7282 | |
2844a921 DL |
7283 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7284 | pipe_name(pipe), plane, fb->width, fb->height, | |
272725c7 | 7285 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 7286 | plane_config->size); |
1ad292b5 | 7287 | |
2d14030b | 7288 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7289 | } |
7290 | ||
70b23a98 | 7291 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7292 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7293 | { |
7294 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7295 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
7296 | int pipe = pipe_config->cpu_transcoder; |
7297 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 7298 | struct dpll clock; |
0d7b6b11 | 7299 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
7300 | int refclk = 100000; |
7301 | ||
b521973b VS |
7302 | /* In case of DSI, DPLL will not be used */ |
7303 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7304 | return; | |
7305 | ||
a580516d | 7306 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7307 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7308 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7309 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7310 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 7311 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 7312 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7313 | |
7314 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
7315 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7316 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
7317 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
7318 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7319 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7320 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7321 | ||
dccbea3b | 7322 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
7323 | } |
7324 | ||
0e8ffe1b | 7325 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7326 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 7327 | { |
6315b5d3 | 7328 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 7329 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 7330 | uint32_t tmp; |
1729050e | 7331 | bool ret; |
0e8ffe1b | 7332 | |
1729050e ID |
7333 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
7334 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
7335 | return false; |
7336 | ||
e143a21c | 7337 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 7338 | pipe_config->shared_dpll = NULL; |
eccb140b | 7339 | |
1729050e ID |
7340 | ret = false; |
7341 | ||
0e8ffe1b DV |
7342 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7343 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 7344 | goto out; |
0e8ffe1b | 7345 | |
9beb5fea TU |
7346 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7347 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
7348 | switch (tmp & PIPECONF_BPC_MASK) { |
7349 | case PIPECONF_6BPC: | |
7350 | pipe_config->pipe_bpp = 18; | |
7351 | break; | |
7352 | case PIPECONF_8BPC: | |
7353 | pipe_config->pipe_bpp = 24; | |
7354 | break; | |
7355 | case PIPECONF_10BPC: | |
7356 | pipe_config->pipe_bpp = 30; | |
7357 | break; | |
7358 | default: | |
7359 | break; | |
7360 | } | |
7361 | } | |
7362 | ||
920a14b2 | 7363 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7364 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
7365 | pipe_config->limited_color_range = true; |
7366 | ||
6315b5d3 | 7367 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
7368 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
7369 | ||
1bd1bd80 | 7370 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 7371 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 7372 | |
2fa2fe9a DV |
7373 | i9xx_get_pfit_config(crtc, pipe_config); |
7374 | ||
6315b5d3 | 7375 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 7376 | /* No way to read it out on pipes B and C */ |
920a14b2 | 7377 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
7378 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
7379 | else | |
7380 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
7381 | pipe_config->pixel_multiplier = |
7382 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7383 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7384 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 7385 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 7386 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
7387 | tmp = I915_READ(DPLL(crtc->pipe)); |
7388 | pipe_config->pixel_multiplier = | |
7389 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7390 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7391 | } else { | |
7392 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7393 | * port and will be fixed up in the encoder->get_config | |
7394 | * function. */ | |
7395 | pipe_config->pixel_multiplier = 1; | |
7396 | } | |
8bcc2795 | 7397 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 7398 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
7399 | /* |
7400 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7401 | * on 830. Filter it out here so that we don't | |
7402 | * report errors due to that. | |
7403 | */ | |
50a0bc90 | 7404 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
7405 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
7406 | ||
8bcc2795 DV |
7407 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7408 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7409 | } else { |
7410 | /* Mask out read-only status bits. */ | |
7411 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7412 | DPLL_PORTC_READY_MASK | | |
7413 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7414 | } |
6c49f241 | 7415 | |
920a14b2 | 7416 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 7417 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 7418 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
7419 | vlv_crtc_clock_get(crtc, pipe_config); |
7420 | else | |
7421 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7422 | |
0f64614d VS |
7423 | /* |
7424 | * Normally the dotclock is filled in by the encoder .get_config() | |
7425 | * but in case the pipe is enabled w/o any ports we need a sane | |
7426 | * default. | |
7427 | */ | |
7428 | pipe_config->base.adjusted_mode.crtc_clock = | |
7429 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
7430 | ||
1729050e ID |
7431 | ret = true; |
7432 | ||
7433 | out: | |
7434 | intel_display_power_put(dev_priv, power_domain); | |
7435 | ||
7436 | return ret; | |
0e8ffe1b DV |
7437 | } |
7438 | ||
c39055b0 | 7439 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 7440 | { |
13d83a67 | 7441 | struct intel_encoder *encoder; |
1c1a24d2 | 7442 | int i; |
74cfd7ac | 7443 | u32 val, final; |
13d83a67 | 7444 | bool has_lvds = false; |
199e5d79 | 7445 | bool has_cpu_edp = false; |
199e5d79 | 7446 | bool has_panel = false; |
99eb6a01 KP |
7447 | bool has_ck505 = false; |
7448 | bool can_ssc = false; | |
1c1a24d2 | 7449 | bool using_ssc_source = false; |
13d83a67 JB |
7450 | |
7451 | /* We need to take the global config into account */ | |
c39055b0 | 7452 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
7453 | switch (encoder->type) { |
7454 | case INTEL_OUTPUT_LVDS: | |
7455 | has_panel = true; | |
7456 | has_lvds = true; | |
7457 | break; | |
7458 | case INTEL_OUTPUT_EDP: | |
7459 | has_panel = true; | |
2de6905f | 7460 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7461 | has_cpu_edp = true; |
7462 | break; | |
6847d71b PZ |
7463 | default: |
7464 | break; | |
13d83a67 JB |
7465 | } |
7466 | } | |
7467 | ||
6e266956 | 7468 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 7469 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7470 | can_ssc = has_ck505; |
7471 | } else { | |
7472 | has_ck505 = false; | |
7473 | can_ssc = true; | |
7474 | } | |
7475 | ||
1c1a24d2 L |
7476 | /* Check if any DPLLs are using the SSC source */ |
7477 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
7478 | u32 temp = I915_READ(PCH_DPLL(i)); | |
7479 | ||
7480 | if (!(temp & DPLL_VCO_ENABLE)) | |
7481 | continue; | |
7482 | ||
7483 | if ((temp & PLL_REF_INPUT_MASK) == | |
7484 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7485 | using_ssc_source = true; | |
7486 | break; | |
7487 | } | |
7488 | } | |
7489 | ||
7490 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
7491 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
7492 | |
7493 | /* Ironlake: try to setup display ref clock before DPLL | |
7494 | * enabling. This is only under driver's control after | |
7495 | * PCH B stepping, previous chipset stepping should be | |
7496 | * ignoring this setting. | |
7497 | */ | |
74cfd7ac CW |
7498 | val = I915_READ(PCH_DREF_CONTROL); |
7499 | ||
7500 | /* As we must carefully and slowly disable/enable each source in turn, | |
7501 | * compute the final state we want first and check if we need to | |
7502 | * make any changes at all. | |
7503 | */ | |
7504 | final = val; | |
7505 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7506 | if (has_ck505) | |
7507 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7508 | else | |
7509 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7510 | ||
8c07eb68 | 7511 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 7512 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 7513 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
7514 | |
7515 | if (has_panel) { | |
7516 | final |= DREF_SSC_SOURCE_ENABLE; | |
7517 | ||
7518 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7519 | final |= DREF_SSC1_ENABLE; | |
7520 | ||
7521 | if (has_cpu_edp) { | |
7522 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7523 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7524 | else | |
7525 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7526 | } else | |
7527 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
7528 | } else if (using_ssc_source) { |
7529 | final |= DREF_SSC_SOURCE_ENABLE; | |
7530 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
7531 | } |
7532 | ||
7533 | if (final == val) | |
7534 | return; | |
7535 | ||
13d83a67 | 7536 | /* Always enable nonspread source */ |
74cfd7ac | 7537 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7538 | |
99eb6a01 | 7539 | if (has_ck505) |
74cfd7ac | 7540 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7541 | else |
74cfd7ac | 7542 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7543 | |
199e5d79 | 7544 | if (has_panel) { |
74cfd7ac CW |
7545 | val &= ~DREF_SSC_SOURCE_MASK; |
7546 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7547 | |
199e5d79 | 7548 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7549 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7550 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7551 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7552 | } else |
74cfd7ac | 7553 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7554 | |
7555 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7556 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7557 | POSTING_READ(PCH_DREF_CONTROL); |
7558 | udelay(200); | |
7559 | ||
74cfd7ac | 7560 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7561 | |
7562 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7563 | if (has_cpu_edp) { |
99eb6a01 | 7564 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7565 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7566 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7567 | } else |
74cfd7ac | 7568 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7569 | } else |
74cfd7ac | 7570 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7571 | |
74cfd7ac | 7572 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7573 | POSTING_READ(PCH_DREF_CONTROL); |
7574 | udelay(200); | |
7575 | } else { | |
1c1a24d2 | 7576 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 7577 | |
74cfd7ac | 7578 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7579 | |
7580 | /* Turn off CPU output */ | |
74cfd7ac | 7581 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7582 | |
74cfd7ac | 7583 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7584 | POSTING_READ(PCH_DREF_CONTROL); |
7585 | udelay(200); | |
7586 | ||
1c1a24d2 L |
7587 | if (!using_ssc_source) { |
7588 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 7589 | |
1c1a24d2 L |
7590 | /* Turn off the SSC source */ |
7591 | val &= ~DREF_SSC_SOURCE_MASK; | |
7592 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 7593 | |
1c1a24d2 L |
7594 | /* Turn off SSC1 */ |
7595 | val &= ~DREF_SSC1_ENABLE; | |
7596 | ||
7597 | I915_WRITE(PCH_DREF_CONTROL, val); | |
7598 | POSTING_READ(PCH_DREF_CONTROL); | |
7599 | udelay(200); | |
7600 | } | |
13d83a67 | 7601 | } |
74cfd7ac CW |
7602 | |
7603 | BUG_ON(val != final); | |
13d83a67 JB |
7604 | } |
7605 | ||
f31f2d55 | 7606 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7607 | { |
f31f2d55 | 7608 | uint32_t tmp; |
dde86e2d | 7609 | |
0ff066a9 PZ |
7610 | tmp = I915_READ(SOUTH_CHICKEN2); |
7611 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7612 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7613 | |
cf3598c2 ID |
7614 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
7615 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 7616 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 7617 | |
0ff066a9 PZ |
7618 | tmp = I915_READ(SOUTH_CHICKEN2); |
7619 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7620 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7621 | |
cf3598c2 ID |
7622 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
7623 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 7624 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
7625 | } |
7626 | ||
7627 | /* WaMPhyProgramming:hsw */ | |
7628 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7629 | { | |
7630 | uint32_t tmp; | |
dde86e2d PZ |
7631 | |
7632 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7633 | tmp &= ~(0xFF << 24); | |
7634 | tmp |= (0x12 << 24); | |
7635 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7636 | ||
dde86e2d PZ |
7637 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7638 | tmp |= (1 << 11); | |
7639 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7640 | ||
7641 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7642 | tmp |= (1 << 11); | |
7643 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7644 | ||
dde86e2d PZ |
7645 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7646 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7647 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7648 | ||
7649 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7650 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7651 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7652 | ||
0ff066a9 PZ |
7653 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7654 | tmp &= ~(7 << 13); | |
7655 | tmp |= (5 << 13); | |
7656 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7657 | |
0ff066a9 PZ |
7658 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7659 | tmp &= ~(7 << 13); | |
7660 | tmp |= (5 << 13); | |
7661 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7662 | |
7663 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7664 | tmp &= ~0xFF; | |
7665 | tmp |= 0x1C; | |
7666 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7667 | ||
7668 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7669 | tmp &= ~0xFF; | |
7670 | tmp |= 0x1C; | |
7671 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7672 | ||
7673 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7674 | tmp &= ~(0xFF << 16); | |
7675 | tmp |= (0x1C << 16); | |
7676 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7677 | ||
7678 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7679 | tmp &= ~(0xFF << 16); | |
7680 | tmp |= (0x1C << 16); | |
7681 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7682 | ||
0ff066a9 PZ |
7683 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7684 | tmp |= (1 << 27); | |
7685 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7686 | |
0ff066a9 PZ |
7687 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7688 | tmp |= (1 << 27); | |
7689 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7690 | |
0ff066a9 PZ |
7691 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7692 | tmp &= ~(0xF << 28); | |
7693 | tmp |= (4 << 28); | |
7694 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7695 | |
0ff066a9 PZ |
7696 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7697 | tmp &= ~(0xF << 28); | |
7698 | tmp |= (4 << 28); | |
7699 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7700 | } |
7701 | ||
2fa86a1f PZ |
7702 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7703 | * Programming" based on the parameters passed: | |
7704 | * - Sequence to enable CLKOUT_DP | |
7705 | * - Sequence to enable CLKOUT_DP without spread | |
7706 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7707 | */ | |
c39055b0 ACO |
7708 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
7709 | bool with_spread, bool with_fdi) | |
f31f2d55 | 7710 | { |
2fa86a1f PZ |
7711 | uint32_t reg, tmp; |
7712 | ||
7713 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7714 | with_spread = true; | |
4f8036a2 TU |
7715 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
7716 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 7717 | with_fdi = false; |
f31f2d55 | 7718 | |
a580516d | 7719 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
7720 | |
7721 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7722 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7723 | tmp |= SBI_SSCCTL_PATHALT; | |
7724 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7725 | ||
7726 | udelay(24); | |
7727 | ||
2fa86a1f PZ |
7728 | if (with_spread) { |
7729 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7730 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7731 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7732 | |
2fa86a1f PZ |
7733 | if (with_fdi) { |
7734 | lpt_reset_fdi_mphy(dev_priv); | |
7735 | lpt_program_fdi_mphy(dev_priv); | |
7736 | } | |
7737 | } | |
dde86e2d | 7738 | |
4f8036a2 | 7739 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
7740 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7741 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7742 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 7743 | |
a580516d | 7744 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
7745 | } |
7746 | ||
47701c3b | 7747 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 7748 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 7749 | { |
47701c3b PZ |
7750 | uint32_t reg, tmp; |
7751 | ||
a580516d | 7752 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 7753 | |
4f8036a2 | 7754 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
7755 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7756 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7757 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7758 | ||
7759 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7760 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7761 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7762 | tmp |= SBI_SSCCTL_PATHALT; | |
7763 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7764 | udelay(32); | |
7765 | } | |
7766 | tmp |= SBI_SSCCTL_DISABLE; | |
7767 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7768 | } | |
7769 | ||
a580516d | 7770 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
7771 | } |
7772 | ||
f7be2c21 VS |
7773 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
7774 | ||
7775 | static const uint16_t sscdivintphase[] = { | |
7776 | [BEND_IDX( 50)] = 0x3B23, | |
7777 | [BEND_IDX( 45)] = 0x3B23, | |
7778 | [BEND_IDX( 40)] = 0x3C23, | |
7779 | [BEND_IDX( 35)] = 0x3C23, | |
7780 | [BEND_IDX( 30)] = 0x3D23, | |
7781 | [BEND_IDX( 25)] = 0x3D23, | |
7782 | [BEND_IDX( 20)] = 0x3E23, | |
7783 | [BEND_IDX( 15)] = 0x3E23, | |
7784 | [BEND_IDX( 10)] = 0x3F23, | |
7785 | [BEND_IDX( 5)] = 0x3F23, | |
7786 | [BEND_IDX( 0)] = 0x0025, | |
7787 | [BEND_IDX( -5)] = 0x0025, | |
7788 | [BEND_IDX(-10)] = 0x0125, | |
7789 | [BEND_IDX(-15)] = 0x0125, | |
7790 | [BEND_IDX(-20)] = 0x0225, | |
7791 | [BEND_IDX(-25)] = 0x0225, | |
7792 | [BEND_IDX(-30)] = 0x0325, | |
7793 | [BEND_IDX(-35)] = 0x0325, | |
7794 | [BEND_IDX(-40)] = 0x0425, | |
7795 | [BEND_IDX(-45)] = 0x0425, | |
7796 | [BEND_IDX(-50)] = 0x0525, | |
7797 | }; | |
7798 | ||
7799 | /* | |
7800 | * Bend CLKOUT_DP | |
7801 | * steps -50 to 50 inclusive, in steps of 5 | |
7802 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
7803 | * change in clock period = -(steps / 10) * 5.787 ps | |
7804 | */ | |
7805 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
7806 | { | |
7807 | uint32_t tmp; | |
7808 | int idx = BEND_IDX(steps); | |
7809 | ||
7810 | if (WARN_ON(steps % 5 != 0)) | |
7811 | return; | |
7812 | ||
7813 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
7814 | return; | |
7815 | ||
7816 | mutex_lock(&dev_priv->sb_lock); | |
7817 | ||
7818 | if (steps % 10 != 0) | |
7819 | tmp = 0xAAAAAAAB; | |
7820 | else | |
7821 | tmp = 0x00000000; | |
7822 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
7823 | ||
7824 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
7825 | tmp &= 0xffff0000; | |
7826 | tmp |= sscdivintphase[idx]; | |
7827 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
7828 | ||
7829 | mutex_unlock(&dev_priv->sb_lock); | |
7830 | } | |
7831 | ||
7832 | #undef BEND_IDX | |
7833 | ||
c39055b0 | 7834 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 7835 | { |
bf8fa3d3 PZ |
7836 | struct intel_encoder *encoder; |
7837 | bool has_vga = false; | |
7838 | ||
c39055b0 | 7839 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
7840 | switch (encoder->type) { |
7841 | case INTEL_OUTPUT_ANALOG: | |
7842 | has_vga = true; | |
7843 | break; | |
6847d71b PZ |
7844 | default: |
7845 | break; | |
bf8fa3d3 PZ |
7846 | } |
7847 | } | |
7848 | ||
f7be2c21 | 7849 | if (has_vga) { |
c39055b0 ACO |
7850 | lpt_bend_clkout_dp(dev_priv, 0); |
7851 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 7852 | } else { |
c39055b0 | 7853 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 7854 | } |
bf8fa3d3 PZ |
7855 | } |
7856 | ||
dde86e2d PZ |
7857 | /* |
7858 | * Initialize reference clocks when the driver loads | |
7859 | */ | |
c39055b0 | 7860 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 7861 | { |
6e266956 | 7862 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 7863 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 7864 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 7865 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
7866 | } |
7867 | ||
6ff93609 | 7868 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7869 | { |
fac5e23e | 7870 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
7871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7872 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7873 | uint32_t val; |
7874 | ||
78114071 | 7875 | val = 0; |
c8203565 | 7876 | |
6e3c9717 | 7877 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7878 | case 18: |
dfd07d72 | 7879 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7880 | break; |
7881 | case 24: | |
dfd07d72 | 7882 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7883 | break; |
7884 | case 30: | |
dfd07d72 | 7885 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7886 | break; |
7887 | case 36: | |
dfd07d72 | 7888 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7889 | break; |
7890 | default: | |
cc769b62 PZ |
7891 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7892 | BUG(); | |
c8203565 PZ |
7893 | } |
7894 | ||
6e3c9717 | 7895 | if (intel_crtc->config->dither) |
c8203565 PZ |
7896 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7897 | ||
6e3c9717 | 7898 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7899 | val |= PIPECONF_INTERLACED_ILK; |
7900 | else | |
7901 | val |= PIPECONF_PROGRESSIVE; | |
7902 | ||
6e3c9717 | 7903 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 7904 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7905 | |
c8203565 PZ |
7906 | I915_WRITE(PIPECONF(pipe), val); |
7907 | POSTING_READ(PIPECONF(pipe)); | |
7908 | } | |
7909 | ||
6ff93609 | 7910 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7911 | { |
fac5e23e | 7912 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 7913 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 7914 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 7915 | u32 val = 0; |
ee2b0b38 | 7916 | |
391bf048 | 7917 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
7918 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7919 | ||
6e3c9717 | 7920 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7921 | val |= PIPECONF_INTERLACED_ILK; |
7922 | else | |
7923 | val |= PIPECONF_PROGRESSIVE; | |
7924 | ||
702e7a56 PZ |
7925 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
7926 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
7927 | } |
7928 | ||
391bf048 JN |
7929 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
7930 | { | |
fac5e23e | 7931 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 7932 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 7933 | |
391bf048 JN |
7934 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
7935 | u32 val = 0; | |
756f85cf | 7936 | |
6e3c9717 | 7937 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
7938 | case 18: |
7939 | val |= PIPEMISC_DITHER_6_BPC; | |
7940 | break; | |
7941 | case 24: | |
7942 | val |= PIPEMISC_DITHER_8_BPC; | |
7943 | break; | |
7944 | case 30: | |
7945 | val |= PIPEMISC_DITHER_10_BPC; | |
7946 | break; | |
7947 | case 36: | |
7948 | val |= PIPEMISC_DITHER_12_BPC; | |
7949 | break; | |
7950 | default: | |
7951 | /* Case prevented by pipe_config_set_bpp. */ | |
7952 | BUG(); | |
7953 | } | |
7954 | ||
6e3c9717 | 7955 | if (intel_crtc->config->dither) |
756f85cf PZ |
7956 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
7957 | ||
391bf048 | 7958 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 7959 | } |
ee2b0b38 PZ |
7960 | } |
7961 | ||
d4b1931c PZ |
7962 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7963 | { | |
7964 | /* | |
7965 | * Account for spread spectrum to avoid | |
7966 | * oversubscribing the link. Max center spread | |
7967 | * is 2.5%; use 5% for safety's sake. | |
7968 | */ | |
7969 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7970 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7971 | } |
7972 | ||
7429e9d4 | 7973 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7974 | { |
7429e9d4 | 7975 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7976 | } |
7977 | ||
b75ca6f6 ACO |
7978 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7979 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7980 | struct dpll *reduced_clock) |
79e53945 | 7981 | { |
de13a2e3 | 7982 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 7983 | struct drm_device *dev = crtc->dev; |
fac5e23e | 7984 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 7985 | u32 dpll, fp, fp2; |
3d6e9ee0 | 7986 | int factor; |
79e53945 | 7987 | |
c1858123 | 7988 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 7989 | factor = 21; |
3d6e9ee0 | 7990 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 7991 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 7992 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 7993 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7994 | factor = 25; |
190f68c5 | 7995 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 7996 | factor = 20; |
c1858123 | 7997 | |
b75ca6f6 ACO |
7998 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
7999 | ||
190f68c5 | 8000 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8001 | fp |= FP_CB_TUNE; |
8002 | ||
8003 | if (reduced_clock) { | |
8004 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8005 | |
b75ca6f6 ACO |
8006 | if (reduced_clock->m < factor * reduced_clock->n) |
8007 | fp2 |= FP_CB_TUNE; | |
8008 | } else { | |
8009 | fp2 = fp; | |
8010 | } | |
9a7c7890 | 8011 | |
5eddb70b | 8012 | dpll = 0; |
2c07245f | 8013 | |
3d6e9ee0 | 8014 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8015 | dpll |= DPLLB_MODE_LVDS; |
8016 | else | |
8017 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8018 | |
190f68c5 | 8019 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8020 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8021 | |
3d6e9ee0 VS |
8022 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8023 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8024 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8025 | |
37a5650b | 8026 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8027 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8028 | |
7d7f8633 VS |
8029 | /* |
8030 | * The high speed IO clock is only really required for | |
8031 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
8032 | * possible to share the DPLL between CRT and HDMI. Enabling | |
8033 | * the clock needlessly does no real harm, except use up a | |
8034 | * bit of power potentially. | |
8035 | * | |
8036 | * We'll limit this to IVB with 3 pipes, since it has only two | |
8037 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
8038 | * driving PCH ports at the same time. On SNB we could do this, | |
8039 | * and potentially avoid enabling the second DPLL, but it's not | |
8040 | * clear if it''s a win or loss power wise. No point in doing | |
8041 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
8042 | */ | |
8043 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
8044 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
8045 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8046 | ||
a07d6787 | 8047 | /* compute bitmask from p1 value */ |
190f68c5 | 8048 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8049 | /* also FPA1 */ |
190f68c5 | 8050 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8051 | |
190f68c5 | 8052 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8053 | case 5: |
8054 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8055 | break; | |
8056 | case 7: | |
8057 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8058 | break; | |
8059 | case 10: | |
8060 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8061 | break; | |
8062 | case 14: | |
8063 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8064 | break; | |
79e53945 JB |
8065 | } |
8066 | ||
3d6e9ee0 VS |
8067 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8068 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8069 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8070 | else |
8071 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8072 | ||
b75ca6f6 ACO |
8073 | dpll |= DPLL_VCO_ENABLE; |
8074 | ||
8075 | crtc_state->dpll_hw_state.dpll = dpll; | |
8076 | crtc_state->dpll_hw_state.fp0 = fp; | |
8077 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8078 | } |
8079 | ||
190f68c5 ACO |
8080 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8081 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8082 | { |
997c030c | 8083 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8084 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8085 | const struct intel_limit *limit; |
997c030c | 8086 | int refclk = 120000; |
de13a2e3 | 8087 | |
dd3cd74a ACO |
8088 | memset(&crtc_state->dpll_hw_state, 0, |
8089 | sizeof(crtc_state->dpll_hw_state)); | |
8090 | ||
ded220e2 ACO |
8091 | crtc->lowfreq_avail = false; |
8092 | ||
8093 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8094 | if (!crtc_state->has_pch_encoder) | |
8095 | return 0; | |
79e53945 | 8096 | |
2d84d2b3 | 8097 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8098 | if (intel_panel_use_ssc(dev_priv)) { |
8099 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8100 | dev_priv->vbt.lvds_ssc_freq); | |
8101 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8102 | } | |
8103 | ||
8104 | if (intel_is_dual_link_lvds(dev)) { | |
8105 | if (refclk == 100000) | |
8106 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8107 | else | |
8108 | limit = &intel_limits_ironlake_dual_lvds; | |
8109 | } else { | |
8110 | if (refclk == 100000) | |
8111 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8112 | else | |
8113 | limit = &intel_limits_ironlake_single_lvds; | |
8114 | } | |
8115 | } else { | |
8116 | limit = &intel_limits_ironlake_dac; | |
8117 | } | |
8118 | ||
364ee29d | 8119 | if (!crtc_state->clock_set && |
997c030c ACO |
8120 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8121 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8122 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8123 | return -EINVAL; | |
f47709a9 | 8124 | } |
79e53945 | 8125 | |
cbaa3315 | 8126 | ironlake_compute_dpll(crtc, crtc_state, NULL); |
66e985c0 | 8127 | |
efd38b68 | 8128 | if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) { |
ded220e2 ACO |
8129 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
8130 | pipe_name(crtc->pipe)); | |
8131 | return -EINVAL; | |
3fb37703 | 8132 | } |
79e53945 | 8133 | |
c8f7a0db | 8134 | return 0; |
79e53945 JB |
8135 | } |
8136 | ||
eb14cb74 VS |
8137 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8138 | struct intel_link_m_n *m_n) | |
8139 | { | |
8140 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8141 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
8142 | enum pipe pipe = crtc->pipe; |
8143 | ||
8144 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8145 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8146 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8147 | & ~TU_SIZE_MASK; | |
8148 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8149 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8150 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8151 | } | |
8152 | ||
8153 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8154 | enum transcoder transcoder, | |
b95af8be VK |
8155 | struct intel_link_m_n *m_n, |
8156 | struct intel_link_m_n *m2_n2) | |
72419203 | 8157 | { |
6315b5d3 | 8158 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 8159 | enum pipe pipe = crtc->pipe; |
72419203 | 8160 | |
6315b5d3 | 8161 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
8162 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
8163 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8164 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8165 | & ~TU_SIZE_MASK; | |
8166 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8167 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8168 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8169 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8170 | * gen < 8) and if DRRS is supported (to make sure the | |
8171 | * registers are not unnecessarily read). | |
8172 | */ | |
6315b5d3 | 8173 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 8174 | crtc->config->has_drrs) { |
b95af8be VK |
8175 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8176 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8177 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8178 | & ~TU_SIZE_MASK; | |
8179 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8180 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8181 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8182 | } | |
eb14cb74 VS |
8183 | } else { |
8184 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8185 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8186 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8187 | & ~TU_SIZE_MASK; | |
8188 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8189 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8190 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8191 | } | |
8192 | } | |
8193 | ||
8194 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8195 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8196 | { |
681a8504 | 8197 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8198 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8199 | else | |
8200 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8201 | &pipe_config->dp_m_n, |
8202 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8203 | } |
72419203 | 8204 | |
eb14cb74 | 8205 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8206 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8207 | { |
8208 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8209 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8210 | } |
8211 | ||
bd2e244f | 8212 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8213 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8214 | { |
8215 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8216 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
8217 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8218 | uint32_t ps_ctrl = 0; | |
8219 | int id = -1; | |
8220 | int i; | |
bd2e244f | 8221 | |
a1b2278e CK |
8222 | /* find scaler attached to this pipe */ |
8223 | for (i = 0; i < crtc->num_scalers; i++) { | |
8224 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8225 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8226 | id = i; | |
8227 | pipe_config->pch_pfit.enabled = true; | |
8228 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8229 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8230 | break; | |
8231 | } | |
8232 | } | |
bd2e244f | 8233 | |
a1b2278e CK |
8234 | scaler_state->scaler_id = id; |
8235 | if (id >= 0) { | |
8236 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8237 | } else { | |
8238 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8239 | } |
8240 | } | |
8241 | ||
5724dbd1 DL |
8242 | static void |
8243 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8244 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8245 | { |
8246 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8247 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 8248 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8249 | int pipe = crtc->pipe; |
8250 | int fourcc, pixel_format; | |
6761dd31 | 8251 | unsigned int aligned_height; |
bc8d7dff | 8252 | struct drm_framebuffer *fb; |
1b842c89 | 8253 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8254 | |
d9806c9f | 8255 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8256 | if (!intel_fb) { |
bc8d7dff DL |
8257 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8258 | return; | |
8259 | } | |
8260 | ||
1b842c89 DL |
8261 | fb = &intel_fb->base; |
8262 | ||
d2e9f5fc VS |
8263 | fb->dev = dev; |
8264 | ||
bc8d7dff | 8265 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8266 | if (!(val & PLANE_CTL_ENABLE)) |
8267 | goto error; | |
8268 | ||
bc8d7dff DL |
8269 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8270 | fourcc = skl_format_to_fourcc(pixel_format, | |
8271 | val & PLANE_CTL_ORDER_RGBX, | |
8272 | val & PLANE_CTL_ALPHA_MASK); | |
2f3f4763 | 8273 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 8274 | |
40f46283 DL |
8275 | tiling = val & PLANE_CTL_TILED_MASK; |
8276 | switch (tiling) { | |
8277 | case PLANE_CTL_TILED_LINEAR: | |
2f075565 | 8278 | fb->modifier = DRM_FORMAT_MOD_LINEAR; |
40f46283 DL |
8279 | break; |
8280 | case PLANE_CTL_TILED_X: | |
8281 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 8282 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
8283 | break; |
8284 | case PLANE_CTL_TILED_Y: | |
bae781b2 | 8285 | fb->modifier = I915_FORMAT_MOD_Y_TILED; |
40f46283 DL |
8286 | break; |
8287 | case PLANE_CTL_TILED_YF: | |
bae781b2 | 8288 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; |
40f46283 DL |
8289 | break; |
8290 | default: | |
8291 | MISSING_CASE(tiling); | |
8292 | goto error; | |
8293 | } | |
8294 | ||
bc8d7dff DL |
8295 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8296 | plane_config->base = base; | |
8297 | ||
8298 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8299 | ||
8300 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8301 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8302 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8303 | ||
8304 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
d88c4afd | 8305 | stride_mult = intel_fb_stride_alignment(fb, 0); |
bc8d7dff DL |
8306 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8307 | ||
d88c4afd | 8308 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
bc8d7dff | 8309 | |
f37b5c2b | 8310 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8311 | |
8312 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8313 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8314 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
bc8d7dff DL |
8315 | plane_config->size); |
8316 | ||
2d14030b | 8317 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8318 | return; |
8319 | ||
8320 | error: | |
d1a3a036 | 8321 | kfree(intel_fb); |
bc8d7dff DL |
8322 | } |
8323 | ||
2fa2fe9a | 8324 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8325 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8326 | { |
8327 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8328 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8329 | uint32_t tmp; |
8330 | ||
8331 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8332 | ||
8333 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8334 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8335 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8336 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8337 | |
8338 | /* We currently do not free assignements of panel fitters on | |
8339 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8340 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 8341 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
8342 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
8343 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8344 | } | |
2fa2fe9a | 8345 | } |
79e53945 JB |
8346 | } |
8347 | ||
5724dbd1 DL |
8348 | static void |
8349 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8350 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8351 | { |
8352 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8353 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 8354 | u32 val, base, offset; |
aeee5a49 | 8355 | int pipe = crtc->pipe; |
4c6baa59 | 8356 | int fourcc, pixel_format; |
6761dd31 | 8357 | unsigned int aligned_height; |
b113d5ee | 8358 | struct drm_framebuffer *fb; |
1b842c89 | 8359 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8360 | |
42a7b088 DL |
8361 | val = I915_READ(DSPCNTR(pipe)); |
8362 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8363 | return; | |
8364 | ||
d9806c9f | 8365 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8366 | if (!intel_fb) { |
4c6baa59 JB |
8367 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8368 | return; | |
8369 | } | |
8370 | ||
1b842c89 DL |
8371 | fb = &intel_fb->base; |
8372 | ||
d2e9f5fc VS |
8373 | fb->dev = dev; |
8374 | ||
6315b5d3 | 8375 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8376 | if (val & DISPPLANE_TILED) { |
49af449b | 8377 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8378 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8379 | } |
8380 | } | |
4c6baa59 JB |
8381 | |
8382 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8383 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 8384 | fb->format = drm_format_info(fourcc); |
4c6baa59 | 8385 | |
aeee5a49 | 8386 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 8387 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 8388 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8389 | } else { |
49af449b | 8390 | if (plane_config->tiling) |
aeee5a49 | 8391 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8392 | else |
aeee5a49 | 8393 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8394 | } |
8395 | plane_config->base = base; | |
8396 | ||
8397 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8398 | fb->width = ((val >> 16) & 0xfff) + 1; |
8399 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8400 | |
8401 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8402 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8403 | |
d88c4afd | 8404 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
4c6baa59 | 8405 | |
f37b5c2b | 8406 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8407 | |
2844a921 DL |
8408 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8409 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8410 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 8411 | plane_config->size); |
b113d5ee | 8412 | |
2d14030b | 8413 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8414 | } |
8415 | ||
0e8ffe1b | 8416 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8417 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8418 | { |
8419 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8420 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8421 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8422 | uint32_t tmp; |
1729050e | 8423 | bool ret; |
0e8ffe1b | 8424 | |
1729050e ID |
8425 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8426 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
8427 | return false; |
8428 | ||
e143a21c | 8429 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8430 | pipe_config->shared_dpll = NULL; |
eccb140b | 8431 | |
1729050e | 8432 | ret = false; |
0e8ffe1b DV |
8433 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8434 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8435 | goto out; |
0e8ffe1b | 8436 | |
42571aef VS |
8437 | switch (tmp & PIPECONF_BPC_MASK) { |
8438 | case PIPECONF_6BPC: | |
8439 | pipe_config->pipe_bpp = 18; | |
8440 | break; | |
8441 | case PIPECONF_8BPC: | |
8442 | pipe_config->pipe_bpp = 24; | |
8443 | break; | |
8444 | case PIPECONF_10BPC: | |
8445 | pipe_config->pipe_bpp = 30; | |
8446 | break; | |
8447 | case PIPECONF_12BPC: | |
8448 | pipe_config->pipe_bpp = 36; | |
8449 | break; | |
8450 | default: | |
8451 | break; | |
8452 | } | |
8453 | ||
b5a9fa09 DV |
8454 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8455 | pipe_config->limited_color_range = true; | |
8456 | ||
ab9412ba | 8457 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 8458 | struct intel_shared_dpll *pll; |
8106ddbd | 8459 | enum intel_dpll_id pll_id; |
66e985c0 | 8460 | |
88adfff1 DV |
8461 | pipe_config->has_pch_encoder = true; |
8462 | ||
627eb5a3 DV |
8463 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8464 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8465 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8466 | |
8467 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8468 | |
2d1fe073 | 8469 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
8470 | /* |
8471 | * The pipe->pch transcoder and pch transcoder->pll | |
8472 | * mapping is fixed. | |
8473 | */ | |
8106ddbd | 8474 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
8475 | } else { |
8476 | tmp = I915_READ(PCH_DPLL_SEL); | |
8477 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 8478 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 8479 | else |
8106ddbd | 8480 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 8481 | } |
66e985c0 | 8482 | |
8106ddbd ACO |
8483 | pipe_config->shared_dpll = |
8484 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
8485 | pll = pipe_config->shared_dpll; | |
66e985c0 | 8486 | |
2edd6443 ACO |
8487 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8488 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8489 | |
8490 | tmp = pipe_config->dpll_hw_state.dpll; | |
8491 | pipe_config->pixel_multiplier = | |
8492 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8493 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8494 | |
8495 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8496 | } else { |
8497 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8498 | } |
8499 | ||
1bd1bd80 | 8500 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8501 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8502 | |
2fa2fe9a DV |
8503 | ironlake_get_pfit_config(crtc, pipe_config); |
8504 | ||
1729050e ID |
8505 | ret = true; |
8506 | ||
8507 | out: | |
8508 | intel_display_power_put(dev_priv, power_domain); | |
8509 | ||
8510 | return ret; | |
0e8ffe1b DV |
8511 | } |
8512 | ||
be256dc7 PZ |
8513 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8514 | { | |
91c8a326 | 8515 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 8516 | struct intel_crtc *crtc; |
be256dc7 | 8517 | |
d3fcc808 | 8518 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8519 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8520 | pipe_name(crtc->pipe)); |
8521 | ||
e2c719b7 RC |
8522 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8523 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
8524 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
8525 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 8526 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 8527 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 8528 | "CPU PWM1 enabled\n"); |
772c2a51 | 8529 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 8530 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8531 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8532 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8533 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8534 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8535 | "Utility pin enabled\n"); |
e2c719b7 | 8536 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8537 | |
9926ada1 PZ |
8538 | /* |
8539 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8540 | * interrupts remain enabled. We used to check for that, but since it's | |
8541 | * gen-specific and since we only disable LCPLL after we fully disable | |
8542 | * the interrupts, the check below should be enough. | |
8543 | */ | |
e2c719b7 | 8544 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8545 | } |
8546 | ||
9ccd5aeb PZ |
8547 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8548 | { | |
772c2a51 | 8549 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
8550 | return I915_READ(D_COMP_HSW); |
8551 | else | |
8552 | return I915_READ(D_COMP_BDW); | |
8553 | } | |
8554 | ||
3c4c9b81 PZ |
8555 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8556 | { | |
772c2a51 | 8557 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
8558 | mutex_lock(&dev_priv->rps.hw_lock); |
8559 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8560 | val)) | |
79cf219a | 8561 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8562 | mutex_unlock(&dev_priv->rps.hw_lock); |
8563 | } else { | |
9ccd5aeb PZ |
8564 | I915_WRITE(D_COMP_BDW, val); |
8565 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8566 | } |
be256dc7 PZ |
8567 | } |
8568 | ||
8569 | /* | |
8570 | * This function implements pieces of two sequences from BSpec: | |
8571 | * - Sequence for display software to disable LCPLL | |
8572 | * - Sequence for display software to allow package C8+ | |
8573 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8574 | * register. Callers should take care of disabling all the display engine | |
8575 | * functions, doing the mode unset, fixing interrupts, etc. | |
8576 | */ | |
6ff58d53 PZ |
8577 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8578 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8579 | { |
8580 | uint32_t val; | |
8581 | ||
8582 | assert_can_disable_lcpll(dev_priv); | |
8583 | ||
8584 | val = I915_READ(LCPLL_CTL); | |
8585 | ||
8586 | if (switch_to_fclk) { | |
8587 | val |= LCPLL_CD_SOURCE_FCLK; | |
8588 | I915_WRITE(LCPLL_CTL, val); | |
8589 | ||
f53dd63f ID |
8590 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
8591 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
8592 | DRM_ERROR("Switching to FCLK failed\n"); |
8593 | ||
8594 | val = I915_READ(LCPLL_CTL); | |
8595 | } | |
8596 | ||
8597 | val |= LCPLL_PLL_DISABLE; | |
8598 | I915_WRITE(LCPLL_CTL, val); | |
8599 | POSTING_READ(LCPLL_CTL); | |
8600 | ||
24d8441d | 8601 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
8602 | DRM_ERROR("LCPLL still locked\n"); |
8603 | ||
9ccd5aeb | 8604 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8605 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8606 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8607 | ndelay(100); |
8608 | ||
9ccd5aeb PZ |
8609 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8610 | 1)) | |
be256dc7 PZ |
8611 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8612 | ||
8613 | if (allow_power_down) { | |
8614 | val = I915_READ(LCPLL_CTL); | |
8615 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8616 | I915_WRITE(LCPLL_CTL, val); | |
8617 | POSTING_READ(LCPLL_CTL); | |
8618 | } | |
8619 | } | |
8620 | ||
8621 | /* | |
8622 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8623 | * source. | |
8624 | */ | |
6ff58d53 | 8625 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8626 | { |
8627 | uint32_t val; | |
8628 | ||
8629 | val = I915_READ(LCPLL_CTL); | |
8630 | ||
8631 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8632 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8633 | return; | |
8634 | ||
a8a8bd54 PZ |
8635 | /* |
8636 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8637 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8638 | */ |
59bad947 | 8639 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8640 | |
be256dc7 PZ |
8641 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8642 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8643 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8644 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8645 | } |
8646 | ||
9ccd5aeb | 8647 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8648 | val |= D_COMP_COMP_FORCE; |
8649 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8650 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8651 | |
8652 | val = I915_READ(LCPLL_CTL); | |
8653 | val &= ~LCPLL_PLL_DISABLE; | |
8654 | I915_WRITE(LCPLL_CTL, val); | |
8655 | ||
93220c08 CW |
8656 | if (intel_wait_for_register(dev_priv, |
8657 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
8658 | 5)) | |
be256dc7 PZ |
8659 | DRM_ERROR("LCPLL not locked yet\n"); |
8660 | ||
8661 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8662 | val = I915_READ(LCPLL_CTL); | |
8663 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8664 | I915_WRITE(LCPLL_CTL, val); | |
8665 | ||
f53dd63f ID |
8666 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
8667 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
8668 | DRM_ERROR("Switching back to LCPLL failed\n"); |
8669 | } | |
215733fa | 8670 | |
59bad947 | 8671 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 8672 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
8673 | } |
8674 | ||
765dab67 PZ |
8675 | /* |
8676 | * Package states C8 and deeper are really deep PC states that can only be | |
8677 | * reached when all the devices on the system allow it, so even if the graphics | |
8678 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8679 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8680 | * | |
8681 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8682 | * well is disabled and most interrupts are disabled, and these are also | |
8683 | * requirements for runtime PM. When these conditions are met, we manually do | |
8684 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8685 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8686 | * hang the machine. | |
8687 | * | |
8688 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8689 | * the state of some registers, so when we come back from PC8+ we need to | |
8690 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8691 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8692 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8693 | * because of the runtime PM support). | |
8694 | * | |
8695 | * For more, read "Display Sequences for Package C8" on the hardware | |
8696 | * documentation. | |
8697 | */ | |
a14cb6fc | 8698 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8699 | { |
c67a470b PZ |
8700 | uint32_t val; |
8701 | ||
c67a470b PZ |
8702 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8703 | ||
4f8036a2 | 8704 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8705 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8706 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8707 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8708 | } | |
8709 | ||
c39055b0 | 8710 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
8711 | hsw_disable_lcpll(dev_priv, true, true); |
8712 | } | |
8713 | ||
a14cb6fc | 8714 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8715 | { |
c67a470b PZ |
8716 | uint32_t val; |
8717 | ||
c67a470b PZ |
8718 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8719 | ||
8720 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 8721 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 8722 | |
4f8036a2 | 8723 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8724 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8725 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8726 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8727 | } | |
c67a470b PZ |
8728 | } |
8729 | ||
190f68c5 ACO |
8730 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8731 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8732 | { |
d7edc4e5 | 8733 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
44a126ba PZ |
8734 | struct intel_encoder *encoder = |
8735 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
8736 | ||
8737 | if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) { | |
8738 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8739 | pipe_name(crtc->pipe)); | |
af3997b5 | 8740 | return -EINVAL; |
44a126ba | 8741 | } |
af3997b5 | 8742 | } |
716c2e55 | 8743 | |
c7653199 | 8744 | crtc->lowfreq_avail = false; |
644cef34 | 8745 | |
c8f7a0db | 8746 | return 0; |
79e53945 JB |
8747 | } |
8748 | ||
8b0f7e06 KM |
8749 | static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8750 | enum port port, | |
8751 | struct intel_crtc_state *pipe_config) | |
8752 | { | |
8753 | enum intel_dpll_id id; | |
8754 | u32 temp; | |
8755 | ||
8756 | temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); | |
8757 | id = temp >> (port * 2); | |
8758 | ||
8759 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) | |
8760 | return; | |
8761 | ||
8762 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
8763 | } | |
8764 | ||
3760b59c S |
8765 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
8766 | enum port port, | |
8767 | struct intel_crtc_state *pipe_config) | |
8768 | { | |
8106ddbd ACO |
8769 | enum intel_dpll_id id; |
8770 | ||
3760b59c S |
8771 | switch (port) { |
8772 | case PORT_A: | |
08250c4b | 8773 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
8774 | break; |
8775 | case PORT_B: | |
08250c4b | 8776 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
8777 | break; |
8778 | case PORT_C: | |
08250c4b | 8779 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
8780 | break; |
8781 | default: | |
8782 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 8783 | return; |
3760b59c | 8784 | } |
8106ddbd ACO |
8785 | |
8786 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
8787 | } |
8788 | ||
96b7dfb7 S |
8789 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8790 | enum port port, | |
5cec258b | 8791 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8792 | { |
8106ddbd | 8793 | enum intel_dpll_id id; |
a3c988ea | 8794 | u32 temp; |
96b7dfb7 S |
8795 | |
8796 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 8797 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 8798 | |
c856052a | 8799 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 8800 | return; |
8106ddbd ACO |
8801 | |
8802 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
8803 | } |
8804 | ||
7d2c8175 DL |
8805 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8806 | enum port port, | |
5cec258b | 8807 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 8808 | { |
8106ddbd | 8809 | enum intel_dpll_id id; |
c856052a | 8810 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 8811 | |
c856052a | 8812 | switch (ddi_pll_sel) { |
7d2c8175 | 8813 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 8814 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
8815 | break; |
8816 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 8817 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 8818 | break; |
00490c22 | 8819 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 8820 | id = DPLL_ID_SPLL; |
79bd23da | 8821 | break; |
9d16da65 ACO |
8822 | case PORT_CLK_SEL_LCPLL_810: |
8823 | id = DPLL_ID_LCPLL_810; | |
8824 | break; | |
8825 | case PORT_CLK_SEL_LCPLL_1350: | |
8826 | id = DPLL_ID_LCPLL_1350; | |
8827 | break; | |
8828 | case PORT_CLK_SEL_LCPLL_2700: | |
8829 | id = DPLL_ID_LCPLL_2700; | |
8830 | break; | |
8106ddbd | 8831 | default: |
c856052a | 8832 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
8833 | /* fall through */ |
8834 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 8835 | return; |
7d2c8175 | 8836 | } |
8106ddbd ACO |
8837 | |
8838 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
8839 | } |
8840 | ||
cf30429e JN |
8841 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
8842 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8843 | u64 *power_domain_mask) |
cf30429e JN |
8844 | { |
8845 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8846 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
8847 | enum intel_display_power_domain power_domain; |
8848 | u32 tmp; | |
8849 | ||
d9a7bc67 ID |
8850 | /* |
8851 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
8852 | * transcoder handled below. | |
8853 | */ | |
cf30429e JN |
8854 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8855 | ||
8856 | /* | |
8857 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
8858 | * consistency and less surprising code; it's in always on power). | |
8859 | */ | |
8860 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
8861 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8862 | enum pipe trans_edp_pipe; | |
8863 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8864 | default: | |
8865 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8866 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8867 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8868 | trans_edp_pipe = PIPE_A; | |
8869 | break; | |
8870 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8871 | trans_edp_pipe = PIPE_B; | |
8872 | break; | |
8873 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8874 | trans_edp_pipe = PIPE_C; | |
8875 | break; | |
8876 | } | |
8877 | ||
8878 | if (trans_edp_pipe == crtc->pipe) | |
8879 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8880 | } | |
8881 | ||
8882 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
8883 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
8884 | return false; | |
d8fc70b7 | 8885 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e JN |
8886 | |
8887 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
8888 | ||
8889 | return tmp & PIPECONF_ENABLE; | |
8890 | } | |
8891 | ||
4d1de975 JN |
8892 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
8893 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8894 | u64 *power_domain_mask) |
4d1de975 JN |
8895 | { |
8896 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8897 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
8898 | enum intel_display_power_domain power_domain; |
8899 | enum port port; | |
8900 | enum transcoder cpu_transcoder; | |
8901 | u32 tmp; | |
8902 | ||
4d1de975 JN |
8903 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
8904 | if (port == PORT_A) | |
8905 | cpu_transcoder = TRANSCODER_DSI_A; | |
8906 | else | |
8907 | cpu_transcoder = TRANSCODER_DSI_C; | |
8908 | ||
8909 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
8910 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
8911 | continue; | |
d8fc70b7 | 8912 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 8913 | |
db18b6a6 ID |
8914 | /* |
8915 | * The PLL needs to be enabled with a valid divider | |
8916 | * configuration, otherwise accessing DSI registers will hang | |
8917 | * the machine. See BSpec North Display Engine | |
8918 | * registers/MIPI[BXT]. We can break out here early, since we | |
8919 | * need the same DSI PLL to be enabled for both DSI ports. | |
8920 | */ | |
8921 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
8922 | break; | |
8923 | ||
4d1de975 JN |
8924 | /* XXX: this works for video mode only */ |
8925 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
8926 | if (!(tmp & DPI_ENABLE)) | |
8927 | continue; | |
8928 | ||
8929 | tmp = I915_READ(MIPI_CTRL(port)); | |
8930 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
8931 | continue; | |
8932 | ||
8933 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
8934 | break; |
8935 | } | |
8936 | ||
d7edc4e5 | 8937 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
8938 | } |
8939 | ||
26804afd | 8940 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 8941 | struct intel_crtc_state *pipe_config) |
26804afd | 8942 | { |
6315b5d3 | 8943 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 8944 | struct intel_shared_dpll *pll; |
26804afd DV |
8945 | enum port port; |
8946 | uint32_t tmp; | |
8947 | ||
8948 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
8949 | ||
8950 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
8951 | ||
8b0f7e06 KM |
8952 | if (IS_CANNONLAKE(dev_priv)) |
8953 | cannonlake_get_ddi_pll(dev_priv, port, pipe_config); | |
8954 | else if (IS_GEN9_BC(dev_priv)) | |
96b7dfb7 | 8955 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 8956 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 8957 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
8958 | else |
8959 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 8960 | |
8106ddbd ACO |
8961 | pll = pipe_config->shared_dpll; |
8962 | if (pll) { | |
2edd6443 ACO |
8963 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8964 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
8965 | } |
8966 | ||
26804afd DV |
8967 | /* |
8968 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
8969 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
8970 | * the PCH transcoder is on. | |
8971 | */ | |
6315b5d3 | 8972 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 8973 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
8974 | pipe_config->has_pch_encoder = true; |
8975 | ||
8976 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
8977 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8978 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
8979 | ||
8980 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
8981 | } | |
8982 | } | |
8983 | ||
0e8ffe1b | 8984 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8985 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 8986 | { |
6315b5d3 | 8987 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 8988 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 8989 | u64 power_domain_mask; |
cf30429e | 8990 | bool active; |
0e8ffe1b | 8991 | |
e79dfb51 | 8992 | intel_crtc_init_scalers(crtc, pipe_config); |
5fb9dadf | 8993 | |
1729050e ID |
8994 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8995 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 8996 | return false; |
d8fc70b7 | 8997 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 8998 | |
8106ddbd | 8999 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9000 | |
cf30429e | 9001 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9002 | |
cc3f90f0 | 9003 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
9004 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
9005 | WARN_ON(active); | |
9006 | active = true; | |
4d1de975 JN |
9007 | } |
9008 | ||
cf30429e | 9009 | if (!active) |
1729050e | 9010 | goto out; |
0e8ffe1b | 9011 | |
d7edc4e5 | 9012 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
9013 | haswell_get_ddi_port_state(crtc, pipe_config); |
9014 | intel_get_pipe_timings(crtc, pipe_config); | |
9015 | } | |
627eb5a3 | 9016 | |
bc58be60 | 9017 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9018 | |
05dc698c LL |
9019 | pipe_config->gamma_mode = |
9020 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9021 | ||
1729050e ID |
9022 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9023 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
d8fc70b7 | 9024 | power_domain_mask |= BIT_ULL(power_domain); |
6315b5d3 | 9025 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 9026 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9027 | else |
1c132b44 | 9028 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9029 | } |
88adfff1 | 9030 | |
772c2a51 | 9031 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
9032 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
9033 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9034 | |
4d1de975 JN |
9035 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9036 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9037 | pipe_config->pixel_multiplier = |
9038 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9039 | } else { | |
9040 | pipe_config->pixel_multiplier = 1; | |
9041 | } | |
6c49f241 | 9042 | |
1729050e ID |
9043 | out: |
9044 | for_each_power_domain(power_domain, power_domain_mask) | |
9045 | intel_display_power_put(dev_priv, power_domain); | |
9046 | ||
cf30429e | 9047 | return active; |
0e8ffe1b DV |
9048 | } |
9049 | ||
cd5dcbf1 | 9050 | static u32 intel_cursor_base(const struct intel_plane_state *plane_state) |
1cecc830 VS |
9051 | { |
9052 | struct drm_i915_private *dev_priv = | |
9053 | to_i915(plane_state->base.plane->dev); | |
9054 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
9055 | const struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
9056 | u32 base; | |
9057 | ||
9058 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) | |
9059 | base = obj->phys_handle->busaddr; | |
9060 | else | |
9061 | base = intel_plane_ggtt_offset(plane_state); | |
9062 | ||
1e7b4fd8 VS |
9063 | base += plane_state->main.offset; |
9064 | ||
1cecc830 VS |
9065 | /* ILK+ do this automagically */ |
9066 | if (HAS_GMCH_DISPLAY(dev_priv) && | |
a82256bc | 9067 | plane_state->base.rotation & DRM_MODE_ROTATE_180) |
1cecc830 VS |
9068 | base += (plane_state->base.crtc_h * |
9069 | plane_state->base.crtc_w - 1) * fb->format->cpp[0]; | |
9070 | ||
9071 | return base; | |
9072 | } | |
9073 | ||
ed270223 VS |
9074 | static u32 intel_cursor_position(const struct intel_plane_state *plane_state) |
9075 | { | |
9076 | int x = plane_state->base.crtc_x; | |
9077 | int y = plane_state->base.crtc_y; | |
9078 | u32 pos = 0; | |
9079 | ||
9080 | if (x < 0) { | |
9081 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9082 | x = -x; | |
9083 | } | |
9084 | pos |= x << CURSOR_X_SHIFT; | |
9085 | ||
9086 | if (y < 0) { | |
9087 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9088 | y = -y; | |
9089 | } | |
9090 | pos |= y << CURSOR_Y_SHIFT; | |
9091 | ||
9092 | return pos; | |
9093 | } | |
9094 | ||
3637ecf0 VS |
9095 | static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) |
9096 | { | |
9097 | const struct drm_mode_config *config = | |
9098 | &plane_state->base.plane->dev->mode_config; | |
9099 | int width = plane_state->base.crtc_w; | |
9100 | int height = plane_state->base.crtc_h; | |
9101 | ||
9102 | return width > 0 && width <= config->cursor_width && | |
9103 | height > 0 && height <= config->cursor_height; | |
9104 | } | |
9105 | ||
659056f2 VS |
9106 | static int intel_check_cursor(struct intel_crtc_state *crtc_state, |
9107 | struct intel_plane_state *plane_state) | |
9108 | { | |
9109 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
1e7b4fd8 VS |
9110 | int src_x, src_y; |
9111 | u32 offset; | |
659056f2 VS |
9112 | int ret; |
9113 | ||
9114 | ret = drm_plane_helper_check_state(&plane_state->base, | |
9115 | &plane_state->clip, | |
9116 | DRM_PLANE_HELPER_NO_SCALING, | |
9117 | DRM_PLANE_HELPER_NO_SCALING, | |
9118 | true, true); | |
9119 | if (ret) | |
9120 | return ret; | |
9121 | ||
9122 | if (!fb) | |
9123 | return 0; | |
9124 | ||
9125 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { | |
9126 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); | |
9127 | return -EINVAL; | |
9128 | } | |
9129 | ||
1e7b4fd8 VS |
9130 | src_x = plane_state->base.src_x >> 16; |
9131 | src_y = plane_state->base.src_y >> 16; | |
9132 | ||
9133 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); | |
9134 | offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0); | |
9135 | ||
9136 | if (src_x != 0 || src_y != 0) { | |
9137 | DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n"); | |
9138 | return -EINVAL; | |
9139 | } | |
9140 | ||
9141 | plane_state->main.offset = offset; | |
9142 | ||
659056f2 VS |
9143 | return 0; |
9144 | } | |
9145 | ||
292889e1 VS |
9146 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9147 | const struct intel_plane_state *plane_state) | |
9148 | { | |
1e1bb871 | 9149 | const struct drm_framebuffer *fb = plane_state->base.fb; |
292889e1 | 9150 | |
292889e1 VS |
9151 | return CURSOR_ENABLE | |
9152 | CURSOR_GAMMA_ENABLE | | |
9153 | CURSOR_FORMAT_ARGB | | |
1e1bb871 | 9154 | CURSOR_STRIDE(fb->pitches[0]); |
292889e1 VS |
9155 | } |
9156 | ||
659056f2 VS |
9157 | static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) |
9158 | { | |
659056f2 | 9159 | int width = plane_state->base.crtc_w; |
659056f2 VS |
9160 | |
9161 | /* | |
9162 | * 845g/865g are only limited by the width of their cursors, | |
9163 | * the height is arbitrary up to the precision of the register. | |
9164 | */ | |
3637ecf0 | 9165 | return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); |
659056f2 VS |
9166 | } |
9167 | ||
9168 | static int i845_check_cursor(struct intel_plane *plane, | |
9169 | struct intel_crtc_state *crtc_state, | |
9170 | struct intel_plane_state *plane_state) | |
9171 | { | |
9172 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 VS |
9173 | int ret; |
9174 | ||
9175 | ret = intel_check_cursor(crtc_state, plane_state); | |
9176 | if (ret) | |
9177 | return ret; | |
9178 | ||
9179 | /* if we want to turn off the cursor ignore width and height */ | |
1e1bb871 | 9180 | if (!fb) |
659056f2 VS |
9181 | return 0; |
9182 | ||
9183 | /* Check for which cursor types we support */ | |
9184 | if (!i845_cursor_size_ok(plane_state)) { | |
9185 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9186 | plane_state->base.crtc_w, | |
9187 | plane_state->base.crtc_h); | |
9188 | return -EINVAL; | |
9189 | } | |
9190 | ||
1e1bb871 | 9191 | switch (fb->pitches[0]) { |
292889e1 VS |
9192 | case 256: |
9193 | case 512: | |
9194 | case 1024: | |
9195 | case 2048: | |
9196 | break; | |
1e1bb871 VS |
9197 | default: |
9198 | DRM_DEBUG_KMS("Invalid cursor stride (%u)\n", | |
9199 | fb->pitches[0]); | |
9200 | return -EINVAL; | |
292889e1 VS |
9201 | } |
9202 | ||
659056f2 VS |
9203 | plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); |
9204 | ||
9205 | return 0; | |
292889e1 VS |
9206 | } |
9207 | ||
b2d03b0d VS |
9208 | static void i845_update_cursor(struct intel_plane *plane, |
9209 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9210 | const struct intel_plane_state *plane_state) |
560b85bb | 9211 | { |
cd5dcbf1 | 9212 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
b2d03b0d VS |
9213 | u32 cntl = 0, base = 0, pos = 0, size = 0; |
9214 | unsigned long irqflags; | |
560b85bb | 9215 | |
936e71e3 | 9216 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
9217 | unsigned int width = plane_state->base.crtc_w; |
9218 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 | 9219 | |
a0864d59 | 9220 | cntl = plane_state->ctl; |
dc41c154 | 9221 | size = (height << 12) | width; |
560b85bb | 9222 | |
b2d03b0d VS |
9223 | base = intel_cursor_base(plane_state); |
9224 | pos = intel_cursor_position(plane_state); | |
4b0e333e | 9225 | } |
560b85bb | 9226 | |
b2d03b0d | 9227 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
4726e0b0 | 9228 | |
e11ffddb VS |
9229 | /* On these chipsets we can only modify the base/size/stride |
9230 | * whilst the cursor is disabled. | |
9231 | */ | |
9232 | if (plane->cursor.base != base || | |
9233 | plane->cursor.size != size || | |
9234 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9235 | I915_WRITE_FW(CURCNTR(PIPE_A), 0); |
dd584fc0 | 9236 | I915_WRITE_FW(CURBASE(PIPE_A), base); |
dd584fc0 | 9237 | I915_WRITE_FW(CURSIZE, size); |
b2d03b0d | 9238 | I915_WRITE_FW(CURPOS(PIPE_A), pos); |
dd584fc0 | 9239 | I915_WRITE_FW(CURCNTR(PIPE_A), cntl); |
75343a44 | 9240 | |
e11ffddb VS |
9241 | plane->cursor.base = base; |
9242 | plane->cursor.size = size; | |
9243 | plane->cursor.cntl = cntl; | |
9244 | } else { | |
9245 | I915_WRITE_FW(CURPOS(PIPE_A), pos); | |
560b85bb | 9246 | } |
e11ffddb | 9247 | |
75343a44 | 9248 | POSTING_READ_FW(CURCNTR(PIPE_A)); |
b2d03b0d VS |
9249 | |
9250 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
9251 | } | |
9252 | ||
9253 | static void i845_disable_cursor(struct intel_plane *plane, | |
9254 | struct intel_crtc *crtc) | |
9255 | { | |
9256 | i845_update_cursor(plane, NULL, NULL); | |
560b85bb CW |
9257 | } |
9258 | ||
292889e1 VS |
9259 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9260 | const struct intel_plane_state *plane_state) | |
9261 | { | |
9262 | struct drm_i915_private *dev_priv = | |
9263 | to_i915(plane_state->base.plane->dev); | |
9264 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
292889e1 VS |
9265 | u32 cntl; |
9266 | ||
9267 | cntl = MCURSOR_GAMMA_ENABLE; | |
9268 | ||
9269 | if (HAS_DDI(dev_priv)) | |
9270 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
9271 | ||
d509e28b | 9272 | cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); |
292889e1 VS |
9273 | |
9274 | switch (plane_state->base.crtc_w) { | |
9275 | case 64: | |
9276 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9277 | break; | |
9278 | case 128: | |
9279 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9280 | break; | |
9281 | case 256: | |
9282 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9283 | break; | |
9284 | default: | |
9285 | MISSING_CASE(plane_state->base.crtc_w); | |
9286 | return 0; | |
9287 | } | |
9288 | ||
c2c446ad | 9289 | if (plane_state->base.rotation & DRM_MODE_ROTATE_180) |
292889e1 VS |
9290 | cntl |= CURSOR_ROTATE_180; |
9291 | ||
9292 | return cntl; | |
9293 | } | |
9294 | ||
659056f2 | 9295 | static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) |
65a21cd6 | 9296 | { |
024faac7 VS |
9297 | struct drm_i915_private *dev_priv = |
9298 | to_i915(plane_state->base.plane->dev); | |
659056f2 VS |
9299 | int width = plane_state->base.crtc_w; |
9300 | int height = plane_state->base.crtc_h; | |
4b0e333e | 9301 | |
3637ecf0 | 9302 | if (!intel_cursor_size_ok(plane_state)) |
659056f2 | 9303 | return false; |
4398ad45 | 9304 | |
024faac7 VS |
9305 | /* Cursor width is limited to a few power-of-two sizes */ |
9306 | switch (width) { | |
659056f2 VS |
9307 | case 256: |
9308 | case 128: | |
659056f2 VS |
9309 | case 64: |
9310 | break; | |
9311 | default: | |
9312 | return false; | |
65a21cd6 | 9313 | } |
4b0e333e | 9314 | |
024faac7 VS |
9315 | /* |
9316 | * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor | |
9317 | * height from 8 lines up to the cursor width, when the | |
9318 | * cursor is not rotated. Everything else requires square | |
9319 | * cursors. | |
9320 | */ | |
9321 | if (HAS_CUR_FBC(dev_priv) && | |
a82256bc | 9322 | plane_state->base.rotation & DRM_MODE_ROTATE_0) { |
024faac7 VS |
9323 | if (height < 8 || height > width) |
9324 | return false; | |
9325 | } else { | |
9326 | if (height != width) | |
9327 | return false; | |
9328 | } | |
99d1f387 | 9329 | |
659056f2 | 9330 | return true; |
65a21cd6 JB |
9331 | } |
9332 | ||
659056f2 VS |
9333 | static int i9xx_check_cursor(struct intel_plane *plane, |
9334 | struct intel_crtc_state *crtc_state, | |
9335 | struct intel_plane_state *plane_state) | |
cda4b7d3 | 9336 | { |
659056f2 VS |
9337 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9338 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 | 9339 | enum pipe pipe = plane->pipe; |
659056f2 | 9340 | int ret; |
cda4b7d3 | 9341 | |
659056f2 VS |
9342 | ret = intel_check_cursor(crtc_state, plane_state); |
9343 | if (ret) | |
9344 | return ret; | |
cda4b7d3 | 9345 | |
659056f2 | 9346 | /* if we want to turn off the cursor ignore width and height */ |
1e1bb871 | 9347 | if (!fb) |
659056f2 | 9348 | return 0; |
55a08b3f | 9349 | |
659056f2 VS |
9350 | /* Check for which cursor types we support */ |
9351 | if (!i9xx_cursor_size_ok(plane_state)) { | |
9352 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9353 | plane_state->base.crtc_w, | |
9354 | plane_state->base.crtc_h); | |
9355 | return -EINVAL; | |
cda4b7d3 | 9356 | } |
cda4b7d3 | 9357 | |
1e1bb871 VS |
9358 | if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) { |
9359 | DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n", | |
9360 | fb->pitches[0], plane_state->base.crtc_w); | |
9361 | return -EINVAL; | |
659056f2 | 9362 | } |
dd584fc0 | 9363 | |
659056f2 VS |
9364 | /* |
9365 | * There's something wrong with the cursor on CHV pipe C. | |
9366 | * If it straddles the left edge of the screen then | |
9367 | * moving it away from the edge or disabling it often | |
9368 | * results in a pipe underrun, and often that can lead to | |
9369 | * dead pipe (constant underrun reported, and it scans | |
9370 | * out just a solid color). To recover from that, the | |
9371 | * display power well must be turned off and on again. | |
9372 | * Refuse the put the cursor into that compromised position. | |
9373 | */ | |
9374 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && | |
9375 | plane_state->base.visible && plane_state->base.crtc_x < 0) { | |
9376 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
9377 | return -EINVAL; | |
9378 | } | |
5efb3e28 | 9379 | |
659056f2 | 9380 | plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); |
dd584fc0 | 9381 | |
659056f2 | 9382 | return 0; |
cda4b7d3 CW |
9383 | } |
9384 | ||
b2d03b0d VS |
9385 | static void i9xx_update_cursor(struct intel_plane *plane, |
9386 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9387 | const struct intel_plane_state *plane_state) |
dc41c154 | 9388 | { |
cd5dcbf1 VS |
9389 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9390 | enum pipe pipe = plane->pipe; | |
024faac7 | 9391 | u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; |
b2d03b0d | 9392 | unsigned long irqflags; |
dc41c154 | 9393 | |
b2d03b0d | 9394 | if (plane_state && plane_state->base.visible) { |
a0864d59 | 9395 | cntl = plane_state->ctl; |
dc41c154 | 9396 | |
024faac7 VS |
9397 | if (plane_state->base.crtc_h != plane_state->base.crtc_w) |
9398 | fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1); | |
dc41c154 | 9399 | |
b2d03b0d VS |
9400 | base = intel_cursor_base(plane_state); |
9401 | pos = intel_cursor_position(plane_state); | |
9402 | } | |
9403 | ||
9404 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
9405 | ||
e11ffddb VS |
9406 | /* |
9407 | * On some platforms writing CURCNTR first will also | |
9408 | * cause CURPOS to be armed by the CURBASE write. | |
9409 | * Without the CURCNTR write the CURPOS write would | |
8753d2bc VS |
9410 | * arm itself. Thus we always start the full update |
9411 | * with a CURCNTR write. | |
9412 | * | |
9413 | * On other platforms CURPOS always requires the | |
9414 | * CURBASE write to arm the update. Additonally | |
9415 | * a write to any of the cursor register will cancel | |
9416 | * an already armed cursor update. Thus leaving out | |
9417 | * the CURBASE write after CURPOS could lead to a | |
9418 | * cursor that doesn't appear to move, or even change | |
9419 | * shape. Thus we always write CURBASE. | |
e11ffddb VS |
9420 | * |
9421 | * CURCNTR and CUR_FBC_CTL are always | |
9422 | * armed by the CURBASE write only. | |
9423 | */ | |
9424 | if (plane->cursor.base != base || | |
9425 | plane->cursor.size != fbc_ctl || | |
9426 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9427 | I915_WRITE_FW(CURCNTR(pipe), cntl); |
e11ffddb VS |
9428 | if (HAS_CUR_FBC(dev_priv)) |
9429 | I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); | |
b2d03b0d | 9430 | I915_WRITE_FW(CURPOS(pipe), pos); |
75343a44 VS |
9431 | I915_WRITE_FW(CURBASE(pipe), base); |
9432 | ||
e11ffddb VS |
9433 | plane->cursor.base = base; |
9434 | plane->cursor.size = fbc_ctl; | |
9435 | plane->cursor.cntl = cntl; | |
dc41c154 | 9436 | } else { |
e11ffddb | 9437 | I915_WRITE_FW(CURPOS(pipe), pos); |
8753d2bc | 9438 | I915_WRITE_FW(CURBASE(pipe), base); |
dc41c154 VS |
9439 | } |
9440 | ||
dd584fc0 | 9441 | POSTING_READ_FW(CURBASE(pipe)); |
99d1f387 | 9442 | |
b2d03b0d | 9443 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
65a21cd6 JB |
9444 | } |
9445 | ||
b2d03b0d VS |
9446 | static void i9xx_disable_cursor(struct intel_plane *plane, |
9447 | struct intel_crtc *crtc) | |
cda4b7d3 | 9448 | { |
b2d03b0d | 9449 | i9xx_update_cursor(plane, NULL, NULL); |
dc41c154 VS |
9450 | } |
9451 | ||
dc41c154 | 9452 | |
79e53945 JB |
9453 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9454 | static struct drm_display_mode load_detect_mode = { | |
9455 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9456 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9457 | }; | |
9458 | ||
a8bb6818 | 9459 | struct drm_framebuffer * |
24dbf51a CW |
9460 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
9461 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
9462 | { |
9463 | struct intel_framebuffer *intel_fb; | |
9464 | int ret; | |
9465 | ||
9466 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 9467 | if (!intel_fb) |
d2dff872 | 9468 | return ERR_PTR(-ENOMEM); |
d2dff872 | 9469 | |
24dbf51a | 9470 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
9471 | if (ret) |
9472 | goto err; | |
d2dff872 CW |
9473 | |
9474 | return &intel_fb->base; | |
dcb1394e | 9475 | |
dd4916c5 | 9476 | err: |
dd4916c5 | 9477 | kfree(intel_fb); |
dd4916c5 | 9478 | return ERR_PTR(ret); |
d2dff872 CW |
9479 | } |
9480 | ||
9481 | static u32 | |
9482 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9483 | { | |
9484 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9485 | return ALIGN(pitch, 64); | |
9486 | } | |
9487 | ||
9488 | static u32 | |
9489 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9490 | { | |
9491 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9492 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9493 | } |
9494 | ||
9495 | static struct drm_framebuffer * | |
9496 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9497 | struct drm_display_mode *mode, | |
9498 | int depth, int bpp) | |
9499 | { | |
dcb1394e | 9500 | struct drm_framebuffer *fb; |
d2dff872 | 9501 | struct drm_i915_gem_object *obj; |
0fed39bd | 9502 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 9503 | |
12d79d78 | 9504 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 9505 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
9506 | if (IS_ERR(obj)) |
9507 | return ERR_CAST(obj); | |
d2dff872 CW |
9508 | |
9509 | mode_cmd.width = mode->hdisplay; | |
9510 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9511 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9512 | bpp); | |
5ca0c34a | 9513 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 9514 | |
24dbf51a | 9515 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 9516 | if (IS_ERR(fb)) |
f0cd5182 | 9517 | i915_gem_object_put(obj); |
dcb1394e LW |
9518 | |
9519 | return fb; | |
d2dff872 CW |
9520 | } |
9521 | ||
9522 | static struct drm_framebuffer * | |
9523 | mode_fits_in_fbdev(struct drm_device *dev, | |
9524 | struct drm_display_mode *mode) | |
9525 | { | |
0695726e | 9526 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 9527 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
9528 | struct drm_i915_gem_object *obj; |
9529 | struct drm_framebuffer *fb; | |
9530 | ||
4c0e5528 | 9531 | if (!dev_priv->fbdev) |
d2dff872 CW |
9532 | return NULL; |
9533 | ||
4c0e5528 | 9534 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9535 | return NULL; |
9536 | ||
4c0e5528 DV |
9537 | obj = dev_priv->fbdev->fb->obj; |
9538 | BUG_ON(!obj); | |
9539 | ||
8bcd4553 | 9540 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 | 9541 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
272725c7 | 9542 | fb->format->cpp[0] * 8)) |
d2dff872 CW |
9543 | return NULL; |
9544 | ||
01f2c773 | 9545 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9546 | return NULL; |
9547 | ||
edde3617 | 9548 | drm_framebuffer_reference(fb); |
d2dff872 | 9549 | return fb; |
4520f53a DV |
9550 | #else |
9551 | return NULL; | |
9552 | #endif | |
d2dff872 CW |
9553 | } |
9554 | ||
d3a40d1b ACO |
9555 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9556 | struct drm_crtc *crtc, | |
9557 | struct drm_display_mode *mode, | |
9558 | struct drm_framebuffer *fb, | |
9559 | int x, int y) | |
9560 | { | |
9561 | struct drm_plane_state *plane_state; | |
9562 | int hdisplay, vdisplay; | |
9563 | int ret; | |
9564 | ||
9565 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9566 | if (IS_ERR(plane_state)) | |
9567 | return PTR_ERR(plane_state); | |
9568 | ||
9569 | if (mode) | |
196cd5d3 | 9570 | drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay); |
d3a40d1b ACO |
9571 | else |
9572 | hdisplay = vdisplay = 0; | |
9573 | ||
9574 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9575 | if (ret) | |
9576 | return ret; | |
9577 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9578 | plane_state->crtc_x = 0; | |
9579 | plane_state->crtc_y = 0; | |
9580 | plane_state->crtc_w = hdisplay; | |
9581 | plane_state->crtc_h = vdisplay; | |
9582 | plane_state->src_x = x << 16; | |
9583 | plane_state->src_y = y << 16; | |
9584 | plane_state->src_w = hdisplay << 16; | |
9585 | plane_state->src_h = vdisplay << 16; | |
9586 | ||
9587 | return 0; | |
9588 | } | |
9589 | ||
6c5ed5ae ML |
9590 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
9591 | struct drm_display_mode *mode, | |
9592 | struct intel_load_detect_pipe *old, | |
9593 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9594 | { |
9595 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9596 | struct intel_encoder *intel_encoder = |
9597 | intel_attached_encoder(connector); | |
79e53945 | 9598 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9599 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9600 | struct drm_crtc *crtc = NULL; |
9601 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 9602 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 9603 | struct drm_framebuffer *fb; |
51fd371b | 9604 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 9605 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 9606 | struct drm_connector_state *connector_state; |
4be07317 | 9607 | struct intel_crtc_state *crtc_state; |
51fd371b | 9608 | int ret, i = -1; |
79e53945 | 9609 | |
d2dff872 | 9610 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9611 | connector->base.id, connector->name, |
8e329a03 | 9612 | encoder->base.id, encoder->name); |
d2dff872 | 9613 | |
edde3617 ML |
9614 | old->restore_state = NULL; |
9615 | ||
6c5ed5ae | 9616 | WARN_ON(!drm_modeset_is_locked(&config->connection_mutex)); |
6e9f798d | 9617 | |
79e53945 JB |
9618 | /* |
9619 | * Algorithm gets a little messy: | |
7a5e4805 | 9620 | * |
79e53945 JB |
9621 | * - if the connector already has an assigned crtc, use it (but make |
9622 | * sure it's on first) | |
7a5e4805 | 9623 | * |
79e53945 JB |
9624 | * - try to find the first unused crtc that can drive this connector, |
9625 | * and use that if we find one | |
79e53945 JB |
9626 | */ |
9627 | ||
9628 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
9629 | if (connector->state->crtc) { |
9630 | crtc = connector->state->crtc; | |
8261b191 | 9631 | |
51fd371b | 9632 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 9633 | if (ret) |
ad3c558f | 9634 | goto fail; |
8261b191 CW |
9635 | |
9636 | /* Make sure the crtc and connector are running */ | |
edde3617 | 9637 | goto found; |
79e53945 JB |
9638 | } |
9639 | ||
9640 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9641 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9642 | i++; |
9643 | if (!(encoder->possible_crtcs & (1 << i))) | |
9644 | continue; | |
edde3617 ML |
9645 | |
9646 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
9647 | if (ret) | |
9648 | goto fail; | |
9649 | ||
9650 | if (possible_crtc->state->enable) { | |
9651 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 9652 | continue; |
edde3617 | 9653 | } |
a459249c VS |
9654 | |
9655 | crtc = possible_crtc; | |
9656 | break; | |
79e53945 JB |
9657 | } |
9658 | ||
9659 | /* | |
9660 | * If we didn't find an unused CRTC, don't use any. | |
9661 | */ | |
9662 | if (!crtc) { | |
7173188d | 9663 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
f4bf77b4 | 9664 | ret = -ENODEV; |
ad3c558f | 9665 | goto fail; |
79e53945 JB |
9666 | } |
9667 | ||
edde3617 ML |
9668 | found: |
9669 | intel_crtc = to_intel_crtc(crtc); | |
9670 | ||
4d02e2de DV |
9671 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
9672 | if (ret) | |
ad3c558f | 9673 | goto fail; |
79e53945 | 9674 | |
83a57153 | 9675 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
9676 | restore_state = drm_atomic_state_alloc(dev); |
9677 | if (!state || !restore_state) { | |
9678 | ret = -ENOMEM; | |
9679 | goto fail; | |
9680 | } | |
83a57153 ACO |
9681 | |
9682 | state->acquire_ctx = ctx; | |
edde3617 | 9683 | restore_state->acquire_ctx = ctx; |
83a57153 | 9684 | |
944b0c76 ACO |
9685 | connector_state = drm_atomic_get_connector_state(state, connector); |
9686 | if (IS_ERR(connector_state)) { | |
9687 | ret = PTR_ERR(connector_state); | |
9688 | goto fail; | |
9689 | } | |
9690 | ||
edde3617 ML |
9691 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
9692 | if (ret) | |
9693 | goto fail; | |
944b0c76 | 9694 | |
4be07317 ACO |
9695 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9696 | if (IS_ERR(crtc_state)) { | |
9697 | ret = PTR_ERR(crtc_state); | |
9698 | goto fail; | |
9699 | } | |
9700 | ||
49d6fa21 | 9701 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 9702 | |
6492711d CW |
9703 | if (!mode) |
9704 | mode = &load_detect_mode; | |
79e53945 | 9705 | |
d2dff872 CW |
9706 | /* We need a framebuffer large enough to accommodate all accesses |
9707 | * that the plane may generate whilst we perform load detection. | |
9708 | * We can not rely on the fbcon either being present (we get called | |
9709 | * during its initialisation to detect all boot displays, or it may | |
9710 | * not even exist) or that it is large enough to satisfy the | |
9711 | * requested mode. | |
9712 | */ | |
94352cf9 DV |
9713 | fb = mode_fits_in_fbdev(dev, mode); |
9714 | if (fb == NULL) { | |
d2dff872 | 9715 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 9716 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
9717 | } else |
9718 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9719 | if (IS_ERR(fb)) { |
d2dff872 | 9720 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
f4bf77b4 | 9721 | ret = PTR_ERR(fb); |
412b61d8 | 9722 | goto fail; |
79e53945 | 9723 | } |
79e53945 | 9724 | |
d3a40d1b ACO |
9725 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
9726 | if (ret) | |
9727 | goto fail; | |
9728 | ||
edde3617 ML |
9729 | drm_framebuffer_unreference(fb); |
9730 | ||
9731 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
9732 | if (ret) | |
9733 | goto fail; | |
9734 | ||
9735 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
9736 | if (!ret) | |
9737 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
9738 | if (!ret) | |
9739 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
9740 | if (ret) { | |
9741 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
9742 | goto fail; | |
9743 | } | |
8c7b5ccb | 9744 | |
3ba86073 ML |
9745 | ret = drm_atomic_commit(state); |
9746 | if (ret) { | |
6492711d | 9747 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 9748 | goto fail; |
79e53945 | 9749 | } |
edde3617 ML |
9750 | |
9751 | old->restore_state = restore_state; | |
7abbd11f | 9752 | drm_atomic_state_put(state); |
7173188d | 9753 | |
79e53945 | 9754 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 9755 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 9756 | return true; |
412b61d8 | 9757 | |
ad3c558f | 9758 | fail: |
7fb71c8f CW |
9759 | if (state) { |
9760 | drm_atomic_state_put(state); | |
9761 | state = NULL; | |
9762 | } | |
9763 | if (restore_state) { | |
9764 | drm_atomic_state_put(restore_state); | |
9765 | restore_state = NULL; | |
9766 | } | |
83a57153 | 9767 | |
6c5ed5ae ML |
9768 | if (ret == -EDEADLK) |
9769 | return ret; | |
51fd371b | 9770 | |
412b61d8 | 9771 | return false; |
79e53945 JB |
9772 | } |
9773 | ||
d2434ab7 | 9774 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9775 | struct intel_load_detect_pipe *old, |
9776 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9777 | { |
d2434ab7 DV |
9778 | struct intel_encoder *intel_encoder = |
9779 | intel_attached_encoder(connector); | |
4ef69c7a | 9780 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 9781 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 9782 | int ret; |
79e53945 | 9783 | |
d2dff872 | 9784 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9785 | connector->base.id, connector->name, |
8e329a03 | 9786 | encoder->base.id, encoder->name); |
d2dff872 | 9787 | |
edde3617 | 9788 | if (!state) |
0622a53c | 9789 | return; |
79e53945 | 9790 | |
581e49fe | 9791 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
0853695c | 9792 | if (ret) |
edde3617 | 9793 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 9794 | drm_atomic_state_put(state); |
79e53945 JB |
9795 | } |
9796 | ||
da4a1efa | 9797 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9798 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 9799 | { |
fac5e23e | 9800 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
9801 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
9802 | ||
9803 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9804 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 9805 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 9806 | return 120000; |
5db94019 | 9807 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
9808 | return 96000; |
9809 | else | |
9810 | return 48000; | |
9811 | } | |
9812 | ||
79e53945 | 9813 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9814 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9815 | struct intel_crtc_state *pipe_config) |
79e53945 | 9816 | { |
f1f644dc | 9817 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9818 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 9819 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9820 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 9821 | u32 fp; |
9e2c8475 | 9822 | struct dpll clock; |
dccbea3b | 9823 | int port_clock; |
da4a1efa | 9824 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9825 | |
9826 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9827 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9828 | else |
293623f7 | 9829 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9830 | |
9831 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 9832 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
9833 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
9834 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9835 | } else { |
9836 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9837 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9838 | } | |
9839 | ||
5db94019 | 9840 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 9841 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
9842 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
9843 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9844 | else |
9845 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9846 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9847 | ||
9848 | switch (dpll & DPLL_MODE_MASK) { | |
9849 | case DPLLB_MODE_DAC_SERIAL: | |
9850 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9851 | 5 : 10; | |
9852 | break; | |
9853 | case DPLLB_MODE_LVDS: | |
9854 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9855 | 7 : 14; | |
9856 | break; | |
9857 | default: | |
28c97730 | 9858 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9859 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9860 | return; |
79e53945 JB |
9861 | } |
9862 | ||
9b1e14f4 | 9863 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 9864 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 9865 | else |
dccbea3b | 9866 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 9867 | } else { |
50a0bc90 | 9868 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9869 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9870 | |
9871 | if (is_lvds) { | |
9872 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9873 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9874 | |
9875 | if (lvds & LVDS_CLKB_POWER_UP) | |
9876 | clock.p2 = 7; | |
9877 | else | |
9878 | clock.p2 = 14; | |
79e53945 JB |
9879 | } else { |
9880 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9881 | clock.p1 = 2; | |
9882 | else { | |
9883 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9884 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9885 | } | |
9886 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9887 | clock.p2 = 4; | |
9888 | else | |
9889 | clock.p2 = 2; | |
79e53945 | 9890 | } |
da4a1efa | 9891 | |
dccbea3b | 9892 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
9893 | } |
9894 | ||
18442d08 VS |
9895 | /* |
9896 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9897 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9898 | * encoder's get_config() function. |
9899 | */ | |
dccbea3b | 9900 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
9901 | } |
9902 | ||
6878da05 VS |
9903 | int intel_dotclock_calculate(int link_freq, |
9904 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9905 | { |
f1f644dc JB |
9906 | /* |
9907 | * The calculation for the data clock is: | |
1041a02f | 9908 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9909 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9910 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9911 | * |
9912 | * and the link clock is simpler: | |
1041a02f | 9913 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9914 | */ |
9915 | ||
6878da05 VS |
9916 | if (!m_n->link_n) |
9917 | return 0; | |
f1f644dc | 9918 | |
6878da05 VS |
9919 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9920 | } | |
f1f644dc | 9921 | |
18442d08 | 9922 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9923 | struct intel_crtc_state *pipe_config) |
6878da05 | 9924 | { |
e3b247da | 9925 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 9926 | |
18442d08 VS |
9927 | /* read out port_clock from the DPLL */ |
9928 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9929 | |
f1f644dc | 9930 | /* |
e3b247da VS |
9931 | * In case there is an active pipe without active ports, |
9932 | * we may need some idea for the dotclock anyway. | |
9933 | * Calculate one based on the FDI configuration. | |
79e53945 | 9934 | */ |
2d112de7 | 9935 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 9936 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 9937 | &pipe_config->fdi_m_n); |
79e53945 JB |
9938 | } |
9939 | ||
9940 | /** Returns the currently programmed mode of the given pipe. */ | |
9941 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9942 | struct drm_crtc *crtc) | |
9943 | { | |
fac5e23e | 9944 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 9945 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9946 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9947 | struct drm_display_mode *mode; |
3f36b937 | 9948 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
9949 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9950 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9951 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9952 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9953 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9954 | |
9955 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9956 | if (!mode) | |
9957 | return NULL; | |
9958 | ||
3f36b937 TU |
9959 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9960 | if (!pipe_config) { | |
9961 | kfree(mode); | |
9962 | return NULL; | |
9963 | } | |
9964 | ||
f1f644dc JB |
9965 | /* |
9966 | * Construct a pipe_config sufficient for getting the clock info | |
9967 | * back out of crtc_clock_get. | |
9968 | * | |
9969 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9970 | * to use a real value here instead. | |
9971 | */ | |
3f36b937 TU |
9972 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
9973 | pipe_config->pixel_multiplier = 1; | |
9974 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
9975 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9976 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
9977 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
9978 | ||
9979 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
9980 | mode->hdisplay = (htot & 0xffff) + 1; |
9981 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9982 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9983 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9984 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9985 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9986 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9987 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9988 | ||
9989 | drm_mode_set_name(mode); | |
79e53945 | 9990 | |
3f36b937 TU |
9991 | kfree(pipe_config); |
9992 | ||
79e53945 JB |
9993 | return mode; |
9994 | } | |
9995 | ||
9996 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
9997 | { | |
9998 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9999 | ||
10000 | drm_crtc_cleanup(crtc); | |
10001 | kfree(intel_crtc); | |
10002 | } | |
10003 | ||
5a21b665 DV |
10004 | /** |
10005 | * intel_wm_need_update - Check whether watermarks need updating | |
10006 | * @plane: drm plane | |
10007 | * @state: new plane state | |
10008 | * | |
10009 | * Check current plane state versus the new one to determine whether | |
10010 | * watermarks need to be recalculated. | |
10011 | * | |
10012 | * Returns true or false. | |
10013 | */ | |
10014 | static bool intel_wm_need_update(struct drm_plane *plane, | |
10015 | struct drm_plane_state *state) | |
10016 | { | |
10017 | struct intel_plane_state *new = to_intel_plane_state(state); | |
10018 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
10019 | ||
10020 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 10021 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
10022 | return true; |
10023 | ||
10024 | if (!cur->base.fb || !new->base.fb) | |
10025 | return false; | |
10026 | ||
bae781b2 | 10027 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 10028 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
10029 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
10030 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
10031 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
10032 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
10033 | return true; |
10034 | ||
10035 | return false; | |
10036 | } | |
10037 | ||
10038 | static bool needs_scaling(struct intel_plane_state *state) | |
10039 | { | |
936e71e3 VS |
10040 | int src_w = drm_rect_width(&state->base.src) >> 16; |
10041 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
10042 | int dst_w = drm_rect_width(&state->base.dst); | |
10043 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
10044 | |
10045 | return (src_w != dst_w || src_h != dst_h); | |
10046 | } | |
d21fbe87 | 10047 | |
da20eabd ML |
10048 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
10049 | struct drm_plane_state *plane_state) | |
10050 | { | |
ab1d3a0e | 10051 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
10052 | struct drm_crtc *crtc = crtc_state->crtc; |
10053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e9728bd8 | 10054 | struct intel_plane *plane = to_intel_plane(plane_state->plane); |
da20eabd | 10055 | struct drm_device *dev = crtc->dev; |
ed4a6a7c | 10056 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd | 10057 | struct intel_plane_state *old_plane_state = |
e9728bd8 | 10058 | to_intel_plane_state(plane->base.state); |
da20eabd ML |
10059 | bool mode_changed = needs_modeset(crtc_state); |
10060 | bool was_crtc_enabled = crtc->state->active; | |
10061 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
10062 | bool turn_off, turn_on, visible, was_visible; |
10063 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 10064 | int ret; |
da20eabd | 10065 | |
e9728bd8 | 10066 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
da20eabd ML |
10067 | ret = skl_update_scaler_plane( |
10068 | to_intel_crtc_state(crtc_state), | |
10069 | to_intel_plane_state(plane_state)); | |
10070 | if (ret) | |
10071 | return ret; | |
10072 | } | |
10073 | ||
936e71e3 | 10074 | was_visible = old_plane_state->base.visible; |
1d4258db | 10075 | visible = plane_state->visible; |
da20eabd ML |
10076 | |
10077 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
10078 | was_visible = false; | |
10079 | ||
35c08f43 ML |
10080 | /* |
10081 | * Visibility is calculated as if the crtc was on, but | |
10082 | * after scaler setup everything depends on it being off | |
10083 | * when the crtc isn't active. | |
f818ffea VS |
10084 | * |
10085 | * FIXME this is wrong for watermarks. Watermarks should also | |
10086 | * be computed as if the pipe would be active. Perhaps move | |
10087 | * per-plane wm computation to the .check_plane() hook, and | |
10088 | * only combine the results from all planes in the current place? | |
35c08f43 | 10089 | */ |
e9728bd8 | 10090 | if (!is_crtc_enabled) { |
1d4258db | 10091 | plane_state->visible = visible = false; |
e9728bd8 VS |
10092 | to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); |
10093 | } | |
da20eabd ML |
10094 | |
10095 | if (!was_visible && !visible) | |
10096 | return 0; | |
10097 | ||
e8861675 ML |
10098 | if (fb != old_plane_state->base.fb) |
10099 | pipe_config->fb_changed = true; | |
10100 | ||
da20eabd ML |
10101 | turn_off = was_visible && (!visible || mode_changed); |
10102 | turn_on = visible && (!was_visible || mode_changed); | |
10103 | ||
72660ce0 | 10104 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
e9728bd8 VS |
10105 | intel_crtc->base.base.id, intel_crtc->base.name, |
10106 | plane->base.base.id, plane->base.name, | |
72660ce0 | 10107 | fb ? fb->base.id : -1); |
da20eabd | 10108 | |
72660ce0 | 10109 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
e9728bd8 | 10110 | plane->base.base.id, plane->base.name, |
72660ce0 | 10111 | was_visible, visible, |
da20eabd ML |
10112 | turn_off, turn_on, mode_changed); |
10113 | ||
caed361d | 10114 | if (turn_on) { |
04548cba | 10115 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10116 | pipe_config->update_wm_pre = true; |
caed361d VS |
10117 | |
10118 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 10119 | if (plane->id != PLANE_CURSOR) |
caed361d VS |
10120 | pipe_config->disable_cxsr = true; |
10121 | } else if (turn_off) { | |
04548cba | 10122 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10123 | pipe_config->update_wm_post = true; |
92826fcd | 10124 | |
852eb00d | 10125 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 10126 | if (plane->id != PLANE_CURSOR) |
ab1d3a0e | 10127 | pipe_config->disable_cxsr = true; |
e9728bd8 | 10128 | } else if (intel_wm_need_update(&plane->base, plane_state)) { |
04548cba | 10129 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
b4ede6df VS |
10130 | /* FIXME bollocks */ |
10131 | pipe_config->update_wm_pre = true; | |
10132 | pipe_config->update_wm_post = true; | |
10133 | } | |
852eb00d | 10134 | } |
da20eabd | 10135 | |
8be6ca85 | 10136 | if (visible || was_visible) |
e9728bd8 | 10137 | pipe_config->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 10138 | |
31ae71fc ML |
10139 | /* |
10140 | * WaCxSRDisabledForSpriteScaling:ivb | |
10141 | * | |
10142 | * cstate->update_wm was already set above, so this flag will | |
10143 | * take effect when we commit and program watermarks. | |
10144 | */ | |
e9728bd8 | 10145 | if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
10146 | needs_scaling(to_intel_plane_state(plane_state)) && |
10147 | !needs_scaling(old_plane_state)) | |
10148 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 10149 | |
da20eabd ML |
10150 | return 0; |
10151 | } | |
10152 | ||
6d3a1ce7 ML |
10153 | static bool encoders_cloneable(const struct intel_encoder *a, |
10154 | const struct intel_encoder *b) | |
10155 | { | |
10156 | /* masks could be asymmetric, so check both ways */ | |
10157 | return a == b || (a->cloneable & (1 << b->type) && | |
10158 | b->cloneable & (1 << a->type)); | |
10159 | } | |
10160 | ||
10161 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
10162 | struct intel_crtc *crtc, | |
10163 | struct intel_encoder *encoder) | |
10164 | { | |
10165 | struct intel_encoder *source_encoder; | |
10166 | struct drm_connector *connector; | |
10167 | struct drm_connector_state *connector_state; | |
10168 | int i; | |
10169 | ||
aa5e9b47 | 10170 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
6d3a1ce7 ML |
10171 | if (connector_state->crtc != &crtc->base) |
10172 | continue; | |
10173 | ||
10174 | source_encoder = | |
10175 | to_intel_encoder(connector_state->best_encoder); | |
10176 | if (!encoders_cloneable(encoder, source_encoder)) | |
10177 | return false; | |
10178 | } | |
10179 | ||
10180 | return true; | |
10181 | } | |
10182 | ||
6d3a1ce7 ML |
10183 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
10184 | struct drm_crtc_state *crtc_state) | |
10185 | { | |
cf5a15be | 10186 | struct drm_device *dev = crtc->dev; |
fac5e23e | 10187 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 10188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
10189 | struct intel_crtc_state *pipe_config = |
10190 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 10191 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 10192 | int ret; |
6d3a1ce7 ML |
10193 | bool mode_changed = needs_modeset(crtc_state); |
10194 | ||
852eb00d | 10195 | if (mode_changed && !crtc_state->active) |
caed361d | 10196 | pipe_config->update_wm_post = true; |
eddfcbcd | 10197 | |
ad421372 ML |
10198 | if (mode_changed && crtc_state->enable && |
10199 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 10200 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
10201 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
10202 | pipe_config); | |
10203 | if (ret) | |
10204 | return ret; | |
10205 | } | |
10206 | ||
82cf435b LL |
10207 | if (crtc_state->color_mgmt_changed) { |
10208 | ret = intel_color_check(crtc, crtc_state); | |
10209 | if (ret) | |
10210 | return ret; | |
e7852a4b LL |
10211 | |
10212 | /* | |
10213 | * Changing color management on Intel hardware is | |
10214 | * handled as part of planes update. | |
10215 | */ | |
10216 | crtc_state->planes_changed = true; | |
82cf435b LL |
10217 | } |
10218 | ||
e435d6e5 | 10219 | ret = 0; |
86c8bbbe | 10220 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 10221 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
10222 | if (ret) { |
10223 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
10224 | return ret; | |
10225 | } | |
10226 | } | |
10227 | ||
10228 | if (dev_priv->display.compute_intermediate_wm && | |
10229 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
10230 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
10231 | return 0; | |
10232 | ||
10233 | /* | |
10234 | * Calculate 'intermediate' watermarks that satisfy both the | |
10235 | * old state and the new state. We can program these | |
10236 | * immediately. | |
10237 | */ | |
6315b5d3 | 10238 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
10239 | intel_crtc, |
10240 | pipe_config); | |
10241 | if (ret) { | |
10242 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 10243 | return ret; |
ed4a6a7c | 10244 | } |
e3d5457c VS |
10245 | } else if (dev_priv->display.compute_intermediate_wm) { |
10246 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
10247 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
10248 | } |
10249 | ||
6315b5d3 | 10250 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
10251 | if (mode_changed) |
10252 | ret = skl_update_scaler_crtc(pipe_config); | |
10253 | ||
73b0ca8e MK |
10254 | if (!ret) |
10255 | ret = skl_check_pipe_max_pixel_rate(intel_crtc, | |
10256 | pipe_config); | |
e435d6e5 | 10257 | if (!ret) |
6ebc6923 | 10258 | ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, |
e435d6e5 ML |
10259 | pipe_config); |
10260 | } | |
10261 | ||
10262 | return ret; | |
6d3a1ce7 ML |
10263 | } |
10264 | ||
65b38e0d | 10265 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
5a21b665 DV |
10266 | .atomic_begin = intel_begin_crtc_commit, |
10267 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 10268 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
10269 | }; |
10270 | ||
d29b2f9d ACO |
10271 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
10272 | { | |
10273 | struct intel_connector *connector; | |
f9e905ca | 10274 | struct drm_connector_list_iter conn_iter; |
d29b2f9d | 10275 | |
f9e905ca DV |
10276 | drm_connector_list_iter_begin(dev, &conn_iter); |
10277 | for_each_intel_connector_iter(connector, &conn_iter) { | |
8863dc7f DV |
10278 | if (connector->base.state->crtc) |
10279 | drm_connector_unreference(&connector->base); | |
10280 | ||
d29b2f9d ACO |
10281 | if (connector->base.encoder) { |
10282 | connector->base.state->best_encoder = | |
10283 | connector->base.encoder; | |
10284 | connector->base.state->crtc = | |
10285 | connector->base.encoder->crtc; | |
8863dc7f DV |
10286 | |
10287 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
10288 | } else { |
10289 | connector->base.state->best_encoder = NULL; | |
10290 | connector->base.state->crtc = NULL; | |
10291 | } | |
10292 | } | |
f9e905ca | 10293 | drm_connector_list_iter_end(&conn_iter); |
d29b2f9d ACO |
10294 | } |
10295 | ||
050f7aeb | 10296 | static void |
eba905b2 | 10297 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10298 | struct intel_crtc_state *pipe_config) |
050f7aeb | 10299 | { |
6a2a5c5d | 10300 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
10301 | int bpp = pipe_config->pipe_bpp; |
10302 | ||
10303 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
10304 | connector->base.base.id, |
10305 | connector->base.name); | |
050f7aeb DV |
10306 | |
10307 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 10308 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 10309 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
10310 | bpp, info->bpc * 3); |
10311 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
10312 | } |
10313 | ||
196f954e | 10314 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 10315 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
10316 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
10317 | bpp); | |
10318 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
10319 | } |
10320 | } | |
10321 | ||
4e53c2e0 | 10322 | static int |
050f7aeb | 10323 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 10324 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10325 | { |
9beb5fea | 10326 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 10327 | struct drm_atomic_state *state; |
da3ced29 ACO |
10328 | struct drm_connector *connector; |
10329 | struct drm_connector_state *connector_state; | |
1486017f | 10330 | int bpp, i; |
4e53c2e0 | 10331 | |
9beb5fea TU |
10332 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
10333 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 10334 | bpp = 10*3; |
9beb5fea | 10335 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
10336 | bpp = 12*3; |
10337 | else | |
10338 | bpp = 8*3; | |
10339 | ||
4e53c2e0 | 10340 | |
4e53c2e0 DV |
10341 | pipe_config->pipe_bpp = bpp; |
10342 | ||
1486017f ACO |
10343 | state = pipe_config->base.state; |
10344 | ||
4e53c2e0 | 10345 | /* Clamp display bpp to EDID value */ |
aa5e9b47 | 10346 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
da3ced29 | 10347 | if (connector_state->crtc != &crtc->base) |
4e53c2e0 DV |
10348 | continue; |
10349 | ||
da3ced29 ACO |
10350 | connected_sink_compute_bpp(to_intel_connector(connector), |
10351 | pipe_config); | |
4e53c2e0 DV |
10352 | } |
10353 | ||
10354 | return bpp; | |
10355 | } | |
10356 | ||
644db711 DV |
10357 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10358 | { | |
10359 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10360 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10361 | mode->crtc_clock, |
644db711 DV |
10362 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10363 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10364 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10365 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10366 | } | |
10367 | ||
f6982332 TU |
10368 | static inline void |
10369 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 10370 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 10371 | { |
a4309657 TU |
10372 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10373 | id, lane_count, | |
f6982332 TU |
10374 | m_n->gmch_m, m_n->gmch_n, |
10375 | m_n->link_m, m_n->link_n, m_n->tu); | |
10376 | } | |
10377 | ||
c0b03411 | 10378 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10379 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10380 | const char *context) |
10381 | { | |
6a60cd87 | 10382 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 10383 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
10384 | struct drm_plane *plane; |
10385 | struct intel_plane *intel_plane; | |
10386 | struct intel_plane_state *state; | |
10387 | struct drm_framebuffer *fb; | |
10388 | ||
66766e4f TU |
10389 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
10390 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 10391 | |
2c89429e TU |
10392 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
10393 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 10394 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
10395 | |
10396 | if (pipe_config->has_pch_encoder) | |
10397 | intel_dump_m_n_config(pipe_config, "fdi", | |
10398 | pipe_config->fdi_lanes, | |
10399 | &pipe_config->fdi_m_n); | |
f6982332 TU |
10400 | |
10401 | if (intel_crtc_has_dp_encoder(pipe_config)) { | |
a4309657 TU |
10402 | intel_dump_m_n_config(pipe_config, "dp m_n", |
10403 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
10404 | if (pipe_config->has_drrs) |
10405 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
10406 | pipe_config->lane_count, | |
10407 | &pipe_config->dp_m2_n2); | |
f6982332 | 10408 | } |
b95af8be | 10409 | |
55072d19 | 10410 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 10411 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 10412 | |
c0b03411 | 10413 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10414 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10415 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10416 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10417 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
a7d1b3f4 | 10418 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", |
2c89429e | 10419 | pipe_config->port_clock, |
a7d1b3f4 VS |
10420 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
10421 | pipe_config->pixel_rate); | |
dd2f616d TU |
10422 | |
10423 | if (INTEL_GEN(dev_priv) >= 9) | |
10424 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
10425 | crtc->num_scalers, | |
10426 | pipe_config->scaler_state.scaler_users, | |
10427 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
10428 | |
10429 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
10430 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
10431 | pipe_config->gmch_pfit.control, | |
10432 | pipe_config->gmch_pfit.pgm_ratios, | |
10433 | pipe_config->gmch_pfit.lvds_border_bits); | |
10434 | else | |
10435 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
10436 | pipe_config->pch_pfit.pos, | |
10437 | pipe_config->pch_pfit.size, | |
08c4d7fc | 10438 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 10439 | |
2c89429e TU |
10440 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
10441 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 10442 | |
f50b79f0 | 10443 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 10444 | |
6a60cd87 CK |
10445 | DRM_DEBUG_KMS("planes on this crtc\n"); |
10446 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 10447 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
10448 | intel_plane = to_intel_plane(plane); |
10449 | if (intel_plane->pipe != crtc->pipe) | |
10450 | continue; | |
10451 | ||
10452 | state = to_intel_plane_state(plane->state); | |
10453 | fb = state->base.fb; | |
10454 | if (!fb) { | |
1d577e02 VS |
10455 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
10456 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
10457 | continue; |
10458 | } | |
10459 | ||
dd2f616d TU |
10460 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
10461 | plane->base.id, plane->name, | |
b3c11ac2 | 10462 | fb->base.id, fb->width, fb->height, |
438b74a5 | 10463 | drm_get_format_name(fb->format->format, &format_name)); |
dd2f616d TU |
10464 | if (INTEL_GEN(dev_priv) >= 9) |
10465 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
10466 | state->scaler_id, | |
10467 | state->base.src.x1 >> 16, | |
10468 | state->base.src.y1 >> 16, | |
10469 | drm_rect_width(&state->base.src) >> 16, | |
10470 | drm_rect_height(&state->base.src) >> 16, | |
10471 | state->base.dst.x1, state->base.dst.y1, | |
10472 | drm_rect_width(&state->base.dst), | |
10473 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 10474 | } |
c0b03411 DV |
10475 | } |
10476 | ||
5448a00d | 10477 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 10478 | { |
5448a00d | 10479 | struct drm_device *dev = state->dev; |
da3ced29 | 10480 | struct drm_connector *connector; |
2fd96b41 | 10481 | struct drm_connector_list_iter conn_iter; |
00f0b378 | 10482 | unsigned int used_ports = 0; |
477321e0 | 10483 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
10484 | |
10485 | /* | |
10486 | * Walk the connector list instead of the encoder | |
10487 | * list to detect the problem on ddi platforms | |
10488 | * where there's just one encoder per digital port. | |
10489 | */ | |
2fd96b41 GP |
10490 | drm_connector_list_iter_begin(dev, &conn_iter); |
10491 | drm_for_each_connector_iter(connector, &conn_iter) { | |
0bff4858 VS |
10492 | struct drm_connector_state *connector_state; |
10493 | struct intel_encoder *encoder; | |
10494 | ||
10495 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
10496 | if (!connector_state) | |
10497 | connector_state = connector->state; | |
10498 | ||
5448a00d | 10499 | if (!connector_state->best_encoder) |
00f0b378 VS |
10500 | continue; |
10501 | ||
5448a00d ACO |
10502 | encoder = to_intel_encoder(connector_state->best_encoder); |
10503 | ||
10504 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
10505 | |
10506 | switch (encoder->type) { | |
10507 | unsigned int port_mask; | |
10508 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 10509 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 10510 | break; |
cca0502b | 10511 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
10512 | case INTEL_OUTPUT_HDMI: |
10513 | case INTEL_OUTPUT_EDP: | |
10514 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10515 | ||
10516 | /* the same port mustn't appear more than once */ | |
10517 | if (used_ports & port_mask) | |
10518 | return false; | |
10519 | ||
10520 | used_ports |= port_mask; | |
477321e0 VS |
10521 | break; |
10522 | case INTEL_OUTPUT_DP_MST: | |
10523 | used_mst_ports |= | |
10524 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
10525 | break; | |
00f0b378 VS |
10526 | default: |
10527 | break; | |
10528 | } | |
10529 | } | |
2fd96b41 | 10530 | drm_connector_list_iter_end(&conn_iter); |
00f0b378 | 10531 | |
477321e0 VS |
10532 | /* can't mix MST and SST/HDMI on the same port */ |
10533 | if (used_ports & used_mst_ports) | |
10534 | return false; | |
10535 | ||
00f0b378 VS |
10536 | return true; |
10537 | } | |
10538 | ||
83a57153 ACO |
10539 | static void |
10540 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
10541 | { | |
ff32c54e VS |
10542 | struct drm_i915_private *dev_priv = |
10543 | to_i915(crtc_state->base.crtc->dev); | |
663a3640 | 10544 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 10545 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 10546 | struct intel_shared_dpll *shared_dpll; |
ff32c54e | 10547 | struct intel_crtc_wm_state wm_state; |
c4e2d043 | 10548 | bool force_thru; |
83a57153 | 10549 | |
7546a384 ACO |
10550 | /* FIXME: before the switch to atomic started, a new pipe_config was |
10551 | * kzalloc'd. Code that depends on any field being zero should be | |
10552 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
10553 | * only fields that are know to not cause problems are preserved. */ | |
10554 | ||
663a3640 | 10555 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
10556 | shared_dpll = crtc_state->shared_dpll; |
10557 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 10558 | force_thru = crtc_state->pch_pfit.force_thru; |
04548cba VS |
10559 | if (IS_G4X(dev_priv) || |
10560 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10561 | wm_state = crtc_state->wm; |
4978cc93 | 10562 | |
d2fa80a5 CW |
10563 | /* Keep base drm_crtc_state intact, only clear our extended struct */ |
10564 | BUILD_BUG_ON(offsetof(struct intel_crtc_state, base)); | |
10565 | memset(&crtc_state->base + 1, 0, | |
10566 | sizeof(*crtc_state) - sizeof(crtc_state->base)); | |
4978cc93 | 10567 | |
663a3640 | 10568 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
10569 | crtc_state->shared_dpll = shared_dpll; |
10570 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 10571 | crtc_state->pch_pfit.force_thru = force_thru; |
04548cba VS |
10572 | if (IS_G4X(dev_priv) || |
10573 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10574 | crtc_state->wm = wm_state; |
83a57153 ACO |
10575 | } |
10576 | ||
548ee15b | 10577 | static int |
b8cecdf5 | 10578 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 10579 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 10580 | { |
b359283a | 10581 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 10582 | struct intel_encoder *encoder; |
da3ced29 | 10583 | struct drm_connector *connector; |
0b901879 | 10584 | struct drm_connector_state *connector_state; |
d328c9d7 | 10585 | int base_bpp, ret = -EINVAL; |
0b901879 | 10586 | int i; |
e29c22c0 | 10587 | bool retry = true; |
ee7b9f93 | 10588 | |
83a57153 | 10589 | clear_intel_crtc_state(pipe_config); |
7758a113 | 10590 | |
e143a21c DV |
10591 | pipe_config->cpu_transcoder = |
10592 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 10593 | |
2960bc9c ID |
10594 | /* |
10595 | * Sanitize sync polarity flags based on requested ones. If neither | |
10596 | * positive or negative polarity is requested, treat this as meaning | |
10597 | * negative polarity. | |
10598 | */ | |
2d112de7 | 10599 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10600 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10601 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10602 | |
2d112de7 | 10603 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10604 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10605 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10606 | |
d328c9d7 DV |
10607 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
10608 | pipe_config); | |
10609 | if (base_bpp < 0) | |
4e53c2e0 DV |
10610 | goto fail; |
10611 | ||
e41a56be VS |
10612 | /* |
10613 | * Determine the real pipe dimensions. Note that stereo modes can | |
10614 | * increase the actual pipe size due to the frame doubling and | |
10615 | * insertion of additional space for blanks between the frame. This | |
10616 | * is stored in the crtc timings. We use the requested mode to do this | |
10617 | * computation to clearly distinguish it from the adjusted mode, which | |
10618 | * can be changed by the connectors in the below retry loop. | |
10619 | */ | |
196cd5d3 | 10620 | drm_mode_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10621 | &pipe_config->pipe_src_w, |
10622 | &pipe_config->pipe_src_h); | |
e41a56be | 10623 | |
aa5e9b47 | 10624 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
253c84c8 VS |
10625 | if (connector_state->crtc != crtc) |
10626 | continue; | |
10627 | ||
10628 | encoder = to_intel_encoder(connector_state->best_encoder); | |
10629 | ||
e25148d0 VS |
10630 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
10631 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
10632 | goto fail; | |
10633 | } | |
10634 | ||
253c84c8 VS |
10635 | /* |
10636 | * Determine output_types before calling the .compute_config() | |
10637 | * hooks so that the hooks can use this information safely. | |
10638 | */ | |
10639 | pipe_config->output_types |= 1 << encoder->type; | |
10640 | } | |
10641 | ||
e29c22c0 | 10642 | encoder_retry: |
ef1b460d | 10643 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10644 | pipe_config->port_clock = 0; |
ef1b460d | 10645 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10646 | |
135c81b8 | 10647 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10648 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10649 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10650 | |
7758a113 DV |
10651 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10652 | * adjust it according to limitations or connector properties, and also | |
10653 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10654 | */ |
aa5e9b47 | 10655 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 10656 | if (connector_state->crtc != crtc) |
7758a113 | 10657 | continue; |
7ae89233 | 10658 | |
0b901879 ACO |
10659 | encoder = to_intel_encoder(connector_state->best_encoder); |
10660 | ||
0a478c27 | 10661 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 10662 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
10663 | goto fail; |
10664 | } | |
ee7b9f93 | 10665 | } |
47f1c6c9 | 10666 | |
ff9a6750 DV |
10667 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10668 | * done afterwards in case the encoder adjusts the mode. */ | |
10669 | if (!pipe_config->port_clock) | |
2d112de7 | 10670 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10671 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10672 | |
a43f6e0f | 10673 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10674 | if (ret < 0) { |
7758a113 DV |
10675 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10676 | goto fail; | |
ee7b9f93 | 10677 | } |
e29c22c0 DV |
10678 | |
10679 | if (ret == RETRY) { | |
10680 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10681 | ret = -EINVAL; | |
10682 | goto fail; | |
10683 | } | |
10684 | ||
10685 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10686 | retry = false; | |
10687 | goto encoder_retry; | |
10688 | } | |
10689 | ||
e8fa4270 | 10690 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
10691 | * only enable it on 6bpc panels and when its not a compliance |
10692 | * test requesting 6bpc video pattern. | |
10693 | */ | |
10694 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
10695 | !pipe_config->dither_force_disable; | |
62f0ace5 | 10696 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 10697 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 10698 | |
7758a113 | 10699 | fail: |
548ee15b | 10700 | return ret; |
ee7b9f93 | 10701 | } |
47f1c6c9 | 10702 | |
ea9d758d | 10703 | static void |
4740b0f2 | 10704 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 10705 | { |
0a9ab303 | 10706 | struct drm_crtc *crtc; |
aa5e9b47 | 10707 | struct drm_crtc_state *new_crtc_state; |
8a75d157 | 10708 | int i; |
ea9d758d | 10709 | |
7668851f | 10710 | /* Double check state. */ |
aa5e9b47 ML |
10711 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
10712 | to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state); | |
fc467a22 | 10713 | |
61067a5e ML |
10714 | /* |
10715 | * Update legacy state to satisfy fbc code. This can | |
10716 | * be removed when fbc uses the atomic state. | |
10717 | */ | |
10718 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
10719 | struct drm_plane_state *plane_state = crtc->primary->state; | |
10720 | ||
10721 | crtc->primary->fb = plane_state->fb; | |
10722 | crtc->x = plane_state->src_x >> 16; | |
10723 | crtc->y = plane_state->src_y >> 16; | |
10724 | } | |
ea9d758d | 10725 | } |
ea9d758d DV |
10726 | } |
10727 | ||
3bd26263 | 10728 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10729 | { |
3bd26263 | 10730 | int diff; |
f1f644dc JB |
10731 | |
10732 | if (clock1 == clock2) | |
10733 | return true; | |
10734 | ||
10735 | if (!clock1 || !clock2) | |
10736 | return false; | |
10737 | ||
10738 | diff = abs(clock1 - clock2); | |
10739 | ||
10740 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10741 | return true; | |
10742 | ||
10743 | return false; | |
10744 | } | |
10745 | ||
cfb23ed6 ML |
10746 | static bool |
10747 | intel_compare_m_n(unsigned int m, unsigned int n, | |
10748 | unsigned int m2, unsigned int n2, | |
10749 | bool exact) | |
10750 | { | |
10751 | if (m == m2 && n == n2) | |
10752 | return true; | |
10753 | ||
10754 | if (exact || !m || !n || !m2 || !n2) | |
10755 | return false; | |
10756 | ||
10757 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
10758 | ||
31d10b57 ML |
10759 | if (n > n2) { |
10760 | while (n > n2) { | |
cfb23ed6 ML |
10761 | m2 <<= 1; |
10762 | n2 <<= 1; | |
10763 | } | |
31d10b57 ML |
10764 | } else if (n < n2) { |
10765 | while (n < n2) { | |
cfb23ed6 ML |
10766 | m <<= 1; |
10767 | n <<= 1; | |
10768 | } | |
10769 | } | |
10770 | ||
31d10b57 ML |
10771 | if (n != n2) |
10772 | return false; | |
10773 | ||
10774 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
10775 | } |
10776 | ||
10777 | static bool | |
10778 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
10779 | struct intel_link_m_n *m2_n2, | |
10780 | bool adjust) | |
10781 | { | |
10782 | if (m_n->tu == m2_n2->tu && | |
10783 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
10784 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
10785 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
10786 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
10787 | if (adjust) | |
10788 | *m2_n2 = *m_n; | |
10789 | ||
10790 | return true; | |
10791 | } | |
10792 | ||
10793 | return false; | |
10794 | } | |
10795 | ||
4e8048f8 TU |
10796 | static void __printf(3, 4) |
10797 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
10798 | { | |
10799 | char *level; | |
10800 | unsigned int category; | |
10801 | struct va_format vaf; | |
10802 | va_list args; | |
10803 | ||
10804 | if (adjust) { | |
10805 | level = KERN_DEBUG; | |
10806 | category = DRM_UT_KMS; | |
10807 | } else { | |
10808 | level = KERN_ERR; | |
10809 | category = DRM_UT_NONE; | |
10810 | } | |
10811 | ||
10812 | va_start(args, format); | |
10813 | vaf.fmt = format; | |
10814 | vaf.va = &args; | |
10815 | ||
10816 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
10817 | ||
10818 | va_end(args); | |
10819 | } | |
10820 | ||
0e8ffe1b | 10821 | static bool |
6315b5d3 | 10822 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 10823 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
10824 | struct intel_crtc_state *pipe_config, |
10825 | bool adjust) | |
0e8ffe1b | 10826 | { |
cfb23ed6 ML |
10827 | bool ret = true; |
10828 | ||
66e985c0 DV |
10829 | #define PIPE_CONF_CHECK_X(name) \ |
10830 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 10831 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
10832 | "(expected 0x%08x, found 0x%08x)\n", \ |
10833 | current_config->name, \ | |
10834 | pipe_config->name); \ | |
cfb23ed6 | 10835 | ret = false; \ |
66e985c0 DV |
10836 | } |
10837 | ||
08a24034 DV |
10838 | #define PIPE_CONF_CHECK_I(name) \ |
10839 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 10840 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
10841 | "(expected %i, found %i)\n", \ |
10842 | current_config->name, \ | |
10843 | pipe_config->name); \ | |
cfb23ed6 ML |
10844 | ret = false; \ |
10845 | } | |
10846 | ||
8106ddbd ACO |
10847 | #define PIPE_CONF_CHECK_P(name) \ |
10848 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 10849 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
10850 | "(expected %p, found %p)\n", \ |
10851 | current_config->name, \ | |
10852 | pipe_config->name); \ | |
10853 | ret = false; \ | |
10854 | } | |
10855 | ||
cfb23ed6 ML |
10856 | #define PIPE_CONF_CHECK_M_N(name) \ |
10857 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
10858 | &pipe_config->name,\ | |
10859 | adjust)) { \ | |
4e8048f8 | 10860 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
10861 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
10862 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
10863 | current_config->name.tu, \ | |
10864 | current_config->name.gmch_m, \ | |
10865 | current_config->name.gmch_n, \ | |
10866 | current_config->name.link_m, \ | |
10867 | current_config->name.link_n, \ | |
10868 | pipe_config->name.tu, \ | |
10869 | pipe_config->name.gmch_m, \ | |
10870 | pipe_config->name.gmch_n, \ | |
10871 | pipe_config->name.link_m, \ | |
10872 | pipe_config->name.link_n); \ | |
10873 | ret = false; \ | |
10874 | } | |
10875 | ||
55c561a7 DV |
10876 | /* This is required for BDW+ where there is only one set of registers for |
10877 | * switching between high and low RR. | |
10878 | * This macro can be used whenever a comparison has to be made between one | |
10879 | * hw state and multiple sw state variables. | |
10880 | */ | |
cfb23ed6 ML |
10881 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
10882 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
10883 | &pipe_config->name, adjust) && \ | |
10884 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
10885 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 10886 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
10887 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
10888 | "or tu %i gmch %i/%i link %i/%i, " \ | |
10889 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
10890 | current_config->name.tu, \ | |
10891 | current_config->name.gmch_m, \ | |
10892 | current_config->name.gmch_n, \ | |
10893 | current_config->name.link_m, \ | |
10894 | current_config->name.link_n, \ | |
10895 | current_config->alt_name.tu, \ | |
10896 | current_config->alt_name.gmch_m, \ | |
10897 | current_config->alt_name.gmch_n, \ | |
10898 | current_config->alt_name.link_m, \ | |
10899 | current_config->alt_name.link_n, \ | |
10900 | pipe_config->name.tu, \ | |
10901 | pipe_config->name.gmch_m, \ | |
10902 | pipe_config->name.gmch_n, \ | |
10903 | pipe_config->name.link_m, \ | |
10904 | pipe_config->name.link_n); \ | |
10905 | ret = false; \ | |
88adfff1 DV |
10906 | } |
10907 | ||
1bd1bd80 DV |
10908 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10909 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
10910 | pipe_config_err(adjust, __stringify(name), \ |
10911 | "(%x) (expected %i, found %i)\n", \ | |
10912 | (mask), \ | |
1bd1bd80 DV |
10913 | current_config->name & (mask), \ |
10914 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 10915 | ret = false; \ |
1bd1bd80 DV |
10916 | } |
10917 | ||
5e550656 VS |
10918 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10919 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 10920 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
10921 | "(expected %i, found %i)\n", \ |
10922 | current_config->name, \ | |
10923 | pipe_config->name); \ | |
cfb23ed6 | 10924 | ret = false; \ |
5e550656 VS |
10925 | } |
10926 | ||
bb760063 DV |
10927 | #define PIPE_CONF_QUIRK(quirk) \ |
10928 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10929 | ||
eccb140b DV |
10930 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10931 | ||
08a24034 DV |
10932 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10933 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 10934 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 10935 | |
90a6b7b0 | 10936 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 10937 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 10938 | |
6315b5d3 | 10939 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
10940 | PIPE_CONF_CHECK_M_N(dp_m_n); |
10941 | ||
cfb23ed6 ML |
10942 | if (current_config->has_drrs) |
10943 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
10944 | } else | |
10945 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 10946 | |
253c84c8 | 10947 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 10948 | |
2d112de7 ACO |
10949 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
10950 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
10951 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
10952 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
10953 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
10954 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 10955 | |
2d112de7 ACO |
10956 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
10957 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
10958 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
10959 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
10960 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
10961 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 10962 | |
c93f54cf | 10963 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10964 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 10965 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 10966 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 10967 | PIPE_CONF_CHECK_I(limited_color_range); |
15953637 SS |
10968 | |
10969 | PIPE_CONF_CHECK_I(hdmi_scrambling); | |
10970 | PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio); | |
e43823ec | 10971 | PIPE_CONF_CHECK_I(has_infoframe); |
60436fd4 | 10972 | PIPE_CONF_CHECK_I(ycbcr420); |
6c49f241 | 10973 | |
9ed109a7 DV |
10974 | PIPE_CONF_CHECK_I(has_audio); |
10975 | ||
2d112de7 | 10976 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
10977 | DRM_MODE_FLAG_INTERLACE); |
10978 | ||
bb760063 | 10979 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 10980 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10981 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 10982 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10983 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 10984 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10985 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 10986 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
10987 | DRM_MODE_FLAG_NVSYNC); |
10988 | } | |
045ac3b5 | 10989 | |
333b8ca8 | 10990 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 10991 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 10992 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 10993 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 10994 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 10995 | |
bfd16b2a ML |
10996 | if (!adjust) { |
10997 | PIPE_CONF_CHECK_I(pipe_src_w); | |
10998 | PIPE_CONF_CHECK_I(pipe_src_h); | |
10999 | ||
11000 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
11001 | if (current_config->pch_pfit.enabled) { | |
11002 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
11003 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
11004 | } | |
2fa2fe9a | 11005 | |
7aefe2b5 | 11006 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 11007 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
7aefe2b5 | 11008 | } |
a1b2278e | 11009 | |
e59150dc | 11010 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 11011 | if (IS_HASWELL(dev_priv)) |
e59150dc | 11012 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 11013 | |
282740f7 VS |
11014 | PIPE_CONF_CHECK_I(double_wide); |
11015 | ||
8106ddbd | 11016 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 11017 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11018 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11019 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11020 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11021 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 11022 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
11023 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11024 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11025 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11026 | |
47eacbab VS |
11027 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
11028 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
11029 | ||
9beb5fea | 11030 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
11031 | PIPE_CONF_CHECK_I(pipe_bpp); |
11032 | ||
2d112de7 | 11033 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11034 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11035 | |
66e985c0 | 11036 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11037 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 11038 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 11039 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11040 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11041 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11042 | |
cfb23ed6 | 11043 | return ret; |
0e8ffe1b DV |
11044 | } |
11045 | ||
e3b247da VS |
11046 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
11047 | const struct intel_crtc_state *pipe_config) | |
11048 | { | |
11049 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 11050 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
11051 | &pipe_config->fdi_m_n); |
11052 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
11053 | ||
11054 | /* | |
11055 | * FDI already provided one idea for the dotclock. | |
11056 | * Yell if the encoder disagrees. | |
11057 | */ | |
11058 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
11059 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
11060 | fdi_dotclock, dotclock); | |
11061 | } | |
11062 | } | |
11063 | ||
c0ead703 ML |
11064 | static void verify_wm_state(struct drm_crtc *crtc, |
11065 | struct drm_crtc_state *new_state) | |
08db6652 | 11066 | { |
6315b5d3 | 11067 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 11068 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 11069 | struct skl_pipe_wm hw_wm, *sw_wm; |
11070 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
11071 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
11072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11073 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 11074 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 11075 | |
6315b5d3 | 11076 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
11077 | return; |
11078 | ||
3de8a14c | 11079 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 11080 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 11081 | |
08db6652 DL |
11082 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
11083 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11084 | ||
e7c84544 | 11085 | /* planes */ |
8b364b41 | 11086 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 11087 | hw_plane_wm = &hw_wm.planes[plane]; |
11088 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 11089 | |
3de8a14c | 11090 | /* Watermarks */ |
11091 | for (level = 0; level <= max_level; level++) { | |
11092 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11093 | &sw_plane_wm->wm[level])) | |
11094 | continue; | |
11095 | ||
11096 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11097 | pipe_name(pipe), plane + 1, level, | |
11098 | sw_plane_wm->wm[level].plane_en, | |
11099 | sw_plane_wm->wm[level].plane_res_b, | |
11100 | sw_plane_wm->wm[level].plane_res_l, | |
11101 | hw_plane_wm->wm[level].plane_en, | |
11102 | hw_plane_wm->wm[level].plane_res_b, | |
11103 | hw_plane_wm->wm[level].plane_res_l); | |
11104 | } | |
08db6652 | 11105 | |
3de8a14c | 11106 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
11107 | &sw_plane_wm->trans_wm)) { | |
11108 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11109 | pipe_name(pipe), plane + 1, | |
11110 | sw_plane_wm->trans_wm.plane_en, | |
11111 | sw_plane_wm->trans_wm.plane_res_b, | |
11112 | sw_plane_wm->trans_wm.plane_res_l, | |
11113 | hw_plane_wm->trans_wm.plane_en, | |
11114 | hw_plane_wm->trans_wm.plane_res_b, | |
11115 | hw_plane_wm->trans_wm.plane_res_l); | |
11116 | } | |
11117 | ||
11118 | /* DDB */ | |
11119 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
11120 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
11121 | ||
11122 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 11123 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 11124 | pipe_name(pipe), plane + 1, |
11125 | sw_ddb_entry->start, sw_ddb_entry->end, | |
11126 | hw_ddb_entry->start, hw_ddb_entry->end); | |
11127 | } | |
e7c84544 | 11128 | } |
08db6652 | 11129 | |
27082493 L |
11130 | /* |
11131 | * cursor | |
11132 | * If the cursor plane isn't active, we may not have updated it's ddb | |
11133 | * allocation. In that case since the ddb allocation will be updated | |
11134 | * once the plane becomes visible, we can skip this check | |
11135 | */ | |
cd5dcbf1 | 11136 | if (1) { |
3de8a14c | 11137 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
11138 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
11139 | ||
11140 | /* Watermarks */ | |
11141 | for (level = 0; level <= max_level; level++) { | |
11142 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11143 | &sw_plane_wm->wm[level])) | |
11144 | continue; | |
11145 | ||
11146 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11147 | pipe_name(pipe), level, | |
11148 | sw_plane_wm->wm[level].plane_en, | |
11149 | sw_plane_wm->wm[level].plane_res_b, | |
11150 | sw_plane_wm->wm[level].plane_res_l, | |
11151 | hw_plane_wm->wm[level].plane_en, | |
11152 | hw_plane_wm->wm[level].plane_res_b, | |
11153 | hw_plane_wm->wm[level].plane_res_l); | |
11154 | } | |
11155 | ||
11156 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
11157 | &sw_plane_wm->trans_wm)) { | |
11158 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11159 | pipe_name(pipe), | |
11160 | sw_plane_wm->trans_wm.plane_en, | |
11161 | sw_plane_wm->trans_wm.plane_res_b, | |
11162 | sw_plane_wm->trans_wm.plane_res_l, | |
11163 | hw_plane_wm->trans_wm.plane_en, | |
11164 | hw_plane_wm->trans_wm.plane_res_b, | |
11165 | hw_plane_wm->trans_wm.plane_res_l); | |
11166 | } | |
11167 | ||
11168 | /* DDB */ | |
11169 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
11170 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 11171 | |
3de8a14c | 11172 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 11173 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 11174 | pipe_name(pipe), |
3de8a14c | 11175 | sw_ddb_entry->start, sw_ddb_entry->end, |
11176 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 11177 | } |
08db6652 DL |
11178 | } |
11179 | } | |
11180 | ||
91d1b4bd | 11181 | static void |
677100ce ML |
11182 | verify_connector_state(struct drm_device *dev, |
11183 | struct drm_atomic_state *state, | |
11184 | struct drm_crtc *crtc) | |
8af6cf88 | 11185 | { |
35dd3c64 | 11186 | struct drm_connector *connector; |
aa5e9b47 | 11187 | struct drm_connector_state *new_conn_state; |
677100ce | 11188 | int i; |
8af6cf88 | 11189 | |
aa5e9b47 | 11190 | for_each_new_connector_in_state(state, connector, new_conn_state, i) { |
35dd3c64 | 11191 | struct drm_encoder *encoder = connector->encoder; |
749d98b8 | 11192 | struct drm_crtc_state *crtc_state = NULL; |
ad3c558f | 11193 | |
aa5e9b47 | 11194 | if (new_conn_state->crtc != crtc) |
e7c84544 ML |
11195 | continue; |
11196 | ||
749d98b8 ML |
11197 | if (crtc) |
11198 | crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); | |
11199 | ||
11200 | intel_connector_verify_state(crtc_state, new_conn_state); | |
8af6cf88 | 11201 | |
aa5e9b47 | 11202 | I915_STATE_WARN(new_conn_state->best_encoder != encoder, |
35dd3c64 | 11203 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 11204 | } |
91d1b4bd DV |
11205 | } |
11206 | ||
11207 | static void | |
86b04268 | 11208 | verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state) |
91d1b4bd DV |
11209 | { |
11210 | struct intel_encoder *encoder; | |
86b04268 DV |
11211 | struct drm_connector *connector; |
11212 | struct drm_connector_state *old_conn_state, *new_conn_state; | |
11213 | int i; | |
8af6cf88 | 11214 | |
b2784e15 | 11215 | for_each_intel_encoder(dev, encoder) { |
86b04268 | 11216 | bool enabled = false, found = false; |
4d20cd86 | 11217 | enum pipe pipe; |
8af6cf88 DV |
11218 | |
11219 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11220 | encoder->base.base.id, | |
8e329a03 | 11221 | encoder->base.name); |
8af6cf88 | 11222 | |
86b04268 DV |
11223 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, |
11224 | new_conn_state, i) { | |
11225 | if (old_conn_state->best_encoder == &encoder->base) | |
11226 | found = true; | |
11227 | ||
11228 | if (new_conn_state->best_encoder != &encoder->base) | |
8af6cf88 | 11229 | continue; |
86b04268 | 11230 | found = enabled = true; |
ad3c558f | 11231 | |
86b04268 | 11232 | I915_STATE_WARN(new_conn_state->crtc != |
ad3c558f ML |
11233 | encoder->base.crtc, |
11234 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 11235 | } |
86b04268 DV |
11236 | |
11237 | if (!found) | |
11238 | continue; | |
0e32b39c | 11239 | |
e2c719b7 | 11240 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11241 | "encoder's enabled state mismatch " |
11242 | "(expected %i, found %i)\n", | |
11243 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
11244 | |
11245 | if (!encoder->base.crtc) { | |
4d20cd86 | 11246 | bool active; |
7c60d198 | 11247 | |
4d20cd86 ML |
11248 | active = encoder->get_hw_state(encoder, &pipe); |
11249 | I915_STATE_WARN(active, | |
11250 | "encoder detached but still enabled on pipe %c.\n", | |
11251 | pipe_name(pipe)); | |
7c60d198 | 11252 | } |
8af6cf88 | 11253 | } |
91d1b4bd DV |
11254 | } |
11255 | ||
11256 | static void | |
c0ead703 ML |
11257 | verify_crtc_state(struct drm_crtc *crtc, |
11258 | struct drm_crtc_state *old_crtc_state, | |
11259 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 11260 | { |
e7c84544 | 11261 | struct drm_device *dev = crtc->dev; |
fac5e23e | 11262 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 11263 | struct intel_encoder *encoder; |
e7c84544 ML |
11264 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11265 | struct intel_crtc_state *pipe_config, *sw_config; | |
11266 | struct drm_atomic_state *old_state; | |
11267 | bool active; | |
045ac3b5 | 11268 | |
e7c84544 | 11269 | old_state = old_crtc_state->state; |
ec2dc6a0 | 11270 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
11271 | pipe_config = to_intel_crtc_state(old_crtc_state); |
11272 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
11273 | pipe_config->base.crtc = crtc; | |
11274 | pipe_config->base.state = old_state; | |
8af6cf88 | 11275 | |
78108b7c | 11276 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 11277 | |
e7c84544 | 11278 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 11279 | |
e56134bc VS |
11280 | /* we keep both pipes enabled on 830 */ |
11281 | if (IS_I830(dev_priv)) | |
e7c84544 | 11282 | active = new_crtc_state->active; |
6c49f241 | 11283 | |
e7c84544 ML |
11284 | I915_STATE_WARN(new_crtc_state->active != active, |
11285 | "crtc active state doesn't match with hw state " | |
11286 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 11287 | |
e7c84544 ML |
11288 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
11289 | "transitional active state does not match atomic hw state " | |
11290 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 11291 | |
e7c84544 ML |
11292 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
11293 | enum pipe pipe; | |
4d20cd86 | 11294 | |
e7c84544 ML |
11295 | active = encoder->get_hw_state(encoder, &pipe); |
11296 | I915_STATE_WARN(active != new_crtc_state->active, | |
11297 | "[ENCODER:%i] active %i with crtc active %i\n", | |
11298 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 11299 | |
e7c84544 ML |
11300 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
11301 | "Encoder connected to wrong pipe %c\n", | |
11302 | pipe_name(pipe)); | |
4d20cd86 | 11303 | |
253c84c8 VS |
11304 | if (active) { |
11305 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 11306 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 11307 | } |
e7c84544 | 11308 | } |
53d9f4e9 | 11309 | |
a7d1b3f4 VS |
11310 | intel_crtc_compute_pixel_rate(pipe_config); |
11311 | ||
e7c84544 ML |
11312 | if (!new_crtc_state->active) |
11313 | return; | |
cfb23ed6 | 11314 | |
e7c84544 | 11315 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 11316 | |
749d98b8 | 11317 | sw_config = to_intel_crtc_state(new_crtc_state); |
6315b5d3 | 11318 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
11319 | pipe_config, false)) { |
11320 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
11321 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
11322 | "[hw state]"); | |
11323 | intel_dump_pipe_config(intel_crtc, sw_config, | |
11324 | "[sw state]"); | |
8af6cf88 DV |
11325 | } |
11326 | } | |
11327 | ||
91d1b4bd | 11328 | static void |
c0ead703 ML |
11329 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
11330 | struct intel_shared_dpll *pll, | |
11331 | struct drm_crtc *crtc, | |
11332 | struct drm_crtc_state *new_state) | |
91d1b4bd | 11333 | { |
91d1b4bd | 11334 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
11335 | unsigned crtc_mask; |
11336 | bool active; | |
5358901f | 11337 | |
e7c84544 | 11338 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 11339 | |
e7c84544 | 11340 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 11341 | |
e7c84544 | 11342 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 11343 | |
e7c84544 ML |
11344 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
11345 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
11346 | "pll in active use but not on in sw tracking\n"); | |
11347 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
11348 | "pll is on but not used by any active crtc\n"); | |
11349 | I915_STATE_WARN(pll->on != active, | |
11350 | "pll on state mismatch (expected %i, found %i)\n", | |
11351 | pll->on, active); | |
11352 | } | |
5358901f | 11353 | |
e7c84544 | 11354 | if (!crtc) { |
2c42e535 | 11355 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 11356 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 11357 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 11358 | |
e7c84544 ML |
11359 | return; |
11360 | } | |
11361 | ||
11362 | crtc_mask = 1 << drm_crtc_index(crtc); | |
11363 | ||
11364 | if (new_state->active) | |
11365 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
11366 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
11367 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
11368 | else | |
11369 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11370 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
11371 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 11372 | |
2c42e535 | 11373 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 11374 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 11375 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 11376 | |
2c42e535 | 11377 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
11378 | &dpll_hw_state, |
11379 | sizeof(dpll_hw_state)), | |
11380 | "pll hw state mismatch\n"); | |
11381 | } | |
11382 | ||
11383 | static void | |
c0ead703 ML |
11384 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
11385 | struct drm_crtc_state *old_crtc_state, | |
11386 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 11387 | { |
fac5e23e | 11388 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11389 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
11390 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
11391 | ||
11392 | if (new_state->shared_dpll) | |
c0ead703 | 11393 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
11394 | |
11395 | if (old_state->shared_dpll && | |
11396 | old_state->shared_dpll != new_state->shared_dpll) { | |
11397 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
11398 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
11399 | ||
11400 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11401 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
11402 | pipe_name(drm_crtc_index(crtc))); | |
2c42e535 | 11403 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 ML |
11404 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
11405 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 11406 | } |
8af6cf88 DV |
11407 | } |
11408 | ||
e7c84544 | 11409 | static void |
c0ead703 | 11410 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
11411 | struct drm_atomic_state *state, |
11412 | struct drm_crtc_state *old_state, | |
11413 | struct drm_crtc_state *new_state) | |
e7c84544 | 11414 | { |
5a21b665 DV |
11415 | if (!needs_modeset(new_state) && |
11416 | !to_intel_crtc_state(new_state)->update_pipe) | |
11417 | return; | |
11418 | ||
c0ead703 | 11419 | verify_wm_state(crtc, new_state); |
677100ce | 11420 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
11421 | verify_crtc_state(crtc, old_state, new_state); |
11422 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
11423 | } |
11424 | ||
11425 | static void | |
c0ead703 | 11426 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 11427 | { |
fac5e23e | 11428 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11429 | int i; |
11430 | ||
11431 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 11432 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
11433 | } |
11434 | ||
11435 | static void | |
677100ce ML |
11436 | intel_modeset_verify_disabled(struct drm_device *dev, |
11437 | struct drm_atomic_state *state) | |
e7c84544 | 11438 | { |
86b04268 | 11439 | verify_encoder_state(dev, state); |
677100ce | 11440 | verify_connector_state(dev, state, NULL); |
c0ead703 | 11441 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
11442 | } |
11443 | ||
80715b2f VS |
11444 | static void update_scanline_offset(struct intel_crtc *crtc) |
11445 | { | |
4f8036a2 | 11446 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
11447 | |
11448 | /* | |
11449 | * The scanline counter increments at the leading edge of hsync. | |
11450 | * | |
11451 | * On most platforms it starts counting from vtotal-1 on the | |
11452 | * first active line. That means the scanline counter value is | |
11453 | * always one less than what we would expect. Ie. just after | |
11454 | * start of vblank, which also occurs at start of hsync (on the | |
11455 | * last active line), the scanline counter will read vblank_start-1. | |
11456 | * | |
11457 | * On gen2 the scanline counter starts counting from 1 instead | |
11458 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11459 | * to keep the value positive), instead of adding one. | |
11460 | * | |
11461 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11462 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11463 | * there's an extra 1 line difference. So we need to add two instead of | |
11464 | * one to the value. | |
ec1b4ee2 VS |
11465 | * |
11466 | * On VLV/CHV DSI the scanline counter would appear to increment | |
11467 | * approx. 1/3 of a scanline before start of vblank. Unfortunately | |
11468 | * that means we can't tell whether we're in vblank or not while | |
11469 | * we're on that particular line. We must still set scanline_offset | |
11470 | * to 1 so that the vblank timestamps come out correct when we query | |
11471 | * the scanline counter from within the vblank interrupt handler. | |
11472 | * However if queried just before the start of vblank we'll get an | |
11473 | * answer that's slightly in the future. | |
80715b2f | 11474 | */ |
4f8036a2 | 11475 | if (IS_GEN2(dev_priv)) { |
124abe07 | 11476 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11477 | int vtotal; |
11478 | ||
124abe07 VS |
11479 | vtotal = adjusted_mode->crtc_vtotal; |
11480 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
11481 | vtotal /= 2; |
11482 | ||
11483 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 11484 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 11485 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11486 | crtc->scanline_offset = 2; |
11487 | } else | |
11488 | crtc->scanline_offset = 1; | |
11489 | } | |
11490 | ||
ad421372 | 11491 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 11492 | { |
225da59b | 11493 | struct drm_device *dev = state->dev; |
ed6739ef | 11494 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 11495 | struct drm_crtc *crtc; |
aa5e9b47 | 11496 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
0a9ab303 | 11497 | int i; |
ed6739ef ACO |
11498 | |
11499 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 11500 | return; |
ed6739ef | 11501 | |
aa5e9b47 | 11502 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
fb1a38a9 | 11503 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd | 11504 | struct intel_shared_dpll *old_dpll = |
aa5e9b47 | 11505 | to_intel_crtc_state(old_crtc_state)->shared_dpll; |
0a9ab303 | 11506 | |
aa5e9b47 | 11507 | if (!needs_modeset(new_crtc_state)) |
225da59b ACO |
11508 | continue; |
11509 | ||
aa5e9b47 | 11510 | to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 11511 | |
8106ddbd | 11512 | if (!old_dpll) |
fb1a38a9 | 11513 | continue; |
0a9ab303 | 11514 | |
a1c414ee | 11515 | intel_release_shared_dpll(old_dpll, intel_crtc, state); |
ad421372 | 11516 | } |
ed6739ef ACO |
11517 | } |
11518 | ||
99d736a2 ML |
11519 | /* |
11520 | * This implements the workaround described in the "notes" section of the mode | |
11521 | * set sequence documentation. When going from no pipes or single pipe to | |
11522 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
11523 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
11524 | */ | |
11525 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
11526 | { | |
11527 | struct drm_crtc_state *crtc_state; | |
11528 | struct intel_crtc *intel_crtc; | |
11529 | struct drm_crtc *crtc; | |
11530 | struct intel_crtc_state *first_crtc_state = NULL; | |
11531 | struct intel_crtc_state *other_crtc_state = NULL; | |
11532 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
11533 | int i; | |
11534 | ||
11535 | /* look at all crtc's that are going to be enabled in during modeset */ | |
aa5e9b47 | 11536 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
99d736a2 ML |
11537 | intel_crtc = to_intel_crtc(crtc); |
11538 | ||
11539 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
11540 | continue; | |
11541 | ||
11542 | if (first_crtc_state) { | |
11543 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
11544 | break; | |
11545 | } else { | |
11546 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
11547 | first_pipe = intel_crtc->pipe; | |
11548 | } | |
11549 | } | |
11550 | ||
11551 | /* No workaround needed? */ | |
11552 | if (!first_crtc_state) | |
11553 | return 0; | |
11554 | ||
11555 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
11556 | for_each_intel_crtc(state->dev, intel_crtc) { | |
11557 | struct intel_crtc_state *pipe_config; | |
11558 | ||
11559 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
11560 | if (IS_ERR(pipe_config)) | |
11561 | return PTR_ERR(pipe_config); | |
11562 | ||
11563 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
11564 | ||
11565 | if (!pipe_config->base.active || | |
11566 | needs_modeset(&pipe_config->base)) | |
11567 | continue; | |
11568 | ||
11569 | /* 2 or more enabled crtcs means no need for w/a */ | |
11570 | if (enabled_pipe != INVALID_PIPE) | |
11571 | return 0; | |
11572 | ||
11573 | enabled_pipe = intel_crtc->pipe; | |
11574 | } | |
11575 | ||
11576 | if (enabled_pipe != INVALID_PIPE) | |
11577 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
11578 | else if (other_crtc_state) | |
11579 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
11580 | ||
11581 | return 0; | |
11582 | } | |
11583 | ||
8d96561a VS |
11584 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
11585 | { | |
11586 | struct drm_crtc *crtc; | |
11587 | ||
11588 | /* Add all pipes to the state */ | |
11589 | for_each_crtc(state->dev, crtc) { | |
11590 | struct drm_crtc_state *crtc_state; | |
11591 | ||
11592 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
11593 | if (IS_ERR(crtc_state)) | |
11594 | return PTR_ERR(crtc_state); | |
11595 | } | |
11596 | ||
11597 | return 0; | |
11598 | } | |
11599 | ||
27c329ed ML |
11600 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
11601 | { | |
11602 | struct drm_crtc *crtc; | |
27c329ed | 11603 | |
8d96561a VS |
11604 | /* |
11605 | * Add all pipes to the state, and force | |
11606 | * a modeset on all the active ones. | |
11607 | */ | |
27c329ed | 11608 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
11609 | struct drm_crtc_state *crtc_state; |
11610 | int ret; | |
11611 | ||
27c329ed ML |
11612 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
11613 | if (IS_ERR(crtc_state)) | |
11614 | return PTR_ERR(crtc_state); | |
11615 | ||
11616 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
11617 | continue; | |
11618 | ||
11619 | crtc_state->mode_changed = true; | |
11620 | ||
11621 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
11622 | if (ret) | |
9780aad5 | 11623 | return ret; |
27c329ed ML |
11624 | |
11625 | ret = drm_atomic_add_affected_planes(state, crtc); | |
11626 | if (ret) | |
9780aad5 | 11627 | return ret; |
27c329ed ML |
11628 | } |
11629 | ||
9780aad5 | 11630 | return 0; |
27c329ed ML |
11631 | } |
11632 | ||
c347a676 | 11633 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 11634 | { |
565602d7 | 11635 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 11636 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 | 11637 | struct drm_crtc *crtc; |
aa5e9b47 | 11638 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
565602d7 | 11639 | int ret = 0, i; |
054518dd | 11640 | |
b359283a ML |
11641 | if (!check_digital_port_conflicts(state)) { |
11642 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
11643 | return -EINVAL; | |
11644 | } | |
11645 | ||
565602d7 ML |
11646 | intel_state->modeset = true; |
11647 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
bb0f4aab VS |
11648 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
11649 | intel_state->cdclk.actual = dev_priv->cdclk.actual; | |
565602d7 | 11650 | |
aa5e9b47 ML |
11651 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
11652 | if (new_crtc_state->active) | |
565602d7 ML |
11653 | intel_state->active_crtcs |= 1 << i; |
11654 | else | |
11655 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 | 11656 | |
aa5e9b47 | 11657 | if (old_crtc_state->active != new_crtc_state->active) |
8b4a7d05 | 11658 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); |
565602d7 ML |
11659 | } |
11660 | ||
054518dd ACO |
11661 | /* |
11662 | * See if the config requires any additional preparation, e.g. | |
11663 | * to adjust global state with pipes off. We need to do this | |
11664 | * here so we can get the modeset_pipe updated config for the new | |
11665 | * mode set on this crtc. For other crtcs we need to use the | |
11666 | * adjusted_mode bits in the crtc directly. | |
11667 | */ | |
27c329ed | 11668 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed | 11669 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
11670 | if (ret < 0) |
11671 | return ret; | |
27c329ed | 11672 | |
8d96561a | 11673 | /* |
bb0f4aab | 11674 | * Writes to dev_priv->cdclk.logical must protected by |
8d96561a VS |
11675 | * holding all the crtc locks, even if we don't end up |
11676 | * touching the hardware | |
11677 | */ | |
bb0f4aab VS |
11678 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical, |
11679 | &intel_state->cdclk.logical)) { | |
8d96561a VS |
11680 | ret = intel_lock_all_pipes(state); |
11681 | if (ret < 0) | |
11682 | return ret; | |
11683 | } | |
11684 | ||
11685 | /* All pipes must be switched off while we change the cdclk. */ | |
bb0f4aab VS |
11686 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual, |
11687 | &intel_state->cdclk.actual)) { | |
27c329ed | 11688 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
11689 | if (ret < 0) |
11690 | return ret; | |
11691 | } | |
e8788cbc | 11692 | |
bb0f4aab VS |
11693 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", |
11694 | intel_state->cdclk.logical.cdclk, | |
11695 | intel_state->cdclk.actual.cdclk); | |
e0ca7a6b | 11696 | } else { |
bb0f4aab | 11697 | to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 11698 | } |
054518dd | 11699 | |
ad421372 | 11700 | intel_modeset_clear_plls(state); |
054518dd | 11701 | |
565602d7 | 11702 | if (IS_HASWELL(dev_priv)) |
ad421372 | 11703 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 11704 | |
ad421372 | 11705 | return 0; |
c347a676 ACO |
11706 | } |
11707 | ||
aa363136 MR |
11708 | /* |
11709 | * Handle calculation of various watermark data at the end of the atomic check | |
11710 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
11711 | * handlers to ensure that all derived state has been updated. | |
11712 | */ | |
55994c2c | 11713 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
11714 | { |
11715 | struct drm_device *dev = state->dev; | |
98d39494 | 11716 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
11717 | |
11718 | /* Is there platform-specific watermark information to calculate? */ | |
11719 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
11720 | return dev_priv->display.compute_global_watermarks(state); |
11721 | ||
11722 | return 0; | |
aa363136 MR |
11723 | } |
11724 | ||
74c090b1 ML |
11725 | /** |
11726 | * intel_atomic_check - validate state object | |
11727 | * @dev: drm device | |
11728 | * @state: state to validate | |
11729 | */ | |
11730 | static int intel_atomic_check(struct drm_device *dev, | |
11731 | struct drm_atomic_state *state) | |
c347a676 | 11732 | { |
dd8b3bdb | 11733 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 11734 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 | 11735 | struct drm_crtc *crtc; |
aa5e9b47 | 11736 | struct drm_crtc_state *old_crtc_state, *crtc_state; |
c347a676 | 11737 | int ret, i; |
61333b60 | 11738 | bool any_ms = false; |
c347a676 | 11739 | |
74c090b1 | 11740 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
11741 | if (ret) |
11742 | return ret; | |
11743 | ||
aa5e9b47 | 11744 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) { |
cfb23ed6 ML |
11745 | struct intel_crtc_state *pipe_config = |
11746 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
11747 | |
11748 | /* Catch I915_MODE_FLAG_INHERITED */ | |
aa5e9b47 | 11749 | if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags) |
1ed51de9 | 11750 | crtc_state->mode_changed = true; |
cfb23ed6 | 11751 | |
af4a879e | 11752 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
11753 | continue; |
11754 | ||
af4a879e DV |
11755 | if (!crtc_state->enable) { |
11756 | any_ms = true; | |
cfb23ed6 | 11757 | continue; |
af4a879e | 11758 | } |
cfb23ed6 | 11759 | |
26495481 DV |
11760 | /* FIXME: For only active_changed we shouldn't need to do any |
11761 | * state recomputation at all. */ | |
11762 | ||
1ed51de9 DV |
11763 | ret = drm_atomic_add_affected_connectors(state, crtc); |
11764 | if (ret) | |
11765 | return ret; | |
b359283a | 11766 | |
cfb23ed6 | 11767 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
11768 | if (ret) { |
11769 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
11770 | pipe_config, "[failed]"); | |
c347a676 | 11771 | return ret; |
25aa1c39 | 11772 | } |
c347a676 | 11773 | |
73831236 | 11774 | if (i915.fastboot && |
6315b5d3 | 11775 | intel_pipe_config_compare(dev_priv, |
aa5e9b47 | 11776 | to_intel_crtc_state(old_crtc_state), |
1ed51de9 | 11777 | pipe_config, true)) { |
26495481 | 11778 | crtc_state->mode_changed = false; |
aa5e9b47 | 11779 | pipe_config->update_pipe = true; |
26495481 DV |
11780 | } |
11781 | ||
af4a879e | 11782 | if (needs_modeset(crtc_state)) |
26495481 | 11783 | any_ms = true; |
cfb23ed6 | 11784 | |
af4a879e DV |
11785 | ret = drm_atomic_add_affected_planes(state, crtc); |
11786 | if (ret) | |
11787 | return ret; | |
61333b60 | 11788 | |
26495481 DV |
11789 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
11790 | needs_modeset(crtc_state) ? | |
11791 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
11792 | } |
11793 | ||
61333b60 ML |
11794 | if (any_ms) { |
11795 | ret = intel_modeset_checks(state); | |
11796 | ||
11797 | if (ret) | |
11798 | return ret; | |
e0ca7a6b | 11799 | } else { |
bb0f4aab | 11800 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 11801 | } |
76305b1a | 11802 | |
dd8b3bdb | 11803 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
11804 | if (ret) |
11805 | return ret; | |
11806 | ||
f51be2e0 | 11807 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 11808 | return calc_watermark_data(state); |
054518dd ACO |
11809 | } |
11810 | ||
5008e874 | 11811 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 11812 | struct drm_atomic_state *state) |
5008e874 | 11813 | { |
3118cb06 | 11814 | int ret; |
d55dbd06 | 11815 | |
f935675f ML |
11816 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
11817 | if (ret) | |
11818 | return ret; | |
11819 | ||
5008e874 | 11820 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 11821 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 11822 | |
5008e874 ML |
11823 | return ret; |
11824 | } | |
11825 | ||
a2991414 ML |
11826 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
11827 | { | |
11828 | struct drm_device *dev = crtc->base.dev; | |
11829 | ||
11830 | if (!dev->max_vblank_count) | |
ca814b25 | 11831 | return drm_crtc_accurate_vblank_count(&crtc->base); |
a2991414 ML |
11832 | |
11833 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
11834 | } | |
11835 | ||
5a21b665 DV |
11836 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
11837 | struct drm_i915_private *dev_priv, | |
11838 | unsigned crtc_mask) | |
e8861675 | 11839 | { |
5a21b665 DV |
11840 | unsigned last_vblank_count[I915_MAX_PIPES]; |
11841 | enum pipe pipe; | |
11842 | int ret; | |
e8861675 | 11843 | |
5a21b665 DV |
11844 | if (!crtc_mask) |
11845 | return; | |
e8861675 | 11846 | |
5a21b665 | 11847 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
11848 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
11849 | pipe); | |
e8861675 | 11850 | |
5a21b665 | 11851 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
11852 | continue; |
11853 | ||
e2af48c6 | 11854 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
11855 | if (WARN_ON(ret != 0)) { |
11856 | crtc_mask &= ~(1 << pipe); | |
11857 | continue; | |
e8861675 ML |
11858 | } |
11859 | ||
e2af48c6 | 11860 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
11861 | } |
11862 | ||
5a21b665 | 11863 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
11864 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
11865 | pipe); | |
5a21b665 | 11866 | long lret; |
e8861675 | 11867 | |
5a21b665 DV |
11868 | if (!((1 << pipe) & crtc_mask)) |
11869 | continue; | |
d55dbd06 | 11870 | |
5a21b665 DV |
11871 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
11872 | last_vblank_count[pipe] != | |
e2af48c6 | 11873 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 11874 | msecs_to_jiffies(50)); |
d55dbd06 | 11875 | |
5a21b665 | 11876 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 11877 | |
e2af48c6 | 11878 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
11879 | } |
11880 | } | |
11881 | ||
5a21b665 | 11882 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 11883 | { |
5a21b665 DV |
11884 | /* fb updated, need to unpin old fb */ |
11885 | if (crtc_state->fb_changed) | |
11886 | return true; | |
a6747b73 | 11887 | |
5a21b665 DV |
11888 | /* wm changes, need vblank before final wm's */ |
11889 | if (crtc_state->update_wm_post) | |
11890 | return true; | |
a6747b73 | 11891 | |
5eeb798b | 11892 | if (crtc_state->wm.need_postvbl_update) |
5a21b665 | 11893 | return true; |
a6747b73 | 11894 | |
5a21b665 | 11895 | return false; |
e8861675 ML |
11896 | } |
11897 | ||
896e5bb0 L |
11898 | static void intel_update_crtc(struct drm_crtc *crtc, |
11899 | struct drm_atomic_state *state, | |
11900 | struct drm_crtc_state *old_crtc_state, | |
aa5e9b47 | 11901 | struct drm_crtc_state *new_crtc_state, |
896e5bb0 L |
11902 | unsigned int *crtc_vblank_mask) |
11903 | { | |
11904 | struct drm_device *dev = crtc->dev; | |
11905 | struct drm_i915_private *dev_priv = to_i915(dev); | |
11906 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
aa5e9b47 ML |
11907 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); |
11908 | bool modeset = needs_modeset(new_crtc_state); | |
896e5bb0 L |
11909 | |
11910 | if (modeset) { | |
11911 | update_scanline_offset(intel_crtc); | |
11912 | dev_priv->display.crtc_enable(pipe_config, state); | |
11913 | } else { | |
aa5e9b47 ML |
11914 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
11915 | pipe_config); | |
896e5bb0 L |
11916 | } |
11917 | ||
11918 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
11919 | intel_fbc_enable( | |
11920 | intel_crtc, pipe_config, | |
11921 | to_intel_plane_state(crtc->primary->state)); | |
11922 | } | |
11923 | ||
11924 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
11925 | ||
11926 | if (needs_vblank_wait(pipe_config)) | |
11927 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
11928 | } | |
11929 | ||
11930 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
11931 | unsigned int *crtc_vblank_mask) | |
11932 | { | |
11933 | struct drm_crtc *crtc; | |
aa5e9b47 | 11934 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
896e5bb0 L |
11935 | int i; |
11936 | ||
aa5e9b47 ML |
11937 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
11938 | if (!new_crtc_state->active) | |
896e5bb0 L |
11939 | continue; |
11940 | ||
11941 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 11942 | new_crtc_state, crtc_vblank_mask); |
896e5bb0 L |
11943 | } |
11944 | } | |
11945 | ||
27082493 L |
11946 | static void skl_update_crtcs(struct drm_atomic_state *state, |
11947 | unsigned int *crtc_vblank_mask) | |
11948 | { | |
0f0f74bc | 11949 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
11950 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
11951 | struct drm_crtc *crtc; | |
ce0ba283 | 11952 | struct intel_crtc *intel_crtc; |
aa5e9b47 | 11953 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
ce0ba283 | 11954 | struct intel_crtc_state *cstate; |
27082493 L |
11955 | unsigned int updated = 0; |
11956 | bool progress; | |
11957 | enum pipe pipe; | |
5eff503b ML |
11958 | int i; |
11959 | ||
11960 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
11961 | ||
aa5e9b47 | 11962 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) |
5eff503b | 11963 | /* ignore allocations for crtc's that have been turned off. */ |
aa5e9b47 | 11964 | if (new_crtc_state->active) |
5eff503b | 11965 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; |
27082493 L |
11966 | |
11967 | /* | |
11968 | * Whenever the number of active pipes changes, we need to make sure we | |
11969 | * update the pipes in the right order so that their ddb allocations | |
11970 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
11971 | * cause pipe underruns and other bad stuff. | |
11972 | */ | |
11973 | do { | |
27082493 L |
11974 | progress = false; |
11975 | ||
aa5e9b47 | 11976 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
27082493 L |
11977 | bool vbl_wait = false; |
11978 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
11979 | |
11980 | intel_crtc = to_intel_crtc(crtc); | |
11981 | cstate = to_intel_crtc_state(crtc->state); | |
11982 | pipe = intel_crtc->pipe; | |
27082493 | 11983 | |
5eff503b | 11984 | if (updated & cmask || !cstate->base.active) |
27082493 | 11985 | continue; |
5eff503b ML |
11986 | |
11987 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
11988 | continue; |
11989 | ||
11990 | updated |= cmask; | |
5eff503b | 11991 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
11992 | |
11993 | /* | |
11994 | * If this is an already active pipe, it's DDB changed, | |
11995 | * and this isn't the last pipe that needs updating | |
11996 | * then we need to wait for a vblank to pass for the | |
11997 | * new ddb allocation to take effect. | |
11998 | */ | |
ce0ba283 | 11999 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 12000 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
aa5e9b47 | 12001 | !new_crtc_state->active_changed && |
27082493 L |
12002 | intel_state->wm_results.dirty_pipes != updated) |
12003 | vbl_wait = true; | |
12004 | ||
12005 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 12006 | new_crtc_state, crtc_vblank_mask); |
27082493 L |
12007 | |
12008 | if (vbl_wait) | |
0f0f74bc | 12009 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
12010 | |
12011 | progress = true; | |
12012 | } | |
12013 | } while (progress); | |
12014 | } | |
12015 | ||
ba318c61 CW |
12016 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
12017 | { | |
12018 | struct intel_atomic_state *state, *next; | |
12019 | struct llist_node *freed; | |
12020 | ||
12021 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
12022 | llist_for_each_entry_safe(state, next, freed, freed) | |
12023 | drm_atomic_state_put(&state->base); | |
12024 | } | |
12025 | ||
12026 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
12027 | { | |
12028 | struct drm_i915_private *dev_priv = | |
12029 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
12030 | ||
12031 | intel_atomic_helper_free_state(dev_priv); | |
12032 | } | |
12033 | ||
94f05024 | 12034 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 12035 | { |
94f05024 | 12036 | struct drm_device *dev = state->dev; |
565602d7 | 12037 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12038 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa5e9b47 | 12039 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
7580d774 | 12040 | struct drm_crtc *crtc; |
5a21b665 | 12041 | struct intel_crtc_state *intel_cstate; |
5a21b665 | 12042 | bool hw_check = intel_state->modeset; |
d8fc70b7 | 12043 | u64 put_domains[I915_MAX_PIPES] = {}; |
5a21b665 | 12044 | unsigned crtc_vblank_mask = 0; |
e95433c7 | 12045 | int i; |
a6778b3c | 12046 | |
ea0000f0 DV |
12047 | drm_atomic_helper_wait_for_dependencies(state); |
12048 | ||
c3b32658 | 12049 | if (intel_state->modeset) |
5a21b665 | 12050 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 12051 | |
aa5e9b47 | 12052 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
a539205a ML |
12053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12054 | ||
aa5e9b47 ML |
12055 | if (needs_modeset(new_crtc_state) || |
12056 | to_intel_crtc_state(new_crtc_state)->update_pipe) { | |
5a21b665 DV |
12057 | hw_check = true; |
12058 | ||
12059 | put_domains[to_intel_crtc(crtc)->pipe] = | |
12060 | modeset_get_crtc_power_domains(crtc, | |
aa5e9b47 | 12061 | to_intel_crtc_state(new_crtc_state)); |
5a21b665 DV |
12062 | } |
12063 | ||
aa5e9b47 | 12064 | if (!needs_modeset(new_crtc_state)) |
61333b60 ML |
12065 | continue; |
12066 | ||
aa5e9b47 ML |
12067 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12068 | to_intel_crtc_state(new_crtc_state)); | |
460da916 | 12069 | |
29ceb0e6 VS |
12070 | if (old_crtc_state->active) { |
12071 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 12072 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 12073 | intel_crtc->active = false; |
58f9c0bc | 12074 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 12075 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
12076 | |
12077 | /* | |
12078 | * Underruns don't always raise | |
12079 | * interrupts, so check manually. | |
12080 | */ | |
12081 | intel_check_cpu_fifo_underruns(dev_priv); | |
12082 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 12083 | |
e62929b3 ML |
12084 | if (!crtc->state->active) { |
12085 | /* | |
12086 | * Make sure we don't call initial_watermarks | |
12087 | * for ILK-style watermark updates. | |
ff32c54e VS |
12088 | * |
12089 | * No clue what this is supposed to achieve. | |
e62929b3 | 12090 | */ |
ff32c54e | 12091 | if (INTEL_GEN(dev_priv) >= 9) |
e62929b3 ML |
12092 | dev_priv->display.initial_watermarks(intel_state, |
12093 | to_intel_crtc_state(crtc->state)); | |
e62929b3 | 12094 | } |
a539205a | 12095 | } |
b8cecdf5 | 12096 | } |
7758a113 | 12097 | |
ea9d758d DV |
12098 | /* Only after disabling all output pipelines that will be changed can we |
12099 | * update the the output configuration. */ | |
4740b0f2 | 12100 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 12101 | |
565602d7 | 12102 | if (intel_state->modeset) { |
4740b0f2 | 12103 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 | 12104 | |
b0587e4d | 12105 | intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
f6d1973d | 12106 | |
656d1b89 L |
12107 | /* |
12108 | * SKL workaround: bspec recommends we disable the SAGV when we | |
12109 | * have more then one pipe enabled | |
12110 | */ | |
56feca91 | 12111 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 12112 | intel_disable_sagv(dev_priv); |
656d1b89 | 12113 | |
677100ce | 12114 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 12115 | } |
47fab737 | 12116 | |
896e5bb0 | 12117 | /* Complete the events for pipes that have now been disabled */ |
aa5e9b47 ML |
12118 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12119 | bool modeset = needs_modeset(new_crtc_state); | |
80715b2f | 12120 | |
1f7528c4 | 12121 | /* Complete events for now disable pipes here. */ |
aa5e9b47 | 12122 | if (modeset && !new_crtc_state->active && new_crtc_state->event) { |
1f7528c4 | 12123 | spin_lock_irq(&dev->event_lock); |
aa5e9b47 | 12124 | drm_crtc_send_vblank_event(crtc, new_crtc_state->event); |
1f7528c4 DV |
12125 | spin_unlock_irq(&dev->event_lock); |
12126 | ||
aa5e9b47 | 12127 | new_crtc_state->event = NULL; |
1f7528c4 | 12128 | } |
177246a8 MR |
12129 | } |
12130 | ||
896e5bb0 L |
12131 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
12132 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
12133 | ||
94f05024 DV |
12134 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
12135 | * already, but still need the state for the delayed optimization. To | |
12136 | * fix this: | |
12137 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
12138 | * - schedule that vblank worker _before_ calling hw_done | |
12139 | * - at the start of commit_tail, cancel it _synchrously | |
12140 | * - switch over to the vblank wait helper in the core after that since | |
12141 | * we don't need out special handling any more. | |
12142 | */ | |
5a21b665 DV |
12143 | if (!state->legacy_cursor_update) |
12144 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
12145 | ||
12146 | /* | |
12147 | * Now that the vblank has passed, we can go ahead and program the | |
12148 | * optimal watermarks on platforms that need two-step watermark | |
12149 | * programming. | |
12150 | * | |
12151 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
12152 | */ | |
aa5e9b47 ML |
12153 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12154 | intel_cstate = to_intel_crtc_state(new_crtc_state); | |
5a21b665 DV |
12155 | |
12156 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
12157 | dev_priv->display.optimize_watermarks(intel_state, |
12158 | intel_cstate); | |
5a21b665 DV |
12159 | } |
12160 | ||
aa5e9b47 | 12161 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
5a21b665 DV |
12162 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); |
12163 | ||
12164 | if (put_domains[i]) | |
12165 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
12166 | ||
aa5e9b47 | 12167 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); |
5a21b665 DV |
12168 | } |
12169 | ||
56feca91 | 12170 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 12171 | intel_enable_sagv(dev_priv); |
656d1b89 | 12172 | |
94f05024 DV |
12173 | drm_atomic_helper_commit_hw_done(state); |
12174 | ||
d5553c09 CW |
12175 | if (intel_state->modeset) { |
12176 | /* As one of the primary mmio accessors, KMS has a high | |
12177 | * likelihood of triggering bugs in unclaimed access. After we | |
12178 | * finish modesetting, see if an error has been flagged, and if | |
12179 | * so enable debugging for the next modeset - and hope we catch | |
12180 | * the culprit. | |
12181 | */ | |
12182 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
5a21b665 | 12183 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
d5553c09 | 12184 | } |
5a21b665 DV |
12185 | |
12186 | mutex_lock(&dev->struct_mutex); | |
12187 | drm_atomic_helper_cleanup_planes(dev, state); | |
12188 | mutex_unlock(&dev->struct_mutex); | |
12189 | ||
ea0000f0 DV |
12190 | drm_atomic_helper_commit_cleanup_done(state); |
12191 | ||
0853695c | 12192 | drm_atomic_state_put(state); |
f30da187 | 12193 | |
ba318c61 | 12194 | intel_atomic_helper_free_state(dev_priv); |
94f05024 DV |
12195 | } |
12196 | ||
12197 | static void intel_atomic_commit_work(struct work_struct *work) | |
12198 | { | |
c004a90b CW |
12199 | struct drm_atomic_state *state = |
12200 | container_of(work, struct drm_atomic_state, commit_work); | |
12201 | ||
94f05024 DV |
12202 | intel_atomic_commit_tail(state); |
12203 | } | |
12204 | ||
c004a90b CW |
12205 | static int __i915_sw_fence_call |
12206 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
12207 | enum i915_sw_fence_notify notify) | |
12208 | { | |
12209 | struct intel_atomic_state *state = | |
12210 | container_of(fence, struct intel_atomic_state, commit_ready); | |
12211 | ||
12212 | switch (notify) { | |
12213 | case FENCE_COMPLETE: | |
12214 | if (state->base.commit_work.func) | |
12215 | queue_work(system_unbound_wq, &state->base.commit_work); | |
12216 | break; | |
12217 | ||
12218 | case FENCE_FREE: | |
eb955eee CW |
12219 | { |
12220 | struct intel_atomic_helper *helper = | |
12221 | &to_i915(state->base.dev)->atomic_helper; | |
12222 | ||
12223 | if (llist_add(&state->freed, &helper->free_list)) | |
12224 | schedule_work(&helper->free_work); | |
12225 | break; | |
12226 | } | |
c004a90b CW |
12227 | } |
12228 | ||
12229 | return NOTIFY_DONE; | |
12230 | } | |
12231 | ||
6c9c1b38 DV |
12232 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
12233 | { | |
aa5e9b47 | 12234 | struct drm_plane_state *old_plane_state, *new_plane_state; |
6c9c1b38 | 12235 | struct drm_plane *plane; |
6c9c1b38 DV |
12236 | int i; |
12237 | ||
aa5e9b47 | 12238 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) |
faf5bf0a | 12239 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), |
aa5e9b47 | 12240 | intel_fb_obj(new_plane_state->fb), |
faf5bf0a | 12241 | to_intel_plane(plane)->frontbuffer_bit); |
6c9c1b38 DV |
12242 | } |
12243 | ||
94f05024 DV |
12244 | /** |
12245 | * intel_atomic_commit - commit validated state object | |
12246 | * @dev: DRM device | |
12247 | * @state: the top-level driver state object | |
12248 | * @nonblock: nonblocking commit | |
12249 | * | |
12250 | * This function commits a top-level state object that has been validated | |
12251 | * with drm_atomic_helper_check(). | |
12252 | * | |
94f05024 DV |
12253 | * RETURNS |
12254 | * Zero for success or -errno. | |
12255 | */ | |
12256 | static int intel_atomic_commit(struct drm_device *dev, | |
12257 | struct drm_atomic_state *state, | |
12258 | bool nonblock) | |
12259 | { | |
12260 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 12261 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
12262 | int ret = 0; |
12263 | ||
94f05024 DV |
12264 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
12265 | if (ret) | |
12266 | return ret; | |
12267 | ||
c004a90b CW |
12268 | drm_atomic_state_get(state); |
12269 | i915_sw_fence_init(&intel_state->commit_ready, | |
12270 | intel_atomic_commit_ready); | |
94f05024 | 12271 | |
d07f0e59 | 12272 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
12273 | if (ret) { |
12274 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 12275 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
12276 | return ret; |
12277 | } | |
12278 | ||
440df938 VS |
12279 | /* |
12280 | * The intel_legacy_cursor_update() fast path takes care | |
12281 | * of avoiding the vblank waits for simple cursor | |
12282 | * movement and flips. For cursor on/off and size changes, | |
12283 | * we want to perform the vblank waits so that watermark | |
12284 | * updates happen during the correct frames. Gen9+ have | |
12285 | * double buffered watermarks and so shouldn't need this. | |
12286 | * | |
12287 | * Do this after drm_atomic_helper_setup_commit() and | |
12288 | * intel_atomic_prepare_commit() because we still want | |
12289 | * to skip the flip and fb cleanup waits. Although that | |
12290 | * does risk yanking the mapping from under the display | |
12291 | * engine. | |
12292 | * | |
12293 | * FIXME doing watermarks and fb cleanup from a vblank worker | |
12294 | * (assuming we had any) would solve these problems. | |
12295 | */ | |
12296 | if (INTEL_GEN(dev_priv) < 9) | |
12297 | state->legacy_cursor_update = false; | |
12298 | ||
0806f4ee ML |
12299 | ret = drm_atomic_helper_swap_state(state, true); |
12300 | if (ret) { | |
12301 | i915_sw_fence_commit(&intel_state->commit_ready); | |
12302 | ||
12303 | mutex_lock(&dev->struct_mutex); | |
12304 | drm_atomic_helper_cleanup_planes(dev, state); | |
12305 | mutex_unlock(&dev->struct_mutex); | |
12306 | return ret; | |
12307 | } | |
94f05024 | 12308 | dev_priv->wm.distrust_bios_wm = false; |
3c0fb588 | 12309 | intel_shared_dpll_swap_state(state); |
6c9c1b38 | 12310 | intel_atomic_track_fbs(state); |
94f05024 | 12311 | |
c3b32658 ML |
12312 | if (intel_state->modeset) { |
12313 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
12314 | sizeof(intel_state->min_pixclk)); | |
12315 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
bb0f4aab VS |
12316 | dev_priv->cdclk.logical = intel_state->cdclk.logical; |
12317 | dev_priv->cdclk.actual = intel_state->cdclk.actual; | |
c3b32658 ML |
12318 | } |
12319 | ||
0853695c | 12320 | drm_atomic_state_get(state); |
c004a90b CW |
12321 | INIT_WORK(&state->commit_work, |
12322 | nonblock ? intel_atomic_commit_work : NULL); | |
12323 | ||
12324 | i915_sw_fence_commit(&intel_state->commit_ready); | |
12325 | if (!nonblock) { | |
12326 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 12327 | intel_atomic_commit_tail(state); |
c004a90b | 12328 | } |
75714940 | 12329 | |
74c090b1 | 12330 | return 0; |
7f27126e JB |
12331 | } |
12332 | ||
f6e5b160 | 12333 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
3fab2f09 | 12334 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 12335 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 12336 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 12337 | .destroy = intel_crtc_destroy, |
4c01ded5 | 12338 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
12339 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12340 | .atomic_destroy_state = intel_crtc_destroy_state, | |
8c6b709d | 12341 | .set_crc_source = intel_crtc_set_crc_source, |
f6e5b160 CW |
12342 | }; |
12343 | ||
6beb8c23 MR |
12344 | /** |
12345 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12346 | * @plane: drm plane to prepare for | |
12347 | * @fb: framebuffer to prepare for presentation | |
12348 | * | |
12349 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12350 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12351 | * bits. Some older platforms need special physical address handling for | |
12352 | * cursor planes. | |
12353 | * | |
f935675f ML |
12354 | * Must be called with struct_mutex held. |
12355 | * | |
6beb8c23 MR |
12356 | * Returns 0 on success, negative error code on failure. |
12357 | */ | |
12358 | int | |
12359 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 12360 | struct drm_plane_state *new_state) |
465c120c | 12361 | { |
c004a90b CW |
12362 | struct intel_atomic_state *intel_state = |
12363 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 12364 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 12365 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 12366 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 12367 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 12368 | int ret; |
465c120c | 12369 | |
57822dc6 CW |
12370 | if (obj) { |
12371 | if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
12372 | INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
fabac484 | 12373 | const int align = intel_cursor_alignment(dev_priv); |
57822dc6 CW |
12374 | |
12375 | ret = i915_gem_object_attach_phys(obj, align); | |
12376 | if (ret) { | |
12377 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
12378 | return ret; | |
12379 | } | |
12380 | } else { | |
12381 | struct i915_vma *vma; | |
12382 | ||
12383 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
12384 | if (IS_ERR(vma)) { | |
12385 | DRM_DEBUG_KMS("failed to pin object\n"); | |
12386 | return PTR_ERR(vma); | |
12387 | } | |
12388 | ||
12389 | to_intel_plane_state(new_state)->vma = vma; | |
12390 | } | |
12391 | } | |
12392 | ||
1ee49399 | 12393 | if (!obj && !old_obj) |
465c120c MR |
12394 | return 0; |
12395 | ||
5008e874 ML |
12396 | if (old_obj) { |
12397 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
12398 | drm_atomic_get_existing_crtc_state(new_state->state, |
12399 | plane->state->crtc); | |
5008e874 ML |
12400 | |
12401 | /* Big Hammer, we also need to ensure that any pending | |
12402 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
12403 | * current scanout is retired before unpinning the old | |
12404 | * framebuffer. Note that we rely on userspace rendering | |
12405 | * into the buffer attached to the pipe they are waiting | |
12406 | * on. If not, userspace generates a GPU hang with IPEHR | |
12407 | * point to the MI_WAIT_FOR_EVENT. | |
12408 | * | |
12409 | * This should only fail upon a hung GPU, in which case we | |
12410 | * can safely continue. | |
12411 | */ | |
c004a90b CW |
12412 | if (needs_modeset(crtc_state)) { |
12413 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
12414 | old_obj->resv, NULL, | |
12415 | false, 0, | |
12416 | GFP_KERNEL); | |
12417 | if (ret < 0) | |
12418 | return ret; | |
f4457ae7 | 12419 | } |
5008e874 ML |
12420 | } |
12421 | ||
c004a90b CW |
12422 | if (new_state->fence) { /* explicit fencing */ |
12423 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
12424 | new_state->fence, | |
12425 | I915_FENCE_TIMEOUT, | |
12426 | GFP_KERNEL); | |
12427 | if (ret < 0) | |
12428 | return ret; | |
12429 | } | |
12430 | ||
c37efb99 CW |
12431 | if (!obj) |
12432 | return 0; | |
12433 | ||
c004a90b CW |
12434 | if (!new_state->fence) { /* implicit fencing */ |
12435 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
12436 | obj->resv, NULL, | |
12437 | false, I915_FENCE_TIMEOUT, | |
12438 | GFP_KERNEL); | |
12439 | if (ret < 0) | |
12440 | return ret; | |
6b5e90f5 CW |
12441 | |
12442 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
c004a90b | 12443 | } |
5a21b665 | 12444 | |
d07f0e59 | 12445 | return 0; |
6beb8c23 MR |
12446 | } |
12447 | ||
38f3ce3a MR |
12448 | /** |
12449 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12450 | * @plane: drm plane to clean up for | |
12451 | * @fb: old framebuffer that was on plane | |
12452 | * | |
12453 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
12454 | * |
12455 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
12456 | */ |
12457 | void | |
12458 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 12459 | struct drm_plane_state *old_state) |
38f3ce3a | 12460 | { |
be1e3415 | 12461 | struct i915_vma *vma; |
38f3ce3a | 12462 | |
be1e3415 CW |
12463 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
12464 | vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); | |
12465 | if (vma) | |
12466 | intel_unpin_fb_vma(vma); | |
465c120c MR |
12467 | } |
12468 | ||
6156a456 CK |
12469 | int |
12470 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
12471 | { | |
5b7280f0 | 12472 | struct drm_i915_private *dev_priv; |
6156a456 | 12473 | int max_scale; |
5b7280f0 | 12474 | int crtc_clock, max_dotclk; |
6156a456 | 12475 | |
bf8a0af0 | 12476 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
12477 | return DRM_PLANE_HELPER_NO_SCALING; |
12478 | ||
5b7280f0 ACO |
12479 | dev_priv = to_i915(intel_crtc->base.dev); |
12480 | ||
6156a456 | 12481 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
5b7280f0 ACO |
12482 | max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; |
12483 | ||
12484 | if (IS_GEMINILAKE(dev_priv)) | |
12485 | max_dotclk *= 2; | |
6156a456 | 12486 | |
5b7280f0 | 12487 | if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) |
6156a456 CK |
12488 | return DRM_PLANE_HELPER_NO_SCALING; |
12489 | ||
12490 | /* | |
12491 | * skl max scale is lower of: | |
12492 | * close to 3 but not 3, -1 is for that purpose | |
12493 | * or | |
12494 | * cdclk/crtc_clock | |
12495 | */ | |
5b7280f0 ACO |
12496 | max_scale = min((1 << 16) * 3 - 1, |
12497 | (1 << 8) * ((max_dotclk << 8) / crtc_clock)); | |
6156a456 CK |
12498 | |
12499 | return max_scale; | |
12500 | } | |
12501 | ||
465c120c | 12502 | static int |
282dbf9b | 12503 | intel_check_primary_plane(struct intel_plane *plane, |
061e4b8d | 12504 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
12505 | struct intel_plane_state *state) |
12506 | { | |
282dbf9b | 12507 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
2b875c22 | 12508 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 12509 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
12510 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
12511 | bool can_position = false; | |
b63a16f6 | 12512 | int ret; |
465c120c | 12513 | |
b63a16f6 | 12514 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
12515 | /* use scaler when colorkey is not required */ |
12516 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
12517 | min_scale = 1; | |
12518 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
12519 | } | |
d8106366 | 12520 | can_position = true; |
6156a456 | 12521 | } |
d8106366 | 12522 | |
cc926387 DV |
12523 | ret = drm_plane_helper_check_state(&state->base, |
12524 | &state->clip, | |
12525 | min_scale, max_scale, | |
12526 | can_position, true); | |
b63a16f6 VS |
12527 | if (ret) |
12528 | return ret; | |
12529 | ||
cc926387 | 12530 | if (!state->base.fb) |
b63a16f6 VS |
12531 | return 0; |
12532 | ||
12533 | if (INTEL_GEN(dev_priv) >= 9) { | |
12534 | ret = skl_check_plane_surface(state); | |
12535 | if (ret) | |
12536 | return ret; | |
a0864d59 VS |
12537 | |
12538 | state->ctl = skl_plane_ctl(crtc_state, state); | |
12539 | } else { | |
5b7fcc44 VS |
12540 | ret = i9xx_check_plane_surface(state); |
12541 | if (ret) | |
12542 | return ret; | |
12543 | ||
a0864d59 | 12544 | state->ctl = i9xx_plane_ctl(crtc_state, state); |
b63a16f6 VS |
12545 | } |
12546 | ||
12547 | return 0; | |
14af293f GP |
12548 | } |
12549 | ||
5a21b665 DV |
12550 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
12551 | struct drm_crtc_state *old_crtc_state) | |
12552 | { | |
12553 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 12554 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 12555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
12556 | struct intel_crtc_state *intel_cstate = |
12557 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 12558 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 12559 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
12560 | struct intel_atomic_state *old_intel_state = |
12561 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
12562 | bool modeset = needs_modeset(crtc->state); |
12563 | ||
567f0792 ML |
12564 | if (!modeset && |
12565 | (intel_cstate->base.color_mgmt_changed || | |
12566 | intel_cstate->update_pipe)) { | |
12567 | intel_color_set_csc(crtc->state); | |
12568 | intel_color_load_luts(crtc->state); | |
12569 | } | |
12570 | ||
5a21b665 DV |
12571 | /* Perform vblank evasion around commit operation */ |
12572 | intel_pipe_update_start(intel_crtc); | |
12573 | ||
12574 | if (modeset) | |
e62929b3 | 12575 | goto out; |
5a21b665 | 12576 | |
ccf010fb ML |
12577 | if (intel_cstate->update_pipe) |
12578 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
12579 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 12580 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 12581 | |
e62929b3 | 12582 | out: |
ccf010fb ML |
12583 | if (dev_priv->display.atomic_update_watermarks) |
12584 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
12585 | intel_cstate); | |
5a21b665 DV |
12586 | } |
12587 | ||
12588 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
12589 | struct drm_crtc_state *old_crtc_state) | |
12590 | { | |
12591 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12592 | ||
8b5d27b9 | 12593 | intel_pipe_update_end(intel_crtc); |
5a21b665 DV |
12594 | } |
12595 | ||
cf4c7c12 | 12596 | /** |
4a3b8769 MR |
12597 | * intel_plane_destroy - destroy a plane |
12598 | * @plane: plane to destroy | |
cf4c7c12 | 12599 | * |
4a3b8769 MR |
12600 | * Common destruction function for all types of planes (primary, cursor, |
12601 | * sprite). | |
cf4c7c12 | 12602 | */ |
4a3b8769 | 12603 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 12604 | { |
465c120c | 12605 | drm_plane_cleanup(plane); |
69ae561f | 12606 | kfree(to_intel_plane(plane)); |
465c120c MR |
12607 | } |
12608 | ||
65a3fea0 | 12609 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
12610 | .update_plane = drm_atomic_helper_update_plane, |
12611 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 12612 | .destroy = intel_plane_destroy, |
c196e1d6 | 12613 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
12614 | .atomic_get_property = intel_plane_atomic_get_property, |
12615 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
12616 | .atomic_duplicate_state = intel_plane_duplicate_state, |
12617 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
12618 | }; |
12619 | ||
f79f2692 ML |
12620 | static int |
12621 | intel_legacy_cursor_update(struct drm_plane *plane, | |
12622 | struct drm_crtc *crtc, | |
12623 | struct drm_framebuffer *fb, | |
12624 | int crtc_x, int crtc_y, | |
12625 | unsigned int crtc_w, unsigned int crtc_h, | |
12626 | uint32_t src_x, uint32_t src_y, | |
34a2ab5e DV |
12627 | uint32_t src_w, uint32_t src_h, |
12628 | struct drm_modeset_acquire_ctx *ctx) | |
f79f2692 ML |
12629 | { |
12630 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
12631 | int ret; | |
12632 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
12633 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
12634 | struct drm_framebuffer *old_fb; | |
12635 | struct drm_crtc_state *crtc_state = crtc->state; | |
be1e3415 | 12636 | struct i915_vma *old_vma; |
f79f2692 ML |
12637 | |
12638 | /* | |
12639 | * When crtc is inactive or there is a modeset pending, | |
12640 | * wait for it to complete in the slowpath | |
12641 | */ | |
12642 | if (!crtc_state->active || needs_modeset(crtc_state) || | |
12643 | to_intel_crtc_state(crtc_state)->update_pipe) | |
12644 | goto slow; | |
12645 | ||
12646 | old_plane_state = plane->state; | |
12647 | ||
12648 | /* | |
12649 | * If any parameters change that may affect watermarks, | |
12650 | * take the slowpath. Only changing fb or position should be | |
12651 | * in the fastpath. | |
12652 | */ | |
12653 | if (old_plane_state->crtc != crtc || | |
12654 | old_plane_state->src_w != src_w || | |
12655 | old_plane_state->src_h != src_h || | |
12656 | old_plane_state->crtc_w != crtc_w || | |
12657 | old_plane_state->crtc_h != crtc_h || | |
a5509abd | 12658 | !old_plane_state->fb != !fb) |
f79f2692 ML |
12659 | goto slow; |
12660 | ||
12661 | new_plane_state = intel_plane_duplicate_state(plane); | |
12662 | if (!new_plane_state) | |
12663 | return -ENOMEM; | |
12664 | ||
12665 | drm_atomic_set_fb_for_plane(new_plane_state, fb); | |
12666 | ||
12667 | new_plane_state->src_x = src_x; | |
12668 | new_plane_state->src_y = src_y; | |
12669 | new_plane_state->src_w = src_w; | |
12670 | new_plane_state->src_h = src_h; | |
12671 | new_plane_state->crtc_x = crtc_x; | |
12672 | new_plane_state->crtc_y = crtc_y; | |
12673 | new_plane_state->crtc_w = crtc_w; | |
12674 | new_plane_state->crtc_h = crtc_h; | |
12675 | ||
12676 | ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), | |
12677 | to_intel_plane_state(new_plane_state)); | |
12678 | if (ret) | |
12679 | goto out_free; | |
12680 | ||
f79f2692 ML |
12681 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
12682 | if (ret) | |
12683 | goto out_free; | |
12684 | ||
12685 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
fabac484 | 12686 | int align = intel_cursor_alignment(dev_priv); |
f79f2692 ML |
12687 | |
12688 | ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align); | |
12689 | if (ret) { | |
12690 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
12691 | goto out_unlock; | |
12692 | } | |
12693 | } else { | |
12694 | struct i915_vma *vma; | |
12695 | ||
12696 | vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); | |
12697 | if (IS_ERR(vma)) { | |
12698 | DRM_DEBUG_KMS("failed to pin object\n"); | |
12699 | ||
12700 | ret = PTR_ERR(vma); | |
12701 | goto out_unlock; | |
12702 | } | |
be1e3415 CW |
12703 | |
12704 | to_intel_plane_state(new_plane_state)->vma = vma; | |
f79f2692 ML |
12705 | } |
12706 | ||
12707 | old_fb = old_plane_state->fb; | |
be1e3415 | 12708 | old_vma = to_intel_plane_state(old_plane_state)->vma; |
f79f2692 ML |
12709 | |
12710 | i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), | |
12711 | intel_plane->frontbuffer_bit); | |
12712 | ||
12713 | /* Swap plane state */ | |
12714 | new_plane_state->fence = old_plane_state->fence; | |
12715 | *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state); | |
12716 | new_plane_state->fence = NULL; | |
12717 | new_plane_state->fb = old_fb; | |
be1e3415 | 12718 | to_intel_plane_state(new_plane_state)->vma = old_vma; |
f79f2692 | 12719 | |
72259536 VS |
12720 | if (plane->state->visible) { |
12721 | trace_intel_update_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 12722 | intel_plane->update_plane(intel_plane, |
a5509abd VS |
12723 | to_intel_crtc_state(crtc->state), |
12724 | to_intel_plane_state(plane->state)); | |
72259536 VS |
12725 | } else { |
12726 | trace_intel_disable_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 12727 | intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc)); |
72259536 | 12728 | } |
f79f2692 ML |
12729 | |
12730 | intel_cleanup_plane_fb(plane, new_plane_state); | |
12731 | ||
12732 | out_unlock: | |
12733 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
12734 | out_free: | |
12735 | intel_plane_destroy_state(plane, new_plane_state); | |
12736 | return ret; | |
12737 | ||
f79f2692 ML |
12738 | slow: |
12739 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
12740 | crtc_x, crtc_y, crtc_w, crtc_h, | |
34a2ab5e | 12741 | src_x, src_y, src_w, src_h, ctx); |
f79f2692 ML |
12742 | } |
12743 | ||
12744 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
12745 | .update_plane = intel_legacy_cursor_update, | |
12746 | .disable_plane = drm_atomic_helper_disable_plane, | |
12747 | .destroy = intel_plane_destroy, | |
12748 | .set_property = drm_atomic_helper_plane_set_property, | |
12749 | .atomic_get_property = intel_plane_atomic_get_property, | |
12750 | .atomic_set_property = intel_plane_atomic_set_property, | |
12751 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
12752 | .atomic_destroy_state = intel_plane_destroy_state, | |
12753 | }; | |
12754 | ||
b079bd17 | 12755 | static struct intel_plane * |
580503c7 | 12756 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 12757 | { |
fca0ce2a VS |
12758 | struct intel_plane *primary = NULL; |
12759 | struct intel_plane_state *state = NULL; | |
465c120c | 12760 | const uint32_t *intel_primary_formats; |
93ca7e00 | 12761 | unsigned int supported_rotations; |
45e3743a | 12762 | unsigned int num_formats; |
fca0ce2a | 12763 | int ret; |
465c120c MR |
12764 | |
12765 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
12766 | if (!primary) { |
12767 | ret = -ENOMEM; | |
fca0ce2a | 12768 | goto fail; |
b079bd17 | 12769 | } |
465c120c | 12770 | |
8e7d688b | 12771 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
12772 | if (!state) { |
12773 | ret = -ENOMEM; | |
fca0ce2a | 12774 | goto fail; |
b079bd17 VS |
12775 | } |
12776 | ||
8e7d688b | 12777 | primary->base.state = &state->base; |
ea2c67bb | 12778 | |
465c120c MR |
12779 | primary->can_scale = false; |
12780 | primary->max_downscale = 1; | |
580503c7 | 12781 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 12782 | primary->can_scale = true; |
af99ceda | 12783 | state->scaler_id = -1; |
6156a456 | 12784 | } |
465c120c | 12785 | primary->pipe = pipe; |
e3c566df VS |
12786 | /* |
12787 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
12788 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
12789 | */ | |
12790 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
12791 | primary->plane = (enum plane) !pipe; | |
12792 | else | |
12793 | primary->plane = (enum plane) pipe; | |
b14e5848 | 12794 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 12795 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 12796 | primary->check_plane = intel_check_primary_plane; |
465c120c | 12797 | |
580503c7 | 12798 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
12799 | intel_primary_formats = skl_primary_formats; |
12800 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
12801 | |
12802 | primary->update_plane = skylake_update_primary_plane; | |
12803 | primary->disable_plane = skylake_disable_primary_plane; | |
580503c7 | 12804 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
12805 | intel_primary_formats = i965_primary_formats; |
12806 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
12807 | |
12808 | primary->update_plane = i9xx_update_primary_plane; | |
12809 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
12810 | } else { |
12811 | intel_primary_formats = i8xx_primary_formats; | |
12812 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
12813 | |
12814 | primary->update_plane = i9xx_update_primary_plane; | |
12815 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
12816 | } |
12817 | ||
580503c7 VS |
12818 | if (INTEL_GEN(dev_priv) >= 9) |
12819 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
12820 | 0, &intel_plane_funcs, | |
38573dc1 VS |
12821 | intel_primary_formats, num_formats, |
12822 | DRM_PLANE_TYPE_PRIMARY, | |
12823 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 12824 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
12825 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
12826 | 0, &intel_plane_funcs, | |
38573dc1 VS |
12827 | intel_primary_formats, num_formats, |
12828 | DRM_PLANE_TYPE_PRIMARY, | |
12829 | "primary %c", pipe_name(pipe)); | |
12830 | else | |
580503c7 VS |
12831 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
12832 | 0, &intel_plane_funcs, | |
38573dc1 VS |
12833 | intel_primary_formats, num_formats, |
12834 | DRM_PLANE_TYPE_PRIMARY, | |
12835 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
12836 | if (ret) |
12837 | goto fail; | |
48404c1e | 12838 | |
5481e27f | 12839 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 | 12840 | supported_rotations = |
c2c446ad RF |
12841 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | |
12842 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; | |
4ea7be2b VS |
12843 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
12844 | supported_rotations = | |
c2c446ad RF |
12845 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | |
12846 | DRM_MODE_REFLECT_X; | |
5481e27f | 12847 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 | 12848 | supported_rotations = |
c2c446ad | 12849 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; |
93ca7e00 | 12850 | } else { |
c2c446ad | 12851 | supported_rotations = DRM_MODE_ROTATE_0; |
93ca7e00 VS |
12852 | } |
12853 | ||
5481e27f | 12854 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 12855 | drm_plane_create_rotation_property(&primary->base, |
c2c446ad | 12856 | DRM_MODE_ROTATE_0, |
93ca7e00 | 12857 | supported_rotations); |
48404c1e | 12858 | |
ea2c67bb MR |
12859 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
12860 | ||
b079bd17 | 12861 | return primary; |
fca0ce2a VS |
12862 | |
12863 | fail: | |
12864 | kfree(state); | |
12865 | kfree(primary); | |
12866 | ||
b079bd17 | 12867 | return ERR_PTR(ret); |
465c120c MR |
12868 | } |
12869 | ||
b079bd17 | 12870 | static struct intel_plane * |
b2d03b0d VS |
12871 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, |
12872 | enum pipe pipe) | |
3d7d6510 | 12873 | { |
fca0ce2a VS |
12874 | struct intel_plane *cursor = NULL; |
12875 | struct intel_plane_state *state = NULL; | |
12876 | int ret; | |
3d7d6510 MR |
12877 | |
12878 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
12879 | if (!cursor) { |
12880 | ret = -ENOMEM; | |
fca0ce2a | 12881 | goto fail; |
b079bd17 | 12882 | } |
3d7d6510 | 12883 | |
8e7d688b | 12884 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
12885 | if (!state) { |
12886 | ret = -ENOMEM; | |
fca0ce2a | 12887 | goto fail; |
b079bd17 VS |
12888 | } |
12889 | ||
8e7d688b | 12890 | cursor->base.state = &state->base; |
ea2c67bb | 12891 | |
3d7d6510 MR |
12892 | cursor->can_scale = false; |
12893 | cursor->max_downscale = 1; | |
12894 | cursor->pipe = pipe; | |
12895 | cursor->plane = pipe; | |
b14e5848 | 12896 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 12897 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
b2d03b0d VS |
12898 | |
12899 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { | |
12900 | cursor->update_plane = i845_update_cursor; | |
12901 | cursor->disable_plane = i845_disable_cursor; | |
659056f2 | 12902 | cursor->check_plane = i845_check_cursor; |
b2d03b0d VS |
12903 | } else { |
12904 | cursor->update_plane = i9xx_update_cursor; | |
12905 | cursor->disable_plane = i9xx_disable_cursor; | |
659056f2 | 12906 | cursor->check_plane = i9xx_check_cursor; |
b2d03b0d | 12907 | } |
3d7d6510 | 12908 | |
cd5dcbf1 VS |
12909 | cursor->cursor.base = ~0; |
12910 | cursor->cursor.cntl = ~0; | |
024faac7 VS |
12911 | |
12912 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) | |
12913 | cursor->cursor.size = ~0; | |
3d7d6510 | 12914 | |
580503c7 | 12915 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
f79f2692 | 12916 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
12917 | intel_cursor_formats, |
12918 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
12919 | DRM_PLANE_TYPE_CURSOR, |
12920 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
12921 | if (ret) |
12922 | goto fail; | |
4398ad45 | 12923 | |
5481e27f | 12924 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 12925 | drm_plane_create_rotation_property(&cursor->base, |
c2c446ad RF |
12926 | DRM_MODE_ROTATE_0, |
12927 | DRM_MODE_ROTATE_0 | | |
12928 | DRM_MODE_ROTATE_180); | |
4398ad45 | 12929 | |
580503c7 | 12930 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
12931 | state->scaler_id = -1; |
12932 | ||
ea2c67bb MR |
12933 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
12934 | ||
b079bd17 | 12935 | return cursor; |
fca0ce2a VS |
12936 | |
12937 | fail: | |
12938 | kfree(state); | |
12939 | kfree(cursor); | |
12940 | ||
b079bd17 | 12941 | return ERR_PTR(ret); |
3d7d6510 MR |
12942 | } |
12943 | ||
1c74eeaf NM |
12944 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
12945 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 12946 | { |
65edccce VS |
12947 | struct intel_crtc_scaler_state *scaler_state = |
12948 | &crtc_state->scaler_state; | |
1c74eeaf | 12949 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
549e2bfb | 12950 | int i; |
549e2bfb | 12951 | |
1c74eeaf NM |
12952 | crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; |
12953 | if (!crtc->num_scalers) | |
12954 | return; | |
12955 | ||
65edccce VS |
12956 | for (i = 0; i < crtc->num_scalers; i++) { |
12957 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
12958 | ||
12959 | scaler->in_use = 0; | |
12960 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
12961 | } |
12962 | ||
12963 | scaler_state->scaler_id = -1; | |
12964 | } | |
12965 | ||
5ab0d85b | 12966 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
12967 | { |
12968 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 12969 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
12970 | struct intel_plane *primary = NULL; |
12971 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 12972 | int sprite, ret; |
79e53945 | 12973 | |
955382f3 | 12974 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
12975 | if (!intel_crtc) |
12976 | return -ENOMEM; | |
79e53945 | 12977 | |
f5de6e07 | 12978 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
12979 | if (!crtc_state) { |
12980 | ret = -ENOMEM; | |
f5de6e07 | 12981 | goto fail; |
b079bd17 | 12982 | } |
550acefd ACO |
12983 | intel_crtc->config = crtc_state; |
12984 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 12985 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 12986 | |
580503c7 | 12987 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
12988 | if (IS_ERR(primary)) { |
12989 | ret = PTR_ERR(primary); | |
3d7d6510 | 12990 | goto fail; |
b079bd17 | 12991 | } |
d97d7b48 | 12992 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 12993 | |
a81d6fa0 | 12994 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
12995 | struct intel_plane *plane; |
12996 | ||
580503c7 | 12997 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 12998 | if (IS_ERR(plane)) { |
b079bd17 VS |
12999 | ret = PTR_ERR(plane); |
13000 | goto fail; | |
13001 | } | |
d97d7b48 | 13002 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
13003 | } |
13004 | ||
580503c7 | 13005 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 13006 | if (IS_ERR(cursor)) { |
b079bd17 | 13007 | ret = PTR_ERR(cursor); |
3d7d6510 | 13008 | goto fail; |
b079bd17 | 13009 | } |
d97d7b48 | 13010 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 13011 | |
5ab0d85b | 13012 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
13013 | &primary->base, &cursor->base, |
13014 | &intel_crtc_funcs, | |
4d5d72b7 | 13015 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
13016 | if (ret) |
13017 | goto fail; | |
79e53945 | 13018 | |
80824003 | 13019 | intel_crtc->pipe = pipe; |
e3c566df | 13020 | intel_crtc->plane = primary->plane; |
80824003 | 13021 | |
1c74eeaf NM |
13022 | /* initialize shared scalers */ |
13023 | intel_crtc_init_scalers(intel_crtc, crtc_state); | |
13024 | ||
22fd0fab JB |
13025 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13026 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
13027 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
13028 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 13029 | |
79e53945 | 13030 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13031 | |
8563b1e8 LL |
13032 | intel_color_init(&intel_crtc->base); |
13033 | ||
87b6b101 | 13034 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
13035 | |
13036 | return 0; | |
3d7d6510 MR |
13037 | |
13038 | fail: | |
b079bd17 VS |
13039 | /* |
13040 | * drm_mode_config_cleanup() will free up any | |
13041 | * crtcs/planes already initialized. | |
13042 | */ | |
f5de6e07 | 13043 | kfree(crtc_state); |
3d7d6510 | 13044 | kfree(intel_crtc); |
b079bd17 VS |
13045 | |
13046 | return ret; | |
79e53945 JB |
13047 | } |
13048 | ||
752aa88a JB |
13049 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13050 | { | |
6e9f798d | 13051 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13052 | |
51fd371b | 13053 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13054 | |
51ec53da | 13055 | if (!connector->base.state->crtc) |
752aa88a JB |
13056 | return INVALID_PIPE; |
13057 | ||
51ec53da | 13058 | return to_intel_crtc(connector->base.state->crtc)->pipe; |
752aa88a JB |
13059 | } |
13060 | ||
08d7b3d1 | 13061 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13062 | struct drm_file *file) |
08d7b3d1 | 13063 | { |
08d7b3d1 | 13064 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13065 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13066 | struct intel_crtc *crtc; |
08d7b3d1 | 13067 | |
7707e653 | 13068 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 13069 | if (!drmmode_crtc) |
3f2c2057 | 13070 | return -ENOENT; |
08d7b3d1 | 13071 | |
7707e653 | 13072 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13073 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13074 | |
c05422d5 | 13075 | return 0; |
08d7b3d1 CW |
13076 | } |
13077 | ||
66a9278e | 13078 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13079 | { |
66a9278e DV |
13080 | struct drm_device *dev = encoder->base.dev; |
13081 | struct intel_encoder *source_encoder; | |
79e53945 | 13082 | int index_mask = 0; |
79e53945 JB |
13083 | int entry = 0; |
13084 | ||
b2784e15 | 13085 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13086 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13087 | index_mask |= (1 << entry); |
13088 | ||
79e53945 JB |
13089 | entry++; |
13090 | } | |
4ef69c7a | 13091 | |
79e53945 JB |
13092 | return index_mask; |
13093 | } | |
13094 | ||
646d5772 | 13095 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 13096 | { |
646d5772 | 13097 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
13098 | return false; |
13099 | ||
13100 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13101 | return false; | |
13102 | ||
5db94019 | 13103 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13104 | return false; |
13105 | ||
13106 | return true; | |
13107 | } | |
13108 | ||
6315b5d3 | 13109 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 13110 | { |
6315b5d3 | 13111 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
13112 | return false; |
13113 | ||
50a0bc90 | 13114 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
13115 | return false; |
13116 | ||
920a14b2 | 13117 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
13118 | return false; |
13119 | ||
4f8036a2 TU |
13120 | if (HAS_PCH_LPT_H(dev_priv) && |
13121 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
13122 | return false; |
13123 | ||
70ac54d0 | 13124 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 13125 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
13126 | return false; |
13127 | ||
e4abb733 | 13128 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
13129 | return false; |
13130 | ||
13131 | return true; | |
13132 | } | |
13133 | ||
8090ba8c ID |
13134 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
13135 | { | |
13136 | int pps_num; | |
13137 | int pps_idx; | |
13138 | ||
13139 | if (HAS_DDI(dev_priv)) | |
13140 | return; | |
13141 | /* | |
13142 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
13143 | * everywhere where registers can be write protected. | |
13144 | */ | |
13145 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13146 | pps_num = 2; | |
13147 | else | |
13148 | pps_num = 1; | |
13149 | ||
13150 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
13151 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
13152 | ||
13153 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
13154 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
13155 | } | |
13156 | } | |
13157 | ||
44cb734c ID |
13158 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
13159 | { | |
cc3f90f0 | 13160 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
13161 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
13162 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13163 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
13164 | else | |
13165 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
13166 | |
13167 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
13168 | } |
13169 | ||
c39055b0 | 13170 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 13171 | { |
4ef69c7a | 13172 | struct intel_encoder *encoder; |
cb0953d7 | 13173 | bool dpd_is_edp = false; |
79e53945 | 13174 | |
44cb734c ID |
13175 | intel_pps_init(dev_priv); |
13176 | ||
97a824e1 ID |
13177 | /* |
13178 | * intel_edp_init_connector() depends on this completing first, to | |
13179 | * prevent the registeration of both eDP and LVDS and the incorrect | |
13180 | * sharing of the PPS. | |
13181 | */ | |
c39055b0 | 13182 | intel_lvds_init(dev_priv); |
79e53945 | 13183 | |
6315b5d3 | 13184 | if (intel_crt_present(dev_priv)) |
c39055b0 | 13185 | intel_crt_init(dev_priv); |
cb0953d7 | 13186 | |
cc3f90f0 | 13187 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
13188 | /* |
13189 | * FIXME: Broxton doesn't support port detection via the | |
13190 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13191 | * detect the ports. | |
13192 | */ | |
c39055b0 ACO |
13193 | intel_ddi_init(dev_priv, PORT_A); |
13194 | intel_ddi_init(dev_priv, PORT_B); | |
13195 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 13196 | |
c39055b0 | 13197 | intel_dsi_init(dev_priv); |
4f8036a2 | 13198 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
13199 | int found; |
13200 | ||
de31facd JB |
13201 | /* |
13202 | * Haswell uses DDI functions to detect digital outputs. | |
13203 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13204 | * it's there. | |
13205 | */ | |
77179400 | 13206 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 13207 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 13208 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 13209 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
13210 | |
13211 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13212 | * register */ | |
13213 | found = I915_READ(SFUSE_STRAP); | |
13214 | ||
13215 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 13216 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 13217 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 13218 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 13219 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 13220 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
13221 | /* |
13222 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
13223 | */ | |
b976dc53 | 13224 | if (IS_GEN9_BC(dev_priv) && |
2800e4c2 RV |
13225 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
13226 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
13227 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 13228 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 13229 | |
6e266956 | 13230 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 13231 | int found; |
dd11bc10 | 13232 | dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); |
270b3042 | 13233 | |
646d5772 | 13234 | if (has_edp_a(dev_priv)) |
c39055b0 | 13235 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 13236 | |
dc0fa718 | 13237 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13238 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 13239 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 13240 | if (!found) |
c39055b0 | 13241 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 13242 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 13243 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13244 | } |
13245 | ||
dc0fa718 | 13246 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 13247 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 13248 | |
dc0fa718 | 13249 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 13250 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 13251 | |
5eb08b69 | 13252 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 13253 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 13254 | |
270b3042 | 13255 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 13256 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 13257 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 13258 | bool has_edp, has_port; |
457c52d8 | 13259 | |
e17ac6db VS |
13260 | /* |
13261 | * The DP_DETECTED bit is the latched state of the DDC | |
13262 | * SDA pin at boot. However since eDP doesn't require DDC | |
13263 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13264 | * eDP ports may have been muxed to an alternate function. | |
13265 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13266 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13267 | * detect eDP ports. | |
22f35042 VS |
13268 | * |
13269 | * Sadly the straps seem to be missing sometimes even for HDMI | |
13270 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
13271 | * and VBT for the presence of the port. Additionally we can't | |
13272 | * trust the port type the VBT declares as we've seen at least | |
13273 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 13274 | */ |
dd11bc10 | 13275 | has_edp = intel_dp_is_edp(dev_priv, PORT_B); |
22f35042 VS |
13276 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
13277 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 13278 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 13279 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13280 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 13281 | |
dd11bc10 | 13282 | has_edp = intel_dp_is_edp(dev_priv, PORT_C); |
22f35042 VS |
13283 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
13284 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 13285 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 13286 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13287 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 13288 | |
920a14b2 | 13289 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
13290 | /* |
13291 | * eDP not supported on port D, | |
13292 | * so no need to worry about it | |
13293 | */ | |
13294 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
13295 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 13296 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 13297 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 13298 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
13299 | } |
13300 | ||
c39055b0 | 13301 | intel_dsi_init(dev_priv); |
5db94019 | 13302 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 13303 | bool found = false; |
7d57382e | 13304 | |
e2debe91 | 13305 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13306 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 13307 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 13308 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 13309 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 13310 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13311 | } |
27185ae1 | 13312 | |
9beb5fea | 13313 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 13314 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 13315 | } |
13520b05 KH |
13316 | |
13317 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13318 | |
e2debe91 | 13319 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13320 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 13321 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 13322 | } |
27185ae1 | 13323 | |
e2debe91 | 13324 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13325 | |
9beb5fea | 13326 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 13327 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 13328 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13329 | } |
9beb5fea | 13330 | if (IS_G4X(dev_priv)) |
c39055b0 | 13331 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 13332 | } |
27185ae1 | 13333 | |
9beb5fea | 13334 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 13335 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 13336 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 13337 | intel_dvo_init(dev_priv); |
79e53945 | 13338 | |
56b857a5 | 13339 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 13340 | intel_tv_init(dev_priv); |
79e53945 | 13341 | |
c39055b0 | 13342 | intel_psr_init(dev_priv); |
7c8f8a70 | 13343 | |
c39055b0 | 13344 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
13345 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13346 | encoder->base.possible_clones = | |
66a9278e | 13347 | intel_encoder_clones(encoder); |
79e53945 | 13348 | } |
47356eb6 | 13349 | |
c39055b0 | 13350 | intel_init_pch_refclk(dev_priv); |
270b3042 | 13351 | |
c39055b0 | 13352 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
13353 | } |
13354 | ||
13355 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13356 | { | |
13357 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 13358 | |
ef2d633e | 13359 | drm_framebuffer_cleanup(fb); |
70001cd2 | 13360 | |
dd689287 CW |
13361 | i915_gem_object_lock(intel_fb->obj); |
13362 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
13363 | i915_gem_object_unlock(intel_fb->obj); | |
13364 | ||
f8c417cd | 13365 | i915_gem_object_put(intel_fb->obj); |
70001cd2 | 13366 | |
79e53945 JB |
13367 | kfree(intel_fb); |
13368 | } | |
13369 | ||
13370 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13371 | struct drm_file *file, |
79e53945 JB |
13372 | unsigned int *handle) |
13373 | { | |
13374 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13375 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13376 | |
cc917ab4 CW |
13377 | if (obj->userptr.mm) { |
13378 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
13379 | return -EINVAL; | |
13380 | } | |
13381 | ||
05394f39 | 13382 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13383 | } |
13384 | ||
86c98588 RV |
13385 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
13386 | struct drm_file *file, | |
13387 | unsigned flags, unsigned color, | |
13388 | struct drm_clip_rect *clips, | |
13389 | unsigned num_clips) | |
13390 | { | |
5a97bcc6 | 13391 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 13392 | |
5a97bcc6 | 13393 | i915_gem_object_flush_if_display(obj); |
d59b21ec | 13394 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
86c98588 RV |
13395 | |
13396 | return 0; | |
13397 | } | |
13398 | ||
79e53945 JB |
13399 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
13400 | .destroy = intel_user_framebuffer_destroy, | |
13401 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 13402 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
13403 | }; |
13404 | ||
b321803d | 13405 | static |
920a14b2 TU |
13406 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
13407 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 13408 | { |
24dbf51a | 13409 | u32 gen = INTEL_GEN(dev_priv); |
b321803d DL |
13410 | |
13411 | if (gen >= 9) { | |
ac484963 VS |
13412 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
13413 | ||
b321803d DL |
13414 | /* "The stride in bytes must not exceed the of the size of 8K |
13415 | * pixels and 32K bytes." | |
13416 | */ | |
ac484963 | 13417 | return min(8192 * cpp, 32768); |
6401c37d | 13418 | } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) { |
b321803d DL |
13419 | return 32*1024; |
13420 | } else if (gen >= 4) { | |
13421 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13422 | return 16*1024; | |
13423 | else | |
13424 | return 32*1024; | |
13425 | } else if (gen >= 3) { | |
13426 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13427 | return 8*1024; | |
13428 | else | |
13429 | return 16*1024; | |
13430 | } else { | |
13431 | /* XXX DSPC is limited to 4k tiled */ | |
13432 | return 8*1024; | |
13433 | } | |
13434 | } | |
13435 | ||
24dbf51a CW |
13436 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
13437 | struct drm_i915_gem_object *obj, | |
13438 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 13439 | { |
24dbf51a | 13440 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
b3c11ac2 | 13441 | struct drm_format_name_buf format_name; |
dd689287 CW |
13442 | u32 pitch_limit, stride_alignment; |
13443 | unsigned int tiling, stride; | |
24dbf51a | 13444 | int ret = -EINVAL; |
79e53945 | 13445 | |
dd689287 CW |
13446 | i915_gem_object_lock(obj); |
13447 | obj->framebuffer_references++; | |
13448 | tiling = i915_gem_object_get_tiling(obj); | |
13449 | stride = i915_gem_object_get_stride(obj); | |
13450 | i915_gem_object_unlock(obj); | |
dd4916c5 | 13451 | |
2a80eada | 13452 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
13453 | /* |
13454 | * If there's a fence, enforce that | |
13455 | * the fb modifier and tiling mode match. | |
13456 | */ | |
13457 | if (tiling != I915_TILING_NONE && | |
13458 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13459 | DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n"); |
24dbf51a | 13460 | goto err; |
2a80eada DV |
13461 | } |
13462 | } else { | |
c2ff7370 | 13463 | if (tiling == I915_TILING_X) { |
2a80eada | 13464 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 13465 | } else if (tiling == I915_TILING_Y) { |
144cc143 | 13466 | DRM_DEBUG_KMS("No Y tiling for legacy addfb\n"); |
24dbf51a | 13467 | goto err; |
2a80eada DV |
13468 | } |
13469 | } | |
13470 | ||
9a8f0a12 TU |
13471 | /* Passed in modifier sanity checking. */ |
13472 | switch (mode_cmd->modifier[0]) { | |
13473 | case I915_FORMAT_MOD_Y_TILED: | |
13474 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 13475 | if (INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
13476 | DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", |
13477 | mode_cmd->modifier[0]); | |
24dbf51a | 13478 | goto err; |
9a8f0a12 | 13479 | } |
2f075565 | 13480 | case DRM_FORMAT_MOD_LINEAR: |
9a8f0a12 TU |
13481 | case I915_FORMAT_MOD_X_TILED: |
13482 | break; | |
13483 | default: | |
144cc143 VS |
13484 | DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n", |
13485 | mode_cmd->modifier[0]); | |
24dbf51a | 13486 | goto err; |
c16ed4be | 13487 | } |
57cd6508 | 13488 | |
c2ff7370 VS |
13489 | /* |
13490 | * gen2/3 display engine uses the fence if present, | |
13491 | * so the tiling mode must match the fb modifier exactly. | |
13492 | */ | |
13493 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
13494 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13495 | DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); |
9aceb5c1 | 13496 | goto err; |
c2ff7370 VS |
13497 | } |
13498 | ||
920a14b2 | 13499 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 13500 | mode_cmd->pixel_format); |
a35cdaa0 | 13501 | if (mode_cmd->pitches[0] > pitch_limit) { |
144cc143 | 13502 | DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n", |
2f075565 | 13503 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? |
144cc143 VS |
13504 | "tiled" : "linear", |
13505 | mode_cmd->pitches[0], pitch_limit); | |
24dbf51a | 13506 | goto err; |
c16ed4be | 13507 | } |
5d7bd705 | 13508 | |
c2ff7370 VS |
13509 | /* |
13510 | * If there's a fence, enforce that | |
13511 | * the fb pitch and fence stride match. | |
13512 | */ | |
144cc143 VS |
13513 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
13514 | DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n", | |
13515 | mode_cmd->pitches[0], stride); | |
24dbf51a | 13516 | goto err; |
c16ed4be | 13517 | } |
5d7bd705 | 13518 | |
57779d06 | 13519 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13520 | switch (mode_cmd->pixel_format) { |
57779d06 | 13521 | case DRM_FORMAT_C8: |
04b3924d VS |
13522 | case DRM_FORMAT_RGB565: |
13523 | case DRM_FORMAT_XRGB8888: | |
13524 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13525 | break; |
13526 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 13527 | if (INTEL_GEN(dev_priv) > 3) { |
144cc143 VS |
13528 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13529 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13530 | goto err; |
c16ed4be | 13531 | } |
57779d06 | 13532 | break; |
57779d06 | 13533 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 13534 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 13535 | INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
13536 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13537 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13538 | goto err; |
6c0fd451 DL |
13539 | } |
13540 | break; | |
13541 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 13542 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 13543 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 13544 | if (INTEL_GEN(dev_priv) < 4) { |
144cc143 VS |
13545 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13546 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13547 | goto err; |
c16ed4be | 13548 | } |
b5626747 | 13549 | break; |
7531208b | 13550 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 13551 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
144cc143 VS |
13552 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13553 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13554 | goto err; |
7531208b DL |
13555 | } |
13556 | break; | |
04b3924d VS |
13557 | case DRM_FORMAT_YUYV: |
13558 | case DRM_FORMAT_UYVY: | |
13559 | case DRM_FORMAT_YVYU: | |
13560 | case DRM_FORMAT_VYUY: | |
ab33081a | 13561 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
144cc143 VS |
13562 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13563 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13564 | goto err; |
c16ed4be | 13565 | } |
57cd6508 CW |
13566 | break; |
13567 | default: | |
144cc143 VS |
13568 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13569 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13570 | goto err; |
57cd6508 CW |
13571 | } |
13572 | ||
90f9a336 VS |
13573 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
13574 | if (mode_cmd->offsets[0] != 0) | |
24dbf51a | 13575 | goto err; |
90f9a336 | 13576 | |
24dbf51a CW |
13577 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, |
13578 | &intel_fb->base, mode_cmd); | |
d88c4afd VS |
13579 | |
13580 | stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0); | |
13581 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
144cc143 VS |
13582 | DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n", |
13583 | mode_cmd->pitches[0], stride_alignment); | |
d88c4afd VS |
13584 | goto err; |
13585 | } | |
13586 | ||
c7d73f6a DV |
13587 | intel_fb->obj = obj; |
13588 | ||
6687c906 VS |
13589 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
13590 | if (ret) | |
9aceb5c1 | 13591 | goto err; |
2d7a215f | 13592 | |
24dbf51a CW |
13593 | ret = drm_framebuffer_init(obj->base.dev, |
13594 | &intel_fb->base, | |
13595 | &intel_fb_funcs); | |
79e53945 JB |
13596 | if (ret) { |
13597 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
24dbf51a | 13598 | goto err; |
79e53945 JB |
13599 | } |
13600 | ||
79e53945 | 13601 | return 0; |
24dbf51a CW |
13602 | |
13603 | err: | |
dd689287 CW |
13604 | i915_gem_object_lock(obj); |
13605 | obj->framebuffer_references--; | |
13606 | i915_gem_object_unlock(obj); | |
24dbf51a | 13607 | return ret; |
79e53945 JB |
13608 | } |
13609 | ||
79e53945 JB |
13610 | static struct drm_framebuffer * |
13611 | intel_user_framebuffer_create(struct drm_device *dev, | |
13612 | struct drm_file *filp, | |
1eb83451 | 13613 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 13614 | { |
dcb1394e | 13615 | struct drm_framebuffer *fb; |
05394f39 | 13616 | struct drm_i915_gem_object *obj; |
76dc3769 | 13617 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 13618 | |
03ac0642 CW |
13619 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
13620 | if (!obj) | |
cce13ff7 | 13621 | return ERR_PTR(-ENOENT); |
79e53945 | 13622 | |
24dbf51a | 13623 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 13624 | if (IS_ERR(fb)) |
f0cd5182 | 13625 | i915_gem_object_put(obj); |
dcb1394e LW |
13626 | |
13627 | return fb; | |
79e53945 JB |
13628 | } |
13629 | ||
778e23a9 CW |
13630 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
13631 | { | |
13632 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13633 | ||
13634 | drm_atomic_state_default_release(state); | |
13635 | ||
13636 | i915_sw_fence_fini(&intel_state->commit_ready); | |
13637 | ||
13638 | kfree(state); | |
13639 | } | |
13640 | ||
79e53945 | 13641 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 13642 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 13643 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
13644 | .atomic_check = intel_atomic_check, |
13645 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
13646 | .atomic_state_alloc = intel_atomic_state_alloc, |
13647 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 13648 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
13649 | }; |
13650 | ||
88212941 ID |
13651 | /** |
13652 | * intel_init_display_hooks - initialize the display modesetting hooks | |
13653 | * @dev_priv: device private | |
13654 | */ | |
13655 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 13656 | { |
7ff89ca2 VS |
13657 | intel_init_cdclk_hooks(dev_priv); |
13658 | ||
88212941 | 13659 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 13660 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
13661 | dev_priv->display.get_initial_plane_config = |
13662 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
13663 | dev_priv->display.crtc_compute_clock = |
13664 | haswell_crtc_compute_clock; | |
13665 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
13666 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 13667 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 13668 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
13669 | dev_priv->display.get_initial_plane_config = |
13670 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
13671 | dev_priv->display.crtc_compute_clock = |
13672 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
13673 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
13674 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 13675 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 13676 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
13677 | dev_priv->display.get_initial_plane_config = |
13678 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
13679 | dev_priv->display.crtc_compute_clock = |
13680 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
13681 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
13682 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 13683 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 13684 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
13685 | dev_priv->display.get_initial_plane_config = |
13686 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
13687 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
13688 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
13689 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
13690 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
13691 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
13692 | dev_priv->display.get_initial_plane_config = | |
13693 | i9xx_get_initial_plane_config; | |
13694 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
13695 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
13696 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
13697 | } else if (IS_G4X(dev_priv)) { |
13698 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
13699 | dev_priv->display.get_initial_plane_config = | |
13700 | i9xx_get_initial_plane_config; | |
13701 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
13702 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
13703 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
13704 | } else if (IS_PINEVIEW(dev_priv)) { |
13705 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
13706 | dev_priv->display.get_initial_plane_config = | |
13707 | i9xx_get_initial_plane_config; | |
13708 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
13709 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
13710 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 13711 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 13712 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
13713 | dev_priv->display.get_initial_plane_config = |
13714 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13715 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
13716 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
13717 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
13718 | } else { |
13719 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
13720 | dev_priv->display.get_initial_plane_config = | |
13721 | i9xx_get_initial_plane_config; | |
13722 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
13723 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
13724 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 13725 | } |
e70236a8 | 13726 | |
88212941 | 13727 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 13728 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 13729 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 13730 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 13731 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
13732 | /* FIXME: detect B0+ stepping and use auto training */ |
13733 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 13734 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 13735 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
13736 | } |
13737 | ||
27082493 L |
13738 | if (dev_priv->info.gen >= 9) |
13739 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
13740 | else | |
13741 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
e70236a8 JB |
13742 | } |
13743 | ||
435793df KP |
13744 | /* |
13745 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
13746 | */ | |
13747 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
13748 | { | |
fac5e23e | 13749 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 13750 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 13751 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
13752 | } |
13753 | ||
4dca20ef | 13754 | /* |
5a15ab5b CE |
13755 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
13756 | * brightness value | |
4dca20ef CE |
13757 | */ |
13758 | static void quirk_invert_brightness(struct drm_device *dev) | |
13759 | { | |
fac5e23e | 13760 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 13761 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 13762 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
13763 | } |
13764 | ||
9c72cc6f SD |
13765 | /* Some VBT's incorrectly indicate no backlight is present */ |
13766 | static void quirk_backlight_present(struct drm_device *dev) | |
13767 | { | |
fac5e23e | 13768 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
13769 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
13770 | DRM_INFO("applying backlight present quirk\n"); | |
13771 | } | |
13772 | ||
c99a259b MN |
13773 | /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms |
13774 | * which is 300 ms greater than eDP spec T12 min. | |
13775 | */ | |
13776 | static void quirk_increase_t12_delay(struct drm_device *dev) | |
13777 | { | |
13778 | struct drm_i915_private *dev_priv = to_i915(dev); | |
13779 | ||
13780 | dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY; | |
13781 | DRM_INFO("Applying T12 delay quirk\n"); | |
13782 | } | |
13783 | ||
b690e96c JB |
13784 | struct intel_quirk { |
13785 | int device; | |
13786 | int subsystem_vendor; | |
13787 | int subsystem_device; | |
13788 | void (*hook)(struct drm_device *dev); | |
13789 | }; | |
13790 | ||
5f85f176 EE |
13791 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
13792 | struct intel_dmi_quirk { | |
13793 | void (*hook)(struct drm_device *dev); | |
13794 | const struct dmi_system_id (*dmi_id_list)[]; | |
13795 | }; | |
13796 | ||
13797 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
13798 | { | |
13799 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
13800 | return 1; | |
13801 | } | |
13802 | ||
13803 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
13804 | { | |
13805 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
13806 | { | |
13807 | .callback = intel_dmi_reverse_brightness, | |
13808 | .ident = "NCR Corporation", | |
13809 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
13810 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
13811 | }, | |
13812 | }, | |
13813 | { } /* terminating entry */ | |
13814 | }, | |
13815 | .hook = quirk_invert_brightness, | |
13816 | }, | |
13817 | }; | |
13818 | ||
c43b5634 | 13819 | static struct intel_quirk intel_quirks[] = { |
435793df KP |
13820 | /* Lenovo U160 cannot use SSC on LVDS */ |
13821 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
13822 | |
13823 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
13824 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 13825 | |
be505f64 AH |
13826 | /* Acer Aspire 5734Z must invert backlight brightness */ |
13827 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
13828 | ||
13829 | /* Acer/eMachines G725 */ | |
13830 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
13831 | ||
13832 | /* Acer/eMachines e725 */ | |
13833 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
13834 | ||
13835 | /* Acer/Packard Bell NCL20 */ | |
13836 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
13837 | ||
13838 | /* Acer Aspire 4736Z */ | |
13839 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
13840 | |
13841 | /* Acer Aspire 5336 */ | |
13842 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
13843 | |
13844 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
13845 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 13846 | |
dfb3d47b SD |
13847 | /* Acer C720 Chromebook (Core i3 4005U) */ |
13848 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
13849 | ||
b2a9601c | 13850 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
13851 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
13852 | ||
1b9448b0 JN |
13853 | /* Apple Macbook 4,1 */ |
13854 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
13855 | ||
d4967d8c SD |
13856 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
13857 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
13858 | |
13859 | /* HP Chromebook 14 (Celeron 2955U) */ | |
13860 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
13861 | |
13862 | /* Dell Chromebook 11 */ | |
13863 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
13864 | |
13865 | /* Dell Chromebook 11 (2015 version) */ | |
13866 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
c99a259b MN |
13867 | |
13868 | /* Toshiba Satellite P50-C-18C */ | |
13869 | { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay }, | |
b690e96c JB |
13870 | }; |
13871 | ||
13872 | static void intel_init_quirks(struct drm_device *dev) | |
13873 | { | |
13874 | struct pci_dev *d = dev->pdev; | |
13875 | int i; | |
13876 | ||
13877 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
13878 | struct intel_quirk *q = &intel_quirks[i]; | |
13879 | ||
13880 | if (d->device == q->device && | |
13881 | (d->subsystem_vendor == q->subsystem_vendor || | |
13882 | q->subsystem_vendor == PCI_ANY_ID) && | |
13883 | (d->subsystem_device == q->subsystem_device || | |
13884 | q->subsystem_device == PCI_ANY_ID)) | |
13885 | q->hook(dev); | |
13886 | } | |
5f85f176 EE |
13887 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
13888 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
13889 | intel_dmi_quirks[i].hook(dev); | |
13890 | } | |
b690e96c JB |
13891 | } |
13892 | ||
9cce37f4 | 13893 | /* Disable the VGA plane that we never use */ |
29b74b7f | 13894 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 13895 | { |
52a05c30 | 13896 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 13897 | u8 sr1; |
920a14b2 | 13898 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 13899 | |
2b37c616 | 13900 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 13901 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 13902 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
13903 | sr1 = inb(VGA_SR_DATA); |
13904 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 13905 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
13906 | udelay(300); |
13907 | ||
01f5a626 | 13908 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
13909 | POSTING_READ(vga_reg); |
13910 | } | |
13911 | ||
f817586c DV |
13912 | void intel_modeset_init_hw(struct drm_device *dev) |
13913 | { | |
fac5e23e | 13914 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 13915 | |
4c75b940 | 13916 | intel_update_cdclk(dev_priv); |
bb0f4aab | 13917 | dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; |
1a617b77 | 13918 | |
46f16e63 | 13919 | intel_init_clock_gating(dev_priv); |
f817586c DV |
13920 | } |
13921 | ||
d93c0372 MR |
13922 | /* |
13923 | * Calculate what we think the watermarks should be for the state we've read | |
13924 | * out of the hardware and then immediately program those watermarks so that | |
13925 | * we ensure the hardware settings match our internal state. | |
13926 | * | |
13927 | * We can calculate what we think WM's should be by creating a duplicate of the | |
13928 | * current state (which was constructed during hardware readout) and running it | |
13929 | * through the atomic check code to calculate new watermark values in the | |
13930 | * state object. | |
13931 | */ | |
13932 | static void sanitize_watermarks(struct drm_device *dev) | |
13933 | { | |
13934 | struct drm_i915_private *dev_priv = to_i915(dev); | |
13935 | struct drm_atomic_state *state; | |
ccf010fb | 13936 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
13937 | struct drm_crtc *crtc; |
13938 | struct drm_crtc_state *cstate; | |
13939 | struct drm_modeset_acquire_ctx ctx; | |
13940 | int ret; | |
13941 | int i; | |
13942 | ||
13943 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 13944 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
13945 | return; |
13946 | ||
13947 | /* | |
13948 | * We need to hold connection_mutex before calling duplicate_state so | |
13949 | * that the connector loop is protected. | |
13950 | */ | |
13951 | drm_modeset_acquire_init(&ctx, 0); | |
13952 | retry: | |
0cd1262d | 13953 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
13954 | if (ret == -EDEADLK) { |
13955 | drm_modeset_backoff(&ctx); | |
13956 | goto retry; | |
13957 | } else if (WARN_ON(ret)) { | |
0cd1262d | 13958 | goto fail; |
d93c0372 MR |
13959 | } |
13960 | ||
13961 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
13962 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 13963 | goto fail; |
d93c0372 | 13964 | |
ccf010fb ML |
13965 | intel_state = to_intel_atomic_state(state); |
13966 | ||
ed4a6a7c MR |
13967 | /* |
13968 | * Hardware readout is the only time we don't want to calculate | |
13969 | * intermediate watermarks (since we don't trust the current | |
13970 | * watermarks). | |
13971 | */ | |
602ae835 VS |
13972 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
13973 | intel_state->skip_intermediate_wm = true; | |
ed4a6a7c | 13974 | |
d93c0372 MR |
13975 | ret = intel_atomic_check(dev, state); |
13976 | if (ret) { | |
13977 | /* | |
13978 | * If we fail here, it means that the hardware appears to be | |
13979 | * programmed in a way that shouldn't be possible, given our | |
13980 | * understanding of watermark requirements. This might mean a | |
13981 | * mistake in the hardware readout code or a mistake in the | |
13982 | * watermark calculations for a given platform. Raise a WARN | |
13983 | * so that this is noticeable. | |
13984 | * | |
13985 | * If this actually happens, we'll have to just leave the | |
13986 | * BIOS-programmed watermarks untouched and hope for the best. | |
13987 | */ | |
13988 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 13989 | goto put_state; |
d93c0372 MR |
13990 | } |
13991 | ||
13992 | /* Write calculated watermark values back */ | |
aa5e9b47 | 13993 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
d93c0372 MR |
13994 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); |
13995 | ||
ed4a6a7c | 13996 | cs->wm.need_postvbl_update = true; |
ccf010fb | 13997 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
13998 | } |
13999 | ||
b9a1b717 | 14000 | put_state: |
0853695c | 14001 | drm_atomic_state_put(state); |
0cd1262d | 14002 | fail: |
d93c0372 MR |
14003 | drm_modeset_drop_locks(&ctx); |
14004 | drm_modeset_acquire_fini(&ctx); | |
14005 | } | |
14006 | ||
b079bd17 | 14007 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 14008 | { |
72e96d64 JL |
14009 | struct drm_i915_private *dev_priv = to_i915(dev); |
14010 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 14011 | enum pipe pipe; |
46f297fb | 14012 | struct intel_crtc *crtc; |
79e53945 JB |
14013 | |
14014 | drm_mode_config_init(dev); | |
14015 | ||
14016 | dev->mode_config.min_width = 0; | |
14017 | dev->mode_config.min_height = 0; | |
14018 | ||
019d96cb DA |
14019 | dev->mode_config.preferred_depth = 24; |
14020 | dev->mode_config.prefer_shadow = 1; | |
14021 | ||
25bab385 TU |
14022 | dev->mode_config.allow_fb_modifiers = true; |
14023 | ||
e6ecefaa | 14024 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14025 | |
400c19d9 | 14026 | init_llist_head(&dev_priv->atomic_helper.free_list); |
eb955eee | 14027 | INIT_WORK(&dev_priv->atomic_helper.free_work, |
ba318c61 | 14028 | intel_atomic_helper_free_state_worker); |
eb955eee | 14029 | |
b690e96c JB |
14030 | intel_init_quirks(dev); |
14031 | ||
62d75df7 | 14032 | intel_init_pm(dev_priv); |
1fa61106 | 14033 | |
b7f05d4a | 14034 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 14035 | return 0; |
e3c74757 | 14036 | |
69f92f67 LW |
14037 | /* |
14038 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14039 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14040 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14041 | * indicates as much. | |
14042 | */ | |
6e266956 | 14043 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
14044 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
14045 | DREF_SSC1_ENABLE); | |
14046 | ||
14047 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14048 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14049 | bios_lvds_use_ssc ? "en" : "dis", | |
14050 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14051 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14052 | } | |
14053 | } | |
14054 | ||
5db94019 | 14055 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
14056 | dev->mode_config.max_width = 2048; |
14057 | dev->mode_config.max_height = 2048; | |
5db94019 | 14058 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
14059 | dev->mode_config.max_width = 4096; |
14060 | dev->mode_config.max_height = 4096; | |
79e53945 | 14061 | } else { |
a6c45cf0 CW |
14062 | dev->mode_config.max_width = 8192; |
14063 | dev->mode_config.max_height = 8192; | |
79e53945 | 14064 | } |
068be561 | 14065 | |
2a307c2e JN |
14066 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
14067 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 14068 | dev->mode_config.cursor_height = 1023; |
5db94019 | 14069 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
14070 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14071 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14072 | } else { | |
14073 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14074 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14075 | } | |
14076 | ||
72e96d64 | 14077 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 14078 | |
28c97730 | 14079 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
14080 | INTEL_INFO(dev_priv)->num_pipes, |
14081 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14082 | |
055e393f | 14083 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
14084 | int ret; |
14085 | ||
5ab0d85b | 14086 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
14087 | if (ret) { |
14088 | drm_mode_config_cleanup(dev); | |
14089 | return ret; | |
14090 | } | |
79e53945 JB |
14091 | } |
14092 | ||
e72f9fbf | 14093 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14094 | |
5be6e334 VS |
14095 | intel_update_czclk(dev_priv); |
14096 | intel_modeset_init_hw(dev); | |
14097 | ||
b2045352 | 14098 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 14099 | intel_update_max_cdclk(dev_priv); |
b2045352 | 14100 | |
9cce37f4 | 14101 | /* Just disable it once at startup */ |
29b74b7f | 14102 | i915_disable_vga(dev_priv); |
c39055b0 | 14103 | intel_setup_outputs(dev_priv); |
11be49eb | 14104 | |
6e9f798d | 14105 | drm_modeset_lock_all(dev); |
aecd36b8 | 14106 | intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); |
6e9f798d | 14107 | drm_modeset_unlock_all(dev); |
46f297fb | 14108 | |
d3fcc808 | 14109 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14110 | struct intel_initial_plane_config plane_config = {}; |
14111 | ||
46f297fb JB |
14112 | if (!crtc->active) |
14113 | continue; | |
14114 | ||
46f297fb | 14115 | /* |
46f297fb JB |
14116 | * Note that reserving the BIOS fb up front prevents us |
14117 | * from stuffing other stolen allocations like the ring | |
14118 | * on top. This prevents some ugliness at boot time, and | |
14119 | * can even allow for smooth boot transitions if the BIOS | |
14120 | * fb is large enough for the active pipe configuration. | |
14121 | */ | |
eeebeac5 ML |
14122 | dev_priv->display.get_initial_plane_config(crtc, |
14123 | &plane_config); | |
14124 | ||
14125 | /* | |
14126 | * If the fb is shared between multiple heads, we'll | |
14127 | * just get the first one. | |
14128 | */ | |
14129 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 14130 | } |
d93c0372 MR |
14131 | |
14132 | /* | |
14133 | * Make sure hardware watermarks really match the state we read out. | |
14134 | * Note that we need to do this after reconstructing the BIOS fb's | |
14135 | * since the watermark calculation done here will use pstate->fb. | |
14136 | */ | |
602ae835 VS |
14137 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14138 | sanitize_watermarks(dev); | |
b079bd17 VS |
14139 | |
14140 | return 0; | |
2c7111db CW |
14141 | } |
14142 | ||
2ee0da16 VS |
14143 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
14144 | { | |
14145 | /* 640x480@60Hz, ~25175 kHz */ | |
14146 | struct dpll clock = { | |
14147 | .m1 = 18, | |
14148 | .m2 = 7, | |
14149 | .p1 = 13, | |
14150 | .p2 = 4, | |
14151 | .n = 2, | |
14152 | }; | |
14153 | u32 dpll, fp; | |
14154 | int i; | |
14155 | ||
14156 | WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154); | |
14157 | ||
14158 | DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n", | |
14159 | pipe_name(pipe), clock.vco, clock.dot); | |
14160 | ||
14161 | fp = i9xx_dpll_compute_fp(&clock); | |
14162 | dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) | | |
14163 | DPLL_VGA_MODE_DIS | | |
14164 | ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | | |
14165 | PLL_P2_DIVIDE_BY_4 | | |
14166 | PLL_REF_INPUT_DREFCLK | | |
14167 | DPLL_VCO_ENABLE; | |
14168 | ||
14169 | I915_WRITE(FP0(pipe), fp); | |
14170 | I915_WRITE(FP1(pipe), fp); | |
14171 | ||
14172 | I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14173 | I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14174 | I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); | |
14175 | I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14176 | I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14177 | I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); | |
14178 | I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); | |
14179 | ||
14180 | /* | |
14181 | * Apparently we need to have VGA mode enabled prior to changing | |
14182 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
14183 | * dividers, even though the register value does change. | |
14184 | */ | |
14185 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); | |
14186 | I915_WRITE(DPLL(pipe), dpll); | |
14187 | ||
14188 | /* Wait for the clocks to stabilize. */ | |
14189 | POSTING_READ(DPLL(pipe)); | |
14190 | udelay(150); | |
14191 | ||
14192 | /* The pixel multiplier can only be updated once the | |
14193 | * DPLL is enabled and the clocks are stable. | |
14194 | * | |
14195 | * So write it again. | |
14196 | */ | |
14197 | I915_WRITE(DPLL(pipe), dpll); | |
14198 | ||
14199 | /* We do this three times for luck */ | |
14200 | for (i = 0; i < 3 ; i++) { | |
14201 | I915_WRITE(DPLL(pipe), dpll); | |
14202 | POSTING_READ(DPLL(pipe)); | |
14203 | udelay(150); /* wait for warmup */ | |
14204 | } | |
14205 | ||
14206 | I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); | |
14207 | POSTING_READ(PIPECONF(pipe)); | |
14208 | } | |
14209 | ||
14210 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) | |
14211 | { | |
14212 | DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n", | |
14213 | pipe_name(pipe)); | |
14214 | ||
14215 | assert_plane_disabled(dev_priv, PLANE_A); | |
14216 | assert_plane_disabled(dev_priv, PLANE_B); | |
14217 | ||
14218 | I915_WRITE(PIPECONF(pipe), 0); | |
14219 | POSTING_READ(PIPECONF(pipe)); | |
14220 | ||
14221 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) | |
14222 | DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe)); | |
14223 | ||
14224 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); | |
14225 | POSTING_READ(DPLL(pipe)); | |
14226 | } | |
14227 | ||
fa555837 DV |
14228 | static bool |
14229 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14230 | { | |
b7f05d4a | 14231 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 14232 | u32 val; |
fa555837 | 14233 | |
b7f05d4a | 14234 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
14235 | return true; |
14236 | ||
649636ef | 14237 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
14238 | |
14239 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14240 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14241 | return false; | |
14242 | ||
14243 | return true; | |
14244 | } | |
14245 | ||
02e93c35 VS |
14246 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
14247 | { | |
14248 | struct drm_device *dev = crtc->base.dev; | |
14249 | struct intel_encoder *encoder; | |
14250 | ||
14251 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
14252 | return true; | |
14253 | ||
14254 | return false; | |
14255 | } | |
14256 | ||
496b0fc3 ML |
14257 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
14258 | { | |
14259 | struct drm_device *dev = encoder->base.dev; | |
14260 | struct intel_connector *connector; | |
14261 | ||
14262 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
14263 | return connector; | |
14264 | ||
14265 | return NULL; | |
14266 | } | |
14267 | ||
a168f5b3 VS |
14268 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
14269 | enum transcoder pch_transcoder) | |
14270 | { | |
14271 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
14272 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
14273 | } | |
14274 | ||
aecd36b8 VS |
14275 | static void intel_sanitize_crtc(struct intel_crtc *crtc, |
14276 | struct drm_modeset_acquire_ctx *ctx) | |
24929352 DV |
14277 | { |
14278 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 14279 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 14280 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 14281 | |
24929352 | 14282 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
14283 | if (!transcoder_is_dsi(cpu_transcoder)) { |
14284 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
14285 | ||
14286 | I915_WRITE(reg, | |
14287 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
14288 | } | |
24929352 | 14289 | |
d3eaf884 | 14290 | /* restore vblank interrupts to correct state */ |
9625604c | 14291 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 14292 | if (crtc->active) { |
f9cd7b88 VS |
14293 | struct intel_plane *plane; |
14294 | ||
9625604c | 14295 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
14296 | |
14297 | /* Disable everything but the primary plane */ | |
14298 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
14299 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
14300 | continue; | |
14301 | ||
72259536 | 14302 | trace_intel_disable_plane(&plane->base, crtc); |
282dbf9b | 14303 | plane->disable_plane(plane, crtc); |
f9cd7b88 | 14304 | } |
9625604c | 14305 | } |
d3eaf884 | 14306 | |
24929352 | 14307 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14308 | * disable the crtc (and hence change the state) if it is wrong. Note |
14309 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 14310 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
14311 | bool plane; |
14312 | ||
78108b7c VS |
14313 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
14314 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
14315 | |
14316 | /* Pipe has the wrong plane attached and the plane is active. | |
14317 | * Temporarily change the plane mapping and disable everything | |
14318 | * ... */ | |
14319 | plane = crtc->plane; | |
1d4258db | 14320 | crtc->base.primary->state->visible = true; |
24929352 | 14321 | crtc->plane = !plane; |
da1d0e26 | 14322 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14323 | crtc->plane = plane; |
24929352 | 14324 | } |
24929352 DV |
14325 | |
14326 | /* Adjust the state of the output pipe according to whether we | |
14327 | * have active connectors/encoders. */ | |
842e0307 | 14328 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
da1d0e26 | 14329 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14330 | |
49cff963 | 14331 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
14332 | /* |
14333 | * We start out with underrun reporting disabled to avoid races. | |
14334 | * For correct bookkeeping mark this on active crtcs. | |
14335 | * | |
c5ab3bc0 DV |
14336 | * Also on gmch platforms we dont have any hardware bits to |
14337 | * disable the underrun reporting. Which means we need to start | |
14338 | * out with underrun reporting disabled also on inactive pipes, | |
14339 | * since otherwise we'll complain about the garbage we read when | |
14340 | * e.g. coming up after runtime pm. | |
14341 | * | |
4cc31489 DV |
14342 | * No protection against concurrent access is required - at |
14343 | * worst a fifo underrun happens which also sets this to false. | |
14344 | */ | |
14345 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
14346 | /* |
14347 | * We track the PCH trancoder underrun reporting state | |
14348 | * within the crtc. With crtc for pipe A housing the underrun | |
14349 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
14350 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
14351 | * and marking underrun reporting as disabled for the non-existing | |
14352 | * PCH transcoders B and C would prevent enabling the south | |
14353 | * error interrupt (see cpt_can_enable_serr_int()). | |
14354 | */ | |
14355 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
14356 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 14357 | } |
24929352 DV |
14358 | } |
14359 | ||
14360 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14361 | { | |
14362 | struct intel_connector *connector; | |
24929352 DV |
14363 | |
14364 | /* We need to check both for a crtc link (meaning that the | |
14365 | * encoder is active and trying to read from a pipe) and the | |
14366 | * pipe itself being active. */ | |
14367 | bool has_active_crtc = encoder->base.crtc && | |
14368 | to_intel_crtc(encoder->base.crtc)->active; | |
14369 | ||
496b0fc3 ML |
14370 | connector = intel_encoder_find_connector(encoder); |
14371 | if (connector && !has_active_crtc) { | |
24929352 DV |
14372 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
14373 | encoder->base.base.id, | |
8e329a03 | 14374 | encoder->base.name); |
24929352 DV |
14375 | |
14376 | /* Connector is active, but has no active pipe. This is | |
14377 | * fallout from our resume register restoring. Disable | |
14378 | * the encoder manually again. */ | |
14379 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
14380 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
14381 | ||
24929352 DV |
14382 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
14383 | encoder->base.base.id, | |
8e329a03 | 14384 | encoder->base.name); |
fd6bbda9 | 14385 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 14386 | if (encoder->post_disable) |
fd6bbda9 | 14387 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 14388 | } |
7f1950fb | 14389 | encoder->base.crtc = NULL; |
24929352 DV |
14390 | |
14391 | /* Inconsistent output/port/pipe state happens presumably due to | |
14392 | * a bug in one of the get_hw_state functions. Or someplace else | |
14393 | * in our code, like the register restore mess on resume. Clamp | |
14394 | * things to off as a safer default. */ | |
fd6bbda9 ML |
14395 | |
14396 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14397 | connector->base.encoder = NULL; | |
24929352 DV |
14398 | } |
14399 | /* Enabled encoders without active connectors will be fixed in | |
14400 | * the crtc fixup. */ | |
14401 | } | |
14402 | ||
29b74b7f | 14403 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 14404 | { |
920a14b2 | 14405 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 14406 | |
04098753 ID |
14407 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14408 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 14409 | i915_disable_vga(dev_priv); |
04098753 ID |
14410 | } |
14411 | } | |
14412 | ||
29b74b7f | 14413 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 14414 | { |
8dc8a27c PZ |
14415 | /* This function can be called both from intel_modeset_setup_hw_state or |
14416 | * at a very early point in our resume sequence, where the power well | |
14417 | * structures are not yet restored. Since this function is at a very | |
14418 | * paranoid "someone might have enabled VGA while we were not looking" | |
14419 | * level, just check if the power well is enabled instead of trying to | |
14420 | * follow the "don't touch the power well if we don't need it" policy | |
14421 | * the rest of the driver uses. */ | |
6392f847 | 14422 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14423 | return; |
14424 | ||
29b74b7f | 14425 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
14426 | |
14427 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
14428 | } |
14429 | ||
f9cd7b88 | 14430 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 14431 | { |
f9cd7b88 | 14432 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 14433 | |
f9cd7b88 | 14434 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
14435 | } |
14436 | ||
f9cd7b88 VS |
14437 | /* FIXME read out full plane state for all planes */ |
14438 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 14439 | { |
e9728bd8 VS |
14440 | struct intel_plane *primary = to_intel_plane(crtc->base.primary); |
14441 | bool visible; | |
d032ffa0 | 14442 | |
e9728bd8 | 14443 | visible = crtc->active && primary_get_hw_state(primary); |
b26d3ea3 | 14444 | |
e9728bd8 VS |
14445 | intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), |
14446 | to_intel_plane_state(primary->base.state), | |
14447 | visible); | |
98ec7739 VS |
14448 | } |
14449 | ||
30e984df | 14450 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 14451 | { |
fac5e23e | 14452 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 14453 | enum pipe pipe; |
24929352 DV |
14454 | struct intel_crtc *crtc; |
14455 | struct intel_encoder *encoder; | |
14456 | struct intel_connector *connector; | |
f9e905ca | 14457 | struct drm_connector_list_iter conn_iter; |
5358901f | 14458 | int i; |
24929352 | 14459 | |
565602d7 ML |
14460 | dev_priv->active_crtcs = 0; |
14461 | ||
d3fcc808 | 14462 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
14463 | struct intel_crtc_state *crtc_state = |
14464 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 14465 | |
ec2dc6a0 | 14466 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
14467 | memset(crtc_state, 0, sizeof(*crtc_state)); |
14468 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 14469 | |
565602d7 ML |
14470 | crtc_state->base.active = crtc_state->base.enable = |
14471 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
14472 | ||
14473 | crtc->base.enabled = crtc_state->base.enable; | |
14474 | crtc->active = crtc_state->base.active; | |
14475 | ||
aca1ebf4 | 14476 | if (crtc_state->base.active) |
565602d7 ML |
14477 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
14478 | ||
f9cd7b88 | 14479 | readout_plane_state(crtc); |
24929352 | 14480 | |
78108b7c VS |
14481 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
14482 | crtc->base.base.id, crtc->base.name, | |
a8cd6da0 | 14483 | enableddisabled(crtc_state->base.active)); |
24929352 DV |
14484 | } |
14485 | ||
5358901f DV |
14486 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14487 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14488 | ||
2edd6443 | 14489 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
2c42e535 ACO |
14490 | &pll->state.hw_state); |
14491 | pll->state.crtc_mask = 0; | |
d3fcc808 | 14492 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
14493 | struct intel_crtc_state *crtc_state = |
14494 | to_intel_crtc_state(crtc->base.state); | |
14495 | ||
14496 | if (crtc_state->base.active && | |
14497 | crtc_state->shared_dpll == pll) | |
2c42e535 | 14498 | pll->state.crtc_mask |= 1 << crtc->pipe; |
5358901f | 14499 | } |
2c42e535 | 14500 | pll->active_mask = pll->state.crtc_mask; |
5358901f | 14501 | |
1e6f2ddc | 14502 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
2c42e535 | 14503 | pll->name, pll->state.crtc_mask, pll->on); |
5358901f DV |
14504 | } |
14505 | ||
b2784e15 | 14506 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14507 | pipe = 0; |
14508 | ||
14509 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
14510 | struct intel_crtc_state *crtc_state; |
14511 | ||
98187836 | 14512 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 14513 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 14514 | |
045ac3b5 | 14515 | encoder->base.crtc = &crtc->base; |
a8cd6da0 VS |
14516 | crtc_state->output_types |= 1 << encoder->type; |
14517 | encoder->get_config(encoder, crtc_state); | |
24929352 DV |
14518 | } else { |
14519 | encoder->base.crtc = NULL; | |
14520 | } | |
14521 | ||
6f2bcceb | 14522 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
14523 | encoder->base.base.id, encoder->base.name, |
14524 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 14525 | pipe_name(pipe)); |
24929352 DV |
14526 | } |
14527 | ||
f9e905ca DV |
14528 | drm_connector_list_iter_begin(dev, &conn_iter); |
14529 | for_each_intel_connector_iter(connector, &conn_iter) { | |
24929352 DV |
14530 | if (connector->get_hw_state(connector)) { |
14531 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
14532 | |
14533 | encoder = connector->encoder; | |
14534 | connector->base.encoder = &encoder->base; | |
14535 | ||
14536 | if (encoder->base.crtc && | |
14537 | encoder->base.crtc->state->active) { | |
14538 | /* | |
14539 | * This has to be done during hardware readout | |
14540 | * because anything calling .crtc_disable may | |
14541 | * rely on the connector_mask being accurate. | |
14542 | */ | |
14543 | encoder->base.crtc->state->connector_mask |= | |
14544 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
14545 | encoder->base.crtc->state->encoder_mask |= |
14546 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
14547 | } |
14548 | ||
24929352 DV |
14549 | } else { |
14550 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14551 | connector->base.encoder = NULL; | |
14552 | } | |
14553 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
14554 | connector->base.base.id, connector->base.name, |
14555 | enableddisabled(connector->base.encoder)); | |
24929352 | 14556 | } |
f9e905ca | 14557 | drm_connector_list_iter_end(&conn_iter); |
7f4c6284 VS |
14558 | |
14559 | for_each_intel_crtc(dev, crtc) { | |
a8cd6da0 VS |
14560 | struct intel_crtc_state *crtc_state = |
14561 | to_intel_crtc_state(crtc->base.state); | |
aca1ebf4 VS |
14562 | int pixclk = 0; |
14563 | ||
7f4c6284 | 14564 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
a8cd6da0 VS |
14565 | if (crtc_state->base.active) { |
14566 | intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); | |
14567 | intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); | |
7f4c6284 VS |
14568 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
14569 | ||
14570 | /* | |
14571 | * The initial mode needs to be set in order to keep | |
14572 | * the atomic core happy. It wants a valid mode if the | |
14573 | * crtc's enabled, so we do the above call. | |
14574 | * | |
7800fb69 DV |
14575 | * But we don't set all the derived state fully, hence |
14576 | * set a flag to indicate that a full recalculation is | |
14577 | * needed on the next commit. | |
7f4c6284 | 14578 | */ |
a8cd6da0 | 14579 | crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; |
9eca6832 | 14580 | |
a7d1b3f4 VS |
14581 | intel_crtc_compute_pixel_rate(crtc_state); |
14582 | ||
14583 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || | |
14584 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14585 | pixclk = crtc_state->pixel_rate; | |
aca1ebf4 VS |
14586 | else |
14587 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
14588 | ||
14589 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
a8cd6da0 | 14590 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
aca1ebf4 VS |
14591 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
14592 | ||
5caa0fea DV |
14593 | drm_calc_timestamping_constants(&crtc->base, |
14594 | &crtc_state->base.adjusted_mode); | |
9eca6832 | 14595 | update_scanline_offset(crtc); |
7f4c6284 | 14596 | } |
e3b247da | 14597 | |
aca1ebf4 VS |
14598 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
14599 | ||
a8cd6da0 | 14600 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 14601 | } |
30e984df DV |
14602 | } |
14603 | ||
62b69566 ACO |
14604 | static void |
14605 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
14606 | { | |
14607 | struct intel_encoder *encoder; | |
14608 | ||
14609 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
14610 | u64 get_domains; | |
14611 | enum intel_display_power_domain domain; | |
14612 | ||
14613 | if (!encoder->get_power_domains) | |
14614 | continue; | |
14615 | ||
14616 | get_domains = encoder->get_power_domains(encoder); | |
14617 | for_each_power_domain(domain, get_domains) | |
14618 | intel_display_power_get(dev_priv, domain); | |
14619 | } | |
14620 | } | |
14621 | ||
043e9bda ML |
14622 | /* Scan out the current hw modeset state, |
14623 | * and sanitizes it to the current state | |
14624 | */ | |
14625 | static void | |
aecd36b8 VS |
14626 | intel_modeset_setup_hw_state(struct drm_device *dev, |
14627 | struct drm_modeset_acquire_ctx *ctx) | |
30e984df | 14628 | { |
fac5e23e | 14629 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 14630 | enum pipe pipe; |
30e984df DV |
14631 | struct intel_crtc *crtc; |
14632 | struct intel_encoder *encoder; | |
35c95375 | 14633 | int i; |
30e984df DV |
14634 | |
14635 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
14636 | |
14637 | /* HW state is read out, now we need to sanitize this mess. */ | |
62b69566 ACO |
14638 | get_encoder_power_domains(dev_priv); |
14639 | ||
b2784e15 | 14640 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14641 | intel_sanitize_encoder(encoder); |
14642 | } | |
14643 | ||
055e393f | 14644 | for_each_pipe(dev_priv, pipe) { |
98187836 | 14645 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 14646 | |
aecd36b8 | 14647 | intel_sanitize_crtc(crtc, ctx); |
6e3c9717 ACO |
14648 | intel_dump_pipe_config(crtc, crtc->config, |
14649 | "[setup_hw_state]"); | |
24929352 | 14650 | } |
9a935856 | 14651 | |
d29b2f9d ACO |
14652 | intel_modeset_update_connector_atomic_state(dev); |
14653 | ||
35c95375 DV |
14654 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14655 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14656 | ||
2dd66ebd | 14657 | if (!pll->on || pll->active_mask) |
35c95375 DV |
14658 | continue; |
14659 | ||
14660 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
14661 | ||
2edd6443 | 14662 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
14663 | pll->on = false; |
14664 | } | |
14665 | ||
04548cba VS |
14666 | if (IS_G4X(dev_priv)) { |
14667 | g4x_wm_get_hw_state(dev); | |
14668 | g4x_wm_sanitize(dev_priv); | |
14669 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
6eb1a681 | 14670 | vlv_wm_get_hw_state(dev); |
602ae835 VS |
14671 | vlv_wm_sanitize(dev_priv); |
14672 | } else if (IS_GEN9(dev_priv)) { | |
3078999f | 14673 | skl_wm_get_hw_state(dev); |
602ae835 | 14674 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
243e6a44 | 14675 | ilk_wm_get_hw_state(dev); |
602ae835 | 14676 | } |
292b990e ML |
14677 | |
14678 | for_each_intel_crtc(dev, crtc) { | |
d8fc70b7 | 14679 | u64 put_domains; |
292b990e | 14680 | |
74bff5f9 | 14681 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
14682 | if (WARN_ON(put_domains)) |
14683 | modeset_put_power_domains(dev_priv, put_domains); | |
14684 | } | |
14685 | intel_display_set_init_power(dev_priv, false); | |
010cf73d | 14686 | |
8d8c386c ID |
14687 | intel_power_domains_verify_state(dev_priv); |
14688 | ||
010cf73d | 14689 | intel_fbc_init_pipe_state(dev_priv); |
043e9bda | 14690 | } |
7d0bc1ea | 14691 | |
043e9bda ML |
14692 | void intel_display_resume(struct drm_device *dev) |
14693 | { | |
e2c8b870 ML |
14694 | struct drm_i915_private *dev_priv = to_i915(dev); |
14695 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
14696 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 14697 | int ret; |
f30da187 | 14698 | |
e2c8b870 | 14699 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
14700 | if (state) |
14701 | state->acquire_ctx = &ctx; | |
043e9bda | 14702 | |
e2c8b870 | 14703 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 14704 | |
73974893 ML |
14705 | while (1) { |
14706 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
14707 | if (ret != -EDEADLK) | |
14708 | break; | |
043e9bda | 14709 | |
e2c8b870 | 14710 | drm_modeset_backoff(&ctx); |
e2c8b870 | 14711 | } |
043e9bda | 14712 | |
73974893 | 14713 | if (!ret) |
581e49fe | 14714 | ret = __intel_display_resume(dev, state, &ctx); |
73974893 | 14715 | |
e2c8b870 ML |
14716 | drm_modeset_drop_locks(&ctx); |
14717 | drm_modeset_acquire_fini(&ctx); | |
043e9bda | 14718 | |
0853695c | 14719 | if (ret) |
e2c8b870 | 14720 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
3c5e37f1 CW |
14721 | if (state) |
14722 | drm_atomic_state_put(state); | |
2c7111db CW |
14723 | } |
14724 | ||
14725 | void intel_modeset_gem_init(struct drm_device *dev) | |
14726 | { | |
dc97997a | 14727 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 14728 | |
dc97997a | 14729 | intel_init_gt_powersave(dev_priv); |
ae48434c | 14730 | |
1ee8da6d | 14731 | intel_setup_overlay(dev_priv); |
1ebaa0b9 CW |
14732 | } |
14733 | ||
14734 | int intel_connector_register(struct drm_connector *connector) | |
14735 | { | |
14736 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
14737 | int ret; | |
14738 | ||
14739 | ret = intel_backlight_device_register(intel_connector); | |
14740 | if (ret) | |
14741 | goto err; | |
14742 | ||
14743 | return 0; | |
0962c3c9 | 14744 | |
1ebaa0b9 CW |
14745 | err: |
14746 | return ret; | |
79e53945 JB |
14747 | } |
14748 | ||
c191eca1 | 14749 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 14750 | { |
e63d87c0 | 14751 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 14752 | |
e63d87c0 | 14753 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 14754 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
14755 | } |
14756 | ||
79e53945 JB |
14757 | void intel_modeset_cleanup(struct drm_device *dev) |
14758 | { | |
fac5e23e | 14759 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 14760 | |
eb955eee CW |
14761 | flush_work(&dev_priv->atomic_helper.free_work); |
14762 | WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); | |
14763 | ||
dc97997a | 14764 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 14765 | |
fd0c0642 DV |
14766 | /* |
14767 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 14768 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
14769 | * experience fancy races otherwise. |
14770 | */ | |
2aeb7d3a | 14771 | intel_irq_uninstall(dev_priv); |
eb21b92b | 14772 | |
fd0c0642 DV |
14773 | /* |
14774 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
14775 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
14776 | */ | |
f87ea761 | 14777 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 14778 | |
4f256d82 DV |
14779 | /* poll work can call into fbdev, hence clean that up afterwards */ |
14780 | intel_fbdev_fini(dev_priv); | |
14781 | ||
723bfd70 JB |
14782 | intel_unregister_dsm_handler(); |
14783 | ||
c937ab3e | 14784 | intel_fbc_global_disable(dev_priv); |
69341a5e | 14785 | |
1630fe75 CW |
14786 | /* flush any delayed tasks or pending work */ |
14787 | flush_scheduled_work(); | |
14788 | ||
79e53945 | 14789 | drm_mode_config_cleanup(dev); |
4d7bb011 | 14790 | |
1ee8da6d | 14791 | intel_cleanup_overlay(dev_priv); |
ae48434c | 14792 | |
dc97997a | 14793 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 14794 | |
40196446 | 14795 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
14796 | } |
14797 | ||
df0e9248 CW |
14798 | void intel_connector_attach_encoder(struct intel_connector *connector, |
14799 | struct intel_encoder *encoder) | |
14800 | { | |
14801 | connector->encoder = encoder; | |
14802 | drm_mode_connector_attach_encoder(&connector->base, | |
14803 | &encoder->base); | |
79e53945 | 14804 | } |
28d52043 DA |
14805 | |
14806 | /* | |
14807 | * set vga decode state - true == enable VGA decode | |
14808 | */ | |
6315b5d3 | 14809 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 14810 | { |
6315b5d3 | 14811 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
14812 | u16 gmch_ctrl; |
14813 | ||
75fa041d CW |
14814 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
14815 | DRM_ERROR("failed to read control word\n"); | |
14816 | return -EIO; | |
14817 | } | |
14818 | ||
c0cc8a55 CW |
14819 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
14820 | return 0; | |
14821 | ||
28d52043 DA |
14822 | if (state) |
14823 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
14824 | else | |
14825 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
14826 | |
14827 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
14828 | DRM_ERROR("failed to write control word\n"); | |
14829 | return -EIO; | |
14830 | } | |
14831 | ||
28d52043 DA |
14832 | return 0; |
14833 | } | |
c4a1d9e4 | 14834 | |
98a2f411 CW |
14835 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
14836 | ||
c4a1d9e4 | 14837 | struct intel_display_error_state { |
ff57f1b0 PZ |
14838 | |
14839 | u32 power_well_driver; | |
14840 | ||
63b66e5b CW |
14841 | int num_transcoders; |
14842 | ||
c4a1d9e4 CW |
14843 | struct intel_cursor_error_state { |
14844 | u32 control; | |
14845 | u32 position; | |
14846 | u32 base; | |
14847 | u32 size; | |
52331309 | 14848 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14849 | |
14850 | struct intel_pipe_error_state { | |
ddf9c536 | 14851 | bool power_domain_on; |
c4a1d9e4 | 14852 | u32 source; |
f301b1e1 | 14853 | u32 stat; |
52331309 | 14854 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14855 | |
14856 | struct intel_plane_error_state { | |
14857 | u32 control; | |
14858 | u32 stride; | |
14859 | u32 size; | |
14860 | u32 pos; | |
14861 | u32 addr; | |
14862 | u32 surface; | |
14863 | u32 tile_offset; | |
52331309 | 14864 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
14865 | |
14866 | struct intel_transcoder_error_state { | |
ddf9c536 | 14867 | bool power_domain_on; |
63b66e5b CW |
14868 | enum transcoder cpu_transcoder; |
14869 | ||
14870 | u32 conf; | |
14871 | ||
14872 | u32 htotal; | |
14873 | u32 hblank; | |
14874 | u32 hsync; | |
14875 | u32 vtotal; | |
14876 | u32 vblank; | |
14877 | u32 vsync; | |
14878 | } transcoder[4]; | |
c4a1d9e4 CW |
14879 | }; |
14880 | ||
14881 | struct intel_display_error_state * | |
c033666a | 14882 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 14883 | { |
c4a1d9e4 | 14884 | struct intel_display_error_state *error; |
63b66e5b CW |
14885 | int transcoders[] = { |
14886 | TRANSCODER_A, | |
14887 | TRANSCODER_B, | |
14888 | TRANSCODER_C, | |
14889 | TRANSCODER_EDP, | |
14890 | }; | |
c4a1d9e4 CW |
14891 | int i; |
14892 | ||
c033666a | 14893 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
14894 | return NULL; |
14895 | ||
9d1cb914 | 14896 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
14897 | if (error == NULL) |
14898 | return NULL; | |
14899 | ||
c033666a | 14900 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
14901 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
14902 | ||
055e393f | 14903 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 14904 | error->pipe[i].power_domain_on = |
f458ebbc DV |
14905 | __intel_display_power_is_enabled(dev_priv, |
14906 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 14907 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
14908 | continue; |
14909 | ||
5efb3e28 VS |
14910 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
14911 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
14912 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
14913 | |
14914 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
14915 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 14916 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 14917 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
14918 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
14919 | } | |
c033666a | 14920 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 14921 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 14922 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
14923 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
14924 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
14925 | } | |
14926 | ||
c4a1d9e4 | 14927 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 14928 | |
c033666a | 14929 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 14930 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
14931 | } |
14932 | ||
4d1de975 | 14933 | /* Note: this does not include DSI transcoders. */ |
c033666a | 14934 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 14935 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
14936 | error->num_transcoders++; /* Account for eDP. */ |
14937 | ||
14938 | for (i = 0; i < error->num_transcoders; i++) { | |
14939 | enum transcoder cpu_transcoder = transcoders[i]; | |
14940 | ||
ddf9c536 | 14941 | error->transcoder[i].power_domain_on = |
f458ebbc | 14942 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 14943 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 14944 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
14945 | continue; |
14946 | ||
63b66e5b CW |
14947 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
14948 | ||
14949 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
14950 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
14951 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
14952 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
14953 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
14954 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
14955 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
14956 | } |
14957 | ||
14958 | return error; | |
14959 | } | |
14960 | ||
edc3d884 MK |
14961 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
14962 | ||
c4a1d9e4 | 14963 | void |
edc3d884 | 14964 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
14965 | struct intel_display_error_state *error) |
14966 | { | |
5a4c6f1b | 14967 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
14968 | int i; |
14969 | ||
63b66e5b CW |
14970 | if (!error) |
14971 | return; | |
14972 | ||
b7f05d4a | 14973 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 14974 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 14975 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 14976 | error->power_well_driver); |
055e393f | 14977 | for_each_pipe(dev_priv, i) { |
edc3d884 | 14978 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 14979 | err_printf(m, " Power: %s\n", |
87ad3212 | 14980 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 14981 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 14982 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
14983 | |
14984 | err_printf(m, "Plane [%d]:\n", i); | |
14985 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
14986 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 14987 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
14988 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
14989 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 14990 | } |
772c2a51 | 14991 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 14992 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 14993 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
14994 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
14995 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
14996 | } |
14997 | ||
edc3d884 MK |
14998 | err_printf(m, "Cursor [%d]:\n", i); |
14999 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15000 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15001 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15002 | } |
63b66e5b CW |
15003 | |
15004 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15005 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15006 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15007 | err_printf(m, " Power: %s\n", |
87ad3212 | 15008 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15009 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15010 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15011 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15012 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15013 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15014 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15015 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15016 | } | |
c4a1d9e4 | 15017 | } |
98a2f411 CW |
15018 | |
15019 | #endif |