]>
Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
c37efb99 | 40 | #include "i915_gem_dmabuf.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
5a21b665 DV |
52 | static bool is_mmio_work(struct intel_flip_work *work) |
53 | { | |
54 | return work->mmio_work.func; | |
55 | } | |
56 | ||
465c120c | 57 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 58 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
59 | DRM_FORMAT_C8, |
60 | DRM_FORMAT_RGB565, | |
465c120c | 61 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 62 | DRM_FORMAT_XRGB8888, |
465c120c MR |
63 | }; |
64 | ||
65 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 66 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
70 | DRM_FORMAT_XBGR8888, | |
71 | DRM_FORMAT_XRGB2101010, | |
72 | DRM_FORMAT_XBGR2101010, | |
73 | }; | |
74 | ||
75 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
76 | DRM_FORMAT_C8, |
77 | DRM_FORMAT_RGB565, | |
78 | DRM_FORMAT_XRGB8888, | |
465c120c | 79 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 80 | DRM_FORMAT_ARGB8888, |
465c120c MR |
81 | DRM_FORMAT_ABGR8888, |
82 | DRM_FORMAT_XRGB2101010, | |
465c120c | 83 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
84 | DRM_FORMAT_YUYV, |
85 | DRM_FORMAT_YVYU, | |
86 | DRM_FORMAT_UYVY, | |
87 | DRM_FORMAT_VYUY, | |
465c120c MR |
88 | }; |
89 | ||
3d7d6510 MR |
90 | /* Cursor formats */ |
91 | static const uint32_t intel_cursor_formats[] = { | |
92 | DRM_FORMAT_ARGB8888, | |
93 | }; | |
94 | ||
f1f644dc | 95 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 96 | struct intel_crtc_state *pipe_config); |
18442d08 | 97 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 98 | struct intel_crtc_state *pipe_config); |
f1f644dc | 99 | |
eb1bfe80 JB |
100 | static int intel_framebuffer_init(struct drm_device *dev, |
101 | struct intel_framebuffer *ifb, | |
102 | struct drm_mode_fb_cmd2 *mode_cmd, | |
103 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
104 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
105 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 106 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 107 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
108 | struct intel_link_m_n *m_n, |
109 | struct intel_link_m_n *m2_n2); | |
29407aab | 110 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 111 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 112 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 113 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 114 | const struct intel_crtc_state *pipe_config); |
d288f65f | 115 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 116 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
117 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
118 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
119 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
120 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
121 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
122 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
123 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 124 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 125 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 126 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
324513c0 | 127 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 128 | |
d4906093 | 129 | struct intel_limit { |
4c5def93 ACO |
130 | struct { |
131 | int min, max; | |
132 | } dot, vco, n, m, m1, m2, p, p1; | |
133 | ||
134 | struct { | |
135 | int dot_limit; | |
136 | int p2_slow, p2_fast; | |
137 | } p2; | |
d4906093 | 138 | }; |
79e53945 | 139 | |
bfa7df01 VS |
140 | /* returns HPLL frequency in kHz */ |
141 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
142 | { | |
143 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
144 | ||
145 | /* Obtain SKU information */ | |
146 | mutex_lock(&dev_priv->sb_lock); | |
147 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
148 | CCK_FUSE_HPLL_FREQ_MASK; | |
149 | mutex_unlock(&dev_priv->sb_lock); | |
150 | ||
151 | return vco_freq[hpll_freq] * 1000; | |
152 | } | |
153 | ||
c30fec65 VS |
154 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
155 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
156 | { |
157 | u32 val; | |
158 | int divider; | |
159 | ||
bfa7df01 VS |
160 | mutex_lock(&dev_priv->sb_lock); |
161 | val = vlv_cck_read(dev_priv, reg); | |
162 | mutex_unlock(&dev_priv->sb_lock); | |
163 | ||
164 | divider = val & CCK_FREQUENCY_VALUES; | |
165 | ||
166 | WARN((val & CCK_FREQUENCY_STATUS) != | |
167 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
168 | "%s change in progress\n", name); | |
169 | ||
c30fec65 VS |
170 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
171 | } | |
172 | ||
173 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
174 | const char *name, u32 reg) | |
175 | { | |
176 | if (dev_priv->hpll_freq == 0) | |
177 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
178 | ||
179 | return vlv_get_cck_clock(dev_priv, name, reg, | |
180 | dev_priv->hpll_freq); | |
bfa7df01 VS |
181 | } |
182 | ||
e7dc33f3 VS |
183 | static int |
184 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 185 | { |
e7dc33f3 VS |
186 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
187 | } | |
d2acd215 | 188 | |
e7dc33f3 VS |
189 | static int |
190 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
191 | { | |
19ab4ed3 | 192 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
193 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
194 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
195 | } |
196 | ||
e7dc33f3 VS |
197 | static int |
198 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 199 | { |
79e50a4f JN |
200 | uint32_t clkcfg; |
201 | ||
e7dc33f3 | 202 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
203 | clkcfg = I915_READ(CLKCFG); |
204 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
205 | case CLKCFG_FSB_400: | |
e7dc33f3 | 206 | return 100000; |
79e50a4f | 207 | case CLKCFG_FSB_533: |
e7dc33f3 | 208 | return 133333; |
79e50a4f | 209 | case CLKCFG_FSB_667: |
e7dc33f3 | 210 | return 166667; |
79e50a4f | 211 | case CLKCFG_FSB_800: |
e7dc33f3 | 212 | return 200000; |
79e50a4f | 213 | case CLKCFG_FSB_1067: |
e7dc33f3 | 214 | return 266667; |
79e50a4f | 215 | case CLKCFG_FSB_1333: |
e7dc33f3 | 216 | return 333333; |
79e50a4f JN |
217 | /* these two are just a guess; one of them might be right */ |
218 | case CLKCFG_FSB_1600: | |
219 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 220 | return 400000; |
79e50a4f | 221 | default: |
e7dc33f3 | 222 | return 133333; |
79e50a4f JN |
223 | } |
224 | } | |
225 | ||
19ab4ed3 | 226 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
227 | { |
228 | if (HAS_PCH_SPLIT(dev_priv)) | |
229 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
230 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
231 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
232 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
233 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
234 | else | |
235 | return; /* no rawclk on other platforms, or no need to know it */ | |
236 | ||
237 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
238 | } | |
239 | ||
bfa7df01 VS |
240 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
241 | { | |
666a4537 | 242 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
243 | return; |
244 | ||
245 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
246 | CCK_CZ_CLOCK_CONTROL); | |
247 | ||
248 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
249 | } | |
250 | ||
021357ac | 251 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
252 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
253 | const struct intel_crtc_state *pipe_config) | |
021357ac | 254 | { |
21a727b3 VS |
255 | if (HAS_DDI(dev_priv)) |
256 | return pipe_config->port_clock; /* SPLL */ | |
257 | else if (IS_GEN5(dev_priv)) | |
258 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 259 | else |
21a727b3 | 260 | return 270000; |
021357ac CW |
261 | } |
262 | ||
1b6f4958 | 263 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 264 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 265 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 266 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
267 | .m = { .min = 96, .max = 140 }, |
268 | .m1 = { .min = 18, .max = 26 }, | |
269 | .m2 = { .min = 6, .max = 16 }, | |
270 | .p = { .min = 4, .max = 128 }, | |
271 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
272 | .p2 = { .dot_limit = 165000, |
273 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
274 | }; |
275 | ||
1b6f4958 | 276 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 277 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 278 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 279 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
280 | .m = { .min = 96, .max = 140 }, |
281 | .m1 = { .min = 18, .max = 26 }, | |
282 | .m2 = { .min = 6, .max = 16 }, | |
283 | .p = { .min = 4, .max = 128 }, | |
284 | .p1 = { .min = 2, .max = 33 }, | |
285 | .p2 = { .dot_limit = 165000, | |
286 | .p2_slow = 4, .p2_fast = 4 }, | |
287 | }; | |
288 | ||
1b6f4958 | 289 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 290 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 291 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 292 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
293 | .m = { .min = 96, .max = 140 }, |
294 | .m1 = { .min = 18, .max = 26 }, | |
295 | .m2 = { .min = 6, .max = 16 }, | |
296 | .p = { .min = 4, .max = 128 }, | |
297 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
298 | .p2 = { .dot_limit = 165000, |
299 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 300 | }; |
273e27ca | 301 | |
1b6f4958 | 302 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
303 | .dot = { .min = 20000, .max = 400000 }, |
304 | .vco = { .min = 1400000, .max = 2800000 }, | |
305 | .n = { .min = 1, .max = 6 }, | |
306 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
307 | .m1 = { .min = 8, .max = 18 }, |
308 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
309 | .p = { .min = 5, .max = 80 }, |
310 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
311 | .p2 = { .dot_limit = 200000, |
312 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
313 | }; |
314 | ||
1b6f4958 | 315 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
316 | .dot = { .min = 20000, .max = 400000 }, |
317 | .vco = { .min = 1400000, .max = 2800000 }, | |
318 | .n = { .min = 1, .max = 6 }, | |
319 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
320 | .m1 = { .min = 8, .max = 18 }, |
321 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
322 | .p = { .min = 7, .max = 98 }, |
323 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
324 | .p2 = { .dot_limit = 112000, |
325 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
326 | }; |
327 | ||
273e27ca | 328 | |
1b6f4958 | 329 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
330 | .dot = { .min = 25000, .max = 270000 }, |
331 | .vco = { .min = 1750000, .max = 3500000}, | |
332 | .n = { .min = 1, .max = 4 }, | |
333 | .m = { .min = 104, .max = 138 }, | |
334 | .m1 = { .min = 17, .max = 23 }, | |
335 | .m2 = { .min = 5, .max = 11 }, | |
336 | .p = { .min = 10, .max = 30 }, | |
337 | .p1 = { .min = 1, .max = 3}, | |
338 | .p2 = { .dot_limit = 270000, | |
339 | .p2_slow = 10, | |
340 | .p2_fast = 10 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
1b6f4958 | 344 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
345 | .dot = { .min = 22000, .max = 400000 }, |
346 | .vco = { .min = 1750000, .max = 3500000}, | |
347 | .n = { .min = 1, .max = 4 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 16, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 5, .max = 80 }, | |
352 | .p1 = { .min = 1, .max = 8}, | |
353 | .p2 = { .dot_limit = 165000, | |
354 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
355 | }; |
356 | ||
1b6f4958 | 357 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
358 | .dot = { .min = 20000, .max = 115000 }, |
359 | .vco = { .min = 1750000, .max = 3500000 }, | |
360 | .n = { .min = 1, .max = 3 }, | |
361 | .m = { .min = 104, .max = 138 }, | |
362 | .m1 = { .min = 17, .max = 23 }, | |
363 | .m2 = { .min = 5, .max = 11 }, | |
364 | .p = { .min = 28, .max = 112 }, | |
365 | .p1 = { .min = 2, .max = 8 }, | |
366 | .p2 = { .dot_limit = 0, | |
367 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 368 | }, |
e4b36699 KP |
369 | }; |
370 | ||
1b6f4958 | 371 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
372 | .dot = { .min = 80000, .max = 224000 }, |
373 | .vco = { .min = 1750000, .max = 3500000 }, | |
374 | .n = { .min = 1, .max = 3 }, | |
375 | .m = { .min = 104, .max = 138 }, | |
376 | .m1 = { .min = 17, .max = 23 }, | |
377 | .m2 = { .min = 5, .max = 11 }, | |
378 | .p = { .min = 14, .max = 42 }, | |
379 | .p1 = { .min = 2, .max = 6 }, | |
380 | .p2 = { .dot_limit = 0, | |
381 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 382 | }, |
e4b36699 KP |
383 | }; |
384 | ||
1b6f4958 | 385 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
386 | .dot = { .min = 20000, .max = 400000}, |
387 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 388 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
389 | .n = { .min = 3, .max = 6 }, |
390 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 391 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
392 | .m1 = { .min = 0, .max = 0 }, |
393 | .m2 = { .min = 0, .max = 254 }, | |
394 | .p = { .min = 5, .max = 80 }, | |
395 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
396 | .p2 = { .dot_limit = 200000, |
397 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
398 | }; |
399 | ||
1b6f4958 | 400 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
401 | .dot = { .min = 20000, .max = 400000 }, |
402 | .vco = { .min = 1700000, .max = 3500000 }, | |
403 | .n = { .min = 3, .max = 6 }, | |
404 | .m = { .min = 2, .max = 256 }, | |
405 | .m1 = { .min = 0, .max = 0 }, | |
406 | .m2 = { .min = 0, .max = 254 }, | |
407 | .p = { .min = 7, .max = 112 }, | |
408 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
409 | .p2 = { .dot_limit = 112000, |
410 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
411 | }; |
412 | ||
273e27ca EA |
413 | /* Ironlake / Sandybridge |
414 | * | |
415 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
416 | * the range value for them is (actual_value - 2). | |
417 | */ | |
1b6f4958 | 418 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
419 | .dot = { .min = 25000, .max = 350000 }, |
420 | .vco = { .min = 1760000, .max = 3510000 }, | |
421 | .n = { .min = 1, .max = 5 }, | |
422 | .m = { .min = 79, .max = 127 }, | |
423 | .m1 = { .min = 12, .max = 22 }, | |
424 | .m2 = { .min = 5, .max = 9 }, | |
425 | .p = { .min = 5, .max = 80 }, | |
426 | .p1 = { .min = 1, .max = 8 }, | |
427 | .p2 = { .dot_limit = 225000, | |
428 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
429 | }; |
430 | ||
1b6f4958 | 431 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 3 }, | |
435 | .m = { .min = 79, .max = 118 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
439 | .p1 = { .min = 2, .max = 8 }, | |
440 | .p2 = { .dot_limit = 225000, | |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
1b6f4958 | 444 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 127 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 56 }, | |
452 | .p1 = { .min = 2, .max = 8 }, | |
453 | .p2 = { .dot_limit = 225000, | |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
455 | }; |
456 | ||
273e27ca | 457 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 458 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
459 | .dot = { .min = 25000, .max = 350000 }, |
460 | .vco = { .min = 1760000, .max = 3510000 }, | |
461 | .n = { .min = 1, .max = 2 }, | |
462 | .m = { .min = 79, .max = 126 }, | |
463 | .m1 = { .min = 12, .max = 22 }, | |
464 | .m2 = { .min = 5, .max = 9 }, | |
465 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 466 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
467 | .p2 = { .dot_limit = 225000, |
468 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
469 | }; |
470 | ||
1b6f4958 | 471 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
472 | .dot = { .min = 25000, .max = 350000 }, |
473 | .vco = { .min = 1760000, .max = 3510000 }, | |
474 | .n = { .min = 1, .max = 3 }, | |
475 | .m = { .min = 79, .max = 126 }, | |
476 | .m1 = { .min = 12, .max = 22 }, | |
477 | .m2 = { .min = 5, .max = 9 }, | |
478 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 479 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
480 | .p2 = { .dot_limit = 225000, |
481 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
482 | }; |
483 | ||
1b6f4958 | 484 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
485 | /* |
486 | * These are the data rate limits (measured in fast clocks) | |
487 | * since those are the strictest limits we have. The fast | |
488 | * clock and actual rate limits are more relaxed, so checking | |
489 | * them would make no difference. | |
490 | */ | |
491 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 492 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 493 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
494 | .m1 = { .min = 2, .max = 3 }, |
495 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 496 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 497 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
498 | }; |
499 | ||
1b6f4958 | 500 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
501 | /* |
502 | * These are the data rate limits (measured in fast clocks) | |
503 | * since those are the strictest limits we have. The fast | |
504 | * clock and actual rate limits are more relaxed, so checking | |
505 | * them would make no difference. | |
506 | */ | |
507 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 508 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
509 | .n = { .min = 1, .max = 1 }, |
510 | .m1 = { .min = 2, .max = 2 }, | |
511 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
512 | .p1 = { .min = 2, .max = 4 }, | |
513 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
514 | }; | |
515 | ||
1b6f4958 | 516 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
517 | /* FIXME: find real dot limits */ |
518 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 519 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
520 | .n = { .min = 1, .max = 1 }, |
521 | .m1 = { .min = 2, .max = 2 }, | |
522 | /* FIXME: find real m2 limits */ | |
523 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
524 | .p1 = { .min = 2, .max = 4 }, | |
525 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
526 | }; | |
527 | ||
cdba954e ACO |
528 | static bool |
529 | needs_modeset(struct drm_crtc_state *state) | |
530 | { | |
fc596660 | 531 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
532 | } |
533 | ||
dccbea3b ID |
534 | /* |
535 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
536 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
537 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
538 | * The helpers' return value is the rate of the clock that is fed to the | |
539 | * display engine's pipe which can be the above fast dot clock rate or a | |
540 | * divided-down version of it. | |
541 | */ | |
f2b115e6 | 542 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 543 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 544 | { |
2177832f SL |
545 | clock->m = clock->m2 + 2; |
546 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 547 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 548 | return 0; |
fb03ac01 VS |
549 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
550 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
551 | |
552 | return clock->dot; | |
2177832f SL |
553 | } |
554 | ||
7429e9d4 DV |
555 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
556 | { | |
557 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
558 | } | |
559 | ||
9e2c8475 | 560 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 561 | { |
7429e9d4 | 562 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 563 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 564 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 565 | return 0; |
fb03ac01 VS |
566 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
567 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
568 | |
569 | return clock->dot; | |
79e53945 JB |
570 | } |
571 | ||
9e2c8475 | 572 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
573 | { |
574 | clock->m = clock->m1 * clock->m2; | |
575 | clock->p = clock->p1 * clock->p2; | |
576 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 577 | return 0; |
589eca67 ID |
578 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
579 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
580 | |
581 | return clock->dot / 5; | |
589eca67 ID |
582 | } |
583 | ||
9e2c8475 | 584 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
585 | { |
586 | clock->m = clock->m1 * clock->m2; | |
587 | clock->p = clock->p1 * clock->p2; | |
588 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 589 | return 0; |
ef9348c8 CML |
590 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
591 | clock->n << 22); | |
592 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
593 | |
594 | return clock->dot / 5; | |
ef9348c8 CML |
595 | } |
596 | ||
7c04d1d9 | 597 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
598 | /** |
599 | * Returns whether the given set of divisors are valid for a given refclk with | |
600 | * the given connectors. | |
601 | */ | |
602 | ||
1b894b59 | 603 | static bool intel_PLL_is_valid(struct drm_device *dev, |
1b6f4958 | 604 | const struct intel_limit *limit, |
9e2c8475 | 605 | const struct dpll *clock) |
79e53945 | 606 | { |
f01b7962 VS |
607 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
608 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 609 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 610 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 611 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 612 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 613 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 614 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 615 | |
666a4537 WB |
616 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
617 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
618 | if (clock->m1 <= clock->m2) |
619 | INTELPllInvalid("m1 <= m2\n"); | |
620 | ||
666a4537 | 621 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
622 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
623 | INTELPllInvalid("p out of range\n"); | |
624 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
625 | INTELPllInvalid("m out of range\n"); | |
626 | } | |
627 | ||
79e53945 | 628 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 629 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
630 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
631 | * connector, etc., rather than just a single range. | |
632 | */ | |
633 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 634 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
635 | |
636 | return true; | |
637 | } | |
638 | ||
3b1429d9 | 639 | static int |
1b6f4958 | 640 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
641 | const struct intel_crtc_state *crtc_state, |
642 | int target) | |
79e53945 | 643 | { |
3b1429d9 | 644 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 645 | |
2d84d2b3 | 646 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 647 | /* |
a210b028 DV |
648 | * For LVDS just rely on its current settings for dual-channel. |
649 | * We haven't figured out how to reliably set up different | |
650 | * single/dual channel state, if we even can. | |
79e53945 | 651 | */ |
1974cad0 | 652 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 653 | return limit->p2.p2_fast; |
79e53945 | 654 | else |
3b1429d9 | 655 | return limit->p2.p2_slow; |
79e53945 JB |
656 | } else { |
657 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 658 | return limit->p2.p2_slow; |
79e53945 | 659 | else |
3b1429d9 | 660 | return limit->p2.p2_fast; |
79e53945 | 661 | } |
3b1429d9 VS |
662 | } |
663 | ||
70e8aa21 ACO |
664 | /* |
665 | * Returns a set of divisors for the desired target clock with the given | |
666 | * refclk, or FALSE. The returned values represent the clock equation: | |
667 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
668 | * | |
669 | * Target and reference clocks are specified in kHz. | |
670 | * | |
671 | * If match_clock is provided, then best_clock P divider must match the P | |
672 | * divider from @match_clock used for LVDS downclocking. | |
673 | */ | |
3b1429d9 | 674 | static bool |
1b6f4958 | 675 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 676 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
677 | int target, int refclk, struct dpll *match_clock, |
678 | struct dpll *best_clock) | |
3b1429d9 VS |
679 | { |
680 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 681 | struct dpll clock; |
3b1429d9 | 682 | int err = target; |
79e53945 | 683 | |
0206e353 | 684 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 685 | |
3b1429d9 VS |
686 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
687 | ||
42158660 ZY |
688 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
689 | clock.m1++) { | |
690 | for (clock.m2 = limit->m2.min; | |
691 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 692 | if (clock.m2 >= clock.m1) |
42158660 ZY |
693 | break; |
694 | for (clock.n = limit->n.min; | |
695 | clock.n <= limit->n.max; clock.n++) { | |
696 | for (clock.p1 = limit->p1.min; | |
697 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
698 | int this_err; |
699 | ||
dccbea3b | 700 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
701 | if (!intel_PLL_is_valid(dev, limit, |
702 | &clock)) | |
703 | continue; | |
704 | if (match_clock && | |
705 | clock.p != match_clock->p) | |
706 | continue; | |
707 | ||
708 | this_err = abs(clock.dot - target); | |
709 | if (this_err < err) { | |
710 | *best_clock = clock; | |
711 | err = this_err; | |
712 | } | |
713 | } | |
714 | } | |
715 | } | |
716 | } | |
717 | ||
718 | return (err != target); | |
719 | } | |
720 | ||
70e8aa21 ACO |
721 | /* |
722 | * Returns a set of divisors for the desired target clock with the given | |
723 | * refclk, or FALSE. The returned values represent the clock equation: | |
724 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
725 | * | |
726 | * Target and reference clocks are specified in kHz. | |
727 | * | |
728 | * If match_clock is provided, then best_clock P divider must match the P | |
729 | * divider from @match_clock used for LVDS downclocking. | |
730 | */ | |
ac58c3f0 | 731 | static bool |
1b6f4958 | 732 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 733 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
734 | int target, int refclk, struct dpll *match_clock, |
735 | struct dpll *best_clock) | |
79e53945 | 736 | { |
3b1429d9 | 737 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 738 | struct dpll clock; |
79e53945 JB |
739 | int err = target; |
740 | ||
0206e353 | 741 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 742 | |
3b1429d9 VS |
743 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
744 | ||
42158660 ZY |
745 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
746 | clock.m1++) { | |
747 | for (clock.m2 = limit->m2.min; | |
748 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
749 | for (clock.n = limit->n.min; |
750 | clock.n <= limit->n.max; clock.n++) { | |
751 | for (clock.p1 = limit->p1.min; | |
752 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
753 | int this_err; |
754 | ||
dccbea3b | 755 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
756 | if (!intel_PLL_is_valid(dev, limit, |
757 | &clock)) | |
79e53945 | 758 | continue; |
cec2f356 SP |
759 | if (match_clock && |
760 | clock.p != match_clock->p) | |
761 | continue; | |
79e53945 JB |
762 | |
763 | this_err = abs(clock.dot - target); | |
764 | if (this_err < err) { | |
765 | *best_clock = clock; | |
766 | err = this_err; | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
771 | } | |
772 | ||
773 | return (err != target); | |
774 | } | |
775 | ||
997c030c ACO |
776 | /* |
777 | * Returns a set of divisors for the desired target clock with the given | |
778 | * refclk, or FALSE. The returned values represent the clock equation: | |
779 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
780 | * |
781 | * Target and reference clocks are specified in kHz. | |
782 | * | |
783 | * If match_clock is provided, then best_clock P divider must match the P | |
784 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 785 | */ |
d4906093 | 786 | static bool |
1b6f4958 | 787 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 788 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
789 | int target, int refclk, struct dpll *match_clock, |
790 | struct dpll *best_clock) | |
d4906093 | 791 | { |
3b1429d9 | 792 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 793 | struct dpll clock; |
d4906093 | 794 | int max_n; |
3b1429d9 | 795 | bool found = false; |
6ba770dc AJ |
796 | /* approximately equals target * 0.00585 */ |
797 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
798 | |
799 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
800 | |
801 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
802 | ||
d4906093 | 803 | max_n = limit->n.max; |
f77f13e2 | 804 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 805 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 806 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
807 | for (clock.m1 = limit->m1.max; |
808 | clock.m1 >= limit->m1.min; clock.m1--) { | |
809 | for (clock.m2 = limit->m2.max; | |
810 | clock.m2 >= limit->m2.min; clock.m2--) { | |
811 | for (clock.p1 = limit->p1.max; | |
812 | clock.p1 >= limit->p1.min; clock.p1--) { | |
813 | int this_err; | |
814 | ||
dccbea3b | 815 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
816 | if (!intel_PLL_is_valid(dev, limit, |
817 | &clock)) | |
d4906093 | 818 | continue; |
1b894b59 CW |
819 | |
820 | this_err = abs(clock.dot - target); | |
d4906093 ML |
821 | if (this_err < err_most) { |
822 | *best_clock = clock; | |
823 | err_most = this_err; | |
824 | max_n = clock.n; | |
825 | found = true; | |
826 | } | |
827 | } | |
828 | } | |
829 | } | |
830 | } | |
2c07245f ZW |
831 | return found; |
832 | } | |
833 | ||
d5dd62bd ID |
834 | /* |
835 | * Check if the calculated PLL configuration is more optimal compared to the | |
836 | * best configuration and error found so far. Return the calculated error. | |
837 | */ | |
838 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
839 | const struct dpll *calculated_clock, |
840 | const struct dpll *best_clock, | |
d5dd62bd ID |
841 | unsigned int best_error_ppm, |
842 | unsigned int *error_ppm) | |
843 | { | |
9ca3ba01 ID |
844 | /* |
845 | * For CHV ignore the error and consider only the P value. | |
846 | * Prefer a bigger P value based on HW requirements. | |
847 | */ | |
848 | if (IS_CHERRYVIEW(dev)) { | |
849 | *error_ppm = 0; | |
850 | ||
851 | return calculated_clock->p > best_clock->p; | |
852 | } | |
853 | ||
24be4e46 ID |
854 | if (WARN_ON_ONCE(!target_freq)) |
855 | return false; | |
856 | ||
d5dd62bd ID |
857 | *error_ppm = div_u64(1000000ULL * |
858 | abs(target_freq - calculated_clock->dot), | |
859 | target_freq); | |
860 | /* | |
861 | * Prefer a better P value over a better (smaller) error if the error | |
862 | * is small. Ensure this preference for future configurations too by | |
863 | * setting the error to 0. | |
864 | */ | |
865 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
866 | *error_ppm = 0; | |
867 | ||
868 | return true; | |
869 | } | |
870 | ||
871 | return *error_ppm + 10 < best_error_ppm; | |
872 | } | |
873 | ||
65b3d6a9 ACO |
874 | /* |
875 | * Returns a set of divisors for the desired target clock with the given | |
876 | * refclk, or FALSE. The returned values represent the clock equation: | |
877 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
878 | */ | |
a0c4da24 | 879 | static bool |
1b6f4958 | 880 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 881 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
882 | int target, int refclk, struct dpll *match_clock, |
883 | struct dpll *best_clock) | |
a0c4da24 | 884 | { |
a93e255f | 885 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 886 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 887 | struct dpll clock; |
69e4f900 | 888 | unsigned int bestppm = 1000000; |
27e639bf VS |
889 | /* min update 19.2 MHz */ |
890 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 891 | bool found = false; |
a0c4da24 | 892 | |
6b4bf1c4 VS |
893 | target *= 5; /* fast clock */ |
894 | ||
895 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
896 | |
897 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 898 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 899 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 900 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 901 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 902 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 903 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 904 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 905 | unsigned int ppm; |
69e4f900 | 906 | |
6b4bf1c4 VS |
907 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
908 | refclk * clock.m1); | |
909 | ||
dccbea3b | 910 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 911 | |
f01b7962 VS |
912 | if (!intel_PLL_is_valid(dev, limit, |
913 | &clock)) | |
43b0ac53 VS |
914 | continue; |
915 | ||
d5dd62bd ID |
916 | if (!vlv_PLL_is_optimal(dev, target, |
917 | &clock, | |
918 | best_clock, | |
919 | bestppm, &ppm)) | |
920 | continue; | |
6b4bf1c4 | 921 | |
d5dd62bd ID |
922 | *best_clock = clock; |
923 | bestppm = ppm; | |
924 | found = true; | |
a0c4da24 JB |
925 | } |
926 | } | |
927 | } | |
928 | } | |
a0c4da24 | 929 | |
49e497ef | 930 | return found; |
a0c4da24 | 931 | } |
a4fc5ed6 | 932 | |
65b3d6a9 ACO |
933 | /* |
934 | * Returns a set of divisors for the desired target clock with the given | |
935 | * refclk, or FALSE. The returned values represent the clock equation: | |
936 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
937 | */ | |
ef9348c8 | 938 | static bool |
1b6f4958 | 939 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 940 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
941 | int target, int refclk, struct dpll *match_clock, |
942 | struct dpll *best_clock) | |
ef9348c8 | 943 | { |
a93e255f | 944 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 945 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 946 | unsigned int best_error_ppm; |
9e2c8475 | 947 | struct dpll clock; |
ef9348c8 CML |
948 | uint64_t m2; |
949 | int found = false; | |
950 | ||
951 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 952 | best_error_ppm = 1000000; |
ef9348c8 CML |
953 | |
954 | /* | |
955 | * Based on hardware doc, the n always set to 1, and m1 always | |
956 | * set to 2. If requires to support 200Mhz refclk, we need to | |
957 | * revisit this because n may not 1 anymore. | |
958 | */ | |
959 | clock.n = 1, clock.m1 = 2; | |
960 | target *= 5; /* fast clock */ | |
961 | ||
962 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
963 | for (clock.p2 = limit->p2.p2_fast; | |
964 | clock.p2 >= limit->p2.p2_slow; | |
965 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 966 | unsigned int error_ppm; |
ef9348c8 CML |
967 | |
968 | clock.p = clock.p1 * clock.p2; | |
969 | ||
970 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
971 | clock.n) << 22, refclk * clock.m1); | |
972 | ||
973 | if (m2 > INT_MAX/clock.m1) | |
974 | continue; | |
975 | ||
976 | clock.m2 = m2; | |
977 | ||
dccbea3b | 978 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
979 | |
980 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
981 | continue; | |
982 | ||
9ca3ba01 ID |
983 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
984 | best_error_ppm, &error_ppm)) | |
985 | continue; | |
986 | ||
987 | *best_clock = clock; | |
988 | best_error_ppm = error_ppm; | |
989 | found = true; | |
ef9348c8 CML |
990 | } |
991 | } | |
992 | ||
993 | return found; | |
994 | } | |
995 | ||
5ab7b0b7 | 996 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 997 | struct dpll *best_clock) |
5ab7b0b7 | 998 | { |
65b3d6a9 | 999 | int refclk = 100000; |
1b6f4958 | 1000 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1001 | |
65b3d6a9 | 1002 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1003 | target_clock, refclk, NULL, best_clock); |
1004 | } | |
1005 | ||
20ddf665 VS |
1006 | bool intel_crtc_active(struct drm_crtc *crtc) |
1007 | { | |
1008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1009 | ||
1010 | /* Be paranoid as we can arrive here with only partial | |
1011 | * state retrieved from the hardware during setup. | |
1012 | * | |
241bfc38 | 1013 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1014 | * as Haswell has gained clock readout/fastboot support. |
1015 | * | |
66e514c1 | 1016 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1017 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1018 | * |
1019 | * FIXME: The intel_crtc->active here should be switched to | |
1020 | * crtc->state->active once we have proper CRTC states wired up | |
1021 | * for atomic. | |
20ddf665 | 1022 | */ |
c3d1f436 | 1023 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1024 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1025 | } |
1026 | ||
a5c961d1 PZ |
1027 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1028 | enum pipe pipe) | |
1029 | { | |
1030 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1032 | ||
6e3c9717 | 1033 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1034 | } |
1035 | ||
fbf49ea2 VS |
1036 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1037 | { | |
fac5e23e | 1038 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1039 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1040 | u32 line1, line2; |
1041 | u32 line_mask; | |
1042 | ||
1043 | if (IS_GEN2(dev)) | |
1044 | line_mask = DSL_LINEMASK_GEN2; | |
1045 | else | |
1046 | line_mask = DSL_LINEMASK_GEN3; | |
1047 | ||
1048 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1049 | msleep(5); |
fbf49ea2 VS |
1050 | line2 = I915_READ(reg) & line_mask; |
1051 | ||
1052 | return line1 == line2; | |
1053 | } | |
1054 | ||
ab7ad7f6 KP |
1055 | /* |
1056 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1057 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1058 | * |
1059 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1060 | * spinning on the vblank interrupt status bit, since we won't actually | |
1061 | * see an interrupt when the pipe is disabled. | |
1062 | * | |
ab7ad7f6 KP |
1063 | * On Gen4 and above: |
1064 | * wait for the pipe register state bit to turn off | |
1065 | * | |
1066 | * Otherwise: | |
1067 | * wait for the display line value to settle (it usually | |
1068 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1069 | * |
9d0498a2 | 1070 | */ |
575f7ab7 | 1071 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1072 | { |
575f7ab7 | 1073 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1074 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 1075 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1076 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1077 | |
1078 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1079 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1080 | |
1081 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1082 | if (intel_wait_for_register(dev_priv, |
1083 | reg, I965_PIPECONF_ACTIVE, 0, | |
1084 | 100)) | |
284637d9 | 1085 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1086 | } else { |
ab7ad7f6 | 1087 | /* Wait for the display line to settle */ |
fbf49ea2 | 1088 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1089 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1090 | } |
79e53945 JB |
1091 | } |
1092 | ||
b24e7179 | 1093 | /* Only for pre-ILK configs */ |
55607e8a DV |
1094 | void assert_pll(struct drm_i915_private *dev_priv, |
1095 | enum pipe pipe, bool state) | |
b24e7179 | 1096 | { |
b24e7179 JB |
1097 | u32 val; |
1098 | bool cur_state; | |
1099 | ||
649636ef | 1100 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1101 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1102 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1103 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1104 | onoff(state), onoff(cur_state)); |
b24e7179 | 1105 | } |
b24e7179 | 1106 | |
23538ef1 | 1107 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1108 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1109 | { |
1110 | u32 val; | |
1111 | bool cur_state; | |
1112 | ||
a580516d | 1113 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1114 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1115 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1116 | |
1117 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1118 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1119 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1120 | onoff(state), onoff(cur_state)); |
23538ef1 | 1121 | } |
23538ef1 | 1122 | |
040484af JB |
1123 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1124 | enum pipe pipe, bool state) | |
1125 | { | |
040484af | 1126 | bool cur_state; |
ad80a810 PZ |
1127 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1128 | pipe); | |
040484af | 1129 | |
2d1fe073 | 1130 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1131 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1132 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1133 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1134 | } else { |
649636ef | 1135 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1136 | cur_state = !!(val & FDI_TX_ENABLE); |
1137 | } | |
e2c719b7 | 1138 | I915_STATE_WARN(cur_state != state, |
040484af | 1139 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1140 | onoff(state), onoff(cur_state)); |
040484af JB |
1141 | } |
1142 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1143 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1144 | ||
1145 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1146 | enum pipe pipe, bool state) | |
1147 | { | |
040484af JB |
1148 | u32 val; |
1149 | bool cur_state; | |
1150 | ||
649636ef | 1151 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1152 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1153 | I915_STATE_WARN(cur_state != state, |
040484af | 1154 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1155 | onoff(state), onoff(cur_state)); |
040484af JB |
1156 | } |
1157 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1158 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1159 | ||
1160 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1161 | enum pipe pipe) | |
1162 | { | |
040484af JB |
1163 | u32 val; |
1164 | ||
1165 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1166 | if (IS_GEN5(dev_priv)) |
040484af JB |
1167 | return; |
1168 | ||
bf507ef7 | 1169 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1170 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1171 | return; |
1172 | ||
649636ef | 1173 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1174 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1175 | } |
1176 | ||
55607e8a DV |
1177 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1178 | enum pipe pipe, bool state) | |
040484af | 1179 | { |
040484af | 1180 | u32 val; |
55607e8a | 1181 | bool cur_state; |
040484af | 1182 | |
649636ef | 1183 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1184 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1185 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1186 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1187 | onoff(state), onoff(cur_state)); |
040484af JB |
1188 | } |
1189 | ||
b680c37a DV |
1190 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1191 | enum pipe pipe) | |
ea0760cf | 1192 | { |
91c8a326 | 1193 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 | 1194 | i915_reg_t pp_reg; |
ea0760cf JB |
1195 | u32 val; |
1196 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1197 | bool locked = true; |
ea0760cf | 1198 | |
bedd4dba JN |
1199 | if (WARN_ON(HAS_DDI(dev))) |
1200 | return; | |
1201 | ||
1202 | if (HAS_PCH_SPLIT(dev)) { | |
1203 | u32 port_sel; | |
1204 | ||
44cb734c ID |
1205 | pp_reg = PP_CONTROL(0); |
1206 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1207 | |
1208 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1209 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1210 | panel_pipe = PIPE_B; | |
1211 | /* XXX: else fix for eDP */ | |
666a4537 | 1212 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba | 1213 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1214 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1215 | panel_pipe = pipe; |
ea0760cf | 1216 | } else { |
44cb734c | 1217 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1218 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1219 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1220 | } |
1221 | ||
1222 | val = I915_READ(pp_reg); | |
1223 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1224 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1225 | locked = false; |
1226 | ||
e2c719b7 | 1227 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1228 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1229 | pipe_name(pipe)); |
ea0760cf JB |
1230 | } |
1231 | ||
93ce0ba6 JN |
1232 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1233 | enum pipe pipe, bool state) | |
1234 | { | |
91c8a326 | 1235 | struct drm_device *dev = &dev_priv->drm; |
93ce0ba6 JN |
1236 | bool cur_state; |
1237 | ||
d9d82081 | 1238 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1239 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1240 | else |
5efb3e28 | 1241 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1242 | |
e2c719b7 | 1243 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1244 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1245 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1246 | } |
1247 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1248 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1249 | ||
b840d907 JB |
1250 | void assert_pipe(struct drm_i915_private *dev_priv, |
1251 | enum pipe pipe, bool state) | |
b24e7179 | 1252 | { |
63d7bbe9 | 1253 | bool cur_state; |
702e7a56 PZ |
1254 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1255 | pipe); | |
4feed0eb | 1256 | enum intel_display_power_domain power_domain; |
b24e7179 | 1257 | |
b6b5d049 VS |
1258 | /* if we need the pipe quirk it must be always on */ |
1259 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1260 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1261 | state = true; |
1262 | ||
4feed0eb ID |
1263 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1264 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1265 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1266 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1267 | |
1268 | intel_display_power_put(dev_priv, power_domain); | |
1269 | } else { | |
1270 | cur_state = false; | |
69310161 PZ |
1271 | } |
1272 | ||
e2c719b7 | 1273 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1274 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1275 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1276 | } |
1277 | ||
931872fc CW |
1278 | static void assert_plane(struct drm_i915_private *dev_priv, |
1279 | enum plane plane, bool state) | |
b24e7179 | 1280 | { |
b24e7179 | 1281 | u32 val; |
931872fc | 1282 | bool cur_state; |
b24e7179 | 1283 | |
649636ef | 1284 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1285 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1286 | I915_STATE_WARN(cur_state != state, |
931872fc | 1287 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1288 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1289 | } |
1290 | ||
931872fc CW |
1291 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1292 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1293 | ||
b24e7179 JB |
1294 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe) | |
1296 | { | |
91c8a326 | 1297 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1298 | int i; |
b24e7179 | 1299 | |
653e1026 VS |
1300 | /* Primary planes are fixed to pipes on gen4+ */ |
1301 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1302 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1303 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1304 | "plane %c assertion failure, should be disabled but not\n", |
1305 | plane_name(pipe)); | |
19ec1358 | 1306 | return; |
28c05794 | 1307 | } |
19ec1358 | 1308 | |
b24e7179 | 1309 | /* Need to check both planes against the pipe */ |
055e393f | 1310 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1311 | u32 val = I915_READ(DSPCNTR(i)); |
1312 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1313 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1314 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1315 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1316 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1317 | } |
1318 | } | |
1319 | ||
19332d7a JB |
1320 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1321 | enum pipe pipe) | |
1322 | { | |
91c8a326 | 1323 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1324 | int sprite; |
19332d7a | 1325 | |
7feb8b88 | 1326 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1327 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1328 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1329 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1330 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1331 | sprite, pipe_name(pipe)); | |
1332 | } | |
666a4537 | 1333 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1334 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1335 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1336 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1337 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1338 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1339 | } |
1340 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1341 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1342 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1343 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1344 | plane_name(pipe), pipe_name(pipe)); |
1345 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1346 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1347 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1348 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1349 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1350 | } |
1351 | } | |
1352 | ||
08c71e5e VS |
1353 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1354 | { | |
e2c719b7 | 1355 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1356 | drm_crtc_vblank_put(crtc); |
1357 | } | |
1358 | ||
7abd4b35 ACO |
1359 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1360 | enum pipe pipe) | |
92f2584a | 1361 | { |
92f2584a JB |
1362 | u32 val; |
1363 | bool enabled; | |
1364 | ||
649636ef | 1365 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1366 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1367 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1368 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1369 | pipe_name(pipe)); | |
92f2584a JB |
1370 | } |
1371 | ||
4e634389 KP |
1372 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1373 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1374 | { |
1375 | if ((val & DP_PORT_EN) == 0) | |
1376 | return false; | |
1377 | ||
2d1fe073 | 1378 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1379 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1380 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1381 | return false; | |
2d1fe073 | 1382 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1383 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1384 | return false; | |
f0575e92 KP |
1385 | } else { |
1386 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1387 | return false; | |
1388 | } | |
1389 | return true; | |
1390 | } | |
1391 | ||
1519b995 KP |
1392 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1393 | enum pipe pipe, u32 val) | |
1394 | { | |
dc0fa718 | 1395 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1396 | return false; |
1397 | ||
2d1fe073 | 1398 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1399 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1400 | return false; |
2d1fe073 | 1401 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1402 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1403 | return false; | |
1519b995 | 1404 | } else { |
dc0fa718 | 1405 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1406 | return false; |
1407 | } | |
1408 | return true; | |
1409 | } | |
1410 | ||
1411 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1412 | enum pipe pipe, u32 val) | |
1413 | { | |
1414 | if ((val & LVDS_PORT_EN) == 0) | |
1415 | return false; | |
1416 | ||
2d1fe073 | 1417 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1418 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1419 | return false; | |
1420 | } else { | |
1421 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1422 | return false; | |
1423 | } | |
1424 | return true; | |
1425 | } | |
1426 | ||
1427 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1428 | enum pipe pipe, u32 val) | |
1429 | { | |
1430 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1431 | return false; | |
2d1fe073 | 1432 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1433 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1434 | return false; | |
1435 | } else { | |
1436 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1437 | return false; | |
1438 | } | |
1439 | return true; | |
1440 | } | |
1441 | ||
291906f1 | 1442 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1443 | enum pipe pipe, i915_reg_t reg, |
1444 | u32 port_sel) | |
291906f1 | 1445 | { |
47a05eca | 1446 | u32 val = I915_READ(reg); |
e2c719b7 | 1447 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1448 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1449 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1450 | |
2d1fe073 | 1451 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1452 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1453 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1454 | } |
1455 | ||
1456 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1457 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1458 | { |
47a05eca | 1459 | u32 val = I915_READ(reg); |
e2c719b7 | 1460 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1461 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1462 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1463 | |
2d1fe073 | 1464 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1465 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1466 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1467 | } |
1468 | ||
1469 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1470 | enum pipe pipe) | |
1471 | { | |
291906f1 | 1472 | u32 val; |
291906f1 | 1473 | |
f0575e92 KP |
1474 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1475 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1476 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1477 | |
649636ef | 1478 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1479 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1480 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1481 | pipe_name(pipe)); |
291906f1 | 1482 | |
649636ef | 1483 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1484 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1485 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1486 | pipe_name(pipe)); |
291906f1 | 1487 | |
e2debe91 PZ |
1488 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1490 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1491 | } |
1492 | ||
cd2d34d9 VS |
1493 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1494 | const struct intel_crtc_state *pipe_config) | |
1495 | { | |
1496 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1497 | enum pipe pipe = crtc->pipe; | |
1498 | ||
1499 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1500 | POSTING_READ(DPLL(pipe)); | |
1501 | udelay(150); | |
1502 | ||
2c30b43b CW |
1503 | if (intel_wait_for_register(dev_priv, |
1504 | DPLL(pipe), | |
1505 | DPLL_LOCK_VLV, | |
1506 | DPLL_LOCK_VLV, | |
1507 | 1)) | |
cd2d34d9 VS |
1508 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1509 | } | |
1510 | ||
d288f65f | 1511 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1512 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1513 | { |
cd2d34d9 | 1514 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1515 | enum pipe pipe = crtc->pipe; |
87442f73 | 1516 | |
8bd3f301 | 1517 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1518 | |
87442f73 | 1519 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1520 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1521 | |
cd2d34d9 VS |
1522 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1523 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1524 | |
8bd3f301 VS |
1525 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1526 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1527 | } |
1528 | ||
cd2d34d9 VS |
1529 | |
1530 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1531 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1532 | { |
cd2d34d9 | 1533 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1534 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1535 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1536 | u32 tmp; |
1537 | ||
a580516d | 1538 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1539 | |
1540 | /* Enable back the 10bit clock to display controller */ | |
1541 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1542 | tmp |= DPIO_DCLKP_EN; | |
1543 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1544 | ||
54433e91 VS |
1545 | mutex_unlock(&dev_priv->sb_lock); |
1546 | ||
9d556c99 CML |
1547 | /* |
1548 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1549 | */ | |
1550 | udelay(1); | |
1551 | ||
1552 | /* Enable PLL */ | |
d288f65f | 1553 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1554 | |
1555 | /* Check PLL is locked */ | |
6b18826a CW |
1556 | if (intel_wait_for_register(dev_priv, |
1557 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1558 | 1)) | |
9d556c99 | 1559 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1560 | } |
1561 | ||
1562 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1563 | const struct intel_crtc_state *pipe_config) | |
1564 | { | |
1565 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1566 | enum pipe pipe = crtc->pipe; | |
1567 | ||
1568 | assert_pipe_disabled(dev_priv, pipe); | |
1569 | ||
1570 | /* PLL is protected by panel, make sure we can write it */ | |
1571 | assert_panel_unlocked(dev_priv, pipe); | |
1572 | ||
1573 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1574 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1575 | |
c231775c VS |
1576 | if (pipe != PIPE_A) { |
1577 | /* | |
1578 | * WaPixelRepeatModeFixForC0:chv | |
1579 | * | |
1580 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1581 | * the value from DPLLBMD to either pipe B or C. | |
1582 | */ | |
1583 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1584 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1585 | I915_WRITE(CBR4_VLV, 0); | |
1586 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1587 | ||
1588 | /* | |
1589 | * DPLLB VGA mode also seems to cause problems. | |
1590 | * We should always have it disabled. | |
1591 | */ | |
1592 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1593 | } else { | |
1594 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1595 | POSTING_READ(DPLL_MD(pipe)); | |
1596 | } | |
9d556c99 CML |
1597 | } |
1598 | ||
1c4e0274 VS |
1599 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1600 | { | |
1601 | struct intel_crtc *crtc; | |
1602 | int count = 0; | |
1603 | ||
2d84d2b3 | 1604 | for_each_intel_crtc(dev, crtc) { |
3538b9df | 1605 | count += crtc->base.state->active && |
2d84d2b3 VS |
1606 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1607 | } | |
1c4e0274 VS |
1608 | |
1609 | return count; | |
1610 | } | |
1611 | ||
66e3d5c0 | 1612 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1613 | { |
66e3d5c0 | 1614 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1615 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1616 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1617 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1618 | |
66e3d5c0 | 1619 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1620 | |
63d7bbe9 | 1621 | /* PLL is protected by panel, make sure we can write it */ |
66e3d5c0 DV |
1622 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1623 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1624 | |
1c4e0274 VS |
1625 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1626 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1627 | /* | |
1628 | * It appears to be important that we don't enable this | |
1629 | * for the current pipe before otherwise configuring the | |
1630 | * PLL. No idea how this should be handled if multiple | |
1631 | * DVO outputs are enabled simultaneosly. | |
1632 | */ | |
1633 | dpll |= DPLL_DVO_2X_MODE; | |
1634 | I915_WRITE(DPLL(!crtc->pipe), | |
1635 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1636 | } | |
66e3d5c0 | 1637 | |
c2b63374 VS |
1638 | /* |
1639 | * Apparently we need to have VGA mode enabled prior to changing | |
1640 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1641 | * dividers, even though the register value does change. | |
1642 | */ | |
1643 | I915_WRITE(reg, 0); | |
1644 | ||
8e7a65aa VS |
1645 | I915_WRITE(reg, dpll); |
1646 | ||
66e3d5c0 DV |
1647 | /* Wait for the clocks to stabilize. */ |
1648 | POSTING_READ(reg); | |
1649 | udelay(150); | |
1650 | ||
1651 | if (INTEL_INFO(dev)->gen >= 4) { | |
1652 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1653 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1654 | } else { |
1655 | /* The pixel multiplier can only be updated once the | |
1656 | * DPLL is enabled and the clocks are stable. | |
1657 | * | |
1658 | * So write it again. | |
1659 | */ | |
1660 | I915_WRITE(reg, dpll); | |
1661 | } | |
63d7bbe9 JB |
1662 | |
1663 | /* We do this three times for luck */ | |
66e3d5c0 | 1664 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1665 | POSTING_READ(reg); |
1666 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1667 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1668 | POSTING_READ(reg); |
1669 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1670 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1671 | POSTING_READ(reg); |
1672 | udelay(150); /* wait for warmup */ | |
1673 | } | |
1674 | ||
1675 | /** | |
50b44a44 | 1676 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1677 | * @dev_priv: i915 private structure |
1678 | * @pipe: pipe PLL to disable | |
1679 | * | |
1680 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1681 | * | |
1682 | * Note! This is for pre-ILK only. | |
1683 | */ | |
1c4e0274 | 1684 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1685 | { |
1c4e0274 | 1686 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1687 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c4e0274 VS |
1688 | enum pipe pipe = crtc->pipe; |
1689 | ||
1690 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1691 | if (IS_I830(dev) && | |
2d84d2b3 | 1692 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
3538b9df | 1693 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1694 | I915_WRITE(DPLL(PIPE_B), |
1695 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1696 | I915_WRITE(DPLL(PIPE_A), | |
1697 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1698 | } | |
1699 | ||
b6b5d049 VS |
1700 | /* Don't disable pipe or pipe PLLs if needed */ |
1701 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1702 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1703 | return; |
1704 | ||
1705 | /* Make sure the pipe isn't still relying on us */ | |
1706 | assert_pipe_disabled(dev_priv, pipe); | |
1707 | ||
b8afb911 | 1708 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1709 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1710 | } |
1711 | ||
f6071166 JB |
1712 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1713 | { | |
b8afb911 | 1714 | u32 val; |
f6071166 JB |
1715 | |
1716 | /* Make sure the pipe isn't still relying on us */ | |
1717 | assert_pipe_disabled(dev_priv, pipe); | |
1718 | ||
03ed5cbf VS |
1719 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1720 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1721 | if (pipe != PIPE_A) | |
1722 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1723 | ||
f6071166 JB |
1724 | I915_WRITE(DPLL(pipe), val); |
1725 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1726 | } |
1727 | ||
1728 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1729 | { | |
d752048d | 1730 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1731 | u32 val; |
1732 | ||
a11b0703 VS |
1733 | /* Make sure the pipe isn't still relying on us */ |
1734 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1735 | |
60bfe44f VS |
1736 | val = DPLL_SSC_REF_CLK_CHV | |
1737 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1738 | if (pipe != PIPE_A) |
1739 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1740 | |
a11b0703 VS |
1741 | I915_WRITE(DPLL(pipe), val); |
1742 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1743 | |
a580516d | 1744 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1745 | |
1746 | /* Disable 10bit clock to display controller */ | |
1747 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1748 | val &= ~DPIO_DCLKP_EN; | |
1749 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1750 | ||
a580516d | 1751 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1752 | } |
1753 | ||
e4607fcf | 1754 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1755 | struct intel_digital_port *dport, |
1756 | unsigned int expected_mask) | |
89b667f8 JB |
1757 | { |
1758 | u32 port_mask; | |
f0f59a00 | 1759 | i915_reg_t dpll_reg; |
89b667f8 | 1760 | |
e4607fcf CML |
1761 | switch (dport->port) { |
1762 | case PORT_B: | |
89b667f8 | 1763 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1764 | dpll_reg = DPLL(0); |
e4607fcf CML |
1765 | break; |
1766 | case PORT_C: | |
89b667f8 | 1767 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1768 | dpll_reg = DPLL(0); |
9b6de0a1 | 1769 | expected_mask <<= 4; |
00fc31b7 CML |
1770 | break; |
1771 | case PORT_D: | |
1772 | port_mask = DPLL_PORTD_READY_MASK; | |
1773 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1774 | break; |
1775 | default: | |
1776 | BUG(); | |
1777 | } | |
89b667f8 | 1778 | |
370004d3 CW |
1779 | if (intel_wait_for_register(dev_priv, |
1780 | dpll_reg, port_mask, expected_mask, | |
1781 | 1000)) | |
9b6de0a1 VS |
1782 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1783 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1784 | } |
1785 | ||
b8a4f404 PZ |
1786 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1787 | enum pipe pipe) | |
040484af | 1788 | { |
91c8a326 | 1789 | struct drm_device *dev = &dev_priv->drm; |
7c26e5c6 | 1790 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1792 | i915_reg_t reg; |
1793 | uint32_t val, pipeconf_val; | |
040484af | 1794 | |
040484af | 1795 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1796 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1797 | |
1798 | /* FDI must be feeding us bits for PCH ports */ | |
1799 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1800 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1801 | ||
23670b32 DV |
1802 | if (HAS_PCH_CPT(dev)) { |
1803 | /* Workaround: Set the timing override bit before enabling the | |
1804 | * pch transcoder. */ | |
1805 | reg = TRANS_CHICKEN2(pipe); | |
1806 | val = I915_READ(reg); | |
1807 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1808 | I915_WRITE(reg, val); | |
59c859d6 | 1809 | } |
23670b32 | 1810 | |
ab9412ba | 1811 | reg = PCH_TRANSCONF(pipe); |
040484af | 1812 | val = I915_READ(reg); |
5f7f726d | 1813 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1814 | |
2d1fe073 | 1815 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1816 | /* |
c5de7c6f VS |
1817 | * Make the BPC in transcoder be consistent with |
1818 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1819 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1820 | */ |
dfd07d72 | 1821 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1822 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1823 | val |= PIPECONF_8BPC; |
1824 | else | |
1825 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1826 | } |
5f7f726d PZ |
1827 | |
1828 | val &= ~TRANS_INTERLACE_MASK; | |
1829 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1830 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1831 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1832 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1833 | else | |
1834 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1835 | else |
1836 | val |= TRANS_PROGRESSIVE; | |
1837 | ||
040484af | 1838 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1839 | if (intel_wait_for_register(dev_priv, |
1840 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1841 | 100)) | |
4bb6f1f3 | 1842 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1843 | } |
1844 | ||
8fb033d7 | 1845 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1846 | enum transcoder cpu_transcoder) |
040484af | 1847 | { |
8fb033d7 | 1848 | u32 val, pipeconf_val; |
8fb033d7 | 1849 | |
8fb033d7 | 1850 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1851 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1852 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1853 | |
223a6fdf | 1854 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1855 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1856 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1857 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1858 | |
25f3ef11 | 1859 | val = TRANS_ENABLE; |
937bb610 | 1860 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1861 | |
9a76b1c6 PZ |
1862 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1863 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1864 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1865 | else |
1866 | val |= TRANS_PROGRESSIVE; | |
1867 | ||
ab9412ba | 1868 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1869 | if (intel_wait_for_register(dev_priv, |
1870 | LPT_TRANSCONF, | |
1871 | TRANS_STATE_ENABLE, | |
1872 | TRANS_STATE_ENABLE, | |
1873 | 100)) | |
937bb610 | 1874 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1875 | } |
1876 | ||
b8a4f404 PZ |
1877 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1878 | enum pipe pipe) | |
040484af | 1879 | { |
91c8a326 | 1880 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 VS |
1881 | i915_reg_t reg; |
1882 | uint32_t val; | |
040484af JB |
1883 | |
1884 | /* FDI relies on the transcoder */ | |
1885 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1886 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1887 | ||
291906f1 JB |
1888 | /* Ports must be off as well */ |
1889 | assert_pch_ports_disabled(dev_priv, pipe); | |
1890 | ||
ab9412ba | 1891 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1892 | val = I915_READ(reg); |
1893 | val &= ~TRANS_ENABLE; | |
1894 | I915_WRITE(reg, val); | |
1895 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1896 | if (intel_wait_for_register(dev_priv, |
1897 | reg, TRANS_STATE_ENABLE, 0, | |
1898 | 50)) | |
4bb6f1f3 | 1899 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1900 | |
c465613b | 1901 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1902 | /* Workaround: Clear the timing override chicken bit again. */ |
1903 | reg = TRANS_CHICKEN2(pipe); | |
1904 | val = I915_READ(reg); | |
1905 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1906 | I915_WRITE(reg, val); | |
1907 | } | |
040484af JB |
1908 | } |
1909 | ||
ab4d966c | 1910 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1911 | { |
8fb033d7 PZ |
1912 | u32 val; |
1913 | ||
ab9412ba | 1914 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1915 | val &= ~TRANS_ENABLE; |
ab9412ba | 1916 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1917 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1918 | if (intel_wait_for_register(dev_priv, |
1919 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1920 | 50)) | |
8a52fd9f | 1921 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1922 | |
1923 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1924 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1925 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1926 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1927 | } |
1928 | ||
b24e7179 | 1929 | /** |
309cfea8 | 1930 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1931 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1932 | * |
0372264a | 1933 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1934 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1935 | */ |
e1fdc473 | 1936 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1937 | { |
0372264a | 1938 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1939 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1940 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1941 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1942 | enum pipe pch_transcoder; |
f0f59a00 | 1943 | i915_reg_t reg; |
b24e7179 JB |
1944 | u32 val; |
1945 | ||
9e2ee2dd VS |
1946 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1947 | ||
58c6eaa2 | 1948 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1949 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1950 | assert_sprites_disabled(dev_priv, pipe); |
1951 | ||
2d1fe073 | 1952 | if (HAS_PCH_LPT(dev_priv)) |
cc391bbb PZ |
1953 | pch_transcoder = TRANSCODER_A; |
1954 | else | |
1955 | pch_transcoder = pipe; | |
1956 | ||
b24e7179 JB |
1957 | /* |
1958 | * A pipe without a PLL won't actually be able to drive bits from | |
1959 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1960 | * need the check. | |
1961 | */ | |
09fa8bb9 | 1962 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1963 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1964 | assert_dsi_pll_enabled(dev_priv); |
1965 | else | |
1966 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1967 | } else { |
6e3c9717 | 1968 | if (crtc->config->has_pch_encoder) { |
040484af | 1969 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1970 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1971 | assert_fdi_tx_pll_enabled(dev_priv, |
1972 | (enum pipe) cpu_transcoder); | |
040484af JB |
1973 | } |
1974 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1975 | } | |
b24e7179 | 1976 | |
702e7a56 | 1977 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1978 | val = I915_READ(reg); |
7ad25d48 | 1979 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1980 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1981 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1982 | return; |
7ad25d48 | 1983 | } |
00d70b15 CW |
1984 | |
1985 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1986 | POSTING_READ(reg); |
b7792d8b VS |
1987 | |
1988 | /* | |
1989 | * Until the pipe starts DSL will read as 0, which would cause | |
1990 | * an apparent vblank timestamp jump, which messes up also the | |
1991 | * frame count when it's derived from the timestamps. So let's | |
1992 | * wait for the pipe to start properly before we call | |
1993 | * drm_crtc_vblank_on() | |
1994 | */ | |
1995 | if (dev->max_vblank_count == 0 && | |
1996 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1997 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1998 | } |
1999 | ||
2000 | /** | |
309cfea8 | 2001 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2002 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2003 | * |
575f7ab7 VS |
2004 | * Disable the pipe of @crtc, making sure that various hardware |
2005 | * specific requirements are met, if applicable, e.g. plane | |
2006 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2007 | * |
2008 | * Will wait until the pipe has shut down before returning. | |
2009 | */ | |
575f7ab7 | 2010 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2011 | { |
fac5e23e | 2012 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 2013 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2014 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2015 | i915_reg_t reg; |
b24e7179 JB |
2016 | u32 val; |
2017 | ||
9e2ee2dd VS |
2018 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2019 | ||
b24e7179 JB |
2020 | /* |
2021 | * Make sure planes won't keep trying to pump pixels to us, | |
2022 | * or we might hang the display. | |
2023 | */ | |
2024 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2025 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2026 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2027 | |
702e7a56 | 2028 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2029 | val = I915_READ(reg); |
00d70b15 CW |
2030 | if ((val & PIPECONF_ENABLE) == 0) |
2031 | return; | |
2032 | ||
67adc644 VS |
2033 | /* |
2034 | * Double wide has implications for planes | |
2035 | * so best keep it disabled when not needed. | |
2036 | */ | |
6e3c9717 | 2037 | if (crtc->config->double_wide) |
67adc644 VS |
2038 | val &= ~PIPECONF_DOUBLE_WIDE; |
2039 | ||
2040 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2041 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2042 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2043 | val &= ~PIPECONF_ENABLE; |
2044 | ||
2045 | I915_WRITE(reg, val); | |
2046 | if ((val & PIPECONF_ENABLE) == 0) | |
2047 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2048 | } |
2049 | ||
832be82f VS |
2050 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2051 | { | |
2052 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2053 | } | |
2054 | ||
27ba3910 VS |
2055 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2056 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2057 | { |
2058 | switch (fb_modifier) { | |
2059 | case DRM_FORMAT_MOD_NONE: | |
2060 | return cpp; | |
2061 | case I915_FORMAT_MOD_X_TILED: | |
2062 | if (IS_GEN2(dev_priv)) | |
2063 | return 128; | |
2064 | else | |
2065 | return 512; | |
2066 | case I915_FORMAT_MOD_Y_TILED: | |
2067 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2068 | return 128; | |
2069 | else | |
2070 | return 512; | |
2071 | case I915_FORMAT_MOD_Yf_TILED: | |
2072 | switch (cpp) { | |
2073 | case 1: | |
2074 | return 64; | |
2075 | case 2: | |
2076 | case 4: | |
2077 | return 128; | |
2078 | case 8: | |
2079 | case 16: | |
2080 | return 256; | |
2081 | default: | |
2082 | MISSING_CASE(cpp); | |
2083 | return cpp; | |
2084 | } | |
2085 | break; | |
2086 | default: | |
2087 | MISSING_CASE(fb_modifier); | |
2088 | return cpp; | |
2089 | } | |
2090 | } | |
2091 | ||
832be82f VS |
2092 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2093 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2094 | { |
832be82f VS |
2095 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2096 | return 1; | |
2097 | else | |
2098 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2099 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2100 | } |
2101 | ||
8d0deca8 VS |
2102 | /* Return the tile dimensions in pixel units */ |
2103 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2104 | unsigned int *tile_width, | |
2105 | unsigned int *tile_height, | |
2106 | uint64_t fb_modifier, | |
2107 | unsigned int cpp) | |
2108 | { | |
2109 | unsigned int tile_width_bytes = | |
2110 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2111 | ||
2112 | *tile_width = tile_width_bytes / cpp; | |
2113 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2114 | } | |
2115 | ||
6761dd31 TU |
2116 | unsigned int |
2117 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2118 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2119 | { |
832be82f VS |
2120 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2121 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2122 | ||
2123 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2124 | } |
2125 | ||
1663b9d6 VS |
2126 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2127 | { | |
2128 | unsigned int size = 0; | |
2129 | int i; | |
2130 | ||
2131 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2132 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2133 | ||
2134 | return size; | |
2135 | } | |
2136 | ||
75c82a53 | 2137 | static void |
3465c580 VS |
2138 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2139 | const struct drm_framebuffer *fb, | |
2140 | unsigned int rotation) | |
f64b98cd | 2141 | { |
2d7a215f VS |
2142 | if (intel_rotation_90_or_270(rotation)) { |
2143 | *view = i915_ggtt_view_rotated; | |
2144 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2145 | } else { | |
2146 | *view = i915_ggtt_view_normal; | |
2147 | } | |
2148 | } | |
50470bb0 | 2149 | |
603525d7 | 2150 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2151 | { |
2152 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2153 | return 256 * 1024; | |
985b8bb4 | 2154 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2155 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2156 | return 128 * 1024; |
2157 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2158 | return 4 * 1024; | |
2159 | else | |
44c5905e | 2160 | return 0; |
4e9a86b6 VS |
2161 | } |
2162 | ||
603525d7 VS |
2163 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2164 | uint64_t fb_modifier) | |
2165 | { | |
2166 | switch (fb_modifier) { | |
2167 | case DRM_FORMAT_MOD_NONE: | |
2168 | return intel_linear_alignment(dev_priv); | |
2169 | case I915_FORMAT_MOD_X_TILED: | |
2170 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2171 | return 256 * 1024; | |
2172 | return 0; | |
2173 | case I915_FORMAT_MOD_Y_TILED: | |
2174 | case I915_FORMAT_MOD_Yf_TILED: | |
2175 | return 1 * 1024 * 1024; | |
2176 | default: | |
2177 | MISSING_CASE(fb_modifier); | |
2178 | return 0; | |
2179 | } | |
2180 | } | |
2181 | ||
127bd2ac | 2182 | int |
3465c580 VS |
2183 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2184 | unsigned int rotation) | |
6b95a207 | 2185 | { |
850c4cdc | 2186 | struct drm_device *dev = fb->dev; |
fac5e23e | 2187 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2188 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2189 | struct i915_ggtt_view view; |
6b95a207 KH |
2190 | u32 alignment; |
2191 | int ret; | |
2192 | ||
ebcdd39e MR |
2193 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2194 | ||
603525d7 | 2195 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2196 | |
3465c580 | 2197 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2198 | |
693db184 CW |
2199 | /* Note that the w/a also requires 64 PTE of padding following the |
2200 | * bo. We currently fill all unused PTE with the shadow page and so | |
2201 | * we should always have valid PTE following the scanout preventing | |
2202 | * the VT-d warning. | |
2203 | */ | |
48f112fe | 2204 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2205 | alignment = 256 * 1024; |
2206 | ||
d6dd6843 PZ |
2207 | /* |
2208 | * Global gtt pte registers are special registers which actually forward | |
2209 | * writes to a chunk of system memory. Which means that there is no risk | |
2210 | * that the register values disappear as soon as we call | |
2211 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2212 | * pin/unpin/fence and not more. | |
2213 | */ | |
2214 | intel_runtime_pm_get(dev_priv); | |
2215 | ||
7580d774 ML |
2216 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2217 | &view); | |
48b956c5 | 2218 | if (ret) |
b26a6b35 | 2219 | goto err_pm; |
6b95a207 KH |
2220 | |
2221 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2222 | * fence, whereas 965+ only requires a fence if using | |
2223 | * framebuffer compression. For simplicity, we always install | |
2224 | * a fence as the cost is not that onerous. | |
2225 | */ | |
9807216f VK |
2226 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2227 | ret = i915_gem_object_get_fence(obj); | |
2228 | if (ret == -EDEADLK) { | |
2229 | /* | |
2230 | * -EDEADLK means there are no free fences | |
2231 | * no pending flips. | |
2232 | * | |
2233 | * This is propagated to atomic, but it uses | |
2234 | * -EDEADLK to force a locking recovery, so | |
2235 | * change the returned error to -EBUSY. | |
2236 | */ | |
2237 | ret = -EBUSY; | |
2238 | goto err_unpin; | |
2239 | } else if (ret) | |
2240 | goto err_unpin; | |
1690e1eb | 2241 | |
9807216f VK |
2242 | i915_gem_object_pin_fence(obj); |
2243 | } | |
6b95a207 | 2244 | |
d6dd6843 | 2245 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2246 | return 0; |
48b956c5 CW |
2247 | |
2248 | err_unpin: | |
f64b98cd | 2249 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2250 | err_pm: |
d6dd6843 | 2251 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2252 | return ret; |
6b95a207 KH |
2253 | } |
2254 | ||
fb4b8ce1 | 2255 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2256 | { |
82bc3b2d | 2257 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2258 | struct i915_ggtt_view view; |
82bc3b2d | 2259 | |
ebcdd39e MR |
2260 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2261 | ||
3465c580 | 2262 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2263 | |
9807216f VK |
2264 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2265 | i915_gem_object_unpin_fence(obj); | |
2266 | ||
f64b98cd | 2267 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2268 | } |
2269 | ||
6687c906 VS |
2270 | /* |
2271 | * Convert the x/y offsets into a linear offset. | |
2272 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2273 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2274 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2275 | */ | |
2276 | u32 intel_fb_xy_to_linear(int x, int y, | |
2277 | const struct drm_framebuffer *fb, int plane) | |
2278 | { | |
2279 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2280 | unsigned int pitch = fb->pitches[plane]; | |
2281 | ||
2282 | return y * pitch + x * cpp; | |
2283 | } | |
2284 | ||
2285 | /* | |
2286 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2287 | * specified plane src x/y offsets. The resulting x/y offsets | |
2288 | * specify the start of scanout from the beginning of the gtt mapping. | |
2289 | */ | |
2290 | void intel_add_fb_offsets(int *x, int *y, | |
2291 | const struct drm_framebuffer *fb, int plane, | |
2292 | unsigned int rotation) | |
2293 | ||
2294 | { | |
2295 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2296 | ||
2297 | if (intel_rotation_90_or_270(rotation)) { | |
2298 | *x += intel_fb->rotated[plane].x; | |
2299 | *y += intel_fb->rotated[plane].y; | |
2300 | } else { | |
2301 | *x += intel_fb->normal[plane].x; | |
2302 | *y += intel_fb->normal[plane].y; | |
2303 | } | |
2304 | } | |
2305 | ||
29cf9491 VS |
2306 | /* |
2307 | * Adjust the tile offset by moving the difference into | |
2308 | * the x/y offsets. | |
2309 | * | |
2310 | * Input tile dimensions and pitch must already be | |
2311 | * rotated to match x and y, and in pixel units. | |
2312 | */ | |
2313 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2314 | unsigned int tile_width, | |
2315 | unsigned int tile_height, | |
2316 | unsigned int tile_size, | |
2317 | unsigned int pitch_tiles, | |
2318 | u32 old_offset, | |
2319 | u32 new_offset) | |
2320 | { | |
2321 | unsigned int tiles; | |
2322 | ||
2323 | WARN_ON(old_offset & (tile_size - 1)); | |
2324 | WARN_ON(new_offset & (tile_size - 1)); | |
2325 | WARN_ON(new_offset > old_offset); | |
2326 | ||
2327 | tiles = (old_offset - new_offset) / tile_size; | |
2328 | ||
2329 | *y += tiles / pitch_tiles * tile_height; | |
2330 | *x += tiles % pitch_tiles * tile_width; | |
2331 | ||
2332 | return new_offset; | |
2333 | } | |
2334 | ||
8d0deca8 VS |
2335 | /* |
2336 | * Computes the linear offset to the base tile and adjusts | |
2337 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2338 | * | |
2339 | * In the 90/270 rotated case, x and y are assumed | |
2340 | * to be already rotated to match the rotated GTT view, and | |
2341 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2342 | * |
2343 | * This function is used when computing the derived information | |
2344 | * under intel_framebuffer, so using any of that information | |
2345 | * here is not allowed. Anything under drm_framebuffer can be | |
2346 | * used. This is why the user has to pass in the pitch since it | |
2347 | * is specified in the rotated orientation. | |
8d0deca8 | 2348 | */ |
6687c906 VS |
2349 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2350 | int *x, int *y, | |
2351 | const struct drm_framebuffer *fb, int plane, | |
2352 | unsigned int pitch, | |
2353 | unsigned int rotation, | |
2354 | u32 alignment) | |
c2c75131 | 2355 | { |
4f2d9934 VS |
2356 | uint64_t fb_modifier = fb->modifier[plane]; |
2357 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
6687c906 | 2358 | u32 offset, offset_aligned; |
29cf9491 | 2359 | |
29cf9491 VS |
2360 | if (alignment) |
2361 | alignment--; | |
2362 | ||
b5c65338 | 2363 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2364 | unsigned int tile_size, tile_width, tile_height; |
2365 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2366 | |
d843310d | 2367 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2368 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2369 | fb_modifier, cpp); | |
2370 | ||
2371 | if (intel_rotation_90_or_270(rotation)) { | |
2372 | pitch_tiles = pitch / tile_height; | |
2373 | swap(tile_width, tile_height); | |
2374 | } else { | |
2375 | pitch_tiles = pitch / (tile_width * cpp); | |
2376 | } | |
d843310d VS |
2377 | |
2378 | tile_rows = *y / tile_height; | |
2379 | *y %= tile_height; | |
c2c75131 | 2380 | |
8d0deca8 VS |
2381 | tiles = *x / tile_width; |
2382 | *x %= tile_width; | |
bc752862 | 2383 | |
29cf9491 VS |
2384 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2385 | offset_aligned = offset & ~alignment; | |
bc752862 | 2386 | |
29cf9491 VS |
2387 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2388 | tile_size, pitch_tiles, | |
2389 | offset, offset_aligned); | |
2390 | } else { | |
bc752862 | 2391 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2392 | offset_aligned = offset & ~alignment; |
2393 | ||
4e9a86b6 VS |
2394 | *y = (offset & alignment) / pitch; |
2395 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2396 | } |
29cf9491 VS |
2397 | |
2398 | return offset_aligned; | |
c2c75131 DV |
2399 | } |
2400 | ||
6687c906 VS |
2401 | u32 intel_compute_tile_offset(int *x, int *y, |
2402 | const struct drm_framebuffer *fb, int plane, | |
2403 | unsigned int pitch, | |
2404 | unsigned int rotation) | |
2405 | { | |
2406 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
2407 | u32 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]); | |
2408 | ||
2409 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2410 | rotation, alignment); | |
2411 | } | |
2412 | ||
2413 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2414 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2415 | const struct drm_framebuffer *fb, int plane) | |
2416 | { | |
2417 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2418 | unsigned int pitch = fb->pitches[plane]; | |
2419 | u32 linear_offset = fb->offsets[plane]; | |
2420 | ||
2421 | *y = linear_offset / pitch; | |
2422 | *x = linear_offset % pitch / cpp; | |
2423 | } | |
2424 | ||
2425 | static int | |
2426 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2427 | struct drm_framebuffer *fb) | |
2428 | { | |
2429 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2430 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2431 | u32 gtt_offset_rotated = 0; | |
2432 | unsigned int max_size = 0; | |
2433 | uint32_t format = fb->pixel_format; | |
2434 | int i, num_planes = drm_format_num_planes(format); | |
2435 | unsigned int tile_size = intel_tile_size(dev_priv); | |
2436 | ||
2437 | for (i = 0; i < num_planes; i++) { | |
2438 | unsigned int width, height; | |
2439 | unsigned int cpp, size; | |
2440 | u32 offset; | |
2441 | int x, y; | |
2442 | ||
2443 | cpp = drm_format_plane_cpp(format, i); | |
2444 | width = drm_format_plane_width(fb->width, format, i); | |
2445 | height = drm_format_plane_height(fb->height, format, i); | |
2446 | ||
2447 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2448 | ||
2449 | /* | |
2450 | * First pixel of the framebuffer from | |
2451 | * the start of the normal gtt mapping. | |
2452 | */ | |
2453 | intel_fb->normal[i].x = x; | |
2454 | intel_fb->normal[i].y = y; | |
2455 | ||
2456 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
2457 | fb, 0, fb->pitches[i], | |
2458 | BIT(DRM_ROTATE_0), tile_size); | |
2459 | offset /= tile_size; | |
2460 | ||
2461 | if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) { | |
2462 | unsigned int tile_width, tile_height; | |
2463 | unsigned int pitch_tiles; | |
2464 | struct drm_rect r; | |
2465 | ||
2466 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2467 | fb->modifier[i], cpp); | |
2468 | ||
2469 | rot_info->plane[i].offset = offset; | |
2470 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2471 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2472 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2473 | ||
2474 | intel_fb->rotated[i].pitch = | |
2475 | rot_info->plane[i].height * tile_height; | |
2476 | ||
2477 | /* how many tiles does this plane need */ | |
2478 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2479 | /* | |
2480 | * If the plane isn't horizontally tile aligned, | |
2481 | * we need one more tile. | |
2482 | */ | |
2483 | if (x != 0) | |
2484 | size++; | |
2485 | ||
2486 | /* rotate the x/y offsets to match the GTT view */ | |
2487 | r.x1 = x; | |
2488 | r.y1 = y; | |
2489 | r.x2 = x + width; | |
2490 | r.y2 = y + height; | |
2491 | drm_rect_rotate(&r, | |
2492 | rot_info->plane[i].width * tile_width, | |
2493 | rot_info->plane[i].height * tile_height, | |
2494 | BIT(DRM_ROTATE_270)); | |
2495 | x = r.x1; | |
2496 | y = r.y1; | |
2497 | ||
2498 | /* rotate the tile dimensions to match the GTT view */ | |
2499 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2500 | swap(tile_width, tile_height); | |
2501 | ||
2502 | /* | |
2503 | * We only keep the x/y offsets, so push all of the | |
2504 | * gtt offset into the x/y offsets. | |
2505 | */ | |
2506 | intel_adjust_tile_offset(&x, &y, tile_size, | |
2507 | tile_width, tile_height, pitch_tiles, | |
2508 | gtt_offset_rotated * tile_size, 0); | |
2509 | ||
2510 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2511 | ||
2512 | /* | |
2513 | * First pixel of the framebuffer from | |
2514 | * the start of the rotated gtt mapping. | |
2515 | */ | |
2516 | intel_fb->rotated[i].x = x; | |
2517 | intel_fb->rotated[i].y = y; | |
2518 | } else { | |
2519 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2520 | x * cpp, tile_size); | |
2521 | } | |
2522 | ||
2523 | /* how many tiles in total needed in the bo */ | |
2524 | max_size = max(max_size, offset + size); | |
2525 | } | |
2526 | ||
2527 | if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { | |
2528 | DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2529 | max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); | |
2530 | return -EINVAL; | |
2531 | } | |
2532 | ||
2533 | return 0; | |
2534 | } | |
2535 | ||
b35d63fa | 2536 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2537 | { |
2538 | switch (format) { | |
2539 | case DISPPLANE_8BPP: | |
2540 | return DRM_FORMAT_C8; | |
2541 | case DISPPLANE_BGRX555: | |
2542 | return DRM_FORMAT_XRGB1555; | |
2543 | case DISPPLANE_BGRX565: | |
2544 | return DRM_FORMAT_RGB565; | |
2545 | default: | |
2546 | case DISPPLANE_BGRX888: | |
2547 | return DRM_FORMAT_XRGB8888; | |
2548 | case DISPPLANE_RGBX888: | |
2549 | return DRM_FORMAT_XBGR8888; | |
2550 | case DISPPLANE_BGRX101010: | |
2551 | return DRM_FORMAT_XRGB2101010; | |
2552 | case DISPPLANE_RGBX101010: | |
2553 | return DRM_FORMAT_XBGR2101010; | |
2554 | } | |
2555 | } | |
2556 | ||
bc8d7dff DL |
2557 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2558 | { | |
2559 | switch (format) { | |
2560 | case PLANE_CTL_FORMAT_RGB_565: | |
2561 | return DRM_FORMAT_RGB565; | |
2562 | default: | |
2563 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2564 | if (rgb_order) { | |
2565 | if (alpha) | |
2566 | return DRM_FORMAT_ABGR8888; | |
2567 | else | |
2568 | return DRM_FORMAT_XBGR8888; | |
2569 | } else { | |
2570 | if (alpha) | |
2571 | return DRM_FORMAT_ARGB8888; | |
2572 | else | |
2573 | return DRM_FORMAT_XRGB8888; | |
2574 | } | |
2575 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2576 | if (rgb_order) | |
2577 | return DRM_FORMAT_XBGR2101010; | |
2578 | else | |
2579 | return DRM_FORMAT_XRGB2101010; | |
2580 | } | |
2581 | } | |
2582 | ||
5724dbd1 | 2583 | static bool |
f6936e29 DV |
2584 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2585 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2586 | { |
2587 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2588 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2589 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2590 | struct drm_i915_gem_object *obj = NULL; |
2591 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2592 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2593 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2594 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2595 | PAGE_SIZE); | |
2596 | ||
2597 | size_aligned -= base_aligned; | |
46f297fb | 2598 | |
ff2652ea CW |
2599 | if (plane_config->size == 0) |
2600 | return false; | |
2601 | ||
3badb49f PZ |
2602 | /* If the FB is too big, just don't use it since fbdev is not very |
2603 | * important and we should probably use that space with FBC or other | |
2604 | * features. */ | |
72e96d64 | 2605 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2606 | return false; |
2607 | ||
12c83d99 TU |
2608 | mutex_lock(&dev->struct_mutex); |
2609 | ||
f37b5c2b DV |
2610 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2611 | base_aligned, | |
2612 | base_aligned, | |
2613 | size_aligned); | |
12c83d99 TU |
2614 | if (!obj) { |
2615 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2616 | return false; |
12c83d99 | 2617 | } |
46f297fb | 2618 | |
3e510a8e CW |
2619 | if (plane_config->tiling == I915_TILING_X) |
2620 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2621 | |
6bf129df DL |
2622 | mode_cmd.pixel_format = fb->pixel_format; |
2623 | mode_cmd.width = fb->width; | |
2624 | mode_cmd.height = fb->height; | |
2625 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2626 | mode_cmd.modifier[0] = fb->modifier[0]; |
2627 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2628 | |
6bf129df | 2629 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2630 | &mode_cmd, obj)) { |
46f297fb JB |
2631 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2632 | goto out_unref_obj; | |
2633 | } | |
12c83d99 | 2634 | |
46f297fb | 2635 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2636 | |
f6936e29 | 2637 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2638 | return true; |
46f297fb JB |
2639 | |
2640 | out_unref_obj: | |
f8c417cd | 2641 | i915_gem_object_put(obj); |
46f297fb | 2642 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2643 | return false; |
2644 | } | |
2645 | ||
5a21b665 DV |
2646 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2647 | static void | |
2648 | update_state_fb(struct drm_plane *plane) | |
2649 | { | |
2650 | if (plane->fb == plane->state->fb) | |
2651 | return; | |
2652 | ||
2653 | if (plane->state->fb) | |
2654 | drm_framebuffer_unreference(plane->state->fb); | |
2655 | plane->state->fb = plane->fb; | |
2656 | if (plane->state->fb) | |
2657 | drm_framebuffer_reference(plane->state->fb); | |
2658 | } | |
2659 | ||
5724dbd1 | 2660 | static void |
f6936e29 DV |
2661 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2662 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2663 | { |
2664 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2665 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd JB |
2666 | struct drm_crtc *c; |
2667 | struct intel_crtc *i; | |
2ff8fde1 | 2668 | struct drm_i915_gem_object *obj; |
88595ac9 | 2669 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2670 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2671 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2672 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2673 | struct intel_plane_state *intel_state = |
2674 | to_intel_plane_state(plane_state); | |
88595ac9 | 2675 | struct drm_framebuffer *fb; |
484b41dd | 2676 | |
2d14030b | 2677 | if (!plane_config->fb) |
484b41dd JB |
2678 | return; |
2679 | ||
f6936e29 | 2680 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2681 | fb = &plane_config->fb->base; |
2682 | goto valid_fb; | |
f55548b5 | 2683 | } |
484b41dd | 2684 | |
2d14030b | 2685 | kfree(plane_config->fb); |
484b41dd JB |
2686 | |
2687 | /* | |
2688 | * Failed to alloc the obj, check to see if we should share | |
2689 | * an fb with another CRTC instead | |
2690 | */ | |
70e1e0ec | 2691 | for_each_crtc(dev, c) { |
484b41dd JB |
2692 | i = to_intel_crtc(c); |
2693 | ||
2694 | if (c == &intel_crtc->base) | |
2695 | continue; | |
2696 | ||
2ff8fde1 MR |
2697 | if (!i->active) |
2698 | continue; | |
2699 | ||
88595ac9 DV |
2700 | fb = c->primary->fb; |
2701 | if (!fb) | |
484b41dd JB |
2702 | continue; |
2703 | ||
88595ac9 | 2704 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2705 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2706 | drm_framebuffer_reference(fb); |
2707 | goto valid_fb; | |
484b41dd JB |
2708 | } |
2709 | } | |
88595ac9 | 2710 | |
200757f5 MR |
2711 | /* |
2712 | * We've failed to reconstruct the BIOS FB. Current display state | |
2713 | * indicates that the primary plane is visible, but has a NULL FB, | |
2714 | * which will lead to problems later if we don't fix it up. The | |
2715 | * simplest solution is to just disable the primary plane now and | |
2716 | * pretend the BIOS never had it enabled. | |
2717 | */ | |
2718 | to_intel_plane_state(plane_state)->visible = false; | |
2719 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2720 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2721 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2722 | ||
88595ac9 DV |
2723 | return; |
2724 | ||
2725 | valid_fb: | |
f44e2659 VS |
2726 | plane_state->src_x = 0; |
2727 | plane_state->src_y = 0; | |
be5651f2 ML |
2728 | plane_state->src_w = fb->width << 16; |
2729 | plane_state->src_h = fb->height << 16; | |
2730 | ||
f44e2659 VS |
2731 | plane_state->crtc_x = 0; |
2732 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2733 | plane_state->crtc_w = fb->width; |
2734 | plane_state->crtc_h = fb->height; | |
2735 | ||
0a8d8a86 MR |
2736 | intel_state->src.x1 = plane_state->src_x; |
2737 | intel_state->src.y1 = plane_state->src_y; | |
2738 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2739 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2740 | intel_state->dst.x1 = plane_state->crtc_x; | |
2741 | intel_state->dst.y1 = plane_state->crtc_y; | |
2742 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2743 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2744 | ||
88595ac9 | 2745 | obj = intel_fb_obj(fb); |
3e510a8e | 2746 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2747 | dev_priv->preserve_bios_swizzle = true; |
2748 | ||
be5651f2 ML |
2749 | drm_framebuffer_reference(fb); |
2750 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2751 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2752 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
faf5bf0a CW |
2753 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2754 | &obj->frontbuffer_bits); | |
46f297fb JB |
2755 | } |
2756 | ||
a8d201af ML |
2757 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2758 | const struct intel_crtc_state *crtc_state, | |
2759 | const struct intel_plane_state *plane_state) | |
81255565 | 2760 | { |
a8d201af | 2761 | struct drm_device *dev = primary->dev; |
fac5e23e | 2762 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2763 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2764 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2765 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2766 | int plane = intel_crtc->plane; |
54ea9da8 | 2767 | u32 linear_offset; |
81255565 | 2768 | u32 dspcntr; |
f0f59a00 | 2769 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2770 | unsigned int rotation = plane_state->base.rotation; |
54ea9da8 VS |
2771 | int x = plane_state->src.x1 >> 16; |
2772 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2773 | |
f45651ba VS |
2774 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2775 | ||
fdd508a6 | 2776 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2777 | |
2778 | if (INTEL_INFO(dev)->gen < 4) { | |
2779 | if (intel_crtc->pipe == PIPE_B) | |
2780 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2781 | ||
2782 | /* pipesrc and dspsize control the size that is scaled from, | |
2783 | * which should always be the user's requested size. | |
2784 | */ | |
2785 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2786 | ((crtc_state->pipe_src_h - 1) << 16) | |
2787 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2788 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2789 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2790 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2791 | ((crtc_state->pipe_src_h - 1) << 16) | |
2792 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2793 | I915_WRITE(PRIMPOS(plane), 0); |
2794 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2795 | } |
81255565 | 2796 | |
57779d06 VS |
2797 | switch (fb->pixel_format) { |
2798 | case DRM_FORMAT_C8: | |
81255565 JB |
2799 | dspcntr |= DISPPLANE_8BPP; |
2800 | break; | |
57779d06 | 2801 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2802 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2803 | break; |
57779d06 VS |
2804 | case DRM_FORMAT_RGB565: |
2805 | dspcntr |= DISPPLANE_BGRX565; | |
2806 | break; | |
2807 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2808 | dspcntr |= DISPPLANE_BGRX888; |
2809 | break; | |
2810 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2811 | dspcntr |= DISPPLANE_RGBX888; |
2812 | break; | |
2813 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2814 | dspcntr |= DISPPLANE_BGRX101010; |
2815 | break; | |
2816 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2817 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2818 | break; |
2819 | default: | |
baba133a | 2820 | BUG(); |
81255565 | 2821 | } |
57779d06 | 2822 | |
3e510a8e | 2823 | if (INTEL_INFO(dev)->gen >= 4 && i915_gem_object_is_tiled(obj)) |
f45651ba | 2824 | dspcntr |= DISPPLANE_TILED; |
81255565 | 2825 | |
de1aa629 VS |
2826 | if (IS_G4X(dev)) |
2827 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2828 | ||
6687c906 | 2829 | intel_add_fb_offsets(&x, &y, fb, 0, rotation); |
81255565 | 2830 | |
6687c906 | 2831 | if (INTEL_INFO(dev)->gen >= 4) |
c2c75131 | 2832 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2833 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2834 | fb->pitches[0], rotation); |
e506a0c6 | 2835 | |
8d0deca8 | 2836 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2837 | dspcntr |= DISPPLANE_ROTATE_180; |
2838 | ||
a8d201af ML |
2839 | x += (crtc_state->pipe_src_w - 1); |
2840 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2841 | } |
2842 | ||
6687c906 VS |
2843 | linear_offset = intel_fb_xy_to_linear(x, y, fb, 0); |
2844 | ||
2845 | if (INTEL_INFO(dev)->gen < 4) | |
2846 | intel_crtc->dspaddr_offset = linear_offset; | |
2847 | ||
2db3366b PZ |
2848 | intel_crtc->adjusted_x = x; |
2849 | intel_crtc->adjusted_y = y; | |
2850 | ||
48404c1e SJ |
2851 | I915_WRITE(reg, dspcntr); |
2852 | ||
01f2c773 | 2853 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2854 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d | 2855 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
2856 | intel_fb_gtt_offset(fb, rotation) + |
2857 | intel_crtc->dspaddr_offset); | |
5eddb70b | 2858 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2859 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2860 | } else |
f343c5f6 | 2861 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2862 | POSTING_READ(reg); |
17638cd6 JB |
2863 | } |
2864 | ||
a8d201af ML |
2865 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2866 | struct drm_crtc *crtc) | |
17638cd6 JB |
2867 | { |
2868 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 2869 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 2870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 2871 | int plane = intel_crtc->plane; |
f45651ba | 2872 | |
a8d201af ML |
2873 | I915_WRITE(DSPCNTR(plane), 0); |
2874 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2875 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2876 | else |
2877 | I915_WRITE(DSPADDR(plane), 0); | |
2878 | POSTING_READ(DSPCNTR(plane)); | |
2879 | } | |
c9ba6fad | 2880 | |
a8d201af ML |
2881 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2882 | const struct intel_crtc_state *crtc_state, | |
2883 | const struct intel_plane_state *plane_state) | |
2884 | { | |
2885 | struct drm_device *dev = primary->dev; | |
fac5e23e | 2886 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2887 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2888 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2889 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2890 | int plane = intel_crtc->plane; | |
54ea9da8 | 2891 | u32 linear_offset; |
a8d201af ML |
2892 | u32 dspcntr; |
2893 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2894 | unsigned int rotation = plane_state->base.rotation; |
a8d201af ML |
2895 | int x = plane_state->src.x1 >> 16; |
2896 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2897 | |
f45651ba | 2898 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2899 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2900 | |
2901 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2902 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2903 | |
57779d06 VS |
2904 | switch (fb->pixel_format) { |
2905 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2906 | dspcntr |= DISPPLANE_8BPP; |
2907 | break; | |
57779d06 VS |
2908 | case DRM_FORMAT_RGB565: |
2909 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2910 | break; |
57779d06 | 2911 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2912 | dspcntr |= DISPPLANE_BGRX888; |
2913 | break; | |
2914 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2915 | dspcntr |= DISPPLANE_RGBX888; |
2916 | break; | |
2917 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2918 | dspcntr |= DISPPLANE_BGRX101010; |
2919 | break; | |
2920 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2921 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2922 | break; |
2923 | default: | |
baba133a | 2924 | BUG(); |
17638cd6 JB |
2925 | } |
2926 | ||
3e510a8e | 2927 | if (i915_gem_object_is_tiled(obj)) |
17638cd6 | 2928 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 2929 | |
f45651ba | 2930 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2931 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2932 | |
6687c906 VS |
2933 | intel_add_fb_offsets(&x, &y, fb, 0, rotation); |
2934 | ||
c2c75131 | 2935 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2936 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2937 | fb->pitches[0], rotation); |
6687c906 | 2938 | |
8d0deca8 | 2939 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2940 | dspcntr |= DISPPLANE_ROTATE_180; |
2941 | ||
2942 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2943 | x += (crtc_state->pipe_src_w - 1); |
2944 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2945 | } |
2946 | } | |
2947 | ||
6687c906 VS |
2948 | linear_offset = intel_fb_xy_to_linear(x, y, fb, 0); |
2949 | ||
2db3366b PZ |
2950 | intel_crtc->adjusted_x = x; |
2951 | intel_crtc->adjusted_y = y; | |
2952 | ||
48404c1e | 2953 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2954 | |
01f2c773 | 2955 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d | 2956 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
2957 | intel_fb_gtt_offset(fb, rotation) + |
2958 | intel_crtc->dspaddr_offset); | |
b3dc685e | 2959 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2960 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2961 | } else { | |
2962 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2963 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2964 | } | |
17638cd6 | 2965 | POSTING_READ(reg); |
17638cd6 JB |
2966 | } |
2967 | ||
7b49f948 VS |
2968 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2969 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2970 | { |
7b49f948 | 2971 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2972 | return 64; |
7b49f948 VS |
2973 | } else { |
2974 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2975 | ||
27ba3910 | 2976 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2977 | } |
2978 | } | |
2979 | ||
6687c906 VS |
2980 | u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, |
2981 | unsigned int rotation) | |
121920fa | 2982 | { |
6687c906 | 2983 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ce7f1728 | 2984 | struct i915_ggtt_view view; |
44eb0cb9 | 2985 | u64 offset; |
121920fa | 2986 | |
6687c906 | 2987 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
dedf278c | 2988 | |
6687c906 | 2989 | offset = i915_gem_obj_ggtt_offset_view(obj, &view); |
dedf278c | 2990 | |
44eb0cb9 MK |
2991 | WARN_ON(upper_32_bits(offset)); |
2992 | ||
2993 | return lower_32_bits(offset); | |
121920fa TU |
2994 | } |
2995 | ||
e435d6e5 ML |
2996 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2997 | { | |
2998 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2999 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3000 | |
3001 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3002 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3003 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3004 | } |
3005 | ||
a1b2278e CK |
3006 | /* |
3007 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3008 | */ | |
0583236e | 3009 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3010 | { |
a1b2278e CK |
3011 | struct intel_crtc_scaler_state *scaler_state; |
3012 | int i; | |
3013 | ||
a1b2278e CK |
3014 | scaler_state = &intel_crtc->config->scaler_state; |
3015 | ||
3016 | /* loop through and disable scalers that aren't in use */ | |
3017 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3018 | if (!scaler_state->scalers[i].in_use) |
3019 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3020 | } |
3021 | } | |
3022 | ||
6156a456 | 3023 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3024 | { |
6156a456 | 3025 | switch (pixel_format) { |
d161cf7a | 3026 | case DRM_FORMAT_C8: |
c34ce3d1 | 3027 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3028 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3029 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3030 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3031 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3032 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3033 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3034 | /* |
3035 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3036 | * to be already pre-multiplied. We need to add a knob (or a different | |
3037 | * DRM_FORMAT) for user-space to configure that. | |
3038 | */ | |
f75fb42a | 3039 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3040 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3041 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3042 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3043 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3044 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3045 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3046 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3047 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3048 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3049 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3050 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3051 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3052 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3053 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3054 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3055 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3056 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3057 | default: |
4249eeef | 3058 | MISSING_CASE(pixel_format); |
70d21f0e | 3059 | } |
8cfcba41 | 3060 | |
c34ce3d1 | 3061 | return 0; |
6156a456 | 3062 | } |
70d21f0e | 3063 | |
6156a456 CK |
3064 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3065 | { | |
6156a456 | 3066 | switch (fb_modifier) { |
30af77c4 | 3067 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3068 | break; |
30af77c4 | 3069 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3070 | return PLANE_CTL_TILED_X; |
b321803d | 3071 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3072 | return PLANE_CTL_TILED_Y; |
b321803d | 3073 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3074 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3075 | default: |
6156a456 | 3076 | MISSING_CASE(fb_modifier); |
70d21f0e | 3077 | } |
8cfcba41 | 3078 | |
c34ce3d1 | 3079 | return 0; |
6156a456 | 3080 | } |
70d21f0e | 3081 | |
6156a456 CK |
3082 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3083 | { | |
3b7a5119 | 3084 | switch (rotation) { |
6156a456 CK |
3085 | case BIT(DRM_ROTATE_0): |
3086 | break; | |
1e8df167 SJ |
3087 | /* |
3088 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3089 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3090 | */ | |
3b7a5119 | 3091 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3092 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3093 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3094 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3095 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3096 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3097 | default: |
3098 | MISSING_CASE(rotation); | |
3099 | } | |
3100 | ||
c34ce3d1 | 3101 | return 0; |
6156a456 CK |
3102 | } |
3103 | ||
a8d201af ML |
3104 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3105 | const struct intel_crtc_state *crtc_state, | |
3106 | const struct intel_plane_state *plane_state) | |
6156a456 | 3107 | { |
a8d201af | 3108 | struct drm_device *dev = plane->dev; |
fac5e23e | 3109 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3111 | struct drm_framebuffer *fb = plane_state->base.fb; | |
6156a456 CK |
3112 | int pipe = intel_crtc->pipe; |
3113 | u32 plane_ctl, stride_div, stride; | |
a8d201af | 3114 | unsigned int rotation = plane_state->base.rotation; |
44eb0cb9 | 3115 | u32 surf_addr; |
a8d201af ML |
3116 | int scaler_id = plane_state->scaler_id; |
3117 | int src_x = plane_state->src.x1 >> 16; | |
3118 | int src_y = plane_state->src.y1 >> 16; | |
3119 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3120 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3121 | int dst_x = plane_state->dst.x1; | |
3122 | int dst_y = plane_state->dst.y1; | |
3123 | int dst_w = drm_rect_width(&plane_state->dst); | |
3124 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3125 | |
6156a456 CK |
3126 | plane_ctl = PLANE_CTL_ENABLE | |
3127 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3128 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3129 | ||
3130 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3131 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3132 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3133 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3134 | ||
3b7a5119 | 3135 | if (intel_rotation_90_or_270(rotation)) { |
6687c906 VS |
3136 | struct drm_rect r = { |
3137 | .x1 = src_x, | |
3138 | .x2 = src_x + src_w, | |
3139 | .y1 = src_y, | |
3140 | .y2 = src_y + src_h, | |
3141 | }; | |
832be82f | 3142 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
6687c906 VS |
3143 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
3144 | ||
3145 | /* Rotate src coordinates to match rotated GTT view */ | |
3146 | drm_rect_rotate(&r, fb->width, fb->height, BIT(DRM_ROTATE_270)); | |
832be82f | 3147 | |
6687c906 VS |
3148 | src_x = r.x1; |
3149 | src_y = r.y1; | |
3150 | src_w = drm_rect_width(&r); | |
3151 | src_h = drm_rect_height(&r); | |
3152 | ||
3153 | stride_div = intel_tile_height(dev_priv, fb->modifier[0], cpp); | |
3154 | stride = intel_fb->rotated[0].pitch; | |
3b7a5119 | 3155 | } else { |
6687c906 VS |
3156 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
3157 | fb->pixel_format); | |
3158 | stride = fb->pitches[0]; | |
3b7a5119 | 3159 | } |
b321803d | 3160 | |
6687c906 VS |
3161 | intel_add_fb_offsets(&src_x, &src_y, fb, 0, rotation); |
3162 | surf_addr = intel_compute_tile_offset(&src_x, &src_y, fb, 0, | |
3163 | stride, rotation); | |
3164 | ||
3165 | /* Sizes are 0 based */ | |
3166 | src_w--; | |
3167 | src_h--; | |
3168 | dst_w--; | |
3169 | dst_h--; | |
3170 | ||
3171 | intel_crtc->adjusted_x = src_x; | |
3172 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3173 | |
70d21f0e | 3174 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
6687c906 VS |
3175 | I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x); |
3176 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride / stride_div); | |
3177 | I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w); | |
6156a456 CK |
3178 | |
3179 | if (scaler_id >= 0) { | |
3180 | uint32_t ps_ctrl = 0; | |
3181 | ||
3182 | WARN_ON(!dst_w || !dst_h); | |
3183 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3184 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3185 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3186 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3187 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3188 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3189 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3190 | } else { | |
3191 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3192 | } | |
3193 | ||
6687c906 VS |
3194 | I915_WRITE(PLANE_SURF(pipe, 0), |
3195 | intel_fb_gtt_offset(fb, rotation) + surf_addr); | |
70d21f0e DL |
3196 | |
3197 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3198 | } | |
3199 | ||
a8d201af ML |
3200 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3201 | struct drm_crtc *crtc) | |
17638cd6 JB |
3202 | { |
3203 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3204 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af | 3205 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3206 | |
a8d201af ML |
3207 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3208 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3209 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3210 | } | |
29b9bde6 | 3211 | |
a8d201af ML |
3212 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3213 | static int | |
3214 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3215 | int x, int y, enum mode_set_atomic state) | |
3216 | { | |
3217 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3218 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3219 | ||
3220 | return -ENODEV; | |
81255565 JB |
3221 | } |
3222 | ||
5a21b665 DV |
3223 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3224 | { | |
3225 | struct intel_crtc *crtc; | |
3226 | ||
91c8a326 | 3227 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3228 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3229 | } | |
3230 | ||
7514747d VS |
3231 | static void intel_update_primary_planes(struct drm_device *dev) |
3232 | { | |
7514747d | 3233 | struct drm_crtc *crtc; |
96a02917 | 3234 | |
70e1e0ec | 3235 | for_each_crtc(dev, crtc) { |
11c22da6 | 3236 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3237 | struct intel_plane_state *plane_state = |
3238 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3239 | |
a8d201af ML |
3240 | if (plane_state->visible) |
3241 | plane->update_plane(&plane->base, | |
3242 | to_intel_crtc_state(crtc->state), | |
3243 | plane_state); | |
73974893 ML |
3244 | } |
3245 | } | |
3246 | ||
3247 | static int | |
3248 | __intel_display_resume(struct drm_device *dev, | |
3249 | struct drm_atomic_state *state) | |
3250 | { | |
3251 | struct drm_crtc_state *crtc_state; | |
3252 | struct drm_crtc *crtc; | |
3253 | int i, ret; | |
11c22da6 | 3254 | |
73974893 ML |
3255 | intel_modeset_setup_hw_state(dev); |
3256 | i915_redisable_vga(dev); | |
3257 | ||
3258 | if (!state) | |
3259 | return 0; | |
3260 | ||
3261 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3262 | /* | |
3263 | * Force recalculation even if we restore | |
3264 | * current state. With fast modeset this may not result | |
3265 | * in a modeset when the state is compatible. | |
3266 | */ | |
3267 | crtc_state->mode_changed = true; | |
96a02917 | 3268 | } |
73974893 ML |
3269 | |
3270 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
3271 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
3272 | ||
3273 | ret = drm_atomic_commit(state); | |
3274 | ||
3275 | WARN_ON(ret == -EDEADLK); | |
3276 | return ret; | |
96a02917 VS |
3277 | } |
3278 | ||
4ac2ba2f VS |
3279 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3280 | { | |
ae98104b VS |
3281 | return intel_has_gpu_reset(dev_priv) && |
3282 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3283 | } |
3284 | ||
c033666a | 3285 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3286 | { |
73974893 ML |
3287 | struct drm_device *dev = &dev_priv->drm; |
3288 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3289 | struct drm_atomic_state *state; | |
3290 | int ret; | |
3291 | ||
73974893 ML |
3292 | /* |
3293 | * Need mode_config.mutex so that we don't | |
3294 | * trample ongoing ->detect() and whatnot. | |
3295 | */ | |
3296 | mutex_lock(&dev->mode_config.mutex); | |
3297 | drm_modeset_acquire_init(ctx, 0); | |
3298 | while (1) { | |
3299 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3300 | if (ret != -EDEADLK) | |
3301 | break; | |
3302 | ||
3303 | drm_modeset_backoff(ctx); | |
3304 | } | |
3305 | ||
3306 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3307 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3308 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3309 | return; |
3310 | ||
f98ce92f VS |
3311 | /* |
3312 | * Disabling the crtcs gracefully seems nicer. Also the | |
3313 | * g33 docs say we should at least disable all the planes. | |
3314 | */ | |
73974893 ML |
3315 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3316 | if (IS_ERR(state)) { | |
3317 | ret = PTR_ERR(state); | |
3318 | state = NULL; | |
3319 | DRM_ERROR("Duplicating state failed with %i\n", ret); | |
3320 | goto err; | |
3321 | } | |
3322 | ||
3323 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3324 | if (ret) { | |
3325 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
3326 | goto err; | |
3327 | } | |
3328 | ||
3329 | dev_priv->modeset_restore_state = state; | |
3330 | state->acquire_ctx = ctx; | |
3331 | return; | |
3332 | ||
3333 | err: | |
3334 | drm_atomic_state_free(state); | |
7514747d VS |
3335 | } |
3336 | ||
c033666a | 3337 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3338 | { |
73974893 ML |
3339 | struct drm_device *dev = &dev_priv->drm; |
3340 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3341 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3342 | int ret; | |
3343 | ||
5a21b665 DV |
3344 | /* |
3345 | * Flips in the rings will be nuked by the reset, | |
3346 | * so complete all pending flips so that user space | |
3347 | * will get its events and not get stuck. | |
3348 | */ | |
3349 | intel_complete_page_flips(dev_priv); | |
3350 | ||
73974893 ML |
3351 | dev_priv->modeset_restore_state = NULL; |
3352 | ||
7514747d | 3353 | /* reset doesn't touch the display */ |
4ac2ba2f | 3354 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3355 | if (!state) { |
3356 | /* | |
3357 | * Flips in the rings have been nuked by the reset, | |
3358 | * so update the base address of all primary | |
3359 | * planes to the the last fb to make sure we're | |
3360 | * showing the correct fb after a reset. | |
3361 | * | |
3362 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3363 | * CS-based flips (which might get lost in gpu resets) any more. | |
3364 | */ | |
3365 | intel_update_primary_planes(dev); | |
3366 | } else { | |
3367 | ret = __intel_display_resume(dev, state); | |
3368 | if (ret) | |
3369 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3370 | } | |
73974893 ML |
3371 | } else { |
3372 | /* | |
3373 | * The display has been reset as well, | |
3374 | * so need a full re-initialization. | |
3375 | */ | |
3376 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3377 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3378 | |
73974893 | 3379 | intel_modeset_init_hw(dev); |
7514747d | 3380 | |
73974893 ML |
3381 | spin_lock_irq(&dev_priv->irq_lock); |
3382 | if (dev_priv->display.hpd_irq_setup) | |
3383 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3384 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3385 | |
73974893 ML |
3386 | ret = __intel_display_resume(dev, state); |
3387 | if (ret) | |
3388 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3389 | |
73974893 ML |
3390 | intel_hpd_init(dev_priv); |
3391 | } | |
7514747d | 3392 | |
73974893 ML |
3393 | drm_modeset_drop_locks(ctx); |
3394 | drm_modeset_acquire_fini(ctx); | |
3395 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3396 | } |
3397 | ||
7d5e3799 CW |
3398 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3399 | { | |
5a21b665 DV |
3400 | struct drm_device *dev = crtc->dev; |
3401 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3402 | unsigned reset_counter; | |
3403 | bool pending; | |
3404 | ||
3405 | reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error); | |
3406 | if (intel_crtc->reset_counter != reset_counter) | |
3407 | return false; | |
3408 | ||
3409 | spin_lock_irq(&dev->event_lock); | |
3410 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3411 | spin_unlock_irq(&dev->event_lock); | |
3412 | ||
3413 | return pending; | |
7d5e3799 CW |
3414 | } |
3415 | ||
bfd16b2a ML |
3416 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3417 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3418 | { |
3419 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 3420 | struct drm_i915_private *dev_priv = to_i915(dev); |
bfd16b2a ML |
3421 | struct intel_crtc_state *pipe_config = |
3422 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3423 | |
bfd16b2a ML |
3424 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3425 | crtc->base.mode = crtc->base.state->mode; | |
3426 | ||
3427 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3428 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3429 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3430 | |
3431 | /* | |
3432 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3433 | * that in compute_mode_changes we check the native mode (not the pfit | |
3434 | * mode) to see if we can flip rather than do a full mode set. In the | |
3435 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3436 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3437 | * sized surface. | |
e30e8f75 GP |
3438 | */ |
3439 | ||
e30e8f75 | 3440 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3441 | ((pipe_config->pipe_src_w - 1) << 16) | |
3442 | (pipe_config->pipe_src_h - 1)); | |
3443 | ||
3444 | /* on skylake this is done by detaching scalers */ | |
3445 | if (INTEL_INFO(dev)->gen >= 9) { | |
3446 | skl_detach_scalers(crtc); | |
3447 | ||
3448 | if (pipe_config->pch_pfit.enabled) | |
3449 | skylake_pfit_enable(crtc); | |
3450 | } else if (HAS_PCH_SPLIT(dev)) { | |
3451 | if (pipe_config->pch_pfit.enabled) | |
3452 | ironlake_pfit_enable(crtc); | |
3453 | else if (old_crtc_state->pch_pfit.enabled) | |
3454 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3455 | } |
e30e8f75 GP |
3456 | } |
3457 | ||
5e84e1a4 ZW |
3458 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3459 | { | |
3460 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3461 | struct drm_i915_private *dev_priv = to_i915(dev); |
5e84e1a4 ZW |
3462 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3463 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3464 | i915_reg_t reg; |
3465 | u32 temp; | |
5e84e1a4 ZW |
3466 | |
3467 | /* enable normal train */ | |
3468 | reg = FDI_TX_CTL(pipe); | |
3469 | temp = I915_READ(reg); | |
61e499bf | 3470 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3471 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3472 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3473 | } else { |
3474 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3475 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3476 | } |
5e84e1a4 ZW |
3477 | I915_WRITE(reg, temp); |
3478 | ||
3479 | reg = FDI_RX_CTL(pipe); | |
3480 | temp = I915_READ(reg); | |
3481 | if (HAS_PCH_CPT(dev)) { | |
3482 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3483 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3484 | } else { | |
3485 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3486 | temp |= FDI_LINK_TRAIN_NONE; | |
3487 | } | |
3488 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3489 | ||
3490 | /* wait one idle pattern time */ | |
3491 | POSTING_READ(reg); | |
3492 | udelay(1000); | |
357555c0 JB |
3493 | |
3494 | /* IVB wants error correction enabled */ | |
3495 | if (IS_IVYBRIDGE(dev)) | |
3496 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3497 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3498 | } |
3499 | ||
8db9d77b ZW |
3500 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3501 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3502 | { | |
3503 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3504 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3505 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3506 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3507 | i915_reg_t reg; |
3508 | u32 temp, tries; | |
8db9d77b | 3509 | |
1c8562f6 | 3510 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3511 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3512 | |
e1a44743 AJ |
3513 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3514 | for train result */ | |
5eddb70b CW |
3515 | reg = FDI_RX_IMR(pipe); |
3516 | temp = I915_READ(reg); | |
e1a44743 AJ |
3517 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3518 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3519 | I915_WRITE(reg, temp); |
3520 | I915_READ(reg); | |
e1a44743 AJ |
3521 | udelay(150); |
3522 | ||
8db9d77b | 3523 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3524 | reg = FDI_TX_CTL(pipe); |
3525 | temp = I915_READ(reg); | |
627eb5a3 | 3526 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3527 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3528 | temp &= ~FDI_LINK_TRAIN_NONE; |
3529 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3530 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3531 | |
5eddb70b CW |
3532 | reg = FDI_RX_CTL(pipe); |
3533 | temp = I915_READ(reg); | |
8db9d77b ZW |
3534 | temp &= ~FDI_LINK_TRAIN_NONE; |
3535 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3536 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3537 | ||
3538 | POSTING_READ(reg); | |
8db9d77b ZW |
3539 | udelay(150); |
3540 | ||
5b2adf89 | 3541 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3542 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3543 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3544 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3545 | |
5eddb70b | 3546 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3547 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3548 | temp = I915_READ(reg); |
8db9d77b ZW |
3549 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3550 | ||
3551 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3552 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3553 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3554 | break; |
3555 | } | |
8db9d77b | 3556 | } |
e1a44743 | 3557 | if (tries == 5) |
5eddb70b | 3558 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3559 | |
3560 | /* Train 2 */ | |
5eddb70b CW |
3561 | reg = FDI_TX_CTL(pipe); |
3562 | temp = I915_READ(reg); | |
8db9d77b ZW |
3563 | temp &= ~FDI_LINK_TRAIN_NONE; |
3564 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3565 | I915_WRITE(reg, temp); |
8db9d77b | 3566 | |
5eddb70b CW |
3567 | reg = FDI_RX_CTL(pipe); |
3568 | temp = I915_READ(reg); | |
8db9d77b ZW |
3569 | temp &= ~FDI_LINK_TRAIN_NONE; |
3570 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3571 | I915_WRITE(reg, temp); |
8db9d77b | 3572 | |
5eddb70b CW |
3573 | POSTING_READ(reg); |
3574 | udelay(150); | |
8db9d77b | 3575 | |
5eddb70b | 3576 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3577 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3578 | temp = I915_READ(reg); |
8db9d77b ZW |
3579 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3580 | ||
3581 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3582 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3583 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3584 | break; | |
3585 | } | |
8db9d77b | 3586 | } |
e1a44743 | 3587 | if (tries == 5) |
5eddb70b | 3588 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3589 | |
3590 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3591 | |
8db9d77b ZW |
3592 | } |
3593 | ||
0206e353 | 3594 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3595 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3596 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3597 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3598 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3599 | }; | |
3600 | ||
3601 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3602 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3603 | { | |
3604 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3605 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3606 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3607 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3608 | i915_reg_t reg; |
3609 | u32 temp, i, retry; | |
8db9d77b | 3610 | |
e1a44743 AJ |
3611 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3612 | for train result */ | |
5eddb70b CW |
3613 | reg = FDI_RX_IMR(pipe); |
3614 | temp = I915_READ(reg); | |
e1a44743 AJ |
3615 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3616 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3617 | I915_WRITE(reg, temp); |
3618 | ||
3619 | POSTING_READ(reg); | |
e1a44743 AJ |
3620 | udelay(150); |
3621 | ||
8db9d77b | 3622 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3623 | reg = FDI_TX_CTL(pipe); |
3624 | temp = I915_READ(reg); | |
627eb5a3 | 3625 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3626 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3627 | temp &= ~FDI_LINK_TRAIN_NONE; |
3628 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3629 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3630 | /* SNB-B */ | |
3631 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3632 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3633 | |
d74cf324 DV |
3634 | I915_WRITE(FDI_RX_MISC(pipe), |
3635 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3636 | ||
5eddb70b CW |
3637 | reg = FDI_RX_CTL(pipe); |
3638 | temp = I915_READ(reg); | |
8db9d77b ZW |
3639 | if (HAS_PCH_CPT(dev)) { |
3640 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3641 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3642 | } else { | |
3643 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3644 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3645 | } | |
5eddb70b CW |
3646 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3647 | ||
3648 | POSTING_READ(reg); | |
8db9d77b ZW |
3649 | udelay(150); |
3650 | ||
0206e353 | 3651 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3652 | reg = FDI_TX_CTL(pipe); |
3653 | temp = I915_READ(reg); | |
8db9d77b ZW |
3654 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3655 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3656 | I915_WRITE(reg, temp); |
3657 | ||
3658 | POSTING_READ(reg); | |
8db9d77b ZW |
3659 | udelay(500); |
3660 | ||
fa37d39e SP |
3661 | for (retry = 0; retry < 5; retry++) { |
3662 | reg = FDI_RX_IIR(pipe); | |
3663 | temp = I915_READ(reg); | |
3664 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3665 | if (temp & FDI_RX_BIT_LOCK) { | |
3666 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3667 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3668 | break; | |
3669 | } | |
3670 | udelay(50); | |
8db9d77b | 3671 | } |
fa37d39e SP |
3672 | if (retry < 5) |
3673 | break; | |
8db9d77b ZW |
3674 | } |
3675 | if (i == 4) | |
5eddb70b | 3676 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3677 | |
3678 | /* Train 2 */ | |
5eddb70b CW |
3679 | reg = FDI_TX_CTL(pipe); |
3680 | temp = I915_READ(reg); | |
8db9d77b ZW |
3681 | temp &= ~FDI_LINK_TRAIN_NONE; |
3682 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3683 | if (IS_GEN6(dev)) { | |
3684 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3685 | /* SNB-B */ | |
3686 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3687 | } | |
5eddb70b | 3688 | I915_WRITE(reg, temp); |
8db9d77b | 3689 | |
5eddb70b CW |
3690 | reg = FDI_RX_CTL(pipe); |
3691 | temp = I915_READ(reg); | |
8db9d77b ZW |
3692 | if (HAS_PCH_CPT(dev)) { |
3693 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3694 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3695 | } else { | |
3696 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3697 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3698 | } | |
5eddb70b CW |
3699 | I915_WRITE(reg, temp); |
3700 | ||
3701 | POSTING_READ(reg); | |
8db9d77b ZW |
3702 | udelay(150); |
3703 | ||
0206e353 | 3704 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3705 | reg = FDI_TX_CTL(pipe); |
3706 | temp = I915_READ(reg); | |
8db9d77b ZW |
3707 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3708 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3709 | I915_WRITE(reg, temp); |
3710 | ||
3711 | POSTING_READ(reg); | |
8db9d77b ZW |
3712 | udelay(500); |
3713 | ||
fa37d39e SP |
3714 | for (retry = 0; retry < 5; retry++) { |
3715 | reg = FDI_RX_IIR(pipe); | |
3716 | temp = I915_READ(reg); | |
3717 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3718 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3719 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3720 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3721 | break; | |
3722 | } | |
3723 | udelay(50); | |
8db9d77b | 3724 | } |
fa37d39e SP |
3725 | if (retry < 5) |
3726 | break; | |
8db9d77b ZW |
3727 | } |
3728 | if (i == 4) | |
5eddb70b | 3729 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3730 | |
3731 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3732 | } | |
3733 | ||
357555c0 JB |
3734 | /* Manual link training for Ivy Bridge A0 parts */ |
3735 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3736 | { | |
3737 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3738 | struct drm_i915_private *dev_priv = to_i915(dev); |
357555c0 JB |
3739 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3740 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3741 | i915_reg_t reg; |
3742 | u32 temp, i, j; | |
357555c0 JB |
3743 | |
3744 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3745 | for train result */ | |
3746 | reg = FDI_RX_IMR(pipe); | |
3747 | temp = I915_READ(reg); | |
3748 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3749 | temp &= ~FDI_RX_BIT_LOCK; | |
3750 | I915_WRITE(reg, temp); | |
3751 | ||
3752 | POSTING_READ(reg); | |
3753 | udelay(150); | |
3754 | ||
01a415fd DV |
3755 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3756 | I915_READ(FDI_RX_IIR(pipe))); | |
3757 | ||
139ccd3f JB |
3758 | /* Try each vswing and preemphasis setting twice before moving on */ |
3759 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3760 | /* disable first in case we need to retry */ | |
3761 | reg = FDI_TX_CTL(pipe); | |
3762 | temp = I915_READ(reg); | |
3763 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3764 | temp &= ~FDI_TX_ENABLE; | |
3765 | I915_WRITE(reg, temp); | |
357555c0 | 3766 | |
139ccd3f JB |
3767 | reg = FDI_RX_CTL(pipe); |
3768 | temp = I915_READ(reg); | |
3769 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3770 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3771 | temp &= ~FDI_RX_ENABLE; | |
3772 | I915_WRITE(reg, temp); | |
357555c0 | 3773 | |
139ccd3f | 3774 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3775 | reg = FDI_TX_CTL(pipe); |
3776 | temp = I915_READ(reg); | |
139ccd3f | 3777 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3778 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3779 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3780 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3781 | temp |= snb_b_fdi_train_param[j/2]; |
3782 | temp |= FDI_COMPOSITE_SYNC; | |
3783 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3784 | |
139ccd3f JB |
3785 | I915_WRITE(FDI_RX_MISC(pipe), |
3786 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3787 | |
139ccd3f | 3788 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3789 | temp = I915_READ(reg); |
139ccd3f JB |
3790 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3791 | temp |= FDI_COMPOSITE_SYNC; | |
3792 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3793 | |
139ccd3f JB |
3794 | POSTING_READ(reg); |
3795 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3796 | |
139ccd3f JB |
3797 | for (i = 0; i < 4; i++) { |
3798 | reg = FDI_RX_IIR(pipe); | |
3799 | temp = I915_READ(reg); | |
3800 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3801 | |
139ccd3f JB |
3802 | if (temp & FDI_RX_BIT_LOCK || |
3803 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3804 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3805 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3806 | i); | |
3807 | break; | |
3808 | } | |
3809 | udelay(1); /* should be 0.5us */ | |
3810 | } | |
3811 | if (i == 4) { | |
3812 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3813 | continue; | |
3814 | } | |
357555c0 | 3815 | |
139ccd3f | 3816 | /* Train 2 */ |
357555c0 JB |
3817 | reg = FDI_TX_CTL(pipe); |
3818 | temp = I915_READ(reg); | |
139ccd3f JB |
3819 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3820 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3821 | I915_WRITE(reg, temp); | |
3822 | ||
3823 | reg = FDI_RX_CTL(pipe); | |
3824 | temp = I915_READ(reg); | |
3825 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3826 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3827 | I915_WRITE(reg, temp); |
3828 | ||
3829 | POSTING_READ(reg); | |
139ccd3f | 3830 | udelay(2); /* should be 1.5us */ |
357555c0 | 3831 | |
139ccd3f JB |
3832 | for (i = 0; i < 4; i++) { |
3833 | reg = FDI_RX_IIR(pipe); | |
3834 | temp = I915_READ(reg); | |
3835 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3836 | |
139ccd3f JB |
3837 | if (temp & FDI_RX_SYMBOL_LOCK || |
3838 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3839 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3840 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3841 | i); | |
3842 | goto train_done; | |
3843 | } | |
3844 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3845 | } |
139ccd3f JB |
3846 | if (i == 4) |
3847 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3848 | } |
357555c0 | 3849 | |
139ccd3f | 3850 | train_done: |
357555c0 JB |
3851 | DRM_DEBUG_KMS("FDI train done.\n"); |
3852 | } | |
3853 | ||
88cefb6c | 3854 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3855 | { |
88cefb6c | 3856 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 3857 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 3858 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3859 | i915_reg_t reg; |
3860 | u32 temp; | |
c64e311e | 3861 | |
c98e9dcf | 3862 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3863 | reg = FDI_RX_CTL(pipe); |
3864 | temp = I915_READ(reg); | |
627eb5a3 | 3865 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3866 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3867 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3868 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3869 | ||
3870 | POSTING_READ(reg); | |
c98e9dcf JB |
3871 | udelay(200); |
3872 | ||
3873 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3874 | temp = I915_READ(reg); |
3875 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3876 | ||
3877 | POSTING_READ(reg); | |
c98e9dcf JB |
3878 | udelay(200); |
3879 | ||
20749730 PZ |
3880 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3881 | reg = FDI_TX_CTL(pipe); | |
3882 | temp = I915_READ(reg); | |
3883 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3884 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3885 | |
20749730 PZ |
3886 | POSTING_READ(reg); |
3887 | udelay(100); | |
6be4a607 | 3888 | } |
0e23b99d JB |
3889 | } |
3890 | ||
88cefb6c DV |
3891 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3892 | { | |
3893 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3894 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 3895 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3896 | i915_reg_t reg; |
3897 | u32 temp; | |
88cefb6c DV |
3898 | |
3899 | /* Switch from PCDclk to Rawclk */ | |
3900 | reg = FDI_RX_CTL(pipe); | |
3901 | temp = I915_READ(reg); | |
3902 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3903 | ||
3904 | /* Disable CPU FDI TX PLL */ | |
3905 | reg = FDI_TX_CTL(pipe); | |
3906 | temp = I915_READ(reg); | |
3907 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3908 | ||
3909 | POSTING_READ(reg); | |
3910 | udelay(100); | |
3911 | ||
3912 | reg = FDI_RX_CTL(pipe); | |
3913 | temp = I915_READ(reg); | |
3914 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3915 | ||
3916 | /* Wait for the clocks to turn off. */ | |
3917 | POSTING_READ(reg); | |
3918 | udelay(100); | |
3919 | } | |
3920 | ||
0fc932b8 JB |
3921 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3922 | { | |
3923 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3924 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
3925 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3926 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3927 | i915_reg_t reg; |
3928 | u32 temp; | |
0fc932b8 JB |
3929 | |
3930 | /* disable CPU FDI tx and PCH FDI rx */ | |
3931 | reg = FDI_TX_CTL(pipe); | |
3932 | temp = I915_READ(reg); | |
3933 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3934 | POSTING_READ(reg); | |
3935 | ||
3936 | reg = FDI_RX_CTL(pipe); | |
3937 | temp = I915_READ(reg); | |
3938 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3939 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3940 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3941 | ||
3942 | POSTING_READ(reg); | |
3943 | udelay(100); | |
3944 | ||
3945 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3946 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3947 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3948 | |
3949 | /* still set train pattern 1 */ | |
3950 | reg = FDI_TX_CTL(pipe); | |
3951 | temp = I915_READ(reg); | |
3952 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3953 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3954 | I915_WRITE(reg, temp); | |
3955 | ||
3956 | reg = FDI_RX_CTL(pipe); | |
3957 | temp = I915_READ(reg); | |
3958 | if (HAS_PCH_CPT(dev)) { | |
3959 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3960 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3961 | } else { | |
3962 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3963 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3964 | } | |
3965 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3966 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3967 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3968 | I915_WRITE(reg, temp); |
3969 | ||
3970 | POSTING_READ(reg); | |
3971 | udelay(100); | |
3972 | } | |
3973 | ||
5dce5b93 CW |
3974 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3975 | { | |
3976 | struct intel_crtc *crtc; | |
3977 | ||
3978 | /* Note that we don't need to be called with mode_config.lock here | |
3979 | * as our list of CRTC objects is static for the lifetime of the | |
3980 | * device and so cannot disappear as we iterate. Similarly, we can | |
3981 | * happily treat the predicates as racy, atomic checks as userspace | |
3982 | * cannot claim and pin a new fb without at least acquring the | |
3983 | * struct_mutex and so serialising with us. | |
3984 | */ | |
d3fcc808 | 3985 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3986 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3987 | continue; | |
3988 | ||
5a21b665 | 3989 | if (crtc->flip_work) |
5dce5b93 CW |
3990 | intel_wait_for_vblank(dev, crtc->pipe); |
3991 | ||
3992 | return true; | |
3993 | } | |
3994 | ||
3995 | return false; | |
3996 | } | |
3997 | ||
5a21b665 | 3998 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
3999 | { |
4000 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4001 | struct intel_flip_work *work = intel_crtc->flip_work; |
4002 | ||
4003 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4004 | |
4005 | if (work->event) | |
560ce1dc | 4006 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4007 | |
4008 | drm_crtc_vblank_put(&intel_crtc->base); | |
4009 | ||
5a21b665 | 4010 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 4011 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
4012 | |
4013 | trace_i915_flip_complete(intel_crtc->plane, | |
4014 | work->pending_flip_obj); | |
d6bbafa1 CW |
4015 | } |
4016 | ||
5008e874 | 4017 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4018 | { |
0f91128d | 4019 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4020 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4021 | long ret; |
e6c3a2a6 | 4022 | |
2c10d571 | 4023 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4024 | |
4025 | ret = wait_event_interruptible_timeout( | |
4026 | dev_priv->pending_flip_queue, | |
4027 | !intel_crtc_has_pending_flip(crtc), | |
4028 | 60*HZ); | |
4029 | ||
4030 | if (ret < 0) | |
4031 | return ret; | |
4032 | ||
5a21b665 DV |
4033 | if (ret == 0) { |
4034 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4035 | struct intel_flip_work *work; | |
4036 | ||
4037 | spin_lock_irq(&dev->event_lock); | |
4038 | work = intel_crtc->flip_work; | |
4039 | if (work && !is_mmio_work(work)) { | |
4040 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4041 | page_flip_completed(intel_crtc); | |
4042 | } | |
4043 | spin_unlock_irq(&dev->event_lock); | |
4044 | } | |
5bb61643 | 4045 | |
5008e874 | 4046 | return 0; |
e6c3a2a6 CW |
4047 | } |
4048 | ||
060f02d8 VS |
4049 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
4050 | { | |
4051 | u32 temp; | |
4052 | ||
4053 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4054 | ||
4055 | mutex_lock(&dev_priv->sb_lock); | |
4056 | ||
4057 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4058 | temp |= SBI_SSCCTL_DISABLE; | |
4059 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4060 | ||
4061 | mutex_unlock(&dev_priv->sb_lock); | |
4062 | } | |
4063 | ||
e615efe4 ED |
4064 | /* Program iCLKIP clock to the desired frequency */ |
4065 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
4066 | { | |
64b46a06 | 4067 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 4068 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
4069 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4070 | u32 temp; | |
4071 | ||
060f02d8 | 4072 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4073 | |
64b46a06 VS |
4074 | /* The iCLK virtual clock root frequency is in MHz, |
4075 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4076 | * divisors, it is necessary to divide one by another, so we | |
4077 | * convert the virtual clock precision to KHz here for higher | |
4078 | * precision. | |
4079 | */ | |
4080 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4081 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4082 | u32 iclk_pi_range = 64; | |
64b46a06 | 4083 | u32 desired_divisor; |
e615efe4 | 4084 | |
64b46a06 VS |
4085 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4086 | clock << auxdiv); | |
4087 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4088 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4089 | |
64b46a06 VS |
4090 | /* |
4091 | * Near 20MHz is a corner case which is | |
4092 | * out of range for the 7-bit divisor | |
4093 | */ | |
4094 | if (divsel <= 0x7f) | |
4095 | break; | |
e615efe4 ED |
4096 | } |
4097 | ||
4098 | /* This should not happen with any sane values */ | |
4099 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4100 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4101 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4102 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4103 | ||
4104 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4105 | clock, |
e615efe4 ED |
4106 | auxdiv, |
4107 | divsel, | |
4108 | phasedir, | |
4109 | phaseinc); | |
4110 | ||
060f02d8 VS |
4111 | mutex_lock(&dev_priv->sb_lock); |
4112 | ||
e615efe4 | 4113 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4114 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4115 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4116 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4117 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4118 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4119 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4120 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4121 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4122 | |
4123 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4124 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4125 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4126 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4127 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4128 | |
4129 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4130 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4131 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4132 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4133 | |
060f02d8 VS |
4134 | mutex_unlock(&dev_priv->sb_lock); |
4135 | ||
e615efe4 ED |
4136 | /* Wait for initialization time */ |
4137 | udelay(24); | |
4138 | ||
4139 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4140 | } | |
4141 | ||
8802e5b6 VS |
4142 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4143 | { | |
4144 | u32 divsel, phaseinc, auxdiv; | |
4145 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4146 | u32 iclk_pi_range = 64; | |
4147 | u32 desired_divisor; | |
4148 | u32 temp; | |
4149 | ||
4150 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4151 | return 0; | |
4152 | ||
4153 | mutex_lock(&dev_priv->sb_lock); | |
4154 | ||
4155 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4156 | if (temp & SBI_SSCCTL_DISABLE) { | |
4157 | mutex_unlock(&dev_priv->sb_lock); | |
4158 | return 0; | |
4159 | } | |
4160 | ||
4161 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4162 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4163 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4164 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4165 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4166 | ||
4167 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4168 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4169 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4170 | ||
4171 | mutex_unlock(&dev_priv->sb_lock); | |
4172 | ||
4173 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4174 | ||
4175 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4176 | desired_divisor << auxdiv); | |
4177 | } | |
4178 | ||
275f01b2 DV |
4179 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4180 | enum pipe pch_transcoder) | |
4181 | { | |
4182 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4183 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4184 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4185 | |
4186 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4187 | I915_READ(HTOTAL(cpu_transcoder))); | |
4188 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4189 | I915_READ(HBLANK(cpu_transcoder))); | |
4190 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4191 | I915_READ(HSYNC(cpu_transcoder))); | |
4192 | ||
4193 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4194 | I915_READ(VTOTAL(cpu_transcoder))); | |
4195 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4196 | I915_READ(VBLANK(cpu_transcoder))); | |
4197 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4198 | I915_READ(VSYNC(cpu_transcoder))); | |
4199 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4200 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4201 | } | |
4202 | ||
003632d9 | 4203 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4204 | { |
fac5e23e | 4205 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4206 | uint32_t temp; |
4207 | ||
4208 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4209 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4210 | return; |
4211 | ||
4212 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4213 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4214 | ||
003632d9 ACO |
4215 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4216 | if (enable) | |
4217 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4218 | ||
4219 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4220 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4221 | POSTING_READ(SOUTH_CHICKEN1); | |
4222 | } | |
4223 | ||
4224 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4225 | { | |
4226 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4227 | |
4228 | switch (intel_crtc->pipe) { | |
4229 | case PIPE_A: | |
4230 | break; | |
4231 | case PIPE_B: | |
6e3c9717 | 4232 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4233 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4234 | else |
003632d9 | 4235 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4236 | |
4237 | break; | |
4238 | case PIPE_C: | |
003632d9 | 4239 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4240 | |
4241 | break; | |
4242 | default: | |
4243 | BUG(); | |
4244 | } | |
4245 | } | |
4246 | ||
c48b5305 VS |
4247 | /* Return which DP Port should be selected for Transcoder DP control */ |
4248 | static enum port | |
4249 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4250 | { | |
4251 | struct drm_device *dev = crtc->dev; | |
4252 | struct intel_encoder *encoder; | |
4253 | ||
4254 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
cca0502b | 4255 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4256 | encoder->type == INTEL_OUTPUT_EDP) |
4257 | return enc_to_dig_port(&encoder->base)->port; | |
4258 | } | |
4259 | ||
4260 | return -1; | |
4261 | } | |
4262 | ||
f67a559d JB |
4263 | /* |
4264 | * Enable PCH resources required for PCH ports: | |
4265 | * - PCH PLLs | |
4266 | * - FDI training & RX/TX | |
4267 | * - update transcoder timings | |
4268 | * - DP transcoding bits | |
4269 | * - transcoder | |
4270 | */ | |
4271 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4272 | { |
4273 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4274 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e23b99d JB |
4275 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4276 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4277 | u32 temp; |
2c07245f | 4278 | |
ab9412ba | 4279 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4280 | |
1fbc0d78 DV |
4281 | if (IS_IVYBRIDGE(dev)) |
4282 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4283 | ||
cd986abb DV |
4284 | /* Write the TU size bits before fdi link training, so that error |
4285 | * detection works. */ | |
4286 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4287 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4288 | ||
c98e9dcf | 4289 | /* For PCH output, training FDI link */ |
674cf967 | 4290 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4291 | |
3ad8a208 DV |
4292 | /* We need to program the right clock selection before writing the pixel |
4293 | * mutliplier into the DPLL. */ | |
303b81e0 | 4294 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4295 | u32 sel; |
4b645f14 | 4296 | |
c98e9dcf | 4297 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4298 | temp |= TRANS_DPLL_ENABLE(pipe); |
4299 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4300 | if (intel_crtc->config->shared_dpll == |
4301 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4302 | temp |= sel; |
4303 | else | |
4304 | temp &= ~sel; | |
c98e9dcf | 4305 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4306 | } |
5eddb70b | 4307 | |
3ad8a208 DV |
4308 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4309 | * transcoder, and we actually should do this to not upset any PCH | |
4310 | * transcoder that already use the clock when we share it. | |
4311 | * | |
4312 | * Note that enable_shared_dpll tries to do the right thing, but | |
4313 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4314 | * the right LVDS enable sequence. */ | |
85b3894f | 4315 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4316 | |
d9b6cb56 JB |
4317 | /* set transcoder timing, panel must allow it */ |
4318 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4319 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4320 | |
303b81e0 | 4321 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4322 | |
c98e9dcf | 4323 | /* For PCH DP, enable TRANS_DP_CTL */ |
37a5650b | 4324 | if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) { |
9c4edaee VS |
4325 | const struct drm_display_mode *adjusted_mode = |
4326 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4327 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4328 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4329 | temp = I915_READ(reg); |
4330 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4331 | TRANS_DP_SYNC_MASK | |
4332 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4333 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4334 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4335 | |
9c4edaee | 4336 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4337 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4338 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4339 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4340 | |
4341 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4342 | case PORT_B: |
5eddb70b | 4343 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4344 | break; |
c48b5305 | 4345 | case PORT_C: |
5eddb70b | 4346 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4347 | break; |
c48b5305 | 4348 | case PORT_D: |
5eddb70b | 4349 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4350 | break; |
4351 | default: | |
e95d41e1 | 4352 | BUG(); |
32f9d658 | 4353 | } |
2c07245f | 4354 | |
5eddb70b | 4355 | I915_WRITE(reg, temp); |
6be4a607 | 4356 | } |
b52eb4dc | 4357 | |
b8a4f404 | 4358 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4359 | } |
4360 | ||
1507e5bd PZ |
4361 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4362 | { | |
4363 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4364 | struct drm_i915_private *dev_priv = to_i915(dev); |
1507e5bd | 4365 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 4366 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4367 | |
ab9412ba | 4368 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4369 | |
8c52b5e8 | 4370 | lpt_program_iclkip(crtc); |
1507e5bd | 4371 | |
0540e488 | 4372 | /* Set transcoder timing. */ |
275f01b2 | 4373 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4374 | |
937bb610 | 4375 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4376 | } |
4377 | ||
a1520318 | 4378 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4379 | { |
fac5e23e | 4380 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4381 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4382 | u32 temp; |
4383 | ||
4384 | temp = I915_READ(dslreg); | |
4385 | udelay(500); | |
4386 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4387 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4388 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4389 | } |
4390 | } | |
4391 | ||
86adf9d7 ML |
4392 | static int |
4393 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4394 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4395 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4396 | { |
86adf9d7 ML |
4397 | struct intel_crtc_scaler_state *scaler_state = |
4398 | &crtc_state->scaler_state; | |
4399 | struct intel_crtc *intel_crtc = | |
4400 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4401 | int need_scaling; |
6156a456 CK |
4402 | |
4403 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4404 | (src_h != dst_w || src_w != dst_h): | |
4405 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4406 | |
4407 | /* | |
4408 | * if plane is being disabled or scaler is no more required or force detach | |
4409 | * - free scaler binded to this plane/crtc | |
4410 | * - in order to do this, update crtc->scaler_usage | |
4411 | * | |
4412 | * Here scaler state in crtc_state is set free so that | |
4413 | * scaler can be assigned to other user. Actual register | |
4414 | * update to free the scaler is done in plane/panel-fit programming. | |
4415 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4416 | */ | |
86adf9d7 | 4417 | if (force_detach || !need_scaling) { |
a1b2278e | 4418 | if (*scaler_id >= 0) { |
86adf9d7 | 4419 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4420 | scaler_state->scalers[*scaler_id].in_use = 0; |
4421 | ||
86adf9d7 ML |
4422 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4423 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4424 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4425 | scaler_state->scaler_users); |
4426 | *scaler_id = -1; | |
4427 | } | |
4428 | return 0; | |
4429 | } | |
4430 | ||
4431 | /* range checks */ | |
4432 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4433 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4434 | ||
4435 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4436 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4437 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4438 | "size is out of scaler range\n", |
86adf9d7 | 4439 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4440 | return -EINVAL; |
4441 | } | |
4442 | ||
86adf9d7 ML |
4443 | /* mark this plane as a scaler user in crtc_state */ |
4444 | scaler_state->scaler_users |= (1 << scaler_user); | |
4445 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4446 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4447 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4448 | scaler_state->scaler_users); | |
4449 | ||
4450 | return 0; | |
4451 | } | |
4452 | ||
4453 | /** | |
4454 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4455 | * | |
4456 | * @state: crtc's scaler state | |
86adf9d7 ML |
4457 | * |
4458 | * Return | |
4459 | * 0 - scaler_usage updated successfully | |
4460 | * error - requested scaling cannot be supported or other error condition | |
4461 | */ | |
e435d6e5 | 4462 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4463 | { |
4464 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4465 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4466 | |
78108b7c VS |
4467 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n", |
4468 | intel_crtc->base.base.id, intel_crtc->base.name, | |
4469 | intel_crtc->pipe, SKL_CRTC_INDEX); | |
86adf9d7 | 4470 | |
e435d6e5 | 4471 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4472 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4473 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4474 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4475 | } |
4476 | ||
4477 | /** | |
4478 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4479 | * | |
4480 | * @state: crtc's scaler state | |
86adf9d7 ML |
4481 | * @plane_state: atomic plane state to update |
4482 | * | |
4483 | * Return | |
4484 | * 0 - scaler_usage updated successfully | |
4485 | * error - requested scaling cannot be supported or other error condition | |
4486 | */ | |
da20eabd ML |
4487 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4488 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4489 | { |
4490 | ||
4491 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4492 | struct intel_plane *intel_plane = |
4493 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4494 | struct drm_framebuffer *fb = plane_state->base.fb; |
4495 | int ret; | |
4496 | ||
4497 | bool force_detach = !fb || !plane_state->visible; | |
4498 | ||
72660ce0 VS |
4499 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n", |
4500 | intel_plane->base.base.id, intel_plane->base.name, | |
4501 | intel_crtc->pipe, drm_plane_index(&intel_plane->base)); | |
86adf9d7 ML |
4502 | |
4503 | ret = skl_update_scaler(crtc_state, force_detach, | |
4504 | drm_plane_index(&intel_plane->base), | |
4505 | &plane_state->scaler_id, | |
4506 | plane_state->base.rotation, | |
4507 | drm_rect_width(&plane_state->src) >> 16, | |
4508 | drm_rect_height(&plane_state->src) >> 16, | |
4509 | drm_rect_width(&plane_state->dst), | |
4510 | drm_rect_height(&plane_state->dst)); | |
4511 | ||
4512 | if (ret || plane_state->scaler_id < 0) | |
4513 | return ret; | |
4514 | ||
a1b2278e | 4515 | /* check colorkey */ |
818ed961 | 4516 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4517 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4518 | intel_plane->base.base.id, | |
4519 | intel_plane->base.name); | |
a1b2278e CK |
4520 | return -EINVAL; |
4521 | } | |
4522 | ||
4523 | /* Check src format */ | |
86adf9d7 ML |
4524 | switch (fb->pixel_format) { |
4525 | case DRM_FORMAT_RGB565: | |
4526 | case DRM_FORMAT_XBGR8888: | |
4527 | case DRM_FORMAT_XRGB8888: | |
4528 | case DRM_FORMAT_ABGR8888: | |
4529 | case DRM_FORMAT_ARGB8888: | |
4530 | case DRM_FORMAT_XRGB2101010: | |
4531 | case DRM_FORMAT_XBGR2101010: | |
4532 | case DRM_FORMAT_YUYV: | |
4533 | case DRM_FORMAT_YVYU: | |
4534 | case DRM_FORMAT_UYVY: | |
4535 | case DRM_FORMAT_VYUY: | |
4536 | break; | |
4537 | default: | |
72660ce0 VS |
4538 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4539 | intel_plane->base.base.id, intel_plane->base.name, | |
4540 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4541 | return -EINVAL; |
a1b2278e CK |
4542 | } |
4543 | ||
a1b2278e CK |
4544 | return 0; |
4545 | } | |
4546 | ||
e435d6e5 ML |
4547 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4548 | { | |
4549 | int i; | |
4550 | ||
4551 | for (i = 0; i < crtc->num_scalers; i++) | |
4552 | skl_detach_scaler(crtc, i); | |
4553 | } | |
4554 | ||
4555 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4556 | { |
4557 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4558 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4559 | int pipe = crtc->pipe; |
a1b2278e CK |
4560 | struct intel_crtc_scaler_state *scaler_state = |
4561 | &crtc->config->scaler_state; | |
4562 | ||
4563 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4564 | ||
6e3c9717 | 4565 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4566 | int id; |
4567 | ||
4568 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4569 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4570 | return; | |
4571 | } | |
4572 | ||
4573 | id = scaler_state->scaler_id; | |
4574 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4575 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4576 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4577 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4578 | ||
4579 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4580 | } |
4581 | } | |
4582 | ||
b074cec8 JB |
4583 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4584 | { | |
4585 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4586 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4587 | int pipe = crtc->pipe; |
4588 | ||
6e3c9717 | 4589 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4590 | /* Force use of hard-coded filter coefficients |
4591 | * as some pre-programmed values are broken, | |
4592 | * e.g. x201. | |
4593 | */ | |
4594 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4595 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4596 | PF_PIPE_SEL_IVB(pipe)); | |
4597 | else | |
4598 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4599 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4600 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4601 | } |
4602 | } | |
4603 | ||
20bc8673 | 4604 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4605 | { |
cea165c3 | 4606 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4607 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4608 | |
6e3c9717 | 4609 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4610 | return; |
4611 | ||
307e4498 ML |
4612 | /* |
4613 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4614 | * This function is called from post_plane_update, which is run after | |
4615 | * a vblank wait. | |
4616 | */ | |
cea165c3 | 4617 | |
d77e4531 | 4618 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4619 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4620 | mutex_lock(&dev_priv->rps.hw_lock); |
4621 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4622 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4623 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4624 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4625 | * mailbox." Moreover, the mailbox may return a bogus state, |
4626 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4627 | */ |
4628 | } else { | |
4629 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4630 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4631 | * is essentially intel_wait_for_vblank. If we don't have this | |
4632 | * and don't wait for vblanks until the end of crtc_enable, then | |
4633 | * the HW state readout code will complain that the expected | |
4634 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4635 | if (intel_wait_for_register(dev_priv, |
4636 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4637 | 50)) | |
2a114cc1 BW |
4638 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4639 | } | |
d77e4531 PZ |
4640 | } |
4641 | ||
20bc8673 | 4642 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4643 | { |
4644 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4645 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4646 | |
6e3c9717 | 4647 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4648 | return; |
4649 | ||
4650 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4651 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4652 | mutex_lock(&dev_priv->rps.hw_lock); |
4653 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4654 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4655 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4656 | if (intel_wait_for_register(dev_priv, |
4657 | IPS_CTL, IPS_ENABLE, 0, | |
4658 | 42)) | |
23d0b130 | 4659 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4660 | } else { |
2a114cc1 | 4661 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4662 | POSTING_READ(IPS_CTL); |
4663 | } | |
d77e4531 PZ |
4664 | |
4665 | /* We need to wait for a vblank before we can disable the plane. */ | |
4666 | intel_wait_for_vblank(dev, crtc->pipe); | |
4667 | } | |
4668 | ||
7cac945f | 4669 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4670 | { |
7cac945f | 4671 | if (intel_crtc->overlay) { |
d3eedb1a | 4672 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4673 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4674 | |
4675 | mutex_lock(&dev->struct_mutex); | |
4676 | dev_priv->mm.interruptible = false; | |
4677 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4678 | dev_priv->mm.interruptible = true; | |
4679 | mutex_unlock(&dev->struct_mutex); | |
4680 | } | |
4681 | ||
4682 | /* Let userspace switch the overlay on again. In most cases userspace | |
4683 | * has to recompute where to put it anyway. | |
4684 | */ | |
4685 | } | |
4686 | ||
87d4300a ML |
4687 | /** |
4688 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4689 | * @crtc: the CRTC whose primary plane was just enabled | |
4690 | * | |
4691 | * Performs potentially sleeping operations that must be done after the primary | |
4692 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4693 | * called due to an explicit primary plane update, or due to an implicit | |
4694 | * re-enable that is caused when a sprite plane is updated to no longer | |
4695 | * completely hide the primary plane. | |
4696 | */ | |
4697 | static void | |
4698 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4699 | { |
4700 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4701 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4702 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4703 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4704 | |
87d4300a ML |
4705 | /* |
4706 | * FIXME IPS should be fine as long as one plane is | |
4707 | * enabled, but in practice it seems to have problems | |
4708 | * when going from primary only to sprite only and vice | |
4709 | * versa. | |
4710 | */ | |
a5c4d7bc VS |
4711 | hsw_enable_ips(intel_crtc); |
4712 | ||
f99d7069 | 4713 | /* |
87d4300a ML |
4714 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4715 | * So don't enable underrun reporting before at least some planes | |
4716 | * are enabled. | |
4717 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4718 | * but leave the pipe running. | |
f99d7069 | 4719 | */ |
87d4300a ML |
4720 | if (IS_GEN2(dev)) |
4721 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4722 | ||
aca7b684 VS |
4723 | /* Underruns don't always raise interrupts, so check manually. */ |
4724 | intel_check_cpu_fifo_underruns(dev_priv); | |
4725 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4726 | } |
4727 | ||
2622a081 | 4728 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4729 | static void |
4730 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4731 | { |
4732 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4733 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4734 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4735 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4736 | |
87d4300a ML |
4737 | /* |
4738 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4739 | * So diasble underrun reporting before all the planes get disabled. | |
4740 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4741 | * but leave the pipe running. | |
4742 | */ | |
4743 | if (IS_GEN2(dev)) | |
4744 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4745 | |
2622a081 VS |
4746 | /* |
4747 | * FIXME IPS should be fine as long as one plane is | |
4748 | * enabled, but in practice it seems to have problems | |
4749 | * when going from primary only to sprite only and vice | |
4750 | * versa. | |
4751 | */ | |
4752 | hsw_disable_ips(intel_crtc); | |
4753 | } | |
4754 | ||
4755 | /* FIXME get rid of this and use pre_plane_update */ | |
4756 | static void | |
4757 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4758 | { | |
4759 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4760 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4762 | int pipe = intel_crtc->pipe; | |
4763 | ||
4764 | intel_pre_disable_primary(crtc); | |
4765 | ||
87d4300a ML |
4766 | /* |
4767 | * Vblank time updates from the shadow to live plane control register | |
4768 | * are blocked if the memory self-refresh mode is active at that | |
4769 | * moment. So to make sure the plane gets truly disabled, disable | |
4770 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4771 | * will be checked/applied by the HW only at the next frame start | |
4772 | * event which is after the vblank start event, so we need to have a | |
4773 | * wait-for-vblank between disabling the plane and the pipe. | |
4774 | */ | |
262cd2e1 | 4775 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4776 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4777 | dev_priv->wm.vlv.cxsr = false; |
4778 | intel_wait_for_vblank(dev, pipe); | |
4779 | } | |
87d4300a ML |
4780 | } |
4781 | ||
5a21b665 DV |
4782 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4783 | { | |
4784 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4785 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4786 | struct intel_crtc_state *pipe_config = | |
4787 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
4788 | struct drm_plane *primary = crtc->base.primary; |
4789 | struct drm_plane_state *old_pri_state = | |
4790 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4791 | ||
5748b6a1 | 4792 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 DV |
4793 | |
4794 | crtc->wm.cxsr_allowed = true; | |
4795 | ||
4796 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
4797 | intel_update_watermarks(&crtc->base); | |
4798 | ||
4799 | if (old_pri_state) { | |
4800 | struct intel_plane_state *primary_state = | |
4801 | to_intel_plane_state(primary->state); | |
4802 | struct intel_plane_state *old_primary_state = | |
4803 | to_intel_plane_state(old_pri_state); | |
4804 | ||
4805 | intel_fbc_post_update(crtc); | |
4806 | ||
4807 | if (primary_state->visible && | |
4808 | (needs_modeset(&pipe_config->base) || | |
4809 | !old_primary_state->visible)) | |
4810 | intel_post_enable_primary(&crtc->base); | |
4811 | } | |
4812 | } | |
4813 | ||
5c74cd73 | 4814 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4815 | { |
5c74cd73 | 4816 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4817 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4818 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
4819 | struct intel_crtc_state *pipe_config = |
4820 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4821 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4822 | struct drm_plane *primary = crtc->base.primary; | |
4823 | struct drm_plane_state *old_pri_state = | |
4824 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4825 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4826 | |
5c74cd73 ML |
4827 | if (old_pri_state) { |
4828 | struct intel_plane_state *primary_state = | |
4829 | to_intel_plane_state(primary->state); | |
4830 | struct intel_plane_state *old_primary_state = | |
4831 | to_intel_plane_state(old_pri_state); | |
4832 | ||
faf68d92 | 4833 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 4834 | |
5c74cd73 ML |
4835 | if (old_primary_state->visible && |
4836 | (modeset || !primary_state->visible)) | |
4837 | intel_pre_disable_primary(&crtc->base); | |
4838 | } | |
852eb00d | 4839 | |
a4015f9a | 4840 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) { |
852eb00d | 4841 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4842 | |
2622a081 VS |
4843 | /* |
4844 | * Vblank time updates from the shadow to live plane control register | |
4845 | * are blocked if the memory self-refresh mode is active at that | |
4846 | * moment. So to make sure the plane gets truly disabled, disable | |
4847 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4848 | * will be checked/applied by the HW only at the next frame start | |
4849 | * event which is after the vblank start event, so we need to have a | |
4850 | * wait-for-vblank between disabling the plane and the pipe. | |
4851 | */ | |
4852 | if (old_crtc_state->base.active) { | |
2dfd178d | 4853 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4854 | dev_priv->wm.vlv.cxsr = false; |
4855 | intel_wait_for_vblank(dev, crtc->pipe); | |
4856 | } | |
852eb00d | 4857 | } |
92826fcd | 4858 | |
ed4a6a7c MR |
4859 | /* |
4860 | * IVB workaround: must disable low power watermarks for at least | |
4861 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4862 | * when scaling is disabled. | |
4863 | * | |
4864 | * WaCxSRDisabledForSpriteScaling:ivb | |
4865 | */ | |
4866 | if (pipe_config->disable_lp_wm) { | |
4867 | ilk_disable_lp_wm(dev); | |
4868 | intel_wait_for_vblank(dev, crtc->pipe); | |
4869 | } | |
4870 | ||
4871 | /* | |
4872 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4873 | * watermark programming here. | |
4874 | */ | |
4875 | if (needs_modeset(&pipe_config->base)) | |
4876 | return; | |
4877 | ||
4878 | /* | |
4879 | * For platforms that support atomic watermarks, program the | |
4880 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4881 | * will be the intermediate values that are safe for both pre- and | |
4882 | * post- vblank; when vblank happens, the 'active' values will be set | |
4883 | * to the final 'target' values and we'll do this again to get the | |
4884 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4885 | * will be the final target values which will get automatically latched | |
4886 | * at vblank time; no further programming will be necessary. | |
4887 | * | |
4888 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4889 | * we'll continue to update watermarks the old way, if flags tell | |
4890 | * us to. | |
4891 | */ | |
4892 | if (dev_priv->display.initial_watermarks != NULL) | |
4893 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4894 | else if (pipe_config->update_wm_pre) |
92826fcd | 4895 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4896 | } |
4897 | ||
d032ffa0 | 4898 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4899 | { |
4900 | struct drm_device *dev = crtc->dev; | |
4901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4902 | struct drm_plane *p; |
87d4300a ML |
4903 | int pipe = intel_crtc->pipe; |
4904 | ||
7cac945f | 4905 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4906 | |
d032ffa0 ML |
4907 | drm_for_each_plane_mask(p, dev, plane_mask) |
4908 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4909 | |
f99d7069 DV |
4910 | /* |
4911 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4912 | * to compute the mask of flip planes precisely. For the time being | |
4913 | * consider this a flip to a NULL plane. | |
4914 | */ | |
5748b6a1 | 4915 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
4916 | } |
4917 | ||
f67a559d JB |
4918 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4919 | { | |
4920 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4921 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d | 4922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4923 | struct intel_encoder *encoder; |
f67a559d | 4924 | int pipe = intel_crtc->pipe; |
b95c5321 ML |
4925 | struct intel_crtc_state *pipe_config = |
4926 | to_intel_crtc_state(crtc->state); | |
f67a559d | 4927 | |
53d9f4e9 | 4928 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4929 | return; |
4930 | ||
b2c0593a VS |
4931 | /* |
4932 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4933 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4934 | * | |
4935 | * On ILK we get an occasional spurious CPU pipe underruns | |
4936 | * between eDP port A enable and vdd enable. Also PCH port | |
4937 | * enable seems to result in the occasional CPU pipe underrun. | |
4938 | * | |
4939 | * Spurious PCH underruns also occur during PCH enabling. | |
4940 | */ | |
4941 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
4942 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
4943 | if (intel_crtc->config->has_pch_encoder) |
4944 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4945 | ||
6e3c9717 | 4946 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4947 | intel_prepare_shared_dpll(intel_crtc); |
4948 | ||
37a5650b | 4949 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 4950 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4951 | |
4952 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4953 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4954 | |
6e3c9717 | 4955 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4956 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4957 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4958 | } |
4959 | ||
4960 | ironlake_set_pipeconf(crtc); | |
4961 | ||
f67a559d | 4962 | intel_crtc->active = true; |
8664281b | 4963 | |
f6736a1a | 4964 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4965 | if (encoder->pre_enable) |
4966 | encoder->pre_enable(encoder); | |
f67a559d | 4967 | |
6e3c9717 | 4968 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4969 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4970 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4971 | * enabling. */ | |
88cefb6c | 4972 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4973 | } else { |
4974 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4975 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4976 | } | |
f67a559d | 4977 | |
b074cec8 | 4978 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4979 | |
9c54c0dd JB |
4980 | /* |
4981 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4982 | * clocks enabled | |
4983 | */ | |
b95c5321 | 4984 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 4985 | |
1d5bf5d9 ID |
4986 | if (dev_priv->display.initial_watermarks != NULL) |
4987 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4988 | intel_enable_pipe(intel_crtc); |
f67a559d | 4989 | |
6e3c9717 | 4990 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4991 | ironlake_pch_enable(crtc); |
c98e9dcf | 4992 | |
f9b61ff6 DV |
4993 | assert_vblank_disabled(crtc); |
4994 | drm_crtc_vblank_on(crtc); | |
4995 | ||
fa5c73b1 DV |
4996 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4997 | encoder->enable(encoder); | |
61b77ddd DV |
4998 | |
4999 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 5000 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5001 | |
5002 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5003 | if (intel_crtc->config->has_pch_encoder) | |
5004 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 5005 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5006 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5007 | } |
5008 | ||
42db64ef PZ |
5009 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5010 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5011 | { | |
f5adf94e | 5012 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5013 | } |
5014 | ||
4f771f10 PZ |
5015 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
5016 | { | |
5017 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5018 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f771f10 PZ |
5019 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5020 | struct intel_encoder *encoder; | |
99d736a2 | 5021 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5022 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
5023 | struct intel_crtc_state *pipe_config = |
5024 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 5025 | |
53d9f4e9 | 5026 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5027 | return; |
5028 | ||
81b088ca VS |
5029 | if (intel_crtc->config->has_pch_encoder) |
5030 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5031 | false); | |
5032 | ||
95a7a2ae ID |
5033 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5034 | if (encoder->pre_pll_enable) | |
5035 | encoder->pre_pll_enable(encoder); | |
5036 | ||
8106ddbd | 5037 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5038 | intel_enable_shared_dpll(intel_crtc); |
5039 | ||
37a5650b | 5040 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5041 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5042 | |
d7edc4e5 | 5043 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5044 | intel_set_pipe_timings(intel_crtc); |
5045 | ||
bc58be60 | 5046 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5047 | |
4d1de975 JN |
5048 | if (cpu_transcoder != TRANSCODER_EDP && |
5049 | !transcoder_is_dsi(cpu_transcoder)) { | |
5050 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5051 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5052 | } |
5053 | ||
6e3c9717 | 5054 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5055 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5056 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5057 | } |
5058 | ||
d7edc4e5 | 5059 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5060 | haswell_set_pipeconf(crtc); |
5061 | ||
391bf048 | 5062 | haswell_set_pipemisc(crtc); |
229fca97 | 5063 | |
b95c5321 | 5064 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5065 | |
4f771f10 | 5066 | intel_crtc->active = true; |
8664281b | 5067 | |
6b698516 DV |
5068 | if (intel_crtc->config->has_pch_encoder) |
5069 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5070 | else | |
5071 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5072 | ||
7d4aefd0 | 5073 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
5074 | if (encoder->pre_enable) |
5075 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5076 | } |
4f771f10 | 5077 | |
d2d65408 | 5078 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5079 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5080 | |
d7edc4e5 | 5081 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5082 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5083 | |
1c132b44 | 5084 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5085 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5086 | else |
1c132b44 | 5087 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5088 | |
5089 | /* | |
5090 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5091 | * clocks enabled | |
5092 | */ | |
b95c5321 | 5093 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5094 | |
1f544388 | 5095 | intel_ddi_set_pipe_settings(crtc); |
d7edc4e5 | 5096 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5097 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5098 | |
1d5bf5d9 ID |
5099 | if (dev_priv->display.initial_watermarks != NULL) |
5100 | dev_priv->display.initial_watermarks(pipe_config); | |
5101 | else | |
5102 | intel_update_watermarks(crtc); | |
4d1de975 JN |
5103 | |
5104 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5105 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5106 | intel_enable_pipe(intel_crtc); |
42db64ef | 5107 | |
6e3c9717 | 5108 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5109 | lpt_pch_enable(crtc); |
4f771f10 | 5110 | |
a65347ba | 5111 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5112 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5113 | ||
f9b61ff6 DV |
5114 | assert_vblank_disabled(crtc); |
5115 | drm_crtc_vblank_on(crtc); | |
5116 | ||
8807e55b | 5117 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5118 | encoder->enable(encoder); |
8807e55b JN |
5119 | intel_opregion_notify_encoder(encoder, true); |
5120 | } | |
4f771f10 | 5121 | |
6b698516 DV |
5122 | if (intel_crtc->config->has_pch_encoder) { |
5123 | intel_wait_for_vblank(dev, pipe); | |
5124 | intel_wait_for_vblank(dev, pipe); | |
5125 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5126 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5127 | true); | |
6b698516 | 5128 | } |
d2d65408 | 5129 | |
e4916946 PZ |
5130 | /* If we change the relative order between pipe/planes enabling, we need |
5131 | * to change the workaround. */ | |
99d736a2 ML |
5132 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5133 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5134 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5135 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5136 | } | |
4f771f10 PZ |
5137 | } |
5138 | ||
bfd16b2a | 5139 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5140 | { |
5141 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5142 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5143 | int pipe = crtc->pipe; |
5144 | ||
5145 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5146 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5147 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5148 | I915_WRITE(PF_CTL(pipe), 0); |
5149 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5150 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5151 | } | |
5152 | } | |
5153 | ||
6be4a607 JB |
5154 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5155 | { | |
5156 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5157 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 | 5158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5159 | struct intel_encoder *encoder; |
6be4a607 | 5160 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5161 | |
b2c0593a VS |
5162 | /* |
5163 | * Sometimes spurious CPU pipe underruns happen when the | |
5164 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5165 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5166 | */ | |
5167 | if (intel_crtc->config->has_pch_encoder) { | |
5168 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5169 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5170 | } |
37ca8d4c | 5171 | |
ea9d758d DV |
5172 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5173 | encoder->disable(encoder); | |
5174 | ||
f9b61ff6 DV |
5175 | drm_crtc_vblank_off(crtc); |
5176 | assert_vblank_disabled(crtc); | |
5177 | ||
575f7ab7 | 5178 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5179 | |
bfd16b2a | 5180 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5181 | |
b2c0593a | 5182 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5183 | ironlake_fdi_disable(crtc); |
5184 | ||
bf49ec8c DV |
5185 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5186 | if (encoder->post_disable) | |
5187 | encoder->post_disable(encoder); | |
2c07245f | 5188 | |
6e3c9717 | 5189 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5190 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5191 | |
d925c59a | 5192 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5193 | i915_reg_t reg; |
5194 | u32 temp; | |
5195 | ||
d925c59a DV |
5196 | /* disable TRANS_DP_CTL */ |
5197 | reg = TRANS_DP_CTL(pipe); | |
5198 | temp = I915_READ(reg); | |
5199 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5200 | TRANS_DP_PORT_SEL_MASK); | |
5201 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5202 | I915_WRITE(reg, temp); | |
5203 | ||
5204 | /* disable DPLL_SEL */ | |
5205 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5206 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5207 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5208 | } |
e3421a18 | 5209 | |
d925c59a DV |
5210 | ironlake_fdi_pll_disable(intel_crtc); |
5211 | } | |
81b088ca | 5212 | |
b2c0593a | 5213 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5214 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5215 | } |
1b3c7a47 | 5216 | |
4f771f10 | 5217 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5218 | { |
4f771f10 | 5219 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5220 | struct drm_i915_private *dev_priv = to_i915(dev); |
ee7b9f93 | 5221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5222 | struct intel_encoder *encoder; |
6e3c9717 | 5223 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5224 | |
d2d65408 VS |
5225 | if (intel_crtc->config->has_pch_encoder) |
5226 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5227 | false); | |
5228 | ||
8807e55b JN |
5229 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5230 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5231 | encoder->disable(encoder); |
8807e55b | 5232 | } |
4f771f10 | 5233 | |
f9b61ff6 DV |
5234 | drm_crtc_vblank_off(crtc); |
5235 | assert_vblank_disabled(crtc); | |
5236 | ||
4d1de975 | 5237 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5238 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5239 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5240 | |
6e3c9717 | 5241 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5242 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5243 | ||
d7edc4e5 | 5244 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5245 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5246 | |
1c132b44 | 5247 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5248 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5249 | else |
bfd16b2a | 5250 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5251 | |
d7edc4e5 | 5252 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5253 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5254 | |
97b040aa ID |
5255 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5256 | if (encoder->post_disable) | |
5257 | encoder->post_disable(encoder); | |
81b088ca | 5258 | |
92966a37 VS |
5259 | if (intel_crtc->config->has_pch_encoder) { |
5260 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5261 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5262 | intel_ddi_fdi_disable(crtc); |
5263 | ||
81b088ca VS |
5264 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5265 | true); | |
92966a37 | 5266 | } |
4f771f10 PZ |
5267 | } |
5268 | ||
2dd24552 JB |
5269 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5270 | { | |
5271 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5272 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5273 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5274 | |
681a8504 | 5275 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5276 | return; |
5277 | ||
2dd24552 | 5278 | /* |
c0b03411 DV |
5279 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5280 | * according to register description and PRM. | |
2dd24552 | 5281 | */ |
c0b03411 DV |
5282 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5283 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5284 | |
b074cec8 JB |
5285 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5286 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5287 | |
5288 | /* Border color in case we don't scale up to the full screen. Black by | |
5289 | * default, change to something else for debugging. */ | |
5290 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5291 | } |
5292 | ||
d05410f9 DA |
5293 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5294 | { | |
5295 | switch (port) { | |
5296 | case PORT_A: | |
6331a704 | 5297 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5298 | case PORT_B: |
6331a704 | 5299 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5300 | case PORT_C: |
6331a704 | 5301 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5302 | case PORT_D: |
6331a704 | 5303 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5304 | case PORT_E: |
6331a704 | 5305 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5306 | default: |
b9fec167 | 5307 | MISSING_CASE(port); |
d05410f9 DA |
5308 | return POWER_DOMAIN_PORT_OTHER; |
5309 | } | |
5310 | } | |
5311 | ||
25f78f58 VS |
5312 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5313 | { | |
5314 | switch (port) { | |
5315 | case PORT_A: | |
5316 | return POWER_DOMAIN_AUX_A; | |
5317 | case PORT_B: | |
5318 | return POWER_DOMAIN_AUX_B; | |
5319 | case PORT_C: | |
5320 | return POWER_DOMAIN_AUX_C; | |
5321 | case PORT_D: | |
5322 | return POWER_DOMAIN_AUX_D; | |
5323 | case PORT_E: | |
5324 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5325 | return POWER_DOMAIN_AUX_D; | |
5326 | default: | |
b9fec167 | 5327 | MISSING_CASE(port); |
25f78f58 VS |
5328 | return POWER_DOMAIN_AUX_A; |
5329 | } | |
5330 | } | |
5331 | ||
319be8ae ID |
5332 | enum intel_display_power_domain |
5333 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5334 | { | |
5335 | struct drm_device *dev = intel_encoder->base.dev; | |
5336 | struct intel_digital_port *intel_dig_port; | |
5337 | ||
5338 | switch (intel_encoder->type) { | |
5339 | case INTEL_OUTPUT_UNKNOWN: | |
5340 | /* Only DDI platforms should ever use this output type */ | |
5341 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
cca0502b | 5342 | case INTEL_OUTPUT_DP: |
319be8ae ID |
5343 | case INTEL_OUTPUT_HDMI: |
5344 | case INTEL_OUTPUT_EDP: | |
5345 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5346 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5347 | case INTEL_OUTPUT_DP_MST: |
5348 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5349 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5350 | case INTEL_OUTPUT_ANALOG: |
5351 | return POWER_DOMAIN_PORT_CRT; | |
5352 | case INTEL_OUTPUT_DSI: | |
5353 | return POWER_DOMAIN_PORT_DSI; | |
5354 | default: | |
5355 | return POWER_DOMAIN_PORT_OTHER; | |
5356 | } | |
5357 | } | |
5358 | ||
25f78f58 VS |
5359 | enum intel_display_power_domain |
5360 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5361 | { | |
5362 | struct drm_device *dev = intel_encoder->base.dev; | |
5363 | struct intel_digital_port *intel_dig_port; | |
5364 | ||
5365 | switch (intel_encoder->type) { | |
5366 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5367 | case INTEL_OUTPUT_HDMI: |
5368 | /* | |
5369 | * Only DDI platforms should ever use these output types. | |
5370 | * We can get here after the HDMI detect code has already set | |
5371 | * the type of the shared encoder. Since we can't be sure | |
5372 | * what's the status of the given connectors, play safe and | |
5373 | * run the DP detection too. | |
5374 | */ | |
25f78f58 | 5375 | WARN_ON_ONCE(!HAS_DDI(dev)); |
cca0502b | 5376 | case INTEL_OUTPUT_DP: |
25f78f58 VS |
5377 | case INTEL_OUTPUT_EDP: |
5378 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5379 | return port_to_aux_power_domain(intel_dig_port->port); | |
5380 | case INTEL_OUTPUT_DP_MST: | |
5381 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5382 | return port_to_aux_power_domain(intel_dig_port->port); | |
5383 | default: | |
b9fec167 | 5384 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5385 | return POWER_DOMAIN_AUX_A; |
5386 | } | |
5387 | } | |
5388 | ||
74bff5f9 ML |
5389 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5390 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5391 | { |
319be8ae | 5392 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5393 | struct drm_encoder *encoder; |
319be8ae ID |
5394 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5395 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5396 | unsigned long mask; |
74bff5f9 | 5397 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5398 | |
74bff5f9 | 5399 | if (!crtc_state->base.active) |
292b990e ML |
5400 | return 0; |
5401 | ||
77d22dca ID |
5402 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5403 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5404 | if (crtc_state->pch_pfit.enabled || |
5405 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5406 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5407 | ||
74bff5f9 ML |
5408 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5409 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5410 | ||
319be8ae | 5411 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5412 | } |
319be8ae | 5413 | |
15e7ec29 ML |
5414 | if (crtc_state->shared_dpll) |
5415 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5416 | ||
77d22dca ID |
5417 | return mask; |
5418 | } | |
5419 | ||
74bff5f9 ML |
5420 | static unsigned long |
5421 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5422 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5423 | { |
fac5e23e | 5424 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5425 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5426 | enum intel_display_power_domain domain; | |
5a21b665 | 5427 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5428 | |
292b990e | 5429 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5430 | intel_crtc->enabled_power_domains = new_domains = |
5431 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5432 | |
5a21b665 | 5433 | domains = new_domains & ~old_domains; |
292b990e ML |
5434 | |
5435 | for_each_power_domain(domain, domains) | |
5436 | intel_display_power_get(dev_priv, domain); | |
5437 | ||
5a21b665 | 5438 | return old_domains & ~new_domains; |
292b990e ML |
5439 | } |
5440 | ||
5441 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5442 | unsigned long domains) | |
5443 | { | |
5444 | enum intel_display_power_domain domain; | |
5445 | ||
5446 | for_each_power_domain(domain, domains) | |
5447 | intel_display_power_put(dev_priv, domain); | |
5448 | } | |
77d22dca | 5449 | |
adafdc6f MK |
5450 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5451 | { | |
5452 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5453 | ||
5454 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5455 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5456 | return max_cdclk_freq; | |
5457 | else if (IS_CHERRYVIEW(dev_priv)) | |
5458 | return max_cdclk_freq*95/100; | |
5459 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5460 | return 2*max_cdclk_freq*90/100; | |
5461 | else | |
5462 | return max_cdclk_freq*90/100; | |
5463 | } | |
5464 | ||
b2045352 VS |
5465 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5466 | ||
560a7ae4 DL |
5467 | static void intel_update_max_cdclk(struct drm_device *dev) |
5468 | { | |
fac5e23e | 5469 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 | 5470 | |
ef11bdb3 | 5471 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 | 5472 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5473 | int max_cdclk, vco; |
5474 | ||
5475 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5476 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5477 | |
b2045352 VS |
5478 | /* |
5479 | * Use the lower (vco 8640) cdclk values as a | |
5480 | * first guess. skl_calc_cdclk() will correct it | |
5481 | * if the preferred vco is 8100 instead. | |
5482 | */ | |
560a7ae4 | 5483 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5484 | max_cdclk = 617143; |
560a7ae4 | 5485 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5486 | max_cdclk = 540000; |
560a7ae4 | 5487 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5488 | max_cdclk = 432000; |
560a7ae4 | 5489 | else |
487ed2e4 | 5490 | max_cdclk = 308571; |
b2045352 VS |
5491 | |
5492 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
281c114f MR |
5493 | } else if (IS_BROXTON(dev)) { |
5494 | dev_priv->max_cdclk_freq = 624000; | |
560a7ae4 DL |
5495 | } else if (IS_BROADWELL(dev)) { |
5496 | /* | |
5497 | * FIXME with extra cooling we can allow | |
5498 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5499 | * How can we know if extra cooling is | |
5500 | * available? PCI ID, VTB, something else? | |
5501 | */ | |
5502 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5503 | dev_priv->max_cdclk_freq = 450000; | |
5504 | else if (IS_BDW_ULX(dev)) | |
5505 | dev_priv->max_cdclk_freq = 450000; | |
5506 | else if (IS_BDW_ULT(dev)) | |
5507 | dev_priv->max_cdclk_freq = 540000; | |
5508 | else | |
5509 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5510 | } else if (IS_CHERRYVIEW(dev)) { |
5511 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5512 | } else if (IS_VALLEYVIEW(dev)) { |
5513 | dev_priv->max_cdclk_freq = 400000; | |
5514 | } else { | |
5515 | /* otherwise assume cdclk is fixed */ | |
5516 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5517 | } | |
5518 | ||
adafdc6f MK |
5519 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5520 | ||
560a7ae4 DL |
5521 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5522 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5523 | |
5524 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5525 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5526 | } |
5527 | ||
5528 | static void intel_update_cdclk(struct drm_device *dev) | |
5529 | { | |
fac5e23e | 5530 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 DL |
5531 | |
5532 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
2f2a121a | 5533 | |
83d7c81f | 5534 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5535 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5536 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5537 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5538 | else |
5539 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5540 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5541 | |
5542 | /* | |
b5d99ff9 VS |
5543 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5544 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5545 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5546 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5547 | */ |
b5d99ff9 | 5548 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5549 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5550 | } |
5551 | ||
92891e45 VS |
5552 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5553 | static int skl_cdclk_decimal(int cdclk) | |
5554 | { | |
5555 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5556 | } | |
5557 | ||
5f199dfa VS |
5558 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5559 | { | |
5560 | int ratio; | |
5561 | ||
5562 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5563 | return 0; | |
5564 | ||
5565 | switch (cdclk) { | |
5566 | default: | |
5567 | MISSING_CASE(cdclk); | |
5568 | case 144000: | |
5569 | case 288000: | |
5570 | case 384000: | |
5571 | case 576000: | |
5572 | ratio = 60; | |
5573 | break; | |
5574 | case 624000: | |
5575 | ratio = 65; | |
5576 | break; | |
5577 | } | |
5578 | ||
5579 | return dev_priv->cdclk_pll.ref * ratio; | |
5580 | } | |
5581 | ||
2b73001e VS |
5582 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5583 | { | |
5584 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5585 | ||
5586 | /* Timeout 200us */ | |
95cac283 CW |
5587 | if (intel_wait_for_register(dev_priv, |
5588 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
5589 | 1)) | |
2b73001e | 5590 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
83d7c81f VS |
5591 | |
5592 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5593 | } |
5594 | ||
5f199dfa | 5595 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5596 | { |
5f199dfa | 5597 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5598 | u32 val; |
5599 | ||
5600 | val = I915_READ(BXT_DE_PLL_CTL); | |
5601 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5602 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5603 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5604 | ||
5605 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5606 | ||
5607 | /* Timeout 200us */ | |
e084e1b9 CW |
5608 | if (intel_wait_for_register(dev_priv, |
5609 | BXT_DE_PLL_ENABLE, | |
5610 | BXT_DE_PLL_LOCK, | |
5611 | BXT_DE_PLL_LOCK, | |
5612 | 1)) | |
2b73001e | 5613 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
83d7c81f | 5614 | |
5f199dfa | 5615 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5616 | } |
5617 | ||
324513c0 | 5618 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5619 | { |
5f199dfa VS |
5620 | u32 val, divider; |
5621 | int vco, ret; | |
f8437dd1 | 5622 | |
5f199dfa VS |
5623 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
5624 | ||
5625 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5626 | ||
5627 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5628 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5629 | case 8: | |
f8437dd1 | 5630 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5631 | break; |
5f199dfa | 5632 | case 4: |
f8437dd1 | 5633 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 5634 | break; |
5f199dfa | 5635 | case 3: |
f8437dd1 | 5636 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 5637 | break; |
5f199dfa | 5638 | case 2: |
f8437dd1 | 5639 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
5640 | break; |
5641 | default: | |
5f199dfa VS |
5642 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
5643 | WARN_ON(vco != 0); | |
f8437dd1 | 5644 | |
5f199dfa VS |
5645 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
5646 | break; | |
f8437dd1 VK |
5647 | } |
5648 | ||
f8437dd1 | 5649 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 5650 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
5651 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
5652 | 0x80000000); | |
5653 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5654 | ||
5655 | if (ret) { | |
5656 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 5657 | ret, cdclk); |
f8437dd1 VK |
5658 | return; |
5659 | } | |
5660 | ||
5f199dfa VS |
5661 | if (dev_priv->cdclk_pll.vco != 0 && |
5662 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 5663 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 5664 | |
5f199dfa VS |
5665 | if (dev_priv->cdclk_pll.vco != vco) |
5666 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 5667 | |
5f199dfa VS |
5668 | val = divider | skl_cdclk_decimal(cdclk); |
5669 | /* | |
5670 | * FIXME if only the cd2x divider needs changing, it could be done | |
5671 | * without shutting off the pipe (if only one pipe is active). | |
5672 | */ | |
5673 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
5674 | /* | |
5675 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5676 | * enable otherwise. | |
5677 | */ | |
5678 | if (cdclk >= 500000) | |
5679 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5680 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
5681 | |
5682 | mutex_lock(&dev_priv->rps.hw_lock); | |
5683 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 5684 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
5685 | mutex_unlock(&dev_priv->rps.hw_lock); |
5686 | ||
5687 | if (ret) { | |
5688 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 5689 | ret, cdclk); |
f8437dd1 VK |
5690 | return; |
5691 | } | |
5692 | ||
91c8a326 | 5693 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 VK |
5694 | } |
5695 | ||
d66a2194 | 5696 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5697 | { |
d66a2194 ID |
5698 | u32 cdctl, expected; |
5699 | ||
91c8a326 | 5700 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 | 5701 | |
d66a2194 ID |
5702 | if (dev_priv->cdclk_pll.vco == 0 || |
5703 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
5704 | goto sanitize; | |
5705 | ||
5706 | /* DPLL okay; verify the cdclock | |
5707 | * | |
5708 | * Some BIOS versions leave an incorrect decimal frequency value and | |
5709 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
5710 | * so sanitize this register. | |
5711 | */ | |
5712 | cdctl = I915_READ(CDCLK_CTL); | |
5713 | /* | |
5714 | * Let's ignore the pipe field, since BIOS could have configured the | |
5715 | * dividers both synching to an active pipe, or asynchronously | |
5716 | * (PIPE_NONE). | |
5717 | */ | |
5718 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
5719 | ||
5720 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
5721 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5722 | /* | |
5723 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5724 | * enable otherwise. | |
5725 | */ | |
5726 | if (dev_priv->cdclk_freq >= 500000) | |
5727 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5728 | ||
5729 | if (cdctl == expected) | |
5730 | /* All well; nothing to sanitize */ | |
5731 | return; | |
5732 | ||
5733 | sanitize: | |
5734 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
5735 | ||
5736 | /* force cdclk programming */ | |
5737 | dev_priv->cdclk_freq = 0; | |
5738 | ||
5739 | /* force full PLL disable + enable */ | |
5740 | dev_priv->cdclk_pll.vco = -1; | |
5741 | } | |
5742 | ||
324513c0 | 5743 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 ID |
5744 | { |
5745 | bxt_sanitize_cdclk(dev_priv); | |
5746 | ||
5747 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 5748 | return; |
c2e001ef | 5749 | |
f8437dd1 VK |
5750 | /* |
5751 | * FIXME: | |
5752 | * - The initial CDCLK needs to be read from VBT. | |
5753 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 5754 | */ |
324513c0 | 5755 | bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); |
f8437dd1 VK |
5756 | } |
5757 | ||
324513c0 | 5758 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5759 | { |
324513c0 | 5760 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
5761 | } |
5762 | ||
a8ca4934 VS |
5763 | static int skl_calc_cdclk(int max_pixclk, int vco) |
5764 | { | |
63911d72 | 5765 | if (vco == 8640000) { |
a8ca4934 | 5766 | if (max_pixclk > 540000) |
487ed2e4 | 5767 | return 617143; |
a8ca4934 VS |
5768 | else if (max_pixclk > 432000) |
5769 | return 540000; | |
487ed2e4 | 5770 | else if (max_pixclk > 308571) |
a8ca4934 VS |
5771 | return 432000; |
5772 | else | |
487ed2e4 | 5773 | return 308571; |
a8ca4934 | 5774 | } else { |
a8ca4934 VS |
5775 | if (max_pixclk > 540000) |
5776 | return 675000; | |
5777 | else if (max_pixclk > 450000) | |
5778 | return 540000; | |
5779 | else if (max_pixclk > 337500) | |
5780 | return 450000; | |
5781 | else | |
5782 | return 337500; | |
5783 | } | |
5784 | } | |
5785 | ||
ea61791e VS |
5786 | static void |
5787 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 5788 | { |
ea61791e | 5789 | u32 val; |
5d96d8af | 5790 | |
709e05c3 | 5791 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 5792 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 5793 | |
ea61791e | 5794 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 5795 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 5796 | return; |
5d96d8af | 5797 | |
1c3f7700 ID |
5798 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
5799 | return; | |
9f7eb31a | 5800 | |
ea61791e VS |
5801 | val = I915_READ(DPLL_CTRL1); |
5802 | ||
1c3f7700 ID |
5803 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
5804 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5805 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
5806 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
5807 | return; | |
9f7eb31a | 5808 | |
ea61791e VS |
5809 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
5810 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
5811 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
5812 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
5813 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 5814 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
5815 | break; |
5816 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
5817 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 5818 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
5819 | break; |
5820 | default: | |
5821 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
5822 | break; |
5823 | } | |
5d96d8af DL |
5824 | } |
5825 | ||
b2045352 VS |
5826 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
5827 | { | |
5828 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
5829 | ||
5830 | dev_priv->skl_preferred_vco_freq = vco; | |
5831 | ||
5832 | if (changed) | |
91c8a326 | 5833 | intel_update_max_cdclk(&dev_priv->drm); |
b2045352 VS |
5834 | } |
5835 | ||
5d96d8af | 5836 | static void |
3861fc60 | 5837 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 5838 | { |
a8ca4934 | 5839 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
5840 | u32 val; |
5841 | ||
63911d72 | 5842 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 5843 | |
5d96d8af | 5844 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 5845 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
5846 | I915_WRITE(CDCLK_CTL, val); |
5847 | POSTING_READ(CDCLK_CTL); | |
5848 | ||
5849 | /* | |
5850 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5851 | * taking into account the VCO required to operate the eDP panel at the | |
5852 | * desired frequency. The usual DP link rates operate with a VCO of | |
5853 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5854 | * The modeset code is responsible for the selection of the exact link | |
5855 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 5856 | * works with vco. |
5d96d8af DL |
5857 | */ |
5858 | val = I915_READ(DPLL_CTRL1); | |
5859 | ||
5860 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5861 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5862 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 5863 | if (vco == 8640000) |
5d96d8af DL |
5864 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
5865 | SKL_DPLL0); | |
5866 | else | |
5867 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5868 | SKL_DPLL0); | |
5869 | ||
5870 | I915_WRITE(DPLL_CTRL1, val); | |
5871 | POSTING_READ(DPLL_CTRL1); | |
5872 | ||
5873 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5874 | ||
e24ca054 CW |
5875 | if (intel_wait_for_register(dev_priv, |
5876 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
5877 | 5)) | |
5d96d8af | 5878 | DRM_ERROR("DPLL0 not locked\n"); |
1cd593e0 | 5879 | |
63911d72 | 5880 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
5881 | |
5882 | /* We'll want to keep using the current vco from now on. */ | |
5883 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
5884 | } |
5885 | ||
430e05de VS |
5886 | static void |
5887 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
5888 | { | |
5889 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
8ad32a05 CW |
5890 | if (intel_wait_for_register(dev_priv, |
5891 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
5892 | 1)) | |
430e05de | 5893 | DRM_ERROR("Couldn't disable DPLL0\n"); |
1cd593e0 | 5894 | |
63911d72 | 5895 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
5896 | } |
5897 | ||
5d96d8af DL |
5898 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
5899 | { | |
5900 | int ret; | |
5901 | u32 val; | |
5902 | ||
5903 | /* inform PCU we want to change CDCLK */ | |
5904 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5905 | mutex_lock(&dev_priv->rps.hw_lock); | |
5906 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5907 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5908 | ||
5909 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5910 | } | |
5911 | ||
5912 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5913 | { | |
848496e5 | 5914 | return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0; |
5d96d8af DL |
5915 | } |
5916 | ||
1cd593e0 | 5917 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af | 5918 | { |
91c8a326 | 5919 | struct drm_device *dev = &dev_priv->drm; |
5d96d8af DL |
5920 | u32 freq_select, pcu_ack; |
5921 | ||
1cd593e0 VS |
5922 | WARN_ON((cdclk == 24000) != (vco == 0)); |
5923 | ||
63911d72 | 5924 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
5925 | |
5926 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5927 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5928 | return; | |
5929 | } | |
5930 | ||
5931 | /* set CDCLK_CTL */ | |
9ef56154 | 5932 | switch (cdclk) { |
5d96d8af DL |
5933 | case 450000: |
5934 | case 432000: | |
5935 | freq_select = CDCLK_FREQ_450_432; | |
5936 | pcu_ack = 1; | |
5937 | break; | |
5938 | case 540000: | |
5939 | freq_select = CDCLK_FREQ_540; | |
5940 | pcu_ack = 2; | |
5941 | break; | |
487ed2e4 | 5942 | case 308571: |
5d96d8af DL |
5943 | case 337500: |
5944 | default: | |
5945 | freq_select = CDCLK_FREQ_337_308; | |
5946 | pcu_ack = 0; | |
5947 | break; | |
487ed2e4 | 5948 | case 617143: |
5d96d8af DL |
5949 | case 675000: |
5950 | freq_select = CDCLK_FREQ_675_617; | |
5951 | pcu_ack = 3; | |
5952 | break; | |
5953 | } | |
5954 | ||
63911d72 VS |
5955 | if (dev_priv->cdclk_pll.vco != 0 && |
5956 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
5957 | skl_dpll0_disable(dev_priv); |
5958 | ||
63911d72 | 5959 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
5960 | skl_dpll0_enable(dev_priv, vco); |
5961 | ||
9ef56154 | 5962 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
5963 | POSTING_READ(CDCLK_CTL); |
5964 | ||
5965 | /* inform PCU of the change */ | |
5966 | mutex_lock(&dev_priv->rps.hw_lock); | |
5967 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5968 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5969 | |
5970 | intel_update_cdclk(dev); | |
5d96d8af DL |
5971 | } |
5972 | ||
9f7eb31a VS |
5973 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
5974 | ||
5d96d8af DL |
5975 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
5976 | { | |
709e05c3 | 5977 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
5978 | } |
5979 | ||
5980 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5981 | { | |
9f7eb31a VS |
5982 | int cdclk, vco; |
5983 | ||
5984 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 5985 | |
63911d72 | 5986 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
5987 | /* |
5988 | * Use the current vco as our initial | |
5989 | * guess as to what the preferred vco is. | |
5990 | */ | |
5991 | if (dev_priv->skl_preferred_vco_freq == 0) | |
5992 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 5993 | dev_priv->cdclk_pll.vco); |
70c2c184 | 5994 | return; |
1cd593e0 | 5995 | } |
5d96d8af | 5996 | |
70c2c184 VS |
5997 | vco = dev_priv->skl_preferred_vco_freq; |
5998 | if (vco == 0) | |
63911d72 | 5999 | vco = 8100000; |
70c2c184 | 6000 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 6001 | |
70c2c184 | 6002 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
6003 | } |
6004 | ||
9f7eb31a | 6005 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 6006 | { |
09492498 | 6007 | uint32_t cdctl, expected; |
c73666f3 | 6008 | |
f1b391a5 SK |
6009 | /* |
6010 | * check if the pre-os intialized the display | |
6011 | * There is SWF18 scratchpad register defined which is set by the | |
6012 | * pre-os which can be used by the OS drivers to check the status | |
6013 | */ | |
6014 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
6015 | goto sanitize; | |
6016 | ||
91c8a326 | 6017 | intel_update_cdclk(&dev_priv->drm); |
c73666f3 | 6018 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
6019 | if (dev_priv->cdclk_pll.vco == 0 || |
6020 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
6021 | goto sanitize; |
6022 | ||
6023 | /* DPLL okay; verify the cdclock | |
6024 | * | |
6025 | * Noticed in some instances that the freq selection is correct but | |
6026 | * decimal part is programmed wrong from BIOS where pre-os does not | |
6027 | * enable display. Verify the same as well. | |
6028 | */ | |
09492498 VS |
6029 | cdctl = I915_READ(CDCLK_CTL); |
6030 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
6031 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6032 | if (cdctl == expected) | |
c73666f3 | 6033 | /* All well; nothing to sanitize */ |
9f7eb31a | 6034 | return; |
c89e39f3 | 6035 | |
9f7eb31a VS |
6036 | sanitize: |
6037 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 6038 | |
9f7eb31a VS |
6039 | /* force cdclk programming */ |
6040 | dev_priv->cdclk_freq = 0; | |
6041 | /* force full PLL disable + enable */ | |
63911d72 | 6042 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
6043 | } |
6044 | ||
30a970c6 JB |
6045 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
6046 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
6047 | { | |
fac5e23e | 6048 | struct drm_i915_private *dev_priv = to_i915(dev); |
30a970c6 JB |
6049 | u32 val, cmd; |
6050 | ||
164dfd28 VK |
6051 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6052 | != dev_priv->cdclk_freq); | |
d60c4473 | 6053 | |
dfcab17e | 6054 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 6055 | cmd = 2; |
dfcab17e | 6056 | else if (cdclk == 266667) |
30a970c6 JB |
6057 | cmd = 1; |
6058 | else | |
6059 | cmd = 0; | |
6060 | ||
6061 | mutex_lock(&dev_priv->rps.hw_lock); | |
6062 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6063 | val &= ~DSPFREQGUAR_MASK; | |
6064 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
6065 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6066 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6067 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
6068 | 50)) { | |
6069 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6070 | } | |
6071 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6072 | ||
54433e91 VS |
6073 | mutex_lock(&dev_priv->sb_lock); |
6074 | ||
dfcab17e | 6075 | if (cdclk == 400000) { |
6bcda4f0 | 6076 | u32 divider; |
30a970c6 | 6077 | |
6bcda4f0 | 6078 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 6079 | |
30a970c6 JB |
6080 | /* adjust cdclk divider */ |
6081 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 6082 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
6083 | val |= divider; |
6084 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
6085 | |
6086 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 6087 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
6088 | 50)) |
6089 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
6090 | } |
6091 | ||
30a970c6 JB |
6092 | /* adjust self-refresh exit latency value */ |
6093 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
6094 | val &= ~0x7f; | |
6095 | ||
6096 | /* | |
6097 | * For high bandwidth configs, we set a higher latency in the bunit | |
6098 | * so that the core display fetch happens in time to avoid underruns. | |
6099 | */ | |
dfcab17e | 6100 | if (cdclk == 400000) |
30a970c6 JB |
6101 | val |= 4500 / 250; /* 4.5 usec */ |
6102 | else | |
6103 | val |= 3000 / 250; /* 3.0 usec */ | |
6104 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 6105 | |
a580516d | 6106 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 6107 | |
b6283055 | 6108 | intel_update_cdclk(dev); |
30a970c6 JB |
6109 | } |
6110 | ||
383c5a6a VS |
6111 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
6112 | { | |
fac5e23e | 6113 | struct drm_i915_private *dev_priv = to_i915(dev); |
383c5a6a VS |
6114 | u32 val, cmd; |
6115 | ||
164dfd28 VK |
6116 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6117 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
6118 | |
6119 | switch (cdclk) { | |
383c5a6a VS |
6120 | case 333333: |
6121 | case 320000: | |
383c5a6a | 6122 | case 266667: |
383c5a6a | 6123 | case 200000: |
383c5a6a VS |
6124 | break; |
6125 | default: | |
5f77eeb0 | 6126 | MISSING_CASE(cdclk); |
383c5a6a VS |
6127 | return; |
6128 | } | |
6129 | ||
9d0d3fda VS |
6130 | /* |
6131 | * Specs are full of misinformation, but testing on actual | |
6132 | * hardware has shown that we just need to write the desired | |
6133 | * CCK divider into the Punit register. | |
6134 | */ | |
6135 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6136 | ||
383c5a6a VS |
6137 | mutex_lock(&dev_priv->rps.hw_lock); |
6138 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6139 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6140 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6141 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6142 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6143 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6144 | 50)) { | |
6145 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6146 | } | |
6147 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6148 | ||
b6283055 | 6149 | intel_update_cdclk(dev); |
383c5a6a VS |
6150 | } |
6151 | ||
30a970c6 JB |
6152 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6153 | int max_pixclk) | |
6154 | { | |
6bcda4f0 | 6155 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6156 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6157 | |
30a970c6 JB |
6158 | /* |
6159 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6160 | * 200MHz | |
6161 | * 267MHz | |
29dc7ef3 | 6162 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6163 | * 400MHz (VLV only) |
6164 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6165 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6166 | * |
6167 | * We seem to get an unstable or solid color picture at 200MHz. | |
6168 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6169 | * are off. | |
30a970c6 | 6170 | */ |
6cca3195 VS |
6171 | if (!IS_CHERRYVIEW(dev_priv) && |
6172 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6173 | return 400000; |
6cca3195 | 6174 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6175 | return freq_320; |
e37c67a1 | 6176 | else if (max_pixclk > 0) |
dfcab17e | 6177 | return 266667; |
e37c67a1 VS |
6178 | else |
6179 | return 200000; | |
30a970c6 JB |
6180 | } |
6181 | ||
324513c0 | 6182 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 6183 | { |
760e1477 | 6184 | if (max_pixclk > 576000) |
f8437dd1 | 6185 | return 624000; |
760e1477 | 6186 | else if (max_pixclk > 384000) |
f8437dd1 | 6187 | return 576000; |
760e1477 | 6188 | else if (max_pixclk > 288000) |
f8437dd1 | 6189 | return 384000; |
760e1477 | 6190 | else if (max_pixclk > 144000) |
f8437dd1 VK |
6191 | return 288000; |
6192 | else | |
6193 | return 144000; | |
6194 | } | |
6195 | ||
e8788cbc | 6196 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6197 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6198 | struct drm_atomic_state *state) | |
30a970c6 | 6199 | { |
565602d7 | 6200 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 6201 | struct drm_i915_private *dev_priv = to_i915(dev); |
565602d7 ML |
6202 | struct drm_crtc *crtc; |
6203 | struct drm_crtc_state *crtc_state; | |
6204 | unsigned max_pixclk = 0, i; | |
6205 | enum pipe pipe; | |
30a970c6 | 6206 | |
565602d7 ML |
6207 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6208 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6209 | |
565602d7 ML |
6210 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6211 | int pixclk = 0; | |
6212 | ||
6213 | if (crtc_state->enable) | |
6214 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6215 | |
565602d7 | 6216 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6217 | } |
6218 | ||
565602d7 ML |
6219 | for_each_pipe(dev_priv, pipe) |
6220 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6221 | ||
30a970c6 JB |
6222 | return max_pixclk; |
6223 | } | |
6224 | ||
27c329ed | 6225 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6226 | { |
27c329ed | 6227 | struct drm_device *dev = state->dev; |
fac5e23e | 6228 | struct drm_i915_private *dev_priv = to_i915(dev); |
27c329ed | 6229 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
6230 | struct intel_atomic_state *intel_state = |
6231 | to_intel_atomic_state(state); | |
30a970c6 | 6232 | |
1a617b77 | 6233 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6234 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6235 | |
1a617b77 ML |
6236 | if (!intel_state->active_crtcs) |
6237 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6238 | ||
27c329ed ML |
6239 | return 0; |
6240 | } | |
304603f4 | 6241 | |
324513c0 | 6242 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6243 | { |
4e5ca60f | 6244 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6245 | struct intel_atomic_state *intel_state = |
6246 | to_intel_atomic_state(state); | |
85a96e7a | 6247 | |
1a617b77 | 6248 | intel_state->cdclk = intel_state->dev_cdclk = |
324513c0 | 6249 | bxt_calc_cdclk(max_pixclk); |
85a96e7a | 6250 | |
1a617b77 | 6251 | if (!intel_state->active_crtcs) |
324513c0 | 6252 | intel_state->dev_cdclk = bxt_calc_cdclk(0); |
1a617b77 | 6253 | |
27c329ed | 6254 | return 0; |
30a970c6 JB |
6255 | } |
6256 | ||
1e69cd74 VS |
6257 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6258 | { | |
6259 | unsigned int credits, default_credits; | |
6260 | ||
6261 | if (IS_CHERRYVIEW(dev_priv)) | |
6262 | default_credits = PFI_CREDIT(12); | |
6263 | else | |
6264 | default_credits = PFI_CREDIT(8); | |
6265 | ||
bfa7df01 | 6266 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6267 | /* CHV suggested value is 31 or 63 */ |
6268 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6269 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6270 | else |
6271 | credits = PFI_CREDIT(15); | |
6272 | } else { | |
6273 | credits = default_credits; | |
6274 | } | |
6275 | ||
6276 | /* | |
6277 | * WA - write default credits before re-programming | |
6278 | * FIXME: should we also set the resend bit here? | |
6279 | */ | |
6280 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6281 | default_credits); | |
6282 | ||
6283 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6284 | credits | PFI_CREDIT_RESEND); | |
6285 | ||
6286 | /* | |
6287 | * FIXME is this guaranteed to clear | |
6288 | * immediately or should we poll for it? | |
6289 | */ | |
6290 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6291 | } | |
6292 | ||
27c329ed | 6293 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6294 | { |
a821fc46 | 6295 | struct drm_device *dev = old_state->dev; |
fac5e23e | 6296 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 ML |
6297 | struct intel_atomic_state *old_intel_state = |
6298 | to_intel_atomic_state(old_state); | |
6299 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6300 | |
27c329ed ML |
6301 | /* |
6302 | * FIXME: We can end up here with all power domains off, yet | |
6303 | * with a CDCLK frequency other than the minimum. To account | |
6304 | * for this take the PIPE-A power domain, which covers the HW | |
6305 | * blocks needed for the following programming. This can be | |
6306 | * removed once it's guaranteed that we get here either with | |
6307 | * the minimum CDCLK set, or the required power domains | |
6308 | * enabled. | |
6309 | */ | |
6310 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6311 | |
27c329ed ML |
6312 | if (IS_CHERRYVIEW(dev)) |
6313 | cherryview_set_cdclk(dev, req_cdclk); | |
6314 | else | |
6315 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6316 | |
27c329ed | 6317 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6318 | |
27c329ed | 6319 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6320 | } |
6321 | ||
89b667f8 JB |
6322 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6323 | { | |
6324 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6325 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6326 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6327 | struct intel_encoder *encoder; | |
b95c5321 ML |
6328 | struct intel_crtc_state *pipe_config = |
6329 | to_intel_crtc_state(crtc->state); | |
89b667f8 | 6330 | int pipe = intel_crtc->pipe; |
89b667f8 | 6331 | |
53d9f4e9 | 6332 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6333 | return; |
6334 | ||
37a5650b | 6335 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6336 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6337 | |
6338 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6339 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6340 | |
c14b0485 | 6341 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
fac5e23e | 6342 | struct drm_i915_private *dev_priv = to_i915(dev); |
c14b0485 VS |
6343 | |
6344 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6345 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6346 | } | |
6347 | ||
5b18e57c DV |
6348 | i9xx_set_pipeconf(intel_crtc); |
6349 | ||
89b667f8 | 6350 | intel_crtc->active = true; |
89b667f8 | 6351 | |
a72e4c9f | 6352 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6353 | |
89b667f8 JB |
6354 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6355 | if (encoder->pre_pll_enable) | |
6356 | encoder->pre_pll_enable(encoder); | |
6357 | ||
cd2d34d9 VS |
6358 | if (IS_CHERRYVIEW(dev)) { |
6359 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6360 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6361 | } else { | |
6362 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6363 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6364 | } |
89b667f8 JB |
6365 | |
6366 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6367 | if (encoder->pre_enable) | |
6368 | encoder->pre_enable(encoder); | |
6369 | ||
2dd24552 JB |
6370 | i9xx_pfit_enable(intel_crtc); |
6371 | ||
b95c5321 | 6372 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6373 | |
caed361d | 6374 | intel_update_watermarks(crtc); |
e1fdc473 | 6375 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6376 | |
4b3a9526 VS |
6377 | assert_vblank_disabled(crtc); |
6378 | drm_crtc_vblank_on(crtc); | |
6379 | ||
f9b61ff6 DV |
6380 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6381 | encoder->enable(encoder); | |
89b667f8 JB |
6382 | } |
6383 | ||
f13c2ef3 DV |
6384 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6385 | { | |
6386 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6387 | struct drm_i915_private *dev_priv = to_i915(dev); |
f13c2ef3 | 6388 | |
6e3c9717 ACO |
6389 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6390 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6391 | } |
6392 | ||
0b8765c6 | 6393 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6394 | { |
6395 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6396 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6397 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6398 | struct intel_encoder *encoder; |
b95c5321 ML |
6399 | struct intel_crtc_state *pipe_config = |
6400 | to_intel_crtc_state(crtc->state); | |
cd2d34d9 | 6401 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6402 | |
53d9f4e9 | 6403 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6404 | return; |
6405 | ||
f13c2ef3 DV |
6406 | i9xx_set_pll_dividers(intel_crtc); |
6407 | ||
37a5650b | 6408 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6409 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6410 | |
6411 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6412 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6413 | |
5b18e57c DV |
6414 | i9xx_set_pipeconf(intel_crtc); |
6415 | ||
f7abfe8b | 6416 | intel_crtc->active = true; |
6b383a7f | 6417 | |
4a3436e8 | 6418 | if (!IS_GEN2(dev)) |
a72e4c9f | 6419 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6420 | |
9d6d9f19 MK |
6421 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6422 | if (encoder->pre_enable) | |
6423 | encoder->pre_enable(encoder); | |
6424 | ||
f6736a1a DV |
6425 | i9xx_enable_pll(intel_crtc); |
6426 | ||
2dd24552 JB |
6427 | i9xx_pfit_enable(intel_crtc); |
6428 | ||
b95c5321 | 6429 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6430 | |
f37fcc2a | 6431 | intel_update_watermarks(crtc); |
e1fdc473 | 6432 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6433 | |
4b3a9526 VS |
6434 | assert_vblank_disabled(crtc); |
6435 | drm_crtc_vblank_on(crtc); | |
6436 | ||
f9b61ff6 DV |
6437 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6438 | encoder->enable(encoder); | |
0b8765c6 | 6439 | } |
79e53945 | 6440 | |
87476d63 DV |
6441 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6442 | { | |
6443 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6444 | struct drm_i915_private *dev_priv = to_i915(dev); |
87476d63 | 6445 | |
6e3c9717 | 6446 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6447 | return; |
87476d63 | 6448 | |
328d8e82 | 6449 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6450 | |
328d8e82 DV |
6451 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6452 | I915_READ(PFIT_CONTROL)); | |
6453 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6454 | } |
6455 | ||
0b8765c6 JB |
6456 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6457 | { | |
6458 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 6459 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b8765c6 | 6460 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6461 | struct intel_encoder *encoder; |
0b8765c6 | 6462 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6463 | |
6304cd91 VS |
6464 | /* |
6465 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6466 | * wait for planes to fully turn off before disabling the pipe. | |
6467 | */ | |
90e83e53 ACO |
6468 | if (IS_GEN2(dev)) |
6469 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6470 | |
4b3a9526 VS |
6471 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6472 | encoder->disable(encoder); | |
6473 | ||
f9b61ff6 DV |
6474 | drm_crtc_vblank_off(crtc); |
6475 | assert_vblank_disabled(crtc); | |
6476 | ||
575f7ab7 | 6477 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6478 | |
87476d63 | 6479 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6480 | |
89b667f8 JB |
6481 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6482 | if (encoder->post_disable) | |
6483 | encoder->post_disable(encoder); | |
6484 | ||
d7edc4e5 | 6485 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6486 | if (IS_CHERRYVIEW(dev)) |
6487 | chv_disable_pll(dev_priv, pipe); | |
6488 | else if (IS_VALLEYVIEW(dev)) | |
6489 | vlv_disable_pll(dev_priv, pipe); | |
6490 | else | |
1c4e0274 | 6491 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6492 | } |
0b8765c6 | 6493 | |
d6db995f VS |
6494 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6495 | if (encoder->post_pll_disable) | |
6496 | encoder->post_pll_disable(encoder); | |
6497 | ||
4a3436e8 | 6498 | if (!IS_GEN2(dev)) |
a72e4c9f | 6499 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6500 | } |
6501 | ||
b17d48e2 ML |
6502 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6503 | { | |
842e0307 | 6504 | struct intel_encoder *encoder; |
b17d48e2 ML |
6505 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6506 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6507 | enum intel_display_power_domain domain; | |
6508 | unsigned long domains; | |
6509 | ||
6510 | if (!intel_crtc->active) | |
6511 | return; | |
6512 | ||
a539205a | 6513 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
5a21b665 | 6514 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6515 | |
2622a081 | 6516 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6517 | |
6518 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6519 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6520 | } |
6521 | ||
b17d48e2 | 6522 | dev_priv->display.crtc_disable(crtc); |
842e0307 | 6523 | |
78108b7c VS |
6524 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6525 | crtc->base.id, crtc->name); | |
842e0307 ML |
6526 | |
6527 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6528 | crtc->state->active = false; | |
37d9078b | 6529 | intel_crtc->active = false; |
842e0307 ML |
6530 | crtc->enabled = false; |
6531 | crtc->state->connector_mask = 0; | |
6532 | crtc->state->encoder_mask = 0; | |
6533 | ||
6534 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6535 | encoder->base.crtc = NULL; | |
6536 | ||
58f9c0bc | 6537 | intel_fbc_disable(intel_crtc); |
37d9078b | 6538 | intel_update_watermarks(crtc); |
1f7457b1 | 6539 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6540 | |
6541 | domains = intel_crtc->enabled_power_domains; | |
6542 | for_each_power_domain(domain, domains) | |
6543 | intel_display_power_put(dev_priv, domain); | |
6544 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6545 | |
6546 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6547 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6548 | } |
6549 | ||
6b72d486 ML |
6550 | /* |
6551 | * turn all crtc's off, but do not adjust state | |
6552 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6553 | */ | |
70e0bd74 | 6554 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6555 | { |
e2c8b870 | 6556 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6557 | struct drm_atomic_state *state; |
e2c8b870 | 6558 | int ret; |
70e0bd74 | 6559 | |
e2c8b870 ML |
6560 | state = drm_atomic_helper_suspend(dev); |
6561 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6562 | if (ret) |
6563 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6564 | else |
6565 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6566 | return ret; |
ee7b9f93 JB |
6567 | } |
6568 | ||
ea5b213a | 6569 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6570 | { |
4ef69c7a | 6571 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6572 | |
ea5b213a CW |
6573 | drm_encoder_cleanup(encoder); |
6574 | kfree(intel_encoder); | |
7e7d76c3 JB |
6575 | } |
6576 | ||
0a91ca29 DV |
6577 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6578 | * internal consistency). */ | |
5a21b665 | 6579 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6580 | { |
5a21b665 | 6581 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6582 | |
6583 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6584 | connector->base.base.id, | |
6585 | connector->base.name); | |
6586 | ||
0a91ca29 | 6587 | if (connector->get_hw_state(connector)) { |
e85376cb | 6588 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6589 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6590 | |
35dd3c64 ML |
6591 | I915_STATE_WARN(!crtc, |
6592 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6593 | |
35dd3c64 ML |
6594 | if (!crtc) |
6595 | return; | |
6596 | ||
6597 | I915_STATE_WARN(!crtc->state->active, | |
6598 | "connector is active, but attached crtc isn't\n"); | |
6599 | ||
e85376cb | 6600 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6601 | return; |
6602 | ||
e85376cb | 6603 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6604 | "atomic encoder doesn't match attached encoder\n"); |
6605 | ||
e85376cb | 6606 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6607 | "attached encoder crtc differs from connector crtc\n"); |
6608 | } else { | |
4d688a2a ML |
6609 | I915_STATE_WARN(crtc && crtc->state->active, |
6610 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 6611 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 6612 | "best encoder set without crtc!\n"); |
0a91ca29 | 6613 | } |
79e53945 JB |
6614 | } |
6615 | ||
08d9bc92 ACO |
6616 | int intel_connector_init(struct intel_connector *connector) |
6617 | { | |
5350a031 | 6618 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6619 | |
5350a031 | 6620 | if (!connector->base.state) |
08d9bc92 ACO |
6621 | return -ENOMEM; |
6622 | ||
08d9bc92 ACO |
6623 | return 0; |
6624 | } | |
6625 | ||
6626 | struct intel_connector *intel_connector_alloc(void) | |
6627 | { | |
6628 | struct intel_connector *connector; | |
6629 | ||
6630 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6631 | if (!connector) | |
6632 | return NULL; | |
6633 | ||
6634 | if (intel_connector_init(connector) < 0) { | |
6635 | kfree(connector); | |
6636 | return NULL; | |
6637 | } | |
6638 | ||
6639 | return connector; | |
6640 | } | |
6641 | ||
f0947c37 DV |
6642 | /* Simple connector->get_hw_state implementation for encoders that support only |
6643 | * one connector and no cloning and hence the encoder state determines the state | |
6644 | * of the connector. */ | |
6645 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6646 | { |
24929352 | 6647 | enum pipe pipe = 0; |
f0947c37 | 6648 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6649 | |
f0947c37 | 6650 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6651 | } |
6652 | ||
6d293983 | 6653 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6654 | { |
6d293983 ACO |
6655 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6656 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6657 | |
6658 | return 0; | |
6659 | } | |
6660 | ||
6d293983 | 6661 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6662 | struct intel_crtc_state *pipe_config) |
1857e1da | 6663 | { |
6d293983 ACO |
6664 | struct drm_atomic_state *state = pipe_config->base.state; |
6665 | struct intel_crtc *other_crtc; | |
6666 | struct intel_crtc_state *other_crtc_state; | |
6667 | ||
1857e1da DV |
6668 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6669 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6670 | if (pipe_config->fdi_lanes > 4) { | |
6671 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6672 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6673 | return -EINVAL; |
1857e1da DV |
6674 | } |
6675 | ||
bafb6553 | 6676 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6677 | if (pipe_config->fdi_lanes > 2) { |
6678 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6679 | pipe_config->fdi_lanes); | |
6d293983 | 6680 | return -EINVAL; |
1857e1da | 6681 | } else { |
6d293983 | 6682 | return 0; |
1857e1da DV |
6683 | } |
6684 | } | |
6685 | ||
6686 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6687 | return 0; |
1857e1da DV |
6688 | |
6689 | /* Ivybridge 3 pipe is really complicated */ | |
6690 | switch (pipe) { | |
6691 | case PIPE_A: | |
6d293983 | 6692 | return 0; |
1857e1da | 6693 | case PIPE_B: |
6d293983 ACO |
6694 | if (pipe_config->fdi_lanes <= 2) |
6695 | return 0; | |
6696 | ||
6697 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6698 | other_crtc_state = | |
6699 | intel_atomic_get_crtc_state(state, other_crtc); | |
6700 | if (IS_ERR(other_crtc_state)) | |
6701 | return PTR_ERR(other_crtc_state); | |
6702 | ||
6703 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6704 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6705 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6706 | return -EINVAL; |
1857e1da | 6707 | } |
6d293983 | 6708 | return 0; |
1857e1da | 6709 | case PIPE_C: |
251cc67c VS |
6710 | if (pipe_config->fdi_lanes > 2) { |
6711 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6712 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6713 | return -EINVAL; |
251cc67c | 6714 | } |
6d293983 ACO |
6715 | |
6716 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6717 | other_crtc_state = | |
6718 | intel_atomic_get_crtc_state(state, other_crtc); | |
6719 | if (IS_ERR(other_crtc_state)) | |
6720 | return PTR_ERR(other_crtc_state); | |
6721 | ||
6722 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6723 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6724 | return -EINVAL; |
1857e1da | 6725 | } |
6d293983 | 6726 | return 0; |
1857e1da DV |
6727 | default: |
6728 | BUG(); | |
6729 | } | |
6730 | } | |
6731 | ||
e29c22c0 DV |
6732 | #define RETRY 1 |
6733 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6734 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6735 | { |
1857e1da | 6736 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6737 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6738 | int lane, link_bw, fdi_dotclock, ret; |
6739 | bool needs_recompute = false; | |
877d48d5 | 6740 | |
e29c22c0 | 6741 | retry: |
877d48d5 DV |
6742 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6743 | * each output octet as 10 bits. The actual frequency | |
6744 | * is stored as a divider into a 100MHz clock, and the | |
6745 | * mode pixel clock is stored in units of 1KHz. | |
6746 | * Hence the bw of each lane in terms of the mode signal | |
6747 | * is: | |
6748 | */ | |
21a727b3 | 6749 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6750 | |
241bfc38 | 6751 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6752 | |
2bd89a07 | 6753 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6754 | pipe_config->pipe_bpp); |
6755 | ||
6756 | pipe_config->fdi_lanes = lane; | |
6757 | ||
2bd89a07 | 6758 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6759 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6760 | |
e3b247da | 6761 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6762 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6763 | pipe_config->pipe_bpp -= 2*3; |
6764 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6765 | pipe_config->pipe_bpp); | |
6766 | needs_recompute = true; | |
6767 | pipe_config->bw_constrained = true; | |
6768 | ||
6769 | goto retry; | |
6770 | } | |
6771 | ||
6772 | if (needs_recompute) | |
6773 | return RETRY; | |
6774 | ||
6d293983 | 6775 | return ret; |
877d48d5 DV |
6776 | } |
6777 | ||
8cfb3407 VS |
6778 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6779 | struct intel_crtc_state *pipe_config) | |
6780 | { | |
6781 | if (pipe_config->pipe_bpp > 24) | |
6782 | return false; | |
6783 | ||
6784 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 6785 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
6786 | return true; |
6787 | ||
6788 | /* | |
b432e5cf VS |
6789 | * We compare against max which means we must take |
6790 | * the increased cdclk requirement into account when | |
6791 | * calculating the new cdclk. | |
6792 | * | |
6793 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6794 | */ |
6795 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6796 | dev_priv->max_cdclk_freq * 95 / 100; | |
6797 | } | |
6798 | ||
42db64ef | 6799 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6800 | struct intel_crtc_state *pipe_config) |
42db64ef | 6801 | { |
8cfb3407 | 6802 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6803 | struct drm_i915_private *dev_priv = to_i915(dev); |
8cfb3407 | 6804 | |
d330a953 | 6805 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6806 | hsw_crtc_supports_ips(crtc) && |
6807 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6808 | } |
6809 | ||
39acb4aa VS |
6810 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6811 | { | |
6812 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6813 | ||
6814 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6815 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6816 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6817 | } | |
6818 | ||
a43f6e0f | 6819 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6820 | struct intel_crtc_state *pipe_config) |
79e53945 | 6821 | { |
a43f6e0f | 6822 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6823 | struct drm_i915_private *dev_priv = to_i915(dev); |
7c5f93b0 | 6824 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 6825 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 6826 | |
cf532bb2 | 6827 | if (INTEL_INFO(dev)->gen < 4) { |
f3261156 | 6828 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6829 | |
6830 | /* | |
39acb4aa | 6831 | * Enable double wide mode when the dot clock |
cf532bb2 | 6832 | * is > 90% of the (display) core speed. |
cf532bb2 | 6833 | */ |
39acb4aa VS |
6834 | if (intel_crtc_supports_double_wide(crtc) && |
6835 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 6836 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 6837 | pipe_config->double_wide = true; |
ad3a4479 | 6838 | } |
f3261156 | 6839 | } |
ad3a4479 | 6840 | |
f3261156 VS |
6841 | if (adjusted_mode->crtc_clock > clock_limit) { |
6842 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6843 | adjusted_mode->crtc_clock, clock_limit, | |
6844 | yesno(pipe_config->double_wide)); | |
6845 | return -EINVAL; | |
2c07245f | 6846 | } |
89749350 | 6847 | |
1d1d0e27 VS |
6848 | /* |
6849 | * Pipe horizontal size must be even in: | |
6850 | * - DVO ganged mode | |
6851 | * - LVDS dual channel mode | |
6852 | * - Double wide pipe | |
6853 | */ | |
2d84d2b3 | 6854 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6855 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6856 | pipe_config->pipe_src_w &= ~1; | |
6857 | ||
8693a824 DL |
6858 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6859 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6860 | */ |
6861 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6862 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6863 | return -EINVAL; |
44f46b42 | 6864 | |
f5adf94e | 6865 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6866 | hsw_compute_ips_config(crtc, pipe_config); |
6867 | ||
877d48d5 | 6868 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6869 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6870 | |
cf5a15be | 6871 | return 0; |
79e53945 JB |
6872 | } |
6873 | ||
1652d19e VS |
6874 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6875 | { | |
6876 | struct drm_i915_private *dev_priv = to_i915(dev); | |
ea61791e | 6877 | uint32_t cdctl; |
1652d19e | 6878 | |
ea61791e | 6879 | skl_dpll0_update(dev_priv); |
1652d19e | 6880 | |
63911d72 | 6881 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 6882 | return dev_priv->cdclk_pll.ref; |
1652d19e | 6883 | |
ea61791e | 6884 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 6885 | |
63911d72 | 6886 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
6887 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6888 | case CDCLK_FREQ_450_432: | |
6889 | return 432000; | |
6890 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 6891 | return 308571; |
ea61791e VS |
6892 | case CDCLK_FREQ_540: |
6893 | return 540000; | |
1652d19e | 6894 | case CDCLK_FREQ_675_617: |
487ed2e4 | 6895 | return 617143; |
1652d19e | 6896 | default: |
ea61791e | 6897 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6898 | } |
6899 | } else { | |
1652d19e VS |
6900 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6901 | case CDCLK_FREQ_450_432: | |
6902 | return 450000; | |
6903 | case CDCLK_FREQ_337_308: | |
6904 | return 337500; | |
ea61791e VS |
6905 | case CDCLK_FREQ_540: |
6906 | return 540000; | |
1652d19e VS |
6907 | case CDCLK_FREQ_675_617: |
6908 | return 675000; | |
6909 | default: | |
ea61791e | 6910 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6911 | } |
6912 | } | |
6913 | ||
709e05c3 | 6914 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
6915 | } |
6916 | ||
83d7c81f VS |
6917 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
6918 | { | |
6919 | u32 val; | |
6920 | ||
6921 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 6922 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
6923 | |
6924 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 6925 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 6926 | return; |
83d7c81f | 6927 | |
1c3f7700 ID |
6928 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
6929 | return; | |
83d7c81f VS |
6930 | |
6931 | val = I915_READ(BXT_DE_PLL_CTL); | |
6932 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
6933 | dev_priv->cdclk_pll.ref; | |
6934 | } | |
6935 | ||
acd3f3d3 BP |
6936 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6937 | { | |
6938 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f5986242 VS |
6939 | u32 divider; |
6940 | int div, vco; | |
acd3f3d3 | 6941 | |
83d7c81f VS |
6942 | bxt_de_pll_update(dev_priv); |
6943 | ||
f5986242 VS |
6944 | vco = dev_priv->cdclk_pll.vco; |
6945 | if (vco == 0) | |
6946 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 6947 | |
f5986242 | 6948 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 6949 | |
f5986242 | 6950 | switch (divider) { |
acd3f3d3 | 6951 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
6952 | div = 2; |
6953 | break; | |
acd3f3d3 | 6954 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
f5986242 VS |
6955 | div = 3; |
6956 | break; | |
acd3f3d3 | 6957 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
6958 | div = 4; |
6959 | break; | |
acd3f3d3 | 6960 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
6961 | div = 8; |
6962 | break; | |
6963 | default: | |
6964 | MISSING_CASE(divider); | |
6965 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
6966 | } |
6967 | ||
f5986242 | 6968 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
6969 | } |
6970 | ||
1652d19e VS |
6971 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6972 | { | |
fac5e23e | 6973 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
6974 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
6975 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6976 | ||
6977 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6978 | return 800000; | |
6979 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6980 | return 450000; | |
6981 | else if (freq == LCPLL_CLK_FREQ_450) | |
6982 | return 450000; | |
6983 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6984 | return 540000; | |
6985 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6986 | return 337500; | |
6987 | else | |
6988 | return 675000; | |
6989 | } | |
6990 | ||
6991 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6992 | { | |
fac5e23e | 6993 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
6994 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
6995 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6996 | ||
6997 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6998 | return 800000; | |
6999 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7000 | return 450000; | |
7001 | else if (freq == LCPLL_CLK_FREQ_450) | |
7002 | return 450000; | |
7003 | else if (IS_HSW_ULT(dev)) | |
7004 | return 337500; | |
7005 | else | |
7006 | return 540000; | |
79e53945 JB |
7007 | } |
7008 | ||
25eb05fc JB |
7009 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
7010 | { | |
bfa7df01 VS |
7011 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
7012 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
7013 | } |
7014 | ||
b37a6434 VS |
7015 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
7016 | { | |
7017 | return 450000; | |
7018 | } | |
7019 | ||
e70236a8 JB |
7020 | static int i945_get_display_clock_speed(struct drm_device *dev) |
7021 | { | |
7022 | return 400000; | |
7023 | } | |
79e53945 | 7024 | |
e70236a8 | 7025 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 7026 | { |
e907f170 | 7027 | return 333333; |
e70236a8 | 7028 | } |
79e53945 | 7029 | |
e70236a8 JB |
7030 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
7031 | { | |
7032 | return 200000; | |
7033 | } | |
79e53945 | 7034 | |
257a7ffc DV |
7035 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
7036 | { | |
7037 | u16 gcfgc = 0; | |
7038 | ||
7039 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
7040 | ||
7041 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7042 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 7043 | return 266667; |
257a7ffc | 7044 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 7045 | return 333333; |
257a7ffc | 7046 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 7047 | return 444444; |
257a7ffc DV |
7048 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
7049 | return 200000; | |
7050 | default: | |
7051 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
7052 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 7053 | return 133333; |
257a7ffc | 7054 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 7055 | return 166667; |
257a7ffc DV |
7056 | } |
7057 | } | |
7058 | ||
e70236a8 JB |
7059 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
7060 | { | |
7061 | u16 gcfgc = 0; | |
79e53945 | 7062 | |
e70236a8 JB |
7063 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
7064 | ||
7065 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 7066 | return 133333; |
e70236a8 JB |
7067 | else { |
7068 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7069 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 7070 | return 333333; |
e70236a8 JB |
7071 | default: |
7072 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
7073 | return 190000; | |
79e53945 | 7074 | } |
e70236a8 JB |
7075 | } |
7076 | } | |
7077 | ||
7078 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
7079 | { | |
e907f170 | 7080 | return 266667; |
e70236a8 JB |
7081 | } |
7082 | ||
1b1d2716 | 7083 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
7084 | { |
7085 | u16 hpllcc = 0; | |
1b1d2716 | 7086 | |
65cd2b3f VS |
7087 | /* |
7088 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
7089 | * encoding is different :( | |
7090 | * FIXME is this the right way to detect 852GM/852GMV? | |
7091 | */ | |
7092 | if (dev->pdev->revision == 0x1) | |
7093 | return 133333; | |
7094 | ||
1b1d2716 VS |
7095 | pci_bus_read_config_word(dev->pdev->bus, |
7096 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
7097 | ||
e70236a8 JB |
7098 | /* Assume that the hardware is in the high speed state. This |
7099 | * should be the default. | |
7100 | */ | |
7101 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
7102 | case GC_CLOCK_133_200: | |
1b1d2716 | 7103 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
7104 | case GC_CLOCK_100_200: |
7105 | return 200000; | |
7106 | case GC_CLOCK_166_250: | |
7107 | return 250000; | |
7108 | case GC_CLOCK_100_133: | |
e907f170 | 7109 | return 133333; |
1b1d2716 VS |
7110 | case GC_CLOCK_133_266: |
7111 | case GC_CLOCK_133_266_2: | |
7112 | case GC_CLOCK_166_266: | |
7113 | return 266667; | |
e70236a8 | 7114 | } |
79e53945 | 7115 | |
e70236a8 JB |
7116 | /* Shouldn't happen */ |
7117 | return 0; | |
7118 | } | |
79e53945 | 7119 | |
e70236a8 JB |
7120 | static int i830_get_display_clock_speed(struct drm_device *dev) |
7121 | { | |
e907f170 | 7122 | return 133333; |
79e53945 JB |
7123 | } |
7124 | ||
34edce2f VS |
7125 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
7126 | { | |
fac5e23e | 7127 | struct drm_i915_private *dev_priv = to_i915(dev); |
34edce2f VS |
7128 | static const unsigned int blb_vco[8] = { |
7129 | [0] = 3200000, | |
7130 | [1] = 4000000, | |
7131 | [2] = 5333333, | |
7132 | [3] = 4800000, | |
7133 | [4] = 6400000, | |
7134 | }; | |
7135 | static const unsigned int pnv_vco[8] = { | |
7136 | [0] = 3200000, | |
7137 | [1] = 4000000, | |
7138 | [2] = 5333333, | |
7139 | [3] = 4800000, | |
7140 | [4] = 2666667, | |
7141 | }; | |
7142 | static const unsigned int cl_vco[8] = { | |
7143 | [0] = 3200000, | |
7144 | [1] = 4000000, | |
7145 | [2] = 5333333, | |
7146 | [3] = 6400000, | |
7147 | [4] = 3333333, | |
7148 | [5] = 3566667, | |
7149 | [6] = 4266667, | |
7150 | }; | |
7151 | static const unsigned int elk_vco[8] = { | |
7152 | [0] = 3200000, | |
7153 | [1] = 4000000, | |
7154 | [2] = 5333333, | |
7155 | [3] = 4800000, | |
7156 | }; | |
7157 | static const unsigned int ctg_vco[8] = { | |
7158 | [0] = 3200000, | |
7159 | [1] = 4000000, | |
7160 | [2] = 5333333, | |
7161 | [3] = 6400000, | |
7162 | [4] = 2666667, | |
7163 | [5] = 4266667, | |
7164 | }; | |
7165 | const unsigned int *vco_table; | |
7166 | unsigned int vco; | |
7167 | uint8_t tmp = 0; | |
7168 | ||
7169 | /* FIXME other chipsets? */ | |
7170 | if (IS_GM45(dev)) | |
7171 | vco_table = ctg_vco; | |
7172 | else if (IS_G4X(dev)) | |
7173 | vco_table = elk_vco; | |
7174 | else if (IS_CRESTLINE(dev)) | |
7175 | vco_table = cl_vco; | |
7176 | else if (IS_PINEVIEW(dev)) | |
7177 | vco_table = pnv_vco; | |
7178 | else if (IS_G33(dev)) | |
7179 | vco_table = blb_vco; | |
7180 | else | |
7181 | return 0; | |
7182 | ||
7183 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7184 | ||
7185 | vco = vco_table[tmp & 0x7]; | |
7186 | if (vco == 0) | |
7187 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7188 | else | |
7189 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7190 | ||
7191 | return vco; | |
7192 | } | |
7193 | ||
7194 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7195 | { | |
7196 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7197 | uint16_t tmp = 0; | |
7198 | ||
7199 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7200 | ||
7201 | cdclk_sel = (tmp >> 12) & 0x1; | |
7202 | ||
7203 | switch (vco) { | |
7204 | case 2666667: | |
7205 | case 4000000: | |
7206 | case 5333333: | |
7207 | return cdclk_sel ? 333333 : 222222; | |
7208 | case 3200000: | |
7209 | return cdclk_sel ? 320000 : 228571; | |
7210 | default: | |
7211 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7212 | return 222222; | |
7213 | } | |
7214 | } | |
7215 | ||
7216 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7217 | { | |
7218 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7219 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7220 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7221 | const uint8_t *div_table; | |
7222 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7223 | uint16_t tmp = 0; | |
7224 | ||
7225 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7226 | ||
7227 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7228 | ||
7229 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7230 | goto fail; | |
7231 | ||
7232 | switch (vco) { | |
7233 | case 3200000: | |
7234 | div_table = div_3200; | |
7235 | break; | |
7236 | case 4000000: | |
7237 | div_table = div_4000; | |
7238 | break; | |
7239 | case 5333333: | |
7240 | div_table = div_5333; | |
7241 | break; | |
7242 | default: | |
7243 | goto fail; | |
7244 | } | |
7245 | ||
7246 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7247 | ||
caf4e252 | 7248 | fail: |
34edce2f VS |
7249 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7250 | return 200000; | |
7251 | } | |
7252 | ||
7253 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7254 | { | |
7255 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7256 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7257 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7258 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7259 | const uint8_t *div_table; | |
7260 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7261 | uint16_t tmp = 0; | |
7262 | ||
7263 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7264 | ||
7265 | cdclk_sel = (tmp >> 4) & 0x7; | |
7266 | ||
7267 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7268 | goto fail; | |
7269 | ||
7270 | switch (vco) { | |
7271 | case 3200000: | |
7272 | div_table = div_3200; | |
7273 | break; | |
7274 | case 4000000: | |
7275 | div_table = div_4000; | |
7276 | break; | |
7277 | case 4800000: | |
7278 | div_table = div_4800; | |
7279 | break; | |
7280 | case 5333333: | |
7281 | div_table = div_5333; | |
7282 | break; | |
7283 | default: | |
7284 | goto fail; | |
7285 | } | |
7286 | ||
7287 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7288 | ||
caf4e252 | 7289 | fail: |
34edce2f VS |
7290 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7291 | return 190476; | |
7292 | } | |
7293 | ||
2c07245f | 7294 | static void |
a65851af | 7295 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7296 | { |
a65851af VS |
7297 | while (*num > DATA_LINK_M_N_MASK || |
7298 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7299 | *num >>= 1; |
7300 | *den >>= 1; | |
7301 | } | |
7302 | } | |
7303 | ||
a65851af VS |
7304 | static void compute_m_n(unsigned int m, unsigned int n, |
7305 | uint32_t *ret_m, uint32_t *ret_n) | |
7306 | { | |
7307 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7308 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7309 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7310 | } | |
7311 | ||
e69d0bc1 DV |
7312 | void |
7313 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7314 | int pixel_clock, int link_clock, | |
7315 | struct intel_link_m_n *m_n) | |
2c07245f | 7316 | { |
e69d0bc1 | 7317 | m_n->tu = 64; |
a65851af VS |
7318 | |
7319 | compute_m_n(bits_per_pixel * pixel_clock, | |
7320 | link_clock * nlanes * 8, | |
7321 | &m_n->gmch_m, &m_n->gmch_n); | |
7322 | ||
7323 | compute_m_n(pixel_clock, link_clock, | |
7324 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7325 | } |
7326 | ||
a7615030 CW |
7327 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7328 | { | |
d330a953 JN |
7329 | if (i915.panel_use_ssc >= 0) |
7330 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7331 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7332 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7333 | } |
7334 | ||
7429e9d4 | 7335 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7336 | { |
7df00d7a | 7337 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7338 | } |
f47709a9 | 7339 | |
7429e9d4 DV |
7340 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7341 | { | |
7342 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7343 | } |
7344 | ||
f47709a9 | 7345 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7346 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7347 | struct dpll *reduced_clock) |
a7516a05 | 7348 | { |
f47709a9 | 7349 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7350 | u32 fp, fp2 = 0; |
7351 | ||
7352 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7353 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7354 | if (reduced_clock) |
7429e9d4 | 7355 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7356 | } else { |
190f68c5 | 7357 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7358 | if (reduced_clock) |
7429e9d4 | 7359 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7360 | } |
7361 | ||
190f68c5 | 7362 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7363 | |
f47709a9 | 7364 | crtc->lowfreq_avail = false; |
2d84d2b3 | 7365 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7366 | reduced_clock) { |
190f68c5 | 7367 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7368 | crtc->lowfreq_avail = true; |
a7516a05 | 7369 | } else { |
190f68c5 | 7370 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7371 | } |
7372 | } | |
7373 | ||
5e69f97f CML |
7374 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7375 | pipe) | |
89b667f8 JB |
7376 | { |
7377 | u32 reg_val; | |
7378 | ||
7379 | /* | |
7380 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7381 | * and set it to a reasonable value instead. | |
7382 | */ | |
ab3c759a | 7383 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7384 | reg_val &= 0xffffff00; |
7385 | reg_val |= 0x00000030; | |
ab3c759a | 7386 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7387 | |
ab3c759a | 7388 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7389 | reg_val &= 0x8cffffff; |
7390 | reg_val = 0x8c000000; | |
ab3c759a | 7391 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7392 | |
ab3c759a | 7393 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7394 | reg_val &= 0xffffff00; |
ab3c759a | 7395 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7396 | |
ab3c759a | 7397 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7398 | reg_val &= 0x00ffffff; |
7399 | reg_val |= 0xb0000000; | |
ab3c759a | 7400 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7401 | } |
7402 | ||
b551842d DV |
7403 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7404 | struct intel_link_m_n *m_n) | |
7405 | { | |
7406 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7407 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
7408 | int pipe = crtc->pipe; |
7409 | ||
e3b95f1e DV |
7410 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7411 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7412 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7413 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7414 | } |
7415 | ||
7416 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7417 | struct intel_link_m_n *m_n, |
7418 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7419 | { |
7420 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7421 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d | 7422 | int pipe = crtc->pipe; |
6e3c9717 | 7423 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7424 | |
7425 | if (INTEL_INFO(dev)->gen >= 5) { | |
7426 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7427 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7428 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7429 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7430 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7431 | * for gen < 8) and if DRRS is supported (to make sure the | |
7432 | * registers are not unnecessarily accessed). | |
7433 | */ | |
44395bfe | 7434 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7435 | crtc->config->has_drrs) { |
f769cd24 VK |
7436 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7437 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7438 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7439 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7440 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7441 | } | |
b551842d | 7442 | } else { |
e3b95f1e DV |
7443 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7444 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7445 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7446 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7447 | } |
7448 | } | |
7449 | ||
fe3cd48d | 7450 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7451 | { |
fe3cd48d R |
7452 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7453 | ||
7454 | if (m_n == M1_N1) { | |
7455 | dp_m_n = &crtc->config->dp_m_n; | |
7456 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7457 | } else if (m_n == M2_N2) { | |
7458 | ||
7459 | /* | |
7460 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7461 | * needs to be programmed into M1_N1. | |
7462 | */ | |
7463 | dp_m_n = &crtc->config->dp_m2_n2; | |
7464 | } else { | |
7465 | DRM_ERROR("Unsupported divider value\n"); | |
7466 | return; | |
7467 | } | |
7468 | ||
6e3c9717 ACO |
7469 | if (crtc->config->has_pch_encoder) |
7470 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7471 | else |
fe3cd48d | 7472 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7473 | } |
7474 | ||
251ac862 DV |
7475 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7476 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7477 | { |
03ed5cbf | 7478 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7479 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7480 | if (crtc->pipe != PIPE_A) |
7481 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7482 | |
cd2d34d9 | 7483 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7484 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7485 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7486 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7487 | ||
03ed5cbf VS |
7488 | pipe_config->dpll_hw_state.dpll_md = |
7489 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7490 | } | |
bdd4b6a6 | 7491 | |
03ed5cbf VS |
7492 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7493 | struct intel_crtc_state *pipe_config) | |
7494 | { | |
7495 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7496 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7497 | if (crtc->pipe != PIPE_A) |
7498 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7499 | ||
cd2d34d9 | 7500 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7501 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7502 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7503 | ||
03ed5cbf VS |
7504 | pipe_config->dpll_hw_state.dpll_md = |
7505 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7506 | } |
7507 | ||
d288f65f | 7508 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7509 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7510 | { |
f47709a9 | 7511 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7512 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7513 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7514 | u32 mdiv; |
a0c4da24 | 7515 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7516 | u32 coreclk, reg_val; |
a0c4da24 | 7517 | |
cd2d34d9 VS |
7518 | /* Enable Refclk */ |
7519 | I915_WRITE(DPLL(pipe), | |
7520 | pipe_config->dpll_hw_state.dpll & | |
7521 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7522 | ||
7523 | /* No need to actually set up the DPLL with DSI */ | |
7524 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7525 | return; | |
7526 | ||
a580516d | 7527 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7528 | |
d288f65f VS |
7529 | bestn = pipe_config->dpll.n; |
7530 | bestm1 = pipe_config->dpll.m1; | |
7531 | bestm2 = pipe_config->dpll.m2; | |
7532 | bestp1 = pipe_config->dpll.p1; | |
7533 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7534 | |
89b667f8 JB |
7535 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7536 | ||
7537 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7538 | if (pipe == PIPE_B) |
5e69f97f | 7539 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7540 | |
7541 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7542 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7543 | |
7544 | /* Disable target IRef on PLL */ | |
ab3c759a | 7545 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7546 | reg_val &= 0x00ffffff; |
ab3c759a | 7547 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7548 | |
7549 | /* Disable fast lock */ | |
ab3c759a | 7550 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7551 | |
7552 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7553 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7554 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7555 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7556 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7557 | |
7558 | /* | |
7559 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7560 | * but we don't support that). | |
7561 | * Note: don't use the DAC post divider as it seems unstable. | |
7562 | */ | |
7563 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7564 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7565 | |
a0c4da24 | 7566 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7567 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7568 | |
89b667f8 | 7569 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7570 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
7571 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
7572 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7573 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7574 | 0x009f0003); |
89b667f8 | 7575 | else |
ab3c759a | 7576 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7577 | 0x00d0000f); |
7578 | ||
37a5650b | 7579 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 7580 | /* Use SSC source */ |
bdd4b6a6 | 7581 | if (pipe == PIPE_A) |
ab3c759a | 7582 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7583 | 0x0df40000); |
7584 | else | |
ab3c759a | 7585 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7586 | 0x0df70000); |
7587 | } else { /* HDMI or VGA */ | |
7588 | /* Use bend source */ | |
bdd4b6a6 | 7589 | if (pipe == PIPE_A) |
ab3c759a | 7590 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7591 | 0x0df70000); |
7592 | else | |
ab3c759a | 7593 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7594 | 0x0df40000); |
7595 | } | |
a0c4da24 | 7596 | |
ab3c759a | 7597 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7598 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 7599 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 7600 | coreclk |= 0x01000000; |
ab3c759a | 7601 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7602 | |
ab3c759a | 7603 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7604 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7605 | } |
7606 | ||
d288f65f | 7607 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7608 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7609 | { |
7610 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7611 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7612 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7613 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7614 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7615 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7616 | u32 dpio_val; |
9cbe40c1 | 7617 | int vco; |
9d556c99 | 7618 | |
cd2d34d9 VS |
7619 | /* Enable Refclk and SSC */ |
7620 | I915_WRITE(DPLL(pipe), | |
7621 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7622 | ||
7623 | /* No need to actually set up the DPLL with DSI */ | |
7624 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7625 | return; | |
7626 | ||
d288f65f VS |
7627 | bestn = pipe_config->dpll.n; |
7628 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7629 | bestm1 = pipe_config->dpll.m1; | |
7630 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7631 | bestp1 = pipe_config->dpll.p1; | |
7632 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7633 | vco = pipe_config->dpll.vco; |
a945ce7e | 7634 | dpio_val = 0; |
9cbe40c1 | 7635 | loopfilter = 0; |
9d556c99 | 7636 | |
a580516d | 7637 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7638 | |
9d556c99 CML |
7639 | /* p1 and p2 divider */ |
7640 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7641 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7642 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7643 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7644 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7645 | ||
7646 | /* Feedback post-divider - m2 */ | |
7647 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7648 | ||
7649 | /* Feedback refclk divider - n and m1 */ | |
7650 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7651 | DPIO_CHV_M1_DIV_BY_2 | | |
7652 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7653 | ||
7654 | /* M2 fraction division */ | |
25a25dfc | 7655 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7656 | |
7657 | /* M2 fraction division enable */ | |
a945ce7e VP |
7658 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7659 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7660 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7661 | if (bestm2_frac) | |
7662 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7663 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7664 | |
de3a0fde VP |
7665 | /* Program digital lock detect threshold */ |
7666 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7667 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7668 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7669 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7670 | if (!bestm2_frac) | |
7671 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7672 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7673 | ||
9d556c99 | 7674 | /* Loop filter */ |
9cbe40c1 VP |
7675 | if (vco == 5400000) { |
7676 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7677 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7678 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7679 | tribuf_calcntr = 0x9; | |
7680 | } else if (vco <= 6200000) { | |
7681 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7682 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7683 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7684 | tribuf_calcntr = 0x9; | |
7685 | } else if (vco <= 6480000) { | |
7686 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7687 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7688 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7689 | tribuf_calcntr = 0x8; | |
7690 | } else { | |
7691 | /* Not supported. Apply the same limits as in the max case */ | |
7692 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7693 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7694 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7695 | tribuf_calcntr = 0; | |
7696 | } | |
9d556c99 CML |
7697 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7698 | ||
968040b2 | 7699 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7700 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7701 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7702 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7703 | ||
9d556c99 CML |
7704 | /* AFC Recal */ |
7705 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7706 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7707 | DPIO_AFC_RECAL); | |
7708 | ||
a580516d | 7709 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7710 | } |
7711 | ||
d288f65f VS |
7712 | /** |
7713 | * vlv_force_pll_on - forcibly enable just the PLL | |
7714 | * @dev_priv: i915 private structure | |
7715 | * @pipe: pipe PLL to enable | |
7716 | * @dpll: PLL configuration | |
7717 | * | |
7718 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7719 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7720 | * be enabled. | |
7721 | */ | |
3f36b937 TU |
7722 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7723 | const struct dpll *dpll) | |
d288f65f VS |
7724 | { |
7725 | struct intel_crtc *crtc = | |
7726 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7727 | struct intel_crtc_state *pipe_config; |
7728 | ||
7729 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7730 | if (!pipe_config) | |
7731 | return -ENOMEM; | |
7732 | ||
7733 | pipe_config->base.crtc = &crtc->base; | |
7734 | pipe_config->pixel_multiplier = 1; | |
7735 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7736 | |
7737 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7738 | chv_compute_dpll(crtc, pipe_config); |
7739 | chv_prepare_pll(crtc, pipe_config); | |
7740 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7741 | } else { |
3f36b937 TU |
7742 | vlv_compute_dpll(crtc, pipe_config); |
7743 | vlv_prepare_pll(crtc, pipe_config); | |
7744 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7745 | } |
3f36b937 TU |
7746 | |
7747 | kfree(pipe_config); | |
7748 | ||
7749 | return 0; | |
d288f65f VS |
7750 | } |
7751 | ||
7752 | /** | |
7753 | * vlv_force_pll_off - forcibly disable just the PLL | |
7754 | * @dev_priv: i915 private structure | |
7755 | * @pipe: pipe PLL to disable | |
7756 | * | |
7757 | * Disable the PLL for @pipe. To be used in cases where we need | |
7758 | * the PLL enabled even when @pipe is not going to be enabled. | |
7759 | */ | |
7760 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7761 | { | |
7762 | if (IS_CHERRYVIEW(dev)) | |
7763 | chv_disable_pll(to_i915(dev), pipe); | |
7764 | else | |
7765 | vlv_disable_pll(to_i915(dev), pipe); | |
7766 | } | |
7767 | ||
251ac862 DV |
7768 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7769 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7770 | struct dpll *reduced_clock) |
eb1cbe48 | 7771 | { |
f47709a9 | 7772 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7773 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 7774 | u32 dpll; |
190f68c5 | 7775 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7776 | |
190f68c5 | 7777 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7778 | |
eb1cbe48 DV |
7779 | dpll = DPLL_VGA_MODE_DIS; |
7780 | ||
2d84d2b3 | 7781 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7782 | dpll |= DPLLB_MODE_LVDS; |
7783 | else | |
7784 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7785 | |
ef1b460d | 7786 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7787 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7788 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7789 | } |
198a037f | 7790 | |
3d6e9ee0 VS |
7791 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7792 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 7793 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7794 | |
37a5650b | 7795 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 7796 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7797 | |
7798 | /* compute bitmask from p1 value */ | |
7799 | if (IS_PINEVIEW(dev)) | |
7800 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7801 | else { | |
7802 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7803 | if (IS_G4X(dev) && reduced_clock) | |
7804 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7805 | } | |
7806 | switch (clock->p2) { | |
7807 | case 5: | |
7808 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7809 | break; | |
7810 | case 7: | |
7811 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7812 | break; | |
7813 | case 10: | |
7814 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7815 | break; | |
7816 | case 14: | |
7817 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7818 | break; | |
7819 | } | |
7820 | if (INTEL_INFO(dev)->gen >= 4) | |
7821 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7822 | ||
190f68c5 | 7823 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7824 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 7825 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7826 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7827 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7828 | else | |
7829 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7830 | ||
7831 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7832 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7833 | |
eb1cbe48 | 7834 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7835 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7836 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7837 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7838 | } |
7839 | } | |
7840 | ||
251ac862 DV |
7841 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7842 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7843 | struct dpll *reduced_clock) |
eb1cbe48 | 7844 | { |
f47709a9 | 7845 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7846 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 7847 | u32 dpll; |
190f68c5 | 7848 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7849 | |
190f68c5 | 7850 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7851 | |
eb1cbe48 DV |
7852 | dpll = DPLL_VGA_MODE_DIS; |
7853 | ||
2d84d2b3 | 7854 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7855 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7856 | } else { | |
7857 | if (clock->p1 == 2) | |
7858 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7859 | else | |
7860 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7861 | if (clock->p2 == 4) | |
7862 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7863 | } | |
7864 | ||
2d84d2b3 | 7865 | if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7866 | dpll |= DPLL_DVO_2X_MODE; |
7867 | ||
2d84d2b3 | 7868 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7869 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7870 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7871 | else | |
7872 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7873 | ||
7874 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7875 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7876 | } |
7877 | ||
8a654f3b | 7878 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7879 | { |
7880 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7881 | struct drm_i915_private *dev_priv = to_i915(dev); |
b0e77b9c | 7882 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7883 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7884 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7885 | uint32_t crtc_vtotal, crtc_vblank_end; |
7886 | int vsyncshift = 0; | |
4d8a62ea DV |
7887 | |
7888 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7889 | * the hw state checker will get angry at the mismatch. */ | |
7890 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7891 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7892 | |
609aeaca | 7893 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7894 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7895 | crtc_vtotal -= 1; |
7896 | crtc_vblank_end -= 1; | |
609aeaca | 7897 | |
2d84d2b3 | 7898 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7899 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7900 | else | |
7901 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7902 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7903 | if (vsyncshift < 0) |
7904 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7905 | } |
7906 | ||
7907 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7908 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7909 | |
fe2b8f9d | 7910 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7911 | (adjusted_mode->crtc_hdisplay - 1) | |
7912 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7913 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7914 | (adjusted_mode->crtc_hblank_start - 1) | |
7915 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7916 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7917 | (adjusted_mode->crtc_hsync_start - 1) | |
7918 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7919 | ||
fe2b8f9d | 7920 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7921 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7922 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7923 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7924 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7925 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7926 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7927 | (adjusted_mode->crtc_vsync_start - 1) | |
7928 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7929 | ||
b5e508d4 PZ |
7930 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7931 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7932 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7933 | * bits. */ | |
7934 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7935 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7936 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7937 | ||
bc58be60 JN |
7938 | } |
7939 | ||
7940 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7941 | { | |
7942 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7943 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
7944 | enum pipe pipe = intel_crtc->pipe; |
7945 | ||
b0e77b9c PZ |
7946 | /* pipesrc controls the size that is scaled from, which should |
7947 | * always be the user's requested size. | |
7948 | */ | |
7949 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7950 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7951 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7952 | } |
7953 | ||
1bd1bd80 | 7954 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7955 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7956 | { |
7957 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7958 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
7959 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7960 | uint32_t tmp; | |
7961 | ||
7962 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7963 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7964 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7965 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7966 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7967 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7968 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7969 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7970 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7971 | |
7972 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7973 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7974 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7975 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7976 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7977 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7978 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7979 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7980 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7981 | |
7982 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7983 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7984 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7985 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7986 | } |
bc58be60 JN |
7987 | } |
7988 | ||
7989 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7990 | struct intel_crtc_state *pipe_config) | |
7991 | { | |
7992 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7993 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 7994 | u32 tmp; |
1bd1bd80 DV |
7995 | |
7996 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7997 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7998 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7999 | ||
2d112de7 ACO |
8000 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
8001 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
8002 | } |
8003 | ||
f6a83288 | 8004 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 8005 | struct intel_crtc_state *pipe_config) |
babea61d | 8006 | { |
2d112de7 ACO |
8007 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
8008 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
8009 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
8010 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 8011 | |
2d112de7 ACO |
8012 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
8013 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
8014 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
8015 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 8016 | |
2d112de7 | 8017 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 8018 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 8019 | |
2d112de7 ACO |
8020 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
8021 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
8022 | |
8023 | mode->hsync = drm_mode_hsync(mode); | |
8024 | mode->vrefresh = drm_mode_vrefresh(mode); | |
8025 | drm_mode_set_name(mode); | |
babea61d JB |
8026 | } |
8027 | ||
84b046f3 DV |
8028 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
8029 | { | |
8030 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8031 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b046f3 DV |
8032 | uint32_t pipeconf; |
8033 | ||
9f11a9e4 | 8034 | pipeconf = 0; |
84b046f3 | 8035 | |
b6b5d049 VS |
8036 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
8037 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8038 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 8039 | |
6e3c9717 | 8040 | if (intel_crtc->config->double_wide) |
cf532bb2 | 8041 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 8042 | |
ff9ce46e | 8043 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 8044 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 8045 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 8046 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 8047 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 8048 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 8049 | |
6e3c9717 | 8050 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
8051 | case 18: |
8052 | pipeconf |= PIPECONF_6BPC; | |
8053 | break; | |
8054 | case 24: | |
8055 | pipeconf |= PIPECONF_8BPC; | |
8056 | break; | |
8057 | case 30: | |
8058 | pipeconf |= PIPECONF_10BPC; | |
8059 | break; | |
8060 | default: | |
8061 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
8062 | BUG(); | |
84b046f3 DV |
8063 | } |
8064 | } | |
8065 | ||
8066 | if (HAS_PIPE_CXSR(dev)) { | |
8067 | if (intel_crtc->lowfreq_avail) { | |
8068 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
8069 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
8070 | } else { | |
8071 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
8072 | } |
8073 | } | |
8074 | ||
6e3c9717 | 8075 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 8076 | if (INTEL_INFO(dev)->gen < 4 || |
2d84d2b3 | 8077 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
8078 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
8079 | else | |
8080 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
8081 | } else | |
84b046f3 DV |
8082 | pipeconf |= PIPECONF_PROGRESSIVE; |
8083 | ||
666a4537 WB |
8084 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8085 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 8086 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 8087 | |
84b046f3 DV |
8088 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
8089 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
8090 | } | |
8091 | ||
81c97f52 ACO |
8092 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
8093 | struct intel_crtc_state *crtc_state) | |
8094 | { | |
8095 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8096 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8097 | const struct intel_limit *limit; |
81c97f52 ACO |
8098 | int refclk = 48000; |
8099 | ||
8100 | memset(&crtc_state->dpll_hw_state, 0, | |
8101 | sizeof(crtc_state->dpll_hw_state)); | |
8102 | ||
2d84d2b3 | 8103 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
8104 | if (intel_panel_use_ssc(dev_priv)) { |
8105 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8106 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8107 | } | |
8108 | ||
8109 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 8110 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
8111 | limit = &intel_limits_i8xx_dvo; |
8112 | } else { | |
8113 | limit = &intel_limits_i8xx_dac; | |
8114 | } | |
8115 | ||
8116 | if (!crtc_state->clock_set && | |
8117 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8118 | refclk, NULL, &crtc_state->dpll)) { | |
8119 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8120 | return -EINVAL; | |
8121 | } | |
8122 | ||
8123 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
8124 | ||
8125 | return 0; | |
8126 | } | |
8127 | ||
19ec6693 ACO |
8128 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
8129 | struct intel_crtc_state *crtc_state) | |
8130 | { | |
8131 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8132 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8133 | const struct intel_limit *limit; |
19ec6693 ACO |
8134 | int refclk = 96000; |
8135 | ||
8136 | memset(&crtc_state->dpll_hw_state, 0, | |
8137 | sizeof(crtc_state->dpll_hw_state)); | |
8138 | ||
2d84d2b3 | 8139 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
8140 | if (intel_panel_use_ssc(dev_priv)) { |
8141 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8142 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8143 | } | |
8144 | ||
8145 | if (intel_is_dual_link_lvds(dev)) | |
8146 | limit = &intel_limits_g4x_dual_channel_lvds; | |
8147 | else | |
8148 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
8149 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
8150 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 8151 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 8152 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
8153 | limit = &intel_limits_g4x_sdvo; |
8154 | } else { | |
8155 | /* The option is for other outputs */ | |
8156 | limit = &intel_limits_i9xx_sdvo; | |
8157 | } | |
8158 | ||
8159 | if (!crtc_state->clock_set && | |
8160 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8161 | refclk, NULL, &crtc_state->dpll)) { | |
8162 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8163 | return -EINVAL; | |
8164 | } | |
8165 | ||
8166 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8167 | ||
8168 | return 0; | |
8169 | } | |
8170 | ||
70e8aa21 ACO |
8171 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
8172 | struct intel_crtc_state *crtc_state) | |
8173 | { | |
8174 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8175 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8176 | const struct intel_limit *limit; |
70e8aa21 ACO |
8177 | int refclk = 96000; |
8178 | ||
8179 | memset(&crtc_state->dpll_hw_state, 0, | |
8180 | sizeof(crtc_state->dpll_hw_state)); | |
8181 | ||
2d84d2b3 | 8182 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8183 | if (intel_panel_use_ssc(dev_priv)) { |
8184 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8185 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8186 | } | |
8187 | ||
8188 | limit = &intel_limits_pineview_lvds; | |
8189 | } else { | |
8190 | limit = &intel_limits_pineview_sdvo; | |
8191 | } | |
8192 | ||
8193 | if (!crtc_state->clock_set && | |
8194 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8195 | refclk, NULL, &crtc_state->dpll)) { | |
8196 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8197 | return -EINVAL; | |
8198 | } | |
8199 | ||
8200 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8201 | ||
8202 | return 0; | |
8203 | } | |
8204 | ||
190f68c5 ACO |
8205 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8206 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8207 | { |
c7653199 | 8208 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8209 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8210 | const struct intel_limit *limit; |
81c97f52 | 8211 | int refclk = 96000; |
79e53945 | 8212 | |
dd3cd74a ACO |
8213 | memset(&crtc_state->dpll_hw_state, 0, |
8214 | sizeof(crtc_state->dpll_hw_state)); | |
8215 | ||
2d84d2b3 | 8216 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8217 | if (intel_panel_use_ssc(dev_priv)) { |
8218 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8219 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8220 | } | |
43565a06 | 8221 | |
70e8aa21 ACO |
8222 | limit = &intel_limits_i9xx_lvds; |
8223 | } else { | |
8224 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8225 | } |
79e53945 | 8226 | |
70e8aa21 ACO |
8227 | if (!crtc_state->clock_set && |
8228 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8229 | refclk, NULL, &crtc_state->dpll)) { | |
8230 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8231 | return -EINVAL; | |
f47709a9 | 8232 | } |
7026d4ac | 8233 | |
81c97f52 | 8234 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8235 | |
c8f7a0db | 8236 | return 0; |
f564048e EA |
8237 | } |
8238 | ||
65b3d6a9 ACO |
8239 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8240 | struct intel_crtc_state *crtc_state) | |
8241 | { | |
8242 | int refclk = 100000; | |
1b6f4958 | 8243 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8244 | |
8245 | memset(&crtc_state->dpll_hw_state, 0, | |
8246 | sizeof(crtc_state->dpll_hw_state)); | |
8247 | ||
65b3d6a9 ACO |
8248 | if (!crtc_state->clock_set && |
8249 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8250 | refclk, NULL, &crtc_state->dpll)) { | |
8251 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8252 | return -EINVAL; | |
8253 | } | |
8254 | ||
8255 | chv_compute_dpll(crtc, crtc_state); | |
8256 | ||
8257 | return 0; | |
8258 | } | |
8259 | ||
8260 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8261 | struct intel_crtc_state *crtc_state) | |
8262 | { | |
8263 | int refclk = 100000; | |
1b6f4958 | 8264 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8265 | |
8266 | memset(&crtc_state->dpll_hw_state, 0, | |
8267 | sizeof(crtc_state->dpll_hw_state)); | |
8268 | ||
65b3d6a9 ACO |
8269 | if (!crtc_state->clock_set && |
8270 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8271 | refclk, NULL, &crtc_state->dpll)) { | |
8272 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8273 | return -EINVAL; | |
8274 | } | |
8275 | ||
8276 | vlv_compute_dpll(crtc, crtc_state); | |
8277 | ||
8278 | return 0; | |
8279 | } | |
8280 | ||
2fa2fe9a | 8281 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8282 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8283 | { |
8284 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8285 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8286 | uint32_t tmp; |
8287 | ||
dc9e7dec VS |
8288 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8289 | return; | |
8290 | ||
2fa2fe9a | 8291 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8292 | if (!(tmp & PFIT_ENABLE)) |
8293 | return; | |
2fa2fe9a | 8294 | |
06922821 | 8295 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8296 | if (INTEL_INFO(dev)->gen < 4) { |
8297 | if (crtc->pipe != PIPE_B) | |
8298 | return; | |
2fa2fe9a DV |
8299 | } else { |
8300 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8301 | return; | |
8302 | } | |
8303 | ||
06922821 | 8304 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8305 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8306 | } |
8307 | ||
acbec814 | 8308 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8309 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8310 | { |
8311 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8312 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 8313 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 8314 | struct dpll clock; |
acbec814 | 8315 | u32 mdiv; |
662c6ecb | 8316 | int refclk = 100000; |
acbec814 | 8317 | |
b521973b VS |
8318 | /* In case of DSI, DPLL will not be used */ |
8319 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8320 | return; |
8321 | ||
a580516d | 8322 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8323 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8324 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8325 | |
8326 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8327 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8328 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8329 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8330 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8331 | ||
dccbea3b | 8332 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8333 | } |
8334 | ||
5724dbd1 DL |
8335 | static void |
8336 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8337 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8338 | { |
8339 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8340 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
8341 | u32 val, base, offset; |
8342 | int pipe = crtc->pipe, plane = crtc->plane; | |
8343 | int fourcc, pixel_format; | |
6761dd31 | 8344 | unsigned int aligned_height; |
b113d5ee | 8345 | struct drm_framebuffer *fb; |
1b842c89 | 8346 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8347 | |
42a7b088 DL |
8348 | val = I915_READ(DSPCNTR(plane)); |
8349 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8350 | return; | |
8351 | ||
d9806c9f | 8352 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8353 | if (!intel_fb) { |
1ad292b5 JB |
8354 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8355 | return; | |
8356 | } | |
8357 | ||
1b842c89 DL |
8358 | fb = &intel_fb->base; |
8359 | ||
18c5247e DV |
8360 | if (INTEL_INFO(dev)->gen >= 4) { |
8361 | if (val & DISPPLANE_TILED) { | |
49af449b | 8362 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8363 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8364 | } | |
8365 | } | |
1ad292b5 JB |
8366 | |
8367 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8368 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8369 | fb->pixel_format = fourcc; |
8370 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8371 | |
8372 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8373 | if (plane_config->tiling) |
1ad292b5 JB |
8374 | offset = I915_READ(DSPTILEOFF(plane)); |
8375 | else | |
8376 | offset = I915_READ(DSPLINOFF(plane)); | |
8377 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8378 | } else { | |
8379 | base = I915_READ(DSPADDR(plane)); | |
8380 | } | |
8381 | plane_config->base = base; | |
8382 | ||
8383 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8384 | fb->width = ((val >> 16) & 0xfff) + 1; |
8385 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8386 | |
8387 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8388 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8389 | |
b113d5ee | 8390 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8391 | fb->pixel_format, |
8392 | fb->modifier[0]); | |
1ad292b5 | 8393 | |
f37b5c2b | 8394 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8395 | |
2844a921 DL |
8396 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8397 | pipe_name(pipe), plane, fb->width, fb->height, | |
8398 | fb->bits_per_pixel, base, fb->pitches[0], | |
8399 | plane_config->size); | |
1ad292b5 | 8400 | |
2d14030b | 8401 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8402 | } |
8403 | ||
70b23a98 | 8404 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8405 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8406 | { |
8407 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8408 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
8409 | int pipe = pipe_config->cpu_transcoder; |
8410 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8411 | struct dpll clock; |
0d7b6b11 | 8412 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8413 | int refclk = 100000; |
8414 | ||
b521973b VS |
8415 | /* In case of DSI, DPLL will not be used */ |
8416 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8417 | return; | |
8418 | ||
a580516d | 8419 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8420 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8421 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8422 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8423 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8424 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8425 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8426 | |
8427 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8428 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8429 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8430 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8431 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8432 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8433 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8434 | ||
dccbea3b | 8435 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8436 | } |
8437 | ||
0e8ffe1b | 8438 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8439 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8440 | { |
8441 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8442 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8443 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8444 | uint32_t tmp; |
1729050e | 8445 | bool ret; |
0e8ffe1b | 8446 | |
1729050e ID |
8447 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8448 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8449 | return false; |
8450 | ||
e143a21c | 8451 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8452 | pipe_config->shared_dpll = NULL; |
eccb140b | 8453 | |
1729050e ID |
8454 | ret = false; |
8455 | ||
0e8ffe1b DV |
8456 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8457 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8458 | goto out; |
0e8ffe1b | 8459 | |
666a4537 | 8460 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8461 | switch (tmp & PIPECONF_BPC_MASK) { |
8462 | case PIPECONF_6BPC: | |
8463 | pipe_config->pipe_bpp = 18; | |
8464 | break; | |
8465 | case PIPECONF_8BPC: | |
8466 | pipe_config->pipe_bpp = 24; | |
8467 | break; | |
8468 | case PIPECONF_10BPC: | |
8469 | pipe_config->pipe_bpp = 30; | |
8470 | break; | |
8471 | default: | |
8472 | break; | |
8473 | } | |
8474 | } | |
8475 | ||
666a4537 WB |
8476 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8477 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8478 | pipe_config->limited_color_range = true; |
8479 | ||
282740f7 VS |
8480 | if (INTEL_INFO(dev)->gen < 4) |
8481 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8482 | ||
1bd1bd80 | 8483 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8484 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8485 | |
2fa2fe9a DV |
8486 | i9xx_get_pfit_config(crtc, pipe_config); |
8487 | ||
6c49f241 | 8488 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c VS |
8489 | /* No way to read it out on pipes B and C */ |
8490 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8491 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8492 | else | |
8493 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8494 | pipe_config->pixel_multiplier = |
8495 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8496 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8497 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8498 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8499 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8500 | pipe_config->pixel_multiplier = | |
8501 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8502 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8503 | } else { | |
8504 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8505 | * port and will be fixed up in the encoder->get_config | |
8506 | * function. */ | |
8507 | pipe_config->pixel_multiplier = 1; | |
8508 | } | |
8bcc2795 | 8509 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8510 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8511 | /* |
8512 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8513 | * on 830. Filter it out here so that we don't | |
8514 | * report errors due to that. | |
8515 | */ | |
8516 | if (IS_I830(dev)) | |
8517 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8518 | ||
8bcc2795 DV |
8519 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8520 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8521 | } else { |
8522 | /* Mask out read-only status bits. */ | |
8523 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8524 | DPLL_PORTC_READY_MASK | | |
8525 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8526 | } |
6c49f241 | 8527 | |
70b23a98 VS |
8528 | if (IS_CHERRYVIEW(dev)) |
8529 | chv_crtc_clock_get(crtc, pipe_config); | |
8530 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8531 | vlv_crtc_clock_get(crtc, pipe_config); |
8532 | else | |
8533 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8534 | |
0f64614d VS |
8535 | /* |
8536 | * Normally the dotclock is filled in by the encoder .get_config() | |
8537 | * but in case the pipe is enabled w/o any ports we need a sane | |
8538 | * default. | |
8539 | */ | |
8540 | pipe_config->base.adjusted_mode.crtc_clock = | |
8541 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8542 | ||
1729050e ID |
8543 | ret = true; |
8544 | ||
8545 | out: | |
8546 | intel_display_power_put(dev_priv, power_domain); | |
8547 | ||
8548 | return ret; | |
0e8ffe1b DV |
8549 | } |
8550 | ||
dde86e2d | 8551 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 | 8552 | { |
fac5e23e | 8553 | struct drm_i915_private *dev_priv = to_i915(dev); |
13d83a67 | 8554 | struct intel_encoder *encoder; |
1c1a24d2 | 8555 | int i; |
74cfd7ac | 8556 | u32 val, final; |
13d83a67 | 8557 | bool has_lvds = false; |
199e5d79 | 8558 | bool has_cpu_edp = false; |
199e5d79 | 8559 | bool has_panel = false; |
99eb6a01 KP |
8560 | bool has_ck505 = false; |
8561 | bool can_ssc = false; | |
1c1a24d2 | 8562 | bool using_ssc_source = false; |
13d83a67 JB |
8563 | |
8564 | /* We need to take the global config into account */ | |
b2784e15 | 8565 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8566 | switch (encoder->type) { |
8567 | case INTEL_OUTPUT_LVDS: | |
8568 | has_panel = true; | |
8569 | has_lvds = true; | |
8570 | break; | |
8571 | case INTEL_OUTPUT_EDP: | |
8572 | has_panel = true; | |
2de6905f | 8573 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8574 | has_cpu_edp = true; |
8575 | break; | |
6847d71b PZ |
8576 | default: |
8577 | break; | |
13d83a67 JB |
8578 | } |
8579 | } | |
8580 | ||
99eb6a01 | 8581 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8582 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8583 | can_ssc = has_ck505; |
8584 | } else { | |
8585 | has_ck505 = false; | |
8586 | can_ssc = true; | |
8587 | } | |
8588 | ||
1c1a24d2 L |
8589 | /* Check if any DPLLs are using the SSC source */ |
8590 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8591 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8592 | ||
8593 | if (!(temp & DPLL_VCO_ENABLE)) | |
8594 | continue; | |
8595 | ||
8596 | if ((temp & PLL_REF_INPUT_MASK) == | |
8597 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8598 | using_ssc_source = true; | |
8599 | break; | |
8600 | } | |
8601 | } | |
8602 | ||
8603 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
8604 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
8605 | |
8606 | /* Ironlake: try to setup display ref clock before DPLL | |
8607 | * enabling. This is only under driver's control after | |
8608 | * PCH B stepping, previous chipset stepping should be | |
8609 | * ignoring this setting. | |
8610 | */ | |
74cfd7ac CW |
8611 | val = I915_READ(PCH_DREF_CONTROL); |
8612 | ||
8613 | /* As we must carefully and slowly disable/enable each source in turn, | |
8614 | * compute the final state we want first and check if we need to | |
8615 | * make any changes at all. | |
8616 | */ | |
8617 | final = val; | |
8618 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8619 | if (has_ck505) | |
8620 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8621 | else | |
8622 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8623 | ||
8c07eb68 | 8624 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 8625 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 8626 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
8627 | |
8628 | if (has_panel) { | |
8629 | final |= DREF_SSC_SOURCE_ENABLE; | |
8630 | ||
8631 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8632 | final |= DREF_SSC1_ENABLE; | |
8633 | ||
8634 | if (has_cpu_edp) { | |
8635 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8636 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8637 | else | |
8638 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8639 | } else | |
8640 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
8641 | } else if (using_ssc_source) { |
8642 | final |= DREF_SSC_SOURCE_ENABLE; | |
8643 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
8644 | } |
8645 | ||
8646 | if (final == val) | |
8647 | return; | |
8648 | ||
13d83a67 | 8649 | /* Always enable nonspread source */ |
74cfd7ac | 8650 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8651 | |
99eb6a01 | 8652 | if (has_ck505) |
74cfd7ac | 8653 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8654 | else |
74cfd7ac | 8655 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8656 | |
199e5d79 | 8657 | if (has_panel) { |
74cfd7ac CW |
8658 | val &= ~DREF_SSC_SOURCE_MASK; |
8659 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8660 | |
199e5d79 | 8661 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8662 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8663 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8664 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8665 | } else |
74cfd7ac | 8666 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8667 | |
8668 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8669 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8670 | POSTING_READ(PCH_DREF_CONTROL); |
8671 | udelay(200); | |
8672 | ||
74cfd7ac | 8673 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8674 | |
8675 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8676 | if (has_cpu_edp) { |
99eb6a01 | 8677 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8678 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8679 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8680 | } else |
74cfd7ac | 8681 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8682 | } else |
74cfd7ac | 8683 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8684 | |
74cfd7ac | 8685 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8686 | POSTING_READ(PCH_DREF_CONTROL); |
8687 | udelay(200); | |
8688 | } else { | |
1c1a24d2 | 8689 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 8690 | |
74cfd7ac | 8691 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8692 | |
8693 | /* Turn off CPU output */ | |
74cfd7ac | 8694 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8695 | |
74cfd7ac | 8696 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8697 | POSTING_READ(PCH_DREF_CONTROL); |
8698 | udelay(200); | |
8699 | ||
1c1a24d2 L |
8700 | if (!using_ssc_source) { |
8701 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 8702 | |
1c1a24d2 L |
8703 | /* Turn off the SSC source */ |
8704 | val &= ~DREF_SSC_SOURCE_MASK; | |
8705 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 8706 | |
1c1a24d2 L |
8707 | /* Turn off SSC1 */ |
8708 | val &= ~DREF_SSC1_ENABLE; | |
8709 | ||
8710 | I915_WRITE(PCH_DREF_CONTROL, val); | |
8711 | POSTING_READ(PCH_DREF_CONTROL); | |
8712 | udelay(200); | |
8713 | } | |
13d83a67 | 8714 | } |
74cfd7ac CW |
8715 | |
8716 | BUG_ON(val != final); | |
13d83a67 JB |
8717 | } |
8718 | ||
f31f2d55 | 8719 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8720 | { |
f31f2d55 | 8721 | uint32_t tmp; |
dde86e2d | 8722 | |
0ff066a9 PZ |
8723 | tmp = I915_READ(SOUTH_CHICKEN2); |
8724 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8725 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8726 | |
cf3598c2 ID |
8727 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
8728 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 8729 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 8730 | |
0ff066a9 PZ |
8731 | tmp = I915_READ(SOUTH_CHICKEN2); |
8732 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8733 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8734 | |
cf3598c2 ID |
8735 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
8736 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 8737 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
8738 | } |
8739 | ||
8740 | /* WaMPhyProgramming:hsw */ | |
8741 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8742 | { | |
8743 | uint32_t tmp; | |
dde86e2d PZ |
8744 | |
8745 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8746 | tmp &= ~(0xFF << 24); | |
8747 | tmp |= (0x12 << 24); | |
8748 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8749 | ||
dde86e2d PZ |
8750 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8751 | tmp |= (1 << 11); | |
8752 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8753 | ||
8754 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8755 | tmp |= (1 << 11); | |
8756 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8757 | ||
dde86e2d PZ |
8758 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8759 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8760 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8761 | ||
8762 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8763 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8764 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8765 | ||
0ff066a9 PZ |
8766 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8767 | tmp &= ~(7 << 13); | |
8768 | tmp |= (5 << 13); | |
8769 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8770 | |
0ff066a9 PZ |
8771 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8772 | tmp &= ~(7 << 13); | |
8773 | tmp |= (5 << 13); | |
8774 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8775 | |
8776 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8777 | tmp &= ~0xFF; | |
8778 | tmp |= 0x1C; | |
8779 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8780 | ||
8781 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8782 | tmp &= ~0xFF; | |
8783 | tmp |= 0x1C; | |
8784 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8785 | ||
8786 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8787 | tmp &= ~(0xFF << 16); | |
8788 | tmp |= (0x1C << 16); | |
8789 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8790 | ||
8791 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8792 | tmp &= ~(0xFF << 16); | |
8793 | tmp |= (0x1C << 16); | |
8794 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8795 | ||
0ff066a9 PZ |
8796 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8797 | tmp |= (1 << 27); | |
8798 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8799 | |
0ff066a9 PZ |
8800 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8801 | tmp |= (1 << 27); | |
8802 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8803 | |
0ff066a9 PZ |
8804 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8805 | tmp &= ~(0xF << 28); | |
8806 | tmp |= (4 << 28); | |
8807 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8808 | |
0ff066a9 PZ |
8809 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8810 | tmp &= ~(0xF << 28); | |
8811 | tmp |= (4 << 28); | |
8812 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8813 | } |
8814 | ||
2fa86a1f PZ |
8815 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8816 | * Programming" based on the parameters passed: | |
8817 | * - Sequence to enable CLKOUT_DP | |
8818 | * - Sequence to enable CLKOUT_DP without spread | |
8819 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8820 | */ | |
8821 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8822 | bool with_fdi) | |
f31f2d55 | 8823 | { |
fac5e23e | 8824 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa86a1f PZ |
8825 | uint32_t reg, tmp; |
8826 | ||
8827 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8828 | with_spread = true; | |
c2699524 | 8829 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8830 | with_fdi = false; |
f31f2d55 | 8831 | |
a580516d | 8832 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8833 | |
8834 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8835 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8836 | tmp |= SBI_SSCCTL_PATHALT; | |
8837 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8838 | ||
8839 | udelay(24); | |
8840 | ||
2fa86a1f PZ |
8841 | if (with_spread) { |
8842 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8843 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8844 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8845 | |
2fa86a1f PZ |
8846 | if (with_fdi) { |
8847 | lpt_reset_fdi_mphy(dev_priv); | |
8848 | lpt_program_fdi_mphy(dev_priv); | |
8849 | } | |
8850 | } | |
dde86e2d | 8851 | |
c2699524 | 8852 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8853 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8854 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8855 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8856 | |
a580516d | 8857 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8858 | } |
8859 | ||
47701c3b PZ |
8860 | /* Sequence to disable CLKOUT_DP */ |
8861 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8862 | { | |
fac5e23e | 8863 | struct drm_i915_private *dev_priv = to_i915(dev); |
47701c3b PZ |
8864 | uint32_t reg, tmp; |
8865 | ||
a580516d | 8866 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8867 | |
c2699524 | 8868 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8869 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8870 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8871 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8872 | ||
8873 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8874 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8875 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8876 | tmp |= SBI_SSCCTL_PATHALT; | |
8877 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8878 | udelay(32); | |
8879 | } | |
8880 | tmp |= SBI_SSCCTL_DISABLE; | |
8881 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8882 | } | |
8883 | ||
a580516d | 8884 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8885 | } |
8886 | ||
f7be2c21 VS |
8887 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8888 | ||
8889 | static const uint16_t sscdivintphase[] = { | |
8890 | [BEND_IDX( 50)] = 0x3B23, | |
8891 | [BEND_IDX( 45)] = 0x3B23, | |
8892 | [BEND_IDX( 40)] = 0x3C23, | |
8893 | [BEND_IDX( 35)] = 0x3C23, | |
8894 | [BEND_IDX( 30)] = 0x3D23, | |
8895 | [BEND_IDX( 25)] = 0x3D23, | |
8896 | [BEND_IDX( 20)] = 0x3E23, | |
8897 | [BEND_IDX( 15)] = 0x3E23, | |
8898 | [BEND_IDX( 10)] = 0x3F23, | |
8899 | [BEND_IDX( 5)] = 0x3F23, | |
8900 | [BEND_IDX( 0)] = 0x0025, | |
8901 | [BEND_IDX( -5)] = 0x0025, | |
8902 | [BEND_IDX(-10)] = 0x0125, | |
8903 | [BEND_IDX(-15)] = 0x0125, | |
8904 | [BEND_IDX(-20)] = 0x0225, | |
8905 | [BEND_IDX(-25)] = 0x0225, | |
8906 | [BEND_IDX(-30)] = 0x0325, | |
8907 | [BEND_IDX(-35)] = 0x0325, | |
8908 | [BEND_IDX(-40)] = 0x0425, | |
8909 | [BEND_IDX(-45)] = 0x0425, | |
8910 | [BEND_IDX(-50)] = 0x0525, | |
8911 | }; | |
8912 | ||
8913 | /* | |
8914 | * Bend CLKOUT_DP | |
8915 | * steps -50 to 50 inclusive, in steps of 5 | |
8916 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8917 | * change in clock period = -(steps / 10) * 5.787 ps | |
8918 | */ | |
8919 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8920 | { | |
8921 | uint32_t tmp; | |
8922 | int idx = BEND_IDX(steps); | |
8923 | ||
8924 | if (WARN_ON(steps % 5 != 0)) | |
8925 | return; | |
8926 | ||
8927 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8928 | return; | |
8929 | ||
8930 | mutex_lock(&dev_priv->sb_lock); | |
8931 | ||
8932 | if (steps % 10 != 0) | |
8933 | tmp = 0xAAAAAAAB; | |
8934 | else | |
8935 | tmp = 0x00000000; | |
8936 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8937 | ||
8938 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8939 | tmp &= 0xffff0000; | |
8940 | tmp |= sscdivintphase[idx]; | |
8941 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8942 | ||
8943 | mutex_unlock(&dev_priv->sb_lock); | |
8944 | } | |
8945 | ||
8946 | #undef BEND_IDX | |
8947 | ||
bf8fa3d3 PZ |
8948 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8949 | { | |
bf8fa3d3 PZ |
8950 | struct intel_encoder *encoder; |
8951 | bool has_vga = false; | |
8952 | ||
b2784e15 | 8953 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8954 | switch (encoder->type) { |
8955 | case INTEL_OUTPUT_ANALOG: | |
8956 | has_vga = true; | |
8957 | break; | |
6847d71b PZ |
8958 | default: |
8959 | break; | |
bf8fa3d3 PZ |
8960 | } |
8961 | } | |
8962 | ||
f7be2c21 VS |
8963 | if (has_vga) { |
8964 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8965 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8966 | } else { |
47701c3b | 8967 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8968 | } |
bf8fa3d3 PZ |
8969 | } |
8970 | ||
dde86e2d PZ |
8971 | /* |
8972 | * Initialize reference clocks when the driver loads | |
8973 | */ | |
8974 | void intel_init_pch_refclk(struct drm_device *dev) | |
8975 | { | |
8976 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8977 | ironlake_init_pch_refclk(dev); | |
8978 | else if (HAS_PCH_LPT(dev)) | |
8979 | lpt_init_pch_refclk(dev); | |
8980 | } | |
8981 | ||
6ff93609 | 8982 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8983 | { |
fac5e23e | 8984 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
8985 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8986 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8987 | uint32_t val; |
8988 | ||
78114071 | 8989 | val = 0; |
c8203565 | 8990 | |
6e3c9717 | 8991 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8992 | case 18: |
dfd07d72 | 8993 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8994 | break; |
8995 | case 24: | |
dfd07d72 | 8996 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8997 | break; |
8998 | case 30: | |
dfd07d72 | 8999 | val |= PIPECONF_10BPC; |
c8203565 PZ |
9000 | break; |
9001 | case 36: | |
dfd07d72 | 9002 | val |= PIPECONF_12BPC; |
c8203565 PZ |
9003 | break; |
9004 | default: | |
cc769b62 PZ |
9005 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
9006 | BUG(); | |
c8203565 PZ |
9007 | } |
9008 | ||
6e3c9717 | 9009 | if (intel_crtc->config->dither) |
c8203565 PZ |
9010 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9011 | ||
6e3c9717 | 9012 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
9013 | val |= PIPECONF_INTERLACED_ILK; |
9014 | else | |
9015 | val |= PIPECONF_PROGRESSIVE; | |
9016 | ||
6e3c9717 | 9017 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 9018 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 9019 | |
c8203565 PZ |
9020 | I915_WRITE(PIPECONF(pipe), val); |
9021 | POSTING_READ(PIPECONF(pipe)); | |
9022 | } | |
9023 | ||
6ff93609 | 9024 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 9025 | { |
fac5e23e | 9026 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 9027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9028 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 9029 | u32 val = 0; |
ee2b0b38 | 9030 | |
391bf048 | 9031 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
9032 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9033 | ||
6e3c9717 | 9034 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
9035 | val |= PIPECONF_INTERLACED_ILK; |
9036 | else | |
9037 | val |= PIPECONF_PROGRESSIVE; | |
9038 | ||
702e7a56 PZ |
9039 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
9040 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
9041 | } |
9042 | ||
391bf048 JN |
9043 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
9044 | { | |
fac5e23e | 9045 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 9046 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 9047 | |
391bf048 JN |
9048 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
9049 | u32 val = 0; | |
756f85cf | 9050 | |
6e3c9717 | 9051 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
9052 | case 18: |
9053 | val |= PIPEMISC_DITHER_6_BPC; | |
9054 | break; | |
9055 | case 24: | |
9056 | val |= PIPEMISC_DITHER_8_BPC; | |
9057 | break; | |
9058 | case 30: | |
9059 | val |= PIPEMISC_DITHER_10_BPC; | |
9060 | break; | |
9061 | case 36: | |
9062 | val |= PIPEMISC_DITHER_12_BPC; | |
9063 | break; | |
9064 | default: | |
9065 | /* Case prevented by pipe_config_set_bpp. */ | |
9066 | BUG(); | |
9067 | } | |
9068 | ||
6e3c9717 | 9069 | if (intel_crtc->config->dither) |
756f85cf PZ |
9070 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
9071 | ||
391bf048 | 9072 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 9073 | } |
ee2b0b38 PZ |
9074 | } |
9075 | ||
d4b1931c PZ |
9076 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
9077 | { | |
9078 | /* | |
9079 | * Account for spread spectrum to avoid | |
9080 | * oversubscribing the link. Max center spread | |
9081 | * is 2.5%; use 5% for safety's sake. | |
9082 | */ | |
9083 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 9084 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
9085 | } |
9086 | ||
7429e9d4 | 9087 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 9088 | { |
7429e9d4 | 9089 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
9090 | } |
9091 | ||
b75ca6f6 ACO |
9092 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
9093 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 9094 | struct dpll *reduced_clock) |
79e53945 | 9095 | { |
de13a2e3 | 9096 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 9097 | struct drm_device *dev = crtc->dev; |
fac5e23e | 9098 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 9099 | u32 dpll, fp, fp2; |
3d6e9ee0 | 9100 | int factor; |
79e53945 | 9101 | |
c1858123 | 9102 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 9103 | factor = 21; |
3d6e9ee0 | 9104 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 9105 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 9106 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 9107 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 9108 | factor = 25; |
190f68c5 | 9109 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 9110 | factor = 20; |
c1858123 | 9111 | |
b75ca6f6 ACO |
9112 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
9113 | ||
190f68c5 | 9114 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
9115 | fp |= FP_CB_TUNE; |
9116 | ||
9117 | if (reduced_clock) { | |
9118 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 9119 | |
b75ca6f6 ACO |
9120 | if (reduced_clock->m < factor * reduced_clock->n) |
9121 | fp2 |= FP_CB_TUNE; | |
9122 | } else { | |
9123 | fp2 = fp; | |
9124 | } | |
9a7c7890 | 9125 | |
5eddb70b | 9126 | dpll = 0; |
2c07245f | 9127 | |
3d6e9ee0 | 9128 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
9129 | dpll |= DPLLB_MODE_LVDS; |
9130 | else | |
9131 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9132 | |
190f68c5 | 9133 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9134 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 9135 | |
3d6e9ee0 VS |
9136 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
9137 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 9138 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 9139 | |
37a5650b | 9140 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 9141 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9142 | |
a07d6787 | 9143 | /* compute bitmask from p1 value */ |
190f68c5 | 9144 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9145 | /* also FPA1 */ |
190f68c5 | 9146 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9147 | |
190f68c5 | 9148 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9149 | case 5: |
9150 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9151 | break; | |
9152 | case 7: | |
9153 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9154 | break; | |
9155 | case 10: | |
9156 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9157 | break; | |
9158 | case 14: | |
9159 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9160 | break; | |
79e53945 JB |
9161 | } |
9162 | ||
3d6e9ee0 VS |
9163 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
9164 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 9165 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9166 | else |
9167 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9168 | ||
b75ca6f6 ACO |
9169 | dpll |= DPLL_VCO_ENABLE; |
9170 | ||
9171 | crtc_state->dpll_hw_state.dpll = dpll; | |
9172 | crtc_state->dpll_hw_state.fp0 = fp; | |
9173 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
9174 | } |
9175 | ||
190f68c5 ACO |
9176 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9177 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9178 | { |
997c030c | 9179 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9180 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 9181 | struct dpll reduced_clock; |
7ed9f894 | 9182 | bool has_reduced_clock = false; |
e2b78267 | 9183 | struct intel_shared_dpll *pll; |
1b6f4958 | 9184 | const struct intel_limit *limit; |
997c030c | 9185 | int refclk = 120000; |
de13a2e3 | 9186 | |
dd3cd74a ACO |
9187 | memset(&crtc_state->dpll_hw_state, 0, |
9188 | sizeof(crtc_state->dpll_hw_state)); | |
9189 | ||
ded220e2 ACO |
9190 | crtc->lowfreq_avail = false; |
9191 | ||
9192 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
9193 | if (!crtc_state->has_pch_encoder) | |
9194 | return 0; | |
79e53945 | 9195 | |
2d84d2b3 | 9196 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
9197 | if (intel_panel_use_ssc(dev_priv)) { |
9198 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
9199 | dev_priv->vbt.lvds_ssc_freq); | |
9200 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
9201 | } | |
9202 | ||
9203 | if (intel_is_dual_link_lvds(dev)) { | |
9204 | if (refclk == 100000) | |
9205 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
9206 | else | |
9207 | limit = &intel_limits_ironlake_dual_lvds; | |
9208 | } else { | |
9209 | if (refclk == 100000) | |
9210 | limit = &intel_limits_ironlake_single_lvds_100m; | |
9211 | else | |
9212 | limit = &intel_limits_ironlake_single_lvds; | |
9213 | } | |
9214 | } else { | |
9215 | limit = &intel_limits_ironlake_dac; | |
9216 | } | |
9217 | ||
364ee29d | 9218 | if (!crtc_state->clock_set && |
997c030c ACO |
9219 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9220 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9221 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9222 | return -EINVAL; | |
f47709a9 | 9223 | } |
79e53945 | 9224 | |
b75ca6f6 ACO |
9225 | ironlake_compute_dpll(crtc, crtc_state, |
9226 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9227 | |
ded220e2 ACO |
9228 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9229 | if (pll == NULL) { | |
9230 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9231 | pipe_name(crtc->pipe)); | |
9232 | return -EINVAL; | |
3fb37703 | 9233 | } |
79e53945 | 9234 | |
2d84d2b3 | 9235 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 9236 | has_reduced_clock) |
c7653199 | 9237 | crtc->lowfreq_avail = true; |
e2b78267 | 9238 | |
c8f7a0db | 9239 | return 0; |
79e53945 JB |
9240 | } |
9241 | ||
eb14cb74 VS |
9242 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9243 | struct intel_link_m_n *m_n) | |
9244 | { | |
9245 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9246 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
9247 | enum pipe pipe = crtc->pipe; |
9248 | ||
9249 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9250 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9251 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9252 | & ~TU_SIZE_MASK; | |
9253 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9254 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9255 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9256 | } | |
9257 | ||
9258 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9259 | enum transcoder transcoder, | |
b95af8be VK |
9260 | struct intel_link_m_n *m_n, |
9261 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9262 | { |
9263 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9264 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 | 9265 | enum pipe pipe = crtc->pipe; |
72419203 | 9266 | |
eb14cb74 VS |
9267 | if (INTEL_INFO(dev)->gen >= 5) { |
9268 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9269 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9270 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9271 | & ~TU_SIZE_MASK; | |
9272 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9273 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9274 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9275 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9276 | * gen < 8) and if DRRS is supported (to make sure the | |
9277 | * registers are not unnecessarily read). | |
9278 | */ | |
9279 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9280 | crtc->config->has_drrs) { |
b95af8be VK |
9281 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9282 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9283 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9284 | & ~TU_SIZE_MASK; | |
9285 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9286 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9287 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9288 | } | |
eb14cb74 VS |
9289 | } else { |
9290 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9291 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9292 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9293 | & ~TU_SIZE_MASK; | |
9294 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9295 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9296 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9297 | } | |
9298 | } | |
9299 | ||
9300 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9301 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9302 | { |
681a8504 | 9303 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9304 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9305 | else | |
9306 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9307 | &pipe_config->dp_m_n, |
9308 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9309 | } |
72419203 | 9310 | |
eb14cb74 | 9311 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9312 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9313 | { |
9314 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9315 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9316 | } |
9317 | ||
bd2e244f | 9318 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9319 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9320 | { |
9321 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9322 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
9323 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9324 | uint32_t ps_ctrl = 0; | |
9325 | int id = -1; | |
9326 | int i; | |
bd2e244f | 9327 | |
a1b2278e CK |
9328 | /* find scaler attached to this pipe */ |
9329 | for (i = 0; i < crtc->num_scalers; i++) { | |
9330 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9331 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9332 | id = i; | |
9333 | pipe_config->pch_pfit.enabled = true; | |
9334 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9335 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9336 | break; | |
9337 | } | |
9338 | } | |
bd2e244f | 9339 | |
a1b2278e CK |
9340 | scaler_state->scaler_id = id; |
9341 | if (id >= 0) { | |
9342 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9343 | } else { | |
9344 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9345 | } |
9346 | } | |
9347 | ||
5724dbd1 DL |
9348 | static void |
9349 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9350 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9351 | { |
9352 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9353 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 9354 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9355 | int pipe = crtc->pipe; |
9356 | int fourcc, pixel_format; | |
6761dd31 | 9357 | unsigned int aligned_height; |
bc8d7dff | 9358 | struct drm_framebuffer *fb; |
1b842c89 | 9359 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9360 | |
d9806c9f | 9361 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9362 | if (!intel_fb) { |
bc8d7dff DL |
9363 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9364 | return; | |
9365 | } | |
9366 | ||
1b842c89 DL |
9367 | fb = &intel_fb->base; |
9368 | ||
bc8d7dff | 9369 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9370 | if (!(val & PLANE_CTL_ENABLE)) |
9371 | goto error; | |
9372 | ||
bc8d7dff DL |
9373 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9374 | fourcc = skl_format_to_fourcc(pixel_format, | |
9375 | val & PLANE_CTL_ORDER_RGBX, | |
9376 | val & PLANE_CTL_ALPHA_MASK); | |
9377 | fb->pixel_format = fourcc; | |
9378 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9379 | ||
40f46283 DL |
9380 | tiling = val & PLANE_CTL_TILED_MASK; |
9381 | switch (tiling) { | |
9382 | case PLANE_CTL_TILED_LINEAR: | |
9383 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9384 | break; | |
9385 | case PLANE_CTL_TILED_X: | |
9386 | plane_config->tiling = I915_TILING_X; | |
9387 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9388 | break; | |
9389 | case PLANE_CTL_TILED_Y: | |
9390 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9391 | break; | |
9392 | case PLANE_CTL_TILED_YF: | |
9393 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9394 | break; | |
9395 | default: | |
9396 | MISSING_CASE(tiling); | |
9397 | goto error; | |
9398 | } | |
9399 | ||
bc8d7dff DL |
9400 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9401 | plane_config->base = base; | |
9402 | ||
9403 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9404 | ||
9405 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9406 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9407 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9408 | ||
9409 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9410 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9411 | fb->pixel_format); |
bc8d7dff DL |
9412 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9413 | ||
9414 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9415 | fb->pixel_format, |
9416 | fb->modifier[0]); | |
bc8d7dff | 9417 | |
f37b5c2b | 9418 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9419 | |
9420 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9421 | pipe_name(pipe), fb->width, fb->height, | |
9422 | fb->bits_per_pixel, base, fb->pitches[0], | |
9423 | plane_config->size); | |
9424 | ||
2d14030b | 9425 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9426 | return; |
9427 | ||
9428 | error: | |
9429 | kfree(fb); | |
9430 | } | |
9431 | ||
2fa2fe9a | 9432 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9433 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9434 | { |
9435 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9436 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
9437 | uint32_t tmp; |
9438 | ||
9439 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9440 | ||
9441 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9442 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9443 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9444 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9445 | |
9446 | /* We currently do not free assignements of panel fitters on | |
9447 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9448 | * differentiates them) so just WARN about this case for now. */ | |
9449 | if (IS_GEN7(dev)) { | |
9450 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9451 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9452 | } | |
2fa2fe9a | 9453 | } |
79e53945 JB |
9454 | } |
9455 | ||
5724dbd1 DL |
9456 | static void |
9457 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9458 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9459 | { |
9460 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9461 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 9462 | u32 val, base, offset; |
aeee5a49 | 9463 | int pipe = crtc->pipe; |
4c6baa59 | 9464 | int fourcc, pixel_format; |
6761dd31 | 9465 | unsigned int aligned_height; |
b113d5ee | 9466 | struct drm_framebuffer *fb; |
1b842c89 | 9467 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9468 | |
42a7b088 DL |
9469 | val = I915_READ(DSPCNTR(pipe)); |
9470 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9471 | return; | |
9472 | ||
d9806c9f | 9473 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9474 | if (!intel_fb) { |
4c6baa59 JB |
9475 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9476 | return; | |
9477 | } | |
9478 | ||
1b842c89 DL |
9479 | fb = &intel_fb->base; |
9480 | ||
18c5247e DV |
9481 | if (INTEL_INFO(dev)->gen >= 4) { |
9482 | if (val & DISPPLANE_TILED) { | |
49af449b | 9483 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9484 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9485 | } | |
9486 | } | |
4c6baa59 JB |
9487 | |
9488 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9489 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9490 | fb->pixel_format = fourcc; |
9491 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9492 | |
aeee5a49 | 9493 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9494 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9495 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9496 | } else { |
49af449b | 9497 | if (plane_config->tiling) |
aeee5a49 | 9498 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9499 | else |
aeee5a49 | 9500 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9501 | } |
9502 | plane_config->base = base; | |
9503 | ||
9504 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9505 | fb->width = ((val >> 16) & 0xfff) + 1; |
9506 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9507 | |
9508 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9509 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9510 | |
b113d5ee | 9511 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9512 | fb->pixel_format, |
9513 | fb->modifier[0]); | |
4c6baa59 | 9514 | |
f37b5c2b | 9515 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9516 | |
2844a921 DL |
9517 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9518 | pipe_name(pipe), fb->width, fb->height, | |
9519 | fb->bits_per_pixel, base, fb->pitches[0], | |
9520 | plane_config->size); | |
b113d5ee | 9521 | |
2d14030b | 9522 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9523 | } |
9524 | ||
0e8ffe1b | 9525 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9526 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9527 | { |
9528 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9529 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 9530 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9531 | uint32_t tmp; |
1729050e | 9532 | bool ret; |
0e8ffe1b | 9533 | |
1729050e ID |
9534 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9535 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9536 | return false; |
9537 | ||
e143a21c | 9538 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9539 | pipe_config->shared_dpll = NULL; |
eccb140b | 9540 | |
1729050e | 9541 | ret = false; |
0e8ffe1b DV |
9542 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9543 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9544 | goto out; |
0e8ffe1b | 9545 | |
42571aef VS |
9546 | switch (tmp & PIPECONF_BPC_MASK) { |
9547 | case PIPECONF_6BPC: | |
9548 | pipe_config->pipe_bpp = 18; | |
9549 | break; | |
9550 | case PIPECONF_8BPC: | |
9551 | pipe_config->pipe_bpp = 24; | |
9552 | break; | |
9553 | case PIPECONF_10BPC: | |
9554 | pipe_config->pipe_bpp = 30; | |
9555 | break; | |
9556 | case PIPECONF_12BPC: | |
9557 | pipe_config->pipe_bpp = 36; | |
9558 | break; | |
9559 | default: | |
9560 | break; | |
9561 | } | |
9562 | ||
b5a9fa09 DV |
9563 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9564 | pipe_config->limited_color_range = true; | |
9565 | ||
ab9412ba | 9566 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9567 | struct intel_shared_dpll *pll; |
8106ddbd | 9568 | enum intel_dpll_id pll_id; |
66e985c0 | 9569 | |
88adfff1 DV |
9570 | pipe_config->has_pch_encoder = true; |
9571 | ||
627eb5a3 DV |
9572 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9573 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9574 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9575 | |
9576 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9577 | |
2d1fe073 | 9578 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9579 | /* |
9580 | * The pipe->pch transcoder and pch transcoder->pll | |
9581 | * mapping is fixed. | |
9582 | */ | |
8106ddbd | 9583 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9584 | } else { |
9585 | tmp = I915_READ(PCH_DPLL_SEL); | |
9586 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9587 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9588 | else |
8106ddbd | 9589 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9590 | } |
66e985c0 | 9591 | |
8106ddbd ACO |
9592 | pipe_config->shared_dpll = |
9593 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9594 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9595 | |
2edd6443 ACO |
9596 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9597 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9598 | |
9599 | tmp = pipe_config->dpll_hw_state.dpll; | |
9600 | pipe_config->pixel_multiplier = | |
9601 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9602 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9603 | |
9604 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9605 | } else { |
9606 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9607 | } |
9608 | ||
1bd1bd80 | 9609 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9610 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9611 | |
2fa2fe9a DV |
9612 | ironlake_get_pfit_config(crtc, pipe_config); |
9613 | ||
1729050e ID |
9614 | ret = true; |
9615 | ||
9616 | out: | |
9617 | intel_display_power_put(dev_priv, power_domain); | |
9618 | ||
9619 | return ret; | |
0e8ffe1b DV |
9620 | } |
9621 | ||
be256dc7 PZ |
9622 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9623 | { | |
91c8a326 | 9624 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 9625 | struct intel_crtc *crtc; |
be256dc7 | 9626 | |
d3fcc808 | 9627 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9628 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9629 | pipe_name(crtc->pipe)); |
9630 | ||
e2c719b7 RC |
9631 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9632 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9633 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9634 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 9635 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 9636 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 9637 | "CPU PWM1 enabled\n"); |
c5107b87 | 9638 | if (IS_HASWELL(dev)) |
e2c719b7 | 9639 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9640 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9641 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9642 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9643 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9644 | "Utility pin enabled\n"); |
e2c719b7 | 9645 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9646 | |
9926ada1 PZ |
9647 | /* |
9648 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9649 | * interrupts remain enabled. We used to check for that, but since it's | |
9650 | * gen-specific and since we only disable LCPLL after we fully disable | |
9651 | * the interrupts, the check below should be enough. | |
9652 | */ | |
e2c719b7 | 9653 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9654 | } |
9655 | ||
9ccd5aeb PZ |
9656 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9657 | { | |
91c8a326 | 9658 | struct drm_device *dev = &dev_priv->drm; |
9ccd5aeb PZ |
9659 | |
9660 | if (IS_HASWELL(dev)) | |
9661 | return I915_READ(D_COMP_HSW); | |
9662 | else | |
9663 | return I915_READ(D_COMP_BDW); | |
9664 | } | |
9665 | ||
3c4c9b81 PZ |
9666 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9667 | { | |
91c8a326 | 9668 | struct drm_device *dev = &dev_priv->drm; |
3c4c9b81 PZ |
9669 | |
9670 | if (IS_HASWELL(dev)) { | |
9671 | mutex_lock(&dev_priv->rps.hw_lock); | |
9672 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9673 | val)) | |
f475dadf | 9674 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9675 | mutex_unlock(&dev_priv->rps.hw_lock); |
9676 | } else { | |
9ccd5aeb PZ |
9677 | I915_WRITE(D_COMP_BDW, val); |
9678 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9679 | } |
be256dc7 PZ |
9680 | } |
9681 | ||
9682 | /* | |
9683 | * This function implements pieces of two sequences from BSpec: | |
9684 | * - Sequence for display software to disable LCPLL | |
9685 | * - Sequence for display software to allow package C8+ | |
9686 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9687 | * register. Callers should take care of disabling all the display engine | |
9688 | * functions, doing the mode unset, fixing interrupts, etc. | |
9689 | */ | |
6ff58d53 PZ |
9690 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9691 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9692 | { |
9693 | uint32_t val; | |
9694 | ||
9695 | assert_can_disable_lcpll(dev_priv); | |
9696 | ||
9697 | val = I915_READ(LCPLL_CTL); | |
9698 | ||
9699 | if (switch_to_fclk) { | |
9700 | val |= LCPLL_CD_SOURCE_FCLK; | |
9701 | I915_WRITE(LCPLL_CTL, val); | |
9702 | ||
f53dd63f ID |
9703 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9704 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
9705 | DRM_ERROR("Switching to FCLK failed\n"); |
9706 | ||
9707 | val = I915_READ(LCPLL_CTL); | |
9708 | } | |
9709 | ||
9710 | val |= LCPLL_PLL_DISABLE; | |
9711 | I915_WRITE(LCPLL_CTL, val); | |
9712 | POSTING_READ(LCPLL_CTL); | |
9713 | ||
24d8441d | 9714 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
9715 | DRM_ERROR("LCPLL still locked\n"); |
9716 | ||
9ccd5aeb | 9717 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9718 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9719 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9720 | ndelay(100); |
9721 | ||
9ccd5aeb PZ |
9722 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9723 | 1)) | |
be256dc7 PZ |
9724 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9725 | ||
9726 | if (allow_power_down) { | |
9727 | val = I915_READ(LCPLL_CTL); | |
9728 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9729 | I915_WRITE(LCPLL_CTL, val); | |
9730 | POSTING_READ(LCPLL_CTL); | |
9731 | } | |
9732 | } | |
9733 | ||
9734 | /* | |
9735 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9736 | * source. | |
9737 | */ | |
6ff58d53 | 9738 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9739 | { |
9740 | uint32_t val; | |
9741 | ||
9742 | val = I915_READ(LCPLL_CTL); | |
9743 | ||
9744 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9745 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9746 | return; | |
9747 | ||
a8a8bd54 PZ |
9748 | /* |
9749 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9750 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9751 | */ |
59bad947 | 9752 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9753 | |
be256dc7 PZ |
9754 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9755 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9756 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9757 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9758 | } |
9759 | ||
9ccd5aeb | 9760 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9761 | val |= D_COMP_COMP_FORCE; |
9762 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9763 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9764 | |
9765 | val = I915_READ(LCPLL_CTL); | |
9766 | val &= ~LCPLL_PLL_DISABLE; | |
9767 | I915_WRITE(LCPLL_CTL, val); | |
9768 | ||
93220c08 CW |
9769 | if (intel_wait_for_register(dev_priv, |
9770 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
9771 | 5)) | |
be256dc7 PZ |
9772 | DRM_ERROR("LCPLL not locked yet\n"); |
9773 | ||
9774 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9775 | val = I915_READ(LCPLL_CTL); | |
9776 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9777 | I915_WRITE(LCPLL_CTL, val); | |
9778 | ||
f53dd63f ID |
9779 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9780 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
9781 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9782 | } | |
215733fa | 9783 | |
59bad947 | 9784 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
91c8a326 | 9785 | intel_update_cdclk(&dev_priv->drm); |
be256dc7 PZ |
9786 | } |
9787 | ||
765dab67 PZ |
9788 | /* |
9789 | * Package states C8 and deeper are really deep PC states that can only be | |
9790 | * reached when all the devices on the system allow it, so even if the graphics | |
9791 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9792 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9793 | * | |
9794 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9795 | * well is disabled and most interrupts are disabled, and these are also | |
9796 | * requirements for runtime PM. When these conditions are met, we manually do | |
9797 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9798 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9799 | * hang the machine. | |
9800 | * | |
9801 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9802 | * the state of some registers, so when we come back from PC8+ we need to | |
9803 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9804 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9805 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9806 | * because of the runtime PM support). | |
9807 | * | |
9808 | * For more, read "Display Sequences for Package C8" on the hardware | |
9809 | * documentation. | |
9810 | */ | |
a14cb6fc | 9811 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9812 | { |
91c8a326 | 9813 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
9814 | uint32_t val; |
9815 | ||
c67a470b PZ |
9816 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9817 | ||
c2699524 | 9818 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9819 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9820 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9821 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9822 | } | |
9823 | ||
9824 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9825 | hsw_disable_lcpll(dev_priv, true, true); |
9826 | } | |
9827 | ||
a14cb6fc | 9828 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9829 | { |
91c8a326 | 9830 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
9831 | uint32_t val; |
9832 | ||
c67a470b PZ |
9833 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9834 | ||
9835 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9836 | lpt_init_pch_refclk(dev); |
9837 | ||
c2699524 | 9838 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9839 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9840 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9841 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9842 | } | |
c67a470b PZ |
9843 | } |
9844 | ||
324513c0 | 9845 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9846 | { |
a821fc46 | 9847 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9848 | struct intel_atomic_state *old_intel_state = |
9849 | to_intel_atomic_state(old_state); | |
9850 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9851 | |
324513c0 | 9852 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
9853 | } |
9854 | ||
b432e5cf | 9855 | /* compute the max rate for new configuration */ |
27c329ed | 9856 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9857 | { |
565602d7 | 9858 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 9859 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
9860 | struct drm_crtc *crtc; |
9861 | struct drm_crtc_state *cstate; | |
27c329ed | 9862 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9863 | unsigned max_pixel_rate = 0, i; |
9864 | enum pipe pipe; | |
b432e5cf | 9865 | |
565602d7 ML |
9866 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9867 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9868 | |
565602d7 ML |
9869 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9870 | int pixel_rate; | |
27c329ed | 9871 | |
565602d7 ML |
9872 | crtc_state = to_intel_crtc_state(cstate); |
9873 | if (!crtc_state->base.enable) { | |
9874 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9875 | continue; |
565602d7 | 9876 | } |
b432e5cf | 9877 | |
27c329ed | 9878 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9879 | |
9880 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9881 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9882 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9883 | ||
565602d7 | 9884 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9885 | } |
9886 | ||
565602d7 ML |
9887 | for_each_pipe(dev_priv, pipe) |
9888 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9889 | ||
b432e5cf VS |
9890 | return max_pixel_rate; |
9891 | } | |
9892 | ||
9893 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9894 | { | |
fac5e23e | 9895 | struct drm_i915_private *dev_priv = to_i915(dev); |
b432e5cf VS |
9896 | uint32_t val, data; |
9897 | int ret; | |
9898 | ||
9899 | if (WARN((I915_READ(LCPLL_CTL) & | |
9900 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9901 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9902 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9903 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9904 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9905 | return; | |
9906 | ||
9907 | mutex_lock(&dev_priv->rps.hw_lock); | |
9908 | ret = sandybridge_pcode_write(dev_priv, | |
9909 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9910 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9911 | if (ret) { | |
9912 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9913 | return; | |
9914 | } | |
9915 | ||
9916 | val = I915_READ(LCPLL_CTL); | |
9917 | val |= LCPLL_CD_SOURCE_FCLK; | |
9918 | I915_WRITE(LCPLL_CTL, val); | |
9919 | ||
5ba00178 TU |
9920 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9921 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9922 | DRM_ERROR("Switching to FCLK failed\n"); |
9923 | ||
9924 | val = I915_READ(LCPLL_CTL); | |
9925 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9926 | ||
9927 | switch (cdclk) { | |
9928 | case 450000: | |
9929 | val |= LCPLL_CLK_FREQ_450; | |
9930 | data = 0; | |
9931 | break; | |
9932 | case 540000: | |
9933 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9934 | data = 1; | |
9935 | break; | |
9936 | case 337500: | |
9937 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9938 | data = 2; | |
9939 | break; | |
9940 | case 675000: | |
9941 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9942 | data = 3; | |
9943 | break; | |
9944 | default: | |
9945 | WARN(1, "invalid cdclk frequency\n"); | |
9946 | return; | |
9947 | } | |
9948 | ||
9949 | I915_WRITE(LCPLL_CTL, val); | |
9950 | ||
9951 | val = I915_READ(LCPLL_CTL); | |
9952 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9953 | I915_WRITE(LCPLL_CTL, val); | |
9954 | ||
5ba00178 TU |
9955 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9956 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9957 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9958 | ||
9959 | mutex_lock(&dev_priv->rps.hw_lock); | |
9960 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9961 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9962 | ||
7f1052a8 VS |
9963 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
9964 | ||
b432e5cf VS |
9965 | intel_update_cdclk(dev); |
9966 | ||
9967 | WARN(cdclk != dev_priv->cdclk_freq, | |
9968 | "cdclk requested %d kHz but got %d kHz\n", | |
9969 | cdclk, dev_priv->cdclk_freq); | |
9970 | } | |
9971 | ||
587c7914 VS |
9972 | static int broadwell_calc_cdclk(int max_pixclk) |
9973 | { | |
9974 | if (max_pixclk > 540000) | |
9975 | return 675000; | |
9976 | else if (max_pixclk > 450000) | |
9977 | return 540000; | |
9978 | else if (max_pixclk > 337500) | |
9979 | return 450000; | |
9980 | else | |
9981 | return 337500; | |
9982 | } | |
9983 | ||
27c329ed | 9984 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9985 | { |
27c329ed | 9986 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9987 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9988 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9989 | int cdclk; |
9990 | ||
9991 | /* | |
9992 | * FIXME should also account for plane ratio | |
9993 | * once 64bpp pixel formats are supported. | |
9994 | */ | |
587c7914 | 9995 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 9996 | |
b432e5cf | 9997 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9998 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9999 | cdclk, dev_priv->max_cdclk_freq); | |
10000 | return -EINVAL; | |
b432e5cf VS |
10001 | } |
10002 | ||
1a617b77 ML |
10003 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
10004 | if (!intel_state->active_crtcs) | |
587c7914 | 10005 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
10006 | |
10007 | return 0; | |
10008 | } | |
10009 | ||
27c329ed | 10010 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 10011 | { |
27c329ed | 10012 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10013 | struct intel_atomic_state *old_intel_state = |
10014 | to_intel_atomic_state(old_state); | |
10015 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 10016 | |
27c329ed | 10017 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
10018 | } |
10019 | ||
c89e39f3 CT |
10020 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
10021 | { | |
10022 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
10023 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
10024 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 10025 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
10026 | int cdclk; |
10027 | ||
10028 | /* | |
10029 | * FIXME should also account for plane ratio | |
10030 | * once 64bpp pixel formats are supported. | |
10031 | */ | |
a8ca4934 | 10032 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
10033 | |
10034 | /* | |
10035 | * FIXME move the cdclk caclulation to | |
10036 | * compute_config() so we can fail gracegully. | |
10037 | */ | |
10038 | if (cdclk > dev_priv->max_cdclk_freq) { | |
10039 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
10040 | cdclk, dev_priv->max_cdclk_freq); | |
10041 | cdclk = dev_priv->max_cdclk_freq; | |
10042 | } | |
10043 | ||
10044 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
10045 | if (!intel_state->active_crtcs) | |
a8ca4934 | 10046 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
10047 | |
10048 | return 0; | |
10049 | } | |
10050 | ||
10051 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
10052 | { | |
1cd593e0 VS |
10053 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
10054 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
10055 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
10056 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 10057 | |
1cd593e0 | 10058 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
10059 | } |
10060 | ||
190f68c5 ACO |
10061 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
10062 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 10063 | { |
d7edc4e5 | 10064 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
10065 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
10066 | return -EINVAL; | |
10067 | } | |
716c2e55 | 10068 | |
c7653199 | 10069 | crtc->lowfreq_avail = false; |
644cef34 | 10070 | |
c8f7a0db | 10071 | return 0; |
79e53945 JB |
10072 | } |
10073 | ||
3760b59c S |
10074 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
10075 | enum port port, | |
10076 | struct intel_crtc_state *pipe_config) | |
10077 | { | |
8106ddbd ACO |
10078 | enum intel_dpll_id id; |
10079 | ||
3760b59c S |
10080 | switch (port) { |
10081 | case PORT_A: | |
10082 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 10083 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
10084 | break; |
10085 | case PORT_B: | |
10086 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 10087 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
10088 | break; |
10089 | case PORT_C: | |
10090 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 10091 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
10092 | break; |
10093 | default: | |
10094 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 10095 | return; |
3760b59c | 10096 | } |
8106ddbd ACO |
10097 | |
10098 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
10099 | } |
10100 | ||
96b7dfb7 S |
10101 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
10102 | enum port port, | |
5cec258b | 10103 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 10104 | { |
8106ddbd | 10105 | enum intel_dpll_id id; |
a3c988ea | 10106 | u32 temp; |
96b7dfb7 S |
10107 | |
10108 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
10109 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
10110 | ||
10111 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 10112 | case SKL_DPLL0: |
a3c988ea ACO |
10113 | id = DPLL_ID_SKL_DPLL0; |
10114 | break; | |
96b7dfb7 | 10115 | case SKL_DPLL1: |
8106ddbd | 10116 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
10117 | break; |
10118 | case SKL_DPLL2: | |
8106ddbd | 10119 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
10120 | break; |
10121 | case SKL_DPLL3: | |
8106ddbd | 10122 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 10123 | break; |
8106ddbd ACO |
10124 | default: |
10125 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
10126 | return; | |
96b7dfb7 | 10127 | } |
8106ddbd ACO |
10128 | |
10129 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
10130 | } |
10131 | ||
7d2c8175 DL |
10132 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
10133 | enum port port, | |
5cec258b | 10134 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 10135 | { |
8106ddbd ACO |
10136 | enum intel_dpll_id id; |
10137 | ||
7d2c8175 DL |
10138 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
10139 | ||
10140 | switch (pipe_config->ddi_pll_sel) { | |
10141 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 10142 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
10143 | break; |
10144 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 10145 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 10146 | break; |
00490c22 | 10147 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 10148 | id = DPLL_ID_SPLL; |
79bd23da | 10149 | break; |
9d16da65 ACO |
10150 | case PORT_CLK_SEL_LCPLL_810: |
10151 | id = DPLL_ID_LCPLL_810; | |
10152 | break; | |
10153 | case PORT_CLK_SEL_LCPLL_1350: | |
10154 | id = DPLL_ID_LCPLL_1350; | |
10155 | break; | |
10156 | case PORT_CLK_SEL_LCPLL_2700: | |
10157 | id = DPLL_ID_LCPLL_2700; | |
10158 | break; | |
8106ddbd ACO |
10159 | default: |
10160 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
10161 | /* fall through */ | |
10162 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 10163 | return; |
7d2c8175 | 10164 | } |
8106ddbd ACO |
10165 | |
10166 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
10167 | } |
10168 | ||
cf30429e JN |
10169 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
10170 | struct intel_crtc_state *pipe_config, | |
10171 | unsigned long *power_domain_mask) | |
10172 | { | |
10173 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10174 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
10175 | enum intel_display_power_domain power_domain; |
10176 | u32 tmp; | |
10177 | ||
d9a7bc67 ID |
10178 | /* |
10179 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
10180 | * transcoder handled below. | |
10181 | */ | |
cf30429e JN |
10182 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
10183 | ||
10184 | /* | |
10185 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
10186 | * consistency and less surprising code; it's in always on power). | |
10187 | */ | |
10188 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
10189 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10190 | enum pipe trans_edp_pipe; | |
10191 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10192 | default: | |
10193 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10194 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10195 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10196 | trans_edp_pipe = PIPE_A; | |
10197 | break; | |
10198 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10199 | trans_edp_pipe = PIPE_B; | |
10200 | break; | |
10201 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10202 | trans_edp_pipe = PIPE_C; | |
10203 | break; | |
10204 | } | |
10205 | ||
10206 | if (trans_edp_pipe == crtc->pipe) | |
10207 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10208 | } | |
10209 | ||
10210 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
10211 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10212 | return false; | |
10213 | *power_domain_mask |= BIT(power_domain); | |
10214 | ||
10215 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
10216 | ||
10217 | return tmp & PIPECONF_ENABLE; | |
10218 | } | |
10219 | ||
4d1de975 JN |
10220 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10221 | struct intel_crtc_state *pipe_config, | |
10222 | unsigned long *power_domain_mask) | |
10223 | { | |
10224 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10225 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
10226 | enum intel_display_power_domain power_domain; |
10227 | enum port port; | |
10228 | enum transcoder cpu_transcoder; | |
10229 | u32 tmp; | |
10230 | ||
4d1de975 JN |
10231 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
10232 | if (port == PORT_A) | |
10233 | cpu_transcoder = TRANSCODER_DSI_A; | |
10234 | else | |
10235 | cpu_transcoder = TRANSCODER_DSI_C; | |
10236 | ||
10237 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10238 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10239 | continue; | |
10240 | *power_domain_mask |= BIT(power_domain); | |
10241 | ||
db18b6a6 ID |
10242 | /* |
10243 | * The PLL needs to be enabled with a valid divider | |
10244 | * configuration, otherwise accessing DSI registers will hang | |
10245 | * the machine. See BSpec North Display Engine | |
10246 | * registers/MIPI[BXT]. We can break out here early, since we | |
10247 | * need the same DSI PLL to be enabled for both DSI ports. | |
10248 | */ | |
10249 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10250 | break; | |
10251 | ||
4d1de975 JN |
10252 | /* XXX: this works for video mode only */ |
10253 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10254 | if (!(tmp & DPI_ENABLE)) | |
10255 | continue; | |
10256 | ||
10257 | tmp = I915_READ(MIPI_CTRL(port)); | |
10258 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10259 | continue; | |
10260 | ||
10261 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
10262 | break; |
10263 | } | |
10264 | ||
d7edc4e5 | 10265 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
10266 | } |
10267 | ||
26804afd | 10268 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10269 | struct intel_crtc_state *pipe_config) |
26804afd DV |
10270 | { |
10271 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10272 | struct drm_i915_private *dev_priv = to_i915(dev); |
d452c5b6 | 10273 | struct intel_shared_dpll *pll; |
26804afd DV |
10274 | enum port port; |
10275 | uint32_t tmp; | |
10276 | ||
10277 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10278 | ||
10279 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10280 | ||
ef11bdb3 | 10281 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 10282 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
10283 | else if (IS_BROXTON(dev)) |
10284 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
10285 | else |
10286 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10287 | |
8106ddbd ACO |
10288 | pll = pipe_config->shared_dpll; |
10289 | if (pll) { | |
2edd6443 ACO |
10290 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10291 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10292 | } |
10293 | ||
26804afd DV |
10294 | /* |
10295 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10296 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10297 | * the PCH transcoder is on. | |
10298 | */ | |
ca370455 DL |
10299 | if (INTEL_INFO(dev)->gen < 9 && |
10300 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
10301 | pipe_config->has_pch_encoder = true; |
10302 | ||
10303 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10304 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10305 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10306 | ||
10307 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10308 | } | |
10309 | } | |
10310 | ||
0e8ffe1b | 10311 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10312 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10313 | { |
10314 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10315 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e ID |
10316 | enum intel_display_power_domain power_domain; |
10317 | unsigned long power_domain_mask; | |
cf30429e | 10318 | bool active; |
0e8ffe1b | 10319 | |
1729050e ID |
10320 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10321 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10322 | return false; |
1729050e ID |
10323 | power_domain_mask = BIT(power_domain); |
10324 | ||
8106ddbd | 10325 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10326 | |
cf30429e | 10327 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10328 | |
d7edc4e5 VS |
10329 | if (IS_BROXTON(dev_priv) && |
10330 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { | |
10331 | WARN_ON(active); | |
10332 | active = true; | |
4d1de975 JN |
10333 | } |
10334 | ||
cf30429e | 10335 | if (!active) |
1729050e | 10336 | goto out; |
0e8ffe1b | 10337 | |
d7edc4e5 | 10338 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
10339 | haswell_get_ddi_port_state(crtc, pipe_config); |
10340 | intel_get_pipe_timings(crtc, pipe_config); | |
10341 | } | |
627eb5a3 | 10342 | |
bc58be60 | 10343 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10344 | |
05dc698c LL |
10345 | pipe_config->gamma_mode = |
10346 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10347 | ||
a1b2278e CK |
10348 | if (INTEL_INFO(dev)->gen >= 9) { |
10349 | skl_init_scalers(dev, crtc, pipe_config); | |
10350 | } | |
10351 | ||
af99ceda CK |
10352 | if (INTEL_INFO(dev)->gen >= 9) { |
10353 | pipe_config->scaler_state.scaler_id = -1; | |
10354 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10355 | } | |
10356 | ||
1729050e ID |
10357 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10358 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10359 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10360 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10361 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10362 | else |
1c132b44 | 10363 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10364 | } |
88adfff1 | 10365 | |
e59150dc JB |
10366 | if (IS_HASWELL(dev)) |
10367 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10368 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10369 | |
4d1de975 JN |
10370 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10371 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10372 | pipe_config->pixel_multiplier = |
10373 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10374 | } else { | |
10375 | pipe_config->pixel_multiplier = 1; | |
10376 | } | |
6c49f241 | 10377 | |
1729050e ID |
10378 | out: |
10379 | for_each_power_domain(power_domain, power_domain_mask) | |
10380 | intel_display_power_put(dev_priv, power_domain); | |
10381 | ||
cf30429e | 10382 | return active; |
0e8ffe1b DV |
10383 | } |
10384 | ||
55a08b3f ML |
10385 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10386 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10387 | { |
10388 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10389 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 10390 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 10391 | uint32_t cntl = 0, size = 0; |
560b85bb | 10392 | |
55a08b3f ML |
10393 | if (plane_state && plane_state->visible) { |
10394 | unsigned int width = plane_state->base.crtc_w; | |
10395 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10396 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10397 | ||
10398 | switch (stride) { | |
10399 | default: | |
10400 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10401 | width, stride); | |
10402 | stride = 256; | |
10403 | /* fallthrough */ | |
10404 | case 256: | |
10405 | case 512: | |
10406 | case 1024: | |
10407 | case 2048: | |
10408 | break; | |
4b0e333e CW |
10409 | } |
10410 | ||
dc41c154 VS |
10411 | cntl |= CURSOR_ENABLE | |
10412 | CURSOR_GAMMA_ENABLE | | |
10413 | CURSOR_FORMAT_ARGB | | |
10414 | CURSOR_STRIDE(stride); | |
10415 | ||
10416 | size = (height << 12) | width; | |
4b0e333e | 10417 | } |
560b85bb | 10418 | |
dc41c154 VS |
10419 | if (intel_crtc->cursor_cntl != 0 && |
10420 | (intel_crtc->cursor_base != base || | |
10421 | intel_crtc->cursor_size != size || | |
10422 | intel_crtc->cursor_cntl != cntl)) { | |
10423 | /* On these chipsets we can only modify the base/size/stride | |
10424 | * whilst the cursor is disabled. | |
10425 | */ | |
0b87c24e VS |
10426 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10427 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10428 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10429 | } |
560b85bb | 10430 | |
99d1f387 | 10431 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10432 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10433 | intel_crtc->cursor_base = base; |
10434 | } | |
4726e0b0 | 10435 | |
dc41c154 VS |
10436 | if (intel_crtc->cursor_size != size) { |
10437 | I915_WRITE(CURSIZE, size); | |
10438 | intel_crtc->cursor_size = size; | |
4b0e333e | 10439 | } |
560b85bb | 10440 | |
4b0e333e | 10441 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10442 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10443 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10444 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10445 | } |
560b85bb CW |
10446 | } |
10447 | ||
55a08b3f ML |
10448 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10449 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10450 | { |
10451 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10452 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
10453 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10454 | int pipe = intel_crtc->pipe; | |
663f3122 | 10455 | uint32_t cntl = 0; |
4b0e333e | 10456 | |
55a08b3f | 10457 | if (plane_state && plane_state->visible) { |
4b0e333e | 10458 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10459 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10460 | case 64: |
10461 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10462 | break; | |
10463 | case 128: | |
10464 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10465 | break; | |
10466 | case 256: | |
10467 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10468 | break; | |
10469 | default: | |
55a08b3f | 10470 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10471 | return; |
65a21cd6 | 10472 | } |
4b0e333e | 10473 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10474 | |
fc6f93bc | 10475 | if (HAS_DDI(dev)) |
47bf17a7 | 10476 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10477 | |
55a08b3f ML |
10478 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10479 | cntl |= CURSOR_ROTATE_180; | |
10480 | } | |
4398ad45 | 10481 | |
4b0e333e CW |
10482 | if (intel_crtc->cursor_cntl != cntl) { |
10483 | I915_WRITE(CURCNTR(pipe), cntl); | |
10484 | POSTING_READ(CURCNTR(pipe)); | |
10485 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10486 | } |
4b0e333e | 10487 | |
65a21cd6 | 10488 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10489 | I915_WRITE(CURBASE(pipe), base); |
10490 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10491 | |
10492 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10493 | } |
10494 | ||
cda4b7d3 | 10495 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10496 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10497 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10498 | { |
10499 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10500 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
10501 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10502 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10503 | u32 base = intel_crtc->cursor_addr; |
10504 | u32 pos = 0; | |
cda4b7d3 | 10505 | |
55a08b3f ML |
10506 | if (plane_state) { |
10507 | int x = plane_state->base.crtc_x; | |
10508 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10509 | |
55a08b3f ML |
10510 | if (x < 0) { |
10511 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10512 | x = -x; | |
10513 | } | |
10514 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10515 | |
55a08b3f ML |
10516 | if (y < 0) { |
10517 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10518 | y = -y; | |
10519 | } | |
10520 | pos |= y << CURSOR_Y_SHIFT; | |
10521 | ||
10522 | /* ILK+ do this automagically */ | |
10523 | if (HAS_GMCH_DISPLAY(dev) && | |
10524 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10525 | base += (plane_state->base.crtc_h * | |
10526 | plane_state->base.crtc_w - 1) * 4; | |
10527 | } | |
cda4b7d3 | 10528 | } |
cda4b7d3 | 10529 | |
5efb3e28 VS |
10530 | I915_WRITE(CURPOS(pipe), pos); |
10531 | ||
8ac54669 | 10532 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10533 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10534 | else |
55a08b3f | 10535 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10536 | } |
10537 | ||
dc41c154 VS |
10538 | static bool cursor_size_ok(struct drm_device *dev, |
10539 | uint32_t width, uint32_t height) | |
10540 | { | |
10541 | if (width == 0 || height == 0) | |
10542 | return false; | |
10543 | ||
10544 | /* | |
10545 | * 845g/865g are special in that they are only limited by | |
10546 | * the width of their cursors, the height is arbitrary up to | |
10547 | * the precision of the register. Everything else requires | |
10548 | * square cursors, limited to a few power-of-two sizes. | |
10549 | */ | |
10550 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10551 | if ((width & 63) != 0) | |
10552 | return false; | |
10553 | ||
10554 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10555 | return false; | |
10556 | ||
10557 | if (height > 1023) | |
10558 | return false; | |
10559 | } else { | |
10560 | switch (width | height) { | |
10561 | case 256: | |
10562 | case 128: | |
10563 | if (IS_GEN2(dev)) | |
10564 | return false; | |
10565 | case 64: | |
10566 | break; | |
10567 | default: | |
10568 | return false; | |
10569 | } | |
10570 | } | |
10571 | ||
10572 | return true; | |
10573 | } | |
10574 | ||
79e53945 JB |
10575 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10576 | static struct drm_display_mode load_detect_mode = { | |
10577 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10578 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10579 | }; | |
10580 | ||
a8bb6818 DV |
10581 | struct drm_framebuffer * |
10582 | __intel_framebuffer_create(struct drm_device *dev, | |
10583 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10584 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10585 | { |
10586 | struct intel_framebuffer *intel_fb; | |
10587 | int ret; | |
10588 | ||
10589 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10590 | if (!intel_fb) |
d2dff872 | 10591 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10592 | |
10593 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10594 | if (ret) |
10595 | goto err; | |
d2dff872 CW |
10596 | |
10597 | return &intel_fb->base; | |
dcb1394e | 10598 | |
dd4916c5 | 10599 | err: |
dd4916c5 | 10600 | kfree(intel_fb); |
dd4916c5 | 10601 | return ERR_PTR(ret); |
d2dff872 CW |
10602 | } |
10603 | ||
b5ea642a | 10604 | static struct drm_framebuffer * |
a8bb6818 DV |
10605 | intel_framebuffer_create(struct drm_device *dev, |
10606 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10607 | struct drm_i915_gem_object *obj) | |
10608 | { | |
10609 | struct drm_framebuffer *fb; | |
10610 | int ret; | |
10611 | ||
10612 | ret = i915_mutex_lock_interruptible(dev); | |
10613 | if (ret) | |
10614 | return ERR_PTR(ret); | |
10615 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10616 | mutex_unlock(&dev->struct_mutex); | |
10617 | ||
10618 | return fb; | |
10619 | } | |
10620 | ||
d2dff872 CW |
10621 | static u32 |
10622 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10623 | { | |
10624 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10625 | return ALIGN(pitch, 64); | |
10626 | } | |
10627 | ||
10628 | static u32 | |
10629 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10630 | { | |
10631 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10632 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10633 | } |
10634 | ||
10635 | static struct drm_framebuffer * | |
10636 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10637 | struct drm_display_mode *mode, | |
10638 | int depth, int bpp) | |
10639 | { | |
dcb1394e | 10640 | struct drm_framebuffer *fb; |
d2dff872 | 10641 | struct drm_i915_gem_object *obj; |
0fed39bd | 10642 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 10643 | |
d37cd8a8 | 10644 | obj = i915_gem_object_create(dev, |
d2dff872 | 10645 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
10646 | if (IS_ERR(obj)) |
10647 | return ERR_CAST(obj); | |
d2dff872 CW |
10648 | |
10649 | mode_cmd.width = mode->hdisplay; | |
10650 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10651 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10652 | bpp); | |
5ca0c34a | 10653 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10654 | |
dcb1394e LW |
10655 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10656 | if (IS_ERR(fb)) | |
34911fd3 | 10657 | i915_gem_object_put_unlocked(obj); |
dcb1394e LW |
10658 | |
10659 | return fb; | |
d2dff872 CW |
10660 | } |
10661 | ||
10662 | static struct drm_framebuffer * | |
10663 | mode_fits_in_fbdev(struct drm_device *dev, | |
10664 | struct drm_display_mode *mode) | |
10665 | { | |
0695726e | 10666 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 10667 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
10668 | struct drm_i915_gem_object *obj; |
10669 | struct drm_framebuffer *fb; | |
10670 | ||
4c0e5528 | 10671 | if (!dev_priv->fbdev) |
d2dff872 CW |
10672 | return NULL; |
10673 | ||
4c0e5528 | 10674 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10675 | return NULL; |
10676 | ||
4c0e5528 DV |
10677 | obj = dev_priv->fbdev->fb->obj; |
10678 | BUG_ON(!obj); | |
10679 | ||
8bcd4553 | 10680 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10681 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10682 | fb->bits_per_pixel)) | |
d2dff872 CW |
10683 | return NULL; |
10684 | ||
01f2c773 | 10685 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10686 | return NULL; |
10687 | ||
edde3617 | 10688 | drm_framebuffer_reference(fb); |
d2dff872 | 10689 | return fb; |
4520f53a DV |
10690 | #else |
10691 | return NULL; | |
10692 | #endif | |
d2dff872 CW |
10693 | } |
10694 | ||
d3a40d1b ACO |
10695 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10696 | struct drm_crtc *crtc, | |
10697 | struct drm_display_mode *mode, | |
10698 | struct drm_framebuffer *fb, | |
10699 | int x, int y) | |
10700 | { | |
10701 | struct drm_plane_state *plane_state; | |
10702 | int hdisplay, vdisplay; | |
10703 | int ret; | |
10704 | ||
10705 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10706 | if (IS_ERR(plane_state)) | |
10707 | return PTR_ERR(plane_state); | |
10708 | ||
10709 | if (mode) | |
10710 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10711 | else | |
10712 | hdisplay = vdisplay = 0; | |
10713 | ||
10714 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10715 | if (ret) | |
10716 | return ret; | |
10717 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10718 | plane_state->crtc_x = 0; | |
10719 | plane_state->crtc_y = 0; | |
10720 | plane_state->crtc_w = hdisplay; | |
10721 | plane_state->crtc_h = vdisplay; | |
10722 | plane_state->src_x = x << 16; | |
10723 | plane_state->src_y = y << 16; | |
10724 | plane_state->src_w = hdisplay << 16; | |
10725 | plane_state->src_h = vdisplay << 16; | |
10726 | ||
10727 | return 0; | |
10728 | } | |
10729 | ||
d2434ab7 | 10730 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10731 | struct drm_display_mode *mode, |
51fd371b RC |
10732 | struct intel_load_detect_pipe *old, |
10733 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10734 | { |
10735 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10736 | struct intel_encoder *intel_encoder = |
10737 | intel_attached_encoder(connector); | |
79e53945 | 10738 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10739 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10740 | struct drm_crtc *crtc = NULL; |
10741 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10742 | struct drm_framebuffer *fb; |
51fd371b | 10743 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10744 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10745 | struct drm_connector_state *connector_state; |
4be07317 | 10746 | struct intel_crtc_state *crtc_state; |
51fd371b | 10747 | int ret, i = -1; |
79e53945 | 10748 | |
d2dff872 | 10749 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10750 | connector->base.id, connector->name, |
8e329a03 | 10751 | encoder->base.id, encoder->name); |
d2dff872 | 10752 | |
edde3617 ML |
10753 | old->restore_state = NULL; |
10754 | ||
51fd371b RC |
10755 | retry: |
10756 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10757 | if (ret) | |
ad3c558f | 10758 | goto fail; |
6e9f798d | 10759 | |
79e53945 JB |
10760 | /* |
10761 | * Algorithm gets a little messy: | |
7a5e4805 | 10762 | * |
79e53945 JB |
10763 | * - if the connector already has an assigned crtc, use it (but make |
10764 | * sure it's on first) | |
7a5e4805 | 10765 | * |
79e53945 JB |
10766 | * - try to find the first unused crtc that can drive this connector, |
10767 | * and use that if we find one | |
79e53945 JB |
10768 | */ |
10769 | ||
10770 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10771 | if (connector->state->crtc) { |
10772 | crtc = connector->state->crtc; | |
8261b191 | 10773 | |
51fd371b | 10774 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10775 | if (ret) |
ad3c558f | 10776 | goto fail; |
8261b191 CW |
10777 | |
10778 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10779 | goto found; |
79e53945 JB |
10780 | } |
10781 | ||
10782 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10783 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10784 | i++; |
10785 | if (!(encoder->possible_crtcs & (1 << i))) | |
10786 | continue; | |
edde3617 ML |
10787 | |
10788 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10789 | if (ret) | |
10790 | goto fail; | |
10791 | ||
10792 | if (possible_crtc->state->enable) { | |
10793 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10794 | continue; |
edde3617 | 10795 | } |
a459249c VS |
10796 | |
10797 | crtc = possible_crtc; | |
10798 | break; | |
79e53945 JB |
10799 | } |
10800 | ||
10801 | /* | |
10802 | * If we didn't find an unused CRTC, don't use any. | |
10803 | */ | |
10804 | if (!crtc) { | |
7173188d | 10805 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10806 | goto fail; |
79e53945 JB |
10807 | } |
10808 | ||
edde3617 ML |
10809 | found: |
10810 | intel_crtc = to_intel_crtc(crtc); | |
10811 | ||
4d02e2de DV |
10812 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10813 | if (ret) | |
ad3c558f | 10814 | goto fail; |
79e53945 | 10815 | |
83a57153 | 10816 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10817 | restore_state = drm_atomic_state_alloc(dev); |
10818 | if (!state || !restore_state) { | |
10819 | ret = -ENOMEM; | |
10820 | goto fail; | |
10821 | } | |
83a57153 ACO |
10822 | |
10823 | state->acquire_ctx = ctx; | |
edde3617 | 10824 | restore_state->acquire_ctx = ctx; |
83a57153 | 10825 | |
944b0c76 ACO |
10826 | connector_state = drm_atomic_get_connector_state(state, connector); |
10827 | if (IS_ERR(connector_state)) { | |
10828 | ret = PTR_ERR(connector_state); | |
10829 | goto fail; | |
10830 | } | |
10831 | ||
edde3617 ML |
10832 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10833 | if (ret) | |
10834 | goto fail; | |
944b0c76 | 10835 | |
4be07317 ACO |
10836 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10837 | if (IS_ERR(crtc_state)) { | |
10838 | ret = PTR_ERR(crtc_state); | |
10839 | goto fail; | |
10840 | } | |
10841 | ||
49d6fa21 | 10842 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10843 | |
6492711d CW |
10844 | if (!mode) |
10845 | mode = &load_detect_mode; | |
79e53945 | 10846 | |
d2dff872 CW |
10847 | /* We need a framebuffer large enough to accommodate all accesses |
10848 | * that the plane may generate whilst we perform load detection. | |
10849 | * We can not rely on the fbcon either being present (we get called | |
10850 | * during its initialisation to detect all boot displays, or it may | |
10851 | * not even exist) or that it is large enough to satisfy the | |
10852 | * requested mode. | |
10853 | */ | |
94352cf9 DV |
10854 | fb = mode_fits_in_fbdev(dev, mode); |
10855 | if (fb == NULL) { | |
d2dff872 | 10856 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10857 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10858 | } else |
10859 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10860 | if (IS_ERR(fb)) { |
d2dff872 | 10861 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10862 | goto fail; |
79e53945 | 10863 | } |
79e53945 | 10864 | |
d3a40d1b ACO |
10865 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10866 | if (ret) | |
10867 | goto fail; | |
10868 | ||
edde3617 ML |
10869 | drm_framebuffer_unreference(fb); |
10870 | ||
10871 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10872 | if (ret) | |
10873 | goto fail; | |
10874 | ||
10875 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10876 | if (!ret) | |
10877 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10878 | if (!ret) | |
10879 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10880 | if (ret) { | |
10881 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10882 | goto fail; | |
10883 | } | |
8c7b5ccb | 10884 | |
3ba86073 ML |
10885 | ret = drm_atomic_commit(state); |
10886 | if (ret) { | |
6492711d | 10887 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10888 | goto fail; |
79e53945 | 10889 | } |
edde3617 ML |
10890 | |
10891 | old->restore_state = restore_state; | |
7173188d | 10892 | |
79e53945 | 10893 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10894 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10895 | return true; |
412b61d8 | 10896 | |
ad3c558f | 10897 | fail: |
e5d958ef | 10898 | drm_atomic_state_free(state); |
edde3617 ML |
10899 | drm_atomic_state_free(restore_state); |
10900 | restore_state = state = NULL; | |
83a57153 | 10901 | |
51fd371b RC |
10902 | if (ret == -EDEADLK) { |
10903 | drm_modeset_backoff(ctx); | |
10904 | goto retry; | |
10905 | } | |
10906 | ||
412b61d8 | 10907 | return false; |
79e53945 JB |
10908 | } |
10909 | ||
d2434ab7 | 10910 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10911 | struct intel_load_detect_pipe *old, |
10912 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10913 | { |
d2434ab7 DV |
10914 | struct intel_encoder *intel_encoder = |
10915 | intel_attached_encoder(connector); | |
4ef69c7a | 10916 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10917 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10918 | int ret; |
79e53945 | 10919 | |
d2dff872 | 10920 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10921 | connector->base.id, connector->name, |
8e329a03 | 10922 | encoder->base.id, encoder->name); |
d2dff872 | 10923 | |
edde3617 | 10924 | if (!state) |
0622a53c | 10925 | return; |
79e53945 | 10926 | |
edde3617 ML |
10927 | ret = drm_atomic_commit(state); |
10928 | if (ret) { | |
10929 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10930 | drm_atomic_state_free(state); | |
10931 | } | |
79e53945 JB |
10932 | } |
10933 | ||
da4a1efa | 10934 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10935 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 10936 | { |
fac5e23e | 10937 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
10938 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
10939 | ||
10940 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10941 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10942 | else if (HAS_PCH_SPLIT(dev)) |
10943 | return 120000; | |
10944 | else if (!IS_GEN2(dev)) | |
10945 | return 96000; | |
10946 | else | |
10947 | return 48000; | |
10948 | } | |
10949 | ||
79e53945 | 10950 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10951 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10952 | struct intel_crtc_state *pipe_config) |
79e53945 | 10953 | { |
f1f644dc | 10954 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 10955 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 10956 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10957 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10958 | u32 fp; |
9e2c8475 | 10959 | struct dpll clock; |
dccbea3b | 10960 | int port_clock; |
da4a1efa | 10961 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10962 | |
10963 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10964 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10965 | else |
293623f7 | 10966 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10967 | |
10968 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10969 | if (IS_PINEVIEW(dev)) { |
10970 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10971 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10972 | } else { |
10973 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10974 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10975 | } | |
10976 | ||
a6c45cf0 | 10977 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10978 | if (IS_PINEVIEW(dev)) |
10979 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10980 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10981 | else |
10982 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10983 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10984 | ||
10985 | switch (dpll & DPLL_MODE_MASK) { | |
10986 | case DPLLB_MODE_DAC_SERIAL: | |
10987 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10988 | 5 : 10; | |
10989 | break; | |
10990 | case DPLLB_MODE_LVDS: | |
10991 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10992 | 7 : 14; | |
10993 | break; | |
10994 | default: | |
28c97730 | 10995 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10996 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10997 | return; |
79e53945 JB |
10998 | } |
10999 | ||
ac58c3f0 | 11000 | if (IS_PINEVIEW(dev)) |
dccbea3b | 11001 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 11002 | else |
dccbea3b | 11003 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 11004 | } else { |
0fb58223 | 11005 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 11006 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
11007 | |
11008 | if (is_lvds) { | |
11009 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
11010 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
11011 | |
11012 | if (lvds & LVDS_CLKB_POWER_UP) | |
11013 | clock.p2 = 7; | |
11014 | else | |
11015 | clock.p2 = 14; | |
79e53945 JB |
11016 | } else { |
11017 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
11018 | clock.p1 = 2; | |
11019 | else { | |
11020 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
11021 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
11022 | } | |
11023 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
11024 | clock.p2 = 4; | |
11025 | else | |
11026 | clock.p2 = 2; | |
79e53945 | 11027 | } |
da4a1efa | 11028 | |
dccbea3b | 11029 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
11030 | } |
11031 | ||
18442d08 VS |
11032 | /* |
11033 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 11034 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
11035 | * encoder's get_config() function. |
11036 | */ | |
dccbea3b | 11037 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
11038 | } |
11039 | ||
6878da05 VS |
11040 | int intel_dotclock_calculate(int link_freq, |
11041 | const struct intel_link_m_n *m_n) | |
f1f644dc | 11042 | { |
f1f644dc JB |
11043 | /* |
11044 | * The calculation for the data clock is: | |
1041a02f | 11045 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 11046 | * But we want to avoid losing precison if possible, so: |
1041a02f | 11047 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
11048 | * |
11049 | * and the link clock is simpler: | |
1041a02f | 11050 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
11051 | */ |
11052 | ||
6878da05 VS |
11053 | if (!m_n->link_n) |
11054 | return 0; | |
f1f644dc | 11055 | |
6878da05 VS |
11056 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
11057 | } | |
f1f644dc | 11058 | |
18442d08 | 11059 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 11060 | struct intel_crtc_state *pipe_config) |
6878da05 | 11061 | { |
e3b247da | 11062 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 11063 | |
18442d08 VS |
11064 | /* read out port_clock from the DPLL */ |
11065 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 11066 | |
f1f644dc | 11067 | /* |
e3b247da VS |
11068 | * In case there is an active pipe without active ports, |
11069 | * we may need some idea for the dotclock anyway. | |
11070 | * Calculate one based on the FDI configuration. | |
79e53945 | 11071 | */ |
2d112de7 | 11072 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 11073 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 11074 | &pipe_config->fdi_m_n); |
79e53945 JB |
11075 | } |
11076 | ||
11077 | /** Returns the currently programmed mode of the given pipe. */ | |
11078 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
11079 | struct drm_crtc *crtc) | |
11080 | { | |
fac5e23e | 11081 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 11082 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 11083 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 11084 | struct drm_display_mode *mode; |
3f36b937 | 11085 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
11086 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
11087 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11088 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
11089 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 11090 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
11091 | |
11092 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
11093 | if (!mode) | |
11094 | return NULL; | |
11095 | ||
3f36b937 TU |
11096 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
11097 | if (!pipe_config) { | |
11098 | kfree(mode); | |
11099 | return NULL; | |
11100 | } | |
11101 | ||
f1f644dc JB |
11102 | /* |
11103 | * Construct a pipe_config sufficient for getting the clock info | |
11104 | * back out of crtc_clock_get. | |
11105 | * | |
11106 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
11107 | * to use a real value here instead. | |
11108 | */ | |
3f36b937 TU |
11109 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
11110 | pipe_config->pixel_multiplier = 1; | |
11111 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
11112 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
11113 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
11114 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
11115 | ||
11116 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
11117 | mode->hdisplay = (htot & 0xffff) + 1; |
11118 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
11119 | mode->hsync_start = (hsync & 0xffff) + 1; | |
11120 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
11121 | mode->vdisplay = (vtot & 0xffff) + 1; | |
11122 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
11123 | mode->vsync_start = (vsync & 0xffff) + 1; | |
11124 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
11125 | ||
11126 | drm_mode_set_name(mode); | |
79e53945 | 11127 | |
3f36b937 TU |
11128 | kfree(pipe_config); |
11129 | ||
79e53945 JB |
11130 | return mode; |
11131 | } | |
11132 | ||
11133 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
11134 | { | |
11135 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 11136 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 11137 | struct intel_flip_work *work; |
67e77c5a | 11138 | |
5e2d7afc | 11139 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
11140 | work = intel_crtc->flip_work; |
11141 | intel_crtc->flip_work = NULL; | |
11142 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 11143 | |
5a21b665 | 11144 | if (work) { |
51cbaf01 ML |
11145 | cancel_work_sync(&work->mmio_work); |
11146 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 11147 | kfree(work); |
67e77c5a | 11148 | } |
79e53945 JB |
11149 | |
11150 | drm_crtc_cleanup(crtc); | |
67e77c5a | 11151 | |
79e53945 JB |
11152 | kfree(intel_crtc); |
11153 | } | |
11154 | ||
6b95a207 KH |
11155 | static void intel_unpin_work_fn(struct work_struct *__work) |
11156 | { | |
51cbaf01 ML |
11157 | struct intel_flip_work *work = |
11158 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
11159 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
11160 | struct drm_device *dev = crtc->base.dev; | |
11161 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 11162 | |
5a21b665 DV |
11163 | if (is_mmio_work(work)) |
11164 | flush_work(&work->mmio_work); | |
03f476e1 | 11165 | |
5a21b665 DV |
11166 | mutex_lock(&dev->struct_mutex); |
11167 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
f8c417cd | 11168 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 11169 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 11170 | |
e8a261ea CW |
11171 | i915_gem_request_put(work->flip_queued_req); |
11172 | ||
5748b6a1 CW |
11173 | intel_frontbuffer_flip_complete(to_i915(dev), |
11174 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
11175 | intel_fbc_post_update(crtc); |
11176 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 11177 | |
5a21b665 DV |
11178 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11179 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 11180 | |
5a21b665 DV |
11181 | kfree(work); |
11182 | } | |
d9e86c0e | 11183 | |
5a21b665 DV |
11184 | /* Is 'a' after or equal to 'b'? */ |
11185 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11186 | { | |
11187 | return !((a - b) & 0x80000000); | |
11188 | } | |
143f73b3 | 11189 | |
5a21b665 DV |
11190 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
11191 | struct intel_flip_work *work) | |
11192 | { | |
11193 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11194 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 11195 | unsigned reset_counter; |
143f73b3 | 11196 | |
5a21b665 DV |
11197 | reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
11198 | if (crtc->reset_counter != reset_counter) | |
11199 | return true; | |
143f73b3 | 11200 | |
5a21b665 DV |
11201 | /* |
11202 | * The relevant registers doen't exist on pre-ctg. | |
11203 | * As the flip done interrupt doesn't trigger for mmio | |
11204 | * flips on gmch platforms, a flip count check isn't | |
11205 | * really needed there. But since ctg has the registers, | |
11206 | * include it in the check anyway. | |
11207 | */ | |
11208 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11209 | return true; | |
b4a98e57 | 11210 | |
5a21b665 DV |
11211 | /* |
11212 | * BDW signals flip done immediately if the plane | |
11213 | * is disabled, even if the plane enable is already | |
11214 | * armed to occur at the next vblank :( | |
11215 | */ | |
f99d7069 | 11216 | |
5a21b665 DV |
11217 | /* |
11218 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11219 | * used the same base address. In that case the mmio flip might | |
11220 | * have completed, but the CS hasn't even executed the flip yet. | |
11221 | * | |
11222 | * A flip count check isn't enough as the CS might have updated | |
11223 | * the base address just after start of vblank, but before we | |
11224 | * managed to process the interrupt. This means we'd complete the | |
11225 | * CS flip too soon. | |
11226 | * | |
11227 | * Combining both checks should get us a good enough result. It may | |
11228 | * still happen that the CS flip has been executed, but has not | |
11229 | * yet actually completed. But in case the base address is the same | |
11230 | * anyway, we don't really care. | |
11231 | */ | |
11232 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11233 | crtc->flip_work->gtt_offset && | |
11234 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11235 | crtc->flip_work->flip_count); | |
11236 | } | |
b4a98e57 | 11237 | |
5a21b665 DV |
11238 | static bool |
11239 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11240 | struct intel_flip_work *work) | |
11241 | { | |
11242 | /* | |
11243 | * MMIO work completes when vblank is different from | |
11244 | * flip_queued_vblank. | |
11245 | * | |
11246 | * Reset counter value doesn't matter, this is handled by | |
11247 | * i915_wait_request finishing early, so no need to handle | |
11248 | * reset here. | |
11249 | */ | |
11250 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11251 | } |
11252 | ||
51cbaf01 ML |
11253 | |
11254 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11255 | struct intel_flip_work *work) | |
11256 | { | |
11257 | if (!atomic_read(&work->pending)) | |
11258 | return false; | |
11259 | ||
11260 | smp_rmb(); | |
11261 | ||
5a21b665 DV |
11262 | if (is_mmio_work(work)) |
11263 | return __pageflip_finished_mmio(crtc, work); | |
11264 | else | |
11265 | return __pageflip_finished_cs(crtc, work); | |
11266 | } | |
11267 | ||
11268 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11269 | { | |
91c8a326 | 11270 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11271 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11272 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11273 | struct intel_flip_work *work; | |
11274 | unsigned long flags; | |
11275 | ||
11276 | /* Ignore early vblank irqs */ | |
11277 | if (!crtc) | |
11278 | return; | |
11279 | ||
51cbaf01 | 11280 | /* |
5a21b665 DV |
11281 | * This is called both by irq handlers and the reset code (to complete |
11282 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11283 | */ |
5a21b665 DV |
11284 | spin_lock_irqsave(&dev->event_lock, flags); |
11285 | work = intel_crtc->flip_work; | |
11286 | ||
11287 | if (work != NULL && | |
11288 | !is_mmio_work(work) && | |
11289 | pageflip_finished(intel_crtc, work)) | |
11290 | page_flip_completed(intel_crtc); | |
11291 | ||
11292 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11293 | } |
11294 | ||
51cbaf01 | 11295 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11296 | { |
91c8a326 | 11297 | struct drm_device *dev = &dev_priv->drm; |
5251f04e ML |
11298 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11299 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
51cbaf01 | 11300 | struct intel_flip_work *work; |
6b95a207 KH |
11301 | unsigned long flags; |
11302 | ||
5251f04e ML |
11303 | /* Ignore early vblank irqs */ |
11304 | if (!crtc) | |
11305 | return; | |
f326038a DV |
11306 | |
11307 | /* | |
11308 | * This is called both by irq handlers and the reset code (to complete | |
11309 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11310 | */ |
6b95a207 | 11311 | spin_lock_irqsave(&dev->event_lock, flags); |
5a21b665 | 11312 | work = intel_crtc->flip_work; |
5251f04e | 11313 | |
5a21b665 DV |
11314 | if (work != NULL && |
11315 | is_mmio_work(work) && | |
11316 | pageflip_finished(intel_crtc, work)) | |
11317 | page_flip_completed(intel_crtc); | |
5251f04e | 11318 | |
6b95a207 KH |
11319 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11320 | } | |
11321 | ||
5a21b665 DV |
11322 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11323 | struct intel_flip_work *work) | |
84c33a64 | 11324 | { |
5a21b665 | 11325 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11326 | |
5a21b665 DV |
11327 | /* Ensure that the work item is consistent when activating it ... */ |
11328 | smp_mb__before_atomic(); | |
11329 | atomic_set(&work->pending, 1); | |
11330 | } | |
a6747b73 | 11331 | |
5a21b665 DV |
11332 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11333 | struct drm_crtc *crtc, | |
11334 | struct drm_framebuffer *fb, | |
11335 | struct drm_i915_gem_object *obj, | |
11336 | struct drm_i915_gem_request *req, | |
11337 | uint32_t flags) | |
11338 | { | |
7e37f889 | 11339 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11340 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11341 | u32 flip_mask; | |
11342 | int ret; | |
143f73b3 | 11343 | |
5a21b665 DV |
11344 | ret = intel_ring_begin(req, 6); |
11345 | if (ret) | |
11346 | return ret; | |
143f73b3 | 11347 | |
5a21b665 DV |
11348 | /* Can't queue multiple flips, so wait for the previous |
11349 | * one to finish before executing the next. | |
11350 | */ | |
11351 | if (intel_crtc->plane) | |
11352 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11353 | else | |
11354 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11355 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11356 | intel_ring_emit(ring, MI_NOOP); | |
11357 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
5a21b665 | 11358 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11359 | intel_ring_emit(ring, fb->pitches[0]); |
11360 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11361 | intel_ring_emit(ring, 0); /* aux display base address, unused */ | |
143f73b3 | 11362 | |
5a21b665 DV |
11363 | return 0; |
11364 | } | |
84c33a64 | 11365 | |
5a21b665 DV |
11366 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11367 | struct drm_crtc *crtc, | |
11368 | struct drm_framebuffer *fb, | |
11369 | struct drm_i915_gem_object *obj, | |
11370 | struct drm_i915_gem_request *req, | |
11371 | uint32_t flags) | |
11372 | { | |
7e37f889 | 11373 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11374 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11375 | u32 flip_mask; | |
11376 | int ret; | |
d55dbd06 | 11377 | |
5a21b665 DV |
11378 | ret = intel_ring_begin(req, 6); |
11379 | if (ret) | |
11380 | return ret; | |
d55dbd06 | 11381 | |
5a21b665 DV |
11382 | if (intel_crtc->plane) |
11383 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11384 | else | |
11385 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11386 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11387 | intel_ring_emit(ring, MI_NOOP); | |
11388 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
5a21b665 | 11389 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11390 | intel_ring_emit(ring, fb->pitches[0]); |
11391 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11392 | intel_ring_emit(ring, MI_NOOP); | |
fd8e058a | 11393 | |
5a21b665 DV |
11394 | return 0; |
11395 | } | |
84c33a64 | 11396 | |
5a21b665 DV |
11397 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11398 | struct drm_crtc *crtc, | |
11399 | struct drm_framebuffer *fb, | |
11400 | struct drm_i915_gem_object *obj, | |
11401 | struct drm_i915_gem_request *req, | |
11402 | uint32_t flags) | |
11403 | { | |
7e37f889 | 11404 | struct intel_ring *ring = req->ring; |
fac5e23e | 11405 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11406 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11407 | uint32_t pf, pipesrc; | |
11408 | int ret; | |
143f73b3 | 11409 | |
5a21b665 DV |
11410 | ret = intel_ring_begin(req, 4); |
11411 | if (ret) | |
11412 | return ret; | |
143f73b3 | 11413 | |
5a21b665 DV |
11414 | /* i965+ uses the linear or tiled offsets from the |
11415 | * Display Registers (which do not change across a page-flip) | |
11416 | * so we need only reprogram the base address. | |
11417 | */ | |
b5321f30 | 11418 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11419 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11420 | intel_ring_emit(ring, fb->pitches[0]); |
11421 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset | | |
3e510a8e | 11422 | i915_gem_object_get_tiling(obj)); |
5a21b665 DV |
11423 | |
11424 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11425 | * untested on non-native modes, so ignore it for now. | |
11426 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11427 | */ | |
11428 | pf = 0; | |
11429 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11430 | intel_ring_emit(ring, pf | pipesrc); |
143f73b3 | 11431 | |
5a21b665 | 11432 | return 0; |
8c9f3aaf JB |
11433 | } |
11434 | ||
5a21b665 DV |
11435 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11436 | struct drm_crtc *crtc, | |
11437 | struct drm_framebuffer *fb, | |
11438 | struct drm_i915_gem_object *obj, | |
11439 | struct drm_i915_gem_request *req, | |
11440 | uint32_t flags) | |
da20eabd | 11441 | { |
7e37f889 | 11442 | struct intel_ring *ring = req->ring; |
fac5e23e | 11443 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11444 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11445 | uint32_t pf, pipesrc; | |
11446 | int ret; | |
d21fbe87 | 11447 | |
5a21b665 DV |
11448 | ret = intel_ring_begin(req, 4); |
11449 | if (ret) | |
11450 | return ret; | |
92826fcd | 11451 | |
b5321f30 | 11452 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11453 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
3e510a8e | 11454 | intel_ring_emit(ring, fb->pitches[0] | i915_gem_object_get_tiling(obj)); |
b5321f30 | 11455 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
92826fcd | 11456 | |
5a21b665 DV |
11457 | /* Contrary to the suggestions in the documentation, |
11458 | * "Enable Panel Fitter" does not seem to be required when page | |
11459 | * flipping with a non-native mode, and worse causes a normal | |
11460 | * modeset to fail. | |
11461 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11462 | */ | |
11463 | pf = 0; | |
11464 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11465 | intel_ring_emit(ring, pf | pipesrc); |
7809e5ae | 11466 | |
5a21b665 | 11467 | return 0; |
7809e5ae MR |
11468 | } |
11469 | ||
5a21b665 DV |
11470 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11471 | struct drm_crtc *crtc, | |
11472 | struct drm_framebuffer *fb, | |
11473 | struct drm_i915_gem_object *obj, | |
11474 | struct drm_i915_gem_request *req, | |
11475 | uint32_t flags) | |
d21fbe87 | 11476 | { |
7e37f889 | 11477 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11478 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11479 | uint32_t plane_bit = 0; | |
11480 | int len, ret; | |
d21fbe87 | 11481 | |
5a21b665 DV |
11482 | switch (intel_crtc->plane) { |
11483 | case PLANE_A: | |
11484 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11485 | break; | |
11486 | case PLANE_B: | |
11487 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11488 | break; | |
11489 | case PLANE_C: | |
11490 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11491 | break; | |
11492 | default: | |
11493 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11494 | return -ENODEV; | |
11495 | } | |
11496 | ||
11497 | len = 4; | |
b5321f30 | 11498 | if (req->engine->id == RCS) { |
5a21b665 DV |
11499 | len += 6; |
11500 | /* | |
11501 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11502 | * 48bits addresses, and we need a NOOP for the batch size to | |
11503 | * stay even. | |
11504 | */ | |
11505 | if (IS_GEN8(dev)) | |
11506 | len += 2; | |
11507 | } | |
11508 | ||
11509 | /* | |
11510 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11511 | * "The full packet must be contained within the same cache line." | |
11512 | * | |
11513 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11514 | * cacheline, if we ever start emitting more commands before | |
11515 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11516 | * then do the cacheline alignment, and finally emit the | |
11517 | * MI_DISPLAY_FLIP. | |
11518 | */ | |
11519 | ret = intel_ring_cacheline_align(req); | |
11520 | if (ret) | |
11521 | return ret; | |
11522 | ||
11523 | ret = intel_ring_begin(req, len); | |
11524 | if (ret) | |
11525 | return ret; | |
11526 | ||
11527 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11528 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11529 | * more than one flip event at any time (or ensure that one flip message | |
11530 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11531 | * Experimentation says that BCS works despite DERRMR masking all | |
11532 | * flip-done completion events and that unmasking all planes at once | |
11533 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11534 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11535 | */ | |
b5321f30 CW |
11536 | if (req->engine->id == RCS) { |
11537 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11538 | intel_ring_emit_reg(ring, DERRMR); | |
11539 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
5a21b665 DV |
11540 | DERRMR_PIPEB_PRI_FLIP_DONE | |
11541 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
11542 | if (IS_GEN8(dev)) | |
b5321f30 | 11543 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
5a21b665 DV |
11544 | MI_SRM_LRM_GLOBAL_GTT); |
11545 | else | |
b5321f30 | 11546 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
5a21b665 | 11547 | MI_SRM_LRM_GLOBAL_GTT); |
b5321f30 CW |
11548 | intel_ring_emit_reg(ring, DERRMR); |
11549 | intel_ring_emit(ring, req->engine->scratch.gtt_offset + 256); | |
5a21b665 | 11550 | if (IS_GEN8(dev)) { |
b5321f30 CW |
11551 | intel_ring_emit(ring, 0); |
11552 | intel_ring_emit(ring, MI_NOOP); | |
5a21b665 DV |
11553 | } |
11554 | } | |
11555 | ||
b5321f30 | 11556 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
3e510a8e | 11557 | intel_ring_emit(ring, fb->pitches[0] | i915_gem_object_get_tiling(obj)); |
b5321f30 CW |
11558 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
11559 | intel_ring_emit(ring, (MI_NOOP)); | |
5a21b665 DV |
11560 | |
11561 | return 0; | |
11562 | } | |
11563 | ||
11564 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11565 | struct drm_i915_gem_object *obj) | |
11566 | { | |
c37efb99 CW |
11567 | struct reservation_object *resv; |
11568 | ||
5a21b665 DV |
11569 | /* |
11570 | * This is not being used for older platforms, because | |
11571 | * non-availability of flip done interrupt forces us to use | |
11572 | * CS flips. Older platforms derive flip done using some clever | |
11573 | * tricks involving the flip_pending status bits and vblank irqs. | |
11574 | * So using MMIO flips there would disrupt this mechanism. | |
11575 | */ | |
11576 | ||
11577 | if (engine == NULL) | |
11578 | return true; | |
11579 | ||
11580 | if (INTEL_GEN(engine->i915) < 5) | |
11581 | return false; | |
11582 | ||
11583 | if (i915.use_mmio_flip < 0) | |
11584 | return false; | |
11585 | else if (i915.use_mmio_flip > 0) | |
11586 | return true; | |
11587 | else if (i915.enable_execlists) | |
11588 | return true; | |
c37efb99 CW |
11589 | |
11590 | resv = i915_gem_object_get_dmabuf_resv(obj); | |
11591 | if (resv && !reservation_object_test_signaled_rcu(resv, false)) | |
5a21b665 | 11592 | return true; |
c37efb99 | 11593 | |
d72d908b CW |
11594 | return engine != i915_gem_active_get_engine(&obj->last_write, |
11595 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
11596 | } |
11597 | ||
11598 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11599 | unsigned int rotation, | |
11600 | struct intel_flip_work *work) | |
11601 | { | |
11602 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11603 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11604 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
11605 | const enum pipe pipe = intel_crtc->pipe; | |
6687c906 | 11606 | u32 ctl, stride; |
5a21b665 DV |
11607 | |
11608 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11609 | ctl &= ~PLANE_CTL_TILED_MASK; | |
11610 | switch (fb->modifier[0]) { | |
11611 | case DRM_FORMAT_MOD_NONE: | |
11612 | break; | |
11613 | case I915_FORMAT_MOD_X_TILED: | |
11614 | ctl |= PLANE_CTL_TILED_X; | |
11615 | break; | |
11616 | case I915_FORMAT_MOD_Y_TILED: | |
11617 | ctl |= PLANE_CTL_TILED_Y; | |
11618 | break; | |
11619 | case I915_FORMAT_MOD_Yf_TILED: | |
11620 | ctl |= PLANE_CTL_TILED_YF; | |
11621 | break; | |
11622 | default: | |
11623 | MISSING_CASE(fb->modifier[0]); | |
11624 | } | |
11625 | ||
11626 | /* | |
11627 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11628 | * linear buffers or in number of tiles for tiled buffers. | |
11629 | */ | |
11630 | if (intel_rotation_90_or_270(rotation)) { | |
6687c906 VS |
11631 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
11632 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
11633 | ||
11634 | stride = intel_fb->rotated[0].pitch / | |
11635 | intel_tile_height(dev_priv, fb->modifier[0], cpp); | |
5a21b665 DV |
11636 | } else { |
11637 | stride = fb->pitches[0] / | |
11638 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
11639 | fb->pixel_format); | |
11640 | } | |
11641 | ||
11642 | /* | |
11643 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11644 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11645 | */ | |
11646 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11647 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11648 | ||
11649 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
11650 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11651 | } | |
11652 | ||
11653 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11654 | struct intel_flip_work *work) | |
11655 | { | |
11656 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11657 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11658 | struct intel_framebuffer *intel_fb = |
11659 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11660 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11661 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); | |
11662 | u32 dspcntr; | |
11663 | ||
11664 | dspcntr = I915_READ(reg); | |
11665 | ||
3e510a8e | 11666 | if (i915_gem_object_is_tiled(obj)) |
5a21b665 DV |
11667 | dspcntr |= DISPPLANE_TILED; |
11668 | else | |
11669 | dspcntr &= ~DISPPLANE_TILED; | |
11670 | ||
11671 | I915_WRITE(reg, dspcntr); | |
11672 | ||
11673 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
11674 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
11675 | } | |
11676 | ||
11677 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
11678 | { | |
11679 | struct intel_flip_work *work = | |
11680 | container_of(w, struct intel_flip_work, mmio_work); | |
11681 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
11682 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
11683 | struct intel_framebuffer *intel_fb = | |
11684 | to_intel_framebuffer(crtc->base.primary->fb); | |
11685 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
c37efb99 | 11686 | struct reservation_object *resv; |
5a21b665 DV |
11687 | |
11688 | if (work->flip_queued_req) | |
776f3236 CW |
11689 | WARN_ON(i915_wait_request(work->flip_queued_req, |
11690 | false, NULL, | |
11691 | NO_WAITBOOST)); | |
5a21b665 DV |
11692 | |
11693 | /* For framebuffer backed by dmabuf, wait for fence */ | |
c37efb99 CW |
11694 | resv = i915_gem_object_get_dmabuf_resv(obj); |
11695 | if (resv) | |
11696 | WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false, | |
5a21b665 DV |
11697 | MAX_SCHEDULE_TIMEOUT) < 0); |
11698 | ||
11699 | intel_pipe_update_start(crtc); | |
11700 | ||
11701 | if (INTEL_GEN(dev_priv) >= 9) | |
11702 | skl_do_mmio_flip(crtc, work->rotation, work); | |
11703 | else | |
11704 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11705 | ilk_do_mmio_flip(crtc, work); | |
11706 | ||
11707 | intel_pipe_update_end(crtc, work); | |
11708 | } | |
11709 | ||
11710 | static int intel_default_queue_flip(struct drm_device *dev, | |
11711 | struct drm_crtc *crtc, | |
11712 | struct drm_framebuffer *fb, | |
11713 | struct drm_i915_gem_object *obj, | |
11714 | struct drm_i915_gem_request *req, | |
11715 | uint32_t flags) | |
11716 | { | |
11717 | return -ENODEV; | |
11718 | } | |
11719 | ||
11720 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
11721 | struct intel_crtc *intel_crtc, | |
11722 | struct intel_flip_work *work) | |
11723 | { | |
11724 | u32 addr, vblank; | |
11725 | ||
11726 | if (!atomic_read(&work->pending)) | |
11727 | return false; | |
11728 | ||
11729 | smp_rmb(); | |
11730 | ||
11731 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
11732 | if (work->flip_ready_vblank == 0) { | |
11733 | if (work->flip_queued_req && | |
f69a02c9 | 11734 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
11735 | return false; |
11736 | ||
11737 | work->flip_ready_vblank = vblank; | |
11738 | } | |
11739 | ||
11740 | if (vblank - work->flip_ready_vblank < 3) | |
11741 | return false; | |
11742 | ||
11743 | /* Potential stall - if we see that the flip has happened, | |
11744 | * assume a missed interrupt. */ | |
11745 | if (INTEL_GEN(dev_priv) >= 4) | |
11746 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11747 | else | |
11748 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11749 | ||
11750 | /* There is a potential issue here with a false positive after a flip | |
11751 | * to the same address. We could address this by checking for a | |
11752 | * non-incrementing frame counter. | |
11753 | */ | |
11754 | return addr == work->gtt_offset; | |
11755 | } | |
11756 | ||
11757 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
11758 | { | |
91c8a326 | 11759 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11760 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11761 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11762 | struct intel_flip_work *work; | |
11763 | ||
11764 | WARN_ON(!in_interrupt()); | |
11765 | ||
11766 | if (crtc == NULL) | |
11767 | return; | |
11768 | ||
11769 | spin_lock(&dev->event_lock); | |
11770 | work = intel_crtc->flip_work; | |
11771 | ||
11772 | if (work != NULL && !is_mmio_work(work) && | |
11773 | __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) { | |
11774 | WARN_ONCE(1, | |
11775 | "Kicking stuck page flip: queued at %d, now %d\n", | |
11776 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc)); | |
11777 | page_flip_completed(intel_crtc); | |
11778 | work = NULL; | |
11779 | } | |
11780 | ||
11781 | if (work != NULL && !is_mmio_work(work) && | |
11782 | intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1) | |
11783 | intel_queue_rps_boost_for_request(work->flip_queued_req); | |
11784 | spin_unlock(&dev->event_lock); | |
11785 | } | |
11786 | ||
11787 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
11788 | struct drm_framebuffer *fb, | |
11789 | struct drm_pending_vblank_event *event, | |
11790 | uint32_t page_flip_flags) | |
11791 | { | |
11792 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 11793 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11794 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
11795 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11797 | struct drm_plane *primary = crtc->primary; | |
11798 | enum pipe pipe = intel_crtc->pipe; | |
11799 | struct intel_flip_work *work; | |
11800 | struct intel_engine_cs *engine; | |
11801 | bool mmio_flip; | |
8e637178 | 11802 | struct drm_i915_gem_request *request; |
5a21b665 DV |
11803 | int ret; |
11804 | ||
11805 | /* | |
11806 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11807 | * check to be safe. In the future we may enable pageflipping from | |
11808 | * a disabled primary plane. | |
11809 | */ | |
11810 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11811 | return -EBUSY; | |
11812 | ||
11813 | /* Can't change pixel format via MI display flips. */ | |
11814 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
11815 | return -EINVAL; | |
11816 | ||
11817 | /* | |
11818 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11819 | * Note that pitch changes could also affect these register. | |
11820 | */ | |
11821 | if (INTEL_INFO(dev)->gen > 3 && | |
11822 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || | |
11823 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
11824 | return -EINVAL; | |
11825 | ||
11826 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
11827 | goto out_hang; | |
11828 | ||
11829 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
11830 | if (work == NULL) | |
11831 | return -ENOMEM; | |
11832 | ||
11833 | work->event = event; | |
11834 | work->crtc = crtc; | |
11835 | work->old_fb = old_fb; | |
11836 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
11837 | ||
11838 | ret = drm_crtc_vblank_get(crtc); | |
11839 | if (ret) | |
11840 | goto free_work; | |
11841 | ||
11842 | /* We borrow the event spin lock for protecting flip_work */ | |
11843 | spin_lock_irq(&dev->event_lock); | |
11844 | if (intel_crtc->flip_work) { | |
11845 | /* Before declaring the flip queue wedged, check if | |
11846 | * the hardware completed the operation behind our backs. | |
11847 | */ | |
11848 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
11849 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11850 | page_flip_completed(intel_crtc); | |
11851 | } else { | |
11852 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
11853 | spin_unlock_irq(&dev->event_lock); | |
11854 | ||
11855 | drm_crtc_vblank_put(crtc); | |
11856 | kfree(work); | |
11857 | return -EBUSY; | |
11858 | } | |
11859 | } | |
11860 | intel_crtc->flip_work = work; | |
11861 | spin_unlock_irq(&dev->event_lock); | |
11862 | ||
11863 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
11864 | flush_workqueue(dev_priv->wq); | |
11865 | ||
11866 | /* Reference the objects for the scheduled work. */ | |
11867 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
11868 | |
11869 | crtc->primary->fb = fb; | |
11870 | update_state_fb(crtc->primary); | |
faf68d92 ML |
11871 | |
11872 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
11873 | to_intel_plane_state(primary->state)); | |
5a21b665 | 11874 | |
25dc556a | 11875 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
11876 | |
11877 | ret = i915_mutex_lock_interruptible(dev); | |
11878 | if (ret) | |
11879 | goto cleanup; | |
11880 | ||
11881 | intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); | |
11882 | if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) { | |
11883 | ret = -EIO; | |
11884 | goto cleanup; | |
11885 | } | |
11886 | ||
11887 | atomic_inc(&intel_crtc->unpin_work_count); | |
11888 | ||
11889 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
11890 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; | |
11891 | ||
11892 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
11893 | engine = &dev_priv->engine[BCS]; | |
3e510a8e CW |
11894 | if (i915_gem_object_get_tiling(obj) != |
11895 | i915_gem_object_get_tiling(intel_fb_obj(work->old_fb))) | |
5a21b665 DV |
11896 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11897 | engine = NULL; | |
11898 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { | |
11899 | engine = &dev_priv->engine[BCS]; | |
11900 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
d72d908b CW |
11901 | engine = i915_gem_active_get_engine(&obj->last_write, |
11902 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
11903 | if (engine == NULL || engine->id != RCS) |
11904 | engine = &dev_priv->engine[BCS]; | |
11905 | } else { | |
11906 | engine = &dev_priv->engine[RCS]; | |
11907 | } | |
11908 | ||
11909 | mmio_flip = use_mmio_flip(engine, obj); | |
11910 | ||
5a21b665 DV |
11911 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
11912 | if (ret) | |
11913 | goto cleanup_pending; | |
11914 | ||
6687c906 | 11915 | work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation); |
5a21b665 DV |
11916 | work->gtt_offset += intel_crtc->dspaddr_offset; |
11917 | work->rotation = crtc->primary->state->rotation; | |
11918 | ||
11919 | if (mmio_flip) { | |
11920 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
11921 | ||
d72d908b CW |
11922 | work->flip_queued_req = i915_gem_active_get(&obj->last_write, |
11923 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
11924 | schedule_work(&work->mmio_work); |
11925 | } else { | |
8e637178 CW |
11926 | request = i915_gem_request_alloc(engine, engine->last_context); |
11927 | if (IS_ERR(request)) { | |
11928 | ret = PTR_ERR(request); | |
11929 | goto cleanup_unpin; | |
11930 | } | |
11931 | ||
11932 | ret = i915_gem_object_sync(obj, request); | |
11933 | if (ret) | |
11934 | goto cleanup_request; | |
11935 | ||
5a21b665 DV |
11936 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
11937 | page_flip_flags); | |
11938 | if (ret) | |
8e637178 | 11939 | goto cleanup_request; |
5a21b665 DV |
11940 | |
11941 | intel_mark_page_flip_active(intel_crtc, work); | |
11942 | ||
8e637178 | 11943 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
11944 | i915_add_request_no_flush(request); |
11945 | } | |
11946 | ||
11947 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, | |
11948 | to_intel_plane(primary)->frontbuffer_bit); | |
11949 | mutex_unlock(&dev->struct_mutex); | |
11950 | ||
5748b6a1 | 11951 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
11952 | to_intel_plane(primary)->frontbuffer_bit); |
11953 | ||
11954 | trace_i915_flip_request(intel_crtc->plane, obj); | |
11955 | ||
11956 | return 0; | |
11957 | ||
8e637178 CW |
11958 | cleanup_request: |
11959 | i915_add_request_no_flush(request); | |
5a21b665 DV |
11960 | cleanup_unpin: |
11961 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
11962 | cleanup_pending: | |
5a21b665 DV |
11963 | atomic_dec(&intel_crtc->unpin_work_count); |
11964 | mutex_unlock(&dev->struct_mutex); | |
11965 | cleanup: | |
11966 | crtc->primary->fb = old_fb; | |
11967 | update_state_fb(crtc->primary); | |
11968 | ||
34911fd3 | 11969 | i915_gem_object_put_unlocked(obj); |
5a21b665 DV |
11970 | drm_framebuffer_unreference(work->old_fb); |
11971 | ||
11972 | spin_lock_irq(&dev->event_lock); | |
11973 | intel_crtc->flip_work = NULL; | |
11974 | spin_unlock_irq(&dev->event_lock); | |
11975 | ||
11976 | drm_crtc_vblank_put(crtc); | |
11977 | free_work: | |
11978 | kfree(work); | |
11979 | ||
11980 | if (ret == -EIO) { | |
11981 | struct drm_atomic_state *state; | |
11982 | struct drm_plane_state *plane_state; | |
11983 | ||
11984 | out_hang: | |
11985 | state = drm_atomic_state_alloc(dev); | |
11986 | if (!state) | |
11987 | return -ENOMEM; | |
11988 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11989 | ||
11990 | retry: | |
11991 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11992 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11993 | if (!ret) { | |
11994 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11995 | ||
11996 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11997 | if (!ret) | |
11998 | ret = drm_atomic_commit(state); | |
11999 | } | |
12000 | ||
12001 | if (ret == -EDEADLK) { | |
12002 | drm_modeset_backoff(state->acquire_ctx); | |
12003 | drm_atomic_state_clear(state); | |
12004 | goto retry; | |
12005 | } | |
12006 | ||
12007 | if (ret) | |
12008 | drm_atomic_state_free(state); | |
12009 | ||
12010 | if (ret == 0 && event) { | |
12011 | spin_lock_irq(&dev->event_lock); | |
12012 | drm_crtc_send_vblank_event(crtc, event); | |
12013 | spin_unlock_irq(&dev->event_lock); | |
12014 | } | |
12015 | } | |
12016 | return ret; | |
12017 | } | |
12018 | ||
12019 | ||
12020 | /** | |
12021 | * intel_wm_need_update - Check whether watermarks need updating | |
12022 | * @plane: drm plane | |
12023 | * @state: new plane state | |
12024 | * | |
12025 | * Check current plane state versus the new one to determine whether | |
12026 | * watermarks need to be recalculated. | |
12027 | * | |
12028 | * Returns true or false. | |
12029 | */ | |
12030 | static bool intel_wm_need_update(struct drm_plane *plane, | |
12031 | struct drm_plane_state *state) | |
12032 | { | |
12033 | struct intel_plane_state *new = to_intel_plane_state(state); | |
12034 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
12035 | ||
12036 | /* Update watermarks on tiling or size changes. */ | |
12037 | if (new->visible != cur->visible) | |
12038 | return true; | |
12039 | ||
12040 | if (!cur->base.fb || !new->base.fb) | |
12041 | return false; | |
12042 | ||
12043 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
12044 | cur->base.rotation != new->base.rotation || | |
12045 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || | |
12046 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
12047 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
12048 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
12049 | return true; | |
12050 | ||
12051 | return false; | |
12052 | } | |
12053 | ||
12054 | static bool needs_scaling(struct intel_plane_state *state) | |
12055 | { | |
12056 | int src_w = drm_rect_width(&state->src) >> 16; | |
12057 | int src_h = drm_rect_height(&state->src) >> 16; | |
12058 | int dst_w = drm_rect_width(&state->dst); | |
12059 | int dst_h = drm_rect_height(&state->dst); | |
12060 | ||
12061 | return (src_w != dst_w || src_h != dst_h); | |
12062 | } | |
d21fbe87 | 12063 | |
da20eabd ML |
12064 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
12065 | struct drm_plane_state *plane_state) | |
12066 | { | |
ab1d3a0e | 12067 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
12068 | struct drm_crtc *crtc = crtc_state->crtc; |
12069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12070 | struct drm_plane *plane = plane_state->plane; | |
12071 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 12072 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
12073 | struct intel_plane_state *old_plane_state = |
12074 | to_intel_plane_state(plane->state); | |
da20eabd ML |
12075 | bool mode_changed = needs_modeset(crtc_state); |
12076 | bool was_crtc_enabled = crtc->state->active; | |
12077 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
12078 | bool turn_off, turn_on, visible, was_visible; |
12079 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 12080 | int ret; |
da20eabd | 12081 | |
84114990 | 12082 | if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
12083 | ret = skl_update_scaler_plane( |
12084 | to_intel_crtc_state(crtc_state), | |
12085 | to_intel_plane_state(plane_state)); | |
12086 | if (ret) | |
12087 | return ret; | |
12088 | } | |
12089 | ||
da20eabd ML |
12090 | was_visible = old_plane_state->visible; |
12091 | visible = to_intel_plane_state(plane_state)->visible; | |
12092 | ||
12093 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
12094 | was_visible = false; | |
12095 | ||
35c08f43 ML |
12096 | /* |
12097 | * Visibility is calculated as if the crtc was on, but | |
12098 | * after scaler setup everything depends on it being off | |
12099 | * when the crtc isn't active. | |
f818ffea VS |
12100 | * |
12101 | * FIXME this is wrong for watermarks. Watermarks should also | |
12102 | * be computed as if the pipe would be active. Perhaps move | |
12103 | * per-plane wm computation to the .check_plane() hook, and | |
12104 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
12105 | */ |
12106 | if (!is_crtc_enabled) | |
12107 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
12108 | |
12109 | if (!was_visible && !visible) | |
12110 | return 0; | |
12111 | ||
e8861675 ML |
12112 | if (fb != old_plane_state->base.fb) |
12113 | pipe_config->fb_changed = true; | |
12114 | ||
da20eabd ML |
12115 | turn_off = was_visible && (!visible || mode_changed); |
12116 | turn_on = visible && (!was_visible || mode_changed); | |
12117 | ||
72660ce0 | 12118 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
12119 | intel_crtc->base.base.id, |
12120 | intel_crtc->base.name, | |
72660ce0 VS |
12121 | plane->base.id, plane->name, |
12122 | fb ? fb->base.id : -1); | |
da20eabd | 12123 | |
72660ce0 VS |
12124 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
12125 | plane->base.id, plane->name, | |
12126 | was_visible, visible, | |
da20eabd ML |
12127 | turn_off, turn_on, mode_changed); |
12128 | ||
caed361d VS |
12129 | if (turn_on) { |
12130 | pipe_config->update_wm_pre = true; | |
12131 | ||
12132 | /* must disable cxsr around plane enable/disable */ | |
12133 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
12134 | pipe_config->disable_cxsr = true; | |
12135 | } else if (turn_off) { | |
12136 | pipe_config->update_wm_post = true; | |
92826fcd | 12137 | |
852eb00d | 12138 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 12139 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 12140 | pipe_config->disable_cxsr = true; |
852eb00d | 12141 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
12142 | /* FIXME bollocks */ |
12143 | pipe_config->update_wm_pre = true; | |
12144 | pipe_config->update_wm_post = true; | |
852eb00d | 12145 | } |
da20eabd | 12146 | |
ed4a6a7c | 12147 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
12148 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
12149 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
12150 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
12151 | ||
8be6ca85 | 12152 | if (visible || was_visible) |
cd202f69 | 12153 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 12154 | |
31ae71fc ML |
12155 | /* |
12156 | * WaCxSRDisabledForSpriteScaling:ivb | |
12157 | * | |
12158 | * cstate->update_wm was already set above, so this flag will | |
12159 | * take effect when we commit and program watermarks. | |
12160 | */ | |
12161 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
12162 | needs_scaling(to_intel_plane_state(plane_state)) && | |
12163 | !needs_scaling(old_plane_state)) | |
12164 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 12165 | |
da20eabd ML |
12166 | return 0; |
12167 | } | |
12168 | ||
6d3a1ce7 ML |
12169 | static bool encoders_cloneable(const struct intel_encoder *a, |
12170 | const struct intel_encoder *b) | |
12171 | { | |
12172 | /* masks could be asymmetric, so check both ways */ | |
12173 | return a == b || (a->cloneable & (1 << b->type) && | |
12174 | b->cloneable & (1 << a->type)); | |
12175 | } | |
12176 | ||
12177 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12178 | struct intel_crtc *crtc, | |
12179 | struct intel_encoder *encoder) | |
12180 | { | |
12181 | struct intel_encoder *source_encoder; | |
12182 | struct drm_connector *connector; | |
12183 | struct drm_connector_state *connector_state; | |
12184 | int i; | |
12185 | ||
12186 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12187 | if (connector_state->crtc != &crtc->base) | |
12188 | continue; | |
12189 | ||
12190 | source_encoder = | |
12191 | to_intel_encoder(connector_state->best_encoder); | |
12192 | if (!encoders_cloneable(encoder, source_encoder)) | |
12193 | return false; | |
12194 | } | |
12195 | ||
12196 | return true; | |
12197 | } | |
12198 | ||
6d3a1ce7 ML |
12199 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
12200 | struct drm_crtc_state *crtc_state) | |
12201 | { | |
cf5a15be | 12202 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12203 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 12204 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12205 | struct intel_crtc_state *pipe_config = |
12206 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12207 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12208 | int ret; |
6d3a1ce7 ML |
12209 | bool mode_changed = needs_modeset(crtc_state); |
12210 | ||
852eb00d | 12211 | if (mode_changed && !crtc_state->active) |
caed361d | 12212 | pipe_config->update_wm_post = true; |
eddfcbcd | 12213 | |
ad421372 ML |
12214 | if (mode_changed && crtc_state->enable && |
12215 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 12216 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
12217 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12218 | pipe_config); | |
12219 | if (ret) | |
12220 | return ret; | |
12221 | } | |
12222 | ||
82cf435b LL |
12223 | if (crtc_state->color_mgmt_changed) { |
12224 | ret = intel_color_check(crtc, crtc_state); | |
12225 | if (ret) | |
12226 | return ret; | |
e7852a4b LL |
12227 | |
12228 | /* | |
12229 | * Changing color management on Intel hardware is | |
12230 | * handled as part of planes update. | |
12231 | */ | |
12232 | crtc_state->planes_changed = true; | |
82cf435b LL |
12233 | } |
12234 | ||
e435d6e5 | 12235 | ret = 0; |
86c8bbbe | 12236 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12237 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12238 | if (ret) { |
12239 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12240 | return ret; | |
12241 | } | |
12242 | } | |
12243 | ||
12244 | if (dev_priv->display.compute_intermediate_wm && | |
12245 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12246 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12247 | return 0; | |
12248 | ||
12249 | /* | |
12250 | * Calculate 'intermediate' watermarks that satisfy both the | |
12251 | * old state and the new state. We can program these | |
12252 | * immediately. | |
12253 | */ | |
12254 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12255 | intel_crtc, | |
12256 | pipe_config); | |
12257 | if (ret) { | |
12258 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12259 | return ret; |
ed4a6a7c | 12260 | } |
e3d5457c VS |
12261 | } else if (dev_priv->display.compute_intermediate_wm) { |
12262 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12263 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12264 | } |
12265 | ||
e435d6e5 ML |
12266 | if (INTEL_INFO(dev)->gen >= 9) { |
12267 | if (mode_changed) | |
12268 | ret = skl_update_scaler_crtc(pipe_config); | |
12269 | ||
12270 | if (!ret) | |
12271 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12272 | pipe_config); | |
12273 | } | |
12274 | ||
12275 | return ret; | |
6d3a1ce7 ML |
12276 | } |
12277 | ||
65b38e0d | 12278 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12279 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12280 | .atomic_begin = intel_begin_crtc_commit, |
12281 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12282 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12283 | }; |
12284 | ||
d29b2f9d ACO |
12285 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12286 | { | |
12287 | struct intel_connector *connector; | |
12288 | ||
12289 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12290 | if (connector->base.state->crtc) |
12291 | drm_connector_unreference(&connector->base); | |
12292 | ||
d29b2f9d ACO |
12293 | if (connector->base.encoder) { |
12294 | connector->base.state->best_encoder = | |
12295 | connector->base.encoder; | |
12296 | connector->base.state->crtc = | |
12297 | connector->base.encoder->crtc; | |
8863dc7f DV |
12298 | |
12299 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12300 | } else { |
12301 | connector->base.state->best_encoder = NULL; | |
12302 | connector->base.state->crtc = NULL; | |
12303 | } | |
12304 | } | |
12305 | } | |
12306 | ||
050f7aeb | 12307 | static void |
eba905b2 | 12308 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12309 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12310 | { |
12311 | int bpp = pipe_config->pipe_bpp; | |
12312 | ||
12313 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12314 | connector->base.base.id, | |
c23cc417 | 12315 | connector->base.name); |
050f7aeb DV |
12316 | |
12317 | /* Don't use an invalid EDID bpc value */ | |
12318 | if (connector->base.display_info.bpc && | |
12319 | connector->base.display_info.bpc * 3 < bpp) { | |
12320 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12321 | bpp, connector->base.display_info.bpc*3); | |
12322 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12323 | } | |
12324 | ||
013dd9e0 JN |
12325 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12326 | if (connector->base.display_info.bpc == 0) { | |
12327 | int type = connector->base.connector_type; | |
12328 | int clamp_bpp = 24; | |
12329 | ||
12330 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12331 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12332 | type == DRM_MODE_CONNECTOR_eDP) | |
12333 | clamp_bpp = 18; | |
12334 | ||
12335 | if (bpp > clamp_bpp) { | |
12336 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12337 | bpp, clamp_bpp); | |
12338 | pipe_config->pipe_bpp = clamp_bpp; | |
12339 | } | |
050f7aeb DV |
12340 | } |
12341 | } | |
12342 | ||
4e53c2e0 | 12343 | static int |
050f7aeb | 12344 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12345 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12346 | { |
050f7aeb | 12347 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12348 | struct drm_atomic_state *state; |
da3ced29 ACO |
12349 | struct drm_connector *connector; |
12350 | struct drm_connector_state *connector_state; | |
1486017f | 12351 | int bpp, i; |
4e53c2e0 | 12352 | |
666a4537 | 12353 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12354 | bpp = 10*3; |
d328c9d7 DV |
12355 | else if (INTEL_INFO(dev)->gen >= 5) |
12356 | bpp = 12*3; | |
12357 | else | |
12358 | bpp = 8*3; | |
12359 | ||
4e53c2e0 | 12360 | |
4e53c2e0 DV |
12361 | pipe_config->pipe_bpp = bpp; |
12362 | ||
1486017f ACO |
12363 | state = pipe_config->base.state; |
12364 | ||
4e53c2e0 | 12365 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12366 | for_each_connector_in_state(state, connector, connector_state, i) { |
12367 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12368 | continue; |
12369 | ||
da3ced29 ACO |
12370 | connected_sink_compute_bpp(to_intel_connector(connector), |
12371 | pipe_config); | |
4e53c2e0 DV |
12372 | } |
12373 | ||
12374 | return bpp; | |
12375 | } | |
12376 | ||
644db711 DV |
12377 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12378 | { | |
12379 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12380 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12381 | mode->crtc_clock, |
644db711 DV |
12382 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12383 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12384 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12385 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12386 | } | |
12387 | ||
c0b03411 | 12388 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12389 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12390 | const char *context) |
12391 | { | |
6a60cd87 CK |
12392 | struct drm_device *dev = crtc->base.dev; |
12393 | struct drm_plane *plane; | |
12394 | struct intel_plane *intel_plane; | |
12395 | struct intel_plane_state *state; | |
12396 | struct drm_framebuffer *fb; | |
12397 | ||
78108b7c VS |
12398 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n", |
12399 | crtc->base.base.id, crtc->base.name, | |
6a60cd87 | 12400 | context, pipe_config, pipe_name(crtc->pipe)); |
c0b03411 | 12401 | |
da205630 | 12402 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12403 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12404 | pipe_config->pipe_bpp, pipe_config->dither); | |
12405 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12406 | pipe_config->has_pch_encoder, | |
12407 | pipe_config->fdi_lanes, | |
12408 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12409 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12410 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12411 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
37a5650b | 12412 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12413 | pipe_config->lane_count, |
eb14cb74 VS |
12414 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12415 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12416 | pipe_config->dp_m_n.tu); | |
b95af8be | 12417 | |
90a6b7b0 | 12418 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
37a5650b | 12419 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12420 | pipe_config->lane_count, |
b95af8be VK |
12421 | pipe_config->dp_m2_n2.gmch_m, |
12422 | pipe_config->dp_m2_n2.gmch_n, | |
12423 | pipe_config->dp_m2_n2.link_m, | |
12424 | pipe_config->dp_m2_n2.link_n, | |
12425 | pipe_config->dp_m2_n2.tu); | |
12426 | ||
55072d19 DV |
12427 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12428 | pipe_config->has_audio, | |
12429 | pipe_config->has_infoframe); | |
12430 | ||
c0b03411 | 12431 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12432 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12433 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12434 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12435 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12436 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12437 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12438 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12439 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12440 | crtc->num_scalers, | |
12441 | pipe_config->scaler_state.scaler_users, | |
12442 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12443 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12444 | pipe_config->gmch_pfit.control, | |
12445 | pipe_config->gmch_pfit.pgm_ratios, | |
12446 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12447 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12448 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12449 | pipe_config->pch_pfit.size, |
12450 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12451 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12452 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12453 | |
415ff0f6 | 12454 | if (IS_BROXTON(dev)) { |
05712c15 | 12455 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12456 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12457 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12458 | pipe_config->ddi_pll_sel, |
12459 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12460 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12461 | pipe_config->dpll_hw_state.pll0, |
12462 | pipe_config->dpll_hw_state.pll1, | |
12463 | pipe_config->dpll_hw_state.pll2, | |
12464 | pipe_config->dpll_hw_state.pll3, | |
12465 | pipe_config->dpll_hw_state.pll6, | |
12466 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12467 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12468 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12469 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12470 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12471 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12472 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12473 | pipe_config->ddi_pll_sel, | |
12474 | pipe_config->dpll_hw_state.ctrl1, | |
12475 | pipe_config->dpll_hw_state.cfgcr1, | |
12476 | pipe_config->dpll_hw_state.cfgcr2); | |
12477 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12478 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12479 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12480 | pipe_config->dpll_hw_state.wrpll, |
12481 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12482 | } else { |
12483 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12484 | "fp0: 0x%x, fp1: 0x%x\n", | |
12485 | pipe_config->dpll_hw_state.dpll, | |
12486 | pipe_config->dpll_hw_state.dpll_md, | |
12487 | pipe_config->dpll_hw_state.fp0, | |
12488 | pipe_config->dpll_hw_state.fp1); | |
12489 | } | |
12490 | ||
6a60cd87 CK |
12491 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12492 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12493 | intel_plane = to_intel_plane(plane); | |
12494 | if (intel_plane->pipe != crtc->pipe) | |
12495 | continue; | |
12496 | ||
12497 | state = to_intel_plane_state(plane->state); | |
12498 | fb = state->base.fb; | |
12499 | if (!fb) { | |
1d577e02 VS |
12500 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12501 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12502 | continue; |
12503 | } | |
12504 | ||
1d577e02 VS |
12505 | DRM_DEBUG_KMS("[PLANE:%d:%s] enabled", |
12506 | plane->base.id, plane->name); | |
12507 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s", | |
12508 | fb->base.id, fb->width, fb->height, | |
12509 | drm_get_format_name(fb->pixel_format)); | |
12510 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
12511 | state->scaler_id, | |
12512 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12513 | drm_rect_width(&state->src) >> 16, | |
12514 | drm_rect_height(&state->src) >> 16, | |
12515 | state->dst.x1, state->dst.y1, | |
12516 | drm_rect_width(&state->dst), | |
12517 | drm_rect_height(&state->dst)); | |
6a60cd87 | 12518 | } |
c0b03411 DV |
12519 | } |
12520 | ||
5448a00d | 12521 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12522 | { |
5448a00d | 12523 | struct drm_device *dev = state->dev; |
da3ced29 | 12524 | struct drm_connector *connector; |
00f0b378 | 12525 | unsigned int used_ports = 0; |
477321e0 | 12526 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
12527 | |
12528 | /* | |
12529 | * Walk the connector list instead of the encoder | |
12530 | * list to detect the problem on ddi platforms | |
12531 | * where there's just one encoder per digital port. | |
12532 | */ | |
0bff4858 VS |
12533 | drm_for_each_connector(connector, dev) { |
12534 | struct drm_connector_state *connector_state; | |
12535 | struct intel_encoder *encoder; | |
12536 | ||
12537 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12538 | if (!connector_state) | |
12539 | connector_state = connector->state; | |
12540 | ||
5448a00d | 12541 | if (!connector_state->best_encoder) |
00f0b378 VS |
12542 | continue; |
12543 | ||
5448a00d ACO |
12544 | encoder = to_intel_encoder(connector_state->best_encoder); |
12545 | ||
12546 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12547 | |
12548 | switch (encoder->type) { | |
12549 | unsigned int port_mask; | |
12550 | case INTEL_OUTPUT_UNKNOWN: | |
12551 | if (WARN_ON(!HAS_DDI(dev))) | |
12552 | break; | |
cca0502b | 12553 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
12554 | case INTEL_OUTPUT_HDMI: |
12555 | case INTEL_OUTPUT_EDP: | |
12556 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12557 | ||
12558 | /* the same port mustn't appear more than once */ | |
12559 | if (used_ports & port_mask) | |
12560 | return false; | |
12561 | ||
12562 | used_ports |= port_mask; | |
477321e0 VS |
12563 | break; |
12564 | case INTEL_OUTPUT_DP_MST: | |
12565 | used_mst_ports |= | |
12566 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
12567 | break; | |
00f0b378 VS |
12568 | default: |
12569 | break; | |
12570 | } | |
12571 | } | |
12572 | ||
477321e0 VS |
12573 | /* can't mix MST and SST/HDMI on the same port */ |
12574 | if (used_ports & used_mst_ports) | |
12575 | return false; | |
12576 | ||
00f0b378 VS |
12577 | return true; |
12578 | } | |
12579 | ||
83a57153 ACO |
12580 | static void |
12581 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12582 | { | |
12583 | struct drm_crtc_state tmp_state; | |
663a3640 | 12584 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12585 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12586 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12587 | uint32_t ddi_pll_sel; |
c4e2d043 | 12588 | bool force_thru; |
83a57153 | 12589 | |
7546a384 ACO |
12590 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12591 | * kzalloc'd. Code that depends on any field being zero should be | |
12592 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12593 | * only fields that are know to not cause problems are preserved. */ | |
12594 | ||
83a57153 | 12595 | tmp_state = crtc_state->base; |
663a3640 | 12596 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12597 | shared_dpll = crtc_state->shared_dpll; |
12598 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12599 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12600 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12601 | |
83a57153 | 12602 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12603 | |
83a57153 | 12604 | crtc_state->base = tmp_state; |
663a3640 | 12605 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12606 | crtc_state->shared_dpll = shared_dpll; |
12607 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12608 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12609 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12610 | } |
12611 | ||
548ee15b | 12612 | static int |
b8cecdf5 | 12613 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12614 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12615 | { |
b359283a | 12616 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12617 | struct intel_encoder *encoder; |
da3ced29 | 12618 | struct drm_connector *connector; |
0b901879 | 12619 | struct drm_connector_state *connector_state; |
d328c9d7 | 12620 | int base_bpp, ret = -EINVAL; |
0b901879 | 12621 | int i; |
e29c22c0 | 12622 | bool retry = true; |
ee7b9f93 | 12623 | |
83a57153 | 12624 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12625 | |
e143a21c DV |
12626 | pipe_config->cpu_transcoder = |
12627 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12628 | |
2960bc9c ID |
12629 | /* |
12630 | * Sanitize sync polarity flags based on requested ones. If neither | |
12631 | * positive or negative polarity is requested, treat this as meaning | |
12632 | * negative polarity. | |
12633 | */ | |
2d112de7 | 12634 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12635 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12636 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12637 | |
2d112de7 | 12638 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12639 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12640 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12641 | |
d328c9d7 DV |
12642 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12643 | pipe_config); | |
12644 | if (base_bpp < 0) | |
4e53c2e0 DV |
12645 | goto fail; |
12646 | ||
e41a56be VS |
12647 | /* |
12648 | * Determine the real pipe dimensions. Note that stereo modes can | |
12649 | * increase the actual pipe size due to the frame doubling and | |
12650 | * insertion of additional space for blanks between the frame. This | |
12651 | * is stored in the crtc timings. We use the requested mode to do this | |
12652 | * computation to clearly distinguish it from the adjusted mode, which | |
12653 | * can be changed by the connectors in the below retry loop. | |
12654 | */ | |
2d112de7 | 12655 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12656 | &pipe_config->pipe_src_w, |
12657 | &pipe_config->pipe_src_h); | |
e41a56be | 12658 | |
253c84c8 VS |
12659 | for_each_connector_in_state(state, connector, connector_state, i) { |
12660 | if (connector_state->crtc != crtc) | |
12661 | continue; | |
12662 | ||
12663 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12664 | ||
e25148d0 VS |
12665 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
12666 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12667 | goto fail; | |
12668 | } | |
12669 | ||
253c84c8 VS |
12670 | /* |
12671 | * Determine output_types before calling the .compute_config() | |
12672 | * hooks so that the hooks can use this information safely. | |
12673 | */ | |
12674 | pipe_config->output_types |= 1 << encoder->type; | |
12675 | } | |
12676 | ||
e29c22c0 | 12677 | encoder_retry: |
ef1b460d | 12678 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12679 | pipe_config->port_clock = 0; |
ef1b460d | 12680 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12681 | |
135c81b8 | 12682 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12683 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12684 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12685 | |
7758a113 DV |
12686 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12687 | * adjust it according to limitations or connector properties, and also | |
12688 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12689 | */ |
da3ced29 | 12690 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12691 | if (connector_state->crtc != crtc) |
7758a113 | 12692 | continue; |
7ae89233 | 12693 | |
0b901879 ACO |
12694 | encoder = to_intel_encoder(connector_state->best_encoder); |
12695 | ||
efea6e8e DV |
12696 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12697 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12698 | goto fail; |
12699 | } | |
ee7b9f93 | 12700 | } |
47f1c6c9 | 12701 | |
ff9a6750 DV |
12702 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12703 | * done afterwards in case the encoder adjusts the mode. */ | |
12704 | if (!pipe_config->port_clock) | |
2d112de7 | 12705 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12706 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12707 | |
a43f6e0f | 12708 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12709 | if (ret < 0) { |
7758a113 DV |
12710 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12711 | goto fail; | |
ee7b9f93 | 12712 | } |
e29c22c0 DV |
12713 | |
12714 | if (ret == RETRY) { | |
12715 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12716 | ret = -EINVAL; | |
12717 | goto fail; | |
12718 | } | |
12719 | ||
12720 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12721 | retry = false; | |
12722 | goto encoder_retry; | |
12723 | } | |
12724 | ||
e8fa4270 DV |
12725 | /* Dithering seems to not pass-through bits correctly when it should, so |
12726 | * only enable it on 6bpc panels. */ | |
12727 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12728 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12729 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12730 | |
7758a113 | 12731 | fail: |
548ee15b | 12732 | return ret; |
ee7b9f93 | 12733 | } |
47f1c6c9 | 12734 | |
ea9d758d | 12735 | static void |
4740b0f2 | 12736 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12737 | { |
0a9ab303 ACO |
12738 | struct drm_crtc *crtc; |
12739 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12740 | int i; |
ea9d758d | 12741 | |
7668851f | 12742 | /* Double check state. */ |
8a75d157 | 12743 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12744 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12745 | |
12746 | /* Update hwmode for vblank functions */ | |
12747 | if (crtc->state->active) | |
12748 | crtc->hwmode = crtc->state->adjusted_mode; | |
12749 | else | |
12750 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12751 | |
12752 | /* | |
12753 | * Update legacy state to satisfy fbc code. This can | |
12754 | * be removed when fbc uses the atomic state. | |
12755 | */ | |
12756 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12757 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12758 | ||
12759 | crtc->primary->fb = plane_state->fb; | |
12760 | crtc->x = plane_state->src_x >> 16; | |
12761 | crtc->y = plane_state->src_y >> 16; | |
12762 | } | |
ea9d758d | 12763 | } |
ea9d758d DV |
12764 | } |
12765 | ||
3bd26263 | 12766 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12767 | { |
3bd26263 | 12768 | int diff; |
f1f644dc JB |
12769 | |
12770 | if (clock1 == clock2) | |
12771 | return true; | |
12772 | ||
12773 | if (!clock1 || !clock2) | |
12774 | return false; | |
12775 | ||
12776 | diff = abs(clock1 - clock2); | |
12777 | ||
12778 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12779 | return true; | |
12780 | ||
12781 | return false; | |
12782 | } | |
12783 | ||
25c5b266 DV |
12784 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12785 | list_for_each_entry((intel_crtc), \ | |
12786 | &(dev)->mode_config.crtc_list, \ | |
12787 | base.head) \ | |
95150bdf | 12788 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12789 | |
cfb23ed6 ML |
12790 | static bool |
12791 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12792 | unsigned int m2, unsigned int n2, | |
12793 | bool exact) | |
12794 | { | |
12795 | if (m == m2 && n == n2) | |
12796 | return true; | |
12797 | ||
12798 | if (exact || !m || !n || !m2 || !n2) | |
12799 | return false; | |
12800 | ||
12801 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12802 | ||
31d10b57 ML |
12803 | if (n > n2) { |
12804 | while (n > n2) { | |
cfb23ed6 ML |
12805 | m2 <<= 1; |
12806 | n2 <<= 1; | |
12807 | } | |
31d10b57 ML |
12808 | } else if (n < n2) { |
12809 | while (n < n2) { | |
cfb23ed6 ML |
12810 | m <<= 1; |
12811 | n <<= 1; | |
12812 | } | |
12813 | } | |
12814 | ||
31d10b57 ML |
12815 | if (n != n2) |
12816 | return false; | |
12817 | ||
12818 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12819 | } |
12820 | ||
12821 | static bool | |
12822 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12823 | struct intel_link_m_n *m2_n2, | |
12824 | bool adjust) | |
12825 | { | |
12826 | if (m_n->tu == m2_n2->tu && | |
12827 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12828 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12829 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12830 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12831 | if (adjust) | |
12832 | *m2_n2 = *m_n; | |
12833 | ||
12834 | return true; | |
12835 | } | |
12836 | ||
12837 | return false; | |
12838 | } | |
12839 | ||
0e8ffe1b | 12840 | static bool |
2fa2fe9a | 12841 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12842 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12843 | struct intel_crtc_state *pipe_config, |
12844 | bool adjust) | |
0e8ffe1b | 12845 | { |
cfb23ed6 ML |
12846 | bool ret = true; |
12847 | ||
12848 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12849 | do { \ | |
12850 | if (!adjust) \ | |
12851 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12852 | else \ | |
12853 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12854 | } while (0) | |
12855 | ||
66e985c0 DV |
12856 | #define PIPE_CONF_CHECK_X(name) \ |
12857 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12858 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12859 | "(expected 0x%08x, found 0x%08x)\n", \ |
12860 | current_config->name, \ | |
12861 | pipe_config->name); \ | |
cfb23ed6 | 12862 | ret = false; \ |
66e985c0 DV |
12863 | } |
12864 | ||
08a24034 DV |
12865 | #define PIPE_CONF_CHECK_I(name) \ |
12866 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12867 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12868 | "(expected %i, found %i)\n", \ |
12869 | current_config->name, \ | |
12870 | pipe_config->name); \ | |
cfb23ed6 ML |
12871 | ret = false; \ |
12872 | } | |
12873 | ||
8106ddbd ACO |
12874 | #define PIPE_CONF_CHECK_P(name) \ |
12875 | if (current_config->name != pipe_config->name) { \ | |
12876 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12877 | "(expected %p, found %p)\n", \ | |
12878 | current_config->name, \ | |
12879 | pipe_config->name); \ | |
12880 | ret = false; \ | |
12881 | } | |
12882 | ||
cfb23ed6 ML |
12883 | #define PIPE_CONF_CHECK_M_N(name) \ |
12884 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12885 | &pipe_config->name,\ | |
12886 | adjust)) { \ | |
12887 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12888 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12889 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12890 | current_config->name.tu, \ | |
12891 | current_config->name.gmch_m, \ | |
12892 | current_config->name.gmch_n, \ | |
12893 | current_config->name.link_m, \ | |
12894 | current_config->name.link_n, \ | |
12895 | pipe_config->name.tu, \ | |
12896 | pipe_config->name.gmch_m, \ | |
12897 | pipe_config->name.gmch_n, \ | |
12898 | pipe_config->name.link_m, \ | |
12899 | pipe_config->name.link_n); \ | |
12900 | ret = false; \ | |
12901 | } | |
12902 | ||
55c561a7 DV |
12903 | /* This is required for BDW+ where there is only one set of registers for |
12904 | * switching between high and low RR. | |
12905 | * This macro can be used whenever a comparison has to be made between one | |
12906 | * hw state and multiple sw state variables. | |
12907 | */ | |
cfb23ed6 ML |
12908 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
12909 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12910 | &pipe_config->name, adjust) && \ | |
12911 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12912 | &pipe_config->name, adjust)) { \ | |
12913 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12914 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12915 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12916 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12917 | current_config->name.tu, \ | |
12918 | current_config->name.gmch_m, \ | |
12919 | current_config->name.gmch_n, \ | |
12920 | current_config->name.link_m, \ | |
12921 | current_config->name.link_n, \ | |
12922 | current_config->alt_name.tu, \ | |
12923 | current_config->alt_name.gmch_m, \ | |
12924 | current_config->alt_name.gmch_n, \ | |
12925 | current_config->alt_name.link_m, \ | |
12926 | current_config->alt_name.link_n, \ | |
12927 | pipe_config->name.tu, \ | |
12928 | pipe_config->name.gmch_m, \ | |
12929 | pipe_config->name.gmch_n, \ | |
12930 | pipe_config->name.link_m, \ | |
12931 | pipe_config->name.link_n); \ | |
12932 | ret = false; \ | |
88adfff1 DV |
12933 | } |
12934 | ||
1bd1bd80 DV |
12935 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12936 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12937 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12938 | "(expected %i, found %i)\n", \ |
12939 | current_config->name & (mask), \ | |
12940 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12941 | ret = false; \ |
1bd1bd80 DV |
12942 | } |
12943 | ||
5e550656 VS |
12944 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12945 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12946 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12947 | "(expected %i, found %i)\n", \ |
12948 | current_config->name, \ | |
12949 | pipe_config->name); \ | |
cfb23ed6 | 12950 | ret = false; \ |
5e550656 VS |
12951 | } |
12952 | ||
bb760063 DV |
12953 | #define PIPE_CONF_QUIRK(quirk) \ |
12954 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12955 | ||
eccb140b DV |
12956 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12957 | ||
08a24034 DV |
12958 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12959 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12960 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12961 | |
90a6b7b0 | 12962 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 12963 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be VK |
12964 | |
12965 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12966 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12967 | ||
cfb23ed6 ML |
12968 | if (current_config->has_drrs) |
12969 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12970 | } else | |
12971 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12972 | |
253c84c8 | 12973 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 12974 | |
2d112de7 ACO |
12975 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12976 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12977 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12978 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12979 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12980 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12981 | |
2d112de7 ACO |
12982 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12983 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12984 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12985 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12986 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12987 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12988 | |
c93f54cf | 12989 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12990 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12991 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12992 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12993 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12994 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12995 | |
9ed109a7 DV |
12996 | PIPE_CONF_CHECK_I(has_audio); |
12997 | ||
2d112de7 | 12998 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12999 | DRM_MODE_FLAG_INTERLACE); |
13000 | ||
bb760063 | 13001 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 13002 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13003 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 13004 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13005 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 13006 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13007 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 13008 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
13009 | DRM_MODE_FLAG_NVSYNC); |
13010 | } | |
045ac3b5 | 13011 | |
333b8ca8 | 13012 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
13013 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
13014 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 13015 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 13016 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 13017 | |
bfd16b2a ML |
13018 | if (!adjust) { |
13019 | PIPE_CONF_CHECK_I(pipe_src_w); | |
13020 | PIPE_CONF_CHECK_I(pipe_src_h); | |
13021 | ||
13022 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
13023 | if (current_config->pch_pfit.enabled) { | |
13024 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
13025 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
13026 | } | |
2fa2fe9a | 13027 | |
7aefe2b5 ML |
13028 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
13029 | } | |
a1b2278e | 13030 | |
e59150dc JB |
13031 | /* BDW+ don't expose a synchronous way to read the state */ |
13032 | if (IS_HASWELL(dev)) | |
13033 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 13034 | |
282740f7 VS |
13035 | PIPE_CONF_CHECK_I(double_wide); |
13036 | ||
26804afd DV |
13037 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
13038 | ||
8106ddbd | 13039 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 13040 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 13041 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
13042 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
13043 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 13044 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 13045 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
13046 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
13047 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
13048 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 13049 | |
47eacbab VS |
13050 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
13051 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
13052 | ||
42571aef VS |
13053 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
13054 | PIPE_CONF_CHECK_I(pipe_bpp); | |
13055 | ||
2d112de7 | 13056 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 13057 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 13058 | |
66e985c0 | 13059 | #undef PIPE_CONF_CHECK_X |
08a24034 | 13060 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 13061 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 13062 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 13063 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 13064 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 13065 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 13066 | |
cfb23ed6 | 13067 | return ret; |
0e8ffe1b DV |
13068 | } |
13069 | ||
e3b247da VS |
13070 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
13071 | const struct intel_crtc_state *pipe_config) | |
13072 | { | |
13073 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 13074 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
13075 | &pipe_config->fdi_m_n); |
13076 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
13077 | ||
13078 | /* | |
13079 | * FDI already provided one idea for the dotclock. | |
13080 | * Yell if the encoder disagrees. | |
13081 | */ | |
13082 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
13083 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
13084 | fdi_dotclock, dotclock); | |
13085 | } | |
13086 | } | |
13087 | ||
c0ead703 ML |
13088 | static void verify_wm_state(struct drm_crtc *crtc, |
13089 | struct drm_crtc_state *new_state) | |
08db6652 | 13090 | { |
e7c84544 | 13091 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13092 | struct drm_i915_private *dev_priv = to_i915(dev); |
08db6652 | 13093 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
e7c84544 ML |
13094 | struct skl_ddb_entry *hw_entry, *sw_entry; |
13095 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13096 | const enum pipe pipe = intel_crtc->pipe; | |
08db6652 DL |
13097 | int plane; |
13098 | ||
e7c84544 | 13099 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
13100 | return; |
13101 | ||
13102 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
13103 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
13104 | ||
e7c84544 ML |
13105 | /* planes */ |
13106 | for_each_plane(dev_priv, pipe, plane) { | |
13107 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
13108 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
08db6652 | 13109 | |
e7c84544 | 13110 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
08db6652 DL |
13111 | continue; |
13112 | ||
e7c84544 ML |
13113 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
13114 | "(expected (%u,%u), found (%u,%u))\n", | |
13115 | pipe_name(pipe), plane + 1, | |
13116 | sw_entry->start, sw_entry->end, | |
13117 | hw_entry->start, hw_entry->end); | |
13118 | } | |
08db6652 | 13119 | |
e7c84544 ML |
13120 | /* cursor */ |
13121 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
13122 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 | 13123 | |
e7c84544 | 13124 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
08db6652 DL |
13125 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
13126 | "(expected (%u,%u), found (%u,%u))\n", | |
13127 | pipe_name(pipe), | |
13128 | sw_entry->start, sw_entry->end, | |
13129 | hw_entry->start, hw_entry->end); | |
13130 | } | |
13131 | } | |
13132 | ||
91d1b4bd | 13133 | static void |
c0ead703 | 13134 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 13135 | { |
35dd3c64 | 13136 | struct drm_connector *connector; |
8af6cf88 | 13137 | |
e7c84544 | 13138 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
13139 | struct drm_encoder *encoder = connector->encoder; |
13140 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 13141 | |
e7c84544 ML |
13142 | if (state->crtc != crtc) |
13143 | continue; | |
13144 | ||
5a21b665 | 13145 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 13146 | |
ad3c558f | 13147 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 13148 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 13149 | } |
91d1b4bd DV |
13150 | } |
13151 | ||
13152 | static void | |
c0ead703 | 13153 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
13154 | { |
13155 | struct intel_encoder *encoder; | |
13156 | struct intel_connector *connector; | |
8af6cf88 | 13157 | |
b2784e15 | 13158 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13159 | bool enabled = false; |
4d20cd86 | 13160 | enum pipe pipe; |
8af6cf88 DV |
13161 | |
13162 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13163 | encoder->base.base.id, | |
8e329a03 | 13164 | encoder->base.name); |
8af6cf88 | 13165 | |
3a3371ff | 13166 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13167 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13168 | continue; |
13169 | enabled = true; | |
ad3c558f ML |
13170 | |
13171 | I915_STATE_WARN(connector->base.state->crtc != | |
13172 | encoder->base.crtc, | |
13173 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13174 | } |
0e32b39c | 13175 | |
e2c719b7 | 13176 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13177 | "encoder's enabled state mismatch " |
13178 | "(expected %i, found %i)\n", | |
13179 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13180 | |
13181 | if (!encoder->base.crtc) { | |
4d20cd86 | 13182 | bool active; |
7c60d198 | 13183 | |
4d20cd86 ML |
13184 | active = encoder->get_hw_state(encoder, &pipe); |
13185 | I915_STATE_WARN(active, | |
13186 | "encoder detached but still enabled on pipe %c.\n", | |
13187 | pipe_name(pipe)); | |
7c60d198 | 13188 | } |
8af6cf88 | 13189 | } |
91d1b4bd DV |
13190 | } |
13191 | ||
13192 | static void | |
c0ead703 ML |
13193 | verify_crtc_state(struct drm_crtc *crtc, |
13194 | struct drm_crtc_state *old_crtc_state, | |
13195 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 13196 | { |
e7c84544 | 13197 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13198 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 13199 | struct intel_encoder *encoder; |
e7c84544 ML |
13200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13201 | struct intel_crtc_state *pipe_config, *sw_config; | |
13202 | struct drm_atomic_state *old_state; | |
13203 | bool active; | |
045ac3b5 | 13204 | |
e7c84544 | 13205 | old_state = old_crtc_state->state; |
ec2dc6a0 | 13206 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
13207 | pipe_config = to_intel_crtc_state(old_crtc_state); |
13208 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13209 | pipe_config->base.crtc = crtc; | |
13210 | pipe_config->base.state = old_state; | |
8af6cf88 | 13211 | |
78108b7c | 13212 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 13213 | |
e7c84544 | 13214 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 13215 | |
e7c84544 ML |
13216 | /* hw state is inconsistent with the pipe quirk */ |
13217 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
13218 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13219 | active = new_crtc_state->active; | |
6c49f241 | 13220 | |
e7c84544 ML |
13221 | I915_STATE_WARN(new_crtc_state->active != active, |
13222 | "crtc active state doesn't match with hw state " | |
13223 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 13224 | |
e7c84544 ML |
13225 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
13226 | "transitional active state does not match atomic hw state " | |
13227 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13228 | |
e7c84544 ML |
13229 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13230 | enum pipe pipe; | |
4d20cd86 | 13231 | |
e7c84544 ML |
13232 | active = encoder->get_hw_state(encoder, &pipe); |
13233 | I915_STATE_WARN(active != new_crtc_state->active, | |
13234 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13235 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13236 | |
e7c84544 ML |
13237 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13238 | "Encoder connected to wrong pipe %c\n", | |
13239 | pipe_name(pipe)); | |
4d20cd86 | 13240 | |
253c84c8 VS |
13241 | if (active) { |
13242 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 13243 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 13244 | } |
e7c84544 | 13245 | } |
53d9f4e9 | 13246 | |
e7c84544 ML |
13247 | if (!new_crtc_state->active) |
13248 | return; | |
cfb23ed6 | 13249 | |
e7c84544 | 13250 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13251 | |
e7c84544 ML |
13252 | sw_config = to_intel_crtc_state(crtc->state); |
13253 | if (!intel_pipe_config_compare(dev, sw_config, | |
13254 | pipe_config, false)) { | |
13255 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13256 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13257 | "[hw state]"); | |
13258 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13259 | "[sw state]"); | |
8af6cf88 DV |
13260 | } |
13261 | } | |
13262 | ||
91d1b4bd | 13263 | static void |
c0ead703 ML |
13264 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13265 | struct intel_shared_dpll *pll, | |
13266 | struct drm_crtc *crtc, | |
13267 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13268 | { |
91d1b4bd | 13269 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13270 | unsigned crtc_mask; |
13271 | bool active; | |
5358901f | 13272 | |
e7c84544 | 13273 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13274 | |
e7c84544 | 13275 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13276 | |
e7c84544 | 13277 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13278 | |
e7c84544 ML |
13279 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13280 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13281 | "pll in active use but not on in sw tracking\n"); | |
13282 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13283 | "pll is on but not used by any active crtc\n"); | |
13284 | I915_STATE_WARN(pll->on != active, | |
13285 | "pll on state mismatch (expected %i, found %i)\n", | |
13286 | pll->on, active); | |
13287 | } | |
5358901f | 13288 | |
e7c84544 | 13289 | if (!crtc) { |
2dd66ebd | 13290 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13291 | "more active pll users than references: %x vs %x\n", |
13292 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13293 | |
e7c84544 ML |
13294 | return; |
13295 | } | |
13296 | ||
13297 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13298 | ||
13299 | if (new_state->active) | |
13300 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13301 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13302 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13303 | else | |
13304 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13305 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13306 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13307 | |
e7c84544 ML |
13308 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13309 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13310 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13311 | |
e7c84544 ML |
13312 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13313 | &dpll_hw_state, | |
13314 | sizeof(dpll_hw_state)), | |
13315 | "pll hw state mismatch\n"); | |
13316 | } | |
13317 | ||
13318 | static void | |
c0ead703 ML |
13319 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13320 | struct drm_crtc_state *old_crtc_state, | |
13321 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 13322 | { |
fac5e23e | 13323 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13324 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
13325 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13326 | ||
13327 | if (new_state->shared_dpll) | |
c0ead703 | 13328 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13329 | |
13330 | if (old_state->shared_dpll && | |
13331 | old_state->shared_dpll != new_state->shared_dpll) { | |
13332 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13333 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13334 | ||
13335 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13336 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13337 | pipe_name(drm_crtc_index(crtc))); | |
13338 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13339 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13340 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13341 | } |
8af6cf88 DV |
13342 | } |
13343 | ||
e7c84544 | 13344 | static void |
c0ead703 | 13345 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13346 | struct drm_crtc_state *old_state, |
13347 | struct drm_crtc_state *new_state) | |
13348 | { | |
5a21b665 DV |
13349 | if (!needs_modeset(new_state) && |
13350 | !to_intel_crtc_state(new_state)->update_pipe) | |
13351 | return; | |
13352 | ||
c0ead703 | 13353 | verify_wm_state(crtc, new_state); |
5a21b665 | 13354 | verify_connector_state(crtc->dev, crtc); |
c0ead703 ML |
13355 | verify_crtc_state(crtc, old_state, new_state); |
13356 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13357 | } |
13358 | ||
13359 | static void | |
c0ead703 | 13360 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 13361 | { |
fac5e23e | 13362 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13363 | int i; |
13364 | ||
13365 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13366 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13367 | } |
13368 | ||
13369 | static void | |
c0ead703 | 13370 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13371 | { |
c0ead703 ML |
13372 | verify_encoder_state(dev); |
13373 | verify_connector_state(dev, NULL); | |
13374 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13375 | } |
13376 | ||
80715b2f VS |
13377 | static void update_scanline_offset(struct intel_crtc *crtc) |
13378 | { | |
13379 | struct drm_device *dev = crtc->base.dev; | |
13380 | ||
13381 | /* | |
13382 | * The scanline counter increments at the leading edge of hsync. | |
13383 | * | |
13384 | * On most platforms it starts counting from vtotal-1 on the | |
13385 | * first active line. That means the scanline counter value is | |
13386 | * always one less than what we would expect. Ie. just after | |
13387 | * start of vblank, which also occurs at start of hsync (on the | |
13388 | * last active line), the scanline counter will read vblank_start-1. | |
13389 | * | |
13390 | * On gen2 the scanline counter starts counting from 1 instead | |
13391 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13392 | * to keep the value positive), instead of adding one. | |
13393 | * | |
13394 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13395 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13396 | * there's an extra 1 line difference. So we need to add two instead of | |
13397 | * one to the value. | |
13398 | */ | |
13399 | if (IS_GEN2(dev)) { | |
124abe07 | 13400 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13401 | int vtotal; |
13402 | ||
124abe07 VS |
13403 | vtotal = adjusted_mode->crtc_vtotal; |
13404 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13405 | vtotal /= 2; |
13406 | ||
13407 | crtc->scanline_offset = vtotal - 1; | |
13408 | } else if (HAS_DDI(dev) && | |
2d84d2b3 | 13409 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13410 | crtc->scanline_offset = 2; |
13411 | } else | |
13412 | crtc->scanline_offset = 1; | |
13413 | } | |
13414 | ||
ad421372 | 13415 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13416 | { |
225da59b | 13417 | struct drm_device *dev = state->dev; |
ed6739ef | 13418 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13419 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13420 | struct drm_crtc *crtc; |
13421 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13422 | int i; |
ed6739ef ACO |
13423 | |
13424 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13425 | return; |
ed6739ef | 13426 | |
0a9ab303 | 13427 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13428 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13429 | struct intel_shared_dpll *old_dpll = |
13430 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13431 | |
fb1a38a9 | 13432 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13433 | continue; |
13434 | ||
8106ddbd | 13435 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13436 | |
8106ddbd | 13437 | if (!old_dpll) |
fb1a38a9 | 13438 | continue; |
0a9ab303 | 13439 | |
ad421372 ML |
13440 | if (!shared_dpll) |
13441 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13442 | |
8106ddbd | 13443 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13444 | } |
ed6739ef ACO |
13445 | } |
13446 | ||
99d736a2 ML |
13447 | /* |
13448 | * This implements the workaround described in the "notes" section of the mode | |
13449 | * set sequence documentation. When going from no pipes or single pipe to | |
13450 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13451 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13452 | */ | |
13453 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13454 | { | |
13455 | struct drm_crtc_state *crtc_state; | |
13456 | struct intel_crtc *intel_crtc; | |
13457 | struct drm_crtc *crtc; | |
13458 | struct intel_crtc_state *first_crtc_state = NULL; | |
13459 | struct intel_crtc_state *other_crtc_state = NULL; | |
13460 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13461 | int i; | |
13462 | ||
13463 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13464 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13465 | intel_crtc = to_intel_crtc(crtc); | |
13466 | ||
13467 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13468 | continue; | |
13469 | ||
13470 | if (first_crtc_state) { | |
13471 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13472 | break; | |
13473 | } else { | |
13474 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13475 | first_pipe = intel_crtc->pipe; | |
13476 | } | |
13477 | } | |
13478 | ||
13479 | /* No workaround needed? */ | |
13480 | if (!first_crtc_state) | |
13481 | return 0; | |
13482 | ||
13483 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13484 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13485 | struct intel_crtc_state *pipe_config; | |
13486 | ||
13487 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13488 | if (IS_ERR(pipe_config)) | |
13489 | return PTR_ERR(pipe_config); | |
13490 | ||
13491 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13492 | ||
13493 | if (!pipe_config->base.active || | |
13494 | needs_modeset(&pipe_config->base)) | |
13495 | continue; | |
13496 | ||
13497 | /* 2 or more enabled crtcs means no need for w/a */ | |
13498 | if (enabled_pipe != INVALID_PIPE) | |
13499 | return 0; | |
13500 | ||
13501 | enabled_pipe = intel_crtc->pipe; | |
13502 | } | |
13503 | ||
13504 | if (enabled_pipe != INVALID_PIPE) | |
13505 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13506 | else if (other_crtc_state) | |
13507 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13508 | ||
13509 | return 0; | |
13510 | } | |
13511 | ||
27c329ed ML |
13512 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13513 | { | |
13514 | struct drm_crtc *crtc; | |
13515 | struct drm_crtc_state *crtc_state; | |
13516 | int ret = 0; | |
13517 | ||
13518 | /* add all active pipes to the state */ | |
13519 | for_each_crtc(state->dev, crtc) { | |
13520 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13521 | if (IS_ERR(crtc_state)) | |
13522 | return PTR_ERR(crtc_state); | |
13523 | ||
13524 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13525 | continue; | |
13526 | ||
13527 | crtc_state->mode_changed = true; | |
13528 | ||
13529 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13530 | if (ret) | |
13531 | break; | |
13532 | ||
13533 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13534 | if (ret) | |
13535 | break; | |
13536 | } | |
13537 | ||
13538 | return ret; | |
13539 | } | |
13540 | ||
c347a676 | 13541 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13542 | { |
565602d7 | 13543 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13544 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
13545 | struct drm_crtc *crtc; |
13546 | struct drm_crtc_state *crtc_state; | |
13547 | int ret = 0, i; | |
054518dd | 13548 | |
b359283a ML |
13549 | if (!check_digital_port_conflicts(state)) { |
13550 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13551 | return -EINVAL; | |
13552 | } | |
13553 | ||
565602d7 ML |
13554 | intel_state->modeset = true; |
13555 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13556 | ||
13557 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13558 | if (crtc_state->active) | |
13559 | intel_state->active_crtcs |= 1 << i; | |
13560 | else | |
13561 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13562 | |
13563 | if (crtc_state->active != crtc->state->active) | |
13564 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13565 | } |
13566 | ||
054518dd ACO |
13567 | /* |
13568 | * See if the config requires any additional preparation, e.g. | |
13569 | * to adjust global state with pipes off. We need to do this | |
13570 | * here so we can get the modeset_pipe updated config for the new | |
13571 | * mode set on this crtc. For other crtcs we need to use the | |
13572 | * adjusted_mode bits in the crtc directly. | |
13573 | */ | |
27c329ed | 13574 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 13575 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 13576 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
13577 | if (!intel_state->cdclk_pll_vco) |
13578 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 13579 | |
27c329ed | 13580 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
13581 | if (ret < 0) |
13582 | return ret; | |
27c329ed | 13583 | |
c89e39f3 | 13584 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13585 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) |
27c329ed ML |
13586 | ret = intel_modeset_all_pipes(state); |
13587 | ||
13588 | if (ret < 0) | |
054518dd | 13589 | return ret; |
e8788cbc ML |
13590 | |
13591 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13592 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13593 | } else |
1a617b77 | 13594 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13595 | |
ad421372 | 13596 | intel_modeset_clear_plls(state); |
054518dd | 13597 | |
565602d7 | 13598 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13599 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13600 | |
ad421372 | 13601 | return 0; |
c347a676 ACO |
13602 | } |
13603 | ||
aa363136 MR |
13604 | /* |
13605 | * Handle calculation of various watermark data at the end of the atomic check | |
13606 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13607 | * handlers to ensure that all derived state has been updated. | |
13608 | */ | |
55994c2c | 13609 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
13610 | { |
13611 | struct drm_device *dev = state->dev; | |
98d39494 | 13612 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
13613 | |
13614 | /* Is there platform-specific watermark information to calculate? */ | |
13615 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
13616 | return dev_priv->display.compute_global_watermarks(state); |
13617 | ||
13618 | return 0; | |
aa363136 MR |
13619 | } |
13620 | ||
74c090b1 ML |
13621 | /** |
13622 | * intel_atomic_check - validate state object | |
13623 | * @dev: drm device | |
13624 | * @state: state to validate | |
13625 | */ | |
13626 | static int intel_atomic_check(struct drm_device *dev, | |
13627 | struct drm_atomic_state *state) | |
c347a676 | 13628 | { |
dd8b3bdb | 13629 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13630 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13631 | struct drm_crtc *crtc; |
13632 | struct drm_crtc_state *crtc_state; | |
13633 | int ret, i; | |
61333b60 | 13634 | bool any_ms = false; |
c347a676 | 13635 | |
74c090b1 | 13636 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13637 | if (ret) |
13638 | return ret; | |
13639 | ||
c347a676 | 13640 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13641 | struct intel_crtc_state *pipe_config = |
13642 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13643 | |
13644 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13645 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13646 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13647 | |
af4a879e | 13648 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
13649 | continue; |
13650 | ||
af4a879e DV |
13651 | if (!crtc_state->enable) { |
13652 | any_ms = true; | |
cfb23ed6 | 13653 | continue; |
af4a879e | 13654 | } |
cfb23ed6 | 13655 | |
26495481 DV |
13656 | /* FIXME: For only active_changed we shouldn't need to do any |
13657 | * state recomputation at all. */ | |
13658 | ||
1ed51de9 DV |
13659 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13660 | if (ret) | |
13661 | return ret; | |
b359283a | 13662 | |
cfb23ed6 | 13663 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
13664 | if (ret) { |
13665 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
13666 | pipe_config, "[failed]"); | |
c347a676 | 13667 | return ret; |
25aa1c39 | 13668 | } |
c347a676 | 13669 | |
73831236 | 13670 | if (i915.fastboot && |
dd8b3bdb | 13671 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13672 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13673 | pipe_config, true)) { |
26495481 | 13674 | crtc_state->mode_changed = false; |
bfd16b2a | 13675 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13676 | } |
13677 | ||
af4a879e | 13678 | if (needs_modeset(crtc_state)) |
26495481 | 13679 | any_ms = true; |
cfb23ed6 | 13680 | |
af4a879e DV |
13681 | ret = drm_atomic_add_affected_planes(state, crtc); |
13682 | if (ret) | |
13683 | return ret; | |
61333b60 | 13684 | |
26495481 DV |
13685 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13686 | needs_modeset(crtc_state) ? | |
13687 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13688 | } |
13689 | ||
61333b60 ML |
13690 | if (any_ms) { |
13691 | ret = intel_modeset_checks(state); | |
13692 | ||
13693 | if (ret) | |
13694 | return ret; | |
27c329ed | 13695 | } else |
dd8b3bdb | 13696 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13697 | |
dd8b3bdb | 13698 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13699 | if (ret) |
13700 | return ret; | |
13701 | ||
f51be2e0 | 13702 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 13703 | return calc_watermark_data(state); |
054518dd ACO |
13704 | } |
13705 | ||
5008e874 ML |
13706 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13707 | struct drm_atomic_state *state, | |
81072bfd | 13708 | bool nonblock) |
5008e874 | 13709 | { |
fac5e23e | 13710 | struct drm_i915_private *dev_priv = to_i915(dev); |
7580d774 | 13711 | struct drm_plane_state *plane_state; |
5008e874 | 13712 | struct drm_crtc_state *crtc_state; |
7580d774 | 13713 | struct drm_plane *plane; |
5008e874 ML |
13714 | struct drm_crtc *crtc; |
13715 | int i, ret; | |
13716 | ||
5a21b665 DV |
13717 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13718 | if (state->legacy_cursor_update) | |
a6747b73 ML |
13719 | continue; |
13720 | ||
5a21b665 DV |
13721 | ret = intel_crtc_wait_for_pending_flips(crtc); |
13722 | if (ret) | |
13723 | return ret; | |
5008e874 | 13724 | |
5a21b665 DV |
13725 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
13726 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
13727 | } |
13728 | ||
f935675f ML |
13729 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13730 | if (ret) | |
13731 | return ret; | |
13732 | ||
5008e874 | 13733 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 13734 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 13735 | |
21daaeee | 13736 | if (!ret && !nonblock) { |
7580d774 ML |
13737 | for_each_plane_in_state(state, plane, plane_state, i) { |
13738 | struct intel_plane_state *intel_plane_state = | |
13739 | to_intel_plane_state(plane_state); | |
13740 | ||
13741 | if (!intel_plane_state->wait_req) | |
13742 | continue; | |
13743 | ||
776f3236 CW |
13744 | ret = i915_wait_request(intel_plane_state->wait_req, |
13745 | true, NULL, NULL); | |
f7e5838b | 13746 | if (ret) { |
f4457ae7 CW |
13747 | /* Any hang should be swallowed by the wait */ |
13748 | WARN_ON(ret == -EIO); | |
f7e5838b CW |
13749 | mutex_lock(&dev->struct_mutex); |
13750 | drm_atomic_helper_cleanup_planes(dev, state); | |
13751 | mutex_unlock(&dev->struct_mutex); | |
7580d774 | 13752 | break; |
f7e5838b | 13753 | } |
7580d774 | 13754 | } |
7580d774 | 13755 | } |
5008e874 ML |
13756 | |
13757 | return ret; | |
13758 | } | |
13759 | ||
a2991414 ML |
13760 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
13761 | { | |
13762 | struct drm_device *dev = crtc->base.dev; | |
13763 | ||
13764 | if (!dev->max_vblank_count) | |
13765 | return drm_accurate_vblank_count(&crtc->base); | |
13766 | ||
13767 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
13768 | } | |
13769 | ||
5a21b665 DV |
13770 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13771 | struct drm_i915_private *dev_priv, | |
13772 | unsigned crtc_mask) | |
e8861675 | 13773 | { |
5a21b665 DV |
13774 | unsigned last_vblank_count[I915_MAX_PIPES]; |
13775 | enum pipe pipe; | |
13776 | int ret; | |
e8861675 | 13777 | |
5a21b665 DV |
13778 | if (!crtc_mask) |
13779 | return; | |
e8861675 | 13780 | |
5a21b665 DV |
13781 | for_each_pipe(dev_priv, pipe) { |
13782 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
e8861675 | 13783 | |
5a21b665 | 13784 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
13785 | continue; |
13786 | ||
5a21b665 DV |
13787 | ret = drm_crtc_vblank_get(crtc); |
13788 | if (WARN_ON(ret != 0)) { | |
13789 | crtc_mask &= ~(1 << pipe); | |
13790 | continue; | |
e8861675 ML |
13791 | } |
13792 | ||
5a21b665 | 13793 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); |
e8861675 ML |
13794 | } |
13795 | ||
5a21b665 DV |
13796 | for_each_pipe(dev_priv, pipe) { |
13797 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13798 | long lret; | |
e8861675 | 13799 | |
5a21b665 DV |
13800 | if (!((1 << pipe) & crtc_mask)) |
13801 | continue; | |
d55dbd06 | 13802 | |
5a21b665 DV |
13803 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
13804 | last_vblank_count[pipe] != | |
13805 | drm_crtc_vblank_count(crtc), | |
13806 | msecs_to_jiffies(50)); | |
d55dbd06 | 13807 | |
5a21b665 | 13808 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 13809 | |
5a21b665 | 13810 | drm_crtc_vblank_put(crtc); |
d55dbd06 ML |
13811 | } |
13812 | } | |
13813 | ||
5a21b665 | 13814 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 13815 | { |
5a21b665 DV |
13816 | /* fb updated, need to unpin old fb */ |
13817 | if (crtc_state->fb_changed) | |
13818 | return true; | |
a6747b73 | 13819 | |
5a21b665 DV |
13820 | /* wm changes, need vblank before final wm's */ |
13821 | if (crtc_state->update_wm_post) | |
13822 | return true; | |
a6747b73 | 13823 | |
5a21b665 DV |
13824 | /* |
13825 | * cxsr is re-enabled after vblank. | |
13826 | * This is already handled by crtc_state->update_wm_post, | |
13827 | * but added for clarity. | |
13828 | */ | |
13829 | if (crtc_state->disable_cxsr) | |
13830 | return true; | |
a6747b73 | 13831 | |
5a21b665 | 13832 | return false; |
e8861675 ML |
13833 | } |
13834 | ||
94f05024 | 13835 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 13836 | { |
94f05024 | 13837 | struct drm_device *dev = state->dev; |
565602d7 | 13838 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13839 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 13840 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13841 | struct drm_crtc *crtc; |
5a21b665 | 13842 | struct intel_crtc_state *intel_cstate; |
94f05024 DV |
13843 | struct drm_plane *plane; |
13844 | struct drm_plane_state *plane_state; | |
5a21b665 DV |
13845 | bool hw_check = intel_state->modeset; |
13846 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
13847 | unsigned crtc_vblank_mask = 0; | |
94f05024 | 13848 | int i, ret; |
a6778b3c | 13849 | |
94f05024 DV |
13850 | for_each_plane_in_state(state, plane, plane_state, i) { |
13851 | struct intel_plane_state *intel_plane_state = | |
13852 | to_intel_plane_state(plane_state); | |
ea0000f0 | 13853 | |
94f05024 DV |
13854 | if (!intel_plane_state->wait_req) |
13855 | continue; | |
d4afb8cc | 13856 | |
776f3236 CW |
13857 | ret = i915_wait_request(intel_plane_state->wait_req, |
13858 | true, NULL, NULL); | |
94f05024 DV |
13859 | /* EIO should be eaten, and we can't get interrupted in the |
13860 | * worker, and blocking commits have waited already. */ | |
13861 | WARN_ON(ret); | |
13862 | } | |
1c5e19f8 | 13863 | |
ea0000f0 DV |
13864 | drm_atomic_helper_wait_for_dependencies(state); |
13865 | ||
565602d7 ML |
13866 | if (intel_state->modeset) { |
13867 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13868 | sizeof(intel_state->min_pixclk)); | |
13869 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13870 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
5a21b665 DV |
13871 | |
13872 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13873 | } |
13874 | ||
29ceb0e6 | 13875 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13876 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13877 | ||
5a21b665 DV |
13878 | if (needs_modeset(crtc->state) || |
13879 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13880 | hw_check = true; | |
13881 | ||
13882 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13883 | modeset_get_crtc_power_domains(crtc, | |
13884 | to_intel_crtc_state(crtc->state)); | |
13885 | } | |
13886 | ||
61333b60 ML |
13887 | if (!needs_modeset(crtc->state)) |
13888 | continue; | |
13889 | ||
29ceb0e6 | 13890 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13891 | |
29ceb0e6 VS |
13892 | if (old_crtc_state->active) { |
13893 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13894 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13895 | intel_crtc->active = false; |
58f9c0bc | 13896 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13897 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13898 | |
13899 | /* | |
13900 | * Underruns don't always raise | |
13901 | * interrupts, so check manually. | |
13902 | */ | |
13903 | intel_check_cpu_fifo_underruns(dev_priv); | |
13904 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13905 | |
13906 | if (!crtc->state->active) | |
13907 | intel_update_watermarks(crtc); | |
a539205a | 13908 | } |
b8cecdf5 | 13909 | } |
7758a113 | 13910 | |
ea9d758d DV |
13911 | /* Only after disabling all output pipelines that will be changed can we |
13912 | * update the the output configuration. */ | |
4740b0f2 | 13913 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13914 | |
565602d7 | 13915 | if (intel_state->modeset) { |
4740b0f2 | 13916 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13917 | |
13918 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 13919 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13920 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 13921 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 13922 | |
c0ead703 | 13923 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 13924 | } |
47fab737 | 13925 | |
a6778b3c | 13926 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13927 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13928 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13929 | bool modeset = needs_modeset(crtc->state); | |
5a21b665 DV |
13930 | struct intel_crtc_state *pipe_config = |
13931 | to_intel_crtc_state(crtc->state); | |
9f836f90 | 13932 | |
f6ac4b2a | 13933 | if (modeset && crtc->state->active) { |
a539205a ML |
13934 | update_scanline_offset(to_intel_crtc(crtc)); |
13935 | dev_priv->display.crtc_enable(crtc); | |
13936 | } | |
80715b2f | 13937 | |
1f7528c4 DV |
13938 | /* Complete events for now disable pipes here. */ |
13939 | if (modeset && !crtc->state->active && crtc->state->event) { | |
13940 | spin_lock_irq(&dev->event_lock); | |
13941 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
13942 | spin_unlock_irq(&dev->event_lock); | |
13943 | ||
13944 | crtc->state->event = NULL; | |
13945 | } | |
13946 | ||
f6ac4b2a | 13947 | if (!modeset) |
29ceb0e6 | 13948 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13949 | |
5a21b665 DV |
13950 | if (crtc->state->active && |
13951 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
faf68d92 | 13952 | intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state)); |
5a21b665 | 13953 | |
1f7528c4 | 13954 | if (crtc->state->active) |
5a21b665 | 13955 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
f6d1973d | 13956 | |
5a21b665 DV |
13957 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13958 | crtc_vblank_mask |= 1 << i; | |
177246a8 MR |
13959 | } |
13960 | ||
94f05024 DV |
13961 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
13962 | * already, but still need the state for the delayed optimization. To | |
13963 | * fix this: | |
13964 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
13965 | * - schedule that vblank worker _before_ calling hw_done | |
13966 | * - at the start of commit_tail, cancel it _synchrously | |
13967 | * - switch over to the vblank wait helper in the core after that since | |
13968 | * we don't need out special handling any more. | |
13969 | */ | |
5a21b665 DV |
13970 | if (!state->legacy_cursor_update) |
13971 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
13972 | ||
13973 | /* | |
13974 | * Now that the vblank has passed, we can go ahead and program the | |
13975 | * optimal watermarks on platforms that need two-step watermark | |
13976 | * programming. | |
13977 | * | |
13978 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13979 | */ | |
13980 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13981 | intel_cstate = to_intel_crtc_state(crtc->state); | |
13982 | ||
13983 | if (dev_priv->display.optimize_watermarks) | |
13984 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13985 | } | |
13986 | ||
13987 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13988 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13989 | ||
13990 | if (put_domains[i]) | |
13991 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13992 | ||
13993 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); | |
13994 | } | |
13995 | ||
94f05024 DV |
13996 | drm_atomic_helper_commit_hw_done(state); |
13997 | ||
5a21b665 DV |
13998 | if (intel_state->modeset) |
13999 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
14000 | ||
14001 | mutex_lock(&dev->struct_mutex); | |
14002 | drm_atomic_helper_cleanup_planes(dev, state); | |
14003 | mutex_unlock(&dev->struct_mutex); | |
14004 | ||
ea0000f0 DV |
14005 | drm_atomic_helper_commit_cleanup_done(state); |
14006 | ||
ee165b1a | 14007 | drm_atomic_state_free(state); |
f30da187 | 14008 | |
75714940 MK |
14009 | /* As one of the primary mmio accessors, KMS has a high likelihood |
14010 | * of triggering bugs in unclaimed access. After we finish | |
14011 | * modesetting, see if an error has been flagged, and if so | |
14012 | * enable debugging for the next modeset - and hope we catch | |
14013 | * the culprit. | |
14014 | * | |
14015 | * XXX note that we assume display power is on at this point. | |
14016 | * This might hold true now but we need to add pm helper to check | |
14017 | * unclaimed only when the hardware is on, as atomic commits | |
14018 | * can happen also when the device is completely off. | |
14019 | */ | |
14020 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
14021 | } |
14022 | ||
14023 | static void intel_atomic_commit_work(struct work_struct *work) | |
14024 | { | |
14025 | struct drm_atomic_state *state = container_of(work, | |
14026 | struct drm_atomic_state, | |
14027 | commit_work); | |
14028 | intel_atomic_commit_tail(state); | |
14029 | } | |
14030 | ||
6c9c1b38 DV |
14031 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
14032 | { | |
14033 | struct drm_plane_state *old_plane_state; | |
14034 | struct drm_plane *plane; | |
6c9c1b38 DV |
14035 | int i; |
14036 | ||
faf5bf0a CW |
14037 | for_each_plane_in_state(state, plane, old_plane_state, i) |
14038 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
14039 | intel_fb_obj(plane->state->fb), | |
14040 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
14041 | } |
14042 | ||
94f05024 DV |
14043 | /** |
14044 | * intel_atomic_commit - commit validated state object | |
14045 | * @dev: DRM device | |
14046 | * @state: the top-level driver state object | |
14047 | * @nonblock: nonblocking commit | |
14048 | * | |
14049 | * This function commits a top-level state object that has been validated | |
14050 | * with drm_atomic_helper_check(). | |
14051 | * | |
14052 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
14053 | * nonblocking commits are only safe for pure plane updates. Everything else | |
14054 | * should work though. | |
14055 | * | |
14056 | * RETURNS | |
14057 | * Zero for success or -errno. | |
14058 | */ | |
14059 | static int intel_atomic_commit(struct drm_device *dev, | |
14060 | struct drm_atomic_state *state, | |
14061 | bool nonblock) | |
14062 | { | |
14063 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 14064 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
14065 | int ret = 0; |
14066 | ||
14067 | if (intel_state->modeset && nonblock) { | |
14068 | DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n"); | |
14069 | return -EINVAL; | |
14070 | } | |
14071 | ||
14072 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
14073 | if (ret) | |
14074 | return ret; | |
14075 | ||
14076 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); | |
14077 | ||
14078 | ret = intel_atomic_prepare_commit(dev, state, nonblock); | |
14079 | if (ret) { | |
14080 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
14081 | return ret; | |
14082 | } | |
14083 | ||
14084 | drm_atomic_helper_swap_state(state, true); | |
14085 | dev_priv->wm.distrust_bios_wm = false; | |
14086 | dev_priv->wm.skl_results = intel_state->wm_results; | |
14087 | intel_shared_dpll_commit(state); | |
6c9c1b38 | 14088 | intel_atomic_track_fbs(state); |
94f05024 DV |
14089 | |
14090 | if (nonblock) | |
14091 | queue_work(system_unbound_wq, &state->commit_work); | |
14092 | else | |
14093 | intel_atomic_commit_tail(state); | |
75714940 | 14094 | |
74c090b1 | 14095 | return 0; |
7f27126e JB |
14096 | } |
14097 | ||
c0c36b94 CW |
14098 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
14099 | { | |
83a57153 ACO |
14100 | struct drm_device *dev = crtc->dev; |
14101 | struct drm_atomic_state *state; | |
e694eb02 | 14102 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 14103 | int ret; |
83a57153 ACO |
14104 | |
14105 | state = drm_atomic_state_alloc(dev); | |
14106 | if (!state) { | |
78108b7c VS |
14107 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
14108 | crtc->base.id, crtc->name); | |
83a57153 ACO |
14109 | return; |
14110 | } | |
14111 | ||
e694eb02 | 14112 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 14113 | |
e694eb02 ML |
14114 | retry: |
14115 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
14116 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
14117 | if (!ret) { | |
14118 | if (!crtc_state->active) | |
14119 | goto out; | |
83a57153 | 14120 | |
e694eb02 | 14121 | crtc_state->mode_changed = true; |
74c090b1 | 14122 | ret = drm_atomic_commit(state); |
83a57153 ACO |
14123 | } |
14124 | ||
e694eb02 ML |
14125 | if (ret == -EDEADLK) { |
14126 | drm_atomic_state_clear(state); | |
14127 | drm_modeset_backoff(state->acquire_ctx); | |
14128 | goto retry; | |
4ed9fb37 | 14129 | } |
4be07317 | 14130 | |
2bfb4627 | 14131 | if (ret) |
e694eb02 | 14132 | out: |
2bfb4627 | 14133 | drm_atomic_state_free(state); |
c0c36b94 CW |
14134 | } |
14135 | ||
25c5b266 DV |
14136 | #undef for_each_intel_crtc_masked |
14137 | ||
a8784875 BP |
14138 | /* |
14139 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
14140 | * drm_atomic_helper_legacy_gamma_set() directly. | |
14141 | */ | |
14142 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
14143 | u16 *red, u16 *green, u16 *blue, | |
14144 | uint32_t size) | |
14145 | { | |
14146 | struct drm_device *dev = crtc->dev; | |
14147 | struct drm_mode_config *config = &dev->mode_config; | |
14148 | struct drm_crtc_state *state; | |
14149 | int ret; | |
14150 | ||
14151 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
14152 | if (ret) | |
14153 | return ret; | |
14154 | ||
14155 | /* | |
14156 | * Make sure we update the legacy properties so this works when | |
14157 | * atomic is not enabled. | |
14158 | */ | |
14159 | ||
14160 | state = crtc->state; | |
14161 | ||
14162 | drm_object_property_set_value(&crtc->base, | |
14163 | config->degamma_lut_property, | |
14164 | (state->degamma_lut) ? | |
14165 | state->degamma_lut->base.id : 0); | |
14166 | ||
14167 | drm_object_property_set_value(&crtc->base, | |
14168 | config->ctm_property, | |
14169 | (state->ctm) ? | |
14170 | state->ctm->base.id : 0); | |
14171 | ||
14172 | drm_object_property_set_value(&crtc->base, | |
14173 | config->gamma_lut_property, | |
14174 | (state->gamma_lut) ? | |
14175 | state->gamma_lut->base.id : 0); | |
14176 | ||
14177 | return 0; | |
14178 | } | |
14179 | ||
f6e5b160 | 14180 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 14181 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 14182 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 14183 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 14184 | .destroy = intel_crtc_destroy, |
527b6abe | 14185 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
14186 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
14187 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
14188 | }; |
14189 | ||
6beb8c23 MR |
14190 | /** |
14191 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
14192 | * @plane: drm plane to prepare for | |
14193 | * @fb: framebuffer to prepare for presentation | |
14194 | * | |
14195 | * Prepares a framebuffer for usage on a display plane. Generally this | |
14196 | * involves pinning the underlying object and updating the frontbuffer tracking | |
14197 | * bits. Some older platforms need special physical address handling for | |
14198 | * cursor planes. | |
14199 | * | |
f935675f ML |
14200 | * Must be called with struct_mutex held. |
14201 | * | |
6beb8c23 MR |
14202 | * Returns 0 on success, negative error code on failure. |
14203 | */ | |
14204 | int | |
14205 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 14206 | const struct drm_plane_state *new_state) |
465c120c MR |
14207 | { |
14208 | struct drm_device *dev = plane->dev; | |
844f9111 | 14209 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 14210 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14211 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c37efb99 | 14212 | struct reservation_object *resv; |
6beb8c23 | 14213 | int ret = 0; |
465c120c | 14214 | |
1ee49399 | 14215 | if (!obj && !old_obj) |
465c120c MR |
14216 | return 0; |
14217 | ||
5008e874 ML |
14218 | if (old_obj) { |
14219 | struct drm_crtc_state *crtc_state = | |
14220 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
14221 | ||
14222 | /* Big Hammer, we also need to ensure that any pending | |
14223 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14224 | * current scanout is retired before unpinning the old | |
14225 | * framebuffer. Note that we rely on userspace rendering | |
14226 | * into the buffer attached to the pipe they are waiting | |
14227 | * on. If not, userspace generates a GPU hang with IPEHR | |
14228 | * point to the MI_WAIT_FOR_EVENT. | |
14229 | * | |
14230 | * This should only fail upon a hung GPU, in which case we | |
14231 | * can safely continue. | |
14232 | */ | |
14233 | if (needs_modeset(crtc_state)) | |
14234 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
f4457ae7 CW |
14235 | if (ret) { |
14236 | /* GPU hangs should have been swallowed by the wait */ | |
14237 | WARN_ON(ret == -EIO); | |
f935675f | 14238 | return ret; |
f4457ae7 | 14239 | } |
5008e874 ML |
14240 | } |
14241 | ||
c37efb99 CW |
14242 | if (!obj) |
14243 | return 0; | |
14244 | ||
5a21b665 | 14245 | /* For framebuffer backed by dmabuf, wait for fence */ |
c37efb99 CW |
14246 | resv = i915_gem_object_get_dmabuf_resv(obj); |
14247 | if (resv) { | |
5a21b665 DV |
14248 | long lret; |
14249 | ||
c37efb99 | 14250 | lret = reservation_object_wait_timeout_rcu(resv, false, true, |
5a21b665 DV |
14251 | MAX_SCHEDULE_TIMEOUT); |
14252 | if (lret == -ERESTARTSYS) | |
14253 | return lret; | |
14254 | ||
14255 | WARN(lret < 0, "waiting returns %li\n", lret); | |
14256 | } | |
14257 | ||
c37efb99 | 14258 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
6beb8c23 MR |
14259 | INTEL_INFO(dev)->cursor_needs_physical) { |
14260 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
14261 | ret = i915_gem_object_attach_phys(obj, align); | |
14262 | if (ret) | |
14263 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
14264 | } else { | |
3465c580 | 14265 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 14266 | } |
465c120c | 14267 | |
c37efb99 | 14268 | if (ret == 0) { |
27c01aae | 14269 | to_intel_plane_state(new_state)->wait_req = |
d72d908b CW |
14270 | i915_gem_active_get(&obj->last_write, |
14271 | &obj->base.dev->struct_mutex); | |
7580d774 | 14272 | } |
fdd508a6 | 14273 | |
6beb8c23 MR |
14274 | return ret; |
14275 | } | |
14276 | ||
38f3ce3a MR |
14277 | /** |
14278 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14279 | * @plane: drm plane to clean up for | |
14280 | * @fb: old framebuffer that was on plane | |
14281 | * | |
14282 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14283 | * |
14284 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14285 | */ |
14286 | void | |
14287 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 14288 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
14289 | { |
14290 | struct drm_device *dev = plane->dev; | |
7580d774 | 14291 | struct intel_plane_state *old_intel_state; |
84978257 | 14292 | struct intel_plane_state *intel_state = to_intel_plane_state(plane->state); |
1ee49399 ML |
14293 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14294 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14295 | |
7580d774 ML |
14296 | old_intel_state = to_intel_plane_state(old_state); |
14297 | ||
1ee49399 | 14298 | if (!obj && !old_obj) |
38f3ce3a MR |
14299 | return; |
14300 | ||
1ee49399 ML |
14301 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
14302 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 14303 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 | 14304 | |
84978257 | 14305 | i915_gem_request_assign(&intel_state->wait_req, NULL); |
7580d774 | 14306 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); |
465c120c MR |
14307 | } |
14308 | ||
6156a456 CK |
14309 | int |
14310 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14311 | { | |
14312 | int max_scale; | |
6156a456 CK |
14313 | int crtc_clock, cdclk; |
14314 | ||
bf8a0af0 | 14315 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14316 | return DRM_PLANE_HELPER_NO_SCALING; |
14317 | ||
6156a456 | 14318 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
27c329ed | 14319 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14320 | |
54bf1ce6 | 14321 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14322 | return DRM_PLANE_HELPER_NO_SCALING; |
14323 | ||
14324 | /* | |
14325 | * skl max scale is lower of: | |
14326 | * close to 3 but not 3, -1 is for that purpose | |
14327 | * or | |
14328 | * cdclk/crtc_clock | |
14329 | */ | |
14330 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14331 | ||
14332 | return max_scale; | |
14333 | } | |
14334 | ||
465c120c | 14335 | static int |
3c692a41 | 14336 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14337 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14338 | struct intel_plane_state *state) |
14339 | { | |
2b875c22 MR |
14340 | struct drm_crtc *crtc = state->base.crtc; |
14341 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 14342 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14343 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14344 | bool can_position = false; | |
465c120c | 14345 | |
693bdc28 VS |
14346 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
14347 | /* use scaler when colorkey is not required */ | |
14348 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14349 | min_scale = 1; | |
14350 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14351 | } | |
d8106366 | 14352 | can_position = true; |
6156a456 | 14353 | } |
d8106366 | 14354 | |
061e4b8d ML |
14355 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14356 | &state->dst, &state->clip, | |
9b8b013d | 14357 | state->base.rotation, |
da20eabd ML |
14358 | min_scale, max_scale, |
14359 | can_position, true, | |
14360 | &state->visible); | |
14af293f GP |
14361 | } |
14362 | ||
5a21b665 DV |
14363 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14364 | struct drm_crtc_state *old_crtc_state) | |
14365 | { | |
14366 | struct drm_device *dev = crtc->dev; | |
14367 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14368 | struct intel_crtc_state *old_intel_state = | |
14369 | to_intel_crtc_state(old_crtc_state); | |
14370 | bool modeset = needs_modeset(crtc->state); | |
14371 | ||
14372 | /* Perform vblank evasion around commit operation */ | |
14373 | intel_pipe_update_start(intel_crtc); | |
14374 | ||
14375 | if (modeset) | |
14376 | return; | |
14377 | ||
14378 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14379 | intel_color_set_csc(crtc->state); | |
14380 | intel_color_load_luts(crtc->state); | |
14381 | } | |
14382 | ||
14383 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14384 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14385 | else if (INTEL_INFO(dev)->gen >= 9) | |
14386 | skl_detach_scalers(intel_crtc); | |
14387 | } | |
14388 | ||
14389 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
14390 | struct drm_crtc_state *old_crtc_state) | |
14391 | { | |
14392 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14393 | ||
14394 | intel_pipe_update_end(intel_crtc, NULL); | |
14395 | } | |
14396 | ||
cf4c7c12 | 14397 | /** |
4a3b8769 MR |
14398 | * intel_plane_destroy - destroy a plane |
14399 | * @plane: plane to destroy | |
cf4c7c12 | 14400 | * |
4a3b8769 MR |
14401 | * Common destruction function for all types of planes (primary, cursor, |
14402 | * sprite). | |
cf4c7c12 | 14403 | */ |
4a3b8769 | 14404 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 14405 | { |
69ae561f VS |
14406 | if (!plane) |
14407 | return; | |
14408 | ||
465c120c | 14409 | drm_plane_cleanup(plane); |
69ae561f | 14410 | kfree(to_intel_plane(plane)); |
465c120c MR |
14411 | } |
14412 | ||
65a3fea0 | 14413 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14414 | .update_plane = drm_atomic_helper_update_plane, |
14415 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14416 | .destroy = intel_plane_destroy, |
c196e1d6 | 14417 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14418 | .atomic_get_property = intel_plane_atomic_get_property, |
14419 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14420 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14421 | .atomic_destroy_state = intel_plane_destroy_state, | |
14422 | ||
465c120c MR |
14423 | }; |
14424 | ||
14425 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14426 | int pipe) | |
14427 | { | |
fca0ce2a VS |
14428 | struct intel_plane *primary = NULL; |
14429 | struct intel_plane_state *state = NULL; | |
465c120c | 14430 | const uint32_t *intel_primary_formats; |
45e3743a | 14431 | unsigned int num_formats; |
fca0ce2a | 14432 | int ret; |
465c120c MR |
14433 | |
14434 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
fca0ce2a VS |
14435 | if (!primary) |
14436 | goto fail; | |
465c120c | 14437 | |
8e7d688b | 14438 | state = intel_create_plane_state(&primary->base); |
fca0ce2a VS |
14439 | if (!state) |
14440 | goto fail; | |
8e7d688b | 14441 | primary->base.state = &state->base; |
ea2c67bb | 14442 | |
465c120c MR |
14443 | primary->can_scale = false; |
14444 | primary->max_downscale = 1; | |
6156a456 CK |
14445 | if (INTEL_INFO(dev)->gen >= 9) { |
14446 | primary->can_scale = true; | |
af99ceda | 14447 | state->scaler_id = -1; |
6156a456 | 14448 | } |
465c120c MR |
14449 | primary->pipe = pipe; |
14450 | primary->plane = pipe; | |
a9ff8714 | 14451 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14452 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14453 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14454 | primary->plane = !pipe; | |
14455 | ||
6c0fd451 DL |
14456 | if (INTEL_INFO(dev)->gen >= 9) { |
14457 | intel_primary_formats = skl_primary_formats; | |
14458 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14459 | |
14460 | primary->update_plane = skylake_update_primary_plane; | |
14461 | primary->disable_plane = skylake_disable_primary_plane; | |
14462 | } else if (HAS_PCH_SPLIT(dev)) { | |
14463 | intel_primary_formats = i965_primary_formats; | |
14464 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14465 | ||
14466 | primary->update_plane = ironlake_update_primary_plane; | |
14467 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14468 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14469 | intel_primary_formats = i965_primary_formats; |
14470 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14471 | |
14472 | primary->update_plane = i9xx_update_primary_plane; | |
14473 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14474 | } else { |
14475 | intel_primary_formats = i8xx_primary_formats; | |
14476 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14477 | |
14478 | primary->update_plane = i9xx_update_primary_plane; | |
14479 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14480 | } |
14481 | ||
38573dc1 VS |
14482 | if (INTEL_INFO(dev)->gen >= 9) |
14483 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14484 | &intel_plane_funcs, | |
14485 | intel_primary_formats, num_formats, | |
14486 | DRM_PLANE_TYPE_PRIMARY, | |
14487 | "plane 1%c", pipe_name(pipe)); | |
14488 | else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
14489 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14490 | &intel_plane_funcs, | |
14491 | intel_primary_formats, num_formats, | |
14492 | DRM_PLANE_TYPE_PRIMARY, | |
14493 | "primary %c", pipe_name(pipe)); | |
14494 | else | |
14495 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14496 | &intel_plane_funcs, | |
14497 | intel_primary_formats, num_formats, | |
14498 | DRM_PLANE_TYPE_PRIMARY, | |
14499 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
14500 | if (ret) |
14501 | goto fail; | |
48404c1e | 14502 | |
3b7a5119 SJ |
14503 | if (INTEL_INFO(dev)->gen >= 4) |
14504 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14505 | |
ea2c67bb MR |
14506 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14507 | ||
465c120c | 14508 | return &primary->base; |
fca0ce2a VS |
14509 | |
14510 | fail: | |
14511 | kfree(state); | |
14512 | kfree(primary); | |
14513 | ||
14514 | return NULL; | |
465c120c MR |
14515 | } |
14516 | ||
3b7a5119 SJ |
14517 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14518 | { | |
14519 | if (!dev->mode_config.rotation_property) { | |
14520 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14521 | BIT(DRM_ROTATE_180); | |
14522 | ||
14523 | if (INTEL_INFO(dev)->gen >= 9) | |
14524 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14525 | ||
14526 | dev->mode_config.rotation_property = | |
14527 | drm_mode_create_rotation_property(dev, flags); | |
14528 | } | |
14529 | if (dev->mode_config.rotation_property) | |
14530 | drm_object_attach_property(&plane->base.base, | |
14531 | dev->mode_config.rotation_property, | |
14532 | plane->base.state->rotation); | |
14533 | } | |
14534 | ||
3d7d6510 | 14535 | static int |
852e787c | 14536 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14537 | struct intel_crtc_state *crtc_state, |
852e787c | 14538 | struct intel_plane_state *state) |
3d7d6510 | 14539 | { |
061e4b8d | 14540 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14541 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14542 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14543 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14544 | unsigned stride; |
14545 | int ret; | |
3d7d6510 | 14546 | |
061e4b8d ML |
14547 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14548 | &state->dst, &state->clip, | |
9b8b013d | 14549 | state->base.rotation, |
3d7d6510 MR |
14550 | DRM_PLANE_HELPER_NO_SCALING, |
14551 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14552 | true, true, &state->visible); |
757f9a3e GP |
14553 | if (ret) |
14554 | return ret; | |
14555 | ||
757f9a3e GP |
14556 | /* if we want to turn off the cursor ignore width and height */ |
14557 | if (!obj) | |
da20eabd | 14558 | return 0; |
757f9a3e | 14559 | |
757f9a3e | 14560 | /* Check for which cursor types we support */ |
061e4b8d | 14561 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14562 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14563 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14564 | return -EINVAL; |
14565 | } | |
14566 | ||
ea2c67bb MR |
14567 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14568 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14569 | DRM_DEBUG_KMS("buffer is too small\n"); |
14570 | return -ENOMEM; | |
14571 | } | |
14572 | ||
3a656b54 | 14573 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14574 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14575 | return -EINVAL; |
32b7eeec MR |
14576 | } |
14577 | ||
b29ec92c VS |
14578 | /* |
14579 | * There's something wrong with the cursor on CHV pipe C. | |
14580 | * If it straddles the left edge of the screen then | |
14581 | * moving it away from the edge or disabling it often | |
14582 | * results in a pipe underrun, and often that can lead to | |
14583 | * dead pipe (constant underrun reported, and it scans | |
14584 | * out just a solid color). To recover from that, the | |
14585 | * display power well must be turned off and on again. | |
14586 | * Refuse the put the cursor into that compromised position. | |
14587 | */ | |
14588 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14589 | state->visible && state->base.crtc_x < 0) { | |
14590 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14591 | return -EINVAL; | |
14592 | } | |
14593 | ||
da20eabd | 14594 | return 0; |
852e787c | 14595 | } |
3d7d6510 | 14596 | |
a8ad0d8e ML |
14597 | static void |
14598 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14599 | struct drm_crtc *crtc) |
a8ad0d8e | 14600 | { |
f2858021 ML |
14601 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14602 | ||
14603 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14604 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14605 | } |
14606 | ||
f4a2cf29 | 14607 | static void |
55a08b3f ML |
14608 | intel_update_cursor_plane(struct drm_plane *plane, |
14609 | const struct intel_crtc_state *crtc_state, | |
14610 | const struct intel_plane_state *state) | |
852e787c | 14611 | { |
55a08b3f ML |
14612 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14613 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14614 | struct drm_device *dev = plane->dev; |
2b875c22 | 14615 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14616 | uint32_t addr; |
852e787c | 14617 | |
f4a2cf29 | 14618 | if (!obj) |
a912f12f | 14619 | addr = 0; |
f4a2cf29 | 14620 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14621 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14622 | else |
a912f12f | 14623 | addr = obj->phys_handle->busaddr; |
852e787c | 14624 | |
a912f12f | 14625 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14626 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14627 | } |
14628 | ||
3d7d6510 MR |
14629 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14630 | int pipe) | |
14631 | { | |
fca0ce2a VS |
14632 | struct intel_plane *cursor = NULL; |
14633 | struct intel_plane_state *state = NULL; | |
14634 | int ret; | |
3d7d6510 MR |
14635 | |
14636 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
fca0ce2a VS |
14637 | if (!cursor) |
14638 | goto fail; | |
3d7d6510 | 14639 | |
8e7d688b | 14640 | state = intel_create_plane_state(&cursor->base); |
fca0ce2a VS |
14641 | if (!state) |
14642 | goto fail; | |
8e7d688b | 14643 | cursor->base.state = &state->base; |
ea2c67bb | 14644 | |
3d7d6510 MR |
14645 | cursor->can_scale = false; |
14646 | cursor->max_downscale = 1; | |
14647 | cursor->pipe = pipe; | |
14648 | cursor->plane = pipe; | |
a9ff8714 | 14649 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14650 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14651 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14652 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 14653 | |
fca0ce2a VS |
14654 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
14655 | &intel_plane_funcs, | |
14656 | intel_cursor_formats, | |
14657 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
14658 | DRM_PLANE_TYPE_CURSOR, |
14659 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
14660 | if (ret) |
14661 | goto fail; | |
4398ad45 VS |
14662 | |
14663 | if (INTEL_INFO(dev)->gen >= 4) { | |
14664 | if (!dev->mode_config.rotation_property) | |
14665 | dev->mode_config.rotation_property = | |
14666 | drm_mode_create_rotation_property(dev, | |
14667 | BIT(DRM_ROTATE_0) | | |
14668 | BIT(DRM_ROTATE_180)); | |
14669 | if (dev->mode_config.rotation_property) | |
14670 | drm_object_attach_property(&cursor->base.base, | |
14671 | dev->mode_config.rotation_property, | |
8e7d688b | 14672 | state->base.rotation); |
4398ad45 VS |
14673 | } |
14674 | ||
af99ceda CK |
14675 | if (INTEL_INFO(dev)->gen >=9) |
14676 | state->scaler_id = -1; | |
14677 | ||
ea2c67bb MR |
14678 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14679 | ||
3d7d6510 | 14680 | return &cursor->base; |
fca0ce2a VS |
14681 | |
14682 | fail: | |
14683 | kfree(state); | |
14684 | kfree(cursor); | |
14685 | ||
14686 | return NULL; | |
3d7d6510 MR |
14687 | } |
14688 | ||
549e2bfb CK |
14689 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14690 | struct intel_crtc_state *crtc_state) | |
14691 | { | |
14692 | int i; | |
14693 | struct intel_scaler *intel_scaler; | |
14694 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14695 | ||
14696 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14697 | intel_scaler = &scaler_state->scalers[i]; | |
14698 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14699 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14700 | } | |
14701 | ||
14702 | scaler_state->scaler_id = -1; | |
14703 | } | |
14704 | ||
b358d0a6 | 14705 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14706 | { |
fac5e23e | 14707 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 14708 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14709 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14710 | struct drm_plane *primary = NULL; |
14711 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14712 | int ret; |
79e53945 | 14713 | |
955382f3 | 14714 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14715 | if (intel_crtc == NULL) |
14716 | return; | |
14717 | ||
f5de6e07 ACO |
14718 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14719 | if (!crtc_state) | |
14720 | goto fail; | |
550acefd ACO |
14721 | intel_crtc->config = crtc_state; |
14722 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14723 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14724 | |
549e2bfb CK |
14725 | /* initialize shared scalers */ |
14726 | if (INTEL_INFO(dev)->gen >= 9) { | |
14727 | if (pipe == PIPE_C) | |
14728 | intel_crtc->num_scalers = 1; | |
14729 | else | |
14730 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14731 | ||
14732 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14733 | } | |
14734 | ||
465c120c | 14735 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14736 | if (!primary) |
14737 | goto fail; | |
14738 | ||
14739 | cursor = intel_cursor_plane_create(dev, pipe); | |
14740 | if (!cursor) | |
14741 | goto fail; | |
14742 | ||
465c120c | 14743 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
4d5d72b7 VS |
14744 | cursor, &intel_crtc_funcs, |
14745 | "pipe %c", pipe_name(pipe)); | |
3d7d6510 MR |
14746 | if (ret) |
14747 | goto fail; | |
79e53945 | 14748 | |
1f1c2e24 VS |
14749 | /* |
14750 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14751 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14752 | */ |
80824003 JB |
14753 | intel_crtc->pipe = pipe; |
14754 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14755 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14756 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14757 | intel_crtc->plane = !pipe; |
80824003 JB |
14758 | } |
14759 | ||
4b0e333e CW |
14760 | intel_crtc->cursor_base = ~0; |
14761 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14762 | intel_crtc->cursor_size = ~0; |
8d7849db | 14763 | |
852eb00d VS |
14764 | intel_crtc->wm.cxsr_allowed = true; |
14765 | ||
22fd0fab JB |
14766 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14767 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14768 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14769 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14770 | ||
79e53945 | 14771 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14772 | |
8563b1e8 LL |
14773 | intel_color_init(&intel_crtc->base); |
14774 | ||
87b6b101 | 14775 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14776 | return; |
14777 | ||
14778 | fail: | |
69ae561f VS |
14779 | intel_plane_destroy(primary); |
14780 | intel_plane_destroy(cursor); | |
f5de6e07 | 14781 | kfree(crtc_state); |
3d7d6510 | 14782 | kfree(intel_crtc); |
79e53945 JB |
14783 | } |
14784 | ||
752aa88a JB |
14785 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14786 | { | |
14787 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14788 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14789 | |
51fd371b | 14790 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14791 | |
d3babd3f | 14792 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14793 | return INVALID_PIPE; |
14794 | ||
14795 | return to_intel_crtc(encoder->crtc)->pipe; | |
14796 | } | |
14797 | ||
08d7b3d1 | 14798 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14799 | struct drm_file *file) |
08d7b3d1 | 14800 | { |
08d7b3d1 | 14801 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14802 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14803 | struct intel_crtc *crtc; |
08d7b3d1 | 14804 | |
7707e653 | 14805 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 14806 | if (!drmmode_crtc) |
3f2c2057 | 14807 | return -ENOENT; |
08d7b3d1 | 14808 | |
7707e653 | 14809 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14810 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14811 | |
c05422d5 | 14812 | return 0; |
08d7b3d1 CW |
14813 | } |
14814 | ||
66a9278e | 14815 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14816 | { |
66a9278e DV |
14817 | struct drm_device *dev = encoder->base.dev; |
14818 | struct intel_encoder *source_encoder; | |
79e53945 | 14819 | int index_mask = 0; |
79e53945 JB |
14820 | int entry = 0; |
14821 | ||
b2784e15 | 14822 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14823 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14824 | index_mask |= (1 << entry); |
14825 | ||
79e53945 JB |
14826 | entry++; |
14827 | } | |
4ef69c7a | 14828 | |
79e53945 JB |
14829 | return index_mask; |
14830 | } | |
14831 | ||
4d302442 CW |
14832 | static bool has_edp_a(struct drm_device *dev) |
14833 | { | |
fac5e23e | 14834 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d302442 CW |
14835 | |
14836 | if (!IS_MOBILE(dev)) | |
14837 | return false; | |
14838 | ||
14839 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14840 | return false; | |
14841 | ||
e3589908 | 14842 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14843 | return false; |
14844 | ||
14845 | return true; | |
14846 | } | |
14847 | ||
84b4e042 JB |
14848 | static bool intel_crt_present(struct drm_device *dev) |
14849 | { | |
fac5e23e | 14850 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b4e042 | 14851 | |
884497ed DL |
14852 | if (INTEL_INFO(dev)->gen >= 9) |
14853 | return false; | |
14854 | ||
cf404ce4 | 14855 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14856 | return false; |
14857 | ||
14858 | if (IS_CHERRYVIEW(dev)) | |
14859 | return false; | |
14860 | ||
65e472e4 VS |
14861 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14862 | return false; | |
14863 | ||
70ac54d0 VS |
14864 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14865 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14866 | return false; | |
14867 | ||
e4abb733 | 14868 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14869 | return false; |
14870 | ||
14871 | return true; | |
14872 | } | |
14873 | ||
8090ba8c ID |
14874 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
14875 | { | |
14876 | int pps_num; | |
14877 | int pps_idx; | |
14878 | ||
14879 | if (HAS_DDI(dev_priv)) | |
14880 | return; | |
14881 | /* | |
14882 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
14883 | * everywhere where registers can be write protected. | |
14884 | */ | |
14885 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14886 | pps_num = 2; | |
14887 | else | |
14888 | pps_num = 1; | |
14889 | ||
14890 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
14891 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
14892 | ||
14893 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
14894 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
14895 | } | |
14896 | } | |
14897 | ||
44cb734c ID |
14898 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
14899 | { | |
14900 | if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv)) | |
14901 | dev_priv->pps_mmio_base = PCH_PPS_BASE; | |
14902 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14903 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
14904 | else | |
14905 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
14906 | |
14907 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
14908 | } |
14909 | ||
79e53945 JB |
14910 | static void intel_setup_outputs(struct drm_device *dev) |
14911 | { | |
fac5e23e | 14912 | struct drm_i915_private *dev_priv = to_i915(dev); |
4ef69c7a | 14913 | struct intel_encoder *encoder; |
cb0953d7 | 14914 | bool dpd_is_edp = false; |
79e53945 | 14915 | |
44cb734c ID |
14916 | intel_pps_init(dev_priv); |
14917 | ||
97a824e1 ID |
14918 | /* |
14919 | * intel_edp_init_connector() depends on this completing first, to | |
14920 | * prevent the registeration of both eDP and LVDS and the incorrect | |
14921 | * sharing of the PPS. | |
14922 | */ | |
c9093354 | 14923 | intel_lvds_init(dev); |
79e53945 | 14924 | |
84b4e042 | 14925 | if (intel_crt_present(dev)) |
79935fca | 14926 | intel_crt_init(dev); |
cb0953d7 | 14927 | |
c776eb2e VK |
14928 | if (IS_BROXTON(dev)) { |
14929 | /* | |
14930 | * FIXME: Broxton doesn't support port detection via the | |
14931 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14932 | * detect the ports. | |
14933 | */ | |
14934 | intel_ddi_init(dev, PORT_A); | |
14935 | intel_ddi_init(dev, PORT_B); | |
14936 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
14937 | |
14938 | intel_dsi_init(dev); | |
c776eb2e | 14939 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
14940 | int found; |
14941 | ||
de31facd JB |
14942 | /* |
14943 | * Haswell uses DDI functions to detect digital outputs. | |
14944 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14945 | * it's there. | |
14946 | */ | |
77179400 | 14947 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14948 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14949 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14950 | intel_ddi_init(dev, PORT_A); |
14951 | ||
14952 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14953 | * register */ | |
14954 | found = I915_READ(SFUSE_STRAP); | |
14955 | ||
14956 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14957 | intel_ddi_init(dev, PORT_B); | |
14958 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14959 | intel_ddi_init(dev, PORT_C); | |
14960 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14961 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14962 | /* |
14963 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14964 | */ | |
ef11bdb3 | 14965 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14966 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14967 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14968 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14969 | intel_ddi_init(dev, PORT_E); | |
14970 | ||
0e72a5b5 | 14971 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14972 | int found; |
5d8a7752 | 14973 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14974 | |
14975 | if (has_edp_a(dev)) | |
14976 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14977 | |
dc0fa718 | 14978 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14979 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14980 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14981 | if (!found) |
e2debe91 | 14982 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14983 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14984 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14985 | } |
14986 | ||
dc0fa718 | 14987 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14988 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14989 | |
dc0fa718 | 14990 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14991 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14992 | |
5eb08b69 | 14993 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14994 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14995 | |
270b3042 | 14996 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14997 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14998 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
22f35042 | 14999 | bool has_edp, has_port; |
457c52d8 | 15000 | |
e17ac6db VS |
15001 | /* |
15002 | * The DP_DETECTED bit is the latched state of the DDC | |
15003 | * SDA pin at boot. However since eDP doesn't require DDC | |
15004 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
15005 | * eDP ports may have been muxed to an alternate function. | |
15006 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
15007 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
15008 | * detect eDP ports. | |
22f35042 VS |
15009 | * |
15010 | * Sadly the straps seem to be missing sometimes even for HDMI | |
15011 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
15012 | * and VBT for the presence of the port. Additionally we can't | |
15013 | * trust the port type the VBT declares as we've seen at least | |
15014 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 15015 | */ |
457c52d8 | 15016 | has_edp = intel_dp_is_edp(dev, PORT_B); |
22f35042 VS |
15017 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
15018 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
457c52d8 | 15019 | has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); |
22f35042 | 15020 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 15021 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
585a94b8 | 15022 | |
457c52d8 | 15023 | has_edp = intel_dp_is_edp(dev, PORT_C); |
22f35042 VS |
15024 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
15025 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
457c52d8 | 15026 | has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); |
22f35042 | 15027 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 15028 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
19c03924 | 15029 | |
9418c1f1 | 15030 | if (IS_CHERRYVIEW(dev)) { |
22f35042 VS |
15031 | /* |
15032 | * eDP not supported on port D, | |
15033 | * so no need to worry about it | |
15034 | */ | |
15035 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
15036 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
e66eb81d | 15037 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
22f35042 VS |
15038 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
15039 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
9418c1f1 VS |
15040 | } |
15041 | ||
3cfca973 | 15042 | intel_dsi_init(dev); |
09da55dc | 15043 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 15044 | bool found = false; |
7d57382e | 15045 | |
e2debe91 | 15046 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15047 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 15048 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 15049 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 15050 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 15051 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 15052 | } |
27185ae1 | 15053 | |
3fec3d2f | 15054 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 15055 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 15056 | } |
13520b05 KH |
15057 | |
15058 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 15059 | |
e2debe91 | 15060 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15061 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 15062 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 15063 | } |
27185ae1 | 15064 | |
e2debe91 | 15065 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 15066 | |
3fec3d2f | 15067 | if (IS_G4X(dev)) { |
b01f2c3a | 15068 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 15069 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 15070 | } |
3fec3d2f | 15071 | if (IS_G4X(dev)) |
ab9d7c30 | 15072 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 15073 | } |
27185ae1 | 15074 | |
3fec3d2f | 15075 | if (IS_G4X(dev) && |
e7281eab | 15076 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 15077 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 15078 | } else if (IS_GEN2(dev)) |
79e53945 JB |
15079 | intel_dvo_init(dev); |
15080 | ||
103a196f | 15081 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
15082 | intel_tv_init(dev); |
15083 | ||
0bc12bcb | 15084 | intel_psr_init(dev); |
7c8f8a70 | 15085 | |
b2784e15 | 15086 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
15087 | encoder->base.possible_crtcs = encoder->crtc_mask; |
15088 | encoder->base.possible_clones = | |
66a9278e | 15089 | intel_encoder_clones(encoder); |
79e53945 | 15090 | } |
47356eb6 | 15091 | |
dde86e2d | 15092 | intel_init_pch_refclk(dev); |
270b3042 DV |
15093 | |
15094 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
15095 | } |
15096 | ||
15097 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
15098 | { | |
60a5ca01 | 15099 | struct drm_device *dev = fb->dev; |
79e53945 | 15100 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 15101 | |
ef2d633e | 15102 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 15103 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 15104 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
f8c417cd | 15105 | i915_gem_object_put(intel_fb->obj); |
60a5ca01 | 15106 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
15107 | kfree(intel_fb); |
15108 | } | |
15109 | ||
15110 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 15111 | struct drm_file *file, |
79e53945 JB |
15112 | unsigned int *handle) |
15113 | { | |
15114 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 15115 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 15116 | |
cc917ab4 CW |
15117 | if (obj->userptr.mm) { |
15118 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
15119 | return -EINVAL; | |
15120 | } | |
15121 | ||
05394f39 | 15122 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
15123 | } |
15124 | ||
86c98588 RV |
15125 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
15126 | struct drm_file *file, | |
15127 | unsigned flags, unsigned color, | |
15128 | struct drm_clip_rect *clips, | |
15129 | unsigned num_clips) | |
15130 | { | |
15131 | struct drm_device *dev = fb->dev; | |
15132 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
15133 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
15134 | ||
15135 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 15136 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
15137 | mutex_unlock(&dev->struct_mutex); |
15138 | ||
15139 | return 0; | |
15140 | } | |
15141 | ||
79e53945 JB |
15142 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
15143 | .destroy = intel_user_framebuffer_destroy, | |
15144 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 15145 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
15146 | }; |
15147 | ||
b321803d DL |
15148 | static |
15149 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
15150 | uint32_t pixel_format) | |
15151 | { | |
15152 | u32 gen = INTEL_INFO(dev)->gen; | |
15153 | ||
15154 | if (gen >= 9) { | |
ac484963 VS |
15155 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
15156 | ||
b321803d DL |
15157 | /* "The stride in bytes must not exceed the of the size of 8K |
15158 | * pixels and 32K bytes." | |
15159 | */ | |
ac484963 | 15160 | return min(8192 * cpp, 32768); |
666a4537 | 15161 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
15162 | return 32*1024; |
15163 | } else if (gen >= 4) { | |
15164 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15165 | return 16*1024; | |
15166 | else | |
15167 | return 32*1024; | |
15168 | } else if (gen >= 3) { | |
15169 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15170 | return 8*1024; | |
15171 | else | |
15172 | return 16*1024; | |
15173 | } else { | |
15174 | /* XXX DSPC is limited to 4k tiled */ | |
15175 | return 8*1024; | |
15176 | } | |
15177 | } | |
15178 | ||
b5ea642a DV |
15179 | static int intel_framebuffer_init(struct drm_device *dev, |
15180 | struct intel_framebuffer *intel_fb, | |
15181 | struct drm_mode_fb_cmd2 *mode_cmd, | |
15182 | struct drm_i915_gem_object *obj) | |
79e53945 | 15183 | { |
7b49f948 | 15184 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 15185 | int ret; |
b321803d | 15186 | u32 pitch_limit, stride_alignment; |
79e53945 | 15187 | |
dd4916c5 DV |
15188 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
15189 | ||
2a80eada DV |
15190 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
15191 | /* Enforce that fb modifier and tiling mode match, but only for | |
15192 | * X-tiled. This is needed for FBC. */ | |
3e510a8e | 15193 | if (!!(i915_gem_object_get_tiling(obj) == I915_TILING_X) != |
2a80eada DV |
15194 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { |
15195 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
15196 | return -EINVAL; | |
15197 | } | |
15198 | } else { | |
3e510a8e | 15199 | if (i915_gem_object_get_tiling(obj) == I915_TILING_X) |
2a80eada | 15200 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
3e510a8e | 15201 | else if (i915_gem_object_get_tiling(obj) == I915_TILING_Y) { |
2a80eada DV |
15202 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
15203 | return -EINVAL; | |
15204 | } | |
15205 | } | |
15206 | ||
9a8f0a12 TU |
15207 | /* Passed in modifier sanity checking. */ |
15208 | switch (mode_cmd->modifier[0]) { | |
15209 | case I915_FORMAT_MOD_Y_TILED: | |
15210 | case I915_FORMAT_MOD_Yf_TILED: | |
15211 | if (INTEL_INFO(dev)->gen < 9) { | |
15212 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
15213 | mode_cmd->modifier[0]); | |
15214 | return -EINVAL; | |
15215 | } | |
15216 | case DRM_FORMAT_MOD_NONE: | |
15217 | case I915_FORMAT_MOD_X_TILED: | |
15218 | break; | |
15219 | default: | |
c0f40428 JB |
15220 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
15221 | mode_cmd->modifier[0]); | |
57cd6508 | 15222 | return -EINVAL; |
c16ed4be | 15223 | } |
57cd6508 | 15224 | |
7b49f948 VS |
15225 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
15226 | mode_cmd->modifier[0], | |
b321803d DL |
15227 | mode_cmd->pixel_format); |
15228 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
15229 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
15230 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 15231 | return -EINVAL; |
c16ed4be | 15232 | } |
57cd6508 | 15233 | |
b321803d DL |
15234 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
15235 | mode_cmd->pixel_format); | |
a35cdaa0 | 15236 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
15237 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
15238 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 15239 | "tiled" : "linear", |
a35cdaa0 | 15240 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 15241 | return -EINVAL; |
c16ed4be | 15242 | } |
5d7bd705 | 15243 | |
2a80eada | 15244 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
3e510a8e | 15245 | mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) { |
c16ed4be | 15246 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
3e510a8e CW |
15247 | mode_cmd->pitches[0], |
15248 | i915_gem_object_get_stride(obj)); | |
5d7bd705 | 15249 | return -EINVAL; |
c16ed4be | 15250 | } |
5d7bd705 | 15251 | |
57779d06 | 15252 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 15253 | switch (mode_cmd->pixel_format) { |
57779d06 | 15254 | case DRM_FORMAT_C8: |
04b3924d VS |
15255 | case DRM_FORMAT_RGB565: |
15256 | case DRM_FORMAT_XRGB8888: | |
15257 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
15258 | break; |
15259 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 15260 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
15261 | DRM_DEBUG("unsupported pixel format: %s\n", |
15262 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15263 | return -EINVAL; |
c16ed4be | 15264 | } |
57779d06 | 15265 | break; |
57779d06 | 15266 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
15267 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
15268 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
15269 | DRM_DEBUG("unsupported pixel format: %s\n", |
15270 | drm_get_format_name(mode_cmd->pixel_format)); | |
15271 | return -EINVAL; | |
15272 | } | |
15273 | break; | |
15274 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15275 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15276 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 15277 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
15278 | DRM_DEBUG("unsupported pixel format: %s\n", |
15279 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15280 | return -EINVAL; |
c16ed4be | 15281 | } |
b5626747 | 15282 | break; |
7531208b | 15283 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 15284 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
15285 | DRM_DEBUG("unsupported pixel format: %s\n", |
15286 | drm_get_format_name(mode_cmd->pixel_format)); | |
15287 | return -EINVAL; | |
15288 | } | |
15289 | break; | |
04b3924d VS |
15290 | case DRM_FORMAT_YUYV: |
15291 | case DRM_FORMAT_UYVY: | |
15292 | case DRM_FORMAT_YVYU: | |
15293 | case DRM_FORMAT_VYUY: | |
c16ed4be | 15294 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
15295 | DRM_DEBUG("unsupported pixel format: %s\n", |
15296 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15297 | return -EINVAL; |
c16ed4be | 15298 | } |
57cd6508 CW |
15299 | break; |
15300 | default: | |
4ee62c76 VS |
15301 | DRM_DEBUG("unsupported pixel format: %s\n", |
15302 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
15303 | return -EINVAL; |
15304 | } | |
15305 | ||
90f9a336 VS |
15306 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15307 | if (mode_cmd->offsets[0] != 0) | |
15308 | return -EINVAL; | |
15309 | ||
c7d73f6a DV |
15310 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15311 | intel_fb->obj = obj; | |
15312 | ||
6687c906 VS |
15313 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
15314 | if (ret) | |
15315 | return ret; | |
2d7a215f | 15316 | |
79e53945 JB |
15317 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15318 | if (ret) { | |
15319 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15320 | return ret; | |
15321 | } | |
15322 | ||
0b05e1e0 VS |
15323 | intel_fb->obj->framebuffer_references++; |
15324 | ||
79e53945 JB |
15325 | return 0; |
15326 | } | |
15327 | ||
79e53945 JB |
15328 | static struct drm_framebuffer * |
15329 | intel_user_framebuffer_create(struct drm_device *dev, | |
15330 | struct drm_file *filp, | |
1eb83451 | 15331 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15332 | { |
dcb1394e | 15333 | struct drm_framebuffer *fb; |
05394f39 | 15334 | struct drm_i915_gem_object *obj; |
76dc3769 | 15335 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15336 | |
03ac0642 CW |
15337 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
15338 | if (!obj) | |
cce13ff7 | 15339 | return ERR_PTR(-ENOENT); |
79e53945 | 15340 | |
92907cbb | 15341 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e | 15342 | if (IS_ERR(fb)) |
34911fd3 | 15343 | i915_gem_object_put_unlocked(obj); |
dcb1394e LW |
15344 | |
15345 | return fb; | |
79e53945 JB |
15346 | } |
15347 | ||
0695726e | 15348 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 15349 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
15350 | { |
15351 | } | |
15352 | #endif | |
15353 | ||
79e53945 | 15354 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15355 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15356 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15357 | .atomic_check = intel_atomic_check, |
15358 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15359 | .atomic_state_alloc = intel_atomic_state_alloc, |
15360 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15361 | }; |
15362 | ||
88212941 ID |
15363 | /** |
15364 | * intel_init_display_hooks - initialize the display modesetting hooks | |
15365 | * @dev_priv: device private | |
15366 | */ | |
15367 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 15368 | { |
88212941 | 15369 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 15370 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15371 | dev_priv->display.get_initial_plane_config = |
15372 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15373 | dev_priv->display.crtc_compute_clock = |
15374 | haswell_crtc_compute_clock; | |
15375 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15376 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15377 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 15378 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15379 | dev_priv->display.get_initial_plane_config = |
15380 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15381 | dev_priv->display.crtc_compute_clock = |
15382 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15383 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15384 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15385 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 15386 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15387 | dev_priv->display.get_initial_plane_config = |
15388 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15389 | dev_priv->display.crtc_compute_clock = |
15390 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15391 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15392 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 15393 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 15394 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15395 | dev_priv->display.get_initial_plane_config = |
15396 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
15397 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
15398 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
15399 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
15400 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
15401 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15402 | dev_priv->display.get_initial_plane_config = | |
15403 | i9xx_get_initial_plane_config; | |
15404 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
15405 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15406 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
15407 | } else if (IS_G4X(dev_priv)) { |
15408 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15409 | dev_priv->display.get_initial_plane_config = | |
15410 | i9xx_get_initial_plane_config; | |
15411 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
15412 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15413 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
15414 | } else if (IS_PINEVIEW(dev_priv)) { |
15415 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15416 | dev_priv->display.get_initial_plane_config = | |
15417 | i9xx_get_initial_plane_config; | |
15418 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
15419 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15420 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 15421 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 15422 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15423 | dev_priv->display.get_initial_plane_config = |
15424 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15425 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
15426 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
15427 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
15428 | } else { |
15429 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15430 | dev_priv->display.get_initial_plane_config = | |
15431 | i9xx_get_initial_plane_config; | |
15432 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
15433 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15434 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15435 | } |
e70236a8 | 15436 | |
e70236a8 | 15437 | /* Returns the core display clock speed */ |
88212941 | 15438 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
15439 | dev_priv->display.get_display_clock_speed = |
15440 | skylake_get_display_clock_speed; | |
88212941 | 15441 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
15442 | dev_priv->display.get_display_clock_speed = |
15443 | broxton_get_display_clock_speed; | |
88212941 | 15444 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
15445 | dev_priv->display.get_display_clock_speed = |
15446 | broadwell_get_display_clock_speed; | |
88212941 | 15447 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
15448 | dev_priv->display.get_display_clock_speed = |
15449 | haswell_get_display_clock_speed; | |
88212941 | 15450 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
15451 | dev_priv->display.get_display_clock_speed = |
15452 | valleyview_get_display_clock_speed; | |
88212941 | 15453 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
15454 | dev_priv->display.get_display_clock_speed = |
15455 | ilk_get_display_clock_speed; | |
88212941 ID |
15456 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
15457 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
15458 | dev_priv->display.get_display_clock_speed = |
15459 | i945_get_display_clock_speed; | |
88212941 | 15460 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
15461 | dev_priv->display.get_display_clock_speed = |
15462 | gm45_get_display_clock_speed; | |
88212941 | 15463 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
15464 | dev_priv->display.get_display_clock_speed = |
15465 | i965gm_get_display_clock_speed; | |
88212941 | 15466 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
15467 | dev_priv->display.get_display_clock_speed = |
15468 | pnv_get_display_clock_speed; | |
88212941 | 15469 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
15470 | dev_priv->display.get_display_clock_speed = |
15471 | g33_get_display_clock_speed; | |
88212941 | 15472 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
15473 | dev_priv->display.get_display_clock_speed = |
15474 | i915_get_display_clock_speed; | |
88212941 | 15475 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
15476 | dev_priv->display.get_display_clock_speed = |
15477 | i9xx_misc_get_display_clock_speed; | |
88212941 | 15478 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
15479 | dev_priv->display.get_display_clock_speed = |
15480 | i915gm_get_display_clock_speed; | |
88212941 | 15481 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
15482 | dev_priv->display.get_display_clock_speed = |
15483 | i865_get_display_clock_speed; | |
88212941 | 15484 | else if (IS_I85X(dev_priv)) |
e70236a8 | 15485 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15486 | i85x_get_display_clock_speed; |
623e01e5 | 15487 | else { /* 830 */ |
88212941 | 15488 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
15489 | dev_priv->display.get_display_clock_speed = |
15490 | i830_get_display_clock_speed; | |
623e01e5 | 15491 | } |
e70236a8 | 15492 | |
88212941 | 15493 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 15494 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 15495 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 15496 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 15497 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
15498 | /* FIXME: detect B0+ stepping and use auto training */ |
15499 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 15500 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 15501 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
15502 | } |
15503 | ||
15504 | if (IS_BROADWELL(dev_priv)) { | |
15505 | dev_priv->display.modeset_commit_cdclk = | |
15506 | broadwell_modeset_commit_cdclk; | |
15507 | dev_priv->display.modeset_calc_cdclk = | |
15508 | broadwell_modeset_calc_cdclk; | |
88212941 | 15509 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
15510 | dev_priv->display.modeset_commit_cdclk = |
15511 | valleyview_modeset_commit_cdclk; | |
15512 | dev_priv->display.modeset_calc_cdclk = | |
15513 | valleyview_modeset_calc_cdclk; | |
88212941 | 15514 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed | 15515 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 15516 | bxt_modeset_commit_cdclk; |
27c329ed | 15517 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 15518 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
15519 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
15520 | dev_priv->display.modeset_commit_cdclk = | |
15521 | skl_modeset_commit_cdclk; | |
15522 | dev_priv->display.modeset_calc_cdclk = | |
15523 | skl_modeset_calc_cdclk; | |
e70236a8 | 15524 | } |
5a21b665 DV |
15525 | |
15526 | switch (INTEL_INFO(dev_priv)->gen) { | |
15527 | case 2: | |
15528 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15529 | break; | |
15530 | ||
15531 | case 3: | |
15532 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15533 | break; | |
15534 | ||
15535 | case 4: | |
15536 | case 5: | |
15537 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15538 | break; | |
15539 | ||
15540 | case 6: | |
15541 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15542 | break; | |
15543 | case 7: | |
15544 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
15545 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
15546 | break; | |
15547 | case 9: | |
15548 | /* Drop through - unsupported since execlist only. */ | |
15549 | default: | |
15550 | /* Default just returns -ENODEV to indicate unsupported */ | |
15551 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
15552 | } | |
e70236a8 JB |
15553 | } |
15554 | ||
b690e96c JB |
15555 | /* |
15556 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15557 | * resume, or other times. This quirk makes sure that's the case for | |
15558 | * affected systems. | |
15559 | */ | |
0206e353 | 15560 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 15561 | { |
fac5e23e | 15562 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
15563 | |
15564 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15565 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15566 | } |
15567 | ||
b6b5d049 VS |
15568 | static void quirk_pipeb_force(struct drm_device *dev) |
15569 | { | |
fac5e23e | 15570 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
15571 | |
15572 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15573 | DRM_INFO("applying pipe b force quirk\n"); | |
15574 | } | |
15575 | ||
435793df KP |
15576 | /* |
15577 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15578 | */ | |
15579 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15580 | { | |
fac5e23e | 15581 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 15582 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 15583 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15584 | } |
15585 | ||
4dca20ef | 15586 | /* |
5a15ab5b CE |
15587 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15588 | * brightness value | |
4dca20ef CE |
15589 | */ |
15590 | static void quirk_invert_brightness(struct drm_device *dev) | |
15591 | { | |
fac5e23e | 15592 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 15593 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 15594 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15595 | } |
15596 | ||
9c72cc6f SD |
15597 | /* Some VBT's incorrectly indicate no backlight is present */ |
15598 | static void quirk_backlight_present(struct drm_device *dev) | |
15599 | { | |
fac5e23e | 15600 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
15601 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
15602 | DRM_INFO("applying backlight present quirk\n"); | |
15603 | } | |
15604 | ||
b690e96c JB |
15605 | struct intel_quirk { |
15606 | int device; | |
15607 | int subsystem_vendor; | |
15608 | int subsystem_device; | |
15609 | void (*hook)(struct drm_device *dev); | |
15610 | }; | |
15611 | ||
5f85f176 EE |
15612 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15613 | struct intel_dmi_quirk { | |
15614 | void (*hook)(struct drm_device *dev); | |
15615 | const struct dmi_system_id (*dmi_id_list)[]; | |
15616 | }; | |
15617 | ||
15618 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15619 | { | |
15620 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15621 | return 1; | |
15622 | } | |
15623 | ||
15624 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15625 | { | |
15626 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15627 | { | |
15628 | .callback = intel_dmi_reverse_brightness, | |
15629 | .ident = "NCR Corporation", | |
15630 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15631 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15632 | }, | |
15633 | }, | |
15634 | { } /* terminating entry */ | |
15635 | }, | |
15636 | .hook = quirk_invert_brightness, | |
15637 | }, | |
15638 | }; | |
15639 | ||
c43b5634 | 15640 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15641 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15642 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15643 | ||
b690e96c JB |
15644 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15645 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15646 | ||
5f080c0f VS |
15647 | /* 830 needs to leave pipe A & dpll A up */ |
15648 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15649 | ||
b6b5d049 VS |
15650 | /* 830 needs to leave pipe B & dpll B up */ |
15651 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15652 | ||
435793df KP |
15653 | /* Lenovo U160 cannot use SSC on LVDS */ |
15654 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15655 | |
15656 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15657 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15658 | |
be505f64 AH |
15659 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15660 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15661 | ||
15662 | /* Acer/eMachines G725 */ | |
15663 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15664 | ||
15665 | /* Acer/eMachines e725 */ | |
15666 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15667 | ||
15668 | /* Acer/Packard Bell NCL20 */ | |
15669 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15670 | ||
15671 | /* Acer Aspire 4736Z */ | |
15672 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15673 | |
15674 | /* Acer Aspire 5336 */ | |
15675 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15676 | |
15677 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15678 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15679 | |
dfb3d47b SD |
15680 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15681 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15682 | ||
b2a9601c | 15683 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15684 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15685 | ||
1b9448b0 JN |
15686 | /* Apple Macbook 4,1 */ |
15687 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15688 | ||
d4967d8c SD |
15689 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15690 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15691 | |
15692 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15693 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15694 | |
15695 | /* Dell Chromebook 11 */ | |
15696 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15697 | |
15698 | /* Dell Chromebook 11 (2015 version) */ | |
15699 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15700 | }; |
15701 | ||
15702 | static void intel_init_quirks(struct drm_device *dev) | |
15703 | { | |
15704 | struct pci_dev *d = dev->pdev; | |
15705 | int i; | |
15706 | ||
15707 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15708 | struct intel_quirk *q = &intel_quirks[i]; | |
15709 | ||
15710 | if (d->device == q->device && | |
15711 | (d->subsystem_vendor == q->subsystem_vendor || | |
15712 | q->subsystem_vendor == PCI_ANY_ID) && | |
15713 | (d->subsystem_device == q->subsystem_device || | |
15714 | q->subsystem_device == PCI_ANY_ID)) | |
15715 | q->hook(dev); | |
15716 | } | |
5f85f176 EE |
15717 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15718 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15719 | intel_dmi_quirks[i].hook(dev); | |
15720 | } | |
b690e96c JB |
15721 | } |
15722 | ||
9cce37f4 JB |
15723 | /* Disable the VGA plane that we never use */ |
15724 | static void i915_disable_vga(struct drm_device *dev) | |
15725 | { | |
fac5e23e | 15726 | struct drm_i915_private *dev_priv = to_i915(dev); |
9cce37f4 | 15727 | u8 sr1; |
f0f59a00 | 15728 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15729 | |
2b37c616 | 15730 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15731 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15732 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15733 | sr1 = inb(VGA_SR_DATA); |
15734 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15735 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15736 | udelay(300); | |
15737 | ||
01f5a626 | 15738 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15739 | POSTING_READ(vga_reg); |
15740 | } | |
15741 | ||
f817586c DV |
15742 | void intel_modeset_init_hw(struct drm_device *dev) |
15743 | { | |
fac5e23e | 15744 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 15745 | |
b6283055 | 15746 | intel_update_cdclk(dev); |
1a617b77 ML |
15747 | |
15748 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15749 | ||
f817586c | 15750 | intel_init_clock_gating(dev); |
f817586c DV |
15751 | } |
15752 | ||
d93c0372 MR |
15753 | /* |
15754 | * Calculate what we think the watermarks should be for the state we've read | |
15755 | * out of the hardware and then immediately program those watermarks so that | |
15756 | * we ensure the hardware settings match our internal state. | |
15757 | * | |
15758 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15759 | * current state (which was constructed during hardware readout) and running it | |
15760 | * through the atomic check code to calculate new watermark values in the | |
15761 | * state object. | |
15762 | */ | |
15763 | static void sanitize_watermarks(struct drm_device *dev) | |
15764 | { | |
15765 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15766 | struct drm_atomic_state *state; | |
15767 | struct drm_crtc *crtc; | |
15768 | struct drm_crtc_state *cstate; | |
15769 | struct drm_modeset_acquire_ctx ctx; | |
15770 | int ret; | |
15771 | int i; | |
15772 | ||
15773 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15774 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15775 | return; |
15776 | ||
15777 | /* | |
15778 | * We need to hold connection_mutex before calling duplicate_state so | |
15779 | * that the connector loop is protected. | |
15780 | */ | |
15781 | drm_modeset_acquire_init(&ctx, 0); | |
15782 | retry: | |
0cd1262d | 15783 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15784 | if (ret == -EDEADLK) { |
15785 | drm_modeset_backoff(&ctx); | |
15786 | goto retry; | |
15787 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15788 | goto fail; |
d93c0372 MR |
15789 | } |
15790 | ||
15791 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15792 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15793 | goto fail; |
d93c0372 | 15794 | |
ed4a6a7c MR |
15795 | /* |
15796 | * Hardware readout is the only time we don't want to calculate | |
15797 | * intermediate watermarks (since we don't trust the current | |
15798 | * watermarks). | |
15799 | */ | |
15800 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15801 | ||
d93c0372 MR |
15802 | ret = intel_atomic_check(dev, state); |
15803 | if (ret) { | |
15804 | /* | |
15805 | * If we fail here, it means that the hardware appears to be | |
15806 | * programmed in a way that shouldn't be possible, given our | |
15807 | * understanding of watermark requirements. This might mean a | |
15808 | * mistake in the hardware readout code or a mistake in the | |
15809 | * watermark calculations for a given platform. Raise a WARN | |
15810 | * so that this is noticeable. | |
15811 | * | |
15812 | * If this actually happens, we'll have to just leave the | |
15813 | * BIOS-programmed watermarks untouched and hope for the best. | |
15814 | */ | |
15815 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15816 | goto fail; |
d93c0372 MR |
15817 | } |
15818 | ||
15819 | /* Write calculated watermark values back */ | |
d93c0372 MR |
15820 | for_each_crtc_in_state(state, crtc, cstate, i) { |
15821 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15822 | ||
ed4a6a7c MR |
15823 | cs->wm.need_postvbl_update = true; |
15824 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15825 | } |
15826 | ||
15827 | drm_atomic_state_free(state); | |
0cd1262d | 15828 | fail: |
d93c0372 MR |
15829 | drm_modeset_drop_locks(&ctx); |
15830 | drm_modeset_acquire_fini(&ctx); | |
15831 | } | |
15832 | ||
79e53945 JB |
15833 | void intel_modeset_init(struct drm_device *dev) |
15834 | { | |
72e96d64 JL |
15835 | struct drm_i915_private *dev_priv = to_i915(dev); |
15836 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1fe47785 | 15837 | int sprite, ret; |
8cc87b75 | 15838 | enum pipe pipe; |
46f297fb | 15839 | struct intel_crtc *crtc; |
79e53945 JB |
15840 | |
15841 | drm_mode_config_init(dev); | |
15842 | ||
15843 | dev->mode_config.min_width = 0; | |
15844 | dev->mode_config.min_height = 0; | |
15845 | ||
019d96cb DA |
15846 | dev->mode_config.preferred_depth = 24; |
15847 | dev->mode_config.prefer_shadow = 1; | |
15848 | ||
25bab385 TU |
15849 | dev->mode_config.allow_fb_modifiers = true; |
15850 | ||
e6ecefaa | 15851 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15852 | |
b690e96c JB |
15853 | intel_init_quirks(dev); |
15854 | ||
1fa61106 ED |
15855 | intel_init_pm(dev); |
15856 | ||
e3c74757 BW |
15857 | if (INTEL_INFO(dev)->num_pipes == 0) |
15858 | return; | |
15859 | ||
69f92f67 LW |
15860 | /* |
15861 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15862 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15863 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15864 | * indicates as much. | |
15865 | */ | |
15866 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15867 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15868 | DREF_SSC1_ENABLE); | |
15869 | ||
15870 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15871 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15872 | bios_lvds_use_ssc ? "en" : "dis", | |
15873 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15874 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15875 | } | |
15876 | } | |
15877 | ||
a6c45cf0 CW |
15878 | if (IS_GEN2(dev)) { |
15879 | dev->mode_config.max_width = 2048; | |
15880 | dev->mode_config.max_height = 2048; | |
15881 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15882 | dev->mode_config.max_width = 4096; |
15883 | dev->mode_config.max_height = 4096; | |
79e53945 | 15884 | } else { |
a6c45cf0 CW |
15885 | dev->mode_config.max_width = 8192; |
15886 | dev->mode_config.max_height = 8192; | |
79e53945 | 15887 | } |
068be561 | 15888 | |
dc41c154 VS |
15889 | if (IS_845G(dev) || IS_I865G(dev)) { |
15890 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15891 | dev->mode_config.cursor_height = 1023; | |
15892 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15893 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15894 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15895 | } else { | |
15896 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15897 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15898 | } | |
15899 | ||
72e96d64 | 15900 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 15901 | |
28c97730 | 15902 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15903 | INTEL_INFO(dev)->num_pipes, |
15904 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15905 | |
055e393f | 15906 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15907 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15908 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15909 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15910 | if (ret) |
06da8da2 | 15911 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15912 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15913 | } |
79e53945 JB |
15914 | } |
15915 | ||
bfa7df01 VS |
15916 | intel_update_czclk(dev_priv); |
15917 | intel_update_cdclk(dev); | |
15918 | ||
e72f9fbf | 15919 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15920 | |
b2045352 VS |
15921 | if (dev_priv->max_cdclk_freq == 0) |
15922 | intel_update_max_cdclk(dev); | |
15923 | ||
9cce37f4 JB |
15924 | /* Just disable it once at startup */ |
15925 | i915_disable_vga(dev); | |
79e53945 | 15926 | intel_setup_outputs(dev); |
11be49eb | 15927 | |
6e9f798d | 15928 | drm_modeset_lock_all(dev); |
043e9bda | 15929 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15930 | drm_modeset_unlock_all(dev); |
46f297fb | 15931 | |
d3fcc808 | 15932 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15933 | struct intel_initial_plane_config plane_config = {}; |
15934 | ||
46f297fb JB |
15935 | if (!crtc->active) |
15936 | continue; | |
15937 | ||
46f297fb | 15938 | /* |
46f297fb JB |
15939 | * Note that reserving the BIOS fb up front prevents us |
15940 | * from stuffing other stolen allocations like the ring | |
15941 | * on top. This prevents some ugliness at boot time, and | |
15942 | * can even allow for smooth boot transitions if the BIOS | |
15943 | * fb is large enough for the active pipe configuration. | |
15944 | */ | |
eeebeac5 ML |
15945 | dev_priv->display.get_initial_plane_config(crtc, |
15946 | &plane_config); | |
15947 | ||
15948 | /* | |
15949 | * If the fb is shared between multiple heads, we'll | |
15950 | * just get the first one. | |
15951 | */ | |
15952 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15953 | } |
d93c0372 MR |
15954 | |
15955 | /* | |
15956 | * Make sure hardware watermarks really match the state we read out. | |
15957 | * Note that we need to do this after reconstructing the BIOS fb's | |
15958 | * since the watermark calculation done here will use pstate->fb. | |
15959 | */ | |
15960 | sanitize_watermarks(dev); | |
2c7111db CW |
15961 | } |
15962 | ||
7fad798e DV |
15963 | static void intel_enable_pipe_a(struct drm_device *dev) |
15964 | { | |
15965 | struct intel_connector *connector; | |
15966 | struct drm_connector *crt = NULL; | |
15967 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15968 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15969 | |
15970 | /* We can't just switch on the pipe A, we need to set things up with a | |
15971 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15972 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15973 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15974 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15975 | crt = &connector->base; | |
15976 | break; | |
15977 | } | |
15978 | } | |
15979 | ||
15980 | if (!crt) | |
15981 | return; | |
15982 | ||
208bf9fd | 15983 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15984 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15985 | } |
15986 | ||
fa555837 DV |
15987 | static bool |
15988 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15989 | { | |
7eb552ae | 15990 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 15991 | struct drm_i915_private *dev_priv = to_i915(dev); |
649636ef | 15992 | u32 val; |
fa555837 | 15993 | |
7eb552ae | 15994 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15995 | return true; |
15996 | ||
649636ef | 15997 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15998 | |
15999 | if ((val & DISPLAY_PLANE_ENABLE) && | |
16000 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
16001 | return false; | |
16002 | ||
16003 | return true; | |
16004 | } | |
16005 | ||
02e93c35 VS |
16006 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
16007 | { | |
16008 | struct drm_device *dev = crtc->base.dev; | |
16009 | struct intel_encoder *encoder; | |
16010 | ||
16011 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
16012 | return true; | |
16013 | ||
16014 | return false; | |
16015 | } | |
16016 | ||
dd756198 VS |
16017 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
16018 | { | |
16019 | struct drm_device *dev = encoder->base.dev; | |
16020 | struct intel_connector *connector; | |
16021 | ||
16022 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
16023 | return true; | |
16024 | ||
16025 | return false; | |
16026 | } | |
16027 | ||
a168f5b3 VS |
16028 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
16029 | enum transcoder pch_transcoder) | |
16030 | { | |
16031 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
16032 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
16033 | } | |
16034 | ||
24929352 DV |
16035 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
16036 | { | |
16037 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 16038 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 16039 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 16040 | |
24929352 | 16041 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
16042 | if (!transcoder_is_dsi(cpu_transcoder)) { |
16043 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
16044 | ||
16045 | I915_WRITE(reg, | |
16046 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
16047 | } | |
24929352 | 16048 | |
d3eaf884 | 16049 | /* restore vblank interrupts to correct state */ |
9625604c | 16050 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 16051 | if (crtc->active) { |
f9cd7b88 VS |
16052 | struct intel_plane *plane; |
16053 | ||
9625604c | 16054 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
16055 | |
16056 | /* Disable everything but the primary plane */ | |
16057 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
16058 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
16059 | continue; | |
16060 | ||
16061 | plane->disable_plane(&plane->base, &crtc->base); | |
16062 | } | |
9625604c | 16063 | } |
d3eaf884 | 16064 | |
24929352 | 16065 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
16066 | * disable the crtc (and hence change the state) if it is wrong. Note |
16067 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
16068 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
16069 | bool plane; |
16070 | ||
78108b7c VS |
16071 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
16072 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
16073 | |
16074 | /* Pipe has the wrong plane attached and the plane is active. | |
16075 | * Temporarily change the plane mapping and disable everything | |
16076 | * ... */ | |
16077 | plane = crtc->plane; | |
b70709a6 | 16078 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 16079 | crtc->plane = !plane; |
b17d48e2 | 16080 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16081 | crtc->plane = plane; |
24929352 | 16082 | } |
24929352 | 16083 | |
7fad798e DV |
16084 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
16085 | crtc->pipe == PIPE_A && !crtc->active) { | |
16086 | /* BIOS forgot to enable pipe A, this mostly happens after | |
16087 | * resume. Force-enable the pipe to fix this, the update_dpms | |
16088 | * call below we restore the pipe to the right state, but leave | |
16089 | * the required bits on. */ | |
16090 | intel_enable_pipe_a(dev); | |
16091 | } | |
16092 | ||
24929352 DV |
16093 | /* Adjust the state of the output pipe according to whether we |
16094 | * have active connectors/encoders. */ | |
842e0307 | 16095 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 16096 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16097 | |
a3ed6aad | 16098 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
16099 | /* |
16100 | * We start out with underrun reporting disabled to avoid races. | |
16101 | * For correct bookkeeping mark this on active crtcs. | |
16102 | * | |
c5ab3bc0 DV |
16103 | * Also on gmch platforms we dont have any hardware bits to |
16104 | * disable the underrun reporting. Which means we need to start | |
16105 | * out with underrun reporting disabled also on inactive pipes, | |
16106 | * since otherwise we'll complain about the garbage we read when | |
16107 | * e.g. coming up after runtime pm. | |
16108 | * | |
4cc31489 DV |
16109 | * No protection against concurrent access is required - at |
16110 | * worst a fifo underrun happens which also sets this to false. | |
16111 | */ | |
16112 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
16113 | /* |
16114 | * We track the PCH trancoder underrun reporting state | |
16115 | * within the crtc. With crtc for pipe A housing the underrun | |
16116 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
16117 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
16118 | * and marking underrun reporting as disabled for the non-existing | |
16119 | * PCH transcoders B and C would prevent enabling the south | |
16120 | * error interrupt (see cpt_can_enable_serr_int()). | |
16121 | */ | |
16122 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
16123 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 16124 | } |
24929352 DV |
16125 | } |
16126 | ||
16127 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
16128 | { | |
16129 | struct intel_connector *connector; | |
16130 | struct drm_device *dev = encoder->base.dev; | |
16131 | ||
16132 | /* We need to check both for a crtc link (meaning that the | |
16133 | * encoder is active and trying to read from a pipe) and the | |
16134 | * pipe itself being active. */ | |
16135 | bool has_active_crtc = encoder->base.crtc && | |
16136 | to_intel_crtc(encoder->base.crtc)->active; | |
16137 | ||
dd756198 | 16138 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
16139 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
16140 | encoder->base.base.id, | |
8e329a03 | 16141 | encoder->base.name); |
24929352 DV |
16142 | |
16143 | /* Connector is active, but has no active pipe. This is | |
16144 | * fallout from our resume register restoring. Disable | |
16145 | * the encoder manually again. */ | |
16146 | if (encoder->base.crtc) { | |
16147 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
16148 | encoder->base.base.id, | |
8e329a03 | 16149 | encoder->base.name); |
24929352 | 16150 | encoder->disable(encoder); |
a62d1497 VS |
16151 | if (encoder->post_disable) |
16152 | encoder->post_disable(encoder); | |
24929352 | 16153 | } |
7f1950fb | 16154 | encoder->base.crtc = NULL; |
24929352 DV |
16155 | |
16156 | /* Inconsistent output/port/pipe state happens presumably due to | |
16157 | * a bug in one of the get_hw_state functions. Or someplace else | |
16158 | * in our code, like the register restore mess on resume. Clamp | |
16159 | * things to off as a safer default. */ | |
3a3371ff | 16160 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16161 | if (connector->encoder != encoder) |
16162 | continue; | |
7f1950fb EE |
16163 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
16164 | connector->base.encoder = NULL; | |
24929352 DV |
16165 | } |
16166 | } | |
16167 | /* Enabled encoders without active connectors will be fixed in | |
16168 | * the crtc fixup. */ | |
16169 | } | |
16170 | ||
04098753 | 16171 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f | 16172 | { |
fac5e23e | 16173 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 16174 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 16175 | |
04098753 ID |
16176 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
16177 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
16178 | i915_disable_vga(dev); | |
16179 | } | |
16180 | } | |
16181 | ||
16182 | void i915_redisable_vga(struct drm_device *dev) | |
16183 | { | |
fac5e23e | 16184 | struct drm_i915_private *dev_priv = to_i915(dev); |
04098753 | 16185 | |
8dc8a27c PZ |
16186 | /* This function can be called both from intel_modeset_setup_hw_state or |
16187 | * at a very early point in our resume sequence, where the power well | |
16188 | * structures are not yet restored. Since this function is at a very | |
16189 | * paranoid "someone might have enabled VGA while we were not looking" | |
16190 | * level, just check if the power well is enabled instead of trying to | |
16191 | * follow the "don't touch the power well if we don't need it" policy | |
16192 | * the rest of the driver uses. */ | |
6392f847 | 16193 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
16194 | return; |
16195 | ||
04098753 | 16196 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
16197 | |
16198 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
16199 | } |
16200 | ||
f9cd7b88 | 16201 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 16202 | { |
f9cd7b88 | 16203 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 16204 | |
f9cd7b88 | 16205 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
16206 | } |
16207 | ||
f9cd7b88 VS |
16208 | /* FIXME read out full plane state for all planes */ |
16209 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 16210 | { |
b26d3ea3 | 16211 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 16212 | struct intel_plane_state *plane_state = |
b26d3ea3 | 16213 | to_intel_plane_state(primary->state); |
d032ffa0 | 16214 | |
19b8d387 | 16215 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
16216 | primary_get_hw_state(to_intel_plane(primary)); |
16217 | ||
16218 | if (plane_state->visible) | |
16219 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
16220 | } |
16221 | ||
30e984df | 16222 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 16223 | { |
fac5e23e | 16224 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 16225 | enum pipe pipe; |
24929352 DV |
16226 | struct intel_crtc *crtc; |
16227 | struct intel_encoder *encoder; | |
16228 | struct intel_connector *connector; | |
5358901f | 16229 | int i; |
24929352 | 16230 | |
565602d7 ML |
16231 | dev_priv->active_crtcs = 0; |
16232 | ||
d3fcc808 | 16233 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
16234 | struct intel_crtc_state *crtc_state = crtc->config; |
16235 | int pixclk = 0; | |
3b117c8f | 16236 | |
ec2dc6a0 | 16237 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
16238 | memset(crtc_state, 0, sizeof(*crtc_state)); |
16239 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 16240 | |
565602d7 ML |
16241 | crtc_state->base.active = crtc_state->base.enable = |
16242 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
16243 | ||
16244 | crtc->base.enabled = crtc_state->base.enable; | |
16245 | crtc->active = crtc_state->base.active; | |
16246 | ||
16247 | if (crtc_state->base.active) { | |
16248 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
16249 | ||
c89e39f3 | 16250 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 16251 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 16252 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
16253 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
16254 | else | |
16255 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
16256 | |
16257 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
16258 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
16259 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
16260 | } |
16261 | ||
16262 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 16263 | |
f9cd7b88 | 16264 | readout_plane_state(crtc); |
24929352 | 16265 | |
78108b7c VS |
16266 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
16267 | crtc->base.base.id, crtc->base.name, | |
24929352 DV |
16268 | crtc->active ? "enabled" : "disabled"); |
16269 | } | |
16270 | ||
5358901f DV |
16271 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16272 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16273 | ||
2edd6443 ACO |
16274 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16275 | &pll->config.hw_state); | |
3e369b76 | 16276 | pll->config.crtc_mask = 0; |
d3fcc808 | 16277 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16278 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16279 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16280 | } |
2dd66ebd | 16281 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16282 | |
1e6f2ddc | 16283 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16284 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16285 | } |
16286 | ||
b2784e15 | 16287 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16288 | pipe = 0; |
16289 | ||
16290 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
16291 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16292 | encoder->base.crtc = &crtc->base; | |
253c84c8 | 16293 | crtc->config->output_types |= 1 << encoder->type; |
6e3c9717 | 16294 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16295 | } else { |
16296 | encoder->base.crtc = NULL; | |
16297 | } | |
16298 | ||
6f2bcceb | 16299 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 16300 | encoder->base.base.id, |
8e329a03 | 16301 | encoder->base.name, |
24929352 | 16302 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 16303 | pipe_name(pipe)); |
24929352 DV |
16304 | } |
16305 | ||
3a3371ff | 16306 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16307 | if (connector->get_hw_state(connector)) { |
16308 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16309 | |
16310 | encoder = connector->encoder; | |
16311 | connector->base.encoder = &encoder->base; | |
16312 | ||
16313 | if (encoder->base.crtc && | |
16314 | encoder->base.crtc->state->active) { | |
16315 | /* | |
16316 | * This has to be done during hardware readout | |
16317 | * because anything calling .crtc_disable may | |
16318 | * rely on the connector_mask being accurate. | |
16319 | */ | |
16320 | encoder->base.crtc->state->connector_mask |= | |
16321 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16322 | encoder->base.crtc->state->encoder_mask |= |
16323 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16324 | } |
16325 | ||
24929352 DV |
16326 | } else { |
16327 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16328 | connector->base.encoder = NULL; | |
16329 | } | |
16330 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
16331 | connector->base.base.id, | |
c23cc417 | 16332 | connector->base.name, |
24929352 DV |
16333 | connector->base.encoder ? "enabled" : "disabled"); |
16334 | } | |
7f4c6284 VS |
16335 | |
16336 | for_each_intel_crtc(dev, crtc) { | |
16337 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16338 | ||
16339 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16340 | if (crtc->base.state->active) { | |
16341 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16342 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16343 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16344 | ||
16345 | /* | |
16346 | * The initial mode needs to be set in order to keep | |
16347 | * the atomic core happy. It wants a valid mode if the | |
16348 | * crtc's enabled, so we do the above call. | |
16349 | * | |
16350 | * At this point some state updated by the connectors | |
16351 | * in their ->detect() callback has not run yet, so | |
16352 | * no recalculation can be done yet. | |
16353 | * | |
16354 | * Even if we could do a recalculation and modeset | |
16355 | * right now it would cause a double modeset if | |
16356 | * fbdev or userspace chooses a different initial mode. | |
16357 | * | |
16358 | * If that happens, someone indicated they wanted a | |
16359 | * mode change, which means it's safe to do a full | |
16360 | * recalculation. | |
16361 | */ | |
16362 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16363 | |
16364 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16365 | update_scanline_offset(crtc); | |
7f4c6284 | 16366 | } |
e3b247da VS |
16367 | |
16368 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16369 | } |
30e984df DV |
16370 | } |
16371 | ||
043e9bda ML |
16372 | /* Scan out the current hw modeset state, |
16373 | * and sanitizes it to the current state | |
16374 | */ | |
16375 | static void | |
16376 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 16377 | { |
fac5e23e | 16378 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 16379 | enum pipe pipe; |
30e984df DV |
16380 | struct intel_crtc *crtc; |
16381 | struct intel_encoder *encoder; | |
35c95375 | 16382 | int i; |
30e984df DV |
16383 | |
16384 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16385 | |
16386 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16387 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16388 | intel_sanitize_encoder(encoder); |
16389 | } | |
16390 | ||
055e393f | 16391 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
16392 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16393 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
16394 | intel_dump_pipe_config(crtc, crtc->config, |
16395 | "[setup_hw_state]"); | |
24929352 | 16396 | } |
9a935856 | 16397 | |
d29b2f9d ACO |
16398 | intel_modeset_update_connector_atomic_state(dev); |
16399 | ||
35c95375 DV |
16400 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16401 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16402 | ||
2dd66ebd | 16403 | if (!pll->on || pll->active_mask) |
35c95375 DV |
16404 | continue; |
16405 | ||
16406 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
16407 | ||
2edd6443 | 16408 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
16409 | pll->on = false; |
16410 | } | |
16411 | ||
666a4537 | 16412 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
16413 | vlv_wm_get_hw_state(dev); |
16414 | else if (IS_GEN9(dev)) | |
3078999f PB |
16415 | skl_wm_get_hw_state(dev); |
16416 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 16417 | ilk_wm_get_hw_state(dev); |
292b990e ML |
16418 | |
16419 | for_each_intel_crtc(dev, crtc) { | |
16420 | unsigned long put_domains; | |
16421 | ||
74bff5f9 | 16422 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
16423 | if (WARN_ON(put_domains)) |
16424 | modeset_put_power_domains(dev_priv, put_domains); | |
16425 | } | |
16426 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
16427 | |
16428 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 16429 | } |
7d0bc1ea | 16430 | |
043e9bda ML |
16431 | void intel_display_resume(struct drm_device *dev) |
16432 | { | |
e2c8b870 ML |
16433 | struct drm_i915_private *dev_priv = to_i915(dev); |
16434 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
16435 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 16436 | int ret; |
f30da187 | 16437 | |
e2c8b870 | 16438 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
16439 | if (state) |
16440 | state->acquire_ctx = &ctx; | |
043e9bda | 16441 | |
ea49c9ac ML |
16442 | /* |
16443 | * This is a cludge because with real atomic modeset mode_config.mutex | |
16444 | * won't be taken. Unfortunately some probed state like | |
16445 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
16446 | * it here for now. | |
16447 | */ | |
16448 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 16449 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 16450 | |
73974893 ML |
16451 | while (1) { |
16452 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
16453 | if (ret != -EDEADLK) | |
16454 | break; | |
043e9bda | 16455 | |
e2c8b870 | 16456 | drm_modeset_backoff(&ctx); |
e2c8b870 | 16457 | } |
043e9bda | 16458 | |
73974893 ML |
16459 | if (!ret) |
16460 | ret = __intel_display_resume(dev, state); | |
16461 | ||
e2c8b870 ML |
16462 | drm_modeset_drop_locks(&ctx); |
16463 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 16464 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 16465 | |
e2c8b870 ML |
16466 | if (ret) { |
16467 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16468 | drm_atomic_state_free(state); | |
16469 | } | |
2c7111db CW |
16470 | } |
16471 | ||
16472 | void intel_modeset_gem_init(struct drm_device *dev) | |
16473 | { | |
dc97997a | 16474 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 16475 | struct drm_crtc *c; |
2ff8fde1 | 16476 | struct drm_i915_gem_object *obj; |
e0d6149b | 16477 | int ret; |
484b41dd | 16478 | |
dc97997a | 16479 | intel_init_gt_powersave(dev_priv); |
ae48434c | 16480 | |
1833b134 | 16481 | intel_modeset_init_hw(dev); |
02e792fb | 16482 | |
1ee8da6d | 16483 | intel_setup_overlay(dev_priv); |
484b41dd JB |
16484 | |
16485 | /* | |
16486 | * Make sure any fbs we allocated at startup are properly | |
16487 | * pinned & fenced. When we do the allocation it's too early | |
16488 | * for this. | |
16489 | */ | |
70e1e0ec | 16490 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16491 | obj = intel_fb_obj(c->primary->fb); |
16492 | if (obj == NULL) | |
484b41dd JB |
16493 | continue; |
16494 | ||
e0d6149b | 16495 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
16496 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
16497 | c->primary->state->rotation); | |
e0d6149b TU |
16498 | mutex_unlock(&dev->struct_mutex); |
16499 | if (ret) { | |
484b41dd JB |
16500 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16501 | to_intel_crtc(c)->pipe); | |
66e514c1 | 16502 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 16503 | c->primary->fb = NULL; |
36750f28 | 16504 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 16505 | update_state_fb(c->primary); |
36750f28 | 16506 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16507 | } |
16508 | } | |
1ebaa0b9 CW |
16509 | } |
16510 | ||
16511 | int intel_connector_register(struct drm_connector *connector) | |
16512 | { | |
16513 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
16514 | int ret; | |
16515 | ||
16516 | ret = intel_backlight_device_register(intel_connector); | |
16517 | if (ret) | |
16518 | goto err; | |
16519 | ||
16520 | return 0; | |
0962c3c9 | 16521 | |
1ebaa0b9 CW |
16522 | err: |
16523 | return ret; | |
79e53945 JB |
16524 | } |
16525 | ||
c191eca1 | 16526 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 16527 | { |
e63d87c0 | 16528 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 16529 | |
e63d87c0 | 16530 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 16531 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
16532 | } |
16533 | ||
79e53945 JB |
16534 | void intel_modeset_cleanup(struct drm_device *dev) |
16535 | { | |
fac5e23e | 16536 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 16537 | |
dc97997a | 16538 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 16539 | |
fd0c0642 DV |
16540 | /* |
16541 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16542 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16543 | * experience fancy races otherwise. |
16544 | */ | |
2aeb7d3a | 16545 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16546 | |
fd0c0642 DV |
16547 | /* |
16548 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16549 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16550 | */ | |
f87ea761 | 16551 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16552 | |
723bfd70 JB |
16553 | intel_unregister_dsm_handler(); |
16554 | ||
c937ab3e | 16555 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16556 | |
1630fe75 CW |
16557 | /* flush any delayed tasks or pending work */ |
16558 | flush_scheduled_work(); | |
16559 | ||
79e53945 | 16560 | drm_mode_config_cleanup(dev); |
4d7bb011 | 16561 | |
1ee8da6d | 16562 | intel_cleanup_overlay(dev_priv); |
ae48434c | 16563 | |
dc97997a | 16564 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
16565 | |
16566 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16567 | } |
16568 | ||
df0e9248 CW |
16569 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16570 | struct intel_encoder *encoder) | |
16571 | { | |
16572 | connector->encoder = encoder; | |
16573 | drm_mode_connector_attach_encoder(&connector->base, | |
16574 | &encoder->base); | |
79e53945 | 16575 | } |
28d52043 DA |
16576 | |
16577 | /* | |
16578 | * set vga decode state - true == enable VGA decode | |
16579 | */ | |
16580 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16581 | { | |
fac5e23e | 16582 | struct drm_i915_private *dev_priv = to_i915(dev); |
a885b3cc | 16583 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16584 | u16 gmch_ctrl; |
16585 | ||
75fa041d CW |
16586 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16587 | DRM_ERROR("failed to read control word\n"); | |
16588 | return -EIO; | |
16589 | } | |
16590 | ||
c0cc8a55 CW |
16591 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16592 | return 0; | |
16593 | ||
28d52043 DA |
16594 | if (state) |
16595 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16596 | else | |
16597 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16598 | |
16599 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16600 | DRM_ERROR("failed to write control word\n"); | |
16601 | return -EIO; | |
16602 | } | |
16603 | ||
28d52043 DA |
16604 | return 0; |
16605 | } | |
c4a1d9e4 | 16606 | |
c4a1d9e4 | 16607 | struct intel_display_error_state { |
ff57f1b0 PZ |
16608 | |
16609 | u32 power_well_driver; | |
16610 | ||
63b66e5b CW |
16611 | int num_transcoders; |
16612 | ||
c4a1d9e4 CW |
16613 | struct intel_cursor_error_state { |
16614 | u32 control; | |
16615 | u32 position; | |
16616 | u32 base; | |
16617 | u32 size; | |
52331309 | 16618 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16619 | |
16620 | struct intel_pipe_error_state { | |
ddf9c536 | 16621 | bool power_domain_on; |
c4a1d9e4 | 16622 | u32 source; |
f301b1e1 | 16623 | u32 stat; |
52331309 | 16624 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16625 | |
16626 | struct intel_plane_error_state { | |
16627 | u32 control; | |
16628 | u32 stride; | |
16629 | u32 size; | |
16630 | u32 pos; | |
16631 | u32 addr; | |
16632 | u32 surface; | |
16633 | u32 tile_offset; | |
52331309 | 16634 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16635 | |
16636 | struct intel_transcoder_error_state { | |
ddf9c536 | 16637 | bool power_domain_on; |
63b66e5b CW |
16638 | enum transcoder cpu_transcoder; |
16639 | ||
16640 | u32 conf; | |
16641 | ||
16642 | u32 htotal; | |
16643 | u32 hblank; | |
16644 | u32 hsync; | |
16645 | u32 vtotal; | |
16646 | u32 vblank; | |
16647 | u32 vsync; | |
16648 | } transcoder[4]; | |
c4a1d9e4 CW |
16649 | }; |
16650 | ||
16651 | struct intel_display_error_state * | |
c033666a | 16652 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 16653 | { |
c4a1d9e4 | 16654 | struct intel_display_error_state *error; |
63b66e5b CW |
16655 | int transcoders[] = { |
16656 | TRANSCODER_A, | |
16657 | TRANSCODER_B, | |
16658 | TRANSCODER_C, | |
16659 | TRANSCODER_EDP, | |
16660 | }; | |
c4a1d9e4 CW |
16661 | int i; |
16662 | ||
c033666a | 16663 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
16664 | return NULL; |
16665 | ||
9d1cb914 | 16666 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16667 | if (error == NULL) |
16668 | return NULL; | |
16669 | ||
c033666a | 16670 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
16671 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16672 | ||
055e393f | 16673 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16674 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16675 | __intel_display_power_is_enabled(dev_priv, |
16676 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16677 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16678 | continue; |
16679 | ||
5efb3e28 VS |
16680 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16681 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16682 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16683 | |
16684 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16685 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 16686 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 16687 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16688 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16689 | } | |
c033666a | 16690 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 16691 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 16692 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
16693 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
16694 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16695 | } | |
16696 | ||
c4a1d9e4 | 16697 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16698 | |
c033666a | 16699 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 16700 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16701 | } |
16702 | ||
4d1de975 | 16703 | /* Note: this does not include DSI transcoders. */ |
c033666a | 16704 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 16705 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
16706 | error->num_transcoders++; /* Account for eDP. */ |
16707 | ||
16708 | for (i = 0; i < error->num_transcoders; i++) { | |
16709 | enum transcoder cpu_transcoder = transcoders[i]; | |
16710 | ||
ddf9c536 | 16711 | error->transcoder[i].power_domain_on = |
f458ebbc | 16712 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16713 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16714 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16715 | continue; |
16716 | ||
63b66e5b CW |
16717 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16718 | ||
16719 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16720 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16721 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16722 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16723 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16724 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16725 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16726 | } |
16727 | ||
16728 | return error; | |
16729 | } | |
16730 | ||
edc3d884 MK |
16731 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16732 | ||
c4a1d9e4 | 16733 | void |
edc3d884 | 16734 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16735 | struct drm_device *dev, |
16736 | struct intel_display_error_state *error) | |
16737 | { | |
fac5e23e | 16738 | struct drm_i915_private *dev_priv = to_i915(dev); |
c4a1d9e4 CW |
16739 | int i; |
16740 | ||
63b66e5b CW |
16741 | if (!error) |
16742 | return; | |
16743 | ||
edc3d884 | 16744 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16745 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16746 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16747 | error->power_well_driver); |
055e393f | 16748 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16749 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16750 | err_printf(m, " Power: %s\n", |
87ad3212 | 16751 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16752 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16753 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16754 | |
16755 | err_printf(m, "Plane [%d]:\n", i); | |
16756 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16757 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16758 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16759 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16760 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16761 | } |
4b71a570 | 16762 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16763 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16764 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16765 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16766 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16767 | } |
16768 | ||
edc3d884 MK |
16769 | err_printf(m, "Cursor [%d]:\n", i); |
16770 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16771 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16772 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16773 | } |
63b66e5b CW |
16774 | |
16775 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16776 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16777 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16778 | err_printf(m, " Power: %s\n", |
87ad3212 | 16779 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16780 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16781 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16782 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16783 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16784 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16785 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16786 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16787 | } | |
c4a1d9e4 | 16788 | } |