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drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB
28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
c37efb99 39#include "i915_gem_dmabuf.h"
db18b6a6 40#include "intel_dsi.h"
e5510fac 41#include "i915_trace.h"
319c1d42 42#include <drm/drm_atomic.h>
c196e1d6 43#include <drm/drm_atomic_helper.h>
760285e7
DH
44#include <drm/drm_dp_helper.h>
45#include <drm/drm_crtc_helper.h>
465c120c
MR
46#include <drm/drm_plane_helper.h>
47#include <drm/drm_rect.h>
c0f372b3 48#include <linux/dma_remapping.h>
fd8e058a 49#include <linux/reservation.h>
79e53945 50
5a21b665
DV
51static bool is_mmio_work(struct intel_flip_work *work)
52{
53 return work->mmio_work.func;
54}
55
465c120c 56/* Primary plane formats for gen <= 3 */
568db4f2 57static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
465c120c 60 DRM_FORMAT_XRGB1555,
67fe7dc5 61 DRM_FORMAT_XRGB8888,
465c120c
MR
62};
63
64/* Primary plane formats for gen >= 4 */
568db4f2 65static const uint32_t i965_primary_formats[] = {
6c0fd451
DL
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72};
73
74static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
465c120c 78 DRM_FORMAT_XBGR8888,
67fe7dc5 79 DRM_FORMAT_ARGB8888,
465c120c
MR
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
465c120c 82 DRM_FORMAT_XBGR2101010,
ea916ea0
KM
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
465c120c
MR
87};
88
3d7d6510
MR
89/* Cursor formats */
90static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92};
93
f1f644dc 94static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 95 struct intel_crtc_state *pipe_config);
18442d08 96static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 97 struct intel_crtc_state *pipe_config);
f1f644dc 98
eb1bfe80
JB
99static int intel_framebuffer_init(struct drm_device *dev,
100 struct intel_framebuffer *ifb,
101 struct drm_mode_fb_cmd2 *mode_cmd,
102 struct drm_i915_gem_object *obj);
5b18e57c
DV
103static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
bc58be60 105static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
29407aab 106static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
29407aab 109static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97 110static void haswell_set_pipeconf(struct drm_crtc *crtc);
391bf048 111static void haswell_set_pipemisc(struct drm_crtc *crtc);
d288f65f 112static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 113 const struct intel_crtc_state *pipe_config);
d288f65f 114static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 115 const struct intel_crtc_state *pipe_config);
5a21b665
DV
116static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK
118static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
119 struct intel_crtc_state *crtc_state);
bfd16b2a
ML
120static void skylake_pfit_enable(struct intel_crtc *crtc);
121static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122static void ironlake_pfit_enable(struct intel_crtc *crtc);
043e9bda 123static void intel_modeset_setup_hw_state(struct drm_device *dev);
2622a081 124static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
4e5ca60f 125static int ilk_max_pixel_rate(struct drm_atomic_state *state);
324513c0 126static int bxt_calc_cdclk(int max_pixclk);
e7457a9a 127
d4906093 128struct intel_limit {
4c5def93
ACO
129 struct {
130 int min, max;
131 } dot, vco, n, m, m1, m2, p, p1;
132
133 struct {
134 int dot_limit;
135 int p2_slow, p2_fast;
136 } p2;
d4906093 137};
79e53945 138
bfa7df01
VS
139/* returns HPLL frequency in kHz */
140static int valleyview_get_vco(struct drm_i915_private *dev_priv)
141{
142 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
143
144 /* Obtain SKU information */
145 mutex_lock(&dev_priv->sb_lock);
146 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
147 CCK_FUSE_HPLL_FREQ_MASK;
148 mutex_unlock(&dev_priv->sb_lock);
149
150 return vco_freq[hpll_freq] * 1000;
151}
152
c30fec65
VS
153int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
154 const char *name, u32 reg, int ref_freq)
bfa7df01
VS
155{
156 u32 val;
157 int divider;
158
bfa7df01
VS
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
c30fec65
VS
169 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
170}
171
172static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
173 const char *name, u32 reg)
174{
175 if (dev_priv->hpll_freq == 0)
176 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
177
178 return vlv_get_cck_clock(dev_priv, name, reg,
179 dev_priv->hpll_freq);
bfa7df01
VS
180}
181
e7dc33f3
VS
182static int
183intel_pch_rawclk(struct drm_i915_private *dev_priv)
d2acd215 184{
e7dc33f3
VS
185 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
186}
d2acd215 187
e7dc33f3
VS
188static int
189intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
190{
19ab4ed3 191 /* RAWCLK_FREQ_VLV register updated from power well code */
35d38d1f
VS
192 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
193 CCK_DISPLAY_REF_CLOCK_CONTROL);
d2acd215
DV
194}
195
e7dc33f3
VS
196static int
197intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
79e50a4f 198{
79e50a4f
JN
199 uint32_t clkcfg;
200
e7dc33f3 201 /* hrawclock is 1/4 the FSB frequency */
79e50a4f
JN
202 clkcfg = I915_READ(CLKCFG);
203 switch (clkcfg & CLKCFG_FSB_MASK) {
204 case CLKCFG_FSB_400:
e7dc33f3 205 return 100000;
79e50a4f 206 case CLKCFG_FSB_533:
e7dc33f3 207 return 133333;
79e50a4f 208 case CLKCFG_FSB_667:
e7dc33f3 209 return 166667;
79e50a4f 210 case CLKCFG_FSB_800:
e7dc33f3 211 return 200000;
79e50a4f 212 case CLKCFG_FSB_1067:
e7dc33f3 213 return 266667;
79e50a4f 214 case CLKCFG_FSB_1333:
e7dc33f3 215 return 333333;
79e50a4f
JN
216 /* these two are just a guess; one of them might be right */
217 case CLKCFG_FSB_1600:
218 case CLKCFG_FSB_1600_ALT:
e7dc33f3 219 return 400000;
79e50a4f 220 default:
e7dc33f3 221 return 133333;
79e50a4f
JN
222 }
223}
224
19ab4ed3 225void intel_update_rawclk(struct drm_i915_private *dev_priv)
e7dc33f3
VS
226{
227 if (HAS_PCH_SPLIT(dev_priv))
228 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
229 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
230 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
231 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
232 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
233 else
234 return; /* no rawclk on other platforms, or no need to know it */
235
236 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
237}
238
bfa7df01
VS
239static void intel_update_czclk(struct drm_i915_private *dev_priv)
240{
666a4537 241 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
bfa7df01
VS
242 return;
243
244 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
245 CCK_CZ_CLOCK_CONTROL);
246
247 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
248}
249
021357ac 250static inline u32 /* units of 100MHz */
21a727b3
VS
251intel_fdi_link_freq(struct drm_i915_private *dev_priv,
252 const struct intel_crtc_state *pipe_config)
021357ac 253{
21a727b3
VS
254 if (HAS_DDI(dev_priv))
255 return pipe_config->port_clock; /* SPLL */
256 else if (IS_GEN5(dev_priv))
257 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
e3b247da 258 else
21a727b3 259 return 270000;
021357ac
CW
260}
261
1b6f4958 262static const struct intel_limit intel_limits_i8xx_dac = {
0206e353 263 .dot = { .min = 25000, .max = 350000 },
9c333719 264 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 265 .n = { .min = 2, .max = 16 },
0206e353
AJ
266 .m = { .min = 96, .max = 140 },
267 .m1 = { .min = 18, .max = 26 },
268 .m2 = { .min = 6, .max = 16 },
269 .p = { .min = 4, .max = 128 },
270 .p1 = { .min = 2, .max = 33 },
273e27ca
EA
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP
273};
274
1b6f4958 275static const struct intel_limit intel_limits_i8xx_dvo = {
5d536e28 276 .dot = { .min = 25000, .max = 350000 },
9c333719 277 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 278 .n = { .min = 2, .max = 16 },
5d536e28
DV
279 .m = { .min = 96, .max = 140 },
280 .m1 = { .min = 18, .max = 26 },
281 .m2 = { .min = 6, .max = 16 },
282 .p = { .min = 4, .max = 128 },
283 .p1 = { .min = 2, .max = 33 },
284 .p2 = { .dot_limit = 165000,
285 .p2_slow = 4, .p2_fast = 4 },
286};
287
1b6f4958 288static const struct intel_limit intel_limits_i8xx_lvds = {
0206e353 289 .dot = { .min = 25000, .max = 350000 },
9c333719 290 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 291 .n = { .min = 2, .max = 16 },
0206e353
AJ
292 .m = { .min = 96, .max = 140 },
293 .m1 = { .min = 18, .max = 26 },
294 .m2 = { .min = 6, .max = 16 },
295 .p = { .min = 4, .max = 128 },
296 .p1 = { .min = 1, .max = 6 },
273e27ca
EA
297 .p2 = { .dot_limit = 165000,
298 .p2_slow = 14, .p2_fast = 7 },
e4b36699 299};
273e27ca 300
1b6f4958 301static const struct intel_limit intel_limits_i9xx_sdvo = {
0206e353
AJ
302 .dot = { .min = 20000, .max = 400000 },
303 .vco = { .min = 1400000, .max = 2800000 },
304 .n = { .min = 1, .max = 6 },
305 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ
306 .m1 = { .min = 8, .max = 18 },
307 .m2 = { .min = 3, .max = 7 },
0206e353
AJ
308 .p = { .min = 5, .max = 80 },
309 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
310 .p2 = { .dot_limit = 200000,
311 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
312};
313
1b6f4958 314static const struct intel_limit intel_limits_i9xx_lvds = {
0206e353
AJ
315 .dot = { .min = 20000, .max = 400000 },
316 .vco = { .min = 1400000, .max = 2800000 },
317 .n = { .min = 1, .max = 6 },
318 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ
319 .m1 = { .min = 8, .max = 18 },
320 .m2 = { .min = 3, .max = 7 },
0206e353
AJ
321 .p = { .min = 7, .max = 98 },
322 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
323 .p2 = { .dot_limit = 112000,
324 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP
325};
326
273e27ca 327
1b6f4958 328static const struct intel_limit intel_limits_g4x_sdvo = {
273e27ca
EA
329 .dot = { .min = 25000, .max = 270000 },
330 .vco = { .min = 1750000, .max = 3500000},
331 .n = { .min = 1, .max = 4 },
332 .m = { .min = 104, .max = 138 },
333 .m1 = { .min = 17, .max = 23 },
334 .m2 = { .min = 5, .max = 11 },
335 .p = { .min = 10, .max = 30 },
336 .p1 = { .min = 1, .max = 3},
337 .p2 = { .dot_limit = 270000,
338 .p2_slow = 10,
339 .p2_fast = 10
044c7c41 340 },
e4b36699
KP
341};
342
1b6f4958 343static const struct intel_limit intel_limits_g4x_hdmi = {
273e27ca
EA
344 .dot = { .min = 22000, .max = 400000 },
345 .vco = { .min = 1750000, .max = 3500000},
346 .n = { .min = 1, .max = 4 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 16, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 5, .max = 80 },
351 .p1 = { .min = 1, .max = 8},
352 .p2 = { .dot_limit = 165000,
353 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
354};
355
1b6f4958 356static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
273e27ca
EA
357 .dot = { .min = 20000, .max = 115000 },
358 .vco = { .min = 1750000, .max = 3500000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 104, .max = 138 },
361 .m1 = { .min = 17, .max = 23 },
362 .m2 = { .min = 5, .max = 11 },
363 .p = { .min = 28, .max = 112 },
364 .p1 = { .min = 2, .max = 8 },
365 .p2 = { .dot_limit = 0,
366 .p2_slow = 14, .p2_fast = 14
044c7c41 367 },
e4b36699
KP
368};
369
1b6f4958 370static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA
371 .dot = { .min = 80000, .max = 224000 },
372 .vco = { .min = 1750000, .max = 3500000 },
373 .n = { .min = 1, .max = 3 },
374 .m = { .min = 104, .max = 138 },
375 .m1 = { .min = 17, .max = 23 },
376 .m2 = { .min = 5, .max = 11 },
377 .p = { .min = 14, .max = 42 },
378 .p1 = { .min = 2, .max = 6 },
379 .p2 = { .dot_limit = 0,
380 .p2_slow = 7, .p2_fast = 7
044c7c41 381 },
e4b36699
KP
382};
383
1b6f4958 384static const struct intel_limit intel_limits_pineview_sdvo = {
0206e353
AJ
385 .dot = { .min = 20000, .max = 400000},
386 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 387 /* Pineview's Ncounter is a ring counter */
0206e353
AJ
388 .n = { .min = 3, .max = 6 },
389 .m = { .min = 2, .max = 256 },
273e27ca 390 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ
391 .m1 = { .min = 0, .max = 0 },
392 .m2 = { .min = 0, .max = 254 },
393 .p = { .min = 5, .max = 80 },
394 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
395 .p2 = { .dot_limit = 200000,
396 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
397};
398
1b6f4958 399static const struct intel_limit intel_limits_pineview_lvds = {
0206e353
AJ
400 .dot = { .min = 20000, .max = 400000 },
401 .vco = { .min = 1700000, .max = 3500000 },
402 .n = { .min = 3, .max = 6 },
403 .m = { .min = 2, .max = 256 },
404 .m1 = { .min = 0, .max = 0 },
405 .m2 = { .min = 0, .max = 254 },
406 .p = { .min = 7, .max = 112 },
407 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
408 .p2 = { .dot_limit = 112000,
409 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP
410};
411
273e27ca
EA
412/* Ironlake / Sandybridge
413 *
414 * We calculate clock using (register_value + 2) for N/M1/M2, so here
415 * the range value for them is (actual_value - 2).
416 */
1b6f4958 417static const struct intel_limit intel_limits_ironlake_dac = {
273e27ca
EA
418 .dot = { .min = 25000, .max = 350000 },
419 .vco = { .min = 1760000, .max = 3510000 },
420 .n = { .min = 1, .max = 5 },
421 .m = { .min = 79, .max = 127 },
422 .m1 = { .min = 12, .max = 22 },
423 .m2 = { .min = 5, .max = 9 },
424 .p = { .min = 5, .max = 80 },
425 .p1 = { .min = 1, .max = 8 },
426 .p2 = { .dot_limit = 225000,
427 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
428};
429
1b6f4958 430static const struct intel_limit intel_limits_ironlake_single_lvds = {
273e27ca
EA
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 3 },
434 .m = { .min = 79, .max = 118 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW
441};
442
1b6f4958 443static const struct intel_limit intel_limits_ironlake_dual_lvds = {
273e27ca
EA
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 127 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 56 },
451 .p1 = { .min = 2, .max = 8 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW
454};
455
273e27ca 456/* LVDS 100mhz refclk limits. */
1b6f4958 457static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA
458 .dot = { .min = 25000, .max = 350000 },
459 .vco = { .min = 1760000, .max = 3510000 },
460 .n = { .min = 1, .max = 2 },
461 .m = { .min = 79, .max = 126 },
462 .m1 = { .min = 12, .max = 22 },
463 .m2 = { .min = 5, .max = 9 },
464 .p = { .min = 28, .max = 112 },
0206e353 465 .p1 = { .min = 2, .max = 8 },
273e27ca
EA
466 .p2 = { .dot_limit = 225000,
467 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW
468};
469
1b6f4958 470static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA
471 .dot = { .min = 25000, .max = 350000 },
472 .vco = { .min = 1760000, .max = 3510000 },
473 .n = { .min = 1, .max = 3 },
474 .m = { .min = 79, .max = 126 },
475 .m1 = { .min = 12, .max = 22 },
476 .m2 = { .min = 5, .max = 9 },
477 .p = { .min = 14, .max = 42 },
0206e353 478 .p1 = { .min = 2, .max = 6 },
273e27ca
EA
479 .p2 = { .dot_limit = 225000,
480 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY
481};
482
1b6f4958 483static const struct intel_limit intel_limits_vlv = {
f01b7962
VS
484 /*
485 * These are the data rate limits (measured in fast clocks)
486 * since those are the strictest limits we have. The fast
487 * clock and actual rate limits are more relaxed, so checking
488 * them would make no difference.
489 */
490 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 491 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 492 .n = { .min = 1, .max = 7 },
a0c4da24
JB
493 .m1 = { .min = 2, .max = 3 },
494 .m2 = { .min = 11, .max = 156 },
b99ab663 495 .p1 = { .min = 2, .max = 3 },
5fdc9c49 496 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB
497};
498
1b6f4958 499static const struct intel_limit intel_limits_chv = {
ef9348c8
CML
500 /*
501 * These are the data rate limits (measured in fast clocks)
502 * since those are the strictest limits we have. The fast
503 * clock and actual rate limits are more relaxed, so checking
504 * them would make no difference.
505 */
506 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 507 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML
508 .n = { .min = 1, .max = 1 },
509 .m1 = { .min = 2, .max = 2 },
510 .m2 = { .min = 24 << 22, .max = 175 << 22 },
511 .p1 = { .min = 2, .max = 4 },
512 .p2 = { .p2_slow = 1, .p2_fast = 14 },
513};
514
1b6f4958 515static const struct intel_limit intel_limits_bxt = {
5ab7b0b7
ID
516 /* FIXME: find real dot limits */
517 .dot = { .min = 0, .max = INT_MAX },
e6292556 518 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID
519 .n = { .min = 1, .max = 1 },
520 .m1 = { .min = 2, .max = 2 },
521 /* FIXME: find real m2 limits */
522 .m2 = { .min = 2 << 22, .max = 255 << 22 },
523 .p1 = { .min = 2, .max = 4 },
524 .p2 = { .p2_slow = 1, .p2_fast = 20 },
525};
526
cdba954e
ACO
527static bool
528needs_modeset(struct drm_crtc_state *state)
529{
fc596660 530 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO
531}
532
e0638cdf
PZ
533/**
534 * Returns whether any output on the specified pipe is of the specified type
535 */
4093561b 536bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 537{
409ee761 538 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ
539 struct intel_encoder *encoder;
540
409ee761 541 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ
542 if (encoder->type == type)
543 return true;
544
545 return false;
546}
547
d0737e1d
ACO
548/**
549 * Returns whether any output on the specified pipe will have the specified
550 * type after a staged modeset is complete, i.e., the same as
551 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
552 * encoder->crtc.
553 */
a93e255f
ACO
554static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
555 int type)
d0737e1d 556{
a93e255f 557 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 558 struct drm_connector *connector;
a93e255f 559 struct drm_connector_state *connector_state;
d0737e1d 560 struct intel_encoder *encoder;
a93e255f
ACO
561 int i, num_connectors = 0;
562
da3ced29 563 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO
564 if (connector_state->crtc != crtc_state->base.crtc)
565 continue;
566
567 num_connectors++;
d0737e1d 568
a93e255f
ACO
569 encoder = to_intel_encoder(connector_state->best_encoder);
570 if (encoder->type == type)
d0737e1d 571 return true;
a93e255f
ACO
572 }
573
574 WARN_ON(num_connectors == 0);
d0737e1d
ACO
575
576 return false;
577}
578
dccbea3b
ID
579/*
580 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
581 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
582 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
583 * The helpers' return value is the rate of the clock that is fed to the
584 * display engine's pipe which can be the above fast dot clock rate or a
585 * divided-down version of it.
586 */
f2b115e6 587/* m1 is reserved as 0 in Pineview, n is a ring counter */
9e2c8475 588static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
79e53945 589{
2177832f
SL
590 clock->m = clock->m2 + 2;
591 clock->p = clock->p1 * clock->p2;
ed5ca77e 592 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 593 return 0;
fb03ac01
VS
594 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
595 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
596
597 return clock->dot;
2177832f
SL
598}
599
7429e9d4
DV
600static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
601{
602 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
603}
604
9e2c8475 605static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
2177832f 606{
7429e9d4 607 clock->m = i9xx_dpll_compute_m(clock);
79e53945 608 clock->p = clock->p1 * clock->p2;
ed5ca77e 609 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 610 return 0;
fb03ac01
VS
611 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
612 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
613
614 return clock->dot;
79e53945
JB
615}
616
9e2c8475 617static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
589eca67
ID
618{
619 clock->m = clock->m1 * clock->m2;
620 clock->p = clock->p1 * clock->p2;
621 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 622 return 0;
589eca67
ID
623 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
624 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
625
626 return clock->dot / 5;
589eca67
ID
627}
628
9e2c8475 629int chv_calc_dpll_params(int refclk, struct dpll *clock)
ef9348c8
CML
630{
631 clock->m = clock->m1 * clock->m2;
632 clock->p = clock->p1 * clock->p2;
633 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 634 return 0;
ef9348c8
CML
635 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
636 clock->n << 22);
637 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
638
639 return clock->dot / 5;
ef9348c8
CML
640}
641
7c04d1d9 642#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB
643/**
644 * Returns whether the given set of divisors are valid for a given refclk with
645 * the given connectors.
646 */
647
1b894b59 648static bool intel_PLL_is_valid(struct drm_device *dev,
1b6f4958 649 const struct intel_limit *limit,
9e2c8475 650 const struct dpll *clock)
79e53945 651{
f01b7962
VS
652 if (clock->n < limit->n.min || limit->n.max < clock->n)
653 INTELPllInvalid("n out of range\n");
79e53945 654 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 655 INTELPllInvalid("p1 out of range\n");
79e53945 656 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 657 INTELPllInvalid("m2 out of range\n");
79e53945 658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 659 INTELPllInvalid("m1 out of range\n");
f01b7962 660
666a4537
WB
661 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
662 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS
663 if (clock->m1 <= clock->m2)
664 INTELPllInvalid("m1 <= m2\n");
665
666a4537 666 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS
667 if (clock->p < limit->p.min || limit->p.max < clock->p)
668 INTELPllInvalid("p out of range\n");
669 if (clock->m < limit->m.min || limit->m.max < clock->m)
670 INTELPllInvalid("m out of range\n");
671 }
672
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB
680
681 return true;
682}
683
3b1429d9 684static int
1b6f4958 685i9xx_select_p2_div(const struct intel_limit *limit,
3b1429d9
VS
686 const struct intel_crtc_state *crtc_state,
687 int target)
79e53945 688{
3b1429d9 689 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 690
a93e255f 691 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 692 /*
a210b028
DV
693 * For LVDS just rely on its current settings for dual-channel.
694 * We haven't figured out how to reliably set up different
695 * single/dual channel state, if we even can.
79e53945 696 */
1974cad0 697 if (intel_is_dual_link_lvds(dev))
3b1429d9 698 return limit->p2.p2_fast;
79e53945 699 else
3b1429d9 700 return limit->p2.p2_slow;
79e53945
JB
701 } else {
702 if (target < limit->p2.dot_limit)
3b1429d9 703 return limit->p2.p2_slow;
79e53945 704 else
3b1429d9 705 return limit->p2.p2_fast;
79e53945 706 }
3b1429d9
VS
707}
708
70e8aa21
ACO
709/*
710 * Returns a set of divisors for the desired target clock with the given
711 * refclk, or FALSE. The returned values represent the clock equation:
712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
713 *
714 * Target and reference clocks are specified in kHz.
715 *
716 * If match_clock is provided, then best_clock P divider must match the P
717 * divider from @match_clock used for LVDS downclocking.
718 */
3b1429d9 719static bool
1b6f4958 720i9xx_find_best_dpll(const struct intel_limit *limit,
3b1429d9 721 struct intel_crtc_state *crtc_state,
9e2c8475
ACO
722 int target, int refclk, struct dpll *match_clock,
723 struct dpll *best_clock)
3b1429d9
VS
724{
725 struct drm_device *dev = crtc_state->base.crtc->dev;
9e2c8475 726 struct dpll clock;
3b1429d9 727 int err = target;
79e53945 728
0206e353 729 memset(best_clock, 0, sizeof(*best_clock));
79e53945 730
3b1429d9
VS
731 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
732
42158660
ZY
733 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
734 clock.m1++) {
735 for (clock.m2 = limit->m2.min;
736 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 737 if (clock.m2 >= clock.m1)
42158660
ZY
738 break;
739 for (clock.n = limit->n.min;
740 clock.n <= limit->n.max; clock.n++) {
741 for (clock.p1 = limit->p1.min;
742 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB
743 int this_err;
744
dccbea3b 745 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV
746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
748 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752
753 this_err = abs(clock.dot - target);
754 if (this_err < err) {
755 *best_clock = clock;
756 err = this_err;
757 }
758 }
759 }
760 }
761 }
762
763 return (err != target);
764}
765
70e8aa21
ACO
766/*
767 * Returns a set of divisors for the desired target clock with the given
768 * refclk, or FALSE. The returned values represent the clock equation:
769 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
770 *
771 * Target and reference clocks are specified in kHz.
772 *
773 * If match_clock is provided, then best_clock P divider must match the P
774 * divider from @match_clock used for LVDS downclocking.
775 */
ac58c3f0 776static bool
1b6f4958 777pnv_find_best_dpll(const struct intel_limit *limit,
a93e255f 778 struct intel_crtc_state *crtc_state,
9e2c8475
ACO
779 int target, int refclk, struct dpll *match_clock,
780 struct dpll *best_clock)
79e53945 781{
3b1429d9 782 struct drm_device *dev = crtc_state->base.crtc->dev;
9e2c8475 783 struct dpll clock;
79e53945
JB
784 int err = target;
785
0206e353 786 memset(best_clock, 0, sizeof(*best_clock));
79e53945 787
3b1429d9
VS
788 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
789
42158660
ZY
790 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
791 clock.m1++) {
792 for (clock.m2 = limit->m2.min;
793 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY
794 for (clock.n = limit->n.min;
795 clock.n <= limit->n.max; clock.n++) {
796 for (clock.p1 = limit->p1.min;
797 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB
798 int this_err;
799
dccbea3b 800 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW
801 if (!intel_PLL_is_valid(dev, limit,
802 &clock))
79e53945 803 continue;
cec2f356
SP
804 if (match_clock &&
805 clock.p != match_clock->p)
806 continue;
79e53945
JB
807
808 this_err = abs(clock.dot - target);
809 if (this_err < err) {
810 *best_clock = clock;
811 err = this_err;
812 }
813 }
814 }
815 }
816 }
817
818 return (err != target);
819}
820
997c030c
ACO
821/*
822 * Returns a set of divisors for the desired target clock with the given
823 * refclk, or FALSE. The returned values represent the clock equation:
824 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
70e8aa21
ACO
825 *
826 * Target and reference clocks are specified in kHz.
827 *
828 * If match_clock is provided, then best_clock P divider must match the P
829 * divider from @match_clock used for LVDS downclocking.
997c030c 830 */
d4906093 831static bool
1b6f4958 832g4x_find_best_dpll(const struct intel_limit *limit,
a93e255f 833 struct intel_crtc_state *crtc_state,
9e2c8475
ACO
834 int target, int refclk, struct dpll *match_clock,
835 struct dpll *best_clock)
d4906093 836{
3b1429d9 837 struct drm_device *dev = crtc_state->base.crtc->dev;
9e2c8475 838 struct dpll clock;
d4906093 839 int max_n;
3b1429d9 840 bool found = false;
6ba770dc
AJ
841 /* approximately equals target * 0.00585 */
842 int err_most = (target >> 8) + (target >> 9);
d4906093
ML
843
844 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS
845
846 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
847
d4906093 848 max_n = limit->n.max;
f77f13e2 849 /* based on hardware requirement, prefer smaller n to precision */
d4906093 850 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 851 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML
852 for (clock.m1 = limit->m1.max;
853 clock.m1 >= limit->m1.min; clock.m1--) {
854 for (clock.m2 = limit->m2.max;
855 clock.m2 >= limit->m2.min; clock.m2--) {
856 for (clock.p1 = limit->p1.max;
857 clock.p1 >= limit->p1.min; clock.p1--) {
858 int this_err;
859
dccbea3b 860 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW
861 if (!intel_PLL_is_valid(dev, limit,
862 &clock))
d4906093 863 continue;
1b894b59
CW
864
865 this_err = abs(clock.dot - target);
d4906093
ML
866 if (this_err < err_most) {
867 *best_clock = clock;
868 err_most = this_err;
869 max_n = clock.n;
870 found = true;
871 }
872 }
873 }
874 }
875 }
2c07245f
ZW
876 return found;
877}
878
d5dd62bd
ID
879/*
880 * Check if the calculated PLL configuration is more optimal compared to the
881 * best configuration and error found so far. Return the calculated error.
882 */
883static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
9e2c8475
ACO
884 const struct dpll *calculated_clock,
885 const struct dpll *best_clock,
d5dd62bd
ID
886 unsigned int best_error_ppm,
887 unsigned int *error_ppm)
888{
9ca3ba01
ID
889 /*
890 * For CHV ignore the error and consider only the P value.
891 * Prefer a bigger P value based on HW requirements.
892 */
893 if (IS_CHERRYVIEW(dev)) {
894 *error_ppm = 0;
895
896 return calculated_clock->p > best_clock->p;
897 }
898
24be4e46
ID
899 if (WARN_ON_ONCE(!target_freq))
900 return false;
901
d5dd62bd
ID
902 *error_ppm = div_u64(1000000ULL *
903 abs(target_freq - calculated_clock->dot),
904 target_freq);
905 /*
906 * Prefer a better P value over a better (smaller) error if the error
907 * is small. Ensure this preference for future configurations too by
908 * setting the error to 0.
909 */
910 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
911 *error_ppm = 0;
912
913 return true;
914 }
915
916 return *error_ppm + 10 < best_error_ppm;
917}
918
65b3d6a9
ACO
919/*
920 * Returns a set of divisors for the desired target clock with the given
921 * refclk, or FALSE. The returned values represent the clock equation:
922 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
923 */
a0c4da24 924static bool
1b6f4958 925vlv_find_best_dpll(const struct intel_limit *limit,
a93e255f 926 struct intel_crtc_state *crtc_state,
9e2c8475
ACO
927 int target, int refclk, struct dpll *match_clock,
928 struct dpll *best_clock)
a0c4da24 929{
a93e255f 930 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 931 struct drm_device *dev = crtc->base.dev;
9e2c8475 932 struct dpll clock;
69e4f900 933 unsigned int bestppm = 1000000;
27e639bf
VS
934 /* min update 19.2 MHz */
935 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 936 bool found = false;
a0c4da24 937
6b4bf1c4
VS
938 target *= 5; /* fast clock */
939
940 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB
941
942 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 943 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 944 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 945 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 947 clock.p = clock.p1 * clock.p2;
a0c4da24 948 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 949 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 950 unsigned int ppm;
69e4f900 951
6b4bf1c4
VS
952 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
953 refclk * clock.m1);
954
dccbea3b 955 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 956
f01b7962
VS
957 if (!intel_PLL_is_valid(dev, limit,
958 &clock))
43b0ac53
VS
959 continue;
960
d5dd62bd
ID
961 if (!vlv_PLL_is_optimal(dev, target,
962 &clock,
963 best_clock,
964 bestppm, &ppm))
965 continue;
6b4bf1c4 966
d5dd62bd
ID
967 *best_clock = clock;
968 bestppm = ppm;
969 found = true;
a0c4da24
JB
970 }
971 }
972 }
973 }
a0c4da24 974
49e497ef 975 return found;
a0c4da24 976}
a4fc5ed6 977
65b3d6a9
ACO
978/*
979 * Returns a set of divisors for the desired target clock with the given
980 * refclk, or FALSE. The returned values represent the clock equation:
981 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
982 */
ef9348c8 983static bool
1b6f4958 984chv_find_best_dpll(const struct intel_limit *limit,
a93e255f 985 struct intel_crtc_state *crtc_state,
9e2c8475
ACO
986 int target, int refclk, struct dpll *match_clock,
987 struct dpll *best_clock)
ef9348c8 988{
a93e255f 989 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 990 struct drm_device *dev = crtc->base.dev;
9ca3ba01 991 unsigned int best_error_ppm;
9e2c8475 992 struct dpll clock;
ef9348c8
CML
993 uint64_t m2;
994 int found = false;
995
996 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 997 best_error_ppm = 1000000;
ef9348c8
CML
998
999 /*
1000 * Based on hardware doc, the n always set to 1, and m1 always
1001 * set to 2. If requires to support 200Mhz refclk, we need to
1002 * revisit this because n may not 1 anymore.
1003 */
1004 clock.n = 1, clock.m1 = 2;
1005 target *= 5; /* fast clock */
1006
1007 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1008 for (clock.p2 = limit->p2.p2_fast;
1009 clock.p2 >= limit->p2.p2_slow;
1010 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 1011 unsigned int error_ppm;
ef9348c8
CML
1012
1013 clock.p = clock.p1 * clock.p2;
1014
1015 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1016 clock.n) << 22, refclk * clock.m1);
1017
1018 if (m2 > INT_MAX/clock.m1)
1019 continue;
1020
1021 clock.m2 = m2;
1022
dccbea3b 1023 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML
1024
1025 if (!intel_PLL_is_valid(dev, limit, &clock))
1026 continue;
1027
9ca3ba01
ID
1028 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1029 best_error_ppm, &error_ppm))
1030 continue;
1031
1032 *best_clock = clock;
1033 best_error_ppm = error_ppm;
1034 found = true;
ef9348c8
CML
1035 }
1036 }
1037
1038 return found;
1039}
1040
5ab7b0b7 1041bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
9e2c8475 1042 struct dpll *best_clock)
5ab7b0b7 1043{
65b3d6a9 1044 int refclk = 100000;
1b6f4958 1045 const struct intel_limit *limit = &intel_limits_bxt;
5ab7b0b7 1046
65b3d6a9 1047 return chv_find_best_dpll(limit, crtc_state,
5ab7b0b7
ID
1048 target_clock, refclk, NULL, best_clock);
1049}
1050
20ddf665
VS
1051bool intel_crtc_active(struct drm_crtc *crtc)
1052{
1053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1054
1055 /* Be paranoid as we can arrive here with only partial
1056 * state retrieved from the hardware during setup.
1057 *
241bfc38 1058 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS
1059 * as Haswell has gained clock readout/fastboot support.
1060 *
66e514c1 1061 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1062 * properly reconstruct framebuffers.
c3d1f436
MR
1063 *
1064 * FIXME: The intel_crtc->active here should be switched to
1065 * crtc->state->active once we have proper CRTC states wired up
1066 * for atomic.
20ddf665 1067 */
c3d1f436 1068 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1069 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS
1070}
1071
a5c961d1
PZ
1072enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1073 enum pipe pipe)
1074{
1075 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1077
6e3c9717 1078 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ
1079}
1080
fbf49ea2
VS
1081static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1082{
1083 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1084 i915_reg_t reg = PIPEDSL(pipe);
fbf49ea2
VS
1085 u32 line1, line2;
1086 u32 line_mask;
1087
1088 if (IS_GEN2(dev))
1089 line_mask = DSL_LINEMASK_GEN2;
1090 else
1091 line_mask = DSL_LINEMASK_GEN3;
1092
1093 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1094 msleep(5);
fbf49ea2
VS
1095 line2 = I915_READ(reg) & line_mask;
1096
1097 return line1 == line2;
1098}
1099
ab7ad7f6
KP
1100/*
1101 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1102 * @crtc: crtc whose pipe to wait for
9d0498a2
JB
1103 *
1104 * After disabling a pipe, we can't wait for vblank in the usual way,
1105 * spinning on the vblank interrupt status bit, since we won't actually
1106 * see an interrupt when the pipe is disabled.
1107 *
ab7ad7f6
KP
1108 * On Gen4 and above:
1109 * wait for the pipe register state bit to turn off
1110 *
1111 * Otherwise:
1112 * wait for the display line value to settle (it usually
1113 * ends up stopping at the start of the next frame).
58e10eb9 1114 *
9d0498a2 1115 */
575f7ab7 1116static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1117{
575f7ab7 1118 struct drm_device *dev = crtc->base.dev;
9d0498a2 1119 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1120 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1121 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP
1122
1123 if (INTEL_INFO(dev)->gen >= 4) {
f0f59a00 1124 i915_reg_t reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP
1125
1126 /* Wait for the Pipe State to go off */
b8511f53
CW
1127 if (intel_wait_for_register(dev_priv,
1128 reg, I965_PIPECONF_ACTIVE, 0,
1129 100))
284637d9 1130 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1131 } else {
ab7ad7f6 1132 /* Wait for the display line to settle */
fbf49ea2 1133 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1134 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1135 }
79e53945
JB
1136}
1137
b24e7179 1138/* Only for pre-ILK configs */
55607e8a
DV
1139void assert_pll(struct drm_i915_private *dev_priv,
1140 enum pipe pipe, bool state)
b24e7179 1141{
b24e7179
JB
1142 u32 val;
1143 bool cur_state;
1144
649636ef 1145 val = I915_READ(DPLL(pipe));
b24e7179 1146 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1147 I915_STATE_WARN(cur_state != state,
b24e7179 1148 "PLL state assertion failure (expected %s, current %s)\n",
87ad3212 1149 onoff(state), onoff(cur_state));
b24e7179 1150}
b24e7179 1151
23538ef1 1152/* XXX: the dsi pll is shared between MIPI DSI ports */
8563b1e8 1153void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
23538ef1
JN
1154{
1155 u32 val;
1156 bool cur_state;
1157
a580516d 1158 mutex_lock(&dev_priv->sb_lock);
23538ef1 1159 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1160 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN
1161
1162 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1163 I915_STATE_WARN(cur_state != state,
23538ef1 1164 "DSI PLL state assertion failure (expected %s, current %s)\n",
87ad3212 1165 onoff(state), onoff(cur_state));
23538ef1 1166}
23538ef1 1167
040484af
JB
1168static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1169 enum pipe pipe, bool state)
1170{
040484af 1171 bool cur_state;
ad80a810
PZ
1172 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1173 pipe);
040484af 1174
2d1fe073 1175 if (HAS_DDI(dev_priv)) {
affa9354 1176 /* DDI does not have a specific FDI_TX register */
649636ef 1177 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
ad80a810 1178 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7 1179 } else {
649636ef 1180 u32 val = I915_READ(FDI_TX_CTL(pipe));
bf507ef7
ED
1181 cur_state = !!(val & FDI_TX_ENABLE);
1182 }
e2c719b7 1183 I915_STATE_WARN(cur_state != state,
040484af 1184 "FDI TX state assertion failure (expected %s, current %s)\n",
87ad3212 1185 onoff(state), onoff(cur_state));
040484af
JB
1186}
1187#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1188#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1189
1190static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1191 enum pipe pipe, bool state)
1192{
040484af
JB
1193 u32 val;
1194 bool cur_state;
1195
649636ef 1196 val = I915_READ(FDI_RX_CTL(pipe));
d63fa0dc 1197 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1198 I915_STATE_WARN(cur_state != state,
040484af 1199 "FDI RX state assertion failure (expected %s, current %s)\n",
87ad3212 1200 onoff(state), onoff(cur_state));
040484af
JB
1201}
1202#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1203#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1204
1205static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1206 enum pipe pipe)
1207{
040484af
JB
1208 u32 val;
1209
1210 /* ILK FDI PLL is always enabled */
7e22dbbb 1211 if (IS_GEN5(dev_priv))
040484af
JB
1212 return;
1213
bf507ef7 1214 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
2d1fe073 1215 if (HAS_DDI(dev_priv))
bf507ef7
ED
1216 return;
1217
649636ef 1218 val = I915_READ(FDI_TX_CTL(pipe));
e2c719b7 1219 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB
1220}
1221
55607e8a
DV
1222void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1223 enum pipe pipe, bool state)
040484af 1224{
040484af 1225 u32 val;
55607e8a 1226 bool cur_state;
040484af 1227
649636ef 1228 val = I915_READ(FDI_RX_CTL(pipe));
55607e8a 1229 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1230 I915_STATE_WARN(cur_state != state,
55607e8a 1231 "FDI RX PLL assertion failure (expected %s, current %s)\n",
87ad3212 1232 onoff(state), onoff(cur_state));
040484af
JB
1233}
1234
b680c37a
DV
1235void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1236 enum pipe pipe)
ea0760cf 1237{
bedd4dba 1238 struct drm_device *dev = dev_priv->dev;
f0f59a00 1239 i915_reg_t pp_reg;
ea0760cf
JB
1240 u32 val;
1241 enum pipe panel_pipe = PIPE_A;
0de3b485 1242 bool locked = true;
ea0760cf 1243
bedd4dba
JN
1244 if (WARN_ON(HAS_DDI(dev)))
1245 return;
1246
1247 if (HAS_PCH_SPLIT(dev)) {
1248 u32 port_sel;
1249
ea0760cf 1250 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN
1251 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1252
1253 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1254 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1255 panel_pipe = PIPE_B;
1256 /* XXX: else fix for eDP */
666a4537 1257 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
bedd4dba
JN
1258 /* presumably write lock depends on pipe, not port select */
1259 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1260 panel_pipe = pipe;
ea0760cf
JB
1261 } else {
1262 pp_reg = PP_CONTROL;
bedd4dba
JN
1263 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1264 panel_pipe = PIPE_B;
ea0760cf
JB
1265 }
1266
1267 val = I915_READ(pp_reg);
1268 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1269 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB
1270 locked = false;
1271
e2c719b7 1272 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1273 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1274 pipe_name(pipe));
ea0760cf
JB
1275}
1276
93ce0ba6
JN
1277static void assert_cursor(struct drm_i915_private *dev_priv,
1278 enum pipe pipe, bool state)
1279{
1280 struct drm_device *dev = dev_priv->dev;
1281 bool cur_state;
1282
d9d82081 1283 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 1284 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
d9d82081 1285 else
5efb3e28 1286 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1287
e2c719b7 1288 I915_STATE_WARN(cur_state != state,
93ce0ba6 1289 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
87ad3212 1290 pipe_name(pipe), onoff(state), onoff(cur_state));
93ce0ba6
JN
1291}
1292#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1293#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1294
b840d907
JB
1295void assert_pipe(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, bool state)
b24e7179 1297{
63d7bbe9 1298 bool cur_state;
702e7a56
PZ
1299 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1300 pipe);
4feed0eb 1301 enum intel_display_power_domain power_domain;
b24e7179 1302
b6b5d049
VS
1303 /* if we need the pipe quirk it must be always on */
1304 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1305 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV
1306 state = true;
1307
4feed0eb
ID
1308 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1309 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
649636ef 1310 u32 val = I915_READ(PIPECONF(cpu_transcoder));
69310161 1311 cur_state = !!(val & PIPECONF_ENABLE);
4feed0eb
ID
1312
1313 intel_display_power_put(dev_priv, power_domain);
1314 } else {
1315 cur_state = false;
69310161
PZ
1316 }
1317
e2c719b7 1318 I915_STATE_WARN(cur_state != state,
63d7bbe9 1319 "pipe %c assertion failure (expected %s, current %s)\n",
87ad3212 1320 pipe_name(pipe), onoff(state), onoff(cur_state));
b24e7179
JB
1321}
1322
931872fc
CW
1323static void assert_plane(struct drm_i915_private *dev_priv,
1324 enum plane plane, bool state)
b24e7179 1325{
b24e7179 1326 u32 val;
931872fc 1327 bool cur_state;
b24e7179 1328
649636ef 1329 val = I915_READ(DSPCNTR(plane));
931872fc 1330 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1331 I915_STATE_WARN(cur_state != state,
931872fc 1332 "plane %c assertion failure (expected %s, current %s)\n",
87ad3212 1333 plane_name(plane), onoff(state), onoff(cur_state));
b24e7179
JB
1334}
1335
931872fc
CW
1336#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1337#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1338
b24e7179
JB
1339static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341{
653e1026 1342 struct drm_device *dev = dev_priv->dev;
649636ef 1343 int i;
b24e7179 1344
653e1026
VS
1345 /* Primary planes are fixed to pipes on gen4+ */
1346 if (INTEL_INFO(dev)->gen >= 4) {
649636ef 1347 u32 val = I915_READ(DSPCNTR(pipe));
e2c719b7 1348 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ
1349 "plane %c assertion failure, should be disabled but not\n",
1350 plane_name(pipe));
19ec1358 1351 return;
28c05794 1352 }
19ec1358 1353
b24e7179 1354 /* Need to check both planes against the pipe */
055e393f 1355 for_each_pipe(dev_priv, i) {
649636ef
VS
1356 u32 val = I915_READ(DSPCNTR(i));
1357 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
b24e7179 1358 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1359 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB
1360 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1361 plane_name(i), pipe_name(pipe));
b24e7179
JB
1362 }
1363}
1364
19332d7a
JB
1365static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe)
1367{
20674eef 1368 struct drm_device *dev = dev_priv->dev;
649636ef 1369 int sprite;
19332d7a 1370
7feb8b88 1371 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1372 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1373 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1374 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL
1375 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1376 sprite, pipe_name(pipe));
1377 }
666a4537 1378 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
3bdcfc0c 1379 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1380 u32 val = I915_READ(SPCNTR(pipe, sprite));
e2c719b7 1381 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1382 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1383 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS
1384 }
1385 } else if (INTEL_INFO(dev)->gen >= 7) {
649636ef 1386 u32 val = I915_READ(SPRCTL(pipe));
e2c719b7 1387 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1388 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS
1389 plane_name(pipe), pipe_name(pipe));
1390 } else if (INTEL_INFO(dev)->gen >= 5) {
649636ef 1391 u32 val = I915_READ(DVSCNTR(pipe));
e2c719b7 1392 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1393 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1394 plane_name(pipe), pipe_name(pipe));
19332d7a
JB
1395 }
1396}
1397
08c71e5e
VS
1398static void assert_vblank_disabled(struct drm_crtc *crtc)
1399{
e2c719b7 1400 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS
1401 drm_crtc_vblank_put(crtc);
1402}
1403
7abd4b35
ACO
1404void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe)
92f2584a 1406{
92f2584a
JB
1407 u32 val;
1408 bool enabled;
1409
649636ef 1410 val = I915_READ(PCH_TRANSCONF(pipe));
92f2584a 1411 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1412 I915_STATE_WARN(enabled,
9db4a9c7
JB
1413 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1414 pipe_name(pipe));
92f2584a
JB
1415}
1416
4e634389
KP
1417static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1418 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP
1419{
1420 if ((val & DP_PORT_EN) == 0)
1421 return false;
1422
2d1fe073 1423 if (HAS_PCH_CPT(dev_priv)) {
f0f59a00 1424 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
f0575e92
KP
1425 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1426 return false;
2d1fe073 1427 } else if (IS_CHERRYVIEW(dev_priv)) {
44f37d1f
CML
1428 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1429 return false;
f0575e92
KP
1430 } else {
1431 if ((val & DP_PIPE_MASK) != (pipe << 30))
1432 return false;
1433 }
1434 return true;
1435}
1436
1519b995
KP
1437static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, u32 val)
1439{
dc0fa718 1440 if ((val & SDVO_ENABLE) == 0)
1519b995
KP
1441 return false;
1442
2d1fe073 1443 if (HAS_PCH_CPT(dev_priv)) {
dc0fa718 1444 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1445 return false;
2d1fe073 1446 } else if (IS_CHERRYVIEW(dev_priv)) {
44f37d1f
CML
1447 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1448 return false;
1519b995 1449 } else {
dc0fa718 1450 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP
1451 return false;
1452 }
1453 return true;
1454}
1455
1456static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, u32 val)
1458{
1459 if ((val & LVDS_PORT_EN) == 0)
1460 return false;
1461
2d1fe073 1462 if (HAS_PCH_CPT(dev_priv)) {
1519b995
KP
1463 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1464 return false;
1465 } else {
1466 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1467 return false;
1468 }
1469 return true;
1470}
1471
1472static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1473 enum pipe pipe, u32 val)
1474{
1475 if ((val & ADPA_DAC_ENABLE) == 0)
1476 return false;
2d1fe073 1477 if (HAS_PCH_CPT(dev_priv)) {
1519b995
KP
1478 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1479 return false;
1480 } else {
1481 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1482 return false;
1483 }
1484 return true;
1485}
1486
291906f1 1487static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0f59a00
VS
1488 enum pipe pipe, i915_reg_t reg,
1489 u32 port_sel)
291906f1 1490{
47a05eca 1491 u32 val = I915_READ(reg);
e2c719b7 1492 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1493 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
f0f59a00 1494 i915_mmio_reg_offset(reg), pipe_name(pipe));
de9a35ab 1495
2d1fe073 1496 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
75c5da27 1497 && (val & DP_PIPEB_SELECT),
de9a35ab 1498 "IBX PCH dp port still using transcoder B\n");
291906f1
JB
1499}
1500
1501static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
f0f59a00 1502 enum pipe pipe, i915_reg_t reg)
291906f1 1503{
47a05eca 1504 u32 val = I915_READ(reg);
e2c719b7 1505 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1506 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
f0f59a00 1507 i915_mmio_reg_offset(reg), pipe_name(pipe));
de9a35ab 1508
2d1fe073 1509 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
75c5da27 1510 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1511 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB
1512}
1513
1514static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1515 enum pipe pipe)
1516{
291906f1 1517 u32 val;
291906f1 1518
f0575e92
KP
1519 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1520 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1521 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1 1522
649636ef 1523 val = I915_READ(PCH_ADPA);
e2c719b7 1524 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1525 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1526 pipe_name(pipe));
291906f1 1527
649636ef 1528 val = I915_READ(PCH_LVDS);
e2c719b7 1529 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1530 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1531 pipe_name(pipe));
291906f1 1532
e2debe91
PZ
1533 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1534 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1535 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB
1536}
1537
cd2d34d9
VS
1538static void _vlv_enable_pll(struct intel_crtc *crtc,
1539 const struct intel_crtc_state *pipe_config)
1540{
1541 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1542 enum pipe pipe = crtc->pipe;
1543
1544 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1545 POSTING_READ(DPLL(pipe));
1546 udelay(150);
1547
2c30b43b
CW
1548 if (intel_wait_for_register(dev_priv,
1549 DPLL(pipe),
1550 DPLL_LOCK_VLV,
1551 DPLL_LOCK_VLV,
1552 1))
cd2d34d9
VS
1553 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1554}
1555
d288f65f 1556static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1557 const struct intel_crtc_state *pipe_config)
87442f73 1558{
cd2d34d9 1559 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8bd3f301 1560 enum pipe pipe = crtc->pipe;
87442f73 1561
8bd3f301 1562 assert_pipe_disabled(dev_priv, pipe);
87442f73 1563
87442f73 1564 /* PLL is protected by panel, make sure we can write it */
7d1a83cb 1565 assert_panel_unlocked(dev_priv, pipe);
87442f73 1566
cd2d34d9
VS
1567 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1568 _vlv_enable_pll(crtc, pipe_config);
426115cf 1569
8bd3f301
VS
1570 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1571 POSTING_READ(DPLL_MD(pipe));
87442f73
DV
1572}
1573
cd2d34d9
VS
1574
1575static void _chv_enable_pll(struct intel_crtc *crtc,
1576 const struct intel_crtc_state *pipe_config)
9d556c99 1577{
cd2d34d9 1578 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8bd3f301 1579 enum pipe pipe = crtc->pipe;
9d556c99 1580 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML
1581 u32 tmp;
1582
a580516d 1583 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML
1584
1585 /* Enable back the 10bit clock to display controller */
1586 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1587 tmp |= DPIO_DCLKP_EN;
1588 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1589
54433e91
VS
1590 mutex_unlock(&dev_priv->sb_lock);
1591
9d556c99
CML
1592 /*
1593 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1594 */
1595 udelay(1);
1596
1597 /* Enable PLL */
d288f65f 1598 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML
1599
1600 /* Check PLL is locked */
6b18826a
CW
1601 if (intel_wait_for_register(dev_priv,
1602 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1603 1))
9d556c99 1604 DRM_ERROR("PLL %d failed to lock\n", pipe);
cd2d34d9
VS
1605}
1606
1607static void chv_enable_pll(struct intel_crtc *crtc,
1608 const struct intel_crtc_state *pipe_config)
1609{
1610 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1611 enum pipe pipe = crtc->pipe;
1612
1613 assert_pipe_disabled(dev_priv, pipe);
1614
1615 /* PLL is protected by panel, make sure we can write it */
1616 assert_panel_unlocked(dev_priv, pipe);
1617
1618 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1619 _chv_enable_pll(crtc, pipe_config);
9d556c99 1620
c231775c
VS
1621 if (pipe != PIPE_A) {
1622 /*
1623 * WaPixelRepeatModeFixForC0:chv
1624 *
1625 * DPLLCMD is AWOL. Use chicken bits to propagate
1626 * the value from DPLLBMD to either pipe B or C.
1627 */
1628 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1629 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1630 I915_WRITE(CBR4_VLV, 0);
1631 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1632
1633 /*
1634 * DPLLB VGA mode also seems to cause problems.
1635 * We should always have it disabled.
1636 */
1637 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1638 } else {
1639 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1640 POSTING_READ(DPLL_MD(pipe));
1641 }
9d556c99
CML
1642}
1643
1c4e0274
VS
1644static int intel_num_dvo_pipes(struct drm_device *dev)
1645{
1646 struct intel_crtc *crtc;
1647 int count = 0;
1648
1649 for_each_intel_crtc(dev, crtc)
3538b9df 1650 count += crtc->base.state->active &&
409ee761 1651 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS
1652
1653 return count;
1654}
1655
66e3d5c0 1656static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1657{
66e3d5c0
DV
1658 struct drm_device *dev = crtc->base.dev;
1659 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1660 i915_reg_t reg = DPLL(crtc->pipe);
6e3c9717 1661 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1662
66e3d5c0 1663 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1664
63d7bbe9 1665 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV
1666 if (IS_MOBILE(dev) && !IS_I830(dev))
1667 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1668
1c4e0274
VS
1669 /* Enable DVO 2x clock on both PLLs if necessary */
1670 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1671 /*
1672 * It appears to be important that we don't enable this
1673 * for the current pipe before otherwise configuring the
1674 * PLL. No idea how this should be handled if multiple
1675 * DVO outputs are enabled simultaneosly.
1676 */
1677 dpll |= DPLL_DVO_2X_MODE;
1678 I915_WRITE(DPLL(!crtc->pipe),
1679 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1680 }
66e3d5c0 1681
c2b63374
VS
1682 /*
1683 * Apparently we need to have VGA mode enabled prior to changing
1684 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1685 * dividers, even though the register value does change.
1686 */
1687 I915_WRITE(reg, 0);
1688
8e7a65aa
VS
1689 I915_WRITE(reg, dpll);
1690
66e3d5c0
DV
1691 /* Wait for the clocks to stabilize. */
1692 POSTING_READ(reg);
1693 udelay(150);
1694
1695 if (INTEL_INFO(dev)->gen >= 4) {
1696 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1697 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV
1698 } else {
1699 /* The pixel multiplier can only be updated once the
1700 * DPLL is enabled and the clocks are stable.
1701 *
1702 * So write it again.
1703 */
1704 I915_WRITE(reg, dpll);
1705 }
63d7bbe9
JB
1706
1707 /* We do this three times for luck */
66e3d5c0 1708 I915_WRITE(reg, dpll);
63d7bbe9
JB
1709 POSTING_READ(reg);
1710 udelay(150); /* wait for warmup */
66e3d5c0 1711 I915_WRITE(reg, dpll);
63d7bbe9
JB
1712 POSTING_READ(reg);
1713 udelay(150); /* wait for warmup */
66e3d5c0 1714 I915_WRITE(reg, dpll);
63d7bbe9
JB
1715 POSTING_READ(reg);
1716 udelay(150); /* wait for warmup */
1717}
1718
1719/**
50b44a44 1720 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB
1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe PLL to disable
1723 *
1724 * Disable the PLL for @pipe, making sure the pipe is off first.
1725 *
1726 * Note! This is for pre-ILK only.
1727 */
1c4e0274 1728static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1729{
1c4e0274
VS
1730 struct drm_device *dev = crtc->base.dev;
1731 struct drm_i915_private *dev_priv = dev->dev_private;
1732 enum pipe pipe = crtc->pipe;
1733
1734 /* Disable DVO 2x clock on both PLLs if necessary */
1735 if (IS_I830(dev) &&
409ee761 1736 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1737 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS
1738 I915_WRITE(DPLL(PIPE_B),
1739 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1740 I915_WRITE(DPLL(PIPE_A),
1741 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1742 }
1743
b6b5d049
VS
1744 /* Don't disable pipe or pipe PLLs if needed */
1745 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1746 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB
1747 return;
1748
1749 /* Make sure the pipe isn't still relying on us */
1750 assert_pipe_disabled(dev_priv, pipe);
1751
b8afb911 1752 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1753 POSTING_READ(DPLL(pipe));
63d7bbe9
JB
1754}
1755
f6071166
JB
1756static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1757{
b8afb911 1758 u32 val;
f6071166
JB
1759
1760 /* Make sure the pipe isn't still relying on us */
1761 assert_pipe_disabled(dev_priv, pipe);
1762
03ed5cbf
VS
1763 val = DPLL_INTEGRATED_REF_CLK_VLV |
1764 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1765 if (pipe != PIPE_A)
1766 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1767
f6071166
JB
1768 I915_WRITE(DPLL(pipe), val);
1769 POSTING_READ(DPLL(pipe));
076ed3b2
CML
1770}
1771
1772static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1773{
d752048d 1774 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML
1775 u32 val;
1776
a11b0703
VS
1777 /* Make sure the pipe isn't still relying on us */
1778 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1779
60bfe44f
VS
1780 val = DPLL_SSC_REF_CLK_CHV |
1781 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS
1782 if (pipe != PIPE_A)
1783 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
03ed5cbf 1784
a11b0703
VS
1785 I915_WRITE(DPLL(pipe), val);
1786 POSTING_READ(DPLL(pipe));
d752048d 1787
a580516d 1788 mutex_lock(&dev_priv->sb_lock);
d752048d
VS
1789
1790 /* Disable 10bit clock to display controller */
1791 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1792 val &= ~DPIO_DCLKP_EN;
1793 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1794
a580516d 1795 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB
1796}
1797
e4607fcf 1798void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS
1799 struct intel_digital_port *dport,
1800 unsigned int expected_mask)
89b667f8
JB
1801{
1802 u32 port_mask;
f0f59a00 1803 i915_reg_t dpll_reg;
89b667f8 1804
e4607fcf
CML
1805 switch (dport->port) {
1806 case PORT_B:
89b667f8 1807 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1808 dpll_reg = DPLL(0);
e4607fcf
CML
1809 break;
1810 case PORT_C:
89b667f8 1811 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1812 dpll_reg = DPLL(0);
9b6de0a1 1813 expected_mask <<= 4;
00fc31b7
CML
1814 break;
1815 case PORT_D:
1816 port_mask = DPLL_PORTD_READY_MASK;
1817 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML
1818 break;
1819 default:
1820 BUG();
1821 }
89b667f8 1822
9b6de0a1
VS
1823 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1824 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1825 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB
1826}
1827
b8a4f404
PZ
1828static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1829 enum pipe pipe)
040484af 1830{
23670b32 1831 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1832 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f0f59a00
VS
1834 i915_reg_t reg;
1835 uint32_t val, pipeconf_val;
040484af 1836
040484af 1837 /* Make sure PCH DPLL is enabled */
8106ddbd 1838 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
040484af
JB
1839
1840 /* FDI must be feeding us bits for PCH ports */
1841 assert_fdi_tx_enabled(dev_priv, pipe);
1842 assert_fdi_rx_enabled(dev_priv, pipe);
1843
23670b32
DV
1844 if (HAS_PCH_CPT(dev)) {
1845 /* Workaround: Set the timing override bit before enabling the
1846 * pch transcoder. */
1847 reg = TRANS_CHICKEN2(pipe);
1848 val = I915_READ(reg);
1849 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1850 I915_WRITE(reg, val);
59c859d6 1851 }
23670b32 1852
ab9412ba 1853 reg = PCH_TRANSCONF(pipe);
040484af 1854 val = I915_READ(reg);
5f7f726d 1855 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c 1856
2d1fe073 1857 if (HAS_PCH_IBX(dev_priv)) {
e9bcff5c 1858 /*
c5de7c6f
VS
1859 * Make the BPC in transcoder be consistent with
1860 * that in pipeconf reg. For HDMI we must use 8bpc
1861 * here for both 8bpc and 12bpc.
e9bcff5c 1862 */
dfd07d72 1863 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS
1864 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1865 val |= PIPECONF_8BPC;
1866 else
1867 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1868 }
5f7f726d
PZ
1869
1870 val &= ~TRANS_INTERLACE_MASK;
1871 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2d1fe073 1872 if (HAS_PCH_IBX(dev_priv) &&
409ee761 1873 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ
1874 val |= TRANS_LEGACY_INTERLACED_ILK;
1875 else
1876 val |= TRANS_INTERLACED;
5f7f726d
PZ
1877 else
1878 val |= TRANS_PROGRESSIVE;
1879
040484af
JB
1880 I915_WRITE(reg, val | TRANS_ENABLE);
1881 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1882 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB
1883}
1884
8fb033d7 1885static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1886 enum transcoder cpu_transcoder)
040484af 1887{
8fb033d7 1888 u32 val, pipeconf_val;
8fb033d7 1889
8fb033d7 1890 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1891 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1892 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1893
223a6fdf 1894 /* Workaround: set timing override bit. */
36c0d0cf 1895 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 1896 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 1897 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
223a6fdf 1898
25f3ef11 1899 val = TRANS_ENABLE;
937bb610 1900 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1901
9a76b1c6
PZ
1902 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1903 PIPECONF_INTERLACED_ILK)
a35f2679 1904 val |= TRANS_INTERLACED;
8fb033d7
PZ
1905 else
1906 val |= TRANS_PROGRESSIVE;
1907
ab9412ba
DV
1908 I915_WRITE(LPT_TRANSCONF, val);
1909 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1910 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ
1911}
1912
b8a4f404
PZ
1913static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1914 enum pipe pipe)
040484af 1915{
23670b32 1916 struct drm_device *dev = dev_priv->dev;
f0f59a00
VS
1917 i915_reg_t reg;
1918 uint32_t val;
040484af
JB
1919
1920 /* FDI relies on the transcoder */
1921 assert_fdi_tx_disabled(dev_priv, pipe);
1922 assert_fdi_rx_disabled(dev_priv, pipe);
1923
291906f1
JB
1924 /* Ports must be off as well */
1925 assert_pch_ports_disabled(dev_priv, pipe);
1926
ab9412ba 1927 reg = PCH_TRANSCONF(pipe);
040484af
JB
1928 val = I915_READ(reg);
1929 val &= ~TRANS_ENABLE;
1930 I915_WRITE(reg, val);
1931 /* wait for PCH transcoder off, transcoder state */
1932 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1933 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32 1934
c465613b 1935 if (HAS_PCH_CPT(dev)) {
23670b32
DV
1936 /* Workaround: Clear the timing override chicken bit again. */
1937 reg = TRANS_CHICKEN2(pipe);
1938 val = I915_READ(reg);
1939 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1940 I915_WRITE(reg, val);
1941 }
040484af
JB
1942}
1943
ab4d966c 1944static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1945{
8fb033d7
PZ
1946 u32 val;
1947
ab9412ba 1948 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1949 val &= ~TRANS_ENABLE;
ab9412ba 1950 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1951 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1952 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1953 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ
1954
1955 /* Workaround: clear timing override bit. */
36c0d0cf 1956 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 1957 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 1958 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
040484af
JB
1959}
1960
b24e7179 1961/**
309cfea8 1962 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 1963 * @crtc: crtc responsible for the pipe
b24e7179 1964 *
0372264a 1965 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 1966 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 1967 */
e1fdc473 1968static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 1969{
0372264a
PZ
1970 struct drm_device *dev = crtc->base.dev;
1971 struct drm_i915_private *dev_priv = dev->dev_private;
1972 enum pipe pipe = crtc->pipe;
1a70a728 1973 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1a240d4d 1974 enum pipe pch_transcoder;
f0f59a00 1975 i915_reg_t reg;
b24e7179
JB
1976 u32 val;
1977
9e2ee2dd
VS
1978 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1979
58c6eaa2 1980 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1981 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV
1982 assert_sprites_disabled(dev_priv, pipe);
1983
2d1fe073 1984 if (HAS_PCH_LPT(dev_priv))
cc391bbb
PZ
1985 pch_transcoder = TRANSCODER_A;
1986 else
1987 pch_transcoder = pipe;
1988
b24e7179
JB
1989 /*
1990 * A pipe without a PLL won't actually be able to drive bits from
1991 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1992 * need the check.
1993 */
2d1fe073 1994 if (HAS_GMCH_DISPLAY(dev_priv))
a65347ba 1995 if (crtc->config->has_dsi_encoder)
23538ef1
JN
1996 assert_dsi_pll_enabled(dev_priv);
1997 else
1998 assert_pll_enabled(dev_priv, pipe);
040484af 1999 else {
6e3c9717 2000 if (crtc->config->has_pch_encoder) {
040484af 2001 /* if driving the PCH, we need FDI enabled */
cc391bbb 2002 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV
2003 assert_fdi_tx_pll_enabled(dev_priv,
2004 (enum pipe) cpu_transcoder);
040484af
JB
2005 }
2006 /* FIXME: assert CPU port conditions for SNB+ */
2007 }
b24e7179 2008
702e7a56 2009 reg = PIPECONF(cpu_transcoder);
b24e7179 2010 val = I915_READ(reg);
7ad25d48 2011 if (val & PIPECONF_ENABLE) {
b6b5d049
VS
2012 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2013 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2014 return;
7ad25d48 2015 }
00d70b15
CW
2016
2017 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2018 POSTING_READ(reg);
b7792d8b
VS
2019
2020 /*
2021 * Until the pipe starts DSL will read as 0, which would cause
2022 * an apparent vblank timestamp jump, which messes up also the
2023 * frame count when it's derived from the timestamps. So let's
2024 * wait for the pipe to start properly before we call
2025 * drm_crtc_vblank_on()
2026 */
2027 if (dev->max_vblank_count == 0 &&
2028 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2029 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
b24e7179
JB
2030}
2031
2032/**
309cfea8 2033 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2034 * @crtc: crtc whose pipes is to be disabled
b24e7179 2035 *
575f7ab7
VS
2036 * Disable the pipe of @crtc, making sure that various hardware
2037 * specific requirements are met, if applicable, e.g. plane
2038 * disabled, panel fitter off, etc.
b24e7179
JB
2039 *
2040 * Will wait until the pipe has shut down before returning.
2041 */
575f7ab7 2042static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2043{
575f7ab7 2044 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2045 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2046 enum pipe pipe = crtc->pipe;
f0f59a00 2047 i915_reg_t reg;
b24e7179
JB
2048 u32 val;
2049
9e2ee2dd
VS
2050 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2051
b24e7179
JB
2052 /*
2053 * Make sure planes won't keep trying to pump pixels to us,
2054 * or we might hang the display.
2055 */
2056 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2057 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2058 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2059
702e7a56 2060 reg = PIPECONF(cpu_transcoder);
b24e7179 2061 val = I915_READ(reg);
00d70b15
CW
2062 if ((val & PIPECONF_ENABLE) == 0)
2063 return;
2064
67adc644
VS
2065 /*
2066 * Double wide has implications for planes
2067 * so best keep it disabled when not needed.
2068 */
6e3c9717 2069 if (crtc->config->double_wide)
67adc644
VS
2070 val &= ~PIPECONF_DOUBLE_WIDE;
2071
2072 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS
2073 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2074 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS
2075 val &= ~PIPECONF_ENABLE;
2076
2077 I915_WRITE(reg, val);
2078 if ((val & PIPECONF_ENABLE) == 0)
2079 intel_wait_for_pipe_off(crtc);
b24e7179
JB
2080}
2081
693db184
CW
2082static bool need_vtd_wa(struct drm_device *dev)
2083{
2084#ifdef CONFIG_INTEL_IOMMU
2085 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2086 return true;
2087#endif
2088 return false;
2089}
2090
832be82f
VS
2091static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2092{
2093 return IS_GEN2(dev_priv) ? 2048 : 4096;
2094}
2095
27ba3910
VS
2096static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2097 uint64_t fb_modifier, unsigned int cpp)
7b49f948
VS
2098{
2099 switch (fb_modifier) {
2100 case DRM_FORMAT_MOD_NONE:
2101 return cpp;
2102 case I915_FORMAT_MOD_X_TILED:
2103 if (IS_GEN2(dev_priv))
2104 return 128;
2105 else
2106 return 512;
2107 case I915_FORMAT_MOD_Y_TILED:
2108 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2109 return 128;
2110 else
2111 return 512;
2112 case I915_FORMAT_MOD_Yf_TILED:
2113 switch (cpp) {
2114 case 1:
2115 return 64;
2116 case 2:
2117 case 4:
2118 return 128;
2119 case 8:
2120 case 16:
2121 return 256;
2122 default:
2123 MISSING_CASE(cpp);
2124 return cpp;
2125 }
2126 break;
2127 default:
2128 MISSING_CASE(fb_modifier);
2129 return cpp;
2130 }
2131}
2132
832be82f
VS
2133unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2134 uint64_t fb_modifier, unsigned int cpp)
a57ce0b2 2135{
832be82f
VS
2136 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2137 return 1;
2138 else
2139 return intel_tile_size(dev_priv) /
27ba3910 2140 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
6761dd31
TU
2141}
2142
8d0deca8
VS
2143/* Return the tile dimensions in pixel units */
2144static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2145 unsigned int *tile_width,
2146 unsigned int *tile_height,
2147 uint64_t fb_modifier,
2148 unsigned int cpp)
2149{
2150 unsigned int tile_width_bytes =
2151 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2152
2153 *tile_width = tile_width_bytes / cpp;
2154 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2155}
2156
6761dd31
TU
2157unsigned int
2158intel_fb_align_height(struct drm_device *dev, unsigned int height,
832be82f 2159 uint32_t pixel_format, uint64_t fb_modifier)
6761dd31 2160{
832be82f
VS
2161 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2162 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2163
2164 return ALIGN(height, tile_height);
a57ce0b2
JB
2165}
2166
1663b9d6
VS
2167unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2168{
2169 unsigned int size = 0;
2170 int i;
2171
2172 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2173 size += rot_info->plane[i].width * rot_info->plane[i].height;
2174
2175 return size;
2176}
2177
75c82a53 2178static void
3465c580
VS
2179intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2180 const struct drm_framebuffer *fb,
2181 unsigned int rotation)
f64b98cd 2182{
2d7a215f
VS
2183 if (intel_rotation_90_or_270(rotation)) {
2184 *view = i915_ggtt_view_rotated;
2185 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2186 } else {
2187 *view = i915_ggtt_view_normal;
2188 }
2189}
50470bb0 2190
2d7a215f
VS
2191static void
2192intel_fill_fb_info(struct drm_i915_private *dev_priv,
2193 struct drm_framebuffer *fb)
2194{
2195 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2196 unsigned int tile_size, tile_width, tile_height, cpp;
50470bb0 2197
d9b3288e
VS
2198 tile_size = intel_tile_size(dev_priv);
2199
2200 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
8d0deca8
VS
2201 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2202 fb->modifier[0], cpp);
d9b3288e 2203
1663b9d6
VS
2204 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2205 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
84fe03f7 2206
89e3e142 2207 if (info->pixel_format == DRM_FORMAT_NV12) {
832be82f 2208 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
8d0deca8
VS
2209 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2210 fb->modifier[1], cpp);
d9b3288e 2211
2d7a215f 2212 info->uv_offset = fb->offsets[1];
1663b9d6
VS
2213 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2214 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
89e3e142 2215 }
f64b98cd
TU
2216}
2217
603525d7 2218static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
4e9a86b6
VS
2219{
2220 if (INTEL_INFO(dev_priv)->gen >= 9)
2221 return 256 * 1024;
985b8bb4 2222 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
666a4537 2223 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4e9a86b6
VS
2224 return 128 * 1024;
2225 else if (INTEL_INFO(dev_priv)->gen >= 4)
2226 return 4 * 1024;
2227 else
44c5905e 2228 return 0;
4e9a86b6
VS
2229}
2230
603525d7
VS
2231static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2232 uint64_t fb_modifier)
2233{
2234 switch (fb_modifier) {
2235 case DRM_FORMAT_MOD_NONE:
2236 return intel_linear_alignment(dev_priv);
2237 case I915_FORMAT_MOD_X_TILED:
2238 if (INTEL_INFO(dev_priv)->gen >= 9)
2239 return 256 * 1024;
2240 return 0;
2241 case I915_FORMAT_MOD_Y_TILED:
2242 case I915_FORMAT_MOD_Yf_TILED:
2243 return 1 * 1024 * 1024;
2244 default:
2245 MISSING_CASE(fb_modifier);
2246 return 0;
2247 }
2248}
2249
127bd2ac 2250int
3465c580
VS
2251intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2252 unsigned int rotation)
6b95a207 2253{
850c4cdc 2254 struct drm_device *dev = fb->dev;
ce453d81 2255 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2256 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2257 struct i915_ggtt_view view;
6b95a207
KH
2258 u32 alignment;
2259 int ret;
2260
ebcdd39e
MR
2261 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2262
603525d7 2263 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
6b95a207 2264
3465c580 2265 intel_fill_fb_ggtt_view(&view, fb, rotation);
f64b98cd 2266
693db184
CW
2267 /* Note that the w/a also requires 64 PTE of padding following the
2268 * bo. We currently fill all unused PTE with the shadow page and so
2269 * we should always have valid PTE following the scanout preventing
2270 * the VT-d warning.
2271 */
2272 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2273 alignment = 256 * 1024;
2274
d6dd6843
PZ
2275 /*
2276 * Global gtt pte registers are special registers which actually forward
2277 * writes to a chunk of system memory. Which means that there is no risk
2278 * that the register values disappear as soon as we call
2279 * intel_runtime_pm_put(), so it is correct to wrap only the
2280 * pin/unpin/fence and not more.
2281 */
2282 intel_runtime_pm_get(dev_priv);
2283
7580d774
ML
2284 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2285 &view);
48b956c5 2286 if (ret)
b26a6b35 2287 goto err_pm;
6b95a207
KH
2288
2289 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2290 * fence, whereas 965+ only requires a fence if using
2291 * framebuffer compression. For simplicity, we always install
2292 * a fence as the cost is not that onerous.
2293 */
9807216f
VK
2294 if (view.type == I915_GGTT_VIEW_NORMAL) {
2295 ret = i915_gem_object_get_fence(obj);
2296 if (ret == -EDEADLK) {
2297 /*
2298 * -EDEADLK means there are no free fences
2299 * no pending flips.
2300 *
2301 * This is propagated to atomic, but it uses
2302 * -EDEADLK to force a locking recovery, so
2303 * change the returned error to -EBUSY.
2304 */
2305 ret = -EBUSY;
2306 goto err_unpin;
2307 } else if (ret)
2308 goto err_unpin;
1690e1eb 2309
9807216f
VK
2310 i915_gem_object_pin_fence(obj);
2311 }
6b95a207 2312
d6dd6843 2313 intel_runtime_pm_put(dev_priv);
6b95a207 2314 return 0;
48b956c5
CW
2315
2316err_unpin:
f64b98cd 2317 i915_gem_object_unpin_from_display_plane(obj, &view);
b26a6b35 2318err_pm:
d6dd6843 2319 intel_runtime_pm_put(dev_priv);
48b956c5 2320 return ret;
6b95a207
KH
2321}
2322
fb4b8ce1 2323void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
1690e1eb 2324{
82bc3b2d 2325 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2326 struct i915_ggtt_view view;
82bc3b2d 2327
ebcdd39e
MR
2328 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2329
3465c580 2330 intel_fill_fb_ggtt_view(&view, fb, rotation);
f64b98cd 2331
9807216f
VK
2332 if (view.type == I915_GGTT_VIEW_NORMAL)
2333 i915_gem_object_unpin_fence(obj);
2334
f64b98cd 2335 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW
2336}
2337
29cf9491
VS
2338/*
2339 * Adjust the tile offset by moving the difference into
2340 * the x/y offsets.
2341 *
2342 * Input tile dimensions and pitch must already be
2343 * rotated to match x and y, and in pixel units.
2344 */
2345static u32 intel_adjust_tile_offset(int *x, int *y,
2346 unsigned int tile_width,
2347 unsigned int tile_height,
2348 unsigned int tile_size,
2349 unsigned int pitch_tiles,
2350 u32 old_offset,
2351 u32 new_offset)
2352{
2353 unsigned int tiles;
2354
2355 WARN_ON(old_offset & (tile_size - 1));
2356 WARN_ON(new_offset & (tile_size - 1));
2357 WARN_ON(new_offset > old_offset);
2358
2359 tiles = (old_offset - new_offset) / tile_size;
2360
2361 *y += tiles / pitch_tiles * tile_height;
2362 *x += tiles % pitch_tiles * tile_width;
2363
2364 return new_offset;
2365}
2366
8d0deca8
VS
2367/*
2368 * Computes the linear offset to the base tile and adjusts
2369 * x, y. bytes per pixel is assumed to be a power-of-two.
2370 *
2371 * In the 90/270 rotated case, x and y are assumed
2372 * to be already rotated to match the rotated GTT view, and
2373 * pitch is the tile_height aligned framebuffer height.
2374 */
4f2d9934
VS
2375u32 intel_compute_tile_offset(int *x, int *y,
2376 const struct drm_framebuffer *fb, int plane,
8d0deca8
VS
2377 unsigned int pitch,
2378 unsigned int rotation)
c2c75131 2379{
4f2d9934
VS
2380 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2381 uint64_t fb_modifier = fb->modifier[plane];
2382 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
29cf9491
VS
2383 u32 offset, offset_aligned, alignment;
2384
2385 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2386 if (alignment)
2387 alignment--;
2388
b5c65338 2389 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
8d0deca8
VS
2390 unsigned int tile_size, tile_width, tile_height;
2391 unsigned int tile_rows, tiles, pitch_tiles;
c2c75131 2392
d843310d 2393 tile_size = intel_tile_size(dev_priv);
8d0deca8
VS
2394 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2395 fb_modifier, cpp);
2396
2397 if (intel_rotation_90_or_270(rotation)) {
2398 pitch_tiles = pitch / tile_height;
2399 swap(tile_width, tile_height);
2400 } else {
2401 pitch_tiles = pitch / (tile_width * cpp);
2402 }
d843310d
VS
2403
2404 tile_rows = *y / tile_height;
2405 *y %= tile_height;
c2c75131 2406
8d0deca8
VS
2407 tiles = *x / tile_width;
2408 *x %= tile_width;
bc752862 2409
29cf9491
VS
2410 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2411 offset_aligned = offset & ~alignment;
bc752862 2412
29cf9491
VS
2413 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2414 tile_size, pitch_tiles,
2415 offset, offset_aligned);
2416 } else {
bc752862 2417 offset = *y * pitch + *x * cpp;
29cf9491
VS
2418 offset_aligned = offset & ~alignment;
2419
4e9a86b6
VS
2420 *y = (offset & alignment) / pitch;
2421 *x = ((offset & alignment) - *y * pitch) / cpp;
bc752862 2422 }
29cf9491
VS
2423
2424 return offset_aligned;
c2c75131
DV
2425}
2426
b35d63fa 2427static int i9xx_format_to_fourcc(int format)
46f297fb
JB
2428{
2429 switch (format) {
2430 case DISPPLANE_8BPP:
2431 return DRM_FORMAT_C8;
2432 case DISPPLANE_BGRX555:
2433 return DRM_FORMAT_XRGB1555;
2434 case DISPPLANE_BGRX565:
2435 return DRM_FORMAT_RGB565;
2436 default:
2437 case DISPPLANE_BGRX888:
2438 return DRM_FORMAT_XRGB8888;
2439 case DISPPLANE_RGBX888:
2440 return DRM_FORMAT_XBGR8888;
2441 case DISPPLANE_BGRX101010:
2442 return DRM_FORMAT_XRGB2101010;
2443 case DISPPLANE_RGBX101010:
2444 return DRM_FORMAT_XBGR2101010;
2445 }
2446}
2447
bc8d7dff
DL
2448static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2449{
2450 switch (format) {
2451 case PLANE_CTL_FORMAT_RGB_565:
2452 return DRM_FORMAT_RGB565;
2453 default:
2454 case PLANE_CTL_FORMAT_XRGB_8888:
2455 if (rgb_order) {
2456 if (alpha)
2457 return DRM_FORMAT_ABGR8888;
2458 else
2459 return DRM_FORMAT_XBGR8888;
2460 } else {
2461 if (alpha)
2462 return DRM_FORMAT_ARGB8888;
2463 else
2464 return DRM_FORMAT_XRGB8888;
2465 }
2466 case PLANE_CTL_FORMAT_XRGB_2101010:
2467 if (rgb_order)
2468 return DRM_FORMAT_XBGR2101010;
2469 else
2470 return DRM_FORMAT_XRGB2101010;
2471 }
2472}
2473
5724dbd1 2474static bool
f6936e29
DV
2475intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2476 struct intel_initial_plane_config *plane_config)
46f297fb
JB
2477{
2478 struct drm_device *dev = crtc->base.dev;
3badb49f 2479 struct drm_i915_private *dev_priv = to_i915(dev);
72e96d64 2480 struct i915_ggtt *ggtt = &dev_priv->ggtt;
46f297fb
JB
2481 struct drm_i915_gem_object *obj = NULL;
2482 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2483 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV
2484 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2485 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2486 PAGE_SIZE);
2487
2488 size_aligned -= base_aligned;
46f297fb 2489
ff2652ea
CW
2490 if (plane_config->size == 0)
2491 return false;
2492
3badb49f
PZ
2493 /* If the FB is too big, just don't use it since fbdev is not very
2494 * important and we should probably use that space with FBC or other
2495 * features. */
72e96d64 2496 if (size_aligned * 2 > ggtt->stolen_usable_size)
3badb49f
PZ
2497 return false;
2498
12c83d99
TU
2499 mutex_lock(&dev->struct_mutex);
2500
f37b5c2b
DV
2501 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2502 base_aligned,
2503 base_aligned,
2504 size_aligned);
12c83d99
TU
2505 if (!obj) {
2506 mutex_unlock(&dev->struct_mutex);
484b41dd 2507 return false;
12c83d99 2508 }
46f297fb 2509
49af449b
DL
2510 obj->tiling_mode = plane_config->tiling;
2511 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2512 obj->stride = fb->pitches[0];
46f297fb 2513
6bf129df
DL
2514 mode_cmd.pixel_format = fb->pixel_format;
2515 mode_cmd.width = fb->width;
2516 mode_cmd.height = fb->height;
2517 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV
2518 mode_cmd.modifier[0] = fb->modifier[0];
2519 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb 2520
6bf129df 2521 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2522 &mode_cmd, obj)) {
46f297fb
JB
2523 DRM_DEBUG_KMS("intel fb init failed\n");
2524 goto out_unref_obj;
2525 }
12c83d99 2526
46f297fb 2527 mutex_unlock(&dev->struct_mutex);
484b41dd 2528
f6936e29 2529 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2530 return true;
46f297fb
JB
2531
2532out_unref_obj:
2533 drm_gem_object_unreference(&obj->base);
2534 mutex_unlock(&dev->struct_mutex);
484b41dd
JB
2535 return false;
2536}
2537
5a21b665
DV
2538/* Update plane->state->fb to match plane->fb after driver-internal updates */
2539static void
2540update_state_fb(struct drm_plane *plane)
2541{
2542 if (plane->fb == plane->state->fb)
2543 return;
2544
2545 if (plane->state->fb)
2546 drm_framebuffer_unreference(plane->state->fb);
2547 plane->state->fb = plane->fb;
2548 if (plane->state->fb)
2549 drm_framebuffer_reference(plane->state->fb);
2550}
2551
5724dbd1 2552static void
f6936e29
DV
2553intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2554 struct intel_initial_plane_config *plane_config)
484b41dd
JB
2555{
2556 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2557 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB
2558 struct drm_crtc *c;
2559 struct intel_crtc *i;
2ff8fde1 2560 struct drm_i915_gem_object *obj;
88595ac9 2561 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2562 struct drm_plane_state *plane_state = primary->state;
200757f5
MR
2563 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2564 struct intel_plane *intel_plane = to_intel_plane(primary);
0a8d8a86
MR
2565 struct intel_plane_state *intel_state =
2566 to_intel_plane_state(plane_state);
88595ac9 2567 struct drm_framebuffer *fb;
484b41dd 2568
2d14030b 2569 if (!plane_config->fb)
484b41dd
JB
2570 return;
2571
f6936e29 2572 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV
2573 fb = &plane_config->fb->base;
2574 goto valid_fb;
f55548b5 2575 }
484b41dd 2576
2d14030b 2577 kfree(plane_config->fb);
484b41dd
JB
2578
2579 /*
2580 * Failed to alloc the obj, check to see if we should share
2581 * an fb with another CRTC instead
2582 */
70e1e0ec 2583 for_each_crtc(dev, c) {
484b41dd
JB
2584 i = to_intel_crtc(c);
2585
2586 if (c == &intel_crtc->base)
2587 continue;
2588
2ff8fde1
MR
2589 if (!i->active)
2590 continue;
2591
88595ac9
DV
2592 fb = c->primary->fb;
2593 if (!fb)
484b41dd
JB
2594 continue;
2595
88595ac9 2596 obj = intel_fb_obj(fb);
2ff8fde1 2597 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV
2598 drm_framebuffer_reference(fb);
2599 goto valid_fb;
484b41dd
JB
2600 }
2601 }
88595ac9 2602
200757f5
MR
2603 /*
2604 * We've failed to reconstruct the BIOS FB. Current display state
2605 * indicates that the primary plane is visible, but has a NULL FB,
2606 * which will lead to problems later if we don't fix it up. The
2607 * simplest solution is to just disable the primary plane now and
2608 * pretend the BIOS never had it enabled.
2609 */
2610 to_intel_plane_state(plane_state)->visible = false;
2611 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2622a081 2612 intel_pre_disable_primary_noatomic(&intel_crtc->base);
200757f5
MR
2613 intel_plane->disable_plane(primary, &intel_crtc->base);
2614
88595ac9
DV
2615 return;
2616
2617valid_fb:
f44e2659
VS
2618 plane_state->src_x = 0;
2619 plane_state->src_y = 0;
be5651f2
ML
2620 plane_state->src_w = fb->width << 16;
2621 plane_state->src_h = fb->height << 16;
2622
f44e2659
VS
2623 plane_state->crtc_x = 0;
2624 plane_state->crtc_y = 0;
be5651f2
ML
2625 plane_state->crtc_w = fb->width;
2626 plane_state->crtc_h = fb->height;
2627
0a8d8a86
MR
2628 intel_state->src.x1 = plane_state->src_x;
2629 intel_state->src.y1 = plane_state->src_y;
2630 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2631 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2632 intel_state->dst.x1 = plane_state->crtc_x;
2633 intel_state->dst.y1 = plane_state->crtc_y;
2634 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2635 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2636
88595ac9
DV
2637 obj = intel_fb_obj(fb);
2638 if (obj->tiling_mode != I915_TILING_NONE)
2639 dev_priv->preserve_bios_swizzle = true;
2640
be5651f2
ML
2641 drm_framebuffer_reference(fb);
2642 primary->fb = primary->state->fb = fb;
36750f28 2643 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2644 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2645 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB
2646}
2647
a8d201af
ML
2648static void i9xx_update_primary_plane(struct drm_plane *primary,
2649 const struct intel_crtc_state *crtc_state,
2650 const struct intel_plane_state *plane_state)
81255565 2651{
a8d201af 2652 struct drm_device *dev = primary->dev;
81255565 2653 struct drm_i915_private *dev_priv = dev->dev_private;
a8d201af
ML
2654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2655 struct drm_framebuffer *fb = plane_state->base.fb;
2656 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
81255565 2657 int plane = intel_crtc->plane;
54ea9da8 2658 u32 linear_offset;
81255565 2659 u32 dspcntr;
f0f59a00 2660 i915_reg_t reg = DSPCNTR(plane);
8d0deca8 2661 unsigned int rotation = plane_state->base.rotation;
ac484963 2662 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
54ea9da8
VS
2663 int x = plane_state->src.x1 >> 16;
2664 int y = plane_state->src.y1 >> 16;
c9ba6fad 2665
f45651ba
VS
2666 dspcntr = DISPPLANE_GAMMA_ENABLE;
2667
fdd508a6 2668 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS
2669
2670 if (INTEL_INFO(dev)->gen < 4) {
2671 if (intel_crtc->pipe == PIPE_B)
2672 dspcntr |= DISPPLANE_SEL_PIPE_B;
2673
2674 /* pipesrc and dspsize control the size that is scaled from,
2675 * which should always be the user's requested size.
2676 */
2677 I915_WRITE(DSPSIZE(plane),
a8d201af
ML
2678 ((crtc_state->pipe_src_h - 1) << 16) |
2679 (crtc_state->pipe_src_w - 1));
f45651ba 2680 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS
2681 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2682 I915_WRITE(PRIMSIZE(plane),
a8d201af
ML
2683 ((crtc_state->pipe_src_h - 1) << 16) |
2684 (crtc_state->pipe_src_w - 1));
c14b0485
VS
2685 I915_WRITE(PRIMPOS(plane), 0);
2686 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2687 }
81255565 2688
57779d06
VS
2689 switch (fb->pixel_format) {
2690 case DRM_FORMAT_C8:
81255565
JB
2691 dspcntr |= DISPPLANE_8BPP;
2692 break;
57779d06 2693 case DRM_FORMAT_XRGB1555:
57779d06 2694 dspcntr |= DISPPLANE_BGRX555;
81255565 2695 break;
57779d06
VS
2696 case DRM_FORMAT_RGB565:
2697 dspcntr |= DISPPLANE_BGRX565;
2698 break;
2699 case DRM_FORMAT_XRGB8888:
57779d06
VS
2700 dspcntr |= DISPPLANE_BGRX888;
2701 break;
2702 case DRM_FORMAT_XBGR8888:
57779d06
VS
2703 dspcntr |= DISPPLANE_RGBX888;
2704 break;
2705 case DRM_FORMAT_XRGB2101010:
57779d06
VS
2706 dspcntr |= DISPPLANE_BGRX101010;
2707 break;
2708 case DRM_FORMAT_XBGR2101010:
57779d06 2709 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB
2710 break;
2711 default:
baba133a 2712 BUG();
81255565 2713 }
57779d06 2714
f45651ba
VS
2715 if (INTEL_INFO(dev)->gen >= 4 &&
2716 obj->tiling_mode != I915_TILING_NONE)
2717 dspcntr |= DISPPLANE_TILED;
81255565 2718
de1aa629
VS
2719 if (IS_G4X(dev))
2720 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2721
ac484963 2722 linear_offset = y * fb->pitches[0] + x * cpp;
81255565 2723
c2c75131
DV
2724 if (INTEL_INFO(dev)->gen >= 4) {
2725 intel_crtc->dspaddr_offset =
4f2d9934 2726 intel_compute_tile_offset(&x, &y, fb, 0,
8d0deca8 2727 fb->pitches[0], rotation);
c2c75131
DV
2728 linear_offset -= intel_crtc->dspaddr_offset;
2729 } else {
e506a0c6 2730 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2731 }
e506a0c6 2732
8d0deca8 2733 if (rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ
2734 dspcntr |= DISPPLANE_ROTATE_180;
2735
a8d201af
ML
2736 x += (crtc_state->pipe_src_w - 1);
2737 y += (crtc_state->pipe_src_h - 1);
48404c1e
SJ
2738
2739 /* Finding the last pixel of the last line of the display
2740 data and adding to linear_offset*/
2741 linear_offset +=
a8d201af 2742 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
ac484963 2743 (crtc_state->pipe_src_w - 1) * cpp;
48404c1e
SJ
2744 }
2745
2db3366b
PZ
2746 intel_crtc->adjusted_x = x;
2747 intel_crtc->adjusted_y = y;
2748
48404c1e
SJ
2749 I915_WRITE(reg, dspcntr);
2750
01f2c773 2751 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2752 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV
2753 I915_WRITE(DSPSURF(plane),
2754 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2755 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2756 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2757 } else
f343c5f6 2758 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2759 POSTING_READ(reg);
17638cd6
JB
2760}
2761
a8d201af
ML
2762static void i9xx_disable_primary_plane(struct drm_plane *primary,
2763 struct drm_crtc *crtc)
17638cd6
JB
2764{
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
17638cd6 2768 int plane = intel_crtc->plane;
f45651ba 2769
a8d201af
ML
2770 I915_WRITE(DSPCNTR(plane), 0);
2771 if (INTEL_INFO(dev_priv)->gen >= 4)
fdd508a6 2772 I915_WRITE(DSPSURF(plane), 0);
a8d201af
ML
2773 else
2774 I915_WRITE(DSPADDR(plane), 0);
2775 POSTING_READ(DSPCNTR(plane));
2776}
c9ba6fad 2777
a8d201af
ML
2778static void ironlake_update_primary_plane(struct drm_plane *primary,
2779 const struct intel_crtc_state *crtc_state,
2780 const struct intel_plane_state *plane_state)
2781{
2782 struct drm_device *dev = primary->dev;
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2785 struct drm_framebuffer *fb = plane_state->base.fb;
2786 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2787 int plane = intel_crtc->plane;
54ea9da8 2788 u32 linear_offset;
a8d201af
ML
2789 u32 dspcntr;
2790 i915_reg_t reg = DSPCNTR(plane);
8d0deca8 2791 unsigned int rotation = plane_state->base.rotation;
ac484963 2792 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
a8d201af
ML
2793 int x = plane_state->src.x1 >> 16;
2794 int y = plane_state->src.y1 >> 16;
c9ba6fad 2795
f45651ba 2796 dspcntr = DISPPLANE_GAMMA_ENABLE;
fdd508a6 2797 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS
2798
2799 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2800 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2801
57779d06
VS
2802 switch (fb->pixel_format) {
2803 case DRM_FORMAT_C8:
17638cd6
JB
2804 dspcntr |= DISPPLANE_8BPP;
2805 break;
57779d06
VS
2806 case DRM_FORMAT_RGB565:
2807 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2808 break;
57779d06 2809 case DRM_FORMAT_XRGB8888:
57779d06
VS
2810 dspcntr |= DISPPLANE_BGRX888;
2811 break;
2812 case DRM_FORMAT_XBGR8888:
57779d06
VS
2813 dspcntr |= DISPPLANE_RGBX888;
2814 break;
2815 case DRM_FORMAT_XRGB2101010:
57779d06
VS
2816 dspcntr |= DISPPLANE_BGRX101010;
2817 break;
2818 case DRM_FORMAT_XBGR2101010:
57779d06 2819 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB
2820 break;
2821 default:
baba133a 2822 BUG();
17638cd6
JB
2823 }
2824
2825 if (obj->tiling_mode != I915_TILING_NONE)
2826 dspcntr |= DISPPLANE_TILED;
17638cd6 2827
f45651ba 2828 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2829 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2830
ac484963 2831 linear_offset = y * fb->pitches[0] + x * cpp;
c2c75131 2832 intel_crtc->dspaddr_offset =
4f2d9934 2833 intel_compute_tile_offset(&x, &y, fb, 0,
8d0deca8 2834 fb->pitches[0], rotation);
c2c75131 2835 linear_offset -= intel_crtc->dspaddr_offset;
8d0deca8 2836 if (rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ
2837 dspcntr |= DISPPLANE_ROTATE_180;
2838
2839 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
a8d201af
ML
2840 x += (crtc_state->pipe_src_w - 1);
2841 y += (crtc_state->pipe_src_h - 1);
48404c1e
SJ
2842
2843 /* Finding the last pixel of the last line of the display
2844 data and adding to linear_offset*/
2845 linear_offset +=
a8d201af 2846 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
ac484963 2847 (crtc_state->pipe_src_w - 1) * cpp;
48404c1e
SJ
2848 }
2849 }
2850
2db3366b
PZ
2851 intel_crtc->adjusted_x = x;
2852 intel_crtc->adjusted_y = y;
2853
48404c1e 2854 I915_WRITE(reg, dspcntr);
17638cd6 2855
01f2c773 2856 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV
2857 I915_WRITE(DSPSURF(plane),
2858 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2859 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL
2860 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2861 } else {
2862 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2863 I915_WRITE(DSPLINOFF(plane), linear_offset);
2864 }
17638cd6 2865 POSTING_READ(reg);
17638cd6
JB
2866}
2867
7b49f948
VS
2868u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2869 uint64_t fb_modifier, uint32_t pixel_format)
b321803d 2870{
7b49f948 2871 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
b321803d 2872 return 64;
7b49f948
VS
2873 } else {
2874 int cpp = drm_format_plane_cpp(pixel_format, 0);
2875
27ba3910 2876 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
b321803d
DL
2877 }
2878}
2879
44eb0cb9
MK
2880u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2881 struct drm_i915_gem_object *obj,
2882 unsigned int plane)
121920fa 2883{
ce7f1728 2884 struct i915_ggtt_view view;
dedf278c 2885 struct i915_vma *vma;
44eb0cb9 2886 u64 offset;
121920fa 2887
e7941294 2888 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
3465c580 2889 intel_plane->base.state->rotation);
121920fa 2890
ce7f1728 2891 vma = i915_gem_obj_to_ggtt_view(obj, &view);
dedf278c 2892 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
ce7f1728 2893 view.type))
dedf278c
TU
2894 return -1;
2895
44eb0cb9 2896 offset = vma->node.start;
dedf278c
TU
2897
2898 if (plane == 1) {
7723f47d 2899 offset += vma->ggtt_view.params.rotated.uv_start_page *
dedf278c
TU
2900 PAGE_SIZE;
2901 }
2902
44eb0cb9
MK
2903 WARN_ON(upper_32_bits(offset));
2904
2905 return lower_32_bits(offset);
121920fa
TU
2906}
2907
e435d6e5
ML
2908static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2909{
2910 struct drm_device *dev = intel_crtc->base.dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912
2913 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2914 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2915 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML
2916}
2917
a1b2278e
CK
2918/*
2919 * This function detaches (aka. unbinds) unused scalers in hardware
2920 */
0583236e 2921static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2922{
a1b2278e
CK
2923 struct intel_crtc_scaler_state *scaler_state;
2924 int i;
2925
a1b2278e
CK
2926 scaler_state = &intel_crtc->config->scaler_state;
2927
2928 /* loop through and disable scalers that aren't in use */
2929 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML
2930 if (!scaler_state->scalers[i].in_use)
2931 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK
2932 }
2933}
2934
6156a456 2935u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2936{
6156a456 2937 switch (pixel_format) {
d161cf7a 2938 case DRM_FORMAT_C8:
c34ce3d1 2939 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2940 case DRM_FORMAT_RGB565:
c34ce3d1 2941 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2942 case DRM_FORMAT_XBGR8888:
c34ce3d1 2943 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2944 case DRM_FORMAT_XRGB8888:
c34ce3d1 2945 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK
2946 /*
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2950 */
f75fb42a 2951 case DRM_FORMAT_ABGR8888:
c34ce3d1 2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2954 case DRM_FORMAT_ARGB8888:
c34ce3d1 2955 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2957 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2959 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2960 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2961 case DRM_FORMAT_YUYV:
c34ce3d1 2962 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2963 case DRM_FORMAT_YVYU:
c34ce3d1 2964 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2965 case DRM_FORMAT_UYVY:
c34ce3d1 2966 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2967 case DRM_FORMAT_VYUY:
c34ce3d1 2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2969 default:
4249eeef 2970 MISSING_CASE(pixel_format);
70d21f0e 2971 }
8cfcba41 2972
c34ce3d1 2973 return 0;
6156a456 2974}
70d21f0e 2975
6156a456
CK
2976u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2977{
6156a456 2978 switch (fb_modifier) {
30af77c4 2979 case DRM_FORMAT_MOD_NONE:
70d21f0e 2980 break;
30af77c4 2981 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2982 return PLANE_CTL_TILED_X;
b321803d 2983 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2984 return PLANE_CTL_TILED_Y;
b321803d 2985 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2986 return PLANE_CTL_TILED_YF;
70d21f0e 2987 default:
6156a456 2988 MISSING_CASE(fb_modifier);
70d21f0e 2989 }
8cfcba41 2990
c34ce3d1 2991 return 0;
6156a456 2992}
70d21f0e 2993
6156a456
CK
2994u32 skl_plane_ctl_rotation(unsigned int rotation)
2995{
3b7a5119 2996 switch (rotation) {
6156a456
CK
2997 case BIT(DRM_ROTATE_0):
2998 break;
1e8df167
SJ
2999 /*
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3002 */
3b7a5119 3003 case BIT(DRM_ROTATE_90):
1e8df167 3004 return PLANE_CTL_ROTATE_270;
3b7a5119 3005 case BIT(DRM_ROTATE_180):
c34ce3d1 3006 return PLANE_CTL_ROTATE_180;
3b7a5119 3007 case BIT(DRM_ROTATE_270):
1e8df167 3008 return PLANE_CTL_ROTATE_90;
6156a456
CK
3009 default:
3010 MISSING_CASE(rotation);
3011 }
3012
c34ce3d1 3013 return 0;
6156a456
CK
3014}
3015
a8d201af
ML
3016static void skylake_update_primary_plane(struct drm_plane *plane,
3017 const struct intel_crtc_state *crtc_state,
3018 const struct intel_plane_state *plane_state)
6156a456 3019{
a8d201af 3020 struct drm_device *dev = plane->dev;
6156a456 3021 struct drm_i915_private *dev_priv = dev->dev_private;
a8d201af
ML
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3023 struct drm_framebuffer *fb = plane_state->base.fb;
3024 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6156a456
CK
3025 int pipe = intel_crtc->pipe;
3026 u32 plane_ctl, stride_div, stride;
3027 u32 tile_height, plane_offset, plane_size;
a8d201af 3028 unsigned int rotation = plane_state->base.rotation;
6156a456 3029 int x_offset, y_offset;
44eb0cb9 3030 u32 surf_addr;
a8d201af
ML
3031 int scaler_id = plane_state->scaler_id;
3032 int src_x = plane_state->src.x1 >> 16;
3033 int src_y = plane_state->src.y1 >> 16;
3034 int src_w = drm_rect_width(&plane_state->src) >> 16;
3035 int src_h = drm_rect_height(&plane_state->src) >> 16;
3036 int dst_x = plane_state->dst.x1;
3037 int dst_y = plane_state->dst.y1;
3038 int dst_w = drm_rect_width(&plane_state->dst);
3039 int dst_h = drm_rect_height(&plane_state->dst);
70d21f0e 3040
6156a456
CK
3041 plane_ctl = PLANE_CTL_ENABLE |
3042 PLANE_CTL_PIPE_GAMMA_ENABLE |
3043 PLANE_CTL_PIPE_CSC_ENABLE;
3044
3045 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3046 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3047 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
6156a456
CK
3048 plane_ctl |= skl_plane_ctl_rotation(rotation);
3049
7b49f948 3050 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
b321803d 3051 fb->pixel_format);
dedf278c 3052 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3b7a5119 3053
a42e5a23
PZ
3054 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3055
3b7a5119 3056 if (intel_rotation_90_or_270(rotation)) {
832be82f
VS
3057 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3058
3b7a5119 3059 /* stride = Surface height in tiles */
832be82f 3060 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3b7a5119 3061 stride = DIV_ROUND_UP(fb->height, tile_height);
a8d201af
ML
3062 x_offset = stride * tile_height - src_y - src_h;
3063 y_offset = src_x;
6156a456 3064 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ
3065 } else {
3066 stride = fb->pitches[0] / stride_div;
a8d201af
ML
3067 x_offset = src_x;
3068 y_offset = src_y;
6156a456 3069 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ
3070 }
3071 plane_offset = y_offset << 16 | x_offset;
b321803d 3072
2db3366b
PZ
3073 intel_crtc->adjusted_x = x_offset;
3074 intel_crtc->adjusted_y = y_offset;
3075
70d21f0e 3076 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ
3077 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3078 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3079 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK
3080
3081 if (scaler_id >= 0) {
3082 uint32_t ps_ctrl = 0;
3083
3084 WARN_ON(!dst_w || !dst_h);
3085 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3086 crtc_state->scaler_state.scalers[scaler_id].mode;
3087 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3088 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3089 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3090 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3091 I915_WRITE(PLANE_POS(pipe, 0), 0);
3092 } else {
3093 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3094 }
3095
121920fa 3096 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL
3097
3098 POSTING_READ(PLANE_SURF(pipe, 0));
3099}
3100
a8d201af
ML
3101static void skylake_disable_primary_plane(struct drm_plane *primary,
3102 struct drm_crtc *crtc)
17638cd6
JB
3103{
3104 struct drm_device *dev = crtc->dev;
3105 struct drm_i915_private *dev_priv = dev->dev_private;
a8d201af 3106 int pipe = to_intel_crtc(crtc)->pipe;
17638cd6 3107
a8d201af
ML
3108 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3109 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3110 POSTING_READ(PLANE_SURF(pipe, 0));
3111}
29b9bde6 3112
a8d201af
ML
3113/* Assume fb object is pinned & idle & fenced and just update base pointers */
3114static int
3115intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3116 int x, int y, enum mode_set_atomic state)
3117{
3118 /* Support for kgdboc is disabled, this needs a major rework. */
3119 DRM_ERROR("legacy panic handler not supported any more.\n");
3120
3121 return -ENODEV;
81255565
JB
3122}
3123
5a21b665
DV
3124static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3125{
3126 struct intel_crtc *crtc;
3127
3128 for_each_intel_crtc(dev_priv->dev, crtc)
3129 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3130}
3131
7514747d
VS
3132static void intel_update_primary_planes(struct drm_device *dev)
3133{
7514747d 3134 struct drm_crtc *crtc;
96a02917 3135
70e1e0ec 3136 for_each_crtc(dev, crtc) {
11c22da6
ML
3137 struct intel_plane *plane = to_intel_plane(crtc->primary);
3138 struct intel_plane_state *plane_state;
96a02917 3139
11c22da6 3140 drm_modeset_lock_crtc(crtc, &plane->base);
11c22da6
ML
3141 plane_state = to_intel_plane_state(plane->base.state);
3142
a8d201af
ML
3143 if (plane_state->visible)
3144 plane->update_plane(&plane->base,
3145 to_intel_crtc_state(crtc->state),
3146 plane_state);
11c22da6
ML
3147
3148 drm_modeset_unlock_crtc(crtc);
96a02917
VS
3149 }
3150}
3151
c033666a 3152void intel_prepare_reset(struct drm_i915_private *dev_priv)
7514747d
VS
3153{
3154 /* no reset support for gen2 */
c033666a 3155 if (IS_GEN2(dev_priv))
7514747d
VS
3156 return;
3157
3158 /* reset doesn't touch the display */
c033666a 3159 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
7514747d
VS
3160 return;
3161
c033666a 3162 drm_modeset_lock_all(dev_priv->dev);
f98ce92f
VS
3163 /*
3164 * Disabling the crtcs gracefully seems nicer. Also the
3165 * g33 docs say we should at least disable all the planes.
3166 */
c033666a 3167 intel_display_suspend(dev_priv->dev);
7514747d
VS
3168}
3169
c033666a 3170void intel_finish_reset(struct drm_i915_private *dev_priv)
7514747d 3171{
5a21b665
DV
3172 /*
3173 * Flips in the rings will be nuked by the reset,
3174 * so complete all pending flips so that user space
3175 * will get its events and not get stuck.
3176 */
3177 intel_complete_page_flips(dev_priv);
3178
7514747d 3179 /* no reset support for gen2 */
c033666a 3180 if (IS_GEN2(dev_priv))
7514747d
VS
3181 return;
3182
3183 /* reset doesn't touch the display */
c033666a 3184 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
7514747d
VS
3185 /*
3186 * Flips in the rings have been nuked by the reset,
3187 * so update the base address of all primary
3188 * planes to the the last fb to make sure we're
3189 * showing the correct fb after a reset.
11c22da6
ML
3190 *
3191 * FIXME: Atomic will make this obsolete since we won't schedule
3192 * CS-based flips (which might get lost in gpu resets) any more.
7514747d 3193 */
c033666a 3194 intel_update_primary_planes(dev_priv->dev);
7514747d
VS
3195 return;
3196 }
3197
3198 /*
3199 * The display has been reset as well,
3200 * so need a full re-initialization.
3201 */
3202 intel_runtime_pm_disable_interrupts(dev_priv);
3203 intel_runtime_pm_enable_interrupts(dev_priv);
3204
c033666a 3205 intel_modeset_init_hw(dev_priv->dev);
7514747d
VS
3206
3207 spin_lock_irq(&dev_priv->irq_lock);
3208 if (dev_priv->display.hpd_irq_setup)
91d14251 3209 dev_priv->display.hpd_irq_setup(dev_priv);
7514747d
VS
3210 spin_unlock_irq(&dev_priv->irq_lock);
3211
c033666a 3212 intel_display_resume(dev_priv->dev);
7514747d
VS
3213
3214 intel_hpd_init(dev_priv);
3215
c033666a 3216 drm_modeset_unlock_all(dev_priv->dev);
7514747d
VS
3217}
3218
7d5e3799
CW
3219static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3220{
5a21b665
DV
3221 struct drm_device *dev = crtc->dev;
3222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3223 unsigned reset_counter;
3224 bool pending;
3225
3226 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3227 if (intel_crtc->reset_counter != reset_counter)
3228 return false;
3229
3230 spin_lock_irq(&dev->event_lock);
3231 pending = to_intel_crtc(crtc)->flip_work != NULL;
3232 spin_unlock_irq(&dev->event_lock);
3233
3234 return pending;
7d5e3799
CW
3235}
3236
bfd16b2a
ML
3237static void intel_update_pipe_config(struct intel_crtc *crtc,
3238 struct intel_crtc_state *old_crtc_state)
e30e8f75
GP
3239{
3240 struct drm_device *dev = crtc->base.dev;
3241 struct drm_i915_private *dev_priv = dev->dev_private;
bfd16b2a
ML
3242 struct intel_crtc_state *pipe_config =
3243 to_intel_crtc_state(crtc->base.state);
e30e8f75 3244
bfd16b2a
ML
3245 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3246 crtc->base.mode = crtc->base.state->mode;
3247
3248 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3249 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3250 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
e30e8f75
GP
3251
3252 /*
3253 * Update pipe size and adjust fitter if needed: the reason for this is
3254 * that in compute_mode_changes we check the native mode (not the pfit
3255 * mode) to see if we can flip rather than do a full mode set. In the
3256 * fastboot case, we'll flip, but if we don't update the pipesrc and
3257 * pfit state, we'll end up with a big fb scanned out into the wrong
3258 * sized surface.
e30e8f75
GP
3259 */
3260
e30e8f75 3261 I915_WRITE(PIPESRC(crtc->pipe),
bfd16b2a
ML
3262 ((pipe_config->pipe_src_w - 1) << 16) |
3263 (pipe_config->pipe_src_h - 1));
3264
3265 /* on skylake this is done by detaching scalers */
3266 if (INTEL_INFO(dev)->gen >= 9) {
3267 skl_detach_scalers(crtc);
3268
3269 if (pipe_config->pch_pfit.enabled)
3270 skylake_pfit_enable(crtc);
3271 } else if (HAS_PCH_SPLIT(dev)) {
3272 if (pipe_config->pch_pfit.enabled)
3273 ironlake_pfit_enable(crtc);
3274 else if (old_crtc_state->pch_pfit.enabled)
3275 ironlake_pfit_disable(crtc, true);
e30e8f75 3276 }
e30e8f75
GP
3277}
3278
5e84e1a4
ZW
3279static void intel_fdi_normal_train(struct drm_crtc *crtc)
3280{
3281 struct drm_device *dev = crtc->dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284 int pipe = intel_crtc->pipe;
f0f59a00
VS
3285 i915_reg_t reg;
3286 u32 temp;
5e84e1a4
ZW
3287
3288 /* enable normal train */
3289 reg = FDI_TX_CTL(pipe);
3290 temp = I915_READ(reg);
61e499bf 3291 if (IS_IVYBRIDGE(dev)) {
357555c0
JB
3292 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3293 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP
3294 } else {
3295 temp &= ~FDI_LINK_TRAIN_NONE;
3296 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3297 }
5e84e1a4
ZW
3298 I915_WRITE(reg, temp);
3299
3300 reg = FDI_RX_CTL(pipe);
3301 temp = I915_READ(reg);
3302 if (HAS_PCH_CPT(dev)) {
3303 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3304 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3305 } else {
3306 temp &= ~FDI_LINK_TRAIN_NONE;
3307 temp |= FDI_LINK_TRAIN_NONE;
3308 }
3309 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3310
3311 /* wait one idle pattern time */
3312 POSTING_READ(reg);
3313 udelay(1000);
357555c0
JB
3314
3315 /* IVB wants error correction enabled */
3316 if (IS_IVYBRIDGE(dev))
3317 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3318 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW
3319}
3320
8db9d77b
ZW
3321/* The FDI link training functions for ILK/Ibexpeak. */
3322static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3323{
3324 struct drm_device *dev = crtc->dev;
3325 struct drm_i915_private *dev_priv = dev->dev_private;
3326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3327 int pipe = intel_crtc->pipe;
f0f59a00
VS
3328 i915_reg_t reg;
3329 u32 temp, tries;
8db9d77b 3330
1c8562f6 3331 /* FDI needs bits from pipe first */
0fc932b8 3332 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3333
e1a44743
AJ
3334 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3335 for train result */
5eddb70b
CW
3336 reg = FDI_RX_IMR(pipe);
3337 temp = I915_READ(reg);
e1a44743
AJ
3338 temp &= ~FDI_RX_SYMBOL_LOCK;
3339 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
3340 I915_WRITE(reg, temp);
3341 I915_READ(reg);
e1a44743
AJ
3342 udelay(150);
3343
8db9d77b 3344 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
3345 reg = FDI_TX_CTL(pipe);
3346 temp = I915_READ(reg);
627eb5a3 3347 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3348 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW
3349 temp &= ~FDI_LINK_TRAIN_NONE;
3350 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3351 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3352
5eddb70b
CW
3353 reg = FDI_RX_CTL(pipe);
3354 temp = I915_READ(reg);
8db9d77b
ZW
3355 temp &= ~FDI_LINK_TRAIN_NONE;
3356 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW
3357 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3358
3359 POSTING_READ(reg);
8db9d77b
ZW
3360 udelay(150);
3361
5b2adf89 3362 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV
3363 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3364 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3365 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3366
5eddb70b 3367 reg = FDI_RX_IIR(pipe);
e1a44743 3368 for (tries = 0; tries < 5; tries++) {
5eddb70b 3369 temp = I915_READ(reg);
8db9d77b
ZW
3370 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3371
3372 if ((temp & FDI_RX_BIT_LOCK)) {
3373 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3374 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW
3375 break;
3376 }
8db9d77b 3377 }
e1a44743 3378 if (tries == 5)
5eddb70b 3379 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
3380
3381 /* Train 2 */
5eddb70b
CW
3382 reg = FDI_TX_CTL(pipe);
3383 temp = I915_READ(reg);
8db9d77b
ZW
3384 temp &= ~FDI_LINK_TRAIN_NONE;
3385 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3386 I915_WRITE(reg, temp);
8db9d77b 3387
5eddb70b
CW
3388 reg = FDI_RX_CTL(pipe);
3389 temp = I915_READ(reg);
8db9d77b
ZW
3390 temp &= ~FDI_LINK_TRAIN_NONE;
3391 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3392 I915_WRITE(reg, temp);
8db9d77b 3393
5eddb70b
CW
3394 POSTING_READ(reg);
3395 udelay(150);
8db9d77b 3396
5eddb70b 3397 reg = FDI_RX_IIR(pipe);
e1a44743 3398 for (tries = 0; tries < 5; tries++) {
5eddb70b 3399 temp = I915_READ(reg);
8db9d77b
ZW
3400 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3401
3402 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3403 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW
3404 DRM_DEBUG_KMS("FDI train 2 done.\n");
3405 break;
3406 }
8db9d77b 3407 }
e1a44743 3408 if (tries == 5)
5eddb70b 3409 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
3410
3411 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3412
8db9d77b
ZW
3413}
3414
0206e353 3415static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW
3416 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3417 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3418 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3419 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3420};
3421
3422/* The FDI link training functions for SNB/Cougarpoint. */
3423static void gen6_fdi_link_train(struct drm_crtc *crtc)
3424{
3425 struct drm_device *dev = crtc->dev;
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3428 int pipe = intel_crtc->pipe;
f0f59a00
VS
3429 i915_reg_t reg;
3430 u32 temp, i, retry;
8db9d77b 3431
e1a44743
AJ
3432 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3433 for train result */
5eddb70b
CW
3434 reg = FDI_RX_IMR(pipe);
3435 temp = I915_READ(reg);
e1a44743
AJ
3436 temp &= ~FDI_RX_SYMBOL_LOCK;
3437 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
3438 I915_WRITE(reg, temp);
3439
3440 POSTING_READ(reg);
e1a44743
AJ
3441 udelay(150);
3442
8db9d77b 3443 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
3444 reg = FDI_TX_CTL(pipe);
3445 temp = I915_READ(reg);
627eb5a3 3446 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3447 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW
3448 temp &= ~FDI_LINK_TRAIN_NONE;
3449 temp |= FDI_LINK_TRAIN_PATTERN_1;
3450 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3451 /* SNB-B */
3452 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3453 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3454
d74cf324
DV
3455 I915_WRITE(FDI_RX_MISC(pipe),
3456 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3457
5eddb70b
CW
3458 reg = FDI_RX_CTL(pipe);
3459 temp = I915_READ(reg);
8db9d77b
ZW
3460 if (HAS_PCH_CPT(dev)) {
3461 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3462 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3463 } else {
3464 temp &= ~FDI_LINK_TRAIN_NONE;
3465 temp |= FDI_LINK_TRAIN_PATTERN_1;
3466 }
5eddb70b
CW
3467 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3468
3469 POSTING_READ(reg);
8db9d77b
ZW
3470 udelay(150);
3471
0206e353 3472 for (i = 0; i < 4; i++) {
5eddb70b
CW
3473 reg = FDI_TX_CTL(pipe);
3474 temp = I915_READ(reg);
8db9d77b
ZW
3475 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3476 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
3477 I915_WRITE(reg, temp);
3478
3479 POSTING_READ(reg);
8db9d77b
ZW
3480 udelay(500);
3481
fa37d39e
SP
3482 for (retry = 0; retry < 5; retry++) {
3483 reg = FDI_RX_IIR(pipe);
3484 temp = I915_READ(reg);
3485 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3486 if (temp & FDI_RX_BIT_LOCK) {
3487 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3488 DRM_DEBUG_KMS("FDI train 1 done.\n");
3489 break;
3490 }
3491 udelay(50);
8db9d77b 3492 }
fa37d39e
SP
3493 if (retry < 5)
3494 break;
8db9d77b
ZW
3495 }
3496 if (i == 4)
5eddb70b 3497 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
3498
3499 /* Train 2 */
5eddb70b
CW
3500 reg = FDI_TX_CTL(pipe);
3501 temp = I915_READ(reg);
8db9d77b
ZW
3502 temp &= ~FDI_LINK_TRAIN_NONE;
3503 temp |= FDI_LINK_TRAIN_PATTERN_2;
3504 if (IS_GEN6(dev)) {
3505 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3506 /* SNB-B */
3507 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3508 }
5eddb70b 3509 I915_WRITE(reg, temp);
8db9d77b 3510
5eddb70b
CW
3511 reg = FDI_RX_CTL(pipe);
3512 temp = I915_READ(reg);
8db9d77b
ZW
3513 if (HAS_PCH_CPT(dev)) {
3514 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3515 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3516 } else {
3517 temp &= ~FDI_LINK_TRAIN_NONE;
3518 temp |= FDI_LINK_TRAIN_PATTERN_2;
3519 }
5eddb70b
CW
3520 I915_WRITE(reg, temp);
3521
3522 POSTING_READ(reg);
8db9d77b
ZW
3523 udelay(150);
3524
0206e353 3525 for (i = 0; i < 4; i++) {
5eddb70b
CW
3526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
8db9d77b
ZW
3528 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3529 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
3530 I915_WRITE(reg, temp);
3531
3532 POSTING_READ(reg);
8db9d77b
ZW
3533 udelay(500);
3534
fa37d39e
SP
3535 for (retry = 0; retry < 5; retry++) {
3536 reg = FDI_RX_IIR(pipe);
3537 temp = I915_READ(reg);
3538 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3539 if (temp & FDI_RX_SYMBOL_LOCK) {
3540 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3541 DRM_DEBUG_KMS("FDI train 2 done.\n");
3542 break;
3543 }
3544 udelay(50);
8db9d77b 3545 }
fa37d39e
SP
3546 if (retry < 5)
3547 break;
8db9d77b
ZW
3548 }
3549 if (i == 4)
5eddb70b 3550 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
3551
3552 DRM_DEBUG_KMS("FDI train done.\n");
3553}
3554
357555c0
JB
3555/* Manual link training for Ivy Bridge A0 parts */
3556static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3557{
3558 struct drm_device *dev = crtc->dev;
3559 struct drm_i915_private *dev_priv = dev->dev_private;
3560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3561 int pipe = intel_crtc->pipe;
f0f59a00
VS
3562 i915_reg_t reg;
3563 u32 temp, i, j;
357555c0
JB
3564
3565 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3566 for train result */
3567 reg = FDI_RX_IMR(pipe);
3568 temp = I915_READ(reg);
3569 temp &= ~FDI_RX_SYMBOL_LOCK;
3570 temp &= ~FDI_RX_BIT_LOCK;
3571 I915_WRITE(reg, temp);
3572
3573 POSTING_READ(reg);
3574 udelay(150);
3575
01a415fd
DV
3576 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3577 I915_READ(FDI_RX_IIR(pipe)));
3578
139ccd3f
JB
3579 /* Try each vswing and preemphasis setting twice before moving on */
3580 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3581 /* disable first in case we need to retry */
3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
3584 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3585 temp &= ~FDI_TX_ENABLE;
3586 I915_WRITE(reg, temp);
357555c0 3587
139ccd3f
JB
3588 reg = FDI_RX_CTL(pipe);
3589 temp = I915_READ(reg);
3590 temp &= ~FDI_LINK_TRAIN_AUTO;
3591 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3592 temp &= ~FDI_RX_ENABLE;
3593 I915_WRITE(reg, temp);
357555c0 3594
139ccd3f 3595 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB
3596 reg = FDI_TX_CTL(pipe);
3597 temp = I915_READ(reg);
139ccd3f 3598 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3599 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3600 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB
3602 temp |= snb_b_fdi_train_param[j/2];
3603 temp |= FDI_COMPOSITE_SYNC;
3604 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3605
139ccd3f
JB
3606 I915_WRITE(FDI_RX_MISC(pipe),
3607 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3608
139ccd3f 3609 reg = FDI_RX_CTL(pipe);
357555c0 3610 temp = I915_READ(reg);
139ccd3f
JB
3611 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3612 temp |= FDI_COMPOSITE_SYNC;
3613 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3614
139ccd3f
JB
3615 POSTING_READ(reg);
3616 udelay(1); /* should be 0.5us */
357555c0 3617
139ccd3f
JB
3618 for (i = 0; i < 4; i++) {
3619 reg = FDI_RX_IIR(pipe);
3620 temp = I915_READ(reg);
3621 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3622
139ccd3f
JB
3623 if (temp & FDI_RX_BIT_LOCK ||
3624 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3625 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3626 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3627 i);
3628 break;
3629 }
3630 udelay(1); /* should be 0.5us */
3631 }
3632 if (i == 4) {
3633 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3634 continue;
3635 }
357555c0 3636
139ccd3f 3637 /* Train 2 */
357555c0
JB
3638 reg = FDI_TX_CTL(pipe);
3639 temp = I915_READ(reg);
139ccd3f
JB
3640 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3641 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3642 I915_WRITE(reg, temp);
3643
3644 reg = FDI_RX_CTL(pipe);
3645 temp = I915_READ(reg);
3646 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3647 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB
3648 I915_WRITE(reg, temp);
3649
3650 POSTING_READ(reg);
139ccd3f 3651 udelay(2); /* should be 1.5us */
357555c0 3652
139ccd3f
JB
3653 for (i = 0; i < 4; i++) {
3654 reg = FDI_RX_IIR(pipe);
3655 temp = I915_READ(reg);
3656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3657
139ccd3f
JB
3658 if (temp & FDI_RX_SYMBOL_LOCK ||
3659 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3660 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3661 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3662 i);
3663 goto train_done;
3664 }
3665 udelay(2); /* should be 1.5us */
357555c0 3666 }
139ccd3f
JB
3667 if (i == 4)
3668 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3669 }
357555c0 3670
139ccd3f 3671train_done:
357555c0
JB
3672 DRM_DEBUG_KMS("FDI train done.\n");
3673}
3674
88cefb6c 3675static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3676{
88cefb6c 3677 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3678 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3679 int pipe = intel_crtc->pipe;
f0f59a00
VS
3680 i915_reg_t reg;
3681 u32 temp;
c64e311e 3682
c98e9dcf 3683 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW
3684 reg = FDI_RX_CTL(pipe);
3685 temp = I915_READ(reg);
627eb5a3 3686 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3687 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3688 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW
3689 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3690
3691 POSTING_READ(reg);
c98e9dcf
JB
3692 udelay(200);
3693
3694 /* Switch from Rawclk to PCDclk */
5eddb70b
CW
3695 temp = I915_READ(reg);
3696 I915_WRITE(reg, temp | FDI_PCDCLK);
3697
3698 POSTING_READ(reg);
c98e9dcf
JB
3699 udelay(200);
3700
20749730
PZ
3701 /* Enable CPU FDI TX PLL, always on for Ironlake */
3702 reg = FDI_TX_CTL(pipe);
3703 temp = I915_READ(reg);
3704 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3705 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3706
20749730
PZ
3707 POSTING_READ(reg);
3708 udelay(100);
6be4a607 3709 }
0e23b99d
JB
3710}
3711
88cefb6c
DV
3712static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3713{
3714 struct drm_device *dev = intel_crtc->base.dev;
3715 struct drm_i915_private *dev_priv = dev->dev_private;
3716 int pipe = intel_crtc->pipe;
f0f59a00
VS
3717 i915_reg_t reg;
3718 u32 temp;
88cefb6c
DV
3719
3720 /* Switch from PCDclk to Rawclk */
3721 reg = FDI_RX_CTL(pipe);
3722 temp = I915_READ(reg);
3723 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3724
3725 /* Disable CPU FDI TX PLL */
3726 reg = FDI_TX_CTL(pipe);
3727 temp = I915_READ(reg);
3728 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3729
3730 POSTING_READ(reg);
3731 udelay(100);
3732
3733 reg = FDI_RX_CTL(pipe);
3734 temp = I915_READ(reg);
3735 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3736
3737 /* Wait for the clocks to turn off. */
3738 POSTING_READ(reg);
3739 udelay(100);
3740}
3741
0fc932b8
JB
3742static void ironlake_fdi_disable(struct drm_crtc *crtc)
3743{
3744 struct drm_device *dev = crtc->dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3747 int pipe = intel_crtc->pipe;
f0f59a00
VS
3748 i915_reg_t reg;
3749 u32 temp;
0fc932b8
JB
3750
3751 /* disable CPU FDI tx and PCH FDI rx */
3752 reg = FDI_TX_CTL(pipe);
3753 temp = I915_READ(reg);
3754 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3755 POSTING_READ(reg);
3756
3757 reg = FDI_RX_CTL(pipe);
3758 temp = I915_READ(reg);
3759 temp &= ~(0x7 << 16);
dfd07d72 3760 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB
3761 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3762
3763 POSTING_READ(reg);
3764 udelay(100);
3765
3766 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3767 if (HAS_PCH_IBX(dev))
6f06ce18 3768 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB
3769
3770 /* still set train pattern 1 */
3771 reg = FDI_TX_CTL(pipe);
3772 temp = I915_READ(reg);
3773 temp &= ~FDI_LINK_TRAIN_NONE;
3774 temp |= FDI_LINK_TRAIN_PATTERN_1;
3775 I915_WRITE(reg, temp);
3776
3777 reg = FDI_RX_CTL(pipe);
3778 temp = I915_READ(reg);
3779 if (HAS_PCH_CPT(dev)) {
3780 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3781 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3782 } else {
3783 temp &= ~FDI_LINK_TRAIN_NONE;
3784 temp |= FDI_LINK_TRAIN_PATTERN_1;
3785 }
3786 /* BPC in FDI rx is consistent with that in PIPECONF */
3787 temp &= ~(0x07 << 16);
dfd07d72 3788 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB
3789 I915_WRITE(reg, temp);
3790
3791 POSTING_READ(reg);
3792 udelay(100);
3793}
3794
5dce5b93
CW
3795bool intel_has_pending_fb_unpin(struct drm_device *dev)
3796{
3797 struct intel_crtc *crtc;
3798
3799 /* Note that we don't need to be called with mode_config.lock here
3800 * as our list of CRTC objects is static for the lifetime of the
3801 * device and so cannot disappear as we iterate. Similarly, we can
3802 * happily treat the predicates as racy, atomic checks as userspace
3803 * cannot claim and pin a new fb without at least acquring the
3804 * struct_mutex and so serialising with us.
3805 */
d3fcc808 3806 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW
3807 if (atomic_read(&crtc->unpin_work_count) == 0)
3808 continue;
3809
5a21b665 3810 if (crtc->flip_work)
5dce5b93
CW
3811 intel_wait_for_vblank(dev, crtc->pipe);
3812
3813 return true;
3814 }
3815
3816 return false;
3817}
3818
5a21b665 3819static void page_flip_completed(struct intel_crtc *intel_crtc)
d6bbafa1
CW
3820{
3821 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5a21b665
DV
3822 struct intel_flip_work *work = intel_crtc->flip_work;
3823
3824 intel_crtc->flip_work = NULL;
d6bbafa1
CW
3825
3826 if (work->event)
560ce1dc 3827 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
d6bbafa1
CW
3828
3829 drm_crtc_vblank_put(&intel_crtc->base);
3830
5a21b665 3831 wake_up_all(&dev_priv->pending_flip_queue);
143f73b3 3832 queue_work(dev_priv->wq, &work->unpin_work);
5a21b665
DV
3833
3834 trace_i915_flip_complete(intel_crtc->plane,
3835 work->pending_flip_obj);
d6bbafa1
CW
3836}
3837
5008e874 3838static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3839{
0f91128d 3840 struct drm_device *dev = crtc->dev;
5bb61643 3841 struct drm_i915_private *dev_priv = dev->dev_private;
5008e874 3842 long ret;
e6c3a2a6 3843
2c10d571 3844 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
5008e874
ML
3845
3846 ret = wait_event_interruptible_timeout(
3847 dev_priv->pending_flip_queue,
3848 !intel_crtc_has_pending_flip(crtc),
3849 60*HZ);
3850
3851 if (ret < 0)
3852 return ret;
3853
5a21b665
DV
3854 if (ret == 0) {
3855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3856 struct intel_flip_work *work;
3857
3858 spin_lock_irq(&dev->event_lock);
3859 work = intel_crtc->flip_work;
3860 if (work && !is_mmio_work(work)) {
3861 WARN_ONCE(1, "Removing stuck page flip\n");
3862 page_flip_completed(intel_crtc);
3863 }
3864 spin_unlock_irq(&dev->event_lock);
3865 }
5bb61643 3866
5008e874 3867 return 0;
e6c3a2a6
CW
3868}
3869
060f02d8
VS
3870static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3871{
3872 u32 temp;
3873
3874 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3875
3876 mutex_lock(&dev_priv->sb_lock);
3877
3878 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3879 temp |= SBI_SSCCTL_DISABLE;
3880 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3881
3882 mutex_unlock(&dev_priv->sb_lock);
3883}
3884
e615efe4
ED
3885/* Program iCLKIP clock to the desired frequency */
3886static void lpt_program_iclkip(struct drm_crtc *crtc)
3887{
64b46a06 3888 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6e3c9717 3889 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED
3890 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3891 u32 temp;
3892
060f02d8 3893 lpt_disable_iclkip(dev_priv);
e615efe4 3894
64b46a06
VS
3895 /* The iCLK virtual clock root frequency is in MHz,
3896 * but the adjusted_mode->crtc_clock in in KHz. To get the
3897 * divisors, it is necessary to divide one by another, so we
3898 * convert the virtual clock precision to KHz here for higher
3899 * precision.
3900 */
3901 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
e615efe4
ED
3902 u32 iclk_virtual_root_freq = 172800 * 1000;
3903 u32 iclk_pi_range = 64;
64b46a06 3904 u32 desired_divisor;
e615efe4 3905
64b46a06
VS
3906 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3907 clock << auxdiv);
3908 divsel = (desired_divisor / iclk_pi_range) - 2;
3909 phaseinc = desired_divisor % iclk_pi_range;
e615efe4 3910
64b46a06
VS
3911 /*
3912 * Near 20MHz is a corner case which is
3913 * out of range for the 7-bit divisor
3914 */
3915 if (divsel <= 0x7f)
3916 break;
e615efe4
ED
3917 }
3918
3919 /* This should not happen with any sane values */
3920 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3921 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3922 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3923 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3924
3925 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3926 clock,
e615efe4
ED
3927 auxdiv,
3928 divsel,
3929 phasedir,
3930 phaseinc);
3931
060f02d8
VS
3932 mutex_lock(&dev_priv->sb_lock);
3933
e615efe4 3934 /* Program SSCDIVINTPHASE6 */
988d6ee8 3935 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED
3936 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3937 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3938 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3939 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3940 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3941 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3942 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED
3943
3944 /* Program SSCAUXDIV */
988d6ee8 3945 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED
3946 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3947 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3948 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED
3949
3950 /* Enable modulator and associated divider */
988d6ee8 3951 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3952 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3953 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4 3954
060f02d8
VS
3955 mutex_unlock(&dev_priv->sb_lock);
3956
e615efe4
ED
3957 /* Wait for initialization time */
3958 udelay(24);
3959
3960 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3961}
3962
8802e5b6
VS
3963int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3964{
3965 u32 divsel, phaseinc, auxdiv;
3966 u32 iclk_virtual_root_freq = 172800 * 1000;
3967 u32 iclk_pi_range = 64;
3968 u32 desired_divisor;
3969 u32 temp;
3970
3971 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3972 return 0;
3973
3974 mutex_lock(&dev_priv->sb_lock);
3975
3976 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3977 if (temp & SBI_SSCCTL_DISABLE) {
3978 mutex_unlock(&dev_priv->sb_lock);
3979 return 0;
3980 }
3981
3982 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3983 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3984 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3985 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3986 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3987
3988 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3989 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3990 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3991
3992 mutex_unlock(&dev_priv->sb_lock);
3993
3994 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3995
3996 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3997 desired_divisor << auxdiv);
3998}
3999
275f01b2
DV
4000static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4001 enum pipe pch_transcoder)
4002{
4003 struct drm_device *dev = crtc->base.dev;
4004 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4005 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV
4006
4007 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4008 I915_READ(HTOTAL(cpu_transcoder)));
4009 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4010 I915_READ(HBLANK(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4012 I915_READ(HSYNC(cpu_transcoder)));
4013
4014 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4015 I915_READ(VTOTAL(cpu_transcoder)));
4016 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4017 I915_READ(VBLANK(cpu_transcoder)));
4018 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4019 I915_READ(VSYNC(cpu_transcoder)));
4020 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4021 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4022}
4023
003632d9 4024static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV
4025{
4026 struct drm_i915_private *dev_priv = dev->dev_private;
4027 uint32_t temp;
4028
4029 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4030 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV
4031 return;
4032
4033 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4034 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4035
003632d9
ACO
4036 temp &= ~FDI_BC_BIFURCATION_SELECT;
4037 if (enable)
4038 temp |= FDI_BC_BIFURCATION_SELECT;
4039
4040 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV
4041 I915_WRITE(SOUTH_CHICKEN1, temp);
4042 POSTING_READ(SOUTH_CHICKEN1);
4043}
4044
4045static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4046{
4047 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV
4048
4049 switch (intel_crtc->pipe) {
4050 case PIPE_A:
4051 break;
4052 case PIPE_B:
6e3c9717 4053 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4054 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4055 else
003632d9 4056 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV
4057
4058 break;
4059 case PIPE_C:
003632d9 4060 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV
4061
4062 break;
4063 default:
4064 BUG();
4065 }
4066}
4067
c48b5305
VS
4068/* Return which DP Port should be selected for Transcoder DP control */
4069static enum port
4070intel_trans_dp_port_sel(struct drm_crtc *crtc)
4071{
4072 struct drm_device *dev = crtc->dev;
4073 struct intel_encoder *encoder;
4074
4075 for_each_encoder_on_crtc(dev, crtc, encoder) {
4076 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4077 encoder->type == INTEL_OUTPUT_EDP)
4078 return enc_to_dig_port(&encoder->base)->port;
4079 }
4080
4081 return -1;
4082}
4083
f67a559d
JB
4084/*
4085 * Enable PCH resources required for PCH ports:
4086 * - PCH PLLs
4087 * - FDI training & RX/TX
4088 * - update transcoder timings
4089 * - DP transcoding bits
4090 * - transcoder
4091 */
4092static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB
4093{
4094 struct drm_device *dev = crtc->dev;
4095 struct drm_i915_private *dev_priv = dev->dev_private;
4096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4097 int pipe = intel_crtc->pipe;
f0f59a00 4098 u32 temp;
2c07245f 4099
ab9412ba 4100 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4101
1fbc0d78
DV
4102 if (IS_IVYBRIDGE(dev))
4103 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4104
cd986abb
DV
4105 /* Write the TU size bits before fdi link training, so that error
4106 * detection works. */
4107 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4108 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4109
c98e9dcf 4110 /* For PCH output, training FDI link */
674cf967 4111 dev_priv->display.fdi_link_train(crtc);
2c07245f 4112
3ad8a208
DV
4113 /* We need to program the right clock selection before writing the pixel
4114 * mutliplier into the DPLL. */
303b81e0 4115 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4116 u32 sel;
4b645f14 4117
c98e9dcf 4118 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV
4119 temp |= TRANS_DPLL_ENABLE(pipe);
4120 sel = TRANS_DPLLB_SEL(pipe);
8106ddbd
ACO
4121 if (intel_crtc->config->shared_dpll ==
4122 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
ee7b9f93
JB
4123 temp |= sel;
4124 else
4125 temp &= ~sel;
c98e9dcf 4126 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4127 }
5eddb70b 4128
3ad8a208
DV
4129 /* XXX: pch pll's can be enabled any time before we enable the PCH
4130 * transcoder, and we actually should do this to not upset any PCH
4131 * transcoder that already use the clock when we share it.
4132 *
4133 * Note that enable_shared_dpll tries to do the right thing, but
4134 * get_shared_dpll unconditionally resets the pll - we need that to have
4135 * the right LVDS enable sequence. */
85b3894f 4136 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4137
d9b6cb56
JB
4138 /* set transcoder timing, panel must allow it */
4139 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4140 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4141
303b81e0 4142 intel_fdi_normal_train(crtc);
5e84e1a4 4143
c98e9dcf 4144 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4145 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
9c4edaee
VS
4146 const struct drm_display_mode *adjusted_mode =
4147 &intel_crtc->config->base.adjusted_mode;
dfd07d72 4148 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
f0f59a00 4149 i915_reg_t reg = TRANS_DP_CTL(pipe);
5eddb70b
CW
4150 temp = I915_READ(reg);
4151 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA
4152 TRANS_DP_SYNC_MASK |
4153 TRANS_DP_BPC_MASK);
e3ef4479 4154 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4155 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf 4156
9c4edaee 4157 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4158 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
9c4edaee 4159 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4160 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB
4161
4162 switch (intel_trans_dp_port_sel(crtc)) {
c48b5305 4163 case PORT_B:
5eddb70b 4164 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 4165 break;
c48b5305 4166 case PORT_C:
5eddb70b 4167 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf 4168 break;
c48b5305 4169 case PORT_D:
5eddb70b 4170 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB
4171 break;
4172 default:
e95d41e1 4173 BUG();
32f9d658 4174 }
2c07245f 4175
5eddb70b 4176 I915_WRITE(reg, temp);
6be4a607 4177 }
b52eb4dc 4178
b8a4f404 4179 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB
4180}
4181
1507e5bd
PZ
4182static void lpt_pch_enable(struct drm_crtc *crtc)
4183{
4184 struct drm_device *dev = crtc->dev;
4185 struct drm_i915_private *dev_priv = dev->dev_private;
4186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4187 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4188
ab9412ba 4189 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4190
8c52b5e8 4191 lpt_program_iclkip(crtc);
1507e5bd 4192
0540e488 4193 /* Set transcoder timing. */
275f01b2 4194 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4195
937bb610 4196 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB
4197}
4198
a1520318 4199static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB
4200{
4201 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 4202 i915_reg_t dslreg = PIPEDSL(pipe);
d4270e57
JB
4203 u32 temp;
4204
4205 temp = I915_READ(dslreg);
4206 udelay(500);
4207 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4208 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4209 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB
4210 }
4211}
4212
86adf9d7
ML
4213static int
4214skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4215 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4216 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4217{
86adf9d7
ML
4218 struct intel_crtc_scaler_state *scaler_state =
4219 &crtc_state->scaler_state;
4220 struct intel_crtc *intel_crtc =
4221 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4222 int need_scaling;
6156a456
CK
4223
4224 need_scaling = intel_rotation_90_or_270(rotation) ?
4225 (src_h != dst_w || src_w != dst_h):
4226 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK
4227
4228 /*
4229 * if plane is being disabled or scaler is no more required or force detach
4230 * - free scaler binded to this plane/crtc
4231 * - in order to do this, update crtc->scaler_usage
4232 *
4233 * Here scaler state in crtc_state is set free so that
4234 * scaler can be assigned to other user. Actual register
4235 * update to free the scaler is done in plane/panel-fit programming.
4236 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4237 */
86adf9d7 4238 if (force_detach || !need_scaling) {
a1b2278e 4239 if (*scaler_id >= 0) {
86adf9d7 4240 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK
4241 scaler_state->scalers[*scaler_id].in_use = 0;
4242
86adf9d7
ML
4243 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4244 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4245 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK
4246 scaler_state->scaler_users);
4247 *scaler_id = -1;
4248 }
4249 return 0;
4250 }
4251
4252 /* range checks */
4253 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4254 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4255
4256 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4257 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4258 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4259 "size is out of scaler range\n",
86adf9d7 4260 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK
4261 return -EINVAL;
4262 }
4263
86adf9d7
ML
4264 /* mark this plane as a scaler user in crtc_state */
4265 scaler_state->scaler_users |= (1 << scaler_user);
4266 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4267 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4268 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4269 scaler_state->scaler_users);
4270
4271 return 0;
4272}
4273
4274/**
4275 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4276 *
4277 * @state: crtc's scaler state
86adf9d7
ML
4278 *
4279 * Return
4280 * 0 - scaler_usage updated successfully
4281 * error - requested scaling cannot be supported or other error condition
4282 */
e435d6e5 4283int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML
4284{
4285 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
7c5f93b0 4286 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
86adf9d7 4287
78108b7c
VS
4288 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4289 intel_crtc->base.base.id, intel_crtc->base.name,
4290 intel_crtc->pipe, SKL_CRTC_INDEX);
86adf9d7 4291
e435d6e5 4292 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
fa5a7970 4293 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
86adf9d7 4294 state->pipe_src_w, state->pipe_src_h,
aad941d5 4295 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
86adf9d7
ML
4296}
4297
4298/**
4299 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4300 *
4301 * @state: crtc's scaler state
86adf9d7
ML
4302 * @plane_state: atomic plane state to update
4303 *
4304 * Return
4305 * 0 - scaler_usage updated successfully
4306 * error - requested scaling cannot be supported or other error condition
4307 */
da20eabd
ML
4308static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4309 struct intel_plane_state *plane_state)
86adf9d7
ML
4310{
4311
4312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML
4313 struct intel_plane *intel_plane =
4314 to_intel_plane(plane_state->base.plane);
86adf9d7
ML
4315 struct drm_framebuffer *fb = plane_state->base.fb;
4316 int ret;
4317
4318 bool force_detach = !fb || !plane_state->visible;
4319
72660ce0
VS
4320 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4321 intel_plane->base.base.id, intel_plane->base.name,
4322 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
86adf9d7
ML
4323
4324 ret = skl_update_scaler(crtc_state, force_detach,
4325 drm_plane_index(&intel_plane->base),
4326 &plane_state->scaler_id,
4327 plane_state->base.rotation,
4328 drm_rect_width(&plane_state->src) >> 16,
4329 drm_rect_height(&plane_state->src) >> 16,
4330 drm_rect_width(&plane_state->dst),
4331 drm_rect_height(&plane_state->dst));
4332
4333 if (ret || plane_state->scaler_id < 0)
4334 return ret;
4335
a1b2278e 4336 /* check colorkey */
818ed961 4337 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
72660ce0
VS
4338 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4339 intel_plane->base.base.id,
4340 intel_plane->base.name);
a1b2278e
CK
4341 return -EINVAL;
4342 }
4343
4344 /* Check src format */
86adf9d7
ML
4345 switch (fb->pixel_format) {
4346 case DRM_FORMAT_RGB565:
4347 case DRM_FORMAT_XBGR8888:
4348 case DRM_FORMAT_XRGB8888:
4349 case DRM_FORMAT_ABGR8888:
4350 case DRM_FORMAT_ARGB8888:
4351 case DRM_FORMAT_XRGB2101010:
4352 case DRM_FORMAT_XBGR2101010:
4353 case DRM_FORMAT_YUYV:
4354 case DRM_FORMAT_YVYU:
4355 case DRM_FORMAT_UYVY:
4356 case DRM_FORMAT_VYUY:
4357 break;
4358 default:
72660ce0
VS
4359 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4360 intel_plane->base.base.id, intel_plane->base.name,
4361 fb->base.id, fb->pixel_format);
86adf9d7 4362 return -EINVAL;
a1b2278e
CK
4363 }
4364
a1b2278e
CK
4365 return 0;
4366}
4367
e435d6e5
ML
4368static void skylake_scaler_disable(struct intel_crtc *crtc)
4369{
4370 int i;
4371
4372 for (i = 0; i < crtc->num_scalers; i++)
4373 skl_detach_scaler(crtc, i);
4374}
4375
4376static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB
4377{
4378 struct drm_device *dev = crtc->base.dev;
4379 struct drm_i915_private *dev_priv = dev->dev_private;
4380 int pipe = crtc->pipe;
a1b2278e
CK
4381 struct intel_crtc_scaler_state *scaler_state =
4382 &crtc->config->scaler_state;
4383
4384 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4385
6e3c9717 4386 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK
4387 int id;
4388
4389 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4390 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4391 return;
4392 }
4393
4394 id = scaler_state->scaler_id;
4395 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4396 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4397 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4398 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4399
4400 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB
4401 }
4402}
4403
b074cec8
JB
4404static void ironlake_pfit_enable(struct intel_crtc *crtc)
4405{
4406 struct drm_device *dev = crtc->base.dev;
4407 struct drm_i915_private *dev_priv = dev->dev_private;
4408 int pipe = crtc->pipe;
4409
6e3c9717 4410 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB
4411 /* Force use of hard-coded filter coefficients
4412 * as some pre-programmed values are broken,
4413 * e.g. x201.
4414 */
4415 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4416 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4417 PF_PIPE_SEL_IVB(pipe));
4418 else
4419 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO
4420 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4421 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB
4422 }
4423}
4424
20bc8673 4425void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4426{
cea165c3
VS
4427 struct drm_device *dev = crtc->base.dev;
4428 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4429
6e3c9717 4430 if (!crtc->config->ips_enabled)
d77e4531
PZ
4431 return;
4432
307e4498
ML
4433 /*
4434 * We can only enable IPS after we enable a plane and wait for a vblank
4435 * This function is called from post_plane_update, which is run after
4436 * a vblank wait.
4437 */
cea165c3 4438
d77e4531 4439 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4440 if (IS_BROADWELL(dev)) {
2a114cc1
BW
4441 mutex_lock(&dev_priv->rps.hw_lock);
4442 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4443 mutex_unlock(&dev_priv->rps.hw_lock);
4444 /* Quoting Art Runyan: "its not safe to expect any particular
4445 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB
4446 * mailbox." Moreover, the mailbox may return a bogus state,
4447 * so we need to just enable it and continue on.
2a114cc1
BW
4448 */
4449 } else {
4450 I915_WRITE(IPS_CTL, IPS_ENABLE);
4451 /* The bit only becomes 1 in the next vblank, so this wait here
4452 * is essentially intel_wait_for_vblank. If we don't have this
4453 * and don't wait for vblanks until the end of crtc_enable, then
4454 * the HW state readout code will complain that the expected
4455 * IPS_CTL value is not the one we read. */
4456 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4457 DRM_ERROR("Timed out waiting for IPS enable\n");
4458 }
d77e4531
PZ
4459}
4460
20bc8673 4461void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ
4462{
4463 struct drm_device *dev = crtc->base.dev;
4464 struct drm_i915_private *dev_priv = dev->dev_private;
4465
6e3c9717 4466 if (!crtc->config->ips_enabled)
d77e4531
PZ
4467 return;
4468
4469 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4470 if (IS_BROADWELL(dev)) {
2a114cc1
BW
4471 mutex_lock(&dev_priv->rps.hw_lock);
4472 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4473 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW
4474 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4475 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4476 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4477 } else {
2a114cc1 4478 I915_WRITE(IPS_CTL, 0);
e59150dc
JB
4479 POSTING_READ(IPS_CTL);
4480 }
d77e4531
PZ
4481
4482 /* We need to wait for a vblank before we can disable the plane. */
4483 intel_wait_for_vblank(dev, crtc->pipe);
4484}
4485
7cac945f 4486static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4487{
7cac945f 4488 if (intel_crtc->overlay) {
d3eedb1a
VS
4489 struct drm_device *dev = intel_crtc->base.dev;
4490 struct drm_i915_private *dev_priv = dev->dev_private;
4491
4492 mutex_lock(&dev->struct_mutex);
4493 dev_priv->mm.interruptible = false;
4494 (void) intel_overlay_switch_off(intel_crtc->overlay);
4495 dev_priv->mm.interruptible = true;
4496 mutex_unlock(&dev->struct_mutex);
4497 }
4498
4499 /* Let userspace switch the overlay on again. In most cases userspace
4500 * has to recompute where to put it anyway.
4501 */
4502}
4503
87d4300a
ML
4504/**
4505 * intel_post_enable_primary - Perform operations after enabling primary plane
4506 * @crtc: the CRTC whose primary plane was just enabled
4507 *
4508 * Performs potentially sleeping operations that must be done after the primary
4509 * plane is enabled, such as updating FBC and IPS. Note that this may be
4510 * called due to an explicit primary plane update, or due to an implicit
4511 * re-enable that is caused when a sprite plane is updated to no longer
4512 * completely hide the primary plane.
4513 */
4514static void
4515intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS
4516{
4517 struct drm_device *dev = crtc->dev;
87d4300a 4518 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS
4519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4520 int pipe = intel_crtc->pipe;
a5c4d7bc 4521
87d4300a
ML
4522 /*
4523 * FIXME IPS should be fine as long as one plane is
4524 * enabled, but in practice it seems to have problems
4525 * when going from primary only to sprite only and vice
4526 * versa.
4527 */
a5c4d7bc
VS
4528 hsw_enable_ips(intel_crtc);
4529
f99d7069 4530 /*
87d4300a
ML
4531 * Gen2 reports pipe underruns whenever all planes are disabled.
4532 * So don't enable underrun reporting before at least some planes
4533 * are enabled.
4534 * FIXME: Need to fix the logic to work when we turn off all planes
4535 * but leave the pipe running.
f99d7069 4536 */
87d4300a
ML
4537 if (IS_GEN2(dev))
4538 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4539
aca7b684
VS
4540 /* Underruns don't always raise interrupts, so check manually. */
4541 intel_check_cpu_fifo_underruns(dev_priv);
4542 intel_check_pch_fifo_underruns(dev_priv);
a5c4d7bc
VS
4543}
4544
2622a081 4545/* FIXME move all this to pre_plane_update() with proper state tracking */
87d4300a
ML
4546static void
4547intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS
4548{
4549 struct drm_device *dev = crtc->dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4552 int pipe = intel_crtc->pipe;
a5c4d7bc 4553
87d4300a
ML
4554 /*
4555 * Gen2 reports pipe underruns whenever all planes are disabled.
4556 * So diasble underrun reporting before all the planes get disabled.
4557 * FIXME: Need to fix the logic to work when we turn off all planes
4558 * but leave the pipe running.
4559 */
4560 if (IS_GEN2(dev))
4561 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4562
2622a081
VS
4563 /*
4564 * FIXME IPS should be fine as long as one plane is
4565 * enabled, but in practice it seems to have problems
4566 * when going from primary only to sprite only and vice
4567 * versa.
4568 */
4569 hsw_disable_ips(intel_crtc);
4570}
4571
4572/* FIXME get rid of this and use pre_plane_update */
4573static void
4574intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4575{
4576 struct drm_device *dev = crtc->dev;
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4579 int pipe = intel_crtc->pipe;
4580
4581 intel_pre_disable_primary(crtc);
4582
87d4300a
ML
4583 /*
4584 * Vblank time updates from the shadow to live plane control register
4585 * are blocked if the memory self-refresh mode is active at that
4586 * moment. So to make sure the plane gets truly disabled, disable
4587 * first the self-refresh mode. The self-refresh enable bit in turn
4588 * will be checked/applied by the HW only at the next frame start
4589 * event which is after the vblank start event, so we need to have a
4590 * wait-for-vblank between disabling the plane and the pipe.
4591 */
262cd2e1 4592 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4593 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS
4594 dev_priv->wm.vlv.cxsr = false;
4595 intel_wait_for_vblank(dev, pipe);
4596 }
87d4300a
ML
4597}
4598
5a21b665
DV
4599static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4600{
4601 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4602 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4603 struct intel_crtc_state *pipe_config =
4604 to_intel_crtc_state(crtc->base.state);
4605 struct drm_device *dev = crtc->base.dev;
4606 struct drm_plane *primary = crtc->base.primary;
4607 struct drm_plane_state *old_pri_state =
4608 drm_atomic_get_existing_plane_state(old_state, primary);
4609
4610 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4611
4612 crtc->wm.cxsr_allowed = true;
4613
4614 if (pipe_config->update_wm_post && pipe_config->base.active)
4615 intel_update_watermarks(&crtc->base);
4616
4617 if (old_pri_state) {
4618 struct intel_plane_state *primary_state =
4619 to_intel_plane_state(primary->state);
4620 struct intel_plane_state *old_primary_state =
4621 to_intel_plane_state(old_pri_state);
4622
4623 intel_fbc_post_update(crtc);
4624
4625 if (primary_state->visible &&
4626 (needs_modeset(&pipe_config->base) ||
4627 !old_primary_state->visible))
4628 intel_post_enable_primary(&crtc->base);
4629 }
4630}
4631
5c74cd73 4632static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
ac21b225 4633{
5c74cd73 4634 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
ac21b225 4635 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4636 struct drm_i915_private *dev_priv = dev->dev_private;
ab1d3a0e
ML
4637 struct intel_crtc_state *pipe_config =
4638 to_intel_crtc_state(crtc->base.state);
5c74cd73
ML
4639 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4640 struct drm_plane *primary = crtc->base.primary;
4641 struct drm_plane_state *old_pri_state =
4642 drm_atomic_get_existing_plane_state(old_state, primary);
4643 bool modeset = needs_modeset(&pipe_config->base);
ac21b225 4644
5c74cd73
ML
4645 if (old_pri_state) {
4646 struct intel_plane_state *primary_state =
4647 to_intel_plane_state(primary->state);
4648 struct intel_plane_state *old_primary_state =
4649 to_intel_plane_state(old_pri_state);
4650
faf68d92 4651 intel_fbc_pre_update(crtc, pipe_config, primary_state);
31ae71fc 4652
5c74cd73
ML
4653 if (old_primary_state->visible &&
4654 (modeset || !primary_state->visible))
4655 intel_pre_disable_primary(&crtc->base);
4656 }
852eb00d 4657
a4015f9a 4658 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
852eb00d 4659 crtc->wm.cxsr_allowed = false;
2dfd178d 4660
2622a081
VS
4661 /*
4662 * Vblank time updates from the shadow to live plane control register
4663 * are blocked if the memory self-refresh mode is active at that
4664 * moment. So to make sure the plane gets truly disabled, disable
4665 * first the self-refresh mode. The self-refresh enable bit in turn
4666 * will be checked/applied by the HW only at the next frame start
4667 * event which is after the vblank start event, so we need to have a
4668 * wait-for-vblank between disabling the plane and the pipe.
4669 */
4670 if (old_crtc_state->base.active) {
2dfd178d 4671 intel_set_memory_cxsr(dev_priv, false);
2622a081
VS
4672 dev_priv->wm.vlv.cxsr = false;
4673 intel_wait_for_vblank(dev, crtc->pipe);
4674 }
852eb00d 4675 }
92826fcd 4676
ed4a6a7c
MR
4677 /*
4678 * IVB workaround: must disable low power watermarks for at least
4679 * one frame before enabling scaling. LP watermarks can be re-enabled
4680 * when scaling is disabled.
4681 *
4682 * WaCxSRDisabledForSpriteScaling:ivb
4683 */
4684 if (pipe_config->disable_lp_wm) {
4685 ilk_disable_lp_wm(dev);
4686 intel_wait_for_vblank(dev, crtc->pipe);
4687 }
4688
4689 /*
4690 * If we're doing a modeset, we're done. No need to do any pre-vblank
4691 * watermark programming here.
4692 */
4693 if (needs_modeset(&pipe_config->base))
4694 return;
4695
4696 /*
4697 * For platforms that support atomic watermarks, program the
4698 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4699 * will be the intermediate values that are safe for both pre- and
4700 * post- vblank; when vblank happens, the 'active' values will be set
4701 * to the final 'target' values and we'll do this again to get the
4702 * optimal watermarks. For gen9+ platforms, the values we program here
4703 * will be the final target values which will get automatically latched
4704 * at vblank time; no further programming will be necessary.
4705 *
4706 * If a platform hasn't been transitioned to atomic watermarks yet,
4707 * we'll continue to update watermarks the old way, if flags tell
4708 * us to.
4709 */
4710 if (dev_priv->display.initial_watermarks != NULL)
4711 dev_priv->display.initial_watermarks(pipe_config);
caed361d 4712 else if (pipe_config->update_wm_pre)
92826fcd 4713 intel_update_watermarks(&crtc->base);
ac21b225
ML
4714}
4715
d032ffa0 4716static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML
4717{
4718 struct drm_device *dev = crtc->dev;
4719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4720 struct drm_plane *p;
87d4300a
ML
4721 int pipe = intel_crtc->pipe;
4722
7cac945f 4723 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4724
d032ffa0
ML
4725 drm_for_each_plane_mask(p, dev, plane_mask)
4726 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4727
f99d7069
DV
4728 /*
4729 * FIXME: Once we grow proper nuclear flip support out of this we need
4730 * to compute the mask of flip planes precisely. For the time being
4731 * consider this a flip to a NULL plane.
4732 */
4733 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS
4734}
4735
f67a559d
JB
4736static void ironlake_crtc_enable(struct drm_crtc *crtc)
4737{
4738 struct drm_device *dev = crtc->dev;
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4741 struct intel_encoder *encoder;
f67a559d 4742 int pipe = intel_crtc->pipe;
b95c5321
ML
4743 struct intel_crtc_state *pipe_config =
4744 to_intel_crtc_state(crtc->state);
f67a559d 4745
53d9f4e9 4746 if (WARN_ON(intel_crtc->active))
f67a559d
JB
4747 return;
4748
b2c0593a
VS
4749 /*
4750 * Sometimes spurious CPU pipe underruns happen during FDI
4751 * training, at least with VGA+HDMI cloning. Suppress them.
4752 *
4753 * On ILK we get an occasional spurious CPU pipe underruns
4754 * between eDP port A enable and vdd enable. Also PCH port
4755 * enable seems to result in the occasional CPU pipe underrun.
4756 *
4757 * Spurious PCH underruns also occur during PCH enabling.
4758 */
4759 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4760 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
81b088ca
VS
4761 if (intel_crtc->config->has_pch_encoder)
4762 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4763
6e3c9717 4764 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV
4765 intel_prepare_shared_dpll(intel_crtc);
4766
6e3c9717 4767 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4768 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV
4769
4770 intel_set_pipe_timings(intel_crtc);
bc58be60 4771 intel_set_pipe_src_size(intel_crtc);
29407aab 4772
6e3c9717 4773 if (intel_crtc->config->has_pch_encoder) {
29407aab 4774 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4775 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV
4776 }
4777
4778 ironlake_set_pipeconf(crtc);
4779
f67a559d 4780 intel_crtc->active = true;
8664281b 4781
f6736a1a 4782 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV
4783 if (encoder->pre_enable)
4784 encoder->pre_enable(encoder);
f67a559d 4785
6e3c9717 4786 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV
4787 /* Note: FDI PLL enabling _must_ be done before we enable the
4788 * cpu pipes, hence this is separate from all the other fdi/pch
4789 * enabling. */
88cefb6c 4790 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV
4791 } else {
4792 assert_fdi_tx_disabled(dev_priv, pipe);
4793 assert_fdi_rx_disabled(dev_priv, pipe);
4794 }
f67a559d 4795
b074cec8 4796 ironlake_pfit_enable(intel_crtc);
f67a559d 4797
9c54c0dd
JB
4798 /*
4799 * On ILK+ LUT must be loaded before the pipe is running but with
4800 * clocks enabled
4801 */
b95c5321 4802 intel_color_load_luts(&pipe_config->base);
9c54c0dd 4803
1d5bf5d9
ID
4804 if (dev_priv->display.initial_watermarks != NULL)
4805 dev_priv->display.initial_watermarks(intel_crtc->config);
e1fdc473 4806 intel_enable_pipe(intel_crtc);
f67a559d 4807
6e3c9717 4808 if (intel_crtc->config->has_pch_encoder)
f67a559d 4809 ironlake_pch_enable(crtc);
c98e9dcf 4810
f9b61ff6
DV
4811 assert_vblank_disabled(crtc);
4812 drm_crtc_vblank_on(crtc);
4813
fa5c73b1
DV
4814 for_each_encoder_on_crtc(dev, crtc, encoder)
4815 encoder->enable(encoder);
61b77ddd
DV
4816
4817 if (HAS_PCH_CPT(dev))
a1520318 4818 cpt_verify_modeset(dev, intel_crtc->pipe);
37ca8d4c
VS
4819
4820 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4821 if (intel_crtc->config->has_pch_encoder)
4822 intel_wait_for_vblank(dev, pipe);
b2c0593a 4823 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
37ca8d4c 4824 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6be4a607
JB
4825}
4826
42db64ef
PZ
4827/* IPS only exists on ULT machines and is tied to pipe A. */
4828static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4829{
f5adf94e 4830 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ
4831}
4832
4f771f10
PZ
4833static void haswell_crtc_enable(struct drm_crtc *crtc)
4834{
4835 struct drm_device *dev = crtc->dev;
4836 struct drm_i915_private *dev_priv = dev->dev_private;
4837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4838 struct intel_encoder *encoder;
99d736a2 4839 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4d1de975 4840 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
99d736a2
ML
4841 struct intel_crtc_state *pipe_config =
4842 to_intel_crtc_state(crtc->state);
4f771f10 4843
53d9f4e9 4844 if (WARN_ON(intel_crtc->active))
4f771f10
PZ
4845 return;
4846
81b088ca
VS
4847 if (intel_crtc->config->has_pch_encoder)
4848 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4849 false);
4850
95a7a2ae
ID
4851 for_each_encoder_on_crtc(dev, crtc, encoder)
4852 if (encoder->pre_pll_enable)
4853 encoder->pre_pll_enable(encoder);
4854
8106ddbd 4855 if (intel_crtc->config->shared_dpll)
df8ad70c
DV
4856 intel_enable_shared_dpll(intel_crtc);
4857
6e3c9717 4858 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4859 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97 4860
4d1de975
JN
4861 if (!intel_crtc->config->has_dsi_encoder)
4862 intel_set_pipe_timings(intel_crtc);
4863
bc58be60 4864 intel_set_pipe_src_size(intel_crtc);
229fca97 4865
4d1de975
JN
4866 if (cpu_transcoder != TRANSCODER_EDP &&
4867 !transcoder_is_dsi(cpu_transcoder)) {
4868 I915_WRITE(PIPE_MULT(cpu_transcoder),
6e3c9717 4869 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT
4870 }
4871
6e3c9717 4872 if (intel_crtc->config->has_pch_encoder) {
229fca97 4873 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4874 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV
4875 }
4876
4d1de975
JN
4877 if (!intel_crtc->config->has_dsi_encoder)
4878 haswell_set_pipeconf(crtc);
4879
391bf048 4880 haswell_set_pipemisc(crtc);
229fca97 4881
b95c5321 4882 intel_color_set_csc(&pipe_config->base);
229fca97 4883
4f771f10 4884 intel_crtc->active = true;
8664281b 4885
6b698516
DV
4886 if (intel_crtc->config->has_pch_encoder)
4887 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4888 else
4889 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4890
7d4aefd0 4891 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10
PZ
4892 if (encoder->pre_enable)
4893 encoder->pre_enable(encoder);
7d4aefd0 4894 }
4f771f10 4895
d2d65408 4896 if (intel_crtc->config->has_pch_encoder)
4fe9467d 4897 dev_priv->display.fdi_link_train(crtc);
4fe9467d 4898
a65347ba 4899 if (!intel_crtc->config->has_dsi_encoder)
7d4aefd0 4900 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4901
1c132b44 4902 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 4903 skylake_pfit_enable(intel_crtc);
ff6d9f55 4904 else
1c132b44 4905 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ
4906
4907 /*
4908 * On ILK+ LUT must be loaded before the pipe is running but with
4909 * clocks enabled
4910 */
b95c5321 4911 intel_color_load_luts(&pipe_config->base);
4f771f10 4912
1f544388 4913 intel_ddi_set_pipe_settings(crtc);
a65347ba 4914 if (!intel_crtc->config->has_dsi_encoder)
7d4aefd0 4915 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4916
1d5bf5d9
ID
4917 if (dev_priv->display.initial_watermarks != NULL)
4918 dev_priv->display.initial_watermarks(pipe_config);
4919 else
4920 intel_update_watermarks(crtc);
4d1de975
JN
4921
4922 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4923 if (!intel_crtc->config->has_dsi_encoder)
4924 intel_enable_pipe(intel_crtc);
42db64ef 4925
6e3c9717 4926 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4927 lpt_pch_enable(crtc);
4f771f10 4928
a65347ba 4929 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA
4930 intel_ddi_set_vc_payload_alloc(crtc, true);
4931
f9b61ff6
DV
4932 assert_vblank_disabled(crtc);
4933 drm_crtc_vblank_on(crtc);
4934
8807e55b 4935 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4936 encoder->enable(encoder);
8807e55b
JN
4937 intel_opregion_notify_encoder(encoder, true);
4938 }
4f771f10 4939
6b698516
DV
4940 if (intel_crtc->config->has_pch_encoder) {
4941 intel_wait_for_vblank(dev, pipe);
4942 intel_wait_for_vblank(dev, pipe);
4943 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
d2d65408
VS
4944 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4945 true);
6b698516 4946 }
d2d65408 4947
e4916946
PZ
4948 /* If we change the relative order between pipe/planes enabling, we need
4949 * to change the workaround. */
99d736a2
ML
4950 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4951 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4952 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4953 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4954 }
4f771f10
PZ
4955}
4956
bfd16b2a 4957static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
3f8dce3a
DV
4958{
4959 struct drm_device *dev = crtc->base.dev;
4960 struct drm_i915_private *dev_priv = dev->dev_private;
4961 int pipe = crtc->pipe;
4962
4963 /* To avoid upsetting the power well on haswell only disable the pfit if
4964 * it's in use. The hw state code will make sure we get this right. */
bfd16b2a 4965 if (force || crtc->config->pch_pfit.enabled) {
3f8dce3a
DV
4966 I915_WRITE(PF_CTL(pipe), 0);
4967 I915_WRITE(PF_WIN_POS(pipe), 0);
4968 I915_WRITE(PF_WIN_SZ(pipe), 0);
4969 }
4970}
4971
6be4a607
JB
4972static void ironlake_crtc_disable(struct drm_crtc *crtc)
4973{
4974 struct drm_device *dev = crtc->dev;
4975 struct drm_i915_private *dev_priv = dev->dev_private;
4976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4977 struct intel_encoder *encoder;
6be4a607 4978 int pipe = intel_crtc->pipe;
b52eb4dc 4979
b2c0593a
VS
4980 /*
4981 * Sometimes spurious CPU pipe underruns happen when the
4982 * pipe is already disabled, but FDI RX/TX is still enabled.
4983 * Happens at least with VGA+HDMI cloning. Suppress them.
4984 */
4985 if (intel_crtc->config->has_pch_encoder) {
4986 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
37ca8d4c 4987 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
b2c0593a 4988 }
37ca8d4c 4989
ea9d758d
DV
4990 for_each_encoder_on_crtc(dev, crtc, encoder)
4991 encoder->disable(encoder);
4992
f9b61ff6
DV
4993 drm_crtc_vblank_off(crtc);
4994 assert_vblank_disabled(crtc);
4995
575f7ab7 4996 intel_disable_pipe(intel_crtc);
32f9d658 4997
bfd16b2a 4998 ironlake_pfit_disable(intel_crtc, false);
2c07245f 4999
b2c0593a 5000 if (intel_crtc->config->has_pch_encoder)
5a74f70a
VS
5001 ironlake_fdi_disable(crtc);
5002
bf49ec8c
DV
5003 for_each_encoder_on_crtc(dev, crtc, encoder)
5004 if (encoder->post_disable)
5005 encoder->post_disable(encoder);
2c07245f 5006
6e3c9717 5007 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5008 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5009
d925c59a 5010 if (HAS_PCH_CPT(dev)) {
f0f59a00
VS
5011 i915_reg_t reg;
5012 u32 temp;
5013
d925c59a
DV
5014 /* disable TRANS_DP_CTL */
5015 reg = TRANS_DP_CTL(pipe);
5016 temp = I915_READ(reg);
5017 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5018 TRANS_DP_PORT_SEL_MASK);
5019 temp |= TRANS_DP_PORT_SEL_NONE;
5020 I915_WRITE(reg, temp);
5021
5022 /* disable DPLL_SEL */
5023 temp = I915_READ(PCH_DPLL_SEL);
11887397 5024 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5025 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5026 }
e3421a18 5027
d925c59a
DV
5028 ironlake_fdi_pll_disable(intel_crtc);
5029 }
81b088ca 5030
b2c0593a 5031 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
81b088ca 5032 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6be4a607 5033}
1b3c7a47 5034
4f771f10 5035static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5036{
4f771f10
PZ
5037 struct drm_device *dev = crtc->dev;
5038 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5040 struct intel_encoder *encoder;
6e3c9717 5041 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5042
d2d65408
VS
5043 if (intel_crtc->config->has_pch_encoder)
5044 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5045 false);
5046
8807e55b
JN
5047 for_each_encoder_on_crtc(dev, crtc, encoder) {
5048 intel_opregion_notify_encoder(encoder, false);
4f771f10 5049 encoder->disable(encoder);
8807e55b 5050 }
4f771f10 5051
f9b61ff6
DV
5052 drm_crtc_vblank_off(crtc);
5053 assert_vblank_disabled(crtc);
5054
4d1de975
JN
5055 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5056 if (!intel_crtc->config->has_dsi_encoder)
5057 intel_disable_pipe(intel_crtc);
4f771f10 5058
6e3c9717 5059 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS
5060 intel_ddi_set_vc_payload_alloc(crtc, false);
5061
a65347ba 5062 if (!intel_crtc->config->has_dsi_encoder)
7d4aefd0 5063 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5064
1c132b44 5065 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5066 skylake_scaler_disable(intel_crtc);
ff6d9f55 5067 else
bfd16b2a 5068 ironlake_pfit_disable(intel_crtc, false);
4f771f10 5069
a65347ba 5070 if (!intel_crtc->config->has_dsi_encoder)
7d4aefd0 5071 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5072
97b040aa
ID
5073 for_each_encoder_on_crtc(dev, crtc, encoder)
5074 if (encoder->post_disable)
5075 encoder->post_disable(encoder);
81b088ca 5076
92966a37
VS
5077 if (intel_crtc->config->has_pch_encoder) {
5078 lpt_disable_pch_transcoder(dev_priv);
503a74e9 5079 lpt_disable_iclkip(dev_priv);
92966a37
VS
5080 intel_ddi_fdi_disable(crtc);
5081
81b088ca
VS
5082 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5083 true);
92966a37 5084 }
4f771f10
PZ
5085}
5086
2dd24552
JB
5087static void i9xx_pfit_enable(struct intel_crtc *crtc)
5088{
5089 struct drm_device *dev = crtc->base.dev;
5090 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5091 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5092
681a8504 5093 if (!pipe_config->gmch_pfit.control)
2dd24552
JB
5094 return;
5095
2dd24552 5096 /*
c0b03411
DV
5097 * The panel fitter should only be adjusted whilst the pipe is disabled,
5098 * according to register description and PRM.
2dd24552 5099 */
c0b03411
DV
5100 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5101 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5102
b074cec8
JB
5103 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5104 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV
5105
5106 /* Border color in case we don't scale up to the full screen. Black by
5107 * default, change to something else for debugging. */
5108 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB
5109}
5110
d05410f9
DA
5111static enum intel_display_power_domain port_to_power_domain(enum port port)
5112{
5113 switch (port) {
5114 case PORT_A:
6331a704 5115 return POWER_DOMAIN_PORT_DDI_A_LANES;
d05410f9 5116 case PORT_B:
6331a704 5117 return POWER_DOMAIN_PORT_DDI_B_LANES;
d05410f9 5118 case PORT_C:
6331a704 5119 return POWER_DOMAIN_PORT_DDI_C_LANES;
d05410f9 5120 case PORT_D:
6331a704 5121 return POWER_DOMAIN_PORT_DDI_D_LANES;
d8e19f99 5122 case PORT_E:
6331a704 5123 return POWER_DOMAIN_PORT_DDI_E_LANES;
d05410f9 5124 default:
b9fec167 5125 MISSING_CASE(port);
d05410f9
DA
5126 return POWER_DOMAIN_PORT_OTHER;
5127 }
5128}
5129
25f78f58
VS
5130static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5131{
5132 switch (port) {
5133 case PORT_A:
5134 return POWER_DOMAIN_AUX_A;
5135 case PORT_B:
5136 return POWER_DOMAIN_AUX_B;
5137 case PORT_C:
5138 return POWER_DOMAIN_AUX_C;
5139 case PORT_D:
5140 return POWER_DOMAIN_AUX_D;
5141 case PORT_E:
5142 /* FIXME: Check VBT for actual wiring of PORT E */
5143 return POWER_DOMAIN_AUX_D;
5144 default:
b9fec167 5145 MISSING_CASE(port);
25f78f58
VS
5146 return POWER_DOMAIN_AUX_A;
5147 }
5148}
5149
319be8ae
ID
5150enum intel_display_power_domain
5151intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5152{
5153 struct drm_device *dev = intel_encoder->base.dev;
5154 struct intel_digital_port *intel_dig_port;
5155
5156 switch (intel_encoder->type) {
5157 case INTEL_OUTPUT_UNKNOWN:
5158 /* Only DDI platforms should ever use this output type */
5159 WARN_ON_ONCE(!HAS_DDI(dev));
5160 case INTEL_OUTPUT_DISPLAYPORT:
5161 case INTEL_OUTPUT_HDMI:
5162 case INTEL_OUTPUT_EDP:
5163 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5164 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA
5165 case INTEL_OUTPUT_DP_MST:
5166 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5167 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID
5168 case INTEL_OUTPUT_ANALOG:
5169 return POWER_DOMAIN_PORT_CRT;
5170 case INTEL_OUTPUT_DSI:
5171 return POWER_DOMAIN_PORT_DSI;
5172 default:
5173 return POWER_DOMAIN_PORT_OTHER;
5174 }
5175}
5176
25f78f58
VS
5177enum intel_display_power_domain
5178intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5179{
5180 struct drm_device *dev = intel_encoder->base.dev;
5181 struct intel_digital_port *intel_dig_port;
5182
5183 switch (intel_encoder->type) {
5184 case INTEL_OUTPUT_UNKNOWN:
651174a4
ID
5185 case INTEL_OUTPUT_HDMI:
5186 /*
5187 * Only DDI platforms should ever use these output types.
5188 * We can get here after the HDMI detect code has already set
5189 * the type of the shared encoder. Since we can't be sure
5190 * what's the status of the given connectors, play safe and
5191 * run the DP detection too.
5192 */
25f78f58
VS
5193 WARN_ON_ONCE(!HAS_DDI(dev));
5194 case INTEL_OUTPUT_DISPLAYPORT:
5195 case INTEL_OUTPUT_EDP:
5196 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5197 return port_to_aux_power_domain(intel_dig_port->port);
5198 case INTEL_OUTPUT_DP_MST:
5199 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5200 return port_to_aux_power_domain(intel_dig_port->port);
5201 default:
b9fec167 5202 MISSING_CASE(intel_encoder->type);
25f78f58
VS
5203 return POWER_DOMAIN_AUX_A;
5204 }
5205}
5206
74bff5f9
ML
5207static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5208 struct intel_crtc_state *crtc_state)
77d22dca 5209{
319be8ae 5210 struct drm_device *dev = crtc->dev;
74bff5f9 5211 struct drm_encoder *encoder;
319be8ae
ID
5212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5213 enum pipe pipe = intel_crtc->pipe;
77d22dca 5214 unsigned long mask;
74bff5f9 5215 enum transcoder transcoder = crtc_state->cpu_transcoder;
77d22dca 5216
74bff5f9 5217 if (!crtc_state->base.active)
292b990e
ML
5218 return 0;
5219
77d22dca
ID
5220 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5221 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
74bff5f9
ML
5222 if (crtc_state->pch_pfit.enabled ||
5223 crtc_state->pch_pfit.force_thru)
77d22dca
ID
5224 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5225
74bff5f9
ML
5226 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5227 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5228
319be8ae 5229 mask |= BIT(intel_display_port_power_domain(intel_encoder));
74bff5f9 5230 }
319be8ae 5231
15e7ec29
ML
5232 if (crtc_state->shared_dpll)
5233 mask |= BIT(POWER_DOMAIN_PLLS);
5234
77d22dca
ID
5235 return mask;
5236}
5237
74bff5f9
ML
5238static unsigned long
5239modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5240 struct intel_crtc_state *crtc_state)
77d22dca 5241{
292b990e
ML
5242 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5244 enum intel_display_power_domain domain;
5a21b665 5245 unsigned long domains, new_domains, old_domains;
77d22dca 5246
292b990e 5247 old_domains = intel_crtc->enabled_power_domains;
74bff5f9
ML
5248 intel_crtc->enabled_power_domains = new_domains =
5249 get_crtc_power_domains(crtc, crtc_state);
77d22dca 5250
5a21b665 5251 domains = new_domains & ~old_domains;
292b990e
ML
5252
5253 for_each_power_domain(domain, domains)
5254 intel_display_power_get(dev_priv, domain);
5255
5a21b665 5256 return old_domains & ~new_domains;
292b990e
ML
5257}
5258
5259static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5260 unsigned long domains)
5261{
5262 enum intel_display_power_domain domain;
5263
5264 for_each_power_domain(domain, domains)
5265 intel_display_power_put(dev_priv, domain);
5266}
77d22dca 5267
adafdc6f
MK
5268static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5269{
5270 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5271
5272 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5273 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5274 return max_cdclk_freq;
5275 else if (IS_CHERRYVIEW(dev_priv))
5276 return max_cdclk_freq*95/100;
5277 else if (INTEL_INFO(dev_priv)->gen < 4)
5278 return 2*max_cdclk_freq*90/100;
5279 else
5280 return max_cdclk_freq*90/100;
5281}
5282
b2045352
VS
5283static int skl_calc_cdclk(int max_pixclk, int vco);
5284
560a7ae4
DL
5285static void intel_update_max_cdclk(struct drm_device *dev)
5286{
5287 struct drm_i915_private *dev_priv = dev->dev_private;
5288
ef11bdb3 5289 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
560a7ae4 5290 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
b2045352
VS
5291 int max_cdclk, vco;
5292
5293 vco = dev_priv->skl_preferred_vco_freq;
63911d72 5294 WARN_ON(vco != 8100000 && vco != 8640000);
560a7ae4 5295
b2045352
VS
5296 /*
5297 * Use the lower (vco 8640) cdclk values as a
5298 * first guess. skl_calc_cdclk() will correct it
5299 * if the preferred vco is 8100 instead.
5300 */
560a7ae4 5301 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
487ed2e4 5302 max_cdclk = 617143;
560a7ae4 5303 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
b2045352 5304 max_cdclk = 540000;
560a7ae4 5305 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
b2045352 5306 max_cdclk = 432000;
560a7ae4 5307 else
487ed2e4 5308 max_cdclk = 308571;
b2045352
VS
5309
5310 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
281c114f
MR
5311 } else if (IS_BROXTON(dev)) {
5312 dev_priv->max_cdclk_freq = 624000;
560a7ae4
DL
5313 } else if (IS_BROADWELL(dev)) {
5314 /*
5315 * FIXME with extra cooling we can allow
5316 * 540 MHz for ULX and 675 Mhz for ULT.
5317 * How can we know if extra cooling is
5318 * available? PCI ID, VTB, something else?
5319 */
5320 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5321 dev_priv->max_cdclk_freq = 450000;
5322 else if (IS_BDW_ULX(dev))
5323 dev_priv->max_cdclk_freq = 450000;
5324 else if (IS_BDW_ULT(dev))
5325 dev_priv->max_cdclk_freq = 540000;
5326 else
5327 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK
5328 } else if (IS_CHERRYVIEW(dev)) {
5329 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL
5330 } else if (IS_VALLEYVIEW(dev)) {
5331 dev_priv->max_cdclk_freq = 400000;
5332 } else {
5333 /* otherwise assume cdclk is fixed */
5334 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5335 }
5336
adafdc6f
MK
5337 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5338
560a7ae4
DL
5339 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5340 dev_priv->max_cdclk_freq);
adafdc6f
MK
5341
5342 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5343 dev_priv->max_dotclk_freq);
560a7ae4
DL
5344}
5345
5346static void intel_update_cdclk(struct drm_device *dev)
5347{
5348 struct drm_i915_private *dev_priv = dev->dev_private;
5349
5350 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
2f2a121a 5351
83d7c81f 5352 if (INTEL_GEN(dev_priv) >= 9)
709e05c3
VS
5353 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5354 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5355 dev_priv->cdclk_pll.ref);
2f2a121a
VS
5356 else
5357 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5358 dev_priv->cdclk_freq);
560a7ae4
DL
5359
5360 /*
b5d99ff9
VS
5361 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5362 * Programmng [sic] note: bit[9:2] should be programmed to the number
5363 * of cdclk that generates 4MHz reference clock freq which is used to
5364 * generate GMBus clock. This will vary with the cdclk freq.
560a7ae4 5365 */
b5d99ff9 5366 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
560a7ae4 5367 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
560a7ae4
DL
5368}
5369
92891e45
VS
5370/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5371static int skl_cdclk_decimal(int cdclk)
5372{
5373 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5374}
5375
5f199dfa
VS
5376static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5377{
5378 int ratio;
5379
5380 if (cdclk == dev_priv->cdclk_pll.ref)
5381 return 0;
5382
5383 switch (cdclk) {
5384 default:
5385 MISSING_CASE(cdclk);
5386 case 144000:
5387 case 288000:
5388 case 384000:
5389 case 576000:
5390 ratio = 60;
5391 break;
5392 case 624000:
5393 ratio = 65;
5394 break;
5395 }
5396
5397 return dev_priv->cdclk_pll.ref * ratio;
5398}
5399
2b73001e
VS
5400static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5401{
5402 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5403
5404 /* Timeout 200us */
5405 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
5406 DRM_ERROR("timeout waiting for DE PLL unlock\n");
83d7c81f
VS
5407
5408 dev_priv->cdclk_pll.vco = 0;
2b73001e
VS
5409}
5410
5f199dfa 5411static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
2b73001e 5412{
5f199dfa 5413 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
2b73001e
VS
5414 u32 val;
5415
5416 val = I915_READ(BXT_DE_PLL_CTL);
5417 val &= ~BXT_DE_PLL_RATIO_MASK;
5f199dfa 5418 val |= BXT_DE_PLL_RATIO(ratio);
2b73001e
VS
5419 I915_WRITE(BXT_DE_PLL_CTL, val);
5420
5421 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5422
5423 /* Timeout 200us */
5424 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
5425 DRM_ERROR("timeout waiting for DE PLL lock\n");
83d7c81f 5426
5f199dfa 5427 dev_priv->cdclk_pll.vco = vco;
2b73001e
VS
5428}
5429
324513c0 5430static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
f8437dd1 5431{
5f199dfa
VS
5432 u32 val, divider;
5433 int vco, ret;
f8437dd1 5434
5f199dfa
VS
5435 vco = bxt_de_pll_vco(dev_priv, cdclk);
5436
5437 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5438
5439 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5440 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5441 case 8:
f8437dd1 5442 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
f8437dd1 5443 break;
5f199dfa 5444 case 4:
f8437dd1 5445 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
f8437dd1 5446 break;
5f199dfa 5447 case 3:
f8437dd1 5448 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
f8437dd1 5449 break;
5f199dfa 5450 case 2:
f8437dd1 5451 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
f8437dd1
VK
5452 break;
5453 default:
5f199dfa
VS
5454 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5455 WARN_ON(vco != 0);
f8437dd1 5456
5f199dfa
VS
5457 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5458 break;
f8437dd1
VK
5459 }
5460
f8437dd1 5461 /* Inform power controller of upcoming frequency change */
5f199dfa 5462 mutex_lock(&dev_priv->rps.hw_lock);
f8437dd1
VK
5463 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5464 0x80000000);
5465 mutex_unlock(&dev_priv->rps.hw_lock);
5466
5467 if (ret) {
5468 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
9ef56154 5469 ret, cdclk);
f8437dd1
VK
5470 return;
5471 }
5472
5f199dfa
VS
5473 if (dev_priv->cdclk_pll.vco != 0 &&
5474 dev_priv->cdclk_pll.vco != vco)
2b73001e 5475 bxt_de_pll_disable(dev_priv);
f8437dd1 5476
5f199dfa
VS
5477 if (dev_priv->cdclk_pll.vco != vco)
5478 bxt_de_pll_enable(dev_priv, vco);
f8437dd1 5479
5f199dfa
VS
5480 val = divider | skl_cdclk_decimal(cdclk);
5481 /*
5482 * FIXME if only the cd2x divider needs changing, it could be done
5483 * without shutting off the pipe (if only one pipe is active).
5484 */
5485 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5486 /*
5487 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5488 * enable otherwise.
5489 */
5490 if (cdclk >= 500000)
5491 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5492 I915_WRITE(CDCLK_CTL, val);
f8437dd1
VK
5493
5494 mutex_lock(&dev_priv->rps.hw_lock);
5495 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
9ef56154 5496 DIV_ROUND_UP(cdclk, 25000));
f8437dd1
VK
5497 mutex_unlock(&dev_priv->rps.hw_lock);
5498
5499 if (ret) {
5500 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
9ef56154 5501 ret, cdclk);
f8437dd1
VK
5502 return;
5503 }
5504
c6c4696f 5505 intel_update_cdclk(dev_priv->dev);
f8437dd1
VK
5506}
5507
d66a2194 5508static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
f8437dd1 5509{
d66a2194
ID
5510 u32 cdctl, expected;
5511
089c6fd5 5512 intel_update_cdclk(dev_priv->dev);
f8437dd1 5513
d66a2194
ID
5514 if (dev_priv->cdclk_pll.vco == 0 ||
5515 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5516 goto sanitize;
5517
5518 /* DPLL okay; verify the cdclock
5519 *
5520 * Some BIOS versions leave an incorrect decimal frequency value and
5521 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5522 * so sanitize this register.
5523 */
5524 cdctl = I915_READ(CDCLK_CTL);
5525 /*
5526 * Let's ignore the pipe field, since BIOS could have configured the
5527 * dividers both synching to an active pipe, or asynchronously
5528 * (PIPE_NONE).
5529 */
5530 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5531
5532 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5533 skl_cdclk_decimal(dev_priv->cdclk_freq);
5534 /*
5535 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5536 * enable otherwise.
5537 */
5538 if (dev_priv->cdclk_freq >= 500000)
5539 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5540
5541 if (cdctl == expected)
5542 /* All well; nothing to sanitize */
5543 return;
5544
5545sanitize:
5546 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5547
5548 /* force cdclk programming */
5549 dev_priv->cdclk_freq = 0;
5550
5551 /* force full PLL disable + enable */
5552 dev_priv->cdclk_pll.vco = -1;
5553}
5554
324513c0 5555void bxt_init_cdclk(struct drm_i915_private *dev_priv)
d66a2194
ID
5556{
5557 bxt_sanitize_cdclk(dev_priv);
5558
5559 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
089c6fd5 5560 return;
c2e001ef 5561
f8437dd1
VK
5562 /*
5563 * FIXME:
5564 * - The initial CDCLK needs to be read from VBT.
5565 * Need to make this change after VBT has changes for BXT.
f8437dd1 5566 */
324513c0 5567 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
f8437dd1
VK
5568}
5569
324513c0 5570void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
f8437dd1 5571{
324513c0 5572 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
f8437dd1
VK
5573}
5574
a8ca4934
VS
5575static int skl_calc_cdclk(int max_pixclk, int vco)
5576{
63911d72 5577 if (vco == 8640000) {
a8ca4934 5578 if (max_pixclk > 540000)
487ed2e4 5579 return 617143;
a8ca4934
VS
5580 else if (max_pixclk > 432000)
5581 return 540000;
487ed2e4 5582 else if (max_pixclk > 308571)
a8ca4934
VS
5583 return 432000;
5584 else
487ed2e4 5585 return 308571;
a8ca4934 5586 } else {
a8ca4934
VS
5587 if (max_pixclk > 540000)
5588 return 675000;
5589 else if (max_pixclk > 450000)
5590 return 540000;
5591 else if (max_pixclk > 337500)
5592 return 450000;
5593 else
5594 return 337500;
5595 }
5596}
5597
ea61791e
VS
5598static void
5599skl_dpll0_update(struct drm_i915_private *dev_priv)
5d96d8af 5600{
ea61791e 5601 u32 val;
5d96d8af 5602
709e05c3 5603 dev_priv->cdclk_pll.ref = 24000;
1c3f7700 5604 dev_priv->cdclk_pll.vco = 0;
709e05c3 5605
ea61791e 5606 val = I915_READ(LCPLL1_CTL);
1c3f7700 5607 if ((val & LCPLL_PLL_ENABLE) == 0)
ea61791e 5608 return;
5d96d8af 5609
1c3f7700
ID
5610 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5611 return;
9f7eb31a 5612
ea61791e
VS
5613 val = I915_READ(DPLL_CTRL1);
5614
1c3f7700
ID
5615 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5616 DPLL_CTRL1_SSC(SKL_DPLL0) |
5617 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5618 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5619 return;
9f7eb31a 5620
ea61791e
VS
5621 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5622 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5623 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5624 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5625 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
63911d72 5626 dev_priv->cdclk_pll.vco = 8100000;
ea61791e
VS
5627 break;
5628 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5629 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
63911d72 5630 dev_priv->cdclk_pll.vco = 8640000;
ea61791e
VS
5631 break;
5632 default:
5633 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
ea61791e
VS
5634 break;
5635 }
5d96d8af
DL
5636}
5637
b2045352
VS
5638void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5639{
5640 bool changed = dev_priv->skl_preferred_vco_freq != vco;
5641
5642 dev_priv->skl_preferred_vco_freq = vco;
5643
5644 if (changed)
5645 intel_update_max_cdclk(dev_priv->dev);
5646}
5647
5d96d8af 5648static void
3861fc60 5649skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5d96d8af 5650{
a8ca4934 5651 int min_cdclk = skl_calc_cdclk(0, vco);
5d96d8af
DL
5652 u32 val;
5653
63911d72 5654 WARN_ON(vco != 8100000 && vco != 8640000);
b2045352 5655
5d96d8af 5656 /* select the minimum CDCLK before enabling DPLL 0 */
9ef56154 5657 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5d96d8af
DL
5658 I915_WRITE(CDCLK_CTL, val);
5659 POSTING_READ(CDCLK_CTL);
5660
5661 /*
5662 * We always enable DPLL0 with the lowest link rate possible, but still
5663 * taking into account the VCO required to operate the eDP panel at the
5664 * desired frequency. The usual DP link rates operate with a VCO of
5665 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5666 * The modeset code is responsible for the selection of the exact link
5667 * rate later on, with the constraint of choosing a frequency that
a8ca4934 5668 * works with vco.
5d96d8af
DL
5669 */
5670 val = I915_READ(DPLL_CTRL1);
5671
5672 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5673 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5674 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
63911d72 5675 if (vco == 8640000)
5d96d8af
DL
5676 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5677 SKL_DPLL0);
5678 else
5679 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5680 SKL_DPLL0);
5681
5682 I915_WRITE(DPLL_CTRL1, val);
5683 POSTING_READ(DPLL_CTRL1);
5684
5685 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5686
5687 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5688 DRM_ERROR("DPLL0 not locked\n");
1cd593e0 5689
63911d72 5690 dev_priv->cdclk_pll.vco = vco;
b2045352
VS
5691
5692 /* We'll want to keep using the current vco from now on. */
5693 skl_set_preferred_cdclk_vco(dev_priv, vco);
5d96d8af
DL
5694}
5695
430e05de
VS
5696static void
5697skl_dpll0_disable(struct drm_i915_private *dev_priv)
5698{
5699 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5700 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5701 DRM_ERROR("Couldn't disable DPLL0\n");
1cd593e0 5702
63911d72 5703 dev_priv->cdclk_pll.vco = 0;
430e05de
VS
5704}
5705
5d96d8af
DL
5706static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5707{
5708 int ret;
5709 u32 val;
5710
5711 /* inform PCU we want to change CDCLK */
5712 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5713 mutex_lock(&dev_priv->rps.hw_lock);
5714 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5715 mutex_unlock(&dev_priv->rps.hw_lock);
5716
5717 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5718}
5719
5720static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5721{
5722 unsigned int i;
5723
5724 for (i = 0; i < 15; i++) {
5725 if (skl_cdclk_pcu_ready(dev_priv))
5726 return true;
5727 udelay(10);
5728 }
5729
5730 return false;
5731}
5732
1cd593e0 5733static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5d96d8af 5734{
560a7ae4 5735 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL
5736 u32 freq_select, pcu_ack;
5737
1cd593e0
VS
5738 WARN_ON((cdclk == 24000) != (vco == 0));
5739
63911d72 5740 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5d96d8af
DL
5741
5742 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5743 DRM_ERROR("failed to inform PCU about cdclk change\n");
5744 return;
5745 }
5746
5747 /* set CDCLK_CTL */
9ef56154 5748 switch (cdclk) {
5d96d8af
DL
5749 case 450000:
5750 case 432000:
5751 freq_select = CDCLK_FREQ_450_432;
5752 pcu_ack = 1;
5753 break;
5754 case 540000:
5755 freq_select = CDCLK_FREQ_540;
5756 pcu_ack = 2;
5757 break;
487ed2e4 5758 case 308571:
5d96d8af
DL
5759 case 337500:
5760 default:
5761 freq_select = CDCLK_FREQ_337_308;
5762 pcu_ack = 0;
5763 break;
487ed2e4 5764 case 617143:
5d96d8af
DL
5765 case 675000:
5766 freq_select = CDCLK_FREQ_675_617;
5767 pcu_ack = 3;
5768 break;
5769 }
5770
63911d72
VS
5771 if (dev_priv->cdclk_pll.vco != 0 &&
5772 dev_priv->cdclk_pll.vco != vco)
1cd593e0
VS
5773 skl_dpll0_disable(dev_priv);
5774
63911d72 5775 if (dev_priv->cdclk_pll.vco != vco)
1cd593e0
VS
5776 skl_dpll0_enable(dev_priv, vco);
5777
9ef56154 5778 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5d96d8af
DL
5779 POSTING_READ(CDCLK_CTL);
5780
5781 /* inform PCU of the change */
5782 mutex_lock(&dev_priv->rps.hw_lock);
5783 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5784 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL
5785
5786 intel_update_cdclk(dev);
5d96d8af
DL
5787}
5788
9f7eb31a
VS
5789static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5790
5d96d8af
DL
5791void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5792{
709e05c3 5793 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5d96d8af
DL
5794}
5795
5796void skl_init_cdclk(struct drm_i915_private *dev_priv)
5797{
9f7eb31a
VS
5798 int cdclk, vco;
5799
5800 skl_sanitize_cdclk(dev_priv);
5d96d8af 5801
63911d72 5802 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
9f7eb31a
VS
5803 /*
5804 * Use the current vco as our initial
5805 * guess as to what the preferred vco is.
5806 */
5807 if (dev_priv->skl_preferred_vco_freq == 0)
5808 skl_set_preferred_cdclk_vco(dev_priv,
63911d72 5809 dev_priv->cdclk_pll.vco);
70c2c184 5810 return;
1cd593e0 5811 }
5d96d8af 5812
70c2c184
VS
5813 vco = dev_priv->skl_preferred_vco_freq;
5814 if (vco == 0)
63911d72 5815 vco = 8100000;
70c2c184 5816 cdclk = skl_calc_cdclk(0, vco);
5d96d8af 5817
70c2c184 5818 skl_set_cdclk(dev_priv, cdclk, vco);
5d96d8af
DL
5819}
5820
9f7eb31a 5821static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
c73666f3 5822{
09492498 5823 uint32_t cdctl, expected;
c73666f3 5824
f1b391a5
SK
5825 /*
5826 * check if the pre-os intialized the display
5827 * There is SWF18 scratchpad register defined which is set by the
5828 * pre-os which can be used by the OS drivers to check the status
5829 */
5830 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5831 goto sanitize;
5832
1c3f7700 5833 intel_update_cdclk(dev_priv->dev);
c73666f3 5834 /* Is PLL enabled and locked ? */
1c3f7700
ID
5835 if (dev_priv->cdclk_pll.vco == 0 ||
5836 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
c73666f3
SK
5837 goto sanitize;
5838
5839 /* DPLL okay; verify the cdclock
5840 *
5841 * Noticed in some instances that the freq selection is correct but
5842 * decimal part is programmed wrong from BIOS where pre-os does not
5843 * enable display. Verify the same as well.
5844 */
09492498
VS
5845 cdctl = I915_READ(CDCLK_CTL);
5846 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5847 skl_cdclk_decimal(dev_priv->cdclk_freq);
5848 if (cdctl == expected)
c73666f3 5849 /* All well; nothing to sanitize */
9f7eb31a 5850 return;
c89e39f3 5851
9f7eb31a
VS
5852sanitize:
5853 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
c73666f3 5854
9f7eb31a
VS
5855 /* force cdclk programming */
5856 dev_priv->cdclk_freq = 0;
5857 /* force full PLL disable + enable */
63911d72 5858 dev_priv->cdclk_pll.vco = -1;
c73666f3
SK
5859}
5860
30a970c6
JB
5861/* Adjust CDclk dividers to allow high res or save power if possible */
5862static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5863{
5864 struct drm_i915_private *dev_priv = dev->dev_private;
5865 u32 val, cmd;
5866
164dfd28
VK
5867 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5868 != dev_priv->cdclk_freq);
d60c4473 5869
dfcab17e 5870 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5871 cmd = 2;
dfcab17e 5872 else if (cdclk == 266667)
30a970c6
JB
5873 cmd = 1;
5874 else
5875 cmd = 0;
5876
5877 mutex_lock(&dev_priv->rps.hw_lock);
5878 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5879 val &= ~DSPFREQGUAR_MASK;
5880 val |= (cmd << DSPFREQGUAR_SHIFT);
5881 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5882 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5883 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5884 50)) {
5885 DRM_ERROR("timed out waiting for CDclk change\n");
5886 }
5887 mutex_unlock(&dev_priv->rps.hw_lock);
5888
54433e91
VS
5889 mutex_lock(&dev_priv->sb_lock);
5890
dfcab17e 5891 if (cdclk == 400000) {
6bcda4f0 5892 u32 divider;
30a970c6 5893
6bcda4f0 5894 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5895
30a970c6
JB
5896 /* adjust cdclk divider */
5897 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
87d5d259 5898 val &= ~CCK_FREQUENCY_VALUES;
30a970c6
JB
5899 val |= divider;
5900 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS
5901
5902 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
87d5d259 5903 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
a877e801
VS
5904 50))
5905 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB
5906 }
5907
30a970c6
JB
5908 /* adjust self-refresh exit latency value */
5909 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5910 val &= ~0x7f;
5911
5912 /*
5913 * For high bandwidth configs, we set a higher latency in the bunit
5914 * so that the core display fetch happens in time to avoid underruns.
5915 */
dfcab17e 5916 if (cdclk == 400000)
30a970c6
JB
5917 val |= 4500 / 250; /* 4.5 usec */
5918 else
5919 val |= 3000 / 250; /* 3.0 usec */
5920 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5921
a580516d 5922 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5923
b6283055 5924 intel_update_cdclk(dev);
30a970c6
JB
5925}
5926
383c5a6a
VS
5927static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5928{
5929 struct drm_i915_private *dev_priv = dev->dev_private;
5930 u32 val, cmd;
5931
164dfd28
VK
5932 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5933 != dev_priv->cdclk_freq);
383c5a6a
VS
5934
5935 switch (cdclk) {
383c5a6a
VS
5936 case 333333:
5937 case 320000:
383c5a6a 5938 case 266667:
383c5a6a 5939 case 200000:
383c5a6a
VS
5940 break;
5941 default:
5f77eeb0 5942 MISSING_CASE(cdclk);
383c5a6a
VS
5943 return;
5944 }
5945
9d0d3fda
VS
5946 /*
5947 * Specs are full of misinformation, but testing on actual
5948 * hardware has shown that we just need to write the desired
5949 * CCK divider into the Punit register.
5950 */
5951 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5952
383c5a6a
VS
5953 mutex_lock(&dev_priv->rps.hw_lock);
5954 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5955 val &= ~DSPFREQGUAR_MASK_CHV;
5956 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5957 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5958 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5959 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5960 50)) {
5961 DRM_ERROR("timed out waiting for CDclk change\n");
5962 }
5963 mutex_unlock(&dev_priv->rps.hw_lock);
5964
b6283055 5965 intel_update_cdclk(dev);
383c5a6a
VS
5966}
5967
30a970c6
JB
5968static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5969 int max_pixclk)
5970{
6bcda4f0 5971 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5972 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5973
30a970c6
JB
5974 /*
5975 * Really only a few cases to deal with, as only 4 CDclks are supported:
5976 * 200MHz
5977 * 267MHz
29dc7ef3 5978 * 320/333MHz (depends on HPLL freq)
6cca3195
VS
5979 * 400MHz (VLV only)
5980 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5981 * of the lower bin and adjust if needed.
e37c67a1
VS
5982 *
5983 * We seem to get an unstable or solid color picture at 200MHz.
5984 * Not sure what's wrong. For now use 200MHz only when all pipes
5985 * are off.
30a970c6 5986 */
6cca3195
VS
5987 if (!IS_CHERRYVIEW(dev_priv) &&
5988 max_pixclk > freq_320*limit/100)
dfcab17e 5989 return 400000;
6cca3195 5990 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5991 return freq_320;
e37c67a1 5992 else if (max_pixclk > 0)
dfcab17e 5993 return 266667;
e37c67a1
VS
5994 else
5995 return 200000;
30a970c6
JB
5996}
5997
324513c0 5998static int bxt_calc_cdclk(int max_pixclk)
f8437dd1 5999{
760e1477 6000 if (max_pixclk > 576000)
f8437dd1 6001 return 624000;
760e1477 6002 else if (max_pixclk > 384000)
f8437dd1 6003 return 576000;
760e1477 6004 else if (max_pixclk > 288000)
f8437dd1 6005 return 384000;
760e1477 6006 else if (max_pixclk > 144000)
f8437dd1
VK
6007 return 288000;
6008 else
6009 return 144000;
6010}
6011
e8788cbc 6012/* Compute the max pixel clock for new configuration. */
a821fc46
ACO
6013static int intel_mode_max_pixclk(struct drm_device *dev,
6014 struct drm_atomic_state *state)
30a970c6 6015{
565602d7
ML
6016 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6017 struct drm_i915_private *dev_priv = dev->dev_private;
6018 struct drm_crtc *crtc;
6019 struct drm_crtc_state *crtc_state;
6020 unsigned max_pixclk = 0, i;
6021 enum pipe pipe;
30a970c6 6022
565602d7
ML
6023 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6024 sizeof(intel_state->min_pixclk));
304603f4 6025
565602d7
ML
6026 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6027 int pixclk = 0;
6028
6029 if (crtc_state->enable)
6030 pixclk = crtc_state->adjusted_mode.crtc_clock;
304603f4 6031
565602d7 6032 intel_state->min_pixclk[i] = pixclk;
30a970c6
JB
6033 }
6034
565602d7
ML
6035 for_each_pipe(dev_priv, pipe)
6036 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6037
30a970c6
JB
6038 return max_pixclk;
6039}
6040
27c329ed 6041static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 6042{
27c329ed
ML
6043 struct drm_device *dev = state->dev;
6044 struct drm_i915_private *dev_priv = dev->dev_private;
6045 int max_pixclk = intel_mode_max_pixclk(dev, state);
1a617b77
ML
6046 struct intel_atomic_state *intel_state =
6047 to_intel_atomic_state(state);
30a970c6 6048
1a617b77 6049 intel_state->cdclk = intel_state->dev_cdclk =
27c329ed 6050 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 6051
1a617b77
ML
6052 if (!intel_state->active_crtcs)
6053 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6054
27c329ed
ML
6055 return 0;
6056}
304603f4 6057
324513c0 6058static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
27c329ed 6059{
4e5ca60f 6060 int max_pixclk = ilk_max_pixel_rate(state);
1a617b77
ML
6061 struct intel_atomic_state *intel_state =
6062 to_intel_atomic_state(state);
85a96e7a 6063
1a617b77 6064 intel_state->cdclk = intel_state->dev_cdclk =
324513c0 6065 bxt_calc_cdclk(max_pixclk);
85a96e7a 6066
1a617b77 6067 if (!intel_state->active_crtcs)
324513c0 6068 intel_state->dev_cdclk = bxt_calc_cdclk(0);
1a617b77 6069
27c329ed 6070 return 0;
30a970c6
JB
6071}
6072
1e69cd74
VS
6073static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6074{
6075 unsigned int credits, default_credits;
6076
6077 if (IS_CHERRYVIEW(dev_priv))
6078 default_credits = PFI_CREDIT(12);
6079 else
6080 default_credits = PFI_CREDIT(8);
6081
bfa7df01 6082 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
1e69cd74
VS
6083 /* CHV suggested value is 31 or 63 */
6084 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 6085 credits = PFI_CREDIT_63;
1e69cd74
VS
6086 else
6087 credits = PFI_CREDIT(15);
6088 } else {
6089 credits = default_credits;
6090 }
6091
6092 /*
6093 * WA - write default credits before re-programming
6094 * FIXME: should we also set the resend bit here?
6095 */
6096 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6097 default_credits);
6098
6099 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6100 credits | PFI_CREDIT_RESEND);
6101
6102 /*
6103 * FIXME is this guaranteed to clear
6104 * immediately or should we poll for it?
6105 */
6106 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6107}
6108
27c329ed 6109static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 6110{
a821fc46 6111 struct drm_device *dev = old_state->dev;
30a970c6 6112 struct drm_i915_private *dev_priv = dev->dev_private;
1a617b77
ML
6113 struct intel_atomic_state *old_intel_state =
6114 to_intel_atomic_state(old_state);
6115 unsigned req_cdclk = old_intel_state->dev_cdclk;
30a970c6 6116
27c329ed
ML
6117 /*
6118 * FIXME: We can end up here with all power domains off, yet
6119 * with a CDCLK frequency other than the minimum. To account
6120 * for this take the PIPE-A power domain, which covers the HW
6121 * blocks needed for the following programming. This can be
6122 * removed once it's guaranteed that we get here either with
6123 * the minimum CDCLK set, or the required power domains
6124 * enabled.
6125 */
6126 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6127
27c329ed
ML
6128 if (IS_CHERRYVIEW(dev))
6129 cherryview_set_cdclk(dev, req_cdclk);
6130 else
6131 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6132
27c329ed 6133 vlv_program_pfi_credits(dev_priv);
1e69cd74 6134
27c329ed 6135 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB
6136}
6137
89b667f8
JB
6138static void valleyview_crtc_enable(struct drm_crtc *crtc)
6139{
6140 struct drm_device *dev = crtc->dev;
a72e4c9f 6141 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB
6142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6143 struct intel_encoder *encoder;
b95c5321
ML
6144 struct intel_crtc_state *pipe_config =
6145 to_intel_crtc_state(crtc->state);
89b667f8 6146 int pipe = intel_crtc->pipe;
89b667f8 6147
53d9f4e9 6148 if (WARN_ON(intel_crtc->active))
89b667f8
JB
6149 return;
6150
6e3c9717 6151 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6152 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV
6153
6154 intel_set_pipe_timings(intel_crtc);
bc58be60 6155 intel_set_pipe_src_size(intel_crtc);
5b18e57c 6156
c14b0485
VS
6157 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159
6160 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6161 I915_WRITE(CHV_CANVAS(pipe), 0);
6162 }
6163
5b18e57c
DV
6164 i9xx_set_pipeconf(intel_crtc);
6165
89b667f8 6166 intel_crtc->active = true;
89b667f8 6167
a72e4c9f 6168 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6169
89b667f8
JB
6170 for_each_encoder_on_crtc(dev, crtc, encoder)
6171 if (encoder->pre_pll_enable)
6172 encoder->pre_pll_enable(encoder);
6173
cd2d34d9
VS
6174 if (IS_CHERRYVIEW(dev)) {
6175 chv_prepare_pll(intel_crtc, intel_crtc->config);
6176 chv_enable_pll(intel_crtc, intel_crtc->config);
6177 } else {
6178 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6179 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6180 }
89b667f8
JB
6181
6182 for_each_encoder_on_crtc(dev, crtc, encoder)
6183 if (encoder->pre_enable)
6184 encoder->pre_enable(encoder);
6185
2dd24552
JB
6186 i9xx_pfit_enable(intel_crtc);
6187
b95c5321 6188 intel_color_load_luts(&pipe_config->base);
63cbb074 6189
caed361d 6190 intel_update_watermarks(crtc);
e1fdc473 6191 intel_enable_pipe(intel_crtc);
be6a6f8e 6192
4b3a9526
VS
6193 assert_vblank_disabled(crtc);
6194 drm_crtc_vblank_on(crtc);
6195
f9b61ff6
DV
6196 for_each_encoder_on_crtc(dev, crtc, encoder)
6197 encoder->enable(encoder);
89b667f8
JB
6198}
6199
f13c2ef3
DV
6200static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6201{
6202 struct drm_device *dev = crtc->base.dev;
6203 struct drm_i915_private *dev_priv = dev->dev_private;
6204
6e3c9717
ACO
6205 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6206 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV
6207}
6208
0b8765c6 6209static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB
6210{
6211 struct drm_device *dev = crtc->dev;
a72e4c9f 6212 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6214 struct intel_encoder *encoder;
b95c5321
ML
6215 struct intel_crtc_state *pipe_config =
6216 to_intel_crtc_state(crtc->state);
cd2d34d9 6217 enum pipe pipe = intel_crtc->pipe;
79e53945 6218
53d9f4e9 6219 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW
6220 return;
6221
f13c2ef3
DV
6222 i9xx_set_pll_dividers(intel_crtc);
6223
6e3c9717 6224 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6225 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV
6226
6227 intel_set_pipe_timings(intel_crtc);
bc58be60 6228 intel_set_pipe_src_size(intel_crtc);
5b18e57c 6229
5b18e57c
DV
6230 i9xx_set_pipeconf(intel_crtc);
6231
f7abfe8b 6232 intel_crtc->active = true;
6b383a7f 6233
4a3436e8 6234 if (!IS_GEN2(dev))
a72e4c9f 6235 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6236
9d6d9f19
MK
6237 for_each_encoder_on_crtc(dev, crtc, encoder)
6238 if (encoder->pre_enable)
6239 encoder->pre_enable(encoder);
6240
f6736a1a
DV
6241 i9xx_enable_pll(intel_crtc);
6242
2dd24552
JB
6243 i9xx_pfit_enable(intel_crtc);
6244
b95c5321 6245 intel_color_load_luts(&pipe_config->base);
63cbb074 6246
f37fcc2a 6247 intel_update_watermarks(crtc);
e1fdc473 6248 intel_enable_pipe(intel_crtc);
be6a6f8e 6249
4b3a9526
VS
6250 assert_vblank_disabled(crtc);
6251 drm_crtc_vblank_on(crtc);
6252
f9b61ff6
DV
6253 for_each_encoder_on_crtc(dev, crtc, encoder)
6254 encoder->enable(encoder);
0b8765c6 6255}
79e53945 6256
87476d63
DV
6257static void i9xx_pfit_disable(struct intel_crtc *crtc)
6258{
6259 struct drm_device *dev = crtc->base.dev;
6260 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6261
6e3c9717 6262 if (!crtc->config->gmch_pfit.control)
328d8e82 6263 return;
87476d63 6264
328d8e82 6265 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6266
328d8e82
DV
6267 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6268 I915_READ(PFIT_CONTROL));
6269 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV
6270}
6271
0b8765c6
JB
6272static void i9xx_crtc_disable(struct drm_crtc *crtc)
6273{
6274 struct drm_device *dev = crtc->dev;
6275 struct drm_i915_private *dev_priv = dev->dev_private;
6276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6277 struct intel_encoder *encoder;
0b8765c6 6278 int pipe = intel_crtc->pipe;
ef9c3aee 6279
6304cd91
VS
6280 /*
6281 * On gen2 planes are double buffered but the pipe isn't, so we must
6282 * wait for planes to fully turn off before disabling the pipe.
6283 */
90e83e53
ACO
6284 if (IS_GEN2(dev))
6285 intel_wait_for_vblank(dev, pipe);
6304cd91 6286
4b3a9526
VS
6287 for_each_encoder_on_crtc(dev, crtc, encoder)
6288 encoder->disable(encoder);
6289
f9b61ff6
DV
6290 drm_crtc_vblank_off(crtc);
6291 assert_vblank_disabled(crtc);
6292
575f7ab7 6293 intel_disable_pipe(intel_crtc);
24a1f16d 6294
87476d63 6295 i9xx_pfit_disable(intel_crtc);
24a1f16d 6296
89b667f8
JB
6297 for_each_encoder_on_crtc(dev, crtc, encoder)
6298 if (encoder->post_disable)
6299 encoder->post_disable(encoder);
6300
a65347ba 6301 if (!intel_crtc->config->has_dsi_encoder) {
076ed3b2
CML
6302 if (IS_CHERRYVIEW(dev))
6303 chv_disable_pll(dev_priv, pipe);
6304 else if (IS_VALLEYVIEW(dev))
6305 vlv_disable_pll(dev_priv, pipe);
6306 else
1c4e0274 6307 i9xx_disable_pll(intel_crtc);
076ed3b2 6308 }
0b8765c6 6309
d6db995f
VS
6310 for_each_encoder_on_crtc(dev, crtc, encoder)
6311 if (encoder->post_pll_disable)
6312 encoder->post_pll_disable(encoder);
6313
4a3436e8 6314 if (!IS_GEN2(dev))
a72e4c9f 6315 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB
6316}
6317
b17d48e2
ML
6318static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6319{
842e0307 6320 struct intel_encoder *encoder;
b17d48e2
ML
6321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6322 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6323 enum intel_display_power_domain domain;
6324 unsigned long domains;
6325
6326 if (!intel_crtc->active)
6327 return;
6328
a539205a 6329 if (to_intel_plane_state(crtc->primary->state)->visible) {
5a21b665 6330 WARN_ON(intel_crtc->flip_work);
fc32b1fd 6331
2622a081 6332 intel_pre_disable_primary_noatomic(crtc);
54a41961
ML
6333
6334 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6335 to_intel_plane_state(crtc->primary->state)->visible = false;
a539205a
ML
6336 }
6337
b17d48e2 6338 dev_priv->display.crtc_disable(crtc);
842e0307 6339
78108b7c
VS
6340 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6341 crtc->base.id, crtc->name);
842e0307
ML
6342
6343 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6344 crtc->state->active = false;
37d9078b 6345 intel_crtc->active = false;
842e0307
ML
6346 crtc->enabled = false;
6347 crtc->state->connector_mask = 0;
6348 crtc->state->encoder_mask = 0;
6349
6350 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6351 encoder->base.crtc = NULL;
6352
58f9c0bc 6353 intel_fbc_disable(intel_crtc);
37d9078b 6354 intel_update_watermarks(crtc);
1f7457b1 6355 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML
6356
6357 domains = intel_crtc->enabled_power_domains;
6358 for_each_power_domain(domain, domains)
6359 intel_display_power_put(dev_priv, domain);
6360 intel_crtc->enabled_power_domains = 0;
565602d7
ML
6361
6362 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6363 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
b17d48e2
ML
6364}
6365
6b72d486
ML
6366/*
6367 * turn all crtc's off, but do not adjust state
6368 * This has to be paired with a call to intel_modeset_setup_hw_state.
6369 */
70e0bd74 6370int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6371{
e2c8b870 6372 struct drm_i915_private *dev_priv = to_i915(dev);
70e0bd74 6373 struct drm_atomic_state *state;
e2c8b870 6374 int ret;
70e0bd74 6375
e2c8b870
ML
6376 state = drm_atomic_helper_suspend(dev);
6377 ret = PTR_ERR_OR_ZERO(state);
70e0bd74
ML
6378 if (ret)
6379 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
e2c8b870
ML
6380 else
6381 dev_priv->modeset_restore_state = state;
70e0bd74 6382 return ret;
ee7b9f93
JB
6383}
6384
ea5b213a 6385void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6386{
4ef69c7a 6387 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6388
ea5b213a
CW
6389 drm_encoder_cleanup(encoder);
6390 kfree(intel_encoder);
7e7d76c3
JB
6391}
6392
0a91ca29
DV
6393/* Cross check the actual hw state with our own modeset state tracking (and it's
6394 * internal consistency). */
5a21b665 6395static void intel_connector_verify_state(struct intel_connector *connector)
79e53945 6396{
5a21b665 6397 struct drm_crtc *crtc = connector->base.state->crtc;
35dd3c64
ML
6398
6399 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6400 connector->base.base.id,
6401 connector->base.name);
6402
0a91ca29 6403 if (connector->get_hw_state(connector)) {
e85376cb 6404 struct intel_encoder *encoder = connector->encoder;
5a21b665 6405 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6406
35dd3c64
ML
6407 I915_STATE_WARN(!crtc,
6408 "connector enabled without attached crtc\n");
0a91ca29 6409
35dd3c64
ML
6410 if (!crtc)
6411 return;
6412
6413 I915_STATE_WARN(!crtc->state->active,
6414 "connector is active, but attached crtc isn't\n");
6415
e85376cb 6416 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
35dd3c64
ML
6417 return;
6418
e85376cb 6419 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
35dd3c64
ML
6420 "atomic encoder doesn't match attached encoder\n");
6421
e85376cb 6422 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
35dd3c64
ML
6423 "attached encoder crtc differs from connector crtc\n");
6424 } else {
4d688a2a
ML
6425 I915_STATE_WARN(crtc && crtc->state->active,
6426 "attached crtc is active, but connector isn't\n");
5a21b665 6427 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
35dd3c64 6428 "best encoder set without crtc!\n");
0a91ca29 6429 }
79e53945
JB
6430}
6431
08d9bc92
ACO
6432int intel_connector_init(struct intel_connector *connector)
6433{
5350a031 6434 drm_atomic_helper_connector_reset(&connector->base);
08d9bc92 6435
5350a031 6436 if (!connector->base.state)
08d9bc92
ACO
6437 return -ENOMEM;
6438
08d9bc92
ACO
6439 return 0;
6440}
6441
6442struct intel_connector *intel_connector_alloc(void)
6443{
6444 struct intel_connector *connector;
6445
6446 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6447 if (!connector)
6448 return NULL;
6449
6450 if (intel_connector_init(connector) < 0) {
6451 kfree(connector);
6452 return NULL;
6453 }
6454
6455 return connector;
6456}
6457
f0947c37
DV
6458/* Simple connector->get_hw_state implementation for encoders that support only
6459 * one connector and no cloning and hence the encoder state determines the state
6460 * of the connector. */
6461bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6462{
24929352 6463 enum pipe pipe = 0;
f0947c37 6464 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6465
f0947c37 6466 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW
6467}
6468
6d293983 6469static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6470{
6d293983
ACO
6471 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6472 return crtc_state->fdi_lanes;
d272ddfa
VS
6473
6474 return 0;
6475}
6476
6d293983 6477static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6478 struct intel_crtc_state *pipe_config)
1857e1da 6479{
6d293983
ACO
6480 struct drm_atomic_state *state = pipe_config->base.state;
6481 struct intel_crtc *other_crtc;
6482 struct intel_crtc_state *other_crtc_state;
6483
1857e1da
DV
6484 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6485 pipe_name(pipe), pipe_config->fdi_lanes);
6486 if (pipe_config->fdi_lanes > 4) {
6487 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6488 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6489 return -EINVAL;
1857e1da
DV
6490 }
6491
bafb6553 6492 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV
6493 if (pipe_config->fdi_lanes > 2) {
6494 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6495 pipe_config->fdi_lanes);
6d293983 6496 return -EINVAL;
1857e1da 6497 } else {
6d293983 6498 return 0;
1857e1da
DV
6499 }
6500 }
6501
6502 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6503 return 0;
1857e1da
DV
6504
6505 /* Ivybridge 3 pipe is really complicated */
6506 switch (pipe) {
6507 case PIPE_A:
6d293983 6508 return 0;
1857e1da 6509 case PIPE_B:
6d293983
ACO
6510 if (pipe_config->fdi_lanes <= 2)
6511 return 0;
6512
6513 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6514 other_crtc_state =
6515 intel_atomic_get_crtc_state(state, other_crtc);
6516 if (IS_ERR(other_crtc_state))
6517 return PTR_ERR(other_crtc_state);
6518
6519 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV
6520 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6521 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6522 return -EINVAL;
1857e1da 6523 }
6d293983 6524 return 0;
1857e1da 6525 case PIPE_C:
251cc67c
VS
6526 if (pipe_config->fdi_lanes > 2) {
6527 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6528 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6529 return -EINVAL;
251cc67c 6530 }
6d293983
ACO
6531
6532 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6533 other_crtc_state =
6534 intel_atomic_get_crtc_state(state, other_crtc);
6535 if (IS_ERR(other_crtc_state))
6536 return PTR_ERR(other_crtc_state);
6537
6538 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6539 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6540 return -EINVAL;
1857e1da 6541 }
6d293983 6542 return 0;
1857e1da
DV
6543 default:
6544 BUG();
6545 }
6546}
6547
e29c22c0
DV
6548#define RETRY 1
6549static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6550 struct intel_crtc_state *pipe_config)
877d48d5 6551{
1857e1da 6552 struct drm_device *dev = intel_crtc->base.dev;
7c5f93b0 6553 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO
6554 int lane, link_bw, fdi_dotclock, ret;
6555 bool needs_recompute = false;
877d48d5 6556
e29c22c0 6557retry:
877d48d5
DV
6558 /* FDI is a binary signal running at ~2.7GHz, encoding
6559 * each output octet as 10 bits. The actual frequency
6560 * is stored as a divider into a 100MHz clock, and the
6561 * mode pixel clock is stored in units of 1KHz.
6562 * Hence the bw of each lane in terms of the mode signal
6563 * is:
6564 */
21a727b3 6565 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
877d48d5 6566
241bfc38 6567 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6568
2bd89a07 6569 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV
6570 pipe_config->pipe_bpp);
6571
6572 pipe_config->fdi_lanes = lane;
6573
2bd89a07 6574 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6575 link_bw, &pipe_config->fdi_m_n);
1857e1da 6576
e3b247da 6577 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6d293983 6578 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV
6579 pipe_config->pipe_bpp -= 2*3;
6580 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6581 pipe_config->pipe_bpp);
6582 needs_recompute = true;
6583 pipe_config->bw_constrained = true;
6584
6585 goto retry;
6586 }
6587
6588 if (needs_recompute)
6589 return RETRY;
6590
6d293983 6591 return ret;
877d48d5
DV
6592}
6593
8cfb3407
VS
6594static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6595 struct intel_crtc_state *pipe_config)
6596{
6597 if (pipe_config->pipe_bpp > 24)
6598 return false;
6599
6600 /* HSW can handle pixel rate up to cdclk? */
2d1fe073 6601 if (IS_HASWELL(dev_priv))
8cfb3407
VS
6602 return true;
6603
6604 /*
b432e5cf
VS
6605 * We compare against max which means we must take
6606 * the increased cdclk requirement into account when
6607 * calculating the new cdclk.
6608 *
6609 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS
6610 */
6611 return ilk_pipe_pixel_rate(pipe_config) <=
6612 dev_priv->max_cdclk_freq * 95 / 100;
6613}
6614
42db64ef 6615static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6616 struct intel_crtc_state *pipe_config)
42db64ef 6617{
8cfb3407
VS
6618 struct drm_device *dev = crtc->base.dev;
6619 struct drm_i915_private *dev_priv = dev->dev_private;
6620
d330a953 6621 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS
6622 hsw_crtc_supports_ips(crtc) &&
6623 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ
6624}
6625
39acb4aa
VS
6626static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6627{
6628 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6629
6630 /* GDG double wide on either pipe, otherwise pipe A only */
6631 return INTEL_INFO(dev_priv)->gen < 4 &&
6632 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6633}
6634
a43f6e0f 6635static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6636 struct intel_crtc_state *pipe_config)
79e53945 6637{
a43f6e0f 6638 struct drm_device *dev = crtc->base.dev;
8bd31e67 6639 struct drm_i915_private *dev_priv = dev->dev_private;
7c5f93b0 6640 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
f3261156 6641 int clock_limit = dev_priv->max_dotclk_freq;
89749350 6642
cf532bb2 6643 if (INTEL_INFO(dev)->gen < 4) {
f3261156 6644 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
cf532bb2
VS
6645
6646 /*
39acb4aa 6647 * Enable double wide mode when the dot clock
cf532bb2 6648 * is > 90% of the (display) core speed.
cf532bb2 6649 */
39acb4aa
VS
6650 if (intel_crtc_supports_double_wide(crtc) &&
6651 adjusted_mode->crtc_clock > clock_limit) {
f3261156 6652 clock_limit = dev_priv->max_dotclk_freq;
cf532bb2 6653 pipe_config->double_wide = true;
ad3a4479 6654 }
f3261156 6655 }
ad3a4479 6656
f3261156
VS
6657 if (adjusted_mode->crtc_clock > clock_limit) {
6658 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6659 adjusted_mode->crtc_clock, clock_limit,
6660 yesno(pipe_config->double_wide));
6661 return -EINVAL;
2c07245f 6662 }
89749350 6663
1d1d0e27
VS
6664 /*
6665 * Pipe horizontal size must be even in:
6666 * - DVO ganged mode
6667 * - LVDS dual channel mode
6668 * - Double wide pipe
6669 */
a93e255f 6670 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS
6671 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6672 pipe_config->pipe_src_w &= ~1;
6673
8693a824
DL
6674 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6675 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW
6676 */
6677 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
aad941d5 6678 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
e29c22c0 6679 return -EINVAL;
44f46b42 6680
f5adf94e 6681 if (HAS_IPS(dev))
a43f6e0f
DV
6682 hsw_compute_ips_config(crtc, pipe_config);
6683
877d48d5 6684 if (pipe_config->has_pch_encoder)
a43f6e0f 6685 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6686
cf5a15be 6687 return 0;
79e53945
JB
6688}
6689
1652d19e
VS
6690static int skylake_get_display_clock_speed(struct drm_device *dev)
6691{
6692 struct drm_i915_private *dev_priv = to_i915(dev);
ea61791e 6693 uint32_t cdctl;
1652d19e 6694
ea61791e 6695 skl_dpll0_update(dev_priv);
1652d19e 6696
63911d72 6697 if (dev_priv->cdclk_pll.vco == 0)
709e05c3 6698 return dev_priv->cdclk_pll.ref;
1652d19e 6699
ea61791e 6700 cdctl = I915_READ(CDCLK_CTL);
1652d19e 6701
63911d72 6702 if (dev_priv->cdclk_pll.vco == 8640000) {
1652d19e
VS
6703 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6704 case CDCLK_FREQ_450_432:
6705 return 432000;
6706 case CDCLK_FREQ_337_308:
487ed2e4 6707 return 308571;
ea61791e
VS
6708 case CDCLK_FREQ_540:
6709 return 540000;
1652d19e 6710 case CDCLK_FREQ_675_617:
487ed2e4 6711 return 617143;
1652d19e 6712 default:
ea61791e 6713 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1652d19e
VS
6714 }
6715 } else {
1652d19e
VS
6716 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6717 case CDCLK_FREQ_450_432:
6718 return 450000;
6719 case CDCLK_FREQ_337_308:
6720 return 337500;
ea61791e
VS
6721 case CDCLK_FREQ_540:
6722 return 540000;
1652d19e
VS
6723 case CDCLK_FREQ_675_617:
6724 return 675000;
6725 default:
ea61791e 6726 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1652d19e
VS
6727 }
6728 }
6729
709e05c3 6730 return dev_priv->cdclk_pll.ref;
1652d19e
VS
6731}
6732
83d7c81f
VS
6733static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6734{
6735 u32 val;
6736
6737 dev_priv->cdclk_pll.ref = 19200;
1c3f7700 6738 dev_priv->cdclk_pll.vco = 0;
83d7c81f
VS
6739
6740 val = I915_READ(BXT_DE_PLL_ENABLE);
1c3f7700 6741 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
83d7c81f 6742 return;
83d7c81f 6743
1c3f7700
ID
6744 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
6745 return;
83d7c81f
VS
6746
6747 val = I915_READ(BXT_DE_PLL_CTL);
6748 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6749 dev_priv->cdclk_pll.ref;
6750}
6751
acd3f3d3
BP
6752static int broxton_get_display_clock_speed(struct drm_device *dev)
6753{
6754 struct drm_i915_private *dev_priv = to_i915(dev);
f5986242
VS
6755 u32 divider;
6756 int div, vco;
acd3f3d3 6757
83d7c81f
VS
6758 bxt_de_pll_update(dev_priv);
6759
f5986242
VS
6760 vco = dev_priv->cdclk_pll.vco;
6761 if (vco == 0)
6762 return dev_priv->cdclk_pll.ref;
acd3f3d3 6763
f5986242 6764 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
acd3f3d3 6765
f5986242 6766 switch (divider) {
acd3f3d3 6767 case BXT_CDCLK_CD2X_DIV_SEL_1:
f5986242
VS
6768 div = 2;
6769 break;
acd3f3d3 6770 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
f5986242
VS
6771 div = 3;
6772 break;
acd3f3d3 6773 case BXT_CDCLK_CD2X_DIV_SEL_2:
f5986242
VS
6774 div = 4;
6775 break;
acd3f3d3 6776 case BXT_CDCLK_CD2X_DIV_SEL_4:
f5986242
VS
6777 div = 8;
6778 break;
6779 default:
6780 MISSING_CASE(divider);
6781 return dev_priv->cdclk_pll.ref;
acd3f3d3
BP
6782 }
6783
f5986242 6784 return DIV_ROUND_CLOSEST(vco, div);
acd3f3d3
BP
6785}
6786
1652d19e
VS
6787static int broadwell_get_display_clock_speed(struct drm_device *dev)
6788{
6789 struct drm_i915_private *dev_priv = dev->dev_private;
6790 uint32_t lcpll = I915_READ(LCPLL_CTL);
6791 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6792
6793 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6794 return 800000;
6795 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6796 return 450000;
6797 else if (freq == LCPLL_CLK_FREQ_450)
6798 return 450000;
6799 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6800 return 540000;
6801 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6802 return 337500;
6803 else
6804 return 675000;
6805}
6806
6807static int haswell_get_display_clock_speed(struct drm_device *dev)
6808{
6809 struct drm_i915_private *dev_priv = dev->dev_private;
6810 uint32_t lcpll = I915_READ(LCPLL_CTL);
6811 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6812
6813 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6814 return 800000;
6815 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6816 return 450000;
6817 else if (freq == LCPLL_CLK_FREQ_450)
6818 return 450000;
6819 else if (IS_HSW_ULT(dev))
6820 return 337500;
6821 else
6822 return 540000;
79e53945
JB
6823}
6824
25eb05fc
JB
6825static int valleyview_get_display_clock_speed(struct drm_device *dev)
6826{
bfa7df01
VS
6827 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6828 CCK_DISPLAY_CLOCK_CONTROL);
25eb05fc
JB
6829}
6830
b37a6434
VS
6831static int ilk_get_display_clock_speed(struct drm_device *dev)
6832{
6833 return 450000;
6834}
6835
e70236a8
JB
6836static int i945_get_display_clock_speed(struct drm_device *dev)
6837{
6838 return 400000;
6839}
79e53945 6840
e70236a8 6841static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6842{
e907f170 6843 return 333333;
e70236a8 6844}
79e53945 6845
e70236a8
JB
6846static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6847{
6848 return 200000;
6849}
79e53945 6850
257a7ffc
DV
6851static int pnv_get_display_clock_speed(struct drm_device *dev)
6852{
6853 u16 gcfgc = 0;
6854
6855 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6856
6857 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6858 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6859 return 266667;
257a7ffc 6860 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6861 return 333333;
257a7ffc 6862 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6863 return 444444;
257a7ffc
DV
6864 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6865 return 200000;
6866 default:
6867 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6868 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6869 return 133333;
257a7ffc 6870 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6871 return 166667;
257a7ffc
DV
6872 }
6873}
6874
e70236a8
JB
6875static int i915gm_get_display_clock_speed(struct drm_device *dev)
6876{
6877 u16 gcfgc = 0;
79e53945 6878
e70236a8
JB
6879 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6880
6881 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6882 return 133333;
e70236a8
JB
6883 else {
6884 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6885 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6886 return 333333;
e70236a8
JB
6887 default:
6888 case GC_DISPLAY_CLOCK_190_200_MHZ:
6889 return 190000;
79e53945 6890 }
e70236a8
JB
6891 }
6892}
6893
6894static int i865_get_display_clock_speed(struct drm_device *dev)
6895{
e907f170 6896 return 266667;
e70236a8
JB
6897}
6898
1b1d2716 6899static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB
6900{
6901 u16 hpllcc = 0;
1b1d2716 6902
65cd2b3f
VS
6903 /*
6904 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6905 * encoding is different :(
6906 * FIXME is this the right way to detect 852GM/852GMV?
6907 */
6908 if (dev->pdev->revision == 0x1)
6909 return 133333;
6910
1b1d2716
VS
6911 pci_bus_read_config_word(dev->pdev->bus,
6912 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6913
e70236a8
JB
6914 /* Assume that the hardware is in the high speed state. This
6915 * should be the default.
6916 */
6917 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6918 case GC_CLOCK_133_200:
1b1d2716 6919 case GC_CLOCK_133_200_2:
e70236a8
JB
6920 case GC_CLOCK_100_200:
6921 return 200000;
6922 case GC_CLOCK_166_250:
6923 return 250000;
6924 case GC_CLOCK_100_133:
e907f170 6925 return 133333;
1b1d2716
VS
6926 case GC_CLOCK_133_266:
6927 case GC_CLOCK_133_266_2:
6928 case GC_CLOCK_166_266:
6929 return 266667;
e70236a8 6930 }
79e53945 6931
e70236a8
JB
6932 /* Shouldn't happen */
6933 return 0;
6934}
79e53945 6935
e70236a8
JB
6936static int i830_get_display_clock_speed(struct drm_device *dev)
6937{
e907f170 6938 return 133333;
79e53945
JB
6939}
6940
34edce2f
VS
6941static unsigned int intel_hpll_vco(struct drm_device *dev)
6942{
6943 struct drm_i915_private *dev_priv = dev->dev_private;
6944 static const unsigned int blb_vco[8] = {
6945 [0] = 3200000,
6946 [1] = 4000000,
6947 [2] = 5333333,
6948 [3] = 4800000,
6949 [4] = 6400000,
6950 };
6951 static const unsigned int pnv_vco[8] = {
6952 [0] = 3200000,
6953 [1] = 4000000,
6954 [2] = 5333333,
6955 [3] = 4800000,
6956 [4] = 2666667,
6957 };
6958 static const unsigned int cl_vco[8] = {
6959 [0] = 3200000,
6960 [1] = 4000000,
6961 [2] = 5333333,
6962 [3] = 6400000,
6963 [4] = 3333333,
6964 [5] = 3566667,
6965 [6] = 4266667,
6966 };
6967 static const unsigned int elk_vco[8] = {
6968 [0] = 3200000,
6969 [1] = 4000000,
6970 [2] = 5333333,
6971 [3] = 4800000,
6972 };
6973 static const unsigned int ctg_vco[8] = {
6974 [0] = 3200000,
6975 [1] = 4000000,
6976 [2] = 5333333,
6977 [3] = 6400000,
6978 [4] = 2666667,
6979 [5] = 4266667,
6980 };
6981 const unsigned int *vco_table;
6982 unsigned int vco;
6983 uint8_t tmp = 0;
6984
6985 /* FIXME other chipsets? */
6986 if (IS_GM45(dev))
6987 vco_table = ctg_vco;
6988 else if (IS_G4X(dev))
6989 vco_table = elk_vco;
6990 else if (IS_CRESTLINE(dev))
6991 vco_table = cl_vco;
6992 else if (IS_PINEVIEW(dev))
6993 vco_table = pnv_vco;
6994 else if (IS_G33(dev))
6995 vco_table = blb_vco;
6996 else
6997 return 0;
6998
6999 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7000
7001 vco = vco_table[tmp & 0x7];
7002 if (vco == 0)
7003 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7004 else
7005 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7006
7007 return vco;
7008}
7009
7010static int gm45_get_display_clock_speed(struct drm_device *dev)
7011{
7012 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7013 uint16_t tmp = 0;
7014
7015 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7016
7017 cdclk_sel = (tmp >> 12) & 0x1;
7018
7019 switch (vco) {
7020 case 2666667:
7021 case 4000000:
7022 case 5333333:
7023 return cdclk_sel ? 333333 : 222222;
7024 case 3200000:
7025 return cdclk_sel ? 320000 : 228571;
7026 default:
7027 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7028 return 222222;
7029 }
7030}
7031
7032static int i965gm_get_display_clock_speed(struct drm_device *dev)
7033{
7034 static const uint8_t div_3200[] = { 16, 10, 8 };
7035 static const uint8_t div_4000[] = { 20, 12, 10 };
7036 static const uint8_t div_5333[] = { 24, 16, 14 };
7037 const uint8_t *div_table;
7038 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7039 uint16_t tmp = 0;
7040
7041 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7042
7043 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7044
7045 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7046 goto fail;
7047
7048 switch (vco) {
7049 case 3200000:
7050 div_table = div_3200;
7051 break;
7052 case 4000000:
7053 div_table = div_4000;
7054 break;
7055 case 5333333:
7056 div_table = div_5333;
7057 break;
7058 default:
7059 goto fail;
7060 }
7061
7062 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7063
caf4e252 7064fail:
34edce2f
VS
7065 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7066 return 200000;
7067}
7068
7069static int g33_get_display_clock_speed(struct drm_device *dev)
7070{
7071 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7072 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7073 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7074 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7075 const uint8_t *div_table;
7076 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7077 uint16_t tmp = 0;
7078
7079 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7080
7081 cdclk_sel = (tmp >> 4) & 0x7;
7082
7083 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7084 goto fail;
7085
7086 switch (vco) {
7087 case 3200000:
7088 div_table = div_3200;
7089 break;
7090 case 4000000:
7091 div_table = div_4000;
7092 break;
7093 case 4800000:
7094 div_table = div_4800;
7095 break;
7096 case 5333333:
7097 div_table = div_5333;
7098 break;
7099 default:
7100 goto fail;
7101 }
7102
7103 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7104
caf4e252 7105fail:
34edce2f
VS
7106 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7107 return 190476;
7108}
7109
2c07245f 7110static void
a65851af 7111intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7112{
a65851af
VS
7113 while (*num > DATA_LINK_M_N_MASK ||
7114 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW
7115 *num >>= 1;
7116 *den >>= 1;
7117 }
7118}
7119
a65851af
VS
7120static void compute_m_n(unsigned int m, unsigned int n,
7121 uint32_t *ret_m, uint32_t *ret_n)
7122{
7123 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7124 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7125 intel_reduce_m_n_ratio(ret_m, ret_n);
7126}
7127
e69d0bc1
DV
7128void
7129intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7130 int pixel_clock, int link_clock,
7131 struct intel_link_m_n *m_n)
2c07245f 7132{
e69d0bc1 7133 m_n->tu = 64;
a65851af
VS
7134
7135 compute_m_n(bits_per_pixel * pixel_clock,
7136 link_clock * nlanes * 8,
7137 &m_n->gmch_m, &m_n->gmch_n);
7138
7139 compute_m_n(pixel_clock, link_clock,
7140 &m_n->link_m, &m_n->link_n);
2c07245f
ZW
7141}
7142
a7615030
CW
7143static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7144{
d330a953
JN
7145 if (i915.panel_use_ssc >= 0)
7146 return i915.panel_use_ssc != 0;
41aa3448 7147 return dev_priv->vbt.lvds_use_ssc
435793df 7148 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW
7149}
7150
7429e9d4 7151static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7152{
7df00d7a 7153 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7154}
f47709a9 7155
7429e9d4
DV
7156static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7157{
7158 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB
7159}
7160
f47709a9 7161static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7162 struct intel_crtc_state *crtc_state,
9e2c8475 7163 struct dpll *reduced_clock)
a7516a05 7164{
f47709a9 7165 struct drm_device *dev = crtc->base.dev;
a7516a05
JB
7166 u32 fp, fp2 = 0;
7167
7168 if (IS_PINEVIEW(dev)) {
190f68c5 7169 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7170 if (reduced_clock)
7429e9d4 7171 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7172 } else {
190f68c5 7173 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7174 if (reduced_clock)
7429e9d4 7175 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB
7176 }
7177
190f68c5 7178 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7179
f47709a9 7180 crtc->lowfreq_avail = false;
a93e255f 7181 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7182 reduced_clock) {
190f68c5 7183 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7184 crtc->lowfreq_avail = true;
a7516a05 7185 } else {
190f68c5 7186 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB
7187 }
7188}
7189
5e69f97f
CML
7190static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7191 pipe)
89b667f8
JB
7192{
7193 u32 reg_val;
7194
7195 /*
7196 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7197 * and set it to a reasonable value instead.
7198 */
ab3c759a 7199 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB
7200 reg_val &= 0xffffff00;
7201 reg_val |= 0x00000030;
ab3c759a 7202 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7203
ab3c759a 7204 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB
7205 reg_val &= 0x8cffffff;
7206 reg_val = 0x8c000000;
ab3c759a 7207 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7208
ab3c759a 7209 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7210 reg_val &= 0xffffff00;
ab3c759a 7211 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7212
ab3c759a 7213 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB
7214 reg_val &= 0x00ffffff;
7215 reg_val |= 0xb0000000;
ab3c759a 7216 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB
7217}
7218
b551842d
DV
7219static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7220 struct intel_link_m_n *m_n)
7221{
7222 struct drm_device *dev = crtc->base.dev;
7223 struct drm_i915_private *dev_priv = dev->dev_private;
7224 int pipe = crtc->pipe;
7225
e3b95f1e
DV
7226 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7227 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7228 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7229 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV
7230}
7231
7232static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK
7233 struct intel_link_m_n *m_n,
7234 struct intel_link_m_n *m2_n2)
b551842d
DV
7235{
7236 struct drm_device *dev = crtc->base.dev;
7237 struct drm_i915_private *dev_priv = dev->dev_private;
7238 int pipe = crtc->pipe;
6e3c9717 7239 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV
7240
7241 if (INTEL_INFO(dev)->gen >= 5) {
7242 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7243 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7244 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7245 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK
7246 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7247 * for gen < 8) and if DRRS is supported (to make sure the
7248 * registers are not unnecessarily accessed).
7249 */
44395bfe 7250 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7251 crtc->config->has_drrs) {
f769cd24
VK
7252 I915_WRITE(PIPE_DATA_M2(transcoder),
7253 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7254 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7255 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7256 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7257 }
b551842d 7258 } else {
e3b95f1e
DV
7259 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7260 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7261 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7262 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV
7263 }
7264}
7265
fe3cd48d 7266void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7267{
fe3cd48d
R
7268 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7269
7270 if (m_n == M1_N1) {
7271 dp_m_n = &crtc->config->dp_m_n;
7272 dp_m2_n2 = &crtc->config->dp_m2_n2;
7273 } else if (m_n == M2_N2) {
7274
7275 /*
7276 * M2_N2 registers are not supported. Hence m2_n2 divider value
7277 * needs to be programmed into M1_N1.
7278 */
7279 dp_m_n = &crtc->config->dp_m2_n2;
7280 } else {
7281 DRM_ERROR("Unsupported divider value\n");
7282 return;
7283 }
7284
6e3c9717
ACO
7285 if (crtc->config->has_pch_encoder)
7286 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7287 else
fe3cd48d 7288 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV
7289}
7290
251ac862
DV
7291static void vlv_compute_dpll(struct intel_crtc *crtc,
7292 struct intel_crtc_state *pipe_config)
bdd4b6a6 7293{
03ed5cbf 7294 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
cd2d34d9 7295 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
03ed5cbf
VS
7296 if (crtc->pipe != PIPE_A)
7297 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
bdd4b6a6 7298
cd2d34d9 7299 /* DPLL not used with DSI, but still need the rest set up */
187a1c07 7300 if (!pipe_config->has_dsi_encoder)
cd2d34d9
VS
7301 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7302 DPLL_EXT_BUFFER_ENABLE_VLV;
7303
03ed5cbf
VS
7304 pipe_config->dpll_hw_state.dpll_md =
7305 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7306}
bdd4b6a6 7307
03ed5cbf
VS
7308static void chv_compute_dpll(struct intel_crtc *crtc,
7309 struct intel_crtc_state *pipe_config)
7310{
7311 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
cd2d34d9 7312 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
03ed5cbf
VS
7313 if (crtc->pipe != PIPE_A)
7314 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7315
cd2d34d9 7316 /* DPLL not used with DSI, but still need the rest set up */
187a1c07 7317 if (!pipe_config->has_dsi_encoder)
cd2d34d9
VS
7318 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7319
03ed5cbf
VS
7320 pipe_config->dpll_hw_state.dpll_md =
7321 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
bdd4b6a6
DV
7322}
7323
d288f65f 7324static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7325 const struct intel_crtc_state *pipe_config)
a0c4da24 7326{
f47709a9 7327 struct drm_device *dev = crtc->base.dev;
a0c4da24 7328 struct drm_i915_private *dev_priv = dev->dev_private;
cd2d34d9 7329 enum pipe pipe = crtc->pipe;
bdd4b6a6 7330 u32 mdiv;
a0c4da24 7331 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7332 u32 coreclk, reg_val;
a0c4da24 7333
cd2d34d9
VS
7334 /* Enable Refclk */
7335 I915_WRITE(DPLL(pipe),
7336 pipe_config->dpll_hw_state.dpll &
7337 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7338
7339 /* No need to actually set up the DPLL with DSI */
7340 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7341 return;
7342
a580516d 7343 mutex_lock(&dev_priv->sb_lock);
09153000 7344
d288f65f
VS
7345 bestn = pipe_config->dpll.n;
7346 bestm1 = pipe_config->dpll.m1;
7347 bestm2 = pipe_config->dpll.m2;
7348 bestp1 = pipe_config->dpll.p1;
7349 bestp2 = pipe_config->dpll.p2;
a0c4da24 7350
89b667f8
JB
7351 /* See eDP HDMI DPIO driver vbios notes doc */
7352
7353 /* PLL B needs special handling */
bdd4b6a6 7354 if (pipe == PIPE_B)
5e69f97f 7355 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB
7356
7357 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7358 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB
7359
7360 /* Disable target IRef on PLL */
ab3c759a 7361 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7362 reg_val &= 0x00ffffff;
ab3c759a 7363 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB
7364
7365 /* Disable fast lock */
ab3c759a 7366 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB
7367
7368 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB
7369 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7370 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7371 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7372 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB
7373
7374 /*
7375 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7376 * but we don't support that).
7377 * Note: don't use the DAC post divider as it seems unstable.
7378 */
7379 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7380 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7381
a0c4da24 7382 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7383 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7384
89b667f8 7385 /* Set HBR and RBR LPF coefficients */
d288f65f 7386 if (pipe_config->port_clock == 162000 ||
409ee761
ACO
7387 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7388 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7389 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7390 0x009f0003);
89b667f8 7391 else
ab3c759a 7392 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB
7393 0x00d0000f);
7394
681a8504 7395 if (pipe_config->has_dp_encoder) {
89b667f8 7396 /* Use SSC source */
bdd4b6a6 7397 if (pipe == PIPE_A)
ab3c759a 7398 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7399 0x0df40000);
7400 else
ab3c759a 7401 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7402 0x0df70000);
7403 } else { /* HDMI or VGA */
7404 /* Use bend source */
bdd4b6a6 7405 if (pipe == PIPE_A)
ab3c759a 7406 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7407 0x0df70000);
7408 else
ab3c759a 7409 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
7410 0x0df40000);
7411 }
a0c4da24 7412
ab3c759a 7413 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7414 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO
7415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7416 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7417 coreclk |= 0x01000000;
ab3c759a 7418 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7419
ab3c759a 7420 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7421 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB
7422}
7423
d288f65f 7424static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7425 const struct intel_crtc_state *pipe_config)
9d556c99
CML
7426{
7427 struct drm_device *dev = crtc->base.dev;
7428 struct drm_i915_private *dev_priv = dev->dev_private;
cd2d34d9 7429 enum pipe pipe = crtc->pipe;
9d556c99 7430 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7431 u32 loopfilter, tribuf_calcntr;
9d556c99 7432 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7433 u32 dpio_val;
9cbe40c1 7434 int vco;
9d556c99 7435
cd2d34d9
VS
7436 /* Enable Refclk and SSC */
7437 I915_WRITE(DPLL(pipe),
7438 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7439
7440 /* No need to actually set up the DPLL with DSI */
7441 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7442 return;
7443
d288f65f
VS
7444 bestn = pipe_config->dpll.n;
7445 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7446 bestm1 = pipe_config->dpll.m1;
7447 bestm2 = pipe_config->dpll.m2 >> 22;
7448 bestp1 = pipe_config->dpll.p1;
7449 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7450 vco = pipe_config->dpll.vco;
a945ce7e 7451 dpio_val = 0;
9cbe40c1 7452 loopfilter = 0;
9d556c99 7453
a580516d 7454 mutex_lock(&dev_priv->sb_lock);
9d556c99 7455
9d556c99
CML
7456 /* p1 and p2 divider */
7457 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7458 5 << DPIO_CHV_S1_DIV_SHIFT |
7459 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7460 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7461 1 << DPIO_CHV_K_DIV_SHIFT);
7462
7463 /* Feedback post-divider - m2 */
7464 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7465
7466 /* Feedback refclk divider - n and m1 */
7467 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7468 DPIO_CHV_M1_DIV_BY_2 |
7469 1 << DPIO_CHV_N_DIV_SHIFT);
7470
7471 /* M2 fraction division */
25a25dfc 7472 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML
7473
7474 /* M2 fraction division enable */
a945ce7e
VP
7475 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7476 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7477 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7478 if (bestm2_frac)
7479 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7480 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7481
de3a0fde
VP
7482 /* Program digital lock detect threshold */
7483 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7484 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7485 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7486 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7487 if (!bestm2_frac)
7488 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7489 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7490
9d556c99 7491 /* Loop filter */
9cbe40c1
VP
7492 if (vco == 5400000) {
7493 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7494 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7495 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7496 tribuf_calcntr = 0x9;
7497 } else if (vco <= 6200000) {
7498 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7499 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7500 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7501 tribuf_calcntr = 0x9;
7502 } else if (vco <= 6480000) {
7503 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7504 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7505 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7506 tribuf_calcntr = 0x8;
7507 } else {
7508 /* Not supported. Apply the same limits as in the max case */
7509 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7510 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7511 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7512 tribuf_calcntr = 0;
7513 }
9d556c99
CML
7514 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7515
968040b2 7516 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP
7517 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7518 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7519 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7520
9d556c99
CML
7521 /* AFC Recal */
7522 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7523 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7524 DPIO_AFC_RECAL);
7525
a580516d 7526 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML
7527}
7528
d288f65f
VS
7529/**
7530 * vlv_force_pll_on - forcibly enable just the PLL
7531 * @dev_priv: i915 private structure
7532 * @pipe: pipe PLL to enable
7533 * @dpll: PLL configuration
7534 *
7535 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7536 * in cases where we need the PLL enabled even when @pipe is not going to
7537 * be enabled.
7538 */
3f36b937
TU
7539int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7540 const struct dpll *dpll)
d288f65f
VS
7541{
7542 struct intel_crtc *crtc =
7543 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
3f36b937
TU
7544 struct intel_crtc_state *pipe_config;
7545
7546 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7547 if (!pipe_config)
7548 return -ENOMEM;
7549
7550 pipe_config->base.crtc = &crtc->base;
7551 pipe_config->pixel_multiplier = 1;
7552 pipe_config->dpll = *dpll;
d288f65f
VS
7553
7554 if (IS_CHERRYVIEW(dev)) {
3f36b937
TU
7555 chv_compute_dpll(crtc, pipe_config);
7556 chv_prepare_pll(crtc, pipe_config);
7557 chv_enable_pll(crtc, pipe_config);
d288f65f 7558 } else {
3f36b937
TU
7559 vlv_compute_dpll(crtc, pipe_config);
7560 vlv_prepare_pll(crtc, pipe_config);
7561 vlv_enable_pll(crtc, pipe_config);
d288f65f 7562 }
3f36b937
TU
7563
7564 kfree(pipe_config);
7565
7566 return 0;
d288f65f
VS
7567}
7568
7569/**
7570 * vlv_force_pll_off - forcibly disable just the PLL
7571 * @dev_priv: i915 private structure
7572 * @pipe: pipe PLL to disable
7573 *
7574 * Disable the PLL for @pipe. To be used in cases where we need
7575 * the PLL enabled even when @pipe is not going to be enabled.
7576 */
7577void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7578{
7579 if (IS_CHERRYVIEW(dev))
7580 chv_disable_pll(to_i915(dev), pipe);
7581 else
7582 vlv_disable_pll(to_i915(dev), pipe);
7583}
7584
251ac862
DV
7585static void i9xx_compute_dpll(struct intel_crtc *crtc,
7586 struct intel_crtc_state *crtc_state,
9e2c8475 7587 struct dpll *reduced_clock)
eb1cbe48 7588{
f47709a9 7589 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7590 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV
7591 u32 dpll;
7592 bool is_sdvo;
190f68c5 7593 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7594
190f68c5 7595 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7596
a93e255f
ACO
7597 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7598 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV
7599
7600 dpll = DPLL_VGA_MODE_DIS;
7601
a93e255f 7602 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV
7603 dpll |= DPLLB_MODE_LVDS;
7604 else
7605 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7606
ef1b460d 7607 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7608 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7609 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7610 }
198a037f
DV
7611
7612 if (is_sdvo)
4a33e48d 7613 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7614
190f68c5 7615 if (crtc_state->has_dp_encoder)
4a33e48d 7616 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV
7617
7618 /* compute bitmask from p1 value */
7619 if (IS_PINEVIEW(dev))
7620 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7621 else {
7622 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7623 if (IS_G4X(dev) && reduced_clock)
7624 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7625 }
7626 switch (clock->p2) {
7627 case 5:
7628 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7629 break;
7630 case 7:
7631 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7632 break;
7633 case 10:
7634 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7635 break;
7636 case 14:
7637 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7638 break;
7639 }
7640 if (INTEL_INFO(dev)->gen >= 4)
7641 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7642
190f68c5 7643 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7644 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7645 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ceb41007 7646 intel_panel_use_ssc(dev_priv))
eb1cbe48
DV
7647 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7648 else
7649 dpll |= PLL_REF_INPUT_DREFCLK;
7650
7651 dpll |= DPLL_VCO_ENABLE;
190f68c5 7652 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7653
eb1cbe48 7654 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7655 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7656 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7657 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV
7658 }
7659}
7660
251ac862
DV
7661static void i8xx_compute_dpll(struct intel_crtc *crtc,
7662 struct intel_crtc_state *crtc_state,
9e2c8475 7663 struct dpll *reduced_clock)
eb1cbe48 7664{
f47709a9 7665 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7666 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7667 u32 dpll;
190f68c5 7668 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7669
190f68c5 7670 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7671
eb1cbe48
DV
7672 dpll = DPLL_VGA_MODE_DIS;
7673
a93e255f 7674 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV
7675 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7676 } else {
7677 if (clock->p1 == 2)
7678 dpll |= PLL_P1_DIVIDE_BY_TWO;
7679 else
7680 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7681 if (clock->p2 == 4)
7682 dpll |= PLL_P2_DIVIDE_BY_4;
7683 }
7684
a93e255f 7685 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV
7686 dpll |= DPLL_DVO_2X_MODE;
7687
a93e255f 7688 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ceb41007 7689 intel_panel_use_ssc(dev_priv))
eb1cbe48
DV
7690 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7691 else
7692 dpll |= PLL_REF_INPUT_DREFCLK;
7693
7694 dpll |= DPLL_VCO_ENABLE;
190f68c5 7695 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV
7696}
7697
8a654f3b 7698static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ
7699{
7700 struct drm_device *dev = intel_crtc->base.dev;
7701 struct drm_i915_private *dev_priv = dev->dev_private;
7702 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7703 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7c5f93b0 7704 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS
7705 uint32_t crtc_vtotal, crtc_vblank_end;
7706 int vsyncshift = 0;
4d8a62ea
DV
7707
7708 /* We need to be careful not to changed the adjusted mode, for otherwise
7709 * the hw state checker will get angry at the mismatch. */
7710 crtc_vtotal = adjusted_mode->crtc_vtotal;
7711 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7712
609aeaca 7713 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7714 /* the chip adds 2 halflines automatically */
4d8a62ea
DV
7715 crtc_vtotal -= 1;
7716 crtc_vblank_end -= 1;
609aeaca 7717
409ee761 7718 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS
7719 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7720 else
7721 vsyncshift = adjusted_mode->crtc_hsync_start -
7722 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS
7723 if (vsyncshift < 0)
7724 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ
7725 }
7726
7727 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7728 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7729
fe2b8f9d 7730 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ
7731 (adjusted_mode->crtc_hdisplay - 1) |
7732 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7733 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ
7734 (adjusted_mode->crtc_hblank_start - 1) |
7735 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7736 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ
7737 (adjusted_mode->crtc_hsync_start - 1) |
7738 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7739
fe2b8f9d 7740 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7741 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7742 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7743 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7744 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7745 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7746 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ
7747 (adjusted_mode->crtc_vsync_start - 1) |
7748 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7749
b5e508d4
PZ
7750 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7751 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7752 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7753 * bits. */
7754 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7755 (pipe == PIPE_B || pipe == PIPE_C))
7756 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7757
bc58be60
JN
7758}
7759
7760static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7761{
7762 struct drm_device *dev = intel_crtc->base.dev;
7763 struct drm_i915_private *dev_priv = dev->dev_private;
7764 enum pipe pipe = intel_crtc->pipe;
7765
b0e77b9c
PZ
7766 /* pipesrc controls the size that is scaled from, which should
7767 * always be the user's requested size.
7768 */
7769 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO
7770 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7771 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ
7772}
7773
1bd1bd80 7774static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7775 struct intel_crtc_state *pipe_config)
1bd1bd80
DV
7776{
7777 struct drm_device *dev = crtc->base.dev;
7778 struct drm_i915_private *dev_priv = dev->dev_private;
7779 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7780 uint32_t tmp;
7781
7782 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO
7783 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7784 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7785 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO
7786 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7787 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7788 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO
7789 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7790 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV
7791
7792 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO
7793 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7794 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7795 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO
7796 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7797 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7798 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO
7799 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7800 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV
7801
7802 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO
7803 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7804 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7805 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80 7806 }
bc58be60
JN
7807}
7808
7809static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7810 struct intel_crtc_state *pipe_config)
7811{
7812 struct drm_device *dev = crtc->base.dev;
7813 struct drm_i915_private *dev_priv = dev->dev_private;
7814 u32 tmp;
1bd1bd80
DV
7815
7816 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS
7817 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7818 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7819
2d112de7
ACO
7820 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7821 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV
7822}
7823
f6a83288 7824void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7825 struct intel_crtc_state *pipe_config)
babea61d 7826{
2d112de7
ACO
7827 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7828 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7829 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7830 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7831
2d112de7
ACO
7832 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7833 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7834 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7835 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7836
2d112de7 7837 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7838 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7839
2d112de7
ACO
7840 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7841 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML
7842
7843 mode->hsync = drm_mode_hsync(mode);
7844 mode->vrefresh = drm_mode_vrefresh(mode);
7845 drm_mode_set_name(mode);
babea61d
JB
7846}
7847
84b046f3
DV
7848static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7849{
7850 struct drm_device *dev = intel_crtc->base.dev;
7851 struct drm_i915_private *dev_priv = dev->dev_private;
7852 uint32_t pipeconf;
7853
9f11a9e4 7854 pipeconf = 0;
84b046f3 7855
b6b5d049
VS
7856 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7857 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7858 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7859
6e3c9717 7860 if (intel_crtc->config->double_wide)
cf532bb2 7861 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7862
ff9ce46e 7863 /* only g4x and later have fancy bpc/dither controls */
666a4537 7864 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ff9ce46e 7865 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7866 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7867 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7868 PIPECONF_DITHER_TYPE_SP;
84b046f3 7869
6e3c9717 7870 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV
7871 case 18:
7872 pipeconf |= PIPECONF_6BPC;
7873 break;
7874 case 24:
7875 pipeconf |= PIPECONF_8BPC;
7876 break;
7877 case 30:
7878 pipeconf |= PIPECONF_10BPC;
7879 break;
7880 default:
7881 /* Case prevented by intel_choose_pipe_bpp_dither. */
7882 BUG();
84b046f3
DV
7883 }
7884 }
7885
7886 if (HAS_PIPE_CXSR(dev)) {
7887 if (intel_crtc->lowfreq_avail) {
7888 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7889 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7890 } else {
7891 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV
7892 }
7893 }
7894
6e3c9717 7895 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7896 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7897 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS
7898 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7899 else
7900 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7901 } else
84b046f3
DV
7902 pipeconf |= PIPECONF_PROGRESSIVE;
7903
666a4537
WB
7904 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7905 intel_crtc->config->limited_color_range)
9f11a9e4 7906 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7907
84b046f3
DV
7908 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7909 POSTING_READ(PIPECONF(intel_crtc->pipe));
7910}
7911
81c97f52
ACO
7912static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7913 struct intel_crtc_state *crtc_state)
7914{
7915 struct drm_device *dev = crtc->base.dev;
7916 struct drm_i915_private *dev_priv = dev->dev_private;
1b6f4958 7917 const struct intel_limit *limit;
81c97f52
ACO
7918 int refclk = 48000;
7919
7920 memset(&crtc_state->dpll_hw_state, 0,
7921 sizeof(crtc_state->dpll_hw_state));
7922
7923 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7924 if (intel_panel_use_ssc(dev_priv)) {
7925 refclk = dev_priv->vbt.lvds_ssc_freq;
7926 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7927 }
7928
7929 limit = &intel_limits_i8xx_lvds;
7930 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7931 limit = &intel_limits_i8xx_dvo;
7932 } else {
7933 limit = &intel_limits_i8xx_dac;
7934 }
7935
7936 if (!crtc_state->clock_set &&
7937 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7938 refclk, NULL, &crtc_state->dpll)) {
7939 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7940 return -EINVAL;
7941 }
7942
7943 i8xx_compute_dpll(crtc, crtc_state, NULL);
7944
7945 return 0;
7946}
7947
19ec6693
ACO
7948static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7949 struct intel_crtc_state *crtc_state)
7950{
7951 struct drm_device *dev = crtc->base.dev;
7952 struct drm_i915_private *dev_priv = dev->dev_private;
1b6f4958 7953 const struct intel_limit *limit;
19ec6693
ACO
7954 int refclk = 96000;
7955
7956 memset(&crtc_state->dpll_hw_state, 0,
7957 sizeof(crtc_state->dpll_hw_state));
7958
7959 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7960 if (intel_panel_use_ssc(dev_priv)) {
7961 refclk = dev_priv->vbt.lvds_ssc_freq;
7962 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7963 }
7964
7965 if (intel_is_dual_link_lvds(dev))
7966 limit = &intel_limits_g4x_dual_channel_lvds;
7967 else
7968 limit = &intel_limits_g4x_single_channel_lvds;
7969 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7970 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7971 limit = &intel_limits_g4x_hdmi;
7972 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7973 limit = &intel_limits_g4x_sdvo;
7974 } else {
7975 /* The option is for other outputs */
7976 limit = &intel_limits_i9xx_sdvo;
7977 }
7978
7979 if (!crtc_state->clock_set &&
7980 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7981 refclk, NULL, &crtc_state->dpll)) {
7982 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7983 return -EINVAL;
7984 }
7985
7986 i9xx_compute_dpll(crtc, crtc_state, NULL);
7987
7988 return 0;
7989}
7990
70e8aa21
ACO
7991static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7992 struct intel_crtc_state *crtc_state)
7993{
7994 struct drm_device *dev = crtc->base.dev;
7995 struct drm_i915_private *dev_priv = dev->dev_private;
1b6f4958 7996 const struct intel_limit *limit;
70e8aa21
ACO
7997 int refclk = 96000;
7998
7999 memset(&crtc_state->dpll_hw_state, 0,
8000 sizeof(crtc_state->dpll_hw_state));
8001
8002 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8003 if (intel_panel_use_ssc(dev_priv)) {
8004 refclk = dev_priv->vbt.lvds_ssc_freq;
8005 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8006 }
8007
8008 limit = &intel_limits_pineview_lvds;
8009 } else {
8010 limit = &intel_limits_pineview_sdvo;
8011 }
8012
8013 if (!crtc_state->clock_set &&
8014 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8015 refclk, NULL, &crtc_state->dpll)) {
8016 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8017 return -EINVAL;
8018 }
8019
8020 i9xx_compute_dpll(crtc, crtc_state, NULL);
8021
8022 return 0;
8023}
8024
190f68c5
ACO
8025static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8026 struct intel_crtc_state *crtc_state)
79e53945 8027{
c7653199 8028 struct drm_device *dev = crtc->base.dev;
79e53945 8029 struct drm_i915_private *dev_priv = dev->dev_private;
1b6f4958 8030 const struct intel_limit *limit;
81c97f52 8031 int refclk = 96000;
79e53945 8032
dd3cd74a
ACO
8033 memset(&crtc_state->dpll_hw_state, 0,
8034 sizeof(crtc_state->dpll_hw_state));
8035
70e8aa21
ACO
8036 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8037 if (intel_panel_use_ssc(dev_priv)) {
8038 refclk = dev_priv->vbt.lvds_ssc_freq;
8039 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8040 }
43565a06 8041
70e8aa21
ACO
8042 limit = &intel_limits_i9xx_lvds;
8043 } else {
8044 limit = &intel_limits_i9xx_sdvo;
81c97f52 8045 }
79e53945 8046
70e8aa21
ACO
8047 if (!crtc_state->clock_set &&
8048 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8049 refclk, NULL, &crtc_state->dpll)) {
8050 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8051 return -EINVAL;
f47709a9 8052 }
7026d4ac 8053
81c97f52 8054 i9xx_compute_dpll(crtc, crtc_state, NULL);
79e53945 8055
c8f7a0db 8056 return 0;
f564048e
EA
8057}
8058
65b3d6a9
ACO
8059static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8060 struct intel_crtc_state *crtc_state)
8061{
8062 int refclk = 100000;
1b6f4958 8063 const struct intel_limit *limit = &intel_limits_chv;
65b3d6a9
ACO
8064
8065 memset(&crtc_state->dpll_hw_state, 0,
8066 sizeof(crtc_state->dpll_hw_state));
8067
65b3d6a9
ACO
8068 if (!crtc_state->clock_set &&
8069 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8070 refclk, NULL, &crtc_state->dpll)) {
8071 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8072 return -EINVAL;
8073 }
8074
8075 chv_compute_dpll(crtc, crtc_state);
8076
8077 return 0;
8078}
8079
8080static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8081 struct intel_crtc_state *crtc_state)
8082{
8083 int refclk = 100000;
1b6f4958 8084 const struct intel_limit *limit = &intel_limits_vlv;
65b3d6a9
ACO
8085
8086 memset(&crtc_state->dpll_hw_state, 0,
8087 sizeof(crtc_state->dpll_hw_state));
8088
65b3d6a9
ACO
8089 if (!crtc_state->clock_set &&
8090 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8091 refclk, NULL, &crtc_state->dpll)) {
8092 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8093 return -EINVAL;
8094 }
8095
8096 vlv_compute_dpll(crtc, crtc_state);
8097
8098 return 0;
8099}
8100
2fa2fe9a 8101static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8102 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV
8103{
8104 struct drm_device *dev = crtc->base.dev;
8105 struct drm_i915_private *dev_priv = dev->dev_private;
8106 uint32_t tmp;
8107
dc9e7dec
VS
8108 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8109 return;
8110
2fa2fe9a 8111 tmp = I915_READ(PFIT_CONTROL);
06922821
DV
8112 if (!(tmp & PFIT_ENABLE))
8113 return;
2fa2fe9a 8114
06922821 8115 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV
8116 if (INTEL_INFO(dev)->gen < 4) {
8117 if (crtc->pipe != PIPE_B)
8118 return;
2fa2fe9a
DV
8119 } else {
8120 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8121 return;
8122 }
8123
06922821 8124 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a 8125 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
2fa2fe9a
DV
8126}
8127
acbec814 8128static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8129 struct intel_crtc_state *pipe_config)
acbec814
JB
8130{
8131 struct drm_device *dev = crtc->base.dev;
8132 struct drm_i915_private *dev_priv = dev->dev_private;
8133 int pipe = pipe_config->cpu_transcoder;
9e2c8475 8134 struct dpll clock;
acbec814 8135 u32 mdiv;
662c6ecb 8136 int refclk = 100000;
acbec814 8137
b521973b
VS
8138 /* In case of DSI, DPLL will not be used */
8139 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
f573de5a
SK
8140 return;
8141
a580516d 8142 mutex_lock(&dev_priv->sb_lock);
ab3c759a 8143 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 8144 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB
8145
8146 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8147 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8148 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8149 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8150 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8151
dccbea3b 8152 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB
8153}
8154
5724dbd1
DL
8155static void
8156i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8157 struct intel_initial_plane_config *plane_config)
1ad292b5
JB
8158{
8159 struct drm_device *dev = crtc->base.dev;
8160 struct drm_i915_private *dev_priv = dev->dev_private;
8161 u32 val, base, offset;
8162 int pipe = crtc->pipe, plane = crtc->plane;
8163 int fourcc, pixel_format;
6761dd31 8164 unsigned int aligned_height;
b113d5ee 8165 struct drm_framebuffer *fb;
1b842c89 8166 struct intel_framebuffer *intel_fb;
1ad292b5 8167
42a7b088
DL
8168 val = I915_READ(DSPCNTR(plane));
8169 if (!(val & DISPLAY_PLANE_ENABLE))
8170 return;
8171
d9806c9f 8172 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8173 if (!intel_fb) {
1ad292b5
JB
8174 DRM_DEBUG_KMS("failed to alloc fb\n");
8175 return;
8176 }
8177
1b842c89
DL
8178 fb = &intel_fb->base;
8179
18c5247e
DV
8180 if (INTEL_INFO(dev)->gen >= 4) {
8181 if (val & DISPPLANE_TILED) {
49af449b 8182 plane_config->tiling = I915_TILING_X;
18c5247e
DV
8183 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8184 }
8185 }
1ad292b5
JB
8186
8187 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8188 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL
8189 fb->pixel_format = fourcc;
8190 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB
8191
8192 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8193 if (plane_config->tiling)
1ad292b5
JB
8194 offset = I915_READ(DSPTILEOFF(plane));
8195 else
8196 offset = I915_READ(DSPLINOFF(plane));
8197 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8198 } else {
8199 base = I915_READ(DSPADDR(plane));
8200 }
8201 plane_config->base = base;
8202
8203 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL
8204 fb->width = ((val >> 16) & 0xfff) + 1;
8205 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB
8206
8207 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8208 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8209
b113d5ee 8210 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV
8211 fb->pixel_format,
8212 fb->modifier[0]);
1ad292b5 8213
f37b5c2b 8214 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8215
2844a921
DL
8216 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8217 pipe_name(pipe), plane, fb->width, fb->height,
8218 fb->bits_per_pixel, base, fb->pitches[0],
8219 plane_config->size);
1ad292b5 8220
2d14030b 8221 plane_config->fb = intel_fb;
1ad292b5
JB
8222}
8223
70b23a98 8224static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8225 struct intel_crtc_state *pipe_config)
70b23a98
VS
8226{
8227 struct drm_device *dev = crtc->base.dev;
8228 struct drm_i915_private *dev_priv = dev->dev_private;
8229 int pipe = pipe_config->cpu_transcoder;
8230 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9e2c8475 8231 struct dpll clock;
0d7b6b11 8232 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS
8233 int refclk = 100000;
8234
b521973b
VS
8235 /* In case of DSI, DPLL will not be used */
8236 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8237 return;
8238
a580516d 8239 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS
8240 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8241 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8242 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8243 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8244 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8245 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS
8246
8247 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID
8248 clock.m2 = (pll_dw0 & 0xff) << 22;
8249 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8250 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS
8251 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8252 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8253 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8254
dccbea3b 8255 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS
8256}
8257
0e8ffe1b 8258static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8259 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV
8260{
8261 struct drm_device *dev = crtc->base.dev;
8262 struct drm_i915_private *dev_priv = dev->dev_private;
1729050e 8263 enum intel_display_power_domain power_domain;
0e8ffe1b 8264 uint32_t tmp;
1729050e 8265 bool ret;
0e8ffe1b 8266
1729050e
ID
8267 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8268 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b5482bd0
ID
8269 return false;
8270
e143a21c 8271 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8106ddbd 8272 pipe_config->shared_dpll = NULL;
eccb140b 8273
1729050e
ID
8274 ret = false;
8275
0e8ffe1b
DV
8276 tmp = I915_READ(PIPECONF(crtc->pipe));
8277 if (!(tmp & PIPECONF_ENABLE))
1729050e 8278 goto out;
0e8ffe1b 8279
666a4537 8280 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
42571aef
VS
8281 switch (tmp & PIPECONF_BPC_MASK) {
8282 case PIPECONF_6BPC:
8283 pipe_config->pipe_bpp = 18;
8284 break;
8285 case PIPECONF_8BPC:
8286 pipe_config->pipe_bpp = 24;
8287 break;
8288 case PIPECONF_10BPC:
8289 pipe_config->pipe_bpp = 30;
8290 break;
8291 default:
8292 break;
8293 }
8294 }
8295
666a4537
WB
8296 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8297 (tmp & PIPECONF_COLOR_RANGE_SELECT))
b5a9fa09
DV
8298 pipe_config->limited_color_range = true;
8299
282740f7
VS
8300 if (INTEL_INFO(dev)->gen < 4)
8301 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8302
1bd1bd80 8303 intel_get_pipe_timings(crtc, pipe_config);
bc58be60 8304 intel_get_pipe_src_size(crtc, pipe_config);
1bd1bd80 8305
2fa2fe9a
DV
8306 i9xx_get_pfit_config(crtc, pipe_config);
8307
6c49f241 8308 if (INTEL_INFO(dev)->gen >= 4) {
c231775c
VS
8309 /* No way to read it out on pipes B and C */
8310 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8311 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8312 else
8313 tmp = I915_READ(DPLL_MD(crtc->pipe));
6c49f241
DV
8314 pipe_config->pixel_multiplier =
8315 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8316 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8317 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV
8318 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8319 tmp = I915_READ(DPLL(crtc->pipe));
8320 pipe_config->pixel_multiplier =
8321 ((tmp & SDVO_MULTIPLIER_MASK)
8322 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8323 } else {
8324 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8325 * port and will be fixed up in the encoder->get_config
8326 * function. */
8327 pipe_config->pixel_multiplier = 1;
8328 }
8bcc2795 8329 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
666a4537 8330 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
1c4e0274
VS
8331 /*
8332 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8333 * on 830. Filter it out here so that we don't
8334 * report errors due to that.
8335 */
8336 if (IS_I830(dev))
8337 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8338
8bcc2795
DV
8339 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8340 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS
8341 } else {
8342 /* Mask out read-only status bits. */
8343 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8344 DPLL_PORTC_READY_MASK |
8345 DPLL_PORTB_READY_MASK);
8bcc2795 8346 }
6c49f241 8347
70b23a98
VS
8348 if (IS_CHERRYVIEW(dev))
8349 chv_crtc_clock_get(crtc, pipe_config);
8350 else if (IS_VALLEYVIEW(dev))
acbec814
JB
8351 vlv_crtc_clock_get(crtc, pipe_config);
8352 else
8353 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8354
0f64614d
VS
8355 /*
8356 * Normally the dotclock is filled in by the encoder .get_config()
8357 * but in case the pipe is enabled w/o any ports we need a sane
8358 * default.
8359 */
8360 pipe_config->base.adjusted_mode.crtc_clock =
8361 pipe_config->port_clock / pipe_config->pixel_multiplier;
8362
1729050e
ID
8363 ret = true;
8364
8365out:
8366 intel_display_power_put(dev_priv, power_domain);
8367
8368 return ret;
0e8ffe1b
DV
8369}
8370
dde86e2d 8371static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB
8372{
8373 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8374 struct intel_encoder *encoder;
1c1a24d2 8375 int i;
74cfd7ac 8376 u32 val, final;
13d83a67 8377 bool has_lvds = false;
199e5d79 8378 bool has_cpu_edp = false;
199e5d79 8379 bool has_panel = false;
99eb6a01
KP
8380 bool has_ck505 = false;
8381 bool can_ssc = false;
1c1a24d2 8382 bool using_ssc_source = false;
13d83a67
JB
8383
8384 /* We need to take the global config into account */
b2784e15 8385 for_each_intel_encoder(dev, encoder) {
199e5d79
KP
8386 switch (encoder->type) {
8387 case INTEL_OUTPUT_LVDS:
8388 has_panel = true;
8389 has_lvds = true;
8390 break;
8391 case INTEL_OUTPUT_EDP:
8392 has_panel = true;
2de6905f 8393 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP
8394 has_cpu_edp = true;
8395 break;
6847d71b
PZ
8396 default:
8397 break;
13d83a67
JB
8398 }
8399 }
8400
99eb6a01 8401 if (HAS_PCH_IBX(dev)) {
41aa3448 8402 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP
8403 can_ssc = has_ck505;
8404 } else {
8405 has_ck505 = false;
8406 can_ssc = true;
8407 }
8408
1c1a24d2
L
8409 /* Check if any DPLLs are using the SSC source */
8410 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8411 u32 temp = I915_READ(PCH_DPLL(i));
8412
8413 if (!(temp & DPLL_VCO_ENABLE))
8414 continue;
8415
8416 if ((temp & PLL_REF_INPUT_MASK) ==
8417 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8418 using_ssc_source = true;
8419 break;
8420 }
8421 }
8422
8423 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8424 has_panel, has_lvds, has_ck505, using_ssc_source);
13d83a67
JB
8425
8426 /* Ironlake: try to setup display ref clock before DPLL
8427 * enabling. This is only under driver's control after
8428 * PCH B stepping, previous chipset stepping should be
8429 * ignoring this setting.
8430 */
74cfd7ac
CW
8431 val = I915_READ(PCH_DREF_CONTROL);
8432
8433 /* As we must carefully and slowly disable/enable each source in turn,
8434 * compute the final state we want first and check if we need to
8435 * make any changes at all.
8436 */
8437 final = val;
8438 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8439 if (has_ck505)
8440 final |= DREF_NONSPREAD_CK505_ENABLE;
8441 else
8442 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8443
8c07eb68 8444 final &= ~DREF_SSC_SOURCE_MASK;
74cfd7ac 8445 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8c07eb68 8446 final &= ~DREF_SSC1_ENABLE;
74cfd7ac
CW
8447
8448 if (has_panel) {
8449 final |= DREF_SSC_SOURCE_ENABLE;
8450
8451 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8452 final |= DREF_SSC1_ENABLE;
8453
8454 if (has_cpu_edp) {
8455 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8456 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8457 else
8458 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8459 } else
8460 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
1c1a24d2
L
8461 } else if (using_ssc_source) {
8462 final |= DREF_SSC_SOURCE_ENABLE;
8463 final |= DREF_SSC1_ENABLE;
74cfd7ac
CW
8464 }
8465
8466 if (final == val)
8467 return;
8468
13d83a67 8469 /* Always enable nonspread source */
74cfd7ac 8470 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8471
99eb6a01 8472 if (has_ck505)
74cfd7ac 8473 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8474 else
74cfd7ac 8475 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8476
199e5d79 8477 if (has_panel) {
74cfd7ac
CW
8478 val &= ~DREF_SSC_SOURCE_MASK;
8479 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8480
199e5d79 8481 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8482 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8483 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8484 val |= DREF_SSC1_ENABLE;
e77166b5 8485 } else
74cfd7ac 8486 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP
8487
8488 /* Get SSC going before enabling the outputs */
74cfd7ac 8489 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
8490 POSTING_READ(PCH_DREF_CONTROL);
8491 udelay(200);
8492
74cfd7ac 8493 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB
8494
8495 /* Enable CPU source on CPU attached eDP */
199e5d79 8496 if (has_cpu_edp) {
99eb6a01 8497 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8498 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8499 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8500 } else
74cfd7ac 8501 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8502 } else
74cfd7ac 8503 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8504
74cfd7ac 8505 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
8506 POSTING_READ(PCH_DREF_CONTROL);
8507 udelay(200);
8508 } else {
1c1a24d2 8509 DRM_DEBUG_KMS("Disabling CPU source output\n");
199e5d79 8510
74cfd7ac 8511 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP
8512
8513 /* Turn off CPU output */
74cfd7ac 8514 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8515
74cfd7ac 8516 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
8517 POSTING_READ(PCH_DREF_CONTROL);
8518 udelay(200);
8519
1c1a24d2
L
8520 if (!using_ssc_source) {
8521 DRM_DEBUG_KMS("Disabling SSC source\n");
199e5d79 8522
1c1a24d2
L
8523 /* Turn off the SSC source */
8524 val &= ~DREF_SSC_SOURCE_MASK;
8525 val |= DREF_SSC_SOURCE_DISABLE;
f165d283 8526
1c1a24d2
L
8527 /* Turn off SSC1 */
8528 val &= ~DREF_SSC1_ENABLE;
8529
8530 I915_WRITE(PCH_DREF_CONTROL, val);
8531 POSTING_READ(PCH_DREF_CONTROL);
8532 udelay(200);
8533 }
13d83a67 8534 }
74cfd7ac
CW
8535
8536 BUG_ON(val != final);
13d83a67
JB
8537}
8538
f31f2d55 8539static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8540{
f31f2d55 8541 uint32_t tmp;
dde86e2d 8542
0ff066a9
PZ
8543 tmp = I915_READ(SOUTH_CHICKEN2);
8544 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8545 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8546
cf3598c2
ID
8547 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8548 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
0ff066a9 8549 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8550
0ff066a9
PZ
8551 tmp = I915_READ(SOUTH_CHICKEN2);
8552 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8553 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8554
cf3598c2
ID
8555 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8556 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
0ff066a9 8557 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ
8558}
8559
8560/* WaMPhyProgramming:hsw */
8561static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8562{
8563 uint32_t tmp;
dde86e2d
PZ
8564
8565 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8566 tmp &= ~(0xFF << 24);
8567 tmp |= (0x12 << 24);
8568 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8569
dde86e2d
PZ
8570 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8571 tmp |= (1 << 11);
8572 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8573
8574 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8575 tmp |= (1 << 11);
8576 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8577
dde86e2d
PZ
8578 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8579 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8580 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8581
8582 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8583 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8584 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8585
0ff066a9
PZ
8586 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8587 tmp &= ~(7 << 13);
8588 tmp |= (5 << 13);
8589 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8590
0ff066a9
PZ
8591 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8592 tmp &= ~(7 << 13);
8593 tmp |= (5 << 13);
8594 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ
8595
8596 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8597 tmp &= ~0xFF;
8598 tmp |= 0x1C;
8599 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8600
8601 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8602 tmp &= ~0xFF;
8603 tmp |= 0x1C;
8604 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8605
8606 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8607 tmp &= ~(0xFF << 16);
8608 tmp |= (0x1C << 16);
8609 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8610
8611 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8612 tmp &= ~(0xFF << 16);
8613 tmp |= (0x1C << 16);
8614 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8615
0ff066a9
PZ
8616 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8617 tmp |= (1 << 27);
8618 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8619
0ff066a9
PZ
8620 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8621 tmp |= (1 << 27);
8622 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8623
0ff066a9
PZ
8624 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8625 tmp &= ~(0xF << 28);
8626 tmp |= (4 << 28);
8627 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8628
0ff066a9
PZ
8629 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8630 tmp &= ~(0xF << 28);
8631 tmp |= (4 << 28);
8632 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ
8633}
8634
2fa86a1f
PZ
8635/* Implements 3 different sequences from BSpec chapter "Display iCLK
8636 * Programming" based on the parameters passed:
8637 * - Sequence to enable CLKOUT_DP
8638 * - Sequence to enable CLKOUT_DP without spread
8639 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8640 */
8641static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8642 bool with_fdi)
f31f2d55
PZ
8643{
8644 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ
8645 uint32_t reg, tmp;
8646
8647 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8648 with_spread = true;
c2699524 8649 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8650 with_fdi = false;
f31f2d55 8651
a580516d 8652 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ
8653
8654 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8655 tmp &= ~SBI_SSCCTL_DISABLE;
8656 tmp |= SBI_SSCCTL_PATHALT;
8657 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8658
8659 udelay(24);
8660
2fa86a1f
PZ
8661 if (with_spread) {
8662 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8663 tmp &= ~SBI_SSCCTL_PATHALT;
8664 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8665
2fa86a1f
PZ
8666 if (with_fdi) {
8667 lpt_reset_fdi_mphy(dev_priv);
8668 lpt_program_fdi_mphy(dev_priv);
8669 }
8670 }
dde86e2d 8671
c2699524 8672 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ
8673 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8674 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8675 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8676
a580516d 8677 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ
8678}
8679
47701c3b
PZ
8680/* Sequence to disable CLKOUT_DP */
8681static void lpt_disable_clkout_dp(struct drm_device *dev)
8682{
8683 struct drm_i915_private *dev_priv = dev->dev_private;
8684 uint32_t reg, tmp;
8685
a580516d 8686 mutex_lock(&dev_priv->sb_lock);
47701c3b 8687
c2699524 8688 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ
8689 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8690 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8691 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8692
8693 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8694 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8695 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8696 tmp |= SBI_SSCCTL_PATHALT;
8697 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8698 udelay(32);
8699 }
8700 tmp |= SBI_SSCCTL_DISABLE;
8701 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8702 }
8703
a580516d 8704 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ
8705}
8706
f7be2c21
VS
8707#define BEND_IDX(steps) ((50 + (steps)) / 5)
8708
8709static const uint16_t sscdivintphase[] = {
8710 [BEND_IDX( 50)] = 0x3B23,
8711 [BEND_IDX( 45)] = 0x3B23,
8712 [BEND_IDX( 40)] = 0x3C23,
8713 [BEND_IDX( 35)] = 0x3C23,
8714 [BEND_IDX( 30)] = 0x3D23,
8715 [BEND_IDX( 25)] = 0x3D23,
8716 [BEND_IDX( 20)] = 0x3E23,
8717 [BEND_IDX( 15)] = 0x3E23,
8718 [BEND_IDX( 10)] = 0x3F23,
8719 [BEND_IDX( 5)] = 0x3F23,
8720 [BEND_IDX( 0)] = 0x0025,
8721 [BEND_IDX( -5)] = 0x0025,
8722 [BEND_IDX(-10)] = 0x0125,
8723 [BEND_IDX(-15)] = 0x0125,
8724 [BEND_IDX(-20)] = 0x0225,
8725 [BEND_IDX(-25)] = 0x0225,
8726 [BEND_IDX(-30)] = 0x0325,
8727 [BEND_IDX(-35)] = 0x0325,
8728 [BEND_IDX(-40)] = 0x0425,
8729 [BEND_IDX(-45)] = 0x0425,
8730 [BEND_IDX(-50)] = 0x0525,
8731};
8732
8733/*
8734 * Bend CLKOUT_DP
8735 * steps -50 to 50 inclusive, in steps of 5
8736 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8737 * change in clock period = -(steps / 10) * 5.787 ps
8738 */
8739static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8740{
8741 uint32_t tmp;
8742 int idx = BEND_IDX(steps);
8743
8744 if (WARN_ON(steps % 5 != 0))
8745 return;
8746
8747 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8748 return;
8749
8750 mutex_lock(&dev_priv->sb_lock);
8751
8752 if (steps % 10 != 0)
8753 tmp = 0xAAAAAAAB;
8754 else
8755 tmp = 0x00000000;
8756 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8757
8758 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8759 tmp &= 0xffff0000;
8760 tmp |= sscdivintphase[idx];
8761 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8762
8763 mutex_unlock(&dev_priv->sb_lock);
8764}
8765
8766#undef BEND_IDX
8767
bf8fa3d3
PZ
8768static void lpt_init_pch_refclk(struct drm_device *dev)
8769{
bf8fa3d3
PZ
8770 struct intel_encoder *encoder;
8771 bool has_vga = false;
8772
b2784e15 8773 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ
8774 switch (encoder->type) {
8775 case INTEL_OUTPUT_ANALOG:
8776 has_vga = true;
8777 break;
6847d71b
PZ
8778 default:
8779 break;
bf8fa3d3
PZ
8780 }
8781 }
8782
f7be2c21
VS
8783 if (has_vga) {
8784 lpt_bend_clkout_dp(to_i915(dev), 0);
47701c3b 8785 lpt_enable_clkout_dp(dev, true, true);
f7be2c21 8786 } else {
47701c3b 8787 lpt_disable_clkout_dp(dev);
f7be2c21 8788 }
bf8fa3d3
PZ
8789}
8790
dde86e2d
PZ
8791/*
8792 * Initialize reference clocks when the driver loads
8793 */
8794void intel_init_pch_refclk(struct drm_device *dev)
8795{
8796 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8797 ironlake_init_pch_refclk(dev);
8798 else if (HAS_PCH_LPT(dev))
8799 lpt_init_pch_refclk(dev);
8800}
8801
6ff93609 8802static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8803{
c8203565 8804 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB
8805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8806 int pipe = intel_crtc->pipe;
c8203565
PZ
8807 uint32_t val;
8808
78114071 8809 val = 0;
c8203565 8810
6e3c9717 8811 switch (intel_crtc->config->pipe_bpp) {
c8203565 8812 case 18:
dfd07d72 8813 val |= PIPECONF_6BPC;
c8203565
PZ
8814 break;
8815 case 24:
dfd07d72 8816 val |= PIPECONF_8BPC;
c8203565
PZ
8817 break;
8818 case 30:
dfd07d72 8819 val |= PIPECONF_10BPC;
c8203565
PZ
8820 break;
8821 case 36:
dfd07d72 8822 val |= PIPECONF_12BPC;
c8203565
PZ
8823 break;
8824 default:
cc769b62
PZ
8825 /* Case prevented by intel_choose_pipe_bpp_dither. */
8826 BUG();
c8203565
PZ
8827 }
8828
6e3c9717 8829 if (intel_crtc->config->dither)
c8203565
PZ
8830 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8831
6e3c9717 8832 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ
8833 val |= PIPECONF_INTERLACED_ILK;
8834 else
8835 val |= PIPECONF_PROGRESSIVE;
8836
6e3c9717 8837 if (intel_crtc->config->limited_color_range)
3685a8f3 8838 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8839
c8203565
PZ
8840 I915_WRITE(PIPECONF(pipe), val);
8841 POSTING_READ(PIPECONF(pipe));
8842}
8843
6ff93609 8844static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8845{
391bf048 8846 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
ee2b0b38 8847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 8848 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
391bf048 8849 u32 val = 0;
ee2b0b38 8850
391bf048 8851 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
ee2b0b38
PZ
8852 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8853
6e3c9717 8854 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ
8855 val |= PIPECONF_INTERLACED_ILK;
8856 else
8857 val |= PIPECONF_PROGRESSIVE;
8858
702e7a56
PZ
8859 I915_WRITE(PIPECONF(cpu_transcoder), val);
8860 POSTING_READ(PIPECONF(cpu_transcoder));
391bf048
JN
8861}
8862
391bf048
JN
8863static void haswell_set_pipemisc(struct drm_crtc *crtc)
8864{
8865 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8867
391bf048
JN
8868 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8869 u32 val = 0;
756f85cf 8870
6e3c9717 8871 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ
8872 case 18:
8873 val |= PIPEMISC_DITHER_6_BPC;
8874 break;
8875 case 24:
8876 val |= PIPEMISC_DITHER_8_BPC;
8877 break;
8878 case 30:
8879 val |= PIPEMISC_DITHER_10_BPC;
8880 break;
8881 case 36:
8882 val |= PIPEMISC_DITHER_12_BPC;
8883 break;
8884 default:
8885 /* Case prevented by pipe_config_set_bpp. */
8886 BUG();
8887 }
8888
6e3c9717 8889 if (intel_crtc->config->dither)
756f85cf
PZ
8890 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8891
391bf048 8892 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
756f85cf 8893 }
ee2b0b38
PZ
8894}
8895
d4b1931c
PZ
8896int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8897{
8898 /*
8899 * Account for spread spectrum to avoid
8900 * oversubscribing the link. Max center spread
8901 * is 2.5%; use 5% for safety's sake.
8902 */
8903 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8904 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ
8905}
8906
7429e9d4 8907static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8908{
7429e9d4 8909 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ
8910}
8911
b75ca6f6
ACO
8912static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8913 struct intel_crtc_state *crtc_state,
9e2c8475 8914 struct dpll *reduced_clock)
79e53945 8915{
de13a2e3 8916 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB
8917 struct drm_device *dev = crtc->dev;
8918 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8919 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8920 struct drm_connector *connector;
55bb9992
ACO
8921 struct drm_connector_state *connector_state;
8922 struct intel_encoder *encoder;
b75ca6f6 8923 u32 dpll, fp, fp2;
ceb41007 8924 int factor, i;
09ede541 8925 bool is_lvds = false, is_sdvo = false;
79e53945 8926
da3ced29 8927 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO
8928 if (connector_state->crtc != crtc_state->base.crtc)
8929 continue;
8930
8931 encoder = to_intel_encoder(connector_state->best_encoder);
8932
8933 switch (encoder->type) {
79e53945
JB
8934 case INTEL_OUTPUT_LVDS:
8935 is_lvds = true;
8936 break;
8937 case INTEL_OUTPUT_SDVO:
7d57382e 8938 case INTEL_OUTPUT_HDMI:
79e53945 8939 is_sdvo = true;
79e53945 8940 break;
6847d71b
PZ
8941 default:
8942 break;
79e53945
JB
8943 }
8944 }
79e53945 8945
c1858123 8946 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA
8947 factor = 21;
8948 if (is_lvds) {
8949 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8950 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8951 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8952 factor = 25;
190f68c5 8953 } else if (crtc_state->sdvo_tv_clock)
8febb297 8954 factor = 20;
c1858123 8955
b75ca6f6
ACO
8956 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8957
190f68c5 8958 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
b75ca6f6
ACO
8959 fp |= FP_CB_TUNE;
8960
8961 if (reduced_clock) {
8962 fp2 = i9xx_dpll_compute_fp(reduced_clock);
2c07245f 8963
b75ca6f6
ACO
8964 if (reduced_clock->m < factor * reduced_clock->n)
8965 fp2 |= FP_CB_TUNE;
8966 } else {
8967 fp2 = fp;
8968 }
9a7c7890 8969
5eddb70b 8970 dpll = 0;
2c07245f 8971
a07d6787
EA
8972 if (is_lvds)
8973 dpll |= DPLLB_MODE_LVDS;
8974 else
8975 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8976
190f68c5 8977 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8978 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV
8979
8980 if (is_sdvo)
4a33e48d 8981 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8982 if (crtc_state->has_dp_encoder)
4a33e48d 8983 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8984
a07d6787 8985 /* compute bitmask from p1 value */
190f68c5 8986 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8987 /* also FPA1 */
190f68c5 8988 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8989
190f68c5 8990 switch (crtc_state->dpll.p2) {
a07d6787
EA
8991 case 5:
8992 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8993 break;
8994 case 7:
8995 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8996 break;
8997 case 10:
8998 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8999 break;
9000 case 14:
9001 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9002 break;
79e53945
JB
9003 }
9004
ceb41007 9005 if (is_lvds && intel_panel_use_ssc(dev_priv))
43565a06 9006 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB
9007 else
9008 dpll |= PLL_REF_INPUT_DREFCLK;
9009
b75ca6f6
ACO
9010 dpll |= DPLL_VCO_ENABLE;
9011
9012 crtc_state->dpll_hw_state.dpll = dpll;
9013 crtc_state->dpll_hw_state.fp0 = fp;
9014 crtc_state->dpll_hw_state.fp1 = fp2;
de13a2e3
PZ
9015}
9016
190f68c5
ACO
9017static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9018 struct intel_crtc_state *crtc_state)
de13a2e3 9019{
997c030c
ACO
9020 struct drm_device *dev = crtc->base.dev;
9021 struct drm_i915_private *dev_priv = dev->dev_private;
9e2c8475 9022 struct dpll reduced_clock;
7ed9f894 9023 bool has_reduced_clock = false;
e2b78267 9024 struct intel_shared_dpll *pll;
1b6f4958 9025 const struct intel_limit *limit;
997c030c 9026 int refclk = 120000;
de13a2e3 9027
dd3cd74a
ACO
9028 memset(&crtc_state->dpll_hw_state, 0,
9029 sizeof(crtc_state->dpll_hw_state));
9030
ded220e2
ACO
9031 crtc->lowfreq_avail = false;
9032
9033 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9034 if (!crtc_state->has_pch_encoder)
9035 return 0;
79e53945 9036
997c030c
ACO
9037 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9038 if (intel_panel_use_ssc(dev_priv)) {
9039 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9040 dev_priv->vbt.lvds_ssc_freq);
9041 refclk = dev_priv->vbt.lvds_ssc_freq;
9042 }
9043
9044 if (intel_is_dual_link_lvds(dev)) {
9045 if (refclk == 100000)
9046 limit = &intel_limits_ironlake_dual_lvds_100m;
9047 else
9048 limit = &intel_limits_ironlake_dual_lvds;
9049 } else {
9050 if (refclk == 100000)
9051 limit = &intel_limits_ironlake_single_lvds_100m;
9052 else
9053 limit = &intel_limits_ironlake_single_lvds;
9054 }
9055 } else {
9056 limit = &intel_limits_ironlake_dac;
9057 }
9058
364ee29d 9059 if (!crtc_state->clock_set &&
997c030c
ACO
9060 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9061 refclk, NULL, &crtc_state->dpll)) {
364ee29d
ACO
9062 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9063 return -EINVAL;
f47709a9 9064 }
79e53945 9065
b75ca6f6
ACO
9066 ironlake_compute_dpll(crtc, crtc_state,
9067 has_reduced_clock ? &reduced_clock : NULL);
66e985c0 9068
ded220e2
ACO
9069 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9070 if (pll == NULL) {
9071 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9072 pipe_name(crtc->pipe));
9073 return -EINVAL;
3fb37703 9074 }
79e53945 9075
ded220e2
ACO
9076 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9077 has_reduced_clock)
c7653199 9078 crtc->lowfreq_avail = true;
e2b78267 9079
c8f7a0db 9080 return 0;
79e53945
JB
9081}
9082
eb14cb74
VS
9083static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9084 struct intel_link_m_n *m_n)
9085{
9086 struct drm_device *dev = crtc->base.dev;
9087 struct drm_i915_private *dev_priv = dev->dev_private;
9088 enum pipe pipe = crtc->pipe;
9089
9090 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9091 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9092 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9093 & ~TU_SIZE_MASK;
9094 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9095 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9096 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9097}
9098
9099static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9100 enum transcoder transcoder,
b95af8be
VK
9101 struct intel_link_m_n *m_n,
9102 struct intel_link_m_n *m2_n2)
72419203
DV
9103{
9104 struct drm_device *dev = crtc->base.dev;
9105 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 9106 enum pipe pipe = crtc->pipe;
72419203 9107
eb14cb74
VS
9108 if (INTEL_INFO(dev)->gen >= 5) {
9109 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9110 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9111 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9112 & ~TU_SIZE_MASK;
9113 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9114 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9115 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK
9116 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9117 * gen < 8) and if DRRS is supported (to make sure the
9118 * registers are not unnecessarily read).
9119 */
9120 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 9121 crtc->config->has_drrs) {
b95af8be
VK
9122 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9123 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9124 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9125 & ~TU_SIZE_MASK;
9126 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9127 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9128 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9129 }
eb14cb74
VS
9130 } else {
9131 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9132 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9133 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9134 & ~TU_SIZE_MASK;
9135 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9136 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9137 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9138 }
9139}
9140
9141void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9142 struct intel_crtc_state *pipe_config)
eb14cb74 9143{
681a8504 9144 if (pipe_config->has_pch_encoder)
eb14cb74
VS
9145 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9146 else
9147 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK
9148 &pipe_config->dp_m_n,
9149 &pipe_config->dp_m2_n2);
eb14cb74 9150}
72419203 9151
eb14cb74 9152static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9153 struct intel_crtc_state *pipe_config)
eb14cb74
VS
9154{
9155 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9156 &pipe_config->fdi_m_n, NULL);
72419203
DV
9157}
9158
bd2e244f 9159static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9160 struct intel_crtc_state *pipe_config)
bd2e244f
JB
9161{
9162 struct drm_device *dev = crtc->base.dev;
9163 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK
9164 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9165 uint32_t ps_ctrl = 0;
9166 int id = -1;
9167 int i;
bd2e244f 9168
a1b2278e
CK
9169 /* find scaler attached to this pipe */
9170 for (i = 0; i < crtc->num_scalers; i++) {
9171 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9172 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9173 id = i;
9174 pipe_config->pch_pfit.enabled = true;
9175 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9176 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9177 break;
9178 }
9179 }
bd2e244f 9180
a1b2278e
CK
9181 scaler_state->scaler_id = id;
9182 if (id >= 0) {
9183 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9184 } else {
9185 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB
9186 }
9187}
9188
5724dbd1
DL
9189static void
9190skylake_get_initial_plane_config(struct intel_crtc *crtc,
9191 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL
9192{
9193 struct drm_device *dev = crtc->base.dev;
9194 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9195 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL
9196 int pipe = crtc->pipe;
9197 int fourcc, pixel_format;
6761dd31 9198 unsigned int aligned_height;
bc8d7dff 9199 struct drm_framebuffer *fb;
1b842c89 9200 struct intel_framebuffer *intel_fb;
bc8d7dff 9201
d9806c9f 9202 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9203 if (!intel_fb) {
bc8d7dff
DL
9204 DRM_DEBUG_KMS("failed to alloc fb\n");
9205 return;
9206 }
9207
1b842c89
DL
9208 fb = &intel_fb->base;
9209
bc8d7dff 9210 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL
9211 if (!(val & PLANE_CTL_ENABLE))
9212 goto error;
9213
bc8d7dff
DL
9214 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9215 fourcc = skl_format_to_fourcc(pixel_format,
9216 val & PLANE_CTL_ORDER_RGBX,
9217 val & PLANE_CTL_ALPHA_MASK);
9218 fb->pixel_format = fourcc;
9219 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9220
40f46283
DL
9221 tiling = val & PLANE_CTL_TILED_MASK;
9222 switch (tiling) {
9223 case PLANE_CTL_TILED_LINEAR:
9224 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9225 break;
9226 case PLANE_CTL_TILED_X:
9227 plane_config->tiling = I915_TILING_X;
9228 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9229 break;
9230 case PLANE_CTL_TILED_Y:
9231 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9232 break;
9233 case PLANE_CTL_TILED_YF:
9234 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9235 break;
9236 default:
9237 MISSING_CASE(tiling);
9238 goto error;
9239 }
9240
bc8d7dff
DL
9241 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9242 plane_config->base = base;
9243
9244 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9245
9246 val = I915_READ(PLANE_SIZE(pipe, 0));
9247 fb->height = ((val >> 16) & 0xfff) + 1;
9248 fb->width = ((val >> 0) & 0x1fff) + 1;
9249
9250 val = I915_READ(PLANE_STRIDE(pipe, 0));
7b49f948 9251 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
40f46283 9252 fb->pixel_format);
bc8d7dff
DL
9253 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9254
9255 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV
9256 fb->pixel_format,
9257 fb->modifier[0]);
bc8d7dff 9258
f37b5c2b 9259 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL
9260
9261 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9262 pipe_name(pipe), fb->width, fb->height,
9263 fb->bits_per_pixel, base, fb->pitches[0],
9264 plane_config->size);
9265
2d14030b 9266 plane_config->fb = intel_fb;
bc8d7dff
DL
9267 return;
9268
9269error:
9270 kfree(fb);
9271}
9272
2fa2fe9a 9273static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9274 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV
9275{
9276 struct drm_device *dev = crtc->base.dev;
9277 struct drm_i915_private *dev_priv = dev->dev_private;
9278 uint32_t tmp;
9279
9280 tmp = I915_READ(PF_CTL(crtc->pipe));
9281
9282 if (tmp & PF_ENABLE) {
fd4daa9c 9283 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV
9284 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9285 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV
9286
9287 /* We currently do not free assignements of panel fitters on
9288 * ivb/hsw (since we don't use the higher upscaling modes which
9289 * differentiates them) so just WARN about this case for now. */
9290 if (IS_GEN7(dev)) {
9291 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9292 PF_PIPE_SEL_IVB(crtc->pipe));
9293 }
2fa2fe9a 9294 }
79e53945
JB
9295}
9296
5724dbd1
DL
9297static void
9298ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9299 struct intel_initial_plane_config *plane_config)
4c6baa59
JB
9300{
9301 struct drm_device *dev = crtc->base.dev;
9302 struct drm_i915_private *dev_priv = dev->dev_private;
9303 u32 val, base, offset;
aeee5a49 9304 int pipe = crtc->pipe;
4c6baa59 9305 int fourcc, pixel_format;
6761dd31 9306 unsigned int aligned_height;
b113d5ee 9307 struct drm_framebuffer *fb;
1b842c89 9308 struct intel_framebuffer *intel_fb;
4c6baa59 9309
42a7b088
DL
9310 val = I915_READ(DSPCNTR(pipe));
9311 if (!(val & DISPLAY_PLANE_ENABLE))
9312 return;
9313
d9806c9f 9314 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9315 if (!intel_fb) {
4c6baa59
JB
9316 DRM_DEBUG_KMS("failed to alloc fb\n");
9317 return;
9318 }
9319
1b842c89
DL
9320 fb = &intel_fb->base;
9321
18c5247e
DV
9322 if (INTEL_INFO(dev)->gen >= 4) {
9323 if (val & DISPPLANE_TILED) {
49af449b 9324 plane_config->tiling = I915_TILING_X;
18c5247e
DV
9325 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9326 }
9327 }
4c6baa59
JB
9328
9329 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9330 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL
9331 fb->pixel_format = fourcc;
9332 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9333
aeee5a49 9334 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9335 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9336 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9337 } else {
49af449b 9338 if (plane_config->tiling)
aeee5a49 9339 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9340 else
aeee5a49 9341 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB
9342 }
9343 plane_config->base = base;
9344
9345 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL
9346 fb->width = ((val >> 16) & 0xfff) + 1;
9347 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB
9348
9349 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9350 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9351
b113d5ee 9352 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV
9353 fb->pixel_format,
9354 fb->modifier[0]);
4c6baa59 9355
f37b5c2b 9356 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9357
2844a921
DL
9358 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9359 pipe_name(pipe), fb->width, fb->height,
9360 fb->bits_per_pixel, base, fb->pitches[0],
9361 plane_config->size);
b113d5ee 9362
2d14030b 9363 plane_config->fb = intel_fb;
4c6baa59
JB
9364}
9365
0e8ffe1b 9366static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9367 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV
9368{
9369 struct drm_device *dev = crtc->base.dev;
9370 struct drm_i915_private *dev_priv = dev->dev_private;
1729050e 9371 enum intel_display_power_domain power_domain;
0e8ffe1b 9372 uint32_t tmp;
1729050e 9373 bool ret;
0e8ffe1b 9374
1729050e
ID
9375 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9376 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
930e8c9e
PZ
9377 return false;
9378
e143a21c 9379 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8106ddbd 9380 pipe_config->shared_dpll = NULL;
eccb140b 9381
1729050e 9382 ret = false;
0e8ffe1b
DV
9383 tmp = I915_READ(PIPECONF(crtc->pipe));
9384 if (!(tmp & PIPECONF_ENABLE))
1729050e 9385 goto out;
0e8ffe1b 9386
42571aef
VS
9387 switch (tmp & PIPECONF_BPC_MASK) {
9388 case PIPECONF_6BPC:
9389 pipe_config->pipe_bpp = 18;
9390 break;
9391 case PIPECONF_8BPC:
9392 pipe_config->pipe_bpp = 24;
9393 break;
9394 case PIPECONF_10BPC:
9395 pipe_config->pipe_bpp = 30;
9396 break;
9397 case PIPECONF_12BPC:
9398 pipe_config->pipe_bpp = 36;
9399 break;
9400 default:
9401 break;
9402 }
9403
b5a9fa09
DV
9404 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9405 pipe_config->limited_color_range = true;
9406
ab9412ba 9407 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0 9408 struct intel_shared_dpll *pll;
8106ddbd 9409 enum intel_dpll_id pll_id;
66e985c0 9410
88adfff1
DV
9411 pipe_config->has_pch_encoder = true;
9412
627eb5a3
DV
9413 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9414 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9415 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV
9416
9417 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9418
2d1fe073 9419 if (HAS_PCH_IBX(dev_priv)) {
d9a7bc67
ID
9420 /*
9421 * The pipe->pch transcoder and pch transcoder->pll
9422 * mapping is fixed.
9423 */
8106ddbd 9424 pll_id = (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV
9425 } else {
9426 tmp = I915_READ(PCH_DPLL_SEL);
9427 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8106ddbd 9428 pll_id = DPLL_ID_PCH_PLL_B;
c0d43d62 9429 else
8106ddbd 9430 pll_id= DPLL_ID_PCH_PLL_A;
c0d43d62 9431 }
66e985c0 9432
8106ddbd
ACO
9433 pipe_config->shared_dpll =
9434 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9435 pll = pipe_config->shared_dpll;
66e985c0 9436
2edd6443
ACO
9437 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9438 &pipe_config->dpll_hw_state));
c93f54cf
DV
9439
9440 tmp = pipe_config->dpll_hw_state.dpll;
9441 pipe_config->pixel_multiplier =
9442 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9443 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS
9444
9445 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV
9446 } else {
9447 pipe_config->pixel_multiplier = 1;
627eb5a3
DV
9448 }
9449
1bd1bd80 9450 intel_get_pipe_timings(crtc, pipe_config);
bc58be60 9451 intel_get_pipe_src_size(crtc, pipe_config);
1bd1bd80 9452
2fa2fe9a
DV
9453 ironlake_get_pfit_config(crtc, pipe_config);
9454
1729050e
ID
9455 ret = true;
9456
9457out:
9458 intel_display_power_put(dev_priv, power_domain);
9459
9460 return ret;
0e8ffe1b
DV
9461}
9462
be256dc7
PZ
9463static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9464{
9465 struct drm_device *dev = dev_priv->dev;
be256dc7 9466 struct intel_crtc *crtc;
be256dc7 9467
d3fcc808 9468 for_each_intel_crtc(dev, crtc)
e2c719b7 9469 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ
9470 pipe_name(crtc->pipe));
9471
e2c719b7
RC
9472 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9473 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
01403de3
VS
9474 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9475 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
e2c719b7
RC
9476 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9477 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9478 "CPU PWM1 enabled\n");
c5107b87 9479 if (IS_HASWELL(dev))
e2c719b7 9480 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9481 "CPU PWM2 enabled\n");
e2c719b7 9482 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9483 "PCH PWM1 enabled\n");
e2c719b7 9484 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9485 "Utility pin enabled\n");
e2c719b7 9486 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9487
9926ada1
PZ
9488 /*
9489 * In theory we can still leave IRQs enabled, as long as only the HPD
9490 * interrupts remain enabled. We used to check for that, but since it's
9491 * gen-specific and since we only disable LCPLL after we fully disable
9492 * the interrupts, the check below should be enough.
9493 */
e2c719b7 9494 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ
9495}
9496
9ccd5aeb
PZ
9497static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9498{
9499 struct drm_device *dev = dev_priv->dev;
9500
9501 if (IS_HASWELL(dev))
9502 return I915_READ(D_COMP_HSW);
9503 else
9504 return I915_READ(D_COMP_BDW);
9505}
9506
3c4c9b81
PZ
9507static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9508{
9509 struct drm_device *dev = dev_priv->dev;
9510
9511 if (IS_HASWELL(dev)) {
9512 mutex_lock(&dev_priv->rps.hw_lock);
9513 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9514 val))
f475dadf 9515 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ
9516 mutex_unlock(&dev_priv->rps.hw_lock);
9517 } else {
9ccd5aeb
PZ
9518 I915_WRITE(D_COMP_BDW, val);
9519 POSTING_READ(D_COMP_BDW);
3c4c9b81 9520 }
be256dc7
PZ
9521}
9522
9523/*
9524 * This function implements pieces of two sequences from BSpec:
9525 * - Sequence for display software to disable LCPLL
9526 * - Sequence for display software to allow package C8+
9527 * The steps implemented here are just the steps that actually touch the LCPLL
9528 * register. Callers should take care of disabling all the display engine
9529 * functions, doing the mode unset, fixing interrupts, etc.
9530 */
6ff58d53
PZ
9531static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9532 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ
9533{
9534 uint32_t val;
9535
9536 assert_can_disable_lcpll(dev_priv);
9537
9538 val = I915_READ(LCPLL_CTL);
9539
9540 if (switch_to_fclk) {
9541 val |= LCPLL_CD_SOURCE_FCLK;
9542 I915_WRITE(LCPLL_CTL, val);
9543
f53dd63f
ID
9544 if (wait_for_us(I915_READ(LCPLL_CTL) &
9545 LCPLL_CD_SOURCE_FCLK_DONE, 1))
be256dc7
PZ
9546 DRM_ERROR("Switching to FCLK failed\n");
9547
9548 val = I915_READ(LCPLL_CTL);
9549 }
9550
9551 val |= LCPLL_PLL_DISABLE;
9552 I915_WRITE(LCPLL_CTL, val);
9553 POSTING_READ(LCPLL_CTL);
9554
9555 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9556 DRM_ERROR("LCPLL still locked\n");
9557
9ccd5aeb 9558 val = hsw_read_dcomp(dev_priv);
be256dc7 9559 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9560 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ
9561 ndelay(100);
9562
9ccd5aeb
PZ
9563 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9564 1))
be256dc7
PZ
9565 DRM_ERROR("D_COMP RCOMP still in progress\n");
9566
9567 if (allow_power_down) {
9568 val = I915_READ(LCPLL_CTL);
9569 val |= LCPLL_POWER_DOWN_ALLOW;
9570 I915_WRITE(LCPLL_CTL, val);
9571 POSTING_READ(LCPLL_CTL);
9572 }
9573}
9574
9575/*
9576 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9577 * source.
9578 */
6ff58d53 9579static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ
9580{
9581 uint32_t val;
9582
9583 val = I915_READ(LCPLL_CTL);
9584
9585 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9586 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9587 return;
9588
a8a8bd54
PZ
9589 /*
9590 * Make sure we're not on PC8 state before disabling PC8, otherwise
9591 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9592 */
59bad947 9593 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9594
be256dc7
PZ
9595 if (val & LCPLL_POWER_DOWN_ALLOW) {
9596 val &= ~LCPLL_POWER_DOWN_ALLOW;
9597 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9598 POSTING_READ(LCPLL_CTL);
be256dc7
PZ
9599 }
9600
9ccd5aeb 9601 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ
9602 val |= D_COMP_COMP_FORCE;
9603 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9604 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ
9605
9606 val = I915_READ(LCPLL_CTL);
9607 val &= ~LCPLL_PLL_DISABLE;
9608 I915_WRITE(LCPLL_CTL, val);
9609
9610 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9611 DRM_ERROR("LCPLL not locked yet\n");
9612
9613 if (val & LCPLL_CD_SOURCE_FCLK) {
9614 val = I915_READ(LCPLL_CTL);
9615 val &= ~LCPLL_CD_SOURCE_FCLK;
9616 I915_WRITE(LCPLL_CTL, val);
9617
f53dd63f
ID
9618 if (wait_for_us((I915_READ(LCPLL_CTL) &
9619 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
be256dc7
PZ
9620 DRM_ERROR("Switching back to LCPLL failed\n");
9621 }
215733fa 9622
59bad947 9623 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9624 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ
9625}
9626
765dab67
PZ
9627/*
9628 * Package states C8 and deeper are really deep PC states that can only be
9629 * reached when all the devices on the system allow it, so even if the graphics
9630 * device allows PC8+, it doesn't mean the system will actually get to these
9631 * states. Our driver only allows PC8+ when going into runtime PM.
9632 *
9633 * The requirements for PC8+ are that all the outputs are disabled, the power
9634 * well is disabled and most interrupts are disabled, and these are also
9635 * requirements for runtime PM. When these conditions are met, we manually do
9636 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9637 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9638 * hang the machine.
9639 *
9640 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9641 * the state of some registers, so when we come back from PC8+ we need to
9642 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9643 * need to take care of the registers kept by RC6. Notice that this happens even
9644 * if we don't put the device in PCI D3 state (which is what currently happens
9645 * because of the runtime PM support).
9646 *
9647 * For more, read "Display Sequences for Package C8" on the hardware
9648 * documentation.
9649 */
a14cb6fc 9650void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9651{
c67a470b
PZ
9652 struct drm_device *dev = dev_priv->dev;
9653 uint32_t val;
9654
c67a470b
PZ
9655 DRM_DEBUG_KMS("Enabling package C8+\n");
9656
c2699524 9657 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ
9658 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9659 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9660 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9661 }
9662
9663 lpt_disable_clkout_dp(dev);
c67a470b
PZ
9664 hsw_disable_lcpll(dev_priv, true, true);
9665}
9666
a14cb6fc 9667void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ
9668{
9669 struct drm_device *dev = dev_priv->dev;
9670 uint32_t val;
9671
c67a470b
PZ
9672 DRM_DEBUG_KMS("Disabling package C8+\n");
9673
9674 hsw_restore_lcpll(dev_priv);
c67a470b
PZ
9675 lpt_init_pch_refclk(dev);
9676
c2699524 9677 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ
9678 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9679 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9680 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9681 }
c67a470b
PZ
9682}
9683
324513c0 9684static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9685{
a821fc46 9686 struct drm_device *dev = old_state->dev;
1a617b77
ML
9687 struct intel_atomic_state *old_intel_state =
9688 to_intel_atomic_state(old_state);
9689 unsigned int req_cdclk = old_intel_state->dev_cdclk;
f8437dd1 9690
324513c0 9691 bxt_set_cdclk(to_i915(dev), req_cdclk);
f8437dd1
VK
9692}
9693
b432e5cf 9694/* compute the max rate for new configuration */
27c329ed 9695static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9696{
565602d7
ML
9697 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9698 struct drm_i915_private *dev_priv = state->dev->dev_private;
9699 struct drm_crtc *crtc;
9700 struct drm_crtc_state *cstate;
27c329ed 9701 struct intel_crtc_state *crtc_state;
565602d7
ML
9702 unsigned max_pixel_rate = 0, i;
9703 enum pipe pipe;
b432e5cf 9704
565602d7
ML
9705 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9706 sizeof(intel_state->min_pixclk));
27c329ed 9707
565602d7
ML
9708 for_each_crtc_in_state(state, crtc, cstate, i) {
9709 int pixel_rate;
27c329ed 9710
565602d7
ML
9711 crtc_state = to_intel_crtc_state(cstate);
9712 if (!crtc_state->base.enable) {
9713 intel_state->min_pixclk[i] = 0;
b432e5cf 9714 continue;
565602d7 9715 }
b432e5cf 9716
27c329ed 9717 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS
9718
9719 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
565602d7 9720 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
b432e5cf
VS
9721 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9722
565602d7 9723 intel_state->min_pixclk[i] = pixel_rate;
b432e5cf
VS
9724 }
9725
565602d7
ML
9726 for_each_pipe(dev_priv, pipe)
9727 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9728
b432e5cf
VS
9729 return max_pixel_rate;
9730}
9731
9732static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9733{
9734 struct drm_i915_private *dev_priv = dev->dev_private;
9735 uint32_t val, data;
9736 int ret;
9737
9738 if (WARN((I915_READ(LCPLL_CTL) &
9739 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9740 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9741 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9742 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9743 "trying to change cdclk frequency with cdclk not enabled\n"))
9744 return;
9745
9746 mutex_lock(&dev_priv->rps.hw_lock);
9747 ret = sandybridge_pcode_write(dev_priv,
9748 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9749 mutex_unlock(&dev_priv->rps.hw_lock);
9750 if (ret) {
9751 DRM_ERROR("failed to inform pcode about cdclk change\n");
9752 return;
9753 }
9754
9755 val = I915_READ(LCPLL_CTL);
9756 val |= LCPLL_CD_SOURCE_FCLK;
9757 I915_WRITE(LCPLL_CTL, val);
9758
5ba00178
TU
9759 if (wait_for_us(I915_READ(LCPLL_CTL) &
9760 LCPLL_CD_SOURCE_FCLK_DONE, 1))
b432e5cf
VS
9761 DRM_ERROR("Switching to FCLK failed\n");
9762
9763 val = I915_READ(LCPLL_CTL);
9764 val &= ~LCPLL_CLK_FREQ_MASK;
9765
9766 switch (cdclk) {
9767 case 450000:
9768 val |= LCPLL_CLK_FREQ_450;
9769 data = 0;
9770 break;
9771 case 540000:
9772 val |= LCPLL_CLK_FREQ_54O_BDW;
9773 data = 1;
9774 break;
9775 case 337500:
9776 val |= LCPLL_CLK_FREQ_337_5_BDW;
9777 data = 2;
9778 break;
9779 case 675000:
9780 val |= LCPLL_CLK_FREQ_675_BDW;
9781 data = 3;
9782 break;
9783 default:
9784 WARN(1, "invalid cdclk frequency\n");
9785 return;
9786 }
9787
9788 I915_WRITE(LCPLL_CTL, val);
9789
9790 val = I915_READ(LCPLL_CTL);
9791 val &= ~LCPLL_CD_SOURCE_FCLK;
9792 I915_WRITE(LCPLL_CTL, val);
9793
5ba00178
TU
9794 if (wait_for_us((I915_READ(LCPLL_CTL) &
9795 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
b432e5cf
VS
9796 DRM_ERROR("Switching back to LCPLL failed\n");
9797
9798 mutex_lock(&dev_priv->rps.hw_lock);
9799 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9800 mutex_unlock(&dev_priv->rps.hw_lock);
9801
7f1052a8
VS
9802 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9803
b432e5cf
VS
9804 intel_update_cdclk(dev);
9805
9806 WARN(cdclk != dev_priv->cdclk_freq,
9807 "cdclk requested %d kHz but got %d kHz\n",
9808 cdclk, dev_priv->cdclk_freq);
9809}
9810
587c7914
VS
9811static int broadwell_calc_cdclk(int max_pixclk)
9812{
9813 if (max_pixclk > 540000)
9814 return 675000;
9815 else if (max_pixclk > 450000)
9816 return 540000;
9817 else if (max_pixclk > 337500)
9818 return 450000;
9819 else
9820 return 337500;
9821}
9822
27c329ed 9823static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9824{
27c329ed 9825 struct drm_i915_private *dev_priv = to_i915(state->dev);
1a617b77 9826 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
27c329ed 9827 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS
9828 int cdclk;
9829
9830 /*
9831 * FIXME should also account for plane ratio
9832 * once 64bpp pixel formats are supported.
9833 */
587c7914 9834 cdclk = broadwell_calc_cdclk(max_pixclk);
b432e5cf 9835
b432e5cf 9836 if (cdclk > dev_priv->max_cdclk_freq) {
63ba534e
ML
9837 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9838 cdclk, dev_priv->max_cdclk_freq);
9839 return -EINVAL;
b432e5cf
VS
9840 }
9841
1a617b77
ML
9842 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9843 if (!intel_state->active_crtcs)
587c7914 9844 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
b432e5cf
VS
9845
9846 return 0;
9847}
9848
27c329ed 9849static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9850{
27c329ed 9851 struct drm_device *dev = old_state->dev;
1a617b77
ML
9852 struct intel_atomic_state *old_intel_state =
9853 to_intel_atomic_state(old_state);
9854 unsigned req_cdclk = old_intel_state->dev_cdclk;
b432e5cf 9855
27c329ed 9856 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS
9857}
9858
c89e39f3
CT
9859static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9860{
9861 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9862 struct drm_i915_private *dev_priv = to_i915(state->dev);
9863 const int max_pixclk = ilk_max_pixel_rate(state);
a8ca4934 9864 int vco = intel_state->cdclk_pll_vco;
c89e39f3
CT
9865 int cdclk;
9866
9867 /*
9868 * FIXME should also account for plane ratio
9869 * once 64bpp pixel formats are supported.
9870 */
a8ca4934 9871 cdclk = skl_calc_cdclk(max_pixclk, vco);
c89e39f3
CT
9872
9873 /*
9874 * FIXME move the cdclk caclulation to
9875 * compute_config() so we can fail gracegully.
9876 */
9877 if (cdclk > dev_priv->max_cdclk_freq) {
9878 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9879 cdclk, dev_priv->max_cdclk_freq);
9880 cdclk = dev_priv->max_cdclk_freq;
9881 }
9882
9883 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9884 if (!intel_state->active_crtcs)
a8ca4934 9885 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
c89e39f3
CT
9886
9887 return 0;
9888}
9889
9890static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9891{
1cd593e0
VS
9892 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9893 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9894 unsigned int req_cdclk = intel_state->dev_cdclk;
9895 unsigned int req_vco = intel_state->cdclk_pll_vco;
c89e39f3 9896
1cd593e0 9897 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
c89e39f3
CT
9898}
9899
190f68c5
ACO
9900static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9901 struct intel_crtc_state *crtc_state)
09b4ddf9 9902{
af3997b5
MK
9903 struct intel_encoder *intel_encoder =
9904 intel_ddi_get_crtc_new_encoder(crtc_state);
9905
9906 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9907 if (!intel_ddi_pll_select(crtc, crtc_state))
9908 return -EINVAL;
9909 }
716c2e55 9910
c7653199 9911 crtc->lowfreq_avail = false;
644cef34 9912
c8f7a0db 9913 return 0;
79e53945
JB
9914}
9915
3760b59c
S
9916static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9917 enum port port,
9918 struct intel_crtc_state *pipe_config)
9919{
8106ddbd
ACO
9920 enum intel_dpll_id id;
9921
3760b59c
S
9922 switch (port) {
9923 case PORT_A:
9924 pipe_config->ddi_pll_sel = SKL_DPLL0;
08250c4b 9925 id = DPLL_ID_SKL_DPLL0;
3760b59c
S
9926 break;
9927 case PORT_B:
9928 pipe_config->ddi_pll_sel = SKL_DPLL1;
08250c4b 9929 id = DPLL_ID_SKL_DPLL1;
3760b59c
S
9930 break;
9931 case PORT_C:
9932 pipe_config->ddi_pll_sel = SKL_DPLL2;
08250c4b 9933 id = DPLL_ID_SKL_DPLL2;
3760b59c
S
9934 break;
9935 default:
9936 DRM_ERROR("Incorrect port type\n");
8106ddbd 9937 return;
3760b59c 9938 }
8106ddbd
ACO
9939
9940 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
3760b59c
S
9941}
9942
96b7dfb7
S
9943static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9944 enum port port,
5cec258b 9945 struct intel_crtc_state *pipe_config)
96b7dfb7 9946{
8106ddbd 9947 enum intel_dpll_id id;
a3c988ea 9948 u32 temp;
96b7dfb7
S
9949
9950 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9951 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9952
9953 switch (pipe_config->ddi_pll_sel) {
3148ade7 9954 case SKL_DPLL0:
a3c988ea
ACO
9955 id = DPLL_ID_SKL_DPLL0;
9956 break;
96b7dfb7 9957 case SKL_DPLL1:
8106ddbd 9958 id = DPLL_ID_SKL_DPLL1;
96b7dfb7
S
9959 break;
9960 case SKL_DPLL2:
8106ddbd 9961 id = DPLL_ID_SKL_DPLL2;
96b7dfb7
S
9962 break;
9963 case SKL_DPLL3:
8106ddbd 9964 id = DPLL_ID_SKL_DPLL3;
96b7dfb7 9965 break;
8106ddbd
ACO
9966 default:
9967 MISSING_CASE(pipe_config->ddi_pll_sel);
9968 return;
96b7dfb7 9969 }
8106ddbd
ACO
9970
9971 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
96b7dfb7
S
9972}
9973
7d2c8175
DL
9974static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9975 enum port port,
5cec258b 9976 struct intel_crtc_state *pipe_config)
7d2c8175 9977{
8106ddbd
ACO
9978 enum intel_dpll_id id;
9979
7d2c8175
DL
9980 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9981
9982 switch (pipe_config->ddi_pll_sel) {
9983 case PORT_CLK_SEL_WRPLL1:
8106ddbd 9984 id = DPLL_ID_WRPLL1;
7d2c8175
DL
9985 break;
9986 case PORT_CLK_SEL_WRPLL2:
8106ddbd 9987 id = DPLL_ID_WRPLL2;
7d2c8175 9988 break;
00490c22 9989 case PORT_CLK_SEL_SPLL:
8106ddbd 9990 id = DPLL_ID_SPLL;
79bd23da 9991 break;
9d16da65
ACO
9992 case PORT_CLK_SEL_LCPLL_810:
9993 id = DPLL_ID_LCPLL_810;
9994 break;
9995 case PORT_CLK_SEL_LCPLL_1350:
9996 id = DPLL_ID_LCPLL_1350;
9997 break;
9998 case PORT_CLK_SEL_LCPLL_2700:
9999 id = DPLL_ID_LCPLL_2700;
10000 break;
8106ddbd
ACO
10001 default:
10002 MISSING_CASE(pipe_config->ddi_pll_sel);
10003 /* fall through */
10004 case PORT_CLK_SEL_NONE:
8106ddbd 10005 return;
7d2c8175 10006 }
8106ddbd
ACO
10007
10008 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
7d2c8175
DL
10009}
10010
cf30429e
JN
10011static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10012 struct intel_crtc_state *pipe_config,
10013 unsigned long *power_domain_mask)
10014{
10015 struct drm_device *dev = crtc->base.dev;
10016 struct drm_i915_private *dev_priv = dev->dev_private;
10017 enum intel_display_power_domain power_domain;
10018 u32 tmp;
10019
d9a7bc67
ID
10020 /*
10021 * The pipe->transcoder mapping is fixed with the exception of the eDP
10022 * transcoder handled below.
10023 */
cf30429e
JN
10024 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10025
10026 /*
10027 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10028 * consistency and less surprising code; it's in always on power).
10029 */
10030 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10031 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10032 enum pipe trans_edp_pipe;
10033 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10034 default:
10035 WARN(1, "unknown pipe linked to edp transcoder\n");
10036 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10037 case TRANS_DDI_EDP_INPUT_A_ON:
10038 trans_edp_pipe = PIPE_A;
10039 break;
10040 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10041 trans_edp_pipe = PIPE_B;
10042 break;
10043 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10044 trans_edp_pipe = PIPE_C;
10045 break;
10046 }
10047
10048 if (trans_edp_pipe == crtc->pipe)
10049 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10050 }
10051
10052 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10053 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10054 return false;
10055 *power_domain_mask |= BIT(power_domain);
10056
10057 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10058
10059 return tmp & PIPECONF_ENABLE;
10060}
10061
4d1de975
JN
10062static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10063 struct intel_crtc_state *pipe_config,
10064 unsigned long *power_domain_mask)
10065{
10066 struct drm_device *dev = crtc->base.dev;
10067 struct drm_i915_private *dev_priv = dev->dev_private;
10068 enum intel_display_power_domain power_domain;
10069 enum port port;
10070 enum transcoder cpu_transcoder;
10071 u32 tmp;
10072
10073 pipe_config->has_dsi_encoder = false;
10074
10075 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10076 if (port == PORT_A)
10077 cpu_transcoder = TRANSCODER_DSI_A;
10078 else
10079 cpu_transcoder = TRANSCODER_DSI_C;
10080
10081 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10082 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10083 continue;
10084 *power_domain_mask |= BIT(power_domain);
10085
db18b6a6
ID
10086 /*
10087 * The PLL needs to be enabled with a valid divider
10088 * configuration, otherwise accessing DSI registers will hang
10089 * the machine. See BSpec North Display Engine
10090 * registers/MIPI[BXT]. We can break out here early, since we
10091 * need the same DSI PLL to be enabled for both DSI ports.
10092 */
10093 if (!intel_dsi_pll_is_enabled(dev_priv))
10094 break;
10095
4d1de975
JN
10096 /* XXX: this works for video mode only */
10097 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10098 if (!(tmp & DPI_ENABLE))
10099 continue;
10100
10101 tmp = I915_READ(MIPI_CTRL(port));
10102 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10103 continue;
10104
10105 pipe_config->cpu_transcoder = cpu_transcoder;
10106 pipe_config->has_dsi_encoder = true;
10107 break;
10108 }
10109
10110 return pipe_config->has_dsi_encoder;
10111}
10112
26804afd 10113static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 10114 struct intel_crtc_state *pipe_config)
26804afd
DV
10115{
10116 struct drm_device *dev = crtc->base.dev;
10117 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 10118 struct intel_shared_dpll *pll;
26804afd
DV
10119 enum port port;
10120 uint32_t tmp;
10121
10122 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10123
10124 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10125
ef11bdb3 10126 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
96b7dfb7 10127 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S
10128 else if (IS_BROXTON(dev))
10129 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S
10130 else
10131 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 10132
8106ddbd
ACO
10133 pll = pipe_config->shared_dpll;
10134 if (pll) {
2edd6443
ACO
10135 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10136 &pipe_config->dpll_hw_state));
d452c5b6
DV
10137 }
10138
26804afd
DV
10139 /*
10140 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10141 * DDI E. So just check whether this pipe is wired to DDI E and whether
10142 * the PCH transcoder is on.
10143 */
ca370455
DL
10144 if (INTEL_INFO(dev)->gen < 9 &&
10145 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV
10146 pipe_config->has_pch_encoder = true;
10147
10148 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10149 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10150 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10151
10152 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10153 }
10154}
10155
0e8ffe1b 10156static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 10157 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV
10158{
10159 struct drm_device *dev = crtc->base.dev;
10160 struct drm_i915_private *dev_priv = dev->dev_private;
1729050e
ID
10161 enum intel_display_power_domain power_domain;
10162 unsigned long power_domain_mask;
cf30429e 10163 bool active;
0e8ffe1b 10164
1729050e
ID
10165 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10166 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b5482bd0 10167 return false;
1729050e
ID
10168 power_domain_mask = BIT(power_domain);
10169
8106ddbd 10170 pipe_config->shared_dpll = NULL;
c0d43d62 10171
cf30429e 10172 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
eccb140b 10173
4d1de975
JN
10174 if (IS_BROXTON(dev_priv)) {
10175 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10176 &power_domain_mask);
10177 WARN_ON(active && pipe_config->has_dsi_encoder);
10178 if (pipe_config->has_dsi_encoder)
10179 active = true;
10180 }
10181
cf30429e 10182 if (!active)
1729050e 10183 goto out;
0e8ffe1b 10184
4d1de975
JN
10185 if (!pipe_config->has_dsi_encoder) {
10186 haswell_get_ddi_port_state(crtc, pipe_config);
10187 intel_get_pipe_timings(crtc, pipe_config);
10188 }
627eb5a3 10189
bc58be60 10190 intel_get_pipe_src_size(crtc, pipe_config);
1bd1bd80 10191
05dc698c
LL
10192 pipe_config->gamma_mode =
10193 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10194
a1b2278e
CK
10195 if (INTEL_INFO(dev)->gen >= 9) {
10196 skl_init_scalers(dev, crtc, pipe_config);
10197 }
10198
af99ceda
CK
10199 if (INTEL_INFO(dev)->gen >= 9) {
10200 pipe_config->scaler_state.scaler_id = -1;
10201 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10202 }
10203
1729050e
ID
10204 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10205 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10206 power_domain_mask |= BIT(power_domain);
1c132b44 10207 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 10208 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 10209 else
1c132b44 10210 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 10211 }
88adfff1 10212
e59150dc
JB
10213 if (IS_HASWELL(dev))
10214 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10215 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 10216
4d1de975
JN
10217 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10218 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
ebb69c95
CT
10219 pipe_config->pixel_multiplier =
10220 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10221 } else {
10222 pipe_config->pixel_multiplier = 1;
10223 }
6c49f241 10224
1729050e
ID
10225out:
10226 for_each_power_domain(power_domain, power_domain_mask)
10227 intel_display_power_put(dev_priv, power_domain);
10228
cf30429e 10229 return active;
0e8ffe1b
DV
10230}
10231
55a08b3f
ML
10232static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10233 const struct intel_plane_state *plane_state)
560b85bb
CW
10234{
10235 struct drm_device *dev = crtc->dev;
10236 struct drm_i915_private *dev_priv = dev->dev_private;
10237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 10238 uint32_t cntl = 0, size = 0;
560b85bb 10239
55a08b3f
ML
10240 if (plane_state && plane_state->visible) {
10241 unsigned int width = plane_state->base.crtc_w;
10242 unsigned int height = plane_state->base.crtc_h;
dc41c154
VS
10243 unsigned int stride = roundup_pow_of_two(width) * 4;
10244
10245 switch (stride) {
10246 default:
10247 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10248 width, stride);
10249 stride = 256;
10250 /* fallthrough */
10251 case 256:
10252 case 512:
10253 case 1024:
10254 case 2048:
10255 break;
4b0e333e
CW
10256 }
10257
dc41c154
VS
10258 cntl |= CURSOR_ENABLE |
10259 CURSOR_GAMMA_ENABLE |
10260 CURSOR_FORMAT_ARGB |
10261 CURSOR_STRIDE(stride);
10262
10263 size = (height << 12) | width;
4b0e333e 10264 }
560b85bb 10265
dc41c154
VS
10266 if (intel_crtc->cursor_cntl != 0 &&
10267 (intel_crtc->cursor_base != base ||
10268 intel_crtc->cursor_size != size ||
10269 intel_crtc->cursor_cntl != cntl)) {
10270 /* On these chipsets we can only modify the base/size/stride
10271 * whilst the cursor is disabled.
10272 */
0b87c24e
VS
10273 I915_WRITE(CURCNTR(PIPE_A), 0);
10274 POSTING_READ(CURCNTR(PIPE_A));
dc41c154 10275 intel_crtc->cursor_cntl = 0;
4b0e333e 10276 }
560b85bb 10277
99d1f387 10278 if (intel_crtc->cursor_base != base) {
0b87c24e 10279 I915_WRITE(CURBASE(PIPE_A), base);
99d1f387
VS
10280 intel_crtc->cursor_base = base;
10281 }
4726e0b0 10282
dc41c154
VS
10283 if (intel_crtc->cursor_size != size) {
10284 I915_WRITE(CURSIZE, size);
10285 intel_crtc->cursor_size = size;
4b0e333e 10286 }
560b85bb 10287
4b0e333e 10288 if (intel_crtc->cursor_cntl != cntl) {
0b87c24e
VS
10289 I915_WRITE(CURCNTR(PIPE_A), cntl);
10290 POSTING_READ(CURCNTR(PIPE_A));
4b0e333e 10291 intel_crtc->cursor_cntl = cntl;
560b85bb 10292 }
560b85bb
CW
10293}
10294
55a08b3f
ML
10295static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10296 const struct intel_plane_state *plane_state)
65a21cd6
JB
10297{
10298 struct drm_device *dev = crtc->dev;
10299 struct drm_i915_private *dev_priv = dev->dev_private;
10300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10301 int pipe = intel_crtc->pipe;
663f3122 10302 uint32_t cntl = 0;
4b0e333e 10303
55a08b3f 10304 if (plane_state && plane_state->visible) {
4b0e333e 10305 cntl = MCURSOR_GAMMA_ENABLE;
55a08b3f 10306 switch (plane_state->base.crtc_w) {
4726e0b0
SK
10307 case 64:
10308 cntl |= CURSOR_MODE_64_ARGB_AX;
10309 break;
10310 case 128:
10311 cntl |= CURSOR_MODE_128_ARGB_AX;
10312 break;
10313 case 256:
10314 cntl |= CURSOR_MODE_256_ARGB_AX;
10315 break;
10316 default:
55a08b3f 10317 MISSING_CASE(plane_state->base.crtc_w);
4726e0b0 10318 return;
65a21cd6 10319 }
4b0e333e 10320 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7 10321
fc6f93bc 10322 if (HAS_DDI(dev))
47bf17a7 10323 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6 10324
55a08b3f
ML
10325 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10326 cntl |= CURSOR_ROTATE_180;
10327 }
4398ad45 10328
4b0e333e
CW
10329 if (intel_crtc->cursor_cntl != cntl) {
10330 I915_WRITE(CURCNTR(pipe), cntl);
10331 POSTING_READ(CURCNTR(pipe));
10332 intel_crtc->cursor_cntl = cntl;
65a21cd6 10333 }
4b0e333e 10334
65a21cd6 10335 /* and commit changes on next vblank */
5efb3e28
VS
10336 I915_WRITE(CURBASE(pipe), base);
10337 POSTING_READ(CURBASE(pipe));
99d1f387
VS
10338
10339 intel_crtc->cursor_base = base;
65a21cd6
JB
10340}
10341
cda4b7d3 10342/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f 10343static void intel_crtc_update_cursor(struct drm_crtc *crtc,
55a08b3f 10344 const struct intel_plane_state *plane_state)
cda4b7d3
CW
10345{
10346 struct drm_device *dev = crtc->dev;
10347 struct drm_i915_private *dev_priv = dev->dev_private;
10348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10349 int pipe = intel_crtc->pipe;
55a08b3f
ML
10350 u32 base = intel_crtc->cursor_addr;
10351 u32 pos = 0;
cda4b7d3 10352
55a08b3f
ML
10353 if (plane_state) {
10354 int x = plane_state->base.crtc_x;
10355 int y = plane_state->base.crtc_y;
cda4b7d3 10356
55a08b3f
ML
10357 if (x < 0) {
10358 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10359 x = -x;
10360 }
10361 pos |= x << CURSOR_X_SHIFT;
cda4b7d3 10362
55a08b3f
ML
10363 if (y < 0) {
10364 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10365 y = -y;
10366 }
10367 pos |= y << CURSOR_Y_SHIFT;
10368
10369 /* ILK+ do this automagically */
10370 if (HAS_GMCH_DISPLAY(dev) &&
10371 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10372 base += (plane_state->base.crtc_h *
10373 plane_state->base.crtc_w - 1) * 4;
10374 }
cda4b7d3 10375 }
cda4b7d3 10376
5efb3e28
VS
10377 I915_WRITE(CURPOS(pipe), pos);
10378
8ac54669 10379 if (IS_845G(dev) || IS_I865G(dev))
55a08b3f 10380 i845_update_cursor(crtc, base, plane_state);
5efb3e28 10381 else
55a08b3f 10382 i9xx_update_cursor(crtc, base, plane_state);
cda4b7d3
CW
10383}
10384
dc41c154
VS
10385static bool cursor_size_ok(struct drm_device *dev,
10386 uint32_t width, uint32_t height)
10387{
10388 if (width == 0 || height == 0)
10389 return false;
10390
10391 /*
10392 * 845g/865g are special in that they are only limited by
10393 * the width of their cursors, the height is arbitrary up to
10394 * the precision of the register. Everything else requires
10395 * square cursors, limited to a few power-of-two sizes.
10396 */
10397 if (IS_845G(dev) || IS_I865G(dev)) {
10398 if ((width & 63) != 0)
10399 return false;
10400
10401 if (width > (IS_845G(dev) ? 64 : 512))
10402 return false;
10403
10404 if (height > 1023)
10405 return false;
10406 } else {
10407 switch (width | height) {
10408 case 256:
10409 case 128:
10410 if (IS_GEN2(dev))
10411 return false;
10412 case 64:
10413 break;
10414 default:
10415 return false;
10416 }
10417 }
10418
10419 return true;
10420}
10421
79e53945
JB
10422/* VESA 640x480x72Hz mode to set on the pipe */
10423static struct drm_display_mode load_detect_mode = {
10424 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10425 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10426};
10427
a8bb6818
DV
10428struct drm_framebuffer *
10429__intel_framebuffer_create(struct drm_device *dev,
10430 struct drm_mode_fb_cmd2 *mode_cmd,
10431 struct drm_i915_gem_object *obj)
d2dff872
CW
10432{
10433 struct intel_framebuffer *intel_fb;
10434 int ret;
10435
10436 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
dcb1394e 10437 if (!intel_fb)
d2dff872 10438 return ERR_PTR(-ENOMEM);
d2dff872
CW
10439
10440 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV
10441 if (ret)
10442 goto err;
d2dff872
CW
10443
10444 return &intel_fb->base;
dcb1394e 10445
dd4916c5 10446err:
dd4916c5 10447 kfree(intel_fb);
dd4916c5 10448 return ERR_PTR(ret);
d2dff872
CW
10449}
10450
b5ea642a 10451static struct drm_framebuffer *
a8bb6818
DV
10452intel_framebuffer_create(struct drm_device *dev,
10453 struct drm_mode_fb_cmd2 *mode_cmd,
10454 struct drm_i915_gem_object *obj)
10455{
10456 struct drm_framebuffer *fb;
10457 int ret;
10458
10459 ret = i915_mutex_lock_interruptible(dev);
10460 if (ret)
10461 return ERR_PTR(ret);
10462 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10463 mutex_unlock(&dev->struct_mutex);
10464
10465 return fb;
10466}
10467
d2dff872
CW
10468static u32
10469intel_framebuffer_pitch_for_width(int width, int bpp)
10470{
10471 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10472 return ALIGN(pitch, 64);
10473}
10474
10475static u32
10476intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10477{
10478 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10479 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW
10480}
10481
10482static struct drm_framebuffer *
10483intel_framebuffer_create_for_mode(struct drm_device *dev,
10484 struct drm_display_mode *mode,
10485 int depth, int bpp)
10486{
dcb1394e 10487 struct drm_framebuffer *fb;
d2dff872 10488 struct drm_i915_gem_object *obj;
0fed39bd 10489 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872 10490
d37cd8a8 10491 obj = i915_gem_object_create(dev,
d2dff872 10492 intel_framebuffer_size_for_mode(mode, bpp));
fe3db79b
CW
10493 if (IS_ERR(obj))
10494 return ERR_CAST(obj);
d2dff872
CW
10495
10496 mode_cmd.width = mode->hdisplay;
10497 mode_cmd.height = mode->vdisplay;
308e5bcb
JB
10498 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10499 bpp);
5ca0c34a 10500 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872 10501
dcb1394e
LW
10502 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10503 if (IS_ERR(fb))
10504 drm_gem_object_unreference_unlocked(&obj->base);
10505
10506 return fb;
d2dff872
CW
10507}
10508
10509static struct drm_framebuffer *
10510mode_fits_in_fbdev(struct drm_device *dev,
10511 struct drm_display_mode *mode)
10512{
0695726e 10513#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW
10514 struct drm_i915_private *dev_priv = dev->dev_private;
10515 struct drm_i915_gem_object *obj;
10516 struct drm_framebuffer *fb;
10517
4c0e5528 10518 if (!dev_priv->fbdev)
d2dff872
CW
10519 return NULL;
10520
4c0e5528 10521 if (!dev_priv->fbdev->fb)
d2dff872
CW
10522 return NULL;
10523
4c0e5528
DV
10524 obj = dev_priv->fbdev->fb->obj;
10525 BUG_ON(!obj);
10526
8bcd4553 10527 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS
10528 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10529 fb->bits_per_pixel))
d2dff872
CW
10530 return NULL;
10531
01f2c773 10532 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW
10533 return NULL;
10534
edde3617 10535 drm_framebuffer_reference(fb);
d2dff872 10536 return fb;
4520f53a
DV
10537#else
10538 return NULL;
10539#endif
d2dff872
CW
10540}
10541
d3a40d1b
ACO
10542static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10543 struct drm_crtc *crtc,
10544 struct drm_display_mode *mode,
10545 struct drm_framebuffer *fb,
10546 int x, int y)
10547{
10548 struct drm_plane_state *plane_state;
10549 int hdisplay, vdisplay;
10550 int ret;
10551
10552 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10553 if (IS_ERR(plane_state))
10554 return PTR_ERR(plane_state);
10555
10556 if (mode)
10557 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10558 else
10559 hdisplay = vdisplay = 0;
10560
10561 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10562 if (ret)
10563 return ret;
10564 drm_atomic_set_fb_for_plane(plane_state, fb);
10565 plane_state->crtc_x = 0;
10566 plane_state->crtc_y = 0;
10567 plane_state->crtc_w = hdisplay;
10568 plane_state->crtc_h = vdisplay;
10569 plane_state->src_x = x << 16;
10570 plane_state->src_y = y << 16;
10571 plane_state->src_w = hdisplay << 16;
10572 plane_state->src_h = vdisplay << 16;
10573
10574 return 0;
10575}
10576
d2434ab7 10577bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10578 struct drm_display_mode *mode,
51fd371b
RC
10579 struct intel_load_detect_pipe *old,
10580 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB
10581{
10582 struct intel_crtc *intel_crtc;
d2434ab7
DV
10583 struct intel_encoder *intel_encoder =
10584 intel_attached_encoder(connector);
79e53945 10585 struct drm_crtc *possible_crtc;
4ef69c7a 10586 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB
10587 struct drm_crtc *crtc = NULL;
10588 struct drm_device *dev = encoder->dev;
94352cf9 10589 struct drm_framebuffer *fb;
51fd371b 10590 struct drm_mode_config *config = &dev->mode_config;
edde3617 10591 struct drm_atomic_state *state = NULL, *restore_state = NULL;
944b0c76 10592 struct drm_connector_state *connector_state;
4be07317 10593 struct intel_crtc_state *crtc_state;
51fd371b 10594 int ret, i = -1;
79e53945 10595
d2dff872 10596 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10597 connector->base.id, connector->name,
8e329a03 10598 encoder->base.id, encoder->name);
d2dff872 10599
edde3617
ML
10600 old->restore_state = NULL;
10601
51fd371b
RC
10602retry:
10603 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10604 if (ret)
ad3c558f 10605 goto fail;
6e9f798d 10606
79e53945
JB
10607 /*
10608 * Algorithm gets a little messy:
7a5e4805 10609 *
79e53945
JB
10610 * - if the connector already has an assigned crtc, use it (but make
10611 * sure it's on first)
7a5e4805 10612 *
79e53945
JB
10613 * - try to find the first unused crtc that can drive this connector,
10614 * and use that if we find one
79e53945
JB
10615 */
10616
10617 /* See if we already have a CRTC for this connector */
edde3617
ML
10618 if (connector->state->crtc) {
10619 crtc = connector->state->crtc;
8261b191 10620
51fd371b 10621 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10622 if (ret)
ad3c558f 10623 goto fail;
8261b191
CW
10624
10625 /* Make sure the crtc and connector are running */
edde3617 10626 goto found;
79e53945
JB
10627 }
10628
10629 /* Find an unused one (if possible) */
70e1e0ec 10630 for_each_crtc(dev, possible_crtc) {
79e53945
JB
10631 i++;
10632 if (!(encoder->possible_crtcs & (1 << i)))
10633 continue;
edde3617
ML
10634
10635 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10636 if (ret)
10637 goto fail;
10638
10639 if (possible_crtc->state->enable) {
10640 drm_modeset_unlock(&possible_crtc->mutex);
a459249c 10641 continue;
edde3617 10642 }
a459249c
VS
10643
10644 crtc = possible_crtc;
10645 break;
79e53945
JB
10646 }
10647
10648 /*
10649 * If we didn't find an unused CRTC, don't use any.
10650 */
10651 if (!crtc) {
7173188d 10652 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10653 goto fail;
79e53945
JB
10654 }
10655
edde3617
ML
10656found:
10657 intel_crtc = to_intel_crtc(crtc);
10658
4d02e2de
DV
10659 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10660 if (ret)
ad3c558f 10661 goto fail;
79e53945 10662
83a57153 10663 state = drm_atomic_state_alloc(dev);
edde3617
ML
10664 restore_state = drm_atomic_state_alloc(dev);
10665 if (!state || !restore_state) {
10666 ret = -ENOMEM;
10667 goto fail;
10668 }
83a57153
ACO
10669
10670 state->acquire_ctx = ctx;
edde3617 10671 restore_state->acquire_ctx = ctx;
83a57153 10672
944b0c76
ACO
10673 connector_state = drm_atomic_get_connector_state(state, connector);
10674 if (IS_ERR(connector_state)) {
10675 ret = PTR_ERR(connector_state);
10676 goto fail;
10677 }
10678
edde3617
ML
10679 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10680 if (ret)
10681 goto fail;
944b0c76 10682
4be07317
ACO
10683 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10684 if (IS_ERR(crtc_state)) {
10685 ret = PTR_ERR(crtc_state);
10686 goto fail;
10687 }
10688
49d6fa21 10689 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10690
6492711d
CW
10691 if (!mode)
10692 mode = &load_detect_mode;
79e53945 10693
d2dff872
CW
10694 /* We need a framebuffer large enough to accommodate all accesses
10695 * that the plane may generate whilst we perform load detection.
10696 * We can not rely on the fbcon either being present (we get called
10697 * during its initialisation to detect all boot displays, or it may
10698 * not even exist) or that it is large enough to satisfy the
10699 * requested mode.
10700 */
94352cf9
DV
10701 fb = mode_fits_in_fbdev(dev, mode);
10702 if (fb == NULL) {
d2dff872 10703 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9 10704 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
d2dff872
CW
10705 } else
10706 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10707 if (IS_ERR(fb)) {
d2dff872 10708 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10709 goto fail;
79e53945 10710 }
79e53945 10711
d3a40d1b
ACO
10712 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10713 if (ret)
10714 goto fail;
10715
edde3617
ML
10716 drm_framebuffer_unreference(fb);
10717
10718 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10719 if (ret)
10720 goto fail;
10721
10722 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10723 if (!ret)
10724 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10725 if (!ret)
10726 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10727 if (ret) {
10728 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10729 goto fail;
10730 }
8c7b5ccb 10731
3ba86073
ML
10732 ret = drm_atomic_commit(state);
10733 if (ret) {
6492711d 10734 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
412b61d8 10735 goto fail;
79e53945 10736 }
edde3617
ML
10737
10738 old->restore_state = restore_state;
7173188d 10739
79e53945 10740 /* let the connector get through one full cycle before testing */
9d0498a2 10741 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10742 return true;
412b61d8 10743
ad3c558f 10744fail:
e5d958ef 10745 drm_atomic_state_free(state);
edde3617
ML
10746 drm_atomic_state_free(restore_state);
10747 restore_state = state = NULL;
83a57153 10748
51fd371b
RC
10749 if (ret == -EDEADLK) {
10750 drm_modeset_backoff(ctx);
10751 goto retry;
10752 }
10753
412b61d8 10754 return false;
79e53945
JB
10755}
10756
d2434ab7 10757void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO
10758 struct intel_load_detect_pipe *old,
10759 struct drm_modeset_acquire_ctx *ctx)
79e53945 10760{
d2434ab7
DV
10761 struct intel_encoder *intel_encoder =
10762 intel_attached_encoder(connector);
4ef69c7a 10763 struct drm_encoder *encoder = &intel_encoder->base;
edde3617 10764 struct drm_atomic_state *state = old->restore_state;
d3a40d1b 10765 int ret;
79e53945 10766
d2dff872 10767 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10768 connector->base.id, connector->name,
8e329a03 10769 encoder->base.id, encoder->name);
d2dff872 10770
edde3617 10771 if (!state)
0622a53c 10772 return;
79e53945 10773
edde3617
ML
10774 ret = drm_atomic_commit(state);
10775 if (ret) {
10776 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10777 drm_atomic_state_free(state);
10778 }
79e53945
JB
10779}
10780
da4a1efa 10781static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10782 const struct intel_crtc_state *pipe_config)
da4a1efa
VS
10783{
10784 struct drm_i915_private *dev_priv = dev->dev_private;
10785 u32 dpll = pipe_config->dpll_hw_state.dpll;
10786
10787 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10788 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS
10789 else if (HAS_PCH_SPLIT(dev))
10790 return 120000;
10791 else if (!IS_GEN2(dev))
10792 return 96000;
10793 else
10794 return 48000;
10795}
10796
79e53945 10797/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10798static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10799 struct intel_crtc_state *pipe_config)
79e53945 10800{
f1f644dc 10801 struct drm_device *dev = crtc->base.dev;
79e53945 10802 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10803 int pipe = pipe_config->cpu_transcoder;
293623f7 10804 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945 10805 u32 fp;
9e2c8475 10806 struct dpll clock;
dccbea3b 10807 int port_clock;
da4a1efa 10808 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB
10809
10810 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10811 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10812 else
293623f7 10813 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB
10814
10815 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ
10816 if (IS_PINEVIEW(dev)) {
10817 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10818 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL
10819 } else {
10820 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10821 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10822 }
10823
a6c45cf0 10824 if (!IS_GEN2(dev)) {
f2b115e6
AJ
10825 if (IS_PINEVIEW(dev))
10826 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10827 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL
10828 else
10829 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB
10830 DPLL_FPA01_P1_POST_DIV_SHIFT);
10831
10832 switch (dpll & DPLL_MODE_MASK) {
10833 case DPLLB_MODE_DAC_SERIAL:
10834 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10835 5 : 10;
10836 break;
10837 case DPLLB_MODE_LVDS:
10838 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10839 7 : 14;
10840 break;
10841 default:
28c97730 10842 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10843 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10844 return;
79e53945
JB
10845 }
10846
ac58c3f0 10847 if (IS_PINEVIEW(dev))
dccbea3b 10848 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10849 else
dccbea3b 10850 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10851 } else {
0fb58223 10852 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10853 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB
10854
10855 if (is_lvds) {
10856 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10857 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS
10858
10859 if (lvds & LVDS_CLKB_POWER_UP)
10860 clock.p2 = 7;
10861 else
10862 clock.p2 = 14;
79e53945
JB
10863 } else {
10864 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10865 clock.p1 = 2;
10866 else {
10867 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10868 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10869 }
10870 if (dpll & PLL_P2_DIVIDE_BY_4)
10871 clock.p2 = 4;
10872 else
10873 clock.p2 = 2;
79e53945 10874 }
da4a1efa 10875
dccbea3b 10876 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB
10877 }
10878
18442d08
VS
10879 /*
10880 * This value includes pixel_multiplier. We will use
241bfc38 10881 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS
10882 * encoder's get_config() function.
10883 */
dccbea3b 10884 pipe_config->port_clock = port_clock;
f1f644dc
JB
10885}
10886
6878da05
VS
10887int intel_dotclock_calculate(int link_freq,
10888 const struct intel_link_m_n *m_n)
f1f644dc 10889{
f1f644dc
JB
10890 /*
10891 * The calculation for the data clock is:
1041a02f 10892 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10893 * But we want to avoid losing precison if possible, so:
1041a02f 10894 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB
10895 *
10896 * and the link clock is simpler:
1041a02f 10897 * link_clock = (m * link_clock) / n
f1f644dc
JB
10898 */
10899
6878da05
VS
10900 if (!m_n->link_n)
10901 return 0;
f1f644dc 10902
6878da05
VS
10903 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10904}
f1f644dc 10905
18442d08 10906static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10907 struct intel_crtc_state *pipe_config)
6878da05 10908{
e3b247da 10909 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
79e53945 10910
18442d08
VS
10911 /* read out port_clock from the DPLL */
10912 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10913
f1f644dc 10914 /*
e3b247da
VS
10915 * In case there is an active pipe without active ports,
10916 * we may need some idea for the dotclock anyway.
10917 * Calculate one based on the FDI configuration.
79e53945 10918 */
2d112de7 10919 pipe_config->base.adjusted_mode.crtc_clock =
21a727b3 10920 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
18442d08 10921 &pipe_config->fdi_m_n);
79e53945
JB
10922}
10923
10924/** Returns the currently programmed mode of the given pipe. */
10925struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10926 struct drm_crtc *crtc)
10927{
548f245b 10928 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10930 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10931 struct drm_display_mode *mode;
3f36b937 10932 struct intel_crtc_state *pipe_config;
fe2b8f9d
PZ
10933 int htot = I915_READ(HTOTAL(cpu_transcoder));
10934 int hsync = I915_READ(HSYNC(cpu_transcoder));
10935 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10936 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10937 enum pipe pipe = intel_crtc->pipe;
79e53945
JB
10938
10939 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10940 if (!mode)
10941 return NULL;
10942
3f36b937
TU
10943 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10944 if (!pipe_config) {
10945 kfree(mode);
10946 return NULL;
10947 }
10948
f1f644dc
JB
10949 /*
10950 * Construct a pipe_config sufficient for getting the clock info
10951 * back out of crtc_clock_get.
10952 *
10953 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10954 * to use a real value here instead.
10955 */
3f36b937
TU
10956 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10957 pipe_config->pixel_multiplier = 1;
10958 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10959 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10960 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10961 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10962
10963 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
79e53945
JB
10964 mode->hdisplay = (htot & 0xffff) + 1;
10965 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10966 mode->hsync_start = (hsync & 0xffff) + 1;
10967 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10968 mode->vdisplay = (vtot & 0xffff) + 1;
10969 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10970 mode->vsync_start = (vsync & 0xffff) + 1;
10971 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10972
10973 drm_mode_set_name(mode);
79e53945 10974
3f36b937
TU
10975 kfree(pipe_config);
10976
79e53945
JB
10977 return mode;
10978}
10979
7d993739 10980void intel_mark_busy(struct drm_i915_private *dev_priv)
f047e395 10981{
f62a0076
CW
10982 if (dev_priv->mm.busy)
10983 return;
10984
43694d69 10985 intel_runtime_pm_get(dev_priv);
c67a470b 10986 i915_update_gfx_val(dev_priv);
7d993739 10987 if (INTEL_GEN(dev_priv) >= 6)
43cf3bf0 10988 gen6_rps_busy(dev_priv);
f62a0076 10989 dev_priv->mm.busy = true;
f047e395
CW
10990}
10991
7d993739 10992void intel_mark_idle(struct drm_i915_private *dev_priv)
652c393a 10993{
f62a0076
CW
10994 if (!dev_priv->mm.busy)
10995 return;
10996
10997 dev_priv->mm.busy = false;
10998
7d993739
TU
10999 if (INTEL_GEN(dev_priv) >= 6)
11000 gen6_rps_idle(dev_priv);
bb4cdd53 11001
43694d69 11002 intel_runtime_pm_put(dev_priv);
652c393a
JB
11003}
11004
79e53945
JB
11005static void intel_crtc_destroy(struct drm_crtc *crtc)
11006{
11007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a 11008 struct drm_device *dev = crtc->dev;
51cbaf01 11009 struct intel_flip_work *work;
67e77c5a 11010
5e2d7afc 11011 spin_lock_irq(&dev->event_lock);
5a21b665
DV
11012 work = intel_crtc->flip_work;
11013 intel_crtc->flip_work = NULL;
11014 spin_unlock_irq(&dev->event_lock);
67e77c5a 11015
5a21b665 11016 if (work) {
51cbaf01
ML
11017 cancel_work_sync(&work->mmio_work);
11018 cancel_work_sync(&work->unpin_work);
5a21b665 11019 kfree(work);
67e77c5a 11020 }
79e53945
JB
11021
11022 drm_crtc_cleanup(crtc);
67e77c5a 11023
79e53945
JB
11024 kfree(intel_crtc);
11025}
11026
6b95a207
KH
11027static void intel_unpin_work_fn(struct work_struct *__work)
11028{
51cbaf01
ML
11029 struct intel_flip_work *work =
11030 container_of(__work, struct intel_flip_work, unpin_work);
5a21b665
DV
11031 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11032 struct drm_device *dev = crtc->base.dev;
11033 struct drm_plane *primary = crtc->base.primary;
03f476e1 11034
5a21b665
DV
11035 if (is_mmio_work(work))
11036 flush_work(&work->mmio_work);
03f476e1 11037
5a21b665
DV
11038 mutex_lock(&dev->struct_mutex);
11039 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11040 drm_gem_object_unreference(&work->pending_flip_obj->base);
143f73b3 11041
5a21b665
DV
11042 if (work->flip_queued_req)
11043 i915_gem_request_assign(&work->flip_queued_req, NULL);
11044 mutex_unlock(&dev->struct_mutex);
143f73b3 11045
5a21b665
DV
11046 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
11047 intel_fbc_post_update(crtc);
11048 drm_framebuffer_unreference(work->old_fb);
143f73b3 11049
5a21b665
DV
11050 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11051 atomic_dec(&crtc->unpin_work_count);
a6747b73 11052
5a21b665
DV
11053 kfree(work);
11054}
d9e86c0e 11055
5a21b665
DV
11056/* Is 'a' after or equal to 'b'? */
11057static bool g4x_flip_count_after_eq(u32 a, u32 b)
11058{
11059 return !((a - b) & 0x80000000);
11060}
143f73b3 11061
5a21b665
DV
11062static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11063 struct intel_flip_work *work)
11064{
11065 struct drm_device *dev = crtc->base.dev;
11066 struct drm_i915_private *dev_priv = dev->dev_private;
11067 unsigned reset_counter;
143f73b3 11068
5a21b665
DV
11069 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11070 if (crtc->reset_counter != reset_counter)
11071 return true;
143f73b3 11072
5a21b665
DV
11073 /*
11074 * The relevant registers doen't exist on pre-ctg.
11075 * As the flip done interrupt doesn't trigger for mmio
11076 * flips on gmch platforms, a flip count check isn't
11077 * really needed there. But since ctg has the registers,
11078 * include it in the check anyway.
11079 */
11080 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11081 return true;
b4a98e57 11082
5a21b665
DV
11083 /*
11084 * BDW signals flip done immediately if the plane
11085 * is disabled, even if the plane enable is already
11086 * armed to occur at the next vblank :(
11087 */
f99d7069 11088
5a21b665
DV
11089 /*
11090 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11091 * used the same base address. In that case the mmio flip might
11092 * have completed, but the CS hasn't even executed the flip yet.
11093 *
11094 * A flip count check isn't enough as the CS might have updated
11095 * the base address just after start of vblank, but before we
11096 * managed to process the interrupt. This means we'd complete the
11097 * CS flip too soon.
11098 *
11099 * Combining both checks should get us a good enough result. It may
11100 * still happen that the CS flip has been executed, but has not
11101 * yet actually completed. But in case the base address is the same
11102 * anyway, we don't really care.
11103 */
11104 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11105 crtc->flip_work->gtt_offset &&
11106 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11107 crtc->flip_work->flip_count);
11108}
b4a98e57 11109
5a21b665
DV
11110static bool
11111__pageflip_finished_mmio(struct intel_crtc *crtc,
11112 struct intel_flip_work *work)
11113{
11114 /*
11115 * MMIO work completes when vblank is different from
11116 * flip_queued_vblank.
11117 *
11118 * Reset counter value doesn't matter, this is handled by
11119 * i915_wait_request finishing early, so no need to handle
11120 * reset here.
11121 */
11122 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
6b95a207
KH
11123}
11124
51cbaf01
ML
11125
11126static bool pageflip_finished(struct intel_crtc *crtc,
11127 struct intel_flip_work *work)
11128{
11129 if (!atomic_read(&work->pending))
11130 return false;
11131
11132 smp_rmb();
11133
5a21b665
DV
11134 if (is_mmio_work(work))
11135 return __pageflip_finished_mmio(crtc, work);
11136 else
11137 return __pageflip_finished_cs(crtc, work);
11138}
11139
11140void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11141{
11142 struct drm_device *dev = dev_priv->dev;
11143 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11145 struct intel_flip_work *work;
11146 unsigned long flags;
11147
11148 /* Ignore early vblank irqs */
11149 if (!crtc)
11150 return;
11151
51cbaf01 11152 /*
5a21b665
DV
11153 * This is called both by irq handlers and the reset code (to complete
11154 * lost pageflips) so needs the full irqsave spinlocks.
51cbaf01 11155 */
5a21b665
DV
11156 spin_lock_irqsave(&dev->event_lock, flags);
11157 work = intel_crtc->flip_work;
11158
11159 if (work != NULL &&
11160 !is_mmio_work(work) &&
11161 pageflip_finished(intel_crtc, work))
11162 page_flip_completed(intel_crtc);
11163
11164 spin_unlock_irqrestore(&dev->event_lock, flags);
75f7f3ec
VS
11165}
11166
51cbaf01 11167void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
6b95a207 11168{
91d14251 11169 struct drm_device *dev = dev_priv->dev;
5251f04e
ML
11170 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
51cbaf01 11172 struct intel_flip_work *work;
6b95a207
KH
11173 unsigned long flags;
11174
5251f04e
ML
11175 /* Ignore early vblank irqs */
11176 if (!crtc)
11177 return;
f326038a
DV
11178
11179 /*
11180 * This is called both by irq handlers and the reset code (to complete
11181 * lost pageflips) so needs the full irqsave spinlocks.
e7d841ca 11182 */
6b95a207 11183 spin_lock_irqsave(&dev->event_lock, flags);
5a21b665 11184 work = intel_crtc->flip_work;
5251f04e 11185
5a21b665
DV
11186 if (work != NULL &&
11187 is_mmio_work(work) &&
11188 pageflip_finished(intel_crtc, work))
11189 page_flip_completed(intel_crtc);
5251f04e 11190
6b95a207
KH
11191 spin_unlock_irqrestore(&dev->event_lock, flags);
11192}
11193
5a21b665
DV
11194static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11195 struct intel_flip_work *work)
84c33a64 11196{
5a21b665 11197 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
84c33a64 11198
5a21b665
DV
11199 /* Ensure that the work item is consistent when activating it ... */
11200 smp_mb__before_atomic();
11201 atomic_set(&work->pending, 1);
11202}
a6747b73 11203
5a21b665
DV
11204static int intel_gen2_queue_flip(struct drm_device *dev,
11205 struct drm_crtc *crtc,
11206 struct drm_framebuffer *fb,
11207 struct drm_i915_gem_object *obj,
11208 struct drm_i915_gem_request *req,
11209 uint32_t flags)
11210{
11211 struct intel_engine_cs *engine = req->engine;
11212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11213 u32 flip_mask;
11214 int ret;
143f73b3 11215
5a21b665
DV
11216 ret = intel_ring_begin(req, 6);
11217 if (ret)
11218 return ret;
143f73b3 11219
5a21b665
DV
11220 /* Can't queue multiple flips, so wait for the previous
11221 * one to finish before executing the next.
11222 */
11223 if (intel_crtc->plane)
11224 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11225 else
11226 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11227 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11228 intel_ring_emit(engine, MI_NOOP);
11229 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11230 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11231 intel_ring_emit(engine, fb->pitches[0]);
11232 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11233 intel_ring_emit(engine, 0); /* aux display base address, unused */
143f73b3 11234
5a21b665
DV
11235 return 0;
11236}
84c33a64 11237
5a21b665
DV
11238static int intel_gen3_queue_flip(struct drm_device *dev,
11239 struct drm_crtc *crtc,
11240 struct drm_framebuffer *fb,
11241 struct drm_i915_gem_object *obj,
11242 struct drm_i915_gem_request *req,
11243 uint32_t flags)
11244{
11245 struct intel_engine_cs *engine = req->engine;
11246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11247 u32 flip_mask;
11248 int ret;
d55dbd06 11249
5a21b665
DV
11250 ret = intel_ring_begin(req, 6);
11251 if (ret)
11252 return ret;
d55dbd06 11253
5a21b665
DV
11254 if (intel_crtc->plane)
11255 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11256 else
11257 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11258 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11259 intel_ring_emit(engine, MI_NOOP);
11260 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11261 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11262 intel_ring_emit(engine, fb->pitches[0]);
11263 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11264 intel_ring_emit(engine, MI_NOOP);
fd8e058a 11265
5a21b665
DV
11266 return 0;
11267}
84c33a64 11268
5a21b665
DV
11269static int intel_gen4_queue_flip(struct drm_device *dev,
11270 struct drm_crtc *crtc,
11271 struct drm_framebuffer *fb,
11272 struct drm_i915_gem_object *obj,
11273 struct drm_i915_gem_request *req,
11274 uint32_t flags)
11275{
11276 struct intel_engine_cs *engine = req->engine;
11277 struct drm_i915_private *dev_priv = dev->dev_private;
11278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11279 uint32_t pf, pipesrc;
11280 int ret;
143f73b3 11281
5a21b665
DV
11282 ret = intel_ring_begin(req, 4);
11283 if (ret)
11284 return ret;
143f73b3 11285
5a21b665
DV
11286 /* i965+ uses the linear or tiled offsets from the
11287 * Display Registers (which do not change across a page-flip)
11288 * so we need only reprogram the base address.
11289 */
11290 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11291 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11292 intel_ring_emit(engine, fb->pitches[0]);
11293 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |
11294 obj->tiling_mode);
11295
11296 /* XXX Enabling the panel-fitter across page-flip is so far
11297 * untested on non-native modes, so ignore it for now.
11298 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11299 */
11300 pf = 0;
11301 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11302 intel_ring_emit(engine, pf | pipesrc);
143f73b3 11303
5a21b665 11304 return 0;
8c9f3aaf
JB
11305}
11306
5a21b665
DV
11307static int intel_gen6_queue_flip(struct drm_device *dev,
11308 struct drm_crtc *crtc,
11309 struct drm_framebuffer *fb,
11310 struct drm_i915_gem_object *obj,
11311 struct drm_i915_gem_request *req,
11312 uint32_t flags)
da20eabd 11313{
5a21b665
DV
11314 struct intel_engine_cs *engine = req->engine;
11315 struct drm_i915_private *dev_priv = dev->dev_private;
11316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11317 uint32_t pf, pipesrc;
11318 int ret;
d21fbe87 11319
5a21b665
DV
11320 ret = intel_ring_begin(req, 4);
11321 if (ret)
11322 return ret;
92826fcd 11323
5a21b665
DV
11324 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11325 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11326 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11327 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
92826fcd 11328
5a21b665
DV
11329 /* Contrary to the suggestions in the documentation,
11330 * "Enable Panel Fitter" does not seem to be required when page
11331 * flipping with a non-native mode, and worse causes a normal
11332 * modeset to fail.
11333 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11334 */
11335 pf = 0;
11336 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11337 intel_ring_emit(engine, pf | pipesrc);
7809e5ae 11338
5a21b665 11339 return 0;
7809e5ae
MR
11340}
11341
5a21b665
DV
11342static int intel_gen7_queue_flip(struct drm_device *dev,
11343 struct drm_crtc *crtc,
11344 struct drm_framebuffer *fb,
11345 struct drm_i915_gem_object *obj,
11346 struct drm_i915_gem_request *req,
11347 uint32_t flags)
d21fbe87 11348{
5a21b665
DV
11349 struct intel_engine_cs *engine = req->engine;
11350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11351 uint32_t plane_bit = 0;
11352 int len, ret;
d21fbe87 11353
5a21b665
DV
11354 switch (intel_crtc->plane) {
11355 case PLANE_A:
11356 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11357 break;
11358 case PLANE_B:
11359 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11360 break;
11361 case PLANE_C:
11362 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11363 break;
11364 default:
11365 WARN_ONCE(1, "unknown plane in flip command\n");
11366 return -ENODEV;
11367 }
11368
11369 len = 4;
11370 if (engine->id == RCS) {
11371 len += 6;
11372 /*
11373 * On Gen 8, SRM is now taking an extra dword to accommodate
11374 * 48bits addresses, and we need a NOOP for the batch size to
11375 * stay even.
11376 */
11377 if (IS_GEN8(dev))
11378 len += 2;
11379 }
11380
11381 /*
11382 * BSpec MI_DISPLAY_FLIP for IVB:
11383 * "The full packet must be contained within the same cache line."
11384 *
11385 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11386 * cacheline, if we ever start emitting more commands before
11387 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11388 * then do the cacheline alignment, and finally emit the
11389 * MI_DISPLAY_FLIP.
11390 */
11391 ret = intel_ring_cacheline_align(req);
11392 if (ret)
11393 return ret;
11394
11395 ret = intel_ring_begin(req, len);
11396 if (ret)
11397 return ret;
11398
11399 /* Unmask the flip-done completion message. Note that the bspec says that
11400 * we should do this for both the BCS and RCS, and that we must not unmask
11401 * more than one flip event at any time (or ensure that one flip message
11402 * can be sent by waiting for flip-done prior to queueing new flips).
11403 * Experimentation says that BCS works despite DERRMR masking all
11404 * flip-done completion events and that unmasking all planes at once
11405 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11406 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11407 */
11408 if (engine->id == RCS) {
11409 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11410 intel_ring_emit_reg(engine, DERRMR);
11411 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11412 DERRMR_PIPEB_PRI_FLIP_DONE |
11413 DERRMR_PIPEC_PRI_FLIP_DONE));
11414 if (IS_GEN8(dev))
11415 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11416 MI_SRM_LRM_GLOBAL_GTT);
11417 else
11418 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11419 MI_SRM_LRM_GLOBAL_GTT);
11420 intel_ring_emit_reg(engine, DERRMR);
11421 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11422 if (IS_GEN8(dev)) {
11423 intel_ring_emit(engine, 0);
11424 intel_ring_emit(engine, MI_NOOP);
11425 }
11426 }
11427
11428 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11429 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11430 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11431 intel_ring_emit(engine, (MI_NOOP));
11432
11433 return 0;
11434}
11435
11436static bool use_mmio_flip(struct intel_engine_cs *engine,
11437 struct drm_i915_gem_object *obj)
11438{
c37efb99
CW
11439 struct reservation_object *resv;
11440
5a21b665
DV
11441 /*
11442 * This is not being used for older platforms, because
11443 * non-availability of flip done interrupt forces us to use
11444 * CS flips. Older platforms derive flip done using some clever
11445 * tricks involving the flip_pending status bits and vblank irqs.
11446 * So using MMIO flips there would disrupt this mechanism.
11447 */
11448
11449 if (engine == NULL)
11450 return true;
11451
11452 if (INTEL_GEN(engine->i915) < 5)
11453 return false;
11454
11455 if (i915.use_mmio_flip < 0)
11456 return false;
11457 else if (i915.use_mmio_flip > 0)
11458 return true;
11459 else if (i915.enable_execlists)
11460 return true;
c37efb99
CW
11461
11462 resv = i915_gem_object_get_dmabuf_resv(obj);
11463 if (resv && !reservation_object_test_signaled_rcu(resv, false))
5a21b665 11464 return true;
c37efb99
CW
11465
11466 return engine != i915_gem_request_get_engine(obj->last_write_req);
5a21b665
DV
11467}
11468
11469static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11470 unsigned int rotation,
11471 struct intel_flip_work *work)
11472{
11473 struct drm_device *dev = intel_crtc->base.dev;
11474 struct drm_i915_private *dev_priv = dev->dev_private;
11475 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11476 const enum pipe pipe = intel_crtc->pipe;
11477 u32 ctl, stride, tile_height;
11478
11479 ctl = I915_READ(PLANE_CTL(pipe, 0));
11480 ctl &= ~PLANE_CTL_TILED_MASK;
11481 switch (fb->modifier[0]) {
11482 case DRM_FORMAT_MOD_NONE:
11483 break;
11484 case I915_FORMAT_MOD_X_TILED:
11485 ctl |= PLANE_CTL_TILED_X;
11486 break;
11487 case I915_FORMAT_MOD_Y_TILED:
11488 ctl |= PLANE_CTL_TILED_Y;
11489 break;
11490 case I915_FORMAT_MOD_Yf_TILED:
11491 ctl |= PLANE_CTL_TILED_YF;
11492 break;
11493 default:
11494 MISSING_CASE(fb->modifier[0]);
11495 }
11496
11497 /*
11498 * The stride is either expressed as a multiple of 64 bytes chunks for
11499 * linear buffers or in number of tiles for tiled buffers.
11500 */
11501 if (intel_rotation_90_or_270(rotation)) {
11502 /* stride = Surface height in tiles */
11503 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11504 stride = DIV_ROUND_UP(fb->height, tile_height);
11505 } else {
11506 stride = fb->pitches[0] /
11507 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11508 fb->pixel_format);
11509 }
11510
11511 /*
11512 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11513 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11514 */
11515 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11516 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11517
11518 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11519 POSTING_READ(PLANE_SURF(pipe, 0));
11520}
11521
11522static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11523 struct intel_flip_work *work)
11524{
11525 struct drm_device *dev = intel_crtc->base.dev;
11526 struct drm_i915_private *dev_priv = dev->dev_private;
11527 struct intel_framebuffer *intel_fb =
11528 to_intel_framebuffer(intel_crtc->base.primary->fb);
11529 struct drm_i915_gem_object *obj = intel_fb->obj;
11530 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11531 u32 dspcntr;
11532
11533 dspcntr = I915_READ(reg);
11534
11535 if (obj->tiling_mode != I915_TILING_NONE)
11536 dspcntr |= DISPPLANE_TILED;
11537 else
11538 dspcntr &= ~DISPPLANE_TILED;
11539
11540 I915_WRITE(reg, dspcntr);
11541
11542 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11543 POSTING_READ(DSPSURF(intel_crtc->plane));
11544}
11545
11546static void intel_mmio_flip_work_func(struct work_struct *w)
11547{
11548 struct intel_flip_work *work =
11549 container_of(w, struct intel_flip_work, mmio_work);
11550 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11551 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11552 struct intel_framebuffer *intel_fb =
11553 to_intel_framebuffer(crtc->base.primary->fb);
11554 struct drm_i915_gem_object *obj = intel_fb->obj;
c37efb99 11555 struct reservation_object *resv;
5a21b665
DV
11556
11557 if (work->flip_queued_req)
11558 WARN_ON(__i915_wait_request(work->flip_queued_req,
11559 false, NULL,
11560 &dev_priv->rps.mmioflips));
11561
11562 /* For framebuffer backed by dmabuf, wait for fence */
c37efb99
CW
11563 resv = i915_gem_object_get_dmabuf_resv(obj);
11564 if (resv)
11565 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
5a21b665
DV
11566 MAX_SCHEDULE_TIMEOUT) < 0);
11567
11568 intel_pipe_update_start(crtc);
11569
11570 if (INTEL_GEN(dev_priv) >= 9)
11571 skl_do_mmio_flip(crtc, work->rotation, work);
11572 else
11573 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11574 ilk_do_mmio_flip(crtc, work);
11575
11576 intel_pipe_update_end(crtc, work);
11577}
11578
11579static int intel_default_queue_flip(struct drm_device *dev,
11580 struct drm_crtc *crtc,
11581 struct drm_framebuffer *fb,
11582 struct drm_i915_gem_object *obj,
11583 struct drm_i915_gem_request *req,
11584 uint32_t flags)
11585{
11586 return -ENODEV;
11587}
11588
11589static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11590 struct intel_crtc *intel_crtc,
11591 struct intel_flip_work *work)
11592{
11593 u32 addr, vblank;
11594
11595 if (!atomic_read(&work->pending))
11596 return false;
11597
11598 smp_rmb();
11599
11600 vblank = intel_crtc_get_vblank_counter(intel_crtc);
11601 if (work->flip_ready_vblank == 0) {
11602 if (work->flip_queued_req &&
11603 !i915_gem_request_completed(work->flip_queued_req, true))
11604 return false;
11605
11606 work->flip_ready_vblank = vblank;
11607 }
11608
11609 if (vblank - work->flip_ready_vblank < 3)
11610 return false;
11611
11612 /* Potential stall - if we see that the flip has happened,
11613 * assume a missed interrupt. */
11614 if (INTEL_GEN(dev_priv) >= 4)
11615 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11616 else
11617 addr = I915_READ(DSPADDR(intel_crtc->plane));
11618
11619 /* There is a potential issue here with a false positive after a flip
11620 * to the same address. We could address this by checking for a
11621 * non-incrementing frame counter.
11622 */
11623 return addr == work->gtt_offset;
11624}
11625
11626void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11627{
11628 struct drm_device *dev = dev_priv->dev;
11629 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11631 struct intel_flip_work *work;
11632
11633 WARN_ON(!in_interrupt());
11634
11635 if (crtc == NULL)
11636 return;
11637
11638 spin_lock(&dev->event_lock);
11639 work = intel_crtc->flip_work;
11640
11641 if (work != NULL && !is_mmio_work(work) &&
11642 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11643 WARN_ONCE(1,
11644 "Kicking stuck page flip: queued at %d, now %d\n",
11645 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11646 page_flip_completed(intel_crtc);
11647 work = NULL;
11648 }
11649
11650 if (work != NULL && !is_mmio_work(work) &&
11651 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11652 intel_queue_rps_boost_for_request(work->flip_queued_req);
11653 spin_unlock(&dev->event_lock);
11654}
11655
11656static int intel_crtc_page_flip(struct drm_crtc *crtc,
11657 struct drm_framebuffer *fb,
11658 struct drm_pending_vblank_event *event,
11659 uint32_t page_flip_flags)
11660{
11661 struct drm_device *dev = crtc->dev;
11662 struct drm_i915_private *dev_priv = dev->dev_private;
11663 struct drm_framebuffer *old_fb = crtc->primary->fb;
11664 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11666 struct drm_plane *primary = crtc->primary;
11667 enum pipe pipe = intel_crtc->pipe;
11668 struct intel_flip_work *work;
11669 struct intel_engine_cs *engine;
11670 bool mmio_flip;
11671 struct drm_i915_gem_request *request = NULL;
11672 int ret;
11673
11674 /*
11675 * drm_mode_page_flip_ioctl() should already catch this, but double
11676 * check to be safe. In the future we may enable pageflipping from
11677 * a disabled primary plane.
11678 */
11679 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11680 return -EBUSY;
11681
11682 /* Can't change pixel format via MI display flips. */
11683 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11684 return -EINVAL;
11685
11686 /*
11687 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11688 * Note that pitch changes could also affect these register.
11689 */
11690 if (INTEL_INFO(dev)->gen > 3 &&
11691 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11692 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11693 return -EINVAL;
11694
11695 if (i915_terminally_wedged(&dev_priv->gpu_error))
11696 goto out_hang;
11697
11698 work = kzalloc(sizeof(*work), GFP_KERNEL);
11699 if (work == NULL)
11700 return -ENOMEM;
11701
11702 work->event = event;
11703 work->crtc = crtc;
11704 work->old_fb = old_fb;
11705 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11706
11707 ret = drm_crtc_vblank_get(crtc);
11708 if (ret)
11709 goto free_work;
11710
11711 /* We borrow the event spin lock for protecting flip_work */
11712 spin_lock_irq(&dev->event_lock);
11713 if (intel_crtc->flip_work) {
11714 /* Before declaring the flip queue wedged, check if
11715 * the hardware completed the operation behind our backs.
11716 */
11717 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
11718 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11719 page_flip_completed(intel_crtc);
11720 } else {
11721 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11722 spin_unlock_irq(&dev->event_lock);
11723
11724 drm_crtc_vblank_put(crtc);
11725 kfree(work);
11726 return -EBUSY;
11727 }
11728 }
11729 intel_crtc->flip_work = work;
11730 spin_unlock_irq(&dev->event_lock);
11731
11732 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11733 flush_workqueue(dev_priv->wq);
11734
11735 /* Reference the objects for the scheduled work. */
11736 drm_framebuffer_reference(work->old_fb);
11737 drm_gem_object_reference(&obj->base);
11738
11739 crtc->primary->fb = fb;
11740 update_state_fb(crtc->primary);
faf68d92
ML
11741
11742 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
11743 to_intel_plane_state(primary->state));
5a21b665
DV
11744
11745 work->pending_flip_obj = obj;
11746
11747 ret = i915_mutex_lock_interruptible(dev);
11748 if (ret)
11749 goto cleanup;
11750
11751 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11752 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11753 ret = -EIO;
11754 goto cleanup;
11755 }
11756
11757 atomic_inc(&intel_crtc->unpin_work_count);
11758
11759 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11760 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11761
11762 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11763 engine = &dev_priv->engine[BCS];
11764 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11765 /* vlv: DISPLAY_FLIP fails to change tiling */
11766 engine = NULL;
11767 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11768 engine = &dev_priv->engine[BCS];
11769 } else if (INTEL_INFO(dev)->gen >= 7) {
11770 engine = i915_gem_request_get_engine(obj->last_write_req);
11771 if (engine == NULL || engine->id != RCS)
11772 engine = &dev_priv->engine[BCS];
11773 } else {
11774 engine = &dev_priv->engine[RCS];
11775 }
11776
11777 mmio_flip = use_mmio_flip(engine, obj);
11778
11779 /* When using CS flips, we want to emit semaphores between rings.
11780 * However, when using mmio flips we will create a task to do the
11781 * synchronisation, so all we want here is to pin the framebuffer
11782 * into the display plane and skip any waits.
11783 */
11784 if (!mmio_flip) {
11785 ret = i915_gem_object_sync(obj, engine, &request);
11786 if (!ret && !request) {
11787 request = i915_gem_request_alloc(engine, NULL);
11788 ret = PTR_ERR_OR_ZERO(request);
11789 }
11790
11791 if (ret)
11792 goto cleanup_pending;
11793 }
11794
11795 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11796 if (ret)
11797 goto cleanup_pending;
11798
11799 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11800 obj, 0);
11801 work->gtt_offset += intel_crtc->dspaddr_offset;
11802 work->rotation = crtc->primary->state->rotation;
11803
11804 if (mmio_flip) {
11805 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11806
11807 i915_gem_request_assign(&work->flip_queued_req,
11808 obj->last_write_req);
11809
11810 schedule_work(&work->mmio_work);
11811 } else {
11812 i915_gem_request_assign(&work->flip_queued_req, request);
11813 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11814 page_flip_flags);
11815 if (ret)
11816 goto cleanup_unpin;
11817
11818 intel_mark_page_flip_active(intel_crtc, work);
11819
11820 i915_add_request_no_flush(request);
11821 }
11822
11823 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11824 to_intel_plane(primary)->frontbuffer_bit);
11825 mutex_unlock(&dev->struct_mutex);
11826
11827 intel_frontbuffer_flip_prepare(dev,
11828 to_intel_plane(primary)->frontbuffer_bit);
11829
11830 trace_i915_flip_request(intel_crtc->plane, obj);
11831
11832 return 0;
11833
11834cleanup_unpin:
11835 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11836cleanup_pending:
11837 if (!IS_ERR_OR_NULL(request))
11838 i915_add_request_no_flush(request);
11839 atomic_dec(&intel_crtc->unpin_work_count);
11840 mutex_unlock(&dev->struct_mutex);
11841cleanup:
11842 crtc->primary->fb = old_fb;
11843 update_state_fb(crtc->primary);
11844
11845 drm_gem_object_unreference_unlocked(&obj->base);
11846 drm_framebuffer_unreference(work->old_fb);
11847
11848 spin_lock_irq(&dev->event_lock);
11849 intel_crtc->flip_work = NULL;
11850 spin_unlock_irq(&dev->event_lock);
11851
11852 drm_crtc_vblank_put(crtc);
11853free_work:
11854 kfree(work);
11855
11856 if (ret == -EIO) {
11857 struct drm_atomic_state *state;
11858 struct drm_plane_state *plane_state;
11859
11860out_hang:
11861 state = drm_atomic_state_alloc(dev);
11862 if (!state)
11863 return -ENOMEM;
11864 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11865
11866retry:
11867 plane_state = drm_atomic_get_plane_state(state, primary);
11868 ret = PTR_ERR_OR_ZERO(plane_state);
11869 if (!ret) {
11870 drm_atomic_set_fb_for_plane(plane_state, fb);
11871
11872 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11873 if (!ret)
11874 ret = drm_atomic_commit(state);
11875 }
11876
11877 if (ret == -EDEADLK) {
11878 drm_modeset_backoff(state->acquire_ctx);
11879 drm_atomic_state_clear(state);
11880 goto retry;
11881 }
11882
11883 if (ret)
11884 drm_atomic_state_free(state);
11885
11886 if (ret == 0 && event) {
11887 spin_lock_irq(&dev->event_lock);
11888 drm_crtc_send_vblank_event(crtc, event);
11889 spin_unlock_irq(&dev->event_lock);
11890 }
11891 }
11892 return ret;
11893}
11894
11895
11896/**
11897 * intel_wm_need_update - Check whether watermarks need updating
11898 * @plane: drm plane
11899 * @state: new plane state
11900 *
11901 * Check current plane state versus the new one to determine whether
11902 * watermarks need to be recalculated.
11903 *
11904 * Returns true or false.
11905 */
11906static bool intel_wm_need_update(struct drm_plane *plane,
11907 struct drm_plane_state *state)
11908{
11909 struct intel_plane_state *new = to_intel_plane_state(state);
11910 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11911
11912 /* Update watermarks on tiling or size changes. */
11913 if (new->visible != cur->visible)
11914 return true;
11915
11916 if (!cur->base.fb || !new->base.fb)
11917 return false;
11918
11919 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11920 cur->base.rotation != new->base.rotation ||
11921 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11922 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11923 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11924 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11925 return true;
11926
11927 return false;
11928}
11929
11930static bool needs_scaling(struct intel_plane_state *state)
11931{
11932 int src_w = drm_rect_width(&state->src) >> 16;
11933 int src_h = drm_rect_height(&state->src) >> 16;
11934 int dst_w = drm_rect_width(&state->dst);
11935 int dst_h = drm_rect_height(&state->dst);
11936
11937 return (src_w != dst_w || src_h != dst_h);
11938}
d21fbe87 11939
da20eabd
ML
11940int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11941 struct drm_plane_state *plane_state)
11942{
ab1d3a0e 11943 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
da20eabd
ML
11944 struct drm_crtc *crtc = crtc_state->crtc;
11945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11946 struct drm_plane *plane = plane_state->plane;
11947 struct drm_device *dev = crtc->dev;
ed4a6a7c 11948 struct drm_i915_private *dev_priv = to_i915(dev);
da20eabd
ML
11949 struct intel_plane_state *old_plane_state =
11950 to_intel_plane_state(plane->state);
da20eabd
ML
11951 bool mode_changed = needs_modeset(crtc_state);
11952 bool was_crtc_enabled = crtc->state->active;
11953 bool is_crtc_enabled = crtc_state->active;
da20eabd
ML
11954 bool turn_off, turn_on, visible, was_visible;
11955 struct drm_framebuffer *fb = plane_state->fb;
78108b7c 11956 int ret;
da20eabd
ML
11957
11958 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11959 plane->type != DRM_PLANE_TYPE_CURSOR) {
11960 ret = skl_update_scaler_plane(
11961 to_intel_crtc_state(crtc_state),
11962 to_intel_plane_state(plane_state));
11963 if (ret)
11964 return ret;
11965 }
11966
da20eabd
ML
11967 was_visible = old_plane_state->visible;
11968 visible = to_intel_plane_state(plane_state)->visible;
11969
11970 if (!was_crtc_enabled && WARN_ON(was_visible))
11971 was_visible = false;
11972
35c08f43
ML
11973 /*
11974 * Visibility is calculated as if the crtc was on, but
11975 * after scaler setup everything depends on it being off
11976 * when the crtc isn't active.
f818ffea
VS
11977 *
11978 * FIXME this is wrong for watermarks. Watermarks should also
11979 * be computed as if the pipe would be active. Perhaps move
11980 * per-plane wm computation to the .check_plane() hook, and
11981 * only combine the results from all planes in the current place?
35c08f43
ML
11982 */
11983 if (!is_crtc_enabled)
11984 to_intel_plane_state(plane_state)->visible = visible = false;
da20eabd
ML
11985
11986 if (!was_visible && !visible)
11987 return 0;
11988
e8861675
ML
11989 if (fb != old_plane_state->base.fb)
11990 pipe_config->fb_changed = true;
11991
da20eabd
ML
11992 turn_off = was_visible && (!visible || mode_changed);
11993 turn_on = visible && (!was_visible || mode_changed);
11994
72660ce0 11995 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
78108b7c
VS
11996 intel_crtc->base.base.id,
11997 intel_crtc->base.name,
72660ce0
VS
11998 plane->base.id, plane->name,
11999 fb ? fb->base.id : -1);
da20eabd 12000
72660ce0
VS
12001 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12002 plane->base.id, plane->name,
12003 was_visible, visible,
da20eabd
ML
12004 turn_off, turn_on, mode_changed);
12005
caed361d
VS
12006 if (turn_on) {
12007 pipe_config->update_wm_pre = true;
12008
12009 /* must disable cxsr around plane enable/disable */
12010 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12011 pipe_config->disable_cxsr = true;
12012 } else if (turn_off) {
12013 pipe_config->update_wm_post = true;
92826fcd 12014
852eb00d 12015 /* must disable cxsr around plane enable/disable */
e8861675 12016 if (plane->type != DRM_PLANE_TYPE_CURSOR)
ab1d3a0e 12017 pipe_config->disable_cxsr = true;
852eb00d 12018 } else if (intel_wm_need_update(plane, plane_state)) {
caed361d
VS
12019 /* FIXME bollocks */
12020 pipe_config->update_wm_pre = true;
12021 pipe_config->update_wm_post = true;
852eb00d 12022 }
da20eabd 12023
ed4a6a7c 12024 /* Pre-gen9 platforms need two-step watermark updates */
caed361d
VS
12025 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12026 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
ed4a6a7c
MR
12027 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12028
8be6ca85 12029 if (visible || was_visible)
cd202f69 12030 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
a9ff8714 12031
31ae71fc
ML
12032 /*
12033 * WaCxSRDisabledForSpriteScaling:ivb
12034 *
12035 * cstate->update_wm was already set above, so this flag will
12036 * take effect when we commit and program watermarks.
12037 */
12038 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12039 needs_scaling(to_intel_plane_state(plane_state)) &&
12040 !needs_scaling(old_plane_state))
12041 pipe_config->disable_lp_wm = true;
d21fbe87 12042
da20eabd
ML
12043 return 0;
12044}
12045
6d3a1ce7
ML
12046static bool encoders_cloneable(const struct intel_encoder *a,
12047 const struct intel_encoder *b)
12048{
12049 /* masks could be asymmetric, so check both ways */
12050 return a == b || (a->cloneable & (1 << b->type) &&
12051 b->cloneable & (1 << a->type));
12052}
12053
12054static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12055 struct intel_crtc *crtc,
12056 struct intel_encoder *encoder)
12057{
12058 struct intel_encoder *source_encoder;
12059 struct drm_connector *connector;
12060 struct drm_connector_state *connector_state;
12061 int i;
12062
12063 for_each_connector_in_state(state, connector, connector_state, i) {
12064 if (connector_state->crtc != &crtc->base)
12065 continue;
12066
12067 source_encoder =
12068 to_intel_encoder(connector_state->best_encoder);
12069 if (!encoders_cloneable(encoder, source_encoder))
12070 return false;
12071 }
12072
12073 return true;
12074}
12075
12076static bool check_encoder_cloning(struct drm_atomic_state *state,
12077 struct intel_crtc *crtc)
12078{
12079 struct intel_encoder *encoder;
12080 struct drm_connector *connector;
12081 struct drm_connector_state *connector_state;
12082 int i;
12083
12084 for_each_connector_in_state(state, connector, connector_state, i) {
12085 if (connector_state->crtc != &crtc->base)
12086 continue;
12087
12088 encoder = to_intel_encoder(connector_state->best_encoder);
12089 if (!check_single_encoder_cloning(state, crtc, encoder))
12090 return false;
12091 }
12092
12093 return true;
12094}
12095
12096static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12097 struct drm_crtc_state *crtc_state)
12098{
cf5a15be 12099 struct drm_device *dev = crtc->dev;
ad421372 12100 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 12101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML
12102 struct intel_crtc_state *pipe_config =
12103 to_intel_crtc_state(crtc_state);
6d3a1ce7 12104 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 12105 int ret;
6d3a1ce7
ML
12106 bool mode_changed = needs_modeset(crtc_state);
12107
12108 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12109 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12110 return -EINVAL;
12111 }
12112
852eb00d 12113 if (mode_changed && !crtc_state->active)
caed361d 12114 pipe_config->update_wm_post = true;
eddfcbcd 12115
ad421372
ML
12116 if (mode_changed && crtc_state->enable &&
12117 dev_priv->display.crtc_compute_clock &&
8106ddbd 12118 !WARN_ON(pipe_config->shared_dpll)) {
ad421372
ML
12119 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12120 pipe_config);
12121 if (ret)
12122 return ret;
12123 }
12124
82cf435b
LL
12125 if (crtc_state->color_mgmt_changed) {
12126 ret = intel_color_check(crtc, crtc_state);
12127 if (ret)
12128 return ret;
12129 }
12130
e435d6e5 12131 ret = 0;
86c8bbbe 12132 if (dev_priv->display.compute_pipe_wm) {
e3bddded 12133 ret = dev_priv->display.compute_pipe_wm(pipe_config);
ed4a6a7c
MR
12134 if (ret) {
12135 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12136 return ret;
12137 }
12138 }
12139
12140 if (dev_priv->display.compute_intermediate_wm &&
12141 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12142 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12143 return 0;
12144
12145 /*
12146 * Calculate 'intermediate' watermarks that satisfy both the
12147 * old state and the new state. We can program these
12148 * immediately.
12149 */
12150 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12151 intel_crtc,
12152 pipe_config);
12153 if (ret) {
12154 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
86c8bbbe 12155 return ret;
ed4a6a7c 12156 }
e3d5457c
VS
12157 } else if (dev_priv->display.compute_intermediate_wm) {
12158 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12159 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
86c8bbbe
MR
12160 }
12161
e435d6e5
ML
12162 if (INTEL_INFO(dev)->gen >= 9) {
12163 if (mode_changed)
12164 ret = skl_update_scaler_crtc(pipe_config);
12165
12166 if (!ret)
12167 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12168 pipe_config);
12169 }
12170
12171 return ret;
6d3a1ce7
ML
12172}
12173
65b38e0d 12174static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160 12175 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5a21b665
DV
12176 .atomic_begin = intel_begin_crtc_commit,
12177 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 12178 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW
12179};
12180
d29b2f9d
ACO
12181static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12182{
12183 struct intel_connector *connector;
12184
12185 for_each_intel_connector(dev, connector) {
8863dc7f
DV
12186 if (connector->base.state->crtc)
12187 drm_connector_unreference(&connector->base);
12188
d29b2f9d
ACO
12189 if (connector->base.encoder) {
12190 connector->base.state->best_encoder =
12191 connector->base.encoder;
12192 connector->base.state->crtc =
12193 connector->base.encoder->crtc;
8863dc7f
DV
12194
12195 drm_connector_reference(&connector->base);
d29b2f9d
ACO
12196 } else {
12197 connector->base.state->best_encoder = NULL;
12198 connector->base.state->crtc = NULL;
12199 }
12200 }
12201}
12202
050f7aeb 12203static void
eba905b2 12204connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 12205 struct intel_crtc_state *pipe_config)
050f7aeb
DV
12206{
12207 int bpp = pipe_config->pipe_bpp;
12208
12209 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12210 connector->base.base.id,
c23cc417 12211 connector->base.name);
050f7aeb
DV
12212
12213 /* Don't use an invalid EDID bpc value */
12214 if (connector->base.display_info.bpc &&
12215 connector->base.display_info.bpc * 3 < bpp) {
12216 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12217 bpp, connector->base.display_info.bpc*3);
12218 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12219 }
12220
013dd9e0
JN
12221 /* Clamp bpp to default limit on screens without EDID 1.4 */
12222 if (connector->base.display_info.bpc == 0) {
12223 int type = connector->base.connector_type;
12224 int clamp_bpp = 24;
12225
12226 /* Fall back to 18 bpp when DP sink capability is unknown. */
12227 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12228 type == DRM_MODE_CONNECTOR_eDP)
12229 clamp_bpp = 18;
12230
12231 if (bpp > clamp_bpp) {
12232 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12233 bpp, clamp_bpp);
12234 pipe_config->pipe_bpp = clamp_bpp;
12235 }
050f7aeb
DV
12236 }
12237}
12238
4e53c2e0 12239static int
050f7aeb 12240compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 12241 struct intel_crtc_state *pipe_config)
4e53c2e0 12242{
050f7aeb 12243 struct drm_device *dev = crtc->base.dev;
1486017f 12244 struct drm_atomic_state *state;
da3ced29
ACO
12245 struct drm_connector *connector;
12246 struct drm_connector_state *connector_state;
1486017f 12247 int bpp, i;
4e53c2e0 12248
666a4537 12249 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
4e53c2e0 12250 bpp = 10*3;
d328c9d7
DV
12251 else if (INTEL_INFO(dev)->gen >= 5)
12252 bpp = 12*3;
12253 else
12254 bpp = 8*3;
12255
4e53c2e0 12256
4e53c2e0
DV
12257 pipe_config->pipe_bpp = bpp;
12258
1486017f
ACO
12259 state = pipe_config->base.state;
12260
4e53c2e0 12261 /* Clamp display bpp to EDID value */
da3ced29
ACO
12262 for_each_connector_in_state(state, connector, connector_state, i) {
12263 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV
12264 continue;
12265
da3ced29
ACO
12266 connected_sink_compute_bpp(to_intel_connector(connector),
12267 pipe_config);
4e53c2e0
DV
12268 }
12269
12270 return bpp;
12271}
12272
644db711
DV
12273static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12274{
12275 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12276 "type: 0x%x flags: 0x%x\n",
1342830c 12277 mode->crtc_clock,
644db711
DV
12278 mode->crtc_hdisplay, mode->crtc_hsync_start,
12279 mode->crtc_hsync_end, mode->crtc_htotal,
12280 mode->crtc_vdisplay, mode->crtc_vsync_start,
12281 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12282}
12283
c0b03411 12284static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 12285 struct intel_crtc_state *pipe_config,
c0b03411
DV
12286 const char *context)
12287{
6a60cd87
CK
12288 struct drm_device *dev = crtc->base.dev;
12289 struct drm_plane *plane;
12290 struct intel_plane *intel_plane;
12291 struct intel_plane_state *state;
12292 struct drm_framebuffer *fb;
12293
78108b7c
VS
12294 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12295 crtc->base.base.id, crtc->base.name,
6a60cd87 12296 context, pipe_config, pipe_name(crtc->pipe));
c0b03411 12297
da205630 12298 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
c0b03411
DV
12299 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12300 pipe_config->pipe_bpp, pipe_config->dither);
12301 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12302 pipe_config->has_pch_encoder,
12303 pipe_config->fdi_lanes,
12304 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12305 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12306 pipe_config->fdi_m_n.tu);
90a6b7b0 12307 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 12308 pipe_config->has_dp_encoder,
90a6b7b0 12309 pipe_config->lane_count,
eb14cb74
VS
12310 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12311 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12312 pipe_config->dp_m_n.tu);
b95af8be 12313
90a6b7b0 12314 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 12315 pipe_config->has_dp_encoder,
90a6b7b0 12316 pipe_config->lane_count,
b95af8be
VK
12317 pipe_config->dp_m2_n2.gmch_m,
12318 pipe_config->dp_m2_n2.gmch_n,
12319 pipe_config->dp_m2_n2.link_m,
12320 pipe_config->dp_m2_n2.link_n,
12321 pipe_config->dp_m2_n2.tu);
12322
55072d19
DV
12323 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12324 pipe_config->has_audio,
12325 pipe_config->has_infoframe);
12326
c0b03411 12327 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 12328 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 12329 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO
12330 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12331 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 12332 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS
12333 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12334 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU
12335 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12336 crtc->num_scalers,
12337 pipe_config->scaler_state.scaler_users,
12338 pipe_config->scaler_state.scaler_id);
c0b03411
DV
12339 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12340 pipe_config->gmch_pfit.control,
12341 pipe_config->gmch_pfit.pgm_ratios,
12342 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12343 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12344 pipe_config->pch_pfit.pos,
fd4daa9c
CW
12345 pipe_config->pch_pfit.size,
12346 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12347 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12348 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12349
415ff0f6 12350 if (IS_BROXTON(dev)) {
05712c15 12351 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 12352 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 12353 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU
12354 pipe_config->ddi_pll_sel,
12355 pipe_config->dpll_hw_state.ebb0,
05712c15 12356 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU
12357 pipe_config->dpll_hw_state.pll0,
12358 pipe_config->dpll_hw_state.pll1,
12359 pipe_config->dpll_hw_state.pll2,
12360 pipe_config->dpll_hw_state.pll3,
12361 pipe_config->dpll_hw_state.pll6,
12362 pipe_config->dpll_hw_state.pll8,
05712c15 12363 pipe_config->dpll_hw_state.pll9,
c8453338 12364 pipe_config->dpll_hw_state.pll10,
415ff0f6 12365 pipe_config->dpll_hw_state.pcsdw12);
ef11bdb3 12366 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
415ff0f6
TU
12367 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12368 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12369 pipe_config->ddi_pll_sel,
12370 pipe_config->dpll_hw_state.ctrl1,
12371 pipe_config->dpll_hw_state.cfgcr1,
12372 pipe_config->dpll_hw_state.cfgcr2);
12373 } else if (HAS_DDI(dev)) {
1260f07e 12374 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
415ff0f6 12375 pipe_config->ddi_pll_sel,
00490c22
ML
12376 pipe_config->dpll_hw_state.wrpll,
12377 pipe_config->dpll_hw_state.spll);
415ff0f6
TU
12378 } else {
12379 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12380 "fp0: 0x%x, fp1: 0x%x\n",
12381 pipe_config->dpll_hw_state.dpll,
12382 pipe_config->dpll_hw_state.dpll_md,
12383 pipe_config->dpll_hw_state.fp0,
12384 pipe_config->dpll_hw_state.fp1);
12385 }
12386
6a60cd87
CK
12387 DRM_DEBUG_KMS("planes on this crtc\n");
12388 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12389 intel_plane = to_intel_plane(plane);
12390 if (intel_plane->pipe != crtc->pipe)
12391 continue;
12392
12393 state = to_intel_plane_state(plane->state);
12394 fb = state->base.fb;
12395 if (!fb) {
1d577e02
VS
12396 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12397 plane->base.id, plane->name, state->scaler_id);
6a60cd87
CK
12398 continue;
12399 }
12400
1d577e02
VS
12401 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12402 plane->base.id, plane->name);
12403 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12404 fb->base.id, fb->width, fb->height,
12405 drm_get_format_name(fb->pixel_format));
12406 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12407 state->scaler_id,
12408 state->src.x1 >> 16, state->src.y1 >> 16,
12409 drm_rect_width(&state->src) >> 16,
12410 drm_rect_height(&state->src) >> 16,
12411 state->dst.x1, state->dst.y1,
12412 drm_rect_width(&state->dst),
12413 drm_rect_height(&state->dst));
6a60cd87 12414 }
c0b03411
DV
12415}
12416
5448a00d 12417static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12418{
5448a00d 12419 struct drm_device *dev = state->dev;
da3ced29 12420 struct drm_connector *connector;
00f0b378
VS
12421 unsigned int used_ports = 0;
12422
12423 /*
12424 * Walk the connector list instead of the encoder
12425 * list to detect the problem on ddi platforms
12426 * where there's just one encoder per digital port.
12427 */
0bff4858
VS
12428 drm_for_each_connector(connector, dev) {
12429 struct drm_connector_state *connector_state;
12430 struct intel_encoder *encoder;
12431
12432 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12433 if (!connector_state)
12434 connector_state = connector->state;
12435
5448a00d 12436 if (!connector_state->best_encoder)
00f0b378
VS
12437 continue;
12438
5448a00d
ACO
12439 encoder = to_intel_encoder(connector_state->best_encoder);
12440
12441 WARN_ON(!connector_state->crtc);
00f0b378
VS
12442
12443 switch (encoder->type) {
12444 unsigned int port_mask;
12445 case INTEL_OUTPUT_UNKNOWN:
12446 if (WARN_ON(!HAS_DDI(dev)))
12447 break;
12448 case INTEL_OUTPUT_DISPLAYPORT:
12449 case INTEL_OUTPUT_HDMI:
12450 case INTEL_OUTPUT_EDP:
12451 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12452
12453 /* the same port mustn't appear more than once */
12454 if (used_ports & port_mask)
12455 return false;
12456
12457 used_ports |= port_mask;
12458 default:
12459 break;
12460 }
12461 }
12462
12463 return true;
12464}
12465
83a57153
ACO
12466static void
12467clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12468{
12469 struct drm_crtc_state tmp_state;
663a3640 12470 struct intel_crtc_scaler_state scaler_state;
4978cc93 12471 struct intel_dpll_hw_state dpll_hw_state;
8106ddbd 12472 struct intel_shared_dpll *shared_dpll;
8504c74c 12473 uint32_t ddi_pll_sel;
c4e2d043 12474 bool force_thru;
83a57153 12475
7546a384
ACO
12476 /* FIXME: before the switch to atomic started, a new pipe_config was
12477 * kzalloc'd. Code that depends on any field being zero should be
12478 * fixed, so that the crtc_state can be safely duplicated. For now,
12479 * only fields that are know to not cause problems are preserved. */
12480
83a57153 12481 tmp_state = crtc_state->base;
663a3640 12482 scaler_state = crtc_state->scaler_state;
4978cc93
ACO
12483 shared_dpll = crtc_state->shared_dpll;
12484 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12485 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12486 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12487
83a57153 12488 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12489
83a57153 12490 crtc_state->base = tmp_state;
663a3640 12491 crtc_state->scaler_state = scaler_state;
4978cc93
ACO
12492 crtc_state->shared_dpll = shared_dpll;
12493 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12494 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12495 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO
12496}
12497
548ee15b 12498static int
b8cecdf5 12499intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12500 struct intel_crtc_state *pipe_config)
ee7b9f93 12501{
b359283a 12502 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12503 struct intel_encoder *encoder;
da3ced29 12504 struct drm_connector *connector;
0b901879 12505 struct drm_connector_state *connector_state;
d328c9d7 12506 int base_bpp, ret = -EINVAL;
0b901879 12507 int i;
e29c22c0 12508 bool retry = true;
ee7b9f93 12509
83a57153 12510 clear_intel_crtc_state(pipe_config);
7758a113 12511
e143a21c
DV
12512 pipe_config->cpu_transcoder =
12513 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12514
2960bc9c
ID
12515 /*
12516 * Sanitize sync polarity flags based on requested ones. If neither
12517 * positive or negative polarity is requested, treat this as meaning
12518 * negative polarity.
12519 */
2d112de7 12520 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12521 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12522 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12523
2d112de7 12524 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12525 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12526 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12527
d328c9d7
DV
12528 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12529 pipe_config);
12530 if (base_bpp < 0)
4e53c2e0
DV
12531 goto fail;
12532
e41a56be
VS
12533 /*
12534 * Determine the real pipe dimensions. Note that stereo modes can
12535 * increase the actual pipe size due to the frame doubling and
12536 * insertion of additional space for blanks between the frame. This
12537 * is stored in the crtc timings. We use the requested mode to do this
12538 * computation to clearly distinguish it from the adjusted mode, which
12539 * can be changed by the connectors in the below retry loop.
12540 */
2d112de7 12541 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP
12542 &pipe_config->pipe_src_w,
12543 &pipe_config->pipe_src_h);
e41a56be 12544
e29c22c0 12545encoder_retry:
ef1b460d 12546 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12547 pipe_config->port_clock = 0;
ef1b460d 12548 pipe_config->pixel_multiplier = 1;
ff9a6750 12549
135c81b8 12550 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO
12551 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12552 CRTC_STEREO_DOUBLE);
135c81b8 12553
7758a113
DV
12554 /* Pass our mode to the connectors and the CRTC to give them a chance to
12555 * adjust it according to limitations or connector properties, and also
12556 * a chance to reject the mode entirely.
47f1c6c9 12557 */
da3ced29 12558 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12559 if (connector_state->crtc != crtc)
7758a113 12560 continue;
7ae89233 12561
0b901879
ACO
12562 encoder = to_intel_encoder(connector_state->best_encoder);
12563
efea6e8e
DV
12564 if (!(encoder->compute_config(encoder, pipe_config))) {
12565 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV
12566 goto fail;
12567 }
ee7b9f93 12568 }
47f1c6c9 12569
ff9a6750
DV
12570 /* Set default port clock if not overwritten by the encoder. Needs to be
12571 * done afterwards in case the encoder adjusts the mode. */
12572 if (!pipe_config->port_clock)
2d112de7 12573 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12574 * pipe_config->pixel_multiplier;
ff9a6750 12575
a43f6e0f 12576 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12577 if (ret < 0) {
7758a113
DV
12578 DRM_DEBUG_KMS("CRTC fixup failed\n");
12579 goto fail;
ee7b9f93 12580 }
e29c22c0
DV
12581
12582 if (ret == RETRY) {
12583 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12584 ret = -EINVAL;
12585 goto fail;
12586 }
12587
12588 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12589 retry = false;
12590 goto encoder_retry;
12591 }
12592
e8fa4270
DV
12593 /* Dithering seems to not pass-through bits correctly when it should, so
12594 * only enable it on 6bpc panels. */
12595 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12596 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12597 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12598
7758a113 12599fail:
548ee15b 12600 return ret;
ee7b9f93 12601}
47f1c6c9 12602
ea9d758d 12603static void
4740b0f2 12604intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12605{
0a9ab303
ACO
12606 struct drm_crtc *crtc;
12607 struct drm_crtc_state *crtc_state;
8a75d157 12608 int i;
ea9d758d 12609
7668851f 12610 /* Double check state. */
8a75d157 12611 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12612 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML
12613
12614 /* Update hwmode for vblank functions */
12615 if (crtc->state->active)
12616 crtc->hwmode = crtc->state->adjusted_mode;
12617 else
12618 crtc->hwmode.crtc_clock = 0;
61067a5e
ML
12619
12620 /*
12621 * Update legacy state to satisfy fbc code. This can
12622 * be removed when fbc uses the atomic state.
12623 */
12624 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12625 struct drm_plane_state *plane_state = crtc->primary->state;
12626
12627 crtc->primary->fb = plane_state->fb;
12628 crtc->x = plane_state->src_x >> 16;
12629 crtc->y = plane_state->src_y >> 16;
12630 }
ea9d758d 12631 }
ea9d758d
DV
12632}
12633
3bd26263 12634static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12635{
3bd26263 12636 int diff;
f1f644dc
JB
12637
12638 if (clock1 == clock2)
12639 return true;
12640
12641 if (!clock1 || !clock2)
12642 return false;
12643
12644 diff = abs(clock1 - clock2);
12645
12646 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12647 return true;
12648
12649 return false;
12650}
12651
25c5b266
DV
12652#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12653 list_for_each_entry((intel_crtc), \
12654 &(dev)->mode_config.crtc_list, \
12655 base.head) \
95150bdf 12656 for_each_if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12657
cfb23ed6
ML
12658static bool
12659intel_compare_m_n(unsigned int m, unsigned int n,
12660 unsigned int m2, unsigned int n2,
12661 bool exact)
12662{
12663 if (m == m2 && n == n2)
12664 return true;
12665
12666 if (exact || !m || !n || !m2 || !n2)
12667 return false;
12668
12669 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12670
31d10b57
ML
12671 if (n > n2) {
12672 while (n > n2) {
cfb23ed6
ML
12673 m2 <<= 1;
12674 n2 <<= 1;
12675 }
31d10b57
ML
12676 } else if (n < n2) {
12677 while (n < n2) {
cfb23ed6
ML
12678 m <<= 1;
12679 n <<= 1;
12680 }
12681 }
12682
31d10b57
ML
12683 if (n != n2)
12684 return false;
12685
12686 return intel_fuzzy_clock_check(m, m2);
cfb23ed6
ML
12687}
12688
12689static bool
12690intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12691 struct intel_link_m_n *m2_n2,
12692 bool adjust)
12693{
12694 if (m_n->tu == m2_n2->tu &&
12695 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12696 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12697 intel_compare_m_n(m_n->link_m, m_n->link_n,
12698 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12699 if (adjust)
12700 *m2_n2 = *m_n;
12701
12702 return true;
12703 }
12704
12705 return false;
12706}
12707
0e8ffe1b 12708static bool
2fa2fe9a 12709intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12710 struct intel_crtc_state *current_config,
cfb23ed6
ML
12711 struct intel_crtc_state *pipe_config,
12712 bool adjust)
0e8ffe1b 12713{
cfb23ed6
ML
12714 bool ret = true;
12715
12716#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12717 do { \
12718 if (!adjust) \
12719 DRM_ERROR(fmt, ##__VA_ARGS__); \
12720 else \
12721 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12722 } while (0)
12723
66e985c0
DV
12724#define PIPE_CONF_CHECK_X(name) \
12725 if (current_config->name != pipe_config->name) { \
cfb23ed6 12726 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV
12727 "(expected 0x%08x, found 0x%08x)\n", \
12728 current_config->name, \
12729 pipe_config->name); \
cfb23ed6 12730 ret = false; \
66e985c0
DV
12731 }
12732
08a24034
DV
12733#define PIPE_CONF_CHECK_I(name) \
12734 if (current_config->name != pipe_config->name) { \
cfb23ed6 12735 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV
12736 "(expected %i, found %i)\n", \
12737 current_config->name, \
12738 pipe_config->name); \
cfb23ed6
ML
12739 ret = false; \
12740 }
12741
8106ddbd
ACO
12742#define PIPE_CONF_CHECK_P(name) \
12743 if (current_config->name != pipe_config->name) { \
12744 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12745 "(expected %p, found %p)\n", \
12746 current_config->name, \
12747 pipe_config->name); \
12748 ret = false; \
12749 }
12750
cfb23ed6
ML
12751#define PIPE_CONF_CHECK_M_N(name) \
12752 if (!intel_compare_link_m_n(&current_config->name, \
12753 &pipe_config->name,\
12754 adjust)) { \
12755 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12756 "(expected tu %i gmch %i/%i link %i/%i, " \
12757 "found tu %i, gmch %i/%i link %i/%i)\n", \
12758 current_config->name.tu, \
12759 current_config->name.gmch_m, \
12760 current_config->name.gmch_n, \
12761 current_config->name.link_m, \
12762 current_config->name.link_n, \
12763 pipe_config->name.tu, \
12764 pipe_config->name.gmch_m, \
12765 pipe_config->name.gmch_n, \
12766 pipe_config->name.link_m, \
12767 pipe_config->name.link_n); \
12768 ret = false; \
12769 }
12770
55c561a7
DV
12771/* This is required for BDW+ where there is only one set of registers for
12772 * switching between high and low RR.
12773 * This macro can be used whenever a comparison has to be made between one
12774 * hw state and multiple sw state variables.
12775 */
cfb23ed6
ML
12776#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12777 if (!intel_compare_link_m_n(&current_config->name, \
12778 &pipe_config->name, adjust) && \
12779 !intel_compare_link_m_n(&current_config->alt_name, \
12780 &pipe_config->name, adjust)) { \
12781 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12782 "(expected tu %i gmch %i/%i link %i/%i, " \
12783 "or tu %i gmch %i/%i link %i/%i, " \
12784 "found tu %i, gmch %i/%i link %i/%i)\n", \
12785 current_config->name.tu, \
12786 current_config->name.gmch_m, \
12787 current_config->name.gmch_n, \
12788 current_config->name.link_m, \
12789 current_config->name.link_n, \
12790 current_config->alt_name.tu, \
12791 current_config->alt_name.gmch_m, \
12792 current_config->alt_name.gmch_n, \
12793 current_config->alt_name.link_m, \
12794 current_config->alt_name.link_n, \
12795 pipe_config->name.tu, \
12796 pipe_config->name.gmch_m, \
12797 pipe_config->name.gmch_n, \
12798 pipe_config->name.link_m, \
12799 pipe_config->name.link_n); \
12800 ret = false; \
88adfff1
DV
12801 }
12802
1bd1bd80
DV
12803#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12804 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12805 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV
12806 "(expected %i, found %i)\n", \
12807 current_config->name & (mask), \
12808 pipe_config->name & (mask)); \
cfb23ed6 12809 ret = false; \
1bd1bd80
DV
12810 }
12811
5e550656
VS
12812#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12813 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12814 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS
12815 "(expected %i, found %i)\n", \
12816 current_config->name, \
12817 pipe_config->name); \
cfb23ed6 12818 ret = false; \
5e550656
VS
12819 }
12820
bb760063
DV
12821#define PIPE_CONF_QUIRK(quirk) \
12822 ((current_config->quirks | pipe_config->quirks) & (quirk))
12823
eccb140b
DV
12824 PIPE_CONF_CHECK_I(cpu_transcoder);
12825
08a24034
DV
12826 PIPE_CONF_CHECK_I(has_pch_encoder);
12827 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12828 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12829
eb14cb74 12830 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12831 PIPE_CONF_CHECK_I(lane_count);
95a7a2ae 12832 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
b95af8be
VK
12833
12834 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML
12835 PIPE_CONF_CHECK_M_N(dp_m_n);
12836
cfb23ed6
ML
12837 if (current_config->has_drrs)
12838 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12839 } else
12840 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12841
a65347ba
JN
12842 PIPE_CONF_CHECK_I(has_dsi_encoder);
12843
2d112de7
ACO
12844 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12845 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12846 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12847 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12848 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12849 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12850
2d112de7
ACO
12851 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12852 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12853 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12854 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12855 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12856 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12857
c93f54cf 12858 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12859 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09 12860 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
666a4537 12861 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
b5a9fa09 12862 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12863 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12864
9ed109a7
DV
12865 PIPE_CONF_CHECK_I(has_audio);
12866
2d112de7 12867 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV
12868 DRM_MODE_FLAG_INTERLACE);
12869
bb760063 12870 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12871 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12872 DRM_MODE_FLAG_PHSYNC);
2d112de7 12873 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12874 DRM_MODE_FLAG_NHSYNC);
2d112de7 12875 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12876 DRM_MODE_FLAG_PVSYNC);
2d112de7 12877 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV
12878 DRM_MODE_FLAG_NVSYNC);
12879 }
045ac3b5 12880
333b8ca8 12881 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV
12882 /* pfit ratios are autocomputed by the hw on gen4+ */
12883 if (INTEL_INFO(dev)->gen < 4)
7f7d8dd6 12884 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
333b8ca8 12885 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12886
bfd16b2a
ML
12887 if (!adjust) {
12888 PIPE_CONF_CHECK_I(pipe_src_w);
12889 PIPE_CONF_CHECK_I(pipe_src_h);
12890
12891 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12892 if (current_config->pch_pfit.enabled) {
12893 PIPE_CONF_CHECK_X(pch_pfit.pos);
12894 PIPE_CONF_CHECK_X(pch_pfit.size);
12895 }
2fa2fe9a 12896
7aefe2b5
ML
12897 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12898 }
a1b2278e 12899
e59150dc
JB
12900 /* BDW+ don't expose a synchronous way to read the state */
12901 if (IS_HASWELL(dev))
12902 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12903
282740f7
VS
12904 PIPE_CONF_CHECK_I(double_wide);
12905
26804afd
DV
12906 PIPE_CONF_CHECK_X(ddi_pll_sel);
12907
8106ddbd 12908 PIPE_CONF_CHECK_P(shared_dpll);
66e985c0 12909 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12910 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV
12911 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12912 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12913 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
00490c22 12914 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
3f4cd19f
DL
12915 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12916 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12917 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12918
47eacbab
VS
12919 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12920 PIPE_CONF_CHECK_X(dsi_pll.div);
12921
42571aef
VS
12922 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12923 PIPE_CONF_CHECK_I(pipe_bpp);
12924
2d112de7 12925 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12926 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12927
66e985c0 12928#undef PIPE_CONF_CHECK_X
08a24034 12929#undef PIPE_CONF_CHECK_I
8106ddbd 12930#undef PIPE_CONF_CHECK_P
1bd1bd80 12931#undef PIPE_CONF_CHECK_FLAGS
5e550656 12932#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12933#undef PIPE_CONF_QUIRK
cfb23ed6 12934#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12935
cfb23ed6 12936 return ret;
0e8ffe1b
DV
12937}
12938
e3b247da
VS
12939static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12940 const struct intel_crtc_state *pipe_config)
12941{
12942 if (pipe_config->has_pch_encoder) {
21a727b3 12943 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
e3b247da
VS
12944 &pipe_config->fdi_m_n);
12945 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12946
12947 /*
12948 * FDI already provided one idea for the dotclock.
12949 * Yell if the encoder disagrees.
12950 */
12951 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12952 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12953 fdi_dotclock, dotclock);
12954 }
12955}
12956
c0ead703
ML
12957static void verify_wm_state(struct drm_crtc *crtc,
12958 struct drm_crtc_state *new_state)
08db6652 12959{
e7c84544 12960 struct drm_device *dev = crtc->dev;
08db6652
DL
12961 struct drm_i915_private *dev_priv = dev->dev_private;
12962 struct skl_ddb_allocation hw_ddb, *sw_ddb;
e7c84544
ML
12963 struct skl_ddb_entry *hw_entry, *sw_entry;
12964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12965 const enum pipe pipe = intel_crtc->pipe;
08db6652
DL
12966 int plane;
12967
e7c84544 12968 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
08db6652
DL
12969 return;
12970
12971 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12972 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12973
e7c84544
ML
12974 /* planes */
12975 for_each_plane(dev_priv, pipe, plane) {
12976 hw_entry = &hw_ddb.plane[pipe][plane];
12977 sw_entry = &sw_ddb->plane[pipe][plane];
08db6652 12978
e7c84544 12979 if (skl_ddb_entry_equal(hw_entry, sw_entry))
08db6652
DL
12980 continue;
12981
e7c84544
ML
12982 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12983 "(expected (%u,%u), found (%u,%u))\n",
12984 pipe_name(pipe), plane + 1,
12985 sw_entry->start, sw_entry->end,
12986 hw_entry->start, hw_entry->end);
12987 }
08db6652 12988
e7c84544
ML
12989 /* cursor */
12990 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12991 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
08db6652 12992
e7c84544 12993 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
08db6652
DL
12994 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12995 "(expected (%u,%u), found (%u,%u))\n",
12996 pipe_name(pipe),
12997 sw_entry->start, sw_entry->end,
12998 hw_entry->start, hw_entry->end);
12999 }
13000}
13001
91d1b4bd 13002static void
c0ead703 13003verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
8af6cf88 13004{
35dd3c64 13005 struct drm_connector *connector;
8af6cf88 13006
e7c84544 13007 drm_for_each_connector(connector, dev) {
35dd3c64
ML
13008 struct drm_encoder *encoder = connector->encoder;
13009 struct drm_connector_state *state = connector->state;
ad3c558f 13010
e7c84544
ML
13011 if (state->crtc != crtc)
13012 continue;
13013
5a21b665 13014 intel_connector_verify_state(to_intel_connector(connector));
8af6cf88 13015
ad3c558f 13016 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 13017 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 13018 }
91d1b4bd
DV
13019}
13020
13021static void
c0ead703 13022verify_encoder_state(struct drm_device *dev)
91d1b4bd
DV
13023{
13024 struct intel_encoder *encoder;
13025 struct intel_connector *connector;
8af6cf88 13026
b2784e15 13027 for_each_intel_encoder(dev, encoder) {
8af6cf88 13028 bool enabled = false;
4d20cd86 13029 enum pipe pipe;
8af6cf88
DV
13030
13031 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13032 encoder->base.base.id,
8e329a03 13033 encoder->base.name);
8af6cf88 13034
3a3371ff 13035 for_each_intel_connector(dev, connector) {
4d20cd86 13036 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV
13037 continue;
13038 enabled = true;
ad3c558f
ML
13039
13040 I915_STATE_WARN(connector->base.state->crtc !=
13041 encoder->base.crtc,
13042 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 13043 }
0e32b39c 13044
e2c719b7 13045 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV
13046 "encoder's enabled state mismatch "
13047 "(expected %i, found %i)\n",
13048 !!encoder->base.crtc, enabled);
7c60d198
ML
13049
13050 if (!encoder->base.crtc) {
4d20cd86 13051 bool active;
7c60d198 13052
4d20cd86
ML
13053 active = encoder->get_hw_state(encoder, &pipe);
13054 I915_STATE_WARN(active,
13055 "encoder detached but still enabled on pipe %c.\n",
13056 pipe_name(pipe));
7c60d198 13057 }
8af6cf88 13058 }
91d1b4bd
DV
13059}
13060
13061static void
c0ead703
ML
13062verify_crtc_state(struct drm_crtc *crtc,
13063 struct drm_crtc_state *old_crtc_state,
13064 struct drm_crtc_state *new_crtc_state)
91d1b4bd 13065{
e7c84544 13066 struct drm_device *dev = crtc->dev;
fbee40df 13067 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 13068 struct intel_encoder *encoder;
e7c84544
ML
13069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13070 struct intel_crtc_state *pipe_config, *sw_config;
13071 struct drm_atomic_state *old_state;
13072 bool active;
045ac3b5 13073
e7c84544 13074 old_state = old_crtc_state->state;
ec2dc6a0 13075 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
e7c84544
ML
13076 pipe_config = to_intel_crtc_state(old_crtc_state);
13077 memset(pipe_config, 0, sizeof(*pipe_config));
13078 pipe_config->base.crtc = crtc;
13079 pipe_config->base.state = old_state;
8af6cf88 13080
78108b7c 13081 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
8af6cf88 13082
e7c84544 13083 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
d62cf62a 13084
e7c84544
ML
13085 /* hw state is inconsistent with the pipe quirk */
13086 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13087 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13088 active = new_crtc_state->active;
6c49f241 13089
e7c84544
ML
13090 I915_STATE_WARN(new_crtc_state->active != active,
13091 "crtc active state doesn't match with hw state "
13092 "(expected %i, found %i)\n", new_crtc_state->active, active);
0e8ffe1b 13093
e7c84544
ML
13094 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13095 "transitional active state does not match atomic hw state "
13096 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
4d20cd86 13097
e7c84544
ML
13098 for_each_encoder_on_crtc(dev, crtc, encoder) {
13099 enum pipe pipe;
4d20cd86 13100
e7c84544
ML
13101 active = encoder->get_hw_state(encoder, &pipe);
13102 I915_STATE_WARN(active != new_crtc_state->active,
13103 "[ENCODER:%i] active %i with crtc active %i\n",
13104 encoder->base.base.id, active, new_crtc_state->active);
4d20cd86 13105
e7c84544
ML
13106 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13107 "Encoder connected to wrong pipe %c\n",
13108 pipe_name(pipe));
4d20cd86 13109
e7c84544
ML
13110 if (active)
13111 encoder->get_config(encoder, pipe_config);
13112 }
53d9f4e9 13113
e7c84544
ML
13114 if (!new_crtc_state->active)
13115 return;
cfb23ed6 13116
e7c84544 13117 intel_pipe_config_sanity_check(dev_priv, pipe_config);
e3b247da 13118
e7c84544
ML
13119 sw_config = to_intel_crtc_state(crtc->state);
13120 if (!intel_pipe_config_compare(dev, sw_config,
13121 pipe_config, false)) {
13122 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13123 intel_dump_pipe_config(intel_crtc, pipe_config,
13124 "[hw state]");
13125 intel_dump_pipe_config(intel_crtc, sw_config,
13126 "[sw state]");
8af6cf88
DV
13127 }
13128}
13129
91d1b4bd 13130static void
c0ead703
ML
13131verify_single_dpll_state(struct drm_i915_private *dev_priv,
13132 struct intel_shared_dpll *pll,
13133 struct drm_crtc *crtc,
13134 struct drm_crtc_state *new_state)
91d1b4bd 13135{
91d1b4bd 13136 struct intel_dpll_hw_state dpll_hw_state;
e7c84544
ML
13137 unsigned crtc_mask;
13138 bool active;
5358901f 13139
e7c84544 13140 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
5358901f 13141
e7c84544 13142 DRM_DEBUG_KMS("%s\n", pll->name);
5358901f 13143
e7c84544 13144 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
5358901f 13145
e7c84544
ML
13146 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13147 I915_STATE_WARN(!pll->on && pll->active_mask,
13148 "pll in active use but not on in sw tracking\n");
13149 I915_STATE_WARN(pll->on && !pll->active_mask,
13150 "pll is on but not used by any active crtc\n");
13151 I915_STATE_WARN(pll->on != active,
13152 "pll on state mismatch (expected %i, found %i)\n",
13153 pll->on, active);
13154 }
5358901f 13155
e7c84544 13156 if (!crtc) {
2dd66ebd 13157 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
e7c84544
ML
13158 "more active pll users than references: %x vs %x\n",
13159 pll->active_mask, pll->config.crtc_mask);
5358901f 13160
e7c84544
ML
13161 return;
13162 }
13163
13164 crtc_mask = 1 << drm_crtc_index(crtc);
13165
13166 if (new_state->active)
13167 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13168 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13169 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13170 else
13171 I915_STATE_WARN(pll->active_mask & crtc_mask,
13172 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13173 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
2dd66ebd 13174
e7c84544
ML
13175 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13176 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13177 crtc_mask, pll->config.crtc_mask);
66e985c0 13178
e7c84544
ML
13179 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13180 &dpll_hw_state,
13181 sizeof(dpll_hw_state)),
13182 "pll hw state mismatch\n");
13183}
13184
13185static void
c0ead703
ML
13186verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13187 struct drm_crtc_state *old_crtc_state,
13188 struct drm_crtc_state *new_crtc_state)
e7c84544
ML
13189{
13190 struct drm_i915_private *dev_priv = dev->dev_private;
13191 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13192 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13193
13194 if (new_state->shared_dpll)
c0ead703 13195 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
e7c84544
ML
13196
13197 if (old_state->shared_dpll &&
13198 old_state->shared_dpll != new_state->shared_dpll) {
13199 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13200 struct intel_shared_dpll *pll = old_state->shared_dpll;
13201
13202 I915_STATE_WARN(pll->active_mask & crtc_mask,
13203 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13204 pipe_name(drm_crtc_index(crtc)));
13205 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13206 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13207 pipe_name(drm_crtc_index(crtc)));
5358901f 13208 }
8af6cf88
DV
13209}
13210
e7c84544 13211static void
c0ead703 13212intel_modeset_verify_crtc(struct drm_crtc *crtc,
e7c84544
ML
13213 struct drm_crtc_state *old_state,
13214 struct drm_crtc_state *new_state)
13215{
5a21b665
DV
13216 if (!needs_modeset(new_state) &&
13217 !to_intel_crtc_state(new_state)->update_pipe)
13218 return;
13219
c0ead703 13220 verify_wm_state(crtc, new_state);
5a21b665 13221 verify_connector_state(crtc->dev, crtc);
c0ead703
ML
13222 verify_crtc_state(crtc, old_state, new_state);
13223 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
e7c84544
ML
13224}
13225
13226static void
c0ead703 13227verify_disabled_dpll_state(struct drm_device *dev)
e7c84544
ML
13228{
13229 struct drm_i915_private *dev_priv = dev->dev_private;
13230 int i;
13231
13232 for (i = 0; i < dev_priv->num_shared_dpll; i++)
c0ead703 13233 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
e7c84544
ML
13234}
13235
13236static void
c0ead703 13237intel_modeset_verify_disabled(struct drm_device *dev)
e7c84544 13238{
c0ead703
ML
13239 verify_encoder_state(dev);
13240 verify_connector_state(dev, NULL);
13241 verify_disabled_dpll_state(dev);
e7c84544
ML
13242}
13243
80715b2f
VS
13244static void update_scanline_offset(struct intel_crtc *crtc)
13245{
13246 struct drm_device *dev = crtc->base.dev;
13247
13248 /*
13249 * The scanline counter increments at the leading edge of hsync.
13250 *
13251 * On most platforms it starts counting from vtotal-1 on the
13252 * first active line. That means the scanline counter value is
13253 * always one less than what we would expect. Ie. just after
13254 * start of vblank, which also occurs at start of hsync (on the
13255 * last active line), the scanline counter will read vblank_start-1.
13256 *
13257 * On gen2 the scanline counter starts counting from 1 instead
13258 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13259 * to keep the value positive), instead of adding one.
13260 *
13261 * On HSW+ the behaviour of the scanline counter depends on the output
13262 * type. For DP ports it behaves like most other platforms, but on HDMI
13263 * there's an extra 1 line difference. So we need to add two instead of
13264 * one to the value.
13265 */
13266 if (IS_GEN2(dev)) {
124abe07 13267 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
80715b2f
VS
13268 int vtotal;
13269
124abe07
VS
13270 vtotal = adjusted_mode->crtc_vtotal;
13271 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
80715b2f
VS
13272 vtotal /= 2;
13273
13274 crtc->scanline_offset = vtotal - 1;
13275 } else if (HAS_DDI(dev) &&
409ee761 13276 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS
13277 crtc->scanline_offset = 2;
13278 } else
13279 crtc->scanline_offset = 1;
13280}
13281
ad421372 13282static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 13283{
225da59b 13284 struct drm_device *dev = state->dev;
ed6739ef 13285 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 13286 struct intel_shared_dpll_config *shared_dpll = NULL;
0a9ab303
ACO
13287 struct drm_crtc *crtc;
13288 struct drm_crtc_state *crtc_state;
0a9ab303 13289 int i;
ed6739ef
ACO
13290
13291 if (!dev_priv->display.crtc_compute_clock)
ad421372 13292 return;
ed6739ef 13293
0a9ab303 13294 for_each_crtc_in_state(state, crtc, crtc_state, i) {
fb1a38a9 13295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8106ddbd
ACO
13296 struct intel_shared_dpll *old_dpll =
13297 to_intel_crtc_state(crtc->state)->shared_dpll;
0a9ab303 13298
fb1a38a9 13299 if (!needs_modeset(crtc_state))
225da59b
ACO
13300 continue;
13301
8106ddbd 13302 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
fb1a38a9 13303
8106ddbd 13304 if (!old_dpll)
fb1a38a9 13305 continue;
0a9ab303 13306
ad421372
ML
13307 if (!shared_dpll)
13308 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 13309
8106ddbd 13310 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
ad421372 13311 }
ed6739ef
ACO
13312}
13313
99d736a2
ML
13314/*
13315 * This implements the workaround described in the "notes" section of the mode
13316 * set sequence documentation. When going from no pipes or single pipe to
13317 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13318 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13319 */
13320static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13321{
13322 struct drm_crtc_state *crtc_state;
13323 struct intel_crtc *intel_crtc;
13324 struct drm_crtc *crtc;
13325 struct intel_crtc_state *first_crtc_state = NULL;
13326 struct intel_crtc_state *other_crtc_state = NULL;
13327 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13328 int i;
13329
13330 /* look at all crtc's that are going to be enabled in during modeset */
13331 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13332 intel_crtc = to_intel_crtc(crtc);
13333
13334 if (!crtc_state->active || !needs_modeset(crtc_state))
13335 continue;
13336
13337 if (first_crtc_state) {
13338 other_crtc_state = to_intel_crtc_state(crtc_state);
13339 break;
13340 } else {
13341 first_crtc_state = to_intel_crtc_state(crtc_state);
13342 first_pipe = intel_crtc->pipe;
13343 }
13344 }
13345
13346 /* No workaround needed? */
13347 if (!first_crtc_state)
13348 return 0;
13349
13350 /* w/a possibly needed, check how many crtc's are already enabled. */
13351 for_each_intel_crtc(state->dev, intel_crtc) {
13352 struct intel_crtc_state *pipe_config;
13353
13354 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13355 if (IS_ERR(pipe_config))
13356 return PTR_ERR(pipe_config);
13357
13358 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13359
13360 if (!pipe_config->base.active ||
13361 needs_modeset(&pipe_config->base))
13362 continue;
13363
13364 /* 2 or more enabled crtcs means no need for w/a */
13365 if (enabled_pipe != INVALID_PIPE)
13366 return 0;
13367
13368 enabled_pipe = intel_crtc->pipe;
13369 }
13370
13371 if (enabled_pipe != INVALID_PIPE)
13372 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13373 else if (other_crtc_state)
13374 other_crtc_state->hsw_workaround_pipe = first_pipe;
13375
13376 return 0;
13377}
13378
27c329ed
ML
13379static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13380{
13381 struct drm_crtc *crtc;
13382 struct drm_crtc_state *crtc_state;
13383 int ret = 0;
13384
13385 /* add all active pipes to the state */
13386 for_each_crtc(state->dev, crtc) {
13387 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13388 if (IS_ERR(crtc_state))
13389 return PTR_ERR(crtc_state);
13390
13391 if (!crtc_state->active || needs_modeset(crtc_state))
13392 continue;
13393
13394 crtc_state->mode_changed = true;
13395
13396 ret = drm_atomic_add_affected_connectors(state, crtc);
13397 if (ret)
13398 break;
13399
13400 ret = drm_atomic_add_affected_planes(state, crtc);
13401 if (ret)
13402 break;
13403 }
13404
13405 return ret;
13406}
13407
c347a676 13408static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd 13409{
565602d7
ML
13410 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13411 struct drm_i915_private *dev_priv = state->dev->dev_private;
13412 struct drm_crtc *crtc;
13413 struct drm_crtc_state *crtc_state;
13414 int ret = 0, i;
054518dd 13415
b359283a
ML
13416 if (!check_digital_port_conflicts(state)) {
13417 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13418 return -EINVAL;
13419 }
13420
565602d7
ML
13421 intel_state->modeset = true;
13422 intel_state->active_crtcs = dev_priv->active_crtcs;
13423
13424 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13425 if (crtc_state->active)
13426 intel_state->active_crtcs |= 1 << i;
13427 else
13428 intel_state->active_crtcs &= ~(1 << i);
8b4a7d05
MR
13429
13430 if (crtc_state->active != crtc->state->active)
13431 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
565602d7
ML
13432 }
13433
054518dd
ACO
13434 /*
13435 * See if the config requires any additional preparation, e.g.
13436 * to adjust global state with pipes off. We need to do this
13437 * here so we can get the modeset_pipe updated config for the new
13438 * mode set on this crtc. For other crtcs we need to use the
13439 * adjusted_mode bits in the crtc directly.
13440 */
27c329ed 13441 if (dev_priv->display.modeset_calc_cdclk) {
c89e39f3 13442 if (!intel_state->cdclk_pll_vco)
63911d72 13443 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
b2045352
VS
13444 if (!intel_state->cdclk_pll_vco)
13445 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
c89e39f3 13446
27c329ed 13447 ret = dev_priv->display.modeset_calc_cdclk(state);
c89e39f3
CT
13448 if (ret < 0)
13449 return ret;
27c329ed 13450
c89e39f3 13451 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
63911d72 13452 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
27c329ed
ML
13453 ret = intel_modeset_all_pipes(state);
13454
13455 if (ret < 0)
054518dd 13456 return ret;
e8788cbc
ML
13457
13458 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13459 intel_state->cdclk, intel_state->dev_cdclk);
27c329ed 13460 } else
1a617b77 13461 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
054518dd 13462
ad421372 13463 intel_modeset_clear_plls(state);
054518dd 13464
565602d7 13465 if (IS_HASWELL(dev_priv))
ad421372 13466 return haswell_mode_set_planes_workaround(state);
99d736a2 13467
ad421372 13468 return 0;
c347a676
ACO
13469}
13470
aa363136
MR
13471/*
13472 * Handle calculation of various watermark data at the end of the atomic check
13473 * phase. The code here should be run after the per-crtc and per-plane 'check'
13474 * handlers to ensure that all derived state has been updated.
13475 */
55994c2c 13476static int calc_watermark_data(struct drm_atomic_state *state)
aa363136
MR
13477{
13478 struct drm_device *dev = state->dev;
98d39494 13479 struct drm_i915_private *dev_priv = to_i915(dev);
98d39494
MR
13480
13481 /* Is there platform-specific watermark information to calculate? */
13482 if (dev_priv->display.compute_global_watermarks)
55994c2c
MR
13483 return dev_priv->display.compute_global_watermarks(state);
13484
13485 return 0;
aa363136
MR
13486}
13487
74c090b1
ML
13488/**
13489 * intel_atomic_check - validate state object
13490 * @dev: drm device
13491 * @state: state to validate
13492 */
13493static int intel_atomic_check(struct drm_device *dev,
13494 struct drm_atomic_state *state)
c347a676 13495{
dd8b3bdb 13496 struct drm_i915_private *dev_priv = to_i915(dev);
aa363136 13497 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
c347a676
ACO
13498 struct drm_crtc *crtc;
13499 struct drm_crtc_state *crtc_state;
13500 int ret, i;
61333b60 13501 bool any_ms = false;
c347a676 13502
74c090b1 13503 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO
13504 if (ret)
13505 return ret;
13506
c347a676 13507 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML
13508 struct intel_crtc_state *pipe_config =
13509 to_intel_crtc_state(crtc_state);
1ed51de9
DV
13510
13511 /* Catch I915_MODE_FLAG_INHERITED */
13512 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13513 crtc_state->mode_changed = true;
cfb23ed6 13514
af4a879e 13515 if (!needs_modeset(crtc_state))
c347a676
ACO
13516 continue;
13517
af4a879e
DV
13518 if (!crtc_state->enable) {
13519 any_ms = true;
cfb23ed6 13520 continue;
af4a879e 13521 }
cfb23ed6 13522
26495481
DV
13523 /* FIXME: For only active_changed we shouldn't need to do any
13524 * state recomputation at all. */
13525
1ed51de9
DV
13526 ret = drm_atomic_add_affected_connectors(state, crtc);
13527 if (ret)
13528 return ret;
b359283a 13529
cfb23ed6 13530 ret = intel_modeset_pipe_config(crtc, pipe_config);
25aa1c39
ML
13531 if (ret) {
13532 intel_dump_pipe_config(to_intel_crtc(crtc),
13533 pipe_config, "[failed]");
c347a676 13534 return ret;
25aa1c39 13535 }
c347a676 13536
73831236 13537 if (i915.fastboot &&
dd8b3bdb 13538 intel_pipe_config_compare(dev,
cfb23ed6 13539 to_intel_crtc_state(crtc->state),
1ed51de9 13540 pipe_config, true)) {
26495481 13541 crtc_state->mode_changed = false;
bfd16b2a 13542 to_intel_crtc_state(crtc_state)->update_pipe = true;
26495481
DV
13543 }
13544
af4a879e 13545 if (needs_modeset(crtc_state))
26495481 13546 any_ms = true;
cfb23ed6 13547
af4a879e
DV
13548 ret = drm_atomic_add_affected_planes(state, crtc);
13549 if (ret)
13550 return ret;
61333b60 13551
26495481
DV
13552 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13553 needs_modeset(crtc_state) ?
13554 "[modeset]" : "[fastset]");
c347a676
ACO
13555 }
13556
61333b60
ML
13557 if (any_ms) {
13558 ret = intel_modeset_checks(state);
13559
13560 if (ret)
13561 return ret;
27c329ed 13562 } else
dd8b3bdb 13563 intel_state->cdclk = dev_priv->cdclk_freq;
76305b1a 13564
dd8b3bdb 13565 ret = drm_atomic_helper_check_planes(dev, state);
aa363136
MR
13566 if (ret)
13567 return ret;
13568
f51be2e0 13569 intel_fbc_choose_crtc(dev_priv, state);
55994c2c 13570 return calc_watermark_data(state);
054518dd
ACO
13571}
13572
5008e874
ML
13573static int intel_atomic_prepare_commit(struct drm_device *dev,
13574 struct drm_atomic_state *state,
81072bfd 13575 bool nonblock)
5008e874 13576{
7580d774
ML
13577 struct drm_i915_private *dev_priv = dev->dev_private;
13578 struct drm_plane_state *plane_state;
5008e874 13579 struct drm_crtc_state *crtc_state;
7580d774 13580 struct drm_plane *plane;
5008e874
ML
13581 struct drm_crtc *crtc;
13582 int i, ret;
13583
5a21b665
DV
13584 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13585 if (state->legacy_cursor_update)
a6747b73
ML
13586 continue;
13587
5a21b665
DV
13588 ret = intel_crtc_wait_for_pending_flips(crtc);
13589 if (ret)
13590 return ret;
5008e874 13591
5a21b665
DV
13592 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13593 flush_workqueue(dev_priv->wq);
d55dbd06
ML
13594 }
13595
f935675f
ML
13596 ret = mutex_lock_interruptible(&dev->struct_mutex);
13597 if (ret)
13598 return ret;
13599
5008e874 13600 ret = drm_atomic_helper_prepare_planes(dev, state);
f7e5838b 13601 mutex_unlock(&dev->struct_mutex);
7580d774 13602
21daaeee 13603 if (!ret && !nonblock) {
7580d774
ML
13604 for_each_plane_in_state(state, plane, plane_state, i) {
13605 struct intel_plane_state *intel_plane_state =
13606 to_intel_plane_state(plane_state);
13607
13608 if (!intel_plane_state->wait_req)
13609 continue;
13610
13611 ret = __i915_wait_request(intel_plane_state->wait_req,
299259a3 13612 true, NULL, NULL);
f7e5838b 13613 if (ret) {
f4457ae7
CW
13614 /* Any hang should be swallowed by the wait */
13615 WARN_ON(ret == -EIO);
f7e5838b
CW
13616 mutex_lock(&dev->struct_mutex);
13617 drm_atomic_helper_cleanup_planes(dev, state);
13618 mutex_unlock(&dev->struct_mutex);
7580d774 13619 break;
f7e5838b 13620 }
7580d774 13621 }
7580d774 13622 }
5008e874
ML
13623
13624 return ret;
13625}
13626
a2991414
ML
13627u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13628{
13629 struct drm_device *dev = crtc->base.dev;
13630
13631 if (!dev->max_vblank_count)
13632 return drm_accurate_vblank_count(&crtc->base);
13633
13634 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13635}
13636
5a21b665
DV
13637static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13638 struct drm_i915_private *dev_priv,
13639 unsigned crtc_mask)
e8861675 13640{
5a21b665
DV
13641 unsigned last_vblank_count[I915_MAX_PIPES];
13642 enum pipe pipe;
13643 int ret;
e8861675 13644
5a21b665
DV
13645 if (!crtc_mask)
13646 return;
e8861675 13647
5a21b665
DV
13648 for_each_pipe(dev_priv, pipe) {
13649 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e8861675 13650
5a21b665 13651 if (!((1 << pipe) & crtc_mask))
e8861675
ML
13652 continue;
13653
5a21b665
DV
13654 ret = drm_crtc_vblank_get(crtc);
13655 if (WARN_ON(ret != 0)) {
13656 crtc_mask &= ~(1 << pipe);
13657 continue;
e8861675
ML
13658 }
13659
5a21b665 13660 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
e8861675
ML
13661 }
13662
5a21b665
DV
13663 for_each_pipe(dev_priv, pipe) {
13664 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13665 long lret;
e8861675 13666
5a21b665
DV
13667 if (!((1 << pipe) & crtc_mask))
13668 continue;
d55dbd06 13669
5a21b665
DV
13670 lret = wait_event_timeout(dev->vblank[pipe].queue,
13671 last_vblank_count[pipe] !=
13672 drm_crtc_vblank_count(crtc),
13673 msecs_to_jiffies(50));
d55dbd06 13674
5a21b665 13675 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
d55dbd06 13676
5a21b665 13677 drm_crtc_vblank_put(crtc);
d55dbd06
ML
13678 }
13679}
13680
5a21b665 13681static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
a6747b73 13682{
5a21b665
DV
13683 /* fb updated, need to unpin old fb */
13684 if (crtc_state->fb_changed)
13685 return true;
a6747b73 13686
5a21b665
DV
13687 /* wm changes, need vblank before final wm's */
13688 if (crtc_state->update_wm_post)
13689 return true;
a6747b73 13690
5a21b665
DV
13691 /*
13692 * cxsr is re-enabled after vblank.
13693 * This is already handled by crtc_state->update_wm_post,
13694 * but added for clarity.
13695 */
13696 if (crtc_state->disable_cxsr)
13697 return true;
a6747b73 13698
5a21b665 13699 return false;
e8861675
ML
13700}
13701
94f05024 13702static void intel_atomic_commit_tail(struct drm_atomic_state *state)
a6778b3c 13703{
94f05024 13704 struct drm_device *dev = state->dev;
565602d7 13705 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
fbee40df 13706 struct drm_i915_private *dev_priv = dev->dev_private;
29ceb0e6 13707 struct drm_crtc_state *old_crtc_state;
7580d774 13708 struct drm_crtc *crtc;
5a21b665 13709 struct intel_crtc_state *intel_cstate;
94f05024
DV
13710 struct drm_plane *plane;
13711 struct drm_plane_state *plane_state;
5a21b665
DV
13712 bool hw_check = intel_state->modeset;
13713 unsigned long put_domains[I915_MAX_PIPES] = {};
13714 unsigned crtc_vblank_mask = 0;
94f05024 13715 int i, ret;
a6778b3c 13716
94f05024
DV
13717 for_each_plane_in_state(state, plane, plane_state, i) {
13718 struct intel_plane_state *intel_plane_state =
13719 to_intel_plane_state(plane_state);
ea0000f0 13720
94f05024
DV
13721 if (!intel_plane_state->wait_req)
13722 continue;
d4afb8cc 13723
94f05024
DV
13724 ret = __i915_wait_request(intel_plane_state->wait_req,
13725 true, NULL, NULL);
13726 /* EIO should be eaten, and we can't get interrupted in the
13727 * worker, and blocking commits have waited already. */
13728 WARN_ON(ret);
13729 }
1c5e19f8 13730
ea0000f0
DV
13731 drm_atomic_helper_wait_for_dependencies(state);
13732
565602d7
ML
13733 if (intel_state->modeset) {
13734 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13735 sizeof(intel_state->min_pixclk));
13736 dev_priv->active_crtcs = intel_state->active_crtcs;
1a617b77 13737 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
5a21b665
DV
13738
13739 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
565602d7
ML
13740 }
13741
29ceb0e6 13742 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
a539205a
ML
13743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13744
5a21b665
DV
13745 if (needs_modeset(crtc->state) ||
13746 to_intel_crtc_state(crtc->state)->update_pipe) {
13747 hw_check = true;
13748
13749 put_domains[to_intel_crtc(crtc)->pipe] =
13750 modeset_get_crtc_power_domains(crtc,
13751 to_intel_crtc_state(crtc->state));
13752 }
13753
61333b60
ML
13754 if (!needs_modeset(crtc->state))
13755 continue;
13756
29ceb0e6 13757 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
460da916 13758
29ceb0e6
VS
13759 if (old_crtc_state->active) {
13760 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
a539205a 13761 dev_priv->display.crtc_disable(crtc);
eddfcbcd 13762 intel_crtc->active = false;
58f9c0bc 13763 intel_fbc_disable(intel_crtc);
eddfcbcd 13764 intel_disable_shared_dpll(intel_crtc);
9bbc8258
VS
13765
13766 /*
13767 * Underruns don't always raise
13768 * interrupts, so check manually.
13769 */
13770 intel_check_cpu_fifo_underruns(dev_priv);
13771 intel_check_pch_fifo_underruns(dev_priv);
b9001114
ML
13772
13773 if (!crtc->state->active)
13774 intel_update_watermarks(crtc);
a539205a 13775 }
b8cecdf5 13776 }
7758a113 13777
ea9d758d
DV
13778 /* Only after disabling all output pipelines that will be changed can we
13779 * update the the output configuration. */
4740b0f2 13780 intel_modeset_update_crtc_state(state);
f6e5b160 13781
565602d7 13782 if (intel_state->modeset) {
4740b0f2 13783 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
33c8df89
ML
13784
13785 if (dev_priv->display.modeset_commit_cdclk &&
c89e39f3 13786 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
63911d72 13787 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
33c8df89 13788 dev_priv->display.modeset_commit_cdclk(state);
f6d1973d 13789
c0ead703 13790 intel_modeset_verify_disabled(dev);
4740b0f2 13791 }
47fab737 13792
a6778b3c 13793 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
29ceb0e6 13794 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
f6ac4b2a
ML
13795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13796 bool modeset = needs_modeset(crtc->state);
5a21b665
DV
13797 struct intel_crtc_state *pipe_config =
13798 to_intel_crtc_state(crtc->state);
9f836f90 13799
f6ac4b2a 13800 if (modeset && crtc->state->active) {
a539205a
ML
13801 update_scanline_offset(to_intel_crtc(crtc));
13802 dev_priv->display.crtc_enable(crtc);
13803 }
80715b2f 13804
1f7528c4
DV
13805 /* Complete events for now disable pipes here. */
13806 if (modeset && !crtc->state->active && crtc->state->event) {
13807 spin_lock_irq(&dev->event_lock);
13808 drm_crtc_send_vblank_event(crtc, crtc->state->event);
13809 spin_unlock_irq(&dev->event_lock);
13810
13811 crtc->state->event = NULL;
13812 }
13813
f6ac4b2a 13814 if (!modeset)
29ceb0e6 13815 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
f6ac4b2a 13816
5a21b665
DV
13817 if (crtc->state->active &&
13818 drm_atomic_get_existing_plane_state(state, crtc->primary))
faf68d92 13819 intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
5a21b665 13820
1f7528c4 13821 if (crtc->state->active)
5a21b665 13822 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
f6d1973d 13823
5a21b665
DV
13824 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13825 crtc_vblank_mask |= 1 << i;
177246a8
MR
13826 }
13827
94f05024
DV
13828 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13829 * already, but still need the state for the delayed optimization. To
13830 * fix this:
13831 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13832 * - schedule that vblank worker _before_ calling hw_done
13833 * - at the start of commit_tail, cancel it _synchrously
13834 * - switch over to the vblank wait helper in the core after that since
13835 * we don't need out special handling any more.
13836 */
5a21b665
DV
13837 if (!state->legacy_cursor_update)
13838 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13839
13840 /*
13841 * Now that the vblank has passed, we can go ahead and program the
13842 * optimal watermarks on platforms that need two-step watermark
13843 * programming.
13844 *
13845 * TODO: Move this (and other cleanup) to an async worker eventually.
13846 */
13847 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13848 intel_cstate = to_intel_crtc_state(crtc->state);
13849
13850 if (dev_priv->display.optimize_watermarks)
13851 dev_priv->display.optimize_watermarks(intel_cstate);
13852 }
13853
13854 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13855 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13856
13857 if (put_domains[i])
13858 modeset_put_power_domains(dev_priv, put_domains[i]);
13859
13860 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13861 }
13862
94f05024
DV
13863 drm_atomic_helper_commit_hw_done(state);
13864
5a21b665
DV
13865 if (intel_state->modeset)
13866 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13867
13868 mutex_lock(&dev->struct_mutex);
13869 drm_atomic_helper_cleanup_planes(dev, state);
13870 mutex_unlock(&dev->struct_mutex);
13871
ea0000f0
DV
13872 drm_atomic_helper_commit_cleanup_done(state);
13873
ee165b1a 13874 drm_atomic_state_free(state);
f30da187 13875
75714940
MK
13876 /* As one of the primary mmio accessors, KMS has a high likelihood
13877 * of triggering bugs in unclaimed access. After we finish
13878 * modesetting, see if an error has been flagged, and if so
13879 * enable debugging for the next modeset - and hope we catch
13880 * the culprit.
13881 *
13882 * XXX note that we assume display power is on at this point.
13883 * This might hold true now but we need to add pm helper to check
13884 * unclaimed only when the hardware is on, as atomic commits
13885 * can happen also when the device is completely off.
13886 */
13887 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
94f05024
DV
13888}
13889
13890static void intel_atomic_commit_work(struct work_struct *work)
13891{
13892 struct drm_atomic_state *state = container_of(work,
13893 struct drm_atomic_state,
13894 commit_work);
13895 intel_atomic_commit_tail(state);
13896}
13897
6c9c1b38
DV
13898static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13899{
13900 struct drm_plane_state *old_plane_state;
13901 struct drm_plane *plane;
13902 struct drm_i915_gem_object *obj, *old_obj;
13903 struct intel_plane *intel_plane;
13904 int i;
13905
13906 mutex_lock(&state->dev->struct_mutex);
13907 for_each_plane_in_state(state, plane, old_plane_state, i) {
13908 obj = intel_fb_obj(plane->state->fb);
13909 old_obj = intel_fb_obj(old_plane_state->fb);
13910 intel_plane = to_intel_plane(plane);
13911
13912 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13913 }
13914 mutex_unlock(&state->dev->struct_mutex);
13915}
13916
94f05024
DV
13917/**
13918 * intel_atomic_commit - commit validated state object
13919 * @dev: DRM device
13920 * @state: the top-level driver state object
13921 * @nonblock: nonblocking commit
13922 *
13923 * This function commits a top-level state object that has been validated
13924 * with drm_atomic_helper_check().
13925 *
13926 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13927 * nonblocking commits are only safe for pure plane updates. Everything else
13928 * should work though.
13929 *
13930 * RETURNS
13931 * Zero for success or -errno.
13932 */
13933static int intel_atomic_commit(struct drm_device *dev,
13934 struct drm_atomic_state *state,
13935 bool nonblock)
13936{
13937 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13938 struct drm_i915_private *dev_priv = dev->dev_private;
13939 int ret = 0;
13940
13941 if (intel_state->modeset && nonblock) {
13942 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
13943 return -EINVAL;
13944 }
13945
13946 ret = drm_atomic_helper_setup_commit(state, nonblock);
13947 if (ret)
13948 return ret;
13949
13950 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13951
13952 ret = intel_atomic_prepare_commit(dev, state, nonblock);
13953 if (ret) {
13954 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13955 return ret;
13956 }
13957
13958 drm_atomic_helper_swap_state(state, true);
13959 dev_priv->wm.distrust_bios_wm = false;
13960 dev_priv->wm.skl_results = intel_state->wm_results;
13961 intel_shared_dpll_commit(state);
6c9c1b38 13962 intel_atomic_track_fbs(state);
94f05024
DV
13963
13964 if (nonblock)
13965 queue_work(system_unbound_wq, &state->commit_work);
13966 else
13967 intel_atomic_commit_tail(state);
75714940 13968
74c090b1 13969 return 0;
7f27126e
JB
13970}
13971
c0c36b94
CW
13972void intel_crtc_restore_mode(struct drm_crtc *crtc)
13973{
83a57153
ACO
13974 struct drm_device *dev = crtc->dev;
13975 struct drm_atomic_state *state;
e694eb02 13976 struct drm_crtc_state *crtc_state;
2bfb4627 13977 int ret;
83a57153
ACO
13978
13979 state = drm_atomic_state_alloc(dev);
13980 if (!state) {
78108b7c
VS
13981 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13982 crtc->base.id, crtc->name);
83a57153
ACO
13983 return;
13984 }
13985
e694eb02 13986 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13987
e694eb02
ML
13988retry:
13989 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13990 ret = PTR_ERR_OR_ZERO(crtc_state);
13991 if (!ret) {
13992 if (!crtc_state->active)
13993 goto out;
83a57153 13994
e694eb02 13995 crtc_state->mode_changed = true;
74c090b1 13996 ret = drm_atomic_commit(state);
83a57153
ACO
13997 }
13998
e694eb02
ML
13999 if (ret == -EDEADLK) {
14000 drm_atomic_state_clear(state);
14001 drm_modeset_backoff(state->acquire_ctx);
14002 goto retry;
4ed9fb37 14003 }
4be07317 14004
2bfb4627 14005 if (ret)
e694eb02 14006out:
2bfb4627 14007 drm_atomic_state_free(state);
c0c36b94
CW
14008}
14009
25c5b266
DV
14010#undef for_each_intel_crtc_masked
14011
f6e5b160 14012static const struct drm_crtc_funcs intel_crtc_funcs = {
82cf435b 14013 .gamma_set = drm_atomic_helper_legacy_gamma_set,
74c090b1 14014 .set_config = drm_atomic_helper_set_config,
82cf435b 14015 .set_property = drm_atomic_helper_crtc_set_property,
f6e5b160 14016 .destroy = intel_crtc_destroy,
527b6abe 14017 .page_flip = intel_crtc_page_flip,
1356837e
MR
14018 .atomic_duplicate_state = intel_crtc_duplicate_state,
14019 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW
14020};
14021
6beb8c23
MR
14022/**
14023 * intel_prepare_plane_fb - Prepare fb for usage on plane
14024 * @plane: drm plane to prepare for
14025 * @fb: framebuffer to prepare for presentation
14026 *
14027 * Prepares a framebuffer for usage on a display plane. Generally this
14028 * involves pinning the underlying object and updating the frontbuffer tracking
14029 * bits. Some older platforms need special physical address handling for
14030 * cursor planes.
14031 *
f935675f
ML
14032 * Must be called with struct_mutex held.
14033 *
6beb8c23
MR
14034 * Returns 0 on success, negative error code on failure.
14035 */
14036int
14037intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee 14038 const struct drm_plane_state *new_state)
465c120c
MR
14039{
14040 struct drm_device *dev = plane->dev;
844f9111 14041 struct drm_framebuffer *fb = new_state->fb;
6beb8c23 14042 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1ee49399 14043 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
c37efb99 14044 struct reservation_object *resv;
6beb8c23 14045 int ret = 0;
465c120c 14046
1ee49399 14047 if (!obj && !old_obj)
465c120c
MR
14048 return 0;
14049
5008e874
ML
14050 if (old_obj) {
14051 struct drm_crtc_state *crtc_state =
14052 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14053
14054 /* Big Hammer, we also need to ensure that any pending
14055 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14056 * current scanout is retired before unpinning the old
14057 * framebuffer. Note that we rely on userspace rendering
14058 * into the buffer attached to the pipe they are waiting
14059 * on. If not, userspace generates a GPU hang with IPEHR
14060 * point to the MI_WAIT_FOR_EVENT.
14061 *
14062 * This should only fail upon a hung GPU, in which case we
14063 * can safely continue.
14064 */
14065 if (needs_modeset(crtc_state))
14066 ret = i915_gem_object_wait_rendering(old_obj, true);
f4457ae7
CW
14067 if (ret) {
14068 /* GPU hangs should have been swallowed by the wait */
14069 WARN_ON(ret == -EIO);
f935675f 14070 return ret;
f4457ae7 14071 }
5008e874
ML
14072 }
14073
c37efb99
CW
14074 if (!obj)
14075 return 0;
14076
5a21b665 14077 /* For framebuffer backed by dmabuf, wait for fence */
c37efb99
CW
14078 resv = i915_gem_object_get_dmabuf_resv(obj);
14079 if (resv) {
5a21b665
DV
14080 long lret;
14081
c37efb99 14082 lret = reservation_object_wait_timeout_rcu(resv, false, true,
5a21b665
DV
14083 MAX_SCHEDULE_TIMEOUT);
14084 if (lret == -ERESTARTSYS)
14085 return lret;
14086
14087 WARN(lret < 0, "waiting returns %li\n", lret);
14088 }
14089
c37efb99 14090 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
6beb8c23
MR
14091 INTEL_INFO(dev)->cursor_needs_physical) {
14092 int align = IS_I830(dev) ? 16 * 1024 : 256;
14093 ret = i915_gem_object_attach_phys(obj, align);
14094 if (ret)
14095 DRM_DEBUG_KMS("failed to attach phys object\n");
14096 } else {
3465c580 14097 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
6beb8c23 14098 }
465c120c 14099
c37efb99 14100 if (ret == 0) {
6c9c1b38
DV
14101 struct intel_plane_state *plane_state =
14102 to_intel_plane_state(new_state);
7580d774 14103
6c9c1b38
DV
14104 i915_gem_request_assign(&plane_state->wait_req,
14105 obj->last_write_req);
7580d774 14106 }
fdd508a6 14107
6beb8c23
MR
14108 return ret;
14109}
14110
38f3ce3a
MR
14111/**
14112 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14113 * @plane: drm plane to clean up for
14114 * @fb: old framebuffer that was on plane
14115 *
14116 * Cleans up a framebuffer that has just been removed from a plane.
f935675f
ML
14117 *
14118 * Must be called with struct_mutex held.
38f3ce3a
MR
14119 */
14120void
14121intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee 14122 const struct drm_plane_state *old_state)
38f3ce3a
MR
14123{
14124 struct drm_device *dev = plane->dev;
7580d774 14125 struct intel_plane_state *old_intel_state;
1ee49399
ML
14126 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14127 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
38f3ce3a 14128
7580d774
ML
14129 old_intel_state = to_intel_plane_state(old_state);
14130
1ee49399 14131 if (!obj && !old_obj)
38f3ce3a
MR
14132 return;
14133
1ee49399
ML
14134 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14135 !INTEL_INFO(dev)->cursor_needs_physical))
3465c580 14136 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
1ee49399 14137
7580d774 14138 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
465c120c
MR
14139}
14140
6156a456
CK
14141int
14142skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14143{
14144 int max_scale;
14145 struct drm_device *dev;
14146 struct drm_i915_private *dev_priv;
14147 int crtc_clock, cdclk;
14148
bf8a0af0 14149 if (!intel_crtc || !crtc_state->base.enable)
6156a456
CK
14150 return DRM_PLANE_HELPER_NO_SCALING;
14151
14152 dev = intel_crtc->base.dev;
14153 dev_priv = dev->dev_private;
14154 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 14155 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456 14156
54bf1ce6 14157 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
6156a456
CK
14158 return DRM_PLANE_HELPER_NO_SCALING;
14159
14160 /*
14161 * skl max scale is lower of:
14162 * close to 3 but not 3, -1 is for that purpose
14163 * or
14164 * cdclk/crtc_clock
14165 */
14166 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14167
14168 return max_scale;
14169}
14170
465c120c 14171static int
3c692a41 14172intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 14173 struct intel_crtc_state *crtc_state,
3c692a41
GP
14174 struct intel_plane_state *state)
14175{
2b875c22
MR
14176 struct drm_crtc *crtc = state->base.crtc;
14177 struct drm_framebuffer *fb = state->base.fb;
6156a456 14178 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML
14179 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14180 bool can_position = false;
465c120c 14181
693bdc28
VS
14182 if (INTEL_INFO(plane->dev)->gen >= 9) {
14183 /* use scaler when colorkey is not required */
14184 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14185 min_scale = 1;
14186 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14187 }
d8106366 14188 can_position = true;
6156a456 14189 }
d8106366 14190
061e4b8d
ML
14191 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14192 &state->dst, &state->clip,
9b8b013d 14193 state->base.rotation,
da20eabd
ML
14194 min_scale, max_scale,
14195 can_position, true,
14196 &state->visible);
14af293f
GP
14197}
14198
5a21b665
DV
14199static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14200 struct drm_crtc_state *old_crtc_state)
14201{
14202 struct drm_device *dev = crtc->dev;
14203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14204 struct intel_crtc_state *old_intel_state =
14205 to_intel_crtc_state(old_crtc_state);
14206 bool modeset = needs_modeset(crtc->state);
14207
14208 /* Perform vblank evasion around commit operation */
14209 intel_pipe_update_start(intel_crtc);
14210
14211 if (modeset)
14212 return;
14213
14214 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14215 intel_color_set_csc(crtc->state);
14216 intel_color_load_luts(crtc->state);
14217 }
14218
14219 if (to_intel_crtc_state(crtc->state)->update_pipe)
14220 intel_update_pipe_config(intel_crtc, old_intel_state);
14221 else if (INTEL_INFO(dev)->gen >= 9)
14222 skl_detach_scalers(intel_crtc);
14223}
14224
14225static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14226 struct drm_crtc_state *old_crtc_state)
14227{
14228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14229
14230 intel_pipe_update_end(intel_crtc, NULL);
14231}
14232
cf4c7c12 14233/**
4a3b8769
MR
14234 * intel_plane_destroy - destroy a plane
14235 * @plane: plane to destroy
cf4c7c12 14236 *
4a3b8769
MR
14237 * Common destruction function for all types of planes (primary, cursor,
14238 * sprite).
cf4c7c12 14239 */
4a3b8769 14240void intel_plane_destroy(struct drm_plane *plane)
465c120c 14241{
69ae561f
VS
14242 if (!plane)
14243 return;
14244
465c120c 14245 drm_plane_cleanup(plane);
69ae561f 14246 kfree(to_intel_plane(plane));
465c120c
MR
14247}
14248
65a3fea0 14249const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR
14250 .update_plane = drm_atomic_helper_update_plane,
14251 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 14252 .destroy = intel_plane_destroy,
c196e1d6 14253 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR
14254 .atomic_get_property = intel_plane_atomic_get_property,
14255 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR
14256 .atomic_duplicate_state = intel_plane_duplicate_state,
14257 .atomic_destroy_state = intel_plane_destroy_state,
14258
465c120c
MR
14259};
14260
14261static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14262 int pipe)
14263{
fca0ce2a
VS
14264 struct intel_plane *primary = NULL;
14265 struct intel_plane_state *state = NULL;
465c120c 14266 const uint32_t *intel_primary_formats;
45e3743a 14267 unsigned int num_formats;
fca0ce2a 14268 int ret;
465c120c
MR
14269
14270 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
fca0ce2a
VS
14271 if (!primary)
14272 goto fail;
465c120c 14273
8e7d688b 14274 state = intel_create_plane_state(&primary->base);
fca0ce2a
VS
14275 if (!state)
14276 goto fail;
8e7d688b 14277 primary->base.state = &state->base;
ea2c67bb 14278
465c120c
MR
14279 primary->can_scale = false;
14280 primary->max_downscale = 1;
6156a456
CK
14281 if (INTEL_INFO(dev)->gen >= 9) {
14282 primary->can_scale = true;
af99ceda 14283 state->scaler_id = -1;
6156a456 14284 }
465c120c
MR
14285 primary->pipe = pipe;
14286 primary->plane = pipe;
a9ff8714 14287 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179 14288 primary->check_plane = intel_check_primary_plane;
465c120c
MR
14289 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14290 primary->plane = !pipe;
14291
6c0fd451
DL
14292 if (INTEL_INFO(dev)->gen >= 9) {
14293 intel_primary_formats = skl_primary_formats;
14294 num_formats = ARRAY_SIZE(skl_primary_formats);
a8d201af
ML
14295
14296 primary->update_plane = skylake_update_primary_plane;
14297 primary->disable_plane = skylake_disable_primary_plane;
14298 } else if (HAS_PCH_SPLIT(dev)) {
14299 intel_primary_formats = i965_primary_formats;
14300 num_formats = ARRAY_SIZE(i965_primary_formats);
14301
14302 primary->update_plane = ironlake_update_primary_plane;
14303 primary->disable_plane = i9xx_disable_primary_plane;
6c0fd451 14304 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL
14305 intel_primary_formats = i965_primary_formats;
14306 num_formats = ARRAY_SIZE(i965_primary_formats);
a8d201af
ML
14307
14308 primary->update_plane = i9xx_update_primary_plane;
14309 primary->disable_plane = i9xx_disable_primary_plane;
6c0fd451
DL
14310 } else {
14311 intel_primary_formats = i8xx_primary_formats;
14312 num_formats = ARRAY_SIZE(i8xx_primary_formats);
a8d201af
ML
14313
14314 primary->update_plane = i9xx_update_primary_plane;
14315 primary->disable_plane = i9xx_disable_primary_plane;
465c120c
MR
14316 }
14317
38573dc1
VS
14318 if (INTEL_INFO(dev)->gen >= 9)
14319 ret = drm_universal_plane_init(dev, &primary->base, 0,
14320 &intel_plane_funcs,
14321 intel_primary_formats, num_formats,
14322 DRM_PLANE_TYPE_PRIMARY,
14323 "plane 1%c", pipe_name(pipe));
14324 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14325 ret = drm_universal_plane_init(dev, &primary->base, 0,
14326 &intel_plane_funcs,
14327 intel_primary_formats, num_formats,
14328 DRM_PLANE_TYPE_PRIMARY,
14329 "primary %c", pipe_name(pipe));
14330 else
14331 ret = drm_universal_plane_init(dev, &primary->base, 0,
14332 &intel_plane_funcs,
14333 intel_primary_formats, num_formats,
14334 DRM_PLANE_TYPE_PRIMARY,
14335 "plane %c", plane_name(primary->plane));
fca0ce2a
VS
14336 if (ret)
14337 goto fail;
48404c1e 14338
3b7a5119
SJ
14339 if (INTEL_INFO(dev)->gen >= 4)
14340 intel_create_rotation_property(dev, primary);
48404c1e 14341
ea2c67bb
MR
14342 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14343
465c120c 14344 return &primary->base;
fca0ce2a
VS
14345
14346fail:
14347 kfree(state);
14348 kfree(primary);
14349
14350 return NULL;
465c120c
MR
14351}
14352
3b7a5119
SJ
14353void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14354{
14355 if (!dev->mode_config.rotation_property) {
14356 unsigned long flags = BIT(DRM_ROTATE_0) |
14357 BIT(DRM_ROTATE_180);
14358
14359 if (INTEL_INFO(dev)->gen >= 9)
14360 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14361
14362 dev->mode_config.rotation_property =
14363 drm_mode_create_rotation_property(dev, flags);
14364 }
14365 if (dev->mode_config.rotation_property)
14366 drm_object_attach_property(&plane->base.base,
14367 dev->mode_config.rotation_property,
14368 plane->base.state->rotation);
14369}
14370
3d7d6510 14371static int
852e787c 14372intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 14373 struct intel_crtc_state *crtc_state,
852e787c 14374 struct intel_plane_state *state)
3d7d6510 14375{
061e4b8d 14376 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 14377 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 14378 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
b29ec92c 14379 enum pipe pipe = to_intel_plane(plane)->pipe;
757f9a3e
GP
14380 unsigned stride;
14381 int ret;
3d7d6510 14382
061e4b8d
ML
14383 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14384 &state->dst, &state->clip,
9b8b013d 14385 state->base.rotation,
3d7d6510
MR
14386 DRM_PLANE_HELPER_NO_SCALING,
14387 DRM_PLANE_HELPER_NO_SCALING,
852e787c 14388 true, true, &state->visible);
757f9a3e
GP
14389 if (ret)
14390 return ret;
14391
757f9a3e
GP
14392 /* if we want to turn off the cursor ignore width and height */
14393 if (!obj)
da20eabd 14394 return 0;
757f9a3e 14395
757f9a3e 14396 /* Check for which cursor types we support */
061e4b8d 14397 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR
14398 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14399 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP
14400 return -EINVAL;
14401 }
14402
ea2c67bb
MR
14403 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14404 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP
14405 DRM_DEBUG_KMS("buffer is too small\n");
14406 return -ENOMEM;
14407 }
14408
3a656b54 14409 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 14410 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 14411 return -EINVAL;
32b7eeec
MR
14412 }
14413
b29ec92c
VS
14414 /*
14415 * There's something wrong with the cursor on CHV pipe C.
14416 * If it straddles the left edge of the screen then
14417 * moving it away from the edge or disabling it often
14418 * results in a pipe underrun, and often that can lead to
14419 * dead pipe (constant underrun reported, and it scans
14420 * out just a solid color). To recover from that, the
14421 * display power well must be turned off and on again.
14422 * Refuse the put the cursor into that compromised position.
14423 */
14424 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14425 state->visible && state->base.crtc_x < 0) {
14426 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14427 return -EINVAL;
14428 }
14429
da20eabd 14430 return 0;
852e787c 14431}
3d7d6510 14432
a8ad0d8e
ML
14433static void
14434intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 14435 struct drm_crtc *crtc)
a8ad0d8e 14436{
f2858021
ML
14437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14438
14439 intel_crtc->cursor_addr = 0;
55a08b3f 14440 intel_crtc_update_cursor(crtc, NULL);
a8ad0d8e
ML
14441}
14442
f4a2cf29 14443static void
55a08b3f
ML
14444intel_update_cursor_plane(struct drm_plane *plane,
14445 const struct intel_crtc_state *crtc_state,
14446 const struct intel_plane_state *state)
852e787c 14447{
55a08b3f
ML
14448 struct drm_crtc *crtc = crtc_state->base.crtc;
14449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb 14450 struct drm_device *dev = plane->dev;
2b875c22 14451 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 14452 uint32_t addr;
852e787c 14453
f4a2cf29 14454 if (!obj)
a912f12f 14455 addr = 0;
f4a2cf29 14456 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 14457 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 14458 else
a912f12f 14459 addr = obj->phys_handle->busaddr;
852e787c 14460
a912f12f 14461 intel_crtc->cursor_addr = addr;
55a08b3f 14462 intel_crtc_update_cursor(crtc, state);
852e787c
GP
14463}
14464
3d7d6510
MR
14465static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14466 int pipe)
14467{
fca0ce2a
VS
14468 struct intel_plane *cursor = NULL;
14469 struct intel_plane_state *state = NULL;
14470 int ret;
3d7d6510
MR
14471
14472 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
fca0ce2a
VS
14473 if (!cursor)
14474 goto fail;
3d7d6510 14475
8e7d688b 14476 state = intel_create_plane_state(&cursor->base);
fca0ce2a
VS
14477 if (!state)
14478 goto fail;
8e7d688b 14479 cursor->base.state = &state->base;
ea2c67bb 14480
3d7d6510
MR
14481 cursor->can_scale = false;
14482 cursor->max_downscale = 1;
14483 cursor->pipe = pipe;
14484 cursor->plane = pipe;
a9ff8714 14485 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179 14486 cursor->check_plane = intel_check_cursor_plane;
55a08b3f 14487 cursor->update_plane = intel_update_cursor_plane;
a8ad0d8e 14488 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510 14489
fca0ce2a
VS
14490 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14491 &intel_plane_funcs,
14492 intel_cursor_formats,
14493 ARRAY_SIZE(intel_cursor_formats),
38573dc1
VS
14494 DRM_PLANE_TYPE_CURSOR,
14495 "cursor %c", pipe_name(pipe));
fca0ce2a
VS
14496 if (ret)
14497 goto fail;
4398ad45
VS
14498
14499 if (INTEL_INFO(dev)->gen >= 4) {
14500 if (!dev->mode_config.rotation_property)
14501 dev->mode_config.rotation_property =
14502 drm_mode_create_rotation_property(dev,
14503 BIT(DRM_ROTATE_0) |
14504 BIT(DRM_ROTATE_180));
14505 if (dev->mode_config.rotation_property)
14506 drm_object_attach_property(&cursor->base.base,
14507 dev->mode_config.rotation_property,
8e7d688b 14508 state->base.rotation);
4398ad45
VS
14509 }
14510
af99ceda
CK
14511 if (INTEL_INFO(dev)->gen >=9)
14512 state->scaler_id = -1;
14513
ea2c67bb
MR
14514 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14515
3d7d6510 14516 return &cursor->base;
fca0ce2a
VS
14517
14518fail:
14519 kfree(state);
14520 kfree(cursor);
14521
14522 return NULL;
3d7d6510
MR
14523}
14524
549e2bfb
CK
14525static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14526 struct intel_crtc_state *crtc_state)
14527{
14528 int i;
14529 struct intel_scaler *intel_scaler;
14530 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14531
14532 for (i = 0; i < intel_crtc->num_scalers; i++) {
14533 intel_scaler = &scaler_state->scalers[i];
14534 intel_scaler->in_use = 0;
549e2bfb
CK
14535 intel_scaler->mode = PS_SCALER_MODE_DYN;
14536 }
14537
14538 scaler_state->scaler_id = -1;
14539}
14540
b358d0a6 14541static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14542{
fbee40df 14543 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14544 struct intel_crtc *intel_crtc;
f5de6e07 14545 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR
14546 struct drm_plane *primary = NULL;
14547 struct drm_plane *cursor = NULL;
8563b1e8 14548 int ret;
79e53945 14549
955382f3 14550 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB
14551 if (intel_crtc == NULL)
14552 return;
14553
f5de6e07
ACO
14554 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14555 if (!crtc_state)
14556 goto fail;
550acefd
ACO
14557 intel_crtc->config = crtc_state;
14558 intel_crtc->base.state = &crtc_state->base;
07878248 14559 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14560
549e2bfb
CK
14561 /* initialize shared scalers */
14562 if (INTEL_INFO(dev)->gen >= 9) {
14563 if (pipe == PIPE_C)
14564 intel_crtc->num_scalers = 1;
14565 else
14566 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14567
14568 skl_init_scalers(dev, intel_crtc, crtc_state);
14569 }
14570
465c120c 14571 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR
14572 if (!primary)
14573 goto fail;
14574
14575 cursor = intel_cursor_plane_create(dev, pipe);
14576 if (!cursor)
14577 goto fail;
14578
465c120c 14579 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
4d5d72b7
VS
14580 cursor, &intel_crtc_funcs,
14581 "pipe %c", pipe_name(pipe));
3d7d6510
MR
14582 if (ret)
14583 goto fail;
79e53945 14584
1f1c2e24
VS
14585 /*
14586 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14587 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14588 */
80824003
JB
14589 intel_crtc->pipe = pipe;
14590 intel_crtc->plane = pipe;
3a77c4c4 14591 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14592 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14593 intel_crtc->plane = !pipe;
80824003
JB
14594 }
14595
4b0e333e
CW
14596 intel_crtc->cursor_base = ~0;
14597 intel_crtc->cursor_cntl = ~0;
dc41c154 14598 intel_crtc->cursor_size = ~0;
8d7849db 14599
852eb00d
VS
14600 intel_crtc->wm.cxsr_allowed = true;
14601
22fd0fab
JB
14602 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14603 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14604 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14605 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14606
79e53945 14607 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101 14608
8563b1e8
LL
14609 intel_color_init(&intel_crtc->base);
14610
87b6b101 14611 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR
14612 return;
14613
14614fail:
69ae561f
VS
14615 intel_plane_destroy(primary);
14616 intel_plane_destroy(cursor);
f5de6e07 14617 kfree(crtc_state);
3d7d6510 14618 kfree(intel_crtc);
79e53945
JB
14619}
14620
752aa88a
JB
14621enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14622{
14623 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14624 struct drm_device *dev = connector->base.dev;
752aa88a 14625
51fd371b 14626 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14627
d3babd3f 14628 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB
14629 return INVALID_PIPE;
14630
14631 return to_intel_crtc(encoder->crtc)->pipe;
14632}
14633
08d7b3d1 14634int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14635 struct drm_file *file)
08d7b3d1 14636{
08d7b3d1 14637 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14638 struct drm_crtc *drmmode_crtc;
c05422d5 14639 struct intel_crtc *crtc;
08d7b3d1 14640
7707e653 14641 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
71240ed2 14642 if (!drmmode_crtc)
3f2c2057 14643 return -ENOENT;
08d7b3d1 14644
7707e653 14645 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14646 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14647
c05422d5 14648 return 0;
08d7b3d1
CW
14649}
14650
66a9278e 14651static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14652{
66a9278e
DV
14653 struct drm_device *dev = encoder->base.dev;
14654 struct intel_encoder *source_encoder;
79e53945 14655 int index_mask = 0;
79e53945
JB
14656 int entry = 0;
14657
b2784e15 14658 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14659 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV
14660 index_mask |= (1 << entry);
14661
79e53945
JB
14662 entry++;
14663 }
4ef69c7a 14664
79e53945
JB
14665 return index_mask;
14666}
14667
4d302442
CW
14668static bool has_edp_a(struct drm_device *dev)
14669{
14670 struct drm_i915_private *dev_priv = dev->dev_private;
14671
14672 if (!IS_MOBILE(dev))
14673 return false;
14674
14675 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14676 return false;
14677
e3589908 14678 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW
14679 return false;
14680
14681 return true;
14682}
14683
84b4e042
JB
14684static bool intel_crt_present(struct drm_device *dev)
14685{
14686 struct drm_i915_private *dev_priv = dev->dev_private;
14687
884497ed
DL
14688 if (INTEL_INFO(dev)->gen >= 9)
14689 return false;
14690
cf404ce4 14691 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB
14692 return false;
14693
14694 if (IS_CHERRYVIEW(dev))
14695 return false;
14696
65e472e4
VS
14697 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14698 return false;
14699
70ac54d0
VS
14700 /* DDI E can't be used if DDI A requires 4 lanes */
14701 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14702 return false;
14703
e4abb733 14704 if (!dev_priv->vbt.int_crt_support)
84b4e042
JB
14705 return false;
14706
14707 return true;
14708}
14709
79e53945
JB
14710static void intel_setup_outputs(struct drm_device *dev)
14711{
725e30ad 14712 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14713 struct intel_encoder *encoder;
cb0953d7 14714 bool dpd_is_edp = false;
79e53945 14715
97a824e1
ID
14716 /*
14717 * intel_edp_init_connector() depends on this completing first, to
14718 * prevent the registeration of both eDP and LVDS and the incorrect
14719 * sharing of the PPS.
14720 */
c9093354 14721 intel_lvds_init(dev);
79e53945 14722
84b4e042 14723 if (intel_crt_present(dev))
79935fca 14724 intel_crt_init(dev);
cb0953d7 14725
c776eb2e
VK
14726 if (IS_BROXTON(dev)) {
14727 /*
14728 * FIXME: Broxton doesn't support port detection via the
14729 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14730 * detect the ports.
14731 */
14732 intel_ddi_init(dev, PORT_A);
14733 intel_ddi_init(dev, PORT_B);
14734 intel_ddi_init(dev, PORT_C);
c6c794a2
SS
14735
14736 intel_dsi_init(dev);
c776eb2e 14737 } else if (HAS_DDI(dev)) {
0e72a5b5
ED
14738 int found;
14739
de31facd
JB
14740 /*
14741 * Haswell uses DDI functions to detect digital outputs.
14742 * On SKL pre-D0 the strap isn't connected, so we assume
14743 * it's there.
14744 */
77179400 14745 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
de31facd 14746 /* WaIgnoreDDIAStrap: skl */
ef11bdb3 14747 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
0e72a5b5
ED
14748 intel_ddi_init(dev, PORT_A);
14749
14750 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14751 * register */
14752 found = I915_READ(SFUSE_STRAP);
14753
14754 if (found & SFUSE_STRAP_DDIB_DETECTED)
14755 intel_ddi_init(dev, PORT_B);
14756 if (found & SFUSE_STRAP_DDIC_DETECTED)
14757 intel_ddi_init(dev, PORT_C);
14758 if (found & SFUSE_STRAP_DDID_DETECTED)
14759 intel_ddi_init(dev, PORT_D);
2800e4c2
RV
14760 /*
14761 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14762 */
ef11bdb3 14763 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
2800e4c2
RV
14764 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14765 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14766 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14767 intel_ddi_init(dev, PORT_E);
14768
0e72a5b5 14769 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14770 int found;
5d8a7752 14771 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV
14772
14773 if (has_edp_a(dev))
14774 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14775
dc0fa718 14776 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14777 /* PCH SDVOB multiplex with HDMIB */
2a5c0832 14778 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
30ad48b7 14779 if (!found)
e2debe91 14780 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14781 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14782 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW
14783 }
14784
dc0fa718 14785 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14786 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14787
dc0fa718 14788 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14789 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14790
5eb08b69 14791 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14792 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14793
270b3042 14794 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14795 intel_dp_init(dev, PCH_DP_D, PORT_D);
666a4537 14796 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
22f35042 14797 bool has_edp, has_port;
457c52d8 14798
e17ac6db
VS
14799 /*
14800 * The DP_DETECTED bit is the latched state of the DDC
14801 * SDA pin at boot. However since eDP doesn't require DDC
14802 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14803 * eDP ports may have been muxed to an alternate function.
14804 * Thus we can't rely on the DP_DETECTED bit alone to detect
14805 * eDP ports. Consult the VBT as well as DP_DETECTED to
14806 * detect eDP ports.
22f35042
VS
14807 *
14808 * Sadly the straps seem to be missing sometimes even for HDMI
14809 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14810 * and VBT for the presence of the port. Additionally we can't
14811 * trust the port type the VBT declares as we've seen at least
14812 * HDMI ports that the VBT claim are DP or eDP.
e17ac6db 14813 */
457c52d8 14814 has_edp = intel_dp_is_edp(dev, PORT_B);
22f35042
VS
14815 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14816 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
457c52d8 14817 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
22f35042 14818 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
e66eb81d 14819 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
585a94b8 14820
457c52d8 14821 has_edp = intel_dp_is_edp(dev, PORT_C);
22f35042
VS
14822 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14823 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
457c52d8 14824 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
22f35042 14825 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
e66eb81d 14826 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
19c03924 14827
9418c1f1 14828 if (IS_CHERRYVIEW(dev)) {
22f35042
VS
14829 /*
14830 * eDP not supported on port D,
14831 * so no need to worry about it
14832 */
14833 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14834 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
e66eb81d 14835 intel_dp_init(dev, CHV_DP_D, PORT_D);
22f35042
VS
14836 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14837 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
9418c1f1
VS
14838 }
14839
3cfca973 14840 intel_dsi_init(dev);
09da55dc 14841 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14842 bool found = false;
7d57382e 14843
e2debe91 14844 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14845 DRM_DEBUG_KMS("probing SDVOB\n");
2a5c0832 14846 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
3fec3d2f 14847 if (!found && IS_G4X(dev)) {
b01f2c3a 14848 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14849 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14850 }
27185ae1 14851
3fec3d2f 14852 if (!found && IS_G4X(dev))
ab9d7c30 14853 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14854 }
13520b05
KH
14855
14856 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14857
e2debe91 14858 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14859 DRM_DEBUG_KMS("probing SDVOC\n");
2a5c0832 14860 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
b01f2c3a 14861 }
27185ae1 14862
e2debe91 14863 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14864
3fec3d2f 14865 if (IS_G4X(dev)) {
b01f2c3a 14866 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14867 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14868 }
3fec3d2f 14869 if (IS_G4X(dev))
ab9d7c30 14870 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14871 }
27185ae1 14872
3fec3d2f 14873 if (IS_G4X(dev) &&
e7281eab 14874 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14875 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14876 } else if (IS_GEN2(dev))
79e53945
JB
14877 intel_dvo_init(dev);
14878
103a196f 14879 if (SUPPORTS_TV(dev))
79e53945
JB
14880 intel_tv_init(dev);
14881
0bc12bcb 14882 intel_psr_init(dev);
7c8f8a70 14883
b2784e15 14884 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW
14885 encoder->base.possible_crtcs = encoder->crtc_mask;
14886 encoder->base.possible_clones =
66a9278e 14887 intel_encoder_clones(encoder);
79e53945 14888 }
47356eb6 14889
dde86e2d 14890 intel_init_pch_refclk(dev);
270b3042
DV
14891
14892 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB
14893}
14894
14895static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14896{
60a5ca01 14897 struct drm_device *dev = fb->dev;
79e53945 14898 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14899
ef2d633e 14900 drm_framebuffer_cleanup(fb);
60a5ca01 14901 mutex_lock(&dev->struct_mutex);
ef2d633e 14902 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS
14903 drm_gem_object_unreference(&intel_fb->obj->base);
14904 mutex_unlock(&dev->struct_mutex);
79e53945
JB
14905 kfree(intel_fb);
14906}
14907
14908static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14909 struct drm_file *file,
79e53945
JB
14910 unsigned int *handle)
14911{
14912 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14913 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14914
cc917ab4
CW
14915 if (obj->userptr.mm) {
14916 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14917 return -EINVAL;
14918 }
14919
05394f39 14920 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB
14921}
14922
86c98588
RV
14923static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14924 struct drm_file *file,
14925 unsigned flags, unsigned color,
14926 struct drm_clip_rect *clips,
14927 unsigned num_clips)
14928{
14929 struct drm_device *dev = fb->dev;
14930 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14931 struct drm_i915_gem_object *obj = intel_fb->obj;
14932
14933 mutex_lock(&dev->struct_mutex);
74b4ea1e 14934 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV
14935 mutex_unlock(&dev->struct_mutex);
14936
14937 return 0;
14938}
14939
79e53945
JB
14940static const struct drm_framebuffer_funcs intel_fb_funcs = {
14941 .destroy = intel_user_framebuffer_destroy,
14942 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14943 .dirty = intel_user_framebuffer_dirty,
79e53945
JB
14944};
14945
b321803d
DL
14946static
14947u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14948 uint32_t pixel_format)
14949{
14950 u32 gen = INTEL_INFO(dev)->gen;
14951
14952 if (gen >= 9) {
ac484963
VS
14953 int cpp = drm_format_plane_cpp(pixel_format, 0);
14954
b321803d
DL
14955 /* "The stride in bytes must not exceed the of the size of 8K
14956 * pixels and 32K bytes."
14957 */
ac484963 14958 return min(8192 * cpp, 32768);
666a4537 14959 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
b321803d
DL
14960 return 32*1024;
14961 } else if (gen >= 4) {
14962 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14963 return 16*1024;
14964 else
14965 return 32*1024;
14966 } else if (gen >= 3) {
14967 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14968 return 8*1024;
14969 else
14970 return 16*1024;
14971 } else {
14972 /* XXX DSPC is limited to 4k tiled */
14973 return 8*1024;
14974 }
14975}
14976
b5ea642a
DV
14977static int intel_framebuffer_init(struct drm_device *dev,
14978 struct intel_framebuffer *intel_fb,
14979 struct drm_mode_fb_cmd2 *mode_cmd,
14980 struct drm_i915_gem_object *obj)
79e53945 14981{
7b49f948 14982 struct drm_i915_private *dev_priv = to_i915(dev);
6761dd31 14983 unsigned int aligned_height;
79e53945 14984 int ret;
b321803d 14985 u32 pitch_limit, stride_alignment;
79e53945 14986
dd4916c5
DV
14987 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14988
2a80eada
DV
14989 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14990 /* Enforce that fb modifier and tiling mode match, but only for
14991 * X-tiled. This is needed for FBC. */
14992 if (!!(obj->tiling_mode == I915_TILING_X) !=
14993 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14994 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14995 return -EINVAL;
14996 }
14997 } else {
14998 if (obj->tiling_mode == I915_TILING_X)
14999 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15000 else if (obj->tiling_mode == I915_TILING_Y) {
15001 DRM_DEBUG("No Y tiling for legacy addfb\n");
15002 return -EINVAL;
15003 }
15004 }
15005
9a8f0a12
TU
15006 /* Passed in modifier sanity checking. */
15007 switch (mode_cmd->modifier[0]) {
15008 case I915_FORMAT_MOD_Y_TILED:
15009 case I915_FORMAT_MOD_Yf_TILED:
15010 if (INTEL_INFO(dev)->gen < 9) {
15011 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15012 mode_cmd->modifier[0]);
15013 return -EINVAL;
15014 }
15015 case DRM_FORMAT_MOD_NONE:
15016 case I915_FORMAT_MOD_X_TILED:
15017 break;
15018 default:
c0f40428
JB
15019 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15020 mode_cmd->modifier[0]);
57cd6508 15021 return -EINVAL;
c16ed4be 15022 }
57cd6508 15023
7b49f948
VS
15024 stride_alignment = intel_fb_stride_alignment(dev_priv,
15025 mode_cmd->modifier[0],
b321803d
DL
15026 mode_cmd->pixel_format);
15027 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15028 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15029 mode_cmd->pitches[0], stride_alignment);
57cd6508 15030 return -EINVAL;
c16ed4be 15031 }
57cd6508 15032
b321803d
DL
15033 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15034 mode_cmd->pixel_format);
a35cdaa0 15035 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL
15036 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15037 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 15038 "tiled" : "linear",
a35cdaa0 15039 mode_cmd->pitches[0], pitch_limit);
5d7bd705 15040 return -EINVAL;
c16ed4be 15041 }
5d7bd705 15042
2a80eada 15043 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW
15044 mode_cmd->pitches[0] != obj->stride) {
15045 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15046 mode_cmd->pitches[0], obj->stride);
5d7bd705 15047 return -EINVAL;
c16ed4be 15048 }
5d7bd705 15049
57779d06 15050 /* Reject formats not supported by any plane early. */
308e5bcb 15051 switch (mode_cmd->pixel_format) {
57779d06 15052 case DRM_FORMAT_C8:
04b3924d
VS
15053 case DRM_FORMAT_RGB565:
15054 case DRM_FORMAT_XRGB8888:
15055 case DRM_FORMAT_ARGB8888:
57779d06
VS
15056 break;
15057 case DRM_FORMAT_XRGB1555:
c16ed4be 15058 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS
15059 DRM_DEBUG("unsupported pixel format: %s\n",
15060 drm_get_format_name(mode_cmd->pixel_format));
57779d06 15061 return -EINVAL;
c16ed4be 15062 }
57779d06 15063 break;
57779d06 15064 case DRM_FORMAT_ABGR8888:
666a4537
WB
15065 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15066 INTEL_INFO(dev)->gen < 9) {
6c0fd451
DL
15067 DRM_DEBUG("unsupported pixel format: %s\n",
15068 drm_get_format_name(mode_cmd->pixel_format));
15069 return -EINVAL;
15070 }
15071 break;
15072 case DRM_FORMAT_XBGR8888:
04b3924d 15073 case DRM_FORMAT_XRGB2101010:
57779d06 15074 case DRM_FORMAT_XBGR2101010:
c16ed4be 15075 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS
15076 DRM_DEBUG("unsupported pixel format: %s\n",
15077 drm_get_format_name(mode_cmd->pixel_format));
57779d06 15078 return -EINVAL;
c16ed4be 15079 }
b5626747 15080 break;
7531208b 15081 case DRM_FORMAT_ABGR2101010:
666a4537 15082 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7531208b
DL
15083 DRM_DEBUG("unsupported pixel format: %s\n",
15084 drm_get_format_name(mode_cmd->pixel_format));
15085 return -EINVAL;
15086 }
15087 break;
04b3924d
VS
15088 case DRM_FORMAT_YUYV:
15089 case DRM_FORMAT_UYVY:
15090 case DRM_FORMAT_YVYU:
15091 case DRM_FORMAT_VYUY:
c16ed4be 15092 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS
15093 DRM_DEBUG("unsupported pixel format: %s\n",
15094 drm_get_format_name(mode_cmd->pixel_format));
57779d06 15095 return -EINVAL;
c16ed4be 15096 }
57cd6508
CW
15097 break;
15098 default:
4ee62c76
VS
15099 DRM_DEBUG("unsupported pixel format: %s\n",
15100 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW
15101 return -EINVAL;
15102 }
15103
90f9a336
VS
15104 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15105 if (mode_cmd->offsets[0] != 0)
15106 return -EINVAL;
15107
ec2c981e 15108 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV
15109 mode_cmd->pixel_format,
15110 mode_cmd->modifier[0]);
53155c0a
DV
15111 /* FIXME drm helper for size checks (especially planar formats)? */
15112 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
15113 return -EINVAL;
15114
c7d73f6a
DV
15115 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15116 intel_fb->obj = obj;
15117
2d7a215f
VS
15118 intel_fill_fb_info(dev_priv, &intel_fb->base);
15119
79e53945
JB
15120 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15121 if (ret) {
15122 DRM_ERROR("framebuffer init failed %d\n", ret);
15123 return ret;
15124 }
15125
0b05e1e0
VS
15126 intel_fb->obj->framebuffer_references++;
15127
79e53945
JB
15128 return 0;
15129}
15130
79e53945
JB
15131static struct drm_framebuffer *
15132intel_user_framebuffer_create(struct drm_device *dev,
15133 struct drm_file *filp,
1eb83451 15134 const struct drm_mode_fb_cmd2 *user_mode_cmd)
79e53945 15135{
dcb1394e 15136 struct drm_framebuffer *fb;
05394f39 15137 struct drm_i915_gem_object *obj;
76dc3769 15138 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
79e53945 15139
a8ad0bd8 15140 obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0]));
c8725226 15141 if (&obj->base == NULL)
cce13ff7 15142 return ERR_PTR(-ENOENT);
79e53945 15143
92907cbb 15144 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
dcb1394e
LW
15145 if (IS_ERR(fb))
15146 drm_gem_object_unreference_unlocked(&obj->base);
15147
15148 return fb;
79e53945
JB
15149}
15150
0695726e 15151#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 15152static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV
15153{
15154}
15155#endif
15156
79e53945 15157static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 15158 .fb_create = intel_user_framebuffer_create,
0632fef6 15159 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR
15160 .atomic_check = intel_atomic_check,
15161 .atomic_commit = intel_atomic_commit,
de419ab6
ML
15162 .atomic_state_alloc = intel_atomic_state_alloc,
15163 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB
15164};
15165
88212941
ID
15166/**
15167 * intel_init_display_hooks - initialize the display modesetting hooks
15168 * @dev_priv: device private
15169 */
15170void intel_init_display_hooks(struct drm_i915_private *dev_priv)
e70236a8 15171{
88212941 15172 if (INTEL_INFO(dev_priv)->gen >= 9) {
bc8d7dff 15173 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL
15174 dev_priv->display.get_initial_plane_config =
15175 skylake_get_initial_plane_config;
bc8d7dff
DL
15176 dev_priv->display.crtc_compute_clock =
15177 haswell_crtc_compute_clock;
15178 dev_priv->display.crtc_enable = haswell_crtc_enable;
15179 dev_priv->display.crtc_disable = haswell_crtc_disable;
88212941 15180 } else if (HAS_DDI(dev_priv)) {
0e8ffe1b 15181 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL
15182 dev_priv->display.get_initial_plane_config =
15183 ironlake_get_initial_plane_config;
797d0259
ACO
15184 dev_priv->display.crtc_compute_clock =
15185 haswell_crtc_compute_clock;
4f771f10
PZ
15186 dev_priv->display.crtc_enable = haswell_crtc_enable;
15187 dev_priv->display.crtc_disable = haswell_crtc_disable;
88212941 15188 } else if (HAS_PCH_SPLIT(dev_priv)) {
0e8ffe1b 15189 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL
15190 dev_priv->display.get_initial_plane_config =
15191 ironlake_get_initial_plane_config;
3fb37703
ACO
15192 dev_priv->display.crtc_compute_clock =
15193 ironlake_crtc_compute_clock;
76e5a89c
DV
15194 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15195 dev_priv->display.crtc_disable = ironlake_crtc_disable;
65b3d6a9 15196 } else if (IS_CHERRYVIEW(dev_priv)) {
89b667f8 15197 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL
15198 dev_priv->display.get_initial_plane_config =
15199 i9xx_get_initial_plane_config;
65b3d6a9
ACO
15200 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15201 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15202 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15203 } else if (IS_VALLEYVIEW(dev_priv)) {
15204 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15205 dev_priv->display.get_initial_plane_config =
15206 i9xx_get_initial_plane_config;
15207 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
89b667f8
JB
15208 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15209 dev_priv->display.crtc_disable = i9xx_crtc_disable;
19ec6693
ACO
15210 } else if (IS_G4X(dev_priv)) {
15211 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15212 dev_priv->display.get_initial_plane_config =
15213 i9xx_get_initial_plane_config;
15214 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15215 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15216 dev_priv->display.crtc_disable = i9xx_crtc_disable;
70e8aa21
ACO
15217 } else if (IS_PINEVIEW(dev_priv)) {
15218 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15219 dev_priv->display.get_initial_plane_config =
15220 i9xx_get_initial_plane_config;
15221 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15222 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15223 dev_priv->display.crtc_disable = i9xx_crtc_disable;
81c97f52 15224 } else if (!IS_GEN2(dev_priv)) {
0e8ffe1b 15225 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL
15226 dev_priv->display.get_initial_plane_config =
15227 i9xx_get_initial_plane_config;
d6dfee7a 15228 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV
15229 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15230 dev_priv->display.crtc_disable = i9xx_crtc_disable;
81c97f52
ACO
15231 } else {
15232 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15233 dev_priv->display.get_initial_plane_config =
15234 i9xx_get_initial_plane_config;
15235 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15236 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15237 dev_priv->display.crtc_disable = i9xx_crtc_disable;
f564048e 15238 }
e70236a8 15239
e70236a8 15240 /* Returns the core display clock speed */
88212941 15241 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1652d19e
VS
15242 dev_priv->display.get_display_clock_speed =
15243 skylake_get_display_clock_speed;
88212941 15244 else if (IS_BROXTON(dev_priv))
acd3f3d3
BP
15245 dev_priv->display.get_display_clock_speed =
15246 broxton_get_display_clock_speed;
88212941 15247 else if (IS_BROADWELL(dev_priv))
1652d19e
VS
15248 dev_priv->display.get_display_clock_speed =
15249 broadwell_get_display_clock_speed;
88212941 15250 else if (IS_HASWELL(dev_priv))
1652d19e
VS
15251 dev_priv->display.get_display_clock_speed =
15252 haswell_get_display_clock_speed;
88212941 15253 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
25eb05fc
JB
15254 dev_priv->display.get_display_clock_speed =
15255 valleyview_get_display_clock_speed;
88212941 15256 else if (IS_GEN5(dev_priv))
b37a6434
VS
15257 dev_priv->display.get_display_clock_speed =
15258 ilk_get_display_clock_speed;
88212941
ID
15259 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15260 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
e70236a8
JB
15261 dev_priv->display.get_display_clock_speed =
15262 i945_get_display_clock_speed;
88212941 15263 else if (IS_GM45(dev_priv))
34edce2f
VS
15264 dev_priv->display.get_display_clock_speed =
15265 gm45_get_display_clock_speed;
88212941 15266 else if (IS_CRESTLINE(dev_priv))
34edce2f
VS
15267 dev_priv->display.get_display_clock_speed =
15268 i965gm_get_display_clock_speed;
88212941 15269 else if (IS_PINEVIEW(dev_priv))
34edce2f
VS
15270 dev_priv->display.get_display_clock_speed =
15271 pnv_get_display_clock_speed;
88212941 15272 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
34edce2f
VS
15273 dev_priv->display.get_display_clock_speed =
15274 g33_get_display_clock_speed;
88212941 15275 else if (IS_I915G(dev_priv))
e70236a8
JB
15276 dev_priv->display.get_display_clock_speed =
15277 i915_get_display_clock_speed;
88212941 15278 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
e70236a8
JB
15279 dev_priv->display.get_display_clock_speed =
15280 i9xx_misc_get_display_clock_speed;
88212941 15281 else if (IS_I915GM(dev_priv))
e70236a8
JB
15282 dev_priv->display.get_display_clock_speed =
15283 i915gm_get_display_clock_speed;
88212941 15284 else if (IS_I865G(dev_priv))
e70236a8
JB
15285 dev_priv->display.get_display_clock_speed =
15286 i865_get_display_clock_speed;
88212941 15287 else if (IS_I85X(dev_priv))
e70236a8 15288 dev_priv->display.get_display_clock_speed =
1b1d2716 15289 i85x_get_display_clock_speed;
623e01e5 15290 else { /* 830 */
88212941 15291 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB
15292 dev_priv->display.get_display_clock_speed =
15293 i830_get_display_clock_speed;
623e01e5 15294 }
e70236a8 15295
88212941 15296 if (IS_GEN5(dev_priv)) {
3bb11b53 15297 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
88212941 15298 } else if (IS_GEN6(dev_priv)) {
3bb11b53 15299 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
88212941 15300 } else if (IS_IVYBRIDGE(dev_priv)) {
3bb11b53
SJ
15301 /* FIXME: detect B0+ stepping and use auto training */
15302 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
88212941 15303 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3bb11b53 15304 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
445e780b
VS
15305 }
15306
15307 if (IS_BROADWELL(dev_priv)) {
15308 dev_priv->display.modeset_commit_cdclk =
15309 broadwell_modeset_commit_cdclk;
15310 dev_priv->display.modeset_calc_cdclk =
15311 broadwell_modeset_calc_cdclk;
88212941 15312 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
27c329ed
ML
15313 dev_priv->display.modeset_commit_cdclk =
15314 valleyview_modeset_commit_cdclk;
15315 dev_priv->display.modeset_calc_cdclk =
15316 valleyview_modeset_calc_cdclk;
88212941 15317 } else if (IS_BROXTON(dev_priv)) {
27c329ed 15318 dev_priv->display.modeset_commit_cdclk =
324513c0 15319 bxt_modeset_commit_cdclk;
27c329ed 15320 dev_priv->display.modeset_calc_cdclk =
324513c0 15321 bxt_modeset_calc_cdclk;
c89e39f3
CT
15322 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15323 dev_priv->display.modeset_commit_cdclk =
15324 skl_modeset_commit_cdclk;
15325 dev_priv->display.modeset_calc_cdclk =
15326 skl_modeset_calc_cdclk;
e70236a8 15327 }
5a21b665
DV
15328
15329 switch (INTEL_INFO(dev_priv)->gen) {
15330 case 2:
15331 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15332 break;
15333
15334 case 3:
15335 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15336 break;
15337
15338 case 4:
15339 case 5:
15340 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15341 break;
15342
15343 case 6:
15344 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15345 break;
15346 case 7:
15347 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15348 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15349 break;
15350 case 9:
15351 /* Drop through - unsupported since execlist only. */
15352 default:
15353 /* Default just returns -ENODEV to indicate unsupported */
15354 dev_priv->display.queue_flip = intel_default_queue_flip;
15355 }
e70236a8
JB
15356}
15357
b690e96c
JB
15358/*
15359 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15360 * resume, or other times. This quirk makes sure that's the case for
15361 * affected systems.
15362 */
0206e353 15363static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB
15364{
15365 struct drm_i915_private *dev_priv = dev->dev_private;
15366
15367 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 15368 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB
15369}
15370
b6b5d049
VS
15371static void quirk_pipeb_force(struct drm_device *dev)
15372{
15373 struct drm_i915_private *dev_priv = dev->dev_private;
15374
15375 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15376 DRM_INFO("applying pipe b force quirk\n");
15377}
15378
435793df
KP
15379/*
15380 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15381 */
15382static void quirk_ssc_force_disable(struct drm_device *dev)
15383{
15384 struct drm_i915_private *dev_priv = dev->dev_private;
15385 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 15386 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP
15387}
15388
4dca20ef 15389/*
5a15ab5b
CE
15390 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15391 * brightness value
4dca20ef
CE
15392 */
15393static void quirk_invert_brightness(struct drm_device *dev)
15394{
15395 struct drm_i915_private *dev_priv = dev->dev_private;
15396 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 15397 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP
15398}
15399
9c72cc6f
SD
15400/* Some VBT's incorrectly indicate no backlight is present */
15401static void quirk_backlight_present(struct drm_device *dev)
15402{
15403 struct drm_i915_private *dev_priv = dev->dev_private;
15404 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15405 DRM_INFO("applying backlight present quirk\n");
15406}
15407
b690e96c
JB
15408struct intel_quirk {
15409 int device;
15410 int subsystem_vendor;
15411 int subsystem_device;
15412 void (*hook)(struct drm_device *dev);
15413};
15414
5f85f176
EE
15415/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15416struct intel_dmi_quirk {
15417 void (*hook)(struct drm_device *dev);
15418 const struct dmi_system_id (*dmi_id_list)[];
15419};
15420
15421static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15422{
15423 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15424 return 1;
15425}
15426
15427static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15428 {
15429 .dmi_id_list = &(const struct dmi_system_id[]) {
15430 {
15431 .callback = intel_dmi_reverse_brightness,
15432 .ident = "NCR Corporation",
15433 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15434 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15435 },
15436 },
15437 { } /* terminating entry */
15438 },
15439 .hook = quirk_invert_brightness,
15440 },
15441};
15442
c43b5634 15443static struct intel_quirk intel_quirks[] = {
b690e96c
JB
15444 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15445 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15446
b690e96c
JB
15447 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15448 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15449
5f080c0f
VS
15450 /* 830 needs to leave pipe A & dpll A up */
15451 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15452
b6b5d049
VS
15453 /* 830 needs to leave pipe B & dpll B up */
15454 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15455
435793df
KP
15456 /* Lenovo U160 cannot use SSC on LVDS */
15457 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS
15458
15459 /* Sony Vaio Y cannot use SSC on LVDS */
15460 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 15461
be505f64
AH
15462 /* Acer Aspire 5734Z must invert backlight brightness */
15463 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15464
15465 /* Acer/eMachines G725 */
15466 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15467
15468 /* Acer/eMachines e725 */
15469 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15470
15471 /* Acer/Packard Bell NCL20 */
15472 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15473
15474 /* Acer Aspire 4736Z */
15475 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN
15476
15477 /* Acer Aspire 5336 */
15478 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD
15479
15480 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15481 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 15482
dfb3d47b
SD
15483 /* Acer C720 Chromebook (Core i3 4005U) */
15484 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15485
b2a9601c 15486 /* Apple Macbook 2,1 (Core 2 T7400) */
15487 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15488
1b9448b0
JN
15489 /* Apple Macbook 4,1 */
15490 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15491
d4967d8c
SD
15492 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15493 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD
15494
15495 /* HP Chromebook 14 (Celeron 2955U) */
15496 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN
15497
15498 /* Dell Chromebook 11 */
15499 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
9be64eee
JN
15500
15501 /* Dell Chromebook 11 (2015 version) */
15502 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB
15503};
15504
15505static void intel_init_quirks(struct drm_device *dev)
15506{
15507 struct pci_dev *d = dev->pdev;
15508 int i;
15509
15510 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15511 struct intel_quirk *q = &intel_quirks[i];
15512
15513 if (d->device == q->device &&
15514 (d->subsystem_vendor == q->subsystem_vendor ||
15515 q->subsystem_vendor == PCI_ANY_ID) &&
15516 (d->subsystem_device == q->subsystem_device ||
15517 q->subsystem_device == PCI_ANY_ID))
15518 q->hook(dev);
15519 }
5f85f176
EE
15520 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15521 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15522 intel_dmi_quirks[i].hook(dev);
15523 }
b690e96c
JB
15524}
15525
9cce37f4
JB
15526/* Disable the VGA plane that we never use */
15527static void i915_disable_vga(struct drm_device *dev)
15528{
15529 struct drm_i915_private *dev_priv = dev->dev_private;
15530 u8 sr1;
f0f59a00 15531 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 15532
2b37c616 15533 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 15534 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 15535 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB
15536 sr1 = inb(VGA_SR_DATA);
15537 outb(sr1 | 1<<5, VGA_SR_DATA);
15538 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15539 udelay(300);
15540
01f5a626 15541 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB
15542 POSTING_READ(vga_reg);
15543}
15544
f817586c
DV
15545void intel_modeset_init_hw(struct drm_device *dev)
15546{
1a617b77
ML
15547 struct drm_i915_private *dev_priv = dev->dev_private;
15548
b6283055 15549 intel_update_cdclk(dev);
1a617b77
ML
15550
15551 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15552
f817586c 15553 intel_init_clock_gating(dev);
dc97997a 15554 intel_enable_gt_powersave(dev_priv);
f817586c
DV
15555}
15556
d93c0372
MR
15557/*
15558 * Calculate what we think the watermarks should be for the state we've read
15559 * out of the hardware and then immediately program those watermarks so that
15560 * we ensure the hardware settings match our internal state.
15561 *
15562 * We can calculate what we think WM's should be by creating a duplicate of the
15563 * current state (which was constructed during hardware readout) and running it
15564 * through the atomic check code to calculate new watermark values in the
15565 * state object.
15566 */
15567static void sanitize_watermarks(struct drm_device *dev)
15568{
15569 struct drm_i915_private *dev_priv = to_i915(dev);
15570 struct drm_atomic_state *state;
15571 struct drm_crtc *crtc;
15572 struct drm_crtc_state *cstate;
15573 struct drm_modeset_acquire_ctx ctx;
15574 int ret;
15575 int i;
15576
15577 /* Only supported on platforms that use atomic watermark design */
ed4a6a7c 15578 if (!dev_priv->display.optimize_watermarks)
d93c0372
MR
15579 return;
15580
15581 /*
15582 * We need to hold connection_mutex before calling duplicate_state so
15583 * that the connector loop is protected.
15584 */
15585 drm_modeset_acquire_init(&ctx, 0);
15586retry:
0cd1262d 15587 ret = drm_modeset_lock_all_ctx(dev, &ctx);
d93c0372
MR
15588 if (ret == -EDEADLK) {
15589 drm_modeset_backoff(&ctx);
15590 goto retry;
15591 } else if (WARN_ON(ret)) {
0cd1262d 15592 goto fail;
d93c0372
MR
15593 }
15594
15595 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15596 if (WARN_ON(IS_ERR(state)))
0cd1262d 15597 goto fail;
d93c0372 15598
ed4a6a7c
MR
15599 /*
15600 * Hardware readout is the only time we don't want to calculate
15601 * intermediate watermarks (since we don't trust the current
15602 * watermarks).
15603 */
15604 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15605
d93c0372
MR
15606 ret = intel_atomic_check(dev, state);
15607 if (ret) {
15608 /*
15609 * If we fail here, it means that the hardware appears to be
15610 * programmed in a way that shouldn't be possible, given our
15611 * understanding of watermark requirements. This might mean a
15612 * mistake in the hardware readout code or a mistake in the
15613 * watermark calculations for a given platform. Raise a WARN
15614 * so that this is noticeable.
15615 *
15616 * If this actually happens, we'll have to just leave the
15617 * BIOS-programmed watermarks untouched and hope for the best.
15618 */
15619 WARN(true, "Could not determine valid watermarks for inherited state\n");
0cd1262d 15620 goto fail;
d93c0372
MR
15621 }
15622
15623 /* Write calculated watermark values back */
d93c0372
MR
15624 for_each_crtc_in_state(state, crtc, cstate, i) {
15625 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15626
ed4a6a7c
MR
15627 cs->wm.need_postvbl_update = true;
15628 dev_priv->display.optimize_watermarks(cs);
d93c0372
MR
15629 }
15630
15631 drm_atomic_state_free(state);
0cd1262d 15632fail:
d93c0372
MR
15633 drm_modeset_drop_locks(&ctx);
15634 drm_modeset_acquire_fini(&ctx);
15635}
15636
79e53945
JB
15637void intel_modeset_init(struct drm_device *dev)
15638{
72e96d64
JL
15639 struct drm_i915_private *dev_priv = to_i915(dev);
15640 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1fe47785 15641 int sprite, ret;
8cc87b75 15642 enum pipe pipe;
46f297fb 15643 struct intel_crtc *crtc;
79e53945
JB
15644
15645 drm_mode_config_init(dev);
15646
15647 dev->mode_config.min_width = 0;
15648 dev->mode_config.min_height = 0;
15649
019d96cb
DA
15650 dev->mode_config.preferred_depth = 24;
15651 dev->mode_config.prefer_shadow = 1;
15652
25bab385
TU
15653 dev->mode_config.allow_fb_modifiers = true;
15654
e6ecefaa 15655 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15656
b690e96c
JB
15657 intel_init_quirks(dev);
15658
1fa61106
ED
15659 intel_init_pm(dev);
15660
e3c74757
BW
15661 if (INTEL_INFO(dev)->num_pipes == 0)
15662 return;
15663
69f92f67
LW
15664 /*
15665 * There may be no VBT; and if the BIOS enabled SSC we can
15666 * just keep using it to avoid unnecessary flicker. Whereas if the
15667 * BIOS isn't using it, don't assume it will work even if the VBT
15668 * indicates as much.
15669 */
15670 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15671 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15672 DREF_SSC1_ENABLE);
15673
15674 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15675 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15676 bios_lvds_use_ssc ? "en" : "dis",
15677 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15678 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15679 }
15680 }
15681
a6c45cf0
CW
15682 if (IS_GEN2(dev)) {
15683 dev->mode_config.max_width = 2048;
15684 dev->mode_config.max_height = 2048;
15685 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP
15686 dev->mode_config.max_width = 4096;
15687 dev->mode_config.max_height = 4096;
79e53945 15688 } else {
a6c45cf0
CW
15689 dev->mode_config.max_width = 8192;
15690 dev->mode_config.max_height = 8192;
79e53945 15691 }
068be561 15692
dc41c154
VS
15693 if (IS_845G(dev) || IS_I865G(dev)) {
15694 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15695 dev->mode_config.cursor_height = 1023;
15696 } else if (IS_GEN2(dev)) {
068be561
DL
15697 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15698 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15699 } else {
15700 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15701 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15702 }
15703
72e96d64 15704 dev->mode_config.fb_base = ggtt->mappable_base;
79e53945 15705
28c97730 15706 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW
15707 INTEL_INFO(dev)->num_pipes,
15708 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15709
055e393f 15710 for_each_pipe(dev_priv, pipe) {
8cc87b75 15711 intel_crtc_init(dev, pipe);
3bdcfc0c 15712 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15713 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15714 if (ret)
06da8da2 15715 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15716 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15717 }
79e53945
JB
15718 }
15719
bfa7df01
VS
15720 intel_update_czclk(dev_priv);
15721 intel_update_cdclk(dev);
15722
e72f9fbf 15723 intel_shared_dpll_init(dev);
ee7b9f93 15724
b2045352
VS
15725 if (dev_priv->max_cdclk_freq == 0)
15726 intel_update_max_cdclk(dev);
15727
9cce37f4
JB
15728 /* Just disable it once at startup */
15729 i915_disable_vga(dev);
79e53945 15730 intel_setup_outputs(dev);
11be49eb 15731
6e9f798d 15732 drm_modeset_lock_all(dev);
043e9bda 15733 intel_modeset_setup_hw_state(dev);
6e9f798d 15734 drm_modeset_unlock_all(dev);
46f297fb 15735
d3fcc808 15736 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML
15737 struct intel_initial_plane_config plane_config = {};
15738
46f297fb
JB
15739 if (!crtc->active)
15740 continue;
15741
46f297fb 15742 /*
46f297fb
JB
15743 * Note that reserving the BIOS fb up front prevents us
15744 * from stuffing other stolen allocations like the ring
15745 * on top. This prevents some ugliness at boot time, and
15746 * can even allow for smooth boot transitions if the BIOS
15747 * fb is large enough for the active pipe configuration.
15748 */
eeebeac5
ML
15749 dev_priv->display.get_initial_plane_config(crtc,
15750 &plane_config);
15751
15752 /*
15753 * If the fb is shared between multiple heads, we'll
15754 * just get the first one.
15755 */
15756 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 15757 }
d93c0372
MR
15758
15759 /*
15760 * Make sure hardware watermarks really match the state we read out.
15761 * Note that we need to do this after reconstructing the BIOS fb's
15762 * since the watermark calculation done here will use pstate->fb.
15763 */
15764 sanitize_watermarks(dev);
2c7111db
CW
15765}
15766
7fad798e
DV
15767static void intel_enable_pipe_a(struct drm_device *dev)
15768{
15769 struct intel_connector *connector;
15770 struct drm_connector *crt = NULL;
15771 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15772 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV
15773
15774 /* We can't just switch on the pipe A, we need to set things up with a
15775 * proper mode and output configuration. As a gross hack, enable pipe A
15776 * by enabling the load detect pipe once. */
3a3371ff 15777 for_each_intel_connector(dev, connector) {
7fad798e
DV
15778 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15779 crt = &connector->base;
15780 break;
15781 }
15782 }
15783
15784 if (!crt)
15785 return;
15786
208bf9fd 15787 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15788 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV
15789}
15790
fa555837
DV
15791static bool
15792intel_check_plane_mapping(struct intel_crtc *crtc)
15793{
7eb552ae
BW
15794 struct drm_device *dev = crtc->base.dev;
15795 struct drm_i915_private *dev_priv = dev->dev_private;
649636ef 15796 u32 val;
fa555837 15797
7eb552ae 15798 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV
15799 return true;
15800
649636ef 15801 val = I915_READ(DSPCNTR(!crtc->plane));
fa555837
DV
15802
15803 if ((val & DISPLAY_PLANE_ENABLE) &&
15804 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15805 return false;
15806
15807 return true;
15808}
15809
02e93c35
VS
15810static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15811{
15812 struct drm_device *dev = crtc->base.dev;
15813 struct intel_encoder *encoder;
15814
15815 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15816 return true;
15817
15818 return false;
15819}
15820
dd756198
VS
15821static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15822{
15823 struct drm_device *dev = encoder->base.dev;
15824 struct intel_connector *connector;
15825
15826 for_each_connector_on_encoder(dev, &encoder->base, connector)
15827 return true;
15828
15829 return false;
15830}
15831
24929352
DV
15832static void intel_sanitize_crtc(struct intel_crtc *crtc)
15833{
15834 struct drm_device *dev = crtc->base.dev;
15835 struct drm_i915_private *dev_priv = dev->dev_private;
4d1de975 15836 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
24929352 15837
24929352 15838 /* Clear any frame start delays used for debugging left by the BIOS */
4d1de975
JN
15839 if (!transcoder_is_dsi(cpu_transcoder)) {
15840 i915_reg_t reg = PIPECONF(cpu_transcoder);
15841
15842 I915_WRITE(reg,
15843 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15844 }
24929352 15845
d3eaf884 15846 /* restore vblank interrupts to correct state */
9625604c 15847 drm_crtc_vblank_reset(&crtc->base);
d297e103 15848 if (crtc->active) {
f9cd7b88
VS
15849 struct intel_plane *plane;
15850
9625604c 15851 drm_crtc_vblank_on(&crtc->base);
f9cd7b88
VS
15852
15853 /* Disable everything but the primary plane */
15854 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15855 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15856 continue;
15857
15858 plane->disable_plane(&plane->base, &crtc->base);
15859 }
9625604c 15860 }
d3eaf884 15861
24929352 15862 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV
15863 * disable the crtc (and hence change the state) if it is wrong. Note
15864 * that gen4+ has a fixed plane -> pipe mapping. */
15865 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV
15866 bool plane;
15867
78108b7c
VS
15868 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15869 crtc->base.base.id, crtc->base.name);
24929352
DV
15870
15871 /* Pipe has the wrong plane attached and the plane is active.
15872 * Temporarily change the plane mapping and disable everything
15873 * ... */
15874 plane = crtc->plane;
b70709a6 15875 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15876 crtc->plane = !plane;
b17d48e2 15877 intel_crtc_disable_noatomic(&crtc->base);
24929352 15878 crtc->plane = plane;
24929352 15879 }
24929352 15880
7fad798e
DV
15881 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15882 crtc->pipe == PIPE_A && !crtc->active) {
15883 /* BIOS forgot to enable pipe A, this mostly happens after
15884 * resume. Force-enable the pipe to fix this, the update_dpms
15885 * call below we restore the pipe to the right state, but leave
15886 * the required bits on. */
15887 intel_enable_pipe_a(dev);
15888 }
15889
24929352
DV
15890 /* Adjust the state of the output pipe according to whether we
15891 * have active connectors/encoders. */
842e0307 15892 if (crtc->active && !intel_crtc_has_encoders(crtc))
b17d48e2 15893 intel_crtc_disable_noatomic(&crtc->base);
24929352 15894
a3ed6aad 15895 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV
15896 /*
15897 * We start out with underrun reporting disabled to avoid races.
15898 * For correct bookkeeping mark this on active crtcs.
15899 *
c5ab3bc0
DV
15900 * Also on gmch platforms we dont have any hardware bits to
15901 * disable the underrun reporting. Which means we need to start
15902 * out with underrun reporting disabled also on inactive pipes,
15903 * since otherwise we'll complain about the garbage we read when
15904 * e.g. coming up after runtime pm.
15905 *
4cc31489
DV
15906 * No protection against concurrent access is required - at
15907 * worst a fifo underrun happens which also sets this to false.
15908 */
15909 crtc->cpu_fifo_underrun_disabled = true;
15910 crtc->pch_fifo_underrun_disabled = true;
15911 }
24929352
DV
15912}
15913
15914static void intel_sanitize_encoder(struct intel_encoder *encoder)
15915{
15916 struct intel_connector *connector;
15917 struct drm_device *dev = encoder->base.dev;
15918
15919 /* We need to check both for a crtc link (meaning that the
15920 * encoder is active and trying to read from a pipe) and the
15921 * pipe itself being active. */
15922 bool has_active_crtc = encoder->base.crtc &&
15923 to_intel_crtc(encoder->base.crtc)->active;
15924
dd756198 15925 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
24929352
DV
15926 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15927 encoder->base.base.id,
8e329a03 15928 encoder->base.name);
24929352
DV
15929
15930 /* Connector is active, but has no active pipe. This is
15931 * fallout from our resume register restoring. Disable
15932 * the encoder manually again. */
15933 if (encoder->base.crtc) {
15934 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15935 encoder->base.base.id,
8e329a03 15936 encoder->base.name);
24929352 15937 encoder->disable(encoder);
a62d1497
VS
15938 if (encoder->post_disable)
15939 encoder->post_disable(encoder);
24929352 15940 }
7f1950fb 15941 encoder->base.crtc = NULL;
24929352
DV
15942
15943 /* Inconsistent output/port/pipe state happens presumably due to
15944 * a bug in one of the get_hw_state functions. Or someplace else
15945 * in our code, like the register restore mess on resume. Clamp
15946 * things to off as a safer default. */
3a3371ff 15947 for_each_intel_connector(dev, connector) {
24929352
DV
15948 if (connector->encoder != encoder)
15949 continue;
7f1950fb
EE
15950 connector->base.dpms = DRM_MODE_DPMS_OFF;
15951 connector->base.encoder = NULL;
24929352
DV
15952 }
15953 }
15954 /* Enabled encoders without active connectors will be fixed in
15955 * the crtc fixup. */
15956}
15957
04098753 15958void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM
15959{
15960 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 15961 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15962
04098753
ID
15963 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15964 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15965 i915_disable_vga(dev);
15966 }
15967}
15968
15969void i915_redisable_vga(struct drm_device *dev)
15970{
15971 struct drm_i915_private *dev_priv = dev->dev_private;
15972
8dc8a27c
PZ
15973 /* This function can be called both from intel_modeset_setup_hw_state or
15974 * at a very early point in our resume sequence, where the power well
15975 * structures are not yet restored. Since this function is at a very
15976 * paranoid "someone might have enabled VGA while we were not looking"
15977 * level, just check if the power well is enabled instead of trying to
15978 * follow the "don't touch the power well if we don't need it" policy
15979 * the rest of the driver uses. */
6392f847 15980 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ
15981 return;
15982
04098753 15983 i915_redisable_vga_power_on(dev);
6392f847
ID
15984
15985 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
0fde901f
KM
15986}
15987
f9cd7b88 15988static bool primary_get_hw_state(struct intel_plane *plane)
98ec7739 15989{
f9cd7b88 15990 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
98ec7739 15991
f9cd7b88 15992 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
d032ffa0
ML
15993}
15994
f9cd7b88
VS
15995/* FIXME read out full plane state for all planes */
15996static void readout_plane_state(struct intel_crtc *crtc)
d032ffa0 15997{
b26d3ea3 15998 struct drm_plane *primary = crtc->base.primary;
f9cd7b88 15999 struct intel_plane_state *plane_state =
b26d3ea3 16000 to_intel_plane_state(primary->state);
d032ffa0 16001
19b8d387 16002 plane_state->visible = crtc->active &&
b26d3ea3
ML
16003 primary_get_hw_state(to_intel_plane(primary));
16004
16005 if (plane_state->visible)
16006 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
98ec7739
VS
16007}
16008
30e984df 16009static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV
16010{
16011 struct drm_i915_private *dev_priv = dev->dev_private;
16012 enum pipe pipe;
24929352
DV
16013 struct intel_crtc *crtc;
16014 struct intel_encoder *encoder;
16015 struct intel_connector *connector;
5358901f 16016 int i;
24929352 16017
565602d7
ML
16018 dev_priv->active_crtcs = 0;
16019
d3fcc808 16020 for_each_intel_crtc(dev, crtc) {
565602d7
ML
16021 struct intel_crtc_state *crtc_state = crtc->config;
16022 int pixclk = 0;
3b117c8f 16023
ec2dc6a0 16024 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
565602d7
ML
16025 memset(crtc_state, 0, sizeof(*crtc_state));
16026 crtc_state->base.crtc = &crtc->base;
24929352 16027
565602d7
ML
16028 crtc_state->base.active = crtc_state->base.enable =
16029 dev_priv->display.get_pipe_config(crtc, crtc_state);
16030
16031 crtc->base.enabled = crtc_state->base.enable;
16032 crtc->active = crtc_state->base.active;
16033
16034 if (crtc_state->base.active) {
16035 dev_priv->active_crtcs |= 1 << crtc->pipe;
16036
c89e39f3 16037 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
565602d7 16038 pixclk = ilk_pipe_pixel_rate(crtc_state);
9558d15d 16039 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
565602d7
ML
16040 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16041 else
16042 WARN_ON(dev_priv->display.modeset_calc_cdclk);
9558d15d
VS
16043
16044 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16045 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16046 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
565602d7
ML
16047 }
16048
16049 dev_priv->min_pixclk[crtc->pipe] = pixclk;
b70709a6 16050
f9cd7b88 16051 readout_plane_state(crtc);
24929352 16052
78108b7c
VS
16053 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16054 crtc->base.base.id, crtc->base.name,
24929352
DV
16055 crtc->active ? "enabled" : "disabled");
16056 }
16057
5358901f
DV
16058 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16059 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16060
2edd6443
ACO
16061 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16062 &pll->config.hw_state);
3e369b76 16063 pll->config.crtc_mask = 0;
d3fcc808 16064 for_each_intel_crtc(dev, crtc) {
2dd66ebd 16065 if (crtc->active && crtc->config->shared_dpll == pll)
3e369b76 16066 pll->config.crtc_mask |= 1 << crtc->pipe;
5358901f 16067 }
2dd66ebd 16068 pll->active_mask = pll->config.crtc_mask;
5358901f 16069
1e6f2ddc 16070 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 16071 pll->name, pll->config.crtc_mask, pll->on);
5358901f
DV
16072 }
16073
b2784e15 16074 for_each_intel_encoder(dev, encoder) {
24929352
DV
16075 pipe = 0;
16076
16077 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB
16078 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16079 encoder->base.crtc = &crtc->base;
6e3c9717 16080 encoder->get_config(encoder, crtc->config);
24929352
DV
16081 } else {
16082 encoder->base.crtc = NULL;
16083 }
16084
6f2bcceb 16085 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 16086 encoder->base.base.id,
8e329a03 16087 encoder->base.name,
24929352 16088 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 16089 pipe_name(pipe));
24929352
DV
16090 }
16091
3a3371ff 16092 for_each_intel_connector(dev, connector) {
24929352
DV
16093 if (connector->get_hw_state(connector)) {
16094 connector->base.dpms = DRM_MODE_DPMS_ON;
2aa974c9
ML
16095
16096 encoder = connector->encoder;
16097 connector->base.encoder = &encoder->base;
16098
16099 if (encoder->base.crtc &&
16100 encoder->base.crtc->state->active) {
16101 /*
16102 * This has to be done during hardware readout
16103 * because anything calling .crtc_disable may
16104 * rely on the connector_mask being accurate.
16105 */
16106 encoder->base.crtc->state->connector_mask |=
16107 1 << drm_connector_index(&connector->base);
e87a52b3
ML
16108 encoder->base.crtc->state->encoder_mask |=
16109 1 << drm_encoder_index(&encoder->base);
2aa974c9
ML
16110 }
16111
24929352
DV
16112 } else {
16113 connector->base.dpms = DRM_MODE_DPMS_OFF;
16114 connector->base.encoder = NULL;
16115 }
16116 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16117 connector->base.base.id,
c23cc417 16118 connector->base.name,
24929352
DV
16119 connector->base.encoder ? "enabled" : "disabled");
16120 }
7f4c6284
VS
16121
16122 for_each_intel_crtc(dev, crtc) {
16123 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16124
16125 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16126 if (crtc->base.state->active) {
16127 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16128 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16129 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16130
16131 /*
16132 * The initial mode needs to be set in order to keep
16133 * the atomic core happy. It wants a valid mode if the
16134 * crtc's enabled, so we do the above call.
16135 *
16136 * At this point some state updated by the connectors
16137 * in their ->detect() callback has not run yet, so
16138 * no recalculation can be done yet.
16139 *
16140 * Even if we could do a recalculation and modeset
16141 * right now it would cause a double modeset if
16142 * fbdev or userspace chooses a different initial mode.
16143 *
16144 * If that happens, someone indicated they wanted a
16145 * mode change, which means it's safe to do a full
16146 * recalculation.
16147 */
16148 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
9eca6832
VS
16149
16150 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16151 update_scanline_offset(crtc);
7f4c6284 16152 }
e3b247da
VS
16153
16154 intel_pipe_config_sanity_check(dev_priv, crtc->config);
7f4c6284 16155 }
30e984df
DV
16156}
16157
043e9bda
ML
16158/* Scan out the current hw modeset state,
16159 * and sanitizes it to the current state
16160 */
16161static void
16162intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV
16163{
16164 struct drm_i915_private *dev_priv = dev->dev_private;
16165 enum pipe pipe;
30e984df
DV
16166 struct intel_crtc *crtc;
16167 struct intel_encoder *encoder;
35c95375 16168 int i;
30e984df
DV
16169
16170 intel_modeset_readout_hw_state(dev);
24929352
DV
16171
16172 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 16173 for_each_intel_encoder(dev, encoder) {
24929352
DV
16174 intel_sanitize_encoder(encoder);
16175 }
16176
055e393f 16177 for_each_pipe(dev_priv, pipe) {
24929352
DV
16178 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16179 intel_sanitize_crtc(crtc);
6e3c9717
ACO
16180 intel_dump_pipe_config(crtc, crtc->config,
16181 "[setup_hw_state]");
24929352 16182 }
9a935856 16183
d29b2f9d
ACO
16184 intel_modeset_update_connector_atomic_state(dev);
16185
35c95375
DV
16186 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16187 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16188
2dd66ebd 16189 if (!pll->on || pll->active_mask)
35c95375
DV
16190 continue;
16191
16192 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16193
2edd6443 16194 pll->funcs.disable(dev_priv, pll);
35c95375
DV
16195 pll->on = false;
16196 }
16197
666a4537 16198 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6eb1a681
VS
16199 vlv_wm_get_hw_state(dev);
16200 else if (IS_GEN9(dev))
3078999f
PB
16201 skl_wm_get_hw_state(dev);
16202 else if (HAS_PCH_SPLIT(dev))
243e6a44 16203 ilk_wm_get_hw_state(dev);
292b990e
ML
16204
16205 for_each_intel_crtc(dev, crtc) {
16206 unsigned long put_domains;
16207
74bff5f9 16208 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
292b990e
ML
16209 if (WARN_ON(put_domains))
16210 modeset_put_power_domains(dev_priv, put_domains);
16211 }
16212 intel_display_set_init_power(dev_priv, false);
010cf73d
PZ
16213
16214 intel_fbc_init_pipe_state(dev_priv);
043e9bda 16215}
7d0bc1ea 16216
043e9bda
ML
16217void intel_display_resume(struct drm_device *dev)
16218{
e2c8b870
ML
16219 struct drm_i915_private *dev_priv = to_i915(dev);
16220 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16221 struct drm_modeset_acquire_ctx ctx;
043e9bda 16222 int ret;
e2c8b870 16223 bool setup = false;
f30da187 16224
e2c8b870 16225 dev_priv->modeset_restore_state = NULL;
043e9bda 16226
ea49c9ac
ML
16227 /*
16228 * This is a cludge because with real atomic modeset mode_config.mutex
16229 * won't be taken. Unfortunately some probed state like
16230 * audio_codec_enable is still protected by mode_config.mutex, so lock
16231 * it here for now.
16232 */
16233 mutex_lock(&dev->mode_config.mutex);
e2c8b870 16234 drm_modeset_acquire_init(&ctx, 0);
043e9bda 16235
e2c8b870
ML
16236retry:
16237 ret = drm_modeset_lock_all_ctx(dev, &ctx);
043e9bda 16238
e2c8b870
ML
16239 if (ret == 0 && !setup) {
16240 setup = true;
043e9bda 16241
e2c8b870
ML
16242 intel_modeset_setup_hw_state(dev);
16243 i915_redisable_vga(dev);
45e2b5f6 16244 }
8af6cf88 16245
e2c8b870
ML
16246 if (ret == 0 && state) {
16247 struct drm_crtc_state *crtc_state;
16248 struct drm_crtc *crtc;
16249 int i;
043e9bda 16250
e2c8b870
ML
16251 state->acquire_ctx = &ctx;
16252
e3d5457c
VS
16253 /* ignore any reset values/BIOS leftovers in the WM registers */
16254 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16255
e2c8b870
ML
16256 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16257 /*
16258 * Force recalculation even if we restore
16259 * current state. With fast modeset this may not result
16260 * in a modeset when the state is compatible.
16261 */
16262 crtc_state->mode_changed = true;
16263 }
16264
16265 ret = drm_atomic_commit(state);
043e9bda
ML
16266 }
16267
e2c8b870
ML
16268 if (ret == -EDEADLK) {
16269 drm_modeset_backoff(&ctx);
16270 goto retry;
16271 }
043e9bda 16272
e2c8b870
ML
16273 drm_modeset_drop_locks(&ctx);
16274 drm_modeset_acquire_fini(&ctx);
ea49c9ac 16275 mutex_unlock(&dev->mode_config.mutex);
043e9bda 16276
e2c8b870
ML
16277 if (ret) {
16278 DRM_ERROR("Restoring old state failed with %i\n", ret);
16279 drm_atomic_state_free(state);
16280 }
2c7111db
CW
16281}
16282
16283void intel_modeset_gem_init(struct drm_device *dev)
16284{
dc97997a 16285 struct drm_i915_private *dev_priv = to_i915(dev);
484b41dd 16286 struct drm_crtc *c;
2ff8fde1 16287 struct drm_i915_gem_object *obj;
e0d6149b 16288 int ret;
484b41dd 16289
dc97997a 16290 intel_init_gt_powersave(dev_priv);
ae48434c 16291
1833b134 16292 intel_modeset_init_hw(dev);
02e792fb 16293
1ee8da6d 16294 intel_setup_overlay(dev_priv);
484b41dd
JB
16295
16296 /*
16297 * Make sure any fbs we allocated at startup are properly
16298 * pinned & fenced. When we do the allocation it's too early
16299 * for this.
16300 */
70e1e0ec 16301 for_each_crtc(dev, c) {
2ff8fde1
MR
16302 obj = intel_fb_obj(c->primary->fb);
16303 if (obj == NULL)
484b41dd
JB
16304 continue;
16305
e0d6149b 16306 mutex_lock(&dev->struct_mutex);
3465c580
VS
16307 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16308 c->primary->state->rotation);
e0d6149b
TU
16309 mutex_unlock(&dev->struct_mutex);
16310 if (ret) {
484b41dd
JB
16311 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16312 to_intel_crtc(c)->pipe);
66e514c1 16313 drm_framebuffer_unreference(c->primary->fb);
5a21b665 16314 c->primary->fb = NULL;
36750f28 16315 c->primary->crtc = c->primary->state->crtc = NULL;
5a21b665 16316 update_state_fb(c->primary);
36750f28 16317 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB
16318 }
16319 }
1ebaa0b9
CW
16320}
16321
16322int intel_connector_register(struct drm_connector *connector)
16323{
16324 struct intel_connector *intel_connector = to_intel_connector(connector);
16325 int ret;
16326
16327 ret = intel_backlight_device_register(intel_connector);
16328 if (ret)
16329 goto err;
16330
16331 return 0;
0962c3c9 16332
1ebaa0b9
CW
16333err:
16334 return ret;
79e53945
JB
16335}
16336
c191eca1 16337void intel_connector_unregister(struct drm_connector *connector)
4932e2c3 16338{
e63d87c0 16339 struct intel_connector *intel_connector = to_intel_connector(connector);
4932e2c3 16340
e63d87c0 16341 intel_backlight_device_unregister(intel_connector);
4932e2c3 16342 intel_panel_destroy_backlight(connector);
4932e2c3
ID
16343}
16344
79e53945
JB
16345void intel_modeset_cleanup(struct drm_device *dev)
16346{
652c393a 16347 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 16348
dc97997a 16349 intel_disable_gt_powersave(dev_priv);
2eb5252e 16350
fd0c0642
DV
16351 /*
16352 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 16353 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV
16354 * experience fancy races otherwise.
16355 */
2aeb7d3a 16356 intel_irq_uninstall(dev_priv);
eb21b92b 16357
fd0c0642
DV
16358 /*
16359 * Due to the hpd irq storm handling the hotplug work can re-arm the
16360 * poll handlers. Hence disable polling after hpd handling is shut down.
16361 */
f87ea761 16362 drm_kms_helper_poll_fini(dev);
fd0c0642 16363
723bfd70
JB
16364 intel_unregister_dsm_handler();
16365
c937ab3e 16366 intel_fbc_global_disable(dev_priv);
69341a5e 16367
1630fe75
CW
16368 /* flush any delayed tasks or pending work */
16369 flush_scheduled_work();
16370
79e53945 16371 drm_mode_config_cleanup(dev);
4d7bb011 16372
1ee8da6d 16373 intel_cleanup_overlay(dev_priv);
ae48434c 16374
dc97997a 16375 intel_cleanup_gt_powersave(dev_priv);
f5949141
DV
16376
16377 intel_teardown_gmbus(dev);
79e53945
JB
16378}
16379
df0e9248
CW
16380void intel_connector_attach_encoder(struct intel_connector *connector,
16381 struct intel_encoder *encoder)
16382{
16383 connector->encoder = encoder;
16384 drm_mode_connector_attach_encoder(&connector->base,
16385 &encoder->base);
79e53945 16386}
28d52043
DA
16387
16388/*
16389 * set vga decode state - true == enable VGA decode
16390 */
16391int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16392{
16393 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 16394 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA
16395 u16 gmch_ctrl;
16396
75fa041d
CW
16397 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16398 DRM_ERROR("failed to read control word\n");
16399 return -EIO;
16400 }
16401
c0cc8a55
CW
16402 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16403 return 0;
16404
28d52043
DA
16405 if (state)
16406 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16407 else
16408 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW
16409
16410 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16411 DRM_ERROR("failed to write control word\n");
16412 return -EIO;
16413 }
16414
28d52043
DA
16415 return 0;
16416}
c4a1d9e4 16417
c4a1d9e4 16418struct intel_display_error_state {
ff57f1b0
PZ
16419
16420 u32 power_well_driver;
16421
63b66e5b
CW
16422 int num_transcoders;
16423
c4a1d9e4
CW
16424 struct intel_cursor_error_state {
16425 u32 control;
16426 u32 position;
16427 u32 base;
16428 u32 size;
52331309 16429 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW
16430
16431 struct intel_pipe_error_state {
ddf9c536 16432 bool power_domain_on;
c4a1d9e4 16433 u32 source;
f301b1e1 16434 u32 stat;
52331309 16435 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW
16436
16437 struct intel_plane_error_state {
16438 u32 control;
16439 u32 stride;
16440 u32 size;
16441 u32 pos;
16442 u32 addr;
16443 u32 surface;
16444 u32 tile_offset;
52331309 16445 } plane[I915_MAX_PIPES];
63b66e5b
CW
16446
16447 struct intel_transcoder_error_state {
ddf9c536 16448 bool power_domain_on;
63b66e5b
CW
16449 enum transcoder cpu_transcoder;
16450
16451 u32 conf;
16452
16453 u32 htotal;
16454 u32 hblank;
16455 u32 hsync;
16456 u32 vtotal;
16457 u32 vblank;
16458 u32 vsync;
16459 } transcoder[4];
c4a1d9e4
CW
16460};
16461
16462struct intel_display_error_state *
c033666a 16463intel_display_capture_error_state(struct drm_i915_private *dev_priv)
c4a1d9e4 16464{
c4a1d9e4 16465 struct intel_display_error_state *error;
63b66e5b
CW
16466 int transcoders[] = {
16467 TRANSCODER_A,
16468 TRANSCODER_B,
16469 TRANSCODER_C,
16470 TRANSCODER_EDP,
16471 };
c4a1d9e4
CW
16472 int i;
16473
c033666a 16474 if (INTEL_INFO(dev_priv)->num_pipes == 0)
63b66e5b
CW
16475 return NULL;
16476
9d1cb914 16477 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW
16478 if (error == NULL)
16479 return NULL;
16480
c033666a 16481 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ff57f1b0
PZ
16482 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16483
055e393f 16484 for_each_pipe(dev_priv, i) {
ddf9c536 16485 error->pipe[i].power_domain_on =
f458ebbc
DV
16486 __intel_display_power_is_enabled(dev_priv,
16487 POWER_DOMAIN_PIPE(i));
ddf9c536 16488 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ
16489 continue;
16490
5efb3e28
VS
16491 error->cursor[i].control = I915_READ(CURCNTR(i));
16492 error->cursor[i].position = I915_READ(CURPOS(i));
16493 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW
16494
16495 error->plane[i].control = I915_READ(DSPCNTR(i));
16496 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
c033666a 16497 if (INTEL_GEN(dev_priv) <= 3) {
51889b35 16498 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ
16499 error->plane[i].pos = I915_READ(DSPPOS(i));
16500 }
c033666a 16501 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
ca291363 16502 error->plane[i].addr = I915_READ(DSPADDR(i));
c033666a 16503 if (INTEL_GEN(dev_priv) >= 4) {
c4a1d9e4
CW
16504 error->plane[i].surface = I915_READ(DSPSURF(i));
16505 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16506 }
16507
c4a1d9e4 16508 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 16509
c033666a 16510 if (HAS_GMCH_DISPLAY(dev_priv))
f301b1e1 16511 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW
16512 }
16513
4d1de975 16514 /* Note: this does not include DSI transcoders. */
c033666a 16515 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
2d1fe073 16516 if (HAS_DDI(dev_priv))
63b66e5b
CW
16517 error->num_transcoders++; /* Account for eDP. */
16518
16519 for (i = 0; i < error->num_transcoders; i++) {
16520 enum transcoder cpu_transcoder = transcoders[i];
16521
ddf9c536 16522 error->transcoder[i].power_domain_on =
f458ebbc 16523 __intel_display_power_is_enabled(dev_priv,
38cc1daf 16524 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 16525 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ
16526 continue;
16527
63b66e5b
CW
16528 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16529
16530 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16531 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16532 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16533 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16534 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16535 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16536 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW
16537 }
16538
16539 return error;
16540}
16541
edc3d884
MK
16542#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16543
c4a1d9e4 16544void
edc3d884 16545intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW
16546 struct drm_device *dev,
16547 struct intel_display_error_state *error)
16548{
055e393f 16549 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW
16550 int i;
16551
63b66e5b
CW
16552 if (!error)
16553 return;
16554
edc3d884 16555 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 16556 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 16557 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 16558 error->power_well_driver);
055e393f 16559 for_each_pipe(dev_priv, i) {
edc3d884 16560 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536 16561 err_printf(m, " Power: %s\n",
87ad3212 16562 onoff(error->pipe[i].power_domain_on));
edc3d884 16563 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 16564 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK
16565
16566 err_printf(m, "Plane [%d]:\n", i);
16567 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16568 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 16569 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK
16570 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16571 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 16572 }
4b71a570 16573 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 16574 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 16575 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK
16576 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16577 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW
16578 }
16579
edc3d884
MK
16580 err_printf(m, "Cursor [%d]:\n", i);
16581 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16582 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16583 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 16584 }
63b66e5b
CW
16585
16586 for (i = 0; i < error->num_transcoders; i++) {
da205630 16587 err_printf(m, "CPU transcoder: %s\n",
63b66e5b 16588 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536 16589 err_printf(m, " Power: %s\n",
87ad3212 16590 onoff(error->transcoder[i].power_domain_on));
63b66e5b
CW
16591 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16592 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16593 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16594 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16595 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16596 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16597 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16598 }
c4a1d9e4 16599}