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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
200757f5 | 119 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
e7457a9a | 120 | |
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
bfa7df01 VS |
136 | /* returns HPLL frequency in kHz */ |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
150 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
151 | const char *name, u32 reg) | |
152 | { | |
153 | u32 val; | |
154 | int divider; | |
155 | ||
156 | if (dev_priv->hpll_freq == 0) | |
157 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
158 | ||
159 | mutex_lock(&dev_priv->sb_lock); | |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
169 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
170 | } | |
171 | ||
e7dc33f3 VS |
172 | static int |
173 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 174 | { |
e7dc33f3 VS |
175 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
176 | } | |
d2acd215 | 177 | |
e7dc33f3 VS |
178 | static int |
179 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
180 | { | |
35d38d1f VS |
181 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
182 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
183 | } |
184 | ||
e7dc33f3 VS |
185 | static int |
186 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 187 | { |
79e50a4f JN |
188 | uint32_t clkcfg; |
189 | ||
e7dc33f3 | 190 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
191 | clkcfg = I915_READ(CLKCFG); |
192 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
193 | case CLKCFG_FSB_400: | |
e7dc33f3 | 194 | return 100000; |
79e50a4f | 195 | case CLKCFG_FSB_533: |
e7dc33f3 | 196 | return 133333; |
79e50a4f | 197 | case CLKCFG_FSB_667: |
e7dc33f3 | 198 | return 166667; |
79e50a4f | 199 | case CLKCFG_FSB_800: |
e7dc33f3 | 200 | return 200000; |
79e50a4f | 201 | case CLKCFG_FSB_1067: |
e7dc33f3 | 202 | return 266667; |
79e50a4f | 203 | case CLKCFG_FSB_1333: |
e7dc33f3 | 204 | return 333333; |
79e50a4f JN |
205 | /* these two are just a guess; one of them might be right */ |
206 | case CLKCFG_FSB_1600: | |
207 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 208 | return 400000; |
79e50a4f | 209 | default: |
e7dc33f3 | 210 | return 133333; |
79e50a4f JN |
211 | } |
212 | } | |
213 | ||
e7dc33f3 VS |
214 | static void intel_update_rawclk(struct drm_i915_private *dev_priv) |
215 | { | |
216 | if (HAS_PCH_SPLIT(dev_priv)) | |
217 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
218 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
219 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
220 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
221 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
222 | else | |
223 | return; /* no rawclk on other platforms, or no need to know it */ | |
224 | ||
225 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
226 | } | |
227 | ||
bfa7df01 VS |
228 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
229 | { | |
666a4537 | 230 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
231 | return; |
232 | ||
233 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
234 | CCK_CZ_CLOCK_CONTROL); | |
235 | ||
236 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
237 | } | |
238 | ||
021357ac | 239 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
240 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
241 | const struct intel_crtc_state *pipe_config) | |
021357ac | 242 | { |
21a727b3 VS |
243 | if (HAS_DDI(dev_priv)) |
244 | return pipe_config->port_clock; /* SPLL */ | |
245 | else if (IS_GEN5(dev_priv)) | |
246 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 247 | else |
21a727b3 | 248 | return 270000; |
021357ac CW |
249 | } |
250 | ||
5d536e28 | 251 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 252 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 253 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 254 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
255 | .m = { .min = 96, .max = 140 }, |
256 | .m1 = { .min = 18, .max = 26 }, | |
257 | .m2 = { .min = 6, .max = 16 }, | |
258 | .p = { .min = 4, .max = 128 }, | |
259 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
260 | .p2 = { .dot_limit = 165000, |
261 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
262 | }; |
263 | ||
5d536e28 DV |
264 | static const intel_limit_t intel_limits_i8xx_dvo = { |
265 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 266 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 267 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
268 | .m = { .min = 96, .max = 140 }, |
269 | .m1 = { .min = 18, .max = 26 }, | |
270 | .m2 = { .min = 6, .max = 16 }, | |
271 | .p = { .min = 4, .max = 128 }, | |
272 | .p1 = { .min = 2, .max = 33 }, | |
273 | .p2 = { .dot_limit = 165000, | |
274 | .p2_slow = 4, .p2_fast = 4 }, | |
275 | }; | |
276 | ||
e4b36699 | 277 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 278 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 279 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 280 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
281 | .m = { .min = 96, .max = 140 }, |
282 | .m1 = { .min = 18, .max = 26 }, | |
283 | .m2 = { .min = 6, .max = 16 }, | |
284 | .p = { .min = 4, .max = 128 }, | |
285 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
286 | .p2 = { .dot_limit = 165000, |
287 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 288 | }; |
273e27ca | 289 | |
e4b36699 | 290 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
291 | .dot = { .min = 20000, .max = 400000 }, |
292 | .vco = { .min = 1400000, .max = 2800000 }, | |
293 | .n = { .min = 1, .max = 6 }, | |
294 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
295 | .m1 = { .min = 8, .max = 18 }, |
296 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
297 | .p = { .min = 5, .max = 80 }, |
298 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
299 | .p2 = { .dot_limit = 200000, |
300 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
301 | }; |
302 | ||
303 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
304 | .dot = { .min = 20000, .max = 400000 }, |
305 | .vco = { .min = 1400000, .max = 2800000 }, | |
306 | .n = { .min = 1, .max = 6 }, | |
307 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
308 | .m1 = { .min = 8, .max = 18 }, |
309 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
310 | .p = { .min = 7, .max = 98 }, |
311 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
312 | .p2 = { .dot_limit = 112000, |
313 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
314 | }; |
315 | ||
273e27ca | 316 | |
e4b36699 | 317 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
318 | .dot = { .min = 25000, .max = 270000 }, |
319 | .vco = { .min = 1750000, .max = 3500000}, | |
320 | .n = { .min = 1, .max = 4 }, | |
321 | .m = { .min = 104, .max = 138 }, | |
322 | .m1 = { .min = 17, .max = 23 }, | |
323 | .m2 = { .min = 5, .max = 11 }, | |
324 | .p = { .min = 10, .max = 30 }, | |
325 | .p1 = { .min = 1, .max = 3}, | |
326 | .p2 = { .dot_limit = 270000, | |
327 | .p2_slow = 10, | |
328 | .p2_fast = 10 | |
044c7c41 | 329 | }, |
e4b36699 KP |
330 | }; |
331 | ||
332 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
333 | .dot = { .min = 22000, .max = 400000 }, |
334 | .vco = { .min = 1750000, .max = 3500000}, | |
335 | .n = { .min = 1, .max = 4 }, | |
336 | .m = { .min = 104, .max = 138 }, | |
337 | .m1 = { .min = 16, .max = 23 }, | |
338 | .m2 = { .min = 5, .max = 11 }, | |
339 | .p = { .min = 5, .max = 80 }, | |
340 | .p1 = { .min = 1, .max = 8}, | |
341 | .p2 = { .dot_limit = 165000, | |
342 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
343 | }; |
344 | ||
345 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
346 | .dot = { .min = 20000, .max = 115000 }, |
347 | .vco = { .min = 1750000, .max = 3500000 }, | |
348 | .n = { .min = 1, .max = 3 }, | |
349 | .m = { .min = 104, .max = 138 }, | |
350 | .m1 = { .min = 17, .max = 23 }, | |
351 | .m2 = { .min = 5, .max = 11 }, | |
352 | .p = { .min = 28, .max = 112 }, | |
353 | .p1 = { .min = 2, .max = 8 }, | |
354 | .p2 = { .dot_limit = 0, | |
355 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 356 | }, |
e4b36699 KP |
357 | }; |
358 | ||
359 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
360 | .dot = { .min = 80000, .max = 224000 }, |
361 | .vco = { .min = 1750000, .max = 3500000 }, | |
362 | .n = { .min = 1, .max = 3 }, | |
363 | .m = { .min = 104, .max = 138 }, | |
364 | .m1 = { .min = 17, .max = 23 }, | |
365 | .m2 = { .min = 5, .max = 11 }, | |
366 | .p = { .min = 14, .max = 42 }, | |
367 | .p1 = { .min = 2, .max = 6 }, | |
368 | .p2 = { .dot_limit = 0, | |
369 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 370 | }, |
e4b36699 KP |
371 | }; |
372 | ||
f2b115e6 | 373 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
374 | .dot = { .min = 20000, .max = 400000}, |
375 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 376 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
377 | .n = { .min = 3, .max = 6 }, |
378 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 379 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
380 | .m1 = { .min = 0, .max = 0 }, |
381 | .m2 = { .min = 0, .max = 254 }, | |
382 | .p = { .min = 5, .max = 80 }, | |
383 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
384 | .p2 = { .dot_limit = 200000, |
385 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
386 | }; |
387 | ||
f2b115e6 | 388 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
389 | .dot = { .min = 20000, .max = 400000 }, |
390 | .vco = { .min = 1700000, .max = 3500000 }, | |
391 | .n = { .min = 3, .max = 6 }, | |
392 | .m = { .min = 2, .max = 256 }, | |
393 | .m1 = { .min = 0, .max = 0 }, | |
394 | .m2 = { .min = 0, .max = 254 }, | |
395 | .p = { .min = 7, .max = 112 }, | |
396 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
397 | .p2 = { .dot_limit = 112000, |
398 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
399 | }; |
400 | ||
273e27ca EA |
401 | /* Ironlake / Sandybridge |
402 | * | |
403 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
404 | * the range value for them is (actual_value - 2). | |
405 | */ | |
b91ad0ec | 406 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
407 | .dot = { .min = 25000, .max = 350000 }, |
408 | .vco = { .min = 1760000, .max = 3510000 }, | |
409 | .n = { .min = 1, .max = 5 }, | |
410 | .m = { .min = 79, .max = 127 }, | |
411 | .m1 = { .min = 12, .max = 22 }, | |
412 | .m2 = { .min = 5, .max = 9 }, | |
413 | .p = { .min = 5, .max = 80 }, | |
414 | .p1 = { .min = 1, .max = 8 }, | |
415 | .p2 = { .dot_limit = 225000, | |
416 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
417 | }; |
418 | ||
b91ad0ec | 419 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
420 | .dot = { .min = 25000, .max = 350000 }, |
421 | .vco = { .min = 1760000, .max = 3510000 }, | |
422 | .n = { .min = 1, .max = 3 }, | |
423 | .m = { .min = 79, .max = 118 }, | |
424 | .m1 = { .min = 12, .max = 22 }, | |
425 | .m2 = { .min = 5, .max = 9 }, | |
426 | .p = { .min = 28, .max = 112 }, | |
427 | .p1 = { .min = 2, .max = 8 }, | |
428 | .p2 = { .dot_limit = 225000, | |
429 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
430 | }; |
431 | ||
432 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
433 | .dot = { .min = 25000, .max = 350000 }, |
434 | .vco = { .min = 1760000, .max = 3510000 }, | |
435 | .n = { .min = 1, .max = 3 }, | |
436 | .m = { .min = 79, .max = 127 }, | |
437 | .m1 = { .min = 12, .max = 22 }, | |
438 | .m2 = { .min = 5, .max = 9 }, | |
439 | .p = { .min = 14, .max = 56 }, | |
440 | .p1 = { .min = 2, .max = 8 }, | |
441 | .p2 = { .dot_limit = 225000, | |
442 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
443 | }; |
444 | ||
273e27ca | 445 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 446 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
447 | .dot = { .min = 25000, .max = 350000 }, |
448 | .vco = { .min = 1760000, .max = 3510000 }, | |
449 | .n = { .min = 1, .max = 2 }, | |
450 | .m = { .min = 79, .max = 126 }, | |
451 | .m1 = { .min = 12, .max = 22 }, | |
452 | .m2 = { .min = 5, .max = 9 }, | |
453 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 454 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
455 | .p2 = { .dot_limit = 225000, |
456 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
457 | }; |
458 | ||
459 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
460 | .dot = { .min = 25000, .max = 350000 }, |
461 | .vco = { .min = 1760000, .max = 3510000 }, | |
462 | .n = { .min = 1, .max = 3 }, | |
463 | .m = { .min = 79, .max = 126 }, | |
464 | .m1 = { .min = 12, .max = 22 }, | |
465 | .m2 = { .min = 5, .max = 9 }, | |
466 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 467 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
468 | .p2 = { .dot_limit = 225000, |
469 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
470 | }; |
471 | ||
dc730512 | 472 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
473 | /* |
474 | * These are the data rate limits (measured in fast clocks) | |
475 | * since those are the strictest limits we have. The fast | |
476 | * clock and actual rate limits are more relaxed, so checking | |
477 | * them would make no difference. | |
478 | */ | |
479 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 480 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 481 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
482 | .m1 = { .min = 2, .max = 3 }, |
483 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 484 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 485 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
486 | }; |
487 | ||
ef9348c8 CML |
488 | static const intel_limit_t intel_limits_chv = { |
489 | /* | |
490 | * These are the data rate limits (measured in fast clocks) | |
491 | * since those are the strictest limits we have. The fast | |
492 | * clock and actual rate limits are more relaxed, so checking | |
493 | * them would make no difference. | |
494 | */ | |
495 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 496 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
497 | .n = { .min = 1, .max = 1 }, |
498 | .m1 = { .min = 2, .max = 2 }, | |
499 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
500 | .p1 = { .min = 2, .max = 4 }, | |
501 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
502 | }; | |
503 | ||
5ab7b0b7 ID |
504 | static const intel_limit_t intel_limits_bxt = { |
505 | /* FIXME: find real dot limits */ | |
506 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 507 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
508 | .n = { .min = 1, .max = 1 }, |
509 | .m1 = { .min = 2, .max = 2 }, | |
510 | /* FIXME: find real m2 limits */ | |
511 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
512 | .p1 = { .min = 2, .max = 4 }, | |
513 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
514 | }; | |
515 | ||
cdba954e ACO |
516 | static bool |
517 | needs_modeset(struct drm_crtc_state *state) | |
518 | { | |
fc596660 | 519 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
520 | } |
521 | ||
e0638cdf PZ |
522 | /** |
523 | * Returns whether any output on the specified pipe is of the specified type | |
524 | */ | |
4093561b | 525 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 526 | { |
409ee761 | 527 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
528 | struct intel_encoder *encoder; |
529 | ||
409ee761 | 530 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
531 | if (encoder->type == type) |
532 | return true; | |
533 | ||
534 | return false; | |
535 | } | |
536 | ||
d0737e1d ACO |
537 | /** |
538 | * Returns whether any output on the specified pipe will have the specified | |
539 | * type after a staged modeset is complete, i.e., the same as | |
540 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
541 | * encoder->crtc. | |
542 | */ | |
a93e255f ACO |
543 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
544 | int type) | |
d0737e1d | 545 | { |
a93e255f | 546 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 547 | struct drm_connector *connector; |
a93e255f | 548 | struct drm_connector_state *connector_state; |
d0737e1d | 549 | struct intel_encoder *encoder; |
a93e255f ACO |
550 | int i, num_connectors = 0; |
551 | ||
da3ced29 | 552 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
553 | if (connector_state->crtc != crtc_state->base.crtc) |
554 | continue; | |
555 | ||
556 | num_connectors++; | |
d0737e1d | 557 | |
a93e255f ACO |
558 | encoder = to_intel_encoder(connector_state->best_encoder); |
559 | if (encoder->type == type) | |
d0737e1d | 560 | return true; |
a93e255f ACO |
561 | } |
562 | ||
563 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
564 | |
565 | return false; | |
566 | } | |
567 | ||
a93e255f ACO |
568 | static const intel_limit_t * |
569 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 570 | { |
a93e255f | 571 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 572 | const intel_limit_t *limit; |
b91ad0ec | 573 | |
a93e255f | 574 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 575 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 576 | if (refclk == 100000) |
b91ad0ec ZW |
577 | limit = &intel_limits_ironlake_dual_lvds_100m; |
578 | else | |
579 | limit = &intel_limits_ironlake_dual_lvds; | |
580 | } else { | |
1b894b59 | 581 | if (refclk == 100000) |
b91ad0ec ZW |
582 | limit = &intel_limits_ironlake_single_lvds_100m; |
583 | else | |
584 | limit = &intel_limits_ironlake_single_lvds; | |
585 | } | |
c6bb3538 | 586 | } else |
b91ad0ec | 587 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
588 | |
589 | return limit; | |
590 | } | |
591 | ||
a93e255f ACO |
592 | static const intel_limit_t * |
593 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 594 | { |
a93e255f | 595 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
596 | const intel_limit_t *limit; |
597 | ||
a93e255f | 598 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 599 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 600 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 601 | else |
e4b36699 | 602 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
603 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
604 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 605 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 606 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 607 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 608 | } else /* The option is for other outputs */ |
e4b36699 | 609 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
610 | |
611 | return limit; | |
612 | } | |
613 | ||
a93e255f ACO |
614 | static const intel_limit_t * |
615 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 616 | { |
a93e255f | 617 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
618 | const intel_limit_t *limit; |
619 | ||
5ab7b0b7 ID |
620 | if (IS_BROXTON(dev)) |
621 | limit = &intel_limits_bxt; | |
622 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 623 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 624 | else if (IS_G4X(dev)) { |
a93e255f | 625 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 626 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 627 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 628 | limit = &intel_limits_pineview_lvds; |
2177832f | 629 | else |
f2b115e6 | 630 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
631 | } else if (IS_CHERRYVIEW(dev)) { |
632 | limit = &intel_limits_chv; | |
a0c4da24 | 633 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 634 | limit = &intel_limits_vlv; |
a6c45cf0 | 635 | } else if (!IS_GEN2(dev)) { |
a93e255f | 636 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
637 | limit = &intel_limits_i9xx_lvds; |
638 | else | |
639 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 640 | } else { |
a93e255f | 641 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 642 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 643 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 644 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
645 | else |
646 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
647 | } |
648 | return limit; | |
649 | } | |
650 | ||
dccbea3b ID |
651 | /* |
652 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
653 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
654 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
655 | * The helpers' return value is the rate of the clock that is fed to the | |
656 | * display engine's pipe which can be the above fast dot clock rate or a | |
657 | * divided-down version of it. | |
658 | */ | |
f2b115e6 | 659 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 660 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 661 | { |
2177832f SL |
662 | clock->m = clock->m2 + 2; |
663 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 664 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 665 | return 0; |
fb03ac01 VS |
666 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
667 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
668 | |
669 | return clock->dot; | |
2177832f SL |
670 | } |
671 | ||
7429e9d4 DV |
672 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
673 | { | |
674 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
675 | } | |
676 | ||
dccbea3b | 677 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 678 | { |
7429e9d4 | 679 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 680 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 681 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 682 | return 0; |
fb03ac01 VS |
683 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
684 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
685 | |
686 | return clock->dot; | |
79e53945 JB |
687 | } |
688 | ||
dccbea3b | 689 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
690 | { |
691 | clock->m = clock->m1 * clock->m2; | |
692 | clock->p = clock->p1 * clock->p2; | |
693 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 694 | return 0; |
589eca67 ID |
695 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
696 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
697 | |
698 | return clock->dot / 5; | |
589eca67 ID |
699 | } |
700 | ||
dccbea3b | 701 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
702 | { |
703 | clock->m = clock->m1 * clock->m2; | |
704 | clock->p = clock->p1 * clock->p2; | |
705 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 706 | return 0; |
ef9348c8 CML |
707 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
708 | clock->n << 22); | |
709 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
710 | |
711 | return clock->dot / 5; | |
ef9348c8 CML |
712 | } |
713 | ||
7c04d1d9 | 714 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
715 | /** |
716 | * Returns whether the given set of divisors are valid for a given refclk with | |
717 | * the given connectors. | |
718 | */ | |
719 | ||
1b894b59 CW |
720 | static bool intel_PLL_is_valid(struct drm_device *dev, |
721 | const intel_limit_t *limit, | |
722 | const intel_clock_t *clock) | |
79e53945 | 723 | { |
f01b7962 VS |
724 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
725 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 726 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 727 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 728 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 729 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 730 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 731 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 732 | |
666a4537 WB |
733 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
734 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
735 | if (clock->m1 <= clock->m2) |
736 | INTELPllInvalid("m1 <= m2\n"); | |
737 | ||
666a4537 | 738 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
739 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
740 | INTELPllInvalid("p out of range\n"); | |
741 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
742 | INTELPllInvalid("m out of range\n"); | |
743 | } | |
744 | ||
79e53945 | 745 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 746 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
747 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
748 | * connector, etc., rather than just a single range. | |
749 | */ | |
750 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 751 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
752 | |
753 | return true; | |
754 | } | |
755 | ||
3b1429d9 VS |
756 | static int |
757 | i9xx_select_p2_div(const intel_limit_t *limit, | |
758 | const struct intel_crtc_state *crtc_state, | |
759 | int target) | |
79e53945 | 760 | { |
3b1429d9 | 761 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 762 | |
a93e255f | 763 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 764 | /* |
a210b028 DV |
765 | * For LVDS just rely on its current settings for dual-channel. |
766 | * We haven't figured out how to reliably set up different | |
767 | * single/dual channel state, if we even can. | |
79e53945 | 768 | */ |
1974cad0 | 769 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 770 | return limit->p2.p2_fast; |
79e53945 | 771 | else |
3b1429d9 | 772 | return limit->p2.p2_slow; |
79e53945 JB |
773 | } else { |
774 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 775 | return limit->p2.p2_slow; |
79e53945 | 776 | else |
3b1429d9 | 777 | return limit->p2.p2_fast; |
79e53945 | 778 | } |
3b1429d9 VS |
779 | } |
780 | ||
781 | static bool | |
782 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
783 | struct intel_crtc_state *crtc_state, | |
784 | int target, int refclk, intel_clock_t *match_clock, | |
785 | intel_clock_t *best_clock) | |
786 | { | |
787 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
788 | intel_clock_t clock; | |
789 | int err = target; | |
79e53945 | 790 | |
0206e353 | 791 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 792 | |
3b1429d9 VS |
793 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
794 | ||
42158660 ZY |
795 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
796 | clock.m1++) { | |
797 | for (clock.m2 = limit->m2.min; | |
798 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 799 | if (clock.m2 >= clock.m1) |
42158660 ZY |
800 | break; |
801 | for (clock.n = limit->n.min; | |
802 | clock.n <= limit->n.max; clock.n++) { | |
803 | for (clock.p1 = limit->p1.min; | |
804 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
805 | int this_err; |
806 | ||
dccbea3b | 807 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
808 | if (!intel_PLL_is_valid(dev, limit, |
809 | &clock)) | |
810 | continue; | |
811 | if (match_clock && | |
812 | clock.p != match_clock->p) | |
813 | continue; | |
814 | ||
815 | this_err = abs(clock.dot - target); | |
816 | if (this_err < err) { | |
817 | *best_clock = clock; | |
818 | err = this_err; | |
819 | } | |
820 | } | |
821 | } | |
822 | } | |
823 | } | |
824 | ||
825 | return (err != target); | |
826 | } | |
827 | ||
828 | static bool | |
a93e255f ACO |
829 | pnv_find_best_dpll(const intel_limit_t *limit, |
830 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
831 | int target, int refclk, intel_clock_t *match_clock, |
832 | intel_clock_t *best_clock) | |
79e53945 | 833 | { |
3b1429d9 | 834 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 835 | intel_clock_t clock; |
79e53945 JB |
836 | int err = target; |
837 | ||
0206e353 | 838 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 839 | |
3b1429d9 VS |
840 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
841 | ||
42158660 ZY |
842 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
843 | clock.m1++) { | |
844 | for (clock.m2 = limit->m2.min; | |
845 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
846 | for (clock.n = limit->n.min; |
847 | clock.n <= limit->n.max; clock.n++) { | |
848 | for (clock.p1 = limit->p1.min; | |
849 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
850 | int this_err; |
851 | ||
dccbea3b | 852 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
853 | if (!intel_PLL_is_valid(dev, limit, |
854 | &clock)) | |
79e53945 | 855 | continue; |
cec2f356 SP |
856 | if (match_clock && |
857 | clock.p != match_clock->p) | |
858 | continue; | |
79e53945 JB |
859 | |
860 | this_err = abs(clock.dot - target); | |
861 | if (this_err < err) { | |
862 | *best_clock = clock; | |
863 | err = this_err; | |
864 | } | |
865 | } | |
866 | } | |
867 | } | |
868 | } | |
869 | ||
870 | return (err != target); | |
871 | } | |
872 | ||
d4906093 | 873 | static bool |
a93e255f ACO |
874 | g4x_find_best_dpll(const intel_limit_t *limit, |
875 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
876 | int target, int refclk, intel_clock_t *match_clock, |
877 | intel_clock_t *best_clock) | |
d4906093 | 878 | { |
3b1429d9 | 879 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
880 | intel_clock_t clock; |
881 | int max_n; | |
3b1429d9 | 882 | bool found = false; |
6ba770dc AJ |
883 | /* approximately equals target * 0.00585 */ |
884 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
885 | |
886 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
887 | |
888 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
889 | ||
d4906093 | 890 | max_n = limit->n.max; |
f77f13e2 | 891 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 892 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 893 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
894 | for (clock.m1 = limit->m1.max; |
895 | clock.m1 >= limit->m1.min; clock.m1--) { | |
896 | for (clock.m2 = limit->m2.max; | |
897 | clock.m2 >= limit->m2.min; clock.m2--) { | |
898 | for (clock.p1 = limit->p1.max; | |
899 | clock.p1 >= limit->p1.min; clock.p1--) { | |
900 | int this_err; | |
901 | ||
dccbea3b | 902 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
903 | if (!intel_PLL_is_valid(dev, limit, |
904 | &clock)) | |
d4906093 | 905 | continue; |
1b894b59 CW |
906 | |
907 | this_err = abs(clock.dot - target); | |
d4906093 ML |
908 | if (this_err < err_most) { |
909 | *best_clock = clock; | |
910 | err_most = this_err; | |
911 | max_n = clock.n; | |
912 | found = true; | |
913 | } | |
914 | } | |
915 | } | |
916 | } | |
917 | } | |
2c07245f ZW |
918 | return found; |
919 | } | |
920 | ||
d5dd62bd ID |
921 | /* |
922 | * Check if the calculated PLL configuration is more optimal compared to the | |
923 | * best configuration and error found so far. Return the calculated error. | |
924 | */ | |
925 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
926 | const intel_clock_t *calculated_clock, | |
927 | const intel_clock_t *best_clock, | |
928 | unsigned int best_error_ppm, | |
929 | unsigned int *error_ppm) | |
930 | { | |
9ca3ba01 ID |
931 | /* |
932 | * For CHV ignore the error and consider only the P value. | |
933 | * Prefer a bigger P value based on HW requirements. | |
934 | */ | |
935 | if (IS_CHERRYVIEW(dev)) { | |
936 | *error_ppm = 0; | |
937 | ||
938 | return calculated_clock->p > best_clock->p; | |
939 | } | |
940 | ||
24be4e46 ID |
941 | if (WARN_ON_ONCE(!target_freq)) |
942 | return false; | |
943 | ||
d5dd62bd ID |
944 | *error_ppm = div_u64(1000000ULL * |
945 | abs(target_freq - calculated_clock->dot), | |
946 | target_freq); | |
947 | /* | |
948 | * Prefer a better P value over a better (smaller) error if the error | |
949 | * is small. Ensure this preference for future configurations too by | |
950 | * setting the error to 0. | |
951 | */ | |
952 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
953 | *error_ppm = 0; | |
954 | ||
955 | return true; | |
956 | } | |
957 | ||
958 | return *error_ppm + 10 < best_error_ppm; | |
959 | } | |
960 | ||
a0c4da24 | 961 | static bool |
a93e255f ACO |
962 | vlv_find_best_dpll(const intel_limit_t *limit, |
963 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
964 | int target, int refclk, intel_clock_t *match_clock, |
965 | intel_clock_t *best_clock) | |
a0c4da24 | 966 | { |
a93e255f | 967 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 968 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 969 | intel_clock_t clock; |
69e4f900 | 970 | unsigned int bestppm = 1000000; |
27e639bf VS |
971 | /* min update 19.2 MHz */ |
972 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 973 | bool found = false; |
a0c4da24 | 974 | |
6b4bf1c4 VS |
975 | target *= 5; /* fast clock */ |
976 | ||
977 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
978 | |
979 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 980 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 981 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 982 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 983 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 984 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 985 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 986 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 987 | unsigned int ppm; |
69e4f900 | 988 | |
6b4bf1c4 VS |
989 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
990 | refclk * clock.m1); | |
991 | ||
dccbea3b | 992 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 993 | |
f01b7962 VS |
994 | if (!intel_PLL_is_valid(dev, limit, |
995 | &clock)) | |
43b0ac53 VS |
996 | continue; |
997 | ||
d5dd62bd ID |
998 | if (!vlv_PLL_is_optimal(dev, target, |
999 | &clock, | |
1000 | best_clock, | |
1001 | bestppm, &ppm)) | |
1002 | continue; | |
6b4bf1c4 | 1003 | |
d5dd62bd ID |
1004 | *best_clock = clock; |
1005 | bestppm = ppm; | |
1006 | found = true; | |
a0c4da24 JB |
1007 | } |
1008 | } | |
1009 | } | |
1010 | } | |
a0c4da24 | 1011 | |
49e497ef | 1012 | return found; |
a0c4da24 | 1013 | } |
a4fc5ed6 | 1014 | |
ef9348c8 | 1015 | static bool |
a93e255f ACO |
1016 | chv_find_best_dpll(const intel_limit_t *limit, |
1017 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1018 | int target, int refclk, intel_clock_t *match_clock, |
1019 | intel_clock_t *best_clock) | |
1020 | { | |
a93e255f | 1021 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1022 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1023 | unsigned int best_error_ppm; |
ef9348c8 CML |
1024 | intel_clock_t clock; |
1025 | uint64_t m2; | |
1026 | int found = false; | |
1027 | ||
1028 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1029 | best_error_ppm = 1000000; |
ef9348c8 CML |
1030 | |
1031 | /* | |
1032 | * Based on hardware doc, the n always set to 1, and m1 always | |
1033 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1034 | * revisit this because n may not 1 anymore. | |
1035 | */ | |
1036 | clock.n = 1, clock.m1 = 2; | |
1037 | target *= 5; /* fast clock */ | |
1038 | ||
1039 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1040 | for (clock.p2 = limit->p2.p2_fast; | |
1041 | clock.p2 >= limit->p2.p2_slow; | |
1042 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1043 | unsigned int error_ppm; |
ef9348c8 CML |
1044 | |
1045 | clock.p = clock.p1 * clock.p2; | |
1046 | ||
1047 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1048 | clock.n) << 22, refclk * clock.m1); | |
1049 | ||
1050 | if (m2 > INT_MAX/clock.m1) | |
1051 | continue; | |
1052 | ||
1053 | clock.m2 = m2; | |
1054 | ||
dccbea3b | 1055 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1056 | |
1057 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1058 | continue; | |
1059 | ||
9ca3ba01 ID |
1060 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1061 | best_error_ppm, &error_ppm)) | |
1062 | continue; | |
1063 | ||
1064 | *best_clock = clock; | |
1065 | best_error_ppm = error_ppm; | |
1066 | found = true; | |
ef9348c8 CML |
1067 | } |
1068 | } | |
1069 | ||
1070 | return found; | |
1071 | } | |
1072 | ||
5ab7b0b7 ID |
1073 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1074 | intel_clock_t *best_clock) | |
1075 | { | |
1076 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1077 | ||
1078 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1079 | target_clock, refclk, NULL, best_clock); | |
1080 | } | |
1081 | ||
20ddf665 VS |
1082 | bool intel_crtc_active(struct drm_crtc *crtc) |
1083 | { | |
1084 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1085 | ||
1086 | /* Be paranoid as we can arrive here with only partial | |
1087 | * state retrieved from the hardware during setup. | |
1088 | * | |
241bfc38 | 1089 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1090 | * as Haswell has gained clock readout/fastboot support. |
1091 | * | |
66e514c1 | 1092 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1093 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1094 | * |
1095 | * FIXME: The intel_crtc->active here should be switched to | |
1096 | * crtc->state->active once we have proper CRTC states wired up | |
1097 | * for atomic. | |
20ddf665 | 1098 | */ |
c3d1f436 | 1099 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1100 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1101 | } |
1102 | ||
a5c961d1 PZ |
1103 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1104 | enum pipe pipe) | |
1105 | { | |
1106 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1107 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1108 | ||
6e3c9717 | 1109 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1110 | } |
1111 | ||
fbf49ea2 VS |
1112 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1113 | { | |
1114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1115 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1116 | u32 line1, line2; |
1117 | u32 line_mask; | |
1118 | ||
1119 | if (IS_GEN2(dev)) | |
1120 | line_mask = DSL_LINEMASK_GEN2; | |
1121 | else | |
1122 | line_mask = DSL_LINEMASK_GEN3; | |
1123 | ||
1124 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1125 | msleep(5); |
fbf49ea2 VS |
1126 | line2 = I915_READ(reg) & line_mask; |
1127 | ||
1128 | return line1 == line2; | |
1129 | } | |
1130 | ||
ab7ad7f6 KP |
1131 | /* |
1132 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1133 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1134 | * |
1135 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1136 | * spinning on the vblank interrupt status bit, since we won't actually | |
1137 | * see an interrupt when the pipe is disabled. | |
1138 | * | |
ab7ad7f6 KP |
1139 | * On Gen4 and above: |
1140 | * wait for the pipe register state bit to turn off | |
1141 | * | |
1142 | * Otherwise: | |
1143 | * wait for the display line value to settle (it usually | |
1144 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1145 | * |
9d0498a2 | 1146 | */ |
575f7ab7 | 1147 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1148 | { |
575f7ab7 | 1149 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1150 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1151 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1152 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1153 | |
1154 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1155 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1156 | |
1157 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1158 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1159 | 100)) | |
284637d9 | 1160 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1161 | } else { |
ab7ad7f6 | 1162 | /* Wait for the display line to settle */ |
fbf49ea2 | 1163 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1164 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1165 | } |
79e53945 JB |
1166 | } |
1167 | ||
b24e7179 | 1168 | /* Only for pre-ILK configs */ |
55607e8a DV |
1169 | void assert_pll(struct drm_i915_private *dev_priv, |
1170 | enum pipe pipe, bool state) | |
b24e7179 | 1171 | { |
b24e7179 JB |
1172 | u32 val; |
1173 | bool cur_state; | |
1174 | ||
649636ef | 1175 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1176 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1177 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1178 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1179 | onoff(state), onoff(cur_state)); |
b24e7179 | 1180 | } |
b24e7179 | 1181 | |
23538ef1 JN |
1182 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1183 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1184 | { | |
1185 | u32 val; | |
1186 | bool cur_state; | |
1187 | ||
a580516d | 1188 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1189 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1190 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1191 | |
1192 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1193 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1194 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1195 | onoff(state), onoff(cur_state)); |
23538ef1 JN |
1196 | } |
1197 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1198 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1199 | ||
55607e8a | 1200 | struct intel_shared_dpll * |
e2b78267 DV |
1201 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1202 | { | |
1203 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1204 | ||
6e3c9717 | 1205 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1206 | return NULL; |
1207 | ||
6e3c9717 | 1208 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1209 | } |
1210 | ||
040484af | 1211 | /* For ILK+ */ |
55607e8a DV |
1212 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1213 | struct intel_shared_dpll *pll, | |
1214 | bool state) | |
040484af | 1215 | { |
040484af | 1216 | bool cur_state; |
5358901f | 1217 | struct intel_dpll_hw_state hw_state; |
040484af | 1218 | |
87ad3212 | 1219 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) |
ee7b9f93 | 1220 | return; |
ee7b9f93 | 1221 | |
5358901f | 1222 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1223 | I915_STATE_WARN(cur_state != state, |
5358901f | 1224 | "%s assertion failure (expected %s, current %s)\n", |
87ad3212 | 1225 | pll->name, onoff(state), onoff(cur_state)); |
040484af | 1226 | } |
040484af JB |
1227 | |
1228 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1229 | enum pipe pipe, bool state) | |
1230 | { | |
040484af | 1231 | bool cur_state; |
ad80a810 PZ |
1232 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1233 | pipe); | |
040484af | 1234 | |
affa9354 PZ |
1235 | if (HAS_DDI(dev_priv->dev)) { |
1236 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1237 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1238 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1239 | } else { |
649636ef | 1240 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1241 | cur_state = !!(val & FDI_TX_ENABLE); |
1242 | } | |
e2c719b7 | 1243 | I915_STATE_WARN(cur_state != state, |
040484af | 1244 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1245 | onoff(state), onoff(cur_state)); |
040484af JB |
1246 | } |
1247 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1248 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1249 | ||
1250 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1251 | enum pipe pipe, bool state) | |
1252 | { | |
040484af JB |
1253 | u32 val; |
1254 | bool cur_state; | |
1255 | ||
649636ef | 1256 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1257 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1258 | I915_STATE_WARN(cur_state != state, |
040484af | 1259 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1260 | onoff(state), onoff(cur_state)); |
040484af JB |
1261 | } |
1262 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1263 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1264 | ||
1265 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1266 | enum pipe pipe) | |
1267 | { | |
040484af JB |
1268 | u32 val; |
1269 | ||
1270 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1271 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1272 | return; |
1273 | ||
bf507ef7 | 1274 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1275 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1276 | return; |
1277 | ||
649636ef | 1278 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1279 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1280 | } |
1281 | ||
55607e8a DV |
1282 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1283 | enum pipe pipe, bool state) | |
040484af | 1284 | { |
040484af | 1285 | u32 val; |
55607e8a | 1286 | bool cur_state; |
040484af | 1287 | |
649636ef | 1288 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1289 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1290 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1291 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1292 | onoff(state), onoff(cur_state)); |
040484af JB |
1293 | } |
1294 | ||
b680c37a DV |
1295 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1296 | enum pipe pipe) | |
ea0760cf | 1297 | { |
bedd4dba | 1298 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1299 | i915_reg_t pp_reg; |
ea0760cf JB |
1300 | u32 val; |
1301 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1302 | bool locked = true; |
ea0760cf | 1303 | |
bedd4dba JN |
1304 | if (WARN_ON(HAS_DDI(dev))) |
1305 | return; | |
1306 | ||
1307 | if (HAS_PCH_SPLIT(dev)) { | |
1308 | u32 port_sel; | |
1309 | ||
ea0760cf | 1310 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1311 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1312 | ||
1313 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1314 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1315 | panel_pipe = PIPE_B; | |
1316 | /* XXX: else fix for eDP */ | |
666a4537 | 1317 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1318 | /* presumably write lock depends on pipe, not port select */ |
1319 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1320 | panel_pipe = pipe; | |
ea0760cf JB |
1321 | } else { |
1322 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1323 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1324 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1325 | } |
1326 | ||
1327 | val = I915_READ(pp_reg); | |
1328 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1329 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1330 | locked = false; |
1331 | ||
e2c719b7 | 1332 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1333 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1334 | pipe_name(pipe)); |
ea0760cf JB |
1335 | } |
1336 | ||
93ce0ba6 JN |
1337 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1338 | enum pipe pipe, bool state) | |
1339 | { | |
1340 | struct drm_device *dev = dev_priv->dev; | |
1341 | bool cur_state; | |
1342 | ||
d9d82081 | 1343 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1344 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1345 | else |
5efb3e28 | 1346 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1347 | |
e2c719b7 | 1348 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1349 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1350 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1351 | } |
1352 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1353 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1354 | ||
b840d907 JB |
1355 | void assert_pipe(struct drm_i915_private *dev_priv, |
1356 | enum pipe pipe, bool state) | |
b24e7179 | 1357 | { |
63d7bbe9 | 1358 | bool cur_state; |
702e7a56 PZ |
1359 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1360 | pipe); | |
4feed0eb | 1361 | enum intel_display_power_domain power_domain; |
b24e7179 | 1362 | |
b6b5d049 VS |
1363 | /* if we need the pipe quirk it must be always on */ |
1364 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1365 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1366 | state = true; |
1367 | ||
4feed0eb ID |
1368 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1369 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1370 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1371 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1372 | |
1373 | intel_display_power_put(dev_priv, power_domain); | |
1374 | } else { | |
1375 | cur_state = false; | |
69310161 PZ |
1376 | } |
1377 | ||
e2c719b7 | 1378 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1379 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1380 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1381 | } |
1382 | ||
931872fc CW |
1383 | static void assert_plane(struct drm_i915_private *dev_priv, |
1384 | enum plane plane, bool state) | |
b24e7179 | 1385 | { |
b24e7179 | 1386 | u32 val; |
931872fc | 1387 | bool cur_state; |
b24e7179 | 1388 | |
649636ef | 1389 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1390 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1391 | I915_STATE_WARN(cur_state != state, |
931872fc | 1392 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1393 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1394 | } |
1395 | ||
931872fc CW |
1396 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1397 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1398 | ||
b24e7179 JB |
1399 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1400 | enum pipe pipe) | |
1401 | { | |
653e1026 | 1402 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1403 | int i; |
b24e7179 | 1404 | |
653e1026 VS |
1405 | /* Primary planes are fixed to pipes on gen4+ */ |
1406 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1407 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1408 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1409 | "plane %c assertion failure, should be disabled but not\n", |
1410 | plane_name(pipe)); | |
19ec1358 | 1411 | return; |
28c05794 | 1412 | } |
19ec1358 | 1413 | |
b24e7179 | 1414 | /* Need to check both planes against the pipe */ |
055e393f | 1415 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1416 | u32 val = I915_READ(DSPCNTR(i)); |
1417 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1418 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1419 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1420 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1421 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1422 | } |
1423 | } | |
1424 | ||
19332d7a JB |
1425 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1426 | enum pipe pipe) | |
1427 | { | |
20674eef | 1428 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1429 | int sprite; |
19332d7a | 1430 | |
7feb8b88 | 1431 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1432 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1433 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1434 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1435 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1436 | sprite, pipe_name(pipe)); | |
1437 | } | |
666a4537 | 1438 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1439 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1440 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1441 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1442 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1443 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1444 | } |
1445 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1446 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1447 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1448 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1449 | plane_name(pipe), pipe_name(pipe)); |
1450 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1451 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1452 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1453 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1454 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1455 | } |
1456 | } | |
1457 | ||
08c71e5e VS |
1458 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1459 | { | |
e2c719b7 | 1460 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1461 | drm_crtc_vblank_put(crtc); |
1462 | } | |
1463 | ||
89eff4be | 1464 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1465 | { |
1466 | u32 val; | |
1467 | bool enabled; | |
1468 | ||
e2c719b7 | 1469 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1470 | |
92f2584a JB |
1471 | val = I915_READ(PCH_DREF_CONTROL); |
1472 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1473 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1474 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1475 | } |
1476 | ||
ab9412ba DV |
1477 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1478 | enum pipe pipe) | |
92f2584a | 1479 | { |
92f2584a JB |
1480 | u32 val; |
1481 | bool enabled; | |
1482 | ||
649636ef | 1483 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1484 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1485 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1486 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1487 | pipe_name(pipe)); | |
92f2584a JB |
1488 | } |
1489 | ||
4e634389 KP |
1490 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1491 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1492 | { |
1493 | if ((val & DP_PORT_EN) == 0) | |
1494 | return false; | |
1495 | ||
1496 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1497 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1498 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1499 | return false; | |
44f37d1f CML |
1500 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1501 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1502 | return false; | |
f0575e92 KP |
1503 | } else { |
1504 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1505 | return false; | |
1506 | } | |
1507 | return true; | |
1508 | } | |
1509 | ||
1519b995 KP |
1510 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1511 | enum pipe pipe, u32 val) | |
1512 | { | |
dc0fa718 | 1513 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1514 | return false; |
1515 | ||
1516 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1517 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1518 | return false; |
44f37d1f CML |
1519 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1520 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1521 | return false; | |
1519b995 | 1522 | } else { |
dc0fa718 | 1523 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1524 | return false; |
1525 | } | |
1526 | return true; | |
1527 | } | |
1528 | ||
1529 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1530 | enum pipe pipe, u32 val) | |
1531 | { | |
1532 | if ((val & LVDS_PORT_EN) == 0) | |
1533 | return false; | |
1534 | ||
1535 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1536 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1537 | return false; | |
1538 | } else { | |
1539 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1540 | return false; | |
1541 | } | |
1542 | return true; | |
1543 | } | |
1544 | ||
1545 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1546 | enum pipe pipe, u32 val) | |
1547 | { | |
1548 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1549 | return false; | |
1550 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1551 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1552 | return false; | |
1553 | } else { | |
1554 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1555 | return false; | |
1556 | } | |
1557 | return true; | |
1558 | } | |
1559 | ||
291906f1 | 1560 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1561 | enum pipe pipe, i915_reg_t reg, |
1562 | u32 port_sel) | |
291906f1 | 1563 | { |
47a05eca | 1564 | u32 val = I915_READ(reg); |
e2c719b7 | 1565 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1566 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1567 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1568 | |
e2c719b7 | 1569 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1570 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1571 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1572 | } |
1573 | ||
1574 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1575 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1576 | { |
47a05eca | 1577 | u32 val = I915_READ(reg); |
e2c719b7 | 1578 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1579 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1580 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1581 | |
e2c719b7 | 1582 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1583 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1584 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1585 | } |
1586 | ||
1587 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1588 | enum pipe pipe) | |
1589 | { | |
291906f1 | 1590 | u32 val; |
291906f1 | 1591 | |
f0575e92 KP |
1592 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1593 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1594 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1595 | |
649636ef | 1596 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1597 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1598 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1599 | pipe_name(pipe)); |
291906f1 | 1600 | |
649636ef | 1601 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1602 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1603 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1604 | pipe_name(pipe)); |
291906f1 | 1605 | |
e2debe91 PZ |
1606 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1607 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1608 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1609 | } |
1610 | ||
d288f65f | 1611 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1612 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1613 | { |
426115cf DV |
1614 | struct drm_device *dev = crtc->base.dev; |
1615 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1616 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1617 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1618 | |
426115cf | 1619 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1620 | |
87442f73 | 1621 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1622 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1623 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1624 | |
426115cf DV |
1625 | I915_WRITE(reg, dpll); |
1626 | POSTING_READ(reg); | |
1627 | udelay(150); | |
1628 | ||
1629 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1630 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1631 | ||
d288f65f | 1632 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1633 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1634 | |
1635 | /* We do this three times for luck */ | |
426115cf | 1636 | I915_WRITE(reg, dpll); |
87442f73 DV |
1637 | POSTING_READ(reg); |
1638 | udelay(150); /* wait for warmup */ | |
426115cf | 1639 | I915_WRITE(reg, dpll); |
87442f73 DV |
1640 | POSTING_READ(reg); |
1641 | udelay(150); /* wait for warmup */ | |
426115cf | 1642 | I915_WRITE(reg, dpll); |
87442f73 DV |
1643 | POSTING_READ(reg); |
1644 | udelay(150); /* wait for warmup */ | |
1645 | } | |
1646 | ||
d288f65f | 1647 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1648 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1649 | { |
1650 | struct drm_device *dev = crtc->base.dev; | |
1651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1652 | int pipe = crtc->pipe; | |
1653 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1654 | u32 tmp; |
1655 | ||
1656 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1657 | ||
a580516d | 1658 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1659 | |
1660 | /* Enable back the 10bit clock to display controller */ | |
1661 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1662 | tmp |= DPIO_DCLKP_EN; | |
1663 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1664 | ||
54433e91 VS |
1665 | mutex_unlock(&dev_priv->sb_lock); |
1666 | ||
9d556c99 CML |
1667 | /* |
1668 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1669 | */ | |
1670 | udelay(1); | |
1671 | ||
1672 | /* Enable PLL */ | |
d288f65f | 1673 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1674 | |
1675 | /* Check PLL is locked */ | |
a11b0703 | 1676 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1677 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1678 | ||
a11b0703 | 1679 | /* not sure when this should be written */ |
d288f65f | 1680 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1681 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1682 | } |
1683 | ||
1c4e0274 VS |
1684 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1685 | { | |
1686 | struct intel_crtc *crtc; | |
1687 | int count = 0; | |
1688 | ||
1689 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1690 | count += crtc->base.state->active && |
409ee761 | 1691 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1692 | |
1693 | return count; | |
1694 | } | |
1695 | ||
66e3d5c0 | 1696 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1697 | { |
66e3d5c0 DV |
1698 | struct drm_device *dev = crtc->base.dev; |
1699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1700 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1701 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1702 | |
66e3d5c0 | 1703 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1704 | |
63d7bbe9 | 1705 | /* No really, not for ILK+ */ |
3d13ef2e | 1706 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1707 | |
1708 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1709 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1710 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1711 | |
1c4e0274 VS |
1712 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1713 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1714 | /* | |
1715 | * It appears to be important that we don't enable this | |
1716 | * for the current pipe before otherwise configuring the | |
1717 | * PLL. No idea how this should be handled if multiple | |
1718 | * DVO outputs are enabled simultaneosly. | |
1719 | */ | |
1720 | dpll |= DPLL_DVO_2X_MODE; | |
1721 | I915_WRITE(DPLL(!crtc->pipe), | |
1722 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1723 | } | |
66e3d5c0 | 1724 | |
c2b63374 VS |
1725 | /* |
1726 | * Apparently we need to have VGA mode enabled prior to changing | |
1727 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1728 | * dividers, even though the register value does change. | |
1729 | */ | |
1730 | I915_WRITE(reg, 0); | |
1731 | ||
8e7a65aa VS |
1732 | I915_WRITE(reg, dpll); |
1733 | ||
66e3d5c0 DV |
1734 | /* Wait for the clocks to stabilize. */ |
1735 | POSTING_READ(reg); | |
1736 | udelay(150); | |
1737 | ||
1738 | if (INTEL_INFO(dev)->gen >= 4) { | |
1739 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1740 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1741 | } else { |
1742 | /* The pixel multiplier can only be updated once the | |
1743 | * DPLL is enabled and the clocks are stable. | |
1744 | * | |
1745 | * So write it again. | |
1746 | */ | |
1747 | I915_WRITE(reg, dpll); | |
1748 | } | |
63d7bbe9 JB |
1749 | |
1750 | /* We do this three times for luck */ | |
66e3d5c0 | 1751 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1752 | POSTING_READ(reg); |
1753 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1754 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1755 | POSTING_READ(reg); |
1756 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1757 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1758 | POSTING_READ(reg); |
1759 | udelay(150); /* wait for warmup */ | |
1760 | } | |
1761 | ||
1762 | /** | |
50b44a44 | 1763 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1764 | * @dev_priv: i915 private structure |
1765 | * @pipe: pipe PLL to disable | |
1766 | * | |
1767 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1768 | * | |
1769 | * Note! This is for pre-ILK only. | |
1770 | */ | |
1c4e0274 | 1771 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1772 | { |
1c4e0274 VS |
1773 | struct drm_device *dev = crtc->base.dev; |
1774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1775 | enum pipe pipe = crtc->pipe; | |
1776 | ||
1777 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1778 | if (IS_I830(dev) && | |
409ee761 | 1779 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1780 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1781 | I915_WRITE(DPLL(PIPE_B), |
1782 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1783 | I915_WRITE(DPLL(PIPE_A), | |
1784 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1785 | } | |
1786 | ||
b6b5d049 VS |
1787 | /* Don't disable pipe or pipe PLLs if needed */ |
1788 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1789 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1790 | return; |
1791 | ||
1792 | /* Make sure the pipe isn't still relying on us */ | |
1793 | assert_pipe_disabled(dev_priv, pipe); | |
1794 | ||
b8afb911 | 1795 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1796 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1797 | } |
1798 | ||
f6071166 JB |
1799 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1800 | { | |
b8afb911 | 1801 | u32 val; |
f6071166 JB |
1802 | |
1803 | /* Make sure the pipe isn't still relying on us */ | |
1804 | assert_pipe_disabled(dev_priv, pipe); | |
1805 | ||
e5cbfbfb ID |
1806 | /* |
1807 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1808 | * The latter is needed for VGA hotplug / manual detection. | |
1809 | */ | |
b8afb911 | 1810 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1811 | if (pipe == PIPE_B) |
60bfe44f | 1812 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1813 | I915_WRITE(DPLL(pipe), val); |
1814 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1815 | |
1816 | } | |
1817 | ||
1818 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1819 | { | |
d752048d | 1820 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1821 | u32 val; |
1822 | ||
a11b0703 VS |
1823 | /* Make sure the pipe isn't still relying on us */ |
1824 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1825 | |
a11b0703 | 1826 | /* Set PLL en = 0 */ |
60bfe44f VS |
1827 | val = DPLL_SSC_REF_CLK_CHV | |
1828 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1829 | if (pipe != PIPE_A) |
1830 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1831 | I915_WRITE(DPLL(pipe), val); | |
1832 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1833 | |
a580516d | 1834 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1835 | |
1836 | /* Disable 10bit clock to display controller */ | |
1837 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1838 | val &= ~DPIO_DCLKP_EN; | |
1839 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1840 | ||
a580516d | 1841 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1842 | } |
1843 | ||
e4607fcf | 1844 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1845 | struct intel_digital_port *dport, |
1846 | unsigned int expected_mask) | |
89b667f8 JB |
1847 | { |
1848 | u32 port_mask; | |
f0f59a00 | 1849 | i915_reg_t dpll_reg; |
89b667f8 | 1850 | |
e4607fcf CML |
1851 | switch (dport->port) { |
1852 | case PORT_B: | |
89b667f8 | 1853 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1854 | dpll_reg = DPLL(0); |
e4607fcf CML |
1855 | break; |
1856 | case PORT_C: | |
89b667f8 | 1857 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1858 | dpll_reg = DPLL(0); |
9b6de0a1 | 1859 | expected_mask <<= 4; |
00fc31b7 CML |
1860 | break; |
1861 | case PORT_D: | |
1862 | port_mask = DPLL_PORTD_READY_MASK; | |
1863 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1864 | break; |
1865 | default: | |
1866 | BUG(); | |
1867 | } | |
89b667f8 | 1868 | |
9b6de0a1 VS |
1869 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1870 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1871 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1872 | } |
1873 | ||
b14b1055 DV |
1874 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1875 | { | |
1876 | struct drm_device *dev = crtc->base.dev; | |
1877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1878 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1879 | ||
be19f0ff CW |
1880 | if (WARN_ON(pll == NULL)) |
1881 | return; | |
1882 | ||
3e369b76 | 1883 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1884 | if (pll->active == 0) { |
1885 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1886 | WARN_ON(pll->on); | |
1887 | assert_shared_dpll_disabled(dev_priv, pll); | |
1888 | ||
1889 | pll->mode_set(dev_priv, pll); | |
1890 | } | |
1891 | } | |
1892 | ||
92f2584a | 1893 | /** |
85b3894f | 1894 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1895 | * @dev_priv: i915 private structure |
1896 | * @pipe: pipe PLL to enable | |
1897 | * | |
1898 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1899 | * drives the transcoder clock. | |
1900 | */ | |
85b3894f | 1901 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1902 | { |
3d13ef2e DL |
1903 | struct drm_device *dev = crtc->base.dev; |
1904 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1905 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1906 | |
87a875bb | 1907 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1908 | return; |
1909 | ||
3e369b76 | 1910 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1911 | return; |
ee7b9f93 | 1912 | |
74dd6928 | 1913 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1914 | pll->name, pll->active, pll->on, |
e2b78267 | 1915 | crtc->base.base.id); |
92f2584a | 1916 | |
cdbd2316 DV |
1917 | if (pll->active++) { |
1918 | WARN_ON(!pll->on); | |
e9d6944e | 1919 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1920 | return; |
1921 | } | |
f4a091c7 | 1922 | WARN_ON(pll->on); |
ee7b9f93 | 1923 | |
bd2bb1b9 PZ |
1924 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1925 | ||
46edb027 | 1926 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1927 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1928 | pll->on = true; |
92f2584a JB |
1929 | } |
1930 | ||
f6daaec2 | 1931 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1932 | { |
3d13ef2e DL |
1933 | struct drm_device *dev = crtc->base.dev; |
1934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1935 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1936 | |
92f2584a | 1937 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1938 | if (INTEL_INFO(dev)->gen < 5) |
1939 | return; | |
1940 | ||
eddfcbcd ML |
1941 | if (pll == NULL) |
1942 | return; | |
92f2584a | 1943 | |
eddfcbcd | 1944 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1945 | return; |
7a419866 | 1946 | |
46edb027 DV |
1947 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1948 | pll->name, pll->active, pll->on, | |
e2b78267 | 1949 | crtc->base.base.id); |
7a419866 | 1950 | |
48da64a8 | 1951 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1952 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1953 | return; |
1954 | } | |
1955 | ||
e9d6944e | 1956 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1957 | WARN_ON(!pll->on); |
cdbd2316 | 1958 | if (--pll->active) |
7a419866 | 1959 | return; |
ee7b9f93 | 1960 | |
46edb027 | 1961 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1962 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1963 | pll->on = false; |
bd2bb1b9 PZ |
1964 | |
1965 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1966 | } |
1967 | ||
b8a4f404 PZ |
1968 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1969 | enum pipe pipe) | |
040484af | 1970 | { |
23670b32 | 1971 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1972 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1974 | i915_reg_t reg; |
1975 | uint32_t val, pipeconf_val; | |
040484af JB |
1976 | |
1977 | /* PCH only available on ILK+ */ | |
55522f37 | 1978 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1979 | |
1980 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1981 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1982 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1983 | |
1984 | /* FDI must be feeding us bits for PCH ports */ | |
1985 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1986 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1987 | ||
23670b32 DV |
1988 | if (HAS_PCH_CPT(dev)) { |
1989 | /* Workaround: Set the timing override bit before enabling the | |
1990 | * pch transcoder. */ | |
1991 | reg = TRANS_CHICKEN2(pipe); | |
1992 | val = I915_READ(reg); | |
1993 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1994 | I915_WRITE(reg, val); | |
59c859d6 | 1995 | } |
23670b32 | 1996 | |
ab9412ba | 1997 | reg = PCH_TRANSCONF(pipe); |
040484af | 1998 | val = I915_READ(reg); |
5f7f726d | 1999 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
2000 | |
2001 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
2002 | /* | |
c5de7c6f VS |
2003 | * Make the BPC in transcoder be consistent with |
2004 | * that in pipeconf reg. For HDMI we must use 8bpc | |
2005 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 2006 | */ |
dfd07d72 | 2007 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
2008 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
2009 | val |= PIPECONF_8BPC; | |
2010 | else | |
2011 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2012 | } |
5f7f726d PZ |
2013 | |
2014 | val &= ~TRANS_INTERLACE_MASK; | |
2015 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2016 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2017 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2018 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2019 | else | |
2020 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2021 | else |
2022 | val |= TRANS_PROGRESSIVE; | |
2023 | ||
040484af JB |
2024 | I915_WRITE(reg, val | TRANS_ENABLE); |
2025 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2026 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2027 | } |
2028 | ||
8fb033d7 | 2029 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2030 | enum transcoder cpu_transcoder) |
040484af | 2031 | { |
8fb033d7 | 2032 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2033 | |
2034 | /* PCH only available on ILK+ */ | |
55522f37 | 2035 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2036 | |
8fb033d7 | 2037 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2038 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2039 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2040 | |
223a6fdf | 2041 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2042 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2043 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2044 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2045 | |
25f3ef11 | 2046 | val = TRANS_ENABLE; |
937bb610 | 2047 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2048 | |
9a76b1c6 PZ |
2049 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2050 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2051 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2052 | else |
2053 | val |= TRANS_PROGRESSIVE; | |
2054 | ||
ab9412ba DV |
2055 | I915_WRITE(LPT_TRANSCONF, val); |
2056 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2057 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2058 | } |
2059 | ||
b8a4f404 PZ |
2060 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2061 | enum pipe pipe) | |
040484af | 2062 | { |
23670b32 | 2063 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2064 | i915_reg_t reg; |
2065 | uint32_t val; | |
040484af JB |
2066 | |
2067 | /* FDI relies on the transcoder */ | |
2068 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2069 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2070 | ||
291906f1 JB |
2071 | /* Ports must be off as well */ |
2072 | assert_pch_ports_disabled(dev_priv, pipe); | |
2073 | ||
ab9412ba | 2074 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2075 | val = I915_READ(reg); |
2076 | val &= ~TRANS_ENABLE; | |
2077 | I915_WRITE(reg, val); | |
2078 | /* wait for PCH transcoder off, transcoder state */ | |
2079 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2080 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2081 | |
c465613b | 2082 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2083 | /* Workaround: Clear the timing override chicken bit again. */ |
2084 | reg = TRANS_CHICKEN2(pipe); | |
2085 | val = I915_READ(reg); | |
2086 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2087 | I915_WRITE(reg, val); | |
2088 | } | |
040484af JB |
2089 | } |
2090 | ||
ab4d966c | 2091 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2092 | { |
8fb033d7 PZ |
2093 | u32 val; |
2094 | ||
ab9412ba | 2095 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2096 | val &= ~TRANS_ENABLE; |
ab9412ba | 2097 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2098 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2099 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2100 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2101 | |
2102 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2103 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2104 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2105 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2106 | } |
2107 | ||
b24e7179 | 2108 | /** |
309cfea8 | 2109 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2110 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2111 | * |
0372264a | 2112 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2113 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2114 | */ |
e1fdc473 | 2115 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2116 | { |
0372264a PZ |
2117 | struct drm_device *dev = crtc->base.dev; |
2118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2119 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2120 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2121 | enum pipe pch_transcoder; |
f0f59a00 | 2122 | i915_reg_t reg; |
b24e7179 JB |
2123 | u32 val; |
2124 | ||
9e2ee2dd VS |
2125 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2126 | ||
58c6eaa2 | 2127 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2128 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2129 | assert_sprites_disabled(dev_priv, pipe); |
2130 | ||
681e5811 | 2131 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2132 | pch_transcoder = TRANSCODER_A; |
2133 | else | |
2134 | pch_transcoder = pipe; | |
2135 | ||
b24e7179 JB |
2136 | /* |
2137 | * A pipe without a PLL won't actually be able to drive bits from | |
2138 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2139 | * need the check. | |
2140 | */ | |
50360403 | 2141 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2142 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2143 | assert_dsi_pll_enabled(dev_priv); |
2144 | else | |
2145 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2146 | else { |
6e3c9717 | 2147 | if (crtc->config->has_pch_encoder) { |
040484af | 2148 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2149 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2150 | assert_fdi_tx_pll_enabled(dev_priv, |
2151 | (enum pipe) cpu_transcoder); | |
040484af JB |
2152 | } |
2153 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2154 | } | |
b24e7179 | 2155 | |
702e7a56 | 2156 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2157 | val = I915_READ(reg); |
7ad25d48 | 2158 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2159 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2160 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2161 | return; |
7ad25d48 | 2162 | } |
00d70b15 CW |
2163 | |
2164 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2165 | POSTING_READ(reg); |
b7792d8b VS |
2166 | |
2167 | /* | |
2168 | * Until the pipe starts DSL will read as 0, which would cause | |
2169 | * an apparent vblank timestamp jump, which messes up also the | |
2170 | * frame count when it's derived from the timestamps. So let's | |
2171 | * wait for the pipe to start properly before we call | |
2172 | * drm_crtc_vblank_on() | |
2173 | */ | |
2174 | if (dev->max_vblank_count == 0 && | |
2175 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2176 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2177 | } |
2178 | ||
2179 | /** | |
309cfea8 | 2180 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2181 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2182 | * |
575f7ab7 VS |
2183 | * Disable the pipe of @crtc, making sure that various hardware |
2184 | * specific requirements are met, if applicable, e.g. plane | |
2185 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2186 | * |
2187 | * Will wait until the pipe has shut down before returning. | |
2188 | */ | |
575f7ab7 | 2189 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2190 | { |
575f7ab7 | 2191 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2192 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2193 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2194 | i915_reg_t reg; |
b24e7179 JB |
2195 | u32 val; |
2196 | ||
9e2ee2dd VS |
2197 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2198 | ||
b24e7179 JB |
2199 | /* |
2200 | * Make sure planes won't keep trying to pump pixels to us, | |
2201 | * or we might hang the display. | |
2202 | */ | |
2203 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2204 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2205 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2206 | |
702e7a56 | 2207 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2208 | val = I915_READ(reg); |
00d70b15 CW |
2209 | if ((val & PIPECONF_ENABLE) == 0) |
2210 | return; | |
2211 | ||
67adc644 VS |
2212 | /* |
2213 | * Double wide has implications for planes | |
2214 | * so best keep it disabled when not needed. | |
2215 | */ | |
6e3c9717 | 2216 | if (crtc->config->double_wide) |
67adc644 VS |
2217 | val &= ~PIPECONF_DOUBLE_WIDE; |
2218 | ||
2219 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2220 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2221 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2222 | val &= ~PIPECONF_ENABLE; |
2223 | ||
2224 | I915_WRITE(reg, val); | |
2225 | if ((val & PIPECONF_ENABLE) == 0) | |
2226 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2227 | } |
2228 | ||
693db184 CW |
2229 | static bool need_vtd_wa(struct drm_device *dev) |
2230 | { | |
2231 | #ifdef CONFIG_INTEL_IOMMU | |
2232 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2233 | return true; | |
2234 | #endif | |
2235 | return false; | |
2236 | } | |
2237 | ||
832be82f VS |
2238 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2239 | { | |
2240 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2241 | } | |
2242 | ||
27ba3910 VS |
2243 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2244 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2245 | { |
2246 | switch (fb_modifier) { | |
2247 | case DRM_FORMAT_MOD_NONE: | |
2248 | return cpp; | |
2249 | case I915_FORMAT_MOD_X_TILED: | |
2250 | if (IS_GEN2(dev_priv)) | |
2251 | return 128; | |
2252 | else | |
2253 | return 512; | |
2254 | case I915_FORMAT_MOD_Y_TILED: | |
2255 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2256 | return 128; | |
2257 | else | |
2258 | return 512; | |
2259 | case I915_FORMAT_MOD_Yf_TILED: | |
2260 | switch (cpp) { | |
2261 | case 1: | |
2262 | return 64; | |
2263 | case 2: | |
2264 | case 4: | |
2265 | return 128; | |
2266 | case 8: | |
2267 | case 16: | |
2268 | return 256; | |
2269 | default: | |
2270 | MISSING_CASE(cpp); | |
2271 | return cpp; | |
2272 | } | |
2273 | break; | |
2274 | default: | |
2275 | MISSING_CASE(fb_modifier); | |
2276 | return cpp; | |
2277 | } | |
2278 | } | |
2279 | ||
832be82f VS |
2280 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2281 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2282 | { |
832be82f VS |
2283 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2284 | return 1; | |
2285 | else | |
2286 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2287 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2288 | } |
2289 | ||
8d0deca8 VS |
2290 | /* Return the tile dimensions in pixel units */ |
2291 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2292 | unsigned int *tile_width, | |
2293 | unsigned int *tile_height, | |
2294 | uint64_t fb_modifier, | |
2295 | unsigned int cpp) | |
2296 | { | |
2297 | unsigned int tile_width_bytes = | |
2298 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2299 | ||
2300 | *tile_width = tile_width_bytes / cpp; | |
2301 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2302 | } | |
2303 | ||
6761dd31 TU |
2304 | unsigned int |
2305 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2306 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2307 | { |
832be82f VS |
2308 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2309 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2310 | ||
2311 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2312 | } |
2313 | ||
1663b9d6 VS |
2314 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2315 | { | |
2316 | unsigned int size = 0; | |
2317 | int i; | |
2318 | ||
2319 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2320 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2321 | ||
2322 | return size; | |
2323 | } | |
2324 | ||
75c82a53 | 2325 | static void |
3465c580 VS |
2326 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2327 | const struct drm_framebuffer *fb, | |
2328 | unsigned int rotation) | |
f64b98cd | 2329 | { |
2d7a215f VS |
2330 | if (intel_rotation_90_or_270(rotation)) { |
2331 | *view = i915_ggtt_view_rotated; | |
2332 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2333 | } else { | |
2334 | *view = i915_ggtt_view_normal; | |
2335 | } | |
2336 | } | |
50470bb0 | 2337 | |
2d7a215f VS |
2338 | static void |
2339 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2340 | struct drm_framebuffer *fb) | |
2341 | { | |
2342 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2343 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2344 | |
d9b3288e VS |
2345 | tile_size = intel_tile_size(dev_priv); |
2346 | ||
2347 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2348 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2349 | fb->modifier[0], cpp); | |
d9b3288e | 2350 | |
1663b9d6 VS |
2351 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2352 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2353 | |
89e3e142 | 2354 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2355 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2356 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2357 | fb->modifier[1], cpp); | |
d9b3288e | 2358 | |
2d7a215f | 2359 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2360 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2361 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2362 | } |
f64b98cd TU |
2363 | } |
2364 | ||
603525d7 | 2365 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2366 | { |
2367 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2368 | return 256 * 1024; | |
985b8bb4 | 2369 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2370 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2371 | return 128 * 1024; |
2372 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2373 | return 4 * 1024; | |
2374 | else | |
44c5905e | 2375 | return 0; |
4e9a86b6 VS |
2376 | } |
2377 | ||
603525d7 VS |
2378 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2379 | uint64_t fb_modifier) | |
2380 | { | |
2381 | switch (fb_modifier) { | |
2382 | case DRM_FORMAT_MOD_NONE: | |
2383 | return intel_linear_alignment(dev_priv); | |
2384 | case I915_FORMAT_MOD_X_TILED: | |
2385 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2386 | return 256 * 1024; | |
2387 | return 0; | |
2388 | case I915_FORMAT_MOD_Y_TILED: | |
2389 | case I915_FORMAT_MOD_Yf_TILED: | |
2390 | return 1 * 1024 * 1024; | |
2391 | default: | |
2392 | MISSING_CASE(fb_modifier); | |
2393 | return 0; | |
2394 | } | |
2395 | } | |
2396 | ||
127bd2ac | 2397 | int |
3465c580 VS |
2398 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2399 | unsigned int rotation) | |
6b95a207 | 2400 | { |
850c4cdc | 2401 | struct drm_device *dev = fb->dev; |
ce453d81 | 2402 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2403 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2404 | struct i915_ggtt_view view; |
6b95a207 KH |
2405 | u32 alignment; |
2406 | int ret; | |
2407 | ||
ebcdd39e MR |
2408 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2409 | ||
603525d7 | 2410 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2411 | |
3465c580 | 2412 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2413 | |
693db184 CW |
2414 | /* Note that the w/a also requires 64 PTE of padding following the |
2415 | * bo. We currently fill all unused PTE with the shadow page and so | |
2416 | * we should always have valid PTE following the scanout preventing | |
2417 | * the VT-d warning. | |
2418 | */ | |
2419 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2420 | alignment = 256 * 1024; | |
2421 | ||
d6dd6843 PZ |
2422 | /* |
2423 | * Global gtt pte registers are special registers which actually forward | |
2424 | * writes to a chunk of system memory. Which means that there is no risk | |
2425 | * that the register values disappear as soon as we call | |
2426 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2427 | * pin/unpin/fence and not more. | |
2428 | */ | |
2429 | intel_runtime_pm_get(dev_priv); | |
2430 | ||
7580d774 ML |
2431 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2432 | &view); | |
48b956c5 | 2433 | if (ret) |
b26a6b35 | 2434 | goto err_pm; |
6b95a207 KH |
2435 | |
2436 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2437 | * fence, whereas 965+ only requires a fence if using | |
2438 | * framebuffer compression. For simplicity, we always install | |
2439 | * a fence as the cost is not that onerous. | |
2440 | */ | |
9807216f VK |
2441 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2442 | ret = i915_gem_object_get_fence(obj); | |
2443 | if (ret == -EDEADLK) { | |
2444 | /* | |
2445 | * -EDEADLK means there are no free fences | |
2446 | * no pending flips. | |
2447 | * | |
2448 | * This is propagated to atomic, but it uses | |
2449 | * -EDEADLK to force a locking recovery, so | |
2450 | * change the returned error to -EBUSY. | |
2451 | */ | |
2452 | ret = -EBUSY; | |
2453 | goto err_unpin; | |
2454 | } else if (ret) | |
2455 | goto err_unpin; | |
1690e1eb | 2456 | |
9807216f VK |
2457 | i915_gem_object_pin_fence(obj); |
2458 | } | |
6b95a207 | 2459 | |
d6dd6843 | 2460 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2461 | return 0; |
48b956c5 CW |
2462 | |
2463 | err_unpin: | |
f64b98cd | 2464 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2465 | err_pm: |
d6dd6843 | 2466 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2467 | return ret; |
6b95a207 KH |
2468 | } |
2469 | ||
3465c580 | 2470 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2471 | { |
82bc3b2d | 2472 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2473 | struct i915_ggtt_view view; |
82bc3b2d | 2474 | |
ebcdd39e MR |
2475 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2476 | ||
3465c580 | 2477 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2478 | |
9807216f VK |
2479 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2480 | i915_gem_object_unpin_fence(obj); | |
2481 | ||
f64b98cd | 2482 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2483 | } |
2484 | ||
29cf9491 VS |
2485 | /* |
2486 | * Adjust the tile offset by moving the difference into | |
2487 | * the x/y offsets. | |
2488 | * | |
2489 | * Input tile dimensions and pitch must already be | |
2490 | * rotated to match x and y, and in pixel units. | |
2491 | */ | |
2492 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2493 | unsigned int tile_width, | |
2494 | unsigned int tile_height, | |
2495 | unsigned int tile_size, | |
2496 | unsigned int pitch_tiles, | |
2497 | u32 old_offset, | |
2498 | u32 new_offset) | |
2499 | { | |
2500 | unsigned int tiles; | |
2501 | ||
2502 | WARN_ON(old_offset & (tile_size - 1)); | |
2503 | WARN_ON(new_offset & (tile_size - 1)); | |
2504 | WARN_ON(new_offset > old_offset); | |
2505 | ||
2506 | tiles = (old_offset - new_offset) / tile_size; | |
2507 | ||
2508 | *y += tiles / pitch_tiles * tile_height; | |
2509 | *x += tiles % pitch_tiles * tile_width; | |
2510 | ||
2511 | return new_offset; | |
2512 | } | |
2513 | ||
8d0deca8 VS |
2514 | /* |
2515 | * Computes the linear offset to the base tile and adjusts | |
2516 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2517 | * | |
2518 | * In the 90/270 rotated case, x and y are assumed | |
2519 | * to be already rotated to match the rotated GTT view, and | |
2520 | * pitch is the tile_height aligned framebuffer height. | |
2521 | */ | |
4f2d9934 VS |
2522 | u32 intel_compute_tile_offset(int *x, int *y, |
2523 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2524 | unsigned int pitch, |
2525 | unsigned int rotation) | |
c2c75131 | 2526 | { |
4f2d9934 VS |
2527 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2528 | uint64_t fb_modifier = fb->modifier[plane]; | |
2529 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2530 | u32 offset, offset_aligned, alignment; |
2531 | ||
2532 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2533 | if (alignment) | |
2534 | alignment--; | |
2535 | ||
b5c65338 | 2536 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2537 | unsigned int tile_size, tile_width, tile_height; |
2538 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2539 | |
d843310d | 2540 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2541 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2542 | fb_modifier, cpp); | |
2543 | ||
2544 | if (intel_rotation_90_or_270(rotation)) { | |
2545 | pitch_tiles = pitch / tile_height; | |
2546 | swap(tile_width, tile_height); | |
2547 | } else { | |
2548 | pitch_tiles = pitch / (tile_width * cpp); | |
2549 | } | |
d843310d VS |
2550 | |
2551 | tile_rows = *y / tile_height; | |
2552 | *y %= tile_height; | |
c2c75131 | 2553 | |
8d0deca8 VS |
2554 | tiles = *x / tile_width; |
2555 | *x %= tile_width; | |
bc752862 | 2556 | |
29cf9491 VS |
2557 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2558 | offset_aligned = offset & ~alignment; | |
bc752862 | 2559 | |
29cf9491 VS |
2560 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2561 | tile_size, pitch_tiles, | |
2562 | offset, offset_aligned); | |
2563 | } else { | |
bc752862 | 2564 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2565 | offset_aligned = offset & ~alignment; |
2566 | ||
4e9a86b6 VS |
2567 | *y = (offset & alignment) / pitch; |
2568 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2569 | } |
29cf9491 VS |
2570 | |
2571 | return offset_aligned; | |
c2c75131 DV |
2572 | } |
2573 | ||
b35d63fa | 2574 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2575 | { |
2576 | switch (format) { | |
2577 | case DISPPLANE_8BPP: | |
2578 | return DRM_FORMAT_C8; | |
2579 | case DISPPLANE_BGRX555: | |
2580 | return DRM_FORMAT_XRGB1555; | |
2581 | case DISPPLANE_BGRX565: | |
2582 | return DRM_FORMAT_RGB565; | |
2583 | default: | |
2584 | case DISPPLANE_BGRX888: | |
2585 | return DRM_FORMAT_XRGB8888; | |
2586 | case DISPPLANE_RGBX888: | |
2587 | return DRM_FORMAT_XBGR8888; | |
2588 | case DISPPLANE_BGRX101010: | |
2589 | return DRM_FORMAT_XRGB2101010; | |
2590 | case DISPPLANE_RGBX101010: | |
2591 | return DRM_FORMAT_XBGR2101010; | |
2592 | } | |
2593 | } | |
2594 | ||
bc8d7dff DL |
2595 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2596 | { | |
2597 | switch (format) { | |
2598 | case PLANE_CTL_FORMAT_RGB_565: | |
2599 | return DRM_FORMAT_RGB565; | |
2600 | default: | |
2601 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2602 | if (rgb_order) { | |
2603 | if (alpha) | |
2604 | return DRM_FORMAT_ABGR8888; | |
2605 | else | |
2606 | return DRM_FORMAT_XBGR8888; | |
2607 | } else { | |
2608 | if (alpha) | |
2609 | return DRM_FORMAT_ARGB8888; | |
2610 | else | |
2611 | return DRM_FORMAT_XRGB8888; | |
2612 | } | |
2613 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2614 | if (rgb_order) | |
2615 | return DRM_FORMAT_XBGR2101010; | |
2616 | else | |
2617 | return DRM_FORMAT_XRGB2101010; | |
2618 | } | |
2619 | } | |
2620 | ||
5724dbd1 | 2621 | static bool |
f6936e29 DV |
2622 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2623 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2624 | { |
2625 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2626 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2627 | struct drm_i915_gem_object *obj = NULL; |
2628 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2629 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2630 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2631 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2632 | PAGE_SIZE); | |
2633 | ||
2634 | size_aligned -= base_aligned; | |
46f297fb | 2635 | |
ff2652ea CW |
2636 | if (plane_config->size == 0) |
2637 | return false; | |
2638 | ||
3badb49f PZ |
2639 | /* If the FB is too big, just don't use it since fbdev is not very |
2640 | * important and we should probably use that space with FBC or other | |
2641 | * features. */ | |
2642 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2643 | return false; | |
2644 | ||
12c83d99 TU |
2645 | mutex_lock(&dev->struct_mutex); |
2646 | ||
f37b5c2b DV |
2647 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2648 | base_aligned, | |
2649 | base_aligned, | |
2650 | size_aligned); | |
12c83d99 TU |
2651 | if (!obj) { |
2652 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2653 | return false; |
12c83d99 | 2654 | } |
46f297fb | 2655 | |
49af449b DL |
2656 | obj->tiling_mode = plane_config->tiling; |
2657 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2658 | obj->stride = fb->pitches[0]; |
46f297fb | 2659 | |
6bf129df DL |
2660 | mode_cmd.pixel_format = fb->pixel_format; |
2661 | mode_cmd.width = fb->width; | |
2662 | mode_cmd.height = fb->height; | |
2663 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2664 | mode_cmd.modifier[0] = fb->modifier[0]; |
2665 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2666 | |
6bf129df | 2667 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2668 | &mode_cmd, obj)) { |
46f297fb JB |
2669 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2670 | goto out_unref_obj; | |
2671 | } | |
12c83d99 | 2672 | |
46f297fb | 2673 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2674 | |
f6936e29 | 2675 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2676 | return true; |
46f297fb JB |
2677 | |
2678 | out_unref_obj: | |
2679 | drm_gem_object_unreference(&obj->base); | |
2680 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2681 | return false; |
2682 | } | |
2683 | ||
afd65eb4 MR |
2684 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2685 | static void | |
2686 | update_state_fb(struct drm_plane *plane) | |
2687 | { | |
2688 | if (plane->fb == plane->state->fb) | |
2689 | return; | |
2690 | ||
2691 | if (plane->state->fb) | |
2692 | drm_framebuffer_unreference(plane->state->fb); | |
2693 | plane->state->fb = plane->fb; | |
2694 | if (plane->state->fb) | |
2695 | drm_framebuffer_reference(plane->state->fb); | |
2696 | } | |
2697 | ||
5724dbd1 | 2698 | static void |
f6936e29 DV |
2699 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2700 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2701 | { |
2702 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2703 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2704 | struct drm_crtc *c; |
2705 | struct intel_crtc *i; | |
2ff8fde1 | 2706 | struct drm_i915_gem_object *obj; |
88595ac9 | 2707 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2708 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2709 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2710 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2711 | struct intel_plane_state *intel_state = |
2712 | to_intel_plane_state(plane_state); | |
88595ac9 | 2713 | struct drm_framebuffer *fb; |
484b41dd | 2714 | |
2d14030b | 2715 | if (!plane_config->fb) |
484b41dd JB |
2716 | return; |
2717 | ||
f6936e29 | 2718 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2719 | fb = &plane_config->fb->base; |
2720 | goto valid_fb; | |
f55548b5 | 2721 | } |
484b41dd | 2722 | |
2d14030b | 2723 | kfree(plane_config->fb); |
484b41dd JB |
2724 | |
2725 | /* | |
2726 | * Failed to alloc the obj, check to see if we should share | |
2727 | * an fb with another CRTC instead | |
2728 | */ | |
70e1e0ec | 2729 | for_each_crtc(dev, c) { |
484b41dd JB |
2730 | i = to_intel_crtc(c); |
2731 | ||
2732 | if (c == &intel_crtc->base) | |
2733 | continue; | |
2734 | ||
2ff8fde1 MR |
2735 | if (!i->active) |
2736 | continue; | |
2737 | ||
88595ac9 DV |
2738 | fb = c->primary->fb; |
2739 | if (!fb) | |
484b41dd JB |
2740 | continue; |
2741 | ||
88595ac9 | 2742 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2743 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2744 | drm_framebuffer_reference(fb); |
2745 | goto valid_fb; | |
484b41dd JB |
2746 | } |
2747 | } | |
88595ac9 | 2748 | |
200757f5 MR |
2749 | /* |
2750 | * We've failed to reconstruct the BIOS FB. Current display state | |
2751 | * indicates that the primary plane is visible, but has a NULL FB, | |
2752 | * which will lead to problems later if we don't fix it up. The | |
2753 | * simplest solution is to just disable the primary plane now and | |
2754 | * pretend the BIOS never had it enabled. | |
2755 | */ | |
2756 | to_intel_plane_state(plane_state)->visible = false; | |
2757 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2758 | intel_pre_disable_primary(&intel_crtc->base); | |
2759 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2760 | ||
88595ac9 DV |
2761 | return; |
2762 | ||
2763 | valid_fb: | |
f44e2659 VS |
2764 | plane_state->src_x = 0; |
2765 | plane_state->src_y = 0; | |
be5651f2 ML |
2766 | plane_state->src_w = fb->width << 16; |
2767 | plane_state->src_h = fb->height << 16; | |
2768 | ||
f44e2659 VS |
2769 | plane_state->crtc_x = 0; |
2770 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2771 | plane_state->crtc_w = fb->width; |
2772 | plane_state->crtc_h = fb->height; | |
2773 | ||
0a8d8a86 MR |
2774 | intel_state->src.x1 = plane_state->src_x; |
2775 | intel_state->src.y1 = plane_state->src_y; | |
2776 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2777 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2778 | intel_state->dst.x1 = plane_state->crtc_x; | |
2779 | intel_state->dst.y1 = plane_state->crtc_y; | |
2780 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2781 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2782 | ||
88595ac9 DV |
2783 | obj = intel_fb_obj(fb); |
2784 | if (obj->tiling_mode != I915_TILING_NONE) | |
2785 | dev_priv->preserve_bios_swizzle = true; | |
2786 | ||
be5651f2 ML |
2787 | drm_framebuffer_reference(fb); |
2788 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2789 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2790 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2791 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2792 | } |
2793 | ||
a8d201af ML |
2794 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2795 | const struct intel_crtc_state *crtc_state, | |
2796 | const struct intel_plane_state *plane_state) | |
81255565 | 2797 | { |
a8d201af | 2798 | struct drm_device *dev = primary->dev; |
81255565 | 2799 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2800 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2801 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2802 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2803 | int plane = intel_crtc->plane; |
54ea9da8 | 2804 | u32 linear_offset; |
81255565 | 2805 | u32 dspcntr; |
f0f59a00 | 2806 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2807 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2808 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2809 | int x = plane_state->src.x1 >> 16; |
2810 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2811 | |
f45651ba VS |
2812 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2813 | ||
fdd508a6 | 2814 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2815 | |
2816 | if (INTEL_INFO(dev)->gen < 4) { | |
2817 | if (intel_crtc->pipe == PIPE_B) | |
2818 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2819 | ||
2820 | /* pipesrc and dspsize control the size that is scaled from, | |
2821 | * which should always be the user's requested size. | |
2822 | */ | |
2823 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2824 | ((crtc_state->pipe_src_h - 1) << 16) | |
2825 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2826 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2827 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2828 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2829 | ((crtc_state->pipe_src_h - 1) << 16) | |
2830 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2831 | I915_WRITE(PRIMPOS(plane), 0); |
2832 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2833 | } |
81255565 | 2834 | |
57779d06 VS |
2835 | switch (fb->pixel_format) { |
2836 | case DRM_FORMAT_C8: | |
81255565 JB |
2837 | dspcntr |= DISPPLANE_8BPP; |
2838 | break; | |
57779d06 | 2839 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2840 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2841 | break; |
57779d06 VS |
2842 | case DRM_FORMAT_RGB565: |
2843 | dspcntr |= DISPPLANE_BGRX565; | |
2844 | break; | |
2845 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2846 | dspcntr |= DISPPLANE_BGRX888; |
2847 | break; | |
2848 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2849 | dspcntr |= DISPPLANE_RGBX888; |
2850 | break; | |
2851 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2852 | dspcntr |= DISPPLANE_BGRX101010; |
2853 | break; | |
2854 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2855 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2856 | break; |
2857 | default: | |
baba133a | 2858 | BUG(); |
81255565 | 2859 | } |
57779d06 | 2860 | |
f45651ba VS |
2861 | if (INTEL_INFO(dev)->gen >= 4 && |
2862 | obj->tiling_mode != I915_TILING_NONE) | |
2863 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2864 | |
de1aa629 VS |
2865 | if (IS_G4X(dev)) |
2866 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2867 | ||
ac484963 | 2868 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2869 | |
c2c75131 DV |
2870 | if (INTEL_INFO(dev)->gen >= 4) { |
2871 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2872 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2873 | fb->pitches[0], rotation); |
c2c75131 DV |
2874 | linear_offset -= intel_crtc->dspaddr_offset; |
2875 | } else { | |
e506a0c6 | 2876 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2877 | } |
e506a0c6 | 2878 | |
8d0deca8 | 2879 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2880 | dspcntr |= DISPPLANE_ROTATE_180; |
2881 | ||
a8d201af ML |
2882 | x += (crtc_state->pipe_src_w - 1); |
2883 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2884 | |
2885 | /* Finding the last pixel of the last line of the display | |
2886 | data and adding to linear_offset*/ | |
2887 | linear_offset += | |
a8d201af | 2888 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2889 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2890 | } |
2891 | ||
2db3366b PZ |
2892 | intel_crtc->adjusted_x = x; |
2893 | intel_crtc->adjusted_y = y; | |
2894 | ||
48404c1e SJ |
2895 | I915_WRITE(reg, dspcntr); |
2896 | ||
01f2c773 | 2897 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2898 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2899 | I915_WRITE(DSPSURF(plane), |
2900 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2901 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2902 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2903 | } else |
f343c5f6 | 2904 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2905 | POSTING_READ(reg); |
17638cd6 JB |
2906 | } |
2907 | ||
a8d201af ML |
2908 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2909 | struct drm_crtc *crtc) | |
17638cd6 JB |
2910 | { |
2911 | struct drm_device *dev = crtc->dev; | |
2912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2913 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2914 | int plane = intel_crtc->plane; |
f45651ba | 2915 | |
a8d201af ML |
2916 | I915_WRITE(DSPCNTR(plane), 0); |
2917 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2918 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2919 | else |
2920 | I915_WRITE(DSPADDR(plane), 0); | |
2921 | POSTING_READ(DSPCNTR(plane)); | |
2922 | } | |
c9ba6fad | 2923 | |
a8d201af ML |
2924 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2925 | const struct intel_crtc_state *crtc_state, | |
2926 | const struct intel_plane_state *plane_state) | |
2927 | { | |
2928 | struct drm_device *dev = primary->dev; | |
2929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2930 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2931 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2932 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2933 | int plane = intel_crtc->plane; | |
54ea9da8 | 2934 | u32 linear_offset; |
a8d201af ML |
2935 | u32 dspcntr; |
2936 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2937 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2938 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2939 | int x = plane_state->src.x1 >> 16; |
2940 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2941 | |
f45651ba | 2942 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2943 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2944 | |
2945 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2946 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2947 | |
57779d06 VS |
2948 | switch (fb->pixel_format) { |
2949 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2950 | dspcntr |= DISPPLANE_8BPP; |
2951 | break; | |
57779d06 VS |
2952 | case DRM_FORMAT_RGB565: |
2953 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2954 | break; |
57779d06 | 2955 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2956 | dspcntr |= DISPPLANE_BGRX888; |
2957 | break; | |
2958 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2959 | dspcntr |= DISPPLANE_RGBX888; |
2960 | break; | |
2961 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2962 | dspcntr |= DISPPLANE_BGRX101010; |
2963 | break; | |
2964 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2965 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2966 | break; |
2967 | default: | |
baba133a | 2968 | BUG(); |
17638cd6 JB |
2969 | } |
2970 | ||
2971 | if (obj->tiling_mode != I915_TILING_NONE) | |
2972 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2973 | |
f45651ba | 2974 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2975 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2976 | |
ac484963 | 2977 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2978 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2979 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2980 | fb->pitches[0], rotation); |
c2c75131 | 2981 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2982 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2983 | dspcntr |= DISPPLANE_ROTATE_180; |
2984 | ||
2985 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2986 | x += (crtc_state->pipe_src_w - 1); |
2987 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2988 | |
2989 | /* Finding the last pixel of the last line of the display | |
2990 | data and adding to linear_offset*/ | |
2991 | linear_offset += | |
a8d201af | 2992 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2993 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2994 | } |
2995 | } | |
2996 | ||
2db3366b PZ |
2997 | intel_crtc->adjusted_x = x; |
2998 | intel_crtc->adjusted_y = y; | |
2999 | ||
48404c1e | 3000 | I915_WRITE(reg, dspcntr); |
17638cd6 | 3001 | |
01f2c773 | 3002 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
3003 | I915_WRITE(DSPSURF(plane), |
3004 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 3005 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
3006 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
3007 | } else { | |
3008 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
3009 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
3010 | } | |
17638cd6 | 3011 | POSTING_READ(reg); |
17638cd6 JB |
3012 | } |
3013 | ||
7b49f948 VS |
3014 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
3015 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 3016 | { |
7b49f948 | 3017 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 3018 | return 64; |
7b49f948 VS |
3019 | } else { |
3020 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
3021 | ||
27ba3910 | 3022 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
3023 | } |
3024 | } | |
3025 | ||
44eb0cb9 MK |
3026 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
3027 | struct drm_i915_gem_object *obj, | |
3028 | unsigned int plane) | |
121920fa | 3029 | { |
ce7f1728 | 3030 | struct i915_ggtt_view view; |
dedf278c | 3031 | struct i915_vma *vma; |
44eb0cb9 | 3032 | u64 offset; |
121920fa | 3033 | |
e7941294 | 3034 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 3035 | intel_plane->base.state->rotation); |
121920fa | 3036 | |
ce7f1728 | 3037 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 3038 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 3039 | view.type)) |
dedf278c TU |
3040 | return -1; |
3041 | ||
44eb0cb9 | 3042 | offset = vma->node.start; |
dedf278c TU |
3043 | |
3044 | if (plane == 1) { | |
7723f47d | 3045 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
3046 | PAGE_SIZE; |
3047 | } | |
3048 | ||
44eb0cb9 MK |
3049 | WARN_ON(upper_32_bits(offset)); |
3050 | ||
3051 | return lower_32_bits(offset); | |
121920fa TU |
3052 | } |
3053 | ||
e435d6e5 ML |
3054 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3055 | { | |
3056 | struct drm_device *dev = intel_crtc->base.dev; | |
3057 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3058 | ||
3059 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3060 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3061 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3062 | } |
3063 | ||
a1b2278e CK |
3064 | /* |
3065 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3066 | */ | |
0583236e | 3067 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3068 | { |
a1b2278e CK |
3069 | struct intel_crtc_scaler_state *scaler_state; |
3070 | int i; | |
3071 | ||
a1b2278e CK |
3072 | scaler_state = &intel_crtc->config->scaler_state; |
3073 | ||
3074 | /* loop through and disable scalers that aren't in use */ | |
3075 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3076 | if (!scaler_state->scalers[i].in_use) |
3077 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3078 | } |
3079 | } | |
3080 | ||
6156a456 | 3081 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3082 | { |
6156a456 | 3083 | switch (pixel_format) { |
d161cf7a | 3084 | case DRM_FORMAT_C8: |
c34ce3d1 | 3085 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3086 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3087 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3088 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3089 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3090 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3091 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3092 | /* |
3093 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3094 | * to be already pre-multiplied. We need to add a knob (or a different | |
3095 | * DRM_FORMAT) for user-space to configure that. | |
3096 | */ | |
f75fb42a | 3097 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3098 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3099 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3100 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3101 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3102 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3103 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3104 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3105 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3106 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3107 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3108 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3109 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3110 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3111 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3112 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3113 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3114 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3115 | default: |
4249eeef | 3116 | MISSING_CASE(pixel_format); |
70d21f0e | 3117 | } |
8cfcba41 | 3118 | |
c34ce3d1 | 3119 | return 0; |
6156a456 | 3120 | } |
70d21f0e | 3121 | |
6156a456 CK |
3122 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3123 | { | |
6156a456 | 3124 | switch (fb_modifier) { |
30af77c4 | 3125 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3126 | break; |
30af77c4 | 3127 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3128 | return PLANE_CTL_TILED_X; |
b321803d | 3129 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3130 | return PLANE_CTL_TILED_Y; |
b321803d | 3131 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3132 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3133 | default: |
6156a456 | 3134 | MISSING_CASE(fb_modifier); |
70d21f0e | 3135 | } |
8cfcba41 | 3136 | |
c34ce3d1 | 3137 | return 0; |
6156a456 | 3138 | } |
70d21f0e | 3139 | |
6156a456 CK |
3140 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3141 | { | |
3b7a5119 | 3142 | switch (rotation) { |
6156a456 CK |
3143 | case BIT(DRM_ROTATE_0): |
3144 | break; | |
1e8df167 SJ |
3145 | /* |
3146 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3147 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3148 | */ | |
3b7a5119 | 3149 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3150 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3151 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3152 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3153 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3154 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3155 | default: |
3156 | MISSING_CASE(rotation); | |
3157 | } | |
3158 | ||
c34ce3d1 | 3159 | return 0; |
6156a456 CK |
3160 | } |
3161 | ||
a8d201af ML |
3162 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3163 | const struct intel_crtc_state *crtc_state, | |
3164 | const struct intel_plane_state *plane_state) | |
6156a456 | 3165 | { |
a8d201af | 3166 | struct drm_device *dev = plane->dev; |
6156a456 | 3167 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3168 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3169 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3170 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3171 | int pipe = intel_crtc->pipe; |
3172 | u32 plane_ctl, stride_div, stride; | |
3173 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3174 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3175 | int x_offset, y_offset; |
44eb0cb9 | 3176 | u32 surf_addr; |
a8d201af ML |
3177 | int scaler_id = plane_state->scaler_id; |
3178 | int src_x = plane_state->src.x1 >> 16; | |
3179 | int src_y = plane_state->src.y1 >> 16; | |
3180 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3181 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3182 | int dst_x = plane_state->dst.x1; | |
3183 | int dst_y = plane_state->dst.y1; | |
3184 | int dst_w = drm_rect_width(&plane_state->dst); | |
3185 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3186 | |
6156a456 CK |
3187 | plane_ctl = PLANE_CTL_ENABLE | |
3188 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3189 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3190 | ||
3191 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3192 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3193 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3194 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3195 | ||
7b49f948 | 3196 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3197 | fb->pixel_format); |
dedf278c | 3198 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3199 | |
a42e5a23 PZ |
3200 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3201 | ||
3b7a5119 | 3202 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3203 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3204 | ||
3b7a5119 | 3205 | /* stride = Surface height in tiles */ |
832be82f | 3206 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3207 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3208 | x_offset = stride * tile_height - src_y - src_h; |
3209 | y_offset = src_x; | |
6156a456 | 3210 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3211 | } else { |
3212 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3213 | x_offset = src_x; |
3214 | y_offset = src_y; | |
6156a456 | 3215 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3216 | } |
3217 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3218 | |
2db3366b PZ |
3219 | intel_crtc->adjusted_x = x_offset; |
3220 | intel_crtc->adjusted_y = y_offset; | |
3221 | ||
70d21f0e | 3222 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3223 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3224 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3225 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3226 | |
3227 | if (scaler_id >= 0) { | |
3228 | uint32_t ps_ctrl = 0; | |
3229 | ||
3230 | WARN_ON(!dst_w || !dst_h); | |
3231 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3232 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3233 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3234 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3235 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3236 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3237 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3238 | } else { | |
3239 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3240 | } | |
3241 | ||
121920fa | 3242 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3243 | |
3244 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3245 | } | |
3246 | ||
a8d201af ML |
3247 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3248 | struct drm_crtc *crtc) | |
17638cd6 JB |
3249 | { |
3250 | struct drm_device *dev = crtc->dev; | |
3251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3252 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3253 | |
a8d201af ML |
3254 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3255 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3256 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3257 | } | |
29b9bde6 | 3258 | |
a8d201af ML |
3259 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3260 | static int | |
3261 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3262 | int x, int y, enum mode_set_atomic state) | |
3263 | { | |
3264 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3265 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3266 | ||
3267 | return -ENODEV; | |
81255565 JB |
3268 | } |
3269 | ||
7514747d | 3270 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3271 | { |
96a02917 VS |
3272 | struct drm_crtc *crtc; |
3273 | ||
70e1e0ec | 3274 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3275 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3276 | enum plane plane = intel_crtc->plane; | |
3277 | ||
3278 | intel_prepare_page_flip(dev, plane); | |
3279 | intel_finish_page_flip_plane(dev, plane); | |
3280 | } | |
7514747d VS |
3281 | } |
3282 | ||
3283 | static void intel_update_primary_planes(struct drm_device *dev) | |
3284 | { | |
7514747d | 3285 | struct drm_crtc *crtc; |
96a02917 | 3286 | |
70e1e0ec | 3287 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3288 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3289 | struct intel_plane_state *plane_state; | |
96a02917 | 3290 | |
11c22da6 | 3291 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3292 | plane_state = to_intel_plane_state(plane->base.state); |
3293 | ||
a8d201af ML |
3294 | if (plane_state->visible) |
3295 | plane->update_plane(&plane->base, | |
3296 | to_intel_crtc_state(crtc->state), | |
3297 | plane_state); | |
11c22da6 ML |
3298 | |
3299 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3300 | } |
3301 | } | |
3302 | ||
7514747d VS |
3303 | void intel_prepare_reset(struct drm_device *dev) |
3304 | { | |
3305 | /* no reset support for gen2 */ | |
3306 | if (IS_GEN2(dev)) | |
3307 | return; | |
3308 | ||
3309 | /* reset doesn't touch the display */ | |
3310 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3311 | return; | |
3312 | ||
3313 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3314 | /* |
3315 | * Disabling the crtcs gracefully seems nicer. Also the | |
3316 | * g33 docs say we should at least disable all the planes. | |
3317 | */ | |
6b72d486 | 3318 | intel_display_suspend(dev); |
7514747d VS |
3319 | } |
3320 | ||
3321 | void intel_finish_reset(struct drm_device *dev) | |
3322 | { | |
3323 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3324 | ||
3325 | /* | |
3326 | * Flips in the rings will be nuked by the reset, | |
3327 | * so complete all pending flips so that user space | |
3328 | * will get its events and not get stuck. | |
3329 | */ | |
3330 | intel_complete_page_flips(dev); | |
3331 | ||
3332 | /* no reset support for gen2 */ | |
3333 | if (IS_GEN2(dev)) | |
3334 | return; | |
3335 | ||
3336 | /* reset doesn't touch the display */ | |
3337 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3338 | /* | |
3339 | * Flips in the rings have been nuked by the reset, | |
3340 | * so update the base address of all primary | |
3341 | * planes to the the last fb to make sure we're | |
3342 | * showing the correct fb after a reset. | |
11c22da6 ML |
3343 | * |
3344 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3345 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3346 | */ |
3347 | intel_update_primary_planes(dev); | |
3348 | return; | |
3349 | } | |
3350 | ||
3351 | /* | |
3352 | * The display has been reset as well, | |
3353 | * so need a full re-initialization. | |
3354 | */ | |
3355 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3356 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3357 | ||
3358 | intel_modeset_init_hw(dev); | |
3359 | ||
3360 | spin_lock_irq(&dev_priv->irq_lock); | |
3361 | if (dev_priv->display.hpd_irq_setup) | |
3362 | dev_priv->display.hpd_irq_setup(dev); | |
3363 | spin_unlock_irq(&dev_priv->irq_lock); | |
3364 | ||
043e9bda | 3365 | intel_display_resume(dev); |
7514747d VS |
3366 | |
3367 | intel_hpd_init(dev_priv); | |
3368 | ||
3369 | drm_modeset_unlock_all(dev); | |
3370 | } | |
3371 | ||
7d5e3799 CW |
3372 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3373 | { | |
3374 | struct drm_device *dev = crtc->dev; | |
3375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3377 | bool pending; |
3378 | ||
3379 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3380 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3381 | return false; | |
3382 | ||
5e2d7afc | 3383 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3384 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3385 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3386 | |
3387 | return pending; | |
3388 | } | |
3389 | ||
bfd16b2a ML |
3390 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3391 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3392 | { |
3393 | struct drm_device *dev = crtc->base.dev; | |
3394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3395 | struct intel_crtc_state *pipe_config = |
3396 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3397 | |
bfd16b2a ML |
3398 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3399 | crtc->base.mode = crtc->base.state->mode; | |
3400 | ||
3401 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3402 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3403 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3404 | |
44522d85 ML |
3405 | if (HAS_DDI(dev)) |
3406 | intel_set_pipe_csc(&crtc->base); | |
3407 | ||
e30e8f75 GP |
3408 | /* |
3409 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3410 | * that in compute_mode_changes we check the native mode (not the pfit | |
3411 | * mode) to see if we can flip rather than do a full mode set. In the | |
3412 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3413 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3414 | * sized surface. | |
e30e8f75 GP |
3415 | */ |
3416 | ||
e30e8f75 | 3417 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3418 | ((pipe_config->pipe_src_w - 1) << 16) | |
3419 | (pipe_config->pipe_src_h - 1)); | |
3420 | ||
3421 | /* on skylake this is done by detaching scalers */ | |
3422 | if (INTEL_INFO(dev)->gen >= 9) { | |
3423 | skl_detach_scalers(crtc); | |
3424 | ||
3425 | if (pipe_config->pch_pfit.enabled) | |
3426 | skylake_pfit_enable(crtc); | |
3427 | } else if (HAS_PCH_SPLIT(dev)) { | |
3428 | if (pipe_config->pch_pfit.enabled) | |
3429 | ironlake_pfit_enable(crtc); | |
3430 | else if (old_crtc_state->pch_pfit.enabled) | |
3431 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3432 | } |
e30e8f75 GP |
3433 | } |
3434 | ||
5e84e1a4 ZW |
3435 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3436 | { | |
3437 | struct drm_device *dev = crtc->dev; | |
3438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3439 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3440 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3441 | i915_reg_t reg; |
3442 | u32 temp; | |
5e84e1a4 ZW |
3443 | |
3444 | /* enable normal train */ | |
3445 | reg = FDI_TX_CTL(pipe); | |
3446 | temp = I915_READ(reg); | |
61e499bf | 3447 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3448 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3449 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3450 | } else { |
3451 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3452 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3453 | } |
5e84e1a4 ZW |
3454 | I915_WRITE(reg, temp); |
3455 | ||
3456 | reg = FDI_RX_CTL(pipe); | |
3457 | temp = I915_READ(reg); | |
3458 | if (HAS_PCH_CPT(dev)) { | |
3459 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3460 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3461 | } else { | |
3462 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3463 | temp |= FDI_LINK_TRAIN_NONE; | |
3464 | } | |
3465 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3466 | ||
3467 | /* wait one idle pattern time */ | |
3468 | POSTING_READ(reg); | |
3469 | udelay(1000); | |
357555c0 JB |
3470 | |
3471 | /* IVB wants error correction enabled */ | |
3472 | if (IS_IVYBRIDGE(dev)) | |
3473 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3474 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3475 | } |
3476 | ||
8db9d77b ZW |
3477 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3478 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3479 | { | |
3480 | struct drm_device *dev = crtc->dev; | |
3481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3482 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3483 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3484 | i915_reg_t reg; |
3485 | u32 temp, tries; | |
8db9d77b | 3486 | |
1c8562f6 | 3487 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3488 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3489 | |
e1a44743 AJ |
3490 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3491 | for train result */ | |
5eddb70b CW |
3492 | reg = FDI_RX_IMR(pipe); |
3493 | temp = I915_READ(reg); | |
e1a44743 AJ |
3494 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3495 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3496 | I915_WRITE(reg, temp); |
3497 | I915_READ(reg); | |
e1a44743 AJ |
3498 | udelay(150); |
3499 | ||
8db9d77b | 3500 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3501 | reg = FDI_TX_CTL(pipe); |
3502 | temp = I915_READ(reg); | |
627eb5a3 | 3503 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3504 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3505 | temp &= ~FDI_LINK_TRAIN_NONE; |
3506 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3507 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3508 | |
5eddb70b CW |
3509 | reg = FDI_RX_CTL(pipe); |
3510 | temp = I915_READ(reg); | |
8db9d77b ZW |
3511 | temp &= ~FDI_LINK_TRAIN_NONE; |
3512 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3513 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3514 | ||
3515 | POSTING_READ(reg); | |
8db9d77b ZW |
3516 | udelay(150); |
3517 | ||
5b2adf89 | 3518 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3519 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3520 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3521 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3522 | |
5eddb70b | 3523 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3524 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3525 | temp = I915_READ(reg); |
8db9d77b ZW |
3526 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3527 | ||
3528 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3529 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3530 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3531 | break; |
3532 | } | |
8db9d77b | 3533 | } |
e1a44743 | 3534 | if (tries == 5) |
5eddb70b | 3535 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3536 | |
3537 | /* Train 2 */ | |
5eddb70b CW |
3538 | reg = FDI_TX_CTL(pipe); |
3539 | temp = I915_READ(reg); | |
8db9d77b ZW |
3540 | temp &= ~FDI_LINK_TRAIN_NONE; |
3541 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3542 | I915_WRITE(reg, temp); |
8db9d77b | 3543 | |
5eddb70b CW |
3544 | reg = FDI_RX_CTL(pipe); |
3545 | temp = I915_READ(reg); | |
8db9d77b ZW |
3546 | temp &= ~FDI_LINK_TRAIN_NONE; |
3547 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3548 | I915_WRITE(reg, temp); |
8db9d77b | 3549 | |
5eddb70b CW |
3550 | POSTING_READ(reg); |
3551 | udelay(150); | |
8db9d77b | 3552 | |
5eddb70b | 3553 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3554 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3555 | temp = I915_READ(reg); |
8db9d77b ZW |
3556 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3557 | ||
3558 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3559 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3560 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3561 | break; | |
3562 | } | |
8db9d77b | 3563 | } |
e1a44743 | 3564 | if (tries == 5) |
5eddb70b | 3565 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3566 | |
3567 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3568 | |
8db9d77b ZW |
3569 | } |
3570 | ||
0206e353 | 3571 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3572 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3573 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3574 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3575 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3576 | }; | |
3577 | ||
3578 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3579 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3580 | { | |
3581 | struct drm_device *dev = crtc->dev; | |
3582 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3583 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3584 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3585 | i915_reg_t reg; |
3586 | u32 temp, i, retry; | |
8db9d77b | 3587 | |
e1a44743 AJ |
3588 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3589 | for train result */ | |
5eddb70b CW |
3590 | reg = FDI_RX_IMR(pipe); |
3591 | temp = I915_READ(reg); | |
e1a44743 AJ |
3592 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3593 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3594 | I915_WRITE(reg, temp); |
3595 | ||
3596 | POSTING_READ(reg); | |
e1a44743 AJ |
3597 | udelay(150); |
3598 | ||
8db9d77b | 3599 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3600 | reg = FDI_TX_CTL(pipe); |
3601 | temp = I915_READ(reg); | |
627eb5a3 | 3602 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3603 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3604 | temp &= ~FDI_LINK_TRAIN_NONE; |
3605 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3606 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3607 | /* SNB-B */ | |
3608 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3609 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3610 | |
d74cf324 DV |
3611 | I915_WRITE(FDI_RX_MISC(pipe), |
3612 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3613 | ||
5eddb70b CW |
3614 | reg = FDI_RX_CTL(pipe); |
3615 | temp = I915_READ(reg); | |
8db9d77b ZW |
3616 | if (HAS_PCH_CPT(dev)) { |
3617 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3618 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3619 | } else { | |
3620 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3621 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3622 | } | |
5eddb70b CW |
3623 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3624 | ||
3625 | POSTING_READ(reg); | |
8db9d77b ZW |
3626 | udelay(150); |
3627 | ||
0206e353 | 3628 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3629 | reg = FDI_TX_CTL(pipe); |
3630 | temp = I915_READ(reg); | |
8db9d77b ZW |
3631 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3632 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3633 | I915_WRITE(reg, temp); |
3634 | ||
3635 | POSTING_READ(reg); | |
8db9d77b ZW |
3636 | udelay(500); |
3637 | ||
fa37d39e SP |
3638 | for (retry = 0; retry < 5; retry++) { |
3639 | reg = FDI_RX_IIR(pipe); | |
3640 | temp = I915_READ(reg); | |
3641 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3642 | if (temp & FDI_RX_BIT_LOCK) { | |
3643 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3644 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3645 | break; | |
3646 | } | |
3647 | udelay(50); | |
8db9d77b | 3648 | } |
fa37d39e SP |
3649 | if (retry < 5) |
3650 | break; | |
8db9d77b ZW |
3651 | } |
3652 | if (i == 4) | |
5eddb70b | 3653 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3654 | |
3655 | /* Train 2 */ | |
5eddb70b CW |
3656 | reg = FDI_TX_CTL(pipe); |
3657 | temp = I915_READ(reg); | |
8db9d77b ZW |
3658 | temp &= ~FDI_LINK_TRAIN_NONE; |
3659 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3660 | if (IS_GEN6(dev)) { | |
3661 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3662 | /* SNB-B */ | |
3663 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3664 | } | |
5eddb70b | 3665 | I915_WRITE(reg, temp); |
8db9d77b | 3666 | |
5eddb70b CW |
3667 | reg = FDI_RX_CTL(pipe); |
3668 | temp = I915_READ(reg); | |
8db9d77b ZW |
3669 | if (HAS_PCH_CPT(dev)) { |
3670 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3671 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3672 | } else { | |
3673 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3674 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3675 | } | |
5eddb70b CW |
3676 | I915_WRITE(reg, temp); |
3677 | ||
3678 | POSTING_READ(reg); | |
8db9d77b ZW |
3679 | udelay(150); |
3680 | ||
0206e353 | 3681 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3682 | reg = FDI_TX_CTL(pipe); |
3683 | temp = I915_READ(reg); | |
8db9d77b ZW |
3684 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3685 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3686 | I915_WRITE(reg, temp); |
3687 | ||
3688 | POSTING_READ(reg); | |
8db9d77b ZW |
3689 | udelay(500); |
3690 | ||
fa37d39e SP |
3691 | for (retry = 0; retry < 5; retry++) { |
3692 | reg = FDI_RX_IIR(pipe); | |
3693 | temp = I915_READ(reg); | |
3694 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3695 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3696 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3697 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3698 | break; | |
3699 | } | |
3700 | udelay(50); | |
8db9d77b | 3701 | } |
fa37d39e SP |
3702 | if (retry < 5) |
3703 | break; | |
8db9d77b ZW |
3704 | } |
3705 | if (i == 4) | |
5eddb70b | 3706 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3707 | |
3708 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3709 | } | |
3710 | ||
357555c0 JB |
3711 | /* Manual link training for Ivy Bridge A0 parts */ |
3712 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3713 | { | |
3714 | struct drm_device *dev = crtc->dev; | |
3715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3716 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3717 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3718 | i915_reg_t reg; |
3719 | u32 temp, i, j; | |
357555c0 JB |
3720 | |
3721 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3722 | for train result */ | |
3723 | reg = FDI_RX_IMR(pipe); | |
3724 | temp = I915_READ(reg); | |
3725 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3726 | temp &= ~FDI_RX_BIT_LOCK; | |
3727 | I915_WRITE(reg, temp); | |
3728 | ||
3729 | POSTING_READ(reg); | |
3730 | udelay(150); | |
3731 | ||
01a415fd DV |
3732 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3733 | I915_READ(FDI_RX_IIR(pipe))); | |
3734 | ||
139ccd3f JB |
3735 | /* Try each vswing and preemphasis setting twice before moving on */ |
3736 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3737 | /* disable first in case we need to retry */ | |
3738 | reg = FDI_TX_CTL(pipe); | |
3739 | temp = I915_READ(reg); | |
3740 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3741 | temp &= ~FDI_TX_ENABLE; | |
3742 | I915_WRITE(reg, temp); | |
357555c0 | 3743 | |
139ccd3f JB |
3744 | reg = FDI_RX_CTL(pipe); |
3745 | temp = I915_READ(reg); | |
3746 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3747 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3748 | temp &= ~FDI_RX_ENABLE; | |
3749 | I915_WRITE(reg, temp); | |
357555c0 | 3750 | |
139ccd3f | 3751 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3752 | reg = FDI_TX_CTL(pipe); |
3753 | temp = I915_READ(reg); | |
139ccd3f | 3754 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3755 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3756 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3757 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3758 | temp |= snb_b_fdi_train_param[j/2]; |
3759 | temp |= FDI_COMPOSITE_SYNC; | |
3760 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3761 | |
139ccd3f JB |
3762 | I915_WRITE(FDI_RX_MISC(pipe), |
3763 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3764 | |
139ccd3f | 3765 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3766 | temp = I915_READ(reg); |
139ccd3f JB |
3767 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3768 | temp |= FDI_COMPOSITE_SYNC; | |
3769 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3770 | |
139ccd3f JB |
3771 | POSTING_READ(reg); |
3772 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3773 | |
139ccd3f JB |
3774 | for (i = 0; i < 4; i++) { |
3775 | reg = FDI_RX_IIR(pipe); | |
3776 | temp = I915_READ(reg); | |
3777 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3778 | |
139ccd3f JB |
3779 | if (temp & FDI_RX_BIT_LOCK || |
3780 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3781 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3782 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3783 | i); | |
3784 | break; | |
3785 | } | |
3786 | udelay(1); /* should be 0.5us */ | |
3787 | } | |
3788 | if (i == 4) { | |
3789 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3790 | continue; | |
3791 | } | |
357555c0 | 3792 | |
139ccd3f | 3793 | /* Train 2 */ |
357555c0 JB |
3794 | reg = FDI_TX_CTL(pipe); |
3795 | temp = I915_READ(reg); | |
139ccd3f JB |
3796 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3797 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3798 | I915_WRITE(reg, temp); | |
3799 | ||
3800 | reg = FDI_RX_CTL(pipe); | |
3801 | temp = I915_READ(reg); | |
3802 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3803 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3804 | I915_WRITE(reg, temp); |
3805 | ||
3806 | POSTING_READ(reg); | |
139ccd3f | 3807 | udelay(2); /* should be 1.5us */ |
357555c0 | 3808 | |
139ccd3f JB |
3809 | for (i = 0; i < 4; i++) { |
3810 | reg = FDI_RX_IIR(pipe); | |
3811 | temp = I915_READ(reg); | |
3812 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3813 | |
139ccd3f JB |
3814 | if (temp & FDI_RX_SYMBOL_LOCK || |
3815 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3816 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3817 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3818 | i); | |
3819 | goto train_done; | |
3820 | } | |
3821 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3822 | } |
139ccd3f JB |
3823 | if (i == 4) |
3824 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3825 | } |
357555c0 | 3826 | |
139ccd3f | 3827 | train_done: |
357555c0 JB |
3828 | DRM_DEBUG_KMS("FDI train done.\n"); |
3829 | } | |
3830 | ||
88cefb6c | 3831 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3832 | { |
88cefb6c | 3833 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3834 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3835 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3836 | i915_reg_t reg; |
3837 | u32 temp; | |
c64e311e | 3838 | |
c98e9dcf | 3839 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3840 | reg = FDI_RX_CTL(pipe); |
3841 | temp = I915_READ(reg); | |
627eb5a3 | 3842 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3843 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3844 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3845 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3846 | ||
3847 | POSTING_READ(reg); | |
c98e9dcf JB |
3848 | udelay(200); |
3849 | ||
3850 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3851 | temp = I915_READ(reg); |
3852 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3853 | ||
3854 | POSTING_READ(reg); | |
c98e9dcf JB |
3855 | udelay(200); |
3856 | ||
20749730 PZ |
3857 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3858 | reg = FDI_TX_CTL(pipe); | |
3859 | temp = I915_READ(reg); | |
3860 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3861 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3862 | |
20749730 PZ |
3863 | POSTING_READ(reg); |
3864 | udelay(100); | |
6be4a607 | 3865 | } |
0e23b99d JB |
3866 | } |
3867 | ||
88cefb6c DV |
3868 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3869 | { | |
3870 | struct drm_device *dev = intel_crtc->base.dev; | |
3871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3872 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3873 | i915_reg_t reg; |
3874 | u32 temp; | |
88cefb6c DV |
3875 | |
3876 | /* Switch from PCDclk to Rawclk */ | |
3877 | reg = FDI_RX_CTL(pipe); | |
3878 | temp = I915_READ(reg); | |
3879 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3880 | ||
3881 | /* Disable CPU FDI TX PLL */ | |
3882 | reg = FDI_TX_CTL(pipe); | |
3883 | temp = I915_READ(reg); | |
3884 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3885 | ||
3886 | POSTING_READ(reg); | |
3887 | udelay(100); | |
3888 | ||
3889 | reg = FDI_RX_CTL(pipe); | |
3890 | temp = I915_READ(reg); | |
3891 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3892 | ||
3893 | /* Wait for the clocks to turn off. */ | |
3894 | POSTING_READ(reg); | |
3895 | udelay(100); | |
3896 | } | |
3897 | ||
0fc932b8 JB |
3898 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3899 | { | |
3900 | struct drm_device *dev = crtc->dev; | |
3901 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3902 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3903 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3904 | i915_reg_t reg; |
3905 | u32 temp; | |
0fc932b8 JB |
3906 | |
3907 | /* disable CPU FDI tx and PCH FDI rx */ | |
3908 | reg = FDI_TX_CTL(pipe); | |
3909 | temp = I915_READ(reg); | |
3910 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3911 | POSTING_READ(reg); | |
3912 | ||
3913 | reg = FDI_RX_CTL(pipe); | |
3914 | temp = I915_READ(reg); | |
3915 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3916 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3917 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3918 | ||
3919 | POSTING_READ(reg); | |
3920 | udelay(100); | |
3921 | ||
3922 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3923 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3924 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3925 | |
3926 | /* still set train pattern 1 */ | |
3927 | reg = FDI_TX_CTL(pipe); | |
3928 | temp = I915_READ(reg); | |
3929 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3930 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3931 | I915_WRITE(reg, temp); | |
3932 | ||
3933 | reg = FDI_RX_CTL(pipe); | |
3934 | temp = I915_READ(reg); | |
3935 | if (HAS_PCH_CPT(dev)) { | |
3936 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3937 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3938 | } else { | |
3939 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3940 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3941 | } | |
3942 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3943 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3944 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3945 | I915_WRITE(reg, temp); |
3946 | ||
3947 | POSTING_READ(reg); | |
3948 | udelay(100); | |
3949 | } | |
3950 | ||
5dce5b93 CW |
3951 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3952 | { | |
3953 | struct intel_crtc *crtc; | |
3954 | ||
3955 | /* Note that we don't need to be called with mode_config.lock here | |
3956 | * as our list of CRTC objects is static for the lifetime of the | |
3957 | * device and so cannot disappear as we iterate. Similarly, we can | |
3958 | * happily treat the predicates as racy, atomic checks as userspace | |
3959 | * cannot claim and pin a new fb without at least acquring the | |
3960 | * struct_mutex and so serialising with us. | |
3961 | */ | |
d3fcc808 | 3962 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3963 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3964 | continue; | |
3965 | ||
3966 | if (crtc->unpin_work) | |
3967 | intel_wait_for_vblank(dev, crtc->pipe); | |
3968 | ||
3969 | return true; | |
3970 | } | |
3971 | ||
3972 | return false; | |
3973 | } | |
3974 | ||
d6bbafa1 CW |
3975 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3976 | { | |
3977 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3978 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3979 | ||
3980 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3981 | smp_rmb(); | |
3982 | intel_crtc->unpin_work = NULL; | |
3983 | ||
3984 | if (work->event) | |
3985 | drm_send_vblank_event(intel_crtc->base.dev, | |
3986 | intel_crtc->pipe, | |
3987 | work->event); | |
3988 | ||
3989 | drm_crtc_vblank_put(&intel_crtc->base); | |
3990 | ||
3991 | wake_up_all(&dev_priv->pending_flip_queue); | |
3992 | queue_work(dev_priv->wq, &work->work); | |
3993 | ||
3994 | trace_i915_flip_complete(intel_crtc->plane, | |
3995 | work->pending_flip_obj); | |
3996 | } | |
3997 | ||
5008e874 | 3998 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3999 | { |
0f91128d | 4000 | struct drm_device *dev = crtc->dev; |
5bb61643 | 4001 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 4002 | long ret; |
e6c3a2a6 | 4003 | |
2c10d571 | 4004 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4005 | |
4006 | ret = wait_event_interruptible_timeout( | |
4007 | dev_priv->pending_flip_queue, | |
4008 | !intel_crtc_has_pending_flip(crtc), | |
4009 | 60*HZ); | |
4010 | ||
4011 | if (ret < 0) | |
4012 | return ret; | |
4013 | ||
4014 | if (ret == 0) { | |
9c787942 | 4015 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 4016 | |
5e2d7afc | 4017 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
4018 | if (intel_crtc->unpin_work) { |
4019 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4020 | page_flip_completed(intel_crtc); | |
4021 | } | |
5e2d7afc | 4022 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 4023 | } |
5bb61643 | 4024 | |
5008e874 | 4025 | return 0; |
e6c3a2a6 CW |
4026 | } |
4027 | ||
060f02d8 VS |
4028 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
4029 | { | |
4030 | u32 temp; | |
4031 | ||
4032 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4033 | ||
4034 | mutex_lock(&dev_priv->sb_lock); | |
4035 | ||
4036 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4037 | temp |= SBI_SSCCTL_DISABLE; | |
4038 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4039 | ||
4040 | mutex_unlock(&dev_priv->sb_lock); | |
4041 | } | |
4042 | ||
e615efe4 ED |
4043 | /* Program iCLKIP clock to the desired frequency */ |
4044 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
4045 | { | |
64b46a06 | 4046 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 4047 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
4048 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4049 | u32 temp; | |
4050 | ||
060f02d8 | 4051 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4052 | |
64b46a06 VS |
4053 | /* The iCLK virtual clock root frequency is in MHz, |
4054 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4055 | * divisors, it is necessary to divide one by another, so we | |
4056 | * convert the virtual clock precision to KHz here for higher | |
4057 | * precision. | |
4058 | */ | |
4059 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4060 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4061 | u32 iclk_pi_range = 64; | |
64b46a06 | 4062 | u32 desired_divisor; |
e615efe4 | 4063 | |
64b46a06 VS |
4064 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4065 | clock << auxdiv); | |
4066 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4067 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4068 | |
64b46a06 VS |
4069 | /* |
4070 | * Near 20MHz is a corner case which is | |
4071 | * out of range for the 7-bit divisor | |
4072 | */ | |
4073 | if (divsel <= 0x7f) | |
4074 | break; | |
e615efe4 ED |
4075 | } |
4076 | ||
4077 | /* This should not happen with any sane values */ | |
4078 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4079 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4080 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4081 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4082 | ||
4083 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4084 | clock, |
e615efe4 ED |
4085 | auxdiv, |
4086 | divsel, | |
4087 | phasedir, | |
4088 | phaseinc); | |
4089 | ||
060f02d8 VS |
4090 | mutex_lock(&dev_priv->sb_lock); |
4091 | ||
e615efe4 | 4092 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4093 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4094 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4095 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4096 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4097 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4098 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4099 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4100 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4101 | |
4102 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4103 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4104 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4105 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4106 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4107 | |
4108 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4109 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4110 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4111 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4112 | |
060f02d8 VS |
4113 | mutex_unlock(&dev_priv->sb_lock); |
4114 | ||
e615efe4 ED |
4115 | /* Wait for initialization time */ |
4116 | udelay(24); | |
4117 | ||
4118 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4119 | } | |
4120 | ||
8802e5b6 VS |
4121 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4122 | { | |
4123 | u32 divsel, phaseinc, auxdiv; | |
4124 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4125 | u32 iclk_pi_range = 64; | |
4126 | u32 desired_divisor; | |
4127 | u32 temp; | |
4128 | ||
4129 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4130 | return 0; | |
4131 | ||
4132 | mutex_lock(&dev_priv->sb_lock); | |
4133 | ||
4134 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4135 | if (temp & SBI_SSCCTL_DISABLE) { | |
4136 | mutex_unlock(&dev_priv->sb_lock); | |
4137 | return 0; | |
4138 | } | |
4139 | ||
4140 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4141 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4142 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4143 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4144 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4145 | ||
4146 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4147 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4148 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4149 | ||
4150 | mutex_unlock(&dev_priv->sb_lock); | |
4151 | ||
4152 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4153 | ||
4154 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4155 | desired_divisor << auxdiv); | |
4156 | } | |
4157 | ||
275f01b2 DV |
4158 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4159 | enum pipe pch_transcoder) | |
4160 | { | |
4161 | struct drm_device *dev = crtc->base.dev; | |
4162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4163 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4164 | |
4165 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4166 | I915_READ(HTOTAL(cpu_transcoder))); | |
4167 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4168 | I915_READ(HBLANK(cpu_transcoder))); | |
4169 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4170 | I915_READ(HSYNC(cpu_transcoder))); | |
4171 | ||
4172 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4173 | I915_READ(VTOTAL(cpu_transcoder))); | |
4174 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4175 | I915_READ(VBLANK(cpu_transcoder))); | |
4176 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4177 | I915_READ(VSYNC(cpu_transcoder))); | |
4178 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4179 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4180 | } | |
4181 | ||
003632d9 | 4182 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4183 | { |
4184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4185 | uint32_t temp; | |
4186 | ||
4187 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4188 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4189 | return; |
4190 | ||
4191 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4192 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4193 | ||
003632d9 ACO |
4194 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4195 | if (enable) | |
4196 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4197 | ||
4198 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4199 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4200 | POSTING_READ(SOUTH_CHICKEN1); | |
4201 | } | |
4202 | ||
4203 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4204 | { | |
4205 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4206 | |
4207 | switch (intel_crtc->pipe) { | |
4208 | case PIPE_A: | |
4209 | break; | |
4210 | case PIPE_B: | |
6e3c9717 | 4211 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4212 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4213 | else |
003632d9 | 4214 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4215 | |
4216 | break; | |
4217 | case PIPE_C: | |
003632d9 | 4218 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4219 | |
4220 | break; | |
4221 | default: | |
4222 | BUG(); | |
4223 | } | |
4224 | } | |
4225 | ||
c48b5305 VS |
4226 | /* Return which DP Port should be selected for Transcoder DP control */ |
4227 | static enum port | |
4228 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4229 | { | |
4230 | struct drm_device *dev = crtc->dev; | |
4231 | struct intel_encoder *encoder; | |
4232 | ||
4233 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4234 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4235 | encoder->type == INTEL_OUTPUT_EDP) | |
4236 | return enc_to_dig_port(&encoder->base)->port; | |
4237 | } | |
4238 | ||
4239 | return -1; | |
4240 | } | |
4241 | ||
f67a559d JB |
4242 | /* |
4243 | * Enable PCH resources required for PCH ports: | |
4244 | * - PCH PLLs | |
4245 | * - FDI training & RX/TX | |
4246 | * - update transcoder timings | |
4247 | * - DP transcoding bits | |
4248 | * - transcoder | |
4249 | */ | |
4250 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4251 | { |
4252 | struct drm_device *dev = crtc->dev; | |
4253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4255 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4256 | u32 temp; |
2c07245f | 4257 | |
ab9412ba | 4258 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4259 | |
1fbc0d78 DV |
4260 | if (IS_IVYBRIDGE(dev)) |
4261 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4262 | ||
cd986abb DV |
4263 | /* Write the TU size bits before fdi link training, so that error |
4264 | * detection works. */ | |
4265 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4266 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4267 | ||
3860b2ec VS |
4268 | /* |
4269 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4270 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4271 | */ | |
4272 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4273 | ||
c98e9dcf | 4274 | /* For PCH output, training FDI link */ |
674cf967 | 4275 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4276 | |
3ad8a208 DV |
4277 | /* We need to program the right clock selection before writing the pixel |
4278 | * mutliplier into the DPLL. */ | |
303b81e0 | 4279 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4280 | u32 sel; |
4b645f14 | 4281 | |
c98e9dcf | 4282 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4283 | temp |= TRANS_DPLL_ENABLE(pipe); |
4284 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4285 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4286 | temp |= sel; |
4287 | else | |
4288 | temp &= ~sel; | |
c98e9dcf | 4289 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4290 | } |
5eddb70b | 4291 | |
3ad8a208 DV |
4292 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4293 | * transcoder, and we actually should do this to not upset any PCH | |
4294 | * transcoder that already use the clock when we share it. | |
4295 | * | |
4296 | * Note that enable_shared_dpll tries to do the right thing, but | |
4297 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4298 | * the right LVDS enable sequence. */ | |
85b3894f | 4299 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4300 | |
d9b6cb56 JB |
4301 | /* set transcoder timing, panel must allow it */ |
4302 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4303 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4304 | |
303b81e0 | 4305 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4306 | |
3860b2ec VS |
4307 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4308 | ||
c98e9dcf | 4309 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4310 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4311 | const struct drm_display_mode *adjusted_mode = |
4312 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4313 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4314 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4315 | temp = I915_READ(reg); |
4316 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4317 | TRANS_DP_SYNC_MASK | |
4318 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4319 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4320 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4321 | |
9c4edaee | 4322 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4323 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4324 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4325 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4326 | |
4327 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4328 | case PORT_B: |
5eddb70b | 4329 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4330 | break; |
c48b5305 | 4331 | case PORT_C: |
5eddb70b | 4332 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4333 | break; |
c48b5305 | 4334 | case PORT_D: |
5eddb70b | 4335 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4336 | break; |
4337 | default: | |
e95d41e1 | 4338 | BUG(); |
32f9d658 | 4339 | } |
2c07245f | 4340 | |
5eddb70b | 4341 | I915_WRITE(reg, temp); |
6be4a607 | 4342 | } |
b52eb4dc | 4343 | |
b8a4f404 | 4344 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4345 | } |
4346 | ||
1507e5bd PZ |
4347 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4348 | { | |
4349 | struct drm_device *dev = crtc->dev; | |
4350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4351 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4352 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4353 | |
ab9412ba | 4354 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4355 | |
8c52b5e8 | 4356 | lpt_program_iclkip(crtc); |
1507e5bd | 4357 | |
0540e488 | 4358 | /* Set transcoder timing. */ |
275f01b2 | 4359 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4360 | |
937bb610 | 4361 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4362 | } |
4363 | ||
190f68c5 ACO |
4364 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4365 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4366 | { |
e2b78267 | 4367 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4368 | struct intel_shared_dpll *pll; |
de419ab6 | 4369 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4370 | enum intel_dpll_id i; |
00490c22 | 4371 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4372 | |
de419ab6 ML |
4373 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4374 | ||
98b6bd99 DV |
4375 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4376 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4377 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4378 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4379 | |
46edb027 DV |
4380 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4381 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4382 | |
de419ab6 | 4383 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4384 | |
98b6bd99 DV |
4385 | goto found; |
4386 | } | |
4387 | ||
bcddf610 S |
4388 | if (IS_BROXTON(dev_priv->dev)) { |
4389 | /* PLL is attached to port in bxt */ | |
4390 | struct intel_encoder *encoder; | |
4391 | struct intel_digital_port *intel_dig_port; | |
4392 | ||
4393 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4394 | if (WARN_ON(!encoder)) | |
4395 | return NULL; | |
4396 | ||
4397 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4398 | /* 1:1 mapping between ports and PLLs */ | |
4399 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4400 | pll = &dev_priv->shared_dplls[i]; | |
4401 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4402 | crtc->base.base.id, pll->name); | |
de419ab6 | 4403 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4404 | |
4405 | goto found; | |
00490c22 ML |
4406 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4407 | /* Do not consider SPLL */ | |
4408 | max = 2; | |
bcddf610 | 4409 | |
00490c22 | 4410 | for (i = 0; i < max; i++) { |
e72f9fbf | 4411 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4412 | |
4413 | /* Only want to check enabled timings first */ | |
de419ab6 | 4414 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4415 | continue; |
4416 | ||
190f68c5 | 4417 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4418 | &shared_dpll[i].hw_state, |
4419 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4420 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4421 | crtc->base.base.id, pll->name, |
de419ab6 | 4422 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4423 | pll->active); |
ee7b9f93 JB |
4424 | goto found; |
4425 | } | |
4426 | } | |
4427 | ||
4428 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4429 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4430 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4431 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4432 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4433 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4434 | goto found; |
4435 | } | |
4436 | } | |
4437 | ||
4438 | return NULL; | |
4439 | ||
4440 | found: | |
de419ab6 ML |
4441 | if (shared_dpll[i].crtc_mask == 0) |
4442 | shared_dpll[i].hw_state = | |
4443 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4444 | |
190f68c5 | 4445 | crtc_state->shared_dpll = i; |
46edb027 DV |
4446 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4447 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4448 | |
de419ab6 | 4449 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4450 | |
ee7b9f93 JB |
4451 | return pll; |
4452 | } | |
4453 | ||
de419ab6 | 4454 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4455 | { |
de419ab6 ML |
4456 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4457 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4458 | struct intel_shared_dpll *pll; |
4459 | enum intel_dpll_id i; | |
4460 | ||
de419ab6 ML |
4461 | if (!to_intel_atomic_state(state)->dpll_set) |
4462 | return; | |
8bd31e67 | 4463 | |
de419ab6 | 4464 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4465 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4466 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4467 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4468 | } |
4469 | } | |
4470 | ||
a1520318 | 4471 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4472 | { |
4473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4474 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4475 | u32 temp; |
4476 | ||
4477 | temp = I915_READ(dslreg); | |
4478 | udelay(500); | |
4479 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4480 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4481 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4482 | } |
4483 | } | |
4484 | ||
86adf9d7 ML |
4485 | static int |
4486 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4487 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4488 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4489 | { |
86adf9d7 ML |
4490 | struct intel_crtc_scaler_state *scaler_state = |
4491 | &crtc_state->scaler_state; | |
4492 | struct intel_crtc *intel_crtc = | |
4493 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4494 | int need_scaling; |
6156a456 CK |
4495 | |
4496 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4497 | (src_h != dst_w || src_w != dst_h): | |
4498 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4499 | |
4500 | /* | |
4501 | * if plane is being disabled or scaler is no more required or force detach | |
4502 | * - free scaler binded to this plane/crtc | |
4503 | * - in order to do this, update crtc->scaler_usage | |
4504 | * | |
4505 | * Here scaler state in crtc_state is set free so that | |
4506 | * scaler can be assigned to other user. Actual register | |
4507 | * update to free the scaler is done in plane/panel-fit programming. | |
4508 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4509 | */ | |
86adf9d7 | 4510 | if (force_detach || !need_scaling) { |
a1b2278e | 4511 | if (*scaler_id >= 0) { |
86adf9d7 | 4512 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4513 | scaler_state->scalers[*scaler_id].in_use = 0; |
4514 | ||
86adf9d7 ML |
4515 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4516 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4517 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4518 | scaler_state->scaler_users); |
4519 | *scaler_id = -1; | |
4520 | } | |
4521 | return 0; | |
4522 | } | |
4523 | ||
4524 | /* range checks */ | |
4525 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4526 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4527 | ||
4528 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4529 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4530 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4531 | "size is out of scaler range\n", |
86adf9d7 | 4532 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4533 | return -EINVAL; |
4534 | } | |
4535 | ||
86adf9d7 ML |
4536 | /* mark this plane as a scaler user in crtc_state */ |
4537 | scaler_state->scaler_users |= (1 << scaler_user); | |
4538 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4539 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4540 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4541 | scaler_state->scaler_users); | |
4542 | ||
4543 | return 0; | |
4544 | } | |
4545 | ||
4546 | /** | |
4547 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4548 | * | |
4549 | * @state: crtc's scaler state | |
86adf9d7 ML |
4550 | * |
4551 | * Return | |
4552 | * 0 - scaler_usage updated successfully | |
4553 | * error - requested scaling cannot be supported or other error condition | |
4554 | */ | |
e435d6e5 | 4555 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4556 | { |
4557 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4558 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4559 | |
4560 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4561 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4562 | ||
e435d6e5 | 4563 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4564 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4565 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4566 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4567 | } |
4568 | ||
4569 | /** | |
4570 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4571 | * | |
4572 | * @state: crtc's scaler state | |
86adf9d7 ML |
4573 | * @plane_state: atomic plane state to update |
4574 | * | |
4575 | * Return | |
4576 | * 0 - scaler_usage updated successfully | |
4577 | * error - requested scaling cannot be supported or other error condition | |
4578 | */ | |
da20eabd ML |
4579 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4580 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4581 | { |
4582 | ||
4583 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4584 | struct intel_plane *intel_plane = |
4585 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4586 | struct drm_framebuffer *fb = plane_state->base.fb; |
4587 | int ret; | |
4588 | ||
4589 | bool force_detach = !fb || !plane_state->visible; | |
4590 | ||
4591 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4592 | intel_plane->base.base.id, intel_crtc->pipe, | |
4593 | drm_plane_index(&intel_plane->base)); | |
4594 | ||
4595 | ret = skl_update_scaler(crtc_state, force_detach, | |
4596 | drm_plane_index(&intel_plane->base), | |
4597 | &plane_state->scaler_id, | |
4598 | plane_state->base.rotation, | |
4599 | drm_rect_width(&plane_state->src) >> 16, | |
4600 | drm_rect_height(&plane_state->src) >> 16, | |
4601 | drm_rect_width(&plane_state->dst), | |
4602 | drm_rect_height(&plane_state->dst)); | |
4603 | ||
4604 | if (ret || plane_state->scaler_id < 0) | |
4605 | return ret; | |
4606 | ||
a1b2278e | 4607 | /* check colorkey */ |
818ed961 | 4608 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4609 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4610 | intel_plane->base.base.id); |
a1b2278e CK |
4611 | return -EINVAL; |
4612 | } | |
4613 | ||
4614 | /* Check src format */ | |
86adf9d7 ML |
4615 | switch (fb->pixel_format) { |
4616 | case DRM_FORMAT_RGB565: | |
4617 | case DRM_FORMAT_XBGR8888: | |
4618 | case DRM_FORMAT_XRGB8888: | |
4619 | case DRM_FORMAT_ABGR8888: | |
4620 | case DRM_FORMAT_ARGB8888: | |
4621 | case DRM_FORMAT_XRGB2101010: | |
4622 | case DRM_FORMAT_XBGR2101010: | |
4623 | case DRM_FORMAT_YUYV: | |
4624 | case DRM_FORMAT_YVYU: | |
4625 | case DRM_FORMAT_UYVY: | |
4626 | case DRM_FORMAT_VYUY: | |
4627 | break; | |
4628 | default: | |
4629 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4630 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4631 | return -EINVAL; | |
a1b2278e CK |
4632 | } |
4633 | ||
a1b2278e CK |
4634 | return 0; |
4635 | } | |
4636 | ||
e435d6e5 ML |
4637 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4638 | { | |
4639 | int i; | |
4640 | ||
4641 | for (i = 0; i < crtc->num_scalers; i++) | |
4642 | skl_detach_scaler(crtc, i); | |
4643 | } | |
4644 | ||
4645 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4646 | { |
4647 | struct drm_device *dev = crtc->base.dev; | |
4648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4649 | int pipe = crtc->pipe; | |
a1b2278e CK |
4650 | struct intel_crtc_scaler_state *scaler_state = |
4651 | &crtc->config->scaler_state; | |
4652 | ||
4653 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4654 | ||
6e3c9717 | 4655 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4656 | int id; |
4657 | ||
4658 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4659 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4660 | return; | |
4661 | } | |
4662 | ||
4663 | id = scaler_state->scaler_id; | |
4664 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4665 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4666 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4667 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4668 | ||
4669 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4670 | } |
4671 | } | |
4672 | ||
b074cec8 JB |
4673 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4674 | { | |
4675 | struct drm_device *dev = crtc->base.dev; | |
4676 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4677 | int pipe = crtc->pipe; | |
4678 | ||
6e3c9717 | 4679 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4680 | /* Force use of hard-coded filter coefficients |
4681 | * as some pre-programmed values are broken, | |
4682 | * e.g. x201. | |
4683 | */ | |
4684 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4685 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4686 | PF_PIPE_SEL_IVB(pipe)); | |
4687 | else | |
4688 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4689 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4690 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4691 | } |
4692 | } | |
4693 | ||
20bc8673 | 4694 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4695 | { |
cea165c3 VS |
4696 | struct drm_device *dev = crtc->base.dev; |
4697 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4698 | |
6e3c9717 | 4699 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4700 | return; |
4701 | ||
cea165c3 VS |
4702 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4703 | intel_wait_for_vblank(dev, crtc->pipe); | |
4704 | ||
d77e4531 | 4705 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4706 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4707 | mutex_lock(&dev_priv->rps.hw_lock); |
4708 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4709 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4710 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4711 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4712 | * mailbox." Moreover, the mailbox may return a bogus state, |
4713 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4714 | */ |
4715 | } else { | |
4716 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4717 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4718 | * is essentially intel_wait_for_vblank. If we don't have this | |
4719 | * and don't wait for vblanks until the end of crtc_enable, then | |
4720 | * the HW state readout code will complain that the expected | |
4721 | * IPS_CTL value is not the one we read. */ | |
4722 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4723 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4724 | } | |
d77e4531 PZ |
4725 | } |
4726 | ||
20bc8673 | 4727 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4728 | { |
4729 | struct drm_device *dev = crtc->base.dev; | |
4730 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4731 | ||
6e3c9717 | 4732 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4733 | return; |
4734 | ||
4735 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4736 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4737 | mutex_lock(&dev_priv->rps.hw_lock); |
4738 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4739 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4740 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4741 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4742 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4743 | } else { |
2a114cc1 | 4744 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4745 | POSTING_READ(IPS_CTL); |
4746 | } | |
d77e4531 PZ |
4747 | |
4748 | /* We need to wait for a vblank before we can disable the plane. */ | |
4749 | intel_wait_for_vblank(dev, crtc->pipe); | |
4750 | } | |
4751 | ||
4752 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4753 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4754 | { | |
4755 | struct drm_device *dev = crtc->dev; | |
4756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4757 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4758 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4759 | int i; |
4760 | bool reenable_ips = false; | |
4761 | ||
4762 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4763 | if (!crtc->state->active) |
d77e4531 PZ |
4764 | return; |
4765 | ||
50360403 | 4766 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4767 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4768 | assert_dsi_pll_enabled(dev_priv); |
4769 | else | |
4770 | assert_pll_enabled(dev_priv, pipe); | |
4771 | } | |
4772 | ||
d77e4531 PZ |
4773 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4774 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4775 | */ | |
6e3c9717 | 4776 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4777 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4778 | GAMMA_MODE_MODE_SPLIT)) { | |
4779 | hsw_disable_ips(intel_crtc); | |
4780 | reenable_ips = true; | |
4781 | } | |
4782 | ||
4783 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4784 | i915_reg_t palreg; |
f65a9c5b VS |
4785 | |
4786 | if (HAS_GMCH_DISPLAY(dev)) | |
4787 | palreg = PALETTE(pipe, i); | |
4788 | else | |
4789 | palreg = LGC_PALETTE(pipe, i); | |
4790 | ||
4791 | I915_WRITE(palreg, | |
d77e4531 PZ |
4792 | (intel_crtc->lut_r[i] << 16) | |
4793 | (intel_crtc->lut_g[i] << 8) | | |
4794 | intel_crtc->lut_b[i]); | |
4795 | } | |
4796 | ||
4797 | if (reenable_ips) | |
4798 | hsw_enable_ips(intel_crtc); | |
4799 | } | |
4800 | ||
7cac945f | 4801 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4802 | { |
7cac945f | 4803 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4804 | struct drm_device *dev = intel_crtc->base.dev; |
4805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4806 | ||
4807 | mutex_lock(&dev->struct_mutex); | |
4808 | dev_priv->mm.interruptible = false; | |
4809 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4810 | dev_priv->mm.interruptible = true; | |
4811 | mutex_unlock(&dev->struct_mutex); | |
4812 | } | |
4813 | ||
4814 | /* Let userspace switch the overlay on again. In most cases userspace | |
4815 | * has to recompute where to put it anyway. | |
4816 | */ | |
4817 | } | |
4818 | ||
87d4300a ML |
4819 | /** |
4820 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4821 | * @crtc: the CRTC whose primary plane was just enabled | |
4822 | * | |
4823 | * Performs potentially sleeping operations that must be done after the primary | |
4824 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4825 | * called due to an explicit primary plane update, or due to an implicit | |
4826 | * re-enable that is caused when a sprite plane is updated to no longer | |
4827 | * completely hide the primary plane. | |
4828 | */ | |
4829 | static void | |
4830 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4831 | { |
4832 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4833 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4834 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4835 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4836 | |
87d4300a ML |
4837 | /* |
4838 | * FIXME IPS should be fine as long as one plane is | |
4839 | * enabled, but in practice it seems to have problems | |
4840 | * when going from primary only to sprite only and vice | |
4841 | * versa. | |
4842 | */ | |
a5c4d7bc VS |
4843 | hsw_enable_ips(intel_crtc); |
4844 | ||
f99d7069 | 4845 | /* |
87d4300a ML |
4846 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4847 | * So don't enable underrun reporting before at least some planes | |
4848 | * are enabled. | |
4849 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4850 | * but leave the pipe running. | |
f99d7069 | 4851 | */ |
87d4300a ML |
4852 | if (IS_GEN2(dev)) |
4853 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4854 | ||
aca7b684 VS |
4855 | /* Underruns don't always raise interrupts, so check manually. */ |
4856 | intel_check_cpu_fifo_underruns(dev_priv); | |
4857 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4858 | } |
4859 | ||
87d4300a ML |
4860 | /** |
4861 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4862 | * @crtc: the CRTC whose primary plane is to be disabled | |
4863 | * | |
4864 | * Performs potentially sleeping operations that must be done before the | |
4865 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4866 | * be called due to an explicit primary plane update, or due to an implicit | |
4867 | * disable that is caused when a sprite plane completely hides the primary | |
4868 | * plane. | |
4869 | */ | |
4870 | static void | |
4871 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4872 | { |
4873 | struct drm_device *dev = crtc->dev; | |
4874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4875 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4876 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4877 | |
87d4300a ML |
4878 | /* |
4879 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4880 | * So diasble underrun reporting before all the planes get disabled. | |
4881 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4882 | * but leave the pipe running. | |
4883 | */ | |
4884 | if (IS_GEN2(dev)) | |
4885 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4886 | |
87d4300a ML |
4887 | /* |
4888 | * Vblank time updates from the shadow to live plane control register | |
4889 | * are blocked if the memory self-refresh mode is active at that | |
4890 | * moment. So to make sure the plane gets truly disabled, disable | |
4891 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4892 | * will be checked/applied by the HW only at the next frame start | |
4893 | * event which is after the vblank start event, so we need to have a | |
4894 | * wait-for-vblank between disabling the plane and the pipe. | |
4895 | */ | |
262cd2e1 | 4896 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4897 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4898 | dev_priv->wm.vlv.cxsr = false; |
4899 | intel_wait_for_vblank(dev, pipe); | |
4900 | } | |
87d4300a | 4901 | |
87d4300a ML |
4902 | /* |
4903 | * FIXME IPS should be fine as long as one plane is | |
4904 | * enabled, but in practice it seems to have problems | |
4905 | * when going from primary only to sprite only and vice | |
4906 | * versa. | |
4907 | */ | |
a5c4d7bc | 4908 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4909 | } |
4910 | ||
ac21b225 ML |
4911 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4912 | { | |
4913 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4914 | struct intel_crtc_state *pipe_config = |
4915 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4916 | struct drm_device *dev = crtc->base.dev; |
ac21b225 | 4917 | |
ac21b225 ML |
4918 | intel_frontbuffer_flip(dev, atomic->fb_bits); |
4919 | ||
ab1d3a0e | 4920 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4921 | |
b9001114 | 4922 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4923 | intel_update_watermarks(&crtc->base); |
4924 | ||
c80ac854 | 4925 | if (atomic->update_fbc) |
1eb52238 | 4926 | intel_fbc_post_update(crtc); |
ac21b225 ML |
4927 | |
4928 | if (atomic->post_enable_primary) | |
4929 | intel_post_enable_primary(&crtc->base); | |
4930 | ||
ac21b225 ML |
4931 | memset(atomic, 0, sizeof(*atomic)); |
4932 | } | |
4933 | ||
5c74cd73 | 4934 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4935 | { |
5c74cd73 | 4936 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4937 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4938 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4939 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4940 | struct intel_crtc_state *pipe_config = |
4941 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4942 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4943 | struct drm_plane *primary = crtc->base.primary; | |
4944 | struct drm_plane_state *old_pri_state = | |
4945 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4946 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4947 | |
1eb52238 PZ |
4948 | if (atomic->update_fbc) |
4949 | intel_fbc_pre_update(crtc); | |
ac21b225 | 4950 | |
5c74cd73 ML |
4951 | if (old_pri_state) { |
4952 | struct intel_plane_state *primary_state = | |
4953 | to_intel_plane_state(primary->state); | |
4954 | struct intel_plane_state *old_primary_state = | |
4955 | to_intel_plane_state(old_pri_state); | |
4956 | ||
4957 | if (old_primary_state->visible && | |
4958 | (modeset || !primary_state->visible)) | |
4959 | intel_pre_disable_primary(&crtc->base); | |
4960 | } | |
852eb00d | 4961 | |
ab1d3a0e | 4962 | if (pipe_config->disable_cxsr) { |
852eb00d | 4963 | crtc->wm.cxsr_allowed = false; |
2dfd178d ML |
4964 | |
4965 | if (old_crtc_state->base.active) | |
4966 | intel_set_memory_cxsr(dev_priv, false); | |
852eb00d | 4967 | } |
92826fcd | 4968 | |
ed4a6a7c MR |
4969 | /* |
4970 | * IVB workaround: must disable low power watermarks for at least | |
4971 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4972 | * when scaling is disabled. | |
4973 | * | |
4974 | * WaCxSRDisabledForSpriteScaling:ivb | |
4975 | */ | |
4976 | if (pipe_config->disable_lp_wm) { | |
4977 | ilk_disable_lp_wm(dev); | |
4978 | intel_wait_for_vblank(dev, crtc->pipe); | |
4979 | } | |
4980 | ||
4981 | /* | |
4982 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4983 | * watermark programming here. | |
4984 | */ | |
4985 | if (needs_modeset(&pipe_config->base)) | |
4986 | return; | |
4987 | ||
4988 | /* | |
4989 | * For platforms that support atomic watermarks, program the | |
4990 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4991 | * will be the intermediate values that are safe for both pre- and | |
4992 | * post- vblank; when vblank happens, the 'active' values will be set | |
4993 | * to the final 'target' values and we'll do this again to get the | |
4994 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4995 | * will be the final target values which will get automatically latched | |
4996 | * at vblank time; no further programming will be necessary. | |
4997 | * | |
4998 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4999 | * we'll continue to update watermarks the old way, if flags tell | |
5000 | * us to. | |
5001 | */ | |
5002 | if (dev_priv->display.initial_watermarks != NULL) | |
5003 | dev_priv->display.initial_watermarks(pipe_config); | |
5004 | else if (pipe_config->wm_changed) | |
92826fcd | 5005 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
5006 | } |
5007 | ||
d032ffa0 | 5008 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5009 | { |
5010 | struct drm_device *dev = crtc->dev; | |
5011 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5012 | struct drm_plane *p; |
87d4300a ML |
5013 | int pipe = intel_crtc->pipe; |
5014 | ||
7cac945f | 5015 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5016 | |
d032ffa0 ML |
5017 | drm_for_each_plane_mask(p, dev, plane_mask) |
5018 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5019 | |
f99d7069 DV |
5020 | /* |
5021 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5022 | * to compute the mask of flip planes precisely. For the time being | |
5023 | * consider this a flip to a NULL plane. | |
5024 | */ | |
5025 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
5026 | } |
5027 | ||
f67a559d JB |
5028 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
5029 | { | |
5030 | struct drm_device *dev = crtc->dev; | |
5031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5032 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5033 | struct intel_encoder *encoder; |
f67a559d | 5034 | int pipe = intel_crtc->pipe; |
f67a559d | 5035 | |
53d9f4e9 | 5036 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5037 | return; |
5038 | ||
81b088ca VS |
5039 | if (intel_crtc->config->has_pch_encoder) |
5040 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5041 | ||
6e3c9717 | 5042 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5043 | intel_prepare_shared_dpll(intel_crtc); |
5044 | ||
6e3c9717 | 5045 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5046 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5047 | |
5048 | intel_set_pipe_timings(intel_crtc); | |
5049 | ||
6e3c9717 | 5050 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5051 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5052 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5053 | } |
5054 | ||
5055 | ironlake_set_pipeconf(crtc); | |
5056 | ||
f67a559d | 5057 | intel_crtc->active = true; |
8664281b | 5058 | |
a72e4c9f | 5059 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 5060 | |
f6736a1a | 5061 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
5062 | if (encoder->pre_enable) |
5063 | encoder->pre_enable(encoder); | |
f67a559d | 5064 | |
6e3c9717 | 5065 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5066 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5067 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5068 | * enabling. */ | |
88cefb6c | 5069 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5070 | } else { |
5071 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5072 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5073 | } | |
f67a559d | 5074 | |
b074cec8 | 5075 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5076 | |
9c54c0dd JB |
5077 | /* |
5078 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5079 | * clocks enabled | |
5080 | */ | |
5081 | intel_crtc_load_lut(crtc); | |
5082 | ||
1d5bf5d9 ID |
5083 | if (dev_priv->display.initial_watermarks != NULL) |
5084 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 5085 | intel_enable_pipe(intel_crtc); |
f67a559d | 5086 | |
6e3c9717 | 5087 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 5088 | ironlake_pch_enable(crtc); |
c98e9dcf | 5089 | |
f9b61ff6 DV |
5090 | assert_vblank_disabled(crtc); |
5091 | drm_crtc_vblank_on(crtc); | |
5092 | ||
fa5c73b1 DV |
5093 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5094 | encoder->enable(encoder); | |
61b77ddd DV |
5095 | |
5096 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 5097 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5098 | |
5099 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5100 | if (intel_crtc->config->has_pch_encoder) | |
5101 | intel_wait_for_vblank(dev, pipe); | |
5102 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 JB |
5103 | } |
5104 | ||
42db64ef PZ |
5105 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5106 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5107 | { | |
f5adf94e | 5108 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5109 | } |
5110 | ||
4f771f10 PZ |
5111 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
5112 | { | |
5113 | struct drm_device *dev = crtc->dev; | |
5114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5115 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5116 | struct intel_encoder *encoder; | |
99d736a2 ML |
5117 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
5118 | struct intel_crtc_state *pipe_config = | |
5119 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 5120 | |
53d9f4e9 | 5121 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5122 | return; |
5123 | ||
81b088ca VS |
5124 | if (intel_crtc->config->has_pch_encoder) |
5125 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5126 | false); | |
5127 | ||
df8ad70c DV |
5128 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
5129 | intel_enable_shared_dpll(intel_crtc); | |
5130 | ||
6e3c9717 | 5131 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5132 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
5133 | |
5134 | intel_set_pipe_timings(intel_crtc); | |
5135 | ||
6e3c9717 ACO |
5136 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
5137 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
5138 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
5139 | } |
5140 | ||
6e3c9717 | 5141 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5142 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5143 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5144 | } |
5145 | ||
5146 | haswell_set_pipeconf(crtc); | |
5147 | ||
5148 | intel_set_pipe_csc(crtc); | |
5149 | ||
4f771f10 | 5150 | intel_crtc->active = true; |
8664281b | 5151 | |
6b698516 DV |
5152 | if (intel_crtc->config->has_pch_encoder) |
5153 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5154 | else | |
5155 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5156 | ||
7d4aefd0 | 5157 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
5158 | if (encoder->pre_enable) |
5159 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5160 | } |
4f771f10 | 5161 | |
d2d65408 | 5162 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5163 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5164 | |
a65347ba | 5165 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5166 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5167 | |
1c132b44 | 5168 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5169 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5170 | else |
1c132b44 | 5171 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5172 | |
5173 | /* | |
5174 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5175 | * clocks enabled | |
5176 | */ | |
5177 | intel_crtc_load_lut(crtc); | |
5178 | ||
1f544388 | 5179 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5180 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5181 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5182 | |
1d5bf5d9 ID |
5183 | if (dev_priv->display.initial_watermarks != NULL) |
5184 | dev_priv->display.initial_watermarks(pipe_config); | |
5185 | else | |
5186 | intel_update_watermarks(crtc); | |
e1fdc473 | 5187 | intel_enable_pipe(intel_crtc); |
42db64ef | 5188 | |
6e3c9717 | 5189 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5190 | lpt_pch_enable(crtc); |
4f771f10 | 5191 | |
a65347ba | 5192 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5193 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5194 | ||
f9b61ff6 DV |
5195 | assert_vblank_disabled(crtc); |
5196 | drm_crtc_vblank_on(crtc); | |
5197 | ||
8807e55b | 5198 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5199 | encoder->enable(encoder); |
8807e55b JN |
5200 | intel_opregion_notify_encoder(encoder, true); |
5201 | } | |
4f771f10 | 5202 | |
6b698516 DV |
5203 | if (intel_crtc->config->has_pch_encoder) { |
5204 | intel_wait_for_vblank(dev, pipe); | |
5205 | intel_wait_for_vblank(dev, pipe); | |
5206 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5207 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5208 | true); | |
6b698516 | 5209 | } |
d2d65408 | 5210 | |
e4916946 PZ |
5211 | /* If we change the relative order between pipe/planes enabling, we need |
5212 | * to change the workaround. */ | |
99d736a2 ML |
5213 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5214 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5215 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5216 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5217 | } | |
4f771f10 PZ |
5218 | } |
5219 | ||
bfd16b2a | 5220 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5221 | { |
5222 | struct drm_device *dev = crtc->base.dev; | |
5223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5224 | int pipe = crtc->pipe; | |
5225 | ||
5226 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5227 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5228 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5229 | I915_WRITE(PF_CTL(pipe), 0); |
5230 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5231 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5232 | } | |
5233 | } | |
5234 | ||
6be4a607 JB |
5235 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5236 | { | |
5237 | struct drm_device *dev = crtc->dev; | |
5238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5239 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5240 | struct intel_encoder *encoder; |
6be4a607 | 5241 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5242 | |
37ca8d4c VS |
5243 | if (intel_crtc->config->has_pch_encoder) |
5244 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5245 | ||
ea9d758d DV |
5246 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5247 | encoder->disable(encoder); | |
5248 | ||
f9b61ff6 DV |
5249 | drm_crtc_vblank_off(crtc); |
5250 | assert_vblank_disabled(crtc); | |
5251 | ||
3860b2ec VS |
5252 | /* |
5253 | * Sometimes spurious CPU pipe underruns happen when the | |
5254 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5255 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5256 | */ | |
5257 | if (intel_crtc->config->has_pch_encoder) | |
5258 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5259 | ||
575f7ab7 | 5260 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5261 | |
bfd16b2a | 5262 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5263 | |
3860b2ec | 5264 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5265 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5266 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5267 | } | |
5a74f70a | 5268 | |
bf49ec8c DV |
5269 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5270 | if (encoder->post_disable) | |
5271 | encoder->post_disable(encoder); | |
2c07245f | 5272 | |
6e3c9717 | 5273 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5274 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5275 | |
d925c59a | 5276 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5277 | i915_reg_t reg; |
5278 | u32 temp; | |
5279 | ||
d925c59a DV |
5280 | /* disable TRANS_DP_CTL */ |
5281 | reg = TRANS_DP_CTL(pipe); | |
5282 | temp = I915_READ(reg); | |
5283 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5284 | TRANS_DP_PORT_SEL_MASK); | |
5285 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5286 | I915_WRITE(reg, temp); | |
5287 | ||
5288 | /* disable DPLL_SEL */ | |
5289 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5290 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5291 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5292 | } |
e3421a18 | 5293 | |
d925c59a DV |
5294 | ironlake_fdi_pll_disable(intel_crtc); |
5295 | } | |
81b088ca VS |
5296 | |
5297 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 | 5298 | } |
1b3c7a47 | 5299 | |
4f771f10 | 5300 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5301 | { |
4f771f10 PZ |
5302 | struct drm_device *dev = crtc->dev; |
5303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5304 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5305 | struct intel_encoder *encoder; |
6e3c9717 | 5306 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5307 | |
d2d65408 VS |
5308 | if (intel_crtc->config->has_pch_encoder) |
5309 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5310 | false); | |
5311 | ||
8807e55b JN |
5312 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5313 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5314 | encoder->disable(encoder); |
8807e55b | 5315 | } |
4f771f10 | 5316 | |
f9b61ff6 DV |
5317 | drm_crtc_vblank_off(crtc); |
5318 | assert_vblank_disabled(crtc); | |
5319 | ||
575f7ab7 | 5320 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5321 | |
6e3c9717 | 5322 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5323 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5324 | ||
a65347ba | 5325 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5326 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5327 | |
1c132b44 | 5328 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5329 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5330 | else |
bfd16b2a | 5331 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5332 | |
a65347ba | 5333 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5334 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5335 | |
97b040aa ID |
5336 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5337 | if (encoder->post_disable) | |
5338 | encoder->post_disable(encoder); | |
81b088ca | 5339 | |
92966a37 VS |
5340 | if (intel_crtc->config->has_pch_encoder) { |
5341 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5342 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5343 | intel_ddi_fdi_disable(crtc); |
5344 | ||
81b088ca VS |
5345 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5346 | true); | |
92966a37 | 5347 | } |
4f771f10 PZ |
5348 | } |
5349 | ||
2dd24552 JB |
5350 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5351 | { | |
5352 | struct drm_device *dev = crtc->base.dev; | |
5353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5354 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5355 | |
681a8504 | 5356 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5357 | return; |
5358 | ||
2dd24552 | 5359 | /* |
c0b03411 DV |
5360 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5361 | * according to register description and PRM. | |
2dd24552 | 5362 | */ |
c0b03411 DV |
5363 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5364 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5365 | |
b074cec8 JB |
5366 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5367 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5368 | |
5369 | /* Border color in case we don't scale up to the full screen. Black by | |
5370 | * default, change to something else for debugging. */ | |
5371 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5372 | } |
5373 | ||
d05410f9 DA |
5374 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5375 | { | |
5376 | switch (port) { | |
5377 | case PORT_A: | |
6331a704 | 5378 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5379 | case PORT_B: |
6331a704 | 5380 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5381 | case PORT_C: |
6331a704 | 5382 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5383 | case PORT_D: |
6331a704 | 5384 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5385 | case PORT_E: |
6331a704 | 5386 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5387 | default: |
b9fec167 | 5388 | MISSING_CASE(port); |
d05410f9 DA |
5389 | return POWER_DOMAIN_PORT_OTHER; |
5390 | } | |
5391 | } | |
5392 | ||
25f78f58 VS |
5393 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5394 | { | |
5395 | switch (port) { | |
5396 | case PORT_A: | |
5397 | return POWER_DOMAIN_AUX_A; | |
5398 | case PORT_B: | |
5399 | return POWER_DOMAIN_AUX_B; | |
5400 | case PORT_C: | |
5401 | return POWER_DOMAIN_AUX_C; | |
5402 | case PORT_D: | |
5403 | return POWER_DOMAIN_AUX_D; | |
5404 | case PORT_E: | |
5405 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5406 | return POWER_DOMAIN_AUX_D; | |
5407 | default: | |
b9fec167 | 5408 | MISSING_CASE(port); |
25f78f58 VS |
5409 | return POWER_DOMAIN_AUX_A; |
5410 | } | |
5411 | } | |
5412 | ||
319be8ae ID |
5413 | enum intel_display_power_domain |
5414 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5415 | { | |
5416 | struct drm_device *dev = intel_encoder->base.dev; | |
5417 | struct intel_digital_port *intel_dig_port; | |
5418 | ||
5419 | switch (intel_encoder->type) { | |
5420 | case INTEL_OUTPUT_UNKNOWN: | |
5421 | /* Only DDI platforms should ever use this output type */ | |
5422 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5423 | case INTEL_OUTPUT_DISPLAYPORT: | |
5424 | case INTEL_OUTPUT_HDMI: | |
5425 | case INTEL_OUTPUT_EDP: | |
5426 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5427 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5428 | case INTEL_OUTPUT_DP_MST: |
5429 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5430 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5431 | case INTEL_OUTPUT_ANALOG: |
5432 | return POWER_DOMAIN_PORT_CRT; | |
5433 | case INTEL_OUTPUT_DSI: | |
5434 | return POWER_DOMAIN_PORT_DSI; | |
5435 | default: | |
5436 | return POWER_DOMAIN_PORT_OTHER; | |
5437 | } | |
5438 | } | |
5439 | ||
25f78f58 VS |
5440 | enum intel_display_power_domain |
5441 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5442 | { | |
5443 | struct drm_device *dev = intel_encoder->base.dev; | |
5444 | struct intel_digital_port *intel_dig_port; | |
5445 | ||
5446 | switch (intel_encoder->type) { | |
5447 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5448 | case INTEL_OUTPUT_HDMI: |
5449 | /* | |
5450 | * Only DDI platforms should ever use these output types. | |
5451 | * We can get here after the HDMI detect code has already set | |
5452 | * the type of the shared encoder. Since we can't be sure | |
5453 | * what's the status of the given connectors, play safe and | |
5454 | * run the DP detection too. | |
5455 | */ | |
25f78f58 VS |
5456 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5457 | case INTEL_OUTPUT_DISPLAYPORT: | |
5458 | case INTEL_OUTPUT_EDP: | |
5459 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5460 | return port_to_aux_power_domain(intel_dig_port->port); | |
5461 | case INTEL_OUTPUT_DP_MST: | |
5462 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5463 | return port_to_aux_power_domain(intel_dig_port->port); | |
5464 | default: | |
b9fec167 | 5465 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5466 | return POWER_DOMAIN_AUX_A; |
5467 | } | |
5468 | } | |
5469 | ||
74bff5f9 ML |
5470 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5471 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5472 | { |
319be8ae | 5473 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5474 | struct drm_encoder *encoder; |
319be8ae ID |
5475 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5476 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5477 | unsigned long mask; |
74bff5f9 | 5478 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5479 | |
74bff5f9 | 5480 | if (!crtc_state->base.active) |
292b990e ML |
5481 | return 0; |
5482 | ||
77d22dca ID |
5483 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5484 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5485 | if (crtc_state->pch_pfit.enabled || |
5486 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5487 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5488 | ||
74bff5f9 ML |
5489 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5490 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5491 | ||
319be8ae | 5492 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5493 | } |
319be8ae | 5494 | |
77d22dca ID |
5495 | return mask; |
5496 | } | |
5497 | ||
74bff5f9 ML |
5498 | static unsigned long |
5499 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5500 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5501 | { |
292b990e ML |
5502 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5503 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5504 | enum intel_display_power_domain domain; | |
5505 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5506 | |
292b990e | 5507 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5508 | intel_crtc->enabled_power_domains = new_domains = |
5509 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5510 | |
292b990e ML |
5511 | domains = new_domains & ~old_domains; |
5512 | ||
5513 | for_each_power_domain(domain, domains) | |
5514 | intel_display_power_get(dev_priv, domain); | |
5515 | ||
5516 | return old_domains & ~new_domains; | |
5517 | } | |
5518 | ||
5519 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5520 | unsigned long domains) | |
5521 | { | |
5522 | enum intel_display_power_domain domain; | |
5523 | ||
5524 | for_each_power_domain(domain, domains) | |
5525 | intel_display_power_put(dev_priv, domain); | |
5526 | } | |
77d22dca | 5527 | |
adafdc6f MK |
5528 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5529 | { | |
5530 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5531 | ||
5532 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5533 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5534 | return max_cdclk_freq; | |
5535 | else if (IS_CHERRYVIEW(dev_priv)) | |
5536 | return max_cdclk_freq*95/100; | |
5537 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5538 | return 2*max_cdclk_freq*90/100; | |
5539 | else | |
5540 | return max_cdclk_freq*90/100; | |
5541 | } | |
5542 | ||
560a7ae4 DL |
5543 | static void intel_update_max_cdclk(struct drm_device *dev) |
5544 | { | |
5545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5546 | ||
ef11bdb3 | 5547 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5548 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5549 | ||
5550 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5551 | dev_priv->max_cdclk_freq = 675000; | |
5552 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5553 | dev_priv->max_cdclk_freq = 540000; | |
5554 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5555 | dev_priv->max_cdclk_freq = 450000; | |
5556 | else | |
5557 | dev_priv->max_cdclk_freq = 337500; | |
5558 | } else if (IS_BROADWELL(dev)) { | |
5559 | /* | |
5560 | * FIXME with extra cooling we can allow | |
5561 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5562 | * How can we know if extra cooling is | |
5563 | * available? PCI ID, VTB, something else? | |
5564 | */ | |
5565 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5566 | dev_priv->max_cdclk_freq = 450000; | |
5567 | else if (IS_BDW_ULX(dev)) | |
5568 | dev_priv->max_cdclk_freq = 450000; | |
5569 | else if (IS_BDW_ULT(dev)) | |
5570 | dev_priv->max_cdclk_freq = 540000; | |
5571 | else | |
5572 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5573 | } else if (IS_CHERRYVIEW(dev)) { |
5574 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5575 | } else if (IS_VALLEYVIEW(dev)) { |
5576 | dev_priv->max_cdclk_freq = 400000; | |
5577 | } else { | |
5578 | /* otherwise assume cdclk is fixed */ | |
5579 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5580 | } | |
5581 | ||
adafdc6f MK |
5582 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5583 | ||
560a7ae4 DL |
5584 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5585 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5586 | |
5587 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5588 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5589 | } |
5590 | ||
5591 | static void intel_update_cdclk(struct drm_device *dev) | |
5592 | { | |
5593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5594 | ||
5595 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5596 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5597 | dev_priv->cdclk_freq); | |
5598 | ||
5599 | /* | |
5600 | * Program the gmbus_freq based on the cdclk frequency. | |
5601 | * BSpec erroneously claims we should aim for 4MHz, but | |
5602 | * in fact 1MHz is the correct frequency. | |
5603 | */ | |
666a4537 | 5604 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5605 | /* |
5606 | * Program the gmbus_freq based on the cdclk frequency. | |
5607 | * BSpec erroneously claims we should aim for 4MHz, but | |
5608 | * in fact 1MHz is the correct frequency. | |
5609 | */ | |
5610 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5611 | } | |
5612 | ||
5613 | if (dev_priv->max_cdclk_freq == 0) | |
5614 | intel_update_max_cdclk(dev); | |
5615 | } | |
5616 | ||
70d0c574 | 5617 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5618 | { |
5619 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5620 | uint32_t divider; | |
5621 | uint32_t ratio; | |
5622 | uint32_t current_freq; | |
5623 | int ret; | |
5624 | ||
5625 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5626 | switch (frequency) { | |
5627 | case 144000: | |
5628 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5629 | ratio = BXT_DE_PLL_RATIO(60); | |
5630 | break; | |
5631 | case 288000: | |
5632 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5633 | ratio = BXT_DE_PLL_RATIO(60); | |
5634 | break; | |
5635 | case 384000: | |
5636 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5637 | ratio = BXT_DE_PLL_RATIO(60); | |
5638 | break; | |
5639 | case 576000: | |
5640 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5641 | ratio = BXT_DE_PLL_RATIO(60); | |
5642 | break; | |
5643 | case 624000: | |
5644 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5645 | ratio = BXT_DE_PLL_RATIO(65); | |
5646 | break; | |
5647 | case 19200: | |
5648 | /* | |
5649 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5650 | * to suppress GCC warning. | |
5651 | */ | |
5652 | ratio = 0; | |
5653 | divider = 0; | |
5654 | break; | |
5655 | default: | |
5656 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5657 | ||
5658 | return; | |
5659 | } | |
5660 | ||
5661 | mutex_lock(&dev_priv->rps.hw_lock); | |
5662 | /* Inform power controller of upcoming frequency change */ | |
5663 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5664 | 0x80000000); | |
5665 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5666 | ||
5667 | if (ret) { | |
5668 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5669 | ret, frequency); | |
5670 | return; | |
5671 | } | |
5672 | ||
5673 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5674 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5675 | current_freq = current_freq * 500 + 1000; | |
5676 | ||
5677 | /* | |
5678 | * DE PLL has to be disabled when | |
5679 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5680 | * - before setting to 624MHz (PLL needs toggling) | |
5681 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5682 | */ | |
5683 | if (frequency == 19200 || frequency == 624000 || | |
5684 | current_freq == 624000) { | |
5685 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5686 | /* Timeout 200us */ | |
5687 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5688 | 1)) | |
5689 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5690 | } | |
5691 | ||
5692 | if (frequency != 19200) { | |
5693 | uint32_t val; | |
5694 | ||
5695 | val = I915_READ(BXT_DE_PLL_CTL); | |
5696 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5697 | val |= ratio; | |
5698 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5699 | ||
5700 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5701 | /* Timeout 200us */ | |
5702 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5703 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5704 | ||
5705 | val = I915_READ(CDCLK_CTL); | |
5706 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5707 | val |= divider; | |
5708 | /* | |
5709 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5710 | * enable otherwise. | |
5711 | */ | |
5712 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5713 | if (frequency >= 500000) | |
5714 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5715 | ||
5716 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5717 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5718 | val |= (frequency - 1000) / 500; | |
5719 | I915_WRITE(CDCLK_CTL, val); | |
5720 | } | |
5721 | ||
5722 | mutex_lock(&dev_priv->rps.hw_lock); | |
5723 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5724 | DIV_ROUND_UP(frequency, 25000)); | |
5725 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5726 | ||
5727 | if (ret) { | |
5728 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5729 | ret, frequency); | |
5730 | return; | |
5731 | } | |
5732 | ||
a47871bd | 5733 | intel_update_cdclk(dev); |
f8437dd1 VK |
5734 | } |
5735 | ||
5736 | void broxton_init_cdclk(struct drm_device *dev) | |
5737 | { | |
5738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5739 | uint32_t val; | |
5740 | ||
5741 | /* | |
5742 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5743 | * or else the reset will hang because there is no PCH to respond. | |
5744 | * Move the handshake programming to initialization sequence. | |
5745 | * Previously was left up to BIOS. | |
5746 | */ | |
5747 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5748 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5749 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5750 | ||
5751 | /* Enable PG1 for cdclk */ | |
5752 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5753 | ||
5754 | /* check if cd clock is enabled */ | |
5755 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5756 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5757 | return; | |
5758 | } | |
5759 | ||
5760 | /* | |
5761 | * FIXME: | |
5762 | * - The initial CDCLK needs to be read from VBT. | |
5763 | * Need to make this change after VBT has changes for BXT. | |
5764 | * - check if setting the max (or any) cdclk freq is really necessary | |
5765 | * here, it belongs to modeset time | |
5766 | */ | |
5767 | broxton_set_cdclk(dev, 624000); | |
5768 | ||
5769 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5770 | POSTING_READ(DBUF_CTL); |
5771 | ||
f8437dd1 VK |
5772 | udelay(10); |
5773 | ||
5774 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5775 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5776 | } | |
5777 | ||
5778 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5779 | { | |
5780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5781 | ||
5782 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5783 | POSTING_READ(DBUF_CTL); |
5784 | ||
f8437dd1 VK |
5785 | udelay(10); |
5786 | ||
5787 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5788 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5789 | ||
5790 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5791 | broxton_set_cdclk(dev, 19200); | |
5792 | ||
5793 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5794 | } | |
5795 | ||
5d96d8af DL |
5796 | static const struct skl_cdclk_entry { |
5797 | unsigned int freq; | |
5798 | unsigned int vco; | |
5799 | } skl_cdclk_frequencies[] = { | |
5800 | { .freq = 308570, .vco = 8640 }, | |
5801 | { .freq = 337500, .vco = 8100 }, | |
5802 | { .freq = 432000, .vco = 8640 }, | |
5803 | { .freq = 450000, .vco = 8100 }, | |
5804 | { .freq = 540000, .vco = 8100 }, | |
5805 | { .freq = 617140, .vco = 8640 }, | |
5806 | { .freq = 675000, .vco = 8100 }, | |
5807 | }; | |
5808 | ||
5809 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5810 | { | |
5811 | return (freq - 1000) / 500; | |
5812 | } | |
5813 | ||
5814 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5815 | { | |
5816 | unsigned int i; | |
5817 | ||
5818 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5819 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5820 | ||
5821 | if (e->freq == freq) | |
5822 | return e->vco; | |
5823 | } | |
5824 | ||
5825 | return 8100; | |
5826 | } | |
5827 | ||
5828 | static void | |
5829 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5830 | { | |
5831 | unsigned int min_freq; | |
5832 | u32 val; | |
5833 | ||
5834 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5835 | val = I915_READ(CDCLK_CTL); | |
5836 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5837 | val |= CDCLK_FREQ_337_308; | |
5838 | ||
5839 | if (required_vco == 8640) | |
5840 | min_freq = 308570; | |
5841 | else | |
5842 | min_freq = 337500; | |
5843 | ||
5844 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5845 | ||
5846 | I915_WRITE(CDCLK_CTL, val); | |
5847 | POSTING_READ(CDCLK_CTL); | |
5848 | ||
5849 | /* | |
5850 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5851 | * taking into account the VCO required to operate the eDP panel at the | |
5852 | * desired frequency. The usual DP link rates operate with a VCO of | |
5853 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5854 | * The modeset code is responsible for the selection of the exact link | |
5855 | * rate later on, with the constraint of choosing a frequency that | |
5856 | * works with required_vco. | |
5857 | */ | |
5858 | val = I915_READ(DPLL_CTRL1); | |
5859 | ||
5860 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5861 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5862 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5863 | if (required_vco == 8640) | |
5864 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5865 | SKL_DPLL0); | |
5866 | else | |
5867 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5868 | SKL_DPLL0); | |
5869 | ||
5870 | I915_WRITE(DPLL_CTRL1, val); | |
5871 | POSTING_READ(DPLL_CTRL1); | |
5872 | ||
5873 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5874 | ||
5875 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5876 | DRM_ERROR("DPLL0 not locked\n"); | |
5877 | } | |
5878 | ||
5879 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5880 | { | |
5881 | int ret; | |
5882 | u32 val; | |
5883 | ||
5884 | /* inform PCU we want to change CDCLK */ | |
5885 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5886 | mutex_lock(&dev_priv->rps.hw_lock); | |
5887 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5888 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5889 | ||
5890 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5891 | } | |
5892 | ||
5893 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5894 | { | |
5895 | unsigned int i; | |
5896 | ||
5897 | for (i = 0; i < 15; i++) { | |
5898 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5899 | return true; | |
5900 | udelay(10); | |
5901 | } | |
5902 | ||
5903 | return false; | |
5904 | } | |
5905 | ||
5906 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5907 | { | |
560a7ae4 | 5908 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5909 | u32 freq_select, pcu_ack; |
5910 | ||
5911 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5912 | ||
5913 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5914 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5915 | return; | |
5916 | } | |
5917 | ||
5918 | /* set CDCLK_CTL */ | |
5919 | switch(freq) { | |
5920 | case 450000: | |
5921 | case 432000: | |
5922 | freq_select = CDCLK_FREQ_450_432; | |
5923 | pcu_ack = 1; | |
5924 | break; | |
5925 | case 540000: | |
5926 | freq_select = CDCLK_FREQ_540; | |
5927 | pcu_ack = 2; | |
5928 | break; | |
5929 | case 308570: | |
5930 | case 337500: | |
5931 | default: | |
5932 | freq_select = CDCLK_FREQ_337_308; | |
5933 | pcu_ack = 0; | |
5934 | break; | |
5935 | case 617140: | |
5936 | case 675000: | |
5937 | freq_select = CDCLK_FREQ_675_617; | |
5938 | pcu_ack = 3; | |
5939 | break; | |
5940 | } | |
5941 | ||
5942 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5943 | POSTING_READ(CDCLK_CTL); | |
5944 | ||
5945 | /* inform PCU of the change */ | |
5946 | mutex_lock(&dev_priv->rps.hw_lock); | |
5947 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5948 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5949 | |
5950 | intel_update_cdclk(dev); | |
5d96d8af DL |
5951 | } |
5952 | ||
5953 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5954 | { | |
5955 | /* disable DBUF power */ | |
5956 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5957 | POSTING_READ(DBUF_CTL); | |
5958 | ||
5959 | udelay(10); | |
5960 | ||
5961 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5962 | DRM_ERROR("DBuf power disable timeout\n"); | |
5963 | ||
ab96c1ee ID |
5964 | /* disable DPLL0 */ |
5965 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5966 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5967 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5968 | } |
5969 | ||
5970 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5971 | { | |
5d96d8af DL |
5972 | unsigned int required_vco; |
5973 | ||
39d9b85a GW |
5974 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5975 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5976 | /* enable DPLL0 */ | |
5977 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5978 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5979 | } |
5980 | ||
5d96d8af DL |
5981 | /* set CDCLK to the frequency the BIOS chose */ |
5982 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5983 | ||
5984 | /* enable DBUF power */ | |
5985 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5986 | POSTING_READ(DBUF_CTL); | |
5987 | ||
5988 | udelay(10); | |
5989 | ||
5990 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5991 | DRM_ERROR("DBuf power enable timeout\n"); | |
5992 | } | |
5993 | ||
c73666f3 SK |
5994 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5995 | { | |
5996 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5997 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5998 | int freq = dev_priv->skl_boot_cdclk; | |
5999 | ||
f1b391a5 SK |
6000 | /* |
6001 | * check if the pre-os intialized the display | |
6002 | * There is SWF18 scratchpad register defined which is set by the | |
6003 | * pre-os which can be used by the OS drivers to check the status | |
6004 | */ | |
6005 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
6006 | goto sanitize; | |
6007 | ||
c73666f3 SK |
6008 | /* Is PLL enabled and locked ? */ |
6009 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
6010 | goto sanitize; | |
6011 | ||
6012 | /* DPLL okay; verify the cdclock | |
6013 | * | |
6014 | * Noticed in some instances that the freq selection is correct but | |
6015 | * decimal part is programmed wrong from BIOS where pre-os does not | |
6016 | * enable display. Verify the same as well. | |
6017 | */ | |
6018 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
6019 | /* All well; nothing to sanitize */ | |
6020 | return false; | |
6021 | sanitize: | |
6022 | /* | |
6023 | * As of now initialize with max cdclk till | |
6024 | * we get dynamic cdclk support | |
6025 | * */ | |
6026 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
6027 | skl_init_cdclk(dev_priv); | |
6028 | ||
6029 | /* we did have to sanitize */ | |
6030 | return true; | |
6031 | } | |
6032 | ||
30a970c6 JB |
6033 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
6034 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
6035 | { | |
6036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6037 | u32 val, cmd; | |
6038 | ||
164dfd28 VK |
6039 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6040 | != dev_priv->cdclk_freq); | |
d60c4473 | 6041 | |
dfcab17e | 6042 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 6043 | cmd = 2; |
dfcab17e | 6044 | else if (cdclk == 266667) |
30a970c6 JB |
6045 | cmd = 1; |
6046 | else | |
6047 | cmd = 0; | |
6048 | ||
6049 | mutex_lock(&dev_priv->rps.hw_lock); | |
6050 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6051 | val &= ~DSPFREQGUAR_MASK; | |
6052 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
6053 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6054 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6055 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
6056 | 50)) { | |
6057 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6058 | } | |
6059 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6060 | ||
54433e91 VS |
6061 | mutex_lock(&dev_priv->sb_lock); |
6062 | ||
dfcab17e | 6063 | if (cdclk == 400000) { |
6bcda4f0 | 6064 | u32 divider; |
30a970c6 | 6065 | |
6bcda4f0 | 6066 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 6067 | |
30a970c6 JB |
6068 | /* adjust cdclk divider */ |
6069 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 6070 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
6071 | val |= divider; |
6072 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
6073 | |
6074 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 6075 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
6076 | 50)) |
6077 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
6078 | } |
6079 | ||
30a970c6 JB |
6080 | /* adjust self-refresh exit latency value */ |
6081 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
6082 | val &= ~0x7f; | |
6083 | ||
6084 | /* | |
6085 | * For high bandwidth configs, we set a higher latency in the bunit | |
6086 | * so that the core display fetch happens in time to avoid underruns. | |
6087 | */ | |
dfcab17e | 6088 | if (cdclk == 400000) |
30a970c6 JB |
6089 | val |= 4500 / 250; /* 4.5 usec */ |
6090 | else | |
6091 | val |= 3000 / 250; /* 3.0 usec */ | |
6092 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 6093 | |
a580516d | 6094 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 6095 | |
b6283055 | 6096 | intel_update_cdclk(dev); |
30a970c6 JB |
6097 | } |
6098 | ||
383c5a6a VS |
6099 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
6100 | { | |
6101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6102 | u32 val, cmd; | |
6103 | ||
164dfd28 VK |
6104 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6105 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
6106 | |
6107 | switch (cdclk) { | |
383c5a6a VS |
6108 | case 333333: |
6109 | case 320000: | |
383c5a6a | 6110 | case 266667: |
383c5a6a | 6111 | case 200000: |
383c5a6a VS |
6112 | break; |
6113 | default: | |
5f77eeb0 | 6114 | MISSING_CASE(cdclk); |
383c5a6a VS |
6115 | return; |
6116 | } | |
6117 | ||
9d0d3fda VS |
6118 | /* |
6119 | * Specs are full of misinformation, but testing on actual | |
6120 | * hardware has shown that we just need to write the desired | |
6121 | * CCK divider into the Punit register. | |
6122 | */ | |
6123 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6124 | ||
383c5a6a VS |
6125 | mutex_lock(&dev_priv->rps.hw_lock); |
6126 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6127 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6128 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6129 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6130 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6131 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6132 | 50)) { | |
6133 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6134 | } | |
6135 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6136 | ||
b6283055 | 6137 | intel_update_cdclk(dev); |
383c5a6a VS |
6138 | } |
6139 | ||
30a970c6 JB |
6140 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6141 | int max_pixclk) | |
6142 | { | |
6bcda4f0 | 6143 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6144 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6145 | |
30a970c6 JB |
6146 | /* |
6147 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6148 | * 200MHz | |
6149 | * 267MHz | |
29dc7ef3 | 6150 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6151 | * 400MHz (VLV only) |
6152 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6153 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6154 | * |
6155 | * We seem to get an unstable or solid color picture at 200MHz. | |
6156 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6157 | * are off. | |
30a970c6 | 6158 | */ |
6cca3195 VS |
6159 | if (!IS_CHERRYVIEW(dev_priv) && |
6160 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6161 | return 400000; |
6cca3195 | 6162 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6163 | return freq_320; |
e37c67a1 | 6164 | else if (max_pixclk > 0) |
dfcab17e | 6165 | return 266667; |
e37c67a1 VS |
6166 | else |
6167 | return 200000; | |
30a970c6 JB |
6168 | } |
6169 | ||
f8437dd1 VK |
6170 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6171 | int max_pixclk) | |
6172 | { | |
6173 | /* | |
6174 | * FIXME: | |
6175 | * - remove the guardband, it's not needed on BXT | |
6176 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6177 | */ | |
6178 | if (max_pixclk > 576000*9/10) | |
6179 | return 624000; | |
6180 | else if (max_pixclk > 384000*9/10) | |
6181 | return 576000; | |
6182 | else if (max_pixclk > 288000*9/10) | |
6183 | return 384000; | |
6184 | else if (max_pixclk > 144000*9/10) | |
6185 | return 288000; | |
6186 | else | |
6187 | return 144000; | |
6188 | } | |
6189 | ||
e8788cbc | 6190 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6191 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6192 | struct drm_atomic_state *state) | |
30a970c6 | 6193 | { |
565602d7 ML |
6194 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
6195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6196 | struct drm_crtc *crtc; | |
6197 | struct drm_crtc_state *crtc_state; | |
6198 | unsigned max_pixclk = 0, i; | |
6199 | enum pipe pipe; | |
30a970c6 | 6200 | |
565602d7 ML |
6201 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6202 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6203 | |
565602d7 ML |
6204 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6205 | int pixclk = 0; | |
6206 | ||
6207 | if (crtc_state->enable) | |
6208 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6209 | |
565602d7 | 6210 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6211 | } |
6212 | ||
565602d7 ML |
6213 | for_each_pipe(dev_priv, pipe) |
6214 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6215 | ||
30a970c6 JB |
6216 | return max_pixclk; |
6217 | } | |
6218 | ||
27c329ed | 6219 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6220 | { |
27c329ed ML |
6221 | struct drm_device *dev = state->dev; |
6222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6223 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6224 | struct intel_atomic_state *intel_state = |
6225 | to_intel_atomic_state(state); | |
30a970c6 | 6226 | |
304603f4 ACO |
6227 | if (max_pixclk < 0) |
6228 | return max_pixclk; | |
30a970c6 | 6229 | |
1a617b77 | 6230 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6231 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6232 | |
1a617b77 ML |
6233 | if (!intel_state->active_crtcs) |
6234 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6235 | ||
27c329ed ML |
6236 | return 0; |
6237 | } | |
304603f4 | 6238 | |
27c329ed ML |
6239 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6240 | { | |
6241 | struct drm_device *dev = state->dev; | |
6242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6243 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6244 | struct intel_atomic_state *intel_state = |
6245 | to_intel_atomic_state(state); | |
85a96e7a | 6246 | |
27c329ed ML |
6247 | if (max_pixclk < 0) |
6248 | return max_pixclk; | |
85a96e7a | 6249 | |
1a617b77 | 6250 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6251 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 6252 | |
1a617b77 ML |
6253 | if (!intel_state->active_crtcs) |
6254 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
6255 | ||
27c329ed | 6256 | return 0; |
30a970c6 JB |
6257 | } |
6258 | ||
1e69cd74 VS |
6259 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6260 | { | |
6261 | unsigned int credits, default_credits; | |
6262 | ||
6263 | if (IS_CHERRYVIEW(dev_priv)) | |
6264 | default_credits = PFI_CREDIT(12); | |
6265 | else | |
6266 | default_credits = PFI_CREDIT(8); | |
6267 | ||
bfa7df01 | 6268 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6269 | /* CHV suggested value is 31 or 63 */ |
6270 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6271 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6272 | else |
6273 | credits = PFI_CREDIT(15); | |
6274 | } else { | |
6275 | credits = default_credits; | |
6276 | } | |
6277 | ||
6278 | /* | |
6279 | * WA - write default credits before re-programming | |
6280 | * FIXME: should we also set the resend bit here? | |
6281 | */ | |
6282 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6283 | default_credits); | |
6284 | ||
6285 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6286 | credits | PFI_CREDIT_RESEND); | |
6287 | ||
6288 | /* | |
6289 | * FIXME is this guaranteed to clear | |
6290 | * immediately or should we poll for it? | |
6291 | */ | |
6292 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6293 | } | |
6294 | ||
27c329ed | 6295 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6296 | { |
a821fc46 | 6297 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6298 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6299 | struct intel_atomic_state *old_intel_state = |
6300 | to_intel_atomic_state(old_state); | |
6301 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6302 | |
27c329ed ML |
6303 | /* |
6304 | * FIXME: We can end up here with all power domains off, yet | |
6305 | * with a CDCLK frequency other than the minimum. To account | |
6306 | * for this take the PIPE-A power domain, which covers the HW | |
6307 | * blocks needed for the following programming. This can be | |
6308 | * removed once it's guaranteed that we get here either with | |
6309 | * the minimum CDCLK set, or the required power domains | |
6310 | * enabled. | |
6311 | */ | |
6312 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6313 | |
27c329ed ML |
6314 | if (IS_CHERRYVIEW(dev)) |
6315 | cherryview_set_cdclk(dev, req_cdclk); | |
6316 | else | |
6317 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6318 | |
27c329ed | 6319 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6320 | |
27c329ed | 6321 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6322 | } |
6323 | ||
89b667f8 JB |
6324 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6325 | { | |
6326 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6327 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6329 | struct intel_encoder *encoder; | |
6330 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6331 | |
53d9f4e9 | 6332 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6333 | return; |
6334 | ||
6e3c9717 | 6335 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6336 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6337 | |
6338 | intel_set_pipe_timings(intel_crtc); | |
6339 | ||
c14b0485 VS |
6340 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6342 | ||
6343 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6344 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6345 | } | |
6346 | ||
5b18e57c DV |
6347 | i9xx_set_pipeconf(intel_crtc); |
6348 | ||
89b667f8 | 6349 | intel_crtc->active = true; |
89b667f8 | 6350 | |
a72e4c9f | 6351 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6352 | |
89b667f8 JB |
6353 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6354 | if (encoder->pre_pll_enable) | |
6355 | encoder->pre_pll_enable(encoder); | |
6356 | ||
a65347ba | 6357 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6358 | if (IS_CHERRYVIEW(dev)) { |
6359 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6360 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6361 | } else { |
6362 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6363 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6364 | } |
9d556c99 | 6365 | } |
89b667f8 JB |
6366 | |
6367 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6368 | if (encoder->pre_enable) | |
6369 | encoder->pre_enable(encoder); | |
6370 | ||
2dd24552 JB |
6371 | i9xx_pfit_enable(intel_crtc); |
6372 | ||
63cbb074 VS |
6373 | intel_crtc_load_lut(crtc); |
6374 | ||
e1fdc473 | 6375 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6376 | |
4b3a9526 VS |
6377 | assert_vblank_disabled(crtc); |
6378 | drm_crtc_vblank_on(crtc); | |
6379 | ||
f9b61ff6 DV |
6380 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6381 | encoder->enable(encoder); | |
89b667f8 JB |
6382 | } |
6383 | ||
f13c2ef3 DV |
6384 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6385 | { | |
6386 | struct drm_device *dev = crtc->base.dev; | |
6387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6388 | ||
6e3c9717 ACO |
6389 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6390 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6391 | } |
6392 | ||
0b8765c6 | 6393 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6394 | { |
6395 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6396 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6397 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6398 | struct intel_encoder *encoder; |
79e53945 | 6399 | int pipe = intel_crtc->pipe; |
79e53945 | 6400 | |
53d9f4e9 | 6401 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6402 | return; |
6403 | ||
f13c2ef3 DV |
6404 | i9xx_set_pll_dividers(intel_crtc); |
6405 | ||
6e3c9717 | 6406 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6407 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6408 | |
6409 | intel_set_pipe_timings(intel_crtc); | |
6410 | ||
5b18e57c DV |
6411 | i9xx_set_pipeconf(intel_crtc); |
6412 | ||
f7abfe8b | 6413 | intel_crtc->active = true; |
6b383a7f | 6414 | |
4a3436e8 | 6415 | if (!IS_GEN2(dev)) |
a72e4c9f | 6416 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6417 | |
9d6d9f19 MK |
6418 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6419 | if (encoder->pre_enable) | |
6420 | encoder->pre_enable(encoder); | |
6421 | ||
f6736a1a DV |
6422 | i9xx_enable_pll(intel_crtc); |
6423 | ||
2dd24552 JB |
6424 | i9xx_pfit_enable(intel_crtc); |
6425 | ||
63cbb074 VS |
6426 | intel_crtc_load_lut(crtc); |
6427 | ||
f37fcc2a | 6428 | intel_update_watermarks(crtc); |
e1fdc473 | 6429 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6430 | |
4b3a9526 VS |
6431 | assert_vblank_disabled(crtc); |
6432 | drm_crtc_vblank_on(crtc); | |
6433 | ||
f9b61ff6 DV |
6434 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6435 | encoder->enable(encoder); | |
0b8765c6 | 6436 | } |
79e53945 | 6437 | |
87476d63 DV |
6438 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6439 | { | |
6440 | struct drm_device *dev = crtc->base.dev; | |
6441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6442 | |
6e3c9717 | 6443 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6444 | return; |
87476d63 | 6445 | |
328d8e82 | 6446 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6447 | |
328d8e82 DV |
6448 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6449 | I915_READ(PFIT_CONTROL)); | |
6450 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6451 | } |
6452 | ||
0b8765c6 JB |
6453 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6454 | { | |
6455 | struct drm_device *dev = crtc->dev; | |
6456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6458 | struct intel_encoder *encoder; |
0b8765c6 | 6459 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6460 | |
6304cd91 VS |
6461 | /* |
6462 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6463 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6464 | * We also need to wait on all gmch platforms because of the |
6465 | * self-refresh mode constraint explained above. | |
6304cd91 | 6466 | */ |
564ed191 | 6467 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6468 | |
4b3a9526 VS |
6469 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6470 | encoder->disable(encoder); | |
6471 | ||
f9b61ff6 DV |
6472 | drm_crtc_vblank_off(crtc); |
6473 | assert_vblank_disabled(crtc); | |
6474 | ||
575f7ab7 | 6475 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6476 | |
87476d63 | 6477 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6478 | |
89b667f8 JB |
6479 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6480 | if (encoder->post_disable) | |
6481 | encoder->post_disable(encoder); | |
6482 | ||
a65347ba | 6483 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6484 | if (IS_CHERRYVIEW(dev)) |
6485 | chv_disable_pll(dev_priv, pipe); | |
6486 | else if (IS_VALLEYVIEW(dev)) | |
6487 | vlv_disable_pll(dev_priv, pipe); | |
6488 | else | |
1c4e0274 | 6489 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6490 | } |
0b8765c6 | 6491 | |
d6db995f VS |
6492 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6493 | if (encoder->post_pll_disable) | |
6494 | encoder->post_pll_disable(encoder); | |
6495 | ||
4a3436e8 | 6496 | if (!IS_GEN2(dev)) |
a72e4c9f | 6497 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6498 | } |
6499 | ||
b17d48e2 ML |
6500 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6501 | { | |
6502 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6503 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6504 | enum intel_display_power_domain domain; | |
6505 | unsigned long domains; | |
6506 | ||
6507 | if (!intel_crtc->active) | |
6508 | return; | |
6509 | ||
a539205a | 6510 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6511 | WARN_ON(intel_crtc->unpin_work); |
6512 | ||
a539205a | 6513 | intel_pre_disable_primary(crtc); |
54a41961 ML |
6514 | |
6515 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6516 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6517 | } |
6518 | ||
b17d48e2 | 6519 | dev_priv->display.crtc_disable(crtc); |
37d9078b | 6520 | intel_crtc->active = false; |
58f9c0bc | 6521 | intel_fbc_disable(intel_crtc); |
37d9078b | 6522 | intel_update_watermarks(crtc); |
1f7457b1 | 6523 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6524 | |
6525 | domains = intel_crtc->enabled_power_domains; | |
6526 | for_each_power_domain(domain, domains) | |
6527 | intel_display_power_put(dev_priv, domain); | |
6528 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6529 | |
6530 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6531 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6532 | } |
6533 | ||
6b72d486 ML |
6534 | /* |
6535 | * turn all crtc's off, but do not adjust state | |
6536 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6537 | */ | |
70e0bd74 | 6538 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6539 | { |
e2c8b870 | 6540 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6541 | struct drm_atomic_state *state; |
e2c8b870 | 6542 | int ret; |
70e0bd74 | 6543 | |
e2c8b870 ML |
6544 | state = drm_atomic_helper_suspend(dev); |
6545 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6546 | if (ret) |
6547 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6548 | else |
6549 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6550 | return ret; |
ee7b9f93 JB |
6551 | } |
6552 | ||
ea5b213a | 6553 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6554 | { |
4ef69c7a | 6555 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6556 | |
ea5b213a CW |
6557 | drm_encoder_cleanup(encoder); |
6558 | kfree(intel_encoder); | |
7e7d76c3 JB |
6559 | } |
6560 | ||
0a91ca29 DV |
6561 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6562 | * internal consistency). */ | |
b980514c | 6563 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6564 | { |
35dd3c64 ML |
6565 | struct drm_crtc *crtc = connector->base.state->crtc; |
6566 | ||
6567 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6568 | connector->base.base.id, | |
6569 | connector->base.name); | |
6570 | ||
0a91ca29 | 6571 | if (connector->get_hw_state(connector)) { |
e85376cb | 6572 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6573 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6574 | |
35dd3c64 ML |
6575 | I915_STATE_WARN(!crtc, |
6576 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6577 | |
35dd3c64 ML |
6578 | if (!crtc) |
6579 | return; | |
6580 | ||
6581 | I915_STATE_WARN(!crtc->state->active, | |
6582 | "connector is active, but attached crtc isn't\n"); | |
6583 | ||
e85376cb | 6584 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6585 | return; |
6586 | ||
e85376cb | 6587 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6588 | "atomic encoder doesn't match attached encoder\n"); |
6589 | ||
e85376cb | 6590 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6591 | "attached encoder crtc differs from connector crtc\n"); |
6592 | } else { | |
4d688a2a ML |
6593 | I915_STATE_WARN(crtc && crtc->state->active, |
6594 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6595 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6596 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6597 | } |
79e53945 JB |
6598 | } |
6599 | ||
08d9bc92 ACO |
6600 | int intel_connector_init(struct intel_connector *connector) |
6601 | { | |
5350a031 | 6602 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6603 | |
5350a031 | 6604 | if (!connector->base.state) |
08d9bc92 ACO |
6605 | return -ENOMEM; |
6606 | ||
08d9bc92 ACO |
6607 | return 0; |
6608 | } | |
6609 | ||
6610 | struct intel_connector *intel_connector_alloc(void) | |
6611 | { | |
6612 | struct intel_connector *connector; | |
6613 | ||
6614 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6615 | if (!connector) | |
6616 | return NULL; | |
6617 | ||
6618 | if (intel_connector_init(connector) < 0) { | |
6619 | kfree(connector); | |
6620 | return NULL; | |
6621 | } | |
6622 | ||
6623 | return connector; | |
6624 | } | |
6625 | ||
f0947c37 DV |
6626 | /* Simple connector->get_hw_state implementation for encoders that support only |
6627 | * one connector and no cloning and hence the encoder state determines the state | |
6628 | * of the connector. */ | |
6629 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6630 | { |
24929352 | 6631 | enum pipe pipe = 0; |
f0947c37 | 6632 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6633 | |
f0947c37 | 6634 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6635 | } |
6636 | ||
6d293983 | 6637 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6638 | { |
6d293983 ACO |
6639 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6640 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6641 | |
6642 | return 0; | |
6643 | } | |
6644 | ||
6d293983 | 6645 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6646 | struct intel_crtc_state *pipe_config) |
1857e1da | 6647 | { |
6d293983 ACO |
6648 | struct drm_atomic_state *state = pipe_config->base.state; |
6649 | struct intel_crtc *other_crtc; | |
6650 | struct intel_crtc_state *other_crtc_state; | |
6651 | ||
1857e1da DV |
6652 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6653 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6654 | if (pipe_config->fdi_lanes > 4) { | |
6655 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6656 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6657 | return -EINVAL; |
1857e1da DV |
6658 | } |
6659 | ||
bafb6553 | 6660 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6661 | if (pipe_config->fdi_lanes > 2) { |
6662 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6663 | pipe_config->fdi_lanes); | |
6d293983 | 6664 | return -EINVAL; |
1857e1da | 6665 | } else { |
6d293983 | 6666 | return 0; |
1857e1da DV |
6667 | } |
6668 | } | |
6669 | ||
6670 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6671 | return 0; |
1857e1da DV |
6672 | |
6673 | /* Ivybridge 3 pipe is really complicated */ | |
6674 | switch (pipe) { | |
6675 | case PIPE_A: | |
6d293983 | 6676 | return 0; |
1857e1da | 6677 | case PIPE_B: |
6d293983 ACO |
6678 | if (pipe_config->fdi_lanes <= 2) |
6679 | return 0; | |
6680 | ||
6681 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6682 | other_crtc_state = | |
6683 | intel_atomic_get_crtc_state(state, other_crtc); | |
6684 | if (IS_ERR(other_crtc_state)) | |
6685 | return PTR_ERR(other_crtc_state); | |
6686 | ||
6687 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6688 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6689 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6690 | return -EINVAL; |
1857e1da | 6691 | } |
6d293983 | 6692 | return 0; |
1857e1da | 6693 | case PIPE_C: |
251cc67c VS |
6694 | if (pipe_config->fdi_lanes > 2) { |
6695 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6696 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6697 | return -EINVAL; |
251cc67c | 6698 | } |
6d293983 ACO |
6699 | |
6700 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6701 | other_crtc_state = | |
6702 | intel_atomic_get_crtc_state(state, other_crtc); | |
6703 | if (IS_ERR(other_crtc_state)) | |
6704 | return PTR_ERR(other_crtc_state); | |
6705 | ||
6706 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6707 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6708 | return -EINVAL; |
1857e1da | 6709 | } |
6d293983 | 6710 | return 0; |
1857e1da DV |
6711 | default: |
6712 | BUG(); | |
6713 | } | |
6714 | } | |
6715 | ||
e29c22c0 DV |
6716 | #define RETRY 1 |
6717 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6718 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6719 | { |
1857e1da | 6720 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6721 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6722 | int lane, link_bw, fdi_dotclock, ret; |
6723 | bool needs_recompute = false; | |
877d48d5 | 6724 | |
e29c22c0 | 6725 | retry: |
877d48d5 DV |
6726 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6727 | * each output octet as 10 bits. The actual frequency | |
6728 | * is stored as a divider into a 100MHz clock, and the | |
6729 | * mode pixel clock is stored in units of 1KHz. | |
6730 | * Hence the bw of each lane in terms of the mode signal | |
6731 | * is: | |
6732 | */ | |
21a727b3 | 6733 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6734 | |
241bfc38 | 6735 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6736 | |
2bd89a07 | 6737 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6738 | pipe_config->pipe_bpp); |
6739 | ||
6740 | pipe_config->fdi_lanes = lane; | |
6741 | ||
2bd89a07 | 6742 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6743 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6744 | |
e3b247da | 6745 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6746 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6747 | pipe_config->pipe_bpp -= 2*3; |
6748 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6749 | pipe_config->pipe_bpp); | |
6750 | needs_recompute = true; | |
6751 | pipe_config->bw_constrained = true; | |
6752 | ||
6753 | goto retry; | |
6754 | } | |
6755 | ||
6756 | if (needs_recompute) | |
6757 | return RETRY; | |
6758 | ||
6d293983 | 6759 | return ret; |
877d48d5 DV |
6760 | } |
6761 | ||
8cfb3407 VS |
6762 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6763 | struct intel_crtc_state *pipe_config) | |
6764 | { | |
6765 | if (pipe_config->pipe_bpp > 24) | |
6766 | return false; | |
6767 | ||
6768 | /* HSW can handle pixel rate up to cdclk? */ | |
6769 | if (IS_HASWELL(dev_priv->dev)) | |
6770 | return true; | |
6771 | ||
6772 | /* | |
b432e5cf VS |
6773 | * We compare against max which means we must take |
6774 | * the increased cdclk requirement into account when | |
6775 | * calculating the new cdclk. | |
6776 | * | |
6777 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6778 | */ |
6779 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6780 | dev_priv->max_cdclk_freq * 95 / 100; | |
6781 | } | |
6782 | ||
42db64ef | 6783 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6784 | struct intel_crtc_state *pipe_config) |
42db64ef | 6785 | { |
8cfb3407 VS |
6786 | struct drm_device *dev = crtc->base.dev; |
6787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6788 | ||
d330a953 | 6789 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6790 | hsw_crtc_supports_ips(crtc) && |
6791 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6792 | } |
6793 | ||
39acb4aa VS |
6794 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6795 | { | |
6796 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6797 | ||
6798 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6799 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6800 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6801 | } | |
6802 | ||
a43f6e0f | 6803 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6804 | struct intel_crtc_state *pipe_config) |
79e53945 | 6805 | { |
a43f6e0f | 6806 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6807 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6808 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6809 | |
ad3a4479 | 6810 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6811 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6812 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6813 | |
6814 | /* | |
39acb4aa | 6815 | * Enable double wide mode when the dot clock |
cf532bb2 | 6816 | * is > 90% of the (display) core speed. |
cf532bb2 | 6817 | */ |
39acb4aa VS |
6818 | if (intel_crtc_supports_double_wide(crtc) && |
6819 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6820 | clock_limit *= 2; |
cf532bb2 | 6821 | pipe_config->double_wide = true; |
ad3a4479 VS |
6822 | } |
6823 | ||
39acb4aa VS |
6824 | if (adjusted_mode->crtc_clock > clock_limit) { |
6825 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6826 | adjusted_mode->crtc_clock, clock_limit, | |
6827 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6828 | return -EINVAL; |
39acb4aa | 6829 | } |
2c07245f | 6830 | } |
89749350 | 6831 | |
1d1d0e27 VS |
6832 | /* |
6833 | * Pipe horizontal size must be even in: | |
6834 | * - DVO ganged mode | |
6835 | * - LVDS dual channel mode | |
6836 | * - Double wide pipe | |
6837 | */ | |
a93e255f | 6838 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6839 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6840 | pipe_config->pipe_src_w &= ~1; | |
6841 | ||
8693a824 DL |
6842 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6843 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6844 | */ |
6845 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6846 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6847 | return -EINVAL; |
44f46b42 | 6848 | |
f5adf94e | 6849 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6850 | hsw_compute_ips_config(crtc, pipe_config); |
6851 | ||
877d48d5 | 6852 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6853 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6854 | |
cf5a15be | 6855 | return 0; |
79e53945 JB |
6856 | } |
6857 | ||
1652d19e VS |
6858 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6859 | { | |
6860 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6861 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6862 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6863 | uint32_t linkrate; | |
6864 | ||
414355a7 | 6865 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6866 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6867 | |
6868 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6869 | return 540000; | |
6870 | ||
6871 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6872 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6873 | |
71cd8423 DL |
6874 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6875 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6876 | /* vco 8640 */ |
6877 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6878 | case CDCLK_FREQ_450_432: | |
6879 | return 432000; | |
6880 | case CDCLK_FREQ_337_308: | |
6881 | return 308570; | |
6882 | case CDCLK_FREQ_675_617: | |
6883 | return 617140; | |
6884 | default: | |
6885 | WARN(1, "Unknown cd freq selection\n"); | |
6886 | } | |
6887 | } else { | |
6888 | /* vco 8100 */ | |
6889 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6890 | case CDCLK_FREQ_450_432: | |
6891 | return 450000; | |
6892 | case CDCLK_FREQ_337_308: | |
6893 | return 337500; | |
6894 | case CDCLK_FREQ_675_617: | |
6895 | return 675000; | |
6896 | default: | |
6897 | WARN(1, "Unknown cd freq selection\n"); | |
6898 | } | |
6899 | } | |
6900 | ||
6901 | /* error case, do as if DPLL0 isn't enabled */ | |
6902 | return 24000; | |
6903 | } | |
6904 | ||
acd3f3d3 BP |
6905 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6906 | { | |
6907 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6908 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6909 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6910 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6911 | int cdclk; | |
6912 | ||
6913 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6914 | return 19200; | |
6915 | ||
6916 | cdclk = 19200 * pll_ratio / 2; | |
6917 | ||
6918 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6919 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6920 | return cdclk; /* 576MHz or 624MHz */ | |
6921 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6922 | return cdclk * 2 / 3; /* 384MHz */ | |
6923 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6924 | return cdclk / 2; /* 288MHz */ | |
6925 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6926 | return cdclk / 4; /* 144MHz */ | |
6927 | } | |
6928 | ||
6929 | /* error case, do as if DE PLL isn't enabled */ | |
6930 | return 19200; | |
6931 | } | |
6932 | ||
1652d19e VS |
6933 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6934 | { | |
6935 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6936 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6937 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6938 | ||
6939 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6940 | return 800000; | |
6941 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6942 | return 450000; | |
6943 | else if (freq == LCPLL_CLK_FREQ_450) | |
6944 | return 450000; | |
6945 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6946 | return 540000; | |
6947 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6948 | return 337500; | |
6949 | else | |
6950 | return 675000; | |
6951 | } | |
6952 | ||
6953 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6954 | { | |
6955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6956 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6957 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6958 | ||
6959 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6960 | return 800000; | |
6961 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6962 | return 450000; | |
6963 | else if (freq == LCPLL_CLK_FREQ_450) | |
6964 | return 450000; | |
6965 | else if (IS_HSW_ULT(dev)) | |
6966 | return 337500; | |
6967 | else | |
6968 | return 540000; | |
79e53945 JB |
6969 | } |
6970 | ||
25eb05fc JB |
6971 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6972 | { | |
bfa7df01 VS |
6973 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6974 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6975 | } |
6976 | ||
b37a6434 VS |
6977 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6978 | { | |
6979 | return 450000; | |
6980 | } | |
6981 | ||
e70236a8 JB |
6982 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6983 | { | |
6984 | return 400000; | |
6985 | } | |
79e53945 | 6986 | |
e70236a8 | 6987 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6988 | { |
e907f170 | 6989 | return 333333; |
e70236a8 | 6990 | } |
79e53945 | 6991 | |
e70236a8 JB |
6992 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6993 | { | |
6994 | return 200000; | |
6995 | } | |
79e53945 | 6996 | |
257a7ffc DV |
6997 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6998 | { | |
6999 | u16 gcfgc = 0; | |
7000 | ||
7001 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
7002 | ||
7003 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7004 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 7005 | return 266667; |
257a7ffc | 7006 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 7007 | return 333333; |
257a7ffc | 7008 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 7009 | return 444444; |
257a7ffc DV |
7010 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
7011 | return 200000; | |
7012 | default: | |
7013 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
7014 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 7015 | return 133333; |
257a7ffc | 7016 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 7017 | return 166667; |
257a7ffc DV |
7018 | } |
7019 | } | |
7020 | ||
e70236a8 JB |
7021 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
7022 | { | |
7023 | u16 gcfgc = 0; | |
79e53945 | 7024 | |
e70236a8 JB |
7025 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
7026 | ||
7027 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 7028 | return 133333; |
e70236a8 JB |
7029 | else { |
7030 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7031 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 7032 | return 333333; |
e70236a8 JB |
7033 | default: |
7034 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
7035 | return 190000; | |
79e53945 | 7036 | } |
e70236a8 JB |
7037 | } |
7038 | } | |
7039 | ||
7040 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
7041 | { | |
e907f170 | 7042 | return 266667; |
e70236a8 JB |
7043 | } |
7044 | ||
1b1d2716 | 7045 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
7046 | { |
7047 | u16 hpllcc = 0; | |
1b1d2716 | 7048 | |
65cd2b3f VS |
7049 | /* |
7050 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
7051 | * encoding is different :( | |
7052 | * FIXME is this the right way to detect 852GM/852GMV? | |
7053 | */ | |
7054 | if (dev->pdev->revision == 0x1) | |
7055 | return 133333; | |
7056 | ||
1b1d2716 VS |
7057 | pci_bus_read_config_word(dev->pdev->bus, |
7058 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
7059 | ||
e70236a8 JB |
7060 | /* Assume that the hardware is in the high speed state. This |
7061 | * should be the default. | |
7062 | */ | |
7063 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
7064 | case GC_CLOCK_133_200: | |
1b1d2716 | 7065 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
7066 | case GC_CLOCK_100_200: |
7067 | return 200000; | |
7068 | case GC_CLOCK_166_250: | |
7069 | return 250000; | |
7070 | case GC_CLOCK_100_133: | |
e907f170 | 7071 | return 133333; |
1b1d2716 VS |
7072 | case GC_CLOCK_133_266: |
7073 | case GC_CLOCK_133_266_2: | |
7074 | case GC_CLOCK_166_266: | |
7075 | return 266667; | |
e70236a8 | 7076 | } |
79e53945 | 7077 | |
e70236a8 JB |
7078 | /* Shouldn't happen */ |
7079 | return 0; | |
7080 | } | |
79e53945 | 7081 | |
e70236a8 JB |
7082 | static int i830_get_display_clock_speed(struct drm_device *dev) |
7083 | { | |
e907f170 | 7084 | return 133333; |
79e53945 JB |
7085 | } |
7086 | ||
34edce2f VS |
7087 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
7088 | { | |
7089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7090 | static const unsigned int blb_vco[8] = { | |
7091 | [0] = 3200000, | |
7092 | [1] = 4000000, | |
7093 | [2] = 5333333, | |
7094 | [3] = 4800000, | |
7095 | [4] = 6400000, | |
7096 | }; | |
7097 | static const unsigned int pnv_vco[8] = { | |
7098 | [0] = 3200000, | |
7099 | [1] = 4000000, | |
7100 | [2] = 5333333, | |
7101 | [3] = 4800000, | |
7102 | [4] = 2666667, | |
7103 | }; | |
7104 | static const unsigned int cl_vco[8] = { | |
7105 | [0] = 3200000, | |
7106 | [1] = 4000000, | |
7107 | [2] = 5333333, | |
7108 | [3] = 6400000, | |
7109 | [4] = 3333333, | |
7110 | [5] = 3566667, | |
7111 | [6] = 4266667, | |
7112 | }; | |
7113 | static const unsigned int elk_vco[8] = { | |
7114 | [0] = 3200000, | |
7115 | [1] = 4000000, | |
7116 | [2] = 5333333, | |
7117 | [3] = 4800000, | |
7118 | }; | |
7119 | static const unsigned int ctg_vco[8] = { | |
7120 | [0] = 3200000, | |
7121 | [1] = 4000000, | |
7122 | [2] = 5333333, | |
7123 | [3] = 6400000, | |
7124 | [4] = 2666667, | |
7125 | [5] = 4266667, | |
7126 | }; | |
7127 | const unsigned int *vco_table; | |
7128 | unsigned int vco; | |
7129 | uint8_t tmp = 0; | |
7130 | ||
7131 | /* FIXME other chipsets? */ | |
7132 | if (IS_GM45(dev)) | |
7133 | vco_table = ctg_vco; | |
7134 | else if (IS_G4X(dev)) | |
7135 | vco_table = elk_vco; | |
7136 | else if (IS_CRESTLINE(dev)) | |
7137 | vco_table = cl_vco; | |
7138 | else if (IS_PINEVIEW(dev)) | |
7139 | vco_table = pnv_vco; | |
7140 | else if (IS_G33(dev)) | |
7141 | vco_table = blb_vco; | |
7142 | else | |
7143 | return 0; | |
7144 | ||
7145 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7146 | ||
7147 | vco = vco_table[tmp & 0x7]; | |
7148 | if (vco == 0) | |
7149 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7150 | else | |
7151 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7152 | ||
7153 | return vco; | |
7154 | } | |
7155 | ||
7156 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7157 | { | |
7158 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7159 | uint16_t tmp = 0; | |
7160 | ||
7161 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7162 | ||
7163 | cdclk_sel = (tmp >> 12) & 0x1; | |
7164 | ||
7165 | switch (vco) { | |
7166 | case 2666667: | |
7167 | case 4000000: | |
7168 | case 5333333: | |
7169 | return cdclk_sel ? 333333 : 222222; | |
7170 | case 3200000: | |
7171 | return cdclk_sel ? 320000 : 228571; | |
7172 | default: | |
7173 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7174 | return 222222; | |
7175 | } | |
7176 | } | |
7177 | ||
7178 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7179 | { | |
7180 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7181 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7182 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7183 | const uint8_t *div_table; | |
7184 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7185 | uint16_t tmp = 0; | |
7186 | ||
7187 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7188 | ||
7189 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7190 | ||
7191 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7192 | goto fail; | |
7193 | ||
7194 | switch (vco) { | |
7195 | case 3200000: | |
7196 | div_table = div_3200; | |
7197 | break; | |
7198 | case 4000000: | |
7199 | div_table = div_4000; | |
7200 | break; | |
7201 | case 5333333: | |
7202 | div_table = div_5333; | |
7203 | break; | |
7204 | default: | |
7205 | goto fail; | |
7206 | } | |
7207 | ||
7208 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7209 | ||
caf4e252 | 7210 | fail: |
34edce2f VS |
7211 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7212 | return 200000; | |
7213 | } | |
7214 | ||
7215 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7216 | { | |
7217 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7218 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7219 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7220 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7221 | const uint8_t *div_table; | |
7222 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7223 | uint16_t tmp = 0; | |
7224 | ||
7225 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7226 | ||
7227 | cdclk_sel = (tmp >> 4) & 0x7; | |
7228 | ||
7229 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7230 | goto fail; | |
7231 | ||
7232 | switch (vco) { | |
7233 | case 3200000: | |
7234 | div_table = div_3200; | |
7235 | break; | |
7236 | case 4000000: | |
7237 | div_table = div_4000; | |
7238 | break; | |
7239 | case 4800000: | |
7240 | div_table = div_4800; | |
7241 | break; | |
7242 | case 5333333: | |
7243 | div_table = div_5333; | |
7244 | break; | |
7245 | default: | |
7246 | goto fail; | |
7247 | } | |
7248 | ||
7249 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7250 | ||
caf4e252 | 7251 | fail: |
34edce2f VS |
7252 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7253 | return 190476; | |
7254 | } | |
7255 | ||
2c07245f | 7256 | static void |
a65851af | 7257 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7258 | { |
a65851af VS |
7259 | while (*num > DATA_LINK_M_N_MASK || |
7260 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7261 | *num >>= 1; |
7262 | *den >>= 1; | |
7263 | } | |
7264 | } | |
7265 | ||
a65851af VS |
7266 | static void compute_m_n(unsigned int m, unsigned int n, |
7267 | uint32_t *ret_m, uint32_t *ret_n) | |
7268 | { | |
7269 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7270 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7271 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7272 | } | |
7273 | ||
e69d0bc1 DV |
7274 | void |
7275 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7276 | int pixel_clock, int link_clock, | |
7277 | struct intel_link_m_n *m_n) | |
2c07245f | 7278 | { |
e69d0bc1 | 7279 | m_n->tu = 64; |
a65851af VS |
7280 | |
7281 | compute_m_n(bits_per_pixel * pixel_clock, | |
7282 | link_clock * nlanes * 8, | |
7283 | &m_n->gmch_m, &m_n->gmch_n); | |
7284 | ||
7285 | compute_m_n(pixel_clock, link_clock, | |
7286 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7287 | } |
7288 | ||
a7615030 CW |
7289 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7290 | { | |
d330a953 JN |
7291 | if (i915.panel_use_ssc >= 0) |
7292 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7293 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7294 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7295 | } |
7296 | ||
a93e255f ACO |
7297 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7298 | int num_connectors) | |
c65d77d8 | 7299 | { |
a93e255f | 7300 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7301 | struct drm_i915_private *dev_priv = dev->dev_private; |
7302 | int refclk; | |
7303 | ||
a93e255f ACO |
7304 | WARN_ON(!crtc_state->base.state); |
7305 | ||
666a4537 | 7306 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7307 | refclk = 100000; |
a93e255f | 7308 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7309 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7310 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7311 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7312 | } else if (!IS_GEN2(dev)) { |
7313 | refclk = 96000; | |
7314 | } else { | |
7315 | refclk = 48000; | |
7316 | } | |
7317 | ||
7318 | return refclk; | |
7319 | } | |
7320 | ||
7429e9d4 | 7321 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7322 | { |
7df00d7a | 7323 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7324 | } |
f47709a9 | 7325 | |
7429e9d4 DV |
7326 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7327 | { | |
7328 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7329 | } |
7330 | ||
f47709a9 | 7331 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7332 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7333 | intel_clock_t *reduced_clock) |
7334 | { | |
f47709a9 | 7335 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7336 | u32 fp, fp2 = 0; |
7337 | ||
7338 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7339 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7340 | if (reduced_clock) |
7429e9d4 | 7341 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7342 | } else { |
190f68c5 | 7343 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7344 | if (reduced_clock) |
7429e9d4 | 7345 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7346 | } |
7347 | ||
190f68c5 | 7348 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7349 | |
f47709a9 | 7350 | crtc->lowfreq_avail = false; |
a93e255f | 7351 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7352 | reduced_clock) { |
190f68c5 | 7353 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7354 | crtc->lowfreq_avail = true; |
a7516a05 | 7355 | } else { |
190f68c5 | 7356 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7357 | } |
7358 | } | |
7359 | ||
5e69f97f CML |
7360 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7361 | pipe) | |
89b667f8 JB |
7362 | { |
7363 | u32 reg_val; | |
7364 | ||
7365 | /* | |
7366 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7367 | * and set it to a reasonable value instead. | |
7368 | */ | |
ab3c759a | 7369 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7370 | reg_val &= 0xffffff00; |
7371 | reg_val |= 0x00000030; | |
ab3c759a | 7372 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7373 | |
ab3c759a | 7374 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7375 | reg_val &= 0x8cffffff; |
7376 | reg_val = 0x8c000000; | |
ab3c759a | 7377 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7378 | |
ab3c759a | 7379 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7380 | reg_val &= 0xffffff00; |
ab3c759a | 7381 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7382 | |
ab3c759a | 7383 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7384 | reg_val &= 0x00ffffff; |
7385 | reg_val |= 0xb0000000; | |
ab3c759a | 7386 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7387 | } |
7388 | ||
b551842d DV |
7389 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7390 | struct intel_link_m_n *m_n) | |
7391 | { | |
7392 | struct drm_device *dev = crtc->base.dev; | |
7393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7394 | int pipe = crtc->pipe; | |
7395 | ||
e3b95f1e DV |
7396 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7397 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7398 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7399 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7400 | } |
7401 | ||
7402 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7403 | struct intel_link_m_n *m_n, |
7404 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7405 | { |
7406 | struct drm_device *dev = crtc->base.dev; | |
7407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7408 | int pipe = crtc->pipe; | |
6e3c9717 | 7409 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7410 | |
7411 | if (INTEL_INFO(dev)->gen >= 5) { | |
7412 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7413 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7414 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7415 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7416 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7417 | * for gen < 8) and if DRRS is supported (to make sure the | |
7418 | * registers are not unnecessarily accessed). | |
7419 | */ | |
44395bfe | 7420 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7421 | crtc->config->has_drrs) { |
f769cd24 VK |
7422 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7423 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7424 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7425 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7426 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7427 | } | |
b551842d | 7428 | } else { |
e3b95f1e DV |
7429 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7430 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7431 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7432 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7433 | } |
7434 | } | |
7435 | ||
fe3cd48d | 7436 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7437 | { |
fe3cd48d R |
7438 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7439 | ||
7440 | if (m_n == M1_N1) { | |
7441 | dp_m_n = &crtc->config->dp_m_n; | |
7442 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7443 | } else if (m_n == M2_N2) { | |
7444 | ||
7445 | /* | |
7446 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7447 | * needs to be programmed into M1_N1. | |
7448 | */ | |
7449 | dp_m_n = &crtc->config->dp_m2_n2; | |
7450 | } else { | |
7451 | DRM_ERROR("Unsupported divider value\n"); | |
7452 | return; | |
7453 | } | |
7454 | ||
6e3c9717 ACO |
7455 | if (crtc->config->has_pch_encoder) |
7456 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7457 | else |
fe3cd48d | 7458 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7459 | } |
7460 | ||
251ac862 DV |
7461 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7462 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7463 | { |
7464 | u32 dpll, dpll_md; | |
7465 | ||
7466 | /* | |
7467 | * Enable DPIO clock input. We should never disable the reference | |
7468 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7469 | * on it. | |
7470 | */ | |
60bfe44f VS |
7471 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7472 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7473 | /* We should never disable this, set it here for state tracking */ |
7474 | if (crtc->pipe == PIPE_B) | |
7475 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7476 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7477 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7478 | |
d288f65f | 7479 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7480 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7481 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7482 | } |
7483 | ||
d288f65f | 7484 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7485 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7486 | { |
f47709a9 | 7487 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7488 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7489 | int pipe = crtc->pipe; |
bdd4b6a6 | 7490 | u32 mdiv; |
a0c4da24 | 7491 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7492 | u32 coreclk, reg_val; |
a0c4da24 | 7493 | |
a580516d | 7494 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7495 | |
d288f65f VS |
7496 | bestn = pipe_config->dpll.n; |
7497 | bestm1 = pipe_config->dpll.m1; | |
7498 | bestm2 = pipe_config->dpll.m2; | |
7499 | bestp1 = pipe_config->dpll.p1; | |
7500 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7501 | |
89b667f8 JB |
7502 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7503 | ||
7504 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7505 | if (pipe == PIPE_B) |
5e69f97f | 7506 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7507 | |
7508 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7509 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7510 | |
7511 | /* Disable target IRef on PLL */ | |
ab3c759a | 7512 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7513 | reg_val &= 0x00ffffff; |
ab3c759a | 7514 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7515 | |
7516 | /* Disable fast lock */ | |
ab3c759a | 7517 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7518 | |
7519 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7520 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7521 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7522 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7523 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7524 | |
7525 | /* | |
7526 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7527 | * but we don't support that). | |
7528 | * Note: don't use the DAC post divider as it seems unstable. | |
7529 | */ | |
7530 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7531 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7532 | |
a0c4da24 | 7533 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7534 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7535 | |
89b667f8 | 7536 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7537 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7538 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7539 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7540 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7541 | 0x009f0003); |
89b667f8 | 7542 | else |
ab3c759a | 7543 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7544 | 0x00d0000f); |
7545 | ||
681a8504 | 7546 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7547 | /* Use SSC source */ |
bdd4b6a6 | 7548 | if (pipe == PIPE_A) |
ab3c759a | 7549 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7550 | 0x0df40000); |
7551 | else | |
ab3c759a | 7552 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7553 | 0x0df70000); |
7554 | } else { /* HDMI or VGA */ | |
7555 | /* Use bend source */ | |
bdd4b6a6 | 7556 | if (pipe == PIPE_A) |
ab3c759a | 7557 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7558 | 0x0df70000); |
7559 | else | |
ab3c759a | 7560 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7561 | 0x0df40000); |
7562 | } | |
a0c4da24 | 7563 | |
ab3c759a | 7564 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7565 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7566 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7567 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7568 | coreclk |= 0x01000000; |
ab3c759a | 7569 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7570 | |
ab3c759a | 7571 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7572 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7573 | } |
7574 | ||
251ac862 DV |
7575 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7576 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7577 | { |
60bfe44f VS |
7578 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7579 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7580 | DPLL_VCO_ENABLE; |
7581 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7582 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7583 | |
d288f65f VS |
7584 | pipe_config->dpll_hw_state.dpll_md = |
7585 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7586 | } |
7587 | ||
d288f65f | 7588 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7589 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7590 | { |
7591 | struct drm_device *dev = crtc->base.dev; | |
7592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7593 | int pipe = crtc->pipe; | |
f0f59a00 | 7594 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7595 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7596 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7597 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7598 | u32 dpio_val; |
9cbe40c1 | 7599 | int vco; |
9d556c99 | 7600 | |
d288f65f VS |
7601 | bestn = pipe_config->dpll.n; |
7602 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7603 | bestm1 = pipe_config->dpll.m1; | |
7604 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7605 | bestp1 = pipe_config->dpll.p1; | |
7606 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7607 | vco = pipe_config->dpll.vco; |
a945ce7e | 7608 | dpio_val = 0; |
9cbe40c1 | 7609 | loopfilter = 0; |
9d556c99 CML |
7610 | |
7611 | /* | |
7612 | * Enable Refclk and SSC | |
7613 | */ | |
a11b0703 | 7614 | I915_WRITE(dpll_reg, |
d288f65f | 7615 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7616 | |
a580516d | 7617 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7618 | |
9d556c99 CML |
7619 | /* p1 and p2 divider */ |
7620 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7621 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7622 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7623 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7624 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7625 | ||
7626 | /* Feedback post-divider - m2 */ | |
7627 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7628 | ||
7629 | /* Feedback refclk divider - n and m1 */ | |
7630 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7631 | DPIO_CHV_M1_DIV_BY_2 | | |
7632 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7633 | ||
7634 | /* M2 fraction division */ | |
25a25dfc | 7635 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7636 | |
7637 | /* M2 fraction division enable */ | |
a945ce7e VP |
7638 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7639 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7640 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7641 | if (bestm2_frac) | |
7642 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7643 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7644 | |
de3a0fde VP |
7645 | /* Program digital lock detect threshold */ |
7646 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7647 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7648 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7649 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7650 | if (!bestm2_frac) | |
7651 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7652 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7653 | ||
9d556c99 | 7654 | /* Loop filter */ |
9cbe40c1 VP |
7655 | if (vco == 5400000) { |
7656 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7657 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7658 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7659 | tribuf_calcntr = 0x9; | |
7660 | } else if (vco <= 6200000) { | |
7661 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7662 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7663 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7664 | tribuf_calcntr = 0x9; | |
7665 | } else if (vco <= 6480000) { | |
7666 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7667 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7668 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7669 | tribuf_calcntr = 0x8; | |
7670 | } else { | |
7671 | /* Not supported. Apply the same limits as in the max case */ | |
7672 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7673 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7674 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7675 | tribuf_calcntr = 0; | |
7676 | } | |
9d556c99 CML |
7677 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7678 | ||
968040b2 | 7679 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7680 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7681 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7682 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7683 | ||
9d556c99 CML |
7684 | /* AFC Recal */ |
7685 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7686 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7687 | DPIO_AFC_RECAL); | |
7688 | ||
a580516d | 7689 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7690 | } |
7691 | ||
d288f65f VS |
7692 | /** |
7693 | * vlv_force_pll_on - forcibly enable just the PLL | |
7694 | * @dev_priv: i915 private structure | |
7695 | * @pipe: pipe PLL to enable | |
7696 | * @dpll: PLL configuration | |
7697 | * | |
7698 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7699 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7700 | * be enabled. | |
7701 | */ | |
3f36b937 TU |
7702 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7703 | const struct dpll *dpll) | |
d288f65f VS |
7704 | { |
7705 | struct intel_crtc *crtc = | |
7706 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7707 | struct intel_crtc_state *pipe_config; |
7708 | ||
7709 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7710 | if (!pipe_config) | |
7711 | return -ENOMEM; | |
7712 | ||
7713 | pipe_config->base.crtc = &crtc->base; | |
7714 | pipe_config->pixel_multiplier = 1; | |
7715 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7716 | |
7717 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7718 | chv_compute_dpll(crtc, pipe_config); |
7719 | chv_prepare_pll(crtc, pipe_config); | |
7720 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7721 | } else { |
3f36b937 TU |
7722 | vlv_compute_dpll(crtc, pipe_config); |
7723 | vlv_prepare_pll(crtc, pipe_config); | |
7724 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7725 | } |
3f36b937 TU |
7726 | |
7727 | kfree(pipe_config); | |
7728 | ||
7729 | return 0; | |
d288f65f VS |
7730 | } |
7731 | ||
7732 | /** | |
7733 | * vlv_force_pll_off - forcibly disable just the PLL | |
7734 | * @dev_priv: i915 private structure | |
7735 | * @pipe: pipe PLL to disable | |
7736 | * | |
7737 | * Disable the PLL for @pipe. To be used in cases where we need | |
7738 | * the PLL enabled even when @pipe is not going to be enabled. | |
7739 | */ | |
7740 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7741 | { | |
7742 | if (IS_CHERRYVIEW(dev)) | |
7743 | chv_disable_pll(to_i915(dev), pipe); | |
7744 | else | |
7745 | vlv_disable_pll(to_i915(dev), pipe); | |
7746 | } | |
7747 | ||
251ac862 DV |
7748 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7749 | struct intel_crtc_state *crtc_state, | |
7750 | intel_clock_t *reduced_clock, | |
7751 | int num_connectors) | |
eb1cbe48 | 7752 | { |
f47709a9 | 7753 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7754 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7755 | u32 dpll; |
7756 | bool is_sdvo; | |
190f68c5 | 7757 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7758 | |
190f68c5 | 7759 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7760 | |
a93e255f ACO |
7761 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7762 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7763 | |
7764 | dpll = DPLL_VGA_MODE_DIS; | |
7765 | ||
a93e255f | 7766 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7767 | dpll |= DPLLB_MODE_LVDS; |
7768 | else | |
7769 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7770 | |
ef1b460d | 7771 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7772 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7773 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7774 | } |
198a037f DV |
7775 | |
7776 | if (is_sdvo) | |
4a33e48d | 7777 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7778 | |
190f68c5 | 7779 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7780 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7781 | |
7782 | /* compute bitmask from p1 value */ | |
7783 | if (IS_PINEVIEW(dev)) | |
7784 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7785 | else { | |
7786 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7787 | if (IS_G4X(dev) && reduced_clock) | |
7788 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7789 | } | |
7790 | switch (clock->p2) { | |
7791 | case 5: | |
7792 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7793 | break; | |
7794 | case 7: | |
7795 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7796 | break; | |
7797 | case 10: | |
7798 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7799 | break; | |
7800 | case 14: | |
7801 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7802 | break; | |
7803 | } | |
7804 | if (INTEL_INFO(dev)->gen >= 4) | |
7805 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7806 | ||
190f68c5 | 7807 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7808 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7809 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7810 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7811 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7812 | else | |
7813 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7814 | ||
7815 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7816 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7817 | |
eb1cbe48 | 7818 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7819 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7820 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7821 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7822 | } |
7823 | } | |
7824 | ||
251ac862 DV |
7825 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7826 | struct intel_crtc_state *crtc_state, | |
7827 | intel_clock_t *reduced_clock, | |
7828 | int num_connectors) | |
eb1cbe48 | 7829 | { |
f47709a9 | 7830 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7831 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7832 | u32 dpll; |
190f68c5 | 7833 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7834 | |
190f68c5 | 7835 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7836 | |
eb1cbe48 DV |
7837 | dpll = DPLL_VGA_MODE_DIS; |
7838 | ||
a93e255f | 7839 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7840 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7841 | } else { | |
7842 | if (clock->p1 == 2) | |
7843 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7844 | else | |
7845 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7846 | if (clock->p2 == 4) | |
7847 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7848 | } | |
7849 | ||
a93e255f | 7850 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7851 | dpll |= DPLL_DVO_2X_MODE; |
7852 | ||
a93e255f | 7853 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7854 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7855 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7856 | else | |
7857 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7858 | ||
7859 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7860 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7861 | } |
7862 | ||
8a654f3b | 7863 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7864 | { |
7865 | struct drm_device *dev = intel_crtc->base.dev; | |
7866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7867 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7868 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7869 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7870 | uint32_t crtc_vtotal, crtc_vblank_end; |
7871 | int vsyncshift = 0; | |
4d8a62ea DV |
7872 | |
7873 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7874 | * the hw state checker will get angry at the mismatch. */ | |
7875 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7876 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7877 | |
609aeaca | 7878 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7879 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7880 | crtc_vtotal -= 1; |
7881 | crtc_vblank_end -= 1; | |
609aeaca | 7882 | |
409ee761 | 7883 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7884 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7885 | else | |
7886 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7887 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7888 | if (vsyncshift < 0) |
7889 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7890 | } |
7891 | ||
7892 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7893 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7894 | |
fe2b8f9d | 7895 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7896 | (adjusted_mode->crtc_hdisplay - 1) | |
7897 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7898 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7899 | (adjusted_mode->crtc_hblank_start - 1) | |
7900 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7901 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7902 | (adjusted_mode->crtc_hsync_start - 1) | |
7903 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7904 | ||
fe2b8f9d | 7905 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7906 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7907 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7908 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7909 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7910 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7911 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7912 | (adjusted_mode->crtc_vsync_start - 1) | |
7913 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7914 | ||
b5e508d4 PZ |
7915 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7916 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7917 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7918 | * bits. */ | |
7919 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7920 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7921 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7922 | ||
b0e77b9c PZ |
7923 | /* pipesrc controls the size that is scaled from, which should |
7924 | * always be the user's requested size. | |
7925 | */ | |
7926 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7927 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7928 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7929 | } |
7930 | ||
1bd1bd80 | 7931 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7932 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7933 | { |
7934 | struct drm_device *dev = crtc->base.dev; | |
7935 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7936 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7937 | uint32_t tmp; | |
7938 | ||
7939 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7940 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7941 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7942 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7943 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7944 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7945 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7946 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7947 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7948 | |
7949 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7950 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7951 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7952 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7953 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7954 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7955 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7956 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7957 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7958 | |
7959 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7960 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7961 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7962 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7963 | } |
7964 | ||
7965 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7966 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7967 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7968 | ||
2d112de7 ACO |
7969 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7970 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7971 | } |
7972 | ||
f6a83288 | 7973 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7974 | struct intel_crtc_state *pipe_config) |
babea61d | 7975 | { |
2d112de7 ACO |
7976 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7977 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7978 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7979 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7980 | |
2d112de7 ACO |
7981 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7982 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7983 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7984 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7985 | |
2d112de7 | 7986 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7987 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7988 | |
2d112de7 ACO |
7989 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7990 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7991 | |
7992 | mode->hsync = drm_mode_hsync(mode); | |
7993 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7994 | drm_mode_set_name(mode); | |
babea61d JB |
7995 | } |
7996 | ||
84b046f3 DV |
7997 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7998 | { | |
7999 | struct drm_device *dev = intel_crtc->base.dev; | |
8000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8001 | uint32_t pipeconf; | |
8002 | ||
9f11a9e4 | 8003 | pipeconf = 0; |
84b046f3 | 8004 | |
b6b5d049 VS |
8005 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
8006 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8007 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 8008 | |
6e3c9717 | 8009 | if (intel_crtc->config->double_wide) |
cf532bb2 | 8010 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 8011 | |
ff9ce46e | 8012 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 8013 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 8014 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 8015 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 8016 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 8017 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 8018 | |
6e3c9717 | 8019 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
8020 | case 18: |
8021 | pipeconf |= PIPECONF_6BPC; | |
8022 | break; | |
8023 | case 24: | |
8024 | pipeconf |= PIPECONF_8BPC; | |
8025 | break; | |
8026 | case 30: | |
8027 | pipeconf |= PIPECONF_10BPC; | |
8028 | break; | |
8029 | default: | |
8030 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
8031 | BUG(); | |
84b046f3 DV |
8032 | } |
8033 | } | |
8034 | ||
8035 | if (HAS_PIPE_CXSR(dev)) { | |
8036 | if (intel_crtc->lowfreq_avail) { | |
8037 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
8038 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
8039 | } else { | |
8040 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
8041 | } |
8042 | } | |
8043 | ||
6e3c9717 | 8044 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 8045 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 8046 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
8047 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
8048 | else | |
8049 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
8050 | } else | |
84b046f3 DV |
8051 | pipeconf |= PIPECONF_PROGRESSIVE; |
8052 | ||
666a4537 WB |
8053 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8054 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 8055 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 8056 | |
84b046f3 DV |
8057 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
8058 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
8059 | } | |
8060 | ||
190f68c5 ACO |
8061 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8062 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8063 | { |
c7653199 | 8064 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8065 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 8066 | int refclk, num_connectors = 0; |
c329a4ec DV |
8067 | intel_clock_t clock; |
8068 | bool ok; | |
d4906093 | 8069 | const intel_limit_t *limit; |
55bb9992 | 8070 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8071 | struct drm_connector *connector; |
55bb9992 ACO |
8072 | struct drm_connector_state *connector_state; |
8073 | int i; | |
79e53945 | 8074 | |
dd3cd74a ACO |
8075 | memset(&crtc_state->dpll_hw_state, 0, |
8076 | sizeof(crtc_state->dpll_hw_state)); | |
8077 | ||
a65347ba JN |
8078 | if (crtc_state->has_dsi_encoder) |
8079 | return 0; | |
43565a06 | 8080 | |
a65347ba JN |
8081 | for_each_connector_in_state(state, connector, connector_state, i) { |
8082 | if (connector_state->crtc == &crtc->base) | |
8083 | num_connectors++; | |
79e53945 JB |
8084 | } |
8085 | ||
190f68c5 | 8086 | if (!crtc_state->clock_set) { |
a93e255f | 8087 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 8088 | |
e9fd1c02 JN |
8089 | /* |
8090 | * Returns a set of divisors for the desired target clock with | |
8091 | * the given refclk, or FALSE. The returned values represent | |
8092 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
8093 | * 2) / p1 / p2. | |
8094 | */ | |
a93e255f ACO |
8095 | limit = intel_limit(crtc_state, refclk); |
8096 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8097 | crtc_state->port_clock, |
e9fd1c02 | 8098 | refclk, NULL, &clock); |
f2335330 | 8099 | if (!ok) { |
e9fd1c02 JN |
8100 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8101 | return -EINVAL; | |
8102 | } | |
79e53945 | 8103 | |
f2335330 | 8104 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8105 | crtc_state->dpll.n = clock.n; |
8106 | crtc_state->dpll.m1 = clock.m1; | |
8107 | crtc_state->dpll.m2 = clock.m2; | |
8108 | crtc_state->dpll.p1 = clock.p1; | |
8109 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8110 | } |
7026d4ac | 8111 | |
e9fd1c02 | 8112 | if (IS_GEN2(dev)) { |
c329a4ec | 8113 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8114 | num_connectors); |
9d556c99 | 8115 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 8116 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8117 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 8118 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8119 | } else { |
c329a4ec | 8120 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8121 | num_connectors); |
e9fd1c02 | 8122 | } |
79e53945 | 8123 | |
c8f7a0db | 8124 | return 0; |
f564048e EA |
8125 | } |
8126 | ||
2fa2fe9a | 8127 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8128 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8129 | { |
8130 | struct drm_device *dev = crtc->base.dev; | |
8131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8132 | uint32_t tmp; | |
8133 | ||
dc9e7dec VS |
8134 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8135 | return; | |
8136 | ||
2fa2fe9a | 8137 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8138 | if (!(tmp & PFIT_ENABLE)) |
8139 | return; | |
2fa2fe9a | 8140 | |
06922821 | 8141 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8142 | if (INTEL_INFO(dev)->gen < 4) { |
8143 | if (crtc->pipe != PIPE_B) | |
8144 | return; | |
2fa2fe9a DV |
8145 | } else { |
8146 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8147 | return; | |
8148 | } | |
8149 | ||
06922821 | 8150 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8151 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8152 | if (INTEL_INFO(dev)->gen < 5) | |
8153 | pipe_config->gmch_pfit.lvds_border_bits = | |
8154 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8155 | } | |
8156 | ||
acbec814 | 8157 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8158 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8159 | { |
8160 | struct drm_device *dev = crtc->base.dev; | |
8161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8162 | int pipe = pipe_config->cpu_transcoder; | |
8163 | intel_clock_t clock; | |
8164 | u32 mdiv; | |
662c6ecb | 8165 | int refclk = 100000; |
acbec814 | 8166 | |
f573de5a SK |
8167 | /* In case of MIPI DPLL will not even be used */ |
8168 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8169 | return; | |
8170 | ||
a580516d | 8171 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8172 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8173 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8174 | |
8175 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8176 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8177 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8178 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8179 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8180 | ||
dccbea3b | 8181 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8182 | } |
8183 | ||
5724dbd1 DL |
8184 | static void |
8185 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8186 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8187 | { |
8188 | struct drm_device *dev = crtc->base.dev; | |
8189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8190 | u32 val, base, offset; | |
8191 | int pipe = crtc->pipe, plane = crtc->plane; | |
8192 | int fourcc, pixel_format; | |
6761dd31 | 8193 | unsigned int aligned_height; |
b113d5ee | 8194 | struct drm_framebuffer *fb; |
1b842c89 | 8195 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8196 | |
42a7b088 DL |
8197 | val = I915_READ(DSPCNTR(plane)); |
8198 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8199 | return; | |
8200 | ||
d9806c9f | 8201 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8202 | if (!intel_fb) { |
1ad292b5 JB |
8203 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8204 | return; | |
8205 | } | |
8206 | ||
1b842c89 DL |
8207 | fb = &intel_fb->base; |
8208 | ||
18c5247e DV |
8209 | if (INTEL_INFO(dev)->gen >= 4) { |
8210 | if (val & DISPPLANE_TILED) { | |
49af449b | 8211 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8212 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8213 | } | |
8214 | } | |
1ad292b5 JB |
8215 | |
8216 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8217 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8218 | fb->pixel_format = fourcc; |
8219 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8220 | |
8221 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8222 | if (plane_config->tiling) |
1ad292b5 JB |
8223 | offset = I915_READ(DSPTILEOFF(plane)); |
8224 | else | |
8225 | offset = I915_READ(DSPLINOFF(plane)); | |
8226 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8227 | } else { | |
8228 | base = I915_READ(DSPADDR(plane)); | |
8229 | } | |
8230 | plane_config->base = base; | |
8231 | ||
8232 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8233 | fb->width = ((val >> 16) & 0xfff) + 1; |
8234 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8235 | |
8236 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8237 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8238 | |
b113d5ee | 8239 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8240 | fb->pixel_format, |
8241 | fb->modifier[0]); | |
1ad292b5 | 8242 | |
f37b5c2b | 8243 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8244 | |
2844a921 DL |
8245 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8246 | pipe_name(pipe), plane, fb->width, fb->height, | |
8247 | fb->bits_per_pixel, base, fb->pitches[0], | |
8248 | plane_config->size); | |
1ad292b5 | 8249 | |
2d14030b | 8250 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8251 | } |
8252 | ||
70b23a98 | 8253 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8254 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8255 | { |
8256 | struct drm_device *dev = crtc->base.dev; | |
8257 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8258 | int pipe = pipe_config->cpu_transcoder; | |
8259 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8260 | intel_clock_t clock; | |
0d7b6b11 | 8261 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8262 | int refclk = 100000; |
8263 | ||
a580516d | 8264 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8265 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8266 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8267 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8268 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8269 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8270 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8271 | |
8272 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8273 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8274 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8275 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8276 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8277 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8278 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8279 | ||
dccbea3b | 8280 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8281 | } |
8282 | ||
0e8ffe1b | 8283 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8284 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8285 | { |
8286 | struct drm_device *dev = crtc->base.dev; | |
8287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8288 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8289 | uint32_t tmp; |
1729050e | 8290 | bool ret; |
0e8ffe1b | 8291 | |
1729050e ID |
8292 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8293 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8294 | return false; |
8295 | ||
e143a21c | 8296 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8297 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8298 | |
1729050e ID |
8299 | ret = false; |
8300 | ||
0e8ffe1b DV |
8301 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8302 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8303 | goto out; |
0e8ffe1b | 8304 | |
666a4537 | 8305 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8306 | switch (tmp & PIPECONF_BPC_MASK) { |
8307 | case PIPECONF_6BPC: | |
8308 | pipe_config->pipe_bpp = 18; | |
8309 | break; | |
8310 | case PIPECONF_8BPC: | |
8311 | pipe_config->pipe_bpp = 24; | |
8312 | break; | |
8313 | case PIPECONF_10BPC: | |
8314 | pipe_config->pipe_bpp = 30; | |
8315 | break; | |
8316 | default: | |
8317 | break; | |
8318 | } | |
8319 | } | |
8320 | ||
666a4537 WB |
8321 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8322 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8323 | pipe_config->limited_color_range = true; |
8324 | ||
282740f7 VS |
8325 | if (INTEL_INFO(dev)->gen < 4) |
8326 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8327 | ||
1bd1bd80 DV |
8328 | intel_get_pipe_timings(crtc, pipe_config); |
8329 | ||
2fa2fe9a DV |
8330 | i9xx_get_pfit_config(crtc, pipe_config); |
8331 | ||
6c49f241 DV |
8332 | if (INTEL_INFO(dev)->gen >= 4) { |
8333 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8334 | pipe_config->pixel_multiplier = | |
8335 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8336 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8337 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8338 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8339 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8340 | pipe_config->pixel_multiplier = | |
8341 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8342 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8343 | } else { | |
8344 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8345 | * port and will be fixed up in the encoder->get_config | |
8346 | * function. */ | |
8347 | pipe_config->pixel_multiplier = 1; | |
8348 | } | |
8bcc2795 | 8349 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8350 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8351 | /* |
8352 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8353 | * on 830. Filter it out here so that we don't | |
8354 | * report errors due to that. | |
8355 | */ | |
8356 | if (IS_I830(dev)) | |
8357 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8358 | ||
8bcc2795 DV |
8359 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8360 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8361 | } else { |
8362 | /* Mask out read-only status bits. */ | |
8363 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8364 | DPLL_PORTC_READY_MASK | | |
8365 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8366 | } |
6c49f241 | 8367 | |
70b23a98 VS |
8368 | if (IS_CHERRYVIEW(dev)) |
8369 | chv_crtc_clock_get(crtc, pipe_config); | |
8370 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8371 | vlv_crtc_clock_get(crtc, pipe_config); |
8372 | else | |
8373 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8374 | |
0f64614d VS |
8375 | /* |
8376 | * Normally the dotclock is filled in by the encoder .get_config() | |
8377 | * but in case the pipe is enabled w/o any ports we need a sane | |
8378 | * default. | |
8379 | */ | |
8380 | pipe_config->base.adjusted_mode.crtc_clock = | |
8381 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8382 | ||
1729050e ID |
8383 | ret = true; |
8384 | ||
8385 | out: | |
8386 | intel_display_power_put(dev_priv, power_domain); | |
8387 | ||
8388 | return ret; | |
0e8ffe1b DV |
8389 | } |
8390 | ||
dde86e2d | 8391 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8392 | { |
8393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8394 | struct intel_encoder *encoder; |
74cfd7ac | 8395 | u32 val, final; |
13d83a67 | 8396 | bool has_lvds = false; |
199e5d79 | 8397 | bool has_cpu_edp = false; |
199e5d79 | 8398 | bool has_panel = false; |
99eb6a01 KP |
8399 | bool has_ck505 = false; |
8400 | bool can_ssc = false; | |
13d83a67 JB |
8401 | |
8402 | /* We need to take the global config into account */ | |
b2784e15 | 8403 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8404 | switch (encoder->type) { |
8405 | case INTEL_OUTPUT_LVDS: | |
8406 | has_panel = true; | |
8407 | has_lvds = true; | |
8408 | break; | |
8409 | case INTEL_OUTPUT_EDP: | |
8410 | has_panel = true; | |
2de6905f | 8411 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8412 | has_cpu_edp = true; |
8413 | break; | |
6847d71b PZ |
8414 | default: |
8415 | break; | |
13d83a67 JB |
8416 | } |
8417 | } | |
8418 | ||
99eb6a01 | 8419 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8420 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8421 | can_ssc = has_ck505; |
8422 | } else { | |
8423 | has_ck505 = false; | |
8424 | can_ssc = true; | |
8425 | } | |
8426 | ||
2de6905f ID |
8427 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8428 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8429 | |
8430 | /* Ironlake: try to setup display ref clock before DPLL | |
8431 | * enabling. This is only under driver's control after | |
8432 | * PCH B stepping, previous chipset stepping should be | |
8433 | * ignoring this setting. | |
8434 | */ | |
74cfd7ac CW |
8435 | val = I915_READ(PCH_DREF_CONTROL); |
8436 | ||
8437 | /* As we must carefully and slowly disable/enable each source in turn, | |
8438 | * compute the final state we want first and check if we need to | |
8439 | * make any changes at all. | |
8440 | */ | |
8441 | final = val; | |
8442 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8443 | if (has_ck505) | |
8444 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8445 | else | |
8446 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8447 | ||
8448 | final &= ~DREF_SSC_SOURCE_MASK; | |
8449 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8450 | final &= ~DREF_SSC1_ENABLE; | |
8451 | ||
8452 | if (has_panel) { | |
8453 | final |= DREF_SSC_SOURCE_ENABLE; | |
8454 | ||
8455 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8456 | final |= DREF_SSC1_ENABLE; | |
8457 | ||
8458 | if (has_cpu_edp) { | |
8459 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8460 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8461 | else | |
8462 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8463 | } else | |
8464 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8465 | } else { | |
8466 | final |= DREF_SSC_SOURCE_DISABLE; | |
8467 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8468 | } | |
8469 | ||
8470 | if (final == val) | |
8471 | return; | |
8472 | ||
13d83a67 | 8473 | /* Always enable nonspread source */ |
74cfd7ac | 8474 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8475 | |
99eb6a01 | 8476 | if (has_ck505) |
74cfd7ac | 8477 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8478 | else |
74cfd7ac | 8479 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8480 | |
199e5d79 | 8481 | if (has_panel) { |
74cfd7ac CW |
8482 | val &= ~DREF_SSC_SOURCE_MASK; |
8483 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8484 | |
199e5d79 | 8485 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8486 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8487 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8488 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8489 | } else |
74cfd7ac | 8490 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8491 | |
8492 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8493 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8494 | POSTING_READ(PCH_DREF_CONTROL); |
8495 | udelay(200); | |
8496 | ||
74cfd7ac | 8497 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8498 | |
8499 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8500 | if (has_cpu_edp) { |
99eb6a01 | 8501 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8502 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8503 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8504 | } else |
74cfd7ac | 8505 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8506 | } else |
74cfd7ac | 8507 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8508 | |
74cfd7ac | 8509 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8510 | POSTING_READ(PCH_DREF_CONTROL); |
8511 | udelay(200); | |
8512 | } else { | |
8513 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8514 | ||
74cfd7ac | 8515 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8516 | |
8517 | /* Turn off CPU output */ | |
74cfd7ac | 8518 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8519 | |
74cfd7ac | 8520 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8521 | POSTING_READ(PCH_DREF_CONTROL); |
8522 | udelay(200); | |
8523 | ||
8524 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8525 | val &= ~DREF_SSC_SOURCE_MASK; |
8526 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8527 | |
8528 | /* Turn off SSC1 */ | |
74cfd7ac | 8529 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8530 | |
74cfd7ac | 8531 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8532 | POSTING_READ(PCH_DREF_CONTROL); |
8533 | udelay(200); | |
8534 | } | |
74cfd7ac CW |
8535 | |
8536 | BUG_ON(val != final); | |
13d83a67 JB |
8537 | } |
8538 | ||
f31f2d55 | 8539 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8540 | { |
f31f2d55 | 8541 | uint32_t tmp; |
dde86e2d | 8542 | |
0ff066a9 PZ |
8543 | tmp = I915_READ(SOUTH_CHICKEN2); |
8544 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8545 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8546 | |
0ff066a9 PZ |
8547 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8548 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8549 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8550 | |
0ff066a9 PZ |
8551 | tmp = I915_READ(SOUTH_CHICKEN2); |
8552 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8553 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8554 | |
0ff066a9 PZ |
8555 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8556 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8557 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8558 | } |
8559 | ||
8560 | /* WaMPhyProgramming:hsw */ | |
8561 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8562 | { | |
8563 | uint32_t tmp; | |
dde86e2d PZ |
8564 | |
8565 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8566 | tmp &= ~(0xFF << 24); | |
8567 | tmp |= (0x12 << 24); | |
8568 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8569 | ||
dde86e2d PZ |
8570 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8571 | tmp |= (1 << 11); | |
8572 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8573 | ||
8574 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8575 | tmp |= (1 << 11); | |
8576 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8577 | ||
dde86e2d PZ |
8578 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8579 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8580 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8581 | ||
8582 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8583 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8584 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8585 | ||
0ff066a9 PZ |
8586 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8587 | tmp &= ~(7 << 13); | |
8588 | tmp |= (5 << 13); | |
8589 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8590 | |
0ff066a9 PZ |
8591 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8592 | tmp &= ~(7 << 13); | |
8593 | tmp |= (5 << 13); | |
8594 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8595 | |
8596 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8597 | tmp &= ~0xFF; | |
8598 | tmp |= 0x1C; | |
8599 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8600 | ||
8601 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8602 | tmp &= ~0xFF; | |
8603 | tmp |= 0x1C; | |
8604 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8605 | ||
8606 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8607 | tmp &= ~(0xFF << 16); | |
8608 | tmp |= (0x1C << 16); | |
8609 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8610 | ||
8611 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8612 | tmp &= ~(0xFF << 16); | |
8613 | tmp |= (0x1C << 16); | |
8614 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8615 | ||
0ff066a9 PZ |
8616 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8617 | tmp |= (1 << 27); | |
8618 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8619 | |
0ff066a9 PZ |
8620 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8621 | tmp |= (1 << 27); | |
8622 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8623 | |
0ff066a9 PZ |
8624 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8625 | tmp &= ~(0xF << 28); | |
8626 | tmp |= (4 << 28); | |
8627 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8628 | |
0ff066a9 PZ |
8629 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8630 | tmp &= ~(0xF << 28); | |
8631 | tmp |= (4 << 28); | |
8632 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8633 | } |
8634 | ||
2fa86a1f PZ |
8635 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8636 | * Programming" based on the parameters passed: | |
8637 | * - Sequence to enable CLKOUT_DP | |
8638 | * - Sequence to enable CLKOUT_DP without spread | |
8639 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8640 | */ | |
8641 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8642 | bool with_fdi) | |
f31f2d55 PZ |
8643 | { |
8644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8645 | uint32_t reg, tmp; |
8646 | ||
8647 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8648 | with_spread = true; | |
c2699524 | 8649 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8650 | with_fdi = false; |
f31f2d55 | 8651 | |
a580516d | 8652 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8653 | |
8654 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8655 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8656 | tmp |= SBI_SSCCTL_PATHALT; | |
8657 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8658 | ||
8659 | udelay(24); | |
8660 | ||
2fa86a1f PZ |
8661 | if (with_spread) { |
8662 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8663 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8664 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8665 | |
2fa86a1f PZ |
8666 | if (with_fdi) { |
8667 | lpt_reset_fdi_mphy(dev_priv); | |
8668 | lpt_program_fdi_mphy(dev_priv); | |
8669 | } | |
8670 | } | |
dde86e2d | 8671 | |
c2699524 | 8672 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8673 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8674 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8675 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8676 | |
a580516d | 8677 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8678 | } |
8679 | ||
47701c3b PZ |
8680 | /* Sequence to disable CLKOUT_DP */ |
8681 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8682 | { | |
8683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8684 | uint32_t reg, tmp; | |
8685 | ||
a580516d | 8686 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8687 | |
c2699524 | 8688 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8689 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8690 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8691 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8692 | ||
8693 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8694 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8695 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8696 | tmp |= SBI_SSCCTL_PATHALT; | |
8697 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8698 | udelay(32); | |
8699 | } | |
8700 | tmp |= SBI_SSCCTL_DISABLE; | |
8701 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8702 | } | |
8703 | ||
a580516d | 8704 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8705 | } |
8706 | ||
f7be2c21 VS |
8707 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8708 | ||
8709 | static const uint16_t sscdivintphase[] = { | |
8710 | [BEND_IDX( 50)] = 0x3B23, | |
8711 | [BEND_IDX( 45)] = 0x3B23, | |
8712 | [BEND_IDX( 40)] = 0x3C23, | |
8713 | [BEND_IDX( 35)] = 0x3C23, | |
8714 | [BEND_IDX( 30)] = 0x3D23, | |
8715 | [BEND_IDX( 25)] = 0x3D23, | |
8716 | [BEND_IDX( 20)] = 0x3E23, | |
8717 | [BEND_IDX( 15)] = 0x3E23, | |
8718 | [BEND_IDX( 10)] = 0x3F23, | |
8719 | [BEND_IDX( 5)] = 0x3F23, | |
8720 | [BEND_IDX( 0)] = 0x0025, | |
8721 | [BEND_IDX( -5)] = 0x0025, | |
8722 | [BEND_IDX(-10)] = 0x0125, | |
8723 | [BEND_IDX(-15)] = 0x0125, | |
8724 | [BEND_IDX(-20)] = 0x0225, | |
8725 | [BEND_IDX(-25)] = 0x0225, | |
8726 | [BEND_IDX(-30)] = 0x0325, | |
8727 | [BEND_IDX(-35)] = 0x0325, | |
8728 | [BEND_IDX(-40)] = 0x0425, | |
8729 | [BEND_IDX(-45)] = 0x0425, | |
8730 | [BEND_IDX(-50)] = 0x0525, | |
8731 | }; | |
8732 | ||
8733 | /* | |
8734 | * Bend CLKOUT_DP | |
8735 | * steps -50 to 50 inclusive, in steps of 5 | |
8736 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8737 | * change in clock period = -(steps / 10) * 5.787 ps | |
8738 | */ | |
8739 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8740 | { | |
8741 | uint32_t tmp; | |
8742 | int idx = BEND_IDX(steps); | |
8743 | ||
8744 | if (WARN_ON(steps % 5 != 0)) | |
8745 | return; | |
8746 | ||
8747 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8748 | return; | |
8749 | ||
8750 | mutex_lock(&dev_priv->sb_lock); | |
8751 | ||
8752 | if (steps % 10 != 0) | |
8753 | tmp = 0xAAAAAAAB; | |
8754 | else | |
8755 | tmp = 0x00000000; | |
8756 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8757 | ||
8758 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8759 | tmp &= 0xffff0000; | |
8760 | tmp |= sscdivintphase[idx]; | |
8761 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8762 | ||
8763 | mutex_unlock(&dev_priv->sb_lock); | |
8764 | } | |
8765 | ||
8766 | #undef BEND_IDX | |
8767 | ||
bf8fa3d3 PZ |
8768 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8769 | { | |
bf8fa3d3 PZ |
8770 | struct intel_encoder *encoder; |
8771 | bool has_vga = false; | |
8772 | ||
b2784e15 | 8773 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8774 | switch (encoder->type) { |
8775 | case INTEL_OUTPUT_ANALOG: | |
8776 | has_vga = true; | |
8777 | break; | |
6847d71b PZ |
8778 | default: |
8779 | break; | |
bf8fa3d3 PZ |
8780 | } |
8781 | } | |
8782 | ||
f7be2c21 VS |
8783 | if (has_vga) { |
8784 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8785 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8786 | } else { |
47701c3b | 8787 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8788 | } |
bf8fa3d3 PZ |
8789 | } |
8790 | ||
dde86e2d PZ |
8791 | /* |
8792 | * Initialize reference clocks when the driver loads | |
8793 | */ | |
8794 | void intel_init_pch_refclk(struct drm_device *dev) | |
8795 | { | |
8796 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8797 | ironlake_init_pch_refclk(dev); | |
8798 | else if (HAS_PCH_LPT(dev)) | |
8799 | lpt_init_pch_refclk(dev); | |
8800 | } | |
8801 | ||
55bb9992 | 8802 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8803 | { |
55bb9992 | 8804 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8805 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8806 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8807 | struct drm_connector *connector; |
55bb9992 | 8808 | struct drm_connector_state *connector_state; |
d9d444cb | 8809 | struct intel_encoder *encoder; |
55bb9992 | 8810 | int num_connectors = 0, i; |
d9d444cb JB |
8811 | bool is_lvds = false; |
8812 | ||
da3ced29 | 8813 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8814 | if (connector_state->crtc != crtc_state->base.crtc) |
8815 | continue; | |
8816 | ||
8817 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8818 | ||
d9d444cb JB |
8819 | switch (encoder->type) { |
8820 | case INTEL_OUTPUT_LVDS: | |
8821 | is_lvds = true; | |
8822 | break; | |
6847d71b PZ |
8823 | default: |
8824 | break; | |
d9d444cb JB |
8825 | } |
8826 | num_connectors++; | |
8827 | } | |
8828 | ||
8829 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8830 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8831 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8832 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8833 | } |
8834 | ||
8835 | return 120000; | |
8836 | } | |
8837 | ||
6ff93609 | 8838 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8839 | { |
c8203565 | 8840 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8841 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8842 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8843 | uint32_t val; |
8844 | ||
78114071 | 8845 | val = 0; |
c8203565 | 8846 | |
6e3c9717 | 8847 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8848 | case 18: |
dfd07d72 | 8849 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8850 | break; |
8851 | case 24: | |
dfd07d72 | 8852 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8853 | break; |
8854 | case 30: | |
dfd07d72 | 8855 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8856 | break; |
8857 | case 36: | |
dfd07d72 | 8858 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8859 | break; |
8860 | default: | |
cc769b62 PZ |
8861 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8862 | BUG(); | |
c8203565 PZ |
8863 | } |
8864 | ||
6e3c9717 | 8865 | if (intel_crtc->config->dither) |
c8203565 PZ |
8866 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8867 | ||
6e3c9717 | 8868 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8869 | val |= PIPECONF_INTERLACED_ILK; |
8870 | else | |
8871 | val |= PIPECONF_PROGRESSIVE; | |
8872 | ||
6e3c9717 | 8873 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8874 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8875 | |
c8203565 PZ |
8876 | I915_WRITE(PIPECONF(pipe), val); |
8877 | POSTING_READ(PIPECONF(pipe)); | |
8878 | } | |
8879 | ||
86d3efce VS |
8880 | /* |
8881 | * Set up the pipe CSC unit. | |
8882 | * | |
8883 | * Currently only full range RGB to limited range RGB conversion | |
8884 | * is supported, but eventually this should handle various | |
8885 | * RGB<->YCbCr scenarios as well. | |
8886 | */ | |
50f3b016 | 8887 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8888 | { |
8889 | struct drm_device *dev = crtc->dev; | |
8890 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8891 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8892 | int pipe = intel_crtc->pipe; | |
8893 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8894 | ||
8895 | /* | |
8896 | * TODO: Check what kind of values actually come out of the pipe | |
8897 | * with these coeff/postoff values and adjust to get the best | |
8898 | * accuracy. Perhaps we even need to take the bpc value into | |
8899 | * consideration. | |
8900 | */ | |
8901 | ||
6e3c9717 | 8902 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8903 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8904 | ||
8905 | /* | |
8906 | * GY/GU and RY/RU should be the other way around according | |
8907 | * to BSpec, but reality doesn't agree. Just set them up in | |
8908 | * a way that results in the correct picture. | |
8909 | */ | |
8910 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8911 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8912 | ||
8913 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8914 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8915 | ||
8916 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8917 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8918 | ||
8919 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8920 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8921 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8922 | ||
8923 | if (INTEL_INFO(dev)->gen > 6) { | |
8924 | uint16_t postoff = 0; | |
8925 | ||
6e3c9717 | 8926 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8927 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8928 | |
8929 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8930 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8931 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8932 | ||
8933 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8934 | } else { | |
8935 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8936 | ||
6e3c9717 | 8937 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8938 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8939 | ||
8940 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8941 | } | |
8942 | } | |
8943 | ||
6ff93609 | 8944 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8945 | { |
756f85cf PZ |
8946 | struct drm_device *dev = crtc->dev; |
8947 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8948 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8949 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8950 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8951 | uint32_t val; |
8952 | ||
3eff4faa | 8953 | val = 0; |
ee2b0b38 | 8954 | |
6e3c9717 | 8955 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8956 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8957 | ||
6e3c9717 | 8958 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8959 | val |= PIPECONF_INTERLACED_ILK; |
8960 | else | |
8961 | val |= PIPECONF_PROGRESSIVE; | |
8962 | ||
702e7a56 PZ |
8963 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8964 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8965 | |
8966 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8967 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8968 | |
3cdf122c | 8969 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8970 | val = 0; |
8971 | ||
6e3c9717 | 8972 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8973 | case 18: |
8974 | val |= PIPEMISC_DITHER_6_BPC; | |
8975 | break; | |
8976 | case 24: | |
8977 | val |= PIPEMISC_DITHER_8_BPC; | |
8978 | break; | |
8979 | case 30: | |
8980 | val |= PIPEMISC_DITHER_10_BPC; | |
8981 | break; | |
8982 | case 36: | |
8983 | val |= PIPEMISC_DITHER_12_BPC; | |
8984 | break; | |
8985 | default: | |
8986 | /* Case prevented by pipe_config_set_bpp. */ | |
8987 | BUG(); | |
8988 | } | |
8989 | ||
6e3c9717 | 8990 | if (intel_crtc->config->dither) |
756f85cf PZ |
8991 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8992 | ||
8993 | I915_WRITE(PIPEMISC(pipe), val); | |
8994 | } | |
ee2b0b38 PZ |
8995 | } |
8996 | ||
6591c6e4 | 8997 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8998 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8999 | intel_clock_t *clock, |
9000 | bool *has_reduced_clock, | |
9001 | intel_clock_t *reduced_clock) | |
9002 | { | |
9003 | struct drm_device *dev = crtc->dev; | |
9004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 9005 | int refclk; |
d4906093 | 9006 | const intel_limit_t *limit; |
c329a4ec | 9007 | bool ret; |
79e53945 | 9008 | |
55bb9992 | 9009 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 9010 | |
d4906093 ML |
9011 | /* |
9012 | * Returns a set of divisors for the desired target clock with the given | |
9013 | * refclk, or FALSE. The returned values represent the clock equation: | |
9014 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
9015 | */ | |
a93e255f ACO |
9016 | limit = intel_limit(crtc_state, refclk); |
9017 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 9018 | crtc_state->port_clock, |
ee9300bb | 9019 | refclk, NULL, clock); |
6591c6e4 PZ |
9020 | if (!ret) |
9021 | return false; | |
cda4b7d3 | 9022 | |
6591c6e4 PZ |
9023 | return true; |
9024 | } | |
9025 | ||
d4b1931c PZ |
9026 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
9027 | { | |
9028 | /* | |
9029 | * Account for spread spectrum to avoid | |
9030 | * oversubscribing the link. Max center spread | |
9031 | * is 2.5%; use 5% for safety's sake. | |
9032 | */ | |
9033 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 9034 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
9035 | } |
9036 | ||
7429e9d4 | 9037 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 9038 | { |
7429e9d4 | 9039 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
9040 | } |
9041 | ||
de13a2e3 | 9042 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 9043 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 9044 | u32 *fp, |
9a7c7890 | 9045 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 9046 | { |
de13a2e3 | 9047 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
9048 | struct drm_device *dev = crtc->dev; |
9049 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 9050 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 9051 | struct drm_connector *connector; |
55bb9992 ACO |
9052 | struct drm_connector_state *connector_state; |
9053 | struct intel_encoder *encoder; | |
de13a2e3 | 9054 | uint32_t dpll; |
55bb9992 | 9055 | int factor, num_connectors = 0, i; |
09ede541 | 9056 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 9057 | |
da3ced29 | 9058 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
9059 | if (connector_state->crtc != crtc_state->base.crtc) |
9060 | continue; | |
9061 | ||
9062 | encoder = to_intel_encoder(connector_state->best_encoder); | |
9063 | ||
9064 | switch (encoder->type) { | |
79e53945 JB |
9065 | case INTEL_OUTPUT_LVDS: |
9066 | is_lvds = true; | |
9067 | break; | |
9068 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 9069 | case INTEL_OUTPUT_HDMI: |
79e53945 | 9070 | is_sdvo = true; |
79e53945 | 9071 | break; |
6847d71b PZ |
9072 | default: |
9073 | break; | |
79e53945 | 9074 | } |
43565a06 | 9075 | |
c751ce4f | 9076 | num_connectors++; |
79e53945 | 9077 | } |
79e53945 | 9078 | |
c1858123 | 9079 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
9080 | factor = 21; |
9081 | if (is_lvds) { | |
9082 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 9083 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 9084 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 9085 | factor = 25; |
190f68c5 | 9086 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 9087 | factor = 20; |
c1858123 | 9088 | |
190f68c5 | 9089 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 9090 | *fp |= FP_CB_TUNE; |
2c07245f | 9091 | |
9a7c7890 DV |
9092 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
9093 | *fp2 |= FP_CB_TUNE; | |
9094 | ||
5eddb70b | 9095 | dpll = 0; |
2c07245f | 9096 | |
a07d6787 EA |
9097 | if (is_lvds) |
9098 | dpll |= DPLLB_MODE_LVDS; | |
9099 | else | |
9100 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9101 | |
190f68c5 | 9102 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9103 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
9104 | |
9105 | if (is_sdvo) | |
4a33e48d | 9106 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 9107 | if (crtc_state->has_dp_encoder) |
4a33e48d | 9108 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9109 | |
a07d6787 | 9110 | /* compute bitmask from p1 value */ |
190f68c5 | 9111 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9112 | /* also FPA1 */ |
190f68c5 | 9113 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9114 | |
190f68c5 | 9115 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9116 | case 5: |
9117 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9118 | break; | |
9119 | case 7: | |
9120 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9121 | break; | |
9122 | case 10: | |
9123 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9124 | break; | |
9125 | case 14: | |
9126 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9127 | break; | |
79e53945 JB |
9128 | } |
9129 | ||
b4c09f3b | 9130 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 9131 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9132 | else |
9133 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9134 | ||
959e16d6 | 9135 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
9136 | } |
9137 | ||
190f68c5 ACO |
9138 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9139 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9140 | { |
c7653199 | 9141 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 9142 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 9143 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 9144 | bool ok, has_reduced_clock = false; |
8b47047b | 9145 | bool is_lvds = false; |
e2b78267 | 9146 | struct intel_shared_dpll *pll; |
de13a2e3 | 9147 | |
dd3cd74a ACO |
9148 | memset(&crtc_state->dpll_hw_state, 0, |
9149 | sizeof(crtc_state->dpll_hw_state)); | |
9150 | ||
7905df29 | 9151 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 9152 | |
5dc5298b PZ |
9153 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
9154 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 9155 | |
190f68c5 | 9156 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 9157 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 9158 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
9159 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9160 | return -EINVAL; | |
79e53945 | 9161 | } |
f47709a9 | 9162 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9163 | if (!crtc_state->clock_set) { |
9164 | crtc_state->dpll.n = clock.n; | |
9165 | crtc_state->dpll.m1 = clock.m1; | |
9166 | crtc_state->dpll.m2 = clock.m2; | |
9167 | crtc_state->dpll.p1 = clock.p1; | |
9168 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9169 | } |
79e53945 | 9170 | |
5dc5298b | 9171 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9172 | if (crtc_state->has_pch_encoder) { |
9173 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9174 | if (has_reduced_clock) |
7429e9d4 | 9175 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9176 | |
190f68c5 | 9177 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9178 | &fp, &reduced_clock, |
9179 | has_reduced_clock ? &fp2 : NULL); | |
9180 | ||
190f68c5 ACO |
9181 | crtc_state->dpll_hw_state.dpll = dpll; |
9182 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9183 | if (has_reduced_clock) |
190f68c5 | 9184 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9185 | else |
190f68c5 | 9186 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9187 | |
190f68c5 | 9188 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9189 | if (pll == NULL) { |
84f44ce7 | 9190 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9191 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9192 | return -EINVAL; |
9193 | } | |
3fb37703 | 9194 | } |
79e53945 | 9195 | |
ab585dea | 9196 | if (is_lvds && has_reduced_clock) |
c7653199 | 9197 | crtc->lowfreq_avail = true; |
bcd644e0 | 9198 | else |
c7653199 | 9199 | crtc->lowfreq_avail = false; |
e2b78267 | 9200 | |
c8f7a0db | 9201 | return 0; |
79e53945 JB |
9202 | } |
9203 | ||
eb14cb74 VS |
9204 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9205 | struct intel_link_m_n *m_n) | |
9206 | { | |
9207 | struct drm_device *dev = crtc->base.dev; | |
9208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9209 | enum pipe pipe = crtc->pipe; | |
9210 | ||
9211 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9212 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9213 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9214 | & ~TU_SIZE_MASK; | |
9215 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9216 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9217 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9218 | } | |
9219 | ||
9220 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9221 | enum transcoder transcoder, | |
b95af8be VK |
9222 | struct intel_link_m_n *m_n, |
9223 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9224 | { |
9225 | struct drm_device *dev = crtc->base.dev; | |
9226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9227 | enum pipe pipe = crtc->pipe; |
72419203 | 9228 | |
eb14cb74 VS |
9229 | if (INTEL_INFO(dev)->gen >= 5) { |
9230 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9231 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9232 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9233 | & ~TU_SIZE_MASK; | |
9234 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9235 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9236 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9237 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9238 | * gen < 8) and if DRRS is supported (to make sure the | |
9239 | * registers are not unnecessarily read). | |
9240 | */ | |
9241 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9242 | crtc->config->has_drrs) { |
b95af8be VK |
9243 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9244 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9245 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9246 | & ~TU_SIZE_MASK; | |
9247 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9248 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9249 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9250 | } | |
eb14cb74 VS |
9251 | } else { |
9252 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9253 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9254 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9255 | & ~TU_SIZE_MASK; | |
9256 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9257 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9258 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9259 | } | |
9260 | } | |
9261 | ||
9262 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9263 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9264 | { |
681a8504 | 9265 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9266 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9267 | else | |
9268 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9269 | &pipe_config->dp_m_n, |
9270 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9271 | } |
72419203 | 9272 | |
eb14cb74 | 9273 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9274 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9275 | { |
9276 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9277 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9278 | } |
9279 | ||
bd2e244f | 9280 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9281 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9282 | { |
9283 | struct drm_device *dev = crtc->base.dev; | |
9284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9285 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9286 | uint32_t ps_ctrl = 0; | |
9287 | int id = -1; | |
9288 | int i; | |
bd2e244f | 9289 | |
a1b2278e CK |
9290 | /* find scaler attached to this pipe */ |
9291 | for (i = 0; i < crtc->num_scalers; i++) { | |
9292 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9293 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9294 | id = i; | |
9295 | pipe_config->pch_pfit.enabled = true; | |
9296 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9297 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9298 | break; | |
9299 | } | |
9300 | } | |
bd2e244f | 9301 | |
a1b2278e CK |
9302 | scaler_state->scaler_id = id; |
9303 | if (id >= 0) { | |
9304 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9305 | } else { | |
9306 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9307 | } |
9308 | } | |
9309 | ||
5724dbd1 DL |
9310 | static void |
9311 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9312 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9313 | { |
9314 | struct drm_device *dev = crtc->base.dev; | |
9315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9316 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9317 | int pipe = crtc->pipe; |
9318 | int fourcc, pixel_format; | |
6761dd31 | 9319 | unsigned int aligned_height; |
bc8d7dff | 9320 | struct drm_framebuffer *fb; |
1b842c89 | 9321 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9322 | |
d9806c9f | 9323 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9324 | if (!intel_fb) { |
bc8d7dff DL |
9325 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9326 | return; | |
9327 | } | |
9328 | ||
1b842c89 DL |
9329 | fb = &intel_fb->base; |
9330 | ||
bc8d7dff | 9331 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9332 | if (!(val & PLANE_CTL_ENABLE)) |
9333 | goto error; | |
9334 | ||
bc8d7dff DL |
9335 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9336 | fourcc = skl_format_to_fourcc(pixel_format, | |
9337 | val & PLANE_CTL_ORDER_RGBX, | |
9338 | val & PLANE_CTL_ALPHA_MASK); | |
9339 | fb->pixel_format = fourcc; | |
9340 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9341 | ||
40f46283 DL |
9342 | tiling = val & PLANE_CTL_TILED_MASK; |
9343 | switch (tiling) { | |
9344 | case PLANE_CTL_TILED_LINEAR: | |
9345 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9346 | break; | |
9347 | case PLANE_CTL_TILED_X: | |
9348 | plane_config->tiling = I915_TILING_X; | |
9349 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9350 | break; | |
9351 | case PLANE_CTL_TILED_Y: | |
9352 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9353 | break; | |
9354 | case PLANE_CTL_TILED_YF: | |
9355 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9356 | break; | |
9357 | default: | |
9358 | MISSING_CASE(tiling); | |
9359 | goto error; | |
9360 | } | |
9361 | ||
bc8d7dff DL |
9362 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9363 | plane_config->base = base; | |
9364 | ||
9365 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9366 | ||
9367 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9368 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9369 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9370 | ||
9371 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9372 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9373 | fb->pixel_format); |
bc8d7dff DL |
9374 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9375 | ||
9376 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9377 | fb->pixel_format, |
9378 | fb->modifier[0]); | |
bc8d7dff | 9379 | |
f37b5c2b | 9380 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9381 | |
9382 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9383 | pipe_name(pipe), fb->width, fb->height, | |
9384 | fb->bits_per_pixel, base, fb->pitches[0], | |
9385 | plane_config->size); | |
9386 | ||
2d14030b | 9387 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9388 | return; |
9389 | ||
9390 | error: | |
9391 | kfree(fb); | |
9392 | } | |
9393 | ||
2fa2fe9a | 9394 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9395 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9396 | { |
9397 | struct drm_device *dev = crtc->base.dev; | |
9398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9399 | uint32_t tmp; | |
9400 | ||
9401 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9402 | ||
9403 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9404 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9405 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9406 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9407 | |
9408 | /* We currently do not free assignements of panel fitters on | |
9409 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9410 | * differentiates them) so just WARN about this case for now. */ | |
9411 | if (IS_GEN7(dev)) { | |
9412 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9413 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9414 | } | |
2fa2fe9a | 9415 | } |
79e53945 JB |
9416 | } |
9417 | ||
5724dbd1 DL |
9418 | static void |
9419 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9420 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9421 | { |
9422 | struct drm_device *dev = crtc->base.dev; | |
9423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9424 | u32 val, base, offset; | |
aeee5a49 | 9425 | int pipe = crtc->pipe; |
4c6baa59 | 9426 | int fourcc, pixel_format; |
6761dd31 | 9427 | unsigned int aligned_height; |
b113d5ee | 9428 | struct drm_framebuffer *fb; |
1b842c89 | 9429 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9430 | |
42a7b088 DL |
9431 | val = I915_READ(DSPCNTR(pipe)); |
9432 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9433 | return; | |
9434 | ||
d9806c9f | 9435 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9436 | if (!intel_fb) { |
4c6baa59 JB |
9437 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9438 | return; | |
9439 | } | |
9440 | ||
1b842c89 DL |
9441 | fb = &intel_fb->base; |
9442 | ||
18c5247e DV |
9443 | if (INTEL_INFO(dev)->gen >= 4) { |
9444 | if (val & DISPPLANE_TILED) { | |
49af449b | 9445 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9446 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9447 | } | |
9448 | } | |
4c6baa59 JB |
9449 | |
9450 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9451 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9452 | fb->pixel_format = fourcc; |
9453 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9454 | |
aeee5a49 | 9455 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9456 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9457 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9458 | } else { |
49af449b | 9459 | if (plane_config->tiling) |
aeee5a49 | 9460 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9461 | else |
aeee5a49 | 9462 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9463 | } |
9464 | plane_config->base = base; | |
9465 | ||
9466 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9467 | fb->width = ((val >> 16) & 0xfff) + 1; |
9468 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9469 | |
9470 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9471 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9472 | |
b113d5ee | 9473 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9474 | fb->pixel_format, |
9475 | fb->modifier[0]); | |
4c6baa59 | 9476 | |
f37b5c2b | 9477 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9478 | |
2844a921 DL |
9479 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9480 | pipe_name(pipe), fb->width, fb->height, | |
9481 | fb->bits_per_pixel, base, fb->pitches[0], | |
9482 | plane_config->size); | |
b113d5ee | 9483 | |
2d14030b | 9484 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9485 | } |
9486 | ||
0e8ffe1b | 9487 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9488 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9489 | { |
9490 | struct drm_device *dev = crtc->base.dev; | |
9491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9492 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9493 | uint32_t tmp; |
1729050e | 9494 | bool ret; |
0e8ffe1b | 9495 | |
1729050e ID |
9496 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9497 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9498 | return false; |
9499 | ||
e143a21c | 9500 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9501 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9502 | |
1729050e | 9503 | ret = false; |
0e8ffe1b DV |
9504 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9505 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9506 | goto out; |
0e8ffe1b | 9507 | |
42571aef VS |
9508 | switch (tmp & PIPECONF_BPC_MASK) { |
9509 | case PIPECONF_6BPC: | |
9510 | pipe_config->pipe_bpp = 18; | |
9511 | break; | |
9512 | case PIPECONF_8BPC: | |
9513 | pipe_config->pipe_bpp = 24; | |
9514 | break; | |
9515 | case PIPECONF_10BPC: | |
9516 | pipe_config->pipe_bpp = 30; | |
9517 | break; | |
9518 | case PIPECONF_12BPC: | |
9519 | pipe_config->pipe_bpp = 36; | |
9520 | break; | |
9521 | default: | |
9522 | break; | |
9523 | } | |
9524 | ||
b5a9fa09 DV |
9525 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9526 | pipe_config->limited_color_range = true; | |
9527 | ||
ab9412ba | 9528 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9529 | struct intel_shared_dpll *pll; |
9530 | ||
88adfff1 DV |
9531 | pipe_config->has_pch_encoder = true; |
9532 | ||
627eb5a3 DV |
9533 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9534 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9535 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9536 | |
9537 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9538 | |
c0d43d62 | 9539 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9540 | pipe_config->shared_dpll = |
9541 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9542 | } else { |
9543 | tmp = I915_READ(PCH_DPLL_SEL); | |
9544 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9545 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9546 | else | |
9547 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9548 | } | |
66e985c0 DV |
9549 | |
9550 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9551 | ||
9552 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9553 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9554 | |
9555 | tmp = pipe_config->dpll_hw_state.dpll; | |
9556 | pipe_config->pixel_multiplier = | |
9557 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9558 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9559 | |
9560 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9561 | } else { |
9562 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9563 | } |
9564 | ||
1bd1bd80 DV |
9565 | intel_get_pipe_timings(crtc, pipe_config); |
9566 | ||
2fa2fe9a DV |
9567 | ironlake_get_pfit_config(crtc, pipe_config); |
9568 | ||
1729050e ID |
9569 | ret = true; |
9570 | ||
9571 | out: | |
9572 | intel_display_power_put(dev_priv, power_domain); | |
9573 | ||
9574 | return ret; | |
0e8ffe1b DV |
9575 | } |
9576 | ||
be256dc7 PZ |
9577 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9578 | { | |
9579 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9580 | struct intel_crtc *crtc; |
be256dc7 | 9581 | |
d3fcc808 | 9582 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9583 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9584 | pipe_name(crtc->pipe)); |
9585 | ||
e2c719b7 RC |
9586 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9587 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9588 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9589 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9590 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9591 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9592 | "CPU PWM1 enabled\n"); |
c5107b87 | 9593 | if (IS_HASWELL(dev)) |
e2c719b7 | 9594 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9595 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9596 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9597 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9598 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9599 | "Utility pin enabled\n"); |
e2c719b7 | 9600 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9601 | |
9926ada1 PZ |
9602 | /* |
9603 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9604 | * interrupts remain enabled. We used to check for that, but since it's | |
9605 | * gen-specific and since we only disable LCPLL after we fully disable | |
9606 | * the interrupts, the check below should be enough. | |
9607 | */ | |
e2c719b7 | 9608 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9609 | } |
9610 | ||
9ccd5aeb PZ |
9611 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9612 | { | |
9613 | struct drm_device *dev = dev_priv->dev; | |
9614 | ||
9615 | if (IS_HASWELL(dev)) | |
9616 | return I915_READ(D_COMP_HSW); | |
9617 | else | |
9618 | return I915_READ(D_COMP_BDW); | |
9619 | } | |
9620 | ||
3c4c9b81 PZ |
9621 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9622 | { | |
9623 | struct drm_device *dev = dev_priv->dev; | |
9624 | ||
9625 | if (IS_HASWELL(dev)) { | |
9626 | mutex_lock(&dev_priv->rps.hw_lock); | |
9627 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9628 | val)) | |
f475dadf | 9629 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9630 | mutex_unlock(&dev_priv->rps.hw_lock); |
9631 | } else { | |
9ccd5aeb PZ |
9632 | I915_WRITE(D_COMP_BDW, val); |
9633 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9634 | } |
be256dc7 PZ |
9635 | } |
9636 | ||
9637 | /* | |
9638 | * This function implements pieces of two sequences from BSpec: | |
9639 | * - Sequence for display software to disable LCPLL | |
9640 | * - Sequence for display software to allow package C8+ | |
9641 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9642 | * register. Callers should take care of disabling all the display engine | |
9643 | * functions, doing the mode unset, fixing interrupts, etc. | |
9644 | */ | |
6ff58d53 PZ |
9645 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9646 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9647 | { |
9648 | uint32_t val; | |
9649 | ||
9650 | assert_can_disable_lcpll(dev_priv); | |
9651 | ||
9652 | val = I915_READ(LCPLL_CTL); | |
9653 | ||
9654 | if (switch_to_fclk) { | |
9655 | val |= LCPLL_CD_SOURCE_FCLK; | |
9656 | I915_WRITE(LCPLL_CTL, val); | |
9657 | ||
9658 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9659 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9660 | DRM_ERROR("Switching to FCLK failed\n"); | |
9661 | ||
9662 | val = I915_READ(LCPLL_CTL); | |
9663 | } | |
9664 | ||
9665 | val |= LCPLL_PLL_DISABLE; | |
9666 | I915_WRITE(LCPLL_CTL, val); | |
9667 | POSTING_READ(LCPLL_CTL); | |
9668 | ||
9669 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9670 | DRM_ERROR("LCPLL still locked\n"); | |
9671 | ||
9ccd5aeb | 9672 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9673 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9674 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9675 | ndelay(100); |
9676 | ||
9ccd5aeb PZ |
9677 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9678 | 1)) | |
be256dc7 PZ |
9679 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9680 | ||
9681 | if (allow_power_down) { | |
9682 | val = I915_READ(LCPLL_CTL); | |
9683 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9684 | I915_WRITE(LCPLL_CTL, val); | |
9685 | POSTING_READ(LCPLL_CTL); | |
9686 | } | |
9687 | } | |
9688 | ||
9689 | /* | |
9690 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9691 | * source. | |
9692 | */ | |
6ff58d53 | 9693 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9694 | { |
9695 | uint32_t val; | |
9696 | ||
9697 | val = I915_READ(LCPLL_CTL); | |
9698 | ||
9699 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9700 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9701 | return; | |
9702 | ||
a8a8bd54 PZ |
9703 | /* |
9704 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9705 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9706 | */ |
59bad947 | 9707 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9708 | |
be256dc7 PZ |
9709 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9710 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9711 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9712 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9713 | } |
9714 | ||
9ccd5aeb | 9715 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9716 | val |= D_COMP_COMP_FORCE; |
9717 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9718 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9719 | |
9720 | val = I915_READ(LCPLL_CTL); | |
9721 | val &= ~LCPLL_PLL_DISABLE; | |
9722 | I915_WRITE(LCPLL_CTL, val); | |
9723 | ||
9724 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9725 | DRM_ERROR("LCPLL not locked yet\n"); | |
9726 | ||
9727 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9728 | val = I915_READ(LCPLL_CTL); | |
9729 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9730 | I915_WRITE(LCPLL_CTL, val); | |
9731 | ||
9732 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9733 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9734 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9735 | } | |
215733fa | 9736 | |
59bad947 | 9737 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9738 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9739 | } |
9740 | ||
765dab67 PZ |
9741 | /* |
9742 | * Package states C8 and deeper are really deep PC states that can only be | |
9743 | * reached when all the devices on the system allow it, so even if the graphics | |
9744 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9745 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9746 | * | |
9747 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9748 | * well is disabled and most interrupts are disabled, and these are also | |
9749 | * requirements for runtime PM. When these conditions are met, we manually do | |
9750 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9751 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9752 | * hang the machine. | |
9753 | * | |
9754 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9755 | * the state of some registers, so when we come back from PC8+ we need to | |
9756 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9757 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9758 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9759 | * because of the runtime PM support). | |
9760 | * | |
9761 | * For more, read "Display Sequences for Package C8" on the hardware | |
9762 | * documentation. | |
9763 | */ | |
a14cb6fc | 9764 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9765 | { |
c67a470b PZ |
9766 | struct drm_device *dev = dev_priv->dev; |
9767 | uint32_t val; | |
9768 | ||
c67a470b PZ |
9769 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9770 | ||
c2699524 | 9771 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9772 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9773 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9774 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9775 | } | |
9776 | ||
9777 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9778 | hsw_disable_lcpll(dev_priv, true, true); |
9779 | } | |
9780 | ||
a14cb6fc | 9781 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9782 | { |
9783 | struct drm_device *dev = dev_priv->dev; | |
9784 | uint32_t val; | |
9785 | ||
c67a470b PZ |
9786 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9787 | ||
9788 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9789 | lpt_init_pch_refclk(dev); |
9790 | ||
c2699524 | 9791 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9792 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9793 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9794 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9795 | } | |
c67a470b PZ |
9796 | } |
9797 | ||
27c329ed | 9798 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9799 | { |
a821fc46 | 9800 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9801 | struct intel_atomic_state *old_intel_state = |
9802 | to_intel_atomic_state(old_state); | |
9803 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9804 | |
27c329ed | 9805 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9806 | } |
9807 | ||
b432e5cf | 9808 | /* compute the max rate for new configuration */ |
27c329ed | 9809 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9810 | { |
565602d7 ML |
9811 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9812 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9813 | struct drm_crtc *crtc; | |
9814 | struct drm_crtc_state *cstate; | |
27c329ed | 9815 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9816 | unsigned max_pixel_rate = 0, i; |
9817 | enum pipe pipe; | |
b432e5cf | 9818 | |
565602d7 ML |
9819 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9820 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9821 | |
565602d7 ML |
9822 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9823 | int pixel_rate; | |
27c329ed | 9824 | |
565602d7 ML |
9825 | crtc_state = to_intel_crtc_state(cstate); |
9826 | if (!crtc_state->base.enable) { | |
9827 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9828 | continue; |
565602d7 | 9829 | } |
b432e5cf | 9830 | |
27c329ed | 9831 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9832 | |
9833 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9834 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9835 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9836 | ||
565602d7 | 9837 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9838 | } |
9839 | ||
565602d7 ML |
9840 | for_each_pipe(dev_priv, pipe) |
9841 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9842 | ||
b432e5cf VS |
9843 | return max_pixel_rate; |
9844 | } | |
9845 | ||
9846 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9847 | { | |
9848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9849 | uint32_t val, data; | |
9850 | int ret; | |
9851 | ||
9852 | if (WARN((I915_READ(LCPLL_CTL) & | |
9853 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9854 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9855 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9856 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9857 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9858 | return; | |
9859 | ||
9860 | mutex_lock(&dev_priv->rps.hw_lock); | |
9861 | ret = sandybridge_pcode_write(dev_priv, | |
9862 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9863 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9864 | if (ret) { | |
9865 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9866 | return; | |
9867 | } | |
9868 | ||
9869 | val = I915_READ(LCPLL_CTL); | |
9870 | val |= LCPLL_CD_SOURCE_FCLK; | |
9871 | I915_WRITE(LCPLL_CTL, val); | |
9872 | ||
5ba00178 TU |
9873 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9874 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9875 | DRM_ERROR("Switching to FCLK failed\n"); |
9876 | ||
9877 | val = I915_READ(LCPLL_CTL); | |
9878 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9879 | ||
9880 | switch (cdclk) { | |
9881 | case 450000: | |
9882 | val |= LCPLL_CLK_FREQ_450; | |
9883 | data = 0; | |
9884 | break; | |
9885 | case 540000: | |
9886 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9887 | data = 1; | |
9888 | break; | |
9889 | case 337500: | |
9890 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9891 | data = 2; | |
9892 | break; | |
9893 | case 675000: | |
9894 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9895 | data = 3; | |
9896 | break; | |
9897 | default: | |
9898 | WARN(1, "invalid cdclk frequency\n"); | |
9899 | return; | |
9900 | } | |
9901 | ||
9902 | I915_WRITE(LCPLL_CTL, val); | |
9903 | ||
9904 | val = I915_READ(LCPLL_CTL); | |
9905 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9906 | I915_WRITE(LCPLL_CTL, val); | |
9907 | ||
5ba00178 TU |
9908 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9909 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9910 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9911 | ||
9912 | mutex_lock(&dev_priv->rps.hw_lock); | |
9913 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9914 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9915 | ||
9916 | intel_update_cdclk(dev); | |
9917 | ||
9918 | WARN(cdclk != dev_priv->cdclk_freq, | |
9919 | "cdclk requested %d kHz but got %d kHz\n", | |
9920 | cdclk, dev_priv->cdclk_freq); | |
9921 | } | |
9922 | ||
27c329ed | 9923 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9924 | { |
27c329ed | 9925 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9926 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9927 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9928 | int cdclk; |
9929 | ||
9930 | /* | |
9931 | * FIXME should also account for plane ratio | |
9932 | * once 64bpp pixel formats are supported. | |
9933 | */ | |
27c329ed | 9934 | if (max_pixclk > 540000) |
b432e5cf | 9935 | cdclk = 675000; |
27c329ed | 9936 | else if (max_pixclk > 450000) |
b432e5cf | 9937 | cdclk = 540000; |
27c329ed | 9938 | else if (max_pixclk > 337500) |
b432e5cf VS |
9939 | cdclk = 450000; |
9940 | else | |
9941 | cdclk = 337500; | |
9942 | ||
b432e5cf | 9943 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9944 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9945 | cdclk, dev_priv->max_cdclk_freq); | |
9946 | return -EINVAL; | |
b432e5cf VS |
9947 | } |
9948 | ||
1a617b77 ML |
9949 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9950 | if (!intel_state->active_crtcs) | |
9951 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9952 | |
9953 | return 0; | |
9954 | } | |
9955 | ||
27c329ed | 9956 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9957 | { |
27c329ed | 9958 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9959 | struct intel_atomic_state *old_intel_state = |
9960 | to_intel_atomic_state(old_state); | |
9961 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9962 | |
27c329ed | 9963 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9964 | } |
9965 | ||
190f68c5 ACO |
9966 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9967 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9968 | { |
af3997b5 MK |
9969 | struct intel_encoder *intel_encoder = |
9970 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9971 | ||
9972 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9973 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9974 | return -EINVAL; | |
9975 | } | |
716c2e55 | 9976 | |
c7653199 | 9977 | crtc->lowfreq_avail = false; |
644cef34 | 9978 | |
c8f7a0db | 9979 | return 0; |
79e53945 JB |
9980 | } |
9981 | ||
3760b59c S |
9982 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9983 | enum port port, | |
9984 | struct intel_crtc_state *pipe_config) | |
9985 | { | |
9986 | switch (port) { | |
9987 | case PORT_A: | |
9988 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9989 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9990 | break; | |
9991 | case PORT_B: | |
9992 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9993 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9994 | break; | |
9995 | case PORT_C: | |
9996 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9997 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9998 | break; | |
9999 | default: | |
10000 | DRM_ERROR("Incorrect port type\n"); | |
10001 | } | |
10002 | } | |
10003 | ||
96b7dfb7 S |
10004 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
10005 | enum port port, | |
5cec258b | 10006 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 10007 | { |
3148ade7 | 10008 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
10009 | |
10010 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
10011 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
10012 | ||
10013 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
10014 | case SKL_DPLL0: |
10015 | /* | |
10016 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
10017 | * of the shared DPLL framework and thus needs to be read out | |
10018 | * separately | |
10019 | */ | |
10020 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
10021 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
10022 | break; | |
96b7dfb7 S |
10023 | case SKL_DPLL1: |
10024 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
10025 | break; | |
10026 | case SKL_DPLL2: | |
10027 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
10028 | break; | |
10029 | case SKL_DPLL3: | |
10030 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
10031 | break; | |
96b7dfb7 S |
10032 | } |
10033 | } | |
10034 | ||
7d2c8175 DL |
10035 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
10036 | enum port port, | |
5cec258b | 10037 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
10038 | { |
10039 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
10040 | ||
10041 | switch (pipe_config->ddi_pll_sel) { | |
10042 | case PORT_CLK_SEL_WRPLL1: | |
10043 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
10044 | break; | |
10045 | case PORT_CLK_SEL_WRPLL2: | |
10046 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
10047 | break; | |
00490c22 ML |
10048 | case PORT_CLK_SEL_SPLL: |
10049 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 10050 | break; |
7d2c8175 DL |
10051 | } |
10052 | } | |
10053 | ||
26804afd | 10054 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10055 | struct intel_crtc_state *pipe_config) |
26804afd DV |
10056 | { |
10057 | struct drm_device *dev = crtc->base.dev; | |
10058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 10059 | struct intel_shared_dpll *pll; |
26804afd DV |
10060 | enum port port; |
10061 | uint32_t tmp; | |
10062 | ||
10063 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10064 | ||
10065 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10066 | ||
ef11bdb3 | 10067 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 10068 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
10069 | else if (IS_BROXTON(dev)) |
10070 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
10071 | else |
10072 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10073 | |
d452c5b6 DV |
10074 | if (pipe_config->shared_dpll >= 0) { |
10075 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
10076 | ||
10077 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
10078 | &pipe_config->dpll_hw_state)); | |
10079 | } | |
10080 | ||
26804afd DV |
10081 | /* |
10082 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10083 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10084 | * the PCH transcoder is on. | |
10085 | */ | |
ca370455 DL |
10086 | if (INTEL_INFO(dev)->gen < 9 && |
10087 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
10088 | pipe_config->has_pch_encoder = true; |
10089 | ||
10090 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10091 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10092 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10093 | ||
10094 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10095 | } | |
10096 | } | |
10097 | ||
0e8ffe1b | 10098 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10099 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10100 | { |
10101 | struct drm_device *dev = crtc->base.dev; | |
10102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
10103 | enum intel_display_power_domain power_domain; |
10104 | unsigned long power_domain_mask; | |
0e8ffe1b | 10105 | uint32_t tmp; |
1729050e | 10106 | bool ret; |
0e8ffe1b | 10107 | |
1729050e ID |
10108 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10109 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10110 | return false; |
1729050e ID |
10111 | power_domain_mask = BIT(power_domain); |
10112 | ||
10113 | ret = false; | |
b5482bd0 | 10114 | |
e143a21c | 10115 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
10116 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
10117 | ||
eccb140b DV |
10118 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
10119 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10120 | enum pipe trans_edp_pipe; | |
10121 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10122 | default: | |
10123 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10124 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10125 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10126 | trans_edp_pipe = PIPE_A; | |
10127 | break; | |
10128 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10129 | trans_edp_pipe = PIPE_B; | |
10130 | break; | |
10131 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10132 | trans_edp_pipe = PIPE_C; | |
10133 | break; | |
10134 | } | |
10135 | ||
10136 | if (trans_edp_pipe == crtc->pipe) | |
10137 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10138 | } | |
10139 | ||
1729050e ID |
10140 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); |
10141 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10142 | goto out; | |
10143 | power_domain_mask |= BIT(power_domain); | |
2bfce950 | 10144 | |
eccb140b | 10145 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b | 10146 | if (!(tmp & PIPECONF_ENABLE)) |
1729050e | 10147 | goto out; |
0e8ffe1b | 10148 | |
26804afd | 10149 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 10150 | |
1bd1bd80 DV |
10151 | intel_get_pipe_timings(crtc, pipe_config); |
10152 | ||
a1b2278e CK |
10153 | if (INTEL_INFO(dev)->gen >= 9) { |
10154 | skl_init_scalers(dev, crtc, pipe_config); | |
10155 | } | |
10156 | ||
af99ceda CK |
10157 | if (INTEL_INFO(dev)->gen >= 9) { |
10158 | pipe_config->scaler_state.scaler_id = -1; | |
10159 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10160 | } | |
10161 | ||
1729050e ID |
10162 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10163 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10164 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10165 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10166 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10167 | else |
1c132b44 | 10168 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10169 | } |
88adfff1 | 10170 | |
e59150dc JB |
10171 | if (IS_HASWELL(dev)) |
10172 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10173 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10174 | |
ebb69c95 CT |
10175 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10176 | pipe_config->pixel_multiplier = | |
10177 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10178 | } else { | |
10179 | pipe_config->pixel_multiplier = 1; | |
10180 | } | |
6c49f241 | 10181 | |
1729050e ID |
10182 | ret = true; |
10183 | ||
10184 | out: | |
10185 | for_each_power_domain(power_domain, power_domain_mask) | |
10186 | intel_display_power_put(dev_priv, power_domain); | |
10187 | ||
10188 | return ret; | |
0e8ffe1b DV |
10189 | } |
10190 | ||
55a08b3f ML |
10191 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10192 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10193 | { |
10194 | struct drm_device *dev = crtc->dev; | |
10195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10197 | uint32_t cntl = 0, size = 0; |
560b85bb | 10198 | |
55a08b3f ML |
10199 | if (plane_state && plane_state->visible) { |
10200 | unsigned int width = plane_state->base.crtc_w; | |
10201 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10202 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10203 | ||
10204 | switch (stride) { | |
10205 | default: | |
10206 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10207 | width, stride); | |
10208 | stride = 256; | |
10209 | /* fallthrough */ | |
10210 | case 256: | |
10211 | case 512: | |
10212 | case 1024: | |
10213 | case 2048: | |
10214 | break; | |
4b0e333e CW |
10215 | } |
10216 | ||
dc41c154 VS |
10217 | cntl |= CURSOR_ENABLE | |
10218 | CURSOR_GAMMA_ENABLE | | |
10219 | CURSOR_FORMAT_ARGB | | |
10220 | CURSOR_STRIDE(stride); | |
10221 | ||
10222 | size = (height << 12) | width; | |
4b0e333e | 10223 | } |
560b85bb | 10224 | |
dc41c154 VS |
10225 | if (intel_crtc->cursor_cntl != 0 && |
10226 | (intel_crtc->cursor_base != base || | |
10227 | intel_crtc->cursor_size != size || | |
10228 | intel_crtc->cursor_cntl != cntl)) { | |
10229 | /* On these chipsets we can only modify the base/size/stride | |
10230 | * whilst the cursor is disabled. | |
10231 | */ | |
0b87c24e VS |
10232 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10233 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10234 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10235 | } |
560b85bb | 10236 | |
99d1f387 | 10237 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10238 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10239 | intel_crtc->cursor_base = base; |
10240 | } | |
4726e0b0 | 10241 | |
dc41c154 VS |
10242 | if (intel_crtc->cursor_size != size) { |
10243 | I915_WRITE(CURSIZE, size); | |
10244 | intel_crtc->cursor_size = size; | |
4b0e333e | 10245 | } |
560b85bb | 10246 | |
4b0e333e | 10247 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10248 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10249 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10250 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10251 | } |
560b85bb CW |
10252 | } |
10253 | ||
55a08b3f ML |
10254 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10255 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10256 | { |
10257 | struct drm_device *dev = crtc->dev; | |
10258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10259 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10260 | int pipe = intel_crtc->pipe; | |
663f3122 | 10261 | uint32_t cntl = 0; |
4b0e333e | 10262 | |
55a08b3f | 10263 | if (plane_state && plane_state->visible) { |
4b0e333e | 10264 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10265 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10266 | case 64: |
10267 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10268 | break; | |
10269 | case 128: | |
10270 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10271 | break; | |
10272 | case 256: | |
10273 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10274 | break; | |
10275 | default: | |
55a08b3f | 10276 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10277 | return; |
65a21cd6 | 10278 | } |
4b0e333e | 10279 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10280 | |
fc6f93bc | 10281 | if (HAS_DDI(dev)) |
47bf17a7 | 10282 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10283 | |
55a08b3f ML |
10284 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10285 | cntl |= CURSOR_ROTATE_180; | |
10286 | } | |
4398ad45 | 10287 | |
4b0e333e CW |
10288 | if (intel_crtc->cursor_cntl != cntl) { |
10289 | I915_WRITE(CURCNTR(pipe), cntl); | |
10290 | POSTING_READ(CURCNTR(pipe)); | |
10291 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10292 | } |
4b0e333e | 10293 | |
65a21cd6 | 10294 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10295 | I915_WRITE(CURBASE(pipe), base); |
10296 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10297 | |
10298 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10299 | } |
10300 | ||
cda4b7d3 | 10301 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10302 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10303 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10304 | { |
10305 | struct drm_device *dev = crtc->dev; | |
10306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10307 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10308 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10309 | u32 base = intel_crtc->cursor_addr; |
10310 | u32 pos = 0; | |
cda4b7d3 | 10311 | |
55a08b3f ML |
10312 | if (plane_state) { |
10313 | int x = plane_state->base.crtc_x; | |
10314 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10315 | |
55a08b3f ML |
10316 | if (x < 0) { |
10317 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10318 | x = -x; | |
10319 | } | |
10320 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10321 | |
55a08b3f ML |
10322 | if (y < 0) { |
10323 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10324 | y = -y; | |
10325 | } | |
10326 | pos |= y << CURSOR_Y_SHIFT; | |
10327 | ||
10328 | /* ILK+ do this automagically */ | |
10329 | if (HAS_GMCH_DISPLAY(dev) && | |
10330 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10331 | base += (plane_state->base.crtc_h * | |
10332 | plane_state->base.crtc_w - 1) * 4; | |
10333 | } | |
cda4b7d3 | 10334 | } |
cda4b7d3 | 10335 | |
5efb3e28 VS |
10336 | I915_WRITE(CURPOS(pipe), pos); |
10337 | ||
8ac54669 | 10338 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10339 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10340 | else |
55a08b3f | 10341 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10342 | } |
10343 | ||
dc41c154 VS |
10344 | static bool cursor_size_ok(struct drm_device *dev, |
10345 | uint32_t width, uint32_t height) | |
10346 | { | |
10347 | if (width == 0 || height == 0) | |
10348 | return false; | |
10349 | ||
10350 | /* | |
10351 | * 845g/865g are special in that they are only limited by | |
10352 | * the width of their cursors, the height is arbitrary up to | |
10353 | * the precision of the register. Everything else requires | |
10354 | * square cursors, limited to a few power-of-two sizes. | |
10355 | */ | |
10356 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10357 | if ((width & 63) != 0) | |
10358 | return false; | |
10359 | ||
10360 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10361 | return false; | |
10362 | ||
10363 | if (height > 1023) | |
10364 | return false; | |
10365 | } else { | |
10366 | switch (width | height) { | |
10367 | case 256: | |
10368 | case 128: | |
10369 | if (IS_GEN2(dev)) | |
10370 | return false; | |
10371 | case 64: | |
10372 | break; | |
10373 | default: | |
10374 | return false; | |
10375 | } | |
10376 | } | |
10377 | ||
10378 | return true; | |
10379 | } | |
10380 | ||
79e53945 | 10381 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10382 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10383 | { |
7203425a | 10384 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10386 | |
7203425a | 10387 | for (i = start; i < end; i++) { |
79e53945 JB |
10388 | intel_crtc->lut_r[i] = red[i] >> 8; |
10389 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10390 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10391 | } | |
10392 | ||
10393 | intel_crtc_load_lut(crtc); | |
10394 | } | |
10395 | ||
79e53945 JB |
10396 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10397 | static struct drm_display_mode load_detect_mode = { | |
10398 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10399 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10400 | }; | |
10401 | ||
a8bb6818 DV |
10402 | struct drm_framebuffer * |
10403 | __intel_framebuffer_create(struct drm_device *dev, | |
10404 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10405 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10406 | { |
10407 | struct intel_framebuffer *intel_fb; | |
10408 | int ret; | |
10409 | ||
10410 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10411 | if (!intel_fb) |
d2dff872 | 10412 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10413 | |
10414 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10415 | if (ret) |
10416 | goto err; | |
d2dff872 CW |
10417 | |
10418 | return &intel_fb->base; | |
dcb1394e | 10419 | |
dd4916c5 | 10420 | err: |
dd4916c5 | 10421 | kfree(intel_fb); |
dd4916c5 | 10422 | return ERR_PTR(ret); |
d2dff872 CW |
10423 | } |
10424 | ||
b5ea642a | 10425 | static struct drm_framebuffer * |
a8bb6818 DV |
10426 | intel_framebuffer_create(struct drm_device *dev, |
10427 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10428 | struct drm_i915_gem_object *obj) | |
10429 | { | |
10430 | struct drm_framebuffer *fb; | |
10431 | int ret; | |
10432 | ||
10433 | ret = i915_mutex_lock_interruptible(dev); | |
10434 | if (ret) | |
10435 | return ERR_PTR(ret); | |
10436 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10437 | mutex_unlock(&dev->struct_mutex); | |
10438 | ||
10439 | return fb; | |
10440 | } | |
10441 | ||
d2dff872 CW |
10442 | static u32 |
10443 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10444 | { | |
10445 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10446 | return ALIGN(pitch, 64); | |
10447 | } | |
10448 | ||
10449 | static u32 | |
10450 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10451 | { | |
10452 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10453 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10454 | } |
10455 | ||
10456 | static struct drm_framebuffer * | |
10457 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10458 | struct drm_display_mode *mode, | |
10459 | int depth, int bpp) | |
10460 | { | |
dcb1394e | 10461 | struct drm_framebuffer *fb; |
d2dff872 | 10462 | struct drm_i915_gem_object *obj; |
0fed39bd | 10463 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10464 | |
10465 | obj = i915_gem_alloc_object(dev, | |
10466 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10467 | if (obj == NULL) | |
10468 | return ERR_PTR(-ENOMEM); | |
10469 | ||
10470 | mode_cmd.width = mode->hdisplay; | |
10471 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10472 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10473 | bpp); | |
5ca0c34a | 10474 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10475 | |
dcb1394e LW |
10476 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10477 | if (IS_ERR(fb)) | |
10478 | drm_gem_object_unreference_unlocked(&obj->base); | |
10479 | ||
10480 | return fb; | |
d2dff872 CW |
10481 | } |
10482 | ||
10483 | static struct drm_framebuffer * | |
10484 | mode_fits_in_fbdev(struct drm_device *dev, | |
10485 | struct drm_display_mode *mode) | |
10486 | { | |
0695726e | 10487 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10488 | struct drm_i915_private *dev_priv = dev->dev_private; |
10489 | struct drm_i915_gem_object *obj; | |
10490 | struct drm_framebuffer *fb; | |
10491 | ||
4c0e5528 | 10492 | if (!dev_priv->fbdev) |
d2dff872 CW |
10493 | return NULL; |
10494 | ||
4c0e5528 | 10495 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10496 | return NULL; |
10497 | ||
4c0e5528 DV |
10498 | obj = dev_priv->fbdev->fb->obj; |
10499 | BUG_ON(!obj); | |
10500 | ||
8bcd4553 | 10501 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10502 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10503 | fb->bits_per_pixel)) | |
d2dff872 CW |
10504 | return NULL; |
10505 | ||
01f2c773 | 10506 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10507 | return NULL; |
10508 | ||
edde3617 | 10509 | drm_framebuffer_reference(fb); |
d2dff872 | 10510 | return fb; |
4520f53a DV |
10511 | #else |
10512 | return NULL; | |
10513 | #endif | |
d2dff872 CW |
10514 | } |
10515 | ||
d3a40d1b ACO |
10516 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10517 | struct drm_crtc *crtc, | |
10518 | struct drm_display_mode *mode, | |
10519 | struct drm_framebuffer *fb, | |
10520 | int x, int y) | |
10521 | { | |
10522 | struct drm_plane_state *plane_state; | |
10523 | int hdisplay, vdisplay; | |
10524 | int ret; | |
10525 | ||
10526 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10527 | if (IS_ERR(plane_state)) | |
10528 | return PTR_ERR(plane_state); | |
10529 | ||
10530 | if (mode) | |
10531 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10532 | else | |
10533 | hdisplay = vdisplay = 0; | |
10534 | ||
10535 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10536 | if (ret) | |
10537 | return ret; | |
10538 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10539 | plane_state->crtc_x = 0; | |
10540 | plane_state->crtc_y = 0; | |
10541 | plane_state->crtc_w = hdisplay; | |
10542 | plane_state->crtc_h = vdisplay; | |
10543 | plane_state->src_x = x << 16; | |
10544 | plane_state->src_y = y << 16; | |
10545 | plane_state->src_w = hdisplay << 16; | |
10546 | plane_state->src_h = vdisplay << 16; | |
10547 | ||
10548 | return 0; | |
10549 | } | |
10550 | ||
d2434ab7 | 10551 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10552 | struct drm_display_mode *mode, |
51fd371b RC |
10553 | struct intel_load_detect_pipe *old, |
10554 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10555 | { |
10556 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10557 | struct intel_encoder *intel_encoder = |
10558 | intel_attached_encoder(connector); | |
79e53945 | 10559 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10560 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10561 | struct drm_crtc *crtc = NULL; |
10562 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10563 | struct drm_framebuffer *fb; |
51fd371b | 10564 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10565 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10566 | struct drm_connector_state *connector_state; |
4be07317 | 10567 | struct intel_crtc_state *crtc_state; |
51fd371b | 10568 | int ret, i = -1; |
79e53945 | 10569 | |
d2dff872 | 10570 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10571 | connector->base.id, connector->name, |
8e329a03 | 10572 | encoder->base.id, encoder->name); |
d2dff872 | 10573 | |
edde3617 ML |
10574 | old->restore_state = NULL; |
10575 | ||
51fd371b RC |
10576 | retry: |
10577 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10578 | if (ret) | |
ad3c558f | 10579 | goto fail; |
6e9f798d | 10580 | |
79e53945 JB |
10581 | /* |
10582 | * Algorithm gets a little messy: | |
7a5e4805 | 10583 | * |
79e53945 JB |
10584 | * - if the connector already has an assigned crtc, use it (but make |
10585 | * sure it's on first) | |
7a5e4805 | 10586 | * |
79e53945 JB |
10587 | * - try to find the first unused crtc that can drive this connector, |
10588 | * and use that if we find one | |
79e53945 JB |
10589 | */ |
10590 | ||
10591 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10592 | if (connector->state->crtc) { |
10593 | crtc = connector->state->crtc; | |
8261b191 | 10594 | |
51fd371b | 10595 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10596 | if (ret) |
ad3c558f | 10597 | goto fail; |
8261b191 CW |
10598 | |
10599 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10600 | goto found; |
79e53945 JB |
10601 | } |
10602 | ||
10603 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10604 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10605 | i++; |
10606 | if (!(encoder->possible_crtcs & (1 << i))) | |
10607 | continue; | |
edde3617 ML |
10608 | |
10609 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10610 | if (ret) | |
10611 | goto fail; | |
10612 | ||
10613 | if (possible_crtc->state->enable) { | |
10614 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10615 | continue; |
edde3617 | 10616 | } |
a459249c VS |
10617 | |
10618 | crtc = possible_crtc; | |
10619 | break; | |
79e53945 JB |
10620 | } |
10621 | ||
10622 | /* | |
10623 | * If we didn't find an unused CRTC, don't use any. | |
10624 | */ | |
10625 | if (!crtc) { | |
7173188d | 10626 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10627 | goto fail; |
79e53945 JB |
10628 | } |
10629 | ||
edde3617 ML |
10630 | found: |
10631 | intel_crtc = to_intel_crtc(crtc); | |
10632 | ||
4d02e2de DV |
10633 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10634 | if (ret) | |
ad3c558f | 10635 | goto fail; |
79e53945 | 10636 | |
83a57153 | 10637 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10638 | restore_state = drm_atomic_state_alloc(dev); |
10639 | if (!state || !restore_state) { | |
10640 | ret = -ENOMEM; | |
10641 | goto fail; | |
10642 | } | |
83a57153 ACO |
10643 | |
10644 | state->acquire_ctx = ctx; | |
edde3617 | 10645 | restore_state->acquire_ctx = ctx; |
83a57153 | 10646 | |
944b0c76 ACO |
10647 | connector_state = drm_atomic_get_connector_state(state, connector); |
10648 | if (IS_ERR(connector_state)) { | |
10649 | ret = PTR_ERR(connector_state); | |
10650 | goto fail; | |
10651 | } | |
10652 | ||
edde3617 ML |
10653 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10654 | if (ret) | |
10655 | goto fail; | |
944b0c76 | 10656 | |
4be07317 ACO |
10657 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10658 | if (IS_ERR(crtc_state)) { | |
10659 | ret = PTR_ERR(crtc_state); | |
10660 | goto fail; | |
10661 | } | |
10662 | ||
49d6fa21 | 10663 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10664 | |
6492711d CW |
10665 | if (!mode) |
10666 | mode = &load_detect_mode; | |
79e53945 | 10667 | |
d2dff872 CW |
10668 | /* We need a framebuffer large enough to accommodate all accesses |
10669 | * that the plane may generate whilst we perform load detection. | |
10670 | * We can not rely on the fbcon either being present (we get called | |
10671 | * during its initialisation to detect all boot displays, or it may | |
10672 | * not even exist) or that it is large enough to satisfy the | |
10673 | * requested mode. | |
10674 | */ | |
94352cf9 DV |
10675 | fb = mode_fits_in_fbdev(dev, mode); |
10676 | if (fb == NULL) { | |
d2dff872 | 10677 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10678 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10679 | } else |
10680 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10681 | if (IS_ERR(fb)) { |
d2dff872 | 10682 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10683 | goto fail; |
79e53945 | 10684 | } |
79e53945 | 10685 | |
d3a40d1b ACO |
10686 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10687 | if (ret) | |
10688 | goto fail; | |
10689 | ||
edde3617 ML |
10690 | drm_framebuffer_unreference(fb); |
10691 | ||
10692 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10693 | if (ret) | |
10694 | goto fail; | |
10695 | ||
10696 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10697 | if (!ret) | |
10698 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10699 | if (!ret) | |
10700 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10701 | if (ret) { | |
10702 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10703 | goto fail; | |
10704 | } | |
8c7b5ccb | 10705 | |
3ba86073 ML |
10706 | ret = drm_atomic_commit(state); |
10707 | if (ret) { | |
6492711d | 10708 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10709 | goto fail; |
79e53945 | 10710 | } |
edde3617 ML |
10711 | |
10712 | old->restore_state = restore_state; | |
7173188d | 10713 | |
79e53945 | 10714 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10715 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10716 | return true; |
412b61d8 | 10717 | |
ad3c558f | 10718 | fail: |
e5d958ef | 10719 | drm_atomic_state_free(state); |
edde3617 ML |
10720 | drm_atomic_state_free(restore_state); |
10721 | restore_state = state = NULL; | |
83a57153 | 10722 | |
51fd371b RC |
10723 | if (ret == -EDEADLK) { |
10724 | drm_modeset_backoff(ctx); | |
10725 | goto retry; | |
10726 | } | |
10727 | ||
412b61d8 | 10728 | return false; |
79e53945 JB |
10729 | } |
10730 | ||
d2434ab7 | 10731 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10732 | struct intel_load_detect_pipe *old, |
10733 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10734 | { |
d2434ab7 DV |
10735 | struct intel_encoder *intel_encoder = |
10736 | intel_attached_encoder(connector); | |
4ef69c7a | 10737 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10738 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10739 | int ret; |
79e53945 | 10740 | |
d2dff872 | 10741 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10742 | connector->base.id, connector->name, |
8e329a03 | 10743 | encoder->base.id, encoder->name); |
d2dff872 | 10744 | |
edde3617 | 10745 | if (!state) |
0622a53c | 10746 | return; |
79e53945 | 10747 | |
edde3617 ML |
10748 | ret = drm_atomic_commit(state); |
10749 | if (ret) { | |
10750 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10751 | drm_atomic_state_free(state); | |
10752 | } | |
79e53945 JB |
10753 | } |
10754 | ||
da4a1efa | 10755 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10756 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10757 | { |
10758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10759 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10760 | ||
10761 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10762 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10763 | else if (HAS_PCH_SPLIT(dev)) |
10764 | return 120000; | |
10765 | else if (!IS_GEN2(dev)) | |
10766 | return 96000; | |
10767 | else | |
10768 | return 48000; | |
10769 | } | |
10770 | ||
79e53945 | 10771 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10772 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10773 | struct intel_crtc_state *pipe_config) |
79e53945 | 10774 | { |
f1f644dc | 10775 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10776 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10777 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10778 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10779 | u32 fp; |
10780 | intel_clock_t clock; | |
dccbea3b | 10781 | int port_clock; |
da4a1efa | 10782 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10783 | |
10784 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10785 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10786 | else |
293623f7 | 10787 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10788 | |
10789 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10790 | if (IS_PINEVIEW(dev)) { |
10791 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10792 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10793 | } else { |
10794 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10795 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10796 | } | |
10797 | ||
a6c45cf0 | 10798 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10799 | if (IS_PINEVIEW(dev)) |
10800 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10801 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10802 | else |
10803 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10804 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10805 | ||
10806 | switch (dpll & DPLL_MODE_MASK) { | |
10807 | case DPLLB_MODE_DAC_SERIAL: | |
10808 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10809 | 5 : 10; | |
10810 | break; | |
10811 | case DPLLB_MODE_LVDS: | |
10812 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10813 | 7 : 14; | |
10814 | break; | |
10815 | default: | |
28c97730 | 10816 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10817 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10818 | return; |
79e53945 JB |
10819 | } |
10820 | ||
ac58c3f0 | 10821 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10822 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10823 | else |
dccbea3b | 10824 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10825 | } else { |
0fb58223 | 10826 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10827 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10828 | |
10829 | if (is_lvds) { | |
10830 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10831 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10832 | |
10833 | if (lvds & LVDS_CLKB_POWER_UP) | |
10834 | clock.p2 = 7; | |
10835 | else | |
10836 | clock.p2 = 14; | |
79e53945 JB |
10837 | } else { |
10838 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10839 | clock.p1 = 2; | |
10840 | else { | |
10841 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10842 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10843 | } | |
10844 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10845 | clock.p2 = 4; | |
10846 | else | |
10847 | clock.p2 = 2; | |
79e53945 | 10848 | } |
da4a1efa | 10849 | |
dccbea3b | 10850 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10851 | } |
10852 | ||
18442d08 VS |
10853 | /* |
10854 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10855 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10856 | * encoder's get_config() function. |
10857 | */ | |
dccbea3b | 10858 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10859 | } |
10860 | ||
6878da05 VS |
10861 | int intel_dotclock_calculate(int link_freq, |
10862 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10863 | { |
f1f644dc JB |
10864 | /* |
10865 | * The calculation for the data clock is: | |
1041a02f | 10866 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10867 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10868 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10869 | * |
10870 | * and the link clock is simpler: | |
1041a02f | 10871 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10872 | */ |
10873 | ||
6878da05 VS |
10874 | if (!m_n->link_n) |
10875 | return 0; | |
f1f644dc | 10876 | |
6878da05 VS |
10877 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10878 | } | |
f1f644dc | 10879 | |
18442d08 | 10880 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10881 | struct intel_crtc_state *pipe_config) |
6878da05 | 10882 | { |
e3b247da | 10883 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10884 | |
18442d08 VS |
10885 | /* read out port_clock from the DPLL */ |
10886 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10887 | |
f1f644dc | 10888 | /* |
e3b247da VS |
10889 | * In case there is an active pipe without active ports, |
10890 | * we may need some idea for the dotclock anyway. | |
10891 | * Calculate one based on the FDI configuration. | |
79e53945 | 10892 | */ |
2d112de7 | 10893 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10894 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10895 | &pipe_config->fdi_m_n); |
79e53945 JB |
10896 | } |
10897 | ||
10898 | /** Returns the currently programmed mode of the given pipe. */ | |
10899 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10900 | struct drm_crtc *crtc) | |
10901 | { | |
548f245b | 10902 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10903 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10904 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10905 | struct drm_display_mode *mode; |
3f36b937 | 10906 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10907 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10908 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10909 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10910 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10911 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10912 | |
10913 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10914 | if (!mode) | |
10915 | return NULL; | |
10916 | ||
3f36b937 TU |
10917 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10918 | if (!pipe_config) { | |
10919 | kfree(mode); | |
10920 | return NULL; | |
10921 | } | |
10922 | ||
f1f644dc JB |
10923 | /* |
10924 | * Construct a pipe_config sufficient for getting the clock info | |
10925 | * back out of crtc_clock_get. | |
10926 | * | |
10927 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10928 | * to use a real value here instead. | |
10929 | */ | |
3f36b937 TU |
10930 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10931 | pipe_config->pixel_multiplier = 1; | |
10932 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10933 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10934 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10935 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10936 | ||
10937 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10938 | mode->hdisplay = (htot & 0xffff) + 1; |
10939 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10940 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10941 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10942 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10943 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10944 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10945 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10946 | ||
10947 | drm_mode_set_name(mode); | |
79e53945 | 10948 | |
3f36b937 TU |
10949 | kfree(pipe_config); |
10950 | ||
79e53945 JB |
10951 | return mode; |
10952 | } | |
10953 | ||
f047e395 CW |
10954 | void intel_mark_busy(struct drm_device *dev) |
10955 | { | |
c67a470b PZ |
10956 | struct drm_i915_private *dev_priv = dev->dev_private; |
10957 | ||
f62a0076 CW |
10958 | if (dev_priv->mm.busy) |
10959 | return; | |
10960 | ||
43694d69 | 10961 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10962 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10963 | if (INTEL_INFO(dev)->gen >= 6) |
10964 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10965 | dev_priv->mm.busy = true; |
f047e395 CW |
10966 | } |
10967 | ||
10968 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10969 | { |
c67a470b | 10970 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10971 | |
f62a0076 CW |
10972 | if (!dev_priv->mm.busy) |
10973 | return; | |
10974 | ||
10975 | dev_priv->mm.busy = false; | |
10976 | ||
3d13ef2e | 10977 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10978 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10979 | |
43694d69 | 10980 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10981 | } |
10982 | ||
79e53945 JB |
10983 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10984 | { | |
10985 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10986 | struct drm_device *dev = crtc->dev; |
10987 | struct intel_unpin_work *work; | |
67e77c5a | 10988 | |
5e2d7afc | 10989 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10990 | work = intel_crtc->unpin_work; |
10991 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10992 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10993 | |
10994 | if (work) { | |
10995 | cancel_work_sync(&work->work); | |
10996 | kfree(work); | |
10997 | } | |
79e53945 JB |
10998 | |
10999 | drm_crtc_cleanup(crtc); | |
67e77c5a | 11000 | |
79e53945 JB |
11001 | kfree(intel_crtc); |
11002 | } | |
11003 | ||
6b95a207 KH |
11004 | static void intel_unpin_work_fn(struct work_struct *__work) |
11005 | { | |
11006 | struct intel_unpin_work *work = | |
11007 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
11008 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
11009 | struct drm_device *dev = crtc->base.dev; | |
11010 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 11011 | |
b4a98e57 | 11012 | mutex_lock(&dev->struct_mutex); |
3465c580 | 11013 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); |
05394f39 | 11014 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 11015 | |
f06cc1b9 | 11016 | if (work->flip_queued_req) |
146d84f0 | 11017 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
11018 | mutex_unlock(&dev->struct_mutex); |
11019 | ||
a9ff8714 | 11020 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 11021 | intel_fbc_post_update(crtc); |
89ed88ba | 11022 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 11023 | |
a9ff8714 VS |
11024 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11025 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 11026 | |
6b95a207 KH |
11027 | kfree(work); |
11028 | } | |
11029 | ||
1afe3e9d | 11030 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 11031 | struct drm_crtc *crtc) |
6b95a207 | 11032 | { |
6b95a207 KH |
11033 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11034 | struct intel_unpin_work *work; | |
6b95a207 KH |
11035 | unsigned long flags; |
11036 | ||
11037 | /* Ignore early vblank irqs */ | |
11038 | if (intel_crtc == NULL) | |
11039 | return; | |
11040 | ||
f326038a DV |
11041 | /* |
11042 | * This is called both by irq handlers and the reset code (to complete | |
11043 | * lost pageflips) so needs the full irqsave spinlocks. | |
11044 | */ | |
6b95a207 KH |
11045 | spin_lock_irqsave(&dev->event_lock, flags); |
11046 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
11047 | |
11048 | /* Ensure we don't miss a work->pending update ... */ | |
11049 | smp_rmb(); | |
11050 | ||
11051 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
11052 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11053 | return; | |
11054 | } | |
11055 | ||
d6bbafa1 | 11056 | page_flip_completed(intel_crtc); |
0af7e4df | 11057 | |
6b95a207 | 11058 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
11059 | } |
11060 | ||
1afe3e9d JB |
11061 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
11062 | { | |
fbee40df | 11063 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
11064 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11065 | ||
49b14a5c | 11066 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
11067 | } |
11068 | ||
11069 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
11070 | { | |
fbee40df | 11071 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
11072 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
11073 | ||
49b14a5c | 11074 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
11075 | } |
11076 | ||
75f7f3ec VS |
11077 | /* Is 'a' after or equal to 'b'? */ |
11078 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11079 | { | |
11080 | return !((a - b) & 0x80000000); | |
11081 | } | |
11082 | ||
11083 | static bool page_flip_finished(struct intel_crtc *crtc) | |
11084 | { | |
11085 | struct drm_device *dev = crtc->base.dev; | |
11086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11087 | ||
bdfa7542 VS |
11088 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
11089 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
11090 | return true; | |
11091 | ||
75f7f3ec VS |
11092 | /* |
11093 | * The relevant registers doen't exist on pre-ctg. | |
11094 | * As the flip done interrupt doesn't trigger for mmio | |
11095 | * flips on gmch platforms, a flip count check isn't | |
11096 | * really needed there. But since ctg has the registers, | |
11097 | * include it in the check anyway. | |
11098 | */ | |
11099 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11100 | return true; | |
11101 | ||
e8861675 ML |
11102 | /* |
11103 | * BDW signals flip done immediately if the plane | |
11104 | * is disabled, even if the plane enable is already | |
11105 | * armed to occur at the next vblank :( | |
11106 | */ | |
11107 | ||
75f7f3ec VS |
11108 | /* |
11109 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11110 | * used the same base address. In that case the mmio flip might | |
11111 | * have completed, but the CS hasn't even executed the flip yet. | |
11112 | * | |
11113 | * A flip count check isn't enough as the CS might have updated | |
11114 | * the base address just after start of vblank, but before we | |
11115 | * managed to process the interrupt. This means we'd complete the | |
11116 | * CS flip too soon. | |
11117 | * | |
11118 | * Combining both checks should get us a good enough result. It may | |
11119 | * still happen that the CS flip has been executed, but has not | |
11120 | * yet actually completed. But in case the base address is the same | |
11121 | * anyway, we don't really care. | |
11122 | */ | |
11123 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11124 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 11125 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
11126 | crtc->unpin_work->flip_count); |
11127 | } | |
11128 | ||
6b95a207 KH |
11129 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
11130 | { | |
fbee40df | 11131 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
11132 | struct intel_crtc *intel_crtc = |
11133 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
11134 | unsigned long flags; | |
11135 | ||
f326038a DV |
11136 | |
11137 | /* | |
11138 | * This is called both by irq handlers and the reset code (to complete | |
11139 | * lost pageflips) so needs the full irqsave spinlocks. | |
11140 | * | |
11141 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
11142 | * generate a page-flip completion irq, i.e. every modeset |
11143 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
11144 | */ | |
6b95a207 | 11145 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 11146 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 11147 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
11148 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11149 | } | |
11150 | ||
6042639c | 11151 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
11152 | { |
11153 | /* Ensure that the work item is consistent when activating it ... */ | |
11154 | smp_wmb(); | |
6042639c | 11155 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11156 | /* and that it is marked active as soon as the irq could fire. */ |
11157 | smp_wmb(); | |
11158 | } | |
11159 | ||
8c9f3aaf JB |
11160 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11161 | struct drm_crtc *crtc, | |
11162 | struct drm_framebuffer *fb, | |
ed8d1975 | 11163 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11164 | struct drm_i915_gem_request *req, |
ed8d1975 | 11165 | uint32_t flags) |
8c9f3aaf | 11166 | { |
6258fbe2 | 11167 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11168 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11169 | u32 flip_mask; |
11170 | int ret; | |
11171 | ||
5fb9de1a | 11172 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11173 | if (ret) |
4fa62c89 | 11174 | return ret; |
8c9f3aaf JB |
11175 | |
11176 | /* Can't queue multiple flips, so wait for the previous | |
11177 | * one to finish before executing the next. | |
11178 | */ | |
11179 | if (intel_crtc->plane) | |
11180 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11181 | else | |
11182 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11183 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11184 | intel_ring_emit(ring, MI_NOOP); | |
11185 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11186 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11187 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11188 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11189 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11190 | |
6042639c | 11191 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11192 | return 0; |
8c9f3aaf JB |
11193 | } |
11194 | ||
11195 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11196 | struct drm_crtc *crtc, | |
11197 | struct drm_framebuffer *fb, | |
ed8d1975 | 11198 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11199 | struct drm_i915_gem_request *req, |
ed8d1975 | 11200 | uint32_t flags) |
8c9f3aaf | 11201 | { |
6258fbe2 | 11202 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11203 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11204 | u32 flip_mask; |
11205 | int ret; | |
11206 | ||
5fb9de1a | 11207 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11208 | if (ret) |
4fa62c89 | 11209 | return ret; |
8c9f3aaf JB |
11210 | |
11211 | if (intel_crtc->plane) | |
11212 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11213 | else | |
11214 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11215 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11216 | intel_ring_emit(ring, MI_NOOP); | |
11217 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11218 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11219 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11220 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11221 | intel_ring_emit(ring, MI_NOOP); |
11222 | ||
6042639c | 11223 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11224 | return 0; |
8c9f3aaf JB |
11225 | } |
11226 | ||
11227 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11228 | struct drm_crtc *crtc, | |
11229 | struct drm_framebuffer *fb, | |
ed8d1975 | 11230 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11231 | struct drm_i915_gem_request *req, |
ed8d1975 | 11232 | uint32_t flags) |
8c9f3aaf | 11233 | { |
6258fbe2 | 11234 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11235 | struct drm_i915_private *dev_priv = dev->dev_private; |
11236 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11237 | uint32_t pf, pipesrc; | |
11238 | int ret; | |
11239 | ||
5fb9de1a | 11240 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11241 | if (ret) |
4fa62c89 | 11242 | return ret; |
8c9f3aaf JB |
11243 | |
11244 | /* i965+ uses the linear or tiled offsets from the | |
11245 | * Display Registers (which do not change across a page-flip) | |
11246 | * so we need only reprogram the base address. | |
11247 | */ | |
6d90c952 DV |
11248 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11249 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11250 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11251 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11252 | obj->tiling_mode); |
8c9f3aaf JB |
11253 | |
11254 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11255 | * untested on non-native modes, so ignore it for now. | |
11256 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11257 | */ | |
11258 | pf = 0; | |
11259 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11260 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11261 | |
6042639c | 11262 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11263 | return 0; |
8c9f3aaf JB |
11264 | } |
11265 | ||
11266 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11267 | struct drm_crtc *crtc, | |
11268 | struct drm_framebuffer *fb, | |
ed8d1975 | 11269 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11270 | struct drm_i915_gem_request *req, |
ed8d1975 | 11271 | uint32_t flags) |
8c9f3aaf | 11272 | { |
6258fbe2 | 11273 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11274 | struct drm_i915_private *dev_priv = dev->dev_private; |
11275 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11276 | uint32_t pf, pipesrc; | |
11277 | int ret; | |
11278 | ||
5fb9de1a | 11279 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11280 | if (ret) |
4fa62c89 | 11281 | return ret; |
8c9f3aaf | 11282 | |
6d90c952 DV |
11283 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11284 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11285 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11286 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11287 | |
dc257cf1 DV |
11288 | /* Contrary to the suggestions in the documentation, |
11289 | * "Enable Panel Fitter" does not seem to be required when page | |
11290 | * flipping with a non-native mode, and worse causes a normal | |
11291 | * modeset to fail. | |
11292 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11293 | */ | |
11294 | pf = 0; | |
8c9f3aaf | 11295 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11296 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11297 | |
6042639c | 11298 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11299 | return 0; |
8c9f3aaf JB |
11300 | } |
11301 | ||
7c9017e5 JB |
11302 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11303 | struct drm_crtc *crtc, | |
11304 | struct drm_framebuffer *fb, | |
ed8d1975 | 11305 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11306 | struct drm_i915_gem_request *req, |
ed8d1975 | 11307 | uint32_t flags) |
7c9017e5 | 11308 | { |
6258fbe2 | 11309 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11311 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11312 | int len, ret; |
11313 | ||
eba905b2 | 11314 | switch (intel_crtc->plane) { |
cb05d8de DV |
11315 | case PLANE_A: |
11316 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11317 | break; | |
11318 | case PLANE_B: | |
11319 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11320 | break; | |
11321 | case PLANE_C: | |
11322 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11323 | break; | |
11324 | default: | |
11325 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11326 | return -ENODEV; |
cb05d8de DV |
11327 | } |
11328 | ||
ffe74d75 | 11329 | len = 4; |
f476828a | 11330 | if (ring->id == RCS) { |
ffe74d75 | 11331 | len += 6; |
f476828a DL |
11332 | /* |
11333 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11334 | * 48bits addresses, and we need a NOOP for the batch size to | |
11335 | * stay even. | |
11336 | */ | |
11337 | if (IS_GEN8(dev)) | |
11338 | len += 2; | |
11339 | } | |
ffe74d75 | 11340 | |
f66fab8e VS |
11341 | /* |
11342 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11343 | * "The full packet must be contained within the same cache line." | |
11344 | * | |
11345 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11346 | * cacheline, if we ever start emitting more commands before | |
11347 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11348 | * then do the cacheline alignment, and finally emit the | |
11349 | * MI_DISPLAY_FLIP. | |
11350 | */ | |
bba09b12 | 11351 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11352 | if (ret) |
4fa62c89 | 11353 | return ret; |
f66fab8e | 11354 | |
5fb9de1a | 11355 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11356 | if (ret) |
4fa62c89 | 11357 | return ret; |
7c9017e5 | 11358 | |
ffe74d75 CW |
11359 | /* Unmask the flip-done completion message. Note that the bspec says that |
11360 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11361 | * more than one flip event at any time (or ensure that one flip message | |
11362 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11363 | * Experimentation says that BCS works despite DERRMR masking all | |
11364 | * flip-done completion events and that unmasking all planes at once | |
11365 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11366 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11367 | */ | |
11368 | if (ring->id == RCS) { | |
11369 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11370 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11371 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11372 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11373 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11374 | if (IS_GEN8(dev)) |
f1afe24f | 11375 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11376 | MI_SRM_LRM_GLOBAL_GTT); |
11377 | else | |
f1afe24f | 11378 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11379 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11380 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11381 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11382 | if (IS_GEN8(dev)) { |
11383 | intel_ring_emit(ring, 0); | |
11384 | intel_ring_emit(ring, MI_NOOP); | |
11385 | } | |
ffe74d75 CW |
11386 | } |
11387 | ||
cb05d8de | 11388 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11389 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11390 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11391 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11392 | |
6042639c | 11393 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11394 | return 0; |
7c9017e5 JB |
11395 | } |
11396 | ||
84c33a64 SG |
11397 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11398 | struct drm_i915_gem_object *obj) | |
11399 | { | |
11400 | /* | |
11401 | * This is not being used for older platforms, because | |
11402 | * non-availability of flip done interrupt forces us to use | |
11403 | * CS flips. Older platforms derive flip done using some clever | |
11404 | * tricks involving the flip_pending status bits and vblank irqs. | |
11405 | * So using MMIO flips there would disrupt this mechanism. | |
11406 | */ | |
11407 | ||
8e09bf83 CW |
11408 | if (ring == NULL) |
11409 | return true; | |
11410 | ||
84c33a64 SG |
11411 | if (INTEL_INFO(ring->dev)->gen < 5) |
11412 | return false; | |
11413 | ||
11414 | if (i915.use_mmio_flip < 0) | |
11415 | return false; | |
11416 | else if (i915.use_mmio_flip > 0) | |
11417 | return true; | |
14bf993e OM |
11418 | else if (i915.enable_execlists) |
11419 | return true; | |
fd8e058a AG |
11420 | else if (obj->base.dma_buf && |
11421 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11422 | false)) | |
11423 | return true; | |
84c33a64 | 11424 | else |
b4716185 | 11425 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11426 | } |
11427 | ||
6042639c | 11428 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11429 | unsigned int rotation, |
6042639c | 11430 | struct intel_unpin_work *work) |
ff944564 DL |
11431 | { |
11432 | struct drm_device *dev = intel_crtc->base.dev; | |
11433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11434 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11435 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11436 | u32 ctl, stride, tile_height; |
ff944564 DL |
11437 | |
11438 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11439 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11440 | switch (fb->modifier[0]) { |
11441 | case DRM_FORMAT_MOD_NONE: | |
11442 | break; | |
11443 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11444 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11445 | break; |
11446 | case I915_FORMAT_MOD_Y_TILED: | |
11447 | ctl |= PLANE_CTL_TILED_Y; | |
11448 | break; | |
11449 | case I915_FORMAT_MOD_Yf_TILED: | |
11450 | ctl |= PLANE_CTL_TILED_YF; | |
11451 | break; | |
11452 | default: | |
11453 | MISSING_CASE(fb->modifier[0]); | |
11454 | } | |
ff944564 DL |
11455 | |
11456 | /* | |
11457 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11458 | * linear buffers or in number of tiles for tiled buffers. | |
11459 | */ | |
86efe24a TU |
11460 | if (intel_rotation_90_or_270(rotation)) { |
11461 | /* stride = Surface height in tiles */ | |
832be82f | 11462 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11463 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11464 | } else { | |
11465 | stride = fb->pitches[0] / | |
7b49f948 VS |
11466 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11467 | fb->pixel_format); | |
86efe24a | 11468 | } |
ff944564 DL |
11469 | |
11470 | /* | |
11471 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11472 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11473 | */ | |
11474 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11475 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11476 | ||
6042639c | 11477 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11478 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11479 | } | |
11480 | ||
6042639c CW |
11481 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11482 | struct intel_unpin_work *work) | |
84c33a64 SG |
11483 | { |
11484 | struct drm_device *dev = intel_crtc->base.dev; | |
11485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11486 | struct intel_framebuffer *intel_fb = | |
11487 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11488 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11489 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11490 | u32 dspcntr; |
84c33a64 | 11491 | |
84c33a64 SG |
11492 | dspcntr = I915_READ(reg); |
11493 | ||
c5d97472 DL |
11494 | if (obj->tiling_mode != I915_TILING_NONE) |
11495 | dspcntr |= DISPPLANE_TILED; | |
11496 | else | |
11497 | dspcntr &= ~DISPPLANE_TILED; | |
11498 | ||
84c33a64 SG |
11499 | I915_WRITE(reg, dspcntr); |
11500 | ||
6042639c | 11501 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11502 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11503 | } |
11504 | ||
11505 | /* | |
11506 | * XXX: This is the temporary way to update the plane registers until we get | |
11507 | * around to using the usual plane update functions for MMIO flips | |
11508 | */ | |
6042639c | 11509 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11510 | { |
6042639c CW |
11511 | struct intel_crtc *crtc = mmio_flip->crtc; |
11512 | struct intel_unpin_work *work; | |
11513 | ||
11514 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11515 | work = crtc->unpin_work; | |
11516 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11517 | if (work == NULL) | |
11518 | return; | |
ff944564 | 11519 | |
6042639c | 11520 | intel_mark_page_flip_active(work); |
ff944564 | 11521 | |
6042639c | 11522 | intel_pipe_update_start(crtc); |
ff944564 | 11523 | |
6042639c | 11524 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11525 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11526 | else |
11527 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11528 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11529 | |
6042639c | 11530 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11531 | } |
11532 | ||
9362c7c5 | 11533 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11534 | { |
b2cfe0ab CW |
11535 | struct intel_mmio_flip *mmio_flip = |
11536 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11537 | struct intel_framebuffer *intel_fb = |
11538 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11539 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11540 | |
6042639c | 11541 | if (mmio_flip->req) { |
eed29a5b | 11542 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11543 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11544 | false, NULL, |
11545 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11546 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11547 | } | |
84c33a64 | 11548 | |
fd8e058a AG |
11549 | /* For framebuffer backed by dmabuf, wait for fence */ |
11550 | if (obj->base.dma_buf) | |
11551 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11552 | false, false, | |
11553 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11554 | ||
6042639c | 11555 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11556 | kfree(mmio_flip); |
84c33a64 SG |
11557 | } |
11558 | ||
11559 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11560 | struct drm_crtc *crtc, | |
86efe24a | 11561 | struct drm_i915_gem_object *obj) |
84c33a64 | 11562 | { |
b2cfe0ab CW |
11563 | struct intel_mmio_flip *mmio_flip; |
11564 | ||
11565 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11566 | if (mmio_flip == NULL) | |
11567 | return -ENOMEM; | |
84c33a64 | 11568 | |
bcafc4e3 | 11569 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11570 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11571 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11572 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11573 | |
b2cfe0ab CW |
11574 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11575 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11576 | |
84c33a64 SG |
11577 | return 0; |
11578 | } | |
11579 | ||
8c9f3aaf JB |
11580 | static int intel_default_queue_flip(struct drm_device *dev, |
11581 | struct drm_crtc *crtc, | |
11582 | struct drm_framebuffer *fb, | |
ed8d1975 | 11583 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11584 | struct drm_i915_gem_request *req, |
ed8d1975 | 11585 | uint32_t flags) |
8c9f3aaf JB |
11586 | { |
11587 | return -ENODEV; | |
11588 | } | |
11589 | ||
d6bbafa1 CW |
11590 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11591 | struct drm_crtc *crtc) | |
11592 | { | |
11593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11594 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11595 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11596 | u32 addr; | |
11597 | ||
11598 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11599 | return true; | |
11600 | ||
908565c2 CW |
11601 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11602 | return false; | |
11603 | ||
d6bbafa1 CW |
11604 | if (!work->enable_stall_check) |
11605 | return false; | |
11606 | ||
11607 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11608 | if (work->flip_queued_req && |
11609 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11610 | return false; |
11611 | ||
1e3feefd | 11612 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11613 | } |
11614 | ||
1e3feefd | 11615 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11616 | return false; |
11617 | ||
11618 | /* Potential stall - if we see that the flip has happened, | |
11619 | * assume a missed interrupt. */ | |
11620 | if (INTEL_INFO(dev)->gen >= 4) | |
11621 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11622 | else | |
11623 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11624 | ||
11625 | /* There is a potential issue here with a false positive after a flip | |
11626 | * to the same address. We could address this by checking for a | |
11627 | * non-incrementing frame counter. | |
11628 | */ | |
11629 | return addr == work->gtt_offset; | |
11630 | } | |
11631 | ||
11632 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11633 | { | |
11634 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11635 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11636 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11637 | struct intel_unpin_work *work; |
f326038a | 11638 | |
6c51d46f | 11639 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11640 | |
11641 | if (crtc == NULL) | |
11642 | return; | |
11643 | ||
f326038a | 11644 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11645 | work = intel_crtc->unpin_work; |
11646 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11647 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11648 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11649 | page_flip_completed(intel_crtc); |
6ad790c0 | 11650 | work = NULL; |
d6bbafa1 | 11651 | } |
6ad790c0 CW |
11652 | if (work != NULL && |
11653 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11654 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11655 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11656 | } |
11657 | ||
6b95a207 KH |
11658 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11659 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11660 | struct drm_pending_vblank_event *event, |
11661 | uint32_t page_flip_flags) | |
6b95a207 KH |
11662 | { |
11663 | struct drm_device *dev = crtc->dev; | |
11664 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11665 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11666 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11667 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11668 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11669 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11670 | struct intel_unpin_work *work; |
a4872ba6 | 11671 | struct intel_engine_cs *ring; |
cf5d8a46 | 11672 | bool mmio_flip; |
91af127f | 11673 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11674 | int ret; |
6b95a207 | 11675 | |
2ff8fde1 MR |
11676 | /* |
11677 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11678 | * check to be safe. In the future we may enable pageflipping from | |
11679 | * a disabled primary plane. | |
11680 | */ | |
11681 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11682 | return -EBUSY; | |
11683 | ||
e6a595d2 | 11684 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11685 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11686 | return -EINVAL; |
11687 | ||
11688 | /* | |
11689 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11690 | * Note that pitch changes could also affect these register. | |
11691 | */ | |
11692 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11693 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11694 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11695 | return -EINVAL; |
11696 | ||
f900db47 CW |
11697 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11698 | goto out_hang; | |
11699 | ||
b14c5679 | 11700 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11701 | if (work == NULL) |
11702 | return -ENOMEM; | |
11703 | ||
6b95a207 | 11704 | work->event = event; |
b4a98e57 | 11705 | work->crtc = crtc; |
ab8d6675 | 11706 | work->old_fb = old_fb; |
6b95a207 KH |
11707 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11708 | ||
87b6b101 | 11709 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11710 | if (ret) |
11711 | goto free_work; | |
11712 | ||
6b95a207 | 11713 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11714 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11715 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11716 | /* Before declaring the flip queue wedged, check if |
11717 | * the hardware completed the operation behind our backs. | |
11718 | */ | |
11719 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11720 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11721 | page_flip_completed(intel_crtc); | |
11722 | } else { | |
11723 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11724 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11725 | |
d6bbafa1 CW |
11726 | drm_crtc_vblank_put(crtc); |
11727 | kfree(work); | |
11728 | return -EBUSY; | |
11729 | } | |
6b95a207 KH |
11730 | } |
11731 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11732 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11733 | |
b4a98e57 CW |
11734 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11735 | flush_workqueue(dev_priv->wq); | |
11736 | ||
75dfca80 | 11737 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11738 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11739 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11740 | |
f4510a27 | 11741 | crtc->primary->fb = fb; |
afd65eb4 | 11742 | update_state_fb(crtc->primary); |
e8216e50 | 11743 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11744 | |
e1f99ce6 | 11745 | work->pending_flip_obj = obj; |
e1f99ce6 | 11746 | |
89ed88ba CW |
11747 | ret = i915_mutex_lock_interruptible(dev); |
11748 | if (ret) | |
11749 | goto cleanup; | |
11750 | ||
b4a98e57 | 11751 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11752 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11753 | |
75f7f3ec | 11754 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11755 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11756 | |
666a4537 | 11757 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11758 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11759 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11760 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11761 | ring = NULL; | |
48bf5b2d | 11762 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11763 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11764 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11765 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11766 | if (ring == NULL || ring->id != RCS) |
11767 | ring = &dev_priv->ring[BCS]; | |
11768 | } else { | |
11769 | ring = &dev_priv->ring[RCS]; | |
11770 | } | |
11771 | ||
cf5d8a46 CW |
11772 | mmio_flip = use_mmio_flip(ring, obj); |
11773 | ||
11774 | /* When using CS flips, we want to emit semaphores between rings. | |
11775 | * However, when using mmio flips we will create a task to do the | |
11776 | * synchronisation, so all we want here is to pin the framebuffer | |
11777 | * into the display plane and skip any waits. | |
11778 | */ | |
7580d774 ML |
11779 | if (!mmio_flip) { |
11780 | ret = i915_gem_object_sync(obj, ring, &request); | |
11781 | if (ret) | |
11782 | goto cleanup_pending; | |
11783 | } | |
11784 | ||
3465c580 | 11785 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
8c9f3aaf JB |
11786 | if (ret) |
11787 | goto cleanup_pending; | |
6b95a207 | 11788 | |
dedf278c TU |
11789 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11790 | obj, 0); | |
11791 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11792 | |
cf5d8a46 | 11793 | if (mmio_flip) { |
86efe24a | 11794 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11795 | if (ret) |
11796 | goto cleanup_unpin; | |
11797 | ||
f06cc1b9 JH |
11798 | i915_gem_request_assign(&work->flip_queued_req, |
11799 | obj->last_write_req); | |
d6bbafa1 | 11800 | } else { |
6258fbe2 | 11801 | if (!request) { |
26827088 DG |
11802 | request = i915_gem_request_alloc(ring, NULL); |
11803 | if (IS_ERR(request)) { | |
11804 | ret = PTR_ERR(request); | |
6258fbe2 | 11805 | goto cleanup_unpin; |
26827088 | 11806 | } |
6258fbe2 JH |
11807 | } |
11808 | ||
11809 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11810 | page_flip_flags); |
11811 | if (ret) | |
11812 | goto cleanup_unpin; | |
11813 | ||
6258fbe2 | 11814 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11815 | } |
11816 | ||
91af127f | 11817 | if (request) |
75289874 | 11818 | i915_add_request_no_flush(request); |
91af127f | 11819 | |
1e3feefd | 11820 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11821 | work->enable_stall_check = true; |
4fa62c89 | 11822 | |
ab8d6675 | 11823 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11824 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11825 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11826 | |
a9ff8714 VS |
11827 | intel_frontbuffer_flip_prepare(dev, |
11828 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11829 | |
e5510fac JB |
11830 | trace_i915_flip_request(intel_crtc->plane, obj); |
11831 | ||
6b95a207 | 11832 | return 0; |
96b099fd | 11833 | |
4fa62c89 | 11834 | cleanup_unpin: |
3465c580 | 11835 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); |
8c9f3aaf | 11836 | cleanup_pending: |
0aa498d5 | 11837 | if (!IS_ERR_OR_NULL(request)) |
91af127f | 11838 | i915_gem_request_cancel(request); |
b4a98e57 | 11839 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11840 | mutex_unlock(&dev->struct_mutex); |
11841 | cleanup: | |
f4510a27 | 11842 | crtc->primary->fb = old_fb; |
afd65eb4 | 11843 | update_state_fb(crtc->primary); |
89ed88ba CW |
11844 | |
11845 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11846 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11847 | |
5e2d7afc | 11848 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11849 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11850 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11851 | |
87b6b101 | 11852 | drm_crtc_vblank_put(crtc); |
7317c75e | 11853 | free_work: |
96b099fd CW |
11854 | kfree(work); |
11855 | ||
f900db47 | 11856 | if (ret == -EIO) { |
02e0efb5 ML |
11857 | struct drm_atomic_state *state; |
11858 | struct drm_plane_state *plane_state; | |
11859 | ||
f900db47 | 11860 | out_hang: |
02e0efb5 ML |
11861 | state = drm_atomic_state_alloc(dev); |
11862 | if (!state) | |
11863 | return -ENOMEM; | |
11864 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11865 | ||
11866 | retry: | |
11867 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11868 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11869 | if (!ret) { | |
11870 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11871 | ||
11872 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11873 | if (!ret) | |
11874 | ret = drm_atomic_commit(state); | |
11875 | } | |
11876 | ||
11877 | if (ret == -EDEADLK) { | |
11878 | drm_modeset_backoff(state->acquire_ctx); | |
11879 | drm_atomic_state_clear(state); | |
11880 | goto retry; | |
11881 | } | |
11882 | ||
11883 | if (ret) | |
11884 | drm_atomic_state_free(state); | |
11885 | ||
f0d3dad3 | 11886 | if (ret == 0 && event) { |
5e2d7afc | 11887 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11888 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11889 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11890 | } |
f900db47 | 11891 | } |
96b099fd | 11892 | return ret; |
6b95a207 KH |
11893 | } |
11894 | ||
da20eabd ML |
11895 | |
11896 | /** | |
11897 | * intel_wm_need_update - Check whether watermarks need updating | |
11898 | * @plane: drm plane | |
11899 | * @state: new plane state | |
11900 | * | |
11901 | * Check current plane state versus the new one to determine whether | |
11902 | * watermarks need to be recalculated. | |
11903 | * | |
11904 | * Returns true or false. | |
11905 | */ | |
11906 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11907 | struct drm_plane_state *state) | |
11908 | { | |
d21fbe87 MR |
11909 | struct intel_plane_state *new = to_intel_plane_state(state); |
11910 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11911 | ||
11912 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11913 | if (new->visible != cur->visible) |
11914 | return true; | |
11915 | ||
11916 | if (!cur->base.fb || !new->base.fb) | |
11917 | return false; | |
11918 | ||
11919 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11920 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11921 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11922 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11923 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11924 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11925 | return true; |
7809e5ae | 11926 | |
2791a16c | 11927 | return false; |
7809e5ae MR |
11928 | } |
11929 | ||
d21fbe87 MR |
11930 | static bool needs_scaling(struct intel_plane_state *state) |
11931 | { | |
11932 | int src_w = drm_rect_width(&state->src) >> 16; | |
11933 | int src_h = drm_rect_height(&state->src) >> 16; | |
11934 | int dst_w = drm_rect_width(&state->dst); | |
11935 | int dst_h = drm_rect_height(&state->dst); | |
11936 | ||
11937 | return (src_w != dst_w || src_h != dst_h); | |
11938 | } | |
11939 | ||
da20eabd ML |
11940 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11941 | struct drm_plane_state *plane_state) | |
11942 | { | |
ab1d3a0e | 11943 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11944 | struct drm_crtc *crtc = crtc_state->crtc; |
11945 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11946 | struct drm_plane *plane = plane_state->plane; | |
11947 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11948 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11949 | struct intel_plane_state *old_plane_state = |
11950 | to_intel_plane_state(plane->state); | |
11951 | int idx = intel_crtc->base.base.id, ret; | |
da20eabd ML |
11952 | bool mode_changed = needs_modeset(crtc_state); |
11953 | bool was_crtc_enabled = crtc->state->active; | |
11954 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11955 | bool turn_off, turn_on, visible, was_visible; |
11956 | struct drm_framebuffer *fb = plane_state->fb; | |
11957 | ||
11958 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11959 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11960 | ret = skl_update_scaler_plane( | |
11961 | to_intel_crtc_state(crtc_state), | |
11962 | to_intel_plane_state(plane_state)); | |
11963 | if (ret) | |
11964 | return ret; | |
11965 | } | |
11966 | ||
da20eabd ML |
11967 | was_visible = old_plane_state->visible; |
11968 | visible = to_intel_plane_state(plane_state)->visible; | |
11969 | ||
11970 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11971 | was_visible = false; | |
11972 | ||
35c08f43 ML |
11973 | /* |
11974 | * Visibility is calculated as if the crtc was on, but | |
11975 | * after scaler setup everything depends on it being off | |
11976 | * when the crtc isn't active. | |
11977 | */ | |
11978 | if (!is_crtc_enabled) | |
11979 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11980 | |
11981 | if (!was_visible && !visible) | |
11982 | return 0; | |
11983 | ||
e8861675 ML |
11984 | if (fb != old_plane_state->base.fb) |
11985 | pipe_config->fb_changed = true; | |
11986 | ||
da20eabd ML |
11987 | turn_off = was_visible && (!visible || mode_changed); |
11988 | turn_on = visible && (!was_visible || mode_changed); | |
11989 | ||
11990 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11991 | plane->base.id, fb ? fb->base.id : -1); | |
11992 | ||
11993 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11994 | plane->base.id, was_visible, visible, | |
11995 | turn_off, turn_on, mode_changed); | |
11996 | ||
92826fcd ML |
11997 | if (turn_on || turn_off) { |
11998 | pipe_config->wm_changed = true; | |
11999 | ||
852eb00d | 12000 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 12001 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 12002 | pipe_config->disable_cxsr = true; |
852eb00d | 12003 | } else if (intel_wm_need_update(plane, plane_state)) { |
92826fcd | 12004 | pipe_config->wm_changed = true; |
852eb00d | 12005 | } |
da20eabd | 12006 | |
ed4a6a7c MR |
12007 | /* Pre-gen9 platforms need two-step watermark updates */ |
12008 | if (pipe_config->wm_changed && INTEL_INFO(dev)->gen < 9 && | |
12009 | dev_priv->display.optimize_watermarks) | |
12010 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; | |
12011 | ||
8be6ca85 | 12012 | if (visible || was_visible) |
a9ff8714 VS |
12013 | intel_crtc->atomic.fb_bits |= |
12014 | to_intel_plane(plane)->frontbuffer_bit; | |
12015 | ||
da20eabd ML |
12016 | switch (plane->type) { |
12017 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd | 12018 | intel_crtc->atomic.post_enable_primary = turn_on; |
fcf38d13 | 12019 | intel_crtc->atomic.update_fbc = true; |
da20eabd | 12020 | |
da20eabd ML |
12021 | break; |
12022 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
12023 | break; |
12024 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
12025 | /* |
12026 | * WaCxSRDisabledForSpriteScaling:ivb | |
12027 | * | |
12028 | * cstate->update_wm was already set above, so this flag will | |
12029 | * take effect when we commit and program watermarks. | |
12030 | */ | |
12031 | if (IS_IVYBRIDGE(dev) && | |
12032 | needs_scaling(to_intel_plane_state(plane_state)) && | |
e8861675 ML |
12033 | !needs_scaling(old_plane_state)) |
12034 | pipe_config->disable_lp_wm = true; | |
d21fbe87 MR |
12035 | |
12036 | break; | |
da20eabd ML |
12037 | } |
12038 | return 0; | |
12039 | } | |
12040 | ||
6d3a1ce7 ML |
12041 | static bool encoders_cloneable(const struct intel_encoder *a, |
12042 | const struct intel_encoder *b) | |
12043 | { | |
12044 | /* masks could be asymmetric, so check both ways */ | |
12045 | return a == b || (a->cloneable & (1 << b->type) && | |
12046 | b->cloneable & (1 << a->type)); | |
12047 | } | |
12048 | ||
12049 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12050 | struct intel_crtc *crtc, | |
12051 | struct intel_encoder *encoder) | |
12052 | { | |
12053 | struct intel_encoder *source_encoder; | |
12054 | struct drm_connector *connector; | |
12055 | struct drm_connector_state *connector_state; | |
12056 | int i; | |
12057 | ||
12058 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12059 | if (connector_state->crtc != &crtc->base) | |
12060 | continue; | |
12061 | ||
12062 | source_encoder = | |
12063 | to_intel_encoder(connector_state->best_encoder); | |
12064 | if (!encoders_cloneable(encoder, source_encoder)) | |
12065 | return false; | |
12066 | } | |
12067 | ||
12068 | return true; | |
12069 | } | |
12070 | ||
12071 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
12072 | struct intel_crtc *crtc) | |
12073 | { | |
12074 | struct intel_encoder *encoder; | |
12075 | struct drm_connector *connector; | |
12076 | struct drm_connector_state *connector_state; | |
12077 | int i; | |
12078 | ||
12079 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12080 | if (connector_state->crtc != &crtc->base) | |
12081 | continue; | |
12082 | ||
12083 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12084 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
12085 | return false; | |
12086 | } | |
12087 | ||
12088 | return true; | |
12089 | } | |
12090 | ||
12091 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
12092 | struct drm_crtc_state *crtc_state) | |
12093 | { | |
cf5a15be | 12094 | struct drm_device *dev = crtc->dev; |
ad421372 | 12095 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 12096 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12097 | struct intel_crtc_state *pipe_config = |
12098 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12099 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12100 | int ret; |
6d3a1ce7 ML |
12101 | bool mode_changed = needs_modeset(crtc_state); |
12102 | ||
12103 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
12104 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12105 | return -EINVAL; | |
12106 | } | |
12107 | ||
852eb00d | 12108 | if (mode_changed && !crtc_state->active) |
92826fcd | 12109 | pipe_config->wm_changed = true; |
eddfcbcd | 12110 | |
ad421372 ML |
12111 | if (mode_changed && crtc_state->enable && |
12112 | dev_priv->display.crtc_compute_clock && | |
12113 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
12114 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
12115 | pipe_config); | |
12116 | if (ret) | |
12117 | return ret; | |
12118 | } | |
12119 | ||
e435d6e5 | 12120 | ret = 0; |
86c8bbbe | 12121 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12122 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12123 | if (ret) { |
12124 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12125 | return ret; | |
12126 | } | |
12127 | } | |
12128 | ||
12129 | if (dev_priv->display.compute_intermediate_wm && | |
12130 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12131 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12132 | return 0; | |
12133 | ||
12134 | /* | |
12135 | * Calculate 'intermediate' watermarks that satisfy both the | |
12136 | * old state and the new state. We can program these | |
12137 | * immediately. | |
12138 | */ | |
12139 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12140 | intel_crtc, | |
12141 | pipe_config); | |
12142 | if (ret) { | |
12143 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12144 | return ret; |
ed4a6a7c | 12145 | } |
86c8bbbe MR |
12146 | } |
12147 | ||
e435d6e5 ML |
12148 | if (INTEL_INFO(dev)->gen >= 9) { |
12149 | if (mode_changed) | |
12150 | ret = skl_update_scaler_crtc(pipe_config); | |
12151 | ||
12152 | if (!ret) | |
12153 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12154 | pipe_config); | |
12155 | } | |
12156 | ||
12157 | return ret; | |
6d3a1ce7 ML |
12158 | } |
12159 | ||
65b38e0d | 12160 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
12161 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
12162 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
12163 | .atomic_begin = intel_begin_crtc_commit, |
12164 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12165 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12166 | }; |
12167 | ||
d29b2f9d ACO |
12168 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12169 | { | |
12170 | struct intel_connector *connector; | |
12171 | ||
12172 | for_each_intel_connector(dev, connector) { | |
12173 | if (connector->base.encoder) { | |
12174 | connector->base.state->best_encoder = | |
12175 | connector->base.encoder; | |
12176 | connector->base.state->crtc = | |
12177 | connector->base.encoder->crtc; | |
12178 | } else { | |
12179 | connector->base.state->best_encoder = NULL; | |
12180 | connector->base.state->crtc = NULL; | |
12181 | } | |
12182 | } | |
12183 | } | |
12184 | ||
050f7aeb | 12185 | static void |
eba905b2 | 12186 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12187 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12188 | { |
12189 | int bpp = pipe_config->pipe_bpp; | |
12190 | ||
12191 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12192 | connector->base.base.id, | |
c23cc417 | 12193 | connector->base.name); |
050f7aeb DV |
12194 | |
12195 | /* Don't use an invalid EDID bpc value */ | |
12196 | if (connector->base.display_info.bpc && | |
12197 | connector->base.display_info.bpc * 3 < bpp) { | |
12198 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12199 | bpp, connector->base.display_info.bpc*3); | |
12200 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12201 | } | |
12202 | ||
013dd9e0 JN |
12203 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12204 | if (connector->base.display_info.bpc == 0) { | |
12205 | int type = connector->base.connector_type; | |
12206 | int clamp_bpp = 24; | |
12207 | ||
12208 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12209 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12210 | type == DRM_MODE_CONNECTOR_eDP) | |
12211 | clamp_bpp = 18; | |
12212 | ||
12213 | if (bpp > clamp_bpp) { | |
12214 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12215 | bpp, clamp_bpp); | |
12216 | pipe_config->pipe_bpp = clamp_bpp; | |
12217 | } | |
050f7aeb DV |
12218 | } |
12219 | } | |
12220 | ||
4e53c2e0 | 12221 | static int |
050f7aeb | 12222 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12223 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12224 | { |
050f7aeb | 12225 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12226 | struct drm_atomic_state *state; |
da3ced29 ACO |
12227 | struct drm_connector *connector; |
12228 | struct drm_connector_state *connector_state; | |
1486017f | 12229 | int bpp, i; |
4e53c2e0 | 12230 | |
666a4537 | 12231 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12232 | bpp = 10*3; |
d328c9d7 DV |
12233 | else if (INTEL_INFO(dev)->gen >= 5) |
12234 | bpp = 12*3; | |
12235 | else | |
12236 | bpp = 8*3; | |
12237 | ||
4e53c2e0 | 12238 | |
4e53c2e0 DV |
12239 | pipe_config->pipe_bpp = bpp; |
12240 | ||
1486017f ACO |
12241 | state = pipe_config->base.state; |
12242 | ||
4e53c2e0 | 12243 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12244 | for_each_connector_in_state(state, connector, connector_state, i) { |
12245 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12246 | continue; |
12247 | ||
da3ced29 ACO |
12248 | connected_sink_compute_bpp(to_intel_connector(connector), |
12249 | pipe_config); | |
4e53c2e0 DV |
12250 | } |
12251 | ||
12252 | return bpp; | |
12253 | } | |
12254 | ||
644db711 DV |
12255 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12256 | { | |
12257 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12258 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12259 | mode->crtc_clock, |
644db711 DV |
12260 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12261 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12262 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12263 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12264 | } | |
12265 | ||
c0b03411 | 12266 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12267 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12268 | const char *context) |
12269 | { | |
6a60cd87 CK |
12270 | struct drm_device *dev = crtc->base.dev; |
12271 | struct drm_plane *plane; | |
12272 | struct intel_plane *intel_plane; | |
12273 | struct intel_plane_state *state; | |
12274 | struct drm_framebuffer *fb; | |
12275 | ||
12276 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12277 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12278 | |
12279 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12280 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12281 | pipe_config->pipe_bpp, pipe_config->dither); | |
12282 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12283 | pipe_config->has_pch_encoder, | |
12284 | pipe_config->fdi_lanes, | |
12285 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12286 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12287 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12288 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12289 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12290 | pipe_config->lane_count, |
eb14cb74 VS |
12291 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12292 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12293 | pipe_config->dp_m_n.tu); | |
b95af8be | 12294 | |
90a6b7b0 | 12295 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12296 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12297 | pipe_config->lane_count, |
b95af8be VK |
12298 | pipe_config->dp_m2_n2.gmch_m, |
12299 | pipe_config->dp_m2_n2.gmch_n, | |
12300 | pipe_config->dp_m2_n2.link_m, | |
12301 | pipe_config->dp_m2_n2.link_n, | |
12302 | pipe_config->dp_m2_n2.tu); | |
12303 | ||
55072d19 DV |
12304 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12305 | pipe_config->has_audio, | |
12306 | pipe_config->has_infoframe); | |
12307 | ||
c0b03411 | 12308 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12309 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12310 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12311 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12312 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12313 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12314 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12315 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12316 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12317 | crtc->num_scalers, | |
12318 | pipe_config->scaler_state.scaler_users, | |
12319 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12320 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12321 | pipe_config->gmch_pfit.control, | |
12322 | pipe_config->gmch_pfit.pgm_ratios, | |
12323 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12324 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12325 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12326 | pipe_config->pch_pfit.size, |
12327 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12328 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12329 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12330 | |
415ff0f6 | 12331 | if (IS_BROXTON(dev)) { |
05712c15 | 12332 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12333 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12334 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12335 | pipe_config->ddi_pll_sel, |
12336 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12337 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12338 | pipe_config->dpll_hw_state.pll0, |
12339 | pipe_config->dpll_hw_state.pll1, | |
12340 | pipe_config->dpll_hw_state.pll2, | |
12341 | pipe_config->dpll_hw_state.pll3, | |
12342 | pipe_config->dpll_hw_state.pll6, | |
12343 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12344 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12345 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12346 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12347 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12348 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12349 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12350 | pipe_config->ddi_pll_sel, | |
12351 | pipe_config->dpll_hw_state.ctrl1, | |
12352 | pipe_config->dpll_hw_state.cfgcr1, | |
12353 | pipe_config->dpll_hw_state.cfgcr2); | |
12354 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12355 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12356 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12357 | pipe_config->dpll_hw_state.wrpll, |
12358 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12359 | } else { |
12360 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12361 | "fp0: 0x%x, fp1: 0x%x\n", | |
12362 | pipe_config->dpll_hw_state.dpll, | |
12363 | pipe_config->dpll_hw_state.dpll_md, | |
12364 | pipe_config->dpll_hw_state.fp0, | |
12365 | pipe_config->dpll_hw_state.fp1); | |
12366 | } | |
12367 | ||
6a60cd87 CK |
12368 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12369 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12370 | intel_plane = to_intel_plane(plane); | |
12371 | if (intel_plane->pipe != crtc->pipe) | |
12372 | continue; | |
12373 | ||
12374 | state = to_intel_plane_state(plane->state); | |
12375 | fb = state->base.fb; | |
12376 | if (!fb) { | |
12377 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12378 | "disabled, scaler_id = %d\n", | |
12379 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12380 | plane->base.id, intel_plane->pipe, | |
12381 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12382 | drm_plane_index(plane), state->scaler_id); | |
12383 | continue; | |
12384 | } | |
12385 | ||
12386 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12387 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12388 | plane->base.id, intel_plane->pipe, | |
12389 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12390 | drm_plane_index(plane)); | |
12391 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12392 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12393 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12394 | state->scaler_id, | |
12395 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12396 | drm_rect_width(&state->src) >> 16, | |
12397 | drm_rect_height(&state->src) >> 16, | |
12398 | state->dst.x1, state->dst.y1, | |
12399 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12400 | } | |
c0b03411 DV |
12401 | } |
12402 | ||
5448a00d | 12403 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12404 | { |
5448a00d | 12405 | struct drm_device *dev = state->dev; |
da3ced29 | 12406 | struct drm_connector *connector; |
00f0b378 VS |
12407 | unsigned int used_ports = 0; |
12408 | ||
12409 | /* | |
12410 | * Walk the connector list instead of the encoder | |
12411 | * list to detect the problem on ddi platforms | |
12412 | * where there's just one encoder per digital port. | |
12413 | */ | |
0bff4858 VS |
12414 | drm_for_each_connector(connector, dev) { |
12415 | struct drm_connector_state *connector_state; | |
12416 | struct intel_encoder *encoder; | |
12417 | ||
12418 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12419 | if (!connector_state) | |
12420 | connector_state = connector->state; | |
12421 | ||
5448a00d | 12422 | if (!connector_state->best_encoder) |
00f0b378 VS |
12423 | continue; |
12424 | ||
5448a00d ACO |
12425 | encoder = to_intel_encoder(connector_state->best_encoder); |
12426 | ||
12427 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12428 | |
12429 | switch (encoder->type) { | |
12430 | unsigned int port_mask; | |
12431 | case INTEL_OUTPUT_UNKNOWN: | |
12432 | if (WARN_ON(!HAS_DDI(dev))) | |
12433 | break; | |
12434 | case INTEL_OUTPUT_DISPLAYPORT: | |
12435 | case INTEL_OUTPUT_HDMI: | |
12436 | case INTEL_OUTPUT_EDP: | |
12437 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12438 | ||
12439 | /* the same port mustn't appear more than once */ | |
12440 | if (used_ports & port_mask) | |
12441 | return false; | |
12442 | ||
12443 | used_ports |= port_mask; | |
12444 | default: | |
12445 | break; | |
12446 | } | |
12447 | } | |
12448 | ||
12449 | return true; | |
12450 | } | |
12451 | ||
83a57153 ACO |
12452 | static void |
12453 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12454 | { | |
12455 | struct drm_crtc_state tmp_state; | |
663a3640 | 12456 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12457 | struct intel_dpll_hw_state dpll_hw_state; |
12458 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12459 | uint32_t ddi_pll_sel; |
c4e2d043 | 12460 | bool force_thru; |
83a57153 | 12461 | |
7546a384 ACO |
12462 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12463 | * kzalloc'd. Code that depends on any field being zero should be | |
12464 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12465 | * only fields that are know to not cause problems are preserved. */ | |
12466 | ||
83a57153 | 12467 | tmp_state = crtc_state->base; |
663a3640 | 12468 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12469 | shared_dpll = crtc_state->shared_dpll; |
12470 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12471 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12472 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12473 | |
83a57153 | 12474 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12475 | |
83a57153 | 12476 | crtc_state->base = tmp_state; |
663a3640 | 12477 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12478 | crtc_state->shared_dpll = shared_dpll; |
12479 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12480 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12481 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12482 | } |
12483 | ||
548ee15b | 12484 | static int |
b8cecdf5 | 12485 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12486 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12487 | { |
b359283a | 12488 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12489 | struct intel_encoder *encoder; |
da3ced29 | 12490 | struct drm_connector *connector; |
0b901879 | 12491 | struct drm_connector_state *connector_state; |
d328c9d7 | 12492 | int base_bpp, ret = -EINVAL; |
0b901879 | 12493 | int i; |
e29c22c0 | 12494 | bool retry = true; |
ee7b9f93 | 12495 | |
83a57153 | 12496 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12497 | |
e143a21c DV |
12498 | pipe_config->cpu_transcoder = |
12499 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12500 | |
2960bc9c ID |
12501 | /* |
12502 | * Sanitize sync polarity flags based on requested ones. If neither | |
12503 | * positive or negative polarity is requested, treat this as meaning | |
12504 | * negative polarity. | |
12505 | */ | |
2d112de7 | 12506 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12507 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12508 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12509 | |
2d112de7 | 12510 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12511 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12512 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12513 | |
d328c9d7 DV |
12514 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12515 | pipe_config); | |
12516 | if (base_bpp < 0) | |
4e53c2e0 DV |
12517 | goto fail; |
12518 | ||
e41a56be VS |
12519 | /* |
12520 | * Determine the real pipe dimensions. Note that stereo modes can | |
12521 | * increase the actual pipe size due to the frame doubling and | |
12522 | * insertion of additional space for blanks between the frame. This | |
12523 | * is stored in the crtc timings. We use the requested mode to do this | |
12524 | * computation to clearly distinguish it from the adjusted mode, which | |
12525 | * can be changed by the connectors in the below retry loop. | |
12526 | */ | |
2d112de7 | 12527 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12528 | &pipe_config->pipe_src_w, |
12529 | &pipe_config->pipe_src_h); | |
e41a56be | 12530 | |
e29c22c0 | 12531 | encoder_retry: |
ef1b460d | 12532 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12533 | pipe_config->port_clock = 0; |
ef1b460d | 12534 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12535 | |
135c81b8 | 12536 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12537 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12538 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12539 | |
7758a113 DV |
12540 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12541 | * adjust it according to limitations or connector properties, and also | |
12542 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12543 | */ |
da3ced29 | 12544 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12545 | if (connector_state->crtc != crtc) |
7758a113 | 12546 | continue; |
7ae89233 | 12547 | |
0b901879 ACO |
12548 | encoder = to_intel_encoder(connector_state->best_encoder); |
12549 | ||
efea6e8e DV |
12550 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12551 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12552 | goto fail; |
12553 | } | |
ee7b9f93 | 12554 | } |
47f1c6c9 | 12555 | |
ff9a6750 DV |
12556 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12557 | * done afterwards in case the encoder adjusts the mode. */ | |
12558 | if (!pipe_config->port_clock) | |
2d112de7 | 12559 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12560 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12561 | |
a43f6e0f | 12562 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12563 | if (ret < 0) { |
7758a113 DV |
12564 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12565 | goto fail; | |
ee7b9f93 | 12566 | } |
e29c22c0 DV |
12567 | |
12568 | if (ret == RETRY) { | |
12569 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12570 | ret = -EINVAL; | |
12571 | goto fail; | |
12572 | } | |
12573 | ||
12574 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12575 | retry = false; | |
12576 | goto encoder_retry; | |
12577 | } | |
12578 | ||
e8fa4270 DV |
12579 | /* Dithering seems to not pass-through bits correctly when it should, so |
12580 | * only enable it on 6bpc panels. */ | |
12581 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12582 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12583 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12584 | |
7758a113 | 12585 | fail: |
548ee15b | 12586 | return ret; |
ee7b9f93 | 12587 | } |
47f1c6c9 | 12588 | |
ea9d758d | 12589 | static void |
4740b0f2 | 12590 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12591 | { |
0a9ab303 ACO |
12592 | struct drm_crtc *crtc; |
12593 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12594 | int i; |
ea9d758d | 12595 | |
7668851f | 12596 | /* Double check state. */ |
8a75d157 | 12597 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12598 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12599 | |
12600 | /* Update hwmode for vblank functions */ | |
12601 | if (crtc->state->active) | |
12602 | crtc->hwmode = crtc->state->adjusted_mode; | |
12603 | else | |
12604 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12605 | |
12606 | /* | |
12607 | * Update legacy state to satisfy fbc code. This can | |
12608 | * be removed when fbc uses the atomic state. | |
12609 | */ | |
12610 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12611 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12612 | ||
12613 | crtc->primary->fb = plane_state->fb; | |
12614 | crtc->x = plane_state->src_x >> 16; | |
12615 | crtc->y = plane_state->src_y >> 16; | |
12616 | } | |
ea9d758d | 12617 | } |
ea9d758d DV |
12618 | } |
12619 | ||
3bd26263 | 12620 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12621 | { |
3bd26263 | 12622 | int diff; |
f1f644dc JB |
12623 | |
12624 | if (clock1 == clock2) | |
12625 | return true; | |
12626 | ||
12627 | if (!clock1 || !clock2) | |
12628 | return false; | |
12629 | ||
12630 | diff = abs(clock1 - clock2); | |
12631 | ||
12632 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12633 | return true; | |
12634 | ||
12635 | return false; | |
12636 | } | |
12637 | ||
25c5b266 DV |
12638 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12639 | list_for_each_entry((intel_crtc), \ | |
12640 | &(dev)->mode_config.crtc_list, \ | |
12641 | base.head) \ | |
95150bdf | 12642 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12643 | |
cfb23ed6 ML |
12644 | static bool |
12645 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12646 | unsigned int m2, unsigned int n2, | |
12647 | bool exact) | |
12648 | { | |
12649 | if (m == m2 && n == n2) | |
12650 | return true; | |
12651 | ||
12652 | if (exact || !m || !n || !m2 || !n2) | |
12653 | return false; | |
12654 | ||
12655 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12656 | ||
31d10b57 ML |
12657 | if (n > n2) { |
12658 | while (n > n2) { | |
cfb23ed6 ML |
12659 | m2 <<= 1; |
12660 | n2 <<= 1; | |
12661 | } | |
31d10b57 ML |
12662 | } else if (n < n2) { |
12663 | while (n < n2) { | |
cfb23ed6 ML |
12664 | m <<= 1; |
12665 | n <<= 1; | |
12666 | } | |
12667 | } | |
12668 | ||
31d10b57 ML |
12669 | if (n != n2) |
12670 | return false; | |
12671 | ||
12672 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12673 | } |
12674 | ||
12675 | static bool | |
12676 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12677 | struct intel_link_m_n *m2_n2, | |
12678 | bool adjust) | |
12679 | { | |
12680 | if (m_n->tu == m2_n2->tu && | |
12681 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12682 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12683 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12684 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12685 | if (adjust) | |
12686 | *m2_n2 = *m_n; | |
12687 | ||
12688 | return true; | |
12689 | } | |
12690 | ||
12691 | return false; | |
12692 | } | |
12693 | ||
0e8ffe1b | 12694 | static bool |
2fa2fe9a | 12695 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12696 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12697 | struct intel_crtc_state *pipe_config, |
12698 | bool adjust) | |
0e8ffe1b | 12699 | { |
cfb23ed6 ML |
12700 | bool ret = true; |
12701 | ||
12702 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12703 | do { \ | |
12704 | if (!adjust) \ | |
12705 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12706 | else \ | |
12707 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12708 | } while (0) | |
12709 | ||
66e985c0 DV |
12710 | #define PIPE_CONF_CHECK_X(name) \ |
12711 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12712 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12713 | "(expected 0x%08x, found 0x%08x)\n", \ |
12714 | current_config->name, \ | |
12715 | pipe_config->name); \ | |
cfb23ed6 | 12716 | ret = false; \ |
66e985c0 DV |
12717 | } |
12718 | ||
08a24034 DV |
12719 | #define PIPE_CONF_CHECK_I(name) \ |
12720 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12721 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12722 | "(expected %i, found %i)\n", \ |
12723 | current_config->name, \ | |
12724 | pipe_config->name); \ | |
cfb23ed6 ML |
12725 | ret = false; \ |
12726 | } | |
12727 | ||
12728 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12729 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12730 | &pipe_config->name,\ | |
12731 | adjust)) { \ | |
12732 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12733 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12734 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12735 | current_config->name.tu, \ | |
12736 | current_config->name.gmch_m, \ | |
12737 | current_config->name.gmch_n, \ | |
12738 | current_config->name.link_m, \ | |
12739 | current_config->name.link_n, \ | |
12740 | pipe_config->name.tu, \ | |
12741 | pipe_config->name.gmch_m, \ | |
12742 | pipe_config->name.gmch_n, \ | |
12743 | pipe_config->name.link_m, \ | |
12744 | pipe_config->name.link_n); \ | |
12745 | ret = false; \ | |
12746 | } | |
12747 | ||
12748 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12749 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12750 | &pipe_config->name, adjust) && \ | |
12751 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12752 | &pipe_config->name, adjust)) { \ | |
12753 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12754 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12755 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12756 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12757 | current_config->name.tu, \ | |
12758 | current_config->name.gmch_m, \ | |
12759 | current_config->name.gmch_n, \ | |
12760 | current_config->name.link_m, \ | |
12761 | current_config->name.link_n, \ | |
12762 | current_config->alt_name.tu, \ | |
12763 | current_config->alt_name.gmch_m, \ | |
12764 | current_config->alt_name.gmch_n, \ | |
12765 | current_config->alt_name.link_m, \ | |
12766 | current_config->alt_name.link_n, \ | |
12767 | pipe_config->name.tu, \ | |
12768 | pipe_config->name.gmch_m, \ | |
12769 | pipe_config->name.gmch_n, \ | |
12770 | pipe_config->name.link_m, \ | |
12771 | pipe_config->name.link_n); \ | |
12772 | ret = false; \ | |
88adfff1 DV |
12773 | } |
12774 | ||
b95af8be VK |
12775 | /* This is required for BDW+ where there is only one set of registers for |
12776 | * switching between high and low RR. | |
12777 | * This macro can be used whenever a comparison has to be made between one | |
12778 | * hw state and multiple sw state variables. | |
12779 | */ | |
12780 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12781 | if ((current_config->name != pipe_config->name) && \ | |
12782 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12783 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12784 | "(expected %i or %i, found %i)\n", \ |
12785 | current_config->name, \ | |
12786 | current_config->alt_name, \ | |
12787 | pipe_config->name); \ | |
cfb23ed6 | 12788 | ret = false; \ |
b95af8be VK |
12789 | } |
12790 | ||
1bd1bd80 DV |
12791 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12792 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12793 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12794 | "(expected %i, found %i)\n", \ |
12795 | current_config->name & (mask), \ | |
12796 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12797 | ret = false; \ |
1bd1bd80 DV |
12798 | } |
12799 | ||
5e550656 VS |
12800 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12801 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12802 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12803 | "(expected %i, found %i)\n", \ |
12804 | current_config->name, \ | |
12805 | pipe_config->name); \ | |
cfb23ed6 | 12806 | ret = false; \ |
5e550656 VS |
12807 | } |
12808 | ||
bb760063 DV |
12809 | #define PIPE_CONF_QUIRK(quirk) \ |
12810 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12811 | ||
eccb140b DV |
12812 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12813 | ||
08a24034 DV |
12814 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12815 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12816 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12817 | |
eb14cb74 | 12818 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12819 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12820 | |
12821 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12822 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12823 | ||
cfb23ed6 ML |
12824 | if (current_config->has_drrs) |
12825 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12826 | } else | |
12827 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12828 | |
a65347ba JN |
12829 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12830 | ||
2d112de7 ACO |
12831 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12832 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12833 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12834 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12835 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12836 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12837 | |
2d112de7 ACO |
12838 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12839 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12840 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12841 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12842 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12843 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12844 | |
c93f54cf | 12845 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12846 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12847 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12848 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12849 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12850 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12851 | |
9ed109a7 DV |
12852 | PIPE_CONF_CHECK_I(has_audio); |
12853 | ||
2d112de7 | 12854 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12855 | DRM_MODE_FLAG_INTERLACE); |
12856 | ||
bb760063 | 12857 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12858 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12859 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12860 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12861 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12862 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12863 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12864 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12865 | DRM_MODE_FLAG_NVSYNC); |
12866 | } | |
045ac3b5 | 12867 | |
333b8ca8 | 12868 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12869 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12870 | if (INTEL_INFO(dev)->gen < 4) | |
12871 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12872 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12873 | |
bfd16b2a ML |
12874 | if (!adjust) { |
12875 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12876 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12877 | ||
12878 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12879 | if (current_config->pch_pfit.enabled) { | |
12880 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12881 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12882 | } | |
2fa2fe9a | 12883 | |
7aefe2b5 ML |
12884 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12885 | } | |
a1b2278e | 12886 | |
e59150dc JB |
12887 | /* BDW+ don't expose a synchronous way to read the state */ |
12888 | if (IS_HASWELL(dev)) | |
12889 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12890 | |
282740f7 VS |
12891 | PIPE_CONF_CHECK_I(double_wide); |
12892 | ||
26804afd DV |
12893 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12894 | ||
c0d43d62 | 12895 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12896 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12897 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12898 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12899 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12900 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12901 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12902 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12903 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12904 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12905 | |
42571aef VS |
12906 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12907 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12908 | ||
2d112de7 | 12909 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12910 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12911 | |
66e985c0 | 12912 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12913 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12914 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12915 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12916 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12917 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12918 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12919 | |
cfb23ed6 | 12920 | return ret; |
0e8ffe1b DV |
12921 | } |
12922 | ||
e3b247da VS |
12923 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12924 | const struct intel_crtc_state *pipe_config) | |
12925 | { | |
12926 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12927 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12928 | &pipe_config->fdi_m_n); |
12929 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12930 | ||
12931 | /* | |
12932 | * FDI already provided one idea for the dotclock. | |
12933 | * Yell if the encoder disagrees. | |
12934 | */ | |
12935 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12936 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12937 | fdi_dotclock, dotclock); | |
12938 | } | |
12939 | } | |
12940 | ||
08db6652 DL |
12941 | static void check_wm_state(struct drm_device *dev) |
12942 | { | |
12943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12944 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12945 | struct intel_crtc *intel_crtc; | |
12946 | int plane; | |
12947 | ||
12948 | if (INTEL_INFO(dev)->gen < 9) | |
12949 | return; | |
12950 | ||
12951 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12952 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12953 | ||
12954 | for_each_intel_crtc(dev, intel_crtc) { | |
12955 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12956 | const enum pipe pipe = intel_crtc->pipe; | |
12957 | ||
12958 | if (!intel_crtc->active) | |
12959 | continue; | |
12960 | ||
12961 | /* planes */ | |
dd740780 | 12962 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12963 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12964 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12965 | ||
12966 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12967 | continue; | |
12968 | ||
12969 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12970 | "(expected (%u,%u), found (%u,%u))\n", | |
12971 | pipe_name(pipe), plane + 1, | |
12972 | sw_entry->start, sw_entry->end, | |
12973 | hw_entry->start, hw_entry->end); | |
12974 | } | |
12975 | ||
12976 | /* cursor */ | |
4969d33e MR |
12977 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12978 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12979 | |
12980 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12981 | continue; | |
12982 | ||
12983 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12984 | "(expected (%u,%u), found (%u,%u))\n", | |
12985 | pipe_name(pipe), | |
12986 | sw_entry->start, sw_entry->end, | |
12987 | hw_entry->start, hw_entry->end); | |
12988 | } | |
12989 | } | |
12990 | ||
91d1b4bd | 12991 | static void |
35dd3c64 ML |
12992 | check_connector_state(struct drm_device *dev, |
12993 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12994 | { |
35dd3c64 ML |
12995 | struct drm_connector_state *old_conn_state; |
12996 | struct drm_connector *connector; | |
12997 | int i; | |
8af6cf88 | 12998 | |
35dd3c64 ML |
12999 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
13000 | struct drm_encoder *encoder = connector->encoder; | |
13001 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 13002 | |
8af6cf88 DV |
13003 | /* This also checks the encoder/connector hw state with the |
13004 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 13005 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 13006 | |
ad3c558f | 13007 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 13008 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 13009 | } |
91d1b4bd DV |
13010 | } |
13011 | ||
13012 | static void | |
13013 | check_encoder_state(struct drm_device *dev) | |
13014 | { | |
13015 | struct intel_encoder *encoder; | |
13016 | struct intel_connector *connector; | |
8af6cf88 | 13017 | |
b2784e15 | 13018 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13019 | bool enabled = false; |
4d20cd86 | 13020 | enum pipe pipe; |
8af6cf88 DV |
13021 | |
13022 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13023 | encoder->base.base.id, | |
8e329a03 | 13024 | encoder->base.name); |
8af6cf88 | 13025 | |
3a3371ff | 13026 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13027 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13028 | continue; |
13029 | enabled = true; | |
ad3c558f ML |
13030 | |
13031 | I915_STATE_WARN(connector->base.state->crtc != | |
13032 | encoder->base.crtc, | |
13033 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13034 | } |
0e32b39c | 13035 | |
e2c719b7 | 13036 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13037 | "encoder's enabled state mismatch " |
13038 | "(expected %i, found %i)\n", | |
13039 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13040 | |
13041 | if (!encoder->base.crtc) { | |
4d20cd86 | 13042 | bool active; |
7c60d198 | 13043 | |
4d20cd86 ML |
13044 | active = encoder->get_hw_state(encoder, &pipe); |
13045 | I915_STATE_WARN(active, | |
13046 | "encoder detached but still enabled on pipe %c.\n", | |
13047 | pipe_name(pipe)); | |
7c60d198 | 13048 | } |
8af6cf88 | 13049 | } |
91d1b4bd DV |
13050 | } |
13051 | ||
13052 | static void | |
4d20cd86 | 13053 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 13054 | { |
fbee40df | 13055 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 13056 | struct intel_encoder *encoder; |
4d20cd86 ML |
13057 | struct drm_crtc_state *old_crtc_state; |
13058 | struct drm_crtc *crtc; | |
13059 | int i; | |
8af6cf88 | 13060 | |
4d20cd86 ML |
13061 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
13062 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13063 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 13064 | bool active; |
8af6cf88 | 13065 | |
bfd16b2a ML |
13066 | if (!needs_modeset(crtc->state) && |
13067 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 13068 | continue; |
045ac3b5 | 13069 | |
4d20cd86 ML |
13070 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
13071 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
13072 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13073 | pipe_config->base.crtc = crtc; | |
13074 | pipe_config->base.state = old_state; | |
8af6cf88 | 13075 | |
4d20cd86 ML |
13076 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
13077 | crtc->base.id); | |
8af6cf88 | 13078 | |
4d20cd86 ML |
13079 | active = dev_priv->display.get_pipe_config(intel_crtc, |
13080 | pipe_config); | |
d62cf62a | 13081 | |
b6b5d049 | 13082 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
13083 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
13084 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13085 | active = crtc->state->active; | |
6c49f241 | 13086 | |
4d20cd86 | 13087 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 13088 | "crtc active state doesn't match with hw state " |
4d20cd86 | 13089 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 13090 | |
4d20cd86 | 13091 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 13092 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
13093 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
13094 | ||
13095 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
13096 | enum pipe pipe; | |
13097 | ||
13098 | active = encoder->get_hw_state(encoder, &pipe); | |
13099 | I915_STATE_WARN(active != crtc->state->active, | |
13100 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13101 | encoder->base.base.id, active, crtc->state->active); | |
13102 | ||
13103 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
13104 | "Encoder connected to wrong pipe %c\n", | |
13105 | pipe_name(pipe)); | |
13106 | ||
13107 | if (active) | |
13108 | encoder->get_config(encoder, pipe_config); | |
13109 | } | |
53d9f4e9 | 13110 | |
4d20cd86 | 13111 | if (!crtc->state->active) |
cfb23ed6 ML |
13112 | continue; |
13113 | ||
e3b247da VS |
13114 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
13115 | ||
4d20cd86 ML |
13116 | sw_config = to_intel_crtc_state(crtc->state); |
13117 | if (!intel_pipe_config_compare(dev, sw_config, | |
13118 | pipe_config, false)) { | |
e2c719b7 | 13119 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 13120 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 13121 | "[hw state]"); |
4d20cd86 | 13122 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
13123 | "[sw state]"); |
13124 | } | |
8af6cf88 DV |
13125 | } |
13126 | } | |
13127 | ||
91d1b4bd DV |
13128 | static void |
13129 | check_shared_dpll_state(struct drm_device *dev) | |
13130 | { | |
fbee40df | 13131 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
13132 | struct intel_crtc *crtc; |
13133 | struct intel_dpll_hw_state dpll_hw_state; | |
13134 | int i; | |
5358901f DV |
13135 | |
13136 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
13137 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13138 | int enabled_crtcs = 0, active_crtcs = 0; | |
13139 | bool active; | |
13140 | ||
13141 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
13142 | ||
13143 | DRM_DEBUG_KMS("%s\n", pll->name); | |
13144 | ||
13145 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
13146 | ||
e2c719b7 | 13147 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 13148 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 13149 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 13150 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 13151 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 13152 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 13153 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 13154 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
13155 | "pll on state mismatch (expected %i, found %i)\n", |
13156 | pll->on, active); | |
13157 | ||
d3fcc808 | 13158 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 13159 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
13160 | enabled_crtcs++; |
13161 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
13162 | active_crtcs++; | |
13163 | } | |
e2c719b7 | 13164 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
13165 | "pll active crtcs mismatch (expected %i, found %i)\n", |
13166 | pll->active, active_crtcs); | |
e2c719b7 | 13167 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 13168 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 13169 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 13170 | |
e2c719b7 | 13171 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
13172 | sizeof(dpll_hw_state)), |
13173 | "pll hw state mismatch\n"); | |
5358901f | 13174 | } |
8af6cf88 DV |
13175 | } |
13176 | ||
ee165b1a ML |
13177 | static void |
13178 | intel_modeset_check_state(struct drm_device *dev, | |
13179 | struct drm_atomic_state *old_state) | |
91d1b4bd | 13180 | { |
08db6652 | 13181 | check_wm_state(dev); |
35dd3c64 | 13182 | check_connector_state(dev, old_state); |
91d1b4bd | 13183 | check_encoder_state(dev); |
4d20cd86 | 13184 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
13185 | check_shared_dpll_state(dev); |
13186 | } | |
13187 | ||
80715b2f VS |
13188 | static void update_scanline_offset(struct intel_crtc *crtc) |
13189 | { | |
13190 | struct drm_device *dev = crtc->base.dev; | |
13191 | ||
13192 | /* | |
13193 | * The scanline counter increments at the leading edge of hsync. | |
13194 | * | |
13195 | * On most platforms it starts counting from vtotal-1 on the | |
13196 | * first active line. That means the scanline counter value is | |
13197 | * always one less than what we would expect. Ie. just after | |
13198 | * start of vblank, which also occurs at start of hsync (on the | |
13199 | * last active line), the scanline counter will read vblank_start-1. | |
13200 | * | |
13201 | * On gen2 the scanline counter starts counting from 1 instead | |
13202 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13203 | * to keep the value positive), instead of adding one. | |
13204 | * | |
13205 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13206 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13207 | * there's an extra 1 line difference. So we need to add two instead of | |
13208 | * one to the value. | |
13209 | */ | |
13210 | if (IS_GEN2(dev)) { | |
124abe07 | 13211 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13212 | int vtotal; |
13213 | ||
124abe07 VS |
13214 | vtotal = adjusted_mode->crtc_vtotal; |
13215 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13216 | vtotal /= 2; |
13217 | ||
13218 | crtc->scanline_offset = vtotal - 1; | |
13219 | } else if (HAS_DDI(dev) && | |
409ee761 | 13220 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13221 | crtc->scanline_offset = 2; |
13222 | } else | |
13223 | crtc->scanline_offset = 1; | |
13224 | } | |
13225 | ||
ad421372 | 13226 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13227 | { |
225da59b | 13228 | struct drm_device *dev = state->dev; |
ed6739ef | 13229 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13230 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13231 | struct drm_crtc *crtc; |
13232 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13233 | int i; |
ed6739ef ACO |
13234 | |
13235 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13236 | return; |
ed6739ef | 13237 | |
0a9ab303 | 13238 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 ML |
13239 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13240 | int old_dpll = to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13241 | |
fb1a38a9 | 13242 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13243 | continue; |
13244 | ||
fb1a38a9 ML |
13245 | to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE; |
13246 | ||
13247 | if (old_dpll == DPLL_ID_PRIVATE) | |
13248 | continue; | |
0a9ab303 | 13249 | |
ad421372 ML |
13250 | if (!shared_dpll) |
13251 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13252 | |
fb1a38a9 | 13253 | shared_dpll[old_dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
ad421372 | 13254 | } |
ed6739ef ACO |
13255 | } |
13256 | ||
99d736a2 ML |
13257 | /* |
13258 | * This implements the workaround described in the "notes" section of the mode | |
13259 | * set sequence documentation. When going from no pipes or single pipe to | |
13260 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13261 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13262 | */ | |
13263 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13264 | { | |
13265 | struct drm_crtc_state *crtc_state; | |
13266 | struct intel_crtc *intel_crtc; | |
13267 | struct drm_crtc *crtc; | |
13268 | struct intel_crtc_state *first_crtc_state = NULL; | |
13269 | struct intel_crtc_state *other_crtc_state = NULL; | |
13270 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13271 | int i; | |
13272 | ||
13273 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13274 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13275 | intel_crtc = to_intel_crtc(crtc); | |
13276 | ||
13277 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13278 | continue; | |
13279 | ||
13280 | if (first_crtc_state) { | |
13281 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13282 | break; | |
13283 | } else { | |
13284 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13285 | first_pipe = intel_crtc->pipe; | |
13286 | } | |
13287 | } | |
13288 | ||
13289 | /* No workaround needed? */ | |
13290 | if (!first_crtc_state) | |
13291 | return 0; | |
13292 | ||
13293 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13294 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13295 | struct intel_crtc_state *pipe_config; | |
13296 | ||
13297 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13298 | if (IS_ERR(pipe_config)) | |
13299 | return PTR_ERR(pipe_config); | |
13300 | ||
13301 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13302 | ||
13303 | if (!pipe_config->base.active || | |
13304 | needs_modeset(&pipe_config->base)) | |
13305 | continue; | |
13306 | ||
13307 | /* 2 or more enabled crtcs means no need for w/a */ | |
13308 | if (enabled_pipe != INVALID_PIPE) | |
13309 | return 0; | |
13310 | ||
13311 | enabled_pipe = intel_crtc->pipe; | |
13312 | } | |
13313 | ||
13314 | if (enabled_pipe != INVALID_PIPE) | |
13315 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13316 | else if (other_crtc_state) | |
13317 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13318 | ||
13319 | return 0; | |
13320 | } | |
13321 | ||
27c329ed ML |
13322 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13323 | { | |
13324 | struct drm_crtc *crtc; | |
13325 | struct drm_crtc_state *crtc_state; | |
13326 | int ret = 0; | |
13327 | ||
13328 | /* add all active pipes to the state */ | |
13329 | for_each_crtc(state->dev, crtc) { | |
13330 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13331 | if (IS_ERR(crtc_state)) | |
13332 | return PTR_ERR(crtc_state); | |
13333 | ||
13334 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13335 | continue; | |
13336 | ||
13337 | crtc_state->mode_changed = true; | |
13338 | ||
13339 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13340 | if (ret) | |
13341 | break; | |
13342 | ||
13343 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13344 | if (ret) | |
13345 | break; | |
13346 | } | |
13347 | ||
13348 | return ret; | |
13349 | } | |
13350 | ||
c347a676 | 13351 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13352 | { |
565602d7 ML |
13353 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13354 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13355 | struct drm_crtc *crtc; | |
13356 | struct drm_crtc_state *crtc_state; | |
13357 | int ret = 0, i; | |
054518dd | 13358 | |
b359283a ML |
13359 | if (!check_digital_port_conflicts(state)) { |
13360 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13361 | return -EINVAL; | |
13362 | } | |
13363 | ||
565602d7 ML |
13364 | intel_state->modeset = true; |
13365 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13366 | ||
13367 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13368 | if (crtc_state->active) | |
13369 | intel_state->active_crtcs |= 1 << i; | |
13370 | else | |
13371 | intel_state->active_crtcs &= ~(1 << i); | |
13372 | } | |
13373 | ||
054518dd ACO |
13374 | /* |
13375 | * See if the config requires any additional preparation, e.g. | |
13376 | * to adjust global state with pipes off. We need to do this | |
13377 | * here so we can get the modeset_pipe updated config for the new | |
13378 | * mode set on this crtc. For other crtcs we need to use the | |
13379 | * adjusted_mode bits in the crtc directly. | |
13380 | */ | |
27c329ed | 13381 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13382 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13383 | ||
1a617b77 | 13384 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13385 | ret = intel_modeset_all_pipes(state); |
13386 | ||
13387 | if (ret < 0) | |
054518dd | 13388 | return ret; |
e8788cbc ML |
13389 | |
13390 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13391 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13392 | } else |
1a617b77 | 13393 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13394 | |
ad421372 | 13395 | intel_modeset_clear_plls(state); |
054518dd | 13396 | |
565602d7 | 13397 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13398 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13399 | |
ad421372 | 13400 | return 0; |
c347a676 ACO |
13401 | } |
13402 | ||
aa363136 MR |
13403 | /* |
13404 | * Handle calculation of various watermark data at the end of the atomic check | |
13405 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13406 | * handlers to ensure that all derived state has been updated. | |
13407 | */ | |
13408 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13409 | { | |
13410 | struct drm_device *dev = state->dev; | |
13411 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13412 | struct drm_crtc *crtc; | |
13413 | struct drm_crtc_state *cstate; | |
13414 | struct drm_plane *plane; | |
13415 | struct drm_plane_state *pstate; | |
13416 | ||
13417 | /* | |
13418 | * Calculate watermark configuration details now that derived | |
13419 | * plane/crtc state is all properly updated. | |
13420 | */ | |
13421 | drm_for_each_crtc(crtc, dev) { | |
13422 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13423 | crtc->state; | |
13424 | ||
13425 | if (cstate->active) | |
13426 | intel_state->wm_config.num_pipes_active++; | |
13427 | } | |
13428 | drm_for_each_legacy_plane(plane, dev) { | |
13429 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13430 | plane->state; | |
13431 | ||
13432 | if (!to_intel_plane_state(pstate)->visible) | |
13433 | continue; | |
13434 | ||
13435 | intel_state->wm_config.sprites_enabled = true; | |
13436 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13437 | pstate->crtc_h != pstate->src_h >> 16) | |
13438 | intel_state->wm_config.sprites_scaled = true; | |
13439 | } | |
13440 | } | |
13441 | ||
74c090b1 ML |
13442 | /** |
13443 | * intel_atomic_check - validate state object | |
13444 | * @dev: drm device | |
13445 | * @state: state to validate | |
13446 | */ | |
13447 | static int intel_atomic_check(struct drm_device *dev, | |
13448 | struct drm_atomic_state *state) | |
c347a676 | 13449 | { |
dd8b3bdb | 13450 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13451 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13452 | struct drm_crtc *crtc; |
13453 | struct drm_crtc_state *crtc_state; | |
13454 | int ret, i; | |
61333b60 | 13455 | bool any_ms = false; |
c347a676 | 13456 | |
74c090b1 | 13457 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13458 | if (ret) |
13459 | return ret; | |
13460 | ||
c347a676 | 13461 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13462 | struct intel_crtc_state *pipe_config = |
13463 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13464 | |
ba8af3e5 ML |
13465 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13466 | sizeof(struct intel_crtc_atomic_commit)); | |
13467 | ||
1ed51de9 DV |
13468 | /* Catch I915_MODE_FLAG_INHERITED */ |
13469 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13470 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13471 | |
61333b60 ML |
13472 | if (!crtc_state->enable) { |
13473 | if (needs_modeset(crtc_state)) | |
13474 | any_ms = true; | |
c347a676 | 13475 | continue; |
61333b60 | 13476 | } |
c347a676 | 13477 | |
26495481 | 13478 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13479 | continue; |
13480 | ||
26495481 DV |
13481 | /* FIXME: For only active_changed we shouldn't need to do any |
13482 | * state recomputation at all. */ | |
13483 | ||
1ed51de9 DV |
13484 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13485 | if (ret) | |
13486 | return ret; | |
b359283a | 13487 | |
cfb23ed6 | 13488 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13489 | if (ret) |
13490 | return ret; | |
13491 | ||
73831236 | 13492 | if (i915.fastboot && |
dd8b3bdb | 13493 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13494 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13495 | pipe_config, true)) { |
26495481 | 13496 | crtc_state->mode_changed = false; |
bfd16b2a | 13497 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13498 | } |
13499 | ||
13500 | if (needs_modeset(crtc_state)) { | |
13501 | any_ms = true; | |
cfb23ed6 ML |
13502 | |
13503 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13504 | if (ret) | |
13505 | return ret; | |
13506 | } | |
61333b60 | 13507 | |
26495481 DV |
13508 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13509 | needs_modeset(crtc_state) ? | |
13510 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13511 | } |
13512 | ||
61333b60 ML |
13513 | if (any_ms) { |
13514 | ret = intel_modeset_checks(state); | |
13515 | ||
13516 | if (ret) | |
13517 | return ret; | |
27c329ed | 13518 | } else |
dd8b3bdb | 13519 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13520 | |
dd8b3bdb | 13521 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13522 | if (ret) |
13523 | return ret; | |
13524 | ||
f51be2e0 | 13525 | intel_fbc_choose_crtc(dev_priv, state); |
aa363136 MR |
13526 | calc_watermark_data(state); |
13527 | ||
13528 | return 0; | |
054518dd ACO |
13529 | } |
13530 | ||
5008e874 ML |
13531 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13532 | struct drm_atomic_state *state, | |
13533 | bool async) | |
13534 | { | |
7580d774 ML |
13535 | struct drm_i915_private *dev_priv = dev->dev_private; |
13536 | struct drm_plane_state *plane_state; | |
5008e874 | 13537 | struct drm_crtc_state *crtc_state; |
7580d774 | 13538 | struct drm_plane *plane; |
5008e874 ML |
13539 | struct drm_crtc *crtc; |
13540 | int i, ret; | |
13541 | ||
13542 | if (async) { | |
13543 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13544 | return -EINVAL; | |
13545 | } | |
13546 | ||
13547 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13548 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13549 | if (ret) | |
13550 | return ret; | |
7580d774 ML |
13551 | |
13552 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13553 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13554 | } |
13555 | ||
f935675f ML |
13556 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13557 | if (ret) | |
13558 | return ret; | |
13559 | ||
5008e874 | 13560 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13561 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13562 | u32 reset_counter; | |
13563 | ||
13564 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13565 | mutex_unlock(&dev->struct_mutex); | |
13566 | ||
13567 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13568 | struct intel_plane_state *intel_plane_state = | |
13569 | to_intel_plane_state(plane_state); | |
13570 | ||
13571 | if (!intel_plane_state->wait_req) | |
13572 | continue; | |
13573 | ||
13574 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13575 | reset_counter, true, | |
13576 | NULL, NULL); | |
13577 | ||
13578 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13579 | if (ret == -EIO) | |
13580 | ret = 0; | |
13581 | ||
13582 | if (ret) | |
13583 | break; | |
13584 | } | |
13585 | ||
13586 | if (!ret) | |
13587 | return 0; | |
13588 | ||
13589 | mutex_lock(&dev->struct_mutex); | |
13590 | drm_atomic_helper_cleanup_planes(dev, state); | |
13591 | } | |
5008e874 | 13592 | |
f935675f | 13593 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13594 | return ret; |
13595 | } | |
13596 | ||
e8861675 ML |
13597 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13598 | struct drm_i915_private *dev_priv, | |
13599 | unsigned crtc_mask) | |
13600 | { | |
13601 | unsigned last_vblank_count[I915_MAX_PIPES]; | |
13602 | enum pipe pipe; | |
13603 | int ret; | |
13604 | ||
13605 | if (!crtc_mask) | |
13606 | return; | |
13607 | ||
13608 | for_each_pipe(dev_priv, pipe) { | |
13609 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13610 | ||
13611 | if (!((1 << pipe) & crtc_mask)) | |
13612 | continue; | |
13613 | ||
13614 | ret = drm_crtc_vblank_get(crtc); | |
13615 | if (WARN_ON(ret != 0)) { | |
13616 | crtc_mask &= ~(1 << pipe); | |
13617 | continue; | |
13618 | } | |
13619 | ||
13620 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); | |
13621 | } | |
13622 | ||
13623 | for_each_pipe(dev_priv, pipe) { | |
13624 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13625 | long lret; | |
13626 | ||
13627 | if (!((1 << pipe) & crtc_mask)) | |
13628 | continue; | |
13629 | ||
13630 | lret = wait_event_timeout(dev->vblank[pipe].queue, | |
13631 | last_vblank_count[pipe] != | |
13632 | drm_crtc_vblank_count(crtc), | |
13633 | msecs_to_jiffies(50)); | |
13634 | ||
13635 | WARN_ON(!lret); | |
13636 | ||
13637 | drm_crtc_vblank_put(crtc); | |
13638 | } | |
13639 | } | |
13640 | ||
13641 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) | |
13642 | { | |
13643 | /* fb updated, need to unpin old fb */ | |
13644 | if (crtc_state->fb_changed) | |
13645 | return true; | |
13646 | ||
13647 | /* wm changes, need vblank before final wm's */ | |
13648 | if (crtc_state->wm_changed) | |
13649 | return true; | |
13650 | ||
13651 | /* | |
13652 | * cxsr is re-enabled after vblank. | |
13653 | * This is already handled by crtc_state->wm_changed, | |
13654 | * but added for clarity. | |
13655 | */ | |
13656 | if (crtc_state->disable_cxsr) | |
13657 | return true; | |
13658 | ||
13659 | return false; | |
13660 | } | |
13661 | ||
74c090b1 ML |
13662 | /** |
13663 | * intel_atomic_commit - commit validated state object | |
13664 | * @dev: DRM device | |
13665 | * @state: the top-level driver state object | |
13666 | * @async: asynchronous commit | |
13667 | * | |
13668 | * This function commits a top-level state object that has been validated | |
13669 | * with drm_atomic_helper_check(). | |
13670 | * | |
13671 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13672 | * we can only handle plane-related operations and do not yet support | |
13673 | * asynchronous commit. | |
13674 | * | |
13675 | * RETURNS | |
13676 | * Zero for success or -errno. | |
13677 | */ | |
13678 | static int intel_atomic_commit(struct drm_device *dev, | |
13679 | struct drm_atomic_state *state, | |
13680 | bool async) | |
a6778b3c | 13681 | { |
565602d7 | 13682 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13683 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13684 | struct drm_crtc_state *crtc_state; |
7580d774 | 13685 | struct drm_crtc *crtc; |
ed4a6a7c | 13686 | struct intel_crtc_state *intel_cstate; |
565602d7 ML |
13687 | int ret = 0, i; |
13688 | bool hw_check = intel_state->modeset; | |
33c8df89 | 13689 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
e8861675 | 13690 | unsigned crtc_vblank_mask = 0; |
a6778b3c | 13691 | |
5008e874 | 13692 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13693 | if (ret) { |
13694 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13695 | return ret; |
7580d774 | 13696 | } |
d4afb8cc | 13697 | |
1c5e19f8 | 13698 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13699 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13700 | |
565602d7 ML |
13701 | if (intel_state->modeset) { |
13702 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13703 | sizeof(intel_state->min_pixclk)); | |
13704 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13705 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
33c8df89 ML |
13706 | |
13707 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13708 | } |
13709 | ||
0a9ab303 | 13710 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13711 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13712 | ||
33c8df89 ML |
13713 | if (needs_modeset(crtc->state) || |
13714 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13715 | hw_check = true; | |
13716 | ||
13717 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13718 | modeset_get_crtc_power_domains(crtc, | |
13719 | to_intel_crtc_state(crtc->state)); | |
13720 | } | |
13721 | ||
61333b60 ML |
13722 | if (!needs_modeset(crtc->state)) |
13723 | continue; | |
13724 | ||
5c74cd73 | 13725 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
460da916 | 13726 | |
a539205a ML |
13727 | if (crtc_state->active) { |
13728 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13729 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd | 13730 | intel_crtc->active = false; |
58f9c0bc | 13731 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13732 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13733 | |
13734 | /* | |
13735 | * Underruns don't always raise | |
13736 | * interrupts, so check manually. | |
13737 | */ | |
13738 | intel_check_cpu_fifo_underruns(dev_priv); | |
13739 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13740 | |
13741 | if (!crtc->state->active) | |
13742 | intel_update_watermarks(crtc); | |
a539205a | 13743 | } |
b8cecdf5 | 13744 | } |
7758a113 | 13745 | |
ea9d758d DV |
13746 | /* Only after disabling all output pipelines that will be changed can we |
13747 | * update the the output configuration. */ | |
4740b0f2 | 13748 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13749 | |
565602d7 | 13750 | if (intel_state->modeset) { |
4740b0f2 ML |
13751 | intel_shared_dpll_commit(state); |
13752 | ||
13753 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
33c8df89 ML |
13754 | |
13755 | if (dev_priv->display.modeset_commit_cdclk && | |
13756 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13757 | dev_priv->display.modeset_commit_cdclk(state); | |
4740b0f2 | 13758 | } |
47fab737 | 13759 | |
a6778b3c | 13760 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13761 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13762 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13763 | bool modeset = needs_modeset(crtc->state); | |
e8861675 ML |
13764 | struct intel_crtc_state *pipe_config = |
13765 | to_intel_crtc_state(crtc->state); | |
13766 | bool update_pipe = !modeset && pipe_config->update_pipe; | |
9f836f90 | 13767 | |
f6ac4b2a | 13768 | if (modeset && crtc->state->active) { |
a539205a ML |
13769 | update_scanline_offset(to_intel_crtc(crtc)); |
13770 | dev_priv->display.crtc_enable(crtc); | |
13771 | } | |
80715b2f | 13772 | |
f6ac4b2a | 13773 | if (!modeset) |
5c74cd73 | 13774 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
f6ac4b2a | 13775 | |
49227c4a PZ |
13776 | if (crtc->state->active && intel_crtc->atomic.update_fbc) |
13777 | intel_fbc_enable(intel_crtc); | |
13778 | ||
6173ee28 ML |
13779 | if (crtc->state->active && |
13780 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13781 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a | 13782 | |
e8861675 ML |
13783 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13784 | crtc_vblank_mask |= 1 << i; | |
80715b2f | 13785 | } |
a6778b3c | 13786 | |
a6778b3c | 13787 | /* FIXME: add subpixel order */ |
83a57153 | 13788 | |
e8861675 ML |
13789 | if (!state->legacy_cursor_update) |
13790 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
f935675f | 13791 | |
33c8df89 | 13792 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
e8861675 ML |
13793 | intel_post_plane_update(to_intel_crtc(crtc)); |
13794 | ||
33c8df89 ML |
13795 | if (put_domains[i]) |
13796 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13797 | } | |
13798 | ||
13799 | if (intel_state->modeset) | |
13800 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13801 | ||
ed4a6a7c MR |
13802 | /* |
13803 | * Now that the vblank has passed, we can go ahead and program the | |
13804 | * optimal watermarks on platforms that need two-step watermark | |
13805 | * programming. | |
13806 | * | |
13807 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13808 | */ | |
13809 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13810 | intel_cstate = to_intel_crtc_state(crtc->state); | |
13811 | ||
13812 | if (dev_priv->display.optimize_watermarks) | |
13813 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13814 | } | |
13815 | ||
f935675f | 13816 | mutex_lock(&dev->struct_mutex); |
d4afb8cc | 13817 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13818 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13819 | |
565602d7 | 13820 | if (hw_check) |
ee165b1a ML |
13821 | intel_modeset_check_state(dev, state); |
13822 | ||
13823 | drm_atomic_state_free(state); | |
f30da187 | 13824 | |
75714940 MK |
13825 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13826 | * of triggering bugs in unclaimed access. After we finish | |
13827 | * modesetting, see if an error has been flagged, and if so | |
13828 | * enable debugging for the next modeset - and hope we catch | |
13829 | * the culprit. | |
13830 | * | |
13831 | * XXX note that we assume display power is on at this point. | |
13832 | * This might hold true now but we need to add pm helper to check | |
13833 | * unclaimed only when the hardware is on, as atomic commits | |
13834 | * can happen also when the device is completely off. | |
13835 | */ | |
13836 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13837 | ||
74c090b1 | 13838 | return 0; |
7f27126e JB |
13839 | } |
13840 | ||
c0c36b94 CW |
13841 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13842 | { | |
83a57153 ACO |
13843 | struct drm_device *dev = crtc->dev; |
13844 | struct drm_atomic_state *state; | |
e694eb02 | 13845 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13846 | int ret; |
83a57153 ACO |
13847 | |
13848 | state = drm_atomic_state_alloc(dev); | |
13849 | if (!state) { | |
e694eb02 | 13850 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13851 | crtc->base.id); |
13852 | return; | |
13853 | } | |
13854 | ||
e694eb02 | 13855 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13856 | |
e694eb02 ML |
13857 | retry: |
13858 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13859 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13860 | if (!ret) { | |
13861 | if (!crtc_state->active) | |
13862 | goto out; | |
83a57153 | 13863 | |
e694eb02 | 13864 | crtc_state->mode_changed = true; |
74c090b1 | 13865 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13866 | } |
13867 | ||
e694eb02 ML |
13868 | if (ret == -EDEADLK) { |
13869 | drm_atomic_state_clear(state); | |
13870 | drm_modeset_backoff(state->acquire_ctx); | |
13871 | goto retry; | |
4ed9fb37 | 13872 | } |
4be07317 | 13873 | |
2bfb4627 | 13874 | if (ret) |
e694eb02 | 13875 | out: |
2bfb4627 | 13876 | drm_atomic_state_free(state); |
c0c36b94 CW |
13877 | } |
13878 | ||
25c5b266 DV |
13879 | #undef for_each_intel_crtc_masked |
13880 | ||
f6e5b160 | 13881 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13882 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13883 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13884 | .destroy = intel_crtc_destroy, |
13885 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13886 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13887 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13888 | }; |
13889 | ||
5358901f DV |
13890 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13891 | struct intel_shared_dpll *pll, | |
13892 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13893 | { |
5358901f | 13894 | uint32_t val; |
ee7b9f93 | 13895 | |
12fda387 | 13896 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13897 | return false; |
13898 | ||
5358901f | 13899 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13900 | hw_state->dpll = val; |
13901 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13902 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f | 13903 | |
12fda387 ID |
13904 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
13905 | ||
5358901f DV |
13906 | return val & DPLL_VCO_ENABLE; |
13907 | } | |
13908 | ||
15bdd4cf DV |
13909 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13910 | struct intel_shared_dpll *pll) | |
13911 | { | |
3e369b76 ACO |
13912 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13913 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13914 | } |
13915 | ||
e7b903d2 DV |
13916 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13917 | struct intel_shared_dpll *pll) | |
13918 | { | |
e7b903d2 | 13919 | /* PCH refclock must be enabled first */ |
89eff4be | 13920 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13921 | |
3e369b76 | 13922 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13923 | |
13924 | /* Wait for the clocks to stabilize. */ | |
13925 | POSTING_READ(PCH_DPLL(pll->id)); | |
13926 | udelay(150); | |
13927 | ||
13928 | /* The pixel multiplier can only be updated once the | |
13929 | * DPLL is enabled and the clocks are stable. | |
13930 | * | |
13931 | * So write it again. | |
13932 | */ | |
3e369b76 | 13933 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13934 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13935 | udelay(200); |
13936 | } | |
13937 | ||
13938 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13939 | struct intel_shared_dpll *pll) | |
13940 | { | |
13941 | struct drm_device *dev = dev_priv->dev; | |
13942 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13943 | |
13944 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13945 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13946 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13947 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13948 | } |
13949 | ||
15bdd4cf DV |
13950 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13951 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13952 | udelay(200); |
13953 | } | |
13954 | ||
46edb027 DV |
13955 | static char *ibx_pch_dpll_names[] = { |
13956 | "PCH DPLL A", | |
13957 | "PCH DPLL B", | |
13958 | }; | |
13959 | ||
7c74ade1 | 13960 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13961 | { |
e7b903d2 | 13962 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13963 | int i; |
13964 | ||
7c74ade1 | 13965 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13966 | |
e72f9fbf | 13967 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13968 | dev_priv->shared_dplls[i].id = i; |
13969 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13970 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13971 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13972 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13973 | dev_priv->shared_dplls[i].get_hw_state = |
13974 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13975 | } |
13976 | } | |
13977 | ||
7c74ade1 DV |
13978 | static void intel_shared_dpll_init(struct drm_device *dev) |
13979 | { | |
e7b903d2 | 13980 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13981 | |
9cd86933 DV |
13982 | if (HAS_DDI(dev)) |
13983 | intel_ddi_pll_init(dev); | |
13984 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13985 | ibx_pch_dpll_init(dev); |
13986 | else | |
13987 | dev_priv->num_shared_dpll = 0; | |
13988 | ||
13989 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13990 | } |
13991 | ||
6beb8c23 MR |
13992 | /** |
13993 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13994 | * @plane: drm plane to prepare for | |
13995 | * @fb: framebuffer to prepare for presentation | |
13996 | * | |
13997 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13998 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13999 | * bits. Some older platforms need special physical address handling for | |
14000 | * cursor planes. | |
14001 | * | |
f935675f ML |
14002 | * Must be called with struct_mutex held. |
14003 | * | |
6beb8c23 MR |
14004 | * Returns 0 on success, negative error code on failure. |
14005 | */ | |
14006 | int | |
14007 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 14008 | const struct drm_plane_state *new_state) |
465c120c MR |
14009 | { |
14010 | struct drm_device *dev = plane->dev; | |
844f9111 | 14011 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 14012 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 14013 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14014 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 14015 | int ret = 0; |
465c120c | 14016 | |
1ee49399 | 14017 | if (!obj && !old_obj) |
465c120c MR |
14018 | return 0; |
14019 | ||
5008e874 ML |
14020 | if (old_obj) { |
14021 | struct drm_crtc_state *crtc_state = | |
14022 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
14023 | ||
14024 | /* Big Hammer, we also need to ensure that any pending | |
14025 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14026 | * current scanout is retired before unpinning the old | |
14027 | * framebuffer. Note that we rely on userspace rendering | |
14028 | * into the buffer attached to the pipe they are waiting | |
14029 | * on. If not, userspace generates a GPU hang with IPEHR | |
14030 | * point to the MI_WAIT_FOR_EVENT. | |
14031 | * | |
14032 | * This should only fail upon a hung GPU, in which case we | |
14033 | * can safely continue. | |
14034 | */ | |
14035 | if (needs_modeset(crtc_state)) | |
14036 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
14037 | ||
14038 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
14039 | if (ret && ret != -EIO) | |
f935675f | 14040 | return ret; |
5008e874 ML |
14041 | } |
14042 | ||
3c28ff22 AG |
14043 | /* For framebuffer backed by dmabuf, wait for fence */ |
14044 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
14045 | long lret; |
14046 | ||
14047 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
14048 | false, true, | |
14049 | MAX_SCHEDULE_TIMEOUT); | |
14050 | if (lret == -ERESTARTSYS) | |
14051 | return lret; | |
3c28ff22 | 14052 | |
bcf8be27 | 14053 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
14054 | } |
14055 | ||
1ee49399 ML |
14056 | if (!obj) { |
14057 | ret = 0; | |
14058 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
14059 | INTEL_INFO(dev)->cursor_needs_physical) { |
14060 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
14061 | ret = i915_gem_object_attach_phys(obj, align); | |
14062 | if (ret) | |
14063 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
14064 | } else { | |
3465c580 | 14065 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 14066 | } |
465c120c | 14067 | |
7580d774 ML |
14068 | if (ret == 0) { |
14069 | if (obj) { | |
14070 | struct intel_plane_state *plane_state = | |
14071 | to_intel_plane_state(new_state); | |
14072 | ||
14073 | i915_gem_request_assign(&plane_state->wait_req, | |
14074 | obj->last_write_req); | |
14075 | } | |
14076 | ||
a9ff8714 | 14077 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 14078 | } |
fdd508a6 | 14079 | |
6beb8c23 MR |
14080 | return ret; |
14081 | } | |
14082 | ||
38f3ce3a MR |
14083 | /** |
14084 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14085 | * @plane: drm plane to clean up for | |
14086 | * @fb: old framebuffer that was on plane | |
14087 | * | |
14088 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14089 | * |
14090 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14091 | */ |
14092 | void | |
14093 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 14094 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
14095 | { |
14096 | struct drm_device *dev = plane->dev; | |
1ee49399 | 14097 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 14098 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
14099 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14100 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14101 | |
7580d774 ML |
14102 | old_intel_state = to_intel_plane_state(old_state); |
14103 | ||
1ee49399 | 14104 | if (!obj && !old_obj) |
38f3ce3a MR |
14105 | return; |
14106 | ||
1ee49399 ML |
14107 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
14108 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 14109 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 ML |
14110 | |
14111 | /* prepare_fb aborted? */ | |
14112 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
14113 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
14114 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
14115 | |
14116 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
465c120c MR |
14117 | } |
14118 | ||
6156a456 CK |
14119 | int |
14120 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14121 | { | |
14122 | int max_scale; | |
14123 | struct drm_device *dev; | |
14124 | struct drm_i915_private *dev_priv; | |
14125 | int crtc_clock, cdclk; | |
14126 | ||
bf8a0af0 | 14127 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14128 | return DRM_PLANE_HELPER_NO_SCALING; |
14129 | ||
14130 | dev = intel_crtc->base.dev; | |
14131 | dev_priv = dev->dev_private; | |
14132 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 14133 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14134 | |
54bf1ce6 | 14135 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14136 | return DRM_PLANE_HELPER_NO_SCALING; |
14137 | ||
14138 | /* | |
14139 | * skl max scale is lower of: | |
14140 | * close to 3 but not 3, -1 is for that purpose | |
14141 | * or | |
14142 | * cdclk/crtc_clock | |
14143 | */ | |
14144 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14145 | ||
14146 | return max_scale; | |
14147 | } | |
14148 | ||
465c120c | 14149 | static int |
3c692a41 | 14150 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14151 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14152 | struct intel_plane_state *state) |
14153 | { | |
2b875c22 MR |
14154 | struct drm_crtc *crtc = state->base.crtc; |
14155 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 14156 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14157 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14158 | bool can_position = false; | |
465c120c | 14159 | |
693bdc28 VS |
14160 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
14161 | /* use scaler when colorkey is not required */ | |
14162 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14163 | min_scale = 1; | |
14164 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14165 | } | |
d8106366 | 14166 | can_position = true; |
6156a456 | 14167 | } |
d8106366 | 14168 | |
061e4b8d ML |
14169 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14170 | &state->dst, &state->clip, | |
da20eabd ML |
14171 | min_scale, max_scale, |
14172 | can_position, true, | |
14173 | &state->visible); | |
14af293f GP |
14174 | } |
14175 | ||
613d2b27 ML |
14176 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14177 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 14178 | { |
32b7eeec | 14179 | struct drm_device *dev = crtc->dev; |
3c692a41 | 14180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
14181 | struct intel_crtc_state *old_intel_state = |
14182 | to_intel_crtc_state(old_crtc_state); | |
14183 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 14184 | |
c34c9ee4 | 14185 | /* Perform vblank evasion around commit operation */ |
62852622 | 14186 | intel_pipe_update_start(intel_crtc); |
0583236e | 14187 | |
bfd16b2a ML |
14188 | if (modeset) |
14189 | return; | |
14190 | ||
14191 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14192 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14193 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 14194 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
14195 | } |
14196 | ||
613d2b27 ML |
14197 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
14198 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 14199 | { |
32b7eeec | 14200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 14201 | |
62852622 | 14202 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
14203 | } |
14204 | ||
cf4c7c12 | 14205 | /** |
4a3b8769 MR |
14206 | * intel_plane_destroy - destroy a plane |
14207 | * @plane: plane to destroy | |
cf4c7c12 | 14208 | * |
4a3b8769 MR |
14209 | * Common destruction function for all types of planes (primary, cursor, |
14210 | * sprite). | |
cf4c7c12 | 14211 | */ |
4a3b8769 | 14212 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
14213 | { |
14214 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
14215 | drm_plane_cleanup(plane); | |
14216 | kfree(intel_plane); | |
14217 | } | |
14218 | ||
65a3fea0 | 14219 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14220 | .update_plane = drm_atomic_helper_update_plane, |
14221 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14222 | .destroy = intel_plane_destroy, |
c196e1d6 | 14223 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14224 | .atomic_get_property = intel_plane_atomic_get_property, |
14225 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14226 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14227 | .atomic_destroy_state = intel_plane_destroy_state, | |
14228 | ||
465c120c MR |
14229 | }; |
14230 | ||
14231 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14232 | int pipe) | |
14233 | { | |
14234 | struct intel_plane *primary; | |
8e7d688b | 14235 | struct intel_plane_state *state; |
465c120c | 14236 | const uint32_t *intel_primary_formats; |
45e3743a | 14237 | unsigned int num_formats; |
465c120c MR |
14238 | |
14239 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
14240 | if (primary == NULL) | |
14241 | return NULL; | |
14242 | ||
8e7d688b MR |
14243 | state = intel_create_plane_state(&primary->base); |
14244 | if (!state) { | |
ea2c67bb MR |
14245 | kfree(primary); |
14246 | return NULL; | |
14247 | } | |
8e7d688b | 14248 | primary->base.state = &state->base; |
ea2c67bb | 14249 | |
465c120c MR |
14250 | primary->can_scale = false; |
14251 | primary->max_downscale = 1; | |
6156a456 CK |
14252 | if (INTEL_INFO(dev)->gen >= 9) { |
14253 | primary->can_scale = true; | |
af99ceda | 14254 | state->scaler_id = -1; |
6156a456 | 14255 | } |
465c120c MR |
14256 | primary->pipe = pipe; |
14257 | primary->plane = pipe; | |
a9ff8714 | 14258 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14259 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14260 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14261 | primary->plane = !pipe; | |
14262 | ||
6c0fd451 DL |
14263 | if (INTEL_INFO(dev)->gen >= 9) { |
14264 | intel_primary_formats = skl_primary_formats; | |
14265 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14266 | |
14267 | primary->update_plane = skylake_update_primary_plane; | |
14268 | primary->disable_plane = skylake_disable_primary_plane; | |
14269 | } else if (HAS_PCH_SPLIT(dev)) { | |
14270 | intel_primary_formats = i965_primary_formats; | |
14271 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14272 | ||
14273 | primary->update_plane = ironlake_update_primary_plane; | |
14274 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14275 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14276 | intel_primary_formats = i965_primary_formats; |
14277 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14278 | |
14279 | primary->update_plane = i9xx_update_primary_plane; | |
14280 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14281 | } else { |
14282 | intel_primary_formats = i8xx_primary_formats; | |
14283 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14284 | |
14285 | primary->update_plane = i9xx_update_primary_plane; | |
14286 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14287 | } |
14288 | ||
14289 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14290 | &intel_plane_funcs, |
465c120c | 14291 | intel_primary_formats, num_formats, |
b0b3b795 | 14292 | DRM_PLANE_TYPE_PRIMARY, NULL); |
48404c1e | 14293 | |
3b7a5119 SJ |
14294 | if (INTEL_INFO(dev)->gen >= 4) |
14295 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14296 | |
ea2c67bb MR |
14297 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14298 | ||
465c120c MR |
14299 | return &primary->base; |
14300 | } | |
14301 | ||
3b7a5119 SJ |
14302 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14303 | { | |
14304 | if (!dev->mode_config.rotation_property) { | |
14305 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14306 | BIT(DRM_ROTATE_180); | |
14307 | ||
14308 | if (INTEL_INFO(dev)->gen >= 9) | |
14309 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14310 | ||
14311 | dev->mode_config.rotation_property = | |
14312 | drm_mode_create_rotation_property(dev, flags); | |
14313 | } | |
14314 | if (dev->mode_config.rotation_property) | |
14315 | drm_object_attach_property(&plane->base.base, | |
14316 | dev->mode_config.rotation_property, | |
14317 | plane->base.state->rotation); | |
14318 | } | |
14319 | ||
3d7d6510 | 14320 | static int |
852e787c | 14321 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14322 | struct intel_crtc_state *crtc_state, |
852e787c | 14323 | struct intel_plane_state *state) |
3d7d6510 | 14324 | { |
061e4b8d | 14325 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14326 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14327 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14328 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14329 | unsigned stride; |
14330 | int ret; | |
3d7d6510 | 14331 | |
061e4b8d ML |
14332 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14333 | &state->dst, &state->clip, | |
3d7d6510 MR |
14334 | DRM_PLANE_HELPER_NO_SCALING, |
14335 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14336 | true, true, &state->visible); |
757f9a3e GP |
14337 | if (ret) |
14338 | return ret; | |
14339 | ||
757f9a3e GP |
14340 | /* if we want to turn off the cursor ignore width and height */ |
14341 | if (!obj) | |
da20eabd | 14342 | return 0; |
757f9a3e | 14343 | |
757f9a3e | 14344 | /* Check for which cursor types we support */ |
061e4b8d | 14345 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14346 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14347 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14348 | return -EINVAL; |
14349 | } | |
14350 | ||
ea2c67bb MR |
14351 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14352 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14353 | DRM_DEBUG_KMS("buffer is too small\n"); |
14354 | return -ENOMEM; | |
14355 | } | |
14356 | ||
3a656b54 | 14357 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14358 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14359 | return -EINVAL; |
32b7eeec MR |
14360 | } |
14361 | ||
b29ec92c VS |
14362 | /* |
14363 | * There's something wrong with the cursor on CHV pipe C. | |
14364 | * If it straddles the left edge of the screen then | |
14365 | * moving it away from the edge or disabling it often | |
14366 | * results in a pipe underrun, and often that can lead to | |
14367 | * dead pipe (constant underrun reported, and it scans | |
14368 | * out just a solid color). To recover from that, the | |
14369 | * display power well must be turned off and on again. | |
14370 | * Refuse the put the cursor into that compromised position. | |
14371 | */ | |
14372 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14373 | state->visible && state->base.crtc_x < 0) { | |
14374 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14375 | return -EINVAL; | |
14376 | } | |
14377 | ||
da20eabd | 14378 | return 0; |
852e787c | 14379 | } |
3d7d6510 | 14380 | |
a8ad0d8e ML |
14381 | static void |
14382 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14383 | struct drm_crtc *crtc) |
a8ad0d8e | 14384 | { |
f2858021 ML |
14385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14386 | ||
14387 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14388 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14389 | } |
14390 | ||
f4a2cf29 | 14391 | static void |
55a08b3f ML |
14392 | intel_update_cursor_plane(struct drm_plane *plane, |
14393 | const struct intel_crtc_state *crtc_state, | |
14394 | const struct intel_plane_state *state) | |
852e787c | 14395 | { |
55a08b3f ML |
14396 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14397 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14398 | struct drm_device *dev = plane->dev; |
2b875c22 | 14399 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14400 | uint32_t addr; |
852e787c | 14401 | |
f4a2cf29 | 14402 | if (!obj) |
a912f12f | 14403 | addr = 0; |
f4a2cf29 | 14404 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14405 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14406 | else |
a912f12f | 14407 | addr = obj->phys_handle->busaddr; |
852e787c | 14408 | |
a912f12f | 14409 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14410 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14411 | } |
14412 | ||
3d7d6510 MR |
14413 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14414 | int pipe) | |
14415 | { | |
14416 | struct intel_plane *cursor; | |
8e7d688b | 14417 | struct intel_plane_state *state; |
3d7d6510 MR |
14418 | |
14419 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14420 | if (cursor == NULL) | |
14421 | return NULL; | |
14422 | ||
8e7d688b MR |
14423 | state = intel_create_plane_state(&cursor->base); |
14424 | if (!state) { | |
ea2c67bb MR |
14425 | kfree(cursor); |
14426 | return NULL; | |
14427 | } | |
8e7d688b | 14428 | cursor->base.state = &state->base; |
ea2c67bb | 14429 | |
3d7d6510 MR |
14430 | cursor->can_scale = false; |
14431 | cursor->max_downscale = 1; | |
14432 | cursor->pipe = pipe; | |
14433 | cursor->plane = pipe; | |
a9ff8714 | 14434 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14435 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14436 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14437 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14438 | |
14439 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14440 | &intel_plane_funcs, |
3d7d6510 MR |
14441 | intel_cursor_formats, |
14442 | ARRAY_SIZE(intel_cursor_formats), | |
b0b3b795 | 14443 | DRM_PLANE_TYPE_CURSOR, NULL); |
4398ad45 VS |
14444 | |
14445 | if (INTEL_INFO(dev)->gen >= 4) { | |
14446 | if (!dev->mode_config.rotation_property) | |
14447 | dev->mode_config.rotation_property = | |
14448 | drm_mode_create_rotation_property(dev, | |
14449 | BIT(DRM_ROTATE_0) | | |
14450 | BIT(DRM_ROTATE_180)); | |
14451 | if (dev->mode_config.rotation_property) | |
14452 | drm_object_attach_property(&cursor->base.base, | |
14453 | dev->mode_config.rotation_property, | |
8e7d688b | 14454 | state->base.rotation); |
4398ad45 VS |
14455 | } |
14456 | ||
af99ceda CK |
14457 | if (INTEL_INFO(dev)->gen >=9) |
14458 | state->scaler_id = -1; | |
14459 | ||
ea2c67bb MR |
14460 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14461 | ||
3d7d6510 MR |
14462 | return &cursor->base; |
14463 | } | |
14464 | ||
549e2bfb CK |
14465 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14466 | struct intel_crtc_state *crtc_state) | |
14467 | { | |
14468 | int i; | |
14469 | struct intel_scaler *intel_scaler; | |
14470 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14471 | ||
14472 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14473 | intel_scaler = &scaler_state->scalers[i]; | |
14474 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14475 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14476 | } | |
14477 | ||
14478 | scaler_state->scaler_id = -1; | |
14479 | } | |
14480 | ||
b358d0a6 | 14481 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14482 | { |
fbee40df | 14483 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14484 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14485 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14486 | struct drm_plane *primary = NULL; |
14487 | struct drm_plane *cursor = NULL; | |
465c120c | 14488 | int i, ret; |
79e53945 | 14489 | |
955382f3 | 14490 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14491 | if (intel_crtc == NULL) |
14492 | return; | |
14493 | ||
f5de6e07 ACO |
14494 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14495 | if (!crtc_state) | |
14496 | goto fail; | |
550acefd ACO |
14497 | intel_crtc->config = crtc_state; |
14498 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14499 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14500 | |
549e2bfb CK |
14501 | /* initialize shared scalers */ |
14502 | if (INTEL_INFO(dev)->gen >= 9) { | |
14503 | if (pipe == PIPE_C) | |
14504 | intel_crtc->num_scalers = 1; | |
14505 | else | |
14506 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14507 | ||
14508 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14509 | } | |
14510 | ||
465c120c | 14511 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14512 | if (!primary) |
14513 | goto fail; | |
14514 | ||
14515 | cursor = intel_cursor_plane_create(dev, pipe); | |
14516 | if (!cursor) | |
14517 | goto fail; | |
14518 | ||
465c120c | 14519 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14520 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14521 | if (ret) |
14522 | goto fail; | |
79e53945 JB |
14523 | |
14524 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14525 | for (i = 0; i < 256; i++) { |
14526 | intel_crtc->lut_r[i] = i; | |
14527 | intel_crtc->lut_g[i] = i; | |
14528 | intel_crtc->lut_b[i] = i; | |
14529 | } | |
14530 | ||
1f1c2e24 VS |
14531 | /* |
14532 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14533 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14534 | */ |
80824003 JB |
14535 | intel_crtc->pipe = pipe; |
14536 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14537 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14538 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14539 | intel_crtc->plane = !pipe; |
80824003 JB |
14540 | } |
14541 | ||
4b0e333e CW |
14542 | intel_crtc->cursor_base = ~0; |
14543 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14544 | intel_crtc->cursor_size = ~0; |
8d7849db | 14545 | |
852eb00d VS |
14546 | intel_crtc->wm.cxsr_allowed = true; |
14547 | ||
22fd0fab JB |
14548 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14549 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14550 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14551 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14552 | ||
79e53945 | 14553 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14554 | |
14555 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14556 | return; |
14557 | ||
14558 | fail: | |
14559 | if (primary) | |
14560 | drm_plane_cleanup(primary); | |
14561 | if (cursor) | |
14562 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14563 | kfree(crtc_state); |
3d7d6510 | 14564 | kfree(intel_crtc); |
79e53945 JB |
14565 | } |
14566 | ||
752aa88a JB |
14567 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14568 | { | |
14569 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14570 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14571 | |
51fd371b | 14572 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14573 | |
d3babd3f | 14574 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14575 | return INVALID_PIPE; |
14576 | ||
14577 | return to_intel_crtc(encoder->crtc)->pipe; | |
14578 | } | |
14579 | ||
08d7b3d1 | 14580 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14581 | struct drm_file *file) |
08d7b3d1 | 14582 | { |
08d7b3d1 | 14583 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14584 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14585 | struct intel_crtc *crtc; |
08d7b3d1 | 14586 | |
7707e653 | 14587 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14588 | |
7707e653 | 14589 | if (!drmmode_crtc) { |
08d7b3d1 | 14590 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14591 | return -ENOENT; |
08d7b3d1 CW |
14592 | } |
14593 | ||
7707e653 | 14594 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14595 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14596 | |
c05422d5 | 14597 | return 0; |
08d7b3d1 CW |
14598 | } |
14599 | ||
66a9278e | 14600 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14601 | { |
66a9278e DV |
14602 | struct drm_device *dev = encoder->base.dev; |
14603 | struct intel_encoder *source_encoder; | |
79e53945 | 14604 | int index_mask = 0; |
79e53945 JB |
14605 | int entry = 0; |
14606 | ||
b2784e15 | 14607 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14608 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14609 | index_mask |= (1 << entry); |
14610 | ||
79e53945 JB |
14611 | entry++; |
14612 | } | |
4ef69c7a | 14613 | |
79e53945 JB |
14614 | return index_mask; |
14615 | } | |
14616 | ||
4d302442 CW |
14617 | static bool has_edp_a(struct drm_device *dev) |
14618 | { | |
14619 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14620 | ||
14621 | if (!IS_MOBILE(dev)) | |
14622 | return false; | |
14623 | ||
14624 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14625 | return false; | |
14626 | ||
e3589908 | 14627 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14628 | return false; |
14629 | ||
14630 | return true; | |
14631 | } | |
14632 | ||
84b4e042 JB |
14633 | static bool intel_crt_present(struct drm_device *dev) |
14634 | { | |
14635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14636 | ||
884497ed DL |
14637 | if (INTEL_INFO(dev)->gen >= 9) |
14638 | return false; | |
14639 | ||
cf404ce4 | 14640 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14641 | return false; |
14642 | ||
14643 | if (IS_CHERRYVIEW(dev)) | |
14644 | return false; | |
14645 | ||
65e472e4 VS |
14646 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14647 | return false; | |
14648 | ||
70ac54d0 VS |
14649 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14650 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14651 | return false; | |
14652 | ||
e4abb733 | 14653 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14654 | return false; |
14655 | ||
14656 | return true; | |
14657 | } | |
14658 | ||
79e53945 JB |
14659 | static void intel_setup_outputs(struct drm_device *dev) |
14660 | { | |
725e30ad | 14661 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14662 | struct intel_encoder *encoder; |
cb0953d7 | 14663 | bool dpd_is_edp = false; |
79e53945 | 14664 | |
c9093354 | 14665 | intel_lvds_init(dev); |
79e53945 | 14666 | |
84b4e042 | 14667 | if (intel_crt_present(dev)) |
79935fca | 14668 | intel_crt_init(dev); |
cb0953d7 | 14669 | |
c776eb2e VK |
14670 | if (IS_BROXTON(dev)) { |
14671 | /* | |
14672 | * FIXME: Broxton doesn't support port detection via the | |
14673 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14674 | * detect the ports. | |
14675 | */ | |
14676 | intel_ddi_init(dev, PORT_A); | |
14677 | intel_ddi_init(dev, PORT_B); | |
14678 | intel_ddi_init(dev, PORT_C); | |
14679 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14680 | int found; |
14681 | ||
de31facd JB |
14682 | /* |
14683 | * Haswell uses DDI functions to detect digital outputs. | |
14684 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14685 | * it's there. | |
14686 | */ | |
77179400 | 14687 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14688 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14689 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14690 | intel_ddi_init(dev, PORT_A); |
14691 | ||
14692 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14693 | * register */ | |
14694 | found = I915_READ(SFUSE_STRAP); | |
14695 | ||
14696 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14697 | intel_ddi_init(dev, PORT_B); | |
14698 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14699 | intel_ddi_init(dev, PORT_C); | |
14700 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14701 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14702 | /* |
14703 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14704 | */ | |
ef11bdb3 | 14705 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14706 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14707 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14708 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14709 | intel_ddi_init(dev, PORT_E); | |
14710 | ||
0e72a5b5 | 14711 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14712 | int found; |
5d8a7752 | 14713 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14714 | |
14715 | if (has_edp_a(dev)) | |
14716 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14717 | |
dc0fa718 | 14718 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14719 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14720 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14721 | if (!found) |
e2debe91 | 14722 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14723 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14724 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14725 | } |
14726 | ||
dc0fa718 | 14727 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14728 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14729 | |
dc0fa718 | 14730 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14731 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14732 | |
5eb08b69 | 14733 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14734 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14735 | |
270b3042 | 14736 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14737 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14738 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14739 | /* |
14740 | * The DP_DETECTED bit is the latched state of the DDC | |
14741 | * SDA pin at boot. However since eDP doesn't require DDC | |
14742 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14743 | * eDP ports may have been muxed to an alternate function. | |
14744 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14745 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14746 | * detect eDP ports. | |
14747 | */ | |
e66eb81d | 14748 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14749 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14750 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14751 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14752 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14753 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14754 | |
e66eb81d | 14755 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14756 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14757 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14758 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14759 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14760 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14761 | |
9418c1f1 | 14762 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14763 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14764 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14765 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14766 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14767 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14768 | } |
14769 | ||
3cfca973 | 14770 | intel_dsi_init(dev); |
09da55dc | 14771 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14772 | bool found = false; |
7d57382e | 14773 | |
e2debe91 | 14774 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14775 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14776 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14777 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14778 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14779 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14780 | } |
27185ae1 | 14781 | |
3fec3d2f | 14782 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14783 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14784 | } |
13520b05 KH |
14785 | |
14786 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14787 | |
e2debe91 | 14788 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14789 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14790 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14791 | } |
27185ae1 | 14792 | |
e2debe91 | 14793 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14794 | |
3fec3d2f | 14795 | if (IS_G4X(dev)) { |
b01f2c3a | 14796 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14797 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14798 | } |
3fec3d2f | 14799 | if (IS_G4X(dev)) |
ab9d7c30 | 14800 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14801 | } |
27185ae1 | 14802 | |
3fec3d2f | 14803 | if (IS_G4X(dev) && |
e7281eab | 14804 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14805 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14806 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14807 | intel_dvo_init(dev); |
14808 | ||
103a196f | 14809 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14810 | intel_tv_init(dev); |
14811 | ||
0bc12bcb | 14812 | intel_psr_init(dev); |
7c8f8a70 | 14813 | |
b2784e15 | 14814 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14815 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14816 | encoder->base.possible_clones = | |
66a9278e | 14817 | intel_encoder_clones(encoder); |
79e53945 | 14818 | } |
47356eb6 | 14819 | |
dde86e2d | 14820 | intel_init_pch_refclk(dev); |
270b3042 DV |
14821 | |
14822 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14823 | } |
14824 | ||
14825 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14826 | { | |
60a5ca01 | 14827 | struct drm_device *dev = fb->dev; |
79e53945 | 14828 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14829 | |
ef2d633e | 14830 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14831 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14832 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14833 | drm_gem_object_unreference(&intel_fb->obj->base); |
14834 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14835 | kfree(intel_fb); |
14836 | } | |
14837 | ||
14838 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14839 | struct drm_file *file, |
79e53945 JB |
14840 | unsigned int *handle) |
14841 | { | |
14842 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14843 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14844 | |
cc917ab4 CW |
14845 | if (obj->userptr.mm) { |
14846 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14847 | return -EINVAL; | |
14848 | } | |
14849 | ||
05394f39 | 14850 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14851 | } |
14852 | ||
86c98588 RV |
14853 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14854 | struct drm_file *file, | |
14855 | unsigned flags, unsigned color, | |
14856 | struct drm_clip_rect *clips, | |
14857 | unsigned num_clips) | |
14858 | { | |
14859 | struct drm_device *dev = fb->dev; | |
14860 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14861 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14862 | ||
14863 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14864 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14865 | mutex_unlock(&dev->struct_mutex); |
14866 | ||
14867 | return 0; | |
14868 | } | |
14869 | ||
79e53945 JB |
14870 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14871 | .destroy = intel_user_framebuffer_destroy, | |
14872 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14873 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14874 | }; |
14875 | ||
b321803d DL |
14876 | static |
14877 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14878 | uint32_t pixel_format) | |
14879 | { | |
14880 | u32 gen = INTEL_INFO(dev)->gen; | |
14881 | ||
14882 | if (gen >= 9) { | |
ac484963 VS |
14883 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14884 | ||
b321803d DL |
14885 | /* "The stride in bytes must not exceed the of the size of 8K |
14886 | * pixels and 32K bytes." | |
14887 | */ | |
ac484963 | 14888 | return min(8192 * cpp, 32768); |
666a4537 | 14889 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14890 | return 32*1024; |
14891 | } else if (gen >= 4) { | |
14892 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14893 | return 16*1024; | |
14894 | else | |
14895 | return 32*1024; | |
14896 | } else if (gen >= 3) { | |
14897 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14898 | return 8*1024; | |
14899 | else | |
14900 | return 16*1024; | |
14901 | } else { | |
14902 | /* XXX DSPC is limited to 4k tiled */ | |
14903 | return 8*1024; | |
14904 | } | |
14905 | } | |
14906 | ||
b5ea642a DV |
14907 | static int intel_framebuffer_init(struct drm_device *dev, |
14908 | struct intel_framebuffer *intel_fb, | |
14909 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14910 | struct drm_i915_gem_object *obj) | |
79e53945 | 14911 | { |
7b49f948 | 14912 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14913 | unsigned int aligned_height; |
79e53945 | 14914 | int ret; |
b321803d | 14915 | u32 pitch_limit, stride_alignment; |
79e53945 | 14916 | |
dd4916c5 DV |
14917 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14918 | ||
2a80eada DV |
14919 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14920 | /* Enforce that fb modifier and tiling mode match, but only for | |
14921 | * X-tiled. This is needed for FBC. */ | |
14922 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14923 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14924 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14925 | return -EINVAL; | |
14926 | } | |
14927 | } else { | |
14928 | if (obj->tiling_mode == I915_TILING_X) | |
14929 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14930 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14931 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14932 | return -EINVAL; | |
14933 | } | |
14934 | } | |
14935 | ||
9a8f0a12 TU |
14936 | /* Passed in modifier sanity checking. */ |
14937 | switch (mode_cmd->modifier[0]) { | |
14938 | case I915_FORMAT_MOD_Y_TILED: | |
14939 | case I915_FORMAT_MOD_Yf_TILED: | |
14940 | if (INTEL_INFO(dev)->gen < 9) { | |
14941 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14942 | mode_cmd->modifier[0]); | |
14943 | return -EINVAL; | |
14944 | } | |
14945 | case DRM_FORMAT_MOD_NONE: | |
14946 | case I915_FORMAT_MOD_X_TILED: | |
14947 | break; | |
14948 | default: | |
c0f40428 JB |
14949 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14950 | mode_cmd->modifier[0]); | |
57cd6508 | 14951 | return -EINVAL; |
c16ed4be | 14952 | } |
57cd6508 | 14953 | |
7b49f948 VS |
14954 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14955 | mode_cmd->modifier[0], | |
b321803d DL |
14956 | mode_cmd->pixel_format); |
14957 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14958 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14959 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14960 | return -EINVAL; |
c16ed4be | 14961 | } |
57cd6508 | 14962 | |
b321803d DL |
14963 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14964 | mode_cmd->pixel_format); | |
a35cdaa0 | 14965 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14966 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14967 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14968 | "tiled" : "linear", |
a35cdaa0 | 14969 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14970 | return -EINVAL; |
c16ed4be | 14971 | } |
5d7bd705 | 14972 | |
2a80eada | 14973 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14974 | mode_cmd->pitches[0] != obj->stride) { |
14975 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14976 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14977 | return -EINVAL; |
c16ed4be | 14978 | } |
5d7bd705 | 14979 | |
57779d06 | 14980 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14981 | switch (mode_cmd->pixel_format) { |
57779d06 | 14982 | case DRM_FORMAT_C8: |
04b3924d VS |
14983 | case DRM_FORMAT_RGB565: |
14984 | case DRM_FORMAT_XRGB8888: | |
14985 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14986 | break; |
14987 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14988 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14989 | DRM_DEBUG("unsupported pixel format: %s\n", |
14990 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14991 | return -EINVAL; |
c16ed4be | 14992 | } |
57779d06 | 14993 | break; |
57779d06 | 14994 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14995 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14996 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14997 | DRM_DEBUG("unsupported pixel format: %s\n", |
14998 | drm_get_format_name(mode_cmd->pixel_format)); | |
14999 | return -EINVAL; | |
15000 | } | |
15001 | break; | |
15002 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15003 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15004 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 15005 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
15006 | DRM_DEBUG("unsupported pixel format: %s\n", |
15007 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15008 | return -EINVAL; |
c16ed4be | 15009 | } |
b5626747 | 15010 | break; |
7531208b | 15011 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 15012 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
15013 | DRM_DEBUG("unsupported pixel format: %s\n", |
15014 | drm_get_format_name(mode_cmd->pixel_format)); | |
15015 | return -EINVAL; | |
15016 | } | |
15017 | break; | |
04b3924d VS |
15018 | case DRM_FORMAT_YUYV: |
15019 | case DRM_FORMAT_UYVY: | |
15020 | case DRM_FORMAT_YVYU: | |
15021 | case DRM_FORMAT_VYUY: | |
c16ed4be | 15022 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
15023 | DRM_DEBUG("unsupported pixel format: %s\n", |
15024 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15025 | return -EINVAL; |
c16ed4be | 15026 | } |
57cd6508 CW |
15027 | break; |
15028 | default: | |
4ee62c76 VS |
15029 | DRM_DEBUG("unsupported pixel format: %s\n", |
15030 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
15031 | return -EINVAL; |
15032 | } | |
15033 | ||
90f9a336 VS |
15034 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15035 | if (mode_cmd->offsets[0] != 0) | |
15036 | return -EINVAL; | |
15037 | ||
ec2c981e | 15038 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
15039 | mode_cmd->pixel_format, |
15040 | mode_cmd->modifier[0]); | |
53155c0a DV |
15041 | /* FIXME drm helper for size checks (especially planar formats)? */ |
15042 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
15043 | return -EINVAL; | |
15044 | ||
c7d73f6a DV |
15045 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15046 | intel_fb->obj = obj; | |
15047 | ||
2d7a215f VS |
15048 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
15049 | ||
79e53945 JB |
15050 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15051 | if (ret) { | |
15052 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15053 | return ret; | |
15054 | } | |
15055 | ||
0b05e1e0 VS |
15056 | intel_fb->obj->framebuffer_references++; |
15057 | ||
79e53945 JB |
15058 | return 0; |
15059 | } | |
15060 | ||
79e53945 JB |
15061 | static struct drm_framebuffer * |
15062 | intel_user_framebuffer_create(struct drm_device *dev, | |
15063 | struct drm_file *filp, | |
1eb83451 | 15064 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15065 | { |
dcb1394e | 15066 | struct drm_framebuffer *fb; |
05394f39 | 15067 | struct drm_i915_gem_object *obj; |
76dc3769 | 15068 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15069 | |
308e5bcb | 15070 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 15071 | mode_cmd.handles[0])); |
c8725226 | 15072 | if (&obj->base == NULL) |
cce13ff7 | 15073 | return ERR_PTR(-ENOENT); |
79e53945 | 15074 | |
92907cbb | 15075 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
15076 | if (IS_ERR(fb)) |
15077 | drm_gem_object_unreference_unlocked(&obj->base); | |
15078 | ||
15079 | return fb; | |
79e53945 JB |
15080 | } |
15081 | ||
0695726e | 15082 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 15083 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
15084 | { |
15085 | } | |
15086 | #endif | |
15087 | ||
79e53945 | 15088 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15089 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15090 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15091 | .atomic_check = intel_atomic_check, |
15092 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15093 | .atomic_state_alloc = intel_atomic_state_alloc, |
15094 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15095 | }; |
15096 | ||
e70236a8 JB |
15097 | /* Set up chip specific display functions */ |
15098 | static void intel_init_display(struct drm_device *dev) | |
15099 | { | |
15100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15101 | ||
ee9300bb DV |
15102 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
15103 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
15104 | else if (IS_CHERRYVIEW(dev)) |
15105 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
15106 | else if (IS_VALLEYVIEW(dev)) |
15107 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
15108 | else if (IS_PINEVIEW(dev)) | |
15109 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
15110 | else | |
15111 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
15112 | ||
bc8d7dff DL |
15113 | if (INTEL_INFO(dev)->gen >= 9) { |
15114 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
15115 | dev_priv->display.get_initial_plane_config = |
15116 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15117 | dev_priv->display.crtc_compute_clock = |
15118 | haswell_crtc_compute_clock; | |
15119 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15120 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff | 15121 | } else if (HAS_DDI(dev)) { |
0e8ffe1b | 15122 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15123 | dev_priv->display.get_initial_plane_config = |
15124 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15125 | dev_priv->display.crtc_compute_clock = |
15126 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15127 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15128 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
09b4ddf9 | 15129 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 15130 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15131 | dev_priv->display.get_initial_plane_config = |
15132 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15133 | dev_priv->display.crtc_compute_clock = |
15134 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15135 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15136 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
666a4537 | 15137 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 15138 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15139 | dev_priv->display.get_initial_plane_config = |
15140 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15141 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
15142 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15143 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15144 | } else { |
0e8ffe1b | 15145 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15146 | dev_priv->display.get_initial_plane_config = |
15147 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15148 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
15149 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
15150 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15151 | } |
e70236a8 | 15152 | |
e70236a8 | 15153 | /* Returns the core display clock speed */ |
ef11bdb3 | 15154 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
15155 | dev_priv->display.get_display_clock_speed = |
15156 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
15157 | else if (IS_BROXTON(dev)) |
15158 | dev_priv->display.get_display_clock_speed = | |
15159 | broxton_get_display_clock_speed; | |
1652d19e VS |
15160 | else if (IS_BROADWELL(dev)) |
15161 | dev_priv->display.get_display_clock_speed = | |
15162 | broadwell_get_display_clock_speed; | |
15163 | else if (IS_HASWELL(dev)) | |
15164 | dev_priv->display.get_display_clock_speed = | |
15165 | haswell_get_display_clock_speed; | |
666a4537 | 15166 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
15167 | dev_priv->display.get_display_clock_speed = |
15168 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
15169 | else if (IS_GEN5(dev)) |
15170 | dev_priv->display.get_display_clock_speed = | |
15171 | ilk_get_display_clock_speed; | |
a7c66cd8 | 15172 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 15173 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
15174 | dev_priv->display.get_display_clock_speed = |
15175 | i945_get_display_clock_speed; | |
34edce2f VS |
15176 | else if (IS_GM45(dev)) |
15177 | dev_priv->display.get_display_clock_speed = | |
15178 | gm45_get_display_clock_speed; | |
15179 | else if (IS_CRESTLINE(dev)) | |
15180 | dev_priv->display.get_display_clock_speed = | |
15181 | i965gm_get_display_clock_speed; | |
15182 | else if (IS_PINEVIEW(dev)) | |
15183 | dev_priv->display.get_display_clock_speed = | |
15184 | pnv_get_display_clock_speed; | |
15185 | else if (IS_G33(dev) || IS_G4X(dev)) | |
15186 | dev_priv->display.get_display_clock_speed = | |
15187 | g33_get_display_clock_speed; | |
e70236a8 JB |
15188 | else if (IS_I915G(dev)) |
15189 | dev_priv->display.get_display_clock_speed = | |
15190 | i915_get_display_clock_speed; | |
257a7ffc | 15191 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
15192 | dev_priv->display.get_display_clock_speed = |
15193 | i9xx_misc_get_display_clock_speed; | |
15194 | else if (IS_I915GM(dev)) | |
15195 | dev_priv->display.get_display_clock_speed = | |
15196 | i915gm_get_display_clock_speed; | |
15197 | else if (IS_I865G(dev)) | |
15198 | dev_priv->display.get_display_clock_speed = | |
15199 | i865_get_display_clock_speed; | |
f0f8a9ce | 15200 | else if (IS_I85X(dev)) |
e70236a8 | 15201 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15202 | i85x_get_display_clock_speed; |
623e01e5 VS |
15203 | else { /* 830 */ |
15204 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
15205 | dev_priv->display.get_display_clock_speed = |
15206 | i830_get_display_clock_speed; | |
623e01e5 | 15207 | } |
e70236a8 | 15208 | |
7c10a2b5 | 15209 | if (IS_GEN5(dev)) { |
3bb11b53 | 15210 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
15211 | } else if (IS_GEN6(dev)) { |
15212 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
15213 | } else if (IS_IVYBRIDGE(dev)) { |
15214 | /* FIXME: detect B0+ stepping and use auto training */ | |
15215 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 15216 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 15217 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
15218 | if (IS_BROADWELL(dev)) { |
15219 | dev_priv->display.modeset_commit_cdclk = | |
15220 | broadwell_modeset_commit_cdclk; | |
15221 | dev_priv->display.modeset_calc_cdclk = | |
15222 | broadwell_modeset_calc_cdclk; | |
15223 | } | |
666a4537 | 15224 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
15225 | dev_priv->display.modeset_commit_cdclk = |
15226 | valleyview_modeset_commit_cdclk; | |
15227 | dev_priv->display.modeset_calc_cdclk = | |
15228 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 15229 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
15230 | dev_priv->display.modeset_commit_cdclk = |
15231 | broxton_modeset_commit_cdclk; | |
15232 | dev_priv->display.modeset_calc_cdclk = | |
15233 | broxton_modeset_calc_cdclk; | |
e70236a8 | 15234 | } |
8c9f3aaf | 15235 | |
8c9f3aaf JB |
15236 | switch (INTEL_INFO(dev)->gen) { |
15237 | case 2: | |
15238 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15239 | break; | |
15240 | ||
15241 | case 3: | |
15242 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15243 | break; | |
15244 | ||
15245 | case 4: | |
15246 | case 5: | |
15247 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15248 | break; | |
15249 | ||
15250 | case 6: | |
15251 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15252 | break; | |
7c9017e5 | 15253 | case 7: |
4e0bbc31 | 15254 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15255 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15256 | break; | |
830c81db | 15257 | case 9: |
ba343e02 TU |
15258 | /* Drop through - unsupported since execlist only. */ |
15259 | default: | |
15260 | /* Default just returns -ENODEV to indicate unsupported */ | |
15261 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15262 | } |
7bd688cd | 15263 | |
e39b999a | 15264 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
15265 | } |
15266 | ||
b690e96c JB |
15267 | /* |
15268 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15269 | * resume, or other times. This quirk makes sure that's the case for | |
15270 | * affected systems. | |
15271 | */ | |
0206e353 | 15272 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15273 | { |
15274 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15275 | ||
15276 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15277 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15278 | } |
15279 | ||
b6b5d049 VS |
15280 | static void quirk_pipeb_force(struct drm_device *dev) |
15281 | { | |
15282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15283 | ||
15284 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15285 | DRM_INFO("applying pipe b force quirk\n"); | |
15286 | } | |
15287 | ||
435793df KP |
15288 | /* |
15289 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15290 | */ | |
15291 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15292 | { | |
15293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15294 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15295 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15296 | } |
15297 | ||
4dca20ef | 15298 | /* |
5a15ab5b CE |
15299 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15300 | * brightness value | |
4dca20ef CE |
15301 | */ |
15302 | static void quirk_invert_brightness(struct drm_device *dev) | |
15303 | { | |
15304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15305 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15306 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15307 | } |
15308 | ||
9c72cc6f SD |
15309 | /* Some VBT's incorrectly indicate no backlight is present */ |
15310 | static void quirk_backlight_present(struct drm_device *dev) | |
15311 | { | |
15312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15313 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15314 | DRM_INFO("applying backlight present quirk\n"); | |
15315 | } | |
15316 | ||
b690e96c JB |
15317 | struct intel_quirk { |
15318 | int device; | |
15319 | int subsystem_vendor; | |
15320 | int subsystem_device; | |
15321 | void (*hook)(struct drm_device *dev); | |
15322 | }; | |
15323 | ||
5f85f176 EE |
15324 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15325 | struct intel_dmi_quirk { | |
15326 | void (*hook)(struct drm_device *dev); | |
15327 | const struct dmi_system_id (*dmi_id_list)[]; | |
15328 | }; | |
15329 | ||
15330 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15331 | { | |
15332 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15333 | return 1; | |
15334 | } | |
15335 | ||
15336 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15337 | { | |
15338 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15339 | { | |
15340 | .callback = intel_dmi_reverse_brightness, | |
15341 | .ident = "NCR Corporation", | |
15342 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15343 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15344 | }, | |
15345 | }, | |
15346 | { } /* terminating entry */ | |
15347 | }, | |
15348 | .hook = quirk_invert_brightness, | |
15349 | }, | |
15350 | }; | |
15351 | ||
c43b5634 | 15352 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15353 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15354 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15355 | ||
b690e96c JB |
15356 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15357 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15358 | ||
5f080c0f VS |
15359 | /* 830 needs to leave pipe A & dpll A up */ |
15360 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15361 | ||
b6b5d049 VS |
15362 | /* 830 needs to leave pipe B & dpll B up */ |
15363 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15364 | ||
435793df KP |
15365 | /* Lenovo U160 cannot use SSC on LVDS */ |
15366 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15367 | |
15368 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15369 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15370 | |
be505f64 AH |
15371 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15372 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15373 | ||
15374 | /* Acer/eMachines G725 */ | |
15375 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15376 | ||
15377 | /* Acer/eMachines e725 */ | |
15378 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15379 | ||
15380 | /* Acer/Packard Bell NCL20 */ | |
15381 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15382 | ||
15383 | /* Acer Aspire 4736Z */ | |
15384 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15385 | |
15386 | /* Acer Aspire 5336 */ | |
15387 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15388 | |
15389 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15390 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15391 | |
dfb3d47b SD |
15392 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15393 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15394 | ||
b2a9601c | 15395 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15396 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15397 | ||
1b9448b0 JN |
15398 | /* Apple Macbook 4,1 */ |
15399 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15400 | ||
d4967d8c SD |
15401 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15402 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15403 | |
15404 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15405 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15406 | |
15407 | /* Dell Chromebook 11 */ | |
15408 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15409 | |
15410 | /* Dell Chromebook 11 (2015 version) */ | |
15411 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15412 | }; |
15413 | ||
15414 | static void intel_init_quirks(struct drm_device *dev) | |
15415 | { | |
15416 | struct pci_dev *d = dev->pdev; | |
15417 | int i; | |
15418 | ||
15419 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15420 | struct intel_quirk *q = &intel_quirks[i]; | |
15421 | ||
15422 | if (d->device == q->device && | |
15423 | (d->subsystem_vendor == q->subsystem_vendor || | |
15424 | q->subsystem_vendor == PCI_ANY_ID) && | |
15425 | (d->subsystem_device == q->subsystem_device || | |
15426 | q->subsystem_device == PCI_ANY_ID)) | |
15427 | q->hook(dev); | |
15428 | } | |
5f85f176 EE |
15429 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15430 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15431 | intel_dmi_quirks[i].hook(dev); | |
15432 | } | |
b690e96c JB |
15433 | } |
15434 | ||
9cce37f4 JB |
15435 | /* Disable the VGA plane that we never use */ |
15436 | static void i915_disable_vga(struct drm_device *dev) | |
15437 | { | |
15438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15439 | u8 sr1; | |
f0f59a00 | 15440 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15441 | |
2b37c616 | 15442 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15443 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15444 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15445 | sr1 = inb(VGA_SR_DATA); |
15446 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15447 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15448 | udelay(300); | |
15449 | ||
01f5a626 | 15450 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15451 | POSTING_READ(vga_reg); |
15452 | } | |
15453 | ||
f817586c DV |
15454 | void intel_modeset_init_hw(struct drm_device *dev) |
15455 | { | |
1a617b77 ML |
15456 | struct drm_i915_private *dev_priv = dev->dev_private; |
15457 | ||
b6283055 | 15458 | intel_update_cdclk(dev); |
1a617b77 ML |
15459 | |
15460 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15461 | ||
f817586c | 15462 | intel_init_clock_gating(dev); |
8090c6b9 | 15463 | intel_enable_gt_powersave(dev); |
f817586c DV |
15464 | } |
15465 | ||
d93c0372 MR |
15466 | /* |
15467 | * Calculate what we think the watermarks should be for the state we've read | |
15468 | * out of the hardware and then immediately program those watermarks so that | |
15469 | * we ensure the hardware settings match our internal state. | |
15470 | * | |
15471 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15472 | * current state (which was constructed during hardware readout) and running it | |
15473 | * through the atomic check code to calculate new watermark values in the | |
15474 | * state object. | |
15475 | */ | |
15476 | static void sanitize_watermarks(struct drm_device *dev) | |
15477 | { | |
15478 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15479 | struct drm_atomic_state *state; | |
15480 | struct drm_crtc *crtc; | |
15481 | struct drm_crtc_state *cstate; | |
15482 | struct drm_modeset_acquire_ctx ctx; | |
15483 | int ret; | |
15484 | int i; | |
15485 | ||
15486 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15487 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15488 | return; |
15489 | ||
15490 | /* | |
15491 | * We need to hold connection_mutex before calling duplicate_state so | |
15492 | * that the connector loop is protected. | |
15493 | */ | |
15494 | drm_modeset_acquire_init(&ctx, 0); | |
15495 | retry: | |
0cd1262d | 15496 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15497 | if (ret == -EDEADLK) { |
15498 | drm_modeset_backoff(&ctx); | |
15499 | goto retry; | |
15500 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15501 | goto fail; |
d93c0372 MR |
15502 | } |
15503 | ||
15504 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15505 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15506 | goto fail; |
d93c0372 | 15507 | |
ed4a6a7c MR |
15508 | /* |
15509 | * Hardware readout is the only time we don't want to calculate | |
15510 | * intermediate watermarks (since we don't trust the current | |
15511 | * watermarks). | |
15512 | */ | |
15513 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15514 | ||
d93c0372 MR |
15515 | ret = intel_atomic_check(dev, state); |
15516 | if (ret) { | |
15517 | /* | |
15518 | * If we fail here, it means that the hardware appears to be | |
15519 | * programmed in a way that shouldn't be possible, given our | |
15520 | * understanding of watermark requirements. This might mean a | |
15521 | * mistake in the hardware readout code or a mistake in the | |
15522 | * watermark calculations for a given platform. Raise a WARN | |
15523 | * so that this is noticeable. | |
15524 | * | |
15525 | * If this actually happens, we'll have to just leave the | |
15526 | * BIOS-programmed watermarks untouched and hope for the best. | |
15527 | */ | |
15528 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15529 | goto fail; |
d93c0372 MR |
15530 | } |
15531 | ||
15532 | /* Write calculated watermark values back */ | |
15533 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15534 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15535 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15536 | ||
ed4a6a7c MR |
15537 | cs->wm.need_postvbl_update = true; |
15538 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15539 | } |
15540 | ||
15541 | drm_atomic_state_free(state); | |
0cd1262d | 15542 | fail: |
d93c0372 MR |
15543 | drm_modeset_drop_locks(&ctx); |
15544 | drm_modeset_acquire_fini(&ctx); | |
15545 | } | |
15546 | ||
79e53945 JB |
15547 | void intel_modeset_init(struct drm_device *dev) |
15548 | { | |
652c393a | 15549 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15550 | int sprite, ret; |
8cc87b75 | 15551 | enum pipe pipe; |
46f297fb | 15552 | struct intel_crtc *crtc; |
79e53945 JB |
15553 | |
15554 | drm_mode_config_init(dev); | |
15555 | ||
15556 | dev->mode_config.min_width = 0; | |
15557 | dev->mode_config.min_height = 0; | |
15558 | ||
019d96cb DA |
15559 | dev->mode_config.preferred_depth = 24; |
15560 | dev->mode_config.prefer_shadow = 1; | |
15561 | ||
25bab385 TU |
15562 | dev->mode_config.allow_fb_modifiers = true; |
15563 | ||
e6ecefaa | 15564 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15565 | |
b690e96c JB |
15566 | intel_init_quirks(dev); |
15567 | ||
1fa61106 ED |
15568 | intel_init_pm(dev); |
15569 | ||
e3c74757 BW |
15570 | if (INTEL_INFO(dev)->num_pipes == 0) |
15571 | return; | |
15572 | ||
69f92f67 LW |
15573 | /* |
15574 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15575 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15576 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15577 | * indicates as much. | |
15578 | */ | |
15579 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15580 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15581 | DREF_SSC1_ENABLE); | |
15582 | ||
15583 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15584 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15585 | bios_lvds_use_ssc ? "en" : "dis", | |
15586 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15587 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15588 | } | |
15589 | } | |
15590 | ||
e70236a8 | 15591 | intel_init_display(dev); |
7c10a2b5 | 15592 | intel_init_audio(dev); |
e70236a8 | 15593 | |
a6c45cf0 CW |
15594 | if (IS_GEN2(dev)) { |
15595 | dev->mode_config.max_width = 2048; | |
15596 | dev->mode_config.max_height = 2048; | |
15597 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15598 | dev->mode_config.max_width = 4096; |
15599 | dev->mode_config.max_height = 4096; | |
79e53945 | 15600 | } else { |
a6c45cf0 CW |
15601 | dev->mode_config.max_width = 8192; |
15602 | dev->mode_config.max_height = 8192; | |
79e53945 | 15603 | } |
068be561 | 15604 | |
dc41c154 VS |
15605 | if (IS_845G(dev) || IS_I865G(dev)) { |
15606 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15607 | dev->mode_config.cursor_height = 1023; | |
15608 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15609 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15610 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15611 | } else { | |
15612 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15613 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15614 | } | |
15615 | ||
5d4545ae | 15616 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15617 | |
28c97730 | 15618 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15619 | INTEL_INFO(dev)->num_pipes, |
15620 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15621 | |
055e393f | 15622 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15623 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15624 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15625 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15626 | if (ret) |
06da8da2 | 15627 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15628 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15629 | } |
79e53945 JB |
15630 | } |
15631 | ||
bfa7df01 | 15632 | intel_update_czclk(dev_priv); |
e7dc33f3 | 15633 | intel_update_rawclk(dev_priv); |
bfa7df01 VS |
15634 | intel_update_cdclk(dev); |
15635 | ||
e72f9fbf | 15636 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15637 | |
9cce37f4 JB |
15638 | /* Just disable it once at startup */ |
15639 | i915_disable_vga(dev); | |
79e53945 | 15640 | intel_setup_outputs(dev); |
11be49eb | 15641 | |
6e9f798d | 15642 | drm_modeset_lock_all(dev); |
043e9bda | 15643 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15644 | drm_modeset_unlock_all(dev); |
46f297fb | 15645 | |
d3fcc808 | 15646 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15647 | struct intel_initial_plane_config plane_config = {}; |
15648 | ||
46f297fb JB |
15649 | if (!crtc->active) |
15650 | continue; | |
15651 | ||
46f297fb | 15652 | /* |
46f297fb JB |
15653 | * Note that reserving the BIOS fb up front prevents us |
15654 | * from stuffing other stolen allocations like the ring | |
15655 | * on top. This prevents some ugliness at boot time, and | |
15656 | * can even allow for smooth boot transitions if the BIOS | |
15657 | * fb is large enough for the active pipe configuration. | |
15658 | */ | |
eeebeac5 ML |
15659 | dev_priv->display.get_initial_plane_config(crtc, |
15660 | &plane_config); | |
15661 | ||
15662 | /* | |
15663 | * If the fb is shared between multiple heads, we'll | |
15664 | * just get the first one. | |
15665 | */ | |
15666 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15667 | } |
d93c0372 MR |
15668 | |
15669 | /* | |
15670 | * Make sure hardware watermarks really match the state we read out. | |
15671 | * Note that we need to do this after reconstructing the BIOS fb's | |
15672 | * since the watermark calculation done here will use pstate->fb. | |
15673 | */ | |
15674 | sanitize_watermarks(dev); | |
2c7111db CW |
15675 | } |
15676 | ||
7fad798e DV |
15677 | static void intel_enable_pipe_a(struct drm_device *dev) |
15678 | { | |
15679 | struct intel_connector *connector; | |
15680 | struct drm_connector *crt = NULL; | |
15681 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15682 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15683 | |
15684 | /* We can't just switch on the pipe A, we need to set things up with a | |
15685 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15686 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15687 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15688 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15689 | crt = &connector->base; | |
15690 | break; | |
15691 | } | |
15692 | } | |
15693 | ||
15694 | if (!crt) | |
15695 | return; | |
15696 | ||
208bf9fd | 15697 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15698 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15699 | } |
15700 | ||
fa555837 DV |
15701 | static bool |
15702 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15703 | { | |
7eb552ae BW |
15704 | struct drm_device *dev = crtc->base.dev; |
15705 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15706 | u32 val; |
fa555837 | 15707 | |
7eb552ae | 15708 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15709 | return true; |
15710 | ||
649636ef | 15711 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15712 | |
15713 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15714 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15715 | return false; | |
15716 | ||
15717 | return true; | |
15718 | } | |
15719 | ||
02e93c35 VS |
15720 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15721 | { | |
15722 | struct drm_device *dev = crtc->base.dev; | |
15723 | struct intel_encoder *encoder; | |
15724 | ||
15725 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15726 | return true; | |
15727 | ||
15728 | return false; | |
15729 | } | |
15730 | ||
dd756198 VS |
15731 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15732 | { | |
15733 | struct drm_device *dev = encoder->base.dev; | |
15734 | struct intel_connector *connector; | |
15735 | ||
15736 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15737 | return true; | |
15738 | ||
15739 | return false; | |
15740 | } | |
15741 | ||
24929352 DV |
15742 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15743 | { | |
15744 | struct drm_device *dev = crtc->base.dev; | |
15745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15746 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15747 | |
24929352 | 15748 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15749 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15750 | ||
d3eaf884 | 15751 | /* restore vblank interrupts to correct state */ |
9625604c | 15752 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15753 | if (crtc->active) { |
f9cd7b88 VS |
15754 | struct intel_plane *plane; |
15755 | ||
9625604c | 15756 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15757 | |
15758 | /* Disable everything but the primary plane */ | |
15759 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15760 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15761 | continue; | |
15762 | ||
15763 | plane->disable_plane(&plane->base, &crtc->base); | |
15764 | } | |
9625604c | 15765 | } |
d3eaf884 | 15766 | |
24929352 | 15767 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15768 | * disable the crtc (and hence change the state) if it is wrong. Note |
15769 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15770 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15771 | bool plane; |
15772 | ||
24929352 DV |
15773 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15774 | crtc->base.base.id); | |
15775 | ||
15776 | /* Pipe has the wrong plane attached and the plane is active. | |
15777 | * Temporarily change the plane mapping and disable everything | |
15778 | * ... */ | |
15779 | plane = crtc->plane; | |
b70709a6 | 15780 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15781 | crtc->plane = !plane; |
b17d48e2 | 15782 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15783 | crtc->plane = plane; |
24929352 | 15784 | } |
24929352 | 15785 | |
7fad798e DV |
15786 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15787 | crtc->pipe == PIPE_A && !crtc->active) { | |
15788 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15789 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15790 | * call below we restore the pipe to the right state, but leave | |
15791 | * the required bits on. */ | |
15792 | intel_enable_pipe_a(dev); | |
15793 | } | |
15794 | ||
24929352 DV |
15795 | /* Adjust the state of the output pipe according to whether we |
15796 | * have active connectors/encoders. */ | |
02e93c35 | 15797 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15798 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15799 | |
53d9f4e9 | 15800 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15801 | struct intel_encoder *encoder; |
24929352 DV |
15802 | |
15803 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15804 | * functions or because of calls to intel_crtc_disable_noatomic, |
15805 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15806 | * pipe A quirk. */ |
15807 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15808 | crtc->base.base.id, | |
83d65738 | 15809 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15810 | crtc->active ? "enabled" : "disabled"); |
15811 | ||
4be40c98 | 15812 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15813 | crtc->base.state->active = crtc->active; |
24929352 | 15814 | crtc->base.enabled = crtc->active; |
2aa974c9 | 15815 | crtc->base.state->connector_mask = 0; |
e87a52b3 | 15816 | crtc->base.state->encoder_mask = 0; |
24929352 DV |
15817 | |
15818 | /* Because we only establish the connector -> encoder -> | |
15819 | * crtc links if something is active, this means the | |
15820 | * crtc is now deactivated. Break the links. connector | |
15821 | * -> encoder links are only establish when things are | |
15822 | * actually up, hence no need to break them. */ | |
15823 | WARN_ON(crtc->active); | |
15824 | ||
2d406bb0 | 15825 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15826 | encoder->base.crtc = NULL; |
24929352 | 15827 | } |
c5ab3bc0 | 15828 | |
a3ed6aad | 15829 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15830 | /* |
15831 | * We start out with underrun reporting disabled to avoid races. | |
15832 | * For correct bookkeeping mark this on active crtcs. | |
15833 | * | |
c5ab3bc0 DV |
15834 | * Also on gmch platforms we dont have any hardware bits to |
15835 | * disable the underrun reporting. Which means we need to start | |
15836 | * out with underrun reporting disabled also on inactive pipes, | |
15837 | * since otherwise we'll complain about the garbage we read when | |
15838 | * e.g. coming up after runtime pm. | |
15839 | * | |
4cc31489 DV |
15840 | * No protection against concurrent access is required - at |
15841 | * worst a fifo underrun happens which also sets this to false. | |
15842 | */ | |
15843 | crtc->cpu_fifo_underrun_disabled = true; | |
15844 | crtc->pch_fifo_underrun_disabled = true; | |
15845 | } | |
24929352 DV |
15846 | } |
15847 | ||
15848 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15849 | { | |
15850 | struct intel_connector *connector; | |
15851 | struct drm_device *dev = encoder->base.dev; | |
15852 | ||
15853 | /* We need to check both for a crtc link (meaning that the | |
15854 | * encoder is active and trying to read from a pipe) and the | |
15855 | * pipe itself being active. */ | |
15856 | bool has_active_crtc = encoder->base.crtc && | |
15857 | to_intel_crtc(encoder->base.crtc)->active; | |
15858 | ||
dd756198 | 15859 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15860 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15861 | encoder->base.base.id, | |
8e329a03 | 15862 | encoder->base.name); |
24929352 DV |
15863 | |
15864 | /* Connector is active, but has no active pipe. This is | |
15865 | * fallout from our resume register restoring. Disable | |
15866 | * the encoder manually again. */ | |
15867 | if (encoder->base.crtc) { | |
15868 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15869 | encoder->base.base.id, | |
8e329a03 | 15870 | encoder->base.name); |
24929352 | 15871 | encoder->disable(encoder); |
a62d1497 VS |
15872 | if (encoder->post_disable) |
15873 | encoder->post_disable(encoder); | |
24929352 | 15874 | } |
7f1950fb | 15875 | encoder->base.crtc = NULL; |
24929352 DV |
15876 | |
15877 | /* Inconsistent output/port/pipe state happens presumably due to | |
15878 | * a bug in one of the get_hw_state functions. Or someplace else | |
15879 | * in our code, like the register restore mess on resume. Clamp | |
15880 | * things to off as a safer default. */ | |
3a3371ff | 15881 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15882 | if (connector->encoder != encoder) |
15883 | continue; | |
7f1950fb EE |
15884 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15885 | connector->base.encoder = NULL; | |
24929352 DV |
15886 | } |
15887 | } | |
15888 | /* Enabled encoders without active connectors will be fixed in | |
15889 | * the crtc fixup. */ | |
15890 | } | |
15891 | ||
04098753 | 15892 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15893 | { |
15894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15895 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15896 | |
04098753 ID |
15897 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15898 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15899 | i915_disable_vga(dev); | |
15900 | } | |
15901 | } | |
15902 | ||
15903 | void i915_redisable_vga(struct drm_device *dev) | |
15904 | { | |
15905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15906 | ||
8dc8a27c PZ |
15907 | /* This function can be called both from intel_modeset_setup_hw_state or |
15908 | * at a very early point in our resume sequence, where the power well | |
15909 | * structures are not yet restored. Since this function is at a very | |
15910 | * paranoid "someone might have enabled VGA while we were not looking" | |
15911 | * level, just check if the power well is enabled instead of trying to | |
15912 | * follow the "don't touch the power well if we don't need it" policy | |
15913 | * the rest of the driver uses. */ | |
6392f847 | 15914 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15915 | return; |
15916 | ||
04098753 | 15917 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15918 | |
15919 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15920 | } |
15921 | ||
f9cd7b88 | 15922 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15923 | { |
f9cd7b88 | 15924 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15925 | |
f9cd7b88 | 15926 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15927 | } |
15928 | ||
f9cd7b88 VS |
15929 | /* FIXME read out full plane state for all planes */ |
15930 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15931 | { |
b26d3ea3 | 15932 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15933 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15934 | to_intel_plane_state(primary->state); |
d032ffa0 | 15935 | |
19b8d387 | 15936 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15937 | primary_get_hw_state(to_intel_plane(primary)); |
15938 | ||
15939 | if (plane_state->visible) | |
15940 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15941 | } |
15942 | ||
30e984df | 15943 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15944 | { |
15945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15946 | enum pipe pipe; | |
24929352 DV |
15947 | struct intel_crtc *crtc; |
15948 | struct intel_encoder *encoder; | |
15949 | struct intel_connector *connector; | |
5358901f | 15950 | int i; |
24929352 | 15951 | |
565602d7 ML |
15952 | dev_priv->active_crtcs = 0; |
15953 | ||
d3fcc808 | 15954 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15955 | struct intel_crtc_state *crtc_state = crtc->config; |
15956 | int pixclk = 0; | |
3b117c8f | 15957 | |
565602d7 ML |
15958 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15959 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15960 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15961 | |
565602d7 ML |
15962 | crtc_state->base.active = crtc_state->base.enable = |
15963 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15964 | ||
15965 | crtc->base.enabled = crtc_state->base.enable; | |
15966 | crtc->active = crtc_state->base.active; | |
15967 | ||
15968 | if (crtc_state->base.active) { | |
15969 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15970 | ||
15971 | if (IS_BROADWELL(dev_priv)) { | |
15972 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15973 | ||
15974 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15975 | if (crtc_state->ips_enabled) | |
15976 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15977 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15978 | IS_CHERRYVIEW(dev_priv) || | |
15979 | IS_BROXTON(dev_priv)) | |
15980 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15981 | else | |
15982 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15983 | } | |
15984 | ||
15985 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15986 | |
f9cd7b88 | 15987 | readout_plane_state(crtc); |
24929352 DV |
15988 | |
15989 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15990 | crtc->base.base.id, | |
15991 | crtc->active ? "enabled" : "disabled"); | |
15992 | } | |
15993 | ||
5358901f DV |
15994 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15995 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15996 | ||
3e369b76 ACO |
15997 | pll->on = pll->get_hw_state(dev_priv, pll, |
15998 | &pll->config.hw_state); | |
5358901f | 15999 | pll->active = 0; |
3e369b76 | 16000 | pll->config.crtc_mask = 0; |
d3fcc808 | 16001 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 16002 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 16003 | pll->active++; |
3e369b76 | 16004 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 16005 | } |
5358901f | 16006 | } |
5358901f | 16007 | |
1e6f2ddc | 16008 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16009 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 16010 | |
3e369b76 | 16011 | if (pll->config.crtc_mask) |
bd2bb1b9 | 16012 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
16013 | } |
16014 | ||
b2784e15 | 16015 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16016 | pipe = 0; |
16017 | ||
16018 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
16019 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16020 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 16021 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16022 | } else { |
16023 | encoder->base.crtc = NULL; | |
16024 | } | |
16025 | ||
6f2bcceb | 16026 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 16027 | encoder->base.base.id, |
8e329a03 | 16028 | encoder->base.name, |
24929352 | 16029 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 16030 | pipe_name(pipe)); |
24929352 DV |
16031 | } |
16032 | ||
3a3371ff | 16033 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16034 | if (connector->get_hw_state(connector)) { |
16035 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16036 | |
16037 | encoder = connector->encoder; | |
16038 | connector->base.encoder = &encoder->base; | |
16039 | ||
16040 | if (encoder->base.crtc && | |
16041 | encoder->base.crtc->state->active) { | |
16042 | /* | |
16043 | * This has to be done during hardware readout | |
16044 | * because anything calling .crtc_disable may | |
16045 | * rely on the connector_mask being accurate. | |
16046 | */ | |
16047 | encoder->base.crtc->state->connector_mask |= | |
16048 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16049 | encoder->base.crtc->state->encoder_mask |= |
16050 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16051 | } |
16052 | ||
24929352 DV |
16053 | } else { |
16054 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16055 | connector->base.encoder = NULL; | |
16056 | } | |
16057 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
16058 | connector->base.base.id, | |
c23cc417 | 16059 | connector->base.name, |
24929352 DV |
16060 | connector->base.encoder ? "enabled" : "disabled"); |
16061 | } | |
7f4c6284 VS |
16062 | |
16063 | for_each_intel_crtc(dev, crtc) { | |
16064 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16065 | ||
16066 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16067 | if (crtc->base.state->active) { | |
16068 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16069 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16070 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16071 | ||
16072 | /* | |
16073 | * The initial mode needs to be set in order to keep | |
16074 | * the atomic core happy. It wants a valid mode if the | |
16075 | * crtc's enabled, so we do the above call. | |
16076 | * | |
16077 | * At this point some state updated by the connectors | |
16078 | * in their ->detect() callback has not run yet, so | |
16079 | * no recalculation can be done yet. | |
16080 | * | |
16081 | * Even if we could do a recalculation and modeset | |
16082 | * right now it would cause a double modeset if | |
16083 | * fbdev or userspace chooses a different initial mode. | |
16084 | * | |
16085 | * If that happens, someone indicated they wanted a | |
16086 | * mode change, which means it's safe to do a full | |
16087 | * recalculation. | |
16088 | */ | |
16089 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16090 | |
16091 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16092 | update_scanline_offset(crtc); | |
7f4c6284 | 16093 | } |
e3b247da VS |
16094 | |
16095 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16096 | } |
30e984df DV |
16097 | } |
16098 | ||
043e9bda ML |
16099 | /* Scan out the current hw modeset state, |
16100 | * and sanitizes it to the current state | |
16101 | */ | |
16102 | static void | |
16103 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
16104 | { |
16105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
16106 | enum pipe pipe; | |
30e984df DV |
16107 | struct intel_crtc *crtc; |
16108 | struct intel_encoder *encoder; | |
35c95375 | 16109 | int i; |
30e984df DV |
16110 | |
16111 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16112 | |
16113 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16114 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16115 | intel_sanitize_encoder(encoder); |
16116 | } | |
16117 | ||
055e393f | 16118 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
16119 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16120 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
16121 | intel_dump_pipe_config(crtc, crtc->config, |
16122 | "[setup_hw_state]"); | |
24929352 | 16123 | } |
9a935856 | 16124 | |
d29b2f9d ACO |
16125 | intel_modeset_update_connector_atomic_state(dev); |
16126 | ||
35c95375 DV |
16127 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16128 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16129 | ||
16130 | if (!pll->on || pll->active) | |
16131 | continue; | |
16132 | ||
16133 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
16134 | ||
16135 | pll->disable(dev_priv, pll); | |
16136 | pll->on = false; | |
16137 | } | |
16138 | ||
666a4537 | 16139 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
16140 | vlv_wm_get_hw_state(dev); |
16141 | else if (IS_GEN9(dev)) | |
3078999f PB |
16142 | skl_wm_get_hw_state(dev); |
16143 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 16144 | ilk_wm_get_hw_state(dev); |
292b990e ML |
16145 | |
16146 | for_each_intel_crtc(dev, crtc) { | |
16147 | unsigned long put_domains; | |
16148 | ||
74bff5f9 | 16149 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
16150 | if (WARN_ON(put_domains)) |
16151 | modeset_put_power_domains(dev_priv, put_domains); | |
16152 | } | |
16153 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
16154 | |
16155 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 16156 | } |
7d0bc1ea | 16157 | |
043e9bda ML |
16158 | void intel_display_resume(struct drm_device *dev) |
16159 | { | |
e2c8b870 ML |
16160 | struct drm_i915_private *dev_priv = to_i915(dev); |
16161 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
16162 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 16163 | int ret; |
e2c8b870 | 16164 | bool setup = false; |
f30da187 | 16165 | |
e2c8b870 | 16166 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 16167 | |
ea49c9ac ML |
16168 | /* |
16169 | * This is a cludge because with real atomic modeset mode_config.mutex | |
16170 | * won't be taken. Unfortunately some probed state like | |
16171 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
16172 | * it here for now. | |
16173 | */ | |
16174 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 16175 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 16176 | |
e2c8b870 ML |
16177 | retry: |
16178 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 16179 | |
e2c8b870 ML |
16180 | if (ret == 0 && !setup) { |
16181 | setup = true; | |
043e9bda | 16182 | |
e2c8b870 ML |
16183 | intel_modeset_setup_hw_state(dev); |
16184 | i915_redisable_vga(dev); | |
45e2b5f6 | 16185 | } |
8af6cf88 | 16186 | |
e2c8b870 ML |
16187 | if (ret == 0 && state) { |
16188 | struct drm_crtc_state *crtc_state; | |
16189 | struct drm_crtc *crtc; | |
16190 | int i; | |
043e9bda | 16191 | |
e2c8b870 ML |
16192 | state->acquire_ctx = &ctx; |
16193 | ||
16194 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
16195 | /* | |
16196 | * Force recalculation even if we restore | |
16197 | * current state. With fast modeset this may not result | |
16198 | * in a modeset when the state is compatible. | |
16199 | */ | |
16200 | crtc_state->mode_changed = true; | |
16201 | } | |
16202 | ||
16203 | ret = drm_atomic_commit(state); | |
043e9bda ML |
16204 | } |
16205 | ||
e2c8b870 ML |
16206 | if (ret == -EDEADLK) { |
16207 | drm_modeset_backoff(&ctx); | |
16208 | goto retry; | |
16209 | } | |
043e9bda | 16210 | |
e2c8b870 ML |
16211 | drm_modeset_drop_locks(&ctx); |
16212 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 16213 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 16214 | |
e2c8b870 ML |
16215 | if (ret) { |
16216 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16217 | drm_atomic_state_free(state); | |
16218 | } | |
2c7111db CW |
16219 | } |
16220 | ||
16221 | void intel_modeset_gem_init(struct drm_device *dev) | |
16222 | { | |
484b41dd | 16223 | struct drm_crtc *c; |
2ff8fde1 | 16224 | struct drm_i915_gem_object *obj; |
e0d6149b | 16225 | int ret; |
484b41dd | 16226 | |
ae48434c | 16227 | intel_init_gt_powersave(dev); |
ae48434c | 16228 | |
1833b134 | 16229 | intel_modeset_init_hw(dev); |
02e792fb DV |
16230 | |
16231 | intel_setup_overlay(dev); | |
484b41dd JB |
16232 | |
16233 | /* | |
16234 | * Make sure any fbs we allocated at startup are properly | |
16235 | * pinned & fenced. When we do the allocation it's too early | |
16236 | * for this. | |
16237 | */ | |
70e1e0ec | 16238 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16239 | obj = intel_fb_obj(c->primary->fb); |
16240 | if (obj == NULL) | |
484b41dd JB |
16241 | continue; |
16242 | ||
e0d6149b | 16243 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
16244 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
16245 | c->primary->state->rotation); | |
e0d6149b TU |
16246 | mutex_unlock(&dev->struct_mutex); |
16247 | if (ret) { | |
484b41dd JB |
16248 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16249 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
16250 | drm_framebuffer_unreference(c->primary->fb); |
16251 | c->primary->fb = NULL; | |
36750f28 | 16252 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 16253 | update_state_fb(c->primary); |
36750f28 | 16254 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16255 | } |
16256 | } | |
0962c3c9 VS |
16257 | |
16258 | intel_backlight_register(dev); | |
79e53945 JB |
16259 | } |
16260 | ||
4932e2c3 ID |
16261 | void intel_connector_unregister(struct intel_connector *intel_connector) |
16262 | { | |
16263 | struct drm_connector *connector = &intel_connector->base; | |
16264 | ||
16265 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 16266 | drm_connector_unregister(connector); |
4932e2c3 ID |
16267 | } |
16268 | ||
79e53945 JB |
16269 | void intel_modeset_cleanup(struct drm_device *dev) |
16270 | { | |
652c393a | 16271 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 16272 | struct intel_connector *connector; |
652c393a | 16273 | |
2eb5252e ID |
16274 | intel_disable_gt_powersave(dev); |
16275 | ||
0962c3c9 VS |
16276 | intel_backlight_unregister(dev); |
16277 | ||
fd0c0642 DV |
16278 | /* |
16279 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16280 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16281 | * experience fancy races otherwise. |
16282 | */ | |
2aeb7d3a | 16283 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16284 | |
fd0c0642 DV |
16285 | /* |
16286 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16287 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16288 | */ | |
f87ea761 | 16289 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16290 | |
723bfd70 JB |
16291 | intel_unregister_dsm_handler(); |
16292 | ||
c937ab3e | 16293 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16294 | |
1630fe75 CW |
16295 | /* flush any delayed tasks or pending work */ |
16296 | flush_scheduled_work(); | |
16297 | ||
db31af1d | 16298 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16299 | for_each_intel_connector(dev, connector) |
16300 | connector->unregister(connector); | |
d9255d57 | 16301 | |
79e53945 | 16302 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
16303 | |
16304 | intel_cleanup_overlay(dev); | |
ae48434c | 16305 | |
ae48434c | 16306 | intel_cleanup_gt_powersave(dev); |
f5949141 DV |
16307 | |
16308 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16309 | } |
16310 | ||
f1c79df3 ZW |
16311 | /* |
16312 | * Return which encoder is currently attached for connector. | |
16313 | */ | |
df0e9248 | 16314 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16315 | { |
df0e9248 CW |
16316 | return &intel_attached_encoder(connector)->base; |
16317 | } | |
f1c79df3 | 16318 | |
df0e9248 CW |
16319 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16320 | struct intel_encoder *encoder) | |
16321 | { | |
16322 | connector->encoder = encoder; | |
16323 | drm_mode_connector_attach_encoder(&connector->base, | |
16324 | &encoder->base); | |
79e53945 | 16325 | } |
28d52043 DA |
16326 | |
16327 | /* | |
16328 | * set vga decode state - true == enable VGA decode | |
16329 | */ | |
16330 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16331 | { | |
16332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16333 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16334 | u16 gmch_ctrl; |
16335 | ||
75fa041d CW |
16336 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16337 | DRM_ERROR("failed to read control word\n"); | |
16338 | return -EIO; | |
16339 | } | |
16340 | ||
c0cc8a55 CW |
16341 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16342 | return 0; | |
16343 | ||
28d52043 DA |
16344 | if (state) |
16345 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16346 | else | |
16347 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16348 | |
16349 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16350 | DRM_ERROR("failed to write control word\n"); | |
16351 | return -EIO; | |
16352 | } | |
16353 | ||
28d52043 DA |
16354 | return 0; |
16355 | } | |
c4a1d9e4 | 16356 | |
c4a1d9e4 | 16357 | struct intel_display_error_state { |
ff57f1b0 PZ |
16358 | |
16359 | u32 power_well_driver; | |
16360 | ||
63b66e5b CW |
16361 | int num_transcoders; |
16362 | ||
c4a1d9e4 CW |
16363 | struct intel_cursor_error_state { |
16364 | u32 control; | |
16365 | u32 position; | |
16366 | u32 base; | |
16367 | u32 size; | |
52331309 | 16368 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16369 | |
16370 | struct intel_pipe_error_state { | |
ddf9c536 | 16371 | bool power_domain_on; |
c4a1d9e4 | 16372 | u32 source; |
f301b1e1 | 16373 | u32 stat; |
52331309 | 16374 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16375 | |
16376 | struct intel_plane_error_state { | |
16377 | u32 control; | |
16378 | u32 stride; | |
16379 | u32 size; | |
16380 | u32 pos; | |
16381 | u32 addr; | |
16382 | u32 surface; | |
16383 | u32 tile_offset; | |
52331309 | 16384 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16385 | |
16386 | struct intel_transcoder_error_state { | |
ddf9c536 | 16387 | bool power_domain_on; |
63b66e5b CW |
16388 | enum transcoder cpu_transcoder; |
16389 | ||
16390 | u32 conf; | |
16391 | ||
16392 | u32 htotal; | |
16393 | u32 hblank; | |
16394 | u32 hsync; | |
16395 | u32 vtotal; | |
16396 | u32 vblank; | |
16397 | u32 vsync; | |
16398 | } transcoder[4]; | |
c4a1d9e4 CW |
16399 | }; |
16400 | ||
16401 | struct intel_display_error_state * | |
16402 | intel_display_capture_error_state(struct drm_device *dev) | |
16403 | { | |
fbee40df | 16404 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16405 | struct intel_display_error_state *error; |
63b66e5b CW |
16406 | int transcoders[] = { |
16407 | TRANSCODER_A, | |
16408 | TRANSCODER_B, | |
16409 | TRANSCODER_C, | |
16410 | TRANSCODER_EDP, | |
16411 | }; | |
c4a1d9e4 CW |
16412 | int i; |
16413 | ||
63b66e5b CW |
16414 | if (INTEL_INFO(dev)->num_pipes == 0) |
16415 | return NULL; | |
16416 | ||
9d1cb914 | 16417 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16418 | if (error == NULL) |
16419 | return NULL; | |
16420 | ||
190be112 | 16421 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16422 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16423 | ||
055e393f | 16424 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16425 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16426 | __intel_display_power_is_enabled(dev_priv, |
16427 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16428 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16429 | continue; |
16430 | ||
5efb3e28 VS |
16431 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16432 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16433 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16434 | |
16435 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16436 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16437 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16438 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16439 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16440 | } | |
ca291363 PZ |
16441 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16442 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16443 | if (INTEL_INFO(dev)->gen >= 4) { |
16444 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16445 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16446 | } | |
16447 | ||
c4a1d9e4 | 16448 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16449 | |
3abfce77 | 16450 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16451 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16452 | } |
16453 | ||
16454 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16455 | if (HAS_DDI(dev_priv->dev)) | |
16456 | error->num_transcoders++; /* Account for eDP. */ | |
16457 | ||
16458 | for (i = 0; i < error->num_transcoders; i++) { | |
16459 | enum transcoder cpu_transcoder = transcoders[i]; | |
16460 | ||
ddf9c536 | 16461 | error->transcoder[i].power_domain_on = |
f458ebbc | 16462 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16463 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16464 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16465 | continue; |
16466 | ||
63b66e5b CW |
16467 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16468 | ||
16469 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16470 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16471 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16472 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16473 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16474 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16475 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16476 | } |
16477 | ||
16478 | return error; | |
16479 | } | |
16480 | ||
edc3d884 MK |
16481 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16482 | ||
c4a1d9e4 | 16483 | void |
edc3d884 | 16484 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16485 | struct drm_device *dev, |
16486 | struct intel_display_error_state *error) | |
16487 | { | |
055e393f | 16488 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16489 | int i; |
16490 | ||
63b66e5b CW |
16491 | if (!error) |
16492 | return; | |
16493 | ||
edc3d884 | 16494 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16495 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16496 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16497 | error->power_well_driver); |
055e393f | 16498 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16499 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16500 | err_printf(m, " Power: %s\n", |
87ad3212 | 16501 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16502 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16503 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16504 | |
16505 | err_printf(m, "Plane [%d]:\n", i); | |
16506 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16507 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16508 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16509 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16510 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16511 | } |
4b71a570 | 16512 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16513 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16514 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16515 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16516 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16517 | } |
16518 | ||
edc3d884 MK |
16519 | err_printf(m, "Cursor [%d]:\n", i); |
16520 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16521 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16522 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16523 | } |
63b66e5b CW |
16524 | |
16525 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16526 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16527 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16528 | err_printf(m, " Power: %s\n", |
87ad3212 | 16529 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16530 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16531 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16532 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16533 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16534 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16535 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16536 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16537 | } | |
c4a1d9e4 | 16538 | } |