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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
db18b6a6 | 40 | #include "intel_dsi.h" |
e5510fac | 41 | #include "i915_trace.h" |
319c1d42 | 42 | #include <drm/drm_atomic.h> |
c196e1d6 | 43 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
44 | #include <drm/drm_dp_helper.h> |
45 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
46 | #include <drm/drm_plane_helper.h> |
47 | #include <drm/drm_rect.h> | |
c0f372b3 | 48 | #include <linux/dma_remapping.h> |
fd8e058a | 49 | #include <linux/reservation.h> |
79e53945 | 50 | |
5a21b665 DV |
51 | static bool is_mmio_work(struct intel_flip_work *work) |
52 | { | |
53 | return work->mmio_work.func; | |
54 | } | |
55 | ||
465c120c | 56 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 57 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
465c120c | 60 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 61 | DRM_FORMAT_XRGB8888, |
465c120c MR |
62 | }; |
63 | ||
64 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 65 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
66 | DRM_FORMAT_C8, |
67 | DRM_FORMAT_RGB565, | |
68 | DRM_FORMAT_XRGB8888, | |
69 | DRM_FORMAT_XBGR8888, | |
70 | DRM_FORMAT_XRGB2101010, | |
71 | DRM_FORMAT_XBGR2101010, | |
72 | }; | |
73 | ||
74 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
75 | DRM_FORMAT_C8, |
76 | DRM_FORMAT_RGB565, | |
77 | DRM_FORMAT_XRGB8888, | |
465c120c | 78 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 79 | DRM_FORMAT_ARGB8888, |
465c120c MR |
80 | DRM_FORMAT_ABGR8888, |
81 | DRM_FORMAT_XRGB2101010, | |
465c120c | 82 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
83 | DRM_FORMAT_YUYV, |
84 | DRM_FORMAT_YVYU, | |
85 | DRM_FORMAT_UYVY, | |
86 | DRM_FORMAT_VYUY, | |
465c120c MR |
87 | }; |
88 | ||
3d7d6510 MR |
89 | /* Cursor formats */ |
90 | static const uint32_t intel_cursor_formats[] = { | |
91 | DRM_FORMAT_ARGB8888, | |
92 | }; | |
93 | ||
f1f644dc | 94 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 95 | struct intel_crtc_state *pipe_config); |
18442d08 | 96 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 97 | struct intel_crtc_state *pipe_config); |
f1f644dc | 98 | |
eb1bfe80 JB |
99 | static int intel_framebuffer_init(struct drm_device *dev, |
100 | struct intel_framebuffer *ifb, | |
101 | struct drm_mode_fb_cmd2 *mode_cmd, | |
102 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
65edccce VS |
118 | static void skl_init_scalers(struct drm_i915_private *dev_priv, |
119 | struct intel_crtc *crtc, | |
120 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
121 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
122 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
123 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 124 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 125 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 126 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
324513c0 | 127 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 128 | |
d4906093 | 129 | struct intel_limit { |
4c5def93 ACO |
130 | struct { |
131 | int min, max; | |
132 | } dot, vco, n, m, m1, m2, p, p1; | |
133 | ||
134 | struct { | |
135 | int dot_limit; | |
136 | int p2_slow, p2_fast; | |
137 | } p2; | |
d4906093 | 138 | }; |
79e53945 | 139 | |
bfa7df01 VS |
140 | /* returns HPLL frequency in kHz */ |
141 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
142 | { | |
143 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
144 | ||
145 | /* Obtain SKU information */ | |
146 | mutex_lock(&dev_priv->sb_lock); | |
147 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
148 | CCK_FUSE_HPLL_FREQ_MASK; | |
149 | mutex_unlock(&dev_priv->sb_lock); | |
150 | ||
151 | return vco_freq[hpll_freq] * 1000; | |
152 | } | |
153 | ||
c30fec65 VS |
154 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
155 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
156 | { |
157 | u32 val; | |
158 | int divider; | |
159 | ||
bfa7df01 VS |
160 | mutex_lock(&dev_priv->sb_lock); |
161 | val = vlv_cck_read(dev_priv, reg); | |
162 | mutex_unlock(&dev_priv->sb_lock); | |
163 | ||
164 | divider = val & CCK_FREQUENCY_VALUES; | |
165 | ||
166 | WARN((val & CCK_FREQUENCY_STATUS) != | |
167 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
168 | "%s change in progress\n", name); | |
169 | ||
c30fec65 VS |
170 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
171 | } | |
172 | ||
173 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
174 | const char *name, u32 reg) | |
175 | { | |
176 | if (dev_priv->hpll_freq == 0) | |
177 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
178 | ||
179 | return vlv_get_cck_clock(dev_priv, name, reg, | |
180 | dev_priv->hpll_freq); | |
bfa7df01 VS |
181 | } |
182 | ||
e7dc33f3 VS |
183 | static int |
184 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 185 | { |
e7dc33f3 VS |
186 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
187 | } | |
d2acd215 | 188 | |
e7dc33f3 VS |
189 | static int |
190 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
191 | { | |
19ab4ed3 | 192 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
193 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
194 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
195 | } |
196 | ||
e7dc33f3 VS |
197 | static int |
198 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 199 | { |
79e50a4f JN |
200 | uint32_t clkcfg; |
201 | ||
e7dc33f3 | 202 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
203 | clkcfg = I915_READ(CLKCFG); |
204 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
205 | case CLKCFG_FSB_400: | |
e7dc33f3 | 206 | return 100000; |
79e50a4f | 207 | case CLKCFG_FSB_533: |
e7dc33f3 | 208 | return 133333; |
79e50a4f | 209 | case CLKCFG_FSB_667: |
e7dc33f3 | 210 | return 166667; |
79e50a4f | 211 | case CLKCFG_FSB_800: |
e7dc33f3 | 212 | return 200000; |
79e50a4f | 213 | case CLKCFG_FSB_1067: |
e7dc33f3 | 214 | return 266667; |
79e50a4f | 215 | case CLKCFG_FSB_1333: |
e7dc33f3 | 216 | return 333333; |
79e50a4f JN |
217 | /* these two are just a guess; one of them might be right */ |
218 | case CLKCFG_FSB_1600: | |
219 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 220 | return 400000; |
79e50a4f | 221 | default: |
e7dc33f3 | 222 | return 133333; |
79e50a4f JN |
223 | } |
224 | } | |
225 | ||
19ab4ed3 | 226 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
227 | { |
228 | if (HAS_PCH_SPLIT(dev_priv)) | |
229 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
230 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
231 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
232 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
233 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
234 | else | |
235 | return; /* no rawclk on other platforms, or no need to know it */ | |
236 | ||
237 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
238 | } | |
239 | ||
bfa7df01 VS |
240 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
241 | { | |
666a4537 | 242 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
243 | return; |
244 | ||
245 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
246 | CCK_CZ_CLOCK_CONTROL); | |
247 | ||
248 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
249 | } | |
250 | ||
021357ac | 251 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
252 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
253 | const struct intel_crtc_state *pipe_config) | |
021357ac | 254 | { |
21a727b3 VS |
255 | if (HAS_DDI(dev_priv)) |
256 | return pipe_config->port_clock; /* SPLL */ | |
257 | else if (IS_GEN5(dev_priv)) | |
258 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 259 | else |
21a727b3 | 260 | return 270000; |
021357ac CW |
261 | } |
262 | ||
1b6f4958 | 263 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 264 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 265 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 266 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
267 | .m = { .min = 96, .max = 140 }, |
268 | .m1 = { .min = 18, .max = 26 }, | |
269 | .m2 = { .min = 6, .max = 16 }, | |
270 | .p = { .min = 4, .max = 128 }, | |
271 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
272 | .p2 = { .dot_limit = 165000, |
273 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
274 | }; |
275 | ||
1b6f4958 | 276 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 277 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 278 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 279 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
280 | .m = { .min = 96, .max = 140 }, |
281 | .m1 = { .min = 18, .max = 26 }, | |
282 | .m2 = { .min = 6, .max = 16 }, | |
283 | .p = { .min = 4, .max = 128 }, | |
284 | .p1 = { .min = 2, .max = 33 }, | |
285 | .p2 = { .dot_limit = 165000, | |
286 | .p2_slow = 4, .p2_fast = 4 }, | |
287 | }; | |
288 | ||
1b6f4958 | 289 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 290 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 291 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 292 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
293 | .m = { .min = 96, .max = 140 }, |
294 | .m1 = { .min = 18, .max = 26 }, | |
295 | .m2 = { .min = 6, .max = 16 }, | |
296 | .p = { .min = 4, .max = 128 }, | |
297 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
298 | .p2 = { .dot_limit = 165000, |
299 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 300 | }; |
273e27ca | 301 | |
1b6f4958 | 302 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
303 | .dot = { .min = 20000, .max = 400000 }, |
304 | .vco = { .min = 1400000, .max = 2800000 }, | |
305 | .n = { .min = 1, .max = 6 }, | |
306 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
307 | .m1 = { .min = 8, .max = 18 }, |
308 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
309 | .p = { .min = 5, .max = 80 }, |
310 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
311 | .p2 = { .dot_limit = 200000, |
312 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
313 | }; |
314 | ||
1b6f4958 | 315 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
316 | .dot = { .min = 20000, .max = 400000 }, |
317 | .vco = { .min = 1400000, .max = 2800000 }, | |
318 | .n = { .min = 1, .max = 6 }, | |
319 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
320 | .m1 = { .min = 8, .max = 18 }, |
321 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
322 | .p = { .min = 7, .max = 98 }, |
323 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
324 | .p2 = { .dot_limit = 112000, |
325 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
326 | }; |
327 | ||
273e27ca | 328 | |
1b6f4958 | 329 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
330 | .dot = { .min = 25000, .max = 270000 }, |
331 | .vco = { .min = 1750000, .max = 3500000}, | |
332 | .n = { .min = 1, .max = 4 }, | |
333 | .m = { .min = 104, .max = 138 }, | |
334 | .m1 = { .min = 17, .max = 23 }, | |
335 | .m2 = { .min = 5, .max = 11 }, | |
336 | .p = { .min = 10, .max = 30 }, | |
337 | .p1 = { .min = 1, .max = 3}, | |
338 | .p2 = { .dot_limit = 270000, | |
339 | .p2_slow = 10, | |
340 | .p2_fast = 10 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
1b6f4958 | 344 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
345 | .dot = { .min = 22000, .max = 400000 }, |
346 | .vco = { .min = 1750000, .max = 3500000}, | |
347 | .n = { .min = 1, .max = 4 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 16, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 5, .max = 80 }, | |
352 | .p1 = { .min = 1, .max = 8}, | |
353 | .p2 = { .dot_limit = 165000, | |
354 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
355 | }; |
356 | ||
1b6f4958 | 357 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
358 | .dot = { .min = 20000, .max = 115000 }, |
359 | .vco = { .min = 1750000, .max = 3500000 }, | |
360 | .n = { .min = 1, .max = 3 }, | |
361 | .m = { .min = 104, .max = 138 }, | |
362 | .m1 = { .min = 17, .max = 23 }, | |
363 | .m2 = { .min = 5, .max = 11 }, | |
364 | .p = { .min = 28, .max = 112 }, | |
365 | .p1 = { .min = 2, .max = 8 }, | |
366 | .p2 = { .dot_limit = 0, | |
367 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 368 | }, |
e4b36699 KP |
369 | }; |
370 | ||
1b6f4958 | 371 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
372 | .dot = { .min = 80000, .max = 224000 }, |
373 | .vco = { .min = 1750000, .max = 3500000 }, | |
374 | .n = { .min = 1, .max = 3 }, | |
375 | .m = { .min = 104, .max = 138 }, | |
376 | .m1 = { .min = 17, .max = 23 }, | |
377 | .m2 = { .min = 5, .max = 11 }, | |
378 | .p = { .min = 14, .max = 42 }, | |
379 | .p1 = { .min = 2, .max = 6 }, | |
380 | .p2 = { .dot_limit = 0, | |
381 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 382 | }, |
e4b36699 KP |
383 | }; |
384 | ||
1b6f4958 | 385 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
386 | .dot = { .min = 20000, .max = 400000}, |
387 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 388 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
389 | .n = { .min = 3, .max = 6 }, |
390 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 391 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
392 | .m1 = { .min = 0, .max = 0 }, |
393 | .m2 = { .min = 0, .max = 254 }, | |
394 | .p = { .min = 5, .max = 80 }, | |
395 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
396 | .p2 = { .dot_limit = 200000, |
397 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
398 | }; |
399 | ||
1b6f4958 | 400 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
401 | .dot = { .min = 20000, .max = 400000 }, |
402 | .vco = { .min = 1700000, .max = 3500000 }, | |
403 | .n = { .min = 3, .max = 6 }, | |
404 | .m = { .min = 2, .max = 256 }, | |
405 | .m1 = { .min = 0, .max = 0 }, | |
406 | .m2 = { .min = 0, .max = 254 }, | |
407 | .p = { .min = 7, .max = 112 }, | |
408 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
409 | .p2 = { .dot_limit = 112000, |
410 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
411 | }; |
412 | ||
273e27ca EA |
413 | /* Ironlake / Sandybridge |
414 | * | |
415 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
416 | * the range value for them is (actual_value - 2). | |
417 | */ | |
1b6f4958 | 418 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
419 | .dot = { .min = 25000, .max = 350000 }, |
420 | .vco = { .min = 1760000, .max = 3510000 }, | |
421 | .n = { .min = 1, .max = 5 }, | |
422 | .m = { .min = 79, .max = 127 }, | |
423 | .m1 = { .min = 12, .max = 22 }, | |
424 | .m2 = { .min = 5, .max = 9 }, | |
425 | .p = { .min = 5, .max = 80 }, | |
426 | .p1 = { .min = 1, .max = 8 }, | |
427 | .p2 = { .dot_limit = 225000, | |
428 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
429 | }; |
430 | ||
1b6f4958 | 431 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 3 }, | |
435 | .m = { .min = 79, .max = 118 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
439 | .p1 = { .min = 2, .max = 8 }, | |
440 | .p2 = { .dot_limit = 225000, | |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
1b6f4958 | 444 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 127 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 56 }, | |
452 | .p1 = { .min = 2, .max = 8 }, | |
453 | .p2 = { .dot_limit = 225000, | |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
455 | }; |
456 | ||
273e27ca | 457 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 458 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
459 | .dot = { .min = 25000, .max = 350000 }, |
460 | .vco = { .min = 1760000, .max = 3510000 }, | |
461 | .n = { .min = 1, .max = 2 }, | |
462 | .m = { .min = 79, .max = 126 }, | |
463 | .m1 = { .min = 12, .max = 22 }, | |
464 | .m2 = { .min = 5, .max = 9 }, | |
465 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 466 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
467 | .p2 = { .dot_limit = 225000, |
468 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
469 | }; |
470 | ||
1b6f4958 | 471 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
472 | .dot = { .min = 25000, .max = 350000 }, |
473 | .vco = { .min = 1760000, .max = 3510000 }, | |
474 | .n = { .min = 1, .max = 3 }, | |
475 | .m = { .min = 79, .max = 126 }, | |
476 | .m1 = { .min = 12, .max = 22 }, | |
477 | .m2 = { .min = 5, .max = 9 }, | |
478 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 479 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
480 | .p2 = { .dot_limit = 225000, |
481 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
482 | }; |
483 | ||
1b6f4958 | 484 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
485 | /* |
486 | * These are the data rate limits (measured in fast clocks) | |
487 | * since those are the strictest limits we have. The fast | |
488 | * clock and actual rate limits are more relaxed, so checking | |
489 | * them would make no difference. | |
490 | */ | |
491 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 492 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 493 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
494 | .m1 = { .min = 2, .max = 3 }, |
495 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 496 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 497 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
498 | }; |
499 | ||
1b6f4958 | 500 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
501 | /* |
502 | * These are the data rate limits (measured in fast clocks) | |
503 | * since those are the strictest limits we have. The fast | |
504 | * clock and actual rate limits are more relaxed, so checking | |
505 | * them would make no difference. | |
506 | */ | |
507 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 508 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
509 | .n = { .min = 1, .max = 1 }, |
510 | .m1 = { .min = 2, .max = 2 }, | |
511 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
512 | .p1 = { .min = 2, .max = 4 }, | |
513 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
514 | }; | |
515 | ||
1b6f4958 | 516 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
517 | /* FIXME: find real dot limits */ |
518 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 519 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
520 | .n = { .min = 1, .max = 1 }, |
521 | .m1 = { .min = 2, .max = 2 }, | |
522 | /* FIXME: find real m2 limits */ | |
523 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
524 | .p1 = { .min = 2, .max = 4 }, | |
525 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
526 | }; | |
527 | ||
cdba954e ACO |
528 | static bool |
529 | needs_modeset(struct drm_crtc_state *state) | |
530 | { | |
fc596660 | 531 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
532 | } |
533 | ||
dccbea3b ID |
534 | /* |
535 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
536 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
537 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
538 | * The helpers' return value is the rate of the clock that is fed to the | |
539 | * display engine's pipe which can be the above fast dot clock rate or a | |
540 | * divided-down version of it. | |
541 | */ | |
f2b115e6 | 542 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 543 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 544 | { |
2177832f SL |
545 | clock->m = clock->m2 + 2; |
546 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 547 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 548 | return 0; |
fb03ac01 VS |
549 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
550 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
551 | |
552 | return clock->dot; | |
2177832f SL |
553 | } |
554 | ||
7429e9d4 DV |
555 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
556 | { | |
557 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
558 | } | |
559 | ||
9e2c8475 | 560 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 561 | { |
7429e9d4 | 562 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 563 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 564 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 565 | return 0; |
fb03ac01 VS |
566 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
567 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
568 | |
569 | return clock->dot; | |
79e53945 JB |
570 | } |
571 | ||
9e2c8475 | 572 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
573 | { |
574 | clock->m = clock->m1 * clock->m2; | |
575 | clock->p = clock->p1 * clock->p2; | |
576 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 577 | return 0; |
589eca67 ID |
578 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
579 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
580 | |
581 | return clock->dot / 5; | |
589eca67 ID |
582 | } |
583 | ||
9e2c8475 | 584 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
585 | { |
586 | clock->m = clock->m1 * clock->m2; | |
587 | clock->p = clock->p1 * clock->p2; | |
588 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 589 | return 0; |
ef9348c8 CML |
590 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
591 | clock->n << 22); | |
592 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
593 | |
594 | return clock->dot / 5; | |
ef9348c8 CML |
595 | } |
596 | ||
7c04d1d9 | 597 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
598 | /** |
599 | * Returns whether the given set of divisors are valid for a given refclk with | |
600 | * the given connectors. | |
601 | */ | |
602 | ||
e2d214ae | 603 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 604 | const struct intel_limit *limit, |
9e2c8475 | 605 | const struct dpll *clock) |
79e53945 | 606 | { |
f01b7962 VS |
607 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
608 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 609 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 610 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 611 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 612 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 613 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 614 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 615 | |
e2d214ae TU |
616 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
617 | !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv)) | |
f01b7962 VS |
618 | if (clock->m1 <= clock->m2) |
619 | INTELPllInvalid("m1 <= m2\n"); | |
620 | ||
e2d214ae TU |
621 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
622 | !IS_BROXTON(dev_priv)) { | |
f01b7962 VS |
623 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
624 | INTELPllInvalid("p out of range\n"); | |
625 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
626 | INTELPllInvalid("m out of range\n"); | |
627 | } | |
628 | ||
79e53945 | 629 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 630 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
631 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
632 | * connector, etc., rather than just a single range. | |
633 | */ | |
634 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 635 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
636 | |
637 | return true; | |
638 | } | |
639 | ||
3b1429d9 | 640 | static int |
1b6f4958 | 641 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
642 | const struct intel_crtc_state *crtc_state, |
643 | int target) | |
79e53945 | 644 | { |
3b1429d9 | 645 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 646 | |
2d84d2b3 | 647 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 648 | /* |
a210b028 DV |
649 | * For LVDS just rely on its current settings for dual-channel. |
650 | * We haven't figured out how to reliably set up different | |
651 | * single/dual channel state, if we even can. | |
79e53945 | 652 | */ |
1974cad0 | 653 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 654 | return limit->p2.p2_fast; |
79e53945 | 655 | else |
3b1429d9 | 656 | return limit->p2.p2_slow; |
79e53945 JB |
657 | } else { |
658 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 659 | return limit->p2.p2_slow; |
79e53945 | 660 | else |
3b1429d9 | 661 | return limit->p2.p2_fast; |
79e53945 | 662 | } |
3b1429d9 VS |
663 | } |
664 | ||
70e8aa21 ACO |
665 | /* |
666 | * Returns a set of divisors for the desired target clock with the given | |
667 | * refclk, or FALSE. The returned values represent the clock equation: | |
668 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
669 | * | |
670 | * Target and reference clocks are specified in kHz. | |
671 | * | |
672 | * If match_clock is provided, then best_clock P divider must match the P | |
673 | * divider from @match_clock used for LVDS downclocking. | |
674 | */ | |
3b1429d9 | 675 | static bool |
1b6f4958 | 676 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 677 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
678 | int target, int refclk, struct dpll *match_clock, |
679 | struct dpll *best_clock) | |
3b1429d9 VS |
680 | { |
681 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 682 | struct dpll clock; |
3b1429d9 | 683 | int err = target; |
79e53945 | 684 | |
0206e353 | 685 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 686 | |
3b1429d9 VS |
687 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
688 | ||
42158660 ZY |
689 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
690 | clock.m1++) { | |
691 | for (clock.m2 = limit->m2.min; | |
692 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 693 | if (clock.m2 >= clock.m1) |
42158660 ZY |
694 | break; |
695 | for (clock.n = limit->n.min; | |
696 | clock.n <= limit->n.max; clock.n++) { | |
697 | for (clock.p1 = limit->p1.min; | |
698 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
699 | int this_err; |
700 | ||
dccbea3b | 701 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
702 | if (!intel_PLL_is_valid(to_i915(dev), |
703 | limit, | |
ac58c3f0 DV |
704 | &clock)) |
705 | continue; | |
706 | if (match_clock && | |
707 | clock.p != match_clock->p) | |
708 | continue; | |
709 | ||
710 | this_err = abs(clock.dot - target); | |
711 | if (this_err < err) { | |
712 | *best_clock = clock; | |
713 | err = this_err; | |
714 | } | |
715 | } | |
716 | } | |
717 | } | |
718 | } | |
719 | ||
720 | return (err != target); | |
721 | } | |
722 | ||
70e8aa21 ACO |
723 | /* |
724 | * Returns a set of divisors for the desired target clock with the given | |
725 | * refclk, or FALSE. The returned values represent the clock equation: | |
726 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
727 | * | |
728 | * Target and reference clocks are specified in kHz. | |
729 | * | |
730 | * If match_clock is provided, then best_clock P divider must match the P | |
731 | * divider from @match_clock used for LVDS downclocking. | |
732 | */ | |
ac58c3f0 | 733 | static bool |
1b6f4958 | 734 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 735 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
736 | int target, int refclk, struct dpll *match_clock, |
737 | struct dpll *best_clock) | |
79e53945 | 738 | { |
3b1429d9 | 739 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 740 | struct dpll clock; |
79e53945 JB |
741 | int err = target; |
742 | ||
0206e353 | 743 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 744 | |
3b1429d9 VS |
745 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
746 | ||
42158660 ZY |
747 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
748 | clock.m1++) { | |
749 | for (clock.m2 = limit->m2.min; | |
750 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
751 | for (clock.n = limit->n.min; |
752 | clock.n <= limit->n.max; clock.n++) { | |
753 | for (clock.p1 = limit->p1.min; | |
754 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
755 | int this_err; |
756 | ||
dccbea3b | 757 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
758 | if (!intel_PLL_is_valid(to_i915(dev), |
759 | limit, | |
1b894b59 | 760 | &clock)) |
79e53945 | 761 | continue; |
cec2f356 SP |
762 | if (match_clock && |
763 | clock.p != match_clock->p) | |
764 | continue; | |
79e53945 JB |
765 | |
766 | this_err = abs(clock.dot - target); | |
767 | if (this_err < err) { | |
768 | *best_clock = clock; | |
769 | err = this_err; | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
774 | } | |
775 | ||
776 | return (err != target); | |
777 | } | |
778 | ||
997c030c ACO |
779 | /* |
780 | * Returns a set of divisors for the desired target clock with the given | |
781 | * refclk, or FALSE. The returned values represent the clock equation: | |
782 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
783 | * |
784 | * Target and reference clocks are specified in kHz. | |
785 | * | |
786 | * If match_clock is provided, then best_clock P divider must match the P | |
787 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 788 | */ |
d4906093 | 789 | static bool |
1b6f4958 | 790 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 791 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
792 | int target, int refclk, struct dpll *match_clock, |
793 | struct dpll *best_clock) | |
d4906093 | 794 | { |
3b1429d9 | 795 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 796 | struct dpll clock; |
d4906093 | 797 | int max_n; |
3b1429d9 | 798 | bool found = false; |
6ba770dc AJ |
799 | /* approximately equals target * 0.00585 */ |
800 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
801 | |
802 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
803 | |
804 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
805 | ||
d4906093 | 806 | max_n = limit->n.max; |
f77f13e2 | 807 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 808 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 809 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
810 | for (clock.m1 = limit->m1.max; |
811 | clock.m1 >= limit->m1.min; clock.m1--) { | |
812 | for (clock.m2 = limit->m2.max; | |
813 | clock.m2 >= limit->m2.min; clock.m2--) { | |
814 | for (clock.p1 = limit->p1.max; | |
815 | clock.p1 >= limit->p1.min; clock.p1--) { | |
816 | int this_err; | |
817 | ||
dccbea3b | 818 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
819 | if (!intel_PLL_is_valid(to_i915(dev), |
820 | limit, | |
1b894b59 | 821 | &clock)) |
d4906093 | 822 | continue; |
1b894b59 CW |
823 | |
824 | this_err = abs(clock.dot - target); | |
d4906093 ML |
825 | if (this_err < err_most) { |
826 | *best_clock = clock; | |
827 | err_most = this_err; | |
828 | max_n = clock.n; | |
829 | found = true; | |
830 | } | |
831 | } | |
832 | } | |
833 | } | |
834 | } | |
2c07245f ZW |
835 | return found; |
836 | } | |
837 | ||
d5dd62bd ID |
838 | /* |
839 | * Check if the calculated PLL configuration is more optimal compared to the | |
840 | * best configuration and error found so far. Return the calculated error. | |
841 | */ | |
842 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
843 | const struct dpll *calculated_clock, |
844 | const struct dpll *best_clock, | |
d5dd62bd ID |
845 | unsigned int best_error_ppm, |
846 | unsigned int *error_ppm) | |
847 | { | |
9ca3ba01 ID |
848 | /* |
849 | * For CHV ignore the error and consider only the P value. | |
850 | * Prefer a bigger P value based on HW requirements. | |
851 | */ | |
920a14b2 | 852 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
853 | *error_ppm = 0; |
854 | ||
855 | return calculated_clock->p > best_clock->p; | |
856 | } | |
857 | ||
24be4e46 ID |
858 | if (WARN_ON_ONCE(!target_freq)) |
859 | return false; | |
860 | ||
d5dd62bd ID |
861 | *error_ppm = div_u64(1000000ULL * |
862 | abs(target_freq - calculated_clock->dot), | |
863 | target_freq); | |
864 | /* | |
865 | * Prefer a better P value over a better (smaller) error if the error | |
866 | * is small. Ensure this preference for future configurations too by | |
867 | * setting the error to 0. | |
868 | */ | |
869 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
870 | *error_ppm = 0; | |
871 | ||
872 | return true; | |
873 | } | |
874 | ||
875 | return *error_ppm + 10 < best_error_ppm; | |
876 | } | |
877 | ||
65b3d6a9 ACO |
878 | /* |
879 | * Returns a set of divisors for the desired target clock with the given | |
880 | * refclk, or FALSE. The returned values represent the clock equation: | |
881 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
882 | */ | |
a0c4da24 | 883 | static bool |
1b6f4958 | 884 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 885 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
886 | int target, int refclk, struct dpll *match_clock, |
887 | struct dpll *best_clock) | |
a0c4da24 | 888 | { |
a93e255f | 889 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 890 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 891 | struct dpll clock; |
69e4f900 | 892 | unsigned int bestppm = 1000000; |
27e639bf VS |
893 | /* min update 19.2 MHz */ |
894 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 895 | bool found = false; |
a0c4da24 | 896 | |
6b4bf1c4 VS |
897 | target *= 5; /* fast clock */ |
898 | ||
899 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
900 | |
901 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 902 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 903 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 904 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 905 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 906 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 907 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 908 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 909 | unsigned int ppm; |
69e4f900 | 910 | |
6b4bf1c4 VS |
911 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
912 | refclk * clock.m1); | |
913 | ||
dccbea3b | 914 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 915 | |
e2d214ae TU |
916 | if (!intel_PLL_is_valid(to_i915(dev), |
917 | limit, | |
f01b7962 | 918 | &clock)) |
43b0ac53 VS |
919 | continue; |
920 | ||
d5dd62bd ID |
921 | if (!vlv_PLL_is_optimal(dev, target, |
922 | &clock, | |
923 | best_clock, | |
924 | bestppm, &ppm)) | |
925 | continue; | |
6b4bf1c4 | 926 | |
d5dd62bd ID |
927 | *best_clock = clock; |
928 | bestppm = ppm; | |
929 | found = true; | |
a0c4da24 JB |
930 | } |
931 | } | |
932 | } | |
933 | } | |
a0c4da24 | 934 | |
49e497ef | 935 | return found; |
a0c4da24 | 936 | } |
a4fc5ed6 | 937 | |
65b3d6a9 ACO |
938 | /* |
939 | * Returns a set of divisors for the desired target clock with the given | |
940 | * refclk, or FALSE. The returned values represent the clock equation: | |
941 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
942 | */ | |
ef9348c8 | 943 | static bool |
1b6f4958 | 944 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 945 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
946 | int target, int refclk, struct dpll *match_clock, |
947 | struct dpll *best_clock) | |
ef9348c8 | 948 | { |
a93e255f | 949 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 950 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 951 | unsigned int best_error_ppm; |
9e2c8475 | 952 | struct dpll clock; |
ef9348c8 CML |
953 | uint64_t m2; |
954 | int found = false; | |
955 | ||
956 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 957 | best_error_ppm = 1000000; |
ef9348c8 CML |
958 | |
959 | /* | |
960 | * Based on hardware doc, the n always set to 1, and m1 always | |
961 | * set to 2. If requires to support 200Mhz refclk, we need to | |
962 | * revisit this because n may not 1 anymore. | |
963 | */ | |
964 | clock.n = 1, clock.m1 = 2; | |
965 | target *= 5; /* fast clock */ | |
966 | ||
967 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
968 | for (clock.p2 = limit->p2.p2_fast; | |
969 | clock.p2 >= limit->p2.p2_slow; | |
970 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 971 | unsigned int error_ppm; |
ef9348c8 CML |
972 | |
973 | clock.p = clock.p1 * clock.p2; | |
974 | ||
975 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
976 | clock.n) << 22, refclk * clock.m1); | |
977 | ||
978 | if (m2 > INT_MAX/clock.m1) | |
979 | continue; | |
980 | ||
981 | clock.m2 = m2; | |
982 | ||
dccbea3b | 983 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 984 | |
e2d214ae | 985 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
986 | continue; |
987 | ||
9ca3ba01 ID |
988 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
989 | best_error_ppm, &error_ppm)) | |
990 | continue; | |
991 | ||
992 | *best_clock = clock; | |
993 | best_error_ppm = error_ppm; | |
994 | found = true; | |
ef9348c8 CML |
995 | } |
996 | } | |
997 | ||
998 | return found; | |
999 | } | |
1000 | ||
5ab7b0b7 | 1001 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 1002 | struct dpll *best_clock) |
5ab7b0b7 | 1003 | { |
65b3d6a9 | 1004 | int refclk = 100000; |
1b6f4958 | 1005 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1006 | |
65b3d6a9 | 1007 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1008 | target_clock, refclk, NULL, best_clock); |
1009 | } | |
1010 | ||
525b9311 | 1011 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 1012 | { |
20ddf665 VS |
1013 | /* Be paranoid as we can arrive here with only partial |
1014 | * state retrieved from the hardware during setup. | |
1015 | * | |
241bfc38 | 1016 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1017 | * as Haswell has gained clock readout/fastboot support. |
1018 | * | |
66e514c1 | 1019 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1020 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1021 | * |
1022 | * FIXME: The intel_crtc->active here should be switched to | |
1023 | * crtc->state->active once we have proper CRTC states wired up | |
1024 | * for atomic. | |
20ddf665 | 1025 | */ |
525b9311 VS |
1026 | return crtc->active && crtc->base.primary->state->fb && |
1027 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
1028 | } |
1029 | ||
a5c961d1 PZ |
1030 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1031 | enum pipe pipe) | |
1032 | { | |
98187836 | 1033 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 1034 | |
e2af48c6 | 1035 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1036 | } |
1037 | ||
6315b5d3 | 1038 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 1039 | { |
f0f59a00 | 1040 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1041 | u32 line1, line2; |
1042 | u32 line_mask; | |
1043 | ||
5db94019 | 1044 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
1045 | line_mask = DSL_LINEMASK_GEN2; |
1046 | else | |
1047 | line_mask = DSL_LINEMASK_GEN3; | |
1048 | ||
1049 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1050 | msleep(5); |
fbf49ea2 VS |
1051 | line2 = I915_READ(reg) & line_mask; |
1052 | ||
1053 | return line1 == line2; | |
1054 | } | |
1055 | ||
ab7ad7f6 KP |
1056 | /* |
1057 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1058 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1059 | * |
1060 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1061 | * spinning on the vblank interrupt status bit, since we won't actually | |
1062 | * see an interrupt when the pipe is disabled. | |
1063 | * | |
ab7ad7f6 KP |
1064 | * On Gen4 and above: |
1065 | * wait for the pipe register state bit to turn off | |
1066 | * | |
1067 | * Otherwise: | |
1068 | * wait for the display line value to settle (it usually | |
1069 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1070 | * |
9d0498a2 | 1071 | */ |
575f7ab7 | 1072 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1073 | { |
6315b5d3 | 1074 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1075 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1076 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1077 | |
6315b5d3 | 1078 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1079 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1080 | |
1081 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1082 | if (intel_wait_for_register(dev_priv, |
1083 | reg, I965_PIPECONF_ACTIVE, 0, | |
1084 | 100)) | |
284637d9 | 1085 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1086 | } else { |
ab7ad7f6 | 1087 | /* Wait for the display line to settle */ |
6315b5d3 | 1088 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1089 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1090 | } |
79e53945 JB |
1091 | } |
1092 | ||
b24e7179 | 1093 | /* Only for pre-ILK configs */ |
55607e8a DV |
1094 | void assert_pll(struct drm_i915_private *dev_priv, |
1095 | enum pipe pipe, bool state) | |
b24e7179 | 1096 | { |
b24e7179 JB |
1097 | u32 val; |
1098 | bool cur_state; | |
1099 | ||
649636ef | 1100 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1101 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1102 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1103 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1104 | onoff(state), onoff(cur_state)); |
b24e7179 | 1105 | } |
b24e7179 | 1106 | |
23538ef1 | 1107 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1108 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1109 | { |
1110 | u32 val; | |
1111 | bool cur_state; | |
1112 | ||
a580516d | 1113 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1114 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1115 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1116 | |
1117 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1118 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1119 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1120 | onoff(state), onoff(cur_state)); |
23538ef1 | 1121 | } |
23538ef1 | 1122 | |
040484af JB |
1123 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1124 | enum pipe pipe, bool state) | |
1125 | { | |
040484af | 1126 | bool cur_state; |
ad80a810 PZ |
1127 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1128 | pipe); | |
040484af | 1129 | |
2d1fe073 | 1130 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1131 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1132 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1133 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1134 | } else { |
649636ef | 1135 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1136 | cur_state = !!(val & FDI_TX_ENABLE); |
1137 | } | |
e2c719b7 | 1138 | I915_STATE_WARN(cur_state != state, |
040484af | 1139 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1140 | onoff(state), onoff(cur_state)); |
040484af JB |
1141 | } |
1142 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1143 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1144 | ||
1145 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1146 | enum pipe pipe, bool state) | |
1147 | { | |
040484af JB |
1148 | u32 val; |
1149 | bool cur_state; | |
1150 | ||
649636ef | 1151 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1152 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1153 | I915_STATE_WARN(cur_state != state, |
040484af | 1154 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1155 | onoff(state), onoff(cur_state)); |
040484af JB |
1156 | } |
1157 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1158 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1159 | ||
1160 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1161 | enum pipe pipe) | |
1162 | { | |
040484af JB |
1163 | u32 val; |
1164 | ||
1165 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1166 | if (IS_GEN5(dev_priv)) |
040484af JB |
1167 | return; |
1168 | ||
bf507ef7 | 1169 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1170 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1171 | return; |
1172 | ||
649636ef | 1173 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1174 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1175 | } |
1176 | ||
55607e8a DV |
1177 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1178 | enum pipe pipe, bool state) | |
040484af | 1179 | { |
040484af | 1180 | u32 val; |
55607e8a | 1181 | bool cur_state; |
040484af | 1182 | |
649636ef | 1183 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1184 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1185 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1186 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1187 | onoff(state), onoff(cur_state)); |
040484af JB |
1188 | } |
1189 | ||
4f8036a2 | 1190 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1191 | { |
f0f59a00 | 1192 | i915_reg_t pp_reg; |
ea0760cf JB |
1193 | u32 val; |
1194 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1195 | bool locked = true; |
ea0760cf | 1196 | |
4f8036a2 | 1197 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1198 | return; |
1199 | ||
4f8036a2 | 1200 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1201 | u32 port_sel; |
1202 | ||
44cb734c ID |
1203 | pp_reg = PP_CONTROL(0); |
1204 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1205 | |
1206 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1207 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1208 | panel_pipe = PIPE_B; | |
1209 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1210 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1211 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1212 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1213 | panel_pipe = pipe; |
ea0760cf | 1214 | } else { |
44cb734c | 1215 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1216 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1217 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1218 | } |
1219 | ||
1220 | val = I915_READ(pp_reg); | |
1221 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1222 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1223 | locked = false; |
1224 | ||
e2c719b7 | 1225 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1226 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1227 | pipe_name(pipe)); |
ea0760cf JB |
1228 | } |
1229 | ||
93ce0ba6 JN |
1230 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1231 | enum pipe pipe, bool state) | |
1232 | { | |
93ce0ba6 JN |
1233 | bool cur_state; |
1234 | ||
50a0bc90 | 1235 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1236 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1237 | else |
5efb3e28 | 1238 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1239 | |
e2c719b7 | 1240 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1241 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1242 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1243 | } |
1244 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1245 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1246 | ||
b840d907 JB |
1247 | void assert_pipe(struct drm_i915_private *dev_priv, |
1248 | enum pipe pipe, bool state) | |
b24e7179 | 1249 | { |
63d7bbe9 | 1250 | bool cur_state; |
702e7a56 PZ |
1251 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1252 | pipe); | |
4feed0eb | 1253 | enum intel_display_power_domain power_domain; |
b24e7179 | 1254 | |
b6b5d049 VS |
1255 | /* if we need the pipe quirk it must be always on */ |
1256 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1257 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1258 | state = true; |
1259 | ||
4feed0eb ID |
1260 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1261 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1262 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1263 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1264 | |
1265 | intel_display_power_put(dev_priv, power_domain); | |
1266 | } else { | |
1267 | cur_state = false; | |
69310161 PZ |
1268 | } |
1269 | ||
e2c719b7 | 1270 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1271 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1272 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1273 | } |
1274 | ||
931872fc CW |
1275 | static void assert_plane(struct drm_i915_private *dev_priv, |
1276 | enum plane plane, bool state) | |
b24e7179 | 1277 | { |
b24e7179 | 1278 | u32 val; |
931872fc | 1279 | bool cur_state; |
b24e7179 | 1280 | |
649636ef | 1281 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1282 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1283 | I915_STATE_WARN(cur_state != state, |
931872fc | 1284 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1285 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1286 | } |
1287 | ||
931872fc CW |
1288 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1289 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1290 | ||
b24e7179 JB |
1291 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1292 | enum pipe pipe) | |
1293 | { | |
649636ef | 1294 | int i; |
b24e7179 | 1295 | |
653e1026 | 1296 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1297 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1298 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1299 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1300 | "plane %c assertion failure, should be disabled but not\n", |
1301 | plane_name(pipe)); | |
19ec1358 | 1302 | return; |
28c05794 | 1303 | } |
19ec1358 | 1304 | |
b24e7179 | 1305 | /* Need to check both planes against the pipe */ |
055e393f | 1306 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1307 | u32 val = I915_READ(DSPCNTR(i)); |
1308 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1309 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1310 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1311 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1312 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1313 | } |
1314 | } | |
1315 | ||
19332d7a JB |
1316 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1317 | enum pipe pipe) | |
1318 | { | |
649636ef | 1319 | int sprite; |
19332d7a | 1320 | |
6315b5d3 | 1321 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1322 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1323 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1324 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1325 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1326 | sprite, pipe_name(pipe)); | |
1327 | } | |
920a14b2 | 1328 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1329 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1330 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1331 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1332 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1333 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1334 | } |
6315b5d3 | 1335 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1336 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1337 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1338 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1339 | plane_name(pipe), pipe_name(pipe)); |
6315b5d3 | 1340 | } else if (INTEL_GEN(dev_priv) >= 5) { |
649636ef | 1341 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1342 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1343 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1344 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1345 | } |
1346 | } | |
1347 | ||
08c71e5e VS |
1348 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1349 | { | |
e2c719b7 | 1350 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1351 | drm_crtc_vblank_put(crtc); |
1352 | } | |
1353 | ||
7abd4b35 ACO |
1354 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1355 | enum pipe pipe) | |
92f2584a | 1356 | { |
92f2584a JB |
1357 | u32 val; |
1358 | bool enabled; | |
1359 | ||
649636ef | 1360 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1361 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1362 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1363 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1364 | pipe_name(pipe)); | |
92f2584a JB |
1365 | } |
1366 | ||
4e634389 KP |
1367 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1368 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1369 | { |
1370 | if ((val & DP_PORT_EN) == 0) | |
1371 | return false; | |
1372 | ||
2d1fe073 | 1373 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1374 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1375 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1376 | return false; | |
2d1fe073 | 1377 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1378 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1379 | return false; | |
f0575e92 KP |
1380 | } else { |
1381 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1382 | return false; | |
1383 | } | |
1384 | return true; | |
1385 | } | |
1386 | ||
1519b995 KP |
1387 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1388 | enum pipe pipe, u32 val) | |
1389 | { | |
dc0fa718 | 1390 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1391 | return false; |
1392 | ||
2d1fe073 | 1393 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1394 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1395 | return false; |
2d1fe073 | 1396 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1397 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1398 | return false; | |
1519b995 | 1399 | } else { |
dc0fa718 | 1400 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1401 | return false; |
1402 | } | |
1403 | return true; | |
1404 | } | |
1405 | ||
1406 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1407 | enum pipe pipe, u32 val) | |
1408 | { | |
1409 | if ((val & LVDS_PORT_EN) == 0) | |
1410 | return false; | |
1411 | ||
2d1fe073 | 1412 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1413 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1414 | return false; | |
1415 | } else { | |
1416 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1417 | return false; | |
1418 | } | |
1419 | return true; | |
1420 | } | |
1421 | ||
1422 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1423 | enum pipe pipe, u32 val) | |
1424 | { | |
1425 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1426 | return false; | |
2d1fe073 | 1427 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1428 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1429 | return false; | |
1430 | } else { | |
1431 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1432 | return false; | |
1433 | } | |
1434 | return true; | |
1435 | } | |
1436 | ||
291906f1 | 1437 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1438 | enum pipe pipe, i915_reg_t reg, |
1439 | u32 port_sel) | |
291906f1 | 1440 | { |
47a05eca | 1441 | u32 val = I915_READ(reg); |
e2c719b7 | 1442 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1443 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1444 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1445 | |
2d1fe073 | 1446 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1447 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1448 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1449 | } |
1450 | ||
1451 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1452 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1453 | { |
47a05eca | 1454 | u32 val = I915_READ(reg); |
e2c719b7 | 1455 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1456 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1457 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1458 | |
2d1fe073 | 1459 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1460 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1461 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1462 | } |
1463 | ||
1464 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1465 | enum pipe pipe) | |
1466 | { | |
291906f1 | 1467 | u32 val; |
291906f1 | 1468 | |
f0575e92 KP |
1469 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1470 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1471 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1472 | |
649636ef | 1473 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1474 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1475 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1476 | pipe_name(pipe)); |
291906f1 | 1477 | |
649636ef | 1478 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1479 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1480 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1481 | pipe_name(pipe)); |
291906f1 | 1482 | |
e2debe91 PZ |
1483 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1484 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1485 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1486 | } |
1487 | ||
cd2d34d9 VS |
1488 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1489 | const struct intel_crtc_state *pipe_config) | |
1490 | { | |
1491 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1492 | enum pipe pipe = crtc->pipe; | |
1493 | ||
1494 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1495 | POSTING_READ(DPLL(pipe)); | |
1496 | udelay(150); | |
1497 | ||
2c30b43b CW |
1498 | if (intel_wait_for_register(dev_priv, |
1499 | DPLL(pipe), | |
1500 | DPLL_LOCK_VLV, | |
1501 | DPLL_LOCK_VLV, | |
1502 | 1)) | |
cd2d34d9 VS |
1503 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1504 | } | |
1505 | ||
d288f65f | 1506 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1507 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1508 | { |
cd2d34d9 | 1509 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1510 | enum pipe pipe = crtc->pipe; |
87442f73 | 1511 | |
8bd3f301 | 1512 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1513 | |
87442f73 | 1514 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1515 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1516 | |
cd2d34d9 VS |
1517 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1518 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1519 | |
8bd3f301 VS |
1520 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1521 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1522 | } |
1523 | ||
cd2d34d9 VS |
1524 | |
1525 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1526 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1527 | { |
cd2d34d9 | 1528 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1529 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1530 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1531 | u32 tmp; |
1532 | ||
a580516d | 1533 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1534 | |
1535 | /* Enable back the 10bit clock to display controller */ | |
1536 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1537 | tmp |= DPIO_DCLKP_EN; | |
1538 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1539 | ||
54433e91 VS |
1540 | mutex_unlock(&dev_priv->sb_lock); |
1541 | ||
9d556c99 CML |
1542 | /* |
1543 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1544 | */ | |
1545 | udelay(1); | |
1546 | ||
1547 | /* Enable PLL */ | |
d288f65f | 1548 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1549 | |
1550 | /* Check PLL is locked */ | |
6b18826a CW |
1551 | if (intel_wait_for_register(dev_priv, |
1552 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1553 | 1)) | |
9d556c99 | 1554 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1555 | } |
1556 | ||
1557 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1558 | const struct intel_crtc_state *pipe_config) | |
1559 | { | |
1560 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1561 | enum pipe pipe = crtc->pipe; | |
1562 | ||
1563 | assert_pipe_disabled(dev_priv, pipe); | |
1564 | ||
1565 | /* PLL is protected by panel, make sure we can write it */ | |
1566 | assert_panel_unlocked(dev_priv, pipe); | |
1567 | ||
1568 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1569 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1570 | |
c231775c VS |
1571 | if (pipe != PIPE_A) { |
1572 | /* | |
1573 | * WaPixelRepeatModeFixForC0:chv | |
1574 | * | |
1575 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1576 | * the value from DPLLBMD to either pipe B or C. | |
1577 | */ | |
1578 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1579 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1580 | I915_WRITE(CBR4_VLV, 0); | |
1581 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1582 | ||
1583 | /* | |
1584 | * DPLLB VGA mode also seems to cause problems. | |
1585 | * We should always have it disabled. | |
1586 | */ | |
1587 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1588 | } else { | |
1589 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1590 | POSTING_READ(DPLL_MD(pipe)); | |
1591 | } | |
9d556c99 CML |
1592 | } |
1593 | ||
6315b5d3 | 1594 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1595 | { |
1596 | struct intel_crtc *crtc; | |
1597 | int count = 0; | |
1598 | ||
6315b5d3 | 1599 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1600 | count += crtc->base.state->active && |
2d84d2b3 VS |
1601 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1602 | } | |
1c4e0274 VS |
1603 | |
1604 | return count; | |
1605 | } | |
1606 | ||
66e3d5c0 | 1607 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1608 | { |
6315b5d3 | 1609 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1610 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1611 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1612 | |
66e3d5c0 | 1613 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1614 | |
63d7bbe9 | 1615 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1616 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1617 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1618 | |
1c4e0274 | 1619 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1620 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1621 | /* |
1622 | * It appears to be important that we don't enable this | |
1623 | * for the current pipe before otherwise configuring the | |
1624 | * PLL. No idea how this should be handled if multiple | |
1625 | * DVO outputs are enabled simultaneosly. | |
1626 | */ | |
1627 | dpll |= DPLL_DVO_2X_MODE; | |
1628 | I915_WRITE(DPLL(!crtc->pipe), | |
1629 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1630 | } | |
66e3d5c0 | 1631 | |
c2b63374 VS |
1632 | /* |
1633 | * Apparently we need to have VGA mode enabled prior to changing | |
1634 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1635 | * dividers, even though the register value does change. | |
1636 | */ | |
1637 | I915_WRITE(reg, 0); | |
1638 | ||
8e7a65aa VS |
1639 | I915_WRITE(reg, dpll); |
1640 | ||
66e3d5c0 DV |
1641 | /* Wait for the clocks to stabilize. */ |
1642 | POSTING_READ(reg); | |
1643 | udelay(150); | |
1644 | ||
6315b5d3 | 1645 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1646 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1647 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1648 | } else { |
1649 | /* The pixel multiplier can only be updated once the | |
1650 | * DPLL is enabled and the clocks are stable. | |
1651 | * | |
1652 | * So write it again. | |
1653 | */ | |
1654 | I915_WRITE(reg, dpll); | |
1655 | } | |
63d7bbe9 JB |
1656 | |
1657 | /* We do this three times for luck */ | |
66e3d5c0 | 1658 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1659 | POSTING_READ(reg); |
1660 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1661 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1662 | POSTING_READ(reg); |
1663 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1664 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1665 | POSTING_READ(reg); |
1666 | udelay(150); /* wait for warmup */ | |
1667 | } | |
1668 | ||
1669 | /** | |
50b44a44 | 1670 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1671 | * @dev_priv: i915 private structure |
1672 | * @pipe: pipe PLL to disable | |
1673 | * | |
1674 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1675 | * | |
1676 | * Note! This is for pre-ILK only. | |
1677 | */ | |
1c4e0274 | 1678 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1679 | { |
6315b5d3 | 1680 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1681 | enum pipe pipe = crtc->pipe; |
1682 | ||
1683 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1684 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1685 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1686 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1687 | I915_WRITE(DPLL(PIPE_B), |
1688 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1689 | I915_WRITE(DPLL(PIPE_A), | |
1690 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1691 | } | |
1692 | ||
b6b5d049 VS |
1693 | /* Don't disable pipe or pipe PLLs if needed */ |
1694 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1695 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1696 | return; |
1697 | ||
1698 | /* Make sure the pipe isn't still relying on us */ | |
1699 | assert_pipe_disabled(dev_priv, pipe); | |
1700 | ||
b8afb911 | 1701 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1702 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1703 | } |
1704 | ||
f6071166 JB |
1705 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1706 | { | |
b8afb911 | 1707 | u32 val; |
f6071166 JB |
1708 | |
1709 | /* Make sure the pipe isn't still relying on us */ | |
1710 | assert_pipe_disabled(dev_priv, pipe); | |
1711 | ||
03ed5cbf VS |
1712 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1713 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1714 | if (pipe != PIPE_A) | |
1715 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1716 | ||
f6071166 JB |
1717 | I915_WRITE(DPLL(pipe), val); |
1718 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1719 | } |
1720 | ||
1721 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1722 | { | |
d752048d | 1723 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1724 | u32 val; |
1725 | ||
a11b0703 VS |
1726 | /* Make sure the pipe isn't still relying on us */ |
1727 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1728 | |
60bfe44f VS |
1729 | val = DPLL_SSC_REF_CLK_CHV | |
1730 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1731 | if (pipe != PIPE_A) |
1732 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1733 | |
a11b0703 VS |
1734 | I915_WRITE(DPLL(pipe), val); |
1735 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1736 | |
a580516d | 1737 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1738 | |
1739 | /* Disable 10bit clock to display controller */ | |
1740 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1741 | val &= ~DPIO_DCLKP_EN; | |
1742 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1743 | ||
a580516d | 1744 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1745 | } |
1746 | ||
e4607fcf | 1747 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1748 | struct intel_digital_port *dport, |
1749 | unsigned int expected_mask) | |
89b667f8 JB |
1750 | { |
1751 | u32 port_mask; | |
f0f59a00 | 1752 | i915_reg_t dpll_reg; |
89b667f8 | 1753 | |
e4607fcf CML |
1754 | switch (dport->port) { |
1755 | case PORT_B: | |
89b667f8 | 1756 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1757 | dpll_reg = DPLL(0); |
e4607fcf CML |
1758 | break; |
1759 | case PORT_C: | |
89b667f8 | 1760 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1761 | dpll_reg = DPLL(0); |
9b6de0a1 | 1762 | expected_mask <<= 4; |
00fc31b7 CML |
1763 | break; |
1764 | case PORT_D: | |
1765 | port_mask = DPLL_PORTD_READY_MASK; | |
1766 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1767 | break; |
1768 | default: | |
1769 | BUG(); | |
1770 | } | |
89b667f8 | 1771 | |
370004d3 CW |
1772 | if (intel_wait_for_register(dev_priv, |
1773 | dpll_reg, port_mask, expected_mask, | |
1774 | 1000)) | |
9b6de0a1 VS |
1775 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1776 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1777 | } |
1778 | ||
b8a4f404 PZ |
1779 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1780 | enum pipe pipe) | |
040484af | 1781 | { |
98187836 VS |
1782 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1783 | pipe); | |
f0f59a00 VS |
1784 | i915_reg_t reg; |
1785 | uint32_t val, pipeconf_val; | |
040484af | 1786 | |
040484af | 1787 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1788 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1789 | |
1790 | /* FDI must be feeding us bits for PCH ports */ | |
1791 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1792 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1793 | ||
6e266956 | 1794 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1795 | /* Workaround: Set the timing override bit before enabling the |
1796 | * pch transcoder. */ | |
1797 | reg = TRANS_CHICKEN2(pipe); | |
1798 | val = I915_READ(reg); | |
1799 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1800 | I915_WRITE(reg, val); | |
59c859d6 | 1801 | } |
23670b32 | 1802 | |
ab9412ba | 1803 | reg = PCH_TRANSCONF(pipe); |
040484af | 1804 | val = I915_READ(reg); |
5f7f726d | 1805 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1806 | |
2d1fe073 | 1807 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1808 | /* |
c5de7c6f VS |
1809 | * Make the BPC in transcoder be consistent with |
1810 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1811 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1812 | */ |
dfd07d72 | 1813 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1814 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1815 | val |= PIPECONF_8BPC; |
1816 | else | |
1817 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1818 | } |
5f7f726d PZ |
1819 | |
1820 | val &= ~TRANS_INTERLACE_MASK; | |
1821 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1822 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1823 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1824 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1825 | else | |
1826 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1827 | else |
1828 | val |= TRANS_PROGRESSIVE; | |
1829 | ||
040484af | 1830 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1831 | if (intel_wait_for_register(dev_priv, |
1832 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1833 | 100)) | |
4bb6f1f3 | 1834 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1835 | } |
1836 | ||
8fb033d7 | 1837 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1838 | enum transcoder cpu_transcoder) |
040484af | 1839 | { |
8fb033d7 | 1840 | u32 val, pipeconf_val; |
8fb033d7 | 1841 | |
8fb033d7 | 1842 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1843 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1844 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1845 | |
223a6fdf | 1846 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1847 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1848 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1849 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1850 | |
25f3ef11 | 1851 | val = TRANS_ENABLE; |
937bb610 | 1852 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1853 | |
9a76b1c6 PZ |
1854 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1855 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1856 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1857 | else |
1858 | val |= TRANS_PROGRESSIVE; | |
1859 | ||
ab9412ba | 1860 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1861 | if (intel_wait_for_register(dev_priv, |
1862 | LPT_TRANSCONF, | |
1863 | TRANS_STATE_ENABLE, | |
1864 | TRANS_STATE_ENABLE, | |
1865 | 100)) | |
937bb610 | 1866 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1867 | } |
1868 | ||
b8a4f404 PZ |
1869 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1870 | enum pipe pipe) | |
040484af | 1871 | { |
f0f59a00 VS |
1872 | i915_reg_t reg; |
1873 | uint32_t val; | |
040484af JB |
1874 | |
1875 | /* FDI relies on the transcoder */ | |
1876 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1877 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1878 | ||
291906f1 JB |
1879 | /* Ports must be off as well */ |
1880 | assert_pch_ports_disabled(dev_priv, pipe); | |
1881 | ||
ab9412ba | 1882 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1883 | val = I915_READ(reg); |
1884 | val &= ~TRANS_ENABLE; | |
1885 | I915_WRITE(reg, val); | |
1886 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1887 | if (intel_wait_for_register(dev_priv, |
1888 | reg, TRANS_STATE_ENABLE, 0, | |
1889 | 50)) | |
4bb6f1f3 | 1890 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1891 | |
6e266956 | 1892 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1893 | /* Workaround: Clear the timing override chicken bit again. */ |
1894 | reg = TRANS_CHICKEN2(pipe); | |
1895 | val = I915_READ(reg); | |
1896 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1897 | I915_WRITE(reg, val); | |
1898 | } | |
040484af JB |
1899 | } |
1900 | ||
b7076546 | 1901 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1902 | { |
8fb033d7 PZ |
1903 | u32 val; |
1904 | ||
ab9412ba | 1905 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1906 | val &= ~TRANS_ENABLE; |
ab9412ba | 1907 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1908 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1909 | if (intel_wait_for_register(dev_priv, |
1910 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1911 | 50)) | |
8a52fd9f | 1912 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1913 | |
1914 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1915 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1916 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1917 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1918 | } |
1919 | ||
65f2130c VS |
1920 | enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
1921 | { | |
1922 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1923 | ||
1924 | WARN_ON(!crtc->config->has_pch_encoder); | |
1925 | ||
1926 | if (HAS_PCH_LPT(dev_priv)) | |
1927 | return TRANSCODER_A; | |
1928 | else | |
1929 | return (enum transcoder) crtc->pipe; | |
1930 | } | |
1931 | ||
b24e7179 | 1932 | /** |
309cfea8 | 1933 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1934 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1935 | * |
0372264a | 1936 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1937 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1938 | */ |
e1fdc473 | 1939 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1940 | { |
0372264a | 1941 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1942 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1943 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1944 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1945 | i915_reg_t reg; |
b24e7179 JB |
1946 | u32 val; |
1947 | ||
9e2ee2dd VS |
1948 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1949 | ||
58c6eaa2 | 1950 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1951 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1952 | assert_sprites_disabled(dev_priv, pipe); |
1953 | ||
b24e7179 JB |
1954 | /* |
1955 | * A pipe without a PLL won't actually be able to drive bits from | |
1956 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1957 | * need the check. | |
1958 | */ | |
09fa8bb9 | 1959 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1960 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1961 | assert_dsi_pll_enabled(dev_priv); |
1962 | else | |
1963 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1964 | } else { |
6e3c9717 | 1965 | if (crtc->config->has_pch_encoder) { |
040484af | 1966 | /* if driving the PCH, we need FDI enabled */ |
65f2130c VS |
1967 | assert_fdi_rx_pll_enabled(dev_priv, |
1968 | (enum pipe) intel_crtc_pch_transcoder(crtc)); | |
1a240d4d DV |
1969 | assert_fdi_tx_pll_enabled(dev_priv, |
1970 | (enum pipe) cpu_transcoder); | |
040484af JB |
1971 | } |
1972 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1973 | } | |
b24e7179 | 1974 | |
702e7a56 | 1975 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1976 | val = I915_READ(reg); |
7ad25d48 | 1977 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1978 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1979 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1980 | return; |
7ad25d48 | 1981 | } |
00d70b15 CW |
1982 | |
1983 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1984 | POSTING_READ(reg); |
b7792d8b VS |
1985 | |
1986 | /* | |
1987 | * Until the pipe starts DSL will read as 0, which would cause | |
1988 | * an apparent vblank timestamp jump, which messes up also the | |
1989 | * frame count when it's derived from the timestamps. So let's | |
1990 | * wait for the pipe to start properly before we call | |
1991 | * drm_crtc_vblank_on() | |
1992 | */ | |
1993 | if (dev->max_vblank_count == 0 && | |
1994 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1995 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1996 | } |
1997 | ||
1998 | /** | |
309cfea8 | 1999 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2000 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2001 | * |
575f7ab7 VS |
2002 | * Disable the pipe of @crtc, making sure that various hardware |
2003 | * specific requirements are met, if applicable, e.g. plane | |
2004 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2005 | * |
2006 | * Will wait until the pipe has shut down before returning. | |
2007 | */ | |
575f7ab7 | 2008 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2009 | { |
fac5e23e | 2010 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 2011 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2012 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2013 | i915_reg_t reg; |
b24e7179 JB |
2014 | u32 val; |
2015 | ||
9e2ee2dd VS |
2016 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2017 | ||
b24e7179 JB |
2018 | /* |
2019 | * Make sure planes won't keep trying to pump pixels to us, | |
2020 | * or we might hang the display. | |
2021 | */ | |
2022 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2023 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2024 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2025 | |
702e7a56 | 2026 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2027 | val = I915_READ(reg); |
00d70b15 CW |
2028 | if ((val & PIPECONF_ENABLE) == 0) |
2029 | return; | |
2030 | ||
67adc644 VS |
2031 | /* |
2032 | * Double wide has implications for planes | |
2033 | * so best keep it disabled when not needed. | |
2034 | */ | |
6e3c9717 | 2035 | if (crtc->config->double_wide) |
67adc644 VS |
2036 | val &= ~PIPECONF_DOUBLE_WIDE; |
2037 | ||
2038 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2039 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2040 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2041 | val &= ~PIPECONF_ENABLE; |
2042 | ||
2043 | I915_WRITE(reg, val); | |
2044 | if ((val & PIPECONF_ENABLE) == 0) | |
2045 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2046 | } |
2047 | ||
832be82f VS |
2048 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2049 | { | |
2050 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2051 | } | |
2052 | ||
27ba3910 VS |
2053 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2054 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2055 | { |
2056 | switch (fb_modifier) { | |
2057 | case DRM_FORMAT_MOD_NONE: | |
2058 | return cpp; | |
2059 | case I915_FORMAT_MOD_X_TILED: | |
2060 | if (IS_GEN2(dev_priv)) | |
2061 | return 128; | |
2062 | else | |
2063 | return 512; | |
2064 | case I915_FORMAT_MOD_Y_TILED: | |
2065 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2066 | return 128; | |
2067 | else | |
2068 | return 512; | |
2069 | case I915_FORMAT_MOD_Yf_TILED: | |
2070 | switch (cpp) { | |
2071 | case 1: | |
2072 | return 64; | |
2073 | case 2: | |
2074 | case 4: | |
2075 | return 128; | |
2076 | case 8: | |
2077 | case 16: | |
2078 | return 256; | |
2079 | default: | |
2080 | MISSING_CASE(cpp); | |
2081 | return cpp; | |
2082 | } | |
2083 | break; | |
2084 | default: | |
2085 | MISSING_CASE(fb_modifier); | |
2086 | return cpp; | |
2087 | } | |
2088 | } | |
2089 | ||
832be82f VS |
2090 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2091 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2092 | { |
832be82f VS |
2093 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2094 | return 1; | |
2095 | else | |
2096 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2097 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2098 | } |
2099 | ||
8d0deca8 VS |
2100 | /* Return the tile dimensions in pixel units */ |
2101 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2102 | unsigned int *tile_width, | |
2103 | unsigned int *tile_height, | |
2104 | uint64_t fb_modifier, | |
2105 | unsigned int cpp) | |
2106 | { | |
2107 | unsigned int tile_width_bytes = | |
2108 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2109 | ||
2110 | *tile_width = tile_width_bytes / cpp; | |
2111 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2112 | } | |
2113 | ||
6761dd31 TU |
2114 | unsigned int |
2115 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2116 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2117 | { |
832be82f VS |
2118 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2119 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2120 | ||
2121 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2122 | } |
2123 | ||
1663b9d6 VS |
2124 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2125 | { | |
2126 | unsigned int size = 0; | |
2127 | int i; | |
2128 | ||
2129 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2130 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2131 | ||
2132 | return size; | |
2133 | } | |
2134 | ||
75c82a53 | 2135 | static void |
3465c580 VS |
2136 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2137 | const struct drm_framebuffer *fb, | |
2138 | unsigned int rotation) | |
f64b98cd | 2139 | { |
bd2ef25d | 2140 | if (drm_rotation_90_or_270(rotation)) { |
2d7a215f VS |
2141 | *view = i915_ggtt_view_rotated; |
2142 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2143 | } else { | |
2144 | *view = i915_ggtt_view_normal; | |
2145 | } | |
2146 | } | |
50470bb0 | 2147 | |
603525d7 | 2148 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2149 | { |
2150 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2151 | return 256 * 1024; | |
985b8bb4 | 2152 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2153 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2154 | return 128 * 1024; |
2155 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2156 | return 4 * 1024; | |
2157 | else | |
44c5905e | 2158 | return 0; |
4e9a86b6 VS |
2159 | } |
2160 | ||
603525d7 VS |
2161 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2162 | uint64_t fb_modifier) | |
2163 | { | |
2164 | switch (fb_modifier) { | |
2165 | case DRM_FORMAT_MOD_NONE: | |
2166 | return intel_linear_alignment(dev_priv); | |
2167 | case I915_FORMAT_MOD_X_TILED: | |
2168 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2169 | return 256 * 1024; | |
2170 | return 0; | |
2171 | case I915_FORMAT_MOD_Y_TILED: | |
2172 | case I915_FORMAT_MOD_Yf_TILED: | |
2173 | return 1 * 1024 * 1024; | |
2174 | default: | |
2175 | MISSING_CASE(fb_modifier); | |
2176 | return 0; | |
2177 | } | |
2178 | } | |
2179 | ||
058d88c4 CW |
2180 | struct i915_vma * |
2181 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2182 | { |
850c4cdc | 2183 | struct drm_device *dev = fb->dev; |
fac5e23e | 2184 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2185 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2186 | struct i915_ggtt_view view; |
058d88c4 | 2187 | struct i915_vma *vma; |
6b95a207 | 2188 | u32 alignment; |
6b95a207 | 2189 | |
ebcdd39e MR |
2190 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2191 | ||
603525d7 | 2192 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2193 | |
3465c580 | 2194 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2195 | |
693db184 CW |
2196 | /* Note that the w/a also requires 64 PTE of padding following the |
2197 | * bo. We currently fill all unused PTE with the shadow page and so | |
2198 | * we should always have valid PTE following the scanout preventing | |
2199 | * the VT-d warning. | |
2200 | */ | |
48f112fe | 2201 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2202 | alignment = 256 * 1024; |
2203 | ||
d6dd6843 PZ |
2204 | /* |
2205 | * Global gtt pte registers are special registers which actually forward | |
2206 | * writes to a chunk of system memory. Which means that there is no risk | |
2207 | * that the register values disappear as soon as we call | |
2208 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2209 | * pin/unpin/fence and not more. | |
2210 | */ | |
2211 | intel_runtime_pm_get(dev_priv); | |
2212 | ||
058d88c4 | 2213 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2214 | if (IS_ERR(vma)) |
2215 | goto err; | |
6b95a207 | 2216 | |
05a20d09 | 2217 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2218 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2219 | * fence, whereas 965+ only requires a fence if using | |
2220 | * framebuffer compression. For simplicity, we always, when | |
2221 | * possible, install a fence as the cost is not that onerous. | |
2222 | * | |
2223 | * If we fail to fence the tiled scanout, then either the | |
2224 | * modeset will reject the change (which is highly unlikely as | |
2225 | * the affected systems, all but one, do not have unmappable | |
2226 | * space) or we will not be able to enable full powersaving | |
2227 | * techniques (also likely not to apply due to various limits | |
2228 | * FBC and the like impose on the size of the buffer, which | |
2229 | * presumably we violated anyway with this unmappable buffer). | |
2230 | * Anyway, it is presumably better to stumble onwards with | |
2231 | * something and try to run the system in a "less than optimal" | |
2232 | * mode that matches the user configuration. | |
2233 | */ | |
2234 | if (i915_vma_get_fence(vma) == 0) | |
2235 | i915_vma_pin_fence(vma); | |
9807216f | 2236 | } |
6b95a207 | 2237 | |
49ef5294 | 2238 | err: |
d6dd6843 | 2239 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2240 | return vma; |
6b95a207 KH |
2241 | } |
2242 | ||
fb4b8ce1 | 2243 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2244 | { |
82bc3b2d | 2245 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2246 | struct i915_ggtt_view view; |
058d88c4 | 2247 | struct i915_vma *vma; |
82bc3b2d | 2248 | |
ebcdd39e MR |
2249 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2250 | ||
3465c580 | 2251 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
05a20d09 | 2252 | vma = i915_gem_object_to_ggtt(obj, &view); |
f64b98cd | 2253 | |
49ef5294 | 2254 | i915_vma_unpin_fence(vma); |
058d88c4 | 2255 | i915_gem_object_unpin_from_display_plane(vma); |
1690e1eb CW |
2256 | } |
2257 | ||
ef78ec94 VS |
2258 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2259 | unsigned int rotation) | |
2260 | { | |
bd2ef25d | 2261 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2262 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2263 | else | |
2264 | return fb->pitches[plane]; | |
2265 | } | |
2266 | ||
6687c906 VS |
2267 | /* |
2268 | * Convert the x/y offsets into a linear offset. | |
2269 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2270 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2271 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2272 | */ | |
2273 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2274 | const struct intel_plane_state *state, |
2275 | int plane) | |
6687c906 | 2276 | { |
2949056c | 2277 | const struct drm_framebuffer *fb = state->base.fb; |
6687c906 VS |
2278 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
2279 | unsigned int pitch = fb->pitches[plane]; | |
2280 | ||
2281 | return y * pitch + x * cpp; | |
2282 | } | |
2283 | ||
2284 | /* | |
2285 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2286 | * specified plane src x/y offsets. The resulting x/y offsets | |
2287 | * specify the start of scanout from the beginning of the gtt mapping. | |
2288 | */ | |
2289 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2290 | const struct intel_plane_state *state, |
2291 | int plane) | |
6687c906 VS |
2292 | |
2293 | { | |
2949056c VS |
2294 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2295 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2296 | |
bd2ef25d | 2297 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2298 | *x += intel_fb->rotated[plane].x; |
2299 | *y += intel_fb->rotated[plane].y; | |
2300 | } else { | |
2301 | *x += intel_fb->normal[plane].x; | |
2302 | *y += intel_fb->normal[plane].y; | |
2303 | } | |
2304 | } | |
2305 | ||
29cf9491 | 2306 | /* |
29cf9491 VS |
2307 | * Input tile dimensions and pitch must already be |
2308 | * rotated to match x and y, and in pixel units. | |
2309 | */ | |
66a2d927 VS |
2310 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2311 | unsigned int tile_width, | |
2312 | unsigned int tile_height, | |
2313 | unsigned int tile_size, | |
2314 | unsigned int pitch_tiles, | |
2315 | u32 old_offset, | |
2316 | u32 new_offset) | |
29cf9491 | 2317 | { |
b9b24038 | 2318 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2319 | unsigned int tiles; |
2320 | ||
2321 | WARN_ON(old_offset & (tile_size - 1)); | |
2322 | WARN_ON(new_offset & (tile_size - 1)); | |
2323 | WARN_ON(new_offset > old_offset); | |
2324 | ||
2325 | tiles = (old_offset - new_offset) / tile_size; | |
2326 | ||
2327 | *y += tiles / pitch_tiles * tile_height; | |
2328 | *x += tiles % pitch_tiles * tile_width; | |
2329 | ||
b9b24038 VS |
2330 | /* minimize x in case it got needlessly big */ |
2331 | *y += *x / pitch_pixels * tile_height; | |
2332 | *x %= pitch_pixels; | |
2333 | ||
29cf9491 VS |
2334 | return new_offset; |
2335 | } | |
2336 | ||
66a2d927 VS |
2337 | /* |
2338 | * Adjust the tile offset by moving the difference into | |
2339 | * the x/y offsets. | |
2340 | */ | |
2341 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2342 | const struct intel_plane_state *state, int plane, | |
2343 | u32 old_offset, u32 new_offset) | |
2344 | { | |
2345 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2346 | const struct drm_framebuffer *fb = state->base.fb; | |
2347 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2348 | unsigned int rotation = state->base.rotation; | |
2349 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2350 | ||
2351 | WARN_ON(new_offset > old_offset); | |
2352 | ||
2353 | if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) { | |
2354 | unsigned int tile_size, tile_width, tile_height; | |
2355 | unsigned int pitch_tiles; | |
2356 | ||
2357 | tile_size = intel_tile_size(dev_priv); | |
2358 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2359 | fb->modifier[plane], cpp); | |
2360 | ||
bd2ef25d | 2361 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2362 | pitch_tiles = pitch / tile_height; |
2363 | swap(tile_width, tile_height); | |
2364 | } else { | |
2365 | pitch_tiles = pitch / (tile_width * cpp); | |
2366 | } | |
2367 | ||
2368 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2369 | tile_size, pitch_tiles, | |
2370 | old_offset, new_offset); | |
2371 | } else { | |
2372 | old_offset += *y * pitch + *x * cpp; | |
2373 | ||
2374 | *y = (old_offset - new_offset) / pitch; | |
2375 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2376 | } | |
2377 | ||
2378 | return new_offset; | |
2379 | } | |
2380 | ||
8d0deca8 VS |
2381 | /* |
2382 | * Computes the linear offset to the base tile and adjusts | |
2383 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2384 | * | |
2385 | * In the 90/270 rotated case, x and y are assumed | |
2386 | * to be already rotated to match the rotated GTT view, and | |
2387 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2388 | * |
2389 | * This function is used when computing the derived information | |
2390 | * under intel_framebuffer, so using any of that information | |
2391 | * here is not allowed. Anything under drm_framebuffer can be | |
2392 | * used. This is why the user has to pass in the pitch since it | |
2393 | * is specified in the rotated orientation. | |
8d0deca8 | 2394 | */ |
6687c906 VS |
2395 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2396 | int *x, int *y, | |
2397 | const struct drm_framebuffer *fb, int plane, | |
2398 | unsigned int pitch, | |
2399 | unsigned int rotation, | |
2400 | u32 alignment) | |
c2c75131 | 2401 | { |
4f2d9934 VS |
2402 | uint64_t fb_modifier = fb->modifier[plane]; |
2403 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
6687c906 | 2404 | u32 offset, offset_aligned; |
29cf9491 | 2405 | |
29cf9491 VS |
2406 | if (alignment) |
2407 | alignment--; | |
2408 | ||
b5c65338 | 2409 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2410 | unsigned int tile_size, tile_width, tile_height; |
2411 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2412 | |
d843310d | 2413 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2414 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2415 | fb_modifier, cpp); | |
2416 | ||
bd2ef25d | 2417 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2418 | pitch_tiles = pitch / tile_height; |
2419 | swap(tile_width, tile_height); | |
2420 | } else { | |
2421 | pitch_tiles = pitch / (tile_width * cpp); | |
2422 | } | |
d843310d VS |
2423 | |
2424 | tile_rows = *y / tile_height; | |
2425 | *y %= tile_height; | |
c2c75131 | 2426 | |
8d0deca8 VS |
2427 | tiles = *x / tile_width; |
2428 | *x %= tile_width; | |
bc752862 | 2429 | |
29cf9491 VS |
2430 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2431 | offset_aligned = offset & ~alignment; | |
bc752862 | 2432 | |
66a2d927 VS |
2433 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2434 | tile_size, pitch_tiles, | |
2435 | offset, offset_aligned); | |
29cf9491 | 2436 | } else { |
bc752862 | 2437 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2438 | offset_aligned = offset & ~alignment; |
2439 | ||
4e9a86b6 VS |
2440 | *y = (offset & alignment) / pitch; |
2441 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2442 | } |
29cf9491 VS |
2443 | |
2444 | return offset_aligned; | |
c2c75131 DV |
2445 | } |
2446 | ||
6687c906 | 2447 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2448 | const struct intel_plane_state *state, |
2449 | int plane) | |
6687c906 | 2450 | { |
2949056c VS |
2451 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
2452 | const struct drm_framebuffer *fb = state->base.fb; | |
2453 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2454 | int pitch = intel_fb_pitch(fb, plane, rotation); |
8d970654 VS |
2455 | u32 alignment; |
2456 | ||
2457 | /* AUX_DIST needs only 4K alignment */ | |
2458 | if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1) | |
2459 | alignment = 4096; | |
2460 | else | |
2461 | alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]); | |
6687c906 VS |
2462 | |
2463 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2464 | rotation, alignment); | |
2465 | } | |
2466 | ||
2467 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2468 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2469 | const struct drm_framebuffer *fb, int plane) | |
2470 | { | |
2471 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2472 | unsigned int pitch = fb->pitches[plane]; | |
2473 | u32 linear_offset = fb->offsets[plane]; | |
2474 | ||
2475 | *y = linear_offset / pitch; | |
2476 | *x = linear_offset % pitch / cpp; | |
2477 | } | |
2478 | ||
72618ebf VS |
2479 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2480 | { | |
2481 | switch (fb_modifier) { | |
2482 | case I915_FORMAT_MOD_X_TILED: | |
2483 | return I915_TILING_X; | |
2484 | case I915_FORMAT_MOD_Y_TILED: | |
2485 | return I915_TILING_Y; | |
2486 | default: | |
2487 | return I915_TILING_NONE; | |
2488 | } | |
2489 | } | |
2490 | ||
6687c906 VS |
2491 | static int |
2492 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2493 | struct drm_framebuffer *fb) | |
2494 | { | |
2495 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2496 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2497 | u32 gtt_offset_rotated = 0; | |
2498 | unsigned int max_size = 0; | |
2499 | uint32_t format = fb->pixel_format; | |
2500 | int i, num_planes = drm_format_num_planes(format); | |
2501 | unsigned int tile_size = intel_tile_size(dev_priv); | |
2502 | ||
2503 | for (i = 0; i < num_planes; i++) { | |
2504 | unsigned int width, height; | |
2505 | unsigned int cpp, size; | |
2506 | u32 offset; | |
2507 | int x, y; | |
2508 | ||
2509 | cpp = drm_format_plane_cpp(format, i); | |
2510 | width = drm_format_plane_width(fb->width, format, i); | |
2511 | height = drm_format_plane_height(fb->height, format, i); | |
2512 | ||
2513 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2514 | ||
60d5f2a4 VS |
2515 | /* |
2516 | * The fence (if used) is aligned to the start of the object | |
2517 | * so having the framebuffer wrap around across the edge of the | |
2518 | * fenced region doesn't really work. We have no API to configure | |
2519 | * the fence start offset within the object (nor could we probably | |
2520 | * on gen2/3). So it's just easier if we just require that the | |
2521 | * fb layout agrees with the fence layout. We already check that the | |
2522 | * fb stride matches the fence stride elsewhere. | |
2523 | */ | |
2524 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2525 | (x + width) * cpp > fb->pitches[i]) { | |
2526 | DRM_DEBUG("bad fb plane %d offset: 0x%x\n", | |
2527 | i, fb->offsets[i]); | |
2528 | return -EINVAL; | |
2529 | } | |
2530 | ||
6687c906 VS |
2531 | /* |
2532 | * First pixel of the framebuffer from | |
2533 | * the start of the normal gtt mapping. | |
2534 | */ | |
2535 | intel_fb->normal[i].x = x; | |
2536 | intel_fb->normal[i].y = y; | |
2537 | ||
2538 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
2539 | fb, 0, fb->pitches[i], | |
cc926387 | 2540 | DRM_ROTATE_0, tile_size); |
6687c906 VS |
2541 | offset /= tile_size; |
2542 | ||
2543 | if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) { | |
2544 | unsigned int tile_width, tile_height; | |
2545 | unsigned int pitch_tiles; | |
2546 | struct drm_rect r; | |
2547 | ||
2548 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2549 | fb->modifier[i], cpp); | |
2550 | ||
2551 | rot_info->plane[i].offset = offset; | |
2552 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2553 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2554 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2555 | ||
2556 | intel_fb->rotated[i].pitch = | |
2557 | rot_info->plane[i].height * tile_height; | |
2558 | ||
2559 | /* how many tiles does this plane need */ | |
2560 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2561 | /* | |
2562 | * If the plane isn't horizontally tile aligned, | |
2563 | * we need one more tile. | |
2564 | */ | |
2565 | if (x != 0) | |
2566 | size++; | |
2567 | ||
2568 | /* rotate the x/y offsets to match the GTT view */ | |
2569 | r.x1 = x; | |
2570 | r.y1 = y; | |
2571 | r.x2 = x + width; | |
2572 | r.y2 = y + height; | |
2573 | drm_rect_rotate(&r, | |
2574 | rot_info->plane[i].width * tile_width, | |
2575 | rot_info->plane[i].height * tile_height, | |
cc926387 | 2576 | DRM_ROTATE_270); |
6687c906 VS |
2577 | x = r.x1; |
2578 | y = r.y1; | |
2579 | ||
2580 | /* rotate the tile dimensions to match the GTT view */ | |
2581 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2582 | swap(tile_width, tile_height); | |
2583 | ||
2584 | /* | |
2585 | * We only keep the x/y offsets, so push all of the | |
2586 | * gtt offset into the x/y offsets. | |
2587 | */ | |
66a2d927 VS |
2588 | _intel_adjust_tile_offset(&x, &y, tile_size, |
2589 | tile_width, tile_height, pitch_tiles, | |
2590 | gtt_offset_rotated * tile_size, 0); | |
6687c906 VS |
2591 | |
2592 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2593 | ||
2594 | /* | |
2595 | * First pixel of the framebuffer from | |
2596 | * the start of the rotated gtt mapping. | |
2597 | */ | |
2598 | intel_fb->rotated[i].x = x; | |
2599 | intel_fb->rotated[i].y = y; | |
2600 | } else { | |
2601 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2602 | x * cpp, tile_size); | |
2603 | } | |
2604 | ||
2605 | /* how many tiles in total needed in the bo */ | |
2606 | max_size = max(max_size, offset + size); | |
2607 | } | |
2608 | ||
2609 | if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { | |
2610 | DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2611 | max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); | |
2612 | return -EINVAL; | |
2613 | } | |
2614 | ||
2615 | return 0; | |
2616 | } | |
2617 | ||
b35d63fa | 2618 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2619 | { |
2620 | switch (format) { | |
2621 | case DISPPLANE_8BPP: | |
2622 | return DRM_FORMAT_C8; | |
2623 | case DISPPLANE_BGRX555: | |
2624 | return DRM_FORMAT_XRGB1555; | |
2625 | case DISPPLANE_BGRX565: | |
2626 | return DRM_FORMAT_RGB565; | |
2627 | default: | |
2628 | case DISPPLANE_BGRX888: | |
2629 | return DRM_FORMAT_XRGB8888; | |
2630 | case DISPPLANE_RGBX888: | |
2631 | return DRM_FORMAT_XBGR8888; | |
2632 | case DISPPLANE_BGRX101010: | |
2633 | return DRM_FORMAT_XRGB2101010; | |
2634 | case DISPPLANE_RGBX101010: | |
2635 | return DRM_FORMAT_XBGR2101010; | |
2636 | } | |
2637 | } | |
2638 | ||
bc8d7dff DL |
2639 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2640 | { | |
2641 | switch (format) { | |
2642 | case PLANE_CTL_FORMAT_RGB_565: | |
2643 | return DRM_FORMAT_RGB565; | |
2644 | default: | |
2645 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2646 | if (rgb_order) { | |
2647 | if (alpha) | |
2648 | return DRM_FORMAT_ABGR8888; | |
2649 | else | |
2650 | return DRM_FORMAT_XBGR8888; | |
2651 | } else { | |
2652 | if (alpha) | |
2653 | return DRM_FORMAT_ARGB8888; | |
2654 | else | |
2655 | return DRM_FORMAT_XRGB8888; | |
2656 | } | |
2657 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2658 | if (rgb_order) | |
2659 | return DRM_FORMAT_XBGR2101010; | |
2660 | else | |
2661 | return DRM_FORMAT_XRGB2101010; | |
2662 | } | |
2663 | } | |
2664 | ||
5724dbd1 | 2665 | static bool |
f6936e29 DV |
2666 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2667 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2668 | { |
2669 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2670 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2671 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2672 | struct drm_i915_gem_object *obj = NULL; |
2673 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2674 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2675 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2676 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2677 | PAGE_SIZE); | |
2678 | ||
2679 | size_aligned -= base_aligned; | |
46f297fb | 2680 | |
ff2652ea CW |
2681 | if (plane_config->size == 0) |
2682 | return false; | |
2683 | ||
3badb49f PZ |
2684 | /* If the FB is too big, just don't use it since fbdev is not very |
2685 | * important and we should probably use that space with FBC or other | |
2686 | * features. */ | |
72e96d64 | 2687 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2688 | return false; |
2689 | ||
12c83d99 TU |
2690 | mutex_lock(&dev->struct_mutex); |
2691 | ||
187685cb | 2692 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2693 | base_aligned, |
2694 | base_aligned, | |
2695 | size_aligned); | |
12c83d99 TU |
2696 | if (!obj) { |
2697 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2698 | return false; |
12c83d99 | 2699 | } |
46f297fb | 2700 | |
3e510a8e CW |
2701 | if (plane_config->tiling == I915_TILING_X) |
2702 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2703 | |
6bf129df DL |
2704 | mode_cmd.pixel_format = fb->pixel_format; |
2705 | mode_cmd.width = fb->width; | |
2706 | mode_cmd.height = fb->height; | |
2707 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2708 | mode_cmd.modifier[0] = fb->modifier[0]; |
2709 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2710 | |
6bf129df | 2711 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2712 | &mode_cmd, obj)) { |
46f297fb JB |
2713 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2714 | goto out_unref_obj; | |
2715 | } | |
12c83d99 | 2716 | |
46f297fb | 2717 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2718 | |
f6936e29 | 2719 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2720 | return true; |
46f297fb JB |
2721 | |
2722 | out_unref_obj: | |
f8c417cd | 2723 | i915_gem_object_put(obj); |
46f297fb | 2724 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2725 | return false; |
2726 | } | |
2727 | ||
5a21b665 DV |
2728 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2729 | static void | |
2730 | update_state_fb(struct drm_plane *plane) | |
2731 | { | |
2732 | if (plane->fb == plane->state->fb) | |
2733 | return; | |
2734 | ||
2735 | if (plane->state->fb) | |
2736 | drm_framebuffer_unreference(plane->state->fb); | |
2737 | plane->state->fb = plane->fb; | |
2738 | if (plane->state->fb) | |
2739 | drm_framebuffer_reference(plane->state->fb); | |
2740 | } | |
2741 | ||
5724dbd1 | 2742 | static void |
f6936e29 DV |
2743 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2744 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2745 | { |
2746 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2747 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd JB |
2748 | struct drm_crtc *c; |
2749 | struct intel_crtc *i; | |
2ff8fde1 | 2750 | struct drm_i915_gem_object *obj; |
88595ac9 | 2751 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2752 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2753 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2754 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2755 | struct intel_plane_state *intel_state = |
2756 | to_intel_plane_state(plane_state); | |
88595ac9 | 2757 | struct drm_framebuffer *fb; |
484b41dd | 2758 | |
2d14030b | 2759 | if (!plane_config->fb) |
484b41dd JB |
2760 | return; |
2761 | ||
f6936e29 | 2762 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2763 | fb = &plane_config->fb->base; |
2764 | goto valid_fb; | |
f55548b5 | 2765 | } |
484b41dd | 2766 | |
2d14030b | 2767 | kfree(plane_config->fb); |
484b41dd JB |
2768 | |
2769 | /* | |
2770 | * Failed to alloc the obj, check to see if we should share | |
2771 | * an fb with another CRTC instead | |
2772 | */ | |
70e1e0ec | 2773 | for_each_crtc(dev, c) { |
484b41dd JB |
2774 | i = to_intel_crtc(c); |
2775 | ||
2776 | if (c == &intel_crtc->base) | |
2777 | continue; | |
2778 | ||
2ff8fde1 MR |
2779 | if (!i->active) |
2780 | continue; | |
2781 | ||
88595ac9 DV |
2782 | fb = c->primary->fb; |
2783 | if (!fb) | |
484b41dd JB |
2784 | continue; |
2785 | ||
88595ac9 | 2786 | obj = intel_fb_obj(fb); |
058d88c4 | 2787 | if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) { |
88595ac9 DV |
2788 | drm_framebuffer_reference(fb); |
2789 | goto valid_fb; | |
484b41dd JB |
2790 | } |
2791 | } | |
88595ac9 | 2792 | |
200757f5 MR |
2793 | /* |
2794 | * We've failed to reconstruct the BIOS FB. Current display state | |
2795 | * indicates that the primary plane is visible, but has a NULL FB, | |
2796 | * which will lead to problems later if we don't fix it up. The | |
2797 | * simplest solution is to just disable the primary plane now and | |
2798 | * pretend the BIOS never had it enabled. | |
2799 | */ | |
936e71e3 | 2800 | to_intel_plane_state(plane_state)->base.visible = false; |
200757f5 | 2801 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); |
2622a081 | 2802 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2803 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2804 | ||
88595ac9 DV |
2805 | return; |
2806 | ||
2807 | valid_fb: | |
f44e2659 VS |
2808 | plane_state->src_x = 0; |
2809 | plane_state->src_y = 0; | |
be5651f2 ML |
2810 | plane_state->src_w = fb->width << 16; |
2811 | plane_state->src_h = fb->height << 16; | |
2812 | ||
f44e2659 VS |
2813 | plane_state->crtc_x = 0; |
2814 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2815 | plane_state->crtc_w = fb->width; |
2816 | plane_state->crtc_h = fb->height; | |
2817 | ||
1638d30c RC |
2818 | intel_state->base.src = drm_plane_state_src(plane_state); |
2819 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2820 | |
88595ac9 | 2821 | obj = intel_fb_obj(fb); |
3e510a8e | 2822 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2823 | dev_priv->preserve_bios_swizzle = true; |
2824 | ||
be5651f2 ML |
2825 | drm_framebuffer_reference(fb); |
2826 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2827 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2828 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
faf5bf0a CW |
2829 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2830 | &obj->frontbuffer_bits); | |
46f297fb JB |
2831 | } |
2832 | ||
b63a16f6 VS |
2833 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2834 | unsigned int rotation) | |
2835 | { | |
2836 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2837 | ||
2838 | switch (fb->modifier[plane]) { | |
2839 | case DRM_FORMAT_MOD_NONE: | |
2840 | case I915_FORMAT_MOD_X_TILED: | |
2841 | switch (cpp) { | |
2842 | case 8: | |
2843 | return 4096; | |
2844 | case 4: | |
2845 | case 2: | |
2846 | case 1: | |
2847 | return 8192; | |
2848 | default: | |
2849 | MISSING_CASE(cpp); | |
2850 | break; | |
2851 | } | |
2852 | break; | |
2853 | case I915_FORMAT_MOD_Y_TILED: | |
2854 | case I915_FORMAT_MOD_Yf_TILED: | |
2855 | switch (cpp) { | |
2856 | case 8: | |
2857 | return 2048; | |
2858 | case 4: | |
2859 | return 4096; | |
2860 | case 2: | |
2861 | case 1: | |
2862 | return 8192; | |
2863 | default: | |
2864 | MISSING_CASE(cpp); | |
2865 | break; | |
2866 | } | |
2867 | break; | |
2868 | default: | |
2869 | MISSING_CASE(fb->modifier[plane]); | |
2870 | } | |
2871 | ||
2872 | return 2048; | |
2873 | } | |
2874 | ||
2875 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2876 | { | |
2877 | const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); | |
2878 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2879 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2880 | int x = plane_state->base.src.x1 >> 16; |
2881 | int y = plane_state->base.src.y1 >> 16; | |
2882 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2883 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2884 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2885 | int max_height = 4096; | |
8d970654 | 2886 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2887 | |
2888 | if (w > max_width || h > max_height) { | |
2889 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2890 | w, h, max_width, max_height); | |
2891 | return -EINVAL; | |
2892 | } | |
2893 | ||
2894 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2895 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
2896 | ||
2897 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); | |
2898 | ||
8d970654 VS |
2899 | /* |
2900 | * AUX surface offset is specified as the distance from the | |
2901 | * main surface offset, and it must be non-negative. Make | |
2902 | * sure that is what we will get. | |
2903 | */ | |
2904 | if (offset > aux_offset) | |
2905 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2906 | offset, aux_offset & ~(alignment - 1)); | |
2907 | ||
b63a16f6 VS |
2908 | /* |
2909 | * When using an X-tiled surface, the plane blows up | |
2910 | * if the x offset + width exceed the stride. | |
2911 | * | |
2912 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2913 | */ | |
2914 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) { | |
2915 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
2916 | ||
2917 | while ((x + w) * cpp > fb->pitches[0]) { | |
2918 | if (offset == 0) { | |
2919 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2920 | return -EINVAL; | |
2921 | } | |
2922 | ||
2923 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2924 | offset, offset - alignment); | |
2925 | } | |
2926 | } | |
2927 | ||
2928 | plane_state->main.offset = offset; | |
2929 | plane_state->main.x = x; | |
2930 | plane_state->main.y = y; | |
2931 | ||
2932 | return 0; | |
2933 | } | |
2934 | ||
8d970654 VS |
2935 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2936 | { | |
2937 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2938 | unsigned int rotation = plane_state->base.rotation; | |
2939 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2940 | int max_height = 4096; | |
cc926387 DV |
2941 | int x = plane_state->base.src.x1 >> 17; |
2942 | int y = plane_state->base.src.y1 >> 17; | |
2943 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2944 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2945 | u32 offset; |
2946 | ||
2947 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2948 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2949 | ||
2950 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2951 | if (w > max_width || h > max_height) { | |
2952 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2953 | w, h, max_width, max_height); | |
2954 | return -EINVAL; | |
2955 | } | |
2956 | ||
2957 | plane_state->aux.offset = offset; | |
2958 | plane_state->aux.x = x; | |
2959 | plane_state->aux.y = y; | |
2960 | ||
2961 | return 0; | |
2962 | } | |
2963 | ||
b63a16f6 VS |
2964 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2965 | { | |
2966 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2967 | unsigned int rotation = plane_state->base.rotation; | |
2968 | int ret; | |
2969 | ||
2970 | /* Rotate src coordinates to match rotated GTT view */ | |
bd2ef25d | 2971 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 2972 | drm_rect_rotate(&plane_state->base.src, |
da064b47 VS |
2973 | fb->width << 16, fb->height << 16, |
2974 | DRM_ROTATE_270); | |
b63a16f6 | 2975 | |
8d970654 VS |
2976 | /* |
2977 | * Handle the AUX surface first since | |
2978 | * the main surface setup depends on it. | |
2979 | */ | |
2980 | if (fb->pixel_format == DRM_FORMAT_NV12) { | |
2981 | ret = skl_check_nv12_aux_surface(plane_state); | |
2982 | if (ret) | |
2983 | return ret; | |
2984 | } else { | |
2985 | plane_state->aux.offset = ~0xfff; | |
2986 | plane_state->aux.x = 0; | |
2987 | plane_state->aux.y = 0; | |
2988 | } | |
2989 | ||
b63a16f6 VS |
2990 | ret = skl_check_main_surface(plane_state); |
2991 | if (ret) | |
2992 | return ret; | |
2993 | ||
2994 | return 0; | |
2995 | } | |
2996 | ||
a8d201af ML |
2997 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2998 | const struct intel_crtc_state *crtc_state, | |
2999 | const struct intel_plane_state *plane_state) | |
81255565 | 3000 | { |
6315b5d3 | 3001 | struct drm_i915_private *dev_priv = to_i915(primary->dev); |
a8d201af ML |
3002 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3003 | struct drm_framebuffer *fb = plane_state->base.fb; | |
81255565 | 3004 | int plane = intel_crtc->plane; |
54ea9da8 | 3005 | u32 linear_offset; |
81255565 | 3006 | u32 dspcntr; |
f0f59a00 | 3007 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 3008 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3009 | int x = plane_state->base.src.x1 >> 16; |
3010 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3011 | |
f45651ba VS |
3012 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
3013 | ||
fdd508a6 | 3014 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 3015 | |
6315b5d3 | 3016 | if (INTEL_GEN(dev_priv) < 4) { |
f45651ba VS |
3017 | if (intel_crtc->pipe == PIPE_B) |
3018 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
3019 | ||
3020 | /* pipesrc and dspsize control the size that is scaled from, | |
3021 | * which should always be the user's requested size. | |
3022 | */ | |
3023 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
3024 | ((crtc_state->pipe_src_h - 1) << 16) | |
3025 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 3026 | I915_WRITE(DSPPOS(plane), 0); |
920a14b2 | 3027 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
c14b0485 | 3028 | I915_WRITE(PRIMSIZE(plane), |
a8d201af ML |
3029 | ((crtc_state->pipe_src_h - 1) << 16) | |
3030 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
3031 | I915_WRITE(PRIMPOS(plane), 0); |
3032 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 3033 | } |
81255565 | 3034 | |
57779d06 VS |
3035 | switch (fb->pixel_format) { |
3036 | case DRM_FORMAT_C8: | |
81255565 JB |
3037 | dspcntr |= DISPPLANE_8BPP; |
3038 | break; | |
57779d06 | 3039 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3040 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3041 | break; |
57779d06 VS |
3042 | case DRM_FORMAT_RGB565: |
3043 | dspcntr |= DISPPLANE_BGRX565; | |
3044 | break; | |
3045 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3046 | dspcntr |= DISPPLANE_BGRX888; |
3047 | break; | |
3048 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3049 | dspcntr |= DISPPLANE_RGBX888; |
3050 | break; | |
3051 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3052 | dspcntr |= DISPPLANE_BGRX101010; |
3053 | break; | |
3054 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3055 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3056 | break; |
3057 | default: | |
baba133a | 3058 | BUG(); |
81255565 | 3059 | } |
57779d06 | 3060 | |
72618ebf VS |
3061 | if (INTEL_GEN(dev_priv) >= 4 && |
3062 | fb->modifier[0] == I915_FORMAT_MOD_X_TILED) | |
f45651ba | 3063 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3064 | |
df0cd455 VS |
3065 | if (rotation & DRM_ROTATE_180) |
3066 | dspcntr |= DISPPLANE_ROTATE_180; | |
3067 | ||
4ea7be2b VS |
3068 | if (rotation & DRM_REFLECT_X) |
3069 | dspcntr |= DISPPLANE_MIRROR; | |
3070 | ||
9beb5fea | 3071 | if (IS_G4X(dev_priv)) |
de1aa629 VS |
3072 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
3073 | ||
2949056c | 3074 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
81255565 | 3075 | |
6315b5d3 | 3076 | if (INTEL_GEN(dev_priv) >= 4) |
c2c75131 | 3077 | intel_crtc->dspaddr_offset = |
2949056c | 3078 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
e506a0c6 | 3079 | |
f22aa143 | 3080 | if (rotation & DRM_ROTATE_180) { |
df0cd455 VS |
3081 | x += crtc_state->pipe_src_w - 1; |
3082 | y += crtc_state->pipe_src_h - 1; | |
4ea7be2b VS |
3083 | } else if (rotation & DRM_REFLECT_X) { |
3084 | x += crtc_state->pipe_src_w - 1; | |
48404c1e SJ |
3085 | } |
3086 | ||
2949056c | 3087 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3088 | |
6315b5d3 | 3089 | if (INTEL_GEN(dev_priv) < 4) |
6687c906 VS |
3090 | intel_crtc->dspaddr_offset = linear_offset; |
3091 | ||
2db3366b PZ |
3092 | intel_crtc->adjusted_x = x; |
3093 | intel_crtc->adjusted_y = y; | |
3094 | ||
48404c1e SJ |
3095 | I915_WRITE(reg, dspcntr); |
3096 | ||
01f2c773 | 3097 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
6315b5d3 | 3098 | if (INTEL_GEN(dev_priv) >= 4) { |
85ba7b7d | 3099 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3100 | intel_fb_gtt_offset(fb, rotation) + |
3101 | intel_crtc->dspaddr_offset); | |
5eddb70b | 3102 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 3103 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
bfb81049 VS |
3104 | } else { |
3105 | I915_WRITE(DSPADDR(plane), | |
3106 | intel_fb_gtt_offset(fb, rotation) + | |
3107 | intel_crtc->dspaddr_offset); | |
3108 | } | |
5eddb70b | 3109 | POSTING_READ(reg); |
17638cd6 JB |
3110 | } |
3111 | ||
a8d201af ML |
3112 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
3113 | struct drm_crtc *crtc) | |
17638cd6 JB |
3114 | { |
3115 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3116 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 3117 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 3118 | int plane = intel_crtc->plane; |
f45651ba | 3119 | |
a8d201af ML |
3120 | I915_WRITE(DSPCNTR(plane), 0); |
3121 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 3122 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
3123 | else |
3124 | I915_WRITE(DSPADDR(plane), 0); | |
3125 | POSTING_READ(DSPCNTR(plane)); | |
3126 | } | |
c9ba6fad | 3127 | |
a8d201af ML |
3128 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
3129 | const struct intel_crtc_state *crtc_state, | |
3130 | const struct intel_plane_state *plane_state) | |
3131 | { | |
3132 | struct drm_device *dev = primary->dev; | |
fac5e23e | 3133 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3135 | struct drm_framebuffer *fb = plane_state->base.fb; | |
a8d201af | 3136 | int plane = intel_crtc->plane; |
54ea9da8 | 3137 | u32 linear_offset; |
a8d201af ML |
3138 | u32 dspcntr; |
3139 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 3140 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3141 | int x = plane_state->base.src.x1 >> 16; |
3142 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3143 | |
f45651ba | 3144 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 3145 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 3146 | |
8652744b | 3147 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f45651ba | 3148 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
17638cd6 | 3149 | |
57779d06 VS |
3150 | switch (fb->pixel_format) { |
3151 | case DRM_FORMAT_C8: | |
17638cd6 JB |
3152 | dspcntr |= DISPPLANE_8BPP; |
3153 | break; | |
57779d06 VS |
3154 | case DRM_FORMAT_RGB565: |
3155 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 3156 | break; |
57779d06 | 3157 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
3158 | dspcntr |= DISPPLANE_BGRX888; |
3159 | break; | |
3160 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3161 | dspcntr |= DISPPLANE_RGBX888; |
3162 | break; | |
3163 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3164 | dspcntr |= DISPPLANE_BGRX101010; |
3165 | break; | |
3166 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3167 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
3168 | break; |
3169 | default: | |
baba133a | 3170 | BUG(); |
17638cd6 JB |
3171 | } |
3172 | ||
72618ebf | 3173 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
17638cd6 | 3174 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 3175 | |
df0cd455 VS |
3176 | if (rotation & DRM_ROTATE_180) |
3177 | dspcntr |= DISPPLANE_ROTATE_180; | |
3178 | ||
8652744b | 3179 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) |
1f5d76db | 3180 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 3181 | |
2949056c | 3182 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
6687c906 | 3183 | |
c2c75131 | 3184 | intel_crtc->dspaddr_offset = |
2949056c | 3185 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
6687c906 | 3186 | |
df0cd455 VS |
3187 | /* HSW+ does this automagically in hardware */ |
3188 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) && | |
3189 | rotation & DRM_ROTATE_180) { | |
3190 | x += crtc_state->pipe_src_w - 1; | |
3191 | y += crtc_state->pipe_src_h - 1; | |
48404c1e SJ |
3192 | } |
3193 | ||
2949056c | 3194 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3195 | |
2db3366b PZ |
3196 | intel_crtc->adjusted_x = x; |
3197 | intel_crtc->adjusted_y = y; | |
3198 | ||
48404c1e | 3199 | I915_WRITE(reg, dspcntr); |
17638cd6 | 3200 | |
01f2c773 | 3201 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d | 3202 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3203 | intel_fb_gtt_offset(fb, rotation) + |
3204 | intel_crtc->dspaddr_offset); | |
8652744b | 3205 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
bc1c91eb DL |
3206 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
3207 | } else { | |
3208 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
3209 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
3210 | } | |
17638cd6 | 3211 | POSTING_READ(reg); |
17638cd6 JB |
3212 | } |
3213 | ||
7b49f948 VS |
3214 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
3215 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 3216 | { |
7b49f948 | 3217 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 3218 | return 64; |
7b49f948 VS |
3219 | } else { |
3220 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
3221 | ||
27ba3910 | 3222 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
3223 | } |
3224 | } | |
3225 | ||
6687c906 VS |
3226 | u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, |
3227 | unsigned int rotation) | |
121920fa | 3228 | { |
6687c906 | 3229 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ce7f1728 | 3230 | struct i915_ggtt_view view; |
058d88c4 | 3231 | struct i915_vma *vma; |
121920fa | 3232 | |
6687c906 | 3233 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
dedf278c | 3234 | |
058d88c4 CW |
3235 | vma = i915_gem_object_to_ggtt(obj, &view); |
3236 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", | |
3237 | view.type)) | |
3238 | return -1; | |
3239 | ||
bde13ebd | 3240 | return i915_ggtt_offset(vma); |
121920fa TU |
3241 | } |
3242 | ||
e435d6e5 ML |
3243 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3244 | { | |
3245 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3246 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3247 | |
3248 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3249 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3250 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3251 | } |
3252 | ||
a1b2278e CK |
3253 | /* |
3254 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3255 | */ | |
0583236e | 3256 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3257 | { |
a1b2278e CK |
3258 | struct intel_crtc_scaler_state *scaler_state; |
3259 | int i; | |
3260 | ||
a1b2278e CK |
3261 | scaler_state = &intel_crtc->config->scaler_state; |
3262 | ||
3263 | /* loop through and disable scalers that aren't in use */ | |
3264 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3265 | if (!scaler_state->scalers[i].in_use) |
3266 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3267 | } |
3268 | } | |
3269 | ||
d2196774 VS |
3270 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3271 | unsigned int rotation) | |
3272 | { | |
3273 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
3274 | u32 stride = intel_fb_pitch(fb, plane, rotation); | |
3275 | ||
3276 | /* | |
3277 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3278 | * linear buffers or in number of tiles for tiled buffers. | |
3279 | */ | |
bd2ef25d | 3280 | if (drm_rotation_90_or_270(rotation)) { |
d2196774 VS |
3281 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
3282 | ||
3283 | stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp); | |
3284 | } else { | |
3285 | stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
3286 | fb->pixel_format); | |
3287 | } | |
3288 | ||
3289 | return stride; | |
3290 | } | |
3291 | ||
6156a456 | 3292 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3293 | { |
6156a456 | 3294 | switch (pixel_format) { |
d161cf7a | 3295 | case DRM_FORMAT_C8: |
c34ce3d1 | 3296 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3297 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3298 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3299 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3300 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3301 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3302 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3303 | /* |
3304 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3305 | * to be already pre-multiplied. We need to add a knob (or a different | |
3306 | * DRM_FORMAT) for user-space to configure that. | |
3307 | */ | |
f75fb42a | 3308 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3309 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3310 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3311 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3312 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3313 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3314 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3315 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3316 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3317 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3318 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3319 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3320 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3321 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3322 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3323 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3324 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3325 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3326 | default: |
4249eeef | 3327 | MISSING_CASE(pixel_format); |
70d21f0e | 3328 | } |
8cfcba41 | 3329 | |
c34ce3d1 | 3330 | return 0; |
6156a456 | 3331 | } |
70d21f0e | 3332 | |
6156a456 CK |
3333 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3334 | { | |
6156a456 | 3335 | switch (fb_modifier) { |
30af77c4 | 3336 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3337 | break; |
30af77c4 | 3338 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3339 | return PLANE_CTL_TILED_X; |
b321803d | 3340 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3341 | return PLANE_CTL_TILED_Y; |
b321803d | 3342 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3343 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3344 | default: |
6156a456 | 3345 | MISSING_CASE(fb_modifier); |
70d21f0e | 3346 | } |
8cfcba41 | 3347 | |
c34ce3d1 | 3348 | return 0; |
6156a456 | 3349 | } |
70d21f0e | 3350 | |
6156a456 CK |
3351 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3352 | { | |
3b7a5119 | 3353 | switch (rotation) { |
31ad61e4 | 3354 | case DRM_ROTATE_0: |
6156a456 | 3355 | break; |
1e8df167 SJ |
3356 | /* |
3357 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3358 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3359 | */ | |
31ad61e4 | 3360 | case DRM_ROTATE_90: |
1e8df167 | 3361 | return PLANE_CTL_ROTATE_270; |
31ad61e4 | 3362 | case DRM_ROTATE_180: |
c34ce3d1 | 3363 | return PLANE_CTL_ROTATE_180; |
31ad61e4 | 3364 | case DRM_ROTATE_270: |
1e8df167 | 3365 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3366 | default: |
3367 | MISSING_CASE(rotation); | |
3368 | } | |
3369 | ||
c34ce3d1 | 3370 | return 0; |
6156a456 CK |
3371 | } |
3372 | ||
a8d201af ML |
3373 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3374 | const struct intel_crtc_state *crtc_state, | |
3375 | const struct intel_plane_state *plane_state) | |
6156a456 | 3376 | { |
a8d201af | 3377 | struct drm_device *dev = plane->dev; |
fac5e23e | 3378 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3379 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3380 | struct drm_framebuffer *fb = plane_state->base.fb; | |
8e816bb4 VS |
3381 | enum plane_id plane_id = to_intel_plane(plane)->id; |
3382 | enum pipe pipe = to_intel_plane(plane)->pipe; | |
d2196774 | 3383 | u32 plane_ctl; |
a8d201af | 3384 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3385 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3386 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3387 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3388 | int src_x = plane_state->main.x; |
3389 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3390 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3391 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3392 | int dst_x = plane_state->base.dst.x1; | |
3393 | int dst_y = plane_state->base.dst.y1; | |
3394 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3395 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
70d21f0e | 3396 | |
6156a456 CK |
3397 | plane_ctl = PLANE_CTL_ENABLE | |
3398 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3399 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3400 | ||
3401 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3402 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3403 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3404 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3405 | ||
6687c906 VS |
3406 | /* Sizes are 0 based */ |
3407 | src_w--; | |
3408 | src_h--; | |
3409 | dst_w--; | |
3410 | dst_h--; | |
3411 | ||
4c0b8a8b PZ |
3412 | intel_crtc->dspaddr_offset = surf_addr; |
3413 | ||
6687c906 VS |
3414 | intel_crtc->adjusted_x = src_x; |
3415 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3416 | |
8e816bb4 VS |
3417 | I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl); |
3418 | I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3419 | I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride); | |
3420 | I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
6156a456 CK |
3421 | |
3422 | if (scaler_id >= 0) { | |
3423 | uint32_t ps_ctrl = 0; | |
3424 | ||
3425 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3426 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 CK |
3427 | crtc_state->scaler_state.scalers[scaler_id].mode; |
3428 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3429 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3430 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3431 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
8e816bb4 | 3432 | I915_WRITE(PLANE_POS(pipe, plane_id), 0); |
6156a456 | 3433 | } else { |
8e816bb4 | 3434 | I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3435 | } |
3436 | ||
8e816bb4 | 3437 | I915_WRITE(PLANE_SURF(pipe, plane_id), |
6687c906 | 3438 | intel_fb_gtt_offset(fb, rotation) + surf_addr); |
70d21f0e | 3439 | |
8e816bb4 | 3440 | POSTING_READ(PLANE_SURF(pipe, plane_id)); |
70d21f0e DL |
3441 | } |
3442 | ||
a8d201af ML |
3443 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3444 | struct drm_crtc *crtc) | |
17638cd6 JB |
3445 | { |
3446 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3447 | struct drm_i915_private *dev_priv = to_i915(dev); |
8e816bb4 VS |
3448 | enum plane_id plane_id = to_intel_plane(primary)->id; |
3449 | enum pipe pipe = to_intel_plane(primary)->pipe; | |
62e0fb88 | 3450 | |
8e816bb4 VS |
3451 | I915_WRITE(PLANE_CTL(pipe, plane_id), 0); |
3452 | I915_WRITE(PLANE_SURF(pipe, plane_id), 0); | |
3453 | POSTING_READ(PLANE_SURF(pipe, plane_id)); | |
a8d201af | 3454 | } |
29b9bde6 | 3455 | |
a8d201af ML |
3456 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3457 | static int | |
3458 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3459 | int x, int y, enum mode_set_atomic state) | |
3460 | { | |
3461 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3462 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3463 | ||
3464 | return -ENODEV; | |
81255565 JB |
3465 | } |
3466 | ||
5a21b665 DV |
3467 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3468 | { | |
3469 | struct intel_crtc *crtc; | |
3470 | ||
91c8a326 | 3471 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3472 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3473 | } | |
3474 | ||
7514747d VS |
3475 | static void intel_update_primary_planes(struct drm_device *dev) |
3476 | { | |
7514747d | 3477 | struct drm_crtc *crtc; |
96a02917 | 3478 | |
70e1e0ec | 3479 | for_each_crtc(dev, crtc) { |
11c22da6 | 3480 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3481 | struct intel_plane_state *plane_state = |
3482 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3483 | |
936e71e3 | 3484 | if (plane_state->base.visible) |
a8d201af ML |
3485 | plane->update_plane(&plane->base, |
3486 | to_intel_crtc_state(crtc->state), | |
3487 | plane_state); | |
73974893 ML |
3488 | } |
3489 | } | |
3490 | ||
3491 | static int | |
3492 | __intel_display_resume(struct drm_device *dev, | |
3493 | struct drm_atomic_state *state) | |
3494 | { | |
3495 | struct drm_crtc_state *crtc_state; | |
3496 | struct drm_crtc *crtc; | |
3497 | int i, ret; | |
11c22da6 | 3498 | |
73974893 | 3499 | intel_modeset_setup_hw_state(dev); |
29b74b7f | 3500 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3501 | |
3502 | if (!state) | |
3503 | return 0; | |
3504 | ||
3505 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3506 | /* | |
3507 | * Force recalculation even if we restore | |
3508 | * current state. With fast modeset this may not result | |
3509 | * in a modeset when the state is compatible. | |
3510 | */ | |
3511 | crtc_state->mode_changed = true; | |
96a02917 | 3512 | } |
73974893 ML |
3513 | |
3514 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
3515 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
3516 | ||
3517 | ret = drm_atomic_commit(state); | |
3518 | ||
3519 | WARN_ON(ret == -EDEADLK); | |
3520 | return ret; | |
96a02917 VS |
3521 | } |
3522 | ||
4ac2ba2f VS |
3523 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3524 | { | |
ae98104b VS |
3525 | return intel_has_gpu_reset(dev_priv) && |
3526 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3527 | } |
3528 | ||
c033666a | 3529 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3530 | { |
73974893 ML |
3531 | struct drm_device *dev = &dev_priv->drm; |
3532 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3533 | struct drm_atomic_state *state; | |
3534 | int ret; | |
3535 | ||
73974893 ML |
3536 | /* |
3537 | * Need mode_config.mutex so that we don't | |
3538 | * trample ongoing ->detect() and whatnot. | |
3539 | */ | |
3540 | mutex_lock(&dev->mode_config.mutex); | |
3541 | drm_modeset_acquire_init(ctx, 0); | |
3542 | while (1) { | |
3543 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3544 | if (ret != -EDEADLK) | |
3545 | break; | |
3546 | ||
3547 | drm_modeset_backoff(ctx); | |
3548 | } | |
3549 | ||
3550 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3551 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3552 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3553 | return; |
3554 | ||
f98ce92f VS |
3555 | /* |
3556 | * Disabling the crtcs gracefully seems nicer. Also the | |
3557 | * g33 docs say we should at least disable all the planes. | |
3558 | */ | |
73974893 ML |
3559 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3560 | if (IS_ERR(state)) { | |
3561 | ret = PTR_ERR(state); | |
3562 | state = NULL; | |
3563 | DRM_ERROR("Duplicating state failed with %i\n", ret); | |
3564 | goto err; | |
3565 | } | |
3566 | ||
3567 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3568 | if (ret) { | |
3569 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
3570 | goto err; | |
3571 | } | |
3572 | ||
3573 | dev_priv->modeset_restore_state = state; | |
3574 | state->acquire_ctx = ctx; | |
3575 | return; | |
3576 | ||
3577 | err: | |
0853695c | 3578 | drm_atomic_state_put(state); |
7514747d VS |
3579 | } |
3580 | ||
c033666a | 3581 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3582 | { |
73974893 ML |
3583 | struct drm_device *dev = &dev_priv->drm; |
3584 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3585 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3586 | int ret; | |
3587 | ||
5a21b665 DV |
3588 | /* |
3589 | * Flips in the rings will be nuked by the reset, | |
3590 | * so complete all pending flips so that user space | |
3591 | * will get its events and not get stuck. | |
3592 | */ | |
3593 | intel_complete_page_flips(dev_priv); | |
3594 | ||
73974893 ML |
3595 | dev_priv->modeset_restore_state = NULL; |
3596 | ||
7514747d | 3597 | /* reset doesn't touch the display */ |
4ac2ba2f | 3598 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3599 | if (!state) { |
3600 | /* | |
3601 | * Flips in the rings have been nuked by the reset, | |
3602 | * so update the base address of all primary | |
3603 | * planes to the the last fb to make sure we're | |
3604 | * showing the correct fb after a reset. | |
3605 | * | |
3606 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3607 | * CS-based flips (which might get lost in gpu resets) any more. | |
3608 | */ | |
3609 | intel_update_primary_planes(dev); | |
3610 | } else { | |
3611 | ret = __intel_display_resume(dev, state); | |
3612 | if (ret) | |
3613 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3614 | } | |
73974893 ML |
3615 | } else { |
3616 | /* | |
3617 | * The display has been reset as well, | |
3618 | * so need a full re-initialization. | |
3619 | */ | |
3620 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3621 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3622 | |
51f59205 | 3623 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3624 | intel_modeset_init_hw(dev); |
7514747d | 3625 | |
73974893 ML |
3626 | spin_lock_irq(&dev_priv->irq_lock); |
3627 | if (dev_priv->display.hpd_irq_setup) | |
3628 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3629 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3630 | |
73974893 ML |
3631 | ret = __intel_display_resume(dev, state); |
3632 | if (ret) | |
3633 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3634 | |
73974893 ML |
3635 | intel_hpd_init(dev_priv); |
3636 | } | |
7514747d | 3637 | |
0853695c CW |
3638 | if (state) |
3639 | drm_atomic_state_put(state); | |
73974893 ML |
3640 | drm_modeset_drop_locks(ctx); |
3641 | drm_modeset_acquire_fini(ctx); | |
3642 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3643 | } |
3644 | ||
8af29b0c CW |
3645 | static bool abort_flip_on_reset(struct intel_crtc *crtc) |
3646 | { | |
3647 | struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; | |
3648 | ||
3649 | if (i915_reset_in_progress(error)) | |
3650 | return true; | |
3651 | ||
3652 | if (crtc->reset_count != i915_reset_count(error)) | |
3653 | return true; | |
3654 | ||
3655 | return false; | |
3656 | } | |
3657 | ||
7d5e3799 CW |
3658 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3659 | { | |
5a21b665 DV |
3660 | struct drm_device *dev = crtc->dev; |
3661 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5a21b665 DV |
3662 | bool pending; |
3663 | ||
8af29b0c | 3664 | if (abort_flip_on_reset(intel_crtc)) |
5a21b665 DV |
3665 | return false; |
3666 | ||
3667 | spin_lock_irq(&dev->event_lock); | |
3668 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3669 | spin_unlock_irq(&dev->event_lock); | |
3670 | ||
3671 | return pending; | |
7d5e3799 CW |
3672 | } |
3673 | ||
bfd16b2a ML |
3674 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3675 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3676 | { |
6315b5d3 | 3677 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3678 | struct intel_crtc_state *pipe_config = |
3679 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3680 | |
bfd16b2a ML |
3681 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3682 | crtc->base.mode = crtc->base.state->mode; | |
3683 | ||
3684 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3685 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3686 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3687 | |
3688 | /* | |
3689 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3690 | * that in compute_mode_changes we check the native mode (not the pfit | |
3691 | * mode) to see if we can flip rather than do a full mode set. In the | |
3692 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3693 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3694 | * sized surface. | |
e30e8f75 GP |
3695 | */ |
3696 | ||
e30e8f75 | 3697 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3698 | ((pipe_config->pipe_src_w - 1) << 16) | |
3699 | (pipe_config->pipe_src_h - 1)); | |
3700 | ||
3701 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3702 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3703 | skl_detach_scalers(crtc); |
3704 | ||
3705 | if (pipe_config->pch_pfit.enabled) | |
3706 | skylake_pfit_enable(crtc); | |
6e266956 | 3707 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3708 | if (pipe_config->pch_pfit.enabled) |
3709 | ironlake_pfit_enable(crtc); | |
3710 | else if (old_crtc_state->pch_pfit.enabled) | |
3711 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3712 | } |
e30e8f75 GP |
3713 | } |
3714 | ||
5e84e1a4 ZW |
3715 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3716 | { | |
3717 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3718 | struct drm_i915_private *dev_priv = to_i915(dev); |
5e84e1a4 ZW |
3719 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3720 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3721 | i915_reg_t reg; |
3722 | u32 temp; | |
5e84e1a4 ZW |
3723 | |
3724 | /* enable normal train */ | |
3725 | reg = FDI_TX_CTL(pipe); | |
3726 | temp = I915_READ(reg); | |
fd6b8f43 | 3727 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3728 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3729 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3730 | } else { |
3731 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3732 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3733 | } |
5e84e1a4 ZW |
3734 | I915_WRITE(reg, temp); |
3735 | ||
3736 | reg = FDI_RX_CTL(pipe); | |
3737 | temp = I915_READ(reg); | |
6e266956 | 3738 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3739 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3740 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3741 | } else { | |
3742 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3743 | temp |= FDI_LINK_TRAIN_NONE; | |
3744 | } | |
3745 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3746 | ||
3747 | /* wait one idle pattern time */ | |
3748 | POSTING_READ(reg); | |
3749 | udelay(1000); | |
357555c0 JB |
3750 | |
3751 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3752 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3753 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3754 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3755 | } |
3756 | ||
8db9d77b ZW |
3757 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3758 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3759 | { | |
3760 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3761 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3762 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3763 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3764 | i915_reg_t reg; |
3765 | u32 temp, tries; | |
8db9d77b | 3766 | |
1c8562f6 | 3767 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3768 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3769 | |
e1a44743 AJ |
3770 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3771 | for train result */ | |
5eddb70b CW |
3772 | reg = FDI_RX_IMR(pipe); |
3773 | temp = I915_READ(reg); | |
e1a44743 AJ |
3774 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3775 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3776 | I915_WRITE(reg, temp); |
3777 | I915_READ(reg); | |
e1a44743 AJ |
3778 | udelay(150); |
3779 | ||
8db9d77b | 3780 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3781 | reg = FDI_TX_CTL(pipe); |
3782 | temp = I915_READ(reg); | |
627eb5a3 | 3783 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3784 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3785 | temp &= ~FDI_LINK_TRAIN_NONE; |
3786 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3787 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3788 | |
5eddb70b CW |
3789 | reg = FDI_RX_CTL(pipe); |
3790 | temp = I915_READ(reg); | |
8db9d77b ZW |
3791 | temp &= ~FDI_LINK_TRAIN_NONE; |
3792 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3793 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3794 | ||
3795 | POSTING_READ(reg); | |
8db9d77b ZW |
3796 | udelay(150); |
3797 | ||
5b2adf89 | 3798 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3799 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3800 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3801 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3802 | |
5eddb70b | 3803 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3804 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3805 | temp = I915_READ(reg); |
8db9d77b ZW |
3806 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3807 | ||
3808 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3809 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3810 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3811 | break; |
3812 | } | |
8db9d77b | 3813 | } |
e1a44743 | 3814 | if (tries == 5) |
5eddb70b | 3815 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3816 | |
3817 | /* Train 2 */ | |
5eddb70b CW |
3818 | reg = FDI_TX_CTL(pipe); |
3819 | temp = I915_READ(reg); | |
8db9d77b ZW |
3820 | temp &= ~FDI_LINK_TRAIN_NONE; |
3821 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3822 | I915_WRITE(reg, temp); |
8db9d77b | 3823 | |
5eddb70b CW |
3824 | reg = FDI_RX_CTL(pipe); |
3825 | temp = I915_READ(reg); | |
8db9d77b ZW |
3826 | temp &= ~FDI_LINK_TRAIN_NONE; |
3827 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3828 | I915_WRITE(reg, temp); |
8db9d77b | 3829 | |
5eddb70b CW |
3830 | POSTING_READ(reg); |
3831 | udelay(150); | |
8db9d77b | 3832 | |
5eddb70b | 3833 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3834 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3835 | temp = I915_READ(reg); |
8db9d77b ZW |
3836 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3837 | ||
3838 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3839 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3840 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3841 | break; | |
3842 | } | |
8db9d77b | 3843 | } |
e1a44743 | 3844 | if (tries == 5) |
5eddb70b | 3845 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3846 | |
3847 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3848 | |
8db9d77b ZW |
3849 | } |
3850 | ||
0206e353 | 3851 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3852 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3853 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3854 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3855 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3856 | }; | |
3857 | ||
3858 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3859 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3860 | { | |
3861 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3862 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3863 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3864 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3865 | i915_reg_t reg; |
3866 | u32 temp, i, retry; | |
8db9d77b | 3867 | |
e1a44743 AJ |
3868 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3869 | for train result */ | |
5eddb70b CW |
3870 | reg = FDI_RX_IMR(pipe); |
3871 | temp = I915_READ(reg); | |
e1a44743 AJ |
3872 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3873 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3874 | I915_WRITE(reg, temp); |
3875 | ||
3876 | POSTING_READ(reg); | |
e1a44743 AJ |
3877 | udelay(150); |
3878 | ||
8db9d77b | 3879 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3880 | reg = FDI_TX_CTL(pipe); |
3881 | temp = I915_READ(reg); | |
627eb5a3 | 3882 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3883 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3884 | temp &= ~FDI_LINK_TRAIN_NONE; |
3885 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3886 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3887 | /* SNB-B */ | |
3888 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3889 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3890 | |
d74cf324 DV |
3891 | I915_WRITE(FDI_RX_MISC(pipe), |
3892 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3893 | ||
5eddb70b CW |
3894 | reg = FDI_RX_CTL(pipe); |
3895 | temp = I915_READ(reg); | |
6e266956 | 3896 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3897 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3898 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3899 | } else { | |
3900 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3901 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3902 | } | |
5eddb70b CW |
3903 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3904 | ||
3905 | POSTING_READ(reg); | |
8db9d77b ZW |
3906 | udelay(150); |
3907 | ||
0206e353 | 3908 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3909 | reg = FDI_TX_CTL(pipe); |
3910 | temp = I915_READ(reg); | |
8db9d77b ZW |
3911 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3912 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3913 | I915_WRITE(reg, temp); |
3914 | ||
3915 | POSTING_READ(reg); | |
8db9d77b ZW |
3916 | udelay(500); |
3917 | ||
fa37d39e SP |
3918 | for (retry = 0; retry < 5; retry++) { |
3919 | reg = FDI_RX_IIR(pipe); | |
3920 | temp = I915_READ(reg); | |
3921 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3922 | if (temp & FDI_RX_BIT_LOCK) { | |
3923 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3924 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3925 | break; | |
3926 | } | |
3927 | udelay(50); | |
8db9d77b | 3928 | } |
fa37d39e SP |
3929 | if (retry < 5) |
3930 | break; | |
8db9d77b ZW |
3931 | } |
3932 | if (i == 4) | |
5eddb70b | 3933 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3934 | |
3935 | /* Train 2 */ | |
5eddb70b CW |
3936 | reg = FDI_TX_CTL(pipe); |
3937 | temp = I915_READ(reg); | |
8db9d77b ZW |
3938 | temp &= ~FDI_LINK_TRAIN_NONE; |
3939 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3940 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3941 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3942 | /* SNB-B */ | |
3943 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3944 | } | |
5eddb70b | 3945 | I915_WRITE(reg, temp); |
8db9d77b | 3946 | |
5eddb70b CW |
3947 | reg = FDI_RX_CTL(pipe); |
3948 | temp = I915_READ(reg); | |
6e266956 | 3949 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3950 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3951 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3952 | } else { | |
3953 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3954 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3955 | } | |
5eddb70b CW |
3956 | I915_WRITE(reg, temp); |
3957 | ||
3958 | POSTING_READ(reg); | |
8db9d77b ZW |
3959 | udelay(150); |
3960 | ||
0206e353 | 3961 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3962 | reg = FDI_TX_CTL(pipe); |
3963 | temp = I915_READ(reg); | |
8db9d77b ZW |
3964 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3965 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3966 | I915_WRITE(reg, temp); |
3967 | ||
3968 | POSTING_READ(reg); | |
8db9d77b ZW |
3969 | udelay(500); |
3970 | ||
fa37d39e SP |
3971 | for (retry = 0; retry < 5; retry++) { |
3972 | reg = FDI_RX_IIR(pipe); | |
3973 | temp = I915_READ(reg); | |
3974 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3975 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3976 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3977 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3978 | break; | |
3979 | } | |
3980 | udelay(50); | |
8db9d77b | 3981 | } |
fa37d39e SP |
3982 | if (retry < 5) |
3983 | break; | |
8db9d77b ZW |
3984 | } |
3985 | if (i == 4) | |
5eddb70b | 3986 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3987 | |
3988 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3989 | } | |
3990 | ||
357555c0 JB |
3991 | /* Manual link training for Ivy Bridge A0 parts */ |
3992 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3993 | { | |
3994 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3995 | struct drm_i915_private *dev_priv = to_i915(dev); |
357555c0 JB |
3996 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3997 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3998 | i915_reg_t reg; |
3999 | u32 temp, i, j; | |
357555c0 JB |
4000 | |
4001 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
4002 | for train result */ | |
4003 | reg = FDI_RX_IMR(pipe); | |
4004 | temp = I915_READ(reg); | |
4005 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
4006 | temp &= ~FDI_RX_BIT_LOCK; | |
4007 | I915_WRITE(reg, temp); | |
4008 | ||
4009 | POSTING_READ(reg); | |
4010 | udelay(150); | |
4011 | ||
01a415fd DV |
4012 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
4013 | I915_READ(FDI_RX_IIR(pipe))); | |
4014 | ||
139ccd3f JB |
4015 | /* Try each vswing and preemphasis setting twice before moving on */ |
4016 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
4017 | /* disable first in case we need to retry */ | |
4018 | reg = FDI_TX_CTL(pipe); | |
4019 | temp = I915_READ(reg); | |
4020 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
4021 | temp &= ~FDI_TX_ENABLE; | |
4022 | I915_WRITE(reg, temp); | |
357555c0 | 4023 | |
139ccd3f JB |
4024 | reg = FDI_RX_CTL(pipe); |
4025 | temp = I915_READ(reg); | |
4026 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
4027 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4028 | temp &= ~FDI_RX_ENABLE; | |
4029 | I915_WRITE(reg, temp); | |
357555c0 | 4030 | |
139ccd3f | 4031 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
4032 | reg = FDI_TX_CTL(pipe); |
4033 | temp = I915_READ(reg); | |
139ccd3f | 4034 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 4035 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 4036 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 4037 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4038 | temp |= snb_b_fdi_train_param[j/2]; |
4039 | temp |= FDI_COMPOSITE_SYNC; | |
4040 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4041 | |
139ccd3f JB |
4042 | I915_WRITE(FDI_RX_MISC(pipe), |
4043 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4044 | |
139ccd3f | 4045 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4046 | temp = I915_READ(reg); |
139ccd3f JB |
4047 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4048 | temp |= FDI_COMPOSITE_SYNC; | |
4049 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4050 | |
139ccd3f JB |
4051 | POSTING_READ(reg); |
4052 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4053 | |
139ccd3f JB |
4054 | for (i = 0; i < 4; i++) { |
4055 | reg = FDI_RX_IIR(pipe); | |
4056 | temp = I915_READ(reg); | |
4057 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4058 | |
139ccd3f JB |
4059 | if (temp & FDI_RX_BIT_LOCK || |
4060 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4061 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4062 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4063 | i); | |
4064 | break; | |
4065 | } | |
4066 | udelay(1); /* should be 0.5us */ | |
4067 | } | |
4068 | if (i == 4) { | |
4069 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4070 | continue; | |
4071 | } | |
357555c0 | 4072 | |
139ccd3f | 4073 | /* Train 2 */ |
357555c0 JB |
4074 | reg = FDI_TX_CTL(pipe); |
4075 | temp = I915_READ(reg); | |
139ccd3f JB |
4076 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4077 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4078 | I915_WRITE(reg, temp); | |
4079 | ||
4080 | reg = FDI_RX_CTL(pipe); | |
4081 | temp = I915_READ(reg); | |
4082 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4083 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4084 | I915_WRITE(reg, temp); |
4085 | ||
4086 | POSTING_READ(reg); | |
139ccd3f | 4087 | udelay(2); /* should be 1.5us */ |
357555c0 | 4088 | |
139ccd3f JB |
4089 | for (i = 0; i < 4; i++) { |
4090 | reg = FDI_RX_IIR(pipe); | |
4091 | temp = I915_READ(reg); | |
4092 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4093 | |
139ccd3f JB |
4094 | if (temp & FDI_RX_SYMBOL_LOCK || |
4095 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4096 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4097 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4098 | i); | |
4099 | goto train_done; | |
4100 | } | |
4101 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4102 | } |
139ccd3f JB |
4103 | if (i == 4) |
4104 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4105 | } |
357555c0 | 4106 | |
139ccd3f | 4107 | train_done: |
357555c0 JB |
4108 | DRM_DEBUG_KMS("FDI train done.\n"); |
4109 | } | |
4110 | ||
88cefb6c | 4111 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4112 | { |
88cefb6c | 4113 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4114 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4115 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4116 | i915_reg_t reg; |
4117 | u32 temp; | |
c64e311e | 4118 | |
c98e9dcf | 4119 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4120 | reg = FDI_RX_CTL(pipe); |
4121 | temp = I915_READ(reg); | |
627eb5a3 | 4122 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4123 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4124 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4125 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4126 | ||
4127 | POSTING_READ(reg); | |
c98e9dcf JB |
4128 | udelay(200); |
4129 | ||
4130 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4131 | temp = I915_READ(reg); |
4132 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4133 | ||
4134 | POSTING_READ(reg); | |
c98e9dcf JB |
4135 | udelay(200); |
4136 | ||
20749730 PZ |
4137 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4138 | reg = FDI_TX_CTL(pipe); | |
4139 | temp = I915_READ(reg); | |
4140 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4141 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4142 | |
20749730 PZ |
4143 | POSTING_READ(reg); |
4144 | udelay(100); | |
6be4a607 | 4145 | } |
0e23b99d JB |
4146 | } |
4147 | ||
88cefb6c DV |
4148 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4149 | { | |
4150 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4151 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4152 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4153 | i915_reg_t reg; |
4154 | u32 temp; | |
88cefb6c DV |
4155 | |
4156 | /* Switch from PCDclk to Rawclk */ | |
4157 | reg = FDI_RX_CTL(pipe); | |
4158 | temp = I915_READ(reg); | |
4159 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4160 | ||
4161 | /* Disable CPU FDI TX PLL */ | |
4162 | reg = FDI_TX_CTL(pipe); | |
4163 | temp = I915_READ(reg); | |
4164 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4165 | ||
4166 | POSTING_READ(reg); | |
4167 | udelay(100); | |
4168 | ||
4169 | reg = FDI_RX_CTL(pipe); | |
4170 | temp = I915_READ(reg); | |
4171 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4172 | ||
4173 | /* Wait for the clocks to turn off. */ | |
4174 | POSTING_READ(reg); | |
4175 | udelay(100); | |
4176 | } | |
4177 | ||
0fc932b8 JB |
4178 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4179 | { | |
4180 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4181 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4182 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4183 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4184 | i915_reg_t reg; |
4185 | u32 temp; | |
0fc932b8 JB |
4186 | |
4187 | /* disable CPU FDI tx and PCH FDI rx */ | |
4188 | reg = FDI_TX_CTL(pipe); | |
4189 | temp = I915_READ(reg); | |
4190 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4191 | POSTING_READ(reg); | |
4192 | ||
4193 | reg = FDI_RX_CTL(pipe); | |
4194 | temp = I915_READ(reg); | |
4195 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4196 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4197 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4198 | ||
4199 | POSTING_READ(reg); | |
4200 | udelay(100); | |
4201 | ||
4202 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4203 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4204 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4205 | |
4206 | /* still set train pattern 1 */ | |
4207 | reg = FDI_TX_CTL(pipe); | |
4208 | temp = I915_READ(reg); | |
4209 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4210 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4211 | I915_WRITE(reg, temp); | |
4212 | ||
4213 | reg = FDI_RX_CTL(pipe); | |
4214 | temp = I915_READ(reg); | |
6e266956 | 4215 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4216 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4217 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4218 | } else { | |
4219 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4220 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4221 | } | |
4222 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4223 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4224 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4225 | I915_WRITE(reg, temp); |
4226 | ||
4227 | POSTING_READ(reg); | |
4228 | udelay(100); | |
4229 | } | |
4230 | ||
49d73912 | 4231 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 CW |
4232 | { |
4233 | struct intel_crtc *crtc; | |
4234 | ||
4235 | /* Note that we don't need to be called with mode_config.lock here | |
4236 | * as our list of CRTC objects is static for the lifetime of the | |
4237 | * device and so cannot disappear as we iterate. Similarly, we can | |
4238 | * happily treat the predicates as racy, atomic checks as userspace | |
4239 | * cannot claim and pin a new fb without at least acquring the | |
4240 | * struct_mutex and so serialising with us. | |
4241 | */ | |
49d73912 | 4242 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
5dce5b93 CW |
4243 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4244 | continue; | |
4245 | ||
5a21b665 | 4246 | if (crtc->flip_work) |
0f0f74bc | 4247 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
5dce5b93 CW |
4248 | |
4249 | return true; | |
4250 | } | |
4251 | ||
4252 | return false; | |
4253 | } | |
4254 | ||
5a21b665 | 4255 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4256 | { |
4257 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4258 | struct intel_flip_work *work = intel_crtc->flip_work; |
4259 | ||
4260 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4261 | |
4262 | if (work->event) | |
560ce1dc | 4263 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4264 | |
4265 | drm_crtc_vblank_put(&intel_crtc->base); | |
4266 | ||
5a21b665 | 4267 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 4268 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
4269 | |
4270 | trace_i915_flip_complete(intel_crtc->plane, | |
4271 | work->pending_flip_obj); | |
d6bbafa1 CW |
4272 | } |
4273 | ||
5008e874 | 4274 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4275 | { |
0f91128d | 4276 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4277 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4278 | long ret; |
e6c3a2a6 | 4279 | |
2c10d571 | 4280 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4281 | |
4282 | ret = wait_event_interruptible_timeout( | |
4283 | dev_priv->pending_flip_queue, | |
4284 | !intel_crtc_has_pending_flip(crtc), | |
4285 | 60*HZ); | |
4286 | ||
4287 | if (ret < 0) | |
4288 | return ret; | |
4289 | ||
5a21b665 DV |
4290 | if (ret == 0) { |
4291 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4292 | struct intel_flip_work *work; | |
4293 | ||
4294 | spin_lock_irq(&dev->event_lock); | |
4295 | work = intel_crtc->flip_work; | |
4296 | if (work && !is_mmio_work(work)) { | |
4297 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4298 | page_flip_completed(intel_crtc); | |
4299 | } | |
4300 | spin_unlock_irq(&dev->event_lock); | |
4301 | } | |
5bb61643 | 4302 | |
5008e874 | 4303 | return 0; |
e6c3a2a6 CW |
4304 | } |
4305 | ||
b7076546 | 4306 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4307 | { |
4308 | u32 temp; | |
4309 | ||
4310 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4311 | ||
4312 | mutex_lock(&dev_priv->sb_lock); | |
4313 | ||
4314 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4315 | temp |= SBI_SSCCTL_DISABLE; | |
4316 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4317 | ||
4318 | mutex_unlock(&dev_priv->sb_lock); | |
4319 | } | |
4320 | ||
e615efe4 ED |
4321 | /* Program iCLKIP clock to the desired frequency */ |
4322 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
4323 | { | |
64b46a06 | 4324 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 4325 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
4326 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4327 | u32 temp; | |
4328 | ||
060f02d8 | 4329 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4330 | |
64b46a06 VS |
4331 | /* The iCLK virtual clock root frequency is in MHz, |
4332 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4333 | * divisors, it is necessary to divide one by another, so we | |
4334 | * convert the virtual clock precision to KHz here for higher | |
4335 | * precision. | |
4336 | */ | |
4337 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4338 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4339 | u32 iclk_pi_range = 64; | |
64b46a06 | 4340 | u32 desired_divisor; |
e615efe4 | 4341 | |
64b46a06 VS |
4342 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4343 | clock << auxdiv); | |
4344 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4345 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4346 | |
64b46a06 VS |
4347 | /* |
4348 | * Near 20MHz is a corner case which is | |
4349 | * out of range for the 7-bit divisor | |
4350 | */ | |
4351 | if (divsel <= 0x7f) | |
4352 | break; | |
e615efe4 ED |
4353 | } |
4354 | ||
4355 | /* This should not happen with any sane values */ | |
4356 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4357 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4358 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4359 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4360 | ||
4361 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4362 | clock, |
e615efe4 ED |
4363 | auxdiv, |
4364 | divsel, | |
4365 | phasedir, | |
4366 | phaseinc); | |
4367 | ||
060f02d8 VS |
4368 | mutex_lock(&dev_priv->sb_lock); |
4369 | ||
e615efe4 | 4370 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4371 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4372 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4373 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4374 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4375 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4376 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4377 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4378 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4379 | |
4380 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4381 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4382 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4383 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4384 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4385 | |
4386 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4387 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4388 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4389 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4390 | |
060f02d8 VS |
4391 | mutex_unlock(&dev_priv->sb_lock); |
4392 | ||
e615efe4 ED |
4393 | /* Wait for initialization time */ |
4394 | udelay(24); | |
4395 | ||
4396 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4397 | } | |
4398 | ||
8802e5b6 VS |
4399 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4400 | { | |
4401 | u32 divsel, phaseinc, auxdiv; | |
4402 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4403 | u32 iclk_pi_range = 64; | |
4404 | u32 desired_divisor; | |
4405 | u32 temp; | |
4406 | ||
4407 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4408 | return 0; | |
4409 | ||
4410 | mutex_lock(&dev_priv->sb_lock); | |
4411 | ||
4412 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4413 | if (temp & SBI_SSCCTL_DISABLE) { | |
4414 | mutex_unlock(&dev_priv->sb_lock); | |
4415 | return 0; | |
4416 | } | |
4417 | ||
4418 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4419 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4420 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4421 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4422 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4423 | ||
4424 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4425 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4426 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4427 | ||
4428 | mutex_unlock(&dev_priv->sb_lock); | |
4429 | ||
4430 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4431 | ||
4432 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4433 | desired_divisor << auxdiv); | |
4434 | } | |
4435 | ||
275f01b2 DV |
4436 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4437 | enum pipe pch_transcoder) | |
4438 | { | |
4439 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4440 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4441 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4442 | |
4443 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4444 | I915_READ(HTOTAL(cpu_transcoder))); | |
4445 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4446 | I915_READ(HBLANK(cpu_transcoder))); | |
4447 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4448 | I915_READ(HSYNC(cpu_transcoder))); | |
4449 | ||
4450 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4451 | I915_READ(VTOTAL(cpu_transcoder))); | |
4452 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4453 | I915_READ(VBLANK(cpu_transcoder))); | |
4454 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4455 | I915_READ(VSYNC(cpu_transcoder))); | |
4456 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4457 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4458 | } | |
4459 | ||
003632d9 | 4460 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4461 | { |
fac5e23e | 4462 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4463 | uint32_t temp; |
4464 | ||
4465 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4466 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4467 | return; |
4468 | ||
4469 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4470 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4471 | ||
003632d9 ACO |
4472 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4473 | if (enable) | |
4474 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4475 | ||
4476 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4477 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4478 | POSTING_READ(SOUTH_CHICKEN1); | |
4479 | } | |
4480 | ||
4481 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4482 | { | |
4483 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4484 | |
4485 | switch (intel_crtc->pipe) { | |
4486 | case PIPE_A: | |
4487 | break; | |
4488 | case PIPE_B: | |
6e3c9717 | 4489 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4490 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4491 | else |
003632d9 | 4492 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4493 | |
4494 | break; | |
4495 | case PIPE_C: | |
003632d9 | 4496 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4497 | |
4498 | break; | |
4499 | default: | |
4500 | BUG(); | |
4501 | } | |
4502 | } | |
4503 | ||
c48b5305 VS |
4504 | /* Return which DP Port should be selected for Transcoder DP control */ |
4505 | static enum port | |
4506 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4507 | { | |
4508 | struct drm_device *dev = crtc->dev; | |
4509 | struct intel_encoder *encoder; | |
4510 | ||
4511 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
cca0502b | 4512 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4513 | encoder->type == INTEL_OUTPUT_EDP) |
4514 | return enc_to_dig_port(&encoder->base)->port; | |
4515 | } | |
4516 | ||
4517 | return -1; | |
4518 | } | |
4519 | ||
f67a559d JB |
4520 | /* |
4521 | * Enable PCH resources required for PCH ports: | |
4522 | * - PCH PLLs | |
4523 | * - FDI training & RX/TX | |
4524 | * - update transcoder timings | |
4525 | * - DP transcoding bits | |
4526 | * - transcoder | |
4527 | */ | |
4528 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4529 | { |
4530 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4531 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e23b99d JB |
4532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4533 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4534 | u32 temp; |
2c07245f | 4535 | |
ab9412ba | 4536 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4537 | |
fd6b8f43 | 4538 | if (IS_IVYBRIDGE(dev_priv)) |
1fbc0d78 DV |
4539 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
4540 | ||
cd986abb DV |
4541 | /* Write the TU size bits before fdi link training, so that error |
4542 | * detection works. */ | |
4543 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4544 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4545 | ||
c98e9dcf | 4546 | /* For PCH output, training FDI link */ |
674cf967 | 4547 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4548 | |
3ad8a208 DV |
4549 | /* We need to program the right clock selection before writing the pixel |
4550 | * mutliplier into the DPLL. */ | |
6e266956 | 4551 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4552 | u32 sel; |
4b645f14 | 4553 | |
c98e9dcf | 4554 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4555 | temp |= TRANS_DPLL_ENABLE(pipe); |
4556 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4557 | if (intel_crtc->config->shared_dpll == |
4558 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4559 | temp |= sel; |
4560 | else | |
4561 | temp &= ~sel; | |
c98e9dcf | 4562 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4563 | } |
5eddb70b | 4564 | |
3ad8a208 DV |
4565 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4566 | * transcoder, and we actually should do this to not upset any PCH | |
4567 | * transcoder that already use the clock when we share it. | |
4568 | * | |
4569 | * Note that enable_shared_dpll tries to do the right thing, but | |
4570 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4571 | * the right LVDS enable sequence. */ | |
85b3894f | 4572 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4573 | |
d9b6cb56 JB |
4574 | /* set transcoder timing, panel must allow it */ |
4575 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4576 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4577 | |
303b81e0 | 4578 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4579 | |
c98e9dcf | 4580 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 TU |
4581 | if (HAS_PCH_CPT(dev_priv) && |
4582 | intel_crtc_has_dp_encoder(intel_crtc->config)) { | |
9c4edaee VS |
4583 | const struct drm_display_mode *adjusted_mode = |
4584 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4585 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4586 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4587 | temp = I915_READ(reg); |
4588 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4589 | TRANS_DP_SYNC_MASK | |
4590 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4591 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4592 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4593 | |
9c4edaee | 4594 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4595 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4596 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4597 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4598 | |
4599 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4600 | case PORT_B: |
5eddb70b | 4601 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4602 | break; |
c48b5305 | 4603 | case PORT_C: |
5eddb70b | 4604 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4605 | break; |
c48b5305 | 4606 | case PORT_D: |
5eddb70b | 4607 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4608 | break; |
4609 | default: | |
e95d41e1 | 4610 | BUG(); |
32f9d658 | 4611 | } |
2c07245f | 4612 | |
5eddb70b | 4613 | I915_WRITE(reg, temp); |
6be4a607 | 4614 | } |
b52eb4dc | 4615 | |
b8a4f404 | 4616 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4617 | } |
4618 | ||
1507e5bd PZ |
4619 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4620 | { | |
4621 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4622 | struct drm_i915_private *dev_priv = to_i915(dev); |
1507e5bd | 4623 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 4624 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4625 | |
ab9412ba | 4626 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4627 | |
8c52b5e8 | 4628 | lpt_program_iclkip(crtc); |
1507e5bd | 4629 | |
0540e488 | 4630 | /* Set transcoder timing. */ |
275f01b2 | 4631 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4632 | |
937bb610 | 4633 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4634 | } |
4635 | ||
a1520318 | 4636 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4637 | { |
fac5e23e | 4638 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4639 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4640 | u32 temp; |
4641 | ||
4642 | temp = I915_READ(dslreg); | |
4643 | udelay(500); | |
4644 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4645 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4646 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4647 | } |
4648 | } | |
4649 | ||
86adf9d7 ML |
4650 | static int |
4651 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4652 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4653 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4654 | { |
86adf9d7 ML |
4655 | struct intel_crtc_scaler_state *scaler_state = |
4656 | &crtc_state->scaler_state; | |
4657 | struct intel_crtc *intel_crtc = | |
4658 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4659 | int need_scaling; |
6156a456 | 4660 | |
bd2ef25d | 4661 | need_scaling = drm_rotation_90_or_270(rotation) ? |
6156a456 CK |
4662 | (src_h != dst_w || src_w != dst_h): |
4663 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4664 | |
4665 | /* | |
4666 | * if plane is being disabled or scaler is no more required or force detach | |
4667 | * - free scaler binded to this plane/crtc | |
4668 | * - in order to do this, update crtc->scaler_usage | |
4669 | * | |
4670 | * Here scaler state in crtc_state is set free so that | |
4671 | * scaler can be assigned to other user. Actual register | |
4672 | * update to free the scaler is done in plane/panel-fit programming. | |
4673 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4674 | */ | |
86adf9d7 | 4675 | if (force_detach || !need_scaling) { |
a1b2278e | 4676 | if (*scaler_id >= 0) { |
86adf9d7 | 4677 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4678 | scaler_state->scalers[*scaler_id].in_use = 0; |
4679 | ||
86adf9d7 ML |
4680 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4681 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4682 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4683 | scaler_state->scaler_users); |
4684 | *scaler_id = -1; | |
4685 | } | |
4686 | return 0; | |
4687 | } | |
4688 | ||
4689 | /* range checks */ | |
4690 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4691 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4692 | ||
4693 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4694 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4695 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4696 | "size is out of scaler range\n", |
86adf9d7 | 4697 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4698 | return -EINVAL; |
4699 | } | |
4700 | ||
86adf9d7 ML |
4701 | /* mark this plane as a scaler user in crtc_state */ |
4702 | scaler_state->scaler_users |= (1 << scaler_user); | |
4703 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4704 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4705 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4706 | scaler_state->scaler_users); | |
4707 | ||
4708 | return 0; | |
4709 | } | |
4710 | ||
4711 | /** | |
4712 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4713 | * | |
4714 | * @state: crtc's scaler state | |
86adf9d7 ML |
4715 | * |
4716 | * Return | |
4717 | * 0 - scaler_usage updated successfully | |
4718 | * error - requested scaling cannot be supported or other error condition | |
4719 | */ | |
e435d6e5 | 4720 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4721 | { |
7c5f93b0 | 4722 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4723 | |
e435d6e5 | 4724 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
31ad61e4 | 4725 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
86adf9d7 | 4726 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4727 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4728 | } |
4729 | ||
4730 | /** | |
4731 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4732 | * | |
4733 | * @state: crtc's scaler state | |
86adf9d7 ML |
4734 | * @plane_state: atomic plane state to update |
4735 | * | |
4736 | * Return | |
4737 | * 0 - scaler_usage updated successfully | |
4738 | * error - requested scaling cannot be supported or other error condition | |
4739 | */ | |
da20eabd ML |
4740 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4741 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4742 | { |
4743 | ||
da20eabd ML |
4744 | struct intel_plane *intel_plane = |
4745 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4746 | struct drm_framebuffer *fb = plane_state->base.fb; |
4747 | int ret; | |
4748 | ||
936e71e3 | 4749 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4750 | |
86adf9d7 ML |
4751 | ret = skl_update_scaler(crtc_state, force_detach, |
4752 | drm_plane_index(&intel_plane->base), | |
4753 | &plane_state->scaler_id, | |
4754 | plane_state->base.rotation, | |
936e71e3 VS |
4755 | drm_rect_width(&plane_state->base.src) >> 16, |
4756 | drm_rect_height(&plane_state->base.src) >> 16, | |
4757 | drm_rect_width(&plane_state->base.dst), | |
4758 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4759 | |
4760 | if (ret || plane_state->scaler_id < 0) | |
4761 | return ret; | |
4762 | ||
a1b2278e | 4763 | /* check colorkey */ |
818ed961 | 4764 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4765 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4766 | intel_plane->base.base.id, | |
4767 | intel_plane->base.name); | |
a1b2278e CK |
4768 | return -EINVAL; |
4769 | } | |
4770 | ||
4771 | /* Check src format */ | |
86adf9d7 ML |
4772 | switch (fb->pixel_format) { |
4773 | case DRM_FORMAT_RGB565: | |
4774 | case DRM_FORMAT_XBGR8888: | |
4775 | case DRM_FORMAT_XRGB8888: | |
4776 | case DRM_FORMAT_ABGR8888: | |
4777 | case DRM_FORMAT_ARGB8888: | |
4778 | case DRM_FORMAT_XRGB2101010: | |
4779 | case DRM_FORMAT_XBGR2101010: | |
4780 | case DRM_FORMAT_YUYV: | |
4781 | case DRM_FORMAT_YVYU: | |
4782 | case DRM_FORMAT_UYVY: | |
4783 | case DRM_FORMAT_VYUY: | |
4784 | break; | |
4785 | default: | |
72660ce0 VS |
4786 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4787 | intel_plane->base.base.id, intel_plane->base.name, | |
4788 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4789 | return -EINVAL; |
a1b2278e CK |
4790 | } |
4791 | ||
a1b2278e CK |
4792 | return 0; |
4793 | } | |
4794 | ||
e435d6e5 ML |
4795 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4796 | { | |
4797 | int i; | |
4798 | ||
4799 | for (i = 0; i < crtc->num_scalers; i++) | |
4800 | skl_detach_scaler(crtc, i); | |
4801 | } | |
4802 | ||
4803 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4804 | { |
4805 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4806 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4807 | int pipe = crtc->pipe; |
a1b2278e CK |
4808 | struct intel_crtc_scaler_state *scaler_state = |
4809 | &crtc->config->scaler_state; | |
4810 | ||
4811 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4812 | ||
6e3c9717 | 4813 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4814 | int id; |
4815 | ||
4816 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4817 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4818 | return; | |
4819 | } | |
4820 | ||
4821 | id = scaler_state->scaler_id; | |
4822 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4823 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4824 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4825 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4826 | ||
4827 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4828 | } |
4829 | } | |
4830 | ||
b074cec8 JB |
4831 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4832 | { | |
4833 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4834 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4835 | int pipe = crtc->pipe; |
4836 | ||
6e3c9717 | 4837 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4838 | /* Force use of hard-coded filter coefficients |
4839 | * as some pre-programmed values are broken, | |
4840 | * e.g. x201. | |
4841 | */ | |
fd6b8f43 | 4842 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4843 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4844 | PF_PIPE_SEL_IVB(pipe)); | |
4845 | else | |
4846 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4847 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4848 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4849 | } |
4850 | } | |
4851 | ||
20bc8673 | 4852 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4853 | { |
cea165c3 | 4854 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4855 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4856 | |
6e3c9717 | 4857 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4858 | return; |
4859 | ||
307e4498 ML |
4860 | /* |
4861 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4862 | * This function is called from post_plane_update, which is run after | |
4863 | * a vblank wait. | |
4864 | */ | |
cea165c3 | 4865 | |
d77e4531 | 4866 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4867 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4868 | mutex_lock(&dev_priv->rps.hw_lock); |
4869 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4870 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4871 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4872 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4873 | * mailbox." Moreover, the mailbox may return a bogus state, |
4874 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4875 | */ |
4876 | } else { | |
4877 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4878 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4879 | * is essentially intel_wait_for_vblank. If we don't have this | |
4880 | * and don't wait for vblanks until the end of crtc_enable, then | |
4881 | * the HW state readout code will complain that the expected | |
4882 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4883 | if (intel_wait_for_register(dev_priv, |
4884 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4885 | 50)) | |
2a114cc1 BW |
4886 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4887 | } | |
d77e4531 PZ |
4888 | } |
4889 | ||
20bc8673 | 4890 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4891 | { |
4892 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4893 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4894 | |
6e3c9717 | 4895 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4896 | return; |
4897 | ||
4898 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4899 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4900 | mutex_lock(&dev_priv->rps.hw_lock); |
4901 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4902 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4903 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4904 | if (intel_wait_for_register(dev_priv, |
4905 | IPS_CTL, IPS_ENABLE, 0, | |
4906 | 42)) | |
23d0b130 | 4907 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4908 | } else { |
2a114cc1 | 4909 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4910 | POSTING_READ(IPS_CTL); |
4911 | } | |
d77e4531 PZ |
4912 | |
4913 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4914 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4915 | } |
4916 | ||
7cac945f | 4917 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4918 | { |
7cac945f | 4919 | if (intel_crtc->overlay) { |
d3eedb1a | 4920 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4921 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4922 | |
4923 | mutex_lock(&dev->struct_mutex); | |
4924 | dev_priv->mm.interruptible = false; | |
4925 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4926 | dev_priv->mm.interruptible = true; | |
4927 | mutex_unlock(&dev->struct_mutex); | |
4928 | } | |
4929 | ||
4930 | /* Let userspace switch the overlay on again. In most cases userspace | |
4931 | * has to recompute where to put it anyway. | |
4932 | */ | |
4933 | } | |
4934 | ||
87d4300a ML |
4935 | /** |
4936 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4937 | * @crtc: the CRTC whose primary plane was just enabled | |
4938 | * | |
4939 | * Performs potentially sleeping operations that must be done after the primary | |
4940 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4941 | * called due to an explicit primary plane update, or due to an implicit | |
4942 | * re-enable that is caused when a sprite plane is updated to no longer | |
4943 | * completely hide the primary plane. | |
4944 | */ | |
4945 | static void | |
4946 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4947 | { |
4948 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4949 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4950 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4951 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4952 | |
87d4300a ML |
4953 | /* |
4954 | * FIXME IPS should be fine as long as one plane is | |
4955 | * enabled, but in practice it seems to have problems | |
4956 | * when going from primary only to sprite only and vice | |
4957 | * versa. | |
4958 | */ | |
a5c4d7bc VS |
4959 | hsw_enable_ips(intel_crtc); |
4960 | ||
f99d7069 | 4961 | /* |
87d4300a ML |
4962 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4963 | * So don't enable underrun reporting before at least some planes | |
4964 | * are enabled. | |
4965 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4966 | * but leave the pipe running. | |
f99d7069 | 4967 | */ |
5db94019 | 4968 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4969 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4970 | ||
aca7b684 VS |
4971 | /* Underruns don't always raise interrupts, so check manually. */ |
4972 | intel_check_cpu_fifo_underruns(dev_priv); | |
4973 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4974 | } |
4975 | ||
2622a081 | 4976 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4977 | static void |
4978 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4979 | { |
4980 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4981 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4982 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4983 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4984 | |
87d4300a ML |
4985 | /* |
4986 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4987 | * So diasble underrun reporting before all the planes get disabled. | |
4988 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4989 | * but leave the pipe running. | |
4990 | */ | |
5db94019 | 4991 | if (IS_GEN2(dev_priv)) |
87d4300a | 4992 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 4993 | |
2622a081 VS |
4994 | /* |
4995 | * FIXME IPS should be fine as long as one plane is | |
4996 | * enabled, but in practice it seems to have problems | |
4997 | * when going from primary only to sprite only and vice | |
4998 | * versa. | |
4999 | */ | |
5000 | hsw_disable_ips(intel_crtc); | |
5001 | } | |
5002 | ||
5003 | /* FIXME get rid of this and use pre_plane_update */ | |
5004 | static void | |
5005 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
5006 | { | |
5007 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5008 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
5009 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5010 | int pipe = intel_crtc->pipe; | |
5011 | ||
5012 | intel_pre_disable_primary(crtc); | |
5013 | ||
87d4300a ML |
5014 | /* |
5015 | * Vblank time updates from the shadow to live plane control register | |
5016 | * are blocked if the memory self-refresh mode is active at that | |
5017 | * moment. So to make sure the plane gets truly disabled, disable | |
5018 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5019 | * will be checked/applied by the HW only at the next frame start | |
5020 | * event which is after the vblank start event, so we need to have a | |
5021 | * wait-for-vblank between disabling the plane and the pipe. | |
5022 | */ | |
49cff963 | 5023 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
87d4300a | 5024 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 | 5025 | dev_priv->wm.vlv.cxsr = false; |
0f0f74bc | 5026 | intel_wait_for_vblank(dev_priv, pipe); |
262cd2e1 | 5027 | } |
87d4300a ML |
5028 | } |
5029 | ||
5a21b665 DV |
5030 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
5031 | { | |
5032 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
5033 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
5034 | struct intel_crtc_state *pipe_config = | |
5035 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
5036 | struct drm_plane *primary = crtc->base.primary; |
5037 | struct drm_plane_state *old_pri_state = | |
5038 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5039 | ||
5748b6a1 | 5040 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 DV |
5041 | |
5042 | crtc->wm.cxsr_allowed = true; | |
5043 | ||
5044 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
432081bc | 5045 | intel_update_watermarks(crtc); |
5a21b665 DV |
5046 | |
5047 | if (old_pri_state) { | |
5048 | struct intel_plane_state *primary_state = | |
5049 | to_intel_plane_state(primary->state); | |
5050 | struct intel_plane_state *old_primary_state = | |
5051 | to_intel_plane_state(old_pri_state); | |
5052 | ||
5053 | intel_fbc_post_update(crtc); | |
5054 | ||
936e71e3 | 5055 | if (primary_state->base.visible && |
5a21b665 | 5056 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5057 | !old_primary_state->base.visible)) |
5a21b665 DV |
5058 | intel_post_enable_primary(&crtc->base); |
5059 | } | |
5060 | } | |
5061 | ||
5c74cd73 | 5062 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 5063 | { |
5c74cd73 | 5064 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5065 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5066 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
5067 | struct intel_crtc_state *pipe_config = |
5068 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
5069 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5070 | struct drm_plane *primary = crtc->base.primary; | |
5071 | struct drm_plane_state *old_pri_state = | |
5072 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5073 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5074 | struct intel_atomic_state *old_intel_state = |
5075 | to_intel_atomic_state(old_state); | |
ac21b225 | 5076 | |
5c74cd73 ML |
5077 | if (old_pri_state) { |
5078 | struct intel_plane_state *primary_state = | |
5079 | to_intel_plane_state(primary->state); | |
5080 | struct intel_plane_state *old_primary_state = | |
5081 | to_intel_plane_state(old_pri_state); | |
5082 | ||
faf68d92 | 5083 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5084 | |
936e71e3 VS |
5085 | if (old_primary_state->base.visible && |
5086 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5087 | intel_pre_disable_primary(&crtc->base); |
5088 | } | |
852eb00d | 5089 | |
49cff963 | 5090 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) { |
852eb00d | 5091 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 5092 | |
2622a081 VS |
5093 | /* |
5094 | * Vblank time updates from the shadow to live plane control register | |
5095 | * are blocked if the memory self-refresh mode is active at that | |
5096 | * moment. So to make sure the plane gets truly disabled, disable | |
5097 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5098 | * will be checked/applied by the HW only at the next frame start | |
5099 | * event which is after the vblank start event, so we need to have a | |
5100 | * wait-for-vblank between disabling the plane and the pipe. | |
5101 | */ | |
5102 | if (old_crtc_state->base.active) { | |
2dfd178d | 5103 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 | 5104 | dev_priv->wm.vlv.cxsr = false; |
0f0f74bc | 5105 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
2622a081 | 5106 | } |
852eb00d | 5107 | } |
92826fcd | 5108 | |
ed4a6a7c MR |
5109 | /* |
5110 | * IVB workaround: must disable low power watermarks for at least | |
5111 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5112 | * when scaling is disabled. | |
5113 | * | |
5114 | * WaCxSRDisabledForSpriteScaling:ivb | |
5115 | */ | |
5116 | if (pipe_config->disable_lp_wm) { | |
5117 | ilk_disable_lp_wm(dev); | |
0f0f74bc | 5118 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5119 | } |
5120 | ||
5121 | /* | |
5122 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5123 | * watermark programming here. | |
5124 | */ | |
5125 | if (needs_modeset(&pipe_config->base)) | |
5126 | return; | |
5127 | ||
5128 | /* | |
5129 | * For platforms that support atomic watermarks, program the | |
5130 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5131 | * will be the intermediate values that are safe for both pre- and | |
5132 | * post- vblank; when vblank happens, the 'active' values will be set | |
5133 | * to the final 'target' values and we'll do this again to get the | |
5134 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5135 | * will be the final target values which will get automatically latched | |
5136 | * at vblank time; no further programming will be necessary. | |
5137 | * | |
5138 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5139 | * we'll continue to update watermarks the old way, if flags tell | |
5140 | * us to. | |
5141 | */ | |
5142 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5143 | dev_priv->display.initial_watermarks(old_intel_state, |
5144 | pipe_config); | |
caed361d | 5145 | else if (pipe_config->update_wm_pre) |
432081bc | 5146 | intel_update_watermarks(crtc); |
ac21b225 ML |
5147 | } |
5148 | ||
d032ffa0 | 5149 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5150 | { |
5151 | struct drm_device *dev = crtc->dev; | |
5152 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5153 | struct drm_plane *p; |
87d4300a ML |
5154 | int pipe = intel_crtc->pipe; |
5155 | ||
7cac945f | 5156 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5157 | |
d032ffa0 ML |
5158 | drm_for_each_plane_mask(p, dev, plane_mask) |
5159 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5160 | |
f99d7069 DV |
5161 | /* |
5162 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5163 | * to compute the mask of flip planes precisely. For the time being | |
5164 | * consider this a flip to a NULL plane. | |
5165 | */ | |
5748b6a1 | 5166 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5167 | } |
5168 | ||
fb1c98b1 | 5169 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5170 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5171 | struct drm_atomic_state *old_state) |
5172 | { | |
5173 | struct drm_connector_state *old_conn_state; | |
5174 | struct drm_connector *conn; | |
5175 | int i; | |
5176 | ||
5177 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5178 | struct drm_connector_state *conn_state = conn->state; | |
5179 | struct intel_encoder *encoder = | |
5180 | to_intel_encoder(conn_state->best_encoder); | |
5181 | ||
5182 | if (conn_state->crtc != crtc) | |
5183 | continue; | |
5184 | ||
5185 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5186 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5187 | } |
5188 | } | |
5189 | ||
5190 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5191 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5192 | struct drm_atomic_state *old_state) |
5193 | { | |
5194 | struct drm_connector_state *old_conn_state; | |
5195 | struct drm_connector *conn; | |
5196 | int i; | |
5197 | ||
5198 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5199 | struct drm_connector_state *conn_state = conn->state; | |
5200 | struct intel_encoder *encoder = | |
5201 | to_intel_encoder(conn_state->best_encoder); | |
5202 | ||
5203 | if (conn_state->crtc != crtc) | |
5204 | continue; | |
5205 | ||
5206 | if (encoder->pre_enable) | |
fd6bbda9 | 5207 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5208 | } |
5209 | } | |
5210 | ||
5211 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5212 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5213 | struct drm_atomic_state *old_state) |
5214 | { | |
5215 | struct drm_connector_state *old_conn_state; | |
5216 | struct drm_connector *conn; | |
5217 | int i; | |
5218 | ||
5219 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5220 | struct drm_connector_state *conn_state = conn->state; | |
5221 | struct intel_encoder *encoder = | |
5222 | to_intel_encoder(conn_state->best_encoder); | |
5223 | ||
5224 | if (conn_state->crtc != crtc) | |
5225 | continue; | |
5226 | ||
fd6bbda9 | 5227 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5228 | intel_opregion_notify_encoder(encoder, true); |
5229 | } | |
5230 | } | |
5231 | ||
5232 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5233 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5234 | struct drm_atomic_state *old_state) |
5235 | { | |
5236 | struct drm_connector_state *old_conn_state; | |
5237 | struct drm_connector *conn; | |
5238 | int i; | |
5239 | ||
5240 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5241 | struct intel_encoder *encoder = | |
5242 | to_intel_encoder(old_conn_state->best_encoder); | |
5243 | ||
5244 | if (old_conn_state->crtc != crtc) | |
5245 | continue; | |
5246 | ||
5247 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5248 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5249 | } |
5250 | } | |
5251 | ||
5252 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5253 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5254 | struct drm_atomic_state *old_state) |
5255 | { | |
5256 | struct drm_connector_state *old_conn_state; | |
5257 | struct drm_connector *conn; | |
5258 | int i; | |
5259 | ||
5260 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5261 | struct intel_encoder *encoder = | |
5262 | to_intel_encoder(old_conn_state->best_encoder); | |
5263 | ||
5264 | if (old_conn_state->crtc != crtc) | |
5265 | continue; | |
5266 | ||
5267 | if (encoder->post_disable) | |
fd6bbda9 | 5268 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5269 | } |
5270 | } | |
5271 | ||
5272 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5273 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5274 | struct drm_atomic_state *old_state) |
5275 | { | |
5276 | struct drm_connector_state *old_conn_state; | |
5277 | struct drm_connector *conn; | |
5278 | int i; | |
5279 | ||
5280 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5281 | struct intel_encoder *encoder = | |
5282 | to_intel_encoder(old_conn_state->best_encoder); | |
5283 | ||
5284 | if (old_conn_state->crtc != crtc) | |
5285 | continue; | |
5286 | ||
5287 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5288 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5289 | } |
5290 | } | |
5291 | ||
4a806558 ML |
5292 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5293 | struct drm_atomic_state *old_state) | |
f67a559d | 5294 | { |
4a806558 | 5295 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5296 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5297 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5298 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5299 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5300 | struct intel_atomic_state *old_intel_state = |
5301 | to_intel_atomic_state(old_state); | |
f67a559d | 5302 | |
53d9f4e9 | 5303 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5304 | return; |
5305 | ||
b2c0593a VS |
5306 | /* |
5307 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5308 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5309 | * | |
5310 | * On ILK we get an occasional spurious CPU pipe underruns | |
5311 | * between eDP port A enable and vdd enable. Also PCH port | |
5312 | * enable seems to result in the occasional CPU pipe underrun. | |
5313 | * | |
5314 | * Spurious PCH underruns also occur during PCH enabling. | |
5315 | */ | |
5316 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5317 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5318 | if (intel_crtc->config->has_pch_encoder) |
5319 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5320 | ||
6e3c9717 | 5321 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5322 | intel_prepare_shared_dpll(intel_crtc); |
5323 | ||
37a5650b | 5324 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5325 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5326 | |
5327 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5328 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5329 | |
6e3c9717 | 5330 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5331 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5332 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5333 | } |
5334 | ||
5335 | ironlake_set_pipeconf(crtc); | |
5336 | ||
f67a559d | 5337 | intel_crtc->active = true; |
8664281b | 5338 | |
fd6bbda9 | 5339 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5340 | |
6e3c9717 | 5341 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5342 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5343 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5344 | * enabling. */ | |
88cefb6c | 5345 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5346 | } else { |
5347 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5348 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5349 | } | |
f67a559d | 5350 | |
b074cec8 | 5351 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5352 | |
9c54c0dd JB |
5353 | /* |
5354 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5355 | * clocks enabled | |
5356 | */ | |
b95c5321 | 5357 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5358 | |
1d5bf5d9 | 5359 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5360 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5361 | intel_enable_pipe(intel_crtc); |
f67a559d | 5362 | |
6e3c9717 | 5363 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 5364 | ironlake_pch_enable(crtc); |
c98e9dcf | 5365 | |
f9b61ff6 DV |
5366 | assert_vblank_disabled(crtc); |
5367 | drm_crtc_vblank_on(crtc); | |
5368 | ||
fd6bbda9 | 5369 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5370 | |
6e266956 | 5371 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5372 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5373 | |
5374 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5375 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5376 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5377 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5378 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5379 | } |
5380 | ||
42db64ef PZ |
5381 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5382 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5383 | { | |
50a0bc90 | 5384 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5385 | } |
5386 | ||
4a806558 ML |
5387 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5388 | struct drm_atomic_state *old_state) | |
4f771f10 | 5389 | { |
4a806558 | 5390 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5391 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5392 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5393 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5394 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5395 | struct intel_atomic_state *old_intel_state = |
5396 | to_intel_atomic_state(old_state); | |
4f771f10 | 5397 | |
53d9f4e9 | 5398 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5399 | return; |
5400 | ||
81b088ca VS |
5401 | if (intel_crtc->config->has_pch_encoder) |
5402 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5403 | false); | |
5404 | ||
fd6bbda9 | 5405 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5406 | |
8106ddbd | 5407 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5408 | intel_enable_shared_dpll(intel_crtc); |
5409 | ||
37a5650b | 5410 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5411 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5412 | |
d7edc4e5 | 5413 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5414 | intel_set_pipe_timings(intel_crtc); |
5415 | ||
bc58be60 | 5416 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5417 | |
4d1de975 JN |
5418 | if (cpu_transcoder != TRANSCODER_EDP && |
5419 | !transcoder_is_dsi(cpu_transcoder)) { | |
5420 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5421 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5422 | } |
5423 | ||
6e3c9717 | 5424 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5425 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5426 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5427 | } |
5428 | ||
d7edc4e5 | 5429 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5430 | haswell_set_pipeconf(crtc); |
5431 | ||
391bf048 | 5432 | haswell_set_pipemisc(crtc); |
229fca97 | 5433 | |
b95c5321 | 5434 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5435 | |
4f771f10 | 5436 | intel_crtc->active = true; |
8664281b | 5437 | |
6b698516 DV |
5438 | if (intel_crtc->config->has_pch_encoder) |
5439 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5440 | else | |
5441 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5442 | ||
fd6bbda9 | 5443 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5444 | |
d2d65408 | 5445 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5446 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5447 | |
d7edc4e5 | 5448 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5449 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5450 | |
6315b5d3 | 5451 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5452 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5453 | else |
1c132b44 | 5454 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5455 | |
5456 | /* | |
5457 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5458 | * clocks enabled | |
5459 | */ | |
b95c5321 | 5460 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5461 | |
1f544388 | 5462 | intel_ddi_set_pipe_settings(crtc); |
d7edc4e5 | 5463 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5464 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5465 | |
1d5bf5d9 | 5466 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb ML |
5467 | dev_priv->display.initial_watermarks(old_intel_state, |
5468 | pipe_config); | |
1d5bf5d9 | 5469 | else |
432081bc | 5470 | intel_update_watermarks(intel_crtc); |
4d1de975 JN |
5471 | |
5472 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5473 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5474 | intel_enable_pipe(intel_crtc); |
42db64ef | 5475 | |
6e3c9717 | 5476 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5477 | lpt_pch_enable(crtc); |
4f771f10 | 5478 | |
0037071d | 5479 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
0e32b39c DA |
5480 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5481 | ||
f9b61ff6 DV |
5482 | assert_vblank_disabled(crtc); |
5483 | drm_crtc_vblank_on(crtc); | |
5484 | ||
fd6bbda9 | 5485 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5486 | |
6b698516 | 5487 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5488 | intel_wait_for_vblank(dev_priv, pipe); |
5489 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5490 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
d2d65408 VS |
5491 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5492 | true); | |
6b698516 | 5493 | } |
d2d65408 | 5494 | |
e4916946 PZ |
5495 | /* If we change the relative order between pipe/planes enabling, we need |
5496 | * to change the workaround. */ | |
99d736a2 | 5497 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5498 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5499 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5500 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5501 | } |
4f771f10 PZ |
5502 | } |
5503 | ||
bfd16b2a | 5504 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5505 | { |
5506 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5507 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5508 | int pipe = crtc->pipe; |
5509 | ||
5510 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5511 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5512 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5513 | I915_WRITE(PF_CTL(pipe), 0); |
5514 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5515 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5516 | } | |
5517 | } | |
5518 | ||
4a806558 ML |
5519 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5520 | struct drm_atomic_state *old_state) | |
6be4a607 | 5521 | { |
4a806558 | 5522 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5523 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5524 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5525 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5526 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5527 | |
b2c0593a VS |
5528 | /* |
5529 | * Sometimes spurious CPU pipe underruns happen when the | |
5530 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5531 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5532 | */ | |
5533 | if (intel_crtc->config->has_pch_encoder) { | |
5534 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5535 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5536 | } |
37ca8d4c | 5537 | |
fd6bbda9 | 5538 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5539 | |
f9b61ff6 DV |
5540 | drm_crtc_vblank_off(crtc); |
5541 | assert_vblank_disabled(crtc); | |
5542 | ||
575f7ab7 | 5543 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5544 | |
bfd16b2a | 5545 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5546 | |
b2c0593a | 5547 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5548 | ironlake_fdi_disable(crtc); |
5549 | ||
fd6bbda9 | 5550 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5551 | |
6e3c9717 | 5552 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5553 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5554 | |
6e266956 | 5555 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5556 | i915_reg_t reg; |
5557 | u32 temp; | |
5558 | ||
d925c59a DV |
5559 | /* disable TRANS_DP_CTL */ |
5560 | reg = TRANS_DP_CTL(pipe); | |
5561 | temp = I915_READ(reg); | |
5562 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5563 | TRANS_DP_PORT_SEL_MASK); | |
5564 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5565 | I915_WRITE(reg, temp); | |
5566 | ||
5567 | /* disable DPLL_SEL */ | |
5568 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5569 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5570 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5571 | } |
e3421a18 | 5572 | |
d925c59a DV |
5573 | ironlake_fdi_pll_disable(intel_crtc); |
5574 | } | |
81b088ca | 5575 | |
b2c0593a | 5576 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5577 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5578 | } |
1b3c7a47 | 5579 | |
4a806558 ML |
5580 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5581 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5582 | { |
4a806558 | 5583 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5584 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5585 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5586 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5587 | |
d2d65408 VS |
5588 | if (intel_crtc->config->has_pch_encoder) |
5589 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5590 | false); | |
5591 | ||
fd6bbda9 | 5592 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5593 | |
f9b61ff6 DV |
5594 | drm_crtc_vblank_off(crtc); |
5595 | assert_vblank_disabled(crtc); | |
5596 | ||
4d1de975 | 5597 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5598 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5599 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5600 | |
0037071d | 5601 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
a4bf214f VS |
5602 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5603 | ||
d7edc4e5 | 5604 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5605 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5606 | |
6315b5d3 | 5607 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5608 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5609 | else |
bfd16b2a | 5610 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5611 | |
d7edc4e5 | 5612 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5613 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5614 | |
fd6bbda9 | 5615 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5616 | |
b7076546 | 5617 | if (old_crtc_state->has_pch_encoder) |
81b088ca VS |
5618 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5619 | true); | |
4f771f10 PZ |
5620 | } |
5621 | ||
2dd24552 JB |
5622 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5623 | { | |
5624 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5625 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5626 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5627 | |
681a8504 | 5628 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5629 | return; |
5630 | ||
2dd24552 | 5631 | /* |
c0b03411 DV |
5632 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5633 | * according to register description and PRM. | |
2dd24552 | 5634 | */ |
c0b03411 DV |
5635 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5636 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5637 | |
b074cec8 JB |
5638 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5639 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5640 | |
5641 | /* Border color in case we don't scale up to the full screen. Black by | |
5642 | * default, change to something else for debugging. */ | |
5643 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5644 | } |
5645 | ||
d05410f9 DA |
5646 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5647 | { | |
5648 | switch (port) { | |
5649 | case PORT_A: | |
6331a704 | 5650 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5651 | case PORT_B: |
6331a704 | 5652 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5653 | case PORT_C: |
6331a704 | 5654 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5655 | case PORT_D: |
6331a704 | 5656 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5657 | case PORT_E: |
6331a704 | 5658 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5659 | default: |
b9fec167 | 5660 | MISSING_CASE(port); |
d05410f9 DA |
5661 | return POWER_DOMAIN_PORT_OTHER; |
5662 | } | |
5663 | } | |
5664 | ||
25f78f58 VS |
5665 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5666 | { | |
5667 | switch (port) { | |
5668 | case PORT_A: | |
5669 | return POWER_DOMAIN_AUX_A; | |
5670 | case PORT_B: | |
5671 | return POWER_DOMAIN_AUX_B; | |
5672 | case PORT_C: | |
5673 | return POWER_DOMAIN_AUX_C; | |
5674 | case PORT_D: | |
5675 | return POWER_DOMAIN_AUX_D; | |
5676 | case PORT_E: | |
5677 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5678 | return POWER_DOMAIN_AUX_D; | |
5679 | default: | |
b9fec167 | 5680 | MISSING_CASE(port); |
25f78f58 VS |
5681 | return POWER_DOMAIN_AUX_A; |
5682 | } | |
5683 | } | |
5684 | ||
319be8ae ID |
5685 | enum intel_display_power_domain |
5686 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5687 | { | |
4f8036a2 | 5688 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
319be8ae ID |
5689 | struct intel_digital_port *intel_dig_port; |
5690 | ||
5691 | switch (intel_encoder->type) { | |
5692 | case INTEL_OUTPUT_UNKNOWN: | |
5693 | /* Only DDI platforms should ever use this output type */ | |
4f8036a2 | 5694 | WARN_ON_ONCE(!HAS_DDI(dev_priv)); |
cca0502b | 5695 | case INTEL_OUTPUT_DP: |
319be8ae ID |
5696 | case INTEL_OUTPUT_HDMI: |
5697 | case INTEL_OUTPUT_EDP: | |
5698 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5699 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5700 | case INTEL_OUTPUT_DP_MST: |
5701 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5702 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5703 | case INTEL_OUTPUT_ANALOG: |
5704 | return POWER_DOMAIN_PORT_CRT; | |
5705 | case INTEL_OUTPUT_DSI: | |
5706 | return POWER_DOMAIN_PORT_DSI; | |
5707 | default: | |
5708 | return POWER_DOMAIN_PORT_OTHER; | |
5709 | } | |
5710 | } | |
5711 | ||
25f78f58 VS |
5712 | enum intel_display_power_domain |
5713 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5714 | { | |
4f8036a2 | 5715 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
25f78f58 VS |
5716 | struct intel_digital_port *intel_dig_port; |
5717 | ||
5718 | switch (intel_encoder->type) { | |
5719 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5720 | case INTEL_OUTPUT_HDMI: |
5721 | /* | |
5722 | * Only DDI platforms should ever use these output types. | |
5723 | * We can get here after the HDMI detect code has already set | |
5724 | * the type of the shared encoder. Since we can't be sure | |
5725 | * what's the status of the given connectors, play safe and | |
5726 | * run the DP detection too. | |
5727 | */ | |
4f8036a2 | 5728 | WARN_ON_ONCE(!HAS_DDI(dev_priv)); |
cca0502b | 5729 | case INTEL_OUTPUT_DP: |
25f78f58 VS |
5730 | case INTEL_OUTPUT_EDP: |
5731 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5732 | return port_to_aux_power_domain(intel_dig_port->port); | |
5733 | case INTEL_OUTPUT_DP_MST: | |
5734 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5735 | return port_to_aux_power_domain(intel_dig_port->port); | |
5736 | default: | |
b9fec167 | 5737 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5738 | return POWER_DOMAIN_AUX_A; |
5739 | } | |
5740 | } | |
5741 | ||
74bff5f9 ML |
5742 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5743 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5744 | { |
319be8ae | 5745 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5746 | struct drm_encoder *encoder; |
319be8ae ID |
5747 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5748 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5749 | unsigned long mask; |
74bff5f9 | 5750 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5751 | |
74bff5f9 | 5752 | if (!crtc_state->base.active) |
292b990e ML |
5753 | return 0; |
5754 | ||
77d22dca ID |
5755 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5756 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5757 | if (crtc_state->pch_pfit.enabled || |
5758 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5759 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5760 | ||
74bff5f9 ML |
5761 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5762 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5763 | ||
319be8ae | 5764 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5765 | } |
319be8ae | 5766 | |
15e7ec29 ML |
5767 | if (crtc_state->shared_dpll) |
5768 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5769 | ||
77d22dca ID |
5770 | return mask; |
5771 | } | |
5772 | ||
74bff5f9 ML |
5773 | static unsigned long |
5774 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5775 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5776 | { |
fac5e23e | 5777 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5778 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5779 | enum intel_display_power_domain domain; | |
5a21b665 | 5780 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5781 | |
292b990e | 5782 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5783 | intel_crtc->enabled_power_domains = new_domains = |
5784 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5785 | |
5a21b665 | 5786 | domains = new_domains & ~old_domains; |
292b990e ML |
5787 | |
5788 | for_each_power_domain(domain, domains) | |
5789 | intel_display_power_get(dev_priv, domain); | |
5790 | ||
5a21b665 | 5791 | return old_domains & ~new_domains; |
292b990e ML |
5792 | } |
5793 | ||
5794 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5795 | unsigned long domains) | |
5796 | { | |
5797 | enum intel_display_power_domain domain; | |
5798 | ||
5799 | for_each_power_domain(domain, domains) | |
5800 | intel_display_power_put(dev_priv, domain); | |
5801 | } | |
77d22dca | 5802 | |
adafdc6f MK |
5803 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5804 | { | |
5805 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5806 | ||
5807 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5808 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5809 | return max_cdclk_freq; | |
5810 | else if (IS_CHERRYVIEW(dev_priv)) | |
5811 | return max_cdclk_freq*95/100; | |
5812 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5813 | return 2*max_cdclk_freq*90/100; | |
5814 | else | |
5815 | return max_cdclk_freq*90/100; | |
5816 | } | |
5817 | ||
b2045352 VS |
5818 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5819 | ||
4c75b940 | 5820 | static void intel_update_max_cdclk(struct drm_i915_private *dev_priv) |
560a7ae4 | 5821 | { |
0853723b | 5822 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
560a7ae4 | 5823 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5824 | int max_cdclk, vco; |
5825 | ||
5826 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5827 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5828 | |
b2045352 VS |
5829 | /* |
5830 | * Use the lower (vco 8640) cdclk values as a | |
5831 | * first guess. skl_calc_cdclk() will correct it | |
5832 | * if the preferred vco is 8100 instead. | |
5833 | */ | |
560a7ae4 | 5834 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5835 | max_cdclk = 617143; |
560a7ae4 | 5836 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5837 | max_cdclk = 540000; |
560a7ae4 | 5838 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5839 | max_cdclk = 432000; |
560a7ae4 | 5840 | else |
487ed2e4 | 5841 | max_cdclk = 308571; |
b2045352 VS |
5842 | |
5843 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
e2d214ae | 5844 | } else if (IS_BROXTON(dev_priv)) { |
281c114f | 5845 | dev_priv->max_cdclk_freq = 624000; |
8652744b | 5846 | } else if (IS_BROADWELL(dev_priv)) { |
560a7ae4 DL |
5847 | /* |
5848 | * FIXME with extra cooling we can allow | |
5849 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5850 | * How can we know if extra cooling is | |
5851 | * available? PCI ID, VTB, something else? | |
5852 | */ | |
5853 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5854 | dev_priv->max_cdclk_freq = 450000; | |
50a0bc90 | 5855 | else if (IS_BDW_ULX(dev_priv)) |
560a7ae4 | 5856 | dev_priv->max_cdclk_freq = 450000; |
50a0bc90 | 5857 | else if (IS_BDW_ULT(dev_priv)) |
560a7ae4 DL |
5858 | dev_priv->max_cdclk_freq = 540000; |
5859 | else | |
5860 | dev_priv->max_cdclk_freq = 675000; | |
920a14b2 | 5861 | } else if (IS_CHERRYVIEW(dev_priv)) { |
0904deaf | 5862 | dev_priv->max_cdclk_freq = 320000; |
11a914c2 | 5863 | } else if (IS_VALLEYVIEW(dev_priv)) { |
560a7ae4 DL |
5864 | dev_priv->max_cdclk_freq = 400000; |
5865 | } else { | |
5866 | /* otherwise assume cdclk is fixed */ | |
5867 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5868 | } | |
5869 | ||
adafdc6f MK |
5870 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5871 | ||
560a7ae4 DL |
5872 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5873 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5874 | |
5875 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5876 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5877 | } |
5878 | ||
4c75b940 | 5879 | static void intel_update_cdclk(struct drm_i915_private *dev_priv) |
560a7ae4 | 5880 | { |
1353c4fb | 5881 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv); |
2f2a121a | 5882 | |
83d7c81f | 5883 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5884 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5885 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5886 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5887 | else |
5888 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5889 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5890 | |
5891 | /* | |
b5d99ff9 VS |
5892 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5893 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5894 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5895 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5896 | */ |
b5d99ff9 | 5897 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5898 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5899 | } |
5900 | ||
92891e45 VS |
5901 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5902 | static int skl_cdclk_decimal(int cdclk) | |
5903 | { | |
5904 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5905 | } | |
5906 | ||
5f199dfa VS |
5907 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5908 | { | |
5909 | int ratio; | |
5910 | ||
5911 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5912 | return 0; | |
5913 | ||
5914 | switch (cdclk) { | |
5915 | default: | |
5916 | MISSING_CASE(cdclk); | |
5917 | case 144000: | |
5918 | case 288000: | |
5919 | case 384000: | |
5920 | case 576000: | |
5921 | ratio = 60; | |
5922 | break; | |
5923 | case 624000: | |
5924 | ratio = 65; | |
5925 | break; | |
5926 | } | |
5927 | ||
5928 | return dev_priv->cdclk_pll.ref * ratio; | |
5929 | } | |
5930 | ||
2b73001e VS |
5931 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5932 | { | |
5933 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5934 | ||
5935 | /* Timeout 200us */ | |
95cac283 CW |
5936 | if (intel_wait_for_register(dev_priv, |
5937 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
5938 | 1)) | |
2b73001e | 5939 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
83d7c81f VS |
5940 | |
5941 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5942 | } |
5943 | ||
5f199dfa | 5944 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5945 | { |
5f199dfa | 5946 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5947 | u32 val; |
5948 | ||
5949 | val = I915_READ(BXT_DE_PLL_CTL); | |
5950 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5951 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5952 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5953 | ||
5954 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5955 | ||
5956 | /* Timeout 200us */ | |
e084e1b9 CW |
5957 | if (intel_wait_for_register(dev_priv, |
5958 | BXT_DE_PLL_ENABLE, | |
5959 | BXT_DE_PLL_LOCK, | |
5960 | BXT_DE_PLL_LOCK, | |
5961 | 1)) | |
2b73001e | 5962 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
83d7c81f | 5963 | |
5f199dfa | 5964 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5965 | } |
5966 | ||
324513c0 | 5967 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5968 | { |
5f199dfa VS |
5969 | u32 val, divider; |
5970 | int vco, ret; | |
f8437dd1 | 5971 | |
5f199dfa VS |
5972 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
5973 | ||
5974 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5975 | ||
5976 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5977 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5978 | case 8: | |
f8437dd1 | 5979 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5980 | break; |
5f199dfa | 5981 | case 4: |
f8437dd1 | 5982 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 5983 | break; |
5f199dfa | 5984 | case 3: |
f8437dd1 | 5985 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 5986 | break; |
5f199dfa | 5987 | case 2: |
f8437dd1 | 5988 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
5989 | break; |
5990 | default: | |
5f199dfa VS |
5991 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
5992 | WARN_ON(vco != 0); | |
f8437dd1 | 5993 | |
5f199dfa VS |
5994 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
5995 | break; | |
f8437dd1 VK |
5996 | } |
5997 | ||
f8437dd1 | 5998 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 5999 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
6000 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
6001 | 0x80000000); | |
6002 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6003 | ||
6004 | if (ret) { | |
6005 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 6006 | ret, cdclk); |
f8437dd1 VK |
6007 | return; |
6008 | } | |
6009 | ||
5f199dfa VS |
6010 | if (dev_priv->cdclk_pll.vco != 0 && |
6011 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 6012 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 6013 | |
5f199dfa VS |
6014 | if (dev_priv->cdclk_pll.vco != vco) |
6015 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 6016 | |
5f199dfa VS |
6017 | val = divider | skl_cdclk_decimal(cdclk); |
6018 | /* | |
6019 | * FIXME if only the cd2x divider needs changing, it could be done | |
6020 | * without shutting off the pipe (if only one pipe is active). | |
6021 | */ | |
6022 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
6023 | /* | |
6024 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
6025 | * enable otherwise. | |
6026 | */ | |
6027 | if (cdclk >= 500000) | |
6028 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
6029 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
6030 | |
6031 | mutex_lock(&dev_priv->rps.hw_lock); | |
6032 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 6033 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
6034 | mutex_unlock(&dev_priv->rps.hw_lock); |
6035 | ||
6036 | if (ret) { | |
6037 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 6038 | ret, cdclk); |
f8437dd1 VK |
6039 | return; |
6040 | } | |
6041 | ||
4c75b940 | 6042 | intel_update_cdclk(dev_priv); |
f8437dd1 VK |
6043 | } |
6044 | ||
d66a2194 | 6045 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 6046 | { |
d66a2194 ID |
6047 | u32 cdctl, expected; |
6048 | ||
4c75b940 | 6049 | intel_update_cdclk(dev_priv); |
f8437dd1 | 6050 | |
d66a2194 ID |
6051 | if (dev_priv->cdclk_pll.vco == 0 || |
6052 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
6053 | goto sanitize; | |
6054 | ||
6055 | /* DPLL okay; verify the cdclock | |
6056 | * | |
6057 | * Some BIOS versions leave an incorrect decimal frequency value and | |
6058 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
6059 | * so sanitize this register. | |
6060 | */ | |
6061 | cdctl = I915_READ(CDCLK_CTL); | |
6062 | /* | |
6063 | * Let's ignore the pipe field, since BIOS could have configured the | |
6064 | * dividers both synching to an active pipe, or asynchronously | |
6065 | * (PIPE_NONE). | |
6066 | */ | |
6067 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
6068 | ||
6069 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
6070 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6071 | /* | |
6072 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
6073 | * enable otherwise. | |
6074 | */ | |
6075 | if (dev_priv->cdclk_freq >= 500000) | |
6076 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
6077 | ||
6078 | if (cdctl == expected) | |
6079 | /* All well; nothing to sanitize */ | |
6080 | return; | |
6081 | ||
6082 | sanitize: | |
6083 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
6084 | ||
6085 | /* force cdclk programming */ | |
6086 | dev_priv->cdclk_freq = 0; | |
6087 | ||
6088 | /* force full PLL disable + enable */ | |
6089 | dev_priv->cdclk_pll.vco = -1; | |
6090 | } | |
6091 | ||
324513c0 | 6092 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 ID |
6093 | { |
6094 | bxt_sanitize_cdclk(dev_priv); | |
6095 | ||
6096 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 6097 | return; |
c2e001ef | 6098 | |
f8437dd1 VK |
6099 | /* |
6100 | * FIXME: | |
6101 | * - The initial CDCLK needs to be read from VBT. | |
6102 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 6103 | */ |
324513c0 | 6104 | bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); |
f8437dd1 VK |
6105 | } |
6106 | ||
324513c0 | 6107 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 6108 | { |
324513c0 | 6109 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
6110 | } |
6111 | ||
a8ca4934 VS |
6112 | static int skl_calc_cdclk(int max_pixclk, int vco) |
6113 | { | |
63911d72 | 6114 | if (vco == 8640000) { |
a8ca4934 | 6115 | if (max_pixclk > 540000) |
487ed2e4 | 6116 | return 617143; |
a8ca4934 VS |
6117 | else if (max_pixclk > 432000) |
6118 | return 540000; | |
487ed2e4 | 6119 | else if (max_pixclk > 308571) |
a8ca4934 VS |
6120 | return 432000; |
6121 | else | |
487ed2e4 | 6122 | return 308571; |
a8ca4934 | 6123 | } else { |
a8ca4934 VS |
6124 | if (max_pixclk > 540000) |
6125 | return 675000; | |
6126 | else if (max_pixclk > 450000) | |
6127 | return 540000; | |
6128 | else if (max_pixclk > 337500) | |
6129 | return 450000; | |
6130 | else | |
6131 | return 337500; | |
6132 | } | |
6133 | } | |
6134 | ||
ea61791e VS |
6135 | static void |
6136 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 6137 | { |
ea61791e | 6138 | u32 val; |
5d96d8af | 6139 | |
709e05c3 | 6140 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 6141 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 6142 | |
ea61791e | 6143 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 6144 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 6145 | return; |
5d96d8af | 6146 | |
1c3f7700 ID |
6147 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
6148 | return; | |
9f7eb31a | 6149 | |
ea61791e VS |
6150 | val = I915_READ(DPLL_CTRL1); |
6151 | ||
1c3f7700 ID |
6152 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
6153 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6154 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
6155 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
6156 | return; | |
9f7eb31a | 6157 | |
ea61791e VS |
6158 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
6159 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
6160 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
6161 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
6162 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 6163 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
6164 | break; |
6165 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
6166 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 6167 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
6168 | break; |
6169 | default: | |
6170 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
6171 | break; |
6172 | } | |
5d96d8af DL |
6173 | } |
6174 | ||
b2045352 VS |
6175 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
6176 | { | |
6177 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
6178 | ||
6179 | dev_priv->skl_preferred_vco_freq = vco; | |
6180 | ||
6181 | if (changed) | |
4c75b940 | 6182 | intel_update_max_cdclk(dev_priv); |
b2045352 VS |
6183 | } |
6184 | ||
5d96d8af | 6185 | static void |
3861fc60 | 6186 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 6187 | { |
a8ca4934 | 6188 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
6189 | u32 val; |
6190 | ||
63911d72 | 6191 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 6192 | |
5d96d8af | 6193 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 6194 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
6195 | I915_WRITE(CDCLK_CTL, val); |
6196 | POSTING_READ(CDCLK_CTL); | |
6197 | ||
6198 | /* | |
6199 | * We always enable DPLL0 with the lowest link rate possible, but still | |
6200 | * taking into account the VCO required to operate the eDP panel at the | |
6201 | * desired frequency. The usual DP link rates operate with a VCO of | |
6202 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
6203 | * The modeset code is responsible for the selection of the exact link | |
6204 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 6205 | * works with vco. |
5d96d8af DL |
6206 | */ |
6207 | val = I915_READ(DPLL_CTRL1); | |
6208 | ||
6209 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6210 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
6211 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 6212 | if (vco == 8640000) |
5d96d8af DL |
6213 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
6214 | SKL_DPLL0); | |
6215 | else | |
6216 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
6217 | SKL_DPLL0); | |
6218 | ||
6219 | I915_WRITE(DPLL_CTRL1, val); | |
6220 | POSTING_READ(DPLL_CTRL1); | |
6221 | ||
6222 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
6223 | ||
e24ca054 CW |
6224 | if (intel_wait_for_register(dev_priv, |
6225 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
6226 | 5)) | |
5d96d8af | 6227 | DRM_ERROR("DPLL0 not locked\n"); |
1cd593e0 | 6228 | |
63911d72 | 6229 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
6230 | |
6231 | /* We'll want to keep using the current vco from now on. */ | |
6232 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
6233 | } |
6234 | ||
430e05de VS |
6235 | static void |
6236 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
6237 | { | |
6238 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
8ad32a05 CW |
6239 | if (intel_wait_for_register(dev_priv, |
6240 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
6241 | 1)) | |
430e05de | 6242 | DRM_ERROR("Couldn't disable DPLL0\n"); |
1cd593e0 | 6243 | |
63911d72 | 6244 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
6245 | } |
6246 | ||
5d96d8af DL |
6247 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
6248 | { | |
6249 | int ret; | |
6250 | u32 val; | |
6251 | ||
6252 | /* inform PCU we want to change CDCLK */ | |
6253 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
6254 | mutex_lock(&dev_priv->rps.hw_lock); | |
6255 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
6256 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6257 | ||
6258 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
6259 | } | |
6260 | ||
6261 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
6262 | { | |
848496e5 | 6263 | return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0; |
5d96d8af DL |
6264 | } |
6265 | ||
1cd593e0 | 6266 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af DL |
6267 | { |
6268 | u32 freq_select, pcu_ack; | |
6269 | ||
1cd593e0 VS |
6270 | WARN_ON((cdclk == 24000) != (vco == 0)); |
6271 | ||
63911d72 | 6272 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
6273 | |
6274 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
6275 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
6276 | return; | |
6277 | } | |
6278 | ||
6279 | /* set CDCLK_CTL */ | |
9ef56154 | 6280 | switch (cdclk) { |
5d96d8af DL |
6281 | case 450000: |
6282 | case 432000: | |
6283 | freq_select = CDCLK_FREQ_450_432; | |
6284 | pcu_ack = 1; | |
6285 | break; | |
6286 | case 540000: | |
6287 | freq_select = CDCLK_FREQ_540; | |
6288 | pcu_ack = 2; | |
6289 | break; | |
487ed2e4 | 6290 | case 308571: |
5d96d8af DL |
6291 | case 337500: |
6292 | default: | |
6293 | freq_select = CDCLK_FREQ_337_308; | |
6294 | pcu_ack = 0; | |
6295 | break; | |
487ed2e4 | 6296 | case 617143: |
5d96d8af DL |
6297 | case 675000: |
6298 | freq_select = CDCLK_FREQ_675_617; | |
6299 | pcu_ack = 3; | |
6300 | break; | |
6301 | } | |
6302 | ||
63911d72 VS |
6303 | if (dev_priv->cdclk_pll.vco != 0 && |
6304 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
6305 | skl_dpll0_disable(dev_priv); |
6306 | ||
63911d72 | 6307 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
6308 | skl_dpll0_enable(dev_priv, vco); |
6309 | ||
9ef56154 | 6310 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
6311 | POSTING_READ(CDCLK_CTL); |
6312 | ||
6313 | /* inform PCU of the change */ | |
6314 | mutex_lock(&dev_priv->rps.hw_lock); | |
6315 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
6316 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 | 6317 | |
4c75b940 | 6318 | intel_update_cdclk(dev_priv); |
5d96d8af DL |
6319 | } |
6320 | ||
9f7eb31a VS |
6321 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
6322 | ||
5d96d8af DL |
6323 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
6324 | { | |
709e05c3 | 6325 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
6326 | } |
6327 | ||
6328 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
6329 | { | |
9f7eb31a VS |
6330 | int cdclk, vco; |
6331 | ||
6332 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 6333 | |
63911d72 | 6334 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
6335 | /* |
6336 | * Use the current vco as our initial | |
6337 | * guess as to what the preferred vco is. | |
6338 | */ | |
6339 | if (dev_priv->skl_preferred_vco_freq == 0) | |
6340 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 6341 | dev_priv->cdclk_pll.vco); |
70c2c184 | 6342 | return; |
1cd593e0 | 6343 | } |
5d96d8af | 6344 | |
70c2c184 VS |
6345 | vco = dev_priv->skl_preferred_vco_freq; |
6346 | if (vco == 0) | |
63911d72 | 6347 | vco = 8100000; |
70c2c184 | 6348 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 6349 | |
70c2c184 | 6350 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
6351 | } |
6352 | ||
9f7eb31a | 6353 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 6354 | { |
09492498 | 6355 | uint32_t cdctl, expected; |
c73666f3 | 6356 | |
f1b391a5 SK |
6357 | /* |
6358 | * check if the pre-os intialized the display | |
6359 | * There is SWF18 scratchpad register defined which is set by the | |
6360 | * pre-os which can be used by the OS drivers to check the status | |
6361 | */ | |
6362 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
6363 | goto sanitize; | |
6364 | ||
4c75b940 | 6365 | intel_update_cdclk(dev_priv); |
c73666f3 | 6366 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
6367 | if (dev_priv->cdclk_pll.vco == 0 || |
6368 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
6369 | goto sanitize; |
6370 | ||
6371 | /* DPLL okay; verify the cdclock | |
6372 | * | |
6373 | * Noticed in some instances that the freq selection is correct but | |
6374 | * decimal part is programmed wrong from BIOS where pre-os does not | |
6375 | * enable display. Verify the same as well. | |
6376 | */ | |
09492498 VS |
6377 | cdctl = I915_READ(CDCLK_CTL); |
6378 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
6379 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6380 | if (cdctl == expected) | |
c73666f3 | 6381 | /* All well; nothing to sanitize */ |
9f7eb31a | 6382 | return; |
c89e39f3 | 6383 | |
9f7eb31a VS |
6384 | sanitize: |
6385 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 6386 | |
9f7eb31a VS |
6387 | /* force cdclk programming */ |
6388 | dev_priv->cdclk_freq = 0; | |
6389 | /* force full PLL disable + enable */ | |
63911d72 | 6390 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
6391 | } |
6392 | ||
30a970c6 JB |
6393 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
6394 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
6395 | { | |
fac5e23e | 6396 | struct drm_i915_private *dev_priv = to_i915(dev); |
30a970c6 JB |
6397 | u32 val, cmd; |
6398 | ||
1353c4fb | 6399 | WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) |
164dfd28 | 6400 | != dev_priv->cdclk_freq); |
d60c4473 | 6401 | |
dfcab17e | 6402 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 6403 | cmd = 2; |
dfcab17e | 6404 | else if (cdclk == 266667) |
30a970c6 JB |
6405 | cmd = 1; |
6406 | else | |
6407 | cmd = 0; | |
6408 | ||
6409 | mutex_lock(&dev_priv->rps.hw_lock); | |
6410 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6411 | val &= ~DSPFREQGUAR_MASK; | |
6412 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
6413 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6414 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6415 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
6416 | 50)) { | |
6417 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6418 | } | |
6419 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6420 | ||
54433e91 VS |
6421 | mutex_lock(&dev_priv->sb_lock); |
6422 | ||
dfcab17e | 6423 | if (cdclk == 400000) { |
6bcda4f0 | 6424 | u32 divider; |
30a970c6 | 6425 | |
6bcda4f0 | 6426 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 6427 | |
30a970c6 JB |
6428 | /* adjust cdclk divider */ |
6429 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 6430 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
6431 | val |= divider; |
6432 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
6433 | |
6434 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 6435 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
6436 | 50)) |
6437 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
6438 | } |
6439 | ||
30a970c6 JB |
6440 | /* adjust self-refresh exit latency value */ |
6441 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
6442 | val &= ~0x7f; | |
6443 | ||
6444 | /* | |
6445 | * For high bandwidth configs, we set a higher latency in the bunit | |
6446 | * so that the core display fetch happens in time to avoid underruns. | |
6447 | */ | |
dfcab17e | 6448 | if (cdclk == 400000) |
30a970c6 JB |
6449 | val |= 4500 / 250; /* 4.5 usec */ |
6450 | else | |
6451 | val |= 3000 / 250; /* 3.0 usec */ | |
6452 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 6453 | |
a580516d | 6454 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 6455 | |
4c75b940 | 6456 | intel_update_cdclk(dev_priv); |
30a970c6 JB |
6457 | } |
6458 | ||
383c5a6a VS |
6459 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
6460 | { | |
fac5e23e | 6461 | struct drm_i915_private *dev_priv = to_i915(dev); |
383c5a6a VS |
6462 | u32 val, cmd; |
6463 | ||
1353c4fb | 6464 | WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) |
164dfd28 | 6465 | != dev_priv->cdclk_freq); |
383c5a6a VS |
6466 | |
6467 | switch (cdclk) { | |
383c5a6a VS |
6468 | case 333333: |
6469 | case 320000: | |
383c5a6a | 6470 | case 266667: |
383c5a6a | 6471 | case 200000: |
383c5a6a VS |
6472 | break; |
6473 | default: | |
5f77eeb0 | 6474 | MISSING_CASE(cdclk); |
383c5a6a VS |
6475 | return; |
6476 | } | |
6477 | ||
9d0d3fda VS |
6478 | /* |
6479 | * Specs are full of misinformation, but testing on actual | |
6480 | * hardware has shown that we just need to write the desired | |
6481 | * CCK divider into the Punit register. | |
6482 | */ | |
6483 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6484 | ||
383c5a6a VS |
6485 | mutex_lock(&dev_priv->rps.hw_lock); |
6486 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6487 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6488 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6489 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6490 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6491 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6492 | 50)) { | |
6493 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6494 | } | |
6495 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6496 | ||
4c75b940 | 6497 | intel_update_cdclk(dev_priv); |
383c5a6a VS |
6498 | } |
6499 | ||
30a970c6 JB |
6500 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6501 | int max_pixclk) | |
6502 | { | |
6bcda4f0 | 6503 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6504 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6505 | |
30a970c6 JB |
6506 | /* |
6507 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6508 | * 200MHz | |
6509 | * 267MHz | |
29dc7ef3 | 6510 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6511 | * 400MHz (VLV only) |
6512 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6513 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6514 | * |
6515 | * We seem to get an unstable or solid color picture at 200MHz. | |
6516 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6517 | * are off. | |
30a970c6 | 6518 | */ |
6cca3195 VS |
6519 | if (!IS_CHERRYVIEW(dev_priv) && |
6520 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6521 | return 400000; |
6cca3195 | 6522 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6523 | return freq_320; |
e37c67a1 | 6524 | else if (max_pixclk > 0) |
dfcab17e | 6525 | return 266667; |
e37c67a1 VS |
6526 | else |
6527 | return 200000; | |
30a970c6 JB |
6528 | } |
6529 | ||
324513c0 | 6530 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 6531 | { |
760e1477 | 6532 | if (max_pixclk > 576000) |
f8437dd1 | 6533 | return 624000; |
760e1477 | 6534 | else if (max_pixclk > 384000) |
f8437dd1 | 6535 | return 576000; |
760e1477 | 6536 | else if (max_pixclk > 288000) |
f8437dd1 | 6537 | return 384000; |
760e1477 | 6538 | else if (max_pixclk > 144000) |
f8437dd1 VK |
6539 | return 288000; |
6540 | else | |
6541 | return 144000; | |
6542 | } | |
6543 | ||
e8788cbc | 6544 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6545 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6546 | struct drm_atomic_state *state) | |
30a970c6 | 6547 | { |
565602d7 | 6548 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 6549 | struct drm_i915_private *dev_priv = to_i915(dev); |
565602d7 ML |
6550 | struct drm_crtc *crtc; |
6551 | struct drm_crtc_state *crtc_state; | |
6552 | unsigned max_pixclk = 0, i; | |
6553 | enum pipe pipe; | |
30a970c6 | 6554 | |
565602d7 ML |
6555 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6556 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6557 | |
565602d7 ML |
6558 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6559 | int pixclk = 0; | |
6560 | ||
6561 | if (crtc_state->enable) | |
6562 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6563 | |
565602d7 | 6564 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6565 | } |
6566 | ||
565602d7 ML |
6567 | for_each_pipe(dev_priv, pipe) |
6568 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6569 | ||
30a970c6 JB |
6570 | return max_pixclk; |
6571 | } | |
6572 | ||
27c329ed | 6573 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6574 | { |
27c329ed | 6575 | struct drm_device *dev = state->dev; |
fac5e23e | 6576 | struct drm_i915_private *dev_priv = to_i915(dev); |
27c329ed | 6577 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
6578 | struct intel_atomic_state *intel_state = |
6579 | to_intel_atomic_state(state); | |
30a970c6 | 6580 | |
1a617b77 | 6581 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6582 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6583 | |
1a617b77 ML |
6584 | if (!intel_state->active_crtcs) |
6585 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6586 | ||
27c329ed ML |
6587 | return 0; |
6588 | } | |
304603f4 | 6589 | |
324513c0 | 6590 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6591 | { |
4e5ca60f | 6592 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6593 | struct intel_atomic_state *intel_state = |
6594 | to_intel_atomic_state(state); | |
85a96e7a | 6595 | |
1a617b77 | 6596 | intel_state->cdclk = intel_state->dev_cdclk = |
324513c0 | 6597 | bxt_calc_cdclk(max_pixclk); |
85a96e7a | 6598 | |
1a617b77 | 6599 | if (!intel_state->active_crtcs) |
324513c0 | 6600 | intel_state->dev_cdclk = bxt_calc_cdclk(0); |
1a617b77 | 6601 | |
27c329ed | 6602 | return 0; |
30a970c6 JB |
6603 | } |
6604 | ||
1e69cd74 VS |
6605 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6606 | { | |
6607 | unsigned int credits, default_credits; | |
6608 | ||
6609 | if (IS_CHERRYVIEW(dev_priv)) | |
6610 | default_credits = PFI_CREDIT(12); | |
6611 | else | |
6612 | default_credits = PFI_CREDIT(8); | |
6613 | ||
bfa7df01 | 6614 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6615 | /* CHV suggested value is 31 or 63 */ |
6616 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6617 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6618 | else |
6619 | credits = PFI_CREDIT(15); | |
6620 | } else { | |
6621 | credits = default_credits; | |
6622 | } | |
6623 | ||
6624 | /* | |
6625 | * WA - write default credits before re-programming | |
6626 | * FIXME: should we also set the resend bit here? | |
6627 | */ | |
6628 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6629 | default_credits); | |
6630 | ||
6631 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6632 | credits | PFI_CREDIT_RESEND); | |
6633 | ||
6634 | /* | |
6635 | * FIXME is this guaranteed to clear | |
6636 | * immediately or should we poll for it? | |
6637 | */ | |
6638 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6639 | } | |
6640 | ||
27c329ed | 6641 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6642 | { |
a821fc46 | 6643 | struct drm_device *dev = old_state->dev; |
fac5e23e | 6644 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 ML |
6645 | struct intel_atomic_state *old_intel_state = |
6646 | to_intel_atomic_state(old_state); | |
6647 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6648 | |
27c329ed ML |
6649 | /* |
6650 | * FIXME: We can end up here with all power domains off, yet | |
6651 | * with a CDCLK frequency other than the minimum. To account | |
6652 | * for this take the PIPE-A power domain, which covers the HW | |
6653 | * blocks needed for the following programming. This can be | |
6654 | * removed once it's guaranteed that we get here either with | |
6655 | * the minimum CDCLK set, or the required power domains | |
6656 | * enabled. | |
6657 | */ | |
6658 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6659 | |
920a14b2 | 6660 | if (IS_CHERRYVIEW(dev_priv)) |
27c329ed ML |
6661 | cherryview_set_cdclk(dev, req_cdclk); |
6662 | else | |
6663 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6664 | |
27c329ed | 6665 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6666 | |
27c329ed | 6667 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6668 | } |
6669 | ||
4a806558 ML |
6670 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
6671 | struct drm_atomic_state *old_state) | |
89b667f8 | 6672 | { |
4a806558 | 6673 | struct drm_crtc *crtc = pipe_config->base.crtc; |
89b667f8 | 6674 | struct drm_device *dev = crtc->dev; |
a72e4c9f | 6675 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 | 6676 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
89b667f8 | 6677 | int pipe = intel_crtc->pipe; |
89b667f8 | 6678 | |
53d9f4e9 | 6679 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6680 | return; |
6681 | ||
37a5650b | 6682 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6683 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6684 | |
6685 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6686 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6687 | |
920a14b2 | 6688 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
fac5e23e | 6689 | struct drm_i915_private *dev_priv = to_i915(dev); |
c14b0485 VS |
6690 | |
6691 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6692 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6693 | } | |
6694 | ||
5b18e57c DV |
6695 | i9xx_set_pipeconf(intel_crtc); |
6696 | ||
89b667f8 | 6697 | intel_crtc->active = true; |
89b667f8 | 6698 | |
a72e4c9f | 6699 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6700 | |
fd6bbda9 | 6701 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
89b667f8 | 6702 | |
920a14b2 | 6703 | if (IS_CHERRYVIEW(dev_priv)) { |
cd2d34d9 VS |
6704 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
6705 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6706 | } else { | |
6707 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6708 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6709 | } |
89b667f8 | 6710 | |
fd6bbda9 | 6711 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
89b667f8 | 6712 | |
2dd24552 JB |
6713 | i9xx_pfit_enable(intel_crtc); |
6714 | ||
b95c5321 | 6715 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6716 | |
432081bc | 6717 | intel_update_watermarks(intel_crtc); |
e1fdc473 | 6718 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6719 | |
4b3a9526 VS |
6720 | assert_vblank_disabled(crtc); |
6721 | drm_crtc_vblank_on(crtc); | |
6722 | ||
fd6bbda9 | 6723 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b667f8 JB |
6724 | } |
6725 | ||
f13c2ef3 DV |
6726 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6727 | { | |
6728 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6729 | struct drm_i915_private *dev_priv = to_i915(dev); |
f13c2ef3 | 6730 | |
6e3c9717 ACO |
6731 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6732 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6733 | } |
6734 | ||
4a806558 ML |
6735 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
6736 | struct drm_atomic_state *old_state) | |
79e53945 | 6737 | { |
4a806558 | 6738 | struct drm_crtc *crtc = pipe_config->base.crtc; |
79e53945 | 6739 | struct drm_device *dev = crtc->dev; |
a72e4c9f | 6740 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6741 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cd2d34d9 | 6742 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6743 | |
53d9f4e9 | 6744 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6745 | return; |
6746 | ||
f13c2ef3 DV |
6747 | i9xx_set_pll_dividers(intel_crtc); |
6748 | ||
37a5650b | 6749 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6750 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6751 | |
6752 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6753 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6754 | |
5b18e57c DV |
6755 | i9xx_set_pipeconf(intel_crtc); |
6756 | ||
f7abfe8b | 6757 | intel_crtc->active = true; |
6b383a7f | 6758 | |
5db94019 | 6759 | if (!IS_GEN2(dev_priv)) |
a72e4c9f | 6760 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6761 | |
fd6bbda9 | 6762 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
9d6d9f19 | 6763 | |
f6736a1a DV |
6764 | i9xx_enable_pll(intel_crtc); |
6765 | ||
2dd24552 JB |
6766 | i9xx_pfit_enable(intel_crtc); |
6767 | ||
b95c5321 | 6768 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6769 | |
432081bc | 6770 | intel_update_watermarks(intel_crtc); |
e1fdc473 | 6771 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6772 | |
4b3a9526 VS |
6773 | assert_vblank_disabled(crtc); |
6774 | drm_crtc_vblank_on(crtc); | |
6775 | ||
fd6bbda9 | 6776 | intel_encoders_enable(crtc, pipe_config, old_state); |
0b8765c6 | 6777 | } |
79e53945 | 6778 | |
87476d63 DV |
6779 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6780 | { | |
6781 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6782 | struct drm_i915_private *dev_priv = to_i915(dev); |
87476d63 | 6783 | |
6e3c9717 | 6784 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6785 | return; |
87476d63 | 6786 | |
328d8e82 | 6787 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6788 | |
328d8e82 DV |
6789 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6790 | I915_READ(PFIT_CONTROL)); | |
6791 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6792 | } |
6793 | ||
4a806558 ML |
6794 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
6795 | struct drm_atomic_state *old_state) | |
0b8765c6 | 6796 | { |
4a806558 | 6797 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
0b8765c6 | 6798 | struct drm_device *dev = crtc->dev; |
fac5e23e | 6799 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b8765c6 JB |
6800 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6801 | int pipe = intel_crtc->pipe; | |
ef9c3aee | 6802 | |
6304cd91 VS |
6803 | /* |
6804 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6805 | * wait for planes to fully turn off before disabling the pipe. | |
6806 | */ | |
5db94019 | 6807 | if (IS_GEN2(dev_priv)) |
0f0f74bc | 6808 | intel_wait_for_vblank(dev_priv, pipe); |
6304cd91 | 6809 | |
fd6bbda9 | 6810 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4b3a9526 | 6811 | |
f9b61ff6 DV |
6812 | drm_crtc_vblank_off(crtc); |
6813 | assert_vblank_disabled(crtc); | |
6814 | ||
575f7ab7 | 6815 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6816 | |
87476d63 | 6817 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6818 | |
fd6bbda9 | 6819 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
89b667f8 | 6820 | |
d7edc4e5 | 6821 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
920a14b2 | 6822 | if (IS_CHERRYVIEW(dev_priv)) |
076ed3b2 | 6823 | chv_disable_pll(dev_priv, pipe); |
11a914c2 | 6824 | else if (IS_VALLEYVIEW(dev_priv)) |
076ed3b2 CML |
6825 | vlv_disable_pll(dev_priv, pipe); |
6826 | else | |
1c4e0274 | 6827 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6828 | } |
0b8765c6 | 6829 | |
fd6bbda9 | 6830 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
d6db995f | 6831 | |
5db94019 | 6832 | if (!IS_GEN2(dev_priv)) |
a72e4c9f | 6833 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6834 | } |
6835 | ||
b17d48e2 ML |
6836 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6837 | { | |
842e0307 | 6838 | struct intel_encoder *encoder; |
b17d48e2 ML |
6839 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6840 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6841 | enum intel_display_power_domain domain; | |
6842 | unsigned long domains; | |
4a806558 ML |
6843 | struct drm_atomic_state *state; |
6844 | struct intel_crtc_state *crtc_state; | |
6845 | int ret; | |
b17d48e2 ML |
6846 | |
6847 | if (!intel_crtc->active) | |
6848 | return; | |
6849 | ||
936e71e3 | 6850 | if (to_intel_plane_state(crtc->primary->state)->base.visible) { |
5a21b665 | 6851 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6852 | |
2622a081 | 6853 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6854 | |
6855 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
936e71e3 | 6856 | to_intel_plane_state(crtc->primary->state)->base.visible = false; |
a539205a ML |
6857 | } |
6858 | ||
4a806558 ML |
6859 | state = drm_atomic_state_alloc(crtc->dev); |
6860 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; | |
6861 | ||
6862 | /* Everything's already locked, -EDEADLK can't happen. */ | |
6863 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
6864 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
6865 | ||
6866 | WARN_ON(IS_ERR(crtc_state) || ret); | |
6867 | ||
6868 | dev_priv->display.crtc_disable(crtc_state, state); | |
6869 | ||
0853695c | 6870 | drm_atomic_state_put(state); |
842e0307 | 6871 | |
78108b7c VS |
6872 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6873 | crtc->base.id, crtc->name); | |
842e0307 ML |
6874 | |
6875 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6876 | crtc->state->active = false; | |
37d9078b | 6877 | intel_crtc->active = false; |
842e0307 ML |
6878 | crtc->enabled = false; |
6879 | crtc->state->connector_mask = 0; | |
6880 | crtc->state->encoder_mask = 0; | |
6881 | ||
6882 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6883 | encoder->base.crtc = NULL; | |
6884 | ||
58f9c0bc | 6885 | intel_fbc_disable(intel_crtc); |
432081bc | 6886 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 6887 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6888 | |
6889 | domains = intel_crtc->enabled_power_domains; | |
6890 | for_each_power_domain(domain, domains) | |
6891 | intel_display_power_put(dev_priv, domain); | |
6892 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6893 | |
6894 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6895 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6896 | } |
6897 | ||
6b72d486 ML |
6898 | /* |
6899 | * turn all crtc's off, but do not adjust state | |
6900 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6901 | */ | |
70e0bd74 | 6902 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6903 | { |
e2c8b870 | 6904 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6905 | struct drm_atomic_state *state; |
e2c8b870 | 6906 | int ret; |
70e0bd74 | 6907 | |
e2c8b870 ML |
6908 | state = drm_atomic_helper_suspend(dev); |
6909 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6910 | if (ret) |
6911 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6912 | else |
6913 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6914 | return ret; |
ee7b9f93 JB |
6915 | } |
6916 | ||
ea5b213a | 6917 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6918 | { |
4ef69c7a | 6919 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6920 | |
ea5b213a CW |
6921 | drm_encoder_cleanup(encoder); |
6922 | kfree(intel_encoder); | |
7e7d76c3 JB |
6923 | } |
6924 | ||
0a91ca29 DV |
6925 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6926 | * internal consistency). */ | |
5a21b665 | 6927 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6928 | { |
5a21b665 | 6929 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6930 | |
6931 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6932 | connector->base.base.id, | |
6933 | connector->base.name); | |
6934 | ||
0a91ca29 | 6935 | if (connector->get_hw_state(connector)) { |
e85376cb | 6936 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6937 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6938 | |
35dd3c64 ML |
6939 | I915_STATE_WARN(!crtc, |
6940 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6941 | |
35dd3c64 ML |
6942 | if (!crtc) |
6943 | return; | |
6944 | ||
6945 | I915_STATE_WARN(!crtc->state->active, | |
6946 | "connector is active, but attached crtc isn't\n"); | |
6947 | ||
e85376cb | 6948 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6949 | return; |
6950 | ||
e85376cb | 6951 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6952 | "atomic encoder doesn't match attached encoder\n"); |
6953 | ||
e85376cb | 6954 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6955 | "attached encoder crtc differs from connector crtc\n"); |
6956 | } else { | |
4d688a2a ML |
6957 | I915_STATE_WARN(crtc && crtc->state->active, |
6958 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 6959 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 6960 | "best encoder set without crtc!\n"); |
0a91ca29 | 6961 | } |
79e53945 JB |
6962 | } |
6963 | ||
08d9bc92 ACO |
6964 | int intel_connector_init(struct intel_connector *connector) |
6965 | { | |
5350a031 | 6966 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6967 | |
5350a031 | 6968 | if (!connector->base.state) |
08d9bc92 ACO |
6969 | return -ENOMEM; |
6970 | ||
08d9bc92 ACO |
6971 | return 0; |
6972 | } | |
6973 | ||
6974 | struct intel_connector *intel_connector_alloc(void) | |
6975 | { | |
6976 | struct intel_connector *connector; | |
6977 | ||
6978 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6979 | if (!connector) | |
6980 | return NULL; | |
6981 | ||
6982 | if (intel_connector_init(connector) < 0) { | |
6983 | kfree(connector); | |
6984 | return NULL; | |
6985 | } | |
6986 | ||
6987 | return connector; | |
6988 | } | |
6989 | ||
f0947c37 DV |
6990 | /* Simple connector->get_hw_state implementation for encoders that support only |
6991 | * one connector and no cloning and hence the encoder state determines the state | |
6992 | * of the connector. */ | |
6993 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6994 | { |
24929352 | 6995 | enum pipe pipe = 0; |
f0947c37 | 6996 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6997 | |
f0947c37 | 6998 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6999 | } |
7000 | ||
6d293983 | 7001 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 7002 | { |
6d293983 ACO |
7003 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
7004 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
7005 | |
7006 | return 0; | |
7007 | } | |
7008 | ||
6d293983 | 7009 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 7010 | struct intel_crtc_state *pipe_config) |
1857e1da | 7011 | { |
8652744b | 7012 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
7013 | struct drm_atomic_state *state = pipe_config->base.state; |
7014 | struct intel_crtc *other_crtc; | |
7015 | struct intel_crtc_state *other_crtc_state; | |
7016 | ||
1857e1da DV |
7017 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
7018 | pipe_name(pipe), pipe_config->fdi_lanes); | |
7019 | if (pipe_config->fdi_lanes > 4) { | |
7020 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
7021 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7022 | return -EINVAL; |
1857e1da DV |
7023 | } |
7024 | ||
8652744b | 7025 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
7026 | if (pipe_config->fdi_lanes > 2) { |
7027 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
7028 | pipe_config->fdi_lanes); | |
6d293983 | 7029 | return -EINVAL; |
1857e1da | 7030 | } else { |
6d293983 | 7031 | return 0; |
1857e1da DV |
7032 | } |
7033 | } | |
7034 | ||
b7f05d4a | 7035 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 7036 | return 0; |
1857e1da DV |
7037 | |
7038 | /* Ivybridge 3 pipe is really complicated */ | |
7039 | switch (pipe) { | |
7040 | case PIPE_A: | |
6d293983 | 7041 | return 0; |
1857e1da | 7042 | case PIPE_B: |
6d293983 ACO |
7043 | if (pipe_config->fdi_lanes <= 2) |
7044 | return 0; | |
7045 | ||
b91eb5cc | 7046 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
7047 | other_crtc_state = |
7048 | intel_atomic_get_crtc_state(state, other_crtc); | |
7049 | if (IS_ERR(other_crtc_state)) | |
7050 | return PTR_ERR(other_crtc_state); | |
7051 | ||
7052 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
7053 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
7054 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7055 | return -EINVAL; |
1857e1da | 7056 | } |
6d293983 | 7057 | return 0; |
1857e1da | 7058 | case PIPE_C: |
251cc67c VS |
7059 | if (pipe_config->fdi_lanes > 2) { |
7060 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
7061 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7062 | return -EINVAL; |
251cc67c | 7063 | } |
6d293983 | 7064 | |
b91eb5cc | 7065 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
7066 | other_crtc_state = |
7067 | intel_atomic_get_crtc_state(state, other_crtc); | |
7068 | if (IS_ERR(other_crtc_state)) | |
7069 | return PTR_ERR(other_crtc_state); | |
7070 | ||
7071 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 7072 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 7073 | return -EINVAL; |
1857e1da | 7074 | } |
6d293983 | 7075 | return 0; |
1857e1da DV |
7076 | default: |
7077 | BUG(); | |
7078 | } | |
7079 | } | |
7080 | ||
e29c22c0 DV |
7081 | #define RETRY 1 |
7082 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 7083 | struct intel_crtc_state *pipe_config) |
877d48d5 | 7084 | { |
1857e1da | 7085 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 7086 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
7087 | int lane, link_bw, fdi_dotclock, ret; |
7088 | bool needs_recompute = false; | |
877d48d5 | 7089 | |
e29c22c0 | 7090 | retry: |
877d48d5 DV |
7091 | /* FDI is a binary signal running at ~2.7GHz, encoding |
7092 | * each output octet as 10 bits. The actual frequency | |
7093 | * is stored as a divider into a 100MHz clock, and the | |
7094 | * mode pixel clock is stored in units of 1KHz. | |
7095 | * Hence the bw of each lane in terms of the mode signal | |
7096 | * is: | |
7097 | */ | |
21a727b3 | 7098 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 7099 | |
241bfc38 | 7100 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 7101 | |
2bd89a07 | 7102 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
7103 | pipe_config->pipe_bpp); |
7104 | ||
7105 | pipe_config->fdi_lanes = lane; | |
7106 | ||
2bd89a07 | 7107 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 7108 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 7109 | |
e3b247da | 7110 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 7111 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
7112 | pipe_config->pipe_bpp -= 2*3; |
7113 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
7114 | pipe_config->pipe_bpp); | |
7115 | needs_recompute = true; | |
7116 | pipe_config->bw_constrained = true; | |
7117 | ||
7118 | goto retry; | |
7119 | } | |
7120 | ||
7121 | if (needs_recompute) | |
7122 | return RETRY; | |
7123 | ||
6d293983 | 7124 | return ret; |
877d48d5 DV |
7125 | } |
7126 | ||
8cfb3407 VS |
7127 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
7128 | struct intel_crtc_state *pipe_config) | |
7129 | { | |
7130 | if (pipe_config->pipe_bpp > 24) | |
7131 | return false; | |
7132 | ||
7133 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 7134 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
7135 | return true; |
7136 | ||
7137 | /* | |
b432e5cf VS |
7138 | * We compare against max which means we must take |
7139 | * the increased cdclk requirement into account when | |
7140 | * calculating the new cdclk. | |
7141 | * | |
7142 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
7143 | */ |
7144 | return ilk_pipe_pixel_rate(pipe_config) <= | |
7145 | dev_priv->max_cdclk_freq * 95 / 100; | |
7146 | } | |
7147 | ||
42db64ef | 7148 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 7149 | struct intel_crtc_state *pipe_config) |
42db64ef | 7150 | { |
8cfb3407 | 7151 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7152 | struct drm_i915_private *dev_priv = to_i915(dev); |
8cfb3407 | 7153 | |
d330a953 | 7154 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
7155 | hsw_crtc_supports_ips(crtc) && |
7156 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
7157 | } |
7158 | ||
39acb4aa VS |
7159 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
7160 | { | |
7161 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7162 | ||
7163 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
7164 | return INTEL_INFO(dev_priv)->gen < 4 && | |
7165 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
7166 | } | |
7167 | ||
a43f6e0f | 7168 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 7169 | struct intel_crtc_state *pipe_config) |
79e53945 | 7170 | { |
a43f6e0f | 7171 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7172 | struct drm_i915_private *dev_priv = to_i915(dev); |
7c5f93b0 | 7173 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 7174 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 7175 | |
6315b5d3 | 7176 | if (INTEL_GEN(dev_priv) < 4) { |
f3261156 | 7177 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
7178 | |
7179 | /* | |
39acb4aa | 7180 | * Enable double wide mode when the dot clock |
cf532bb2 | 7181 | * is > 90% of the (display) core speed. |
cf532bb2 | 7182 | */ |
39acb4aa VS |
7183 | if (intel_crtc_supports_double_wide(crtc) && |
7184 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 7185 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 7186 | pipe_config->double_wide = true; |
ad3a4479 | 7187 | } |
f3261156 | 7188 | } |
ad3a4479 | 7189 | |
f3261156 VS |
7190 | if (adjusted_mode->crtc_clock > clock_limit) { |
7191 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
7192 | adjusted_mode->crtc_clock, clock_limit, | |
7193 | yesno(pipe_config->double_wide)); | |
7194 | return -EINVAL; | |
2c07245f | 7195 | } |
89749350 | 7196 | |
1d1d0e27 VS |
7197 | /* |
7198 | * Pipe horizontal size must be even in: | |
7199 | * - DVO ganged mode | |
7200 | * - LVDS dual channel mode | |
7201 | * - Double wide pipe | |
7202 | */ | |
2d84d2b3 | 7203 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
7204 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
7205 | pipe_config->pipe_src_w &= ~1; | |
7206 | ||
8693a824 DL |
7207 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
7208 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 | 7209 | */ |
9beb5fea | 7210 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && |
aad941d5 | 7211 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 7212 | return -EINVAL; |
44f46b42 | 7213 | |
50a0bc90 | 7214 | if (HAS_IPS(dev_priv)) |
a43f6e0f DV |
7215 | hsw_compute_ips_config(crtc, pipe_config); |
7216 | ||
877d48d5 | 7217 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 7218 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 7219 | |
cf5a15be | 7220 | return 0; |
79e53945 JB |
7221 | } |
7222 | ||
1353c4fb | 7223 | static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7224 | { |
1353c4fb | 7225 | u32 cdctl; |
1652d19e | 7226 | |
ea61791e | 7227 | skl_dpll0_update(dev_priv); |
1652d19e | 7228 | |
63911d72 | 7229 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 7230 | return dev_priv->cdclk_pll.ref; |
1652d19e | 7231 | |
ea61791e | 7232 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 7233 | |
63911d72 | 7234 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
7235 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7236 | case CDCLK_FREQ_450_432: | |
7237 | return 432000; | |
7238 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 7239 | return 308571; |
ea61791e VS |
7240 | case CDCLK_FREQ_540: |
7241 | return 540000; | |
1652d19e | 7242 | case CDCLK_FREQ_675_617: |
487ed2e4 | 7243 | return 617143; |
1652d19e | 7244 | default: |
ea61791e | 7245 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7246 | } |
7247 | } else { | |
1652d19e VS |
7248 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7249 | case CDCLK_FREQ_450_432: | |
7250 | return 450000; | |
7251 | case CDCLK_FREQ_337_308: | |
7252 | return 337500; | |
ea61791e VS |
7253 | case CDCLK_FREQ_540: |
7254 | return 540000; | |
1652d19e VS |
7255 | case CDCLK_FREQ_675_617: |
7256 | return 675000; | |
7257 | default: | |
ea61791e | 7258 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7259 | } |
7260 | } | |
7261 | ||
709e05c3 | 7262 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
7263 | } |
7264 | ||
83d7c81f VS |
7265 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
7266 | { | |
7267 | u32 val; | |
7268 | ||
7269 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 7270 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
7271 | |
7272 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 7273 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 7274 | return; |
83d7c81f | 7275 | |
1c3f7700 ID |
7276 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
7277 | return; | |
83d7c81f VS |
7278 | |
7279 | val = I915_READ(BXT_DE_PLL_CTL); | |
7280 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
7281 | dev_priv->cdclk_pll.ref; | |
7282 | } | |
7283 | ||
1353c4fb | 7284 | static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv) |
acd3f3d3 | 7285 | { |
f5986242 VS |
7286 | u32 divider; |
7287 | int div, vco; | |
acd3f3d3 | 7288 | |
83d7c81f VS |
7289 | bxt_de_pll_update(dev_priv); |
7290 | ||
f5986242 VS |
7291 | vco = dev_priv->cdclk_pll.vco; |
7292 | if (vco == 0) | |
7293 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 7294 | |
f5986242 | 7295 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 7296 | |
f5986242 | 7297 | switch (divider) { |
acd3f3d3 | 7298 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
7299 | div = 2; |
7300 | break; | |
acd3f3d3 | 7301 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
f5986242 VS |
7302 | div = 3; |
7303 | break; | |
acd3f3d3 | 7304 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
7305 | div = 4; |
7306 | break; | |
acd3f3d3 | 7307 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
7308 | div = 8; |
7309 | break; | |
7310 | default: | |
7311 | MISSING_CASE(divider); | |
7312 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
7313 | } |
7314 | ||
f5986242 | 7315 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
7316 | } |
7317 | ||
1353c4fb | 7318 | static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7319 | { |
1652d19e VS |
7320 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7321 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7322 | ||
7323 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7324 | return 800000; | |
7325 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7326 | return 450000; | |
7327 | else if (freq == LCPLL_CLK_FREQ_450) | |
7328 | return 450000; | |
7329 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
7330 | return 540000; | |
7331 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
7332 | return 337500; | |
7333 | else | |
7334 | return 675000; | |
7335 | } | |
7336 | ||
1353c4fb | 7337 | static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7338 | { |
1652d19e VS |
7339 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7340 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7341 | ||
7342 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7343 | return 800000; | |
7344 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7345 | return 450000; | |
7346 | else if (freq == LCPLL_CLK_FREQ_450) | |
7347 | return 450000; | |
50a0bc90 | 7348 | else if (IS_HSW_ULT(dev_priv)) |
1652d19e VS |
7349 | return 337500; |
7350 | else | |
7351 | return 540000; | |
79e53945 JB |
7352 | } |
7353 | ||
1353c4fb | 7354 | static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv) |
25eb05fc | 7355 | { |
1353c4fb | 7356 | return vlv_get_cck_clock_hpll(dev_priv, "cdclk", |
bfa7df01 | 7357 | CCK_DISPLAY_CLOCK_CONTROL); |
25eb05fc JB |
7358 | } |
7359 | ||
1353c4fb | 7360 | static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv) |
b37a6434 VS |
7361 | { |
7362 | return 450000; | |
7363 | } | |
7364 | ||
1353c4fb | 7365 | static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 JB |
7366 | { |
7367 | return 400000; | |
7368 | } | |
79e53945 | 7369 | |
1353c4fb | 7370 | static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv) |
79e53945 | 7371 | { |
e907f170 | 7372 | return 333333; |
e70236a8 | 7373 | } |
79e53945 | 7374 | |
1353c4fb | 7375 | static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 JB |
7376 | { |
7377 | return 200000; | |
7378 | } | |
79e53945 | 7379 | |
1353c4fb | 7380 | static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv) |
257a7ffc | 7381 | { |
1353c4fb | 7382 | struct pci_dev *pdev = dev_priv->drm.pdev; |
257a7ffc DV |
7383 | u16 gcfgc = 0; |
7384 | ||
52a05c30 | 7385 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
257a7ffc DV |
7386 | |
7387 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7388 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 7389 | return 266667; |
257a7ffc | 7390 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 7391 | return 333333; |
257a7ffc | 7392 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 7393 | return 444444; |
257a7ffc DV |
7394 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
7395 | return 200000; | |
7396 | default: | |
7397 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
7398 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 7399 | return 133333; |
257a7ffc | 7400 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 7401 | return 166667; |
257a7ffc DV |
7402 | } |
7403 | } | |
7404 | ||
1353c4fb | 7405 | static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7406 | { |
1353c4fb | 7407 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e70236a8 | 7408 | u16 gcfgc = 0; |
79e53945 | 7409 | |
52a05c30 | 7410 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
e70236a8 JB |
7411 | |
7412 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 7413 | return 133333; |
e70236a8 JB |
7414 | else { |
7415 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7416 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 7417 | return 333333; |
e70236a8 JB |
7418 | default: |
7419 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
7420 | return 190000; | |
79e53945 | 7421 | } |
e70236a8 JB |
7422 | } |
7423 | } | |
7424 | ||
1353c4fb | 7425 | static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7426 | { |
e907f170 | 7427 | return 266667; |
e70236a8 JB |
7428 | } |
7429 | ||
1353c4fb | 7430 | static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7431 | { |
1353c4fb | 7432 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e70236a8 | 7433 | u16 hpllcc = 0; |
1b1d2716 | 7434 | |
65cd2b3f VS |
7435 | /* |
7436 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
7437 | * encoding is different :( | |
7438 | * FIXME is this the right way to detect 852GM/852GMV? | |
7439 | */ | |
52a05c30 | 7440 | if (pdev->revision == 0x1) |
65cd2b3f VS |
7441 | return 133333; |
7442 | ||
52a05c30 | 7443 | pci_bus_read_config_word(pdev->bus, |
1b1d2716 VS |
7444 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); |
7445 | ||
e70236a8 JB |
7446 | /* Assume that the hardware is in the high speed state. This |
7447 | * should be the default. | |
7448 | */ | |
7449 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
7450 | case GC_CLOCK_133_200: | |
1b1d2716 | 7451 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
7452 | case GC_CLOCK_100_200: |
7453 | return 200000; | |
7454 | case GC_CLOCK_166_250: | |
7455 | return 250000; | |
7456 | case GC_CLOCK_100_133: | |
e907f170 | 7457 | return 133333; |
1b1d2716 VS |
7458 | case GC_CLOCK_133_266: |
7459 | case GC_CLOCK_133_266_2: | |
7460 | case GC_CLOCK_166_266: | |
7461 | return 266667; | |
e70236a8 | 7462 | } |
79e53945 | 7463 | |
e70236a8 JB |
7464 | /* Shouldn't happen */ |
7465 | return 0; | |
7466 | } | |
79e53945 | 7467 | |
1353c4fb | 7468 | static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7469 | { |
e907f170 | 7470 | return 133333; |
79e53945 JB |
7471 | } |
7472 | ||
1353c4fb | 7473 | static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) |
34edce2f | 7474 | { |
34edce2f VS |
7475 | static const unsigned int blb_vco[8] = { |
7476 | [0] = 3200000, | |
7477 | [1] = 4000000, | |
7478 | [2] = 5333333, | |
7479 | [3] = 4800000, | |
7480 | [4] = 6400000, | |
7481 | }; | |
7482 | static const unsigned int pnv_vco[8] = { | |
7483 | [0] = 3200000, | |
7484 | [1] = 4000000, | |
7485 | [2] = 5333333, | |
7486 | [3] = 4800000, | |
7487 | [4] = 2666667, | |
7488 | }; | |
7489 | static const unsigned int cl_vco[8] = { | |
7490 | [0] = 3200000, | |
7491 | [1] = 4000000, | |
7492 | [2] = 5333333, | |
7493 | [3] = 6400000, | |
7494 | [4] = 3333333, | |
7495 | [5] = 3566667, | |
7496 | [6] = 4266667, | |
7497 | }; | |
7498 | static const unsigned int elk_vco[8] = { | |
7499 | [0] = 3200000, | |
7500 | [1] = 4000000, | |
7501 | [2] = 5333333, | |
7502 | [3] = 4800000, | |
7503 | }; | |
7504 | static const unsigned int ctg_vco[8] = { | |
7505 | [0] = 3200000, | |
7506 | [1] = 4000000, | |
7507 | [2] = 5333333, | |
7508 | [3] = 6400000, | |
7509 | [4] = 2666667, | |
7510 | [5] = 4266667, | |
7511 | }; | |
7512 | const unsigned int *vco_table; | |
7513 | unsigned int vco; | |
7514 | uint8_t tmp = 0; | |
7515 | ||
7516 | /* FIXME other chipsets? */ | |
50a0bc90 | 7517 | if (IS_GM45(dev_priv)) |
34edce2f | 7518 | vco_table = ctg_vco; |
9beb5fea | 7519 | else if (IS_G4X(dev_priv)) |
34edce2f | 7520 | vco_table = elk_vco; |
1353c4fb | 7521 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f | 7522 | vco_table = cl_vco; |
1353c4fb | 7523 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f | 7524 | vco_table = pnv_vco; |
1353c4fb | 7525 | else if (IS_G33(dev_priv)) |
34edce2f VS |
7526 | vco_table = blb_vco; |
7527 | else | |
7528 | return 0; | |
7529 | ||
1353c4fb | 7530 | tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); |
34edce2f VS |
7531 | |
7532 | vco = vco_table[tmp & 0x7]; | |
7533 | if (vco == 0) | |
7534 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7535 | else | |
7536 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7537 | ||
7538 | return vco; | |
7539 | } | |
7540 | ||
1353c4fb | 7541 | static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7542 | { |
1353c4fb VS |
7543 | struct pci_dev *pdev = dev_priv->drm.pdev; |
7544 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); | |
34edce2f VS |
7545 | uint16_t tmp = 0; |
7546 | ||
52a05c30 | 7547 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7548 | |
7549 | cdclk_sel = (tmp >> 12) & 0x1; | |
7550 | ||
7551 | switch (vco) { | |
7552 | case 2666667: | |
7553 | case 4000000: | |
7554 | case 5333333: | |
7555 | return cdclk_sel ? 333333 : 222222; | |
7556 | case 3200000: | |
7557 | return cdclk_sel ? 320000 : 228571; | |
7558 | default: | |
7559 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7560 | return 222222; | |
7561 | } | |
7562 | } | |
7563 | ||
1353c4fb | 7564 | static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7565 | { |
1353c4fb | 7566 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34edce2f VS |
7567 | static const uint8_t div_3200[] = { 16, 10, 8 }; |
7568 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7569 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7570 | const uint8_t *div_table; | |
1353c4fb | 7571 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); |
34edce2f VS |
7572 | uint16_t tmp = 0; |
7573 | ||
52a05c30 | 7574 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7575 | |
7576 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7577 | ||
7578 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7579 | goto fail; | |
7580 | ||
7581 | switch (vco) { | |
7582 | case 3200000: | |
7583 | div_table = div_3200; | |
7584 | break; | |
7585 | case 4000000: | |
7586 | div_table = div_4000; | |
7587 | break; | |
7588 | case 5333333: | |
7589 | div_table = div_5333; | |
7590 | break; | |
7591 | default: | |
7592 | goto fail; | |
7593 | } | |
7594 | ||
7595 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7596 | ||
caf4e252 | 7597 | fail: |
34edce2f VS |
7598 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7599 | return 200000; | |
7600 | } | |
7601 | ||
1353c4fb | 7602 | static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7603 | { |
1353c4fb | 7604 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34edce2f VS |
7605 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; |
7606 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7607 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7608 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7609 | const uint8_t *div_table; | |
1353c4fb | 7610 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); |
34edce2f VS |
7611 | uint16_t tmp = 0; |
7612 | ||
52a05c30 | 7613 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7614 | |
7615 | cdclk_sel = (tmp >> 4) & 0x7; | |
7616 | ||
7617 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7618 | goto fail; | |
7619 | ||
7620 | switch (vco) { | |
7621 | case 3200000: | |
7622 | div_table = div_3200; | |
7623 | break; | |
7624 | case 4000000: | |
7625 | div_table = div_4000; | |
7626 | break; | |
7627 | case 4800000: | |
7628 | div_table = div_4800; | |
7629 | break; | |
7630 | case 5333333: | |
7631 | div_table = div_5333; | |
7632 | break; | |
7633 | default: | |
7634 | goto fail; | |
7635 | } | |
7636 | ||
7637 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7638 | ||
caf4e252 | 7639 | fail: |
34edce2f VS |
7640 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7641 | return 190476; | |
7642 | } | |
7643 | ||
2c07245f | 7644 | static void |
a65851af | 7645 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7646 | { |
a65851af VS |
7647 | while (*num > DATA_LINK_M_N_MASK || |
7648 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7649 | *num >>= 1; |
7650 | *den >>= 1; | |
7651 | } | |
7652 | } | |
7653 | ||
a65851af VS |
7654 | static void compute_m_n(unsigned int m, unsigned int n, |
7655 | uint32_t *ret_m, uint32_t *ret_n) | |
7656 | { | |
7657 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7658 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7659 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7660 | } | |
7661 | ||
e69d0bc1 DV |
7662 | void |
7663 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7664 | int pixel_clock, int link_clock, | |
7665 | struct intel_link_m_n *m_n) | |
2c07245f | 7666 | { |
e69d0bc1 | 7667 | m_n->tu = 64; |
a65851af VS |
7668 | |
7669 | compute_m_n(bits_per_pixel * pixel_clock, | |
7670 | link_clock * nlanes * 8, | |
7671 | &m_n->gmch_m, &m_n->gmch_n); | |
7672 | ||
7673 | compute_m_n(pixel_clock, link_clock, | |
7674 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7675 | } |
7676 | ||
a7615030 CW |
7677 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7678 | { | |
d330a953 JN |
7679 | if (i915.panel_use_ssc >= 0) |
7680 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7681 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7682 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7683 | } |
7684 | ||
7429e9d4 | 7685 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7686 | { |
7df00d7a | 7687 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7688 | } |
f47709a9 | 7689 | |
7429e9d4 DV |
7690 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7691 | { | |
7692 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7693 | } |
7694 | ||
f47709a9 | 7695 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7696 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7697 | struct dpll *reduced_clock) |
a7516a05 | 7698 | { |
9b1e14f4 | 7699 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
7700 | u32 fp, fp2 = 0; |
7701 | ||
9b1e14f4 | 7702 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 7703 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7704 | if (reduced_clock) |
7429e9d4 | 7705 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7706 | } else { |
190f68c5 | 7707 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7708 | if (reduced_clock) |
7429e9d4 | 7709 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7710 | } |
7711 | ||
190f68c5 | 7712 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7713 | |
f47709a9 | 7714 | crtc->lowfreq_avail = false; |
2d84d2b3 | 7715 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7716 | reduced_clock) { |
190f68c5 | 7717 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7718 | crtc->lowfreq_avail = true; |
a7516a05 | 7719 | } else { |
190f68c5 | 7720 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7721 | } |
7722 | } | |
7723 | ||
5e69f97f CML |
7724 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7725 | pipe) | |
89b667f8 JB |
7726 | { |
7727 | u32 reg_val; | |
7728 | ||
7729 | /* | |
7730 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7731 | * and set it to a reasonable value instead. | |
7732 | */ | |
ab3c759a | 7733 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7734 | reg_val &= 0xffffff00; |
7735 | reg_val |= 0x00000030; | |
ab3c759a | 7736 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7737 | |
ab3c759a | 7738 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7739 | reg_val &= 0x8cffffff; |
7740 | reg_val = 0x8c000000; | |
ab3c759a | 7741 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7742 | |
ab3c759a | 7743 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7744 | reg_val &= 0xffffff00; |
ab3c759a | 7745 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7746 | |
ab3c759a | 7747 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7748 | reg_val &= 0x00ffffff; |
7749 | reg_val |= 0xb0000000; | |
ab3c759a | 7750 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7751 | } |
7752 | ||
b551842d DV |
7753 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7754 | struct intel_link_m_n *m_n) | |
7755 | { | |
7756 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7757 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
7758 | int pipe = crtc->pipe; |
7759 | ||
e3b95f1e DV |
7760 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7761 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7762 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7763 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7764 | } |
7765 | ||
7766 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7767 | struct intel_link_m_n *m_n, |
7768 | struct intel_link_m_n *m2_n2) | |
b551842d | 7769 | { |
6315b5d3 | 7770 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 7771 | int pipe = crtc->pipe; |
6e3c9717 | 7772 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 7773 | |
6315b5d3 | 7774 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
7775 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7776 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7777 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7778 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7779 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7780 | * for gen < 8) and if DRRS is supported (to make sure the | |
7781 | * registers are not unnecessarily accessed). | |
7782 | */ | |
920a14b2 TU |
7783 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
7784 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
7785 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7786 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7787 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7788 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7789 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7790 | } | |
b551842d | 7791 | } else { |
e3b95f1e DV |
7792 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7793 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7794 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7795 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7796 | } |
7797 | } | |
7798 | ||
fe3cd48d | 7799 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7800 | { |
fe3cd48d R |
7801 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7802 | ||
7803 | if (m_n == M1_N1) { | |
7804 | dp_m_n = &crtc->config->dp_m_n; | |
7805 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7806 | } else if (m_n == M2_N2) { | |
7807 | ||
7808 | /* | |
7809 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7810 | * needs to be programmed into M1_N1. | |
7811 | */ | |
7812 | dp_m_n = &crtc->config->dp_m2_n2; | |
7813 | } else { | |
7814 | DRM_ERROR("Unsupported divider value\n"); | |
7815 | return; | |
7816 | } | |
7817 | ||
6e3c9717 ACO |
7818 | if (crtc->config->has_pch_encoder) |
7819 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7820 | else |
fe3cd48d | 7821 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7822 | } |
7823 | ||
251ac862 DV |
7824 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7825 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7826 | { |
03ed5cbf | 7827 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7828 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7829 | if (crtc->pipe != PIPE_A) |
7830 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7831 | |
cd2d34d9 | 7832 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7833 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7834 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7835 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7836 | ||
03ed5cbf VS |
7837 | pipe_config->dpll_hw_state.dpll_md = |
7838 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7839 | } | |
bdd4b6a6 | 7840 | |
03ed5cbf VS |
7841 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7842 | struct intel_crtc_state *pipe_config) | |
7843 | { | |
7844 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7845 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7846 | if (crtc->pipe != PIPE_A) |
7847 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7848 | ||
cd2d34d9 | 7849 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7850 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7851 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7852 | ||
03ed5cbf VS |
7853 | pipe_config->dpll_hw_state.dpll_md = |
7854 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7855 | } |
7856 | ||
d288f65f | 7857 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7858 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7859 | { |
f47709a9 | 7860 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7861 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7862 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7863 | u32 mdiv; |
a0c4da24 | 7864 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7865 | u32 coreclk, reg_val; |
a0c4da24 | 7866 | |
cd2d34d9 VS |
7867 | /* Enable Refclk */ |
7868 | I915_WRITE(DPLL(pipe), | |
7869 | pipe_config->dpll_hw_state.dpll & | |
7870 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7871 | ||
7872 | /* No need to actually set up the DPLL with DSI */ | |
7873 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7874 | return; | |
7875 | ||
a580516d | 7876 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7877 | |
d288f65f VS |
7878 | bestn = pipe_config->dpll.n; |
7879 | bestm1 = pipe_config->dpll.m1; | |
7880 | bestm2 = pipe_config->dpll.m2; | |
7881 | bestp1 = pipe_config->dpll.p1; | |
7882 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7883 | |
89b667f8 JB |
7884 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7885 | ||
7886 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7887 | if (pipe == PIPE_B) |
5e69f97f | 7888 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7889 | |
7890 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7891 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7892 | |
7893 | /* Disable target IRef on PLL */ | |
ab3c759a | 7894 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7895 | reg_val &= 0x00ffffff; |
ab3c759a | 7896 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7897 | |
7898 | /* Disable fast lock */ | |
ab3c759a | 7899 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7900 | |
7901 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7902 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7903 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7904 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7905 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7906 | |
7907 | /* | |
7908 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7909 | * but we don't support that). | |
7910 | * Note: don't use the DAC post divider as it seems unstable. | |
7911 | */ | |
7912 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7913 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7914 | |
a0c4da24 | 7915 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7916 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7917 | |
89b667f8 | 7918 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7919 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
7920 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
7921 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7922 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7923 | 0x009f0003); |
89b667f8 | 7924 | else |
ab3c759a | 7925 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7926 | 0x00d0000f); |
7927 | ||
37a5650b | 7928 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 7929 | /* Use SSC source */ |
bdd4b6a6 | 7930 | if (pipe == PIPE_A) |
ab3c759a | 7931 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7932 | 0x0df40000); |
7933 | else | |
ab3c759a | 7934 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7935 | 0x0df70000); |
7936 | } else { /* HDMI or VGA */ | |
7937 | /* Use bend source */ | |
bdd4b6a6 | 7938 | if (pipe == PIPE_A) |
ab3c759a | 7939 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7940 | 0x0df70000); |
7941 | else | |
ab3c759a | 7942 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7943 | 0x0df40000); |
7944 | } | |
a0c4da24 | 7945 | |
ab3c759a | 7946 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7947 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 7948 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 7949 | coreclk |= 0x01000000; |
ab3c759a | 7950 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7951 | |
ab3c759a | 7952 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7953 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7954 | } |
7955 | ||
d288f65f | 7956 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7957 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7958 | { |
7959 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7960 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7961 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7962 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7963 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7964 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7965 | u32 dpio_val; |
9cbe40c1 | 7966 | int vco; |
9d556c99 | 7967 | |
cd2d34d9 VS |
7968 | /* Enable Refclk and SSC */ |
7969 | I915_WRITE(DPLL(pipe), | |
7970 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7971 | ||
7972 | /* No need to actually set up the DPLL with DSI */ | |
7973 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7974 | return; | |
7975 | ||
d288f65f VS |
7976 | bestn = pipe_config->dpll.n; |
7977 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7978 | bestm1 = pipe_config->dpll.m1; | |
7979 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7980 | bestp1 = pipe_config->dpll.p1; | |
7981 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7982 | vco = pipe_config->dpll.vco; |
a945ce7e | 7983 | dpio_val = 0; |
9cbe40c1 | 7984 | loopfilter = 0; |
9d556c99 | 7985 | |
a580516d | 7986 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7987 | |
9d556c99 CML |
7988 | /* p1 and p2 divider */ |
7989 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7990 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7991 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7992 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7993 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7994 | ||
7995 | /* Feedback post-divider - m2 */ | |
7996 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7997 | ||
7998 | /* Feedback refclk divider - n and m1 */ | |
7999 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
8000 | DPIO_CHV_M1_DIV_BY_2 | | |
8001 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
8002 | ||
8003 | /* M2 fraction division */ | |
25a25dfc | 8004 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
8005 | |
8006 | /* M2 fraction division enable */ | |
a945ce7e VP |
8007 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
8008 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
8009 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
8010 | if (bestm2_frac) | |
8011 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
8012 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 8013 | |
de3a0fde VP |
8014 | /* Program digital lock detect threshold */ |
8015 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
8016 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
8017 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
8018 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
8019 | if (!bestm2_frac) | |
8020 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
8021 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
8022 | ||
9d556c99 | 8023 | /* Loop filter */ |
9cbe40c1 VP |
8024 | if (vco == 5400000) { |
8025 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8026 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
8027 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8028 | tribuf_calcntr = 0x9; | |
8029 | } else if (vco <= 6200000) { | |
8030 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8031 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
8032 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8033 | tribuf_calcntr = 0x9; | |
8034 | } else if (vco <= 6480000) { | |
8035 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8036 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8037 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8038 | tribuf_calcntr = 0x8; | |
8039 | } else { | |
8040 | /* Not supported. Apply the same limits as in the max case */ | |
8041 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8042 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8043 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8044 | tribuf_calcntr = 0; | |
8045 | } | |
9d556c99 CML |
8046 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
8047 | ||
968040b2 | 8048 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
8049 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
8050 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
8051 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
8052 | ||
9d556c99 CML |
8053 | /* AFC Recal */ |
8054 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
8055 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
8056 | DPIO_AFC_RECAL); | |
8057 | ||
a580516d | 8058 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
8059 | } |
8060 | ||
d288f65f VS |
8061 | /** |
8062 | * vlv_force_pll_on - forcibly enable just the PLL | |
8063 | * @dev_priv: i915 private structure | |
8064 | * @pipe: pipe PLL to enable | |
8065 | * @dpll: PLL configuration | |
8066 | * | |
8067 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
8068 | * in cases where we need the PLL enabled even when @pipe is not going to | |
8069 | * be enabled. | |
8070 | */ | |
30ad9814 | 8071 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 8072 | const struct dpll *dpll) |
d288f65f | 8073 | { |
b91eb5cc | 8074 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
8075 | struct intel_crtc_state *pipe_config; |
8076 | ||
8077 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
8078 | if (!pipe_config) | |
8079 | return -ENOMEM; | |
8080 | ||
8081 | pipe_config->base.crtc = &crtc->base; | |
8082 | pipe_config->pixel_multiplier = 1; | |
8083 | pipe_config->dpll = *dpll; | |
d288f65f | 8084 | |
30ad9814 | 8085 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
8086 | chv_compute_dpll(crtc, pipe_config); |
8087 | chv_prepare_pll(crtc, pipe_config); | |
8088 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 8089 | } else { |
3f36b937 TU |
8090 | vlv_compute_dpll(crtc, pipe_config); |
8091 | vlv_prepare_pll(crtc, pipe_config); | |
8092 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 8093 | } |
3f36b937 TU |
8094 | |
8095 | kfree(pipe_config); | |
8096 | ||
8097 | return 0; | |
d288f65f VS |
8098 | } |
8099 | ||
8100 | /** | |
8101 | * vlv_force_pll_off - forcibly disable just the PLL | |
8102 | * @dev_priv: i915 private structure | |
8103 | * @pipe: pipe PLL to disable | |
8104 | * | |
8105 | * Disable the PLL for @pipe. To be used in cases where we need | |
8106 | * the PLL enabled even when @pipe is not going to be enabled. | |
8107 | */ | |
30ad9814 | 8108 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 8109 | { |
30ad9814 VS |
8110 | if (IS_CHERRYVIEW(dev_priv)) |
8111 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 8112 | else |
30ad9814 | 8113 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
8114 | } |
8115 | ||
251ac862 DV |
8116 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
8117 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8118 | struct dpll *reduced_clock) |
eb1cbe48 | 8119 | { |
9b1e14f4 | 8120 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 8121 | u32 dpll; |
190f68c5 | 8122 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8123 | |
190f68c5 | 8124 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8125 | |
eb1cbe48 DV |
8126 | dpll = DPLL_VGA_MODE_DIS; |
8127 | ||
2d84d2b3 | 8128 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
8129 | dpll |= DPLLB_MODE_LVDS; |
8130 | else | |
8131 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 8132 | |
50a0bc90 | 8133 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) { |
190f68c5 | 8134 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 8135 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 8136 | } |
198a037f | 8137 | |
3d6e9ee0 VS |
8138 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8139 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8140 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 8141 | |
37a5650b | 8142 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8143 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
8144 | |
8145 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 8146 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
8147 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
8148 | else { | |
8149 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 8150 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
8151 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
8152 | } | |
8153 | switch (clock->p2) { | |
8154 | case 5: | |
8155 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8156 | break; | |
8157 | case 7: | |
8158 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8159 | break; | |
8160 | case 10: | |
8161 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8162 | break; | |
8163 | case 14: | |
8164 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8165 | break; | |
8166 | } | |
9b1e14f4 | 8167 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
8168 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
8169 | ||
190f68c5 | 8170 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 8171 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 8172 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8173 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8174 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8175 | else | |
8176 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8177 | ||
8178 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8179 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 8180 | |
9b1e14f4 | 8181 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 8182 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8183 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 8184 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
8185 | } |
8186 | } | |
8187 | ||
251ac862 DV |
8188 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
8189 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8190 | struct dpll *reduced_clock) |
eb1cbe48 | 8191 | { |
f47709a9 | 8192 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8193 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 8194 | u32 dpll; |
190f68c5 | 8195 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8196 | |
190f68c5 | 8197 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8198 | |
eb1cbe48 DV |
8199 | dpll = DPLL_VGA_MODE_DIS; |
8200 | ||
2d84d2b3 | 8201 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
8202 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
8203 | } else { | |
8204 | if (clock->p1 == 2) | |
8205 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
8206 | else | |
8207 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
8208 | if (clock->p2 == 4) | |
8209 | dpll |= PLL_P2_DIVIDE_BY_4; | |
8210 | } | |
8211 | ||
50a0bc90 TU |
8212 | if (!IS_I830(dev_priv) && |
8213 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
8214 | dpll |= DPLL_DVO_2X_MODE; |
8215 | ||
2d84d2b3 | 8216 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8217 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8218 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8219 | else | |
8220 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8221 | ||
8222 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8223 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
8224 | } |
8225 | ||
8a654f3b | 8226 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 8227 | { |
6315b5d3 | 8228 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 8229 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8230 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 8231 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
8232 | uint32_t crtc_vtotal, crtc_vblank_end; |
8233 | int vsyncshift = 0; | |
4d8a62ea DV |
8234 | |
8235 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
8236 | * the hw state checker will get angry at the mismatch. */ | |
8237 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
8238 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 8239 | |
609aeaca | 8240 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 8241 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
8242 | crtc_vtotal -= 1; |
8243 | crtc_vblank_end -= 1; | |
609aeaca | 8244 | |
2d84d2b3 | 8245 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
8246 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
8247 | else | |
8248 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
8249 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
8250 | if (vsyncshift < 0) |
8251 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
8252 | } |
8253 | ||
6315b5d3 | 8254 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 8255 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 8256 | |
fe2b8f9d | 8257 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
8258 | (adjusted_mode->crtc_hdisplay - 1) | |
8259 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 8260 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
8261 | (adjusted_mode->crtc_hblank_start - 1) | |
8262 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 8263 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
8264 | (adjusted_mode->crtc_hsync_start - 1) | |
8265 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
8266 | ||
fe2b8f9d | 8267 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 8268 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 8269 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 8270 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 8271 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 8272 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 8273 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
8274 | (adjusted_mode->crtc_vsync_start - 1) | |
8275 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
8276 | ||
b5e508d4 PZ |
8277 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
8278 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
8279 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
8280 | * bits. */ | |
772c2a51 | 8281 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
8282 | (pipe == PIPE_B || pipe == PIPE_C)) |
8283 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
8284 | ||
bc58be60 JN |
8285 | } |
8286 | ||
8287 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
8288 | { | |
8289 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8290 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
8291 | enum pipe pipe = intel_crtc->pipe; |
8292 | ||
b0e77b9c PZ |
8293 | /* pipesrc controls the size that is scaled from, which should |
8294 | * always be the user's requested size. | |
8295 | */ | |
8296 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
8297 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
8298 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
8299 | } |
8300 | ||
1bd1bd80 | 8301 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 8302 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
8303 | { |
8304 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8305 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
8306 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
8307 | uint32_t tmp; | |
8308 | ||
8309 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8310 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
8311 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8312 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
8313 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
8314 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8315 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
8316 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
8317 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8318 | |
8319 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8320 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
8321 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8322 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
8323 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
8324 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8325 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
8326 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
8327 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8328 | |
8329 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
8330 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
8331 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
8332 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 8333 | } |
bc58be60 JN |
8334 | } |
8335 | ||
8336 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
8337 | struct intel_crtc_state *pipe_config) | |
8338 | { | |
8339 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8340 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 8341 | u32 tmp; |
1bd1bd80 DV |
8342 | |
8343 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
8344 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
8345 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
8346 | ||
2d112de7 ACO |
8347 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
8348 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
8349 | } |
8350 | ||
f6a83288 | 8351 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 8352 | struct intel_crtc_state *pipe_config) |
babea61d | 8353 | { |
2d112de7 ACO |
8354 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
8355 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
8356 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
8357 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 8358 | |
2d112de7 ACO |
8359 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
8360 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
8361 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
8362 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 8363 | |
2d112de7 | 8364 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 8365 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 8366 | |
2d112de7 ACO |
8367 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
8368 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
8369 | |
8370 | mode->hsync = drm_mode_hsync(mode); | |
8371 | mode->vrefresh = drm_mode_vrefresh(mode); | |
8372 | drm_mode_set_name(mode); | |
babea61d JB |
8373 | } |
8374 | ||
84b046f3 DV |
8375 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
8376 | { | |
6315b5d3 | 8377 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
8378 | uint32_t pipeconf; |
8379 | ||
9f11a9e4 | 8380 | pipeconf = 0; |
84b046f3 | 8381 | |
b6b5d049 VS |
8382 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
8383 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8384 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 8385 | |
6e3c9717 | 8386 | if (intel_crtc->config->double_wide) |
cf532bb2 | 8387 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 8388 | |
ff9ce46e | 8389 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
8390 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
8391 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 8392 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 8393 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 8394 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 8395 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 8396 | |
6e3c9717 | 8397 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
8398 | case 18: |
8399 | pipeconf |= PIPECONF_6BPC; | |
8400 | break; | |
8401 | case 24: | |
8402 | pipeconf |= PIPECONF_8BPC; | |
8403 | break; | |
8404 | case 30: | |
8405 | pipeconf |= PIPECONF_10BPC; | |
8406 | break; | |
8407 | default: | |
8408 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
8409 | BUG(); | |
84b046f3 DV |
8410 | } |
8411 | } | |
8412 | ||
56b857a5 | 8413 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
8414 | if (intel_crtc->lowfreq_avail) { |
8415 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
8416 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
8417 | } else { | |
8418 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
8419 | } |
8420 | } | |
8421 | ||
6e3c9717 | 8422 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 8423 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 8424 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
8425 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
8426 | else | |
8427 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
8428 | } else | |
84b046f3 DV |
8429 | pipeconf |= PIPECONF_PROGRESSIVE; |
8430 | ||
920a14b2 | 8431 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 8432 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 8433 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 8434 | |
84b046f3 DV |
8435 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
8436 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
8437 | } | |
8438 | ||
81c97f52 ACO |
8439 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
8440 | struct intel_crtc_state *crtc_state) | |
8441 | { | |
8442 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8443 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8444 | const struct intel_limit *limit; |
81c97f52 ACO |
8445 | int refclk = 48000; |
8446 | ||
8447 | memset(&crtc_state->dpll_hw_state, 0, | |
8448 | sizeof(crtc_state->dpll_hw_state)); | |
8449 | ||
2d84d2b3 | 8450 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
8451 | if (intel_panel_use_ssc(dev_priv)) { |
8452 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8453 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8454 | } | |
8455 | ||
8456 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 8457 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
8458 | limit = &intel_limits_i8xx_dvo; |
8459 | } else { | |
8460 | limit = &intel_limits_i8xx_dac; | |
8461 | } | |
8462 | ||
8463 | if (!crtc_state->clock_set && | |
8464 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8465 | refclk, NULL, &crtc_state->dpll)) { | |
8466 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8467 | return -EINVAL; | |
8468 | } | |
8469 | ||
8470 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
8471 | ||
8472 | return 0; | |
8473 | } | |
8474 | ||
19ec6693 ACO |
8475 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
8476 | struct intel_crtc_state *crtc_state) | |
8477 | { | |
8478 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8479 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8480 | const struct intel_limit *limit; |
19ec6693 ACO |
8481 | int refclk = 96000; |
8482 | ||
8483 | memset(&crtc_state->dpll_hw_state, 0, | |
8484 | sizeof(crtc_state->dpll_hw_state)); | |
8485 | ||
2d84d2b3 | 8486 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
8487 | if (intel_panel_use_ssc(dev_priv)) { |
8488 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8489 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8490 | } | |
8491 | ||
8492 | if (intel_is_dual_link_lvds(dev)) | |
8493 | limit = &intel_limits_g4x_dual_channel_lvds; | |
8494 | else | |
8495 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
8496 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
8497 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 8498 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 8499 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
8500 | limit = &intel_limits_g4x_sdvo; |
8501 | } else { | |
8502 | /* The option is for other outputs */ | |
8503 | limit = &intel_limits_i9xx_sdvo; | |
8504 | } | |
8505 | ||
8506 | if (!crtc_state->clock_set && | |
8507 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8508 | refclk, NULL, &crtc_state->dpll)) { | |
8509 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8510 | return -EINVAL; | |
8511 | } | |
8512 | ||
8513 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8514 | ||
8515 | return 0; | |
8516 | } | |
8517 | ||
70e8aa21 ACO |
8518 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
8519 | struct intel_crtc_state *crtc_state) | |
8520 | { | |
8521 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8522 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8523 | const struct intel_limit *limit; |
70e8aa21 ACO |
8524 | int refclk = 96000; |
8525 | ||
8526 | memset(&crtc_state->dpll_hw_state, 0, | |
8527 | sizeof(crtc_state->dpll_hw_state)); | |
8528 | ||
2d84d2b3 | 8529 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8530 | if (intel_panel_use_ssc(dev_priv)) { |
8531 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8532 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8533 | } | |
8534 | ||
8535 | limit = &intel_limits_pineview_lvds; | |
8536 | } else { | |
8537 | limit = &intel_limits_pineview_sdvo; | |
8538 | } | |
8539 | ||
8540 | if (!crtc_state->clock_set && | |
8541 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8542 | refclk, NULL, &crtc_state->dpll)) { | |
8543 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8544 | return -EINVAL; | |
8545 | } | |
8546 | ||
8547 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8548 | ||
8549 | return 0; | |
8550 | } | |
8551 | ||
190f68c5 ACO |
8552 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8553 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8554 | { |
c7653199 | 8555 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8556 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8557 | const struct intel_limit *limit; |
81c97f52 | 8558 | int refclk = 96000; |
79e53945 | 8559 | |
dd3cd74a ACO |
8560 | memset(&crtc_state->dpll_hw_state, 0, |
8561 | sizeof(crtc_state->dpll_hw_state)); | |
8562 | ||
2d84d2b3 | 8563 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8564 | if (intel_panel_use_ssc(dev_priv)) { |
8565 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8566 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8567 | } | |
43565a06 | 8568 | |
70e8aa21 ACO |
8569 | limit = &intel_limits_i9xx_lvds; |
8570 | } else { | |
8571 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8572 | } |
79e53945 | 8573 | |
70e8aa21 ACO |
8574 | if (!crtc_state->clock_set && |
8575 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8576 | refclk, NULL, &crtc_state->dpll)) { | |
8577 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8578 | return -EINVAL; | |
f47709a9 | 8579 | } |
7026d4ac | 8580 | |
81c97f52 | 8581 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8582 | |
c8f7a0db | 8583 | return 0; |
f564048e EA |
8584 | } |
8585 | ||
65b3d6a9 ACO |
8586 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8587 | struct intel_crtc_state *crtc_state) | |
8588 | { | |
8589 | int refclk = 100000; | |
1b6f4958 | 8590 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8591 | |
8592 | memset(&crtc_state->dpll_hw_state, 0, | |
8593 | sizeof(crtc_state->dpll_hw_state)); | |
8594 | ||
65b3d6a9 ACO |
8595 | if (!crtc_state->clock_set && |
8596 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8597 | refclk, NULL, &crtc_state->dpll)) { | |
8598 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8599 | return -EINVAL; | |
8600 | } | |
8601 | ||
8602 | chv_compute_dpll(crtc, crtc_state); | |
8603 | ||
8604 | return 0; | |
8605 | } | |
8606 | ||
8607 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8608 | struct intel_crtc_state *crtc_state) | |
8609 | { | |
8610 | int refclk = 100000; | |
1b6f4958 | 8611 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8612 | |
8613 | memset(&crtc_state->dpll_hw_state, 0, | |
8614 | sizeof(crtc_state->dpll_hw_state)); | |
8615 | ||
65b3d6a9 ACO |
8616 | if (!crtc_state->clock_set && |
8617 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8618 | refclk, NULL, &crtc_state->dpll)) { | |
8619 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8620 | return -EINVAL; | |
8621 | } | |
8622 | ||
8623 | vlv_compute_dpll(crtc, crtc_state); | |
8624 | ||
8625 | return 0; | |
8626 | } | |
8627 | ||
2fa2fe9a | 8628 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8629 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 8630 | { |
6315b5d3 | 8631 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
8632 | uint32_t tmp; |
8633 | ||
50a0bc90 TU |
8634 | if (INTEL_GEN(dev_priv) <= 3 && |
8635 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
8636 | return; |
8637 | ||
2fa2fe9a | 8638 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8639 | if (!(tmp & PFIT_ENABLE)) |
8640 | return; | |
2fa2fe9a | 8641 | |
06922821 | 8642 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 8643 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
8644 | if (crtc->pipe != PIPE_B) |
8645 | return; | |
2fa2fe9a DV |
8646 | } else { |
8647 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8648 | return; | |
8649 | } | |
8650 | ||
06922821 | 8651 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8652 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8653 | } |
8654 | ||
acbec814 | 8655 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8656 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8657 | { |
8658 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8659 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 8660 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 8661 | struct dpll clock; |
acbec814 | 8662 | u32 mdiv; |
662c6ecb | 8663 | int refclk = 100000; |
acbec814 | 8664 | |
b521973b VS |
8665 | /* In case of DSI, DPLL will not be used */ |
8666 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8667 | return; |
8668 | ||
a580516d | 8669 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8670 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8671 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8672 | |
8673 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8674 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8675 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8676 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8677 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8678 | ||
dccbea3b | 8679 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8680 | } |
8681 | ||
5724dbd1 DL |
8682 | static void |
8683 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8684 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8685 | { |
8686 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8687 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
8688 | u32 val, base, offset; |
8689 | int pipe = crtc->pipe, plane = crtc->plane; | |
8690 | int fourcc, pixel_format; | |
6761dd31 | 8691 | unsigned int aligned_height; |
b113d5ee | 8692 | struct drm_framebuffer *fb; |
1b842c89 | 8693 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8694 | |
42a7b088 DL |
8695 | val = I915_READ(DSPCNTR(plane)); |
8696 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8697 | return; | |
8698 | ||
d9806c9f | 8699 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8700 | if (!intel_fb) { |
1ad292b5 JB |
8701 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8702 | return; | |
8703 | } | |
8704 | ||
1b842c89 DL |
8705 | fb = &intel_fb->base; |
8706 | ||
6315b5d3 | 8707 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8708 | if (val & DISPPLANE_TILED) { |
49af449b | 8709 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8710 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8711 | } | |
8712 | } | |
1ad292b5 JB |
8713 | |
8714 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8715 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8716 | fb->pixel_format = fourcc; |
8717 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 | 8718 | |
6315b5d3 | 8719 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 8720 | if (plane_config->tiling) |
1ad292b5 JB |
8721 | offset = I915_READ(DSPTILEOFF(plane)); |
8722 | else | |
8723 | offset = I915_READ(DSPLINOFF(plane)); | |
8724 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8725 | } else { | |
8726 | base = I915_READ(DSPADDR(plane)); | |
8727 | } | |
8728 | plane_config->base = base; | |
8729 | ||
8730 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8731 | fb->width = ((val >> 16) & 0xfff) + 1; |
8732 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8733 | |
8734 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8735 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8736 | |
b113d5ee | 8737 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8738 | fb->pixel_format, |
8739 | fb->modifier[0]); | |
1ad292b5 | 8740 | |
f37b5c2b | 8741 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8742 | |
2844a921 DL |
8743 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8744 | pipe_name(pipe), plane, fb->width, fb->height, | |
8745 | fb->bits_per_pixel, base, fb->pitches[0], | |
8746 | plane_config->size); | |
1ad292b5 | 8747 | |
2d14030b | 8748 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8749 | } |
8750 | ||
70b23a98 | 8751 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8752 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8753 | { |
8754 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8755 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
8756 | int pipe = pipe_config->cpu_transcoder; |
8757 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8758 | struct dpll clock; |
0d7b6b11 | 8759 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8760 | int refclk = 100000; |
8761 | ||
b521973b VS |
8762 | /* In case of DSI, DPLL will not be used */ |
8763 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8764 | return; | |
8765 | ||
a580516d | 8766 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8767 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8768 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8769 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8770 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8771 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8772 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8773 | |
8774 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8775 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8776 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8777 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8778 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8779 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8780 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8781 | ||
dccbea3b | 8782 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8783 | } |
8784 | ||
0e8ffe1b | 8785 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8786 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 8787 | { |
6315b5d3 | 8788 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 8789 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8790 | uint32_t tmp; |
1729050e | 8791 | bool ret; |
0e8ffe1b | 8792 | |
1729050e ID |
8793 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8794 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8795 | return false; |
8796 | ||
e143a21c | 8797 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8798 | pipe_config->shared_dpll = NULL; |
eccb140b | 8799 | |
1729050e ID |
8800 | ret = false; |
8801 | ||
0e8ffe1b DV |
8802 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8803 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8804 | goto out; |
0e8ffe1b | 8805 | |
9beb5fea TU |
8806 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
8807 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
8808 | switch (tmp & PIPECONF_BPC_MASK) { |
8809 | case PIPECONF_6BPC: | |
8810 | pipe_config->pipe_bpp = 18; | |
8811 | break; | |
8812 | case PIPECONF_8BPC: | |
8813 | pipe_config->pipe_bpp = 24; | |
8814 | break; | |
8815 | case PIPECONF_10BPC: | |
8816 | pipe_config->pipe_bpp = 30; | |
8817 | break; | |
8818 | default: | |
8819 | break; | |
8820 | } | |
8821 | } | |
8822 | ||
920a14b2 | 8823 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 8824 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
8825 | pipe_config->limited_color_range = true; |
8826 | ||
6315b5d3 | 8827 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
8828 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
8829 | ||
1bd1bd80 | 8830 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8831 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8832 | |
2fa2fe9a DV |
8833 | i9xx_get_pfit_config(crtc, pipe_config); |
8834 | ||
6315b5d3 | 8835 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 8836 | /* No way to read it out on pipes B and C */ |
920a14b2 | 8837 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
8838 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
8839 | else | |
8840 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8841 | pipe_config->pixel_multiplier = |
8842 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8843 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8844 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 TU |
8845 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
8846 | IS_G33(dev_priv)) { | |
6c49f241 DV |
8847 | tmp = I915_READ(DPLL(crtc->pipe)); |
8848 | pipe_config->pixel_multiplier = | |
8849 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8850 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8851 | } else { | |
8852 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8853 | * port and will be fixed up in the encoder->get_config | |
8854 | * function. */ | |
8855 | pipe_config->pixel_multiplier = 1; | |
8856 | } | |
8bcc2795 | 8857 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 8858 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
8859 | /* |
8860 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8861 | * on 830. Filter it out here so that we don't | |
8862 | * report errors due to that. | |
8863 | */ | |
50a0bc90 | 8864 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
8865 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
8866 | ||
8bcc2795 DV |
8867 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8868 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8869 | } else { |
8870 | /* Mask out read-only status bits. */ | |
8871 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8872 | DPLL_PORTC_READY_MASK | | |
8873 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8874 | } |
6c49f241 | 8875 | |
920a14b2 | 8876 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 8877 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 8878 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
8879 | vlv_crtc_clock_get(crtc, pipe_config); |
8880 | else | |
8881 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8882 | |
0f64614d VS |
8883 | /* |
8884 | * Normally the dotclock is filled in by the encoder .get_config() | |
8885 | * but in case the pipe is enabled w/o any ports we need a sane | |
8886 | * default. | |
8887 | */ | |
8888 | pipe_config->base.adjusted_mode.crtc_clock = | |
8889 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8890 | ||
1729050e ID |
8891 | ret = true; |
8892 | ||
8893 | out: | |
8894 | intel_display_power_put(dev_priv, power_domain); | |
8895 | ||
8896 | return ret; | |
0e8ffe1b DV |
8897 | } |
8898 | ||
c39055b0 | 8899 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 8900 | { |
13d83a67 | 8901 | struct intel_encoder *encoder; |
1c1a24d2 | 8902 | int i; |
74cfd7ac | 8903 | u32 val, final; |
13d83a67 | 8904 | bool has_lvds = false; |
199e5d79 | 8905 | bool has_cpu_edp = false; |
199e5d79 | 8906 | bool has_panel = false; |
99eb6a01 KP |
8907 | bool has_ck505 = false; |
8908 | bool can_ssc = false; | |
1c1a24d2 | 8909 | bool using_ssc_source = false; |
13d83a67 JB |
8910 | |
8911 | /* We need to take the global config into account */ | |
c39055b0 | 8912 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
8913 | switch (encoder->type) { |
8914 | case INTEL_OUTPUT_LVDS: | |
8915 | has_panel = true; | |
8916 | has_lvds = true; | |
8917 | break; | |
8918 | case INTEL_OUTPUT_EDP: | |
8919 | has_panel = true; | |
2de6905f | 8920 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8921 | has_cpu_edp = true; |
8922 | break; | |
6847d71b PZ |
8923 | default: |
8924 | break; | |
13d83a67 JB |
8925 | } |
8926 | } | |
8927 | ||
6e266956 | 8928 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 8929 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8930 | can_ssc = has_ck505; |
8931 | } else { | |
8932 | has_ck505 = false; | |
8933 | can_ssc = true; | |
8934 | } | |
8935 | ||
1c1a24d2 L |
8936 | /* Check if any DPLLs are using the SSC source */ |
8937 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8938 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8939 | ||
8940 | if (!(temp & DPLL_VCO_ENABLE)) | |
8941 | continue; | |
8942 | ||
8943 | if ((temp & PLL_REF_INPUT_MASK) == | |
8944 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8945 | using_ssc_source = true; | |
8946 | break; | |
8947 | } | |
8948 | } | |
8949 | ||
8950 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
8951 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
8952 | |
8953 | /* Ironlake: try to setup display ref clock before DPLL | |
8954 | * enabling. This is only under driver's control after | |
8955 | * PCH B stepping, previous chipset stepping should be | |
8956 | * ignoring this setting. | |
8957 | */ | |
74cfd7ac CW |
8958 | val = I915_READ(PCH_DREF_CONTROL); |
8959 | ||
8960 | /* As we must carefully and slowly disable/enable each source in turn, | |
8961 | * compute the final state we want first and check if we need to | |
8962 | * make any changes at all. | |
8963 | */ | |
8964 | final = val; | |
8965 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8966 | if (has_ck505) | |
8967 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8968 | else | |
8969 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8970 | ||
8c07eb68 | 8971 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 8972 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 8973 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
8974 | |
8975 | if (has_panel) { | |
8976 | final |= DREF_SSC_SOURCE_ENABLE; | |
8977 | ||
8978 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8979 | final |= DREF_SSC1_ENABLE; | |
8980 | ||
8981 | if (has_cpu_edp) { | |
8982 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8983 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8984 | else | |
8985 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8986 | } else | |
8987 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
8988 | } else if (using_ssc_source) { |
8989 | final |= DREF_SSC_SOURCE_ENABLE; | |
8990 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
8991 | } |
8992 | ||
8993 | if (final == val) | |
8994 | return; | |
8995 | ||
13d83a67 | 8996 | /* Always enable nonspread source */ |
74cfd7ac | 8997 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8998 | |
99eb6a01 | 8999 | if (has_ck505) |
74cfd7ac | 9000 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 9001 | else |
74cfd7ac | 9002 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 9003 | |
199e5d79 | 9004 | if (has_panel) { |
74cfd7ac CW |
9005 | val &= ~DREF_SSC_SOURCE_MASK; |
9006 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 9007 | |
199e5d79 | 9008 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 9009 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 9010 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 9011 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 9012 | } else |
74cfd7ac | 9013 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
9014 | |
9015 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 9016 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9017 | POSTING_READ(PCH_DREF_CONTROL); |
9018 | udelay(200); | |
9019 | ||
74cfd7ac | 9020 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
9021 | |
9022 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 9023 | if (has_cpu_edp) { |
99eb6a01 | 9024 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 9025 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 9026 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 9027 | } else |
74cfd7ac | 9028 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 9029 | } else |
74cfd7ac | 9030 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9031 | |
74cfd7ac | 9032 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9033 | POSTING_READ(PCH_DREF_CONTROL); |
9034 | udelay(200); | |
9035 | } else { | |
1c1a24d2 | 9036 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 9037 | |
74cfd7ac | 9038 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
9039 | |
9040 | /* Turn off CPU output */ | |
74cfd7ac | 9041 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9042 | |
74cfd7ac | 9043 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9044 | POSTING_READ(PCH_DREF_CONTROL); |
9045 | udelay(200); | |
9046 | ||
1c1a24d2 L |
9047 | if (!using_ssc_source) { |
9048 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 9049 | |
1c1a24d2 L |
9050 | /* Turn off the SSC source */ |
9051 | val &= ~DREF_SSC_SOURCE_MASK; | |
9052 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 9053 | |
1c1a24d2 L |
9054 | /* Turn off SSC1 */ |
9055 | val &= ~DREF_SSC1_ENABLE; | |
9056 | ||
9057 | I915_WRITE(PCH_DREF_CONTROL, val); | |
9058 | POSTING_READ(PCH_DREF_CONTROL); | |
9059 | udelay(200); | |
9060 | } | |
13d83a67 | 9061 | } |
74cfd7ac CW |
9062 | |
9063 | BUG_ON(val != final); | |
13d83a67 JB |
9064 | } |
9065 | ||
f31f2d55 | 9066 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 9067 | { |
f31f2d55 | 9068 | uint32_t tmp; |
dde86e2d | 9069 | |
0ff066a9 PZ |
9070 | tmp = I915_READ(SOUTH_CHICKEN2); |
9071 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
9072 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 9073 | |
cf3598c2 ID |
9074 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
9075 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 9076 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 9077 | |
0ff066a9 PZ |
9078 | tmp = I915_READ(SOUTH_CHICKEN2); |
9079 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
9080 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 9081 | |
cf3598c2 ID |
9082 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
9083 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 9084 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
9085 | } |
9086 | ||
9087 | /* WaMPhyProgramming:hsw */ | |
9088 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
9089 | { | |
9090 | uint32_t tmp; | |
dde86e2d PZ |
9091 | |
9092 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
9093 | tmp &= ~(0xFF << 24); | |
9094 | tmp |= (0x12 << 24); | |
9095 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
9096 | ||
dde86e2d PZ |
9097 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
9098 | tmp |= (1 << 11); | |
9099 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
9100 | ||
9101 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
9102 | tmp |= (1 << 11); | |
9103 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
9104 | ||
dde86e2d PZ |
9105 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
9106 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9107 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
9108 | ||
9109 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
9110 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9111 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
9112 | ||
0ff066a9 PZ |
9113 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
9114 | tmp &= ~(7 << 13); | |
9115 | tmp |= (5 << 13); | |
9116 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 9117 | |
0ff066a9 PZ |
9118 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
9119 | tmp &= ~(7 << 13); | |
9120 | tmp |= (5 << 13); | |
9121 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
9122 | |
9123 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
9124 | tmp &= ~0xFF; | |
9125 | tmp |= 0x1C; | |
9126 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
9127 | ||
9128 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
9129 | tmp &= ~0xFF; | |
9130 | tmp |= 0x1C; | |
9131 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
9132 | ||
9133 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
9134 | tmp &= ~(0xFF << 16); | |
9135 | tmp |= (0x1C << 16); | |
9136 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
9137 | ||
9138 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
9139 | tmp &= ~(0xFF << 16); | |
9140 | tmp |= (0x1C << 16); | |
9141 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
9142 | ||
0ff066a9 PZ |
9143 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
9144 | tmp |= (1 << 27); | |
9145 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 9146 | |
0ff066a9 PZ |
9147 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
9148 | tmp |= (1 << 27); | |
9149 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 9150 | |
0ff066a9 PZ |
9151 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
9152 | tmp &= ~(0xF << 28); | |
9153 | tmp |= (4 << 28); | |
9154 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 9155 | |
0ff066a9 PZ |
9156 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
9157 | tmp &= ~(0xF << 28); | |
9158 | tmp |= (4 << 28); | |
9159 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
9160 | } |
9161 | ||
2fa86a1f PZ |
9162 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
9163 | * Programming" based on the parameters passed: | |
9164 | * - Sequence to enable CLKOUT_DP | |
9165 | * - Sequence to enable CLKOUT_DP without spread | |
9166 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
9167 | */ | |
c39055b0 ACO |
9168 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
9169 | bool with_spread, bool with_fdi) | |
f31f2d55 | 9170 | { |
2fa86a1f PZ |
9171 | uint32_t reg, tmp; |
9172 | ||
9173 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
9174 | with_spread = true; | |
4f8036a2 TU |
9175 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
9176 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 9177 | with_fdi = false; |
f31f2d55 | 9178 | |
a580516d | 9179 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
9180 | |
9181 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9182 | tmp &= ~SBI_SSCCTL_DISABLE; | |
9183 | tmp |= SBI_SSCCTL_PATHALT; | |
9184 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9185 | ||
9186 | udelay(24); | |
9187 | ||
2fa86a1f PZ |
9188 | if (with_spread) { |
9189 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9190 | tmp &= ~SBI_SSCCTL_PATHALT; | |
9191 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 9192 | |
2fa86a1f PZ |
9193 | if (with_fdi) { |
9194 | lpt_reset_fdi_mphy(dev_priv); | |
9195 | lpt_program_fdi_mphy(dev_priv); | |
9196 | } | |
9197 | } | |
dde86e2d | 9198 | |
4f8036a2 | 9199 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
9200 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9201 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9202 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 9203 | |
a580516d | 9204 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
9205 | } |
9206 | ||
47701c3b | 9207 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 9208 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 9209 | { |
47701c3b PZ |
9210 | uint32_t reg, tmp; |
9211 | ||
a580516d | 9212 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 9213 | |
4f8036a2 | 9214 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
9215 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9216 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9217 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
9218 | ||
9219 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9220 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
9221 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
9222 | tmp |= SBI_SSCCTL_PATHALT; | |
9223 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9224 | udelay(32); | |
9225 | } | |
9226 | tmp |= SBI_SSCCTL_DISABLE; | |
9227 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9228 | } | |
9229 | ||
a580516d | 9230 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
9231 | } |
9232 | ||
f7be2c21 VS |
9233 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
9234 | ||
9235 | static const uint16_t sscdivintphase[] = { | |
9236 | [BEND_IDX( 50)] = 0x3B23, | |
9237 | [BEND_IDX( 45)] = 0x3B23, | |
9238 | [BEND_IDX( 40)] = 0x3C23, | |
9239 | [BEND_IDX( 35)] = 0x3C23, | |
9240 | [BEND_IDX( 30)] = 0x3D23, | |
9241 | [BEND_IDX( 25)] = 0x3D23, | |
9242 | [BEND_IDX( 20)] = 0x3E23, | |
9243 | [BEND_IDX( 15)] = 0x3E23, | |
9244 | [BEND_IDX( 10)] = 0x3F23, | |
9245 | [BEND_IDX( 5)] = 0x3F23, | |
9246 | [BEND_IDX( 0)] = 0x0025, | |
9247 | [BEND_IDX( -5)] = 0x0025, | |
9248 | [BEND_IDX(-10)] = 0x0125, | |
9249 | [BEND_IDX(-15)] = 0x0125, | |
9250 | [BEND_IDX(-20)] = 0x0225, | |
9251 | [BEND_IDX(-25)] = 0x0225, | |
9252 | [BEND_IDX(-30)] = 0x0325, | |
9253 | [BEND_IDX(-35)] = 0x0325, | |
9254 | [BEND_IDX(-40)] = 0x0425, | |
9255 | [BEND_IDX(-45)] = 0x0425, | |
9256 | [BEND_IDX(-50)] = 0x0525, | |
9257 | }; | |
9258 | ||
9259 | /* | |
9260 | * Bend CLKOUT_DP | |
9261 | * steps -50 to 50 inclusive, in steps of 5 | |
9262 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
9263 | * change in clock period = -(steps / 10) * 5.787 ps | |
9264 | */ | |
9265 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
9266 | { | |
9267 | uint32_t tmp; | |
9268 | int idx = BEND_IDX(steps); | |
9269 | ||
9270 | if (WARN_ON(steps % 5 != 0)) | |
9271 | return; | |
9272 | ||
9273 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
9274 | return; | |
9275 | ||
9276 | mutex_lock(&dev_priv->sb_lock); | |
9277 | ||
9278 | if (steps % 10 != 0) | |
9279 | tmp = 0xAAAAAAAB; | |
9280 | else | |
9281 | tmp = 0x00000000; | |
9282 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
9283 | ||
9284 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
9285 | tmp &= 0xffff0000; | |
9286 | tmp |= sscdivintphase[idx]; | |
9287 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
9288 | ||
9289 | mutex_unlock(&dev_priv->sb_lock); | |
9290 | } | |
9291 | ||
9292 | #undef BEND_IDX | |
9293 | ||
c39055b0 | 9294 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 9295 | { |
bf8fa3d3 PZ |
9296 | struct intel_encoder *encoder; |
9297 | bool has_vga = false; | |
9298 | ||
c39055b0 | 9299 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
9300 | switch (encoder->type) { |
9301 | case INTEL_OUTPUT_ANALOG: | |
9302 | has_vga = true; | |
9303 | break; | |
6847d71b PZ |
9304 | default: |
9305 | break; | |
bf8fa3d3 PZ |
9306 | } |
9307 | } | |
9308 | ||
f7be2c21 | 9309 | if (has_vga) { |
c39055b0 ACO |
9310 | lpt_bend_clkout_dp(dev_priv, 0); |
9311 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 9312 | } else { |
c39055b0 | 9313 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 9314 | } |
bf8fa3d3 PZ |
9315 | } |
9316 | ||
dde86e2d PZ |
9317 | /* |
9318 | * Initialize reference clocks when the driver loads | |
9319 | */ | |
c39055b0 | 9320 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 9321 | { |
6e266956 | 9322 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 9323 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 9324 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 9325 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
9326 | } |
9327 | ||
6ff93609 | 9328 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 9329 | { |
fac5e23e | 9330 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
9331 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9332 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
9333 | uint32_t val; |
9334 | ||
78114071 | 9335 | val = 0; |
c8203565 | 9336 | |
6e3c9717 | 9337 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 9338 | case 18: |
dfd07d72 | 9339 | val |= PIPECONF_6BPC; |
c8203565 PZ |
9340 | break; |
9341 | case 24: | |
dfd07d72 | 9342 | val |= PIPECONF_8BPC; |
c8203565 PZ |
9343 | break; |
9344 | case 30: | |
dfd07d72 | 9345 | val |= PIPECONF_10BPC; |
c8203565 PZ |
9346 | break; |
9347 | case 36: | |
dfd07d72 | 9348 | val |= PIPECONF_12BPC; |
c8203565 PZ |
9349 | break; |
9350 | default: | |
cc769b62 PZ |
9351 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
9352 | BUG(); | |
c8203565 PZ |
9353 | } |
9354 | ||
6e3c9717 | 9355 | if (intel_crtc->config->dither) |
c8203565 PZ |
9356 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9357 | ||
6e3c9717 | 9358 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
9359 | val |= PIPECONF_INTERLACED_ILK; |
9360 | else | |
9361 | val |= PIPECONF_PROGRESSIVE; | |
9362 | ||
6e3c9717 | 9363 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 9364 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 9365 | |
c8203565 PZ |
9366 | I915_WRITE(PIPECONF(pipe), val); |
9367 | POSTING_READ(PIPECONF(pipe)); | |
9368 | } | |
9369 | ||
6ff93609 | 9370 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 9371 | { |
fac5e23e | 9372 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 9373 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9374 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 9375 | u32 val = 0; |
ee2b0b38 | 9376 | |
391bf048 | 9377 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
9378 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9379 | ||
6e3c9717 | 9380 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
9381 | val |= PIPECONF_INTERLACED_ILK; |
9382 | else | |
9383 | val |= PIPECONF_PROGRESSIVE; | |
9384 | ||
702e7a56 PZ |
9385 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
9386 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
9387 | } |
9388 | ||
391bf048 JN |
9389 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
9390 | { | |
fac5e23e | 9391 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 9392 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 9393 | |
391bf048 JN |
9394 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
9395 | u32 val = 0; | |
756f85cf | 9396 | |
6e3c9717 | 9397 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
9398 | case 18: |
9399 | val |= PIPEMISC_DITHER_6_BPC; | |
9400 | break; | |
9401 | case 24: | |
9402 | val |= PIPEMISC_DITHER_8_BPC; | |
9403 | break; | |
9404 | case 30: | |
9405 | val |= PIPEMISC_DITHER_10_BPC; | |
9406 | break; | |
9407 | case 36: | |
9408 | val |= PIPEMISC_DITHER_12_BPC; | |
9409 | break; | |
9410 | default: | |
9411 | /* Case prevented by pipe_config_set_bpp. */ | |
9412 | BUG(); | |
9413 | } | |
9414 | ||
6e3c9717 | 9415 | if (intel_crtc->config->dither) |
756f85cf PZ |
9416 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
9417 | ||
391bf048 | 9418 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 9419 | } |
ee2b0b38 PZ |
9420 | } |
9421 | ||
d4b1931c PZ |
9422 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
9423 | { | |
9424 | /* | |
9425 | * Account for spread spectrum to avoid | |
9426 | * oversubscribing the link. Max center spread | |
9427 | * is 2.5%; use 5% for safety's sake. | |
9428 | */ | |
9429 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 9430 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
9431 | } |
9432 | ||
7429e9d4 | 9433 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 9434 | { |
7429e9d4 | 9435 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
9436 | } |
9437 | ||
b75ca6f6 ACO |
9438 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
9439 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 9440 | struct dpll *reduced_clock) |
79e53945 | 9441 | { |
de13a2e3 | 9442 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 9443 | struct drm_device *dev = crtc->dev; |
fac5e23e | 9444 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 9445 | u32 dpll, fp, fp2; |
3d6e9ee0 | 9446 | int factor; |
79e53945 | 9447 | |
c1858123 | 9448 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 9449 | factor = 21; |
3d6e9ee0 | 9450 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 9451 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 9452 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 9453 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 9454 | factor = 25; |
190f68c5 | 9455 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 9456 | factor = 20; |
c1858123 | 9457 | |
b75ca6f6 ACO |
9458 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
9459 | ||
190f68c5 | 9460 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
9461 | fp |= FP_CB_TUNE; |
9462 | ||
9463 | if (reduced_clock) { | |
9464 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 9465 | |
b75ca6f6 ACO |
9466 | if (reduced_clock->m < factor * reduced_clock->n) |
9467 | fp2 |= FP_CB_TUNE; | |
9468 | } else { | |
9469 | fp2 = fp; | |
9470 | } | |
9a7c7890 | 9471 | |
5eddb70b | 9472 | dpll = 0; |
2c07245f | 9473 | |
3d6e9ee0 | 9474 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
9475 | dpll |= DPLLB_MODE_LVDS; |
9476 | else | |
9477 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9478 | |
190f68c5 | 9479 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9480 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 9481 | |
3d6e9ee0 VS |
9482 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
9483 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 9484 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 9485 | |
37a5650b | 9486 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 9487 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9488 | |
7d7f8633 VS |
9489 | /* |
9490 | * The high speed IO clock is only really required for | |
9491 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
9492 | * possible to share the DPLL between CRT and HDMI. Enabling | |
9493 | * the clock needlessly does no real harm, except use up a | |
9494 | * bit of power potentially. | |
9495 | * | |
9496 | * We'll limit this to IVB with 3 pipes, since it has only two | |
9497 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
9498 | * driving PCH ports at the same time. On SNB we could do this, | |
9499 | * and potentially avoid enabling the second DPLL, but it's not | |
9500 | * clear if it''s a win or loss power wise. No point in doing | |
9501 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
9502 | */ | |
9503 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
9504 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
9505 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
9506 | ||
a07d6787 | 9507 | /* compute bitmask from p1 value */ |
190f68c5 | 9508 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9509 | /* also FPA1 */ |
190f68c5 | 9510 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9511 | |
190f68c5 | 9512 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9513 | case 5: |
9514 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9515 | break; | |
9516 | case 7: | |
9517 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9518 | break; | |
9519 | case 10: | |
9520 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9521 | break; | |
9522 | case 14: | |
9523 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9524 | break; | |
79e53945 JB |
9525 | } |
9526 | ||
3d6e9ee0 VS |
9527 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
9528 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 9529 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9530 | else |
9531 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9532 | ||
b75ca6f6 ACO |
9533 | dpll |= DPLL_VCO_ENABLE; |
9534 | ||
9535 | crtc_state->dpll_hw_state.dpll = dpll; | |
9536 | crtc_state->dpll_hw_state.fp0 = fp; | |
9537 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
9538 | } |
9539 | ||
190f68c5 ACO |
9540 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9541 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9542 | { |
997c030c | 9543 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9544 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 9545 | struct dpll reduced_clock; |
7ed9f894 | 9546 | bool has_reduced_clock = false; |
e2b78267 | 9547 | struct intel_shared_dpll *pll; |
1b6f4958 | 9548 | const struct intel_limit *limit; |
997c030c | 9549 | int refclk = 120000; |
de13a2e3 | 9550 | |
dd3cd74a ACO |
9551 | memset(&crtc_state->dpll_hw_state, 0, |
9552 | sizeof(crtc_state->dpll_hw_state)); | |
9553 | ||
ded220e2 ACO |
9554 | crtc->lowfreq_avail = false; |
9555 | ||
9556 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
9557 | if (!crtc_state->has_pch_encoder) | |
9558 | return 0; | |
79e53945 | 9559 | |
2d84d2b3 | 9560 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
9561 | if (intel_panel_use_ssc(dev_priv)) { |
9562 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
9563 | dev_priv->vbt.lvds_ssc_freq); | |
9564 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
9565 | } | |
9566 | ||
9567 | if (intel_is_dual_link_lvds(dev)) { | |
9568 | if (refclk == 100000) | |
9569 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
9570 | else | |
9571 | limit = &intel_limits_ironlake_dual_lvds; | |
9572 | } else { | |
9573 | if (refclk == 100000) | |
9574 | limit = &intel_limits_ironlake_single_lvds_100m; | |
9575 | else | |
9576 | limit = &intel_limits_ironlake_single_lvds; | |
9577 | } | |
9578 | } else { | |
9579 | limit = &intel_limits_ironlake_dac; | |
9580 | } | |
9581 | ||
364ee29d | 9582 | if (!crtc_state->clock_set && |
997c030c ACO |
9583 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9584 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9585 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9586 | return -EINVAL; | |
f47709a9 | 9587 | } |
79e53945 | 9588 | |
b75ca6f6 ACO |
9589 | ironlake_compute_dpll(crtc, crtc_state, |
9590 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9591 | |
ded220e2 ACO |
9592 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9593 | if (pll == NULL) { | |
9594 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9595 | pipe_name(crtc->pipe)); | |
9596 | return -EINVAL; | |
3fb37703 | 9597 | } |
79e53945 | 9598 | |
2d84d2b3 | 9599 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 9600 | has_reduced_clock) |
c7653199 | 9601 | crtc->lowfreq_avail = true; |
e2b78267 | 9602 | |
c8f7a0db | 9603 | return 0; |
79e53945 JB |
9604 | } |
9605 | ||
eb14cb74 VS |
9606 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9607 | struct intel_link_m_n *m_n) | |
9608 | { | |
9609 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9610 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
9611 | enum pipe pipe = crtc->pipe; |
9612 | ||
9613 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9614 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9615 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9616 | & ~TU_SIZE_MASK; | |
9617 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9618 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9619 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9620 | } | |
9621 | ||
9622 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9623 | enum transcoder transcoder, | |
b95af8be VK |
9624 | struct intel_link_m_n *m_n, |
9625 | struct intel_link_m_n *m2_n2) | |
72419203 | 9626 | { |
6315b5d3 | 9627 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 9628 | enum pipe pipe = crtc->pipe; |
72419203 | 9629 | |
6315b5d3 | 9630 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
9631 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
9632 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9633 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9634 | & ~TU_SIZE_MASK; | |
9635 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9636 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9637 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9638 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9639 | * gen < 8) and if DRRS is supported (to make sure the | |
9640 | * registers are not unnecessarily read). | |
9641 | */ | |
6315b5d3 | 9642 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 9643 | crtc->config->has_drrs) { |
b95af8be VK |
9644 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9645 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9646 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9647 | & ~TU_SIZE_MASK; | |
9648 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9649 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9650 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9651 | } | |
eb14cb74 VS |
9652 | } else { |
9653 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9654 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9655 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9656 | & ~TU_SIZE_MASK; | |
9657 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9658 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9659 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9660 | } | |
9661 | } | |
9662 | ||
9663 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9664 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9665 | { |
681a8504 | 9666 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9667 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9668 | else | |
9669 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9670 | &pipe_config->dp_m_n, |
9671 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9672 | } |
72419203 | 9673 | |
eb14cb74 | 9674 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9675 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9676 | { |
9677 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9678 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9679 | } |
9680 | ||
bd2e244f | 9681 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9682 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9683 | { |
9684 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9685 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
9686 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9687 | uint32_t ps_ctrl = 0; | |
9688 | int id = -1; | |
9689 | int i; | |
bd2e244f | 9690 | |
a1b2278e CK |
9691 | /* find scaler attached to this pipe */ |
9692 | for (i = 0; i < crtc->num_scalers; i++) { | |
9693 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9694 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9695 | id = i; | |
9696 | pipe_config->pch_pfit.enabled = true; | |
9697 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9698 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9699 | break; | |
9700 | } | |
9701 | } | |
bd2e244f | 9702 | |
a1b2278e CK |
9703 | scaler_state->scaler_id = id; |
9704 | if (id >= 0) { | |
9705 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9706 | } else { | |
9707 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9708 | } |
9709 | } | |
9710 | ||
5724dbd1 DL |
9711 | static void |
9712 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9713 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9714 | { |
9715 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9716 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 9717 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9718 | int pipe = crtc->pipe; |
9719 | int fourcc, pixel_format; | |
6761dd31 | 9720 | unsigned int aligned_height; |
bc8d7dff | 9721 | struct drm_framebuffer *fb; |
1b842c89 | 9722 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9723 | |
d9806c9f | 9724 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9725 | if (!intel_fb) { |
bc8d7dff DL |
9726 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9727 | return; | |
9728 | } | |
9729 | ||
1b842c89 DL |
9730 | fb = &intel_fb->base; |
9731 | ||
bc8d7dff | 9732 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9733 | if (!(val & PLANE_CTL_ENABLE)) |
9734 | goto error; | |
9735 | ||
bc8d7dff DL |
9736 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9737 | fourcc = skl_format_to_fourcc(pixel_format, | |
9738 | val & PLANE_CTL_ORDER_RGBX, | |
9739 | val & PLANE_CTL_ALPHA_MASK); | |
9740 | fb->pixel_format = fourcc; | |
9741 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9742 | ||
40f46283 DL |
9743 | tiling = val & PLANE_CTL_TILED_MASK; |
9744 | switch (tiling) { | |
9745 | case PLANE_CTL_TILED_LINEAR: | |
9746 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9747 | break; | |
9748 | case PLANE_CTL_TILED_X: | |
9749 | plane_config->tiling = I915_TILING_X; | |
9750 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9751 | break; | |
9752 | case PLANE_CTL_TILED_Y: | |
9753 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9754 | break; | |
9755 | case PLANE_CTL_TILED_YF: | |
9756 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9757 | break; | |
9758 | default: | |
9759 | MISSING_CASE(tiling); | |
9760 | goto error; | |
9761 | } | |
9762 | ||
bc8d7dff DL |
9763 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9764 | plane_config->base = base; | |
9765 | ||
9766 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9767 | ||
9768 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9769 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9770 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9771 | ||
9772 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9773 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9774 | fb->pixel_format); |
bc8d7dff DL |
9775 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9776 | ||
9777 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9778 | fb->pixel_format, |
9779 | fb->modifier[0]); | |
bc8d7dff | 9780 | |
f37b5c2b | 9781 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9782 | |
9783 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9784 | pipe_name(pipe), fb->width, fb->height, | |
9785 | fb->bits_per_pixel, base, fb->pitches[0], | |
9786 | plane_config->size); | |
9787 | ||
2d14030b | 9788 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9789 | return; |
9790 | ||
9791 | error: | |
d1a3a036 | 9792 | kfree(intel_fb); |
bc8d7dff DL |
9793 | } |
9794 | ||
2fa2fe9a | 9795 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9796 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9797 | { |
9798 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9799 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
9800 | uint32_t tmp; |
9801 | ||
9802 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9803 | ||
9804 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9805 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9806 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9807 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9808 | |
9809 | /* We currently do not free assignements of panel fitters on | |
9810 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9811 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 9812 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
9813 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
9814 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9815 | } | |
2fa2fe9a | 9816 | } |
79e53945 JB |
9817 | } |
9818 | ||
5724dbd1 DL |
9819 | static void |
9820 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9821 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9822 | { |
9823 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9824 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 9825 | u32 val, base, offset; |
aeee5a49 | 9826 | int pipe = crtc->pipe; |
4c6baa59 | 9827 | int fourcc, pixel_format; |
6761dd31 | 9828 | unsigned int aligned_height; |
b113d5ee | 9829 | struct drm_framebuffer *fb; |
1b842c89 | 9830 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9831 | |
42a7b088 DL |
9832 | val = I915_READ(DSPCNTR(pipe)); |
9833 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9834 | return; | |
9835 | ||
d9806c9f | 9836 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9837 | if (!intel_fb) { |
4c6baa59 JB |
9838 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9839 | return; | |
9840 | } | |
9841 | ||
1b842c89 DL |
9842 | fb = &intel_fb->base; |
9843 | ||
6315b5d3 | 9844 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 9845 | if (val & DISPPLANE_TILED) { |
49af449b | 9846 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9847 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9848 | } | |
9849 | } | |
4c6baa59 JB |
9850 | |
9851 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9852 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9853 | fb->pixel_format = fourcc; |
9854 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9855 | |
aeee5a49 | 9856 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 9857 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 9858 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9859 | } else { |
49af449b | 9860 | if (plane_config->tiling) |
aeee5a49 | 9861 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9862 | else |
aeee5a49 | 9863 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9864 | } |
9865 | plane_config->base = base; | |
9866 | ||
9867 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9868 | fb->width = ((val >> 16) & 0xfff) + 1; |
9869 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9870 | |
9871 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9872 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9873 | |
b113d5ee | 9874 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9875 | fb->pixel_format, |
9876 | fb->modifier[0]); | |
4c6baa59 | 9877 | |
f37b5c2b | 9878 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9879 | |
2844a921 DL |
9880 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9881 | pipe_name(pipe), fb->width, fb->height, | |
9882 | fb->bits_per_pixel, base, fb->pitches[0], | |
9883 | plane_config->size); | |
b113d5ee | 9884 | |
2d14030b | 9885 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9886 | } |
9887 | ||
0e8ffe1b | 9888 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9889 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9890 | { |
9891 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9892 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 9893 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9894 | uint32_t tmp; |
1729050e | 9895 | bool ret; |
0e8ffe1b | 9896 | |
1729050e ID |
9897 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9898 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9899 | return false; |
9900 | ||
e143a21c | 9901 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9902 | pipe_config->shared_dpll = NULL; |
eccb140b | 9903 | |
1729050e | 9904 | ret = false; |
0e8ffe1b DV |
9905 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9906 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9907 | goto out; |
0e8ffe1b | 9908 | |
42571aef VS |
9909 | switch (tmp & PIPECONF_BPC_MASK) { |
9910 | case PIPECONF_6BPC: | |
9911 | pipe_config->pipe_bpp = 18; | |
9912 | break; | |
9913 | case PIPECONF_8BPC: | |
9914 | pipe_config->pipe_bpp = 24; | |
9915 | break; | |
9916 | case PIPECONF_10BPC: | |
9917 | pipe_config->pipe_bpp = 30; | |
9918 | break; | |
9919 | case PIPECONF_12BPC: | |
9920 | pipe_config->pipe_bpp = 36; | |
9921 | break; | |
9922 | default: | |
9923 | break; | |
9924 | } | |
9925 | ||
b5a9fa09 DV |
9926 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9927 | pipe_config->limited_color_range = true; | |
9928 | ||
ab9412ba | 9929 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9930 | struct intel_shared_dpll *pll; |
8106ddbd | 9931 | enum intel_dpll_id pll_id; |
66e985c0 | 9932 | |
88adfff1 DV |
9933 | pipe_config->has_pch_encoder = true; |
9934 | ||
627eb5a3 DV |
9935 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9936 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9937 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9938 | |
9939 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9940 | |
2d1fe073 | 9941 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9942 | /* |
9943 | * The pipe->pch transcoder and pch transcoder->pll | |
9944 | * mapping is fixed. | |
9945 | */ | |
8106ddbd | 9946 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9947 | } else { |
9948 | tmp = I915_READ(PCH_DPLL_SEL); | |
9949 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9950 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9951 | else |
8106ddbd | 9952 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9953 | } |
66e985c0 | 9954 | |
8106ddbd ACO |
9955 | pipe_config->shared_dpll = |
9956 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9957 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9958 | |
2edd6443 ACO |
9959 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9960 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9961 | |
9962 | tmp = pipe_config->dpll_hw_state.dpll; | |
9963 | pipe_config->pixel_multiplier = | |
9964 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9965 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9966 | |
9967 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9968 | } else { |
9969 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9970 | } |
9971 | ||
1bd1bd80 | 9972 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9973 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9974 | |
2fa2fe9a DV |
9975 | ironlake_get_pfit_config(crtc, pipe_config); |
9976 | ||
1729050e ID |
9977 | ret = true; |
9978 | ||
9979 | out: | |
9980 | intel_display_power_put(dev_priv, power_domain); | |
9981 | ||
9982 | return ret; | |
0e8ffe1b DV |
9983 | } |
9984 | ||
be256dc7 PZ |
9985 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9986 | { | |
91c8a326 | 9987 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 9988 | struct intel_crtc *crtc; |
be256dc7 | 9989 | |
d3fcc808 | 9990 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9991 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9992 | pipe_name(crtc->pipe)); |
9993 | ||
e2c719b7 RC |
9994 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9995 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9996 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9997 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 9998 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 9999 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 10000 | "CPU PWM1 enabled\n"); |
772c2a51 | 10001 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 10002 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 10003 | "CPU PWM2 enabled\n"); |
e2c719b7 | 10004 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 10005 | "PCH PWM1 enabled\n"); |
e2c719b7 | 10006 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 10007 | "Utility pin enabled\n"); |
e2c719b7 | 10008 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 10009 | |
9926ada1 PZ |
10010 | /* |
10011 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
10012 | * interrupts remain enabled. We used to check for that, but since it's | |
10013 | * gen-specific and since we only disable LCPLL after we fully disable | |
10014 | * the interrupts, the check below should be enough. | |
10015 | */ | |
e2c719b7 | 10016 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
10017 | } |
10018 | ||
9ccd5aeb PZ |
10019 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
10020 | { | |
772c2a51 | 10021 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
10022 | return I915_READ(D_COMP_HSW); |
10023 | else | |
10024 | return I915_READ(D_COMP_BDW); | |
10025 | } | |
10026 | ||
3c4c9b81 PZ |
10027 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
10028 | { | |
772c2a51 | 10029 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
10030 | mutex_lock(&dev_priv->rps.hw_lock); |
10031 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
10032 | val)) | |
79cf219a | 10033 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
10034 | mutex_unlock(&dev_priv->rps.hw_lock); |
10035 | } else { | |
9ccd5aeb PZ |
10036 | I915_WRITE(D_COMP_BDW, val); |
10037 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 10038 | } |
be256dc7 PZ |
10039 | } |
10040 | ||
10041 | /* | |
10042 | * This function implements pieces of two sequences from BSpec: | |
10043 | * - Sequence for display software to disable LCPLL | |
10044 | * - Sequence for display software to allow package C8+ | |
10045 | * The steps implemented here are just the steps that actually touch the LCPLL | |
10046 | * register. Callers should take care of disabling all the display engine | |
10047 | * functions, doing the mode unset, fixing interrupts, etc. | |
10048 | */ | |
6ff58d53 PZ |
10049 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
10050 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
10051 | { |
10052 | uint32_t val; | |
10053 | ||
10054 | assert_can_disable_lcpll(dev_priv); | |
10055 | ||
10056 | val = I915_READ(LCPLL_CTL); | |
10057 | ||
10058 | if (switch_to_fclk) { | |
10059 | val |= LCPLL_CD_SOURCE_FCLK; | |
10060 | I915_WRITE(LCPLL_CTL, val); | |
10061 | ||
f53dd63f ID |
10062 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
10063 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
10064 | DRM_ERROR("Switching to FCLK failed\n"); |
10065 | ||
10066 | val = I915_READ(LCPLL_CTL); | |
10067 | } | |
10068 | ||
10069 | val |= LCPLL_PLL_DISABLE; | |
10070 | I915_WRITE(LCPLL_CTL, val); | |
10071 | POSTING_READ(LCPLL_CTL); | |
10072 | ||
24d8441d | 10073 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
10074 | DRM_ERROR("LCPLL still locked\n"); |
10075 | ||
9ccd5aeb | 10076 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 10077 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 10078 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
10079 | ndelay(100); |
10080 | ||
9ccd5aeb PZ |
10081 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
10082 | 1)) | |
be256dc7 PZ |
10083 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
10084 | ||
10085 | if (allow_power_down) { | |
10086 | val = I915_READ(LCPLL_CTL); | |
10087 | val |= LCPLL_POWER_DOWN_ALLOW; | |
10088 | I915_WRITE(LCPLL_CTL, val); | |
10089 | POSTING_READ(LCPLL_CTL); | |
10090 | } | |
10091 | } | |
10092 | ||
10093 | /* | |
10094 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
10095 | * source. | |
10096 | */ | |
6ff58d53 | 10097 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
10098 | { |
10099 | uint32_t val; | |
10100 | ||
10101 | val = I915_READ(LCPLL_CTL); | |
10102 | ||
10103 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
10104 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
10105 | return; | |
10106 | ||
a8a8bd54 PZ |
10107 | /* |
10108 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
10109 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 10110 | */ |
59bad947 | 10111 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 10112 | |
be256dc7 PZ |
10113 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
10114 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
10115 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 10116 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
10117 | } |
10118 | ||
9ccd5aeb | 10119 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
10120 | val |= D_COMP_COMP_FORCE; |
10121 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 10122 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
10123 | |
10124 | val = I915_READ(LCPLL_CTL); | |
10125 | val &= ~LCPLL_PLL_DISABLE; | |
10126 | I915_WRITE(LCPLL_CTL, val); | |
10127 | ||
93220c08 CW |
10128 | if (intel_wait_for_register(dev_priv, |
10129 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
10130 | 5)) | |
be256dc7 PZ |
10131 | DRM_ERROR("LCPLL not locked yet\n"); |
10132 | ||
10133 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
10134 | val = I915_READ(LCPLL_CTL); | |
10135 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10136 | I915_WRITE(LCPLL_CTL, val); | |
10137 | ||
f53dd63f ID |
10138 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10139 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
10140 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10141 | } | |
215733fa | 10142 | |
59bad947 | 10143 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 10144 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
10145 | } |
10146 | ||
765dab67 PZ |
10147 | /* |
10148 | * Package states C8 and deeper are really deep PC states that can only be | |
10149 | * reached when all the devices on the system allow it, so even if the graphics | |
10150 | * device allows PC8+, it doesn't mean the system will actually get to these | |
10151 | * states. Our driver only allows PC8+ when going into runtime PM. | |
10152 | * | |
10153 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
10154 | * well is disabled and most interrupts are disabled, and these are also | |
10155 | * requirements for runtime PM. When these conditions are met, we manually do | |
10156 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
10157 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
10158 | * hang the machine. | |
10159 | * | |
10160 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
10161 | * the state of some registers, so when we come back from PC8+ we need to | |
10162 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
10163 | * need to take care of the registers kept by RC6. Notice that this happens even | |
10164 | * if we don't put the device in PCI D3 state (which is what currently happens | |
10165 | * because of the runtime PM support). | |
10166 | * | |
10167 | * For more, read "Display Sequences for Package C8" on the hardware | |
10168 | * documentation. | |
10169 | */ | |
a14cb6fc | 10170 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10171 | { |
c67a470b PZ |
10172 | uint32_t val; |
10173 | ||
c67a470b PZ |
10174 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
10175 | ||
4f8036a2 | 10176 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
10177 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10178 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
10179 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10180 | } | |
10181 | ||
c39055b0 | 10182 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
10183 | hsw_disable_lcpll(dev_priv, true, true); |
10184 | } | |
10185 | ||
a14cb6fc | 10186 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10187 | { |
c67a470b PZ |
10188 | uint32_t val; |
10189 | ||
c67a470b PZ |
10190 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
10191 | ||
10192 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 10193 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 10194 | |
4f8036a2 | 10195 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
10196 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10197 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
10198 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10199 | } | |
c67a470b PZ |
10200 | } |
10201 | ||
324513c0 | 10202 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 10203 | { |
a821fc46 | 10204 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10205 | struct intel_atomic_state *old_intel_state = |
10206 | to_intel_atomic_state(old_state); | |
10207 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 10208 | |
324513c0 | 10209 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
10210 | } |
10211 | ||
b30ce9e0 DP |
10212 | static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, |
10213 | int pixel_rate) | |
10214 | { | |
9c754024 DP |
10215 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
10216 | ||
b30ce9e0 | 10217 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
9c754024 | 10218 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b30ce9e0 DP |
10219 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
10220 | ||
10221 | /* BSpec says "Do not use DisplayPort with CDCLK less than | |
10222 | * 432 MHz, audio enabled, port width x4, and link rate | |
10223 | * HBR2 (5.4 GHz), or else there may be audio corruption or | |
10224 | * screen corruption." | |
10225 | */ | |
10226 | if (intel_crtc_has_dp_encoder(crtc_state) && | |
10227 | crtc_state->has_audio && | |
10228 | crtc_state->port_clock >= 540000 && | |
10229 | crtc_state->lane_count == 4) | |
10230 | pixel_rate = max(432000, pixel_rate); | |
10231 | ||
10232 | return pixel_rate; | |
10233 | } | |
10234 | ||
b432e5cf | 10235 | /* compute the max rate for new configuration */ |
27c329ed | 10236 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 10237 | { |
565602d7 | 10238 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 10239 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
10240 | struct drm_crtc *crtc; |
10241 | struct drm_crtc_state *cstate; | |
27c329ed | 10242 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
10243 | unsigned max_pixel_rate = 0, i; |
10244 | enum pipe pipe; | |
b432e5cf | 10245 | |
565602d7 ML |
10246 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
10247 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 10248 | |
565602d7 ML |
10249 | for_each_crtc_in_state(state, crtc, cstate, i) { |
10250 | int pixel_rate; | |
27c329ed | 10251 | |
565602d7 ML |
10252 | crtc_state = to_intel_crtc_state(cstate); |
10253 | if (!crtc_state->base.enable) { | |
10254 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 10255 | continue; |
565602d7 | 10256 | } |
b432e5cf | 10257 | |
27c329ed | 10258 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf | 10259 | |
9c754024 | 10260 | if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) |
b30ce9e0 DP |
10261 | pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, |
10262 | pixel_rate); | |
b432e5cf | 10263 | |
565602d7 | 10264 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
10265 | } |
10266 | ||
565602d7 ML |
10267 | for_each_pipe(dev_priv, pipe) |
10268 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
10269 | ||
b432e5cf VS |
10270 | return max_pixel_rate; |
10271 | } | |
10272 | ||
10273 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
10274 | { | |
fac5e23e | 10275 | struct drm_i915_private *dev_priv = to_i915(dev); |
b432e5cf VS |
10276 | uint32_t val, data; |
10277 | int ret; | |
10278 | ||
10279 | if (WARN((I915_READ(LCPLL_CTL) & | |
10280 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
10281 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
10282 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
10283 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
10284 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
10285 | return; | |
10286 | ||
10287 | mutex_lock(&dev_priv->rps.hw_lock); | |
10288 | ret = sandybridge_pcode_write(dev_priv, | |
10289 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
10290 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10291 | if (ret) { | |
10292 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
10293 | return; | |
10294 | } | |
10295 | ||
10296 | val = I915_READ(LCPLL_CTL); | |
10297 | val |= LCPLL_CD_SOURCE_FCLK; | |
10298 | I915_WRITE(LCPLL_CTL, val); | |
10299 | ||
5ba00178 TU |
10300 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
10301 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
10302 | DRM_ERROR("Switching to FCLK failed\n"); |
10303 | ||
10304 | val = I915_READ(LCPLL_CTL); | |
10305 | val &= ~LCPLL_CLK_FREQ_MASK; | |
10306 | ||
10307 | switch (cdclk) { | |
10308 | case 450000: | |
10309 | val |= LCPLL_CLK_FREQ_450; | |
10310 | data = 0; | |
10311 | break; | |
10312 | case 540000: | |
10313 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
10314 | data = 1; | |
10315 | break; | |
10316 | case 337500: | |
10317 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
10318 | data = 2; | |
10319 | break; | |
10320 | case 675000: | |
10321 | val |= LCPLL_CLK_FREQ_675_BDW; | |
10322 | data = 3; | |
10323 | break; | |
10324 | default: | |
10325 | WARN(1, "invalid cdclk frequency\n"); | |
10326 | return; | |
10327 | } | |
10328 | ||
10329 | I915_WRITE(LCPLL_CTL, val); | |
10330 | ||
10331 | val = I915_READ(LCPLL_CTL); | |
10332 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10333 | I915_WRITE(LCPLL_CTL, val); | |
10334 | ||
5ba00178 TU |
10335 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10336 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
10337 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10338 | ||
10339 | mutex_lock(&dev_priv->rps.hw_lock); | |
10340 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
10341 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10342 | ||
7f1052a8 VS |
10343 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
10344 | ||
4c75b940 | 10345 | intel_update_cdclk(dev_priv); |
b432e5cf VS |
10346 | |
10347 | WARN(cdclk != dev_priv->cdclk_freq, | |
10348 | "cdclk requested %d kHz but got %d kHz\n", | |
10349 | cdclk, dev_priv->cdclk_freq); | |
10350 | } | |
10351 | ||
587c7914 VS |
10352 | static int broadwell_calc_cdclk(int max_pixclk) |
10353 | { | |
10354 | if (max_pixclk > 540000) | |
10355 | return 675000; | |
10356 | else if (max_pixclk > 450000) | |
10357 | return 540000; | |
10358 | else if (max_pixclk > 337500) | |
10359 | return 450000; | |
10360 | else | |
10361 | return 337500; | |
10362 | } | |
10363 | ||
27c329ed | 10364 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 10365 | { |
27c329ed | 10366 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 10367 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 10368 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
10369 | int cdclk; |
10370 | ||
10371 | /* | |
10372 | * FIXME should also account for plane ratio | |
10373 | * once 64bpp pixel formats are supported. | |
10374 | */ | |
587c7914 | 10375 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 10376 | |
b432e5cf | 10377 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
10378 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
10379 | cdclk, dev_priv->max_cdclk_freq); | |
10380 | return -EINVAL; | |
b432e5cf VS |
10381 | } |
10382 | ||
1a617b77 ML |
10383 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
10384 | if (!intel_state->active_crtcs) | |
587c7914 | 10385 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
10386 | |
10387 | return 0; | |
10388 | } | |
10389 | ||
27c329ed | 10390 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 10391 | { |
27c329ed | 10392 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10393 | struct intel_atomic_state *old_intel_state = |
10394 | to_intel_atomic_state(old_state); | |
10395 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 10396 | |
27c329ed | 10397 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
10398 | } |
10399 | ||
c89e39f3 CT |
10400 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
10401 | { | |
10402 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
10403 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
10404 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 10405 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
10406 | int cdclk; |
10407 | ||
10408 | /* | |
10409 | * FIXME should also account for plane ratio | |
10410 | * once 64bpp pixel formats are supported. | |
10411 | */ | |
a8ca4934 | 10412 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
10413 | |
10414 | /* | |
10415 | * FIXME move the cdclk caclulation to | |
10416 | * compute_config() so we can fail gracegully. | |
10417 | */ | |
10418 | if (cdclk > dev_priv->max_cdclk_freq) { | |
10419 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
10420 | cdclk, dev_priv->max_cdclk_freq); | |
10421 | cdclk = dev_priv->max_cdclk_freq; | |
10422 | } | |
10423 | ||
10424 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
10425 | if (!intel_state->active_crtcs) | |
a8ca4934 | 10426 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
10427 | |
10428 | return 0; | |
10429 | } | |
10430 | ||
10431 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
10432 | { | |
1cd593e0 VS |
10433 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
10434 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
10435 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
10436 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 10437 | |
1cd593e0 | 10438 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
10439 | } |
10440 | ||
190f68c5 ACO |
10441 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
10442 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 10443 | { |
d7edc4e5 | 10444 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
10445 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
10446 | return -EINVAL; | |
10447 | } | |
716c2e55 | 10448 | |
c7653199 | 10449 | crtc->lowfreq_avail = false; |
644cef34 | 10450 | |
c8f7a0db | 10451 | return 0; |
79e53945 JB |
10452 | } |
10453 | ||
3760b59c S |
10454 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
10455 | enum port port, | |
10456 | struct intel_crtc_state *pipe_config) | |
10457 | { | |
8106ddbd ACO |
10458 | enum intel_dpll_id id; |
10459 | ||
3760b59c S |
10460 | switch (port) { |
10461 | case PORT_A: | |
08250c4b | 10462 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
10463 | break; |
10464 | case PORT_B: | |
08250c4b | 10465 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
10466 | break; |
10467 | case PORT_C: | |
08250c4b | 10468 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
10469 | break; |
10470 | default: | |
10471 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 10472 | return; |
3760b59c | 10473 | } |
8106ddbd ACO |
10474 | |
10475 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
10476 | } |
10477 | ||
96b7dfb7 S |
10478 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
10479 | enum port port, | |
5cec258b | 10480 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 10481 | { |
8106ddbd | 10482 | enum intel_dpll_id id; |
a3c988ea | 10483 | u32 temp; |
96b7dfb7 S |
10484 | |
10485 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 10486 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 10487 | |
c856052a | 10488 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 10489 | return; |
8106ddbd ACO |
10490 | |
10491 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
10492 | } |
10493 | ||
7d2c8175 DL |
10494 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
10495 | enum port port, | |
5cec258b | 10496 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 10497 | { |
8106ddbd | 10498 | enum intel_dpll_id id; |
c856052a | 10499 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 10500 | |
c856052a | 10501 | switch (ddi_pll_sel) { |
7d2c8175 | 10502 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 10503 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
10504 | break; |
10505 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 10506 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 10507 | break; |
00490c22 | 10508 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 10509 | id = DPLL_ID_SPLL; |
79bd23da | 10510 | break; |
9d16da65 ACO |
10511 | case PORT_CLK_SEL_LCPLL_810: |
10512 | id = DPLL_ID_LCPLL_810; | |
10513 | break; | |
10514 | case PORT_CLK_SEL_LCPLL_1350: | |
10515 | id = DPLL_ID_LCPLL_1350; | |
10516 | break; | |
10517 | case PORT_CLK_SEL_LCPLL_2700: | |
10518 | id = DPLL_ID_LCPLL_2700; | |
10519 | break; | |
8106ddbd | 10520 | default: |
c856052a | 10521 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
10522 | /* fall through */ |
10523 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 10524 | return; |
7d2c8175 | 10525 | } |
8106ddbd ACO |
10526 | |
10527 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
10528 | } |
10529 | ||
cf30429e JN |
10530 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
10531 | struct intel_crtc_state *pipe_config, | |
10532 | unsigned long *power_domain_mask) | |
10533 | { | |
10534 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10535 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
10536 | enum intel_display_power_domain power_domain; |
10537 | u32 tmp; | |
10538 | ||
d9a7bc67 ID |
10539 | /* |
10540 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
10541 | * transcoder handled below. | |
10542 | */ | |
cf30429e JN |
10543 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
10544 | ||
10545 | /* | |
10546 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
10547 | * consistency and less surprising code; it's in always on power). | |
10548 | */ | |
10549 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
10550 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10551 | enum pipe trans_edp_pipe; | |
10552 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10553 | default: | |
10554 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10555 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10556 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10557 | trans_edp_pipe = PIPE_A; | |
10558 | break; | |
10559 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10560 | trans_edp_pipe = PIPE_B; | |
10561 | break; | |
10562 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10563 | trans_edp_pipe = PIPE_C; | |
10564 | break; | |
10565 | } | |
10566 | ||
10567 | if (trans_edp_pipe == crtc->pipe) | |
10568 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10569 | } | |
10570 | ||
10571 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
10572 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10573 | return false; | |
10574 | *power_domain_mask |= BIT(power_domain); | |
10575 | ||
10576 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
10577 | ||
10578 | return tmp & PIPECONF_ENABLE; | |
10579 | } | |
10580 | ||
4d1de975 JN |
10581 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10582 | struct intel_crtc_state *pipe_config, | |
10583 | unsigned long *power_domain_mask) | |
10584 | { | |
10585 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10586 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
10587 | enum intel_display_power_domain power_domain; |
10588 | enum port port; | |
10589 | enum transcoder cpu_transcoder; | |
10590 | u32 tmp; | |
10591 | ||
4d1de975 JN |
10592 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
10593 | if (port == PORT_A) | |
10594 | cpu_transcoder = TRANSCODER_DSI_A; | |
10595 | else | |
10596 | cpu_transcoder = TRANSCODER_DSI_C; | |
10597 | ||
10598 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10599 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10600 | continue; | |
10601 | *power_domain_mask |= BIT(power_domain); | |
10602 | ||
db18b6a6 ID |
10603 | /* |
10604 | * The PLL needs to be enabled with a valid divider | |
10605 | * configuration, otherwise accessing DSI registers will hang | |
10606 | * the machine. See BSpec North Display Engine | |
10607 | * registers/MIPI[BXT]. We can break out here early, since we | |
10608 | * need the same DSI PLL to be enabled for both DSI ports. | |
10609 | */ | |
10610 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10611 | break; | |
10612 | ||
4d1de975 JN |
10613 | /* XXX: this works for video mode only */ |
10614 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10615 | if (!(tmp & DPI_ENABLE)) | |
10616 | continue; | |
10617 | ||
10618 | tmp = I915_READ(MIPI_CTRL(port)); | |
10619 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10620 | continue; | |
10621 | ||
10622 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
10623 | break; |
10624 | } | |
10625 | ||
d7edc4e5 | 10626 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
10627 | } |
10628 | ||
26804afd | 10629 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10630 | struct intel_crtc_state *pipe_config) |
26804afd | 10631 | { |
6315b5d3 | 10632 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 10633 | struct intel_shared_dpll *pll; |
26804afd DV |
10634 | enum port port; |
10635 | uint32_t tmp; | |
10636 | ||
10637 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10638 | ||
10639 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10640 | ||
0853723b | 10641 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
96b7dfb7 | 10642 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
e2d214ae | 10643 | else if (IS_BROXTON(dev_priv)) |
3760b59c | 10644 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
10645 | else |
10646 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10647 | |
8106ddbd ACO |
10648 | pll = pipe_config->shared_dpll; |
10649 | if (pll) { | |
2edd6443 ACO |
10650 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10651 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10652 | } |
10653 | ||
26804afd DV |
10654 | /* |
10655 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10656 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10657 | * the PCH transcoder is on. | |
10658 | */ | |
6315b5d3 | 10659 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 10660 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
10661 | pipe_config->has_pch_encoder = true; |
10662 | ||
10663 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10664 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10665 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10666 | ||
10667 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10668 | } | |
10669 | } | |
10670 | ||
0e8ffe1b | 10671 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10672 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 10673 | { |
6315b5d3 | 10674 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e ID |
10675 | enum intel_display_power_domain power_domain; |
10676 | unsigned long power_domain_mask; | |
cf30429e | 10677 | bool active; |
0e8ffe1b | 10678 | |
1729050e ID |
10679 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10680 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10681 | return false; |
1729050e ID |
10682 | power_domain_mask = BIT(power_domain); |
10683 | ||
8106ddbd | 10684 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10685 | |
cf30429e | 10686 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10687 | |
d7edc4e5 VS |
10688 | if (IS_BROXTON(dev_priv) && |
10689 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { | |
10690 | WARN_ON(active); | |
10691 | active = true; | |
4d1de975 JN |
10692 | } |
10693 | ||
cf30429e | 10694 | if (!active) |
1729050e | 10695 | goto out; |
0e8ffe1b | 10696 | |
d7edc4e5 | 10697 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
10698 | haswell_get_ddi_port_state(crtc, pipe_config); |
10699 | intel_get_pipe_timings(crtc, pipe_config); | |
10700 | } | |
627eb5a3 | 10701 | |
bc58be60 | 10702 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10703 | |
05dc698c LL |
10704 | pipe_config->gamma_mode = |
10705 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10706 | ||
6315b5d3 | 10707 | if (INTEL_GEN(dev_priv) >= 9) { |
65edccce | 10708 | skl_init_scalers(dev_priv, crtc, pipe_config); |
a1b2278e | 10709 | |
af99ceda CK |
10710 | pipe_config->scaler_state.scaler_id = -1; |
10711 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10712 | } | |
10713 | ||
1729050e ID |
10714 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10715 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10716 | power_domain_mask |= BIT(power_domain); | |
6315b5d3 | 10717 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 10718 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10719 | else |
1c132b44 | 10720 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10721 | } |
88adfff1 | 10722 | |
772c2a51 | 10723 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
10724 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
10725 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10726 | |
4d1de975 JN |
10727 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10728 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10729 | pipe_config->pixel_multiplier = |
10730 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10731 | } else { | |
10732 | pipe_config->pixel_multiplier = 1; | |
10733 | } | |
6c49f241 | 10734 | |
1729050e ID |
10735 | out: |
10736 | for_each_power_domain(power_domain, power_domain_mask) | |
10737 | intel_display_power_put(dev_priv, power_domain); | |
10738 | ||
cf30429e | 10739 | return active; |
0e8ffe1b DV |
10740 | } |
10741 | ||
55a08b3f ML |
10742 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10743 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10744 | { |
10745 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10746 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 10747 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 10748 | uint32_t cntl = 0, size = 0; |
560b85bb | 10749 | |
936e71e3 | 10750 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
10751 | unsigned int width = plane_state->base.crtc_w; |
10752 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10753 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10754 | ||
10755 | switch (stride) { | |
10756 | default: | |
10757 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10758 | width, stride); | |
10759 | stride = 256; | |
10760 | /* fallthrough */ | |
10761 | case 256: | |
10762 | case 512: | |
10763 | case 1024: | |
10764 | case 2048: | |
10765 | break; | |
4b0e333e CW |
10766 | } |
10767 | ||
dc41c154 VS |
10768 | cntl |= CURSOR_ENABLE | |
10769 | CURSOR_GAMMA_ENABLE | | |
10770 | CURSOR_FORMAT_ARGB | | |
10771 | CURSOR_STRIDE(stride); | |
10772 | ||
10773 | size = (height << 12) | width; | |
4b0e333e | 10774 | } |
560b85bb | 10775 | |
dc41c154 VS |
10776 | if (intel_crtc->cursor_cntl != 0 && |
10777 | (intel_crtc->cursor_base != base || | |
10778 | intel_crtc->cursor_size != size || | |
10779 | intel_crtc->cursor_cntl != cntl)) { | |
10780 | /* On these chipsets we can only modify the base/size/stride | |
10781 | * whilst the cursor is disabled. | |
10782 | */ | |
0b87c24e VS |
10783 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10784 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10785 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10786 | } |
560b85bb | 10787 | |
99d1f387 | 10788 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10789 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10790 | intel_crtc->cursor_base = base; |
10791 | } | |
4726e0b0 | 10792 | |
dc41c154 VS |
10793 | if (intel_crtc->cursor_size != size) { |
10794 | I915_WRITE(CURSIZE, size); | |
10795 | intel_crtc->cursor_size = size; | |
4b0e333e | 10796 | } |
560b85bb | 10797 | |
4b0e333e | 10798 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10799 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10800 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10801 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10802 | } |
560b85bb CW |
10803 | } |
10804 | ||
55a08b3f ML |
10805 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10806 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10807 | { |
10808 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10809 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
10810 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10811 | int pipe = intel_crtc->pipe; | |
663f3122 | 10812 | uint32_t cntl = 0; |
4b0e333e | 10813 | |
936e71e3 | 10814 | if (plane_state && plane_state->base.visible) { |
4b0e333e | 10815 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10816 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10817 | case 64: |
10818 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10819 | break; | |
10820 | case 128: | |
10821 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10822 | break; | |
10823 | case 256: | |
10824 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10825 | break; | |
10826 | default: | |
55a08b3f | 10827 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10828 | return; |
65a21cd6 | 10829 | } |
4b0e333e | 10830 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10831 | |
4f8036a2 | 10832 | if (HAS_DDI(dev_priv)) |
47bf17a7 | 10833 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10834 | |
f22aa143 | 10835 | if (plane_state->base.rotation & DRM_ROTATE_180) |
55a08b3f ML |
10836 | cntl |= CURSOR_ROTATE_180; |
10837 | } | |
4398ad45 | 10838 | |
4b0e333e CW |
10839 | if (intel_crtc->cursor_cntl != cntl) { |
10840 | I915_WRITE(CURCNTR(pipe), cntl); | |
10841 | POSTING_READ(CURCNTR(pipe)); | |
10842 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10843 | } |
4b0e333e | 10844 | |
65a21cd6 | 10845 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10846 | I915_WRITE(CURBASE(pipe), base); |
10847 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10848 | |
10849 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10850 | } |
10851 | ||
cda4b7d3 | 10852 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10853 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10854 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10855 | { |
10856 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10857 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
10858 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10859 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10860 | u32 base = intel_crtc->cursor_addr; |
10861 | u32 pos = 0; | |
cda4b7d3 | 10862 | |
55a08b3f ML |
10863 | if (plane_state) { |
10864 | int x = plane_state->base.crtc_x; | |
10865 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10866 | |
55a08b3f ML |
10867 | if (x < 0) { |
10868 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10869 | x = -x; | |
10870 | } | |
10871 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10872 | |
55a08b3f ML |
10873 | if (y < 0) { |
10874 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10875 | y = -y; | |
10876 | } | |
10877 | pos |= y << CURSOR_Y_SHIFT; | |
10878 | ||
10879 | /* ILK+ do this automagically */ | |
49cff963 | 10880 | if (HAS_GMCH_DISPLAY(dev_priv) && |
f22aa143 | 10881 | plane_state->base.rotation & DRM_ROTATE_180) { |
55a08b3f ML |
10882 | base += (plane_state->base.crtc_h * |
10883 | plane_state->base.crtc_w - 1) * 4; | |
10884 | } | |
cda4b7d3 | 10885 | } |
cda4b7d3 | 10886 | |
5efb3e28 VS |
10887 | I915_WRITE(CURPOS(pipe), pos); |
10888 | ||
50a0bc90 | 10889 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) |
55a08b3f | 10890 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10891 | else |
55a08b3f | 10892 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10893 | } |
10894 | ||
50a0bc90 | 10895 | static bool cursor_size_ok(struct drm_i915_private *dev_priv, |
dc41c154 VS |
10896 | uint32_t width, uint32_t height) |
10897 | { | |
10898 | if (width == 0 || height == 0) | |
10899 | return false; | |
10900 | ||
10901 | /* | |
10902 | * 845g/865g are special in that they are only limited by | |
10903 | * the width of their cursors, the height is arbitrary up to | |
10904 | * the precision of the register. Everything else requires | |
10905 | * square cursors, limited to a few power-of-two sizes. | |
10906 | */ | |
50a0bc90 | 10907 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { |
dc41c154 VS |
10908 | if ((width & 63) != 0) |
10909 | return false; | |
10910 | ||
50a0bc90 | 10911 | if (width > (IS_845G(dev_priv) ? 64 : 512)) |
dc41c154 VS |
10912 | return false; |
10913 | ||
10914 | if (height > 1023) | |
10915 | return false; | |
10916 | } else { | |
10917 | switch (width | height) { | |
10918 | case 256: | |
10919 | case 128: | |
50a0bc90 | 10920 | if (IS_GEN2(dev_priv)) |
dc41c154 VS |
10921 | return false; |
10922 | case 64: | |
10923 | break; | |
10924 | default: | |
10925 | return false; | |
10926 | } | |
10927 | } | |
10928 | ||
10929 | return true; | |
10930 | } | |
10931 | ||
79e53945 JB |
10932 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10933 | static struct drm_display_mode load_detect_mode = { | |
10934 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10935 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10936 | }; | |
10937 | ||
a8bb6818 DV |
10938 | struct drm_framebuffer * |
10939 | __intel_framebuffer_create(struct drm_device *dev, | |
10940 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10941 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10942 | { |
10943 | struct intel_framebuffer *intel_fb; | |
10944 | int ret; | |
10945 | ||
10946 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10947 | if (!intel_fb) |
d2dff872 | 10948 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10949 | |
10950 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10951 | if (ret) |
10952 | goto err; | |
d2dff872 CW |
10953 | |
10954 | return &intel_fb->base; | |
dcb1394e | 10955 | |
dd4916c5 | 10956 | err: |
dd4916c5 | 10957 | kfree(intel_fb); |
dd4916c5 | 10958 | return ERR_PTR(ret); |
d2dff872 CW |
10959 | } |
10960 | ||
b5ea642a | 10961 | static struct drm_framebuffer * |
a8bb6818 DV |
10962 | intel_framebuffer_create(struct drm_device *dev, |
10963 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10964 | struct drm_i915_gem_object *obj) | |
10965 | { | |
10966 | struct drm_framebuffer *fb; | |
10967 | int ret; | |
10968 | ||
10969 | ret = i915_mutex_lock_interruptible(dev); | |
10970 | if (ret) | |
10971 | return ERR_PTR(ret); | |
10972 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10973 | mutex_unlock(&dev->struct_mutex); | |
10974 | ||
10975 | return fb; | |
10976 | } | |
10977 | ||
d2dff872 CW |
10978 | static u32 |
10979 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10980 | { | |
10981 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10982 | return ALIGN(pitch, 64); | |
10983 | } | |
10984 | ||
10985 | static u32 | |
10986 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10987 | { | |
10988 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10989 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10990 | } |
10991 | ||
10992 | static struct drm_framebuffer * | |
10993 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10994 | struct drm_display_mode *mode, | |
10995 | int depth, int bpp) | |
10996 | { | |
dcb1394e | 10997 | struct drm_framebuffer *fb; |
d2dff872 | 10998 | struct drm_i915_gem_object *obj; |
0fed39bd | 10999 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 11000 | |
12d79d78 | 11001 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 11002 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
11003 | if (IS_ERR(obj)) |
11004 | return ERR_CAST(obj); | |
d2dff872 CW |
11005 | |
11006 | mode_cmd.width = mode->hdisplay; | |
11007 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
11008 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
11009 | bpp); | |
5ca0c34a | 11010 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 11011 | |
dcb1394e LW |
11012 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
11013 | if (IS_ERR(fb)) | |
f0cd5182 | 11014 | i915_gem_object_put(obj); |
dcb1394e LW |
11015 | |
11016 | return fb; | |
d2dff872 CW |
11017 | } |
11018 | ||
11019 | static struct drm_framebuffer * | |
11020 | mode_fits_in_fbdev(struct drm_device *dev, | |
11021 | struct drm_display_mode *mode) | |
11022 | { | |
0695726e | 11023 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 11024 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
11025 | struct drm_i915_gem_object *obj; |
11026 | struct drm_framebuffer *fb; | |
11027 | ||
4c0e5528 | 11028 | if (!dev_priv->fbdev) |
d2dff872 CW |
11029 | return NULL; |
11030 | ||
4c0e5528 | 11031 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
11032 | return NULL; |
11033 | ||
4c0e5528 DV |
11034 | obj = dev_priv->fbdev->fb->obj; |
11035 | BUG_ON(!obj); | |
11036 | ||
8bcd4553 | 11037 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
11038 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
11039 | fb->bits_per_pixel)) | |
d2dff872 CW |
11040 | return NULL; |
11041 | ||
01f2c773 | 11042 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
11043 | return NULL; |
11044 | ||
edde3617 | 11045 | drm_framebuffer_reference(fb); |
d2dff872 | 11046 | return fb; |
4520f53a DV |
11047 | #else |
11048 | return NULL; | |
11049 | #endif | |
d2dff872 CW |
11050 | } |
11051 | ||
d3a40d1b ACO |
11052 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
11053 | struct drm_crtc *crtc, | |
11054 | struct drm_display_mode *mode, | |
11055 | struct drm_framebuffer *fb, | |
11056 | int x, int y) | |
11057 | { | |
11058 | struct drm_plane_state *plane_state; | |
11059 | int hdisplay, vdisplay; | |
11060 | int ret; | |
11061 | ||
11062 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
11063 | if (IS_ERR(plane_state)) | |
11064 | return PTR_ERR(plane_state); | |
11065 | ||
11066 | if (mode) | |
11067 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
11068 | else | |
11069 | hdisplay = vdisplay = 0; | |
11070 | ||
11071 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
11072 | if (ret) | |
11073 | return ret; | |
11074 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11075 | plane_state->crtc_x = 0; | |
11076 | plane_state->crtc_y = 0; | |
11077 | plane_state->crtc_w = hdisplay; | |
11078 | plane_state->crtc_h = vdisplay; | |
11079 | plane_state->src_x = x << 16; | |
11080 | plane_state->src_y = y << 16; | |
11081 | plane_state->src_w = hdisplay << 16; | |
11082 | plane_state->src_h = vdisplay << 16; | |
11083 | ||
11084 | return 0; | |
11085 | } | |
11086 | ||
d2434ab7 | 11087 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 11088 | struct drm_display_mode *mode, |
51fd371b RC |
11089 | struct intel_load_detect_pipe *old, |
11090 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
11091 | { |
11092 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
11093 | struct intel_encoder *intel_encoder = |
11094 | intel_attached_encoder(connector); | |
79e53945 | 11095 | struct drm_crtc *possible_crtc; |
4ef69c7a | 11096 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
11097 | struct drm_crtc *crtc = NULL; |
11098 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 11099 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 11100 | struct drm_framebuffer *fb; |
51fd371b | 11101 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 11102 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 11103 | struct drm_connector_state *connector_state; |
4be07317 | 11104 | struct intel_crtc_state *crtc_state; |
51fd371b | 11105 | int ret, i = -1; |
79e53945 | 11106 | |
d2dff872 | 11107 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 11108 | connector->base.id, connector->name, |
8e329a03 | 11109 | encoder->base.id, encoder->name); |
d2dff872 | 11110 | |
edde3617 ML |
11111 | old->restore_state = NULL; |
11112 | ||
51fd371b RC |
11113 | retry: |
11114 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
11115 | if (ret) | |
ad3c558f | 11116 | goto fail; |
6e9f798d | 11117 | |
79e53945 JB |
11118 | /* |
11119 | * Algorithm gets a little messy: | |
7a5e4805 | 11120 | * |
79e53945 JB |
11121 | * - if the connector already has an assigned crtc, use it (but make |
11122 | * sure it's on first) | |
7a5e4805 | 11123 | * |
79e53945 JB |
11124 | * - try to find the first unused crtc that can drive this connector, |
11125 | * and use that if we find one | |
79e53945 JB |
11126 | */ |
11127 | ||
11128 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
11129 | if (connector->state->crtc) { |
11130 | crtc = connector->state->crtc; | |
8261b191 | 11131 | |
51fd371b | 11132 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 11133 | if (ret) |
ad3c558f | 11134 | goto fail; |
8261b191 CW |
11135 | |
11136 | /* Make sure the crtc and connector are running */ | |
edde3617 | 11137 | goto found; |
79e53945 JB |
11138 | } |
11139 | ||
11140 | /* Find an unused one (if possible) */ | |
70e1e0ec | 11141 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
11142 | i++; |
11143 | if (!(encoder->possible_crtcs & (1 << i))) | |
11144 | continue; | |
edde3617 ML |
11145 | |
11146 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
11147 | if (ret) | |
11148 | goto fail; | |
11149 | ||
11150 | if (possible_crtc->state->enable) { | |
11151 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 11152 | continue; |
edde3617 | 11153 | } |
a459249c VS |
11154 | |
11155 | crtc = possible_crtc; | |
11156 | break; | |
79e53945 JB |
11157 | } |
11158 | ||
11159 | /* | |
11160 | * If we didn't find an unused CRTC, don't use any. | |
11161 | */ | |
11162 | if (!crtc) { | |
7173188d | 11163 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 11164 | goto fail; |
79e53945 JB |
11165 | } |
11166 | ||
edde3617 ML |
11167 | found: |
11168 | intel_crtc = to_intel_crtc(crtc); | |
11169 | ||
4d02e2de DV |
11170 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
11171 | if (ret) | |
ad3c558f | 11172 | goto fail; |
79e53945 | 11173 | |
83a57153 | 11174 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
11175 | restore_state = drm_atomic_state_alloc(dev); |
11176 | if (!state || !restore_state) { | |
11177 | ret = -ENOMEM; | |
11178 | goto fail; | |
11179 | } | |
83a57153 ACO |
11180 | |
11181 | state->acquire_ctx = ctx; | |
edde3617 | 11182 | restore_state->acquire_ctx = ctx; |
83a57153 | 11183 | |
944b0c76 ACO |
11184 | connector_state = drm_atomic_get_connector_state(state, connector); |
11185 | if (IS_ERR(connector_state)) { | |
11186 | ret = PTR_ERR(connector_state); | |
11187 | goto fail; | |
11188 | } | |
11189 | ||
edde3617 ML |
11190 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
11191 | if (ret) | |
11192 | goto fail; | |
944b0c76 | 11193 | |
4be07317 ACO |
11194 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
11195 | if (IS_ERR(crtc_state)) { | |
11196 | ret = PTR_ERR(crtc_state); | |
11197 | goto fail; | |
11198 | } | |
11199 | ||
49d6fa21 | 11200 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 11201 | |
6492711d CW |
11202 | if (!mode) |
11203 | mode = &load_detect_mode; | |
79e53945 | 11204 | |
d2dff872 CW |
11205 | /* We need a framebuffer large enough to accommodate all accesses |
11206 | * that the plane may generate whilst we perform load detection. | |
11207 | * We can not rely on the fbcon either being present (we get called | |
11208 | * during its initialisation to detect all boot displays, or it may | |
11209 | * not even exist) or that it is large enough to satisfy the | |
11210 | * requested mode. | |
11211 | */ | |
94352cf9 DV |
11212 | fb = mode_fits_in_fbdev(dev, mode); |
11213 | if (fb == NULL) { | |
d2dff872 | 11214 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 11215 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
11216 | } else |
11217 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 11218 | if (IS_ERR(fb)) { |
d2dff872 | 11219 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 11220 | goto fail; |
79e53945 | 11221 | } |
79e53945 | 11222 | |
d3a40d1b ACO |
11223 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
11224 | if (ret) | |
11225 | goto fail; | |
11226 | ||
edde3617 ML |
11227 | drm_framebuffer_unreference(fb); |
11228 | ||
11229 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
11230 | if (ret) | |
11231 | goto fail; | |
11232 | ||
11233 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
11234 | if (!ret) | |
11235 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
11236 | if (!ret) | |
11237 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
11238 | if (ret) { | |
11239 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
11240 | goto fail; | |
11241 | } | |
8c7b5ccb | 11242 | |
3ba86073 ML |
11243 | ret = drm_atomic_commit(state); |
11244 | if (ret) { | |
6492711d | 11245 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 11246 | goto fail; |
79e53945 | 11247 | } |
edde3617 ML |
11248 | |
11249 | old->restore_state = restore_state; | |
7173188d | 11250 | |
79e53945 | 11251 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 11252 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 11253 | return true; |
412b61d8 | 11254 | |
ad3c558f | 11255 | fail: |
7fb71c8f CW |
11256 | if (state) { |
11257 | drm_atomic_state_put(state); | |
11258 | state = NULL; | |
11259 | } | |
11260 | if (restore_state) { | |
11261 | drm_atomic_state_put(restore_state); | |
11262 | restore_state = NULL; | |
11263 | } | |
83a57153 | 11264 | |
51fd371b RC |
11265 | if (ret == -EDEADLK) { |
11266 | drm_modeset_backoff(ctx); | |
11267 | goto retry; | |
11268 | } | |
11269 | ||
412b61d8 | 11270 | return false; |
79e53945 JB |
11271 | } |
11272 | ||
d2434ab7 | 11273 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
11274 | struct intel_load_detect_pipe *old, |
11275 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 11276 | { |
d2434ab7 DV |
11277 | struct intel_encoder *intel_encoder = |
11278 | intel_attached_encoder(connector); | |
4ef69c7a | 11279 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 11280 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 11281 | int ret; |
79e53945 | 11282 | |
d2dff872 | 11283 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 11284 | connector->base.id, connector->name, |
8e329a03 | 11285 | encoder->base.id, encoder->name); |
d2dff872 | 11286 | |
edde3617 | 11287 | if (!state) |
0622a53c | 11288 | return; |
79e53945 | 11289 | |
edde3617 | 11290 | ret = drm_atomic_commit(state); |
0853695c | 11291 | if (ret) |
edde3617 | 11292 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 11293 | drm_atomic_state_put(state); |
79e53945 JB |
11294 | } |
11295 | ||
da4a1efa | 11296 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 11297 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 11298 | { |
fac5e23e | 11299 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
11300 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
11301 | ||
11302 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 11303 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 11304 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 11305 | return 120000; |
5db94019 | 11306 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
11307 | return 96000; |
11308 | else | |
11309 | return 48000; | |
11310 | } | |
11311 | ||
79e53945 | 11312 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 11313 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 11314 | struct intel_crtc_state *pipe_config) |
79e53945 | 11315 | { |
f1f644dc | 11316 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 11317 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 11318 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 11319 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 11320 | u32 fp; |
9e2c8475 | 11321 | struct dpll clock; |
dccbea3b | 11322 | int port_clock; |
da4a1efa | 11323 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
11324 | |
11325 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 11326 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 11327 | else |
293623f7 | 11328 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
11329 | |
11330 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 11331 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
11332 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
11333 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
11334 | } else { |
11335 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
11336 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
11337 | } | |
11338 | ||
5db94019 | 11339 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 11340 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
11341 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
11342 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
11343 | else |
11344 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
11345 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
11346 | ||
11347 | switch (dpll & DPLL_MODE_MASK) { | |
11348 | case DPLLB_MODE_DAC_SERIAL: | |
11349 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
11350 | 5 : 10; | |
11351 | break; | |
11352 | case DPLLB_MODE_LVDS: | |
11353 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
11354 | 7 : 14; | |
11355 | break; | |
11356 | default: | |
28c97730 | 11357 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 11358 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 11359 | return; |
79e53945 JB |
11360 | } |
11361 | ||
9b1e14f4 | 11362 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 11363 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 11364 | else |
dccbea3b | 11365 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 11366 | } else { |
50a0bc90 | 11367 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 11368 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
11369 | |
11370 | if (is_lvds) { | |
11371 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
11372 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
11373 | |
11374 | if (lvds & LVDS_CLKB_POWER_UP) | |
11375 | clock.p2 = 7; | |
11376 | else | |
11377 | clock.p2 = 14; | |
79e53945 JB |
11378 | } else { |
11379 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
11380 | clock.p1 = 2; | |
11381 | else { | |
11382 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
11383 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
11384 | } | |
11385 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
11386 | clock.p2 = 4; | |
11387 | else | |
11388 | clock.p2 = 2; | |
79e53945 | 11389 | } |
da4a1efa | 11390 | |
dccbea3b | 11391 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
11392 | } |
11393 | ||
18442d08 VS |
11394 | /* |
11395 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 11396 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
11397 | * encoder's get_config() function. |
11398 | */ | |
dccbea3b | 11399 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
11400 | } |
11401 | ||
6878da05 VS |
11402 | int intel_dotclock_calculate(int link_freq, |
11403 | const struct intel_link_m_n *m_n) | |
f1f644dc | 11404 | { |
f1f644dc JB |
11405 | /* |
11406 | * The calculation for the data clock is: | |
1041a02f | 11407 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 11408 | * But we want to avoid losing precison if possible, so: |
1041a02f | 11409 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
11410 | * |
11411 | * and the link clock is simpler: | |
1041a02f | 11412 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
11413 | */ |
11414 | ||
6878da05 VS |
11415 | if (!m_n->link_n) |
11416 | return 0; | |
f1f644dc | 11417 | |
6878da05 VS |
11418 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
11419 | } | |
f1f644dc | 11420 | |
18442d08 | 11421 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 11422 | struct intel_crtc_state *pipe_config) |
6878da05 | 11423 | { |
e3b247da | 11424 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 11425 | |
18442d08 VS |
11426 | /* read out port_clock from the DPLL */ |
11427 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 11428 | |
f1f644dc | 11429 | /* |
e3b247da VS |
11430 | * In case there is an active pipe without active ports, |
11431 | * we may need some idea for the dotclock anyway. | |
11432 | * Calculate one based on the FDI configuration. | |
79e53945 | 11433 | */ |
2d112de7 | 11434 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 11435 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 11436 | &pipe_config->fdi_m_n); |
79e53945 JB |
11437 | } |
11438 | ||
11439 | /** Returns the currently programmed mode of the given pipe. */ | |
11440 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
11441 | struct drm_crtc *crtc) | |
11442 | { | |
fac5e23e | 11443 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 11444 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 11445 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 11446 | struct drm_display_mode *mode; |
3f36b937 | 11447 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
11448 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
11449 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11450 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
11451 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 11452 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
11453 | |
11454 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
11455 | if (!mode) | |
11456 | return NULL; | |
11457 | ||
3f36b937 TU |
11458 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
11459 | if (!pipe_config) { | |
11460 | kfree(mode); | |
11461 | return NULL; | |
11462 | } | |
11463 | ||
f1f644dc JB |
11464 | /* |
11465 | * Construct a pipe_config sufficient for getting the clock info | |
11466 | * back out of crtc_clock_get. | |
11467 | * | |
11468 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
11469 | * to use a real value here instead. | |
11470 | */ | |
3f36b937 TU |
11471 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
11472 | pipe_config->pixel_multiplier = 1; | |
11473 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
11474 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
11475 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
11476 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
11477 | ||
11478 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
11479 | mode->hdisplay = (htot & 0xffff) + 1; |
11480 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
11481 | mode->hsync_start = (hsync & 0xffff) + 1; | |
11482 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
11483 | mode->vdisplay = (vtot & 0xffff) + 1; | |
11484 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
11485 | mode->vsync_start = (vsync & 0xffff) + 1; | |
11486 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
11487 | ||
11488 | drm_mode_set_name(mode); | |
79e53945 | 11489 | |
3f36b937 TU |
11490 | kfree(pipe_config); |
11491 | ||
79e53945 JB |
11492 | return mode; |
11493 | } | |
11494 | ||
11495 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
11496 | { | |
11497 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 11498 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 11499 | struct intel_flip_work *work; |
67e77c5a | 11500 | |
5e2d7afc | 11501 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
11502 | work = intel_crtc->flip_work; |
11503 | intel_crtc->flip_work = NULL; | |
11504 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 11505 | |
5a21b665 | 11506 | if (work) { |
51cbaf01 ML |
11507 | cancel_work_sync(&work->mmio_work); |
11508 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 11509 | kfree(work); |
67e77c5a | 11510 | } |
79e53945 JB |
11511 | |
11512 | drm_crtc_cleanup(crtc); | |
67e77c5a | 11513 | |
79e53945 JB |
11514 | kfree(intel_crtc); |
11515 | } | |
11516 | ||
6b95a207 KH |
11517 | static void intel_unpin_work_fn(struct work_struct *__work) |
11518 | { | |
51cbaf01 ML |
11519 | struct intel_flip_work *work = |
11520 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
11521 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
11522 | struct drm_device *dev = crtc->base.dev; | |
11523 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 11524 | |
5a21b665 DV |
11525 | if (is_mmio_work(work)) |
11526 | flush_work(&work->mmio_work); | |
03f476e1 | 11527 | |
5a21b665 DV |
11528 | mutex_lock(&dev->struct_mutex); |
11529 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
f8c417cd | 11530 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 11531 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 11532 | |
e8a261ea CW |
11533 | i915_gem_request_put(work->flip_queued_req); |
11534 | ||
5748b6a1 CW |
11535 | intel_frontbuffer_flip_complete(to_i915(dev), |
11536 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
11537 | intel_fbc_post_update(crtc); |
11538 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 11539 | |
5a21b665 DV |
11540 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11541 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 11542 | |
5a21b665 DV |
11543 | kfree(work); |
11544 | } | |
d9e86c0e | 11545 | |
5a21b665 DV |
11546 | /* Is 'a' after or equal to 'b'? */ |
11547 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11548 | { | |
11549 | return !((a - b) & 0x80000000); | |
11550 | } | |
143f73b3 | 11551 | |
5a21b665 DV |
11552 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
11553 | struct intel_flip_work *work) | |
11554 | { | |
11555 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11556 | struct drm_i915_private *dev_priv = to_i915(dev); |
143f73b3 | 11557 | |
8af29b0c | 11558 | if (abort_flip_on_reset(crtc)) |
5a21b665 | 11559 | return true; |
143f73b3 | 11560 | |
5a21b665 DV |
11561 | /* |
11562 | * The relevant registers doen't exist on pre-ctg. | |
11563 | * As the flip done interrupt doesn't trigger for mmio | |
11564 | * flips on gmch platforms, a flip count check isn't | |
11565 | * really needed there. But since ctg has the registers, | |
11566 | * include it in the check anyway. | |
11567 | */ | |
9beb5fea | 11568 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
5a21b665 | 11569 | return true; |
b4a98e57 | 11570 | |
5a21b665 DV |
11571 | /* |
11572 | * BDW signals flip done immediately if the plane | |
11573 | * is disabled, even if the plane enable is already | |
11574 | * armed to occur at the next vblank :( | |
11575 | */ | |
f99d7069 | 11576 | |
5a21b665 DV |
11577 | /* |
11578 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11579 | * used the same base address. In that case the mmio flip might | |
11580 | * have completed, but the CS hasn't even executed the flip yet. | |
11581 | * | |
11582 | * A flip count check isn't enough as the CS might have updated | |
11583 | * the base address just after start of vblank, but before we | |
11584 | * managed to process the interrupt. This means we'd complete the | |
11585 | * CS flip too soon. | |
11586 | * | |
11587 | * Combining both checks should get us a good enough result. It may | |
11588 | * still happen that the CS flip has been executed, but has not | |
11589 | * yet actually completed. But in case the base address is the same | |
11590 | * anyway, we don't really care. | |
11591 | */ | |
11592 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11593 | crtc->flip_work->gtt_offset && | |
11594 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11595 | crtc->flip_work->flip_count); | |
11596 | } | |
b4a98e57 | 11597 | |
5a21b665 DV |
11598 | static bool |
11599 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11600 | struct intel_flip_work *work) | |
11601 | { | |
11602 | /* | |
11603 | * MMIO work completes when vblank is different from | |
11604 | * flip_queued_vblank. | |
11605 | * | |
11606 | * Reset counter value doesn't matter, this is handled by | |
11607 | * i915_wait_request finishing early, so no need to handle | |
11608 | * reset here. | |
11609 | */ | |
11610 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11611 | } |
11612 | ||
51cbaf01 ML |
11613 | |
11614 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11615 | struct intel_flip_work *work) | |
11616 | { | |
11617 | if (!atomic_read(&work->pending)) | |
11618 | return false; | |
11619 | ||
11620 | smp_rmb(); | |
11621 | ||
5a21b665 DV |
11622 | if (is_mmio_work(work)) |
11623 | return __pageflip_finished_mmio(crtc, work); | |
11624 | else | |
11625 | return __pageflip_finished_cs(crtc, work); | |
11626 | } | |
11627 | ||
11628 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11629 | { | |
91c8a326 | 11630 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 11631 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
11632 | struct intel_flip_work *work; |
11633 | unsigned long flags; | |
11634 | ||
11635 | /* Ignore early vblank irqs */ | |
11636 | if (!crtc) | |
11637 | return; | |
11638 | ||
51cbaf01 | 11639 | /* |
5a21b665 DV |
11640 | * This is called both by irq handlers and the reset code (to complete |
11641 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11642 | */ |
5a21b665 | 11643 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 11644 | work = crtc->flip_work; |
5a21b665 DV |
11645 | |
11646 | if (work != NULL && | |
11647 | !is_mmio_work(work) && | |
e2af48c6 VS |
11648 | pageflip_finished(crtc, work)) |
11649 | page_flip_completed(crtc); | |
5a21b665 DV |
11650 | |
11651 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11652 | } |
11653 | ||
51cbaf01 | 11654 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11655 | { |
91c8a326 | 11656 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 11657 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
51cbaf01 | 11658 | struct intel_flip_work *work; |
6b95a207 KH |
11659 | unsigned long flags; |
11660 | ||
5251f04e ML |
11661 | /* Ignore early vblank irqs */ |
11662 | if (!crtc) | |
11663 | return; | |
f326038a DV |
11664 | |
11665 | /* | |
11666 | * This is called both by irq handlers and the reset code (to complete | |
11667 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11668 | */ |
6b95a207 | 11669 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 11670 | work = crtc->flip_work; |
5251f04e | 11671 | |
5a21b665 DV |
11672 | if (work != NULL && |
11673 | is_mmio_work(work) && | |
e2af48c6 VS |
11674 | pageflip_finished(crtc, work)) |
11675 | page_flip_completed(crtc); | |
5251f04e | 11676 | |
6b95a207 KH |
11677 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11678 | } | |
11679 | ||
5a21b665 DV |
11680 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11681 | struct intel_flip_work *work) | |
84c33a64 | 11682 | { |
5a21b665 | 11683 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11684 | |
5a21b665 DV |
11685 | /* Ensure that the work item is consistent when activating it ... */ |
11686 | smp_mb__before_atomic(); | |
11687 | atomic_set(&work->pending, 1); | |
11688 | } | |
a6747b73 | 11689 | |
5a21b665 DV |
11690 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11691 | struct drm_crtc *crtc, | |
11692 | struct drm_framebuffer *fb, | |
11693 | struct drm_i915_gem_object *obj, | |
11694 | struct drm_i915_gem_request *req, | |
11695 | uint32_t flags) | |
11696 | { | |
7e37f889 | 11697 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11698 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11699 | u32 flip_mask; | |
11700 | int ret; | |
143f73b3 | 11701 | |
5a21b665 DV |
11702 | ret = intel_ring_begin(req, 6); |
11703 | if (ret) | |
11704 | return ret; | |
143f73b3 | 11705 | |
5a21b665 DV |
11706 | /* Can't queue multiple flips, so wait for the previous |
11707 | * one to finish before executing the next. | |
11708 | */ | |
11709 | if (intel_crtc->plane) | |
11710 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11711 | else | |
11712 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11713 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11714 | intel_ring_emit(ring, MI_NOOP); | |
11715 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
5a21b665 | 11716 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11717 | intel_ring_emit(ring, fb->pitches[0]); |
11718 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11719 | intel_ring_emit(ring, 0); /* aux display base address, unused */ | |
143f73b3 | 11720 | |
5a21b665 DV |
11721 | return 0; |
11722 | } | |
84c33a64 | 11723 | |
5a21b665 DV |
11724 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11725 | struct drm_crtc *crtc, | |
11726 | struct drm_framebuffer *fb, | |
11727 | struct drm_i915_gem_object *obj, | |
11728 | struct drm_i915_gem_request *req, | |
11729 | uint32_t flags) | |
11730 | { | |
7e37f889 | 11731 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11732 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11733 | u32 flip_mask; | |
11734 | int ret; | |
d55dbd06 | 11735 | |
5a21b665 DV |
11736 | ret = intel_ring_begin(req, 6); |
11737 | if (ret) | |
11738 | return ret; | |
d55dbd06 | 11739 | |
5a21b665 DV |
11740 | if (intel_crtc->plane) |
11741 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11742 | else | |
11743 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11744 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11745 | intel_ring_emit(ring, MI_NOOP); | |
11746 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
5a21b665 | 11747 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11748 | intel_ring_emit(ring, fb->pitches[0]); |
11749 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11750 | intel_ring_emit(ring, MI_NOOP); | |
fd8e058a | 11751 | |
5a21b665 DV |
11752 | return 0; |
11753 | } | |
84c33a64 | 11754 | |
5a21b665 DV |
11755 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11756 | struct drm_crtc *crtc, | |
11757 | struct drm_framebuffer *fb, | |
11758 | struct drm_i915_gem_object *obj, | |
11759 | struct drm_i915_gem_request *req, | |
11760 | uint32_t flags) | |
11761 | { | |
7e37f889 | 11762 | struct intel_ring *ring = req->ring; |
fac5e23e | 11763 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11764 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11765 | uint32_t pf, pipesrc; | |
11766 | int ret; | |
143f73b3 | 11767 | |
5a21b665 DV |
11768 | ret = intel_ring_begin(req, 4); |
11769 | if (ret) | |
11770 | return ret; | |
143f73b3 | 11771 | |
5a21b665 DV |
11772 | /* i965+ uses the linear or tiled offsets from the |
11773 | * Display Registers (which do not change across a page-flip) | |
11774 | * so we need only reprogram the base address. | |
11775 | */ | |
b5321f30 | 11776 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11777 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11778 | intel_ring_emit(ring, fb->pitches[0]); |
11779 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset | | |
72618ebf | 11780 | intel_fb_modifier_to_tiling(fb->modifier[0])); |
5a21b665 DV |
11781 | |
11782 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11783 | * untested on non-native modes, so ignore it for now. | |
11784 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11785 | */ | |
11786 | pf = 0; | |
11787 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11788 | intel_ring_emit(ring, pf | pipesrc); |
143f73b3 | 11789 | |
5a21b665 | 11790 | return 0; |
8c9f3aaf JB |
11791 | } |
11792 | ||
5a21b665 DV |
11793 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11794 | struct drm_crtc *crtc, | |
11795 | struct drm_framebuffer *fb, | |
11796 | struct drm_i915_gem_object *obj, | |
11797 | struct drm_i915_gem_request *req, | |
11798 | uint32_t flags) | |
da20eabd | 11799 | { |
7e37f889 | 11800 | struct intel_ring *ring = req->ring; |
fac5e23e | 11801 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11803 | uint32_t pf, pipesrc; | |
11804 | int ret; | |
d21fbe87 | 11805 | |
5a21b665 DV |
11806 | ret = intel_ring_begin(req, 4); |
11807 | if (ret) | |
11808 | return ret; | |
92826fcd | 11809 | |
b5321f30 | 11810 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11811 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
72618ebf VS |
11812 | intel_ring_emit(ring, fb->pitches[0] | |
11813 | intel_fb_modifier_to_tiling(fb->modifier[0])); | |
b5321f30 | 11814 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
92826fcd | 11815 | |
5a21b665 DV |
11816 | /* Contrary to the suggestions in the documentation, |
11817 | * "Enable Panel Fitter" does not seem to be required when page | |
11818 | * flipping with a non-native mode, and worse causes a normal | |
11819 | * modeset to fail. | |
11820 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11821 | */ | |
11822 | pf = 0; | |
11823 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11824 | intel_ring_emit(ring, pf | pipesrc); |
7809e5ae | 11825 | |
5a21b665 | 11826 | return 0; |
7809e5ae MR |
11827 | } |
11828 | ||
5a21b665 DV |
11829 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11830 | struct drm_crtc *crtc, | |
11831 | struct drm_framebuffer *fb, | |
11832 | struct drm_i915_gem_object *obj, | |
11833 | struct drm_i915_gem_request *req, | |
11834 | uint32_t flags) | |
d21fbe87 | 11835 | { |
5db94019 | 11836 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e37f889 | 11837 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11838 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11839 | uint32_t plane_bit = 0; | |
11840 | int len, ret; | |
d21fbe87 | 11841 | |
5a21b665 DV |
11842 | switch (intel_crtc->plane) { |
11843 | case PLANE_A: | |
11844 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11845 | break; | |
11846 | case PLANE_B: | |
11847 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11848 | break; | |
11849 | case PLANE_C: | |
11850 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11851 | break; | |
11852 | default: | |
11853 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11854 | return -ENODEV; | |
11855 | } | |
11856 | ||
11857 | len = 4; | |
b5321f30 | 11858 | if (req->engine->id == RCS) { |
5a21b665 DV |
11859 | len += 6; |
11860 | /* | |
11861 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11862 | * 48bits addresses, and we need a NOOP for the batch size to | |
11863 | * stay even. | |
11864 | */ | |
5db94019 | 11865 | if (IS_GEN8(dev_priv)) |
5a21b665 DV |
11866 | len += 2; |
11867 | } | |
11868 | ||
11869 | /* | |
11870 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11871 | * "The full packet must be contained within the same cache line." | |
11872 | * | |
11873 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11874 | * cacheline, if we ever start emitting more commands before | |
11875 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11876 | * then do the cacheline alignment, and finally emit the | |
11877 | * MI_DISPLAY_FLIP. | |
11878 | */ | |
11879 | ret = intel_ring_cacheline_align(req); | |
11880 | if (ret) | |
11881 | return ret; | |
11882 | ||
11883 | ret = intel_ring_begin(req, len); | |
11884 | if (ret) | |
11885 | return ret; | |
11886 | ||
11887 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11888 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11889 | * more than one flip event at any time (or ensure that one flip message | |
11890 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11891 | * Experimentation says that BCS works despite DERRMR masking all | |
11892 | * flip-done completion events and that unmasking all planes at once | |
11893 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11894 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11895 | */ | |
b5321f30 CW |
11896 | if (req->engine->id == RCS) { |
11897 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11898 | intel_ring_emit_reg(ring, DERRMR); | |
11899 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
5a21b665 DV |
11900 | DERRMR_PIPEB_PRI_FLIP_DONE | |
11901 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
5db94019 | 11902 | if (IS_GEN8(dev_priv)) |
b5321f30 | 11903 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
5a21b665 DV |
11904 | MI_SRM_LRM_GLOBAL_GTT); |
11905 | else | |
b5321f30 | 11906 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
5a21b665 | 11907 | MI_SRM_LRM_GLOBAL_GTT); |
b5321f30 | 11908 | intel_ring_emit_reg(ring, DERRMR); |
bde13ebd CW |
11909 | intel_ring_emit(ring, |
11910 | i915_ggtt_offset(req->engine->scratch) + 256); | |
5db94019 | 11911 | if (IS_GEN8(dev_priv)) { |
b5321f30 CW |
11912 | intel_ring_emit(ring, 0); |
11913 | intel_ring_emit(ring, MI_NOOP); | |
5a21b665 DV |
11914 | } |
11915 | } | |
11916 | ||
b5321f30 | 11917 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
72618ebf VS |
11918 | intel_ring_emit(ring, fb->pitches[0] | |
11919 | intel_fb_modifier_to_tiling(fb->modifier[0])); | |
b5321f30 CW |
11920 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
11921 | intel_ring_emit(ring, (MI_NOOP)); | |
5a21b665 DV |
11922 | |
11923 | return 0; | |
11924 | } | |
11925 | ||
11926 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11927 | struct drm_i915_gem_object *obj) | |
11928 | { | |
11929 | /* | |
11930 | * This is not being used for older platforms, because | |
11931 | * non-availability of flip done interrupt forces us to use | |
11932 | * CS flips. Older platforms derive flip done using some clever | |
11933 | * tricks involving the flip_pending status bits and vblank irqs. | |
11934 | * So using MMIO flips there would disrupt this mechanism. | |
11935 | */ | |
11936 | ||
11937 | if (engine == NULL) | |
11938 | return true; | |
11939 | ||
11940 | if (INTEL_GEN(engine->i915) < 5) | |
11941 | return false; | |
11942 | ||
11943 | if (i915.use_mmio_flip < 0) | |
11944 | return false; | |
11945 | else if (i915.use_mmio_flip > 0) | |
11946 | return true; | |
11947 | else if (i915.enable_execlists) | |
11948 | return true; | |
c37efb99 | 11949 | |
d07f0e59 | 11950 | return engine != i915_gem_object_last_write_engine(obj); |
5a21b665 DV |
11951 | } |
11952 | ||
11953 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11954 | unsigned int rotation, | |
11955 | struct intel_flip_work *work) | |
11956 | { | |
11957 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11958 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11959 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
11960 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 11961 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
11962 | |
11963 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11964 | ctl &= ~PLANE_CTL_TILED_MASK; | |
11965 | switch (fb->modifier[0]) { | |
11966 | case DRM_FORMAT_MOD_NONE: | |
11967 | break; | |
11968 | case I915_FORMAT_MOD_X_TILED: | |
11969 | ctl |= PLANE_CTL_TILED_X; | |
11970 | break; | |
11971 | case I915_FORMAT_MOD_Y_TILED: | |
11972 | ctl |= PLANE_CTL_TILED_Y; | |
11973 | break; | |
11974 | case I915_FORMAT_MOD_Yf_TILED: | |
11975 | ctl |= PLANE_CTL_TILED_YF; | |
11976 | break; | |
11977 | default: | |
11978 | MISSING_CASE(fb->modifier[0]); | |
11979 | } | |
11980 | ||
5a21b665 DV |
11981 | /* |
11982 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11983 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11984 | */ | |
11985 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11986 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11987 | ||
11988 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
11989 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11990 | } | |
11991 | ||
11992 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11993 | struct intel_flip_work *work) | |
11994 | { | |
11995 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11996 | struct drm_i915_private *dev_priv = to_i915(dev); |
72618ebf | 11997 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
5a21b665 DV |
11998 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
11999 | u32 dspcntr; | |
12000 | ||
12001 | dspcntr = I915_READ(reg); | |
12002 | ||
72618ebf | 12003 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
5a21b665 DV |
12004 | dspcntr |= DISPPLANE_TILED; |
12005 | else | |
12006 | dspcntr &= ~DISPPLANE_TILED; | |
12007 | ||
12008 | I915_WRITE(reg, dspcntr); | |
12009 | ||
12010 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
12011 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
12012 | } | |
12013 | ||
12014 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
12015 | { | |
12016 | struct intel_flip_work *work = | |
12017 | container_of(w, struct intel_flip_work, mmio_work); | |
12018 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
12019 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
12020 | struct intel_framebuffer *intel_fb = | |
12021 | to_intel_framebuffer(crtc->base.primary->fb); | |
12022 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
12023 | ||
d07f0e59 | 12024 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); |
5a21b665 DV |
12025 | |
12026 | intel_pipe_update_start(crtc); | |
12027 | ||
12028 | if (INTEL_GEN(dev_priv) >= 9) | |
12029 | skl_do_mmio_flip(crtc, work->rotation, work); | |
12030 | else | |
12031 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
12032 | ilk_do_mmio_flip(crtc, work); | |
12033 | ||
12034 | intel_pipe_update_end(crtc, work); | |
12035 | } | |
12036 | ||
12037 | static int intel_default_queue_flip(struct drm_device *dev, | |
12038 | struct drm_crtc *crtc, | |
12039 | struct drm_framebuffer *fb, | |
12040 | struct drm_i915_gem_object *obj, | |
12041 | struct drm_i915_gem_request *req, | |
12042 | uint32_t flags) | |
12043 | { | |
12044 | return -ENODEV; | |
12045 | } | |
12046 | ||
12047 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
12048 | struct intel_crtc *intel_crtc, | |
12049 | struct intel_flip_work *work) | |
12050 | { | |
12051 | u32 addr, vblank; | |
12052 | ||
12053 | if (!atomic_read(&work->pending)) | |
12054 | return false; | |
12055 | ||
12056 | smp_rmb(); | |
12057 | ||
12058 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
12059 | if (work->flip_ready_vblank == 0) { | |
12060 | if (work->flip_queued_req && | |
f69a02c9 | 12061 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
12062 | return false; |
12063 | ||
12064 | work->flip_ready_vblank = vblank; | |
12065 | } | |
12066 | ||
12067 | if (vblank - work->flip_ready_vblank < 3) | |
12068 | return false; | |
12069 | ||
12070 | /* Potential stall - if we see that the flip has happened, | |
12071 | * assume a missed interrupt. */ | |
12072 | if (INTEL_GEN(dev_priv) >= 4) | |
12073 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
12074 | else | |
12075 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
12076 | ||
12077 | /* There is a potential issue here with a false positive after a flip | |
12078 | * to the same address. We could address this by checking for a | |
12079 | * non-incrementing frame counter. | |
12080 | */ | |
12081 | return addr == work->gtt_offset; | |
12082 | } | |
12083 | ||
12084 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
12085 | { | |
91c8a326 | 12086 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 12087 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
12088 | struct intel_flip_work *work; |
12089 | ||
12090 | WARN_ON(!in_interrupt()); | |
12091 | ||
12092 | if (crtc == NULL) | |
12093 | return; | |
12094 | ||
12095 | spin_lock(&dev->event_lock); | |
e2af48c6 | 12096 | work = crtc->flip_work; |
5a21b665 DV |
12097 | |
12098 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 12099 | __pageflip_stall_check_cs(dev_priv, crtc, work)) { |
5a21b665 DV |
12100 | WARN_ONCE(1, |
12101 | "Kicking stuck page flip: queued at %d, now %d\n", | |
e2af48c6 VS |
12102 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); |
12103 | page_flip_completed(crtc); | |
5a21b665 DV |
12104 | work = NULL; |
12105 | } | |
12106 | ||
12107 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 12108 | intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) |
5a21b665 DV |
12109 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
12110 | spin_unlock(&dev->event_lock); | |
12111 | } | |
12112 | ||
12113 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
12114 | struct drm_framebuffer *fb, | |
12115 | struct drm_pending_vblank_event *event, | |
12116 | uint32_t page_flip_flags) | |
12117 | { | |
12118 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 12119 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
12120 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
12121 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12122 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12123 | struct drm_plane *primary = crtc->primary; | |
12124 | enum pipe pipe = intel_crtc->pipe; | |
12125 | struct intel_flip_work *work; | |
12126 | struct intel_engine_cs *engine; | |
12127 | bool mmio_flip; | |
8e637178 | 12128 | struct drm_i915_gem_request *request; |
058d88c4 | 12129 | struct i915_vma *vma; |
5a21b665 DV |
12130 | int ret; |
12131 | ||
12132 | /* | |
12133 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
12134 | * check to be safe. In the future we may enable pageflipping from | |
12135 | * a disabled primary plane. | |
12136 | */ | |
12137 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
12138 | return -EBUSY; | |
12139 | ||
12140 | /* Can't change pixel format via MI display flips. */ | |
12141 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
12142 | return -EINVAL; | |
12143 | ||
12144 | /* | |
12145 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
12146 | * Note that pitch changes could also affect these register. | |
12147 | */ | |
6315b5d3 | 12148 | if (INTEL_GEN(dev_priv) > 3 && |
5a21b665 DV |
12149 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
12150 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
12151 | return -EINVAL; | |
12152 | ||
12153 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
12154 | goto out_hang; | |
12155 | ||
12156 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
12157 | if (work == NULL) | |
12158 | return -ENOMEM; | |
12159 | ||
12160 | work->event = event; | |
12161 | work->crtc = crtc; | |
12162 | work->old_fb = old_fb; | |
12163 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
12164 | ||
12165 | ret = drm_crtc_vblank_get(crtc); | |
12166 | if (ret) | |
12167 | goto free_work; | |
12168 | ||
12169 | /* We borrow the event spin lock for protecting flip_work */ | |
12170 | spin_lock_irq(&dev->event_lock); | |
12171 | if (intel_crtc->flip_work) { | |
12172 | /* Before declaring the flip queue wedged, check if | |
12173 | * the hardware completed the operation behind our backs. | |
12174 | */ | |
12175 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
12176 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
12177 | page_flip_completed(intel_crtc); | |
12178 | } else { | |
12179 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
12180 | spin_unlock_irq(&dev->event_lock); | |
12181 | ||
12182 | drm_crtc_vblank_put(crtc); | |
12183 | kfree(work); | |
12184 | return -EBUSY; | |
12185 | } | |
12186 | } | |
12187 | intel_crtc->flip_work = work; | |
12188 | spin_unlock_irq(&dev->event_lock); | |
12189 | ||
12190 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
12191 | flush_workqueue(dev_priv->wq); | |
12192 | ||
12193 | /* Reference the objects for the scheduled work. */ | |
12194 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
12195 | |
12196 | crtc->primary->fb = fb; | |
12197 | update_state_fb(crtc->primary); | |
faf68d92 | 12198 | |
25dc556a | 12199 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
12200 | |
12201 | ret = i915_mutex_lock_interruptible(dev); | |
12202 | if (ret) | |
12203 | goto cleanup; | |
12204 | ||
8af29b0c CW |
12205 | intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); |
12206 | if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) { | |
5a21b665 | 12207 | ret = -EIO; |
ddbb271a | 12208 | goto unlock; |
5a21b665 DV |
12209 | } |
12210 | ||
12211 | atomic_inc(&intel_crtc->unpin_work_count); | |
12212 | ||
9beb5fea | 12213 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
5a21b665 DV |
12214 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
12215 | ||
920a14b2 | 12216 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3b3f1650 | 12217 | engine = dev_priv->engine[BCS]; |
72618ebf | 12218 | if (fb->modifier[0] != old_fb->modifier[0]) |
5a21b665 DV |
12219 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
12220 | engine = NULL; | |
fd6b8f43 | 12221 | } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { |
3b3f1650 | 12222 | engine = dev_priv->engine[BCS]; |
6315b5d3 | 12223 | } else if (INTEL_GEN(dev_priv) >= 7) { |
d07f0e59 | 12224 | engine = i915_gem_object_last_write_engine(obj); |
5a21b665 | 12225 | if (engine == NULL || engine->id != RCS) |
3b3f1650 | 12226 | engine = dev_priv->engine[BCS]; |
5a21b665 | 12227 | } else { |
3b3f1650 | 12228 | engine = dev_priv->engine[RCS]; |
5a21b665 DV |
12229 | } |
12230 | ||
12231 | mmio_flip = use_mmio_flip(engine, obj); | |
12232 | ||
058d88c4 CW |
12233 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
12234 | if (IS_ERR(vma)) { | |
12235 | ret = PTR_ERR(vma); | |
5a21b665 | 12236 | goto cleanup_pending; |
058d88c4 | 12237 | } |
5a21b665 | 12238 | |
6687c906 | 12239 | work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation); |
5a21b665 DV |
12240 | work->gtt_offset += intel_crtc->dspaddr_offset; |
12241 | work->rotation = crtc->primary->state->rotation; | |
12242 | ||
1f061316 PZ |
12243 | /* |
12244 | * There's the potential that the next frame will not be compatible with | |
12245 | * FBC, so we want to call pre_update() before the actual page flip. | |
12246 | * The problem is that pre_update() caches some information about the fb | |
12247 | * object, so we want to do this only after the object is pinned. Let's | |
12248 | * be on the safe side and do this immediately before scheduling the | |
12249 | * flip. | |
12250 | */ | |
12251 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
12252 | to_intel_plane_state(primary->state)); | |
12253 | ||
5a21b665 DV |
12254 | if (mmio_flip) { |
12255 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
6277c8d0 | 12256 | queue_work(system_unbound_wq, &work->mmio_work); |
5a21b665 | 12257 | } else { |
8e637178 CW |
12258 | request = i915_gem_request_alloc(engine, engine->last_context); |
12259 | if (IS_ERR(request)) { | |
12260 | ret = PTR_ERR(request); | |
12261 | goto cleanup_unpin; | |
12262 | } | |
12263 | ||
a2bc4695 | 12264 | ret = i915_gem_request_await_object(request, obj, false); |
8e637178 CW |
12265 | if (ret) |
12266 | goto cleanup_request; | |
12267 | ||
5a21b665 DV |
12268 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
12269 | page_flip_flags); | |
12270 | if (ret) | |
8e637178 | 12271 | goto cleanup_request; |
5a21b665 DV |
12272 | |
12273 | intel_mark_page_flip_active(intel_crtc, work); | |
12274 | ||
8e637178 | 12275 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
12276 | i915_add_request_no_flush(request); |
12277 | } | |
12278 | ||
92117f0b | 12279 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); |
5a21b665 DV |
12280 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, |
12281 | to_intel_plane(primary)->frontbuffer_bit); | |
12282 | mutex_unlock(&dev->struct_mutex); | |
12283 | ||
5748b6a1 | 12284 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
12285 | to_intel_plane(primary)->frontbuffer_bit); |
12286 | ||
12287 | trace_i915_flip_request(intel_crtc->plane, obj); | |
12288 | ||
12289 | return 0; | |
12290 | ||
8e637178 CW |
12291 | cleanup_request: |
12292 | i915_add_request_no_flush(request); | |
5a21b665 DV |
12293 | cleanup_unpin: |
12294 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
12295 | cleanup_pending: | |
5a21b665 | 12296 | atomic_dec(&intel_crtc->unpin_work_count); |
ddbb271a | 12297 | unlock: |
5a21b665 DV |
12298 | mutex_unlock(&dev->struct_mutex); |
12299 | cleanup: | |
12300 | crtc->primary->fb = old_fb; | |
12301 | update_state_fb(crtc->primary); | |
12302 | ||
f0cd5182 | 12303 | i915_gem_object_put(obj); |
5a21b665 DV |
12304 | drm_framebuffer_unreference(work->old_fb); |
12305 | ||
12306 | spin_lock_irq(&dev->event_lock); | |
12307 | intel_crtc->flip_work = NULL; | |
12308 | spin_unlock_irq(&dev->event_lock); | |
12309 | ||
12310 | drm_crtc_vblank_put(crtc); | |
12311 | free_work: | |
12312 | kfree(work); | |
12313 | ||
12314 | if (ret == -EIO) { | |
12315 | struct drm_atomic_state *state; | |
12316 | struct drm_plane_state *plane_state; | |
12317 | ||
12318 | out_hang: | |
12319 | state = drm_atomic_state_alloc(dev); | |
12320 | if (!state) | |
12321 | return -ENOMEM; | |
12322 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
12323 | ||
12324 | retry: | |
12325 | plane_state = drm_atomic_get_plane_state(state, primary); | |
12326 | ret = PTR_ERR_OR_ZERO(plane_state); | |
12327 | if (!ret) { | |
12328 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
12329 | ||
12330 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
12331 | if (!ret) | |
12332 | ret = drm_atomic_commit(state); | |
12333 | } | |
12334 | ||
12335 | if (ret == -EDEADLK) { | |
12336 | drm_modeset_backoff(state->acquire_ctx); | |
12337 | drm_atomic_state_clear(state); | |
12338 | goto retry; | |
12339 | } | |
12340 | ||
0853695c | 12341 | drm_atomic_state_put(state); |
5a21b665 DV |
12342 | |
12343 | if (ret == 0 && event) { | |
12344 | spin_lock_irq(&dev->event_lock); | |
12345 | drm_crtc_send_vblank_event(crtc, event); | |
12346 | spin_unlock_irq(&dev->event_lock); | |
12347 | } | |
12348 | } | |
12349 | return ret; | |
12350 | } | |
12351 | ||
12352 | ||
12353 | /** | |
12354 | * intel_wm_need_update - Check whether watermarks need updating | |
12355 | * @plane: drm plane | |
12356 | * @state: new plane state | |
12357 | * | |
12358 | * Check current plane state versus the new one to determine whether | |
12359 | * watermarks need to be recalculated. | |
12360 | * | |
12361 | * Returns true or false. | |
12362 | */ | |
12363 | static bool intel_wm_need_update(struct drm_plane *plane, | |
12364 | struct drm_plane_state *state) | |
12365 | { | |
12366 | struct intel_plane_state *new = to_intel_plane_state(state); | |
12367 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
12368 | ||
12369 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 12370 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
12371 | return true; |
12372 | ||
12373 | if (!cur->base.fb || !new->base.fb) | |
12374 | return false; | |
12375 | ||
12376 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
12377 | cur->base.rotation != new->base.rotation || | |
936e71e3 VS |
12378 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
12379 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
12380 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
12381 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
12382 | return true; |
12383 | ||
12384 | return false; | |
12385 | } | |
12386 | ||
12387 | static bool needs_scaling(struct intel_plane_state *state) | |
12388 | { | |
936e71e3 VS |
12389 | int src_w = drm_rect_width(&state->base.src) >> 16; |
12390 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
12391 | int dst_w = drm_rect_width(&state->base.dst); | |
12392 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
12393 | |
12394 | return (src_w != dst_w || src_h != dst_h); | |
12395 | } | |
d21fbe87 | 12396 | |
da20eabd ML |
12397 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
12398 | struct drm_plane_state *plane_state) | |
12399 | { | |
ab1d3a0e | 12400 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
12401 | struct drm_crtc *crtc = crtc_state->crtc; |
12402 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12403 | struct drm_plane *plane = plane_state->plane; | |
12404 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 12405 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
12406 | struct intel_plane_state *old_plane_state = |
12407 | to_intel_plane_state(plane->state); | |
da20eabd ML |
12408 | bool mode_changed = needs_modeset(crtc_state); |
12409 | bool was_crtc_enabled = crtc->state->active; | |
12410 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
12411 | bool turn_off, turn_on, visible, was_visible; |
12412 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 12413 | int ret; |
da20eabd | 12414 | |
55b8f2a7 | 12415 | if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
12416 | ret = skl_update_scaler_plane( |
12417 | to_intel_crtc_state(crtc_state), | |
12418 | to_intel_plane_state(plane_state)); | |
12419 | if (ret) | |
12420 | return ret; | |
12421 | } | |
12422 | ||
936e71e3 VS |
12423 | was_visible = old_plane_state->base.visible; |
12424 | visible = to_intel_plane_state(plane_state)->base.visible; | |
da20eabd ML |
12425 | |
12426 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
12427 | was_visible = false; | |
12428 | ||
35c08f43 ML |
12429 | /* |
12430 | * Visibility is calculated as if the crtc was on, but | |
12431 | * after scaler setup everything depends on it being off | |
12432 | * when the crtc isn't active. | |
f818ffea VS |
12433 | * |
12434 | * FIXME this is wrong for watermarks. Watermarks should also | |
12435 | * be computed as if the pipe would be active. Perhaps move | |
12436 | * per-plane wm computation to the .check_plane() hook, and | |
12437 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
12438 | */ |
12439 | if (!is_crtc_enabled) | |
936e71e3 | 12440 | to_intel_plane_state(plane_state)->base.visible = visible = false; |
da20eabd ML |
12441 | |
12442 | if (!was_visible && !visible) | |
12443 | return 0; | |
12444 | ||
e8861675 ML |
12445 | if (fb != old_plane_state->base.fb) |
12446 | pipe_config->fb_changed = true; | |
12447 | ||
da20eabd ML |
12448 | turn_off = was_visible && (!visible || mode_changed); |
12449 | turn_on = visible && (!was_visible || mode_changed); | |
12450 | ||
72660ce0 | 12451 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
12452 | intel_crtc->base.base.id, |
12453 | intel_crtc->base.name, | |
72660ce0 VS |
12454 | plane->base.id, plane->name, |
12455 | fb ? fb->base.id : -1); | |
da20eabd | 12456 | |
72660ce0 VS |
12457 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
12458 | plane->base.id, plane->name, | |
12459 | was_visible, visible, | |
da20eabd ML |
12460 | turn_off, turn_on, mode_changed); |
12461 | ||
caed361d VS |
12462 | if (turn_on) { |
12463 | pipe_config->update_wm_pre = true; | |
12464 | ||
12465 | /* must disable cxsr around plane enable/disable */ | |
12466 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
12467 | pipe_config->disable_cxsr = true; | |
12468 | } else if (turn_off) { | |
12469 | pipe_config->update_wm_post = true; | |
92826fcd | 12470 | |
852eb00d | 12471 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 12472 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 12473 | pipe_config->disable_cxsr = true; |
852eb00d | 12474 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
12475 | /* FIXME bollocks */ |
12476 | pipe_config->update_wm_pre = true; | |
12477 | pipe_config->update_wm_post = true; | |
852eb00d | 12478 | } |
da20eabd | 12479 | |
ed4a6a7c | 12480 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d | 12481 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
6315b5d3 | 12482 | INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks) |
ed4a6a7c MR |
12483 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
12484 | ||
8be6ca85 | 12485 | if (visible || was_visible) |
cd202f69 | 12486 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 12487 | |
31ae71fc ML |
12488 | /* |
12489 | * WaCxSRDisabledForSpriteScaling:ivb | |
12490 | * | |
12491 | * cstate->update_wm was already set above, so this flag will | |
12492 | * take effect when we commit and program watermarks. | |
12493 | */ | |
fd6b8f43 | 12494 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
12495 | needs_scaling(to_intel_plane_state(plane_state)) && |
12496 | !needs_scaling(old_plane_state)) | |
12497 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 12498 | |
da20eabd ML |
12499 | return 0; |
12500 | } | |
12501 | ||
6d3a1ce7 ML |
12502 | static bool encoders_cloneable(const struct intel_encoder *a, |
12503 | const struct intel_encoder *b) | |
12504 | { | |
12505 | /* masks could be asymmetric, so check both ways */ | |
12506 | return a == b || (a->cloneable & (1 << b->type) && | |
12507 | b->cloneable & (1 << a->type)); | |
12508 | } | |
12509 | ||
12510 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12511 | struct intel_crtc *crtc, | |
12512 | struct intel_encoder *encoder) | |
12513 | { | |
12514 | struct intel_encoder *source_encoder; | |
12515 | struct drm_connector *connector; | |
12516 | struct drm_connector_state *connector_state; | |
12517 | int i; | |
12518 | ||
12519 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12520 | if (connector_state->crtc != &crtc->base) | |
12521 | continue; | |
12522 | ||
12523 | source_encoder = | |
12524 | to_intel_encoder(connector_state->best_encoder); | |
12525 | if (!encoders_cloneable(encoder, source_encoder)) | |
12526 | return false; | |
12527 | } | |
12528 | ||
12529 | return true; | |
12530 | } | |
12531 | ||
6d3a1ce7 ML |
12532 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
12533 | struct drm_crtc_state *crtc_state) | |
12534 | { | |
cf5a15be | 12535 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12536 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 12537 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12538 | struct intel_crtc_state *pipe_config = |
12539 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12540 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12541 | int ret; |
6d3a1ce7 ML |
12542 | bool mode_changed = needs_modeset(crtc_state); |
12543 | ||
852eb00d | 12544 | if (mode_changed && !crtc_state->active) |
caed361d | 12545 | pipe_config->update_wm_post = true; |
eddfcbcd | 12546 | |
ad421372 ML |
12547 | if (mode_changed && crtc_state->enable && |
12548 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 12549 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
12550 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12551 | pipe_config); | |
12552 | if (ret) | |
12553 | return ret; | |
12554 | } | |
12555 | ||
82cf435b LL |
12556 | if (crtc_state->color_mgmt_changed) { |
12557 | ret = intel_color_check(crtc, crtc_state); | |
12558 | if (ret) | |
12559 | return ret; | |
e7852a4b LL |
12560 | |
12561 | /* | |
12562 | * Changing color management on Intel hardware is | |
12563 | * handled as part of planes update. | |
12564 | */ | |
12565 | crtc_state->planes_changed = true; | |
82cf435b LL |
12566 | } |
12567 | ||
e435d6e5 | 12568 | ret = 0; |
86c8bbbe | 12569 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12570 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12571 | if (ret) { |
12572 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12573 | return ret; | |
12574 | } | |
12575 | } | |
12576 | ||
12577 | if (dev_priv->display.compute_intermediate_wm && | |
12578 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12579 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12580 | return 0; | |
12581 | ||
12582 | /* | |
12583 | * Calculate 'intermediate' watermarks that satisfy both the | |
12584 | * old state and the new state. We can program these | |
12585 | * immediately. | |
12586 | */ | |
6315b5d3 | 12587 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
12588 | intel_crtc, |
12589 | pipe_config); | |
12590 | if (ret) { | |
12591 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12592 | return ret; |
ed4a6a7c | 12593 | } |
e3d5457c VS |
12594 | } else if (dev_priv->display.compute_intermediate_wm) { |
12595 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12596 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12597 | } |
12598 | ||
6315b5d3 | 12599 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
12600 | if (mode_changed) |
12601 | ret = skl_update_scaler_crtc(pipe_config); | |
12602 | ||
12603 | if (!ret) | |
12604 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12605 | pipe_config); | |
12606 | } | |
12607 | ||
12608 | return ret; | |
6d3a1ce7 ML |
12609 | } |
12610 | ||
65b38e0d | 12611 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12612 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12613 | .atomic_begin = intel_begin_crtc_commit, |
12614 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12615 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12616 | }; |
12617 | ||
d29b2f9d ACO |
12618 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12619 | { | |
12620 | struct intel_connector *connector; | |
12621 | ||
12622 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12623 | if (connector->base.state->crtc) |
12624 | drm_connector_unreference(&connector->base); | |
12625 | ||
d29b2f9d ACO |
12626 | if (connector->base.encoder) { |
12627 | connector->base.state->best_encoder = | |
12628 | connector->base.encoder; | |
12629 | connector->base.state->crtc = | |
12630 | connector->base.encoder->crtc; | |
8863dc7f DV |
12631 | |
12632 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12633 | } else { |
12634 | connector->base.state->best_encoder = NULL; | |
12635 | connector->base.state->crtc = NULL; | |
12636 | } | |
12637 | } | |
12638 | } | |
12639 | ||
050f7aeb | 12640 | static void |
eba905b2 | 12641 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12642 | struct intel_crtc_state *pipe_config) |
050f7aeb | 12643 | { |
6a2a5c5d | 12644 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
12645 | int bpp = pipe_config->pipe_bpp; |
12646 | ||
12647 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
12648 | connector->base.base.id, |
12649 | connector->base.name); | |
050f7aeb DV |
12650 | |
12651 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 12652 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 12653 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
12654 | bpp, info->bpc * 3); |
12655 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
12656 | } |
12657 | ||
196f954e | 12658 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 12659 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
12660 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
12661 | bpp); | |
12662 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
12663 | } |
12664 | } | |
12665 | ||
4e53c2e0 | 12666 | static int |
050f7aeb | 12667 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12668 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12669 | { |
9beb5fea | 12670 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 12671 | struct drm_atomic_state *state; |
da3ced29 ACO |
12672 | struct drm_connector *connector; |
12673 | struct drm_connector_state *connector_state; | |
1486017f | 12674 | int bpp, i; |
4e53c2e0 | 12675 | |
9beb5fea TU |
12676 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
12677 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 12678 | bpp = 10*3; |
9beb5fea | 12679 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
12680 | bpp = 12*3; |
12681 | else | |
12682 | bpp = 8*3; | |
12683 | ||
4e53c2e0 | 12684 | |
4e53c2e0 DV |
12685 | pipe_config->pipe_bpp = bpp; |
12686 | ||
1486017f ACO |
12687 | state = pipe_config->base.state; |
12688 | ||
4e53c2e0 | 12689 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12690 | for_each_connector_in_state(state, connector, connector_state, i) { |
12691 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12692 | continue; |
12693 | ||
da3ced29 ACO |
12694 | connected_sink_compute_bpp(to_intel_connector(connector), |
12695 | pipe_config); | |
4e53c2e0 DV |
12696 | } |
12697 | ||
12698 | return bpp; | |
12699 | } | |
12700 | ||
644db711 DV |
12701 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12702 | { | |
12703 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12704 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12705 | mode->crtc_clock, |
644db711 DV |
12706 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12707 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12708 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12709 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12710 | } | |
12711 | ||
f6982332 TU |
12712 | static inline void |
12713 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 12714 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 12715 | { |
a4309657 TU |
12716 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
12717 | id, lane_count, | |
f6982332 TU |
12718 | m_n->gmch_m, m_n->gmch_n, |
12719 | m_n->link_m, m_n->link_n, m_n->tu); | |
12720 | } | |
12721 | ||
c0b03411 | 12722 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12723 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12724 | const char *context) |
12725 | { | |
6a60cd87 | 12726 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 12727 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
12728 | struct drm_plane *plane; |
12729 | struct intel_plane *intel_plane; | |
12730 | struct intel_plane_state *state; | |
12731 | struct drm_framebuffer *fb; | |
12732 | ||
66766e4f TU |
12733 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
12734 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 12735 | |
2c89429e TU |
12736 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
12737 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 12738 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
12739 | |
12740 | if (pipe_config->has_pch_encoder) | |
12741 | intel_dump_m_n_config(pipe_config, "fdi", | |
12742 | pipe_config->fdi_lanes, | |
12743 | &pipe_config->fdi_m_n); | |
f6982332 TU |
12744 | |
12745 | if (intel_crtc_has_dp_encoder(pipe_config)) { | |
a4309657 TU |
12746 | intel_dump_m_n_config(pipe_config, "dp m_n", |
12747 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
12748 | if (pipe_config->has_drrs) |
12749 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
12750 | pipe_config->lane_count, | |
12751 | &pipe_config->dp_m2_n2); | |
f6982332 | 12752 | } |
b95af8be | 12753 | |
55072d19 | 12754 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 12755 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 12756 | |
c0b03411 | 12757 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12758 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12759 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12760 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12761 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
2c89429e TU |
12762 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n", |
12763 | pipe_config->port_clock, | |
37327abd | 12764 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
dd2f616d TU |
12765 | |
12766 | if (INTEL_GEN(dev_priv) >= 9) | |
12767 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
12768 | crtc->num_scalers, | |
12769 | pipe_config->scaler_state.scaler_users, | |
12770 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
12771 | |
12772 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
12773 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
12774 | pipe_config->gmch_pfit.control, | |
12775 | pipe_config->gmch_pfit.pgm_ratios, | |
12776 | pipe_config->gmch_pfit.lvds_border_bits); | |
12777 | else | |
12778 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
12779 | pipe_config->pch_pfit.pos, | |
12780 | pipe_config->pch_pfit.size, | |
08c4d7fc | 12781 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 12782 | |
2c89429e TU |
12783 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
12784 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 12785 | |
e2d214ae | 12786 | if (IS_BROXTON(dev_priv)) { |
c856052a | 12787 | DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12788 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12789 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 | 12790 | pipe_config->dpll_hw_state.ebb0, |
05712c15 | 12791 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12792 | pipe_config->dpll_hw_state.pll0, |
12793 | pipe_config->dpll_hw_state.pll1, | |
12794 | pipe_config->dpll_hw_state.pll2, | |
12795 | pipe_config->dpll_hw_state.pll3, | |
12796 | pipe_config->dpll_hw_state.pll6, | |
12797 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12798 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12799 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12800 | pipe_config->dpll_hw_state.pcsdw12); |
0853723b | 12801 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
c856052a | 12802 | DRM_DEBUG_KMS("dpll_hw_state: " |
415ff0f6 | 12803 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", |
415ff0f6 TU |
12804 | pipe_config->dpll_hw_state.ctrl1, |
12805 | pipe_config->dpll_hw_state.cfgcr1, | |
12806 | pipe_config->dpll_hw_state.cfgcr2); | |
4f8036a2 | 12807 | } else if (HAS_DDI(dev_priv)) { |
c856052a | 12808 | DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
00490c22 ML |
12809 | pipe_config->dpll_hw_state.wrpll, |
12810 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12811 | } else { |
12812 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12813 | "fp0: 0x%x, fp1: 0x%x\n", | |
12814 | pipe_config->dpll_hw_state.dpll, | |
12815 | pipe_config->dpll_hw_state.dpll_md, | |
12816 | pipe_config->dpll_hw_state.fp0, | |
12817 | pipe_config->dpll_hw_state.fp1); | |
12818 | } | |
12819 | ||
6a60cd87 CK |
12820 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12821 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 12822 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
12823 | intel_plane = to_intel_plane(plane); |
12824 | if (intel_plane->pipe != crtc->pipe) | |
12825 | continue; | |
12826 | ||
12827 | state = to_intel_plane_state(plane->state); | |
12828 | fb = state->base.fb; | |
12829 | if (!fb) { | |
1d577e02 VS |
12830 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12831 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12832 | continue; |
12833 | } | |
12834 | ||
dd2f616d TU |
12835 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
12836 | plane->base.id, plane->name, | |
b3c11ac2 EE |
12837 | fb->base.id, fb->width, fb->height, |
12838 | drm_get_format_name(fb->pixel_format, &format_name)); | |
dd2f616d TU |
12839 | if (INTEL_GEN(dev_priv) >= 9) |
12840 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
12841 | state->scaler_id, | |
12842 | state->base.src.x1 >> 16, | |
12843 | state->base.src.y1 >> 16, | |
12844 | drm_rect_width(&state->base.src) >> 16, | |
12845 | drm_rect_height(&state->base.src) >> 16, | |
12846 | state->base.dst.x1, state->base.dst.y1, | |
12847 | drm_rect_width(&state->base.dst), | |
12848 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 12849 | } |
c0b03411 DV |
12850 | } |
12851 | ||
5448a00d | 12852 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12853 | { |
5448a00d | 12854 | struct drm_device *dev = state->dev; |
da3ced29 | 12855 | struct drm_connector *connector; |
00f0b378 | 12856 | unsigned int used_ports = 0; |
477321e0 | 12857 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
12858 | |
12859 | /* | |
12860 | * Walk the connector list instead of the encoder | |
12861 | * list to detect the problem on ddi platforms | |
12862 | * where there's just one encoder per digital port. | |
12863 | */ | |
0bff4858 VS |
12864 | drm_for_each_connector(connector, dev) { |
12865 | struct drm_connector_state *connector_state; | |
12866 | struct intel_encoder *encoder; | |
12867 | ||
12868 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12869 | if (!connector_state) | |
12870 | connector_state = connector->state; | |
12871 | ||
5448a00d | 12872 | if (!connector_state->best_encoder) |
00f0b378 VS |
12873 | continue; |
12874 | ||
5448a00d ACO |
12875 | encoder = to_intel_encoder(connector_state->best_encoder); |
12876 | ||
12877 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12878 | |
12879 | switch (encoder->type) { | |
12880 | unsigned int port_mask; | |
12881 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 12882 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 12883 | break; |
cca0502b | 12884 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
12885 | case INTEL_OUTPUT_HDMI: |
12886 | case INTEL_OUTPUT_EDP: | |
12887 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12888 | ||
12889 | /* the same port mustn't appear more than once */ | |
12890 | if (used_ports & port_mask) | |
12891 | return false; | |
12892 | ||
12893 | used_ports |= port_mask; | |
477321e0 VS |
12894 | break; |
12895 | case INTEL_OUTPUT_DP_MST: | |
12896 | used_mst_ports |= | |
12897 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
12898 | break; | |
00f0b378 VS |
12899 | default: |
12900 | break; | |
12901 | } | |
12902 | } | |
12903 | ||
477321e0 VS |
12904 | /* can't mix MST and SST/HDMI on the same port */ |
12905 | if (used_ports & used_mst_ports) | |
12906 | return false; | |
12907 | ||
00f0b378 VS |
12908 | return true; |
12909 | } | |
12910 | ||
83a57153 ACO |
12911 | static void |
12912 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12913 | { | |
12914 | struct drm_crtc_state tmp_state; | |
663a3640 | 12915 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12916 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12917 | struct intel_shared_dpll *shared_dpll; |
c4e2d043 | 12918 | bool force_thru; |
83a57153 | 12919 | |
7546a384 ACO |
12920 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12921 | * kzalloc'd. Code that depends on any field being zero should be | |
12922 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12923 | * only fields that are know to not cause problems are preserved. */ | |
12924 | ||
83a57153 | 12925 | tmp_state = crtc_state->base; |
663a3640 | 12926 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12927 | shared_dpll = crtc_state->shared_dpll; |
12928 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 12929 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12930 | |
83a57153 | 12931 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12932 | |
83a57153 | 12933 | crtc_state->base = tmp_state; |
663a3640 | 12934 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12935 | crtc_state->shared_dpll = shared_dpll; |
12936 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 12937 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12938 | } |
12939 | ||
548ee15b | 12940 | static int |
b8cecdf5 | 12941 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12942 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12943 | { |
b359283a | 12944 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12945 | struct intel_encoder *encoder; |
da3ced29 | 12946 | struct drm_connector *connector; |
0b901879 | 12947 | struct drm_connector_state *connector_state; |
d328c9d7 | 12948 | int base_bpp, ret = -EINVAL; |
0b901879 | 12949 | int i; |
e29c22c0 | 12950 | bool retry = true; |
ee7b9f93 | 12951 | |
83a57153 | 12952 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12953 | |
e143a21c DV |
12954 | pipe_config->cpu_transcoder = |
12955 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12956 | |
2960bc9c ID |
12957 | /* |
12958 | * Sanitize sync polarity flags based on requested ones. If neither | |
12959 | * positive or negative polarity is requested, treat this as meaning | |
12960 | * negative polarity. | |
12961 | */ | |
2d112de7 | 12962 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12963 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12964 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12965 | |
2d112de7 | 12966 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12967 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12968 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12969 | |
d328c9d7 DV |
12970 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12971 | pipe_config); | |
12972 | if (base_bpp < 0) | |
4e53c2e0 DV |
12973 | goto fail; |
12974 | ||
e41a56be VS |
12975 | /* |
12976 | * Determine the real pipe dimensions. Note that stereo modes can | |
12977 | * increase the actual pipe size due to the frame doubling and | |
12978 | * insertion of additional space for blanks between the frame. This | |
12979 | * is stored in the crtc timings. We use the requested mode to do this | |
12980 | * computation to clearly distinguish it from the adjusted mode, which | |
12981 | * can be changed by the connectors in the below retry loop. | |
12982 | */ | |
2d112de7 | 12983 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12984 | &pipe_config->pipe_src_w, |
12985 | &pipe_config->pipe_src_h); | |
e41a56be | 12986 | |
253c84c8 VS |
12987 | for_each_connector_in_state(state, connector, connector_state, i) { |
12988 | if (connector_state->crtc != crtc) | |
12989 | continue; | |
12990 | ||
12991 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12992 | ||
e25148d0 VS |
12993 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
12994 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12995 | goto fail; | |
12996 | } | |
12997 | ||
253c84c8 VS |
12998 | /* |
12999 | * Determine output_types before calling the .compute_config() | |
13000 | * hooks so that the hooks can use this information safely. | |
13001 | */ | |
13002 | pipe_config->output_types |= 1 << encoder->type; | |
13003 | } | |
13004 | ||
e29c22c0 | 13005 | encoder_retry: |
ef1b460d | 13006 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 13007 | pipe_config->port_clock = 0; |
ef1b460d | 13008 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 13009 | |
135c81b8 | 13010 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
13011 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
13012 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 13013 | |
7758a113 DV |
13014 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
13015 | * adjust it according to limitations or connector properties, and also | |
13016 | * a chance to reject the mode entirely. | |
47f1c6c9 | 13017 | */ |
da3ced29 | 13018 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 13019 | if (connector_state->crtc != crtc) |
7758a113 | 13020 | continue; |
7ae89233 | 13021 | |
0b901879 ACO |
13022 | encoder = to_intel_encoder(connector_state->best_encoder); |
13023 | ||
0a478c27 | 13024 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 13025 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
13026 | goto fail; |
13027 | } | |
ee7b9f93 | 13028 | } |
47f1c6c9 | 13029 | |
ff9a6750 DV |
13030 | /* Set default port clock if not overwritten by the encoder. Needs to be |
13031 | * done afterwards in case the encoder adjusts the mode. */ | |
13032 | if (!pipe_config->port_clock) | |
2d112de7 | 13033 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 13034 | * pipe_config->pixel_multiplier; |
ff9a6750 | 13035 | |
a43f6e0f | 13036 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 13037 | if (ret < 0) { |
7758a113 DV |
13038 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
13039 | goto fail; | |
ee7b9f93 | 13040 | } |
e29c22c0 DV |
13041 | |
13042 | if (ret == RETRY) { | |
13043 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
13044 | ret = -EINVAL; | |
13045 | goto fail; | |
13046 | } | |
13047 | ||
13048 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
13049 | retry = false; | |
13050 | goto encoder_retry; | |
13051 | } | |
13052 | ||
e8fa4270 DV |
13053 | /* Dithering seems to not pass-through bits correctly when it should, so |
13054 | * only enable it on 6bpc panels. */ | |
13055 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 13056 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 13057 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 13058 | |
7758a113 | 13059 | fail: |
548ee15b | 13060 | return ret; |
ee7b9f93 | 13061 | } |
47f1c6c9 | 13062 | |
ea9d758d | 13063 | static void |
4740b0f2 | 13064 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 13065 | { |
0a9ab303 ACO |
13066 | struct drm_crtc *crtc; |
13067 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 13068 | int i; |
ea9d758d | 13069 | |
7668851f | 13070 | /* Double check state. */ |
8a75d157 | 13071 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 13072 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
13073 | |
13074 | /* Update hwmode for vblank functions */ | |
13075 | if (crtc->state->active) | |
13076 | crtc->hwmode = crtc->state->adjusted_mode; | |
13077 | else | |
13078 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
13079 | |
13080 | /* | |
13081 | * Update legacy state to satisfy fbc code. This can | |
13082 | * be removed when fbc uses the atomic state. | |
13083 | */ | |
13084 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
13085 | struct drm_plane_state *plane_state = crtc->primary->state; | |
13086 | ||
13087 | crtc->primary->fb = plane_state->fb; | |
13088 | crtc->x = plane_state->src_x >> 16; | |
13089 | crtc->y = plane_state->src_y >> 16; | |
13090 | } | |
ea9d758d | 13091 | } |
ea9d758d DV |
13092 | } |
13093 | ||
3bd26263 | 13094 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 13095 | { |
3bd26263 | 13096 | int diff; |
f1f644dc JB |
13097 | |
13098 | if (clock1 == clock2) | |
13099 | return true; | |
13100 | ||
13101 | if (!clock1 || !clock2) | |
13102 | return false; | |
13103 | ||
13104 | diff = abs(clock1 - clock2); | |
13105 | ||
13106 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
13107 | return true; | |
13108 | ||
13109 | return false; | |
13110 | } | |
13111 | ||
cfb23ed6 ML |
13112 | static bool |
13113 | intel_compare_m_n(unsigned int m, unsigned int n, | |
13114 | unsigned int m2, unsigned int n2, | |
13115 | bool exact) | |
13116 | { | |
13117 | if (m == m2 && n == n2) | |
13118 | return true; | |
13119 | ||
13120 | if (exact || !m || !n || !m2 || !n2) | |
13121 | return false; | |
13122 | ||
13123 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
13124 | ||
31d10b57 ML |
13125 | if (n > n2) { |
13126 | while (n > n2) { | |
cfb23ed6 ML |
13127 | m2 <<= 1; |
13128 | n2 <<= 1; | |
13129 | } | |
31d10b57 ML |
13130 | } else if (n < n2) { |
13131 | while (n < n2) { | |
cfb23ed6 ML |
13132 | m <<= 1; |
13133 | n <<= 1; | |
13134 | } | |
13135 | } | |
13136 | ||
31d10b57 ML |
13137 | if (n != n2) |
13138 | return false; | |
13139 | ||
13140 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
13141 | } |
13142 | ||
13143 | static bool | |
13144 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
13145 | struct intel_link_m_n *m2_n2, | |
13146 | bool adjust) | |
13147 | { | |
13148 | if (m_n->tu == m2_n2->tu && | |
13149 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
13150 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
13151 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
13152 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
13153 | if (adjust) | |
13154 | *m2_n2 = *m_n; | |
13155 | ||
13156 | return true; | |
13157 | } | |
13158 | ||
13159 | return false; | |
13160 | } | |
13161 | ||
0e8ffe1b | 13162 | static bool |
6315b5d3 | 13163 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 13164 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
13165 | struct intel_crtc_state *pipe_config, |
13166 | bool adjust) | |
0e8ffe1b | 13167 | { |
cfb23ed6 ML |
13168 | bool ret = true; |
13169 | ||
13170 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
13171 | do { \ | |
13172 | if (!adjust) \ | |
13173 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
13174 | else \ | |
13175 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
13176 | } while (0) | |
13177 | ||
66e985c0 DV |
13178 | #define PIPE_CONF_CHECK_X(name) \ |
13179 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 13180 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
13181 | "(expected 0x%08x, found 0x%08x)\n", \ |
13182 | current_config->name, \ | |
13183 | pipe_config->name); \ | |
cfb23ed6 | 13184 | ret = false; \ |
66e985c0 DV |
13185 | } |
13186 | ||
08a24034 DV |
13187 | #define PIPE_CONF_CHECK_I(name) \ |
13188 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 13189 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
13190 | "(expected %i, found %i)\n", \ |
13191 | current_config->name, \ | |
13192 | pipe_config->name); \ | |
cfb23ed6 ML |
13193 | ret = false; \ |
13194 | } | |
13195 | ||
8106ddbd ACO |
13196 | #define PIPE_CONF_CHECK_P(name) \ |
13197 | if (current_config->name != pipe_config->name) { \ | |
13198 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13199 | "(expected %p, found %p)\n", \ | |
13200 | current_config->name, \ | |
13201 | pipe_config->name); \ | |
13202 | ret = false; \ | |
13203 | } | |
13204 | ||
cfb23ed6 ML |
13205 | #define PIPE_CONF_CHECK_M_N(name) \ |
13206 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13207 | &pipe_config->name,\ | |
13208 | adjust)) { \ | |
13209 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13210 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
13211 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13212 | current_config->name.tu, \ | |
13213 | current_config->name.gmch_m, \ | |
13214 | current_config->name.gmch_n, \ | |
13215 | current_config->name.link_m, \ | |
13216 | current_config->name.link_n, \ | |
13217 | pipe_config->name.tu, \ | |
13218 | pipe_config->name.gmch_m, \ | |
13219 | pipe_config->name.gmch_n, \ | |
13220 | pipe_config->name.link_m, \ | |
13221 | pipe_config->name.link_n); \ | |
13222 | ret = false; \ | |
13223 | } | |
13224 | ||
55c561a7 DV |
13225 | /* This is required for BDW+ where there is only one set of registers for |
13226 | * switching between high and low RR. | |
13227 | * This macro can be used whenever a comparison has to be made between one | |
13228 | * hw state and multiple sw state variables. | |
13229 | */ | |
cfb23ed6 ML |
13230 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
13231 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13232 | &pipe_config->name, adjust) && \ | |
13233 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
13234 | &pipe_config->name, adjust)) { \ | |
13235 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13236 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
13237 | "or tu %i gmch %i/%i link %i/%i, " \ | |
13238 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13239 | current_config->name.tu, \ | |
13240 | current_config->name.gmch_m, \ | |
13241 | current_config->name.gmch_n, \ | |
13242 | current_config->name.link_m, \ | |
13243 | current_config->name.link_n, \ | |
13244 | current_config->alt_name.tu, \ | |
13245 | current_config->alt_name.gmch_m, \ | |
13246 | current_config->alt_name.gmch_n, \ | |
13247 | current_config->alt_name.link_m, \ | |
13248 | current_config->alt_name.link_n, \ | |
13249 | pipe_config->name.tu, \ | |
13250 | pipe_config->name.gmch_m, \ | |
13251 | pipe_config->name.gmch_n, \ | |
13252 | pipe_config->name.link_m, \ | |
13253 | pipe_config->name.link_n); \ | |
13254 | ret = false; \ | |
88adfff1 DV |
13255 | } |
13256 | ||
1bd1bd80 DV |
13257 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
13258 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 13259 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
13260 | "(expected %i, found %i)\n", \ |
13261 | current_config->name & (mask), \ | |
13262 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 13263 | ret = false; \ |
1bd1bd80 DV |
13264 | } |
13265 | ||
5e550656 VS |
13266 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
13267 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 13268 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
13269 | "(expected %i, found %i)\n", \ |
13270 | current_config->name, \ | |
13271 | pipe_config->name); \ | |
cfb23ed6 | 13272 | ret = false; \ |
5e550656 VS |
13273 | } |
13274 | ||
bb760063 DV |
13275 | #define PIPE_CONF_QUIRK(quirk) \ |
13276 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
13277 | ||
eccb140b DV |
13278 | PIPE_CONF_CHECK_I(cpu_transcoder); |
13279 | ||
08a24034 DV |
13280 | PIPE_CONF_CHECK_I(has_pch_encoder); |
13281 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 13282 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 13283 | |
90a6b7b0 | 13284 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 13285 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 13286 | |
6315b5d3 | 13287 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
13288 | PIPE_CONF_CHECK_M_N(dp_m_n); |
13289 | ||
cfb23ed6 ML |
13290 | if (current_config->has_drrs) |
13291 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
13292 | } else | |
13293 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 13294 | |
253c84c8 | 13295 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 13296 | |
2d112de7 ACO |
13297 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
13298 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
13299 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
13300 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
13301 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
13302 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 13303 | |
2d112de7 ACO |
13304 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
13305 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
13306 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
13307 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
13308 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
13309 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 13310 | |
c93f54cf | 13311 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 13312 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 13313 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 13314 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 13315 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 13316 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 13317 | |
9ed109a7 DV |
13318 | PIPE_CONF_CHECK_I(has_audio); |
13319 | ||
2d112de7 | 13320 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
13321 | DRM_MODE_FLAG_INTERLACE); |
13322 | ||
bb760063 | 13323 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 13324 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13325 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 13326 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13327 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 13328 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13329 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 13330 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
13331 | DRM_MODE_FLAG_NVSYNC); |
13332 | } | |
045ac3b5 | 13333 | |
333b8ca8 | 13334 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 13335 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 13336 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 13337 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 13338 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 13339 | |
bfd16b2a ML |
13340 | if (!adjust) { |
13341 | PIPE_CONF_CHECK_I(pipe_src_w); | |
13342 | PIPE_CONF_CHECK_I(pipe_src_h); | |
13343 | ||
13344 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
13345 | if (current_config->pch_pfit.enabled) { | |
13346 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
13347 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
13348 | } | |
2fa2fe9a | 13349 | |
7aefe2b5 ML |
13350 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
13351 | } | |
a1b2278e | 13352 | |
e59150dc | 13353 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 13354 | if (IS_HASWELL(dev_priv)) |
e59150dc | 13355 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 13356 | |
282740f7 VS |
13357 | PIPE_CONF_CHECK_I(double_wide); |
13358 | ||
8106ddbd | 13359 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 13360 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 13361 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
13362 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
13363 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 13364 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 13365 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
13366 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
13367 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
13368 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 13369 | |
47eacbab VS |
13370 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
13371 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
13372 | ||
9beb5fea | 13373 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
13374 | PIPE_CONF_CHECK_I(pipe_bpp); |
13375 | ||
2d112de7 | 13376 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 13377 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 13378 | |
66e985c0 | 13379 | #undef PIPE_CONF_CHECK_X |
08a24034 | 13380 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 13381 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 13382 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 13383 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 13384 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 13385 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 13386 | |
cfb23ed6 | 13387 | return ret; |
0e8ffe1b DV |
13388 | } |
13389 | ||
e3b247da VS |
13390 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
13391 | const struct intel_crtc_state *pipe_config) | |
13392 | { | |
13393 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 13394 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
13395 | &pipe_config->fdi_m_n); |
13396 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
13397 | ||
13398 | /* | |
13399 | * FDI already provided one idea for the dotclock. | |
13400 | * Yell if the encoder disagrees. | |
13401 | */ | |
13402 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
13403 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
13404 | fdi_dotclock, dotclock); | |
13405 | } | |
13406 | } | |
13407 | ||
c0ead703 ML |
13408 | static void verify_wm_state(struct drm_crtc *crtc, |
13409 | struct drm_crtc_state *new_state) | |
08db6652 | 13410 | { |
6315b5d3 | 13411 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 13412 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 13413 | struct skl_pipe_wm hw_wm, *sw_wm; |
13414 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
13415 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
13416 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13417 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 13418 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 13419 | |
6315b5d3 | 13420 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
13421 | return; |
13422 | ||
3de8a14c | 13423 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 13424 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 13425 | |
08db6652 DL |
13426 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
13427 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
13428 | ||
e7c84544 | 13429 | /* planes */ |
8b364b41 | 13430 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 13431 | hw_plane_wm = &hw_wm.planes[plane]; |
13432 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 13433 | |
3de8a14c | 13434 | /* Watermarks */ |
13435 | for (level = 0; level <= max_level; level++) { | |
13436 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
13437 | &sw_plane_wm->wm[level])) | |
13438 | continue; | |
13439 | ||
13440 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13441 | pipe_name(pipe), plane + 1, level, | |
13442 | sw_plane_wm->wm[level].plane_en, | |
13443 | sw_plane_wm->wm[level].plane_res_b, | |
13444 | sw_plane_wm->wm[level].plane_res_l, | |
13445 | hw_plane_wm->wm[level].plane_en, | |
13446 | hw_plane_wm->wm[level].plane_res_b, | |
13447 | hw_plane_wm->wm[level].plane_res_l); | |
13448 | } | |
08db6652 | 13449 | |
3de8a14c | 13450 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
13451 | &sw_plane_wm->trans_wm)) { | |
13452 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13453 | pipe_name(pipe), plane + 1, | |
13454 | sw_plane_wm->trans_wm.plane_en, | |
13455 | sw_plane_wm->trans_wm.plane_res_b, | |
13456 | sw_plane_wm->trans_wm.plane_res_l, | |
13457 | hw_plane_wm->trans_wm.plane_en, | |
13458 | hw_plane_wm->trans_wm.plane_res_b, | |
13459 | hw_plane_wm->trans_wm.plane_res_l); | |
13460 | } | |
13461 | ||
13462 | /* DDB */ | |
13463 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
13464 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
13465 | ||
13466 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 13467 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 13468 | pipe_name(pipe), plane + 1, |
13469 | sw_ddb_entry->start, sw_ddb_entry->end, | |
13470 | hw_ddb_entry->start, hw_ddb_entry->end); | |
13471 | } | |
e7c84544 | 13472 | } |
08db6652 | 13473 | |
27082493 L |
13474 | /* |
13475 | * cursor | |
13476 | * If the cursor plane isn't active, we may not have updated it's ddb | |
13477 | * allocation. In that case since the ddb allocation will be updated | |
13478 | * once the plane becomes visible, we can skip this check | |
13479 | */ | |
13480 | if (intel_crtc->cursor_addr) { | |
3de8a14c | 13481 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
13482 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
13483 | ||
13484 | /* Watermarks */ | |
13485 | for (level = 0; level <= max_level; level++) { | |
13486 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
13487 | &sw_plane_wm->wm[level])) | |
13488 | continue; | |
13489 | ||
13490 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13491 | pipe_name(pipe), level, | |
13492 | sw_plane_wm->wm[level].plane_en, | |
13493 | sw_plane_wm->wm[level].plane_res_b, | |
13494 | sw_plane_wm->wm[level].plane_res_l, | |
13495 | hw_plane_wm->wm[level].plane_en, | |
13496 | hw_plane_wm->wm[level].plane_res_b, | |
13497 | hw_plane_wm->wm[level].plane_res_l); | |
13498 | } | |
13499 | ||
13500 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
13501 | &sw_plane_wm->trans_wm)) { | |
13502 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13503 | pipe_name(pipe), | |
13504 | sw_plane_wm->trans_wm.plane_en, | |
13505 | sw_plane_wm->trans_wm.plane_res_b, | |
13506 | sw_plane_wm->trans_wm.plane_res_l, | |
13507 | hw_plane_wm->trans_wm.plane_en, | |
13508 | hw_plane_wm->trans_wm.plane_res_b, | |
13509 | hw_plane_wm->trans_wm.plane_res_l); | |
13510 | } | |
13511 | ||
13512 | /* DDB */ | |
13513 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
13514 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 13515 | |
3de8a14c | 13516 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 13517 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 13518 | pipe_name(pipe), |
3de8a14c | 13519 | sw_ddb_entry->start, sw_ddb_entry->end, |
13520 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 13521 | } |
08db6652 DL |
13522 | } |
13523 | } | |
13524 | ||
91d1b4bd | 13525 | static void |
677100ce ML |
13526 | verify_connector_state(struct drm_device *dev, |
13527 | struct drm_atomic_state *state, | |
13528 | struct drm_crtc *crtc) | |
8af6cf88 | 13529 | { |
35dd3c64 | 13530 | struct drm_connector *connector; |
677100ce ML |
13531 | struct drm_connector_state *old_conn_state; |
13532 | int i; | |
8af6cf88 | 13533 | |
677100ce | 13534 | for_each_connector_in_state(state, connector, old_conn_state, i) { |
35dd3c64 ML |
13535 | struct drm_encoder *encoder = connector->encoder; |
13536 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 13537 | |
e7c84544 ML |
13538 | if (state->crtc != crtc) |
13539 | continue; | |
13540 | ||
5a21b665 | 13541 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 13542 | |
ad3c558f | 13543 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 13544 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 13545 | } |
91d1b4bd DV |
13546 | } |
13547 | ||
13548 | static void | |
c0ead703 | 13549 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
13550 | { |
13551 | struct intel_encoder *encoder; | |
13552 | struct intel_connector *connector; | |
8af6cf88 | 13553 | |
b2784e15 | 13554 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13555 | bool enabled = false; |
4d20cd86 | 13556 | enum pipe pipe; |
8af6cf88 DV |
13557 | |
13558 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13559 | encoder->base.base.id, | |
8e329a03 | 13560 | encoder->base.name); |
8af6cf88 | 13561 | |
3a3371ff | 13562 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13563 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13564 | continue; |
13565 | enabled = true; | |
ad3c558f ML |
13566 | |
13567 | I915_STATE_WARN(connector->base.state->crtc != | |
13568 | encoder->base.crtc, | |
13569 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13570 | } |
0e32b39c | 13571 | |
e2c719b7 | 13572 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13573 | "encoder's enabled state mismatch " |
13574 | "(expected %i, found %i)\n", | |
13575 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13576 | |
13577 | if (!encoder->base.crtc) { | |
4d20cd86 | 13578 | bool active; |
7c60d198 | 13579 | |
4d20cd86 ML |
13580 | active = encoder->get_hw_state(encoder, &pipe); |
13581 | I915_STATE_WARN(active, | |
13582 | "encoder detached but still enabled on pipe %c.\n", | |
13583 | pipe_name(pipe)); | |
7c60d198 | 13584 | } |
8af6cf88 | 13585 | } |
91d1b4bd DV |
13586 | } |
13587 | ||
13588 | static void | |
c0ead703 ML |
13589 | verify_crtc_state(struct drm_crtc *crtc, |
13590 | struct drm_crtc_state *old_crtc_state, | |
13591 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 13592 | { |
e7c84544 | 13593 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13594 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 13595 | struct intel_encoder *encoder; |
e7c84544 ML |
13596 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13597 | struct intel_crtc_state *pipe_config, *sw_config; | |
13598 | struct drm_atomic_state *old_state; | |
13599 | bool active; | |
045ac3b5 | 13600 | |
e7c84544 | 13601 | old_state = old_crtc_state->state; |
ec2dc6a0 | 13602 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
13603 | pipe_config = to_intel_crtc_state(old_crtc_state); |
13604 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13605 | pipe_config->base.crtc = crtc; | |
13606 | pipe_config->base.state = old_state; | |
8af6cf88 | 13607 | |
78108b7c | 13608 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 13609 | |
e7c84544 | 13610 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 13611 | |
e7c84544 ML |
13612 | /* hw state is inconsistent with the pipe quirk */ |
13613 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
13614 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13615 | active = new_crtc_state->active; | |
6c49f241 | 13616 | |
e7c84544 ML |
13617 | I915_STATE_WARN(new_crtc_state->active != active, |
13618 | "crtc active state doesn't match with hw state " | |
13619 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 13620 | |
e7c84544 ML |
13621 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
13622 | "transitional active state does not match atomic hw state " | |
13623 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13624 | |
e7c84544 ML |
13625 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13626 | enum pipe pipe; | |
4d20cd86 | 13627 | |
e7c84544 ML |
13628 | active = encoder->get_hw_state(encoder, &pipe); |
13629 | I915_STATE_WARN(active != new_crtc_state->active, | |
13630 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13631 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13632 | |
e7c84544 ML |
13633 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13634 | "Encoder connected to wrong pipe %c\n", | |
13635 | pipe_name(pipe)); | |
4d20cd86 | 13636 | |
253c84c8 VS |
13637 | if (active) { |
13638 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 13639 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 13640 | } |
e7c84544 | 13641 | } |
53d9f4e9 | 13642 | |
e7c84544 ML |
13643 | if (!new_crtc_state->active) |
13644 | return; | |
cfb23ed6 | 13645 | |
e7c84544 | 13646 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13647 | |
e7c84544 | 13648 | sw_config = to_intel_crtc_state(crtc->state); |
6315b5d3 | 13649 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
13650 | pipe_config, false)) { |
13651 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13652 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13653 | "[hw state]"); | |
13654 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13655 | "[sw state]"); | |
8af6cf88 DV |
13656 | } |
13657 | } | |
13658 | ||
91d1b4bd | 13659 | static void |
c0ead703 ML |
13660 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13661 | struct intel_shared_dpll *pll, | |
13662 | struct drm_crtc *crtc, | |
13663 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13664 | { |
91d1b4bd | 13665 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13666 | unsigned crtc_mask; |
13667 | bool active; | |
5358901f | 13668 | |
e7c84544 | 13669 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13670 | |
e7c84544 | 13671 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13672 | |
e7c84544 | 13673 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13674 | |
e7c84544 ML |
13675 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13676 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13677 | "pll in active use but not on in sw tracking\n"); | |
13678 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13679 | "pll is on but not used by any active crtc\n"); | |
13680 | I915_STATE_WARN(pll->on != active, | |
13681 | "pll on state mismatch (expected %i, found %i)\n", | |
13682 | pll->on, active); | |
13683 | } | |
5358901f | 13684 | |
e7c84544 | 13685 | if (!crtc) { |
2dd66ebd | 13686 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13687 | "more active pll users than references: %x vs %x\n", |
13688 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13689 | |
e7c84544 ML |
13690 | return; |
13691 | } | |
13692 | ||
13693 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13694 | ||
13695 | if (new_state->active) | |
13696 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13697 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13698 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13699 | else | |
13700 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13701 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13702 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13703 | |
e7c84544 ML |
13704 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13705 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13706 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13707 | |
e7c84544 ML |
13708 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13709 | &dpll_hw_state, | |
13710 | sizeof(dpll_hw_state)), | |
13711 | "pll hw state mismatch\n"); | |
13712 | } | |
13713 | ||
13714 | static void | |
c0ead703 ML |
13715 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13716 | struct drm_crtc_state *old_crtc_state, | |
13717 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 13718 | { |
fac5e23e | 13719 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13720 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
13721 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13722 | ||
13723 | if (new_state->shared_dpll) | |
c0ead703 | 13724 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13725 | |
13726 | if (old_state->shared_dpll && | |
13727 | old_state->shared_dpll != new_state->shared_dpll) { | |
13728 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13729 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13730 | ||
13731 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13732 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13733 | pipe_name(drm_crtc_index(crtc))); | |
13734 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13735 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13736 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13737 | } |
8af6cf88 DV |
13738 | } |
13739 | ||
e7c84544 | 13740 | static void |
c0ead703 | 13741 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
13742 | struct drm_atomic_state *state, |
13743 | struct drm_crtc_state *old_state, | |
13744 | struct drm_crtc_state *new_state) | |
e7c84544 | 13745 | { |
5a21b665 DV |
13746 | if (!needs_modeset(new_state) && |
13747 | !to_intel_crtc_state(new_state)->update_pipe) | |
13748 | return; | |
13749 | ||
c0ead703 | 13750 | verify_wm_state(crtc, new_state); |
677100ce | 13751 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
13752 | verify_crtc_state(crtc, old_state, new_state); |
13753 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13754 | } |
13755 | ||
13756 | static void | |
c0ead703 | 13757 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 13758 | { |
fac5e23e | 13759 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13760 | int i; |
13761 | ||
13762 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13763 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13764 | } |
13765 | ||
13766 | static void | |
677100ce ML |
13767 | intel_modeset_verify_disabled(struct drm_device *dev, |
13768 | struct drm_atomic_state *state) | |
e7c84544 | 13769 | { |
c0ead703 | 13770 | verify_encoder_state(dev); |
677100ce | 13771 | verify_connector_state(dev, state, NULL); |
c0ead703 | 13772 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
13773 | } |
13774 | ||
80715b2f VS |
13775 | static void update_scanline_offset(struct intel_crtc *crtc) |
13776 | { | |
4f8036a2 | 13777 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
13778 | |
13779 | /* | |
13780 | * The scanline counter increments at the leading edge of hsync. | |
13781 | * | |
13782 | * On most platforms it starts counting from vtotal-1 on the | |
13783 | * first active line. That means the scanline counter value is | |
13784 | * always one less than what we would expect. Ie. just after | |
13785 | * start of vblank, which also occurs at start of hsync (on the | |
13786 | * last active line), the scanline counter will read vblank_start-1. | |
13787 | * | |
13788 | * On gen2 the scanline counter starts counting from 1 instead | |
13789 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13790 | * to keep the value positive), instead of adding one. | |
13791 | * | |
13792 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13793 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13794 | * there's an extra 1 line difference. So we need to add two instead of | |
13795 | * one to the value. | |
13796 | */ | |
4f8036a2 | 13797 | if (IS_GEN2(dev_priv)) { |
124abe07 | 13798 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13799 | int vtotal; |
13800 | ||
124abe07 VS |
13801 | vtotal = adjusted_mode->crtc_vtotal; |
13802 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13803 | vtotal /= 2; |
13804 | ||
13805 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 13806 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 13807 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13808 | crtc->scanline_offset = 2; |
13809 | } else | |
13810 | crtc->scanline_offset = 1; | |
13811 | } | |
13812 | ||
ad421372 | 13813 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13814 | { |
225da59b | 13815 | struct drm_device *dev = state->dev; |
ed6739ef | 13816 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13817 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13818 | struct drm_crtc *crtc; |
13819 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13820 | int i; |
ed6739ef ACO |
13821 | |
13822 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13823 | return; |
ed6739ef | 13824 | |
0a9ab303 | 13825 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13826 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13827 | struct intel_shared_dpll *old_dpll = |
13828 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13829 | |
fb1a38a9 | 13830 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13831 | continue; |
13832 | ||
8106ddbd | 13833 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13834 | |
8106ddbd | 13835 | if (!old_dpll) |
fb1a38a9 | 13836 | continue; |
0a9ab303 | 13837 | |
ad421372 ML |
13838 | if (!shared_dpll) |
13839 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13840 | |
8106ddbd | 13841 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13842 | } |
ed6739ef ACO |
13843 | } |
13844 | ||
99d736a2 ML |
13845 | /* |
13846 | * This implements the workaround described in the "notes" section of the mode | |
13847 | * set sequence documentation. When going from no pipes or single pipe to | |
13848 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13849 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13850 | */ | |
13851 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13852 | { | |
13853 | struct drm_crtc_state *crtc_state; | |
13854 | struct intel_crtc *intel_crtc; | |
13855 | struct drm_crtc *crtc; | |
13856 | struct intel_crtc_state *first_crtc_state = NULL; | |
13857 | struct intel_crtc_state *other_crtc_state = NULL; | |
13858 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13859 | int i; | |
13860 | ||
13861 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13862 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13863 | intel_crtc = to_intel_crtc(crtc); | |
13864 | ||
13865 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13866 | continue; | |
13867 | ||
13868 | if (first_crtc_state) { | |
13869 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13870 | break; | |
13871 | } else { | |
13872 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13873 | first_pipe = intel_crtc->pipe; | |
13874 | } | |
13875 | } | |
13876 | ||
13877 | /* No workaround needed? */ | |
13878 | if (!first_crtc_state) | |
13879 | return 0; | |
13880 | ||
13881 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13882 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13883 | struct intel_crtc_state *pipe_config; | |
13884 | ||
13885 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13886 | if (IS_ERR(pipe_config)) | |
13887 | return PTR_ERR(pipe_config); | |
13888 | ||
13889 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13890 | ||
13891 | if (!pipe_config->base.active || | |
13892 | needs_modeset(&pipe_config->base)) | |
13893 | continue; | |
13894 | ||
13895 | /* 2 or more enabled crtcs means no need for w/a */ | |
13896 | if (enabled_pipe != INVALID_PIPE) | |
13897 | return 0; | |
13898 | ||
13899 | enabled_pipe = intel_crtc->pipe; | |
13900 | } | |
13901 | ||
13902 | if (enabled_pipe != INVALID_PIPE) | |
13903 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13904 | else if (other_crtc_state) | |
13905 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13906 | ||
13907 | return 0; | |
13908 | } | |
13909 | ||
8d96561a VS |
13910 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
13911 | { | |
13912 | struct drm_crtc *crtc; | |
13913 | ||
13914 | /* Add all pipes to the state */ | |
13915 | for_each_crtc(state->dev, crtc) { | |
13916 | struct drm_crtc_state *crtc_state; | |
13917 | ||
13918 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13919 | if (IS_ERR(crtc_state)) | |
13920 | return PTR_ERR(crtc_state); | |
13921 | } | |
13922 | ||
13923 | return 0; | |
13924 | } | |
13925 | ||
27c329ed ML |
13926 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13927 | { | |
13928 | struct drm_crtc *crtc; | |
27c329ed | 13929 | |
8d96561a VS |
13930 | /* |
13931 | * Add all pipes to the state, and force | |
13932 | * a modeset on all the active ones. | |
13933 | */ | |
27c329ed | 13934 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
13935 | struct drm_crtc_state *crtc_state; |
13936 | int ret; | |
13937 | ||
27c329ed ML |
13938 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
13939 | if (IS_ERR(crtc_state)) | |
13940 | return PTR_ERR(crtc_state); | |
13941 | ||
13942 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13943 | continue; | |
13944 | ||
13945 | crtc_state->mode_changed = true; | |
13946 | ||
13947 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13948 | if (ret) | |
9780aad5 | 13949 | return ret; |
27c329ed ML |
13950 | |
13951 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13952 | if (ret) | |
9780aad5 | 13953 | return ret; |
27c329ed ML |
13954 | } |
13955 | ||
9780aad5 | 13956 | return 0; |
27c329ed ML |
13957 | } |
13958 | ||
c347a676 | 13959 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13960 | { |
565602d7 | 13961 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13962 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
13963 | struct drm_crtc *crtc; |
13964 | struct drm_crtc_state *crtc_state; | |
13965 | int ret = 0, i; | |
054518dd | 13966 | |
b359283a ML |
13967 | if (!check_digital_port_conflicts(state)) { |
13968 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13969 | return -EINVAL; | |
13970 | } | |
13971 | ||
565602d7 ML |
13972 | intel_state->modeset = true; |
13973 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13974 | ||
13975 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13976 | if (crtc_state->active) | |
13977 | intel_state->active_crtcs |= 1 << i; | |
13978 | else | |
13979 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13980 | |
13981 | if (crtc_state->active != crtc->state->active) | |
13982 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13983 | } |
13984 | ||
054518dd ACO |
13985 | /* |
13986 | * See if the config requires any additional preparation, e.g. | |
13987 | * to adjust global state with pipes off. We need to do this | |
13988 | * here so we can get the modeset_pipe updated config for the new | |
13989 | * mode set on this crtc. For other crtcs we need to use the | |
13990 | * adjusted_mode bits in the crtc directly. | |
13991 | */ | |
27c329ed | 13992 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 13993 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 13994 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
13995 | if (!intel_state->cdclk_pll_vco) |
13996 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 13997 | |
27c329ed | 13998 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
13999 | if (ret < 0) |
14000 | return ret; | |
27c329ed | 14001 | |
8d96561a VS |
14002 | /* |
14003 | * Writes to dev_priv->atomic_cdclk_freq must protected by | |
14004 | * holding all the crtc locks, even if we don't end up | |
14005 | * touching the hardware | |
14006 | */ | |
14007 | if (intel_state->cdclk != dev_priv->atomic_cdclk_freq) { | |
14008 | ret = intel_lock_all_pipes(state); | |
14009 | if (ret < 0) | |
14010 | return ret; | |
14011 | } | |
14012 | ||
14013 | /* All pipes must be switched off while we change the cdclk. */ | |
c89e39f3 | 14014 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
8d96561a | 14015 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) { |
27c329ed | 14016 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
14017 | if (ret < 0) |
14018 | return ret; | |
14019 | } | |
e8788cbc ML |
14020 | |
14021 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
14022 | intel_state->cdclk, intel_state->dev_cdclk); | |
e0ca7a6b | 14023 | } else { |
1a617b77 | 14024 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
e0ca7a6b | 14025 | } |
054518dd | 14026 | |
ad421372 | 14027 | intel_modeset_clear_plls(state); |
054518dd | 14028 | |
565602d7 | 14029 | if (IS_HASWELL(dev_priv)) |
ad421372 | 14030 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 14031 | |
ad421372 | 14032 | return 0; |
c347a676 ACO |
14033 | } |
14034 | ||
aa363136 MR |
14035 | /* |
14036 | * Handle calculation of various watermark data at the end of the atomic check | |
14037 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
14038 | * handlers to ensure that all derived state has been updated. | |
14039 | */ | |
55994c2c | 14040 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
14041 | { |
14042 | struct drm_device *dev = state->dev; | |
98d39494 | 14043 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
14044 | |
14045 | /* Is there platform-specific watermark information to calculate? */ | |
14046 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
14047 | return dev_priv->display.compute_global_watermarks(state); |
14048 | ||
14049 | return 0; | |
aa363136 MR |
14050 | } |
14051 | ||
74c090b1 ML |
14052 | /** |
14053 | * intel_atomic_check - validate state object | |
14054 | * @dev: drm device | |
14055 | * @state: state to validate | |
14056 | */ | |
14057 | static int intel_atomic_check(struct drm_device *dev, | |
14058 | struct drm_atomic_state *state) | |
c347a676 | 14059 | { |
dd8b3bdb | 14060 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 14061 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
14062 | struct drm_crtc *crtc; |
14063 | struct drm_crtc_state *crtc_state; | |
14064 | int ret, i; | |
61333b60 | 14065 | bool any_ms = false; |
c347a676 | 14066 | |
74c090b1 | 14067 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
14068 | if (ret) |
14069 | return ret; | |
14070 | ||
c347a676 | 14071 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
14072 | struct intel_crtc_state *pipe_config = |
14073 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
14074 | |
14075 | /* Catch I915_MODE_FLAG_INHERITED */ | |
14076 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
14077 | crtc_state->mode_changed = true; | |
cfb23ed6 | 14078 | |
af4a879e | 14079 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
14080 | continue; |
14081 | ||
af4a879e DV |
14082 | if (!crtc_state->enable) { |
14083 | any_ms = true; | |
cfb23ed6 | 14084 | continue; |
af4a879e | 14085 | } |
cfb23ed6 | 14086 | |
26495481 DV |
14087 | /* FIXME: For only active_changed we shouldn't need to do any |
14088 | * state recomputation at all. */ | |
14089 | ||
1ed51de9 DV |
14090 | ret = drm_atomic_add_affected_connectors(state, crtc); |
14091 | if (ret) | |
14092 | return ret; | |
b359283a | 14093 | |
cfb23ed6 | 14094 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
14095 | if (ret) { |
14096 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
14097 | pipe_config, "[failed]"); | |
c347a676 | 14098 | return ret; |
25aa1c39 | 14099 | } |
c347a676 | 14100 | |
73831236 | 14101 | if (i915.fastboot && |
6315b5d3 | 14102 | intel_pipe_config_compare(dev_priv, |
cfb23ed6 | 14103 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 14104 | pipe_config, true)) { |
26495481 | 14105 | crtc_state->mode_changed = false; |
bfd16b2a | 14106 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
14107 | } |
14108 | ||
af4a879e | 14109 | if (needs_modeset(crtc_state)) |
26495481 | 14110 | any_ms = true; |
cfb23ed6 | 14111 | |
af4a879e DV |
14112 | ret = drm_atomic_add_affected_planes(state, crtc); |
14113 | if (ret) | |
14114 | return ret; | |
61333b60 | 14115 | |
26495481 DV |
14116 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
14117 | needs_modeset(crtc_state) ? | |
14118 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
14119 | } |
14120 | ||
61333b60 ML |
14121 | if (any_ms) { |
14122 | ret = intel_modeset_checks(state); | |
14123 | ||
14124 | if (ret) | |
14125 | return ret; | |
e0ca7a6b VS |
14126 | } else { |
14127 | intel_state->cdclk = dev_priv->atomic_cdclk_freq; | |
14128 | } | |
76305b1a | 14129 | |
dd8b3bdb | 14130 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
14131 | if (ret) |
14132 | return ret; | |
14133 | ||
f51be2e0 | 14134 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 14135 | return calc_watermark_data(state); |
054518dd ACO |
14136 | } |
14137 | ||
5008e874 | 14138 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 14139 | struct drm_atomic_state *state) |
5008e874 | 14140 | { |
fac5e23e | 14141 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 ML |
14142 | struct drm_crtc_state *crtc_state; |
14143 | struct drm_crtc *crtc; | |
14144 | int i, ret; | |
14145 | ||
5a21b665 DV |
14146 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
14147 | if (state->legacy_cursor_update) | |
a6747b73 ML |
14148 | continue; |
14149 | ||
5a21b665 DV |
14150 | ret = intel_crtc_wait_for_pending_flips(crtc); |
14151 | if (ret) | |
14152 | return ret; | |
5008e874 | 14153 | |
5a21b665 DV |
14154 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
14155 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
14156 | } |
14157 | ||
f935675f ML |
14158 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
14159 | if (ret) | |
14160 | return ret; | |
14161 | ||
5008e874 | 14162 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 14163 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 14164 | |
5008e874 ML |
14165 | return ret; |
14166 | } | |
14167 | ||
a2991414 ML |
14168 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
14169 | { | |
14170 | struct drm_device *dev = crtc->base.dev; | |
14171 | ||
14172 | if (!dev->max_vblank_count) | |
14173 | return drm_accurate_vblank_count(&crtc->base); | |
14174 | ||
14175 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
14176 | } | |
14177 | ||
5a21b665 DV |
14178 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
14179 | struct drm_i915_private *dev_priv, | |
14180 | unsigned crtc_mask) | |
e8861675 | 14181 | { |
5a21b665 DV |
14182 | unsigned last_vblank_count[I915_MAX_PIPES]; |
14183 | enum pipe pipe; | |
14184 | int ret; | |
e8861675 | 14185 | |
5a21b665 DV |
14186 | if (!crtc_mask) |
14187 | return; | |
e8861675 | 14188 | |
5a21b665 | 14189 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
14190 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
14191 | pipe); | |
e8861675 | 14192 | |
5a21b665 | 14193 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
14194 | continue; |
14195 | ||
e2af48c6 | 14196 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
14197 | if (WARN_ON(ret != 0)) { |
14198 | crtc_mask &= ~(1 << pipe); | |
14199 | continue; | |
e8861675 ML |
14200 | } |
14201 | ||
e2af48c6 | 14202 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
14203 | } |
14204 | ||
5a21b665 | 14205 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
14206 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
14207 | pipe); | |
5a21b665 | 14208 | long lret; |
e8861675 | 14209 | |
5a21b665 DV |
14210 | if (!((1 << pipe) & crtc_mask)) |
14211 | continue; | |
d55dbd06 | 14212 | |
5a21b665 DV |
14213 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
14214 | last_vblank_count[pipe] != | |
e2af48c6 | 14215 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 14216 | msecs_to_jiffies(50)); |
d55dbd06 | 14217 | |
5a21b665 | 14218 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 14219 | |
e2af48c6 | 14220 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
14221 | } |
14222 | } | |
14223 | ||
5a21b665 | 14224 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 14225 | { |
5a21b665 DV |
14226 | /* fb updated, need to unpin old fb */ |
14227 | if (crtc_state->fb_changed) | |
14228 | return true; | |
a6747b73 | 14229 | |
5a21b665 DV |
14230 | /* wm changes, need vblank before final wm's */ |
14231 | if (crtc_state->update_wm_post) | |
14232 | return true; | |
a6747b73 | 14233 | |
5a21b665 DV |
14234 | /* |
14235 | * cxsr is re-enabled after vblank. | |
14236 | * This is already handled by crtc_state->update_wm_post, | |
14237 | * but added for clarity. | |
14238 | */ | |
14239 | if (crtc_state->disable_cxsr) | |
14240 | return true; | |
a6747b73 | 14241 | |
5a21b665 | 14242 | return false; |
e8861675 ML |
14243 | } |
14244 | ||
896e5bb0 L |
14245 | static void intel_update_crtc(struct drm_crtc *crtc, |
14246 | struct drm_atomic_state *state, | |
14247 | struct drm_crtc_state *old_crtc_state, | |
14248 | unsigned int *crtc_vblank_mask) | |
14249 | { | |
14250 | struct drm_device *dev = crtc->dev; | |
14251 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14252 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14253 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state); | |
14254 | bool modeset = needs_modeset(crtc->state); | |
14255 | ||
14256 | if (modeset) { | |
14257 | update_scanline_offset(intel_crtc); | |
14258 | dev_priv->display.crtc_enable(pipe_config, state); | |
14259 | } else { | |
14260 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); | |
14261 | } | |
14262 | ||
14263 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
14264 | intel_fbc_enable( | |
14265 | intel_crtc, pipe_config, | |
14266 | to_intel_plane_state(crtc->primary->state)); | |
14267 | } | |
14268 | ||
14269 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
14270 | ||
14271 | if (needs_vblank_wait(pipe_config)) | |
14272 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
14273 | } | |
14274 | ||
14275 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
14276 | unsigned int *crtc_vblank_mask) | |
14277 | { | |
14278 | struct drm_crtc *crtc; | |
14279 | struct drm_crtc_state *old_crtc_state; | |
14280 | int i; | |
14281 | ||
14282 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14283 | if (!crtc->state->active) | |
14284 | continue; | |
14285 | ||
14286 | intel_update_crtc(crtc, state, old_crtc_state, | |
14287 | crtc_vblank_mask); | |
14288 | } | |
14289 | } | |
14290 | ||
27082493 L |
14291 | static void skl_update_crtcs(struct drm_atomic_state *state, |
14292 | unsigned int *crtc_vblank_mask) | |
14293 | { | |
0f0f74bc | 14294 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
14295 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
14296 | struct drm_crtc *crtc; | |
ce0ba283 | 14297 | struct intel_crtc *intel_crtc; |
27082493 | 14298 | struct drm_crtc_state *old_crtc_state; |
ce0ba283 | 14299 | struct intel_crtc_state *cstate; |
27082493 L |
14300 | unsigned int updated = 0; |
14301 | bool progress; | |
14302 | enum pipe pipe; | |
5eff503b ML |
14303 | int i; |
14304 | ||
14305 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
14306 | ||
14307 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) | |
14308 | /* ignore allocations for crtc's that have been turned off. */ | |
14309 | if (crtc->state->active) | |
14310 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; | |
27082493 L |
14311 | |
14312 | /* | |
14313 | * Whenever the number of active pipes changes, we need to make sure we | |
14314 | * update the pipes in the right order so that their ddb allocations | |
14315 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
14316 | * cause pipe underruns and other bad stuff. | |
14317 | */ | |
14318 | do { | |
27082493 L |
14319 | progress = false; |
14320 | ||
14321 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14322 | bool vbl_wait = false; | |
14323 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
14324 | |
14325 | intel_crtc = to_intel_crtc(crtc); | |
14326 | cstate = to_intel_crtc_state(crtc->state); | |
14327 | pipe = intel_crtc->pipe; | |
27082493 | 14328 | |
5eff503b | 14329 | if (updated & cmask || !cstate->base.active) |
27082493 | 14330 | continue; |
5eff503b ML |
14331 | |
14332 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
14333 | continue; |
14334 | ||
14335 | updated |= cmask; | |
5eff503b | 14336 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
14337 | |
14338 | /* | |
14339 | * If this is an already active pipe, it's DDB changed, | |
14340 | * and this isn't the last pipe that needs updating | |
14341 | * then we need to wait for a vblank to pass for the | |
14342 | * new ddb allocation to take effect. | |
14343 | */ | |
ce0ba283 | 14344 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 14345 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
27082493 L |
14346 | !crtc->state->active_changed && |
14347 | intel_state->wm_results.dirty_pipes != updated) | |
14348 | vbl_wait = true; | |
14349 | ||
14350 | intel_update_crtc(crtc, state, old_crtc_state, | |
14351 | crtc_vblank_mask); | |
14352 | ||
14353 | if (vbl_wait) | |
0f0f74bc | 14354 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
14355 | |
14356 | progress = true; | |
14357 | } | |
14358 | } while (progress); | |
14359 | } | |
14360 | ||
94f05024 | 14361 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 14362 | { |
94f05024 | 14363 | struct drm_device *dev = state->dev; |
565602d7 | 14364 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 14365 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 14366 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 14367 | struct drm_crtc *crtc; |
5a21b665 | 14368 | struct intel_crtc_state *intel_cstate; |
5a21b665 DV |
14369 | bool hw_check = intel_state->modeset; |
14370 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
14371 | unsigned crtc_vblank_mask = 0; | |
e95433c7 | 14372 | int i; |
a6778b3c | 14373 | |
ea0000f0 DV |
14374 | drm_atomic_helper_wait_for_dependencies(state); |
14375 | ||
c3b32658 | 14376 | if (intel_state->modeset) |
5a21b665 | 14377 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 14378 | |
29ceb0e6 | 14379 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
14380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14381 | ||
5a21b665 DV |
14382 | if (needs_modeset(crtc->state) || |
14383 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
14384 | hw_check = true; | |
14385 | ||
14386 | put_domains[to_intel_crtc(crtc)->pipe] = | |
14387 | modeset_get_crtc_power_domains(crtc, | |
14388 | to_intel_crtc_state(crtc->state)); | |
14389 | } | |
14390 | ||
61333b60 ML |
14391 | if (!needs_modeset(crtc->state)) |
14392 | continue; | |
14393 | ||
29ceb0e6 | 14394 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 14395 | |
29ceb0e6 VS |
14396 | if (old_crtc_state->active) { |
14397 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 14398 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 14399 | intel_crtc->active = false; |
58f9c0bc | 14400 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 14401 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
14402 | |
14403 | /* | |
14404 | * Underruns don't always raise | |
14405 | * interrupts, so check manually. | |
14406 | */ | |
14407 | intel_check_cpu_fifo_underruns(dev_priv); | |
14408 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 14409 | |
e62929b3 ML |
14410 | if (!crtc->state->active) { |
14411 | /* | |
14412 | * Make sure we don't call initial_watermarks | |
14413 | * for ILK-style watermark updates. | |
14414 | */ | |
14415 | if (dev_priv->display.atomic_update_watermarks) | |
14416 | dev_priv->display.initial_watermarks(intel_state, | |
14417 | to_intel_crtc_state(crtc->state)); | |
14418 | else | |
14419 | intel_update_watermarks(intel_crtc); | |
14420 | } | |
a539205a | 14421 | } |
b8cecdf5 | 14422 | } |
7758a113 | 14423 | |
ea9d758d DV |
14424 | /* Only after disabling all output pipelines that will be changed can we |
14425 | * update the the output configuration. */ | |
4740b0f2 | 14426 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 14427 | |
565602d7 | 14428 | if (intel_state->modeset) { |
4740b0f2 | 14429 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
14430 | |
14431 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 14432 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 14433 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 14434 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 14435 | |
656d1b89 L |
14436 | /* |
14437 | * SKL workaround: bspec recommends we disable the SAGV when we | |
14438 | * have more then one pipe enabled | |
14439 | */ | |
56feca91 | 14440 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 14441 | intel_disable_sagv(dev_priv); |
656d1b89 | 14442 | |
677100ce | 14443 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 14444 | } |
47fab737 | 14445 | |
896e5bb0 | 14446 | /* Complete the events for pipes that have now been disabled */ |
29ceb0e6 | 14447 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a | 14448 | bool modeset = needs_modeset(crtc->state); |
80715b2f | 14449 | |
1f7528c4 DV |
14450 | /* Complete events for now disable pipes here. */ |
14451 | if (modeset && !crtc->state->active && crtc->state->event) { | |
14452 | spin_lock_irq(&dev->event_lock); | |
14453 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
14454 | spin_unlock_irq(&dev->event_lock); | |
14455 | ||
14456 | crtc->state->event = NULL; | |
14457 | } | |
177246a8 MR |
14458 | } |
14459 | ||
896e5bb0 L |
14460 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
14461 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
14462 | ||
94f05024 DV |
14463 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
14464 | * already, but still need the state for the delayed optimization. To | |
14465 | * fix this: | |
14466 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
14467 | * - schedule that vblank worker _before_ calling hw_done | |
14468 | * - at the start of commit_tail, cancel it _synchrously | |
14469 | * - switch over to the vblank wait helper in the core after that since | |
14470 | * we don't need out special handling any more. | |
14471 | */ | |
5a21b665 DV |
14472 | if (!state->legacy_cursor_update) |
14473 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
14474 | ||
14475 | /* | |
14476 | * Now that the vblank has passed, we can go ahead and program the | |
14477 | * optimal watermarks on platforms that need two-step watermark | |
14478 | * programming. | |
14479 | * | |
14480 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
14481 | */ | |
14482 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14483 | intel_cstate = to_intel_crtc_state(crtc->state); | |
14484 | ||
14485 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
14486 | dev_priv->display.optimize_watermarks(intel_state, |
14487 | intel_cstate); | |
5a21b665 DV |
14488 | } |
14489 | ||
14490 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14491 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
14492 | ||
14493 | if (put_domains[i]) | |
14494 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
14495 | ||
677100ce | 14496 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state); |
5a21b665 DV |
14497 | } |
14498 | ||
56feca91 | 14499 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 14500 | intel_enable_sagv(dev_priv); |
656d1b89 | 14501 | |
94f05024 DV |
14502 | drm_atomic_helper_commit_hw_done(state); |
14503 | ||
5a21b665 DV |
14504 | if (intel_state->modeset) |
14505 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
14506 | ||
14507 | mutex_lock(&dev->struct_mutex); | |
14508 | drm_atomic_helper_cleanup_planes(dev, state); | |
14509 | mutex_unlock(&dev->struct_mutex); | |
14510 | ||
ea0000f0 DV |
14511 | drm_atomic_helper_commit_cleanup_done(state); |
14512 | ||
0853695c | 14513 | drm_atomic_state_put(state); |
f30da187 | 14514 | |
75714940 MK |
14515 | /* As one of the primary mmio accessors, KMS has a high likelihood |
14516 | * of triggering bugs in unclaimed access. After we finish | |
14517 | * modesetting, see if an error has been flagged, and if so | |
14518 | * enable debugging for the next modeset - and hope we catch | |
14519 | * the culprit. | |
14520 | * | |
14521 | * XXX note that we assume display power is on at this point. | |
14522 | * This might hold true now but we need to add pm helper to check | |
14523 | * unclaimed only when the hardware is on, as atomic commits | |
14524 | * can happen also when the device is completely off. | |
14525 | */ | |
14526 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
14527 | } |
14528 | ||
14529 | static void intel_atomic_commit_work(struct work_struct *work) | |
14530 | { | |
c004a90b CW |
14531 | struct drm_atomic_state *state = |
14532 | container_of(work, struct drm_atomic_state, commit_work); | |
14533 | ||
94f05024 DV |
14534 | intel_atomic_commit_tail(state); |
14535 | } | |
14536 | ||
c004a90b CW |
14537 | static int __i915_sw_fence_call |
14538 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
14539 | enum i915_sw_fence_notify notify) | |
14540 | { | |
14541 | struct intel_atomic_state *state = | |
14542 | container_of(fence, struct intel_atomic_state, commit_ready); | |
14543 | ||
14544 | switch (notify) { | |
14545 | case FENCE_COMPLETE: | |
14546 | if (state->base.commit_work.func) | |
14547 | queue_work(system_unbound_wq, &state->base.commit_work); | |
14548 | break; | |
14549 | ||
14550 | case FENCE_FREE: | |
14551 | drm_atomic_state_put(&state->base); | |
14552 | break; | |
14553 | } | |
14554 | ||
14555 | return NOTIFY_DONE; | |
14556 | } | |
14557 | ||
6c9c1b38 DV |
14558 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
14559 | { | |
14560 | struct drm_plane_state *old_plane_state; | |
14561 | struct drm_plane *plane; | |
6c9c1b38 DV |
14562 | int i; |
14563 | ||
faf5bf0a CW |
14564 | for_each_plane_in_state(state, plane, old_plane_state, i) |
14565 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
14566 | intel_fb_obj(plane->state->fb), | |
14567 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
14568 | } |
14569 | ||
94f05024 DV |
14570 | /** |
14571 | * intel_atomic_commit - commit validated state object | |
14572 | * @dev: DRM device | |
14573 | * @state: the top-level driver state object | |
14574 | * @nonblock: nonblocking commit | |
14575 | * | |
14576 | * This function commits a top-level state object that has been validated | |
14577 | * with drm_atomic_helper_check(). | |
14578 | * | |
94f05024 DV |
14579 | * RETURNS |
14580 | * Zero for success or -errno. | |
14581 | */ | |
14582 | static int intel_atomic_commit(struct drm_device *dev, | |
14583 | struct drm_atomic_state *state, | |
14584 | bool nonblock) | |
14585 | { | |
14586 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 14587 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
14588 | int ret = 0; |
14589 | ||
94f05024 DV |
14590 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
14591 | if (ret) | |
14592 | return ret; | |
14593 | ||
c004a90b CW |
14594 | drm_atomic_state_get(state); |
14595 | i915_sw_fence_init(&intel_state->commit_ready, | |
14596 | intel_atomic_commit_ready); | |
94f05024 | 14597 | |
d07f0e59 | 14598 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
14599 | if (ret) { |
14600 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 14601 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
14602 | return ret; |
14603 | } | |
14604 | ||
14605 | drm_atomic_helper_swap_state(state, true); | |
14606 | dev_priv->wm.distrust_bios_wm = false; | |
94f05024 | 14607 | intel_shared_dpll_commit(state); |
6c9c1b38 | 14608 | intel_atomic_track_fbs(state); |
94f05024 | 14609 | |
c3b32658 ML |
14610 | if (intel_state->modeset) { |
14611 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
14612 | sizeof(intel_state->min_pixclk)); | |
14613 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
14614 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; | |
14615 | } | |
14616 | ||
0853695c | 14617 | drm_atomic_state_get(state); |
c004a90b CW |
14618 | INIT_WORK(&state->commit_work, |
14619 | nonblock ? intel_atomic_commit_work : NULL); | |
14620 | ||
14621 | i915_sw_fence_commit(&intel_state->commit_ready); | |
14622 | if (!nonblock) { | |
14623 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 14624 | intel_atomic_commit_tail(state); |
c004a90b | 14625 | } |
75714940 | 14626 | |
74c090b1 | 14627 | return 0; |
7f27126e JB |
14628 | } |
14629 | ||
c0c36b94 CW |
14630 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
14631 | { | |
83a57153 ACO |
14632 | struct drm_device *dev = crtc->dev; |
14633 | struct drm_atomic_state *state; | |
e694eb02 | 14634 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 14635 | int ret; |
83a57153 ACO |
14636 | |
14637 | state = drm_atomic_state_alloc(dev); | |
14638 | if (!state) { | |
78108b7c VS |
14639 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
14640 | crtc->base.id, crtc->name); | |
83a57153 ACO |
14641 | return; |
14642 | } | |
14643 | ||
e694eb02 | 14644 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 14645 | |
e694eb02 ML |
14646 | retry: |
14647 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
14648 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
14649 | if (!ret) { | |
14650 | if (!crtc_state->active) | |
14651 | goto out; | |
83a57153 | 14652 | |
e694eb02 | 14653 | crtc_state->mode_changed = true; |
74c090b1 | 14654 | ret = drm_atomic_commit(state); |
83a57153 ACO |
14655 | } |
14656 | ||
e694eb02 ML |
14657 | if (ret == -EDEADLK) { |
14658 | drm_atomic_state_clear(state); | |
14659 | drm_modeset_backoff(state->acquire_ctx); | |
14660 | goto retry; | |
4ed9fb37 | 14661 | } |
4be07317 | 14662 | |
e694eb02 | 14663 | out: |
0853695c | 14664 | drm_atomic_state_put(state); |
c0c36b94 CW |
14665 | } |
14666 | ||
a8784875 BP |
14667 | /* |
14668 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
14669 | * drm_atomic_helper_legacy_gamma_set() directly. | |
14670 | */ | |
14671 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
14672 | u16 *red, u16 *green, u16 *blue, | |
14673 | uint32_t size) | |
14674 | { | |
14675 | struct drm_device *dev = crtc->dev; | |
14676 | struct drm_mode_config *config = &dev->mode_config; | |
14677 | struct drm_crtc_state *state; | |
14678 | int ret; | |
14679 | ||
14680 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
14681 | if (ret) | |
14682 | return ret; | |
14683 | ||
14684 | /* | |
14685 | * Make sure we update the legacy properties so this works when | |
14686 | * atomic is not enabled. | |
14687 | */ | |
14688 | ||
14689 | state = crtc->state; | |
14690 | ||
14691 | drm_object_property_set_value(&crtc->base, | |
14692 | config->degamma_lut_property, | |
14693 | (state->degamma_lut) ? | |
14694 | state->degamma_lut->base.id : 0); | |
14695 | ||
14696 | drm_object_property_set_value(&crtc->base, | |
14697 | config->ctm_property, | |
14698 | (state->ctm) ? | |
14699 | state->ctm->base.id : 0); | |
14700 | ||
14701 | drm_object_property_set_value(&crtc->base, | |
14702 | config->gamma_lut_property, | |
14703 | (state->gamma_lut) ? | |
14704 | state->gamma_lut->base.id : 0); | |
14705 | ||
14706 | return 0; | |
14707 | } | |
14708 | ||
f6e5b160 | 14709 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 14710 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 14711 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 14712 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 14713 | .destroy = intel_crtc_destroy, |
527b6abe | 14714 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
14715 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
14716 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
14717 | }; |
14718 | ||
6beb8c23 MR |
14719 | /** |
14720 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
14721 | * @plane: drm plane to prepare for | |
14722 | * @fb: framebuffer to prepare for presentation | |
14723 | * | |
14724 | * Prepares a framebuffer for usage on a display plane. Generally this | |
14725 | * involves pinning the underlying object and updating the frontbuffer tracking | |
14726 | * bits. Some older platforms need special physical address handling for | |
14727 | * cursor planes. | |
14728 | * | |
f935675f ML |
14729 | * Must be called with struct_mutex held. |
14730 | * | |
6beb8c23 MR |
14731 | * Returns 0 on success, negative error code on failure. |
14732 | */ | |
14733 | int | |
14734 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 14735 | struct drm_plane_state *new_state) |
465c120c | 14736 | { |
c004a90b CW |
14737 | struct intel_atomic_state *intel_state = |
14738 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 14739 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 14740 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 14741 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14742 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 14743 | int ret; |
465c120c | 14744 | |
1ee49399 | 14745 | if (!obj && !old_obj) |
465c120c MR |
14746 | return 0; |
14747 | ||
5008e874 ML |
14748 | if (old_obj) { |
14749 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
14750 | drm_atomic_get_existing_crtc_state(new_state->state, |
14751 | plane->state->crtc); | |
5008e874 ML |
14752 | |
14753 | /* Big Hammer, we also need to ensure that any pending | |
14754 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14755 | * current scanout is retired before unpinning the old | |
14756 | * framebuffer. Note that we rely on userspace rendering | |
14757 | * into the buffer attached to the pipe they are waiting | |
14758 | * on. If not, userspace generates a GPU hang with IPEHR | |
14759 | * point to the MI_WAIT_FOR_EVENT. | |
14760 | * | |
14761 | * This should only fail upon a hung GPU, in which case we | |
14762 | * can safely continue. | |
14763 | */ | |
c004a90b CW |
14764 | if (needs_modeset(crtc_state)) { |
14765 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
14766 | old_obj->resv, NULL, | |
14767 | false, 0, | |
14768 | GFP_KERNEL); | |
14769 | if (ret < 0) | |
14770 | return ret; | |
f4457ae7 | 14771 | } |
5008e874 ML |
14772 | } |
14773 | ||
c004a90b CW |
14774 | if (new_state->fence) { /* explicit fencing */ |
14775 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
14776 | new_state->fence, | |
14777 | I915_FENCE_TIMEOUT, | |
14778 | GFP_KERNEL); | |
14779 | if (ret < 0) | |
14780 | return ret; | |
14781 | } | |
14782 | ||
c37efb99 CW |
14783 | if (!obj) |
14784 | return 0; | |
14785 | ||
c004a90b CW |
14786 | if (!new_state->fence) { /* implicit fencing */ |
14787 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
14788 | obj->resv, NULL, | |
14789 | false, I915_FENCE_TIMEOUT, | |
14790 | GFP_KERNEL); | |
14791 | if (ret < 0) | |
14792 | return ret; | |
6b5e90f5 CW |
14793 | |
14794 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
c004a90b | 14795 | } |
5a21b665 | 14796 | |
c37efb99 | 14797 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
b7f05d4a | 14798 | INTEL_INFO(dev_priv)->cursor_needs_physical) { |
50a0bc90 | 14799 | int align = IS_I830(dev_priv) ? 16 * 1024 : 256; |
6beb8c23 | 14800 | ret = i915_gem_object_attach_phys(obj, align); |
d07f0e59 | 14801 | if (ret) { |
6beb8c23 | 14802 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
d07f0e59 CW |
14803 | return ret; |
14804 | } | |
6beb8c23 | 14805 | } else { |
058d88c4 CW |
14806 | struct i915_vma *vma; |
14807 | ||
14808 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
d07f0e59 CW |
14809 | if (IS_ERR(vma)) { |
14810 | DRM_DEBUG_KMS("failed to pin object\n"); | |
14811 | return PTR_ERR(vma); | |
14812 | } | |
7580d774 | 14813 | } |
fdd508a6 | 14814 | |
d07f0e59 | 14815 | return 0; |
6beb8c23 MR |
14816 | } |
14817 | ||
38f3ce3a MR |
14818 | /** |
14819 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14820 | * @plane: drm plane to clean up for | |
14821 | * @fb: old framebuffer that was on plane | |
14822 | * | |
14823 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14824 | * |
14825 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14826 | */ |
14827 | void | |
14828 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 14829 | struct drm_plane_state *old_state) |
38f3ce3a | 14830 | { |
b7f05d4a | 14831 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
7580d774 | 14832 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
14833 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14834 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14835 | |
7580d774 ML |
14836 | old_intel_state = to_intel_plane_state(old_state); |
14837 | ||
1ee49399 | 14838 | if (!obj && !old_obj) |
38f3ce3a MR |
14839 | return; |
14840 | ||
1ee49399 | 14841 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
b7f05d4a | 14842 | !INTEL_INFO(dev_priv)->cursor_needs_physical)) |
3465c580 | 14843 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
465c120c MR |
14844 | } |
14845 | ||
6156a456 CK |
14846 | int |
14847 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14848 | { | |
14849 | int max_scale; | |
6156a456 CK |
14850 | int crtc_clock, cdclk; |
14851 | ||
bf8a0af0 | 14852 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14853 | return DRM_PLANE_HELPER_NO_SCALING; |
14854 | ||
6156a456 | 14855 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
27c329ed | 14856 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14857 | |
54bf1ce6 | 14858 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14859 | return DRM_PLANE_HELPER_NO_SCALING; |
14860 | ||
14861 | /* | |
14862 | * skl max scale is lower of: | |
14863 | * close to 3 but not 3, -1 is for that purpose | |
14864 | * or | |
14865 | * cdclk/crtc_clock | |
14866 | */ | |
14867 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14868 | ||
14869 | return max_scale; | |
14870 | } | |
14871 | ||
465c120c | 14872 | static int |
3c692a41 | 14873 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14874 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14875 | struct intel_plane_state *state) |
14876 | { | |
b63a16f6 | 14877 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 14878 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 14879 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14880 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14881 | bool can_position = false; | |
b63a16f6 | 14882 | int ret; |
465c120c | 14883 | |
b63a16f6 | 14884 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
14885 | /* use scaler when colorkey is not required */ |
14886 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14887 | min_scale = 1; | |
14888 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14889 | } | |
d8106366 | 14890 | can_position = true; |
6156a456 | 14891 | } |
d8106366 | 14892 | |
cc926387 DV |
14893 | ret = drm_plane_helper_check_state(&state->base, |
14894 | &state->clip, | |
14895 | min_scale, max_scale, | |
14896 | can_position, true); | |
b63a16f6 VS |
14897 | if (ret) |
14898 | return ret; | |
14899 | ||
cc926387 | 14900 | if (!state->base.fb) |
b63a16f6 VS |
14901 | return 0; |
14902 | ||
14903 | if (INTEL_GEN(dev_priv) >= 9) { | |
14904 | ret = skl_check_plane_surface(state); | |
14905 | if (ret) | |
14906 | return ret; | |
14907 | } | |
14908 | ||
14909 | return 0; | |
14af293f GP |
14910 | } |
14911 | ||
5a21b665 DV |
14912 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14913 | struct drm_crtc_state *old_crtc_state) | |
14914 | { | |
14915 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 14916 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 14917 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
14918 | struct intel_crtc_state *intel_cstate = |
14919 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 14920 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 14921 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
14922 | struct intel_atomic_state *old_intel_state = |
14923 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
14924 | bool modeset = needs_modeset(crtc->state); |
14925 | ||
14926 | /* Perform vblank evasion around commit operation */ | |
14927 | intel_pipe_update_start(intel_crtc); | |
14928 | ||
14929 | if (modeset) | |
e62929b3 | 14930 | goto out; |
5a21b665 DV |
14931 | |
14932 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14933 | intel_color_set_csc(crtc->state); | |
14934 | intel_color_load_luts(crtc->state); | |
14935 | } | |
14936 | ||
ccf010fb ML |
14937 | if (intel_cstate->update_pipe) |
14938 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
14939 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 14940 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 14941 | |
e62929b3 | 14942 | out: |
ccf010fb ML |
14943 | if (dev_priv->display.atomic_update_watermarks) |
14944 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
14945 | intel_cstate); | |
5a21b665 DV |
14946 | } |
14947 | ||
14948 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
14949 | struct drm_crtc_state *old_crtc_state) | |
14950 | { | |
14951 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14952 | ||
14953 | intel_pipe_update_end(intel_crtc, NULL); | |
14954 | } | |
14955 | ||
cf4c7c12 | 14956 | /** |
4a3b8769 MR |
14957 | * intel_plane_destroy - destroy a plane |
14958 | * @plane: plane to destroy | |
cf4c7c12 | 14959 | * |
4a3b8769 MR |
14960 | * Common destruction function for all types of planes (primary, cursor, |
14961 | * sprite). | |
cf4c7c12 | 14962 | */ |
4a3b8769 | 14963 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 14964 | { |
465c120c | 14965 | drm_plane_cleanup(plane); |
69ae561f | 14966 | kfree(to_intel_plane(plane)); |
465c120c MR |
14967 | } |
14968 | ||
65a3fea0 | 14969 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14970 | .update_plane = drm_atomic_helper_update_plane, |
14971 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14972 | .destroy = intel_plane_destroy, |
c196e1d6 | 14973 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14974 | .atomic_get_property = intel_plane_atomic_get_property, |
14975 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14976 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14977 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
14978 | }; |
14979 | ||
b079bd17 | 14980 | static struct intel_plane * |
580503c7 | 14981 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 14982 | { |
fca0ce2a VS |
14983 | struct intel_plane *primary = NULL; |
14984 | struct intel_plane_state *state = NULL; | |
465c120c | 14985 | const uint32_t *intel_primary_formats; |
93ca7e00 | 14986 | unsigned int supported_rotations; |
45e3743a | 14987 | unsigned int num_formats; |
fca0ce2a | 14988 | int ret; |
465c120c MR |
14989 | |
14990 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
14991 | if (!primary) { |
14992 | ret = -ENOMEM; | |
fca0ce2a | 14993 | goto fail; |
b079bd17 | 14994 | } |
465c120c | 14995 | |
8e7d688b | 14996 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
14997 | if (!state) { |
14998 | ret = -ENOMEM; | |
fca0ce2a | 14999 | goto fail; |
b079bd17 VS |
15000 | } |
15001 | ||
8e7d688b | 15002 | primary->base.state = &state->base; |
ea2c67bb | 15003 | |
465c120c MR |
15004 | primary->can_scale = false; |
15005 | primary->max_downscale = 1; | |
580503c7 | 15006 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 15007 | primary->can_scale = true; |
af99ceda | 15008 | state->scaler_id = -1; |
6156a456 | 15009 | } |
465c120c | 15010 | primary->pipe = pipe; |
e3c566df VS |
15011 | /* |
15012 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
15013 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
15014 | */ | |
15015 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
15016 | primary->plane = (enum plane) !pipe; | |
15017 | else | |
15018 | primary->plane = (enum plane) pipe; | |
b14e5848 | 15019 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 15020 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 15021 | primary->check_plane = intel_check_primary_plane; |
465c120c | 15022 | |
580503c7 | 15023 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
15024 | intel_primary_formats = skl_primary_formats; |
15025 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
15026 | |
15027 | primary->update_plane = skylake_update_primary_plane; | |
15028 | primary->disable_plane = skylake_disable_primary_plane; | |
6e266956 | 15029 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
a8d201af ML |
15030 | intel_primary_formats = i965_primary_formats; |
15031 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
15032 | ||
15033 | primary->update_plane = ironlake_update_primary_plane; | |
15034 | primary->disable_plane = i9xx_disable_primary_plane; | |
580503c7 | 15035 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
15036 | intel_primary_formats = i965_primary_formats; |
15037 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
15038 | |
15039 | primary->update_plane = i9xx_update_primary_plane; | |
15040 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
15041 | } else { |
15042 | intel_primary_formats = i8xx_primary_formats; | |
15043 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
15044 | |
15045 | primary->update_plane = i9xx_update_primary_plane; | |
15046 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
15047 | } |
15048 | ||
580503c7 VS |
15049 | if (INTEL_GEN(dev_priv) >= 9) |
15050 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
15051 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15052 | intel_primary_formats, num_formats, |
15053 | DRM_PLANE_TYPE_PRIMARY, | |
15054 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 15055 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
15056 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
15057 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15058 | intel_primary_formats, num_formats, |
15059 | DRM_PLANE_TYPE_PRIMARY, | |
15060 | "primary %c", pipe_name(pipe)); | |
15061 | else | |
580503c7 VS |
15062 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
15063 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15064 | intel_primary_formats, num_formats, |
15065 | DRM_PLANE_TYPE_PRIMARY, | |
15066 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
15067 | if (ret) |
15068 | goto fail; | |
48404c1e | 15069 | |
5481e27f | 15070 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 VS |
15071 | supported_rotations = |
15072 | DRM_ROTATE_0 | DRM_ROTATE_90 | | |
15073 | DRM_ROTATE_180 | DRM_ROTATE_270; | |
4ea7be2b VS |
15074 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
15075 | supported_rotations = | |
15076 | DRM_ROTATE_0 | DRM_ROTATE_180 | | |
15077 | DRM_REFLECT_X; | |
5481e27f | 15078 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 VS |
15079 | supported_rotations = |
15080 | DRM_ROTATE_0 | DRM_ROTATE_180; | |
15081 | } else { | |
15082 | supported_rotations = DRM_ROTATE_0; | |
15083 | } | |
15084 | ||
5481e27f | 15085 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
15086 | drm_plane_create_rotation_property(&primary->base, |
15087 | DRM_ROTATE_0, | |
15088 | supported_rotations); | |
48404c1e | 15089 | |
ea2c67bb MR |
15090 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
15091 | ||
b079bd17 | 15092 | return primary; |
fca0ce2a VS |
15093 | |
15094 | fail: | |
15095 | kfree(state); | |
15096 | kfree(primary); | |
15097 | ||
b079bd17 | 15098 | return ERR_PTR(ret); |
465c120c MR |
15099 | } |
15100 | ||
3d7d6510 | 15101 | static int |
852e787c | 15102 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 15103 | struct intel_crtc_state *crtc_state, |
852e787c | 15104 | struct intel_plane_state *state) |
3d7d6510 | 15105 | { |
2b875c22 | 15106 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 15107 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 15108 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
15109 | unsigned stride; |
15110 | int ret; | |
3d7d6510 | 15111 | |
f8856a44 VS |
15112 | ret = drm_plane_helper_check_state(&state->base, |
15113 | &state->clip, | |
15114 | DRM_PLANE_HELPER_NO_SCALING, | |
15115 | DRM_PLANE_HELPER_NO_SCALING, | |
15116 | true, true); | |
757f9a3e GP |
15117 | if (ret) |
15118 | return ret; | |
15119 | ||
757f9a3e GP |
15120 | /* if we want to turn off the cursor ignore width and height */ |
15121 | if (!obj) | |
da20eabd | 15122 | return 0; |
757f9a3e | 15123 | |
757f9a3e | 15124 | /* Check for which cursor types we support */ |
50a0bc90 TU |
15125 | if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w, |
15126 | state->base.crtc_h)) { | |
ea2c67bb MR |
15127 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
15128 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
15129 | return -EINVAL; |
15130 | } | |
15131 | ||
ea2c67bb MR |
15132 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
15133 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
15134 | DRM_DEBUG_KMS("buffer is too small\n"); |
15135 | return -ENOMEM; | |
15136 | } | |
15137 | ||
3a656b54 | 15138 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 15139 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 15140 | return -EINVAL; |
32b7eeec MR |
15141 | } |
15142 | ||
b29ec92c VS |
15143 | /* |
15144 | * There's something wrong with the cursor on CHV pipe C. | |
15145 | * If it straddles the left edge of the screen then | |
15146 | * moving it away from the edge or disabling it often | |
15147 | * results in a pipe underrun, and often that can lead to | |
15148 | * dead pipe (constant underrun reported, and it scans | |
15149 | * out just a solid color). To recover from that, the | |
15150 | * display power well must be turned off and on again. | |
15151 | * Refuse the put the cursor into that compromised position. | |
15152 | */ | |
920a14b2 | 15153 | if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C && |
936e71e3 | 15154 | state->base.visible && state->base.crtc_x < 0) { |
b29ec92c VS |
15155 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
15156 | return -EINVAL; | |
15157 | } | |
15158 | ||
da20eabd | 15159 | return 0; |
852e787c | 15160 | } |
3d7d6510 | 15161 | |
a8ad0d8e ML |
15162 | static void |
15163 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 15164 | struct drm_crtc *crtc) |
a8ad0d8e | 15165 | { |
f2858021 ML |
15166 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
15167 | ||
15168 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 15169 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
15170 | } |
15171 | ||
f4a2cf29 | 15172 | static void |
55a08b3f ML |
15173 | intel_update_cursor_plane(struct drm_plane *plane, |
15174 | const struct intel_crtc_state *crtc_state, | |
15175 | const struct intel_plane_state *state) | |
852e787c | 15176 | { |
55a08b3f ML |
15177 | struct drm_crtc *crtc = crtc_state->base.crtc; |
15178 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b7f05d4a | 15179 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 15180 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 15181 | uint32_t addr; |
852e787c | 15182 | |
f4a2cf29 | 15183 | if (!obj) |
a912f12f | 15184 | addr = 0; |
b7f05d4a | 15185 | else if (!INTEL_INFO(dev_priv)->cursor_needs_physical) |
058d88c4 | 15186 | addr = i915_gem_object_ggtt_offset(obj, NULL); |
f4a2cf29 | 15187 | else |
a912f12f | 15188 | addr = obj->phys_handle->busaddr; |
852e787c | 15189 | |
a912f12f | 15190 | intel_crtc->cursor_addr = addr; |
55a08b3f | 15191 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
15192 | } |
15193 | ||
b079bd17 | 15194 | static struct intel_plane * |
580503c7 | 15195 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
3d7d6510 | 15196 | { |
fca0ce2a VS |
15197 | struct intel_plane *cursor = NULL; |
15198 | struct intel_plane_state *state = NULL; | |
15199 | int ret; | |
3d7d6510 MR |
15200 | |
15201 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
15202 | if (!cursor) { |
15203 | ret = -ENOMEM; | |
fca0ce2a | 15204 | goto fail; |
b079bd17 | 15205 | } |
3d7d6510 | 15206 | |
8e7d688b | 15207 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
15208 | if (!state) { |
15209 | ret = -ENOMEM; | |
fca0ce2a | 15210 | goto fail; |
b079bd17 VS |
15211 | } |
15212 | ||
8e7d688b | 15213 | cursor->base.state = &state->base; |
ea2c67bb | 15214 | |
3d7d6510 MR |
15215 | cursor->can_scale = false; |
15216 | cursor->max_downscale = 1; | |
15217 | cursor->pipe = pipe; | |
15218 | cursor->plane = pipe; | |
b14e5848 | 15219 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 15220 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 15221 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 15222 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 15223 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 15224 | |
580503c7 VS |
15225 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
15226 | 0, &intel_plane_funcs, | |
fca0ce2a VS |
15227 | intel_cursor_formats, |
15228 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
15229 | DRM_PLANE_TYPE_CURSOR, |
15230 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
15231 | if (ret) |
15232 | goto fail; | |
4398ad45 | 15233 | |
5481e27f | 15234 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
15235 | drm_plane_create_rotation_property(&cursor->base, |
15236 | DRM_ROTATE_0, | |
15237 | DRM_ROTATE_0 | | |
15238 | DRM_ROTATE_180); | |
4398ad45 | 15239 | |
580503c7 | 15240 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
15241 | state->scaler_id = -1; |
15242 | ||
ea2c67bb MR |
15243 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
15244 | ||
b079bd17 | 15245 | return cursor; |
fca0ce2a VS |
15246 | |
15247 | fail: | |
15248 | kfree(state); | |
15249 | kfree(cursor); | |
15250 | ||
b079bd17 | 15251 | return ERR_PTR(ret); |
3d7d6510 MR |
15252 | } |
15253 | ||
65edccce VS |
15254 | static void skl_init_scalers(struct drm_i915_private *dev_priv, |
15255 | struct intel_crtc *crtc, | |
15256 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 15257 | { |
65edccce VS |
15258 | struct intel_crtc_scaler_state *scaler_state = |
15259 | &crtc_state->scaler_state; | |
549e2bfb | 15260 | int i; |
549e2bfb | 15261 | |
65edccce VS |
15262 | for (i = 0; i < crtc->num_scalers; i++) { |
15263 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
15264 | ||
15265 | scaler->in_use = 0; | |
15266 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
15267 | } |
15268 | ||
15269 | scaler_state->scaler_id = -1; | |
15270 | } | |
15271 | ||
5ab0d85b | 15272 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
15273 | { |
15274 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 15275 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
15276 | struct intel_plane *primary = NULL; |
15277 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 15278 | int sprite, ret; |
79e53945 | 15279 | |
955382f3 | 15280 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
15281 | if (!intel_crtc) |
15282 | return -ENOMEM; | |
79e53945 | 15283 | |
f5de6e07 | 15284 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
15285 | if (!crtc_state) { |
15286 | ret = -ENOMEM; | |
f5de6e07 | 15287 | goto fail; |
b079bd17 | 15288 | } |
550acefd ACO |
15289 | intel_crtc->config = crtc_state; |
15290 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 15291 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 15292 | |
549e2bfb | 15293 | /* initialize shared scalers */ |
5ab0d85b | 15294 | if (INTEL_GEN(dev_priv) >= 9) { |
549e2bfb CK |
15295 | if (pipe == PIPE_C) |
15296 | intel_crtc->num_scalers = 1; | |
15297 | else | |
15298 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
15299 | ||
65edccce | 15300 | skl_init_scalers(dev_priv, intel_crtc, crtc_state); |
549e2bfb CK |
15301 | } |
15302 | ||
580503c7 | 15303 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
15304 | if (IS_ERR(primary)) { |
15305 | ret = PTR_ERR(primary); | |
3d7d6510 | 15306 | goto fail; |
b079bd17 | 15307 | } |
d97d7b48 | 15308 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 15309 | |
a81d6fa0 | 15310 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
15311 | struct intel_plane *plane; |
15312 | ||
580503c7 | 15313 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 15314 | if (IS_ERR(plane)) { |
b079bd17 VS |
15315 | ret = PTR_ERR(plane); |
15316 | goto fail; | |
15317 | } | |
d97d7b48 | 15318 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
15319 | } |
15320 | ||
580503c7 | 15321 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 15322 | if (IS_ERR(cursor)) { |
b079bd17 | 15323 | ret = PTR_ERR(cursor); |
3d7d6510 | 15324 | goto fail; |
b079bd17 | 15325 | } |
d97d7b48 | 15326 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 15327 | |
5ab0d85b | 15328 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
15329 | &primary->base, &cursor->base, |
15330 | &intel_crtc_funcs, | |
4d5d72b7 | 15331 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
15332 | if (ret) |
15333 | goto fail; | |
79e53945 | 15334 | |
80824003 | 15335 | intel_crtc->pipe = pipe; |
e3c566df | 15336 | intel_crtc->plane = primary->plane; |
80824003 | 15337 | |
4b0e333e CW |
15338 | intel_crtc->cursor_base = ~0; |
15339 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 15340 | intel_crtc->cursor_size = ~0; |
8d7849db | 15341 | |
852eb00d VS |
15342 | intel_crtc->wm.cxsr_allowed = true; |
15343 | ||
22fd0fab JB |
15344 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
15345 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
15346 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
15347 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 15348 | |
79e53945 | 15349 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 15350 | |
8563b1e8 LL |
15351 | intel_color_init(&intel_crtc->base); |
15352 | ||
87b6b101 | 15353 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
15354 | |
15355 | return 0; | |
3d7d6510 MR |
15356 | |
15357 | fail: | |
b079bd17 VS |
15358 | /* |
15359 | * drm_mode_config_cleanup() will free up any | |
15360 | * crtcs/planes already initialized. | |
15361 | */ | |
f5de6e07 | 15362 | kfree(crtc_state); |
3d7d6510 | 15363 | kfree(intel_crtc); |
b079bd17 VS |
15364 | |
15365 | return ret; | |
79e53945 JB |
15366 | } |
15367 | ||
752aa88a JB |
15368 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
15369 | { | |
15370 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 15371 | struct drm_device *dev = connector->base.dev; |
752aa88a | 15372 | |
51fd371b | 15373 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 15374 | |
d3babd3f | 15375 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
15376 | return INVALID_PIPE; |
15377 | ||
15378 | return to_intel_crtc(encoder->crtc)->pipe; | |
15379 | } | |
15380 | ||
08d7b3d1 | 15381 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 15382 | struct drm_file *file) |
08d7b3d1 | 15383 | { |
08d7b3d1 | 15384 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 15385 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 15386 | struct intel_crtc *crtc; |
08d7b3d1 | 15387 | |
7707e653 | 15388 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 15389 | if (!drmmode_crtc) |
3f2c2057 | 15390 | return -ENOENT; |
08d7b3d1 | 15391 | |
7707e653 | 15392 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 15393 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 15394 | |
c05422d5 | 15395 | return 0; |
08d7b3d1 CW |
15396 | } |
15397 | ||
66a9278e | 15398 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 15399 | { |
66a9278e DV |
15400 | struct drm_device *dev = encoder->base.dev; |
15401 | struct intel_encoder *source_encoder; | |
79e53945 | 15402 | int index_mask = 0; |
79e53945 JB |
15403 | int entry = 0; |
15404 | ||
b2784e15 | 15405 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 15406 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
15407 | index_mask |= (1 << entry); |
15408 | ||
79e53945 JB |
15409 | entry++; |
15410 | } | |
4ef69c7a | 15411 | |
79e53945 JB |
15412 | return index_mask; |
15413 | } | |
15414 | ||
646d5772 | 15415 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 15416 | { |
646d5772 | 15417 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
15418 | return false; |
15419 | ||
15420 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
15421 | return false; | |
15422 | ||
5db94019 | 15423 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
15424 | return false; |
15425 | ||
15426 | return true; | |
15427 | } | |
15428 | ||
6315b5d3 | 15429 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 15430 | { |
6315b5d3 | 15431 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
15432 | return false; |
15433 | ||
50a0bc90 | 15434 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
15435 | return false; |
15436 | ||
920a14b2 | 15437 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
15438 | return false; |
15439 | ||
4f8036a2 TU |
15440 | if (HAS_PCH_LPT_H(dev_priv) && |
15441 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
15442 | return false; |
15443 | ||
70ac54d0 | 15444 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 15445 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
15446 | return false; |
15447 | ||
e4abb733 | 15448 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
15449 | return false; |
15450 | ||
15451 | return true; | |
15452 | } | |
15453 | ||
8090ba8c ID |
15454 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
15455 | { | |
15456 | int pps_num; | |
15457 | int pps_idx; | |
15458 | ||
15459 | if (HAS_DDI(dev_priv)) | |
15460 | return; | |
15461 | /* | |
15462 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
15463 | * everywhere where registers can be write protected. | |
15464 | */ | |
15465 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15466 | pps_num = 2; | |
15467 | else | |
15468 | pps_num = 1; | |
15469 | ||
15470 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
15471 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
15472 | ||
15473 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
15474 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
15475 | } | |
15476 | } | |
15477 | ||
44cb734c ID |
15478 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
15479 | { | |
15480 | if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv)) | |
15481 | dev_priv->pps_mmio_base = PCH_PPS_BASE; | |
15482 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15483 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
15484 | else | |
15485 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
15486 | |
15487 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
15488 | } |
15489 | ||
c39055b0 | 15490 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 15491 | { |
4ef69c7a | 15492 | struct intel_encoder *encoder; |
cb0953d7 | 15493 | bool dpd_is_edp = false; |
79e53945 | 15494 | |
44cb734c ID |
15495 | intel_pps_init(dev_priv); |
15496 | ||
97a824e1 ID |
15497 | /* |
15498 | * intel_edp_init_connector() depends on this completing first, to | |
15499 | * prevent the registeration of both eDP and LVDS and the incorrect | |
15500 | * sharing of the PPS. | |
15501 | */ | |
c39055b0 | 15502 | intel_lvds_init(dev_priv); |
79e53945 | 15503 | |
6315b5d3 | 15504 | if (intel_crt_present(dev_priv)) |
c39055b0 | 15505 | intel_crt_init(dev_priv); |
cb0953d7 | 15506 | |
e2d214ae | 15507 | if (IS_BROXTON(dev_priv)) { |
c776eb2e VK |
15508 | /* |
15509 | * FIXME: Broxton doesn't support port detection via the | |
15510 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
15511 | * detect the ports. | |
15512 | */ | |
c39055b0 ACO |
15513 | intel_ddi_init(dev_priv, PORT_A); |
15514 | intel_ddi_init(dev_priv, PORT_B); | |
15515 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 15516 | |
c39055b0 | 15517 | intel_dsi_init(dev_priv); |
4f8036a2 | 15518 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
15519 | int found; |
15520 | ||
de31facd JB |
15521 | /* |
15522 | * Haswell uses DDI functions to detect digital outputs. | |
15523 | * On SKL pre-D0 the strap isn't connected, so we assume | |
15524 | * it's there. | |
15525 | */ | |
77179400 | 15526 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 15527 | /* WaIgnoreDDIAStrap: skl */ |
0853723b | 15528 | if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
c39055b0 | 15529 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
15530 | |
15531 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
15532 | * register */ | |
15533 | found = I915_READ(SFUSE_STRAP); | |
15534 | ||
15535 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 15536 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 15537 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 15538 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 15539 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 15540 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
15541 | /* |
15542 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
15543 | */ | |
0853723b | 15544 | if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && |
2800e4c2 RV |
15545 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
15546 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
15547 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 15548 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 15549 | |
6e266956 | 15550 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 15551 | int found; |
dd11bc10 | 15552 | dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); |
270b3042 | 15553 | |
646d5772 | 15554 | if (has_edp_a(dev_priv)) |
c39055b0 | 15555 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 15556 | |
dc0fa718 | 15557 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 15558 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 15559 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 15560 | if (!found) |
c39055b0 | 15561 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 15562 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 15563 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
15564 | } |
15565 | ||
dc0fa718 | 15566 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 15567 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 15568 | |
dc0fa718 | 15569 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 15570 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 15571 | |
5eb08b69 | 15572 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 15573 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 15574 | |
270b3042 | 15575 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 15576 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 15577 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 15578 | bool has_edp, has_port; |
457c52d8 | 15579 | |
e17ac6db VS |
15580 | /* |
15581 | * The DP_DETECTED bit is the latched state of the DDC | |
15582 | * SDA pin at boot. However since eDP doesn't require DDC | |
15583 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
15584 | * eDP ports may have been muxed to an alternate function. | |
15585 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
15586 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
15587 | * detect eDP ports. | |
22f35042 VS |
15588 | * |
15589 | * Sadly the straps seem to be missing sometimes even for HDMI | |
15590 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
15591 | * and VBT for the presence of the port. Additionally we can't | |
15592 | * trust the port type the VBT declares as we've seen at least | |
15593 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 15594 | */ |
dd11bc10 | 15595 | has_edp = intel_dp_is_edp(dev_priv, PORT_B); |
22f35042 VS |
15596 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
15597 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 15598 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 15599 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 15600 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 15601 | |
dd11bc10 | 15602 | has_edp = intel_dp_is_edp(dev_priv, PORT_C); |
22f35042 VS |
15603 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
15604 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 15605 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 15606 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 15607 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 15608 | |
920a14b2 | 15609 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
15610 | /* |
15611 | * eDP not supported on port D, | |
15612 | * so no need to worry about it | |
15613 | */ | |
15614 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
15615 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 15616 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 15617 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 15618 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
15619 | } |
15620 | ||
c39055b0 | 15621 | intel_dsi_init(dev_priv); |
5db94019 | 15622 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 15623 | bool found = false; |
7d57382e | 15624 | |
e2debe91 | 15625 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15626 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 15627 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 15628 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 15629 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 15630 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 15631 | } |
27185ae1 | 15632 | |
9beb5fea | 15633 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 15634 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 15635 | } |
13520b05 KH |
15636 | |
15637 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 15638 | |
e2debe91 | 15639 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15640 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 15641 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 15642 | } |
27185ae1 | 15643 | |
e2debe91 | 15644 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 15645 | |
9beb5fea | 15646 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 15647 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 15648 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 15649 | } |
9beb5fea | 15650 | if (IS_G4X(dev_priv)) |
c39055b0 | 15651 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 15652 | } |
27185ae1 | 15653 | |
9beb5fea | 15654 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 15655 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 15656 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 15657 | intel_dvo_init(dev_priv); |
79e53945 | 15658 | |
56b857a5 | 15659 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 15660 | intel_tv_init(dev_priv); |
79e53945 | 15661 | |
c39055b0 | 15662 | intel_psr_init(dev_priv); |
7c8f8a70 | 15663 | |
c39055b0 | 15664 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
15665 | encoder->base.possible_crtcs = encoder->crtc_mask; |
15666 | encoder->base.possible_clones = | |
66a9278e | 15667 | intel_encoder_clones(encoder); |
79e53945 | 15668 | } |
47356eb6 | 15669 | |
c39055b0 | 15670 | intel_init_pch_refclk(dev_priv); |
270b3042 | 15671 | |
c39055b0 | 15672 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
15673 | } |
15674 | ||
15675 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
15676 | { | |
60a5ca01 | 15677 | struct drm_device *dev = fb->dev; |
79e53945 | 15678 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 15679 | |
ef2d633e | 15680 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 15681 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 15682 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
f8c417cd | 15683 | i915_gem_object_put(intel_fb->obj); |
60a5ca01 | 15684 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
15685 | kfree(intel_fb); |
15686 | } | |
15687 | ||
15688 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 15689 | struct drm_file *file, |
79e53945 JB |
15690 | unsigned int *handle) |
15691 | { | |
15692 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 15693 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 15694 | |
cc917ab4 CW |
15695 | if (obj->userptr.mm) { |
15696 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
15697 | return -EINVAL; | |
15698 | } | |
15699 | ||
05394f39 | 15700 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
15701 | } |
15702 | ||
86c98588 RV |
15703 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
15704 | struct drm_file *file, | |
15705 | unsigned flags, unsigned color, | |
15706 | struct drm_clip_rect *clips, | |
15707 | unsigned num_clips) | |
15708 | { | |
15709 | struct drm_device *dev = fb->dev; | |
15710 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
15711 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
15712 | ||
15713 | mutex_lock(&dev->struct_mutex); | |
a6a7cc4b CW |
15714 | if (obj->pin_display && obj->cache_dirty) |
15715 | i915_gem_clflush_object(obj, true); | |
74b4ea1e | 15716 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
15717 | mutex_unlock(&dev->struct_mutex); |
15718 | ||
15719 | return 0; | |
15720 | } | |
15721 | ||
79e53945 JB |
15722 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
15723 | .destroy = intel_user_framebuffer_destroy, | |
15724 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 15725 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
15726 | }; |
15727 | ||
b321803d | 15728 | static |
920a14b2 TU |
15729 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
15730 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 15731 | { |
920a14b2 | 15732 | u32 gen = INTEL_INFO(dev_priv)->gen; |
b321803d DL |
15733 | |
15734 | if (gen >= 9) { | |
ac484963 VS |
15735 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
15736 | ||
b321803d DL |
15737 | /* "The stride in bytes must not exceed the of the size of 8K |
15738 | * pixels and 32K bytes." | |
15739 | */ | |
ac484963 | 15740 | return min(8192 * cpp, 32768); |
920a14b2 TU |
15741 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) && |
15742 | !IS_CHERRYVIEW(dev_priv)) { | |
b321803d DL |
15743 | return 32*1024; |
15744 | } else if (gen >= 4) { | |
15745 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15746 | return 16*1024; | |
15747 | else | |
15748 | return 32*1024; | |
15749 | } else if (gen >= 3) { | |
15750 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15751 | return 8*1024; | |
15752 | else | |
15753 | return 16*1024; | |
15754 | } else { | |
15755 | /* XXX DSPC is limited to 4k tiled */ | |
15756 | return 8*1024; | |
15757 | } | |
15758 | } | |
15759 | ||
b5ea642a DV |
15760 | static int intel_framebuffer_init(struct drm_device *dev, |
15761 | struct intel_framebuffer *intel_fb, | |
15762 | struct drm_mode_fb_cmd2 *mode_cmd, | |
15763 | struct drm_i915_gem_object *obj) | |
79e53945 | 15764 | { |
7b49f948 | 15765 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2ff7370 | 15766 | unsigned int tiling = i915_gem_object_get_tiling(obj); |
79e53945 | 15767 | int ret; |
b321803d | 15768 | u32 pitch_limit, stride_alignment; |
b3c11ac2 | 15769 | struct drm_format_name_buf format_name; |
79e53945 | 15770 | |
dd4916c5 DV |
15771 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
15772 | ||
2a80eada | 15773 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
15774 | /* |
15775 | * If there's a fence, enforce that | |
15776 | * the fb modifier and tiling mode match. | |
15777 | */ | |
15778 | if (tiling != I915_TILING_NONE && | |
15779 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
2a80eada DV |
15780 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
15781 | return -EINVAL; | |
15782 | } | |
15783 | } else { | |
c2ff7370 | 15784 | if (tiling == I915_TILING_X) { |
2a80eada | 15785 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 15786 | } else if (tiling == I915_TILING_Y) { |
2a80eada DV |
15787 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
15788 | return -EINVAL; | |
15789 | } | |
15790 | } | |
15791 | ||
9a8f0a12 TU |
15792 | /* Passed in modifier sanity checking. */ |
15793 | switch (mode_cmd->modifier[0]) { | |
15794 | case I915_FORMAT_MOD_Y_TILED: | |
15795 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 15796 | if (INTEL_GEN(dev_priv) < 9) { |
9a8f0a12 TU |
15797 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", |
15798 | mode_cmd->modifier[0]); | |
15799 | return -EINVAL; | |
15800 | } | |
15801 | case DRM_FORMAT_MOD_NONE: | |
15802 | case I915_FORMAT_MOD_X_TILED: | |
15803 | break; | |
15804 | default: | |
c0f40428 JB |
15805 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
15806 | mode_cmd->modifier[0]); | |
57cd6508 | 15807 | return -EINVAL; |
c16ed4be | 15808 | } |
57cd6508 | 15809 | |
c2ff7370 VS |
15810 | /* |
15811 | * gen2/3 display engine uses the fence if present, | |
15812 | * so the tiling mode must match the fb modifier exactly. | |
15813 | */ | |
15814 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
15815 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
15816 | DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n"); | |
15817 | return -EINVAL; | |
15818 | } | |
15819 | ||
7b49f948 VS |
15820 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
15821 | mode_cmd->modifier[0], | |
b321803d DL |
15822 | mode_cmd->pixel_format); |
15823 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
15824 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
15825 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 15826 | return -EINVAL; |
c16ed4be | 15827 | } |
57cd6508 | 15828 | |
920a14b2 | 15829 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 15830 | mode_cmd->pixel_format); |
a35cdaa0 | 15831 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
15832 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
15833 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 15834 | "tiled" : "linear", |
a35cdaa0 | 15835 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 15836 | return -EINVAL; |
c16ed4be | 15837 | } |
5d7bd705 | 15838 | |
c2ff7370 VS |
15839 | /* |
15840 | * If there's a fence, enforce that | |
15841 | * the fb pitch and fence stride match. | |
15842 | */ | |
15843 | if (tiling != I915_TILING_NONE && | |
3e510a8e | 15844 | mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) { |
c16ed4be | 15845 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
3e510a8e CW |
15846 | mode_cmd->pitches[0], |
15847 | i915_gem_object_get_stride(obj)); | |
5d7bd705 | 15848 | return -EINVAL; |
c16ed4be | 15849 | } |
5d7bd705 | 15850 | |
57779d06 | 15851 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 15852 | switch (mode_cmd->pixel_format) { |
57779d06 | 15853 | case DRM_FORMAT_C8: |
04b3924d VS |
15854 | case DRM_FORMAT_RGB565: |
15855 | case DRM_FORMAT_XRGB8888: | |
15856 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
15857 | break; |
15858 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 15859 | if (INTEL_GEN(dev_priv) > 3) { |
b3c11ac2 EE |
15860 | DRM_DEBUG("unsupported pixel format: %s\n", |
15861 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57779d06 | 15862 | return -EINVAL; |
c16ed4be | 15863 | } |
57779d06 | 15864 | break; |
57779d06 | 15865 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 15866 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 15867 | INTEL_GEN(dev_priv) < 9) { |
b3c11ac2 EE |
15868 | DRM_DEBUG("unsupported pixel format: %s\n", |
15869 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
6c0fd451 DL |
15870 | return -EINVAL; |
15871 | } | |
15872 | break; | |
15873 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15874 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15875 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 15876 | if (INTEL_GEN(dev_priv) < 4) { |
b3c11ac2 EE |
15877 | DRM_DEBUG("unsupported pixel format: %s\n", |
15878 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57779d06 | 15879 | return -EINVAL; |
c16ed4be | 15880 | } |
b5626747 | 15881 | break; |
7531208b | 15882 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 15883 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
b3c11ac2 EE |
15884 | DRM_DEBUG("unsupported pixel format: %s\n", |
15885 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
7531208b DL |
15886 | return -EINVAL; |
15887 | } | |
15888 | break; | |
04b3924d VS |
15889 | case DRM_FORMAT_YUYV: |
15890 | case DRM_FORMAT_UYVY: | |
15891 | case DRM_FORMAT_YVYU: | |
15892 | case DRM_FORMAT_VYUY: | |
6315b5d3 | 15893 | if (INTEL_GEN(dev_priv) < 5) { |
b3c11ac2 EE |
15894 | DRM_DEBUG("unsupported pixel format: %s\n", |
15895 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57779d06 | 15896 | return -EINVAL; |
c16ed4be | 15897 | } |
57cd6508 CW |
15898 | break; |
15899 | default: | |
b3c11ac2 EE |
15900 | DRM_DEBUG("unsupported pixel format: %s\n", |
15901 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
57cd6508 CW |
15902 | return -EINVAL; |
15903 | } | |
15904 | ||
90f9a336 VS |
15905 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15906 | if (mode_cmd->offsets[0] != 0) | |
15907 | return -EINVAL; | |
15908 | ||
c7d73f6a DV |
15909 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15910 | intel_fb->obj = obj; | |
15911 | ||
6687c906 VS |
15912 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
15913 | if (ret) | |
15914 | return ret; | |
2d7a215f | 15915 | |
79e53945 JB |
15916 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15917 | if (ret) { | |
15918 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15919 | return ret; | |
15920 | } | |
15921 | ||
0b05e1e0 VS |
15922 | intel_fb->obj->framebuffer_references++; |
15923 | ||
79e53945 JB |
15924 | return 0; |
15925 | } | |
15926 | ||
79e53945 JB |
15927 | static struct drm_framebuffer * |
15928 | intel_user_framebuffer_create(struct drm_device *dev, | |
15929 | struct drm_file *filp, | |
1eb83451 | 15930 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15931 | { |
dcb1394e | 15932 | struct drm_framebuffer *fb; |
05394f39 | 15933 | struct drm_i915_gem_object *obj; |
76dc3769 | 15934 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15935 | |
03ac0642 CW |
15936 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
15937 | if (!obj) | |
cce13ff7 | 15938 | return ERR_PTR(-ENOENT); |
79e53945 | 15939 | |
92907cbb | 15940 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e | 15941 | if (IS_ERR(fb)) |
f0cd5182 | 15942 | i915_gem_object_put(obj); |
dcb1394e LW |
15943 | |
15944 | return fb; | |
79e53945 JB |
15945 | } |
15946 | ||
79e53945 | 15947 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15948 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15949 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15950 | .atomic_check = intel_atomic_check, |
15951 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15952 | .atomic_state_alloc = intel_atomic_state_alloc, |
15953 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15954 | }; |
15955 | ||
88212941 ID |
15956 | /** |
15957 | * intel_init_display_hooks - initialize the display modesetting hooks | |
15958 | * @dev_priv: device private | |
15959 | */ | |
15960 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 15961 | { |
88212941 | 15962 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 15963 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15964 | dev_priv->display.get_initial_plane_config = |
15965 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15966 | dev_priv->display.crtc_compute_clock = |
15967 | haswell_crtc_compute_clock; | |
15968 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15969 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15970 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 15971 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15972 | dev_priv->display.get_initial_plane_config = |
15973 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15974 | dev_priv->display.crtc_compute_clock = |
15975 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15976 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15977 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15978 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 15979 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15980 | dev_priv->display.get_initial_plane_config = |
15981 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15982 | dev_priv->display.crtc_compute_clock = |
15983 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15984 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15985 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 15986 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 15987 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15988 | dev_priv->display.get_initial_plane_config = |
15989 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
15990 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
15991 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
15992 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
15993 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
15994 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15995 | dev_priv->display.get_initial_plane_config = | |
15996 | i9xx_get_initial_plane_config; | |
15997 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
15998 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15999 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
16000 | } else if (IS_G4X(dev_priv)) { |
16001 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16002 | dev_priv->display.get_initial_plane_config = | |
16003 | i9xx_get_initial_plane_config; | |
16004 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
16005 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
16006 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
16007 | } else if (IS_PINEVIEW(dev_priv)) { |
16008 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16009 | dev_priv->display.get_initial_plane_config = | |
16010 | i9xx_get_initial_plane_config; | |
16011 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
16012 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
16013 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 16014 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 16015 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
16016 | dev_priv->display.get_initial_plane_config = |
16017 | i9xx_get_initial_plane_config; | |
d6dfee7a | 16018 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
16019 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
16020 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
16021 | } else { |
16022 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16023 | dev_priv->display.get_initial_plane_config = | |
16024 | i9xx_get_initial_plane_config; | |
16025 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
16026 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
16027 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 16028 | } |
e70236a8 | 16029 | |
e70236a8 | 16030 | /* Returns the core display clock speed */ |
88212941 | 16031 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
16032 | dev_priv->display.get_display_clock_speed = |
16033 | skylake_get_display_clock_speed; | |
88212941 | 16034 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
16035 | dev_priv->display.get_display_clock_speed = |
16036 | broxton_get_display_clock_speed; | |
88212941 | 16037 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
16038 | dev_priv->display.get_display_clock_speed = |
16039 | broadwell_get_display_clock_speed; | |
88212941 | 16040 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
16041 | dev_priv->display.get_display_clock_speed = |
16042 | haswell_get_display_clock_speed; | |
88212941 | 16043 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
16044 | dev_priv->display.get_display_clock_speed = |
16045 | valleyview_get_display_clock_speed; | |
88212941 | 16046 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
16047 | dev_priv->display.get_display_clock_speed = |
16048 | ilk_get_display_clock_speed; | |
88212941 ID |
16049 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
16050 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
16051 | dev_priv->display.get_display_clock_speed = |
16052 | i945_get_display_clock_speed; | |
88212941 | 16053 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
16054 | dev_priv->display.get_display_clock_speed = |
16055 | gm45_get_display_clock_speed; | |
88212941 | 16056 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
16057 | dev_priv->display.get_display_clock_speed = |
16058 | i965gm_get_display_clock_speed; | |
88212941 | 16059 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
16060 | dev_priv->display.get_display_clock_speed = |
16061 | pnv_get_display_clock_speed; | |
88212941 | 16062 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
16063 | dev_priv->display.get_display_clock_speed = |
16064 | g33_get_display_clock_speed; | |
88212941 | 16065 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
16066 | dev_priv->display.get_display_clock_speed = |
16067 | i915_get_display_clock_speed; | |
88212941 | 16068 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
16069 | dev_priv->display.get_display_clock_speed = |
16070 | i9xx_misc_get_display_clock_speed; | |
88212941 | 16071 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
16072 | dev_priv->display.get_display_clock_speed = |
16073 | i915gm_get_display_clock_speed; | |
88212941 | 16074 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
16075 | dev_priv->display.get_display_clock_speed = |
16076 | i865_get_display_clock_speed; | |
88212941 | 16077 | else if (IS_I85X(dev_priv)) |
e70236a8 | 16078 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 16079 | i85x_get_display_clock_speed; |
623e01e5 | 16080 | else { /* 830 */ |
88212941 | 16081 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
16082 | dev_priv->display.get_display_clock_speed = |
16083 | i830_get_display_clock_speed; | |
623e01e5 | 16084 | } |
e70236a8 | 16085 | |
88212941 | 16086 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 16087 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 16088 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 16089 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 16090 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
16091 | /* FIXME: detect B0+ stepping and use auto training */ |
16092 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 16093 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 16094 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
16095 | } |
16096 | ||
16097 | if (IS_BROADWELL(dev_priv)) { | |
16098 | dev_priv->display.modeset_commit_cdclk = | |
16099 | broadwell_modeset_commit_cdclk; | |
16100 | dev_priv->display.modeset_calc_cdclk = | |
16101 | broadwell_modeset_calc_cdclk; | |
88212941 | 16102 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
16103 | dev_priv->display.modeset_commit_cdclk = |
16104 | valleyview_modeset_commit_cdclk; | |
16105 | dev_priv->display.modeset_calc_cdclk = | |
16106 | valleyview_modeset_calc_cdclk; | |
88212941 | 16107 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed | 16108 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 16109 | bxt_modeset_commit_cdclk; |
27c329ed | 16110 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 16111 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
16112 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
16113 | dev_priv->display.modeset_commit_cdclk = | |
16114 | skl_modeset_commit_cdclk; | |
16115 | dev_priv->display.modeset_calc_cdclk = | |
16116 | skl_modeset_calc_cdclk; | |
e70236a8 | 16117 | } |
5a21b665 | 16118 | |
27082493 L |
16119 | if (dev_priv->info.gen >= 9) |
16120 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
16121 | else | |
16122 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
16123 | ||
5a21b665 DV |
16124 | switch (INTEL_INFO(dev_priv)->gen) { |
16125 | case 2: | |
16126 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
16127 | break; | |
16128 | ||
16129 | case 3: | |
16130 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
16131 | break; | |
16132 | ||
16133 | case 4: | |
16134 | case 5: | |
16135 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
16136 | break; | |
16137 | ||
16138 | case 6: | |
16139 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
16140 | break; | |
16141 | case 7: | |
16142 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
16143 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
16144 | break; | |
16145 | case 9: | |
16146 | /* Drop through - unsupported since execlist only. */ | |
16147 | default: | |
16148 | /* Default just returns -ENODEV to indicate unsupported */ | |
16149 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
16150 | } | |
e70236a8 JB |
16151 | } |
16152 | ||
b690e96c JB |
16153 | /* |
16154 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
16155 | * resume, or other times. This quirk makes sure that's the case for | |
16156 | * affected systems. | |
16157 | */ | |
0206e353 | 16158 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 16159 | { |
fac5e23e | 16160 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
16161 | |
16162 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 16163 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
16164 | } |
16165 | ||
b6b5d049 VS |
16166 | static void quirk_pipeb_force(struct drm_device *dev) |
16167 | { | |
fac5e23e | 16168 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
16169 | |
16170 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
16171 | DRM_INFO("applying pipe b force quirk\n"); | |
16172 | } | |
16173 | ||
435793df KP |
16174 | /* |
16175 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
16176 | */ | |
16177 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
16178 | { | |
fac5e23e | 16179 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 16180 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 16181 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
16182 | } |
16183 | ||
4dca20ef | 16184 | /* |
5a15ab5b CE |
16185 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
16186 | * brightness value | |
4dca20ef CE |
16187 | */ |
16188 | static void quirk_invert_brightness(struct drm_device *dev) | |
16189 | { | |
fac5e23e | 16190 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 16191 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 16192 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
16193 | } |
16194 | ||
9c72cc6f SD |
16195 | /* Some VBT's incorrectly indicate no backlight is present */ |
16196 | static void quirk_backlight_present(struct drm_device *dev) | |
16197 | { | |
fac5e23e | 16198 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
16199 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
16200 | DRM_INFO("applying backlight present quirk\n"); | |
16201 | } | |
16202 | ||
b690e96c JB |
16203 | struct intel_quirk { |
16204 | int device; | |
16205 | int subsystem_vendor; | |
16206 | int subsystem_device; | |
16207 | void (*hook)(struct drm_device *dev); | |
16208 | }; | |
16209 | ||
5f85f176 EE |
16210 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
16211 | struct intel_dmi_quirk { | |
16212 | void (*hook)(struct drm_device *dev); | |
16213 | const struct dmi_system_id (*dmi_id_list)[]; | |
16214 | }; | |
16215 | ||
16216 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
16217 | { | |
16218 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
16219 | return 1; | |
16220 | } | |
16221 | ||
16222 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
16223 | { | |
16224 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
16225 | { | |
16226 | .callback = intel_dmi_reverse_brightness, | |
16227 | .ident = "NCR Corporation", | |
16228 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
16229 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
16230 | }, | |
16231 | }, | |
16232 | { } /* terminating entry */ | |
16233 | }, | |
16234 | .hook = quirk_invert_brightness, | |
16235 | }, | |
16236 | }; | |
16237 | ||
c43b5634 | 16238 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
16239 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
16240 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
16241 | ||
b690e96c JB |
16242 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
16243 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
16244 | ||
5f080c0f VS |
16245 | /* 830 needs to leave pipe A & dpll A up */ |
16246 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
16247 | ||
b6b5d049 VS |
16248 | /* 830 needs to leave pipe B & dpll B up */ |
16249 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
16250 | ||
435793df KP |
16251 | /* Lenovo U160 cannot use SSC on LVDS */ |
16252 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
16253 | |
16254 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
16255 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 16256 | |
be505f64 AH |
16257 | /* Acer Aspire 5734Z must invert backlight brightness */ |
16258 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
16259 | ||
16260 | /* Acer/eMachines G725 */ | |
16261 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
16262 | ||
16263 | /* Acer/eMachines e725 */ | |
16264 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
16265 | ||
16266 | /* Acer/Packard Bell NCL20 */ | |
16267 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
16268 | ||
16269 | /* Acer Aspire 4736Z */ | |
16270 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
16271 | |
16272 | /* Acer Aspire 5336 */ | |
16273 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
16274 | |
16275 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
16276 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 16277 | |
dfb3d47b SD |
16278 | /* Acer C720 Chromebook (Core i3 4005U) */ |
16279 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
16280 | ||
b2a9601c | 16281 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
16282 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
16283 | ||
1b9448b0 JN |
16284 | /* Apple Macbook 4,1 */ |
16285 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
16286 | ||
d4967d8c SD |
16287 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
16288 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
16289 | |
16290 | /* HP Chromebook 14 (Celeron 2955U) */ | |
16291 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
16292 | |
16293 | /* Dell Chromebook 11 */ | |
16294 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
16295 | |
16296 | /* Dell Chromebook 11 (2015 version) */ | |
16297 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
16298 | }; |
16299 | ||
16300 | static void intel_init_quirks(struct drm_device *dev) | |
16301 | { | |
16302 | struct pci_dev *d = dev->pdev; | |
16303 | int i; | |
16304 | ||
16305 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
16306 | struct intel_quirk *q = &intel_quirks[i]; | |
16307 | ||
16308 | if (d->device == q->device && | |
16309 | (d->subsystem_vendor == q->subsystem_vendor || | |
16310 | q->subsystem_vendor == PCI_ANY_ID) && | |
16311 | (d->subsystem_device == q->subsystem_device || | |
16312 | q->subsystem_device == PCI_ANY_ID)) | |
16313 | q->hook(dev); | |
16314 | } | |
5f85f176 EE |
16315 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
16316 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
16317 | intel_dmi_quirks[i].hook(dev); | |
16318 | } | |
b690e96c JB |
16319 | } |
16320 | ||
9cce37f4 | 16321 | /* Disable the VGA plane that we never use */ |
29b74b7f | 16322 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 16323 | { |
52a05c30 | 16324 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 16325 | u8 sr1; |
920a14b2 | 16326 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 16327 | |
2b37c616 | 16328 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 16329 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 16330 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
16331 | sr1 = inb(VGA_SR_DATA); |
16332 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 16333 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
16334 | udelay(300); |
16335 | ||
01f5a626 | 16336 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
16337 | POSTING_READ(vga_reg); |
16338 | } | |
16339 | ||
f817586c DV |
16340 | void intel_modeset_init_hw(struct drm_device *dev) |
16341 | { | |
fac5e23e | 16342 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 16343 | |
4c75b940 | 16344 | intel_update_cdclk(dev_priv); |
1a617b77 ML |
16345 | |
16346 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
16347 | ||
46f16e63 | 16348 | intel_init_clock_gating(dev_priv); |
f817586c DV |
16349 | } |
16350 | ||
d93c0372 MR |
16351 | /* |
16352 | * Calculate what we think the watermarks should be for the state we've read | |
16353 | * out of the hardware and then immediately program those watermarks so that | |
16354 | * we ensure the hardware settings match our internal state. | |
16355 | * | |
16356 | * We can calculate what we think WM's should be by creating a duplicate of the | |
16357 | * current state (which was constructed during hardware readout) and running it | |
16358 | * through the atomic check code to calculate new watermark values in the | |
16359 | * state object. | |
16360 | */ | |
16361 | static void sanitize_watermarks(struct drm_device *dev) | |
16362 | { | |
16363 | struct drm_i915_private *dev_priv = to_i915(dev); | |
16364 | struct drm_atomic_state *state; | |
ccf010fb | 16365 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
16366 | struct drm_crtc *crtc; |
16367 | struct drm_crtc_state *cstate; | |
16368 | struct drm_modeset_acquire_ctx ctx; | |
16369 | int ret; | |
16370 | int i; | |
16371 | ||
16372 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 16373 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
16374 | return; |
16375 | ||
16376 | /* | |
16377 | * We need to hold connection_mutex before calling duplicate_state so | |
16378 | * that the connector loop is protected. | |
16379 | */ | |
16380 | drm_modeset_acquire_init(&ctx, 0); | |
16381 | retry: | |
0cd1262d | 16382 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
16383 | if (ret == -EDEADLK) { |
16384 | drm_modeset_backoff(&ctx); | |
16385 | goto retry; | |
16386 | } else if (WARN_ON(ret)) { | |
0cd1262d | 16387 | goto fail; |
d93c0372 MR |
16388 | } |
16389 | ||
16390 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
16391 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 16392 | goto fail; |
d93c0372 | 16393 | |
ccf010fb ML |
16394 | intel_state = to_intel_atomic_state(state); |
16395 | ||
ed4a6a7c MR |
16396 | /* |
16397 | * Hardware readout is the only time we don't want to calculate | |
16398 | * intermediate watermarks (since we don't trust the current | |
16399 | * watermarks). | |
16400 | */ | |
ccf010fb | 16401 | intel_state->skip_intermediate_wm = true; |
ed4a6a7c | 16402 | |
d93c0372 MR |
16403 | ret = intel_atomic_check(dev, state); |
16404 | if (ret) { | |
16405 | /* | |
16406 | * If we fail here, it means that the hardware appears to be | |
16407 | * programmed in a way that shouldn't be possible, given our | |
16408 | * understanding of watermark requirements. This might mean a | |
16409 | * mistake in the hardware readout code or a mistake in the | |
16410 | * watermark calculations for a given platform. Raise a WARN | |
16411 | * so that this is noticeable. | |
16412 | * | |
16413 | * If this actually happens, we'll have to just leave the | |
16414 | * BIOS-programmed watermarks untouched and hope for the best. | |
16415 | */ | |
16416 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 16417 | goto put_state; |
d93c0372 MR |
16418 | } |
16419 | ||
16420 | /* Write calculated watermark values back */ | |
d93c0372 MR |
16421 | for_each_crtc_in_state(state, crtc, cstate, i) { |
16422 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
16423 | ||
ed4a6a7c | 16424 | cs->wm.need_postvbl_update = true; |
ccf010fb | 16425 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
16426 | } |
16427 | ||
b9a1b717 | 16428 | put_state: |
0853695c | 16429 | drm_atomic_state_put(state); |
0cd1262d | 16430 | fail: |
d93c0372 MR |
16431 | drm_modeset_drop_locks(&ctx); |
16432 | drm_modeset_acquire_fini(&ctx); | |
16433 | } | |
16434 | ||
b079bd17 | 16435 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 16436 | { |
72e96d64 JL |
16437 | struct drm_i915_private *dev_priv = to_i915(dev); |
16438 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 16439 | enum pipe pipe; |
46f297fb | 16440 | struct intel_crtc *crtc; |
79e53945 JB |
16441 | |
16442 | drm_mode_config_init(dev); | |
16443 | ||
16444 | dev->mode_config.min_width = 0; | |
16445 | dev->mode_config.min_height = 0; | |
16446 | ||
019d96cb DA |
16447 | dev->mode_config.preferred_depth = 24; |
16448 | dev->mode_config.prefer_shadow = 1; | |
16449 | ||
25bab385 TU |
16450 | dev->mode_config.allow_fb_modifiers = true; |
16451 | ||
e6ecefaa | 16452 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 16453 | |
b690e96c JB |
16454 | intel_init_quirks(dev); |
16455 | ||
62d75df7 | 16456 | intel_init_pm(dev_priv); |
1fa61106 | 16457 | |
b7f05d4a | 16458 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 16459 | return 0; |
e3c74757 | 16460 | |
69f92f67 LW |
16461 | /* |
16462 | * There may be no VBT; and if the BIOS enabled SSC we can | |
16463 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
16464 | * BIOS isn't using it, don't assume it will work even if the VBT | |
16465 | * indicates as much. | |
16466 | */ | |
6e266956 | 16467 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
16468 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
16469 | DREF_SSC1_ENABLE); | |
16470 | ||
16471 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
16472 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
16473 | bios_lvds_use_ssc ? "en" : "dis", | |
16474 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
16475 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
16476 | } | |
16477 | } | |
16478 | ||
5db94019 | 16479 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
16480 | dev->mode_config.max_width = 2048; |
16481 | dev->mode_config.max_height = 2048; | |
5db94019 | 16482 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
16483 | dev->mode_config.max_width = 4096; |
16484 | dev->mode_config.max_height = 4096; | |
79e53945 | 16485 | } else { |
a6c45cf0 CW |
16486 | dev->mode_config.max_width = 8192; |
16487 | dev->mode_config.max_height = 8192; | |
79e53945 | 16488 | } |
068be561 | 16489 | |
50a0bc90 TU |
16490 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { |
16491 | dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512; | |
dc41c154 | 16492 | dev->mode_config.cursor_height = 1023; |
5db94019 | 16493 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
16494 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
16495 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
16496 | } else { | |
16497 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
16498 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
16499 | } | |
16500 | ||
72e96d64 | 16501 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 16502 | |
28c97730 | 16503 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
16504 | INTEL_INFO(dev_priv)->num_pipes, |
16505 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 16506 | |
055e393f | 16507 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
16508 | int ret; |
16509 | ||
5ab0d85b | 16510 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
16511 | if (ret) { |
16512 | drm_mode_config_cleanup(dev); | |
16513 | return ret; | |
16514 | } | |
79e53945 JB |
16515 | } |
16516 | ||
bfa7df01 | 16517 | intel_update_czclk(dev_priv); |
4c75b940 | 16518 | intel_update_cdclk(dev_priv); |
6a259b1f | 16519 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; |
bfa7df01 | 16520 | |
e72f9fbf | 16521 | intel_shared_dpll_init(dev); |
ee7b9f93 | 16522 | |
b2045352 | 16523 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 16524 | intel_update_max_cdclk(dev_priv); |
b2045352 | 16525 | |
9cce37f4 | 16526 | /* Just disable it once at startup */ |
29b74b7f | 16527 | i915_disable_vga(dev_priv); |
c39055b0 | 16528 | intel_setup_outputs(dev_priv); |
11be49eb | 16529 | |
6e9f798d | 16530 | drm_modeset_lock_all(dev); |
043e9bda | 16531 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 16532 | drm_modeset_unlock_all(dev); |
46f297fb | 16533 | |
d3fcc808 | 16534 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
16535 | struct intel_initial_plane_config plane_config = {}; |
16536 | ||
46f297fb JB |
16537 | if (!crtc->active) |
16538 | continue; | |
16539 | ||
46f297fb | 16540 | /* |
46f297fb JB |
16541 | * Note that reserving the BIOS fb up front prevents us |
16542 | * from stuffing other stolen allocations like the ring | |
16543 | * on top. This prevents some ugliness at boot time, and | |
16544 | * can even allow for smooth boot transitions if the BIOS | |
16545 | * fb is large enough for the active pipe configuration. | |
16546 | */ | |
eeebeac5 ML |
16547 | dev_priv->display.get_initial_plane_config(crtc, |
16548 | &plane_config); | |
16549 | ||
16550 | /* | |
16551 | * If the fb is shared between multiple heads, we'll | |
16552 | * just get the first one. | |
16553 | */ | |
16554 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 16555 | } |
d93c0372 MR |
16556 | |
16557 | /* | |
16558 | * Make sure hardware watermarks really match the state we read out. | |
16559 | * Note that we need to do this after reconstructing the BIOS fb's | |
16560 | * since the watermark calculation done here will use pstate->fb. | |
16561 | */ | |
16562 | sanitize_watermarks(dev); | |
b079bd17 VS |
16563 | |
16564 | return 0; | |
2c7111db CW |
16565 | } |
16566 | ||
7fad798e DV |
16567 | static void intel_enable_pipe_a(struct drm_device *dev) |
16568 | { | |
16569 | struct intel_connector *connector; | |
16570 | struct drm_connector *crt = NULL; | |
16571 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 16572 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
16573 | |
16574 | /* We can't just switch on the pipe A, we need to set things up with a | |
16575 | * proper mode and output configuration. As a gross hack, enable pipe A | |
16576 | * by enabling the load detect pipe once. */ | |
3a3371ff | 16577 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
16578 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
16579 | crt = &connector->base; | |
16580 | break; | |
16581 | } | |
16582 | } | |
16583 | ||
16584 | if (!crt) | |
16585 | return; | |
16586 | ||
208bf9fd | 16587 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 16588 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
16589 | } |
16590 | ||
fa555837 DV |
16591 | static bool |
16592 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
16593 | { | |
b7f05d4a | 16594 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 16595 | u32 val; |
fa555837 | 16596 | |
b7f05d4a | 16597 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
16598 | return true; |
16599 | ||
649636ef | 16600 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
16601 | |
16602 | if ((val & DISPLAY_PLANE_ENABLE) && | |
16603 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
16604 | return false; | |
16605 | ||
16606 | return true; | |
16607 | } | |
16608 | ||
02e93c35 VS |
16609 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
16610 | { | |
16611 | struct drm_device *dev = crtc->base.dev; | |
16612 | struct intel_encoder *encoder; | |
16613 | ||
16614 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
16615 | return true; | |
16616 | ||
16617 | return false; | |
16618 | } | |
16619 | ||
496b0fc3 ML |
16620 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
16621 | { | |
16622 | struct drm_device *dev = encoder->base.dev; | |
16623 | struct intel_connector *connector; | |
16624 | ||
16625 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
16626 | return connector; | |
16627 | ||
16628 | return NULL; | |
16629 | } | |
16630 | ||
a168f5b3 VS |
16631 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
16632 | enum transcoder pch_transcoder) | |
16633 | { | |
16634 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
16635 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
16636 | } | |
16637 | ||
24929352 DV |
16638 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
16639 | { | |
16640 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 16641 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 16642 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 16643 | |
24929352 | 16644 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
16645 | if (!transcoder_is_dsi(cpu_transcoder)) { |
16646 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
16647 | ||
16648 | I915_WRITE(reg, | |
16649 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
16650 | } | |
24929352 | 16651 | |
d3eaf884 | 16652 | /* restore vblank interrupts to correct state */ |
9625604c | 16653 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 16654 | if (crtc->active) { |
f9cd7b88 VS |
16655 | struct intel_plane *plane; |
16656 | ||
9625604c | 16657 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
16658 | |
16659 | /* Disable everything but the primary plane */ | |
16660 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
16661 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
16662 | continue; | |
16663 | ||
16664 | plane->disable_plane(&plane->base, &crtc->base); | |
16665 | } | |
9625604c | 16666 | } |
d3eaf884 | 16667 | |
24929352 | 16668 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
16669 | * disable the crtc (and hence change the state) if it is wrong. Note |
16670 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 16671 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
16672 | bool plane; |
16673 | ||
78108b7c VS |
16674 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
16675 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
16676 | |
16677 | /* Pipe has the wrong plane attached and the plane is active. | |
16678 | * Temporarily change the plane mapping and disable everything | |
16679 | * ... */ | |
16680 | plane = crtc->plane; | |
936e71e3 | 16681 | to_intel_plane_state(crtc->base.primary->state)->base.visible = true; |
24929352 | 16682 | crtc->plane = !plane; |
b17d48e2 | 16683 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16684 | crtc->plane = plane; |
24929352 | 16685 | } |
24929352 | 16686 | |
7fad798e DV |
16687 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
16688 | crtc->pipe == PIPE_A && !crtc->active) { | |
16689 | /* BIOS forgot to enable pipe A, this mostly happens after | |
16690 | * resume. Force-enable the pipe to fix this, the update_dpms | |
16691 | * call below we restore the pipe to the right state, but leave | |
16692 | * the required bits on. */ | |
16693 | intel_enable_pipe_a(dev); | |
16694 | } | |
16695 | ||
24929352 DV |
16696 | /* Adjust the state of the output pipe according to whether we |
16697 | * have active connectors/encoders. */ | |
842e0307 | 16698 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 16699 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16700 | |
49cff963 | 16701 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
16702 | /* |
16703 | * We start out with underrun reporting disabled to avoid races. | |
16704 | * For correct bookkeeping mark this on active crtcs. | |
16705 | * | |
c5ab3bc0 DV |
16706 | * Also on gmch platforms we dont have any hardware bits to |
16707 | * disable the underrun reporting. Which means we need to start | |
16708 | * out with underrun reporting disabled also on inactive pipes, | |
16709 | * since otherwise we'll complain about the garbage we read when | |
16710 | * e.g. coming up after runtime pm. | |
16711 | * | |
4cc31489 DV |
16712 | * No protection against concurrent access is required - at |
16713 | * worst a fifo underrun happens which also sets this to false. | |
16714 | */ | |
16715 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
16716 | /* |
16717 | * We track the PCH trancoder underrun reporting state | |
16718 | * within the crtc. With crtc for pipe A housing the underrun | |
16719 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
16720 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
16721 | * and marking underrun reporting as disabled for the non-existing | |
16722 | * PCH transcoders B and C would prevent enabling the south | |
16723 | * error interrupt (see cpt_can_enable_serr_int()). | |
16724 | */ | |
16725 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
16726 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 16727 | } |
24929352 DV |
16728 | } |
16729 | ||
16730 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
16731 | { | |
16732 | struct intel_connector *connector; | |
24929352 DV |
16733 | |
16734 | /* We need to check both for a crtc link (meaning that the | |
16735 | * encoder is active and trying to read from a pipe) and the | |
16736 | * pipe itself being active. */ | |
16737 | bool has_active_crtc = encoder->base.crtc && | |
16738 | to_intel_crtc(encoder->base.crtc)->active; | |
16739 | ||
496b0fc3 ML |
16740 | connector = intel_encoder_find_connector(encoder); |
16741 | if (connector && !has_active_crtc) { | |
24929352 DV |
16742 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
16743 | encoder->base.base.id, | |
8e329a03 | 16744 | encoder->base.name); |
24929352 DV |
16745 | |
16746 | /* Connector is active, but has no active pipe. This is | |
16747 | * fallout from our resume register restoring. Disable | |
16748 | * the encoder manually again. */ | |
16749 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
16750 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
16751 | ||
24929352 DV |
16752 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
16753 | encoder->base.base.id, | |
8e329a03 | 16754 | encoder->base.name); |
fd6bbda9 | 16755 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 16756 | if (encoder->post_disable) |
fd6bbda9 | 16757 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 16758 | } |
7f1950fb | 16759 | encoder->base.crtc = NULL; |
24929352 DV |
16760 | |
16761 | /* Inconsistent output/port/pipe state happens presumably due to | |
16762 | * a bug in one of the get_hw_state functions. Or someplace else | |
16763 | * in our code, like the register restore mess on resume. Clamp | |
16764 | * things to off as a safer default. */ | |
fd6bbda9 ML |
16765 | |
16766 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16767 | connector->base.encoder = NULL; | |
24929352 DV |
16768 | } |
16769 | /* Enabled encoders without active connectors will be fixed in | |
16770 | * the crtc fixup. */ | |
16771 | } | |
16772 | ||
29b74b7f | 16773 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 16774 | { |
920a14b2 | 16775 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 16776 | |
04098753 ID |
16777 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
16778 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 16779 | i915_disable_vga(dev_priv); |
04098753 ID |
16780 | } |
16781 | } | |
16782 | ||
29b74b7f | 16783 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 16784 | { |
8dc8a27c PZ |
16785 | /* This function can be called both from intel_modeset_setup_hw_state or |
16786 | * at a very early point in our resume sequence, where the power well | |
16787 | * structures are not yet restored. Since this function is at a very | |
16788 | * paranoid "someone might have enabled VGA while we were not looking" | |
16789 | * level, just check if the power well is enabled instead of trying to | |
16790 | * follow the "don't touch the power well if we don't need it" policy | |
16791 | * the rest of the driver uses. */ | |
6392f847 | 16792 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
16793 | return; |
16794 | ||
29b74b7f | 16795 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
16796 | |
16797 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
16798 | } |
16799 | ||
f9cd7b88 | 16800 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 16801 | { |
f9cd7b88 | 16802 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 16803 | |
f9cd7b88 | 16804 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
16805 | } |
16806 | ||
f9cd7b88 VS |
16807 | /* FIXME read out full plane state for all planes */ |
16808 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 16809 | { |
b26d3ea3 | 16810 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 16811 | struct intel_plane_state *plane_state = |
b26d3ea3 | 16812 | to_intel_plane_state(primary->state); |
d032ffa0 | 16813 | |
936e71e3 | 16814 | plane_state->base.visible = crtc->active && |
b26d3ea3 ML |
16815 | primary_get_hw_state(to_intel_plane(primary)); |
16816 | ||
936e71e3 | 16817 | if (plane_state->base.visible) |
b26d3ea3 | 16818 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); |
98ec7739 VS |
16819 | } |
16820 | ||
30e984df | 16821 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 16822 | { |
fac5e23e | 16823 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 16824 | enum pipe pipe; |
24929352 DV |
16825 | struct intel_crtc *crtc; |
16826 | struct intel_encoder *encoder; | |
16827 | struct intel_connector *connector; | |
5358901f | 16828 | int i; |
24929352 | 16829 | |
565602d7 ML |
16830 | dev_priv->active_crtcs = 0; |
16831 | ||
d3fcc808 | 16832 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
16833 | struct intel_crtc_state *crtc_state = crtc->config; |
16834 | int pixclk = 0; | |
3b117c8f | 16835 | |
ec2dc6a0 | 16836 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
16837 | memset(crtc_state, 0, sizeof(*crtc_state)); |
16838 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 16839 | |
565602d7 ML |
16840 | crtc_state->base.active = crtc_state->base.enable = |
16841 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
16842 | ||
16843 | crtc->base.enabled = crtc_state->base.enable; | |
16844 | crtc->active = crtc_state->base.active; | |
16845 | ||
16846 | if (crtc_state->base.active) { | |
16847 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
16848 | ||
c89e39f3 | 16849 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 16850 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 16851 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
16852 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
16853 | else | |
16854 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
16855 | |
16856 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
16857 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
16858 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
16859 | } |
16860 | ||
16861 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 16862 | |
f9cd7b88 | 16863 | readout_plane_state(crtc); |
24929352 | 16864 | |
78108b7c VS |
16865 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
16866 | crtc->base.base.id, crtc->base.name, | |
08c4d7fc | 16867 | enableddisabled(crtc->active)); |
24929352 DV |
16868 | } |
16869 | ||
5358901f DV |
16870 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16871 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16872 | ||
2edd6443 ACO |
16873 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16874 | &pll->config.hw_state); | |
3e369b76 | 16875 | pll->config.crtc_mask = 0; |
d3fcc808 | 16876 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16877 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16878 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16879 | } |
2dd66ebd | 16880 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16881 | |
1e6f2ddc | 16882 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16883 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16884 | } |
16885 | ||
b2784e15 | 16886 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16887 | pipe = 0; |
16888 | ||
16889 | if (encoder->get_hw_state(encoder, &pipe)) { | |
98187836 | 16890 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 16891 | |
045ac3b5 | 16892 | encoder->base.crtc = &crtc->base; |
253c84c8 | 16893 | crtc->config->output_types |= 1 << encoder->type; |
6e3c9717 | 16894 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16895 | } else { |
16896 | encoder->base.crtc = NULL; | |
16897 | } | |
16898 | ||
6f2bcceb | 16899 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
16900 | encoder->base.base.id, encoder->base.name, |
16901 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 16902 | pipe_name(pipe)); |
24929352 DV |
16903 | } |
16904 | ||
3a3371ff | 16905 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16906 | if (connector->get_hw_state(connector)) { |
16907 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16908 | |
16909 | encoder = connector->encoder; | |
16910 | connector->base.encoder = &encoder->base; | |
16911 | ||
16912 | if (encoder->base.crtc && | |
16913 | encoder->base.crtc->state->active) { | |
16914 | /* | |
16915 | * This has to be done during hardware readout | |
16916 | * because anything calling .crtc_disable may | |
16917 | * rely on the connector_mask being accurate. | |
16918 | */ | |
16919 | encoder->base.crtc->state->connector_mask |= | |
16920 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16921 | encoder->base.crtc->state->encoder_mask |= |
16922 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16923 | } |
16924 | ||
24929352 DV |
16925 | } else { |
16926 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16927 | connector->base.encoder = NULL; | |
16928 | } | |
16929 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
16930 | connector->base.base.id, connector->base.name, |
16931 | enableddisabled(connector->base.encoder)); | |
24929352 | 16932 | } |
7f4c6284 VS |
16933 | |
16934 | for_each_intel_crtc(dev, crtc) { | |
16935 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16936 | ||
16937 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16938 | if (crtc->base.state->active) { | |
16939 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16940 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16941 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16942 | ||
16943 | /* | |
16944 | * The initial mode needs to be set in order to keep | |
16945 | * the atomic core happy. It wants a valid mode if the | |
16946 | * crtc's enabled, so we do the above call. | |
16947 | * | |
16948 | * At this point some state updated by the connectors | |
16949 | * in their ->detect() callback has not run yet, so | |
16950 | * no recalculation can be done yet. | |
16951 | * | |
16952 | * Even if we could do a recalculation and modeset | |
16953 | * right now it would cause a double modeset if | |
16954 | * fbdev or userspace chooses a different initial mode. | |
16955 | * | |
16956 | * If that happens, someone indicated they wanted a | |
16957 | * mode change, which means it's safe to do a full | |
16958 | * recalculation. | |
16959 | */ | |
16960 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16961 | |
16962 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16963 | update_scanline_offset(crtc); | |
7f4c6284 | 16964 | } |
e3b247da VS |
16965 | |
16966 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16967 | } |
30e984df DV |
16968 | } |
16969 | ||
043e9bda ML |
16970 | /* Scan out the current hw modeset state, |
16971 | * and sanitizes it to the current state | |
16972 | */ | |
16973 | static void | |
16974 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 16975 | { |
fac5e23e | 16976 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 16977 | enum pipe pipe; |
30e984df DV |
16978 | struct intel_crtc *crtc; |
16979 | struct intel_encoder *encoder; | |
35c95375 | 16980 | int i; |
30e984df DV |
16981 | |
16982 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16983 | |
16984 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16985 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16986 | intel_sanitize_encoder(encoder); |
16987 | } | |
16988 | ||
055e393f | 16989 | for_each_pipe(dev_priv, pipe) { |
98187836 | 16990 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 16991 | |
24929352 | 16992 | intel_sanitize_crtc(crtc); |
6e3c9717 ACO |
16993 | intel_dump_pipe_config(crtc, crtc->config, |
16994 | "[setup_hw_state]"); | |
24929352 | 16995 | } |
9a935856 | 16996 | |
d29b2f9d ACO |
16997 | intel_modeset_update_connector_atomic_state(dev); |
16998 | ||
35c95375 DV |
16999 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
17000 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
17001 | ||
2dd66ebd | 17002 | if (!pll->on || pll->active_mask) |
35c95375 DV |
17003 | continue; |
17004 | ||
17005 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
17006 | ||
2edd6443 | 17007 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
17008 | pll->on = false; |
17009 | } | |
17010 | ||
920a14b2 | 17011 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6eb1a681 | 17012 | vlv_wm_get_hw_state(dev); |
5db94019 | 17013 | else if (IS_GEN9(dev_priv)) |
3078999f | 17014 | skl_wm_get_hw_state(dev); |
6e266956 | 17015 | else if (HAS_PCH_SPLIT(dev_priv)) |
243e6a44 | 17016 | ilk_wm_get_hw_state(dev); |
292b990e ML |
17017 | |
17018 | for_each_intel_crtc(dev, crtc) { | |
17019 | unsigned long put_domains; | |
17020 | ||
74bff5f9 | 17021 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
17022 | if (WARN_ON(put_domains)) |
17023 | modeset_put_power_domains(dev_priv, put_domains); | |
17024 | } | |
17025 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
17026 | |
17027 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 17028 | } |
7d0bc1ea | 17029 | |
043e9bda ML |
17030 | void intel_display_resume(struct drm_device *dev) |
17031 | { | |
e2c8b870 ML |
17032 | struct drm_i915_private *dev_priv = to_i915(dev); |
17033 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
17034 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 17035 | int ret; |
f30da187 | 17036 | |
e2c8b870 | 17037 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
17038 | if (state) |
17039 | state->acquire_ctx = &ctx; | |
043e9bda | 17040 | |
ea49c9ac ML |
17041 | /* |
17042 | * This is a cludge because with real atomic modeset mode_config.mutex | |
17043 | * won't be taken. Unfortunately some probed state like | |
17044 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
17045 | * it here for now. | |
17046 | */ | |
17047 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 17048 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 17049 | |
73974893 ML |
17050 | while (1) { |
17051 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
17052 | if (ret != -EDEADLK) | |
17053 | break; | |
043e9bda | 17054 | |
e2c8b870 | 17055 | drm_modeset_backoff(&ctx); |
e2c8b870 | 17056 | } |
043e9bda | 17057 | |
73974893 ML |
17058 | if (!ret) |
17059 | ret = __intel_display_resume(dev, state); | |
17060 | ||
e2c8b870 ML |
17061 | drm_modeset_drop_locks(&ctx); |
17062 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 17063 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 17064 | |
0853695c | 17065 | if (ret) |
e2c8b870 | 17066 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
0853695c | 17067 | drm_atomic_state_put(state); |
2c7111db CW |
17068 | } |
17069 | ||
17070 | void intel_modeset_gem_init(struct drm_device *dev) | |
17071 | { | |
dc97997a | 17072 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 17073 | struct drm_crtc *c; |
2ff8fde1 | 17074 | struct drm_i915_gem_object *obj; |
484b41dd | 17075 | |
dc97997a | 17076 | intel_init_gt_powersave(dev_priv); |
ae48434c | 17077 | |
1833b134 | 17078 | intel_modeset_init_hw(dev); |
02e792fb | 17079 | |
1ee8da6d | 17080 | intel_setup_overlay(dev_priv); |
484b41dd JB |
17081 | |
17082 | /* | |
17083 | * Make sure any fbs we allocated at startup are properly | |
17084 | * pinned & fenced. When we do the allocation it's too early | |
17085 | * for this. | |
17086 | */ | |
70e1e0ec | 17087 | for_each_crtc(dev, c) { |
058d88c4 CW |
17088 | struct i915_vma *vma; |
17089 | ||
2ff8fde1 MR |
17090 | obj = intel_fb_obj(c->primary->fb); |
17091 | if (obj == NULL) | |
484b41dd JB |
17092 | continue; |
17093 | ||
e0d6149b | 17094 | mutex_lock(&dev->struct_mutex); |
058d88c4 | 17095 | vma = intel_pin_and_fence_fb_obj(c->primary->fb, |
3465c580 | 17096 | c->primary->state->rotation); |
e0d6149b | 17097 | mutex_unlock(&dev->struct_mutex); |
058d88c4 | 17098 | if (IS_ERR(vma)) { |
484b41dd JB |
17099 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
17100 | to_intel_crtc(c)->pipe); | |
66e514c1 | 17101 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 17102 | c->primary->fb = NULL; |
36750f28 | 17103 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 17104 | update_state_fb(c->primary); |
36750f28 | 17105 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
17106 | } |
17107 | } | |
1ebaa0b9 CW |
17108 | } |
17109 | ||
17110 | int intel_connector_register(struct drm_connector *connector) | |
17111 | { | |
17112 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
17113 | int ret; | |
17114 | ||
17115 | ret = intel_backlight_device_register(intel_connector); | |
17116 | if (ret) | |
17117 | goto err; | |
17118 | ||
17119 | return 0; | |
0962c3c9 | 17120 | |
1ebaa0b9 CW |
17121 | err: |
17122 | return ret; | |
79e53945 JB |
17123 | } |
17124 | ||
c191eca1 | 17125 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 17126 | { |
e63d87c0 | 17127 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 17128 | |
e63d87c0 | 17129 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 17130 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
17131 | } |
17132 | ||
79e53945 JB |
17133 | void intel_modeset_cleanup(struct drm_device *dev) |
17134 | { | |
fac5e23e | 17135 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 17136 | |
dc97997a | 17137 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 17138 | |
fd0c0642 DV |
17139 | /* |
17140 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 17141 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
17142 | * experience fancy races otherwise. |
17143 | */ | |
2aeb7d3a | 17144 | intel_irq_uninstall(dev_priv); |
eb21b92b | 17145 | |
fd0c0642 DV |
17146 | /* |
17147 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
17148 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
17149 | */ | |
f87ea761 | 17150 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 17151 | |
723bfd70 JB |
17152 | intel_unregister_dsm_handler(); |
17153 | ||
c937ab3e | 17154 | intel_fbc_global_disable(dev_priv); |
69341a5e | 17155 | |
1630fe75 CW |
17156 | /* flush any delayed tasks or pending work */ |
17157 | flush_scheduled_work(); | |
17158 | ||
79e53945 | 17159 | drm_mode_config_cleanup(dev); |
4d7bb011 | 17160 | |
1ee8da6d | 17161 | intel_cleanup_overlay(dev_priv); |
ae48434c | 17162 | |
dc97997a | 17163 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
17164 | |
17165 | intel_teardown_gmbus(dev); | |
79e53945 JB |
17166 | } |
17167 | ||
df0e9248 CW |
17168 | void intel_connector_attach_encoder(struct intel_connector *connector, |
17169 | struct intel_encoder *encoder) | |
17170 | { | |
17171 | connector->encoder = encoder; | |
17172 | drm_mode_connector_attach_encoder(&connector->base, | |
17173 | &encoder->base); | |
79e53945 | 17174 | } |
28d52043 DA |
17175 | |
17176 | /* | |
17177 | * set vga decode state - true == enable VGA decode | |
17178 | */ | |
6315b5d3 | 17179 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 17180 | { |
6315b5d3 | 17181 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
17182 | u16 gmch_ctrl; |
17183 | ||
75fa041d CW |
17184 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
17185 | DRM_ERROR("failed to read control word\n"); | |
17186 | return -EIO; | |
17187 | } | |
17188 | ||
c0cc8a55 CW |
17189 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
17190 | return 0; | |
17191 | ||
28d52043 DA |
17192 | if (state) |
17193 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
17194 | else | |
17195 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
17196 | |
17197 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
17198 | DRM_ERROR("failed to write control word\n"); | |
17199 | return -EIO; | |
17200 | } | |
17201 | ||
28d52043 DA |
17202 | return 0; |
17203 | } | |
c4a1d9e4 | 17204 | |
98a2f411 CW |
17205 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
17206 | ||
c4a1d9e4 | 17207 | struct intel_display_error_state { |
ff57f1b0 PZ |
17208 | |
17209 | u32 power_well_driver; | |
17210 | ||
63b66e5b CW |
17211 | int num_transcoders; |
17212 | ||
c4a1d9e4 CW |
17213 | struct intel_cursor_error_state { |
17214 | u32 control; | |
17215 | u32 position; | |
17216 | u32 base; | |
17217 | u32 size; | |
52331309 | 17218 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
17219 | |
17220 | struct intel_pipe_error_state { | |
ddf9c536 | 17221 | bool power_domain_on; |
c4a1d9e4 | 17222 | u32 source; |
f301b1e1 | 17223 | u32 stat; |
52331309 | 17224 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
17225 | |
17226 | struct intel_plane_error_state { | |
17227 | u32 control; | |
17228 | u32 stride; | |
17229 | u32 size; | |
17230 | u32 pos; | |
17231 | u32 addr; | |
17232 | u32 surface; | |
17233 | u32 tile_offset; | |
52331309 | 17234 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
17235 | |
17236 | struct intel_transcoder_error_state { | |
ddf9c536 | 17237 | bool power_domain_on; |
63b66e5b CW |
17238 | enum transcoder cpu_transcoder; |
17239 | ||
17240 | u32 conf; | |
17241 | ||
17242 | u32 htotal; | |
17243 | u32 hblank; | |
17244 | u32 hsync; | |
17245 | u32 vtotal; | |
17246 | u32 vblank; | |
17247 | u32 vsync; | |
17248 | } transcoder[4]; | |
c4a1d9e4 CW |
17249 | }; |
17250 | ||
17251 | struct intel_display_error_state * | |
c033666a | 17252 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 17253 | { |
c4a1d9e4 | 17254 | struct intel_display_error_state *error; |
63b66e5b CW |
17255 | int transcoders[] = { |
17256 | TRANSCODER_A, | |
17257 | TRANSCODER_B, | |
17258 | TRANSCODER_C, | |
17259 | TRANSCODER_EDP, | |
17260 | }; | |
c4a1d9e4 CW |
17261 | int i; |
17262 | ||
c033666a | 17263 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
17264 | return NULL; |
17265 | ||
9d1cb914 | 17266 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
17267 | if (error == NULL) |
17268 | return NULL; | |
17269 | ||
c033666a | 17270 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
17271 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
17272 | ||
055e393f | 17273 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 17274 | error->pipe[i].power_domain_on = |
f458ebbc DV |
17275 | __intel_display_power_is_enabled(dev_priv, |
17276 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 17277 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
17278 | continue; |
17279 | ||
5efb3e28 VS |
17280 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
17281 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
17282 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
17283 | |
17284 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
17285 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 17286 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 17287 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
17288 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
17289 | } | |
c033666a | 17290 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 17291 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 17292 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
17293 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
17294 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
17295 | } | |
17296 | ||
c4a1d9e4 | 17297 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 17298 | |
c033666a | 17299 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 17300 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
17301 | } |
17302 | ||
4d1de975 | 17303 | /* Note: this does not include DSI transcoders. */ |
c033666a | 17304 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 17305 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
17306 | error->num_transcoders++; /* Account for eDP. */ |
17307 | ||
17308 | for (i = 0; i < error->num_transcoders; i++) { | |
17309 | enum transcoder cpu_transcoder = transcoders[i]; | |
17310 | ||
ddf9c536 | 17311 | error->transcoder[i].power_domain_on = |
f458ebbc | 17312 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 17313 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 17314 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
17315 | continue; |
17316 | ||
63b66e5b CW |
17317 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
17318 | ||
17319 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
17320 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
17321 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
17322 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
17323 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
17324 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
17325 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
17326 | } |
17327 | ||
17328 | return error; | |
17329 | } | |
17330 | ||
edc3d884 MK |
17331 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
17332 | ||
c4a1d9e4 | 17333 | void |
edc3d884 | 17334 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
5f56d5f9 | 17335 | struct drm_i915_private *dev_priv, |
c4a1d9e4 CW |
17336 | struct intel_display_error_state *error) |
17337 | { | |
17338 | int i; | |
17339 | ||
63b66e5b CW |
17340 | if (!error) |
17341 | return; | |
17342 | ||
b7f05d4a | 17343 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 17344 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 17345 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 17346 | error->power_well_driver); |
055e393f | 17347 | for_each_pipe(dev_priv, i) { |
edc3d884 | 17348 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 17349 | err_printf(m, " Power: %s\n", |
87ad3212 | 17350 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 17351 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 17352 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
17353 | |
17354 | err_printf(m, "Plane [%d]:\n", i); | |
17355 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
17356 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 17357 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
17358 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
17359 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 17360 | } |
772c2a51 | 17361 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 17362 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 17363 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
17364 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
17365 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
17366 | } |
17367 | ||
edc3d884 MK |
17368 | err_printf(m, "Cursor [%d]:\n", i); |
17369 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
17370 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
17371 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 17372 | } |
63b66e5b CW |
17373 | |
17374 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 17375 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 17376 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 17377 | err_printf(m, " Power: %s\n", |
87ad3212 | 17378 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
17379 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
17380 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
17381 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
17382 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
17383 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
17384 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
17385 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
17386 | } | |
c4a1d9e4 | 17387 | } |
98a2f411 CW |
17388 | |
17389 | #endif |