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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
db18b6a6 | 39 | #include "intel_dsi.h" |
e5510fac | 40 | #include "i915_trace.h" |
319c1d42 | 41 | #include <drm/drm_atomic.h> |
c196e1d6 | 42 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
43 | #include <drm/drm_dp_helper.h> |
44 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
45 | #include <drm/drm_plane_helper.h> |
46 | #include <drm/drm_rect.h> | |
c0f372b3 | 47 | #include <linux/dma_remapping.h> |
fd8e058a AG |
48 | #include <linux/reservation.h> |
49 | #include <linux/dma-buf.h> | |
79e53945 | 50 | |
465c120c | 51 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 52 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
53 | DRM_FORMAT_C8, |
54 | DRM_FORMAT_RGB565, | |
465c120c | 55 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 56 | DRM_FORMAT_XRGB8888, |
465c120c MR |
57 | }; |
58 | ||
59 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 60 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
61 | DRM_FORMAT_C8, |
62 | DRM_FORMAT_RGB565, | |
63 | DRM_FORMAT_XRGB8888, | |
64 | DRM_FORMAT_XBGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_XBGR2101010, | |
67 | }; | |
68 | ||
69 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
70 | DRM_FORMAT_C8, |
71 | DRM_FORMAT_RGB565, | |
72 | DRM_FORMAT_XRGB8888, | |
465c120c | 73 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 74 | DRM_FORMAT_ARGB8888, |
465c120c MR |
75 | DRM_FORMAT_ABGR8888, |
76 | DRM_FORMAT_XRGB2101010, | |
465c120c | 77 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
78 | DRM_FORMAT_YUYV, |
79 | DRM_FORMAT_YVYU, | |
80 | DRM_FORMAT_UYVY, | |
81 | DRM_FORMAT_VYUY, | |
465c120c MR |
82 | }; |
83 | ||
3d7d6510 MR |
84 | /* Cursor formats */ |
85 | static const uint32_t intel_cursor_formats[] = { | |
86 | DRM_FORMAT_ARGB8888, | |
87 | }; | |
88 | ||
f1f644dc | 89 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 90 | struct intel_crtc_state *pipe_config); |
18442d08 | 91 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 92 | struct intel_crtc_state *pipe_config); |
f1f644dc | 93 | |
eb1bfe80 JB |
94 | static int intel_framebuffer_init(struct drm_device *dev, |
95 | struct intel_framebuffer *ifb, | |
96 | struct drm_mode_fb_cmd2 *mode_cmd, | |
97 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
98 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
99 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 100 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
102 | struct intel_link_m_n *m_n, |
103 | struct intel_link_m_n *m2_n2); | |
29407aab | 104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 106 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 107 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
d288f65f | 109 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 110 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
111 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
112 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
113 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
114 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 119 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 120 | |
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
bfa7df01 VS |
136 | /* returns HPLL frequency in kHz */ |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
c30fec65 VS |
150 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
151 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
152 | { |
153 | u32 val; | |
154 | int divider; | |
155 | ||
bfa7df01 VS |
156 | mutex_lock(&dev_priv->sb_lock); |
157 | val = vlv_cck_read(dev_priv, reg); | |
158 | mutex_unlock(&dev_priv->sb_lock); | |
159 | ||
160 | divider = val & CCK_FREQUENCY_VALUES; | |
161 | ||
162 | WARN((val & CCK_FREQUENCY_STATUS) != | |
163 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
164 | "%s change in progress\n", name); | |
165 | ||
c30fec65 VS |
166 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
167 | } | |
168 | ||
169 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
170 | const char *name, u32 reg) | |
171 | { | |
172 | if (dev_priv->hpll_freq == 0) | |
173 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
174 | ||
175 | return vlv_get_cck_clock(dev_priv, name, reg, | |
176 | dev_priv->hpll_freq); | |
bfa7df01 VS |
177 | } |
178 | ||
e7dc33f3 VS |
179 | static int |
180 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 181 | { |
e7dc33f3 VS |
182 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
183 | } | |
d2acd215 | 184 | |
e7dc33f3 VS |
185 | static int |
186 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
187 | { | |
35d38d1f VS |
188 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
189 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
190 | } |
191 | ||
e7dc33f3 VS |
192 | static int |
193 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 194 | { |
79e50a4f JN |
195 | uint32_t clkcfg; |
196 | ||
e7dc33f3 | 197 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
198 | clkcfg = I915_READ(CLKCFG); |
199 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
200 | case CLKCFG_FSB_400: | |
e7dc33f3 | 201 | return 100000; |
79e50a4f | 202 | case CLKCFG_FSB_533: |
e7dc33f3 | 203 | return 133333; |
79e50a4f | 204 | case CLKCFG_FSB_667: |
e7dc33f3 | 205 | return 166667; |
79e50a4f | 206 | case CLKCFG_FSB_800: |
e7dc33f3 | 207 | return 200000; |
79e50a4f | 208 | case CLKCFG_FSB_1067: |
e7dc33f3 | 209 | return 266667; |
79e50a4f | 210 | case CLKCFG_FSB_1333: |
e7dc33f3 | 211 | return 333333; |
79e50a4f JN |
212 | /* these two are just a guess; one of them might be right */ |
213 | case CLKCFG_FSB_1600: | |
214 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 215 | return 400000; |
79e50a4f | 216 | default: |
e7dc33f3 | 217 | return 133333; |
79e50a4f JN |
218 | } |
219 | } | |
220 | ||
e7dc33f3 VS |
221 | static void intel_update_rawclk(struct drm_i915_private *dev_priv) |
222 | { | |
223 | if (HAS_PCH_SPLIT(dev_priv)) | |
224 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
225 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
226 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
227 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
228 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
229 | else | |
230 | return; /* no rawclk on other platforms, or no need to know it */ | |
231 | ||
232 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
233 | } | |
234 | ||
bfa7df01 VS |
235 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
236 | { | |
666a4537 | 237 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
238 | return; |
239 | ||
240 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
241 | CCK_CZ_CLOCK_CONTROL); | |
242 | ||
243 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
244 | } | |
245 | ||
021357ac | 246 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
247 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
248 | const struct intel_crtc_state *pipe_config) | |
021357ac | 249 | { |
21a727b3 VS |
250 | if (HAS_DDI(dev_priv)) |
251 | return pipe_config->port_clock; /* SPLL */ | |
252 | else if (IS_GEN5(dev_priv)) | |
253 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 254 | else |
21a727b3 | 255 | return 270000; |
021357ac CW |
256 | } |
257 | ||
5d536e28 | 258 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 259 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 260 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 261 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
262 | .m = { .min = 96, .max = 140 }, |
263 | .m1 = { .min = 18, .max = 26 }, | |
264 | .m2 = { .min = 6, .max = 16 }, | |
265 | .p = { .min = 4, .max = 128 }, | |
266 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
267 | .p2 = { .dot_limit = 165000, |
268 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
269 | }; |
270 | ||
5d536e28 DV |
271 | static const intel_limit_t intel_limits_i8xx_dvo = { |
272 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 273 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 274 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
275 | .m = { .min = 96, .max = 140 }, |
276 | .m1 = { .min = 18, .max = 26 }, | |
277 | .m2 = { .min = 6, .max = 16 }, | |
278 | .p = { .min = 4, .max = 128 }, | |
279 | .p1 = { .min = 2, .max = 33 }, | |
280 | .p2 = { .dot_limit = 165000, | |
281 | .p2_slow = 4, .p2_fast = 4 }, | |
282 | }; | |
283 | ||
e4b36699 | 284 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 285 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 286 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 287 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
288 | .m = { .min = 96, .max = 140 }, |
289 | .m1 = { .min = 18, .max = 26 }, | |
290 | .m2 = { .min = 6, .max = 16 }, | |
291 | .p = { .min = 4, .max = 128 }, | |
292 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
293 | .p2 = { .dot_limit = 165000, |
294 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 295 | }; |
273e27ca | 296 | |
e4b36699 | 297 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
298 | .dot = { .min = 20000, .max = 400000 }, |
299 | .vco = { .min = 1400000, .max = 2800000 }, | |
300 | .n = { .min = 1, .max = 6 }, | |
301 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
302 | .m1 = { .min = 8, .max = 18 }, |
303 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
304 | .p = { .min = 5, .max = 80 }, |
305 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
306 | .p2 = { .dot_limit = 200000, |
307 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
308 | }; |
309 | ||
310 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
311 | .dot = { .min = 20000, .max = 400000 }, |
312 | .vco = { .min = 1400000, .max = 2800000 }, | |
313 | .n = { .min = 1, .max = 6 }, | |
314 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
315 | .m1 = { .min = 8, .max = 18 }, |
316 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
317 | .p = { .min = 7, .max = 98 }, |
318 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
319 | .p2 = { .dot_limit = 112000, |
320 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
321 | }; |
322 | ||
273e27ca | 323 | |
e4b36699 | 324 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
325 | .dot = { .min = 25000, .max = 270000 }, |
326 | .vco = { .min = 1750000, .max = 3500000}, | |
327 | .n = { .min = 1, .max = 4 }, | |
328 | .m = { .min = 104, .max = 138 }, | |
329 | .m1 = { .min = 17, .max = 23 }, | |
330 | .m2 = { .min = 5, .max = 11 }, | |
331 | .p = { .min = 10, .max = 30 }, | |
332 | .p1 = { .min = 1, .max = 3}, | |
333 | .p2 = { .dot_limit = 270000, | |
334 | .p2_slow = 10, | |
335 | .p2_fast = 10 | |
044c7c41 | 336 | }, |
e4b36699 KP |
337 | }; |
338 | ||
339 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
340 | .dot = { .min = 22000, .max = 400000 }, |
341 | .vco = { .min = 1750000, .max = 3500000}, | |
342 | .n = { .min = 1, .max = 4 }, | |
343 | .m = { .min = 104, .max = 138 }, | |
344 | .m1 = { .min = 16, .max = 23 }, | |
345 | .m2 = { .min = 5, .max = 11 }, | |
346 | .p = { .min = 5, .max = 80 }, | |
347 | .p1 = { .min = 1, .max = 8}, | |
348 | .p2 = { .dot_limit = 165000, | |
349 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
350 | }; |
351 | ||
352 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
353 | .dot = { .min = 20000, .max = 115000 }, |
354 | .vco = { .min = 1750000, .max = 3500000 }, | |
355 | .n = { .min = 1, .max = 3 }, | |
356 | .m = { .min = 104, .max = 138 }, | |
357 | .m1 = { .min = 17, .max = 23 }, | |
358 | .m2 = { .min = 5, .max = 11 }, | |
359 | .p = { .min = 28, .max = 112 }, | |
360 | .p1 = { .min = 2, .max = 8 }, | |
361 | .p2 = { .dot_limit = 0, | |
362 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 363 | }, |
e4b36699 KP |
364 | }; |
365 | ||
366 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
367 | .dot = { .min = 80000, .max = 224000 }, |
368 | .vco = { .min = 1750000, .max = 3500000 }, | |
369 | .n = { .min = 1, .max = 3 }, | |
370 | .m = { .min = 104, .max = 138 }, | |
371 | .m1 = { .min = 17, .max = 23 }, | |
372 | .m2 = { .min = 5, .max = 11 }, | |
373 | .p = { .min = 14, .max = 42 }, | |
374 | .p1 = { .min = 2, .max = 6 }, | |
375 | .p2 = { .dot_limit = 0, | |
376 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 377 | }, |
e4b36699 KP |
378 | }; |
379 | ||
f2b115e6 | 380 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
381 | .dot = { .min = 20000, .max = 400000}, |
382 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 383 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
384 | .n = { .min = 3, .max = 6 }, |
385 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 386 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
387 | .m1 = { .min = 0, .max = 0 }, |
388 | .m2 = { .min = 0, .max = 254 }, | |
389 | .p = { .min = 5, .max = 80 }, | |
390 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
391 | .p2 = { .dot_limit = 200000, |
392 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
393 | }; |
394 | ||
f2b115e6 | 395 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
396 | .dot = { .min = 20000, .max = 400000 }, |
397 | .vco = { .min = 1700000, .max = 3500000 }, | |
398 | .n = { .min = 3, .max = 6 }, | |
399 | .m = { .min = 2, .max = 256 }, | |
400 | .m1 = { .min = 0, .max = 0 }, | |
401 | .m2 = { .min = 0, .max = 254 }, | |
402 | .p = { .min = 7, .max = 112 }, | |
403 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
404 | .p2 = { .dot_limit = 112000, |
405 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
406 | }; |
407 | ||
273e27ca EA |
408 | /* Ironlake / Sandybridge |
409 | * | |
410 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
411 | * the range value for them is (actual_value - 2). | |
412 | */ | |
b91ad0ec | 413 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
414 | .dot = { .min = 25000, .max = 350000 }, |
415 | .vco = { .min = 1760000, .max = 3510000 }, | |
416 | .n = { .min = 1, .max = 5 }, | |
417 | .m = { .min = 79, .max = 127 }, | |
418 | .m1 = { .min = 12, .max = 22 }, | |
419 | .m2 = { .min = 5, .max = 9 }, | |
420 | .p = { .min = 5, .max = 80 }, | |
421 | .p1 = { .min = 1, .max = 8 }, | |
422 | .p2 = { .dot_limit = 225000, | |
423 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
424 | }; |
425 | ||
b91ad0ec | 426 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
427 | .dot = { .min = 25000, .max = 350000 }, |
428 | .vco = { .min = 1760000, .max = 3510000 }, | |
429 | .n = { .min = 1, .max = 3 }, | |
430 | .m = { .min = 79, .max = 118 }, | |
431 | .m1 = { .min = 12, .max = 22 }, | |
432 | .m2 = { .min = 5, .max = 9 }, | |
433 | .p = { .min = 28, .max = 112 }, | |
434 | .p1 = { .min = 2, .max = 8 }, | |
435 | .p2 = { .dot_limit = 225000, | |
436 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
437 | }; |
438 | ||
439 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
440 | .dot = { .min = 25000, .max = 350000 }, |
441 | .vco = { .min = 1760000, .max = 3510000 }, | |
442 | .n = { .min = 1, .max = 3 }, | |
443 | .m = { .min = 79, .max = 127 }, | |
444 | .m1 = { .min = 12, .max = 22 }, | |
445 | .m2 = { .min = 5, .max = 9 }, | |
446 | .p = { .min = 14, .max = 56 }, | |
447 | .p1 = { .min = 2, .max = 8 }, | |
448 | .p2 = { .dot_limit = 225000, | |
449 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
450 | }; |
451 | ||
273e27ca | 452 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 453 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
454 | .dot = { .min = 25000, .max = 350000 }, |
455 | .vco = { .min = 1760000, .max = 3510000 }, | |
456 | .n = { .min = 1, .max = 2 }, | |
457 | .m = { .min = 79, .max = 126 }, | |
458 | .m1 = { .min = 12, .max = 22 }, | |
459 | .m2 = { .min = 5, .max = 9 }, | |
460 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 461 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
462 | .p2 = { .dot_limit = 225000, |
463 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
464 | }; |
465 | ||
466 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
467 | .dot = { .min = 25000, .max = 350000 }, |
468 | .vco = { .min = 1760000, .max = 3510000 }, | |
469 | .n = { .min = 1, .max = 3 }, | |
470 | .m = { .min = 79, .max = 126 }, | |
471 | .m1 = { .min = 12, .max = 22 }, | |
472 | .m2 = { .min = 5, .max = 9 }, | |
473 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 474 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
475 | .p2 = { .dot_limit = 225000, |
476 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
477 | }; |
478 | ||
dc730512 | 479 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
480 | /* |
481 | * These are the data rate limits (measured in fast clocks) | |
482 | * since those are the strictest limits we have. The fast | |
483 | * clock and actual rate limits are more relaxed, so checking | |
484 | * them would make no difference. | |
485 | */ | |
486 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 487 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 488 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
489 | .m1 = { .min = 2, .max = 3 }, |
490 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 491 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 492 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
493 | }; |
494 | ||
ef9348c8 CML |
495 | static const intel_limit_t intel_limits_chv = { |
496 | /* | |
497 | * These are the data rate limits (measured in fast clocks) | |
498 | * since those are the strictest limits we have. The fast | |
499 | * clock and actual rate limits are more relaxed, so checking | |
500 | * them would make no difference. | |
501 | */ | |
502 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 503 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
504 | .n = { .min = 1, .max = 1 }, |
505 | .m1 = { .min = 2, .max = 2 }, | |
506 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
507 | .p1 = { .min = 2, .max = 4 }, | |
508 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
509 | }; | |
510 | ||
5ab7b0b7 ID |
511 | static const intel_limit_t intel_limits_bxt = { |
512 | /* FIXME: find real dot limits */ | |
513 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 514 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
515 | .n = { .min = 1, .max = 1 }, |
516 | .m1 = { .min = 2, .max = 2 }, | |
517 | /* FIXME: find real m2 limits */ | |
518 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
519 | .p1 = { .min = 2, .max = 4 }, | |
520 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
521 | }; | |
522 | ||
cdba954e ACO |
523 | static bool |
524 | needs_modeset(struct drm_crtc_state *state) | |
525 | { | |
fc596660 | 526 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
527 | } |
528 | ||
e0638cdf PZ |
529 | /** |
530 | * Returns whether any output on the specified pipe is of the specified type | |
531 | */ | |
4093561b | 532 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 533 | { |
409ee761 | 534 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
535 | struct intel_encoder *encoder; |
536 | ||
409ee761 | 537 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
538 | if (encoder->type == type) |
539 | return true; | |
540 | ||
541 | return false; | |
542 | } | |
543 | ||
d0737e1d ACO |
544 | /** |
545 | * Returns whether any output on the specified pipe will have the specified | |
546 | * type after a staged modeset is complete, i.e., the same as | |
547 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
548 | * encoder->crtc. | |
549 | */ | |
a93e255f ACO |
550 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
551 | int type) | |
d0737e1d | 552 | { |
a93e255f | 553 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 554 | struct drm_connector *connector; |
a93e255f | 555 | struct drm_connector_state *connector_state; |
d0737e1d | 556 | struct intel_encoder *encoder; |
a93e255f ACO |
557 | int i, num_connectors = 0; |
558 | ||
da3ced29 | 559 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
560 | if (connector_state->crtc != crtc_state->base.crtc) |
561 | continue; | |
562 | ||
563 | num_connectors++; | |
d0737e1d | 564 | |
a93e255f ACO |
565 | encoder = to_intel_encoder(connector_state->best_encoder); |
566 | if (encoder->type == type) | |
d0737e1d | 567 | return true; |
a93e255f ACO |
568 | } |
569 | ||
570 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
571 | |
572 | return false; | |
573 | } | |
574 | ||
dccbea3b ID |
575 | /* |
576 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
577 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
578 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
579 | * The helpers' return value is the rate of the clock that is fed to the | |
580 | * display engine's pipe which can be the above fast dot clock rate or a | |
581 | * divided-down version of it. | |
582 | */ | |
f2b115e6 | 583 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 584 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 585 | { |
2177832f SL |
586 | clock->m = clock->m2 + 2; |
587 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 588 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 589 | return 0; |
fb03ac01 VS |
590 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
591 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
592 | |
593 | return clock->dot; | |
2177832f SL |
594 | } |
595 | ||
7429e9d4 DV |
596 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
597 | { | |
598 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
599 | } | |
600 | ||
dccbea3b | 601 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 602 | { |
7429e9d4 | 603 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 604 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 605 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 606 | return 0; |
fb03ac01 VS |
607 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
608 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
609 | |
610 | return clock->dot; | |
79e53945 JB |
611 | } |
612 | ||
dccbea3b | 613 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
614 | { |
615 | clock->m = clock->m1 * clock->m2; | |
616 | clock->p = clock->p1 * clock->p2; | |
617 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 618 | return 0; |
589eca67 ID |
619 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
620 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
621 | |
622 | return clock->dot / 5; | |
589eca67 ID |
623 | } |
624 | ||
dccbea3b | 625 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
626 | { |
627 | clock->m = clock->m1 * clock->m2; | |
628 | clock->p = clock->p1 * clock->p2; | |
629 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 630 | return 0; |
ef9348c8 CML |
631 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
632 | clock->n << 22); | |
633 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
634 | |
635 | return clock->dot / 5; | |
ef9348c8 CML |
636 | } |
637 | ||
7c04d1d9 | 638 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
639 | /** |
640 | * Returns whether the given set of divisors are valid for a given refclk with | |
641 | * the given connectors. | |
642 | */ | |
643 | ||
1b894b59 CW |
644 | static bool intel_PLL_is_valid(struct drm_device *dev, |
645 | const intel_limit_t *limit, | |
646 | const intel_clock_t *clock) | |
79e53945 | 647 | { |
f01b7962 VS |
648 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
649 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 650 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 651 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 652 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 653 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 654 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 655 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 656 | |
666a4537 WB |
657 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
658 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
659 | if (clock->m1 <= clock->m2) |
660 | INTELPllInvalid("m1 <= m2\n"); | |
661 | ||
666a4537 | 662 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
663 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
664 | INTELPllInvalid("p out of range\n"); | |
665 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
666 | INTELPllInvalid("m out of range\n"); | |
667 | } | |
668 | ||
79e53945 | 669 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 670 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
671 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
672 | * connector, etc., rather than just a single range. | |
673 | */ | |
674 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 675 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
676 | |
677 | return true; | |
678 | } | |
679 | ||
3b1429d9 VS |
680 | static int |
681 | i9xx_select_p2_div(const intel_limit_t *limit, | |
682 | const struct intel_crtc_state *crtc_state, | |
683 | int target) | |
79e53945 | 684 | { |
3b1429d9 | 685 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 686 | |
a93e255f | 687 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 688 | /* |
a210b028 DV |
689 | * For LVDS just rely on its current settings for dual-channel. |
690 | * We haven't figured out how to reliably set up different | |
691 | * single/dual channel state, if we even can. | |
79e53945 | 692 | */ |
1974cad0 | 693 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 694 | return limit->p2.p2_fast; |
79e53945 | 695 | else |
3b1429d9 | 696 | return limit->p2.p2_slow; |
79e53945 JB |
697 | } else { |
698 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 699 | return limit->p2.p2_slow; |
79e53945 | 700 | else |
3b1429d9 | 701 | return limit->p2.p2_fast; |
79e53945 | 702 | } |
3b1429d9 VS |
703 | } |
704 | ||
70e8aa21 ACO |
705 | /* |
706 | * Returns a set of divisors for the desired target clock with the given | |
707 | * refclk, or FALSE. The returned values represent the clock equation: | |
708 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
709 | * | |
710 | * Target and reference clocks are specified in kHz. | |
711 | * | |
712 | * If match_clock is provided, then best_clock P divider must match the P | |
713 | * divider from @match_clock used for LVDS downclocking. | |
714 | */ | |
3b1429d9 VS |
715 | static bool |
716 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
717 | struct intel_crtc_state *crtc_state, | |
718 | int target, int refclk, intel_clock_t *match_clock, | |
719 | intel_clock_t *best_clock) | |
720 | { | |
721 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
722 | intel_clock_t clock; | |
723 | int err = target; | |
79e53945 | 724 | |
0206e353 | 725 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 726 | |
3b1429d9 VS |
727 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
728 | ||
42158660 ZY |
729 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
730 | clock.m1++) { | |
731 | for (clock.m2 = limit->m2.min; | |
732 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 733 | if (clock.m2 >= clock.m1) |
42158660 ZY |
734 | break; |
735 | for (clock.n = limit->n.min; | |
736 | clock.n <= limit->n.max; clock.n++) { | |
737 | for (clock.p1 = limit->p1.min; | |
738 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
739 | int this_err; |
740 | ||
dccbea3b | 741 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
742 | if (!intel_PLL_is_valid(dev, limit, |
743 | &clock)) | |
744 | continue; | |
745 | if (match_clock && | |
746 | clock.p != match_clock->p) | |
747 | continue; | |
748 | ||
749 | this_err = abs(clock.dot - target); | |
750 | if (this_err < err) { | |
751 | *best_clock = clock; | |
752 | err = this_err; | |
753 | } | |
754 | } | |
755 | } | |
756 | } | |
757 | } | |
758 | ||
759 | return (err != target); | |
760 | } | |
761 | ||
70e8aa21 ACO |
762 | /* |
763 | * Returns a set of divisors for the desired target clock with the given | |
764 | * refclk, or FALSE. The returned values represent the clock equation: | |
765 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
766 | * | |
767 | * Target and reference clocks are specified in kHz. | |
768 | * | |
769 | * If match_clock is provided, then best_clock P divider must match the P | |
770 | * divider from @match_clock used for LVDS downclocking. | |
771 | */ | |
ac58c3f0 | 772 | static bool |
a93e255f ACO |
773 | pnv_find_best_dpll(const intel_limit_t *limit, |
774 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
775 | int target, int refclk, intel_clock_t *match_clock, |
776 | intel_clock_t *best_clock) | |
79e53945 | 777 | { |
3b1429d9 | 778 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 779 | intel_clock_t clock; |
79e53945 JB |
780 | int err = target; |
781 | ||
0206e353 | 782 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 783 | |
3b1429d9 VS |
784 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
785 | ||
42158660 ZY |
786 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
787 | clock.m1++) { | |
788 | for (clock.m2 = limit->m2.min; | |
789 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
790 | for (clock.n = limit->n.min; |
791 | clock.n <= limit->n.max; clock.n++) { | |
792 | for (clock.p1 = limit->p1.min; | |
793 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
794 | int this_err; |
795 | ||
dccbea3b | 796 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
797 | if (!intel_PLL_is_valid(dev, limit, |
798 | &clock)) | |
79e53945 | 799 | continue; |
cec2f356 SP |
800 | if (match_clock && |
801 | clock.p != match_clock->p) | |
802 | continue; | |
79e53945 JB |
803 | |
804 | this_err = abs(clock.dot - target); | |
805 | if (this_err < err) { | |
806 | *best_clock = clock; | |
807 | err = this_err; | |
808 | } | |
809 | } | |
810 | } | |
811 | } | |
812 | } | |
813 | ||
814 | return (err != target); | |
815 | } | |
816 | ||
997c030c ACO |
817 | /* |
818 | * Returns a set of divisors for the desired target clock with the given | |
819 | * refclk, or FALSE. The returned values represent the clock equation: | |
820 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
821 | * |
822 | * Target and reference clocks are specified in kHz. | |
823 | * | |
824 | * If match_clock is provided, then best_clock P divider must match the P | |
825 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 826 | */ |
d4906093 | 827 | static bool |
a93e255f ACO |
828 | g4x_find_best_dpll(const intel_limit_t *limit, |
829 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
830 | int target, int refclk, intel_clock_t *match_clock, |
831 | intel_clock_t *best_clock) | |
d4906093 | 832 | { |
3b1429d9 | 833 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
834 | intel_clock_t clock; |
835 | int max_n; | |
3b1429d9 | 836 | bool found = false; |
6ba770dc AJ |
837 | /* approximately equals target * 0.00585 */ |
838 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
839 | |
840 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
841 | |
842 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
843 | ||
d4906093 | 844 | max_n = limit->n.max; |
f77f13e2 | 845 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 846 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 847 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
848 | for (clock.m1 = limit->m1.max; |
849 | clock.m1 >= limit->m1.min; clock.m1--) { | |
850 | for (clock.m2 = limit->m2.max; | |
851 | clock.m2 >= limit->m2.min; clock.m2--) { | |
852 | for (clock.p1 = limit->p1.max; | |
853 | clock.p1 >= limit->p1.min; clock.p1--) { | |
854 | int this_err; | |
855 | ||
dccbea3b | 856 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
857 | if (!intel_PLL_is_valid(dev, limit, |
858 | &clock)) | |
d4906093 | 859 | continue; |
1b894b59 CW |
860 | |
861 | this_err = abs(clock.dot - target); | |
d4906093 ML |
862 | if (this_err < err_most) { |
863 | *best_clock = clock; | |
864 | err_most = this_err; | |
865 | max_n = clock.n; | |
866 | found = true; | |
867 | } | |
868 | } | |
869 | } | |
870 | } | |
871 | } | |
2c07245f ZW |
872 | return found; |
873 | } | |
874 | ||
d5dd62bd ID |
875 | /* |
876 | * Check if the calculated PLL configuration is more optimal compared to the | |
877 | * best configuration and error found so far. Return the calculated error. | |
878 | */ | |
879 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
880 | const intel_clock_t *calculated_clock, | |
881 | const intel_clock_t *best_clock, | |
882 | unsigned int best_error_ppm, | |
883 | unsigned int *error_ppm) | |
884 | { | |
9ca3ba01 ID |
885 | /* |
886 | * For CHV ignore the error and consider only the P value. | |
887 | * Prefer a bigger P value based on HW requirements. | |
888 | */ | |
889 | if (IS_CHERRYVIEW(dev)) { | |
890 | *error_ppm = 0; | |
891 | ||
892 | return calculated_clock->p > best_clock->p; | |
893 | } | |
894 | ||
24be4e46 ID |
895 | if (WARN_ON_ONCE(!target_freq)) |
896 | return false; | |
897 | ||
d5dd62bd ID |
898 | *error_ppm = div_u64(1000000ULL * |
899 | abs(target_freq - calculated_clock->dot), | |
900 | target_freq); | |
901 | /* | |
902 | * Prefer a better P value over a better (smaller) error if the error | |
903 | * is small. Ensure this preference for future configurations too by | |
904 | * setting the error to 0. | |
905 | */ | |
906 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
907 | *error_ppm = 0; | |
908 | ||
909 | return true; | |
910 | } | |
911 | ||
912 | return *error_ppm + 10 < best_error_ppm; | |
913 | } | |
914 | ||
65b3d6a9 ACO |
915 | /* |
916 | * Returns a set of divisors for the desired target clock with the given | |
917 | * refclk, or FALSE. The returned values represent the clock equation: | |
918 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
919 | */ | |
a0c4da24 | 920 | static bool |
a93e255f ACO |
921 | vlv_find_best_dpll(const intel_limit_t *limit, |
922 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
923 | int target, int refclk, intel_clock_t *match_clock, |
924 | intel_clock_t *best_clock) | |
a0c4da24 | 925 | { |
a93e255f | 926 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 927 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 928 | intel_clock_t clock; |
69e4f900 | 929 | unsigned int bestppm = 1000000; |
27e639bf VS |
930 | /* min update 19.2 MHz */ |
931 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 932 | bool found = false; |
a0c4da24 | 933 | |
6b4bf1c4 VS |
934 | target *= 5; /* fast clock */ |
935 | ||
936 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
937 | |
938 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 939 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 940 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 941 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 942 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 943 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 944 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 945 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 946 | unsigned int ppm; |
69e4f900 | 947 | |
6b4bf1c4 VS |
948 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
949 | refclk * clock.m1); | |
950 | ||
dccbea3b | 951 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 952 | |
f01b7962 VS |
953 | if (!intel_PLL_is_valid(dev, limit, |
954 | &clock)) | |
43b0ac53 VS |
955 | continue; |
956 | ||
d5dd62bd ID |
957 | if (!vlv_PLL_is_optimal(dev, target, |
958 | &clock, | |
959 | best_clock, | |
960 | bestppm, &ppm)) | |
961 | continue; | |
6b4bf1c4 | 962 | |
d5dd62bd ID |
963 | *best_clock = clock; |
964 | bestppm = ppm; | |
965 | found = true; | |
a0c4da24 JB |
966 | } |
967 | } | |
968 | } | |
969 | } | |
a0c4da24 | 970 | |
49e497ef | 971 | return found; |
a0c4da24 | 972 | } |
a4fc5ed6 | 973 | |
65b3d6a9 ACO |
974 | /* |
975 | * Returns a set of divisors for the desired target clock with the given | |
976 | * refclk, or FALSE. The returned values represent the clock equation: | |
977 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
978 | */ | |
ef9348c8 | 979 | static bool |
a93e255f ACO |
980 | chv_find_best_dpll(const intel_limit_t *limit, |
981 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
982 | int target, int refclk, intel_clock_t *match_clock, |
983 | intel_clock_t *best_clock) | |
984 | { | |
a93e255f | 985 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 986 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 987 | unsigned int best_error_ppm; |
ef9348c8 CML |
988 | intel_clock_t clock; |
989 | uint64_t m2; | |
990 | int found = false; | |
991 | ||
992 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 993 | best_error_ppm = 1000000; |
ef9348c8 CML |
994 | |
995 | /* | |
996 | * Based on hardware doc, the n always set to 1, and m1 always | |
997 | * set to 2. If requires to support 200Mhz refclk, we need to | |
998 | * revisit this because n may not 1 anymore. | |
999 | */ | |
1000 | clock.n = 1, clock.m1 = 2; | |
1001 | target *= 5; /* fast clock */ | |
1002 | ||
1003 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1004 | for (clock.p2 = limit->p2.p2_fast; | |
1005 | clock.p2 >= limit->p2.p2_slow; | |
1006 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1007 | unsigned int error_ppm; |
ef9348c8 CML |
1008 | |
1009 | clock.p = clock.p1 * clock.p2; | |
1010 | ||
1011 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1012 | clock.n) << 22, refclk * clock.m1); | |
1013 | ||
1014 | if (m2 > INT_MAX/clock.m1) | |
1015 | continue; | |
1016 | ||
1017 | clock.m2 = m2; | |
1018 | ||
dccbea3b | 1019 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1020 | |
1021 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1022 | continue; | |
1023 | ||
9ca3ba01 ID |
1024 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1025 | best_error_ppm, &error_ppm)) | |
1026 | continue; | |
1027 | ||
1028 | *best_clock = clock; | |
1029 | best_error_ppm = error_ppm; | |
1030 | found = true; | |
ef9348c8 CML |
1031 | } |
1032 | } | |
1033 | ||
1034 | return found; | |
1035 | } | |
1036 | ||
5ab7b0b7 ID |
1037 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1038 | intel_clock_t *best_clock) | |
1039 | { | |
65b3d6a9 ACO |
1040 | int refclk = 100000; |
1041 | const intel_limit_t *limit = &intel_limits_bxt; | |
5ab7b0b7 | 1042 | |
65b3d6a9 | 1043 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1044 | target_clock, refclk, NULL, best_clock); |
1045 | } | |
1046 | ||
20ddf665 VS |
1047 | bool intel_crtc_active(struct drm_crtc *crtc) |
1048 | { | |
1049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1050 | ||
1051 | /* Be paranoid as we can arrive here with only partial | |
1052 | * state retrieved from the hardware during setup. | |
1053 | * | |
241bfc38 | 1054 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1055 | * as Haswell has gained clock readout/fastboot support. |
1056 | * | |
66e514c1 | 1057 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1058 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1059 | * |
1060 | * FIXME: The intel_crtc->active here should be switched to | |
1061 | * crtc->state->active once we have proper CRTC states wired up | |
1062 | * for atomic. | |
20ddf665 | 1063 | */ |
c3d1f436 | 1064 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1065 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1066 | } |
1067 | ||
a5c961d1 PZ |
1068 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1069 | enum pipe pipe) | |
1070 | { | |
1071 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1073 | ||
6e3c9717 | 1074 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1075 | } |
1076 | ||
fbf49ea2 VS |
1077 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1078 | { | |
1079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1080 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1081 | u32 line1, line2; |
1082 | u32 line_mask; | |
1083 | ||
1084 | if (IS_GEN2(dev)) | |
1085 | line_mask = DSL_LINEMASK_GEN2; | |
1086 | else | |
1087 | line_mask = DSL_LINEMASK_GEN3; | |
1088 | ||
1089 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1090 | msleep(5); |
fbf49ea2 VS |
1091 | line2 = I915_READ(reg) & line_mask; |
1092 | ||
1093 | return line1 == line2; | |
1094 | } | |
1095 | ||
ab7ad7f6 KP |
1096 | /* |
1097 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1098 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1099 | * |
1100 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1101 | * spinning on the vblank interrupt status bit, since we won't actually | |
1102 | * see an interrupt when the pipe is disabled. | |
1103 | * | |
ab7ad7f6 KP |
1104 | * On Gen4 and above: |
1105 | * wait for the pipe register state bit to turn off | |
1106 | * | |
1107 | * Otherwise: | |
1108 | * wait for the display line value to settle (it usually | |
1109 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1110 | * |
9d0498a2 | 1111 | */ |
575f7ab7 | 1112 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1113 | { |
575f7ab7 | 1114 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1115 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1116 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1117 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1118 | |
1119 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1120 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1121 | |
1122 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1123 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1124 | 100)) | |
284637d9 | 1125 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1126 | } else { |
ab7ad7f6 | 1127 | /* Wait for the display line to settle */ |
fbf49ea2 | 1128 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1129 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1130 | } |
79e53945 JB |
1131 | } |
1132 | ||
b24e7179 | 1133 | /* Only for pre-ILK configs */ |
55607e8a DV |
1134 | void assert_pll(struct drm_i915_private *dev_priv, |
1135 | enum pipe pipe, bool state) | |
b24e7179 | 1136 | { |
b24e7179 JB |
1137 | u32 val; |
1138 | bool cur_state; | |
1139 | ||
649636ef | 1140 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1141 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1142 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1143 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1144 | onoff(state), onoff(cur_state)); |
b24e7179 | 1145 | } |
b24e7179 | 1146 | |
23538ef1 | 1147 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1148 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1149 | { |
1150 | u32 val; | |
1151 | bool cur_state; | |
1152 | ||
a580516d | 1153 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1154 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1155 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1156 | |
1157 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1158 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1159 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1160 | onoff(state), onoff(cur_state)); |
23538ef1 | 1161 | } |
23538ef1 | 1162 | |
040484af JB |
1163 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1164 | enum pipe pipe, bool state) | |
1165 | { | |
040484af | 1166 | bool cur_state; |
ad80a810 PZ |
1167 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1168 | pipe); | |
040484af | 1169 | |
2d1fe073 | 1170 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1171 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1172 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1173 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1174 | } else { |
649636ef | 1175 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1176 | cur_state = !!(val & FDI_TX_ENABLE); |
1177 | } | |
e2c719b7 | 1178 | I915_STATE_WARN(cur_state != state, |
040484af | 1179 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1180 | onoff(state), onoff(cur_state)); |
040484af JB |
1181 | } |
1182 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1183 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1184 | ||
1185 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1186 | enum pipe pipe, bool state) | |
1187 | { | |
040484af JB |
1188 | u32 val; |
1189 | bool cur_state; | |
1190 | ||
649636ef | 1191 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1192 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1193 | I915_STATE_WARN(cur_state != state, |
040484af | 1194 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1195 | onoff(state), onoff(cur_state)); |
040484af JB |
1196 | } |
1197 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1198 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1199 | ||
1200 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1201 | enum pipe pipe) | |
1202 | { | |
040484af JB |
1203 | u32 val; |
1204 | ||
1205 | /* ILK FDI PLL is always enabled */ | |
2d1fe073 | 1206 | if (INTEL_INFO(dev_priv)->gen == 5) |
040484af JB |
1207 | return; |
1208 | ||
bf507ef7 | 1209 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1210 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1211 | return; |
1212 | ||
649636ef | 1213 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1214 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1215 | } |
1216 | ||
55607e8a DV |
1217 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1218 | enum pipe pipe, bool state) | |
040484af | 1219 | { |
040484af | 1220 | u32 val; |
55607e8a | 1221 | bool cur_state; |
040484af | 1222 | |
649636ef | 1223 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1224 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1225 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1226 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1227 | onoff(state), onoff(cur_state)); |
040484af JB |
1228 | } |
1229 | ||
b680c37a DV |
1230 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1231 | enum pipe pipe) | |
ea0760cf | 1232 | { |
bedd4dba | 1233 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1234 | i915_reg_t pp_reg; |
ea0760cf JB |
1235 | u32 val; |
1236 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1237 | bool locked = true; |
ea0760cf | 1238 | |
bedd4dba JN |
1239 | if (WARN_ON(HAS_DDI(dev))) |
1240 | return; | |
1241 | ||
1242 | if (HAS_PCH_SPLIT(dev)) { | |
1243 | u32 port_sel; | |
1244 | ||
ea0760cf | 1245 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1246 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1247 | ||
1248 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1249 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1250 | panel_pipe = PIPE_B; | |
1251 | /* XXX: else fix for eDP */ | |
666a4537 | 1252 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1253 | /* presumably write lock depends on pipe, not port select */ |
1254 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1255 | panel_pipe = pipe; | |
ea0760cf JB |
1256 | } else { |
1257 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1258 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1259 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1260 | } |
1261 | ||
1262 | val = I915_READ(pp_reg); | |
1263 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1264 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1265 | locked = false; |
1266 | ||
e2c719b7 | 1267 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1268 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1269 | pipe_name(pipe)); |
ea0760cf JB |
1270 | } |
1271 | ||
93ce0ba6 JN |
1272 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1273 | enum pipe pipe, bool state) | |
1274 | { | |
1275 | struct drm_device *dev = dev_priv->dev; | |
1276 | bool cur_state; | |
1277 | ||
d9d82081 | 1278 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1279 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1280 | else |
5efb3e28 | 1281 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1282 | |
e2c719b7 | 1283 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1284 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1285 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1286 | } |
1287 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1288 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1289 | ||
b840d907 JB |
1290 | void assert_pipe(struct drm_i915_private *dev_priv, |
1291 | enum pipe pipe, bool state) | |
b24e7179 | 1292 | { |
63d7bbe9 | 1293 | bool cur_state; |
702e7a56 PZ |
1294 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1295 | pipe); | |
4feed0eb | 1296 | enum intel_display_power_domain power_domain; |
b24e7179 | 1297 | |
b6b5d049 VS |
1298 | /* if we need the pipe quirk it must be always on */ |
1299 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1300 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1301 | state = true; |
1302 | ||
4feed0eb ID |
1303 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1304 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1305 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1306 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1307 | |
1308 | intel_display_power_put(dev_priv, power_domain); | |
1309 | } else { | |
1310 | cur_state = false; | |
69310161 PZ |
1311 | } |
1312 | ||
e2c719b7 | 1313 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1314 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1315 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1316 | } |
1317 | ||
931872fc CW |
1318 | static void assert_plane(struct drm_i915_private *dev_priv, |
1319 | enum plane plane, bool state) | |
b24e7179 | 1320 | { |
b24e7179 | 1321 | u32 val; |
931872fc | 1322 | bool cur_state; |
b24e7179 | 1323 | |
649636ef | 1324 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1325 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1326 | I915_STATE_WARN(cur_state != state, |
931872fc | 1327 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1328 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1329 | } |
1330 | ||
931872fc CW |
1331 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1332 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1333 | ||
b24e7179 JB |
1334 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1335 | enum pipe pipe) | |
1336 | { | |
653e1026 | 1337 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1338 | int i; |
b24e7179 | 1339 | |
653e1026 VS |
1340 | /* Primary planes are fixed to pipes on gen4+ */ |
1341 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1342 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1343 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1344 | "plane %c assertion failure, should be disabled but not\n", |
1345 | plane_name(pipe)); | |
19ec1358 | 1346 | return; |
28c05794 | 1347 | } |
19ec1358 | 1348 | |
b24e7179 | 1349 | /* Need to check both planes against the pipe */ |
055e393f | 1350 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1351 | u32 val = I915_READ(DSPCNTR(i)); |
1352 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1353 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1354 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1355 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1356 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1357 | } |
1358 | } | |
1359 | ||
19332d7a JB |
1360 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1361 | enum pipe pipe) | |
1362 | { | |
20674eef | 1363 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1364 | int sprite; |
19332d7a | 1365 | |
7feb8b88 | 1366 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1367 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1368 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1369 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1370 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1371 | sprite, pipe_name(pipe)); | |
1372 | } | |
666a4537 | 1373 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1374 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1375 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1376 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1377 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1378 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1379 | } |
1380 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1381 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1382 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1383 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1384 | plane_name(pipe), pipe_name(pipe)); |
1385 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1386 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1387 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1388 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1389 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1390 | } |
1391 | } | |
1392 | ||
08c71e5e VS |
1393 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1394 | { | |
e2c719b7 | 1395 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1396 | drm_crtc_vblank_put(crtc); |
1397 | } | |
1398 | ||
7abd4b35 ACO |
1399 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1400 | enum pipe pipe) | |
92f2584a | 1401 | { |
92f2584a JB |
1402 | u32 val; |
1403 | bool enabled; | |
1404 | ||
649636ef | 1405 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1406 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1407 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1408 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1409 | pipe_name(pipe)); | |
92f2584a JB |
1410 | } |
1411 | ||
4e634389 KP |
1412 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1413 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1414 | { |
1415 | if ((val & DP_PORT_EN) == 0) | |
1416 | return false; | |
1417 | ||
2d1fe073 | 1418 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1419 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1420 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1421 | return false; | |
2d1fe073 | 1422 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1423 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1424 | return false; | |
f0575e92 KP |
1425 | } else { |
1426 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1427 | return false; | |
1428 | } | |
1429 | return true; | |
1430 | } | |
1431 | ||
1519b995 KP |
1432 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1433 | enum pipe pipe, u32 val) | |
1434 | { | |
dc0fa718 | 1435 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1436 | return false; |
1437 | ||
2d1fe073 | 1438 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1439 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1440 | return false; |
2d1fe073 | 1441 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1442 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1443 | return false; | |
1519b995 | 1444 | } else { |
dc0fa718 | 1445 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1446 | return false; |
1447 | } | |
1448 | return true; | |
1449 | } | |
1450 | ||
1451 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1452 | enum pipe pipe, u32 val) | |
1453 | { | |
1454 | if ((val & LVDS_PORT_EN) == 0) | |
1455 | return false; | |
1456 | ||
2d1fe073 | 1457 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1458 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1459 | return false; | |
1460 | } else { | |
1461 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1462 | return false; | |
1463 | } | |
1464 | return true; | |
1465 | } | |
1466 | ||
1467 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1468 | enum pipe pipe, u32 val) | |
1469 | { | |
1470 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1471 | return false; | |
2d1fe073 | 1472 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1473 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1474 | return false; | |
1475 | } else { | |
1476 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1477 | return false; | |
1478 | } | |
1479 | return true; | |
1480 | } | |
1481 | ||
291906f1 | 1482 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1483 | enum pipe pipe, i915_reg_t reg, |
1484 | u32 port_sel) | |
291906f1 | 1485 | { |
47a05eca | 1486 | u32 val = I915_READ(reg); |
e2c719b7 | 1487 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1488 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1489 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1490 | |
2d1fe073 | 1491 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1492 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1493 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1494 | } |
1495 | ||
1496 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1497 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1498 | { |
47a05eca | 1499 | u32 val = I915_READ(reg); |
e2c719b7 | 1500 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1501 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1502 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1503 | |
2d1fe073 | 1504 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1505 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1506 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1507 | } |
1508 | ||
1509 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1510 | enum pipe pipe) | |
1511 | { | |
291906f1 | 1512 | u32 val; |
291906f1 | 1513 | |
f0575e92 KP |
1514 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1515 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1516 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1517 | |
649636ef | 1518 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1519 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1520 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1521 | pipe_name(pipe)); |
291906f1 | 1522 | |
649636ef | 1523 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1524 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1525 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1526 | pipe_name(pipe)); |
291906f1 | 1527 | |
e2debe91 PZ |
1528 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1529 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1530 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1531 | } |
1532 | ||
d288f65f | 1533 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1534 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1535 | { |
426115cf DV |
1536 | struct drm_device *dev = crtc->base.dev; |
1537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8bd3f301 VS |
1538 | enum pipe pipe = crtc->pipe; |
1539 | i915_reg_t reg = DPLL(pipe); | |
d288f65f | 1540 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1541 | |
8bd3f301 | 1542 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1543 | |
87442f73 | 1544 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1545 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1546 | |
426115cf DV |
1547 | I915_WRITE(reg, dpll); |
1548 | POSTING_READ(reg); | |
1549 | udelay(150); | |
1550 | ||
1551 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
8bd3f301 | 1552 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
426115cf | 1553 | |
8bd3f301 VS |
1554 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1555 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1556 | } |
1557 | ||
d288f65f | 1558 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1559 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1560 | { |
1561 | struct drm_device *dev = crtc->base.dev; | |
1562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8bd3f301 | 1563 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1564 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1565 | u32 tmp; |
1566 | ||
8bd3f301 | 1567 | assert_pipe_disabled(dev_priv, pipe); |
9d556c99 | 1568 | |
7d1a83cb VS |
1569 | /* PLL is protected by panel, make sure we can write it */ |
1570 | assert_panel_unlocked(dev_priv, pipe); | |
1571 | ||
a580516d | 1572 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1573 | |
1574 | /* Enable back the 10bit clock to display controller */ | |
1575 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1576 | tmp |= DPIO_DCLKP_EN; | |
1577 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1578 | ||
54433e91 VS |
1579 | mutex_unlock(&dev_priv->sb_lock); |
1580 | ||
9d556c99 CML |
1581 | /* |
1582 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1583 | */ | |
1584 | udelay(1); | |
1585 | ||
1586 | /* Enable PLL */ | |
d288f65f | 1587 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1588 | |
1589 | /* Check PLL is locked */ | |
a11b0703 | 1590 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1591 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1592 | ||
c231775c VS |
1593 | if (pipe != PIPE_A) { |
1594 | /* | |
1595 | * WaPixelRepeatModeFixForC0:chv | |
1596 | * | |
1597 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1598 | * the value from DPLLBMD to either pipe B or C. | |
1599 | */ | |
1600 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1601 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1602 | I915_WRITE(CBR4_VLV, 0); | |
1603 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1604 | ||
1605 | /* | |
1606 | * DPLLB VGA mode also seems to cause problems. | |
1607 | * We should always have it disabled. | |
1608 | */ | |
1609 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1610 | } else { | |
1611 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1612 | POSTING_READ(DPLL_MD(pipe)); | |
1613 | } | |
9d556c99 CML |
1614 | } |
1615 | ||
1c4e0274 VS |
1616 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1617 | { | |
1618 | struct intel_crtc *crtc; | |
1619 | int count = 0; | |
1620 | ||
1621 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1622 | count += crtc->base.state->active && |
409ee761 | 1623 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1624 | |
1625 | return count; | |
1626 | } | |
1627 | ||
66e3d5c0 | 1628 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1629 | { |
66e3d5c0 DV |
1630 | struct drm_device *dev = crtc->base.dev; |
1631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1632 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1633 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1634 | |
66e3d5c0 | 1635 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1636 | |
63d7bbe9 | 1637 | /* PLL is protected by panel, make sure we can write it */ |
66e3d5c0 DV |
1638 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1639 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1640 | |
1c4e0274 VS |
1641 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1642 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1643 | /* | |
1644 | * It appears to be important that we don't enable this | |
1645 | * for the current pipe before otherwise configuring the | |
1646 | * PLL. No idea how this should be handled if multiple | |
1647 | * DVO outputs are enabled simultaneosly. | |
1648 | */ | |
1649 | dpll |= DPLL_DVO_2X_MODE; | |
1650 | I915_WRITE(DPLL(!crtc->pipe), | |
1651 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1652 | } | |
66e3d5c0 | 1653 | |
c2b63374 VS |
1654 | /* |
1655 | * Apparently we need to have VGA mode enabled prior to changing | |
1656 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1657 | * dividers, even though the register value does change. | |
1658 | */ | |
1659 | I915_WRITE(reg, 0); | |
1660 | ||
8e7a65aa VS |
1661 | I915_WRITE(reg, dpll); |
1662 | ||
66e3d5c0 DV |
1663 | /* Wait for the clocks to stabilize. */ |
1664 | POSTING_READ(reg); | |
1665 | udelay(150); | |
1666 | ||
1667 | if (INTEL_INFO(dev)->gen >= 4) { | |
1668 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1669 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1670 | } else { |
1671 | /* The pixel multiplier can only be updated once the | |
1672 | * DPLL is enabled and the clocks are stable. | |
1673 | * | |
1674 | * So write it again. | |
1675 | */ | |
1676 | I915_WRITE(reg, dpll); | |
1677 | } | |
63d7bbe9 JB |
1678 | |
1679 | /* We do this three times for luck */ | |
66e3d5c0 | 1680 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1681 | POSTING_READ(reg); |
1682 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1683 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1684 | POSTING_READ(reg); |
1685 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1686 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1687 | POSTING_READ(reg); |
1688 | udelay(150); /* wait for warmup */ | |
1689 | } | |
1690 | ||
1691 | /** | |
50b44a44 | 1692 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1693 | * @dev_priv: i915 private structure |
1694 | * @pipe: pipe PLL to disable | |
1695 | * | |
1696 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1697 | * | |
1698 | * Note! This is for pre-ILK only. | |
1699 | */ | |
1c4e0274 | 1700 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1701 | { |
1c4e0274 VS |
1702 | struct drm_device *dev = crtc->base.dev; |
1703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1704 | enum pipe pipe = crtc->pipe; | |
1705 | ||
1706 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1707 | if (IS_I830(dev) && | |
409ee761 | 1708 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1709 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1710 | I915_WRITE(DPLL(PIPE_B), |
1711 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1712 | I915_WRITE(DPLL(PIPE_A), | |
1713 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1714 | } | |
1715 | ||
b6b5d049 VS |
1716 | /* Don't disable pipe or pipe PLLs if needed */ |
1717 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1718 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1719 | return; |
1720 | ||
1721 | /* Make sure the pipe isn't still relying on us */ | |
1722 | assert_pipe_disabled(dev_priv, pipe); | |
1723 | ||
b8afb911 | 1724 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1725 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1726 | } |
1727 | ||
f6071166 JB |
1728 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1729 | { | |
b8afb911 | 1730 | u32 val; |
f6071166 JB |
1731 | |
1732 | /* Make sure the pipe isn't still relying on us */ | |
1733 | assert_pipe_disabled(dev_priv, pipe); | |
1734 | ||
03ed5cbf VS |
1735 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1736 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1737 | if (pipe != PIPE_A) | |
1738 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1739 | ||
f6071166 JB |
1740 | I915_WRITE(DPLL(pipe), val); |
1741 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1742 | } |
1743 | ||
1744 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1745 | { | |
d752048d | 1746 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1747 | u32 val; |
1748 | ||
a11b0703 VS |
1749 | /* Make sure the pipe isn't still relying on us */ |
1750 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1751 | |
60bfe44f VS |
1752 | val = DPLL_SSC_REF_CLK_CHV | |
1753 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1754 | if (pipe != PIPE_A) |
1755 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1756 | |
a11b0703 VS |
1757 | I915_WRITE(DPLL(pipe), val); |
1758 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1759 | |
a580516d | 1760 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1761 | |
1762 | /* Disable 10bit clock to display controller */ | |
1763 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1764 | val &= ~DPIO_DCLKP_EN; | |
1765 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1766 | ||
a580516d | 1767 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1768 | } |
1769 | ||
e4607fcf | 1770 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1771 | struct intel_digital_port *dport, |
1772 | unsigned int expected_mask) | |
89b667f8 JB |
1773 | { |
1774 | u32 port_mask; | |
f0f59a00 | 1775 | i915_reg_t dpll_reg; |
89b667f8 | 1776 | |
e4607fcf CML |
1777 | switch (dport->port) { |
1778 | case PORT_B: | |
89b667f8 | 1779 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1780 | dpll_reg = DPLL(0); |
e4607fcf CML |
1781 | break; |
1782 | case PORT_C: | |
89b667f8 | 1783 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1784 | dpll_reg = DPLL(0); |
9b6de0a1 | 1785 | expected_mask <<= 4; |
00fc31b7 CML |
1786 | break; |
1787 | case PORT_D: | |
1788 | port_mask = DPLL_PORTD_READY_MASK; | |
1789 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1790 | break; |
1791 | default: | |
1792 | BUG(); | |
1793 | } | |
89b667f8 | 1794 | |
9b6de0a1 VS |
1795 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1796 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1797 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1798 | } |
1799 | ||
b8a4f404 PZ |
1800 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1801 | enum pipe pipe) | |
040484af | 1802 | { |
23670b32 | 1803 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1804 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1805 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1806 | i915_reg_t reg; |
1807 | uint32_t val, pipeconf_val; | |
040484af | 1808 | |
040484af | 1809 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1810 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1811 | |
1812 | /* FDI must be feeding us bits for PCH ports */ | |
1813 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1814 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1815 | ||
23670b32 DV |
1816 | if (HAS_PCH_CPT(dev)) { |
1817 | /* Workaround: Set the timing override bit before enabling the | |
1818 | * pch transcoder. */ | |
1819 | reg = TRANS_CHICKEN2(pipe); | |
1820 | val = I915_READ(reg); | |
1821 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1822 | I915_WRITE(reg, val); | |
59c859d6 | 1823 | } |
23670b32 | 1824 | |
ab9412ba | 1825 | reg = PCH_TRANSCONF(pipe); |
040484af | 1826 | val = I915_READ(reg); |
5f7f726d | 1827 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1828 | |
2d1fe073 | 1829 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1830 | /* |
c5de7c6f VS |
1831 | * Make the BPC in transcoder be consistent with |
1832 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1833 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1834 | */ |
dfd07d72 | 1835 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1836 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1837 | val |= PIPECONF_8BPC; | |
1838 | else | |
1839 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1840 | } |
5f7f726d PZ |
1841 | |
1842 | val &= ~TRANS_INTERLACE_MASK; | |
1843 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1844 | if (HAS_PCH_IBX(dev_priv) && |
409ee761 | 1845 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1846 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1847 | else | |
1848 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1849 | else |
1850 | val |= TRANS_PROGRESSIVE; | |
1851 | ||
040484af JB |
1852 | I915_WRITE(reg, val | TRANS_ENABLE); |
1853 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1854 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1855 | } |
1856 | ||
8fb033d7 | 1857 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1858 | enum transcoder cpu_transcoder) |
040484af | 1859 | { |
8fb033d7 | 1860 | u32 val, pipeconf_val; |
8fb033d7 | 1861 | |
8fb033d7 | 1862 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1863 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1864 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1865 | |
223a6fdf | 1866 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1867 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1868 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1869 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1870 | |
25f3ef11 | 1871 | val = TRANS_ENABLE; |
937bb610 | 1872 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1873 | |
9a76b1c6 PZ |
1874 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1875 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1876 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1877 | else |
1878 | val |= TRANS_PROGRESSIVE; | |
1879 | ||
ab9412ba DV |
1880 | I915_WRITE(LPT_TRANSCONF, val); |
1881 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1882 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1883 | } |
1884 | ||
b8a4f404 PZ |
1885 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1886 | enum pipe pipe) | |
040484af | 1887 | { |
23670b32 | 1888 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
1889 | i915_reg_t reg; |
1890 | uint32_t val; | |
040484af JB |
1891 | |
1892 | /* FDI relies on the transcoder */ | |
1893 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1894 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1895 | ||
291906f1 JB |
1896 | /* Ports must be off as well */ |
1897 | assert_pch_ports_disabled(dev_priv, pipe); | |
1898 | ||
ab9412ba | 1899 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1900 | val = I915_READ(reg); |
1901 | val &= ~TRANS_ENABLE; | |
1902 | I915_WRITE(reg, val); | |
1903 | /* wait for PCH transcoder off, transcoder state */ | |
1904 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1905 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1906 | |
c465613b | 1907 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1908 | /* Workaround: Clear the timing override chicken bit again. */ |
1909 | reg = TRANS_CHICKEN2(pipe); | |
1910 | val = I915_READ(reg); | |
1911 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1912 | I915_WRITE(reg, val); | |
1913 | } | |
040484af JB |
1914 | } |
1915 | ||
ab4d966c | 1916 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1917 | { |
8fb033d7 PZ |
1918 | u32 val; |
1919 | ||
ab9412ba | 1920 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1921 | val &= ~TRANS_ENABLE; |
ab9412ba | 1922 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1923 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1924 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1925 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1926 | |
1927 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1928 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1929 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1930 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1931 | } |
1932 | ||
b24e7179 | 1933 | /** |
309cfea8 | 1934 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1935 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1936 | * |
0372264a | 1937 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1938 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1939 | */ |
e1fdc473 | 1940 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1941 | { |
0372264a PZ |
1942 | struct drm_device *dev = crtc->base.dev; |
1943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1944 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 1945 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1946 | enum pipe pch_transcoder; |
f0f59a00 | 1947 | i915_reg_t reg; |
b24e7179 JB |
1948 | u32 val; |
1949 | ||
9e2ee2dd VS |
1950 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1951 | ||
58c6eaa2 | 1952 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1953 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1954 | assert_sprites_disabled(dev_priv, pipe); |
1955 | ||
2d1fe073 | 1956 | if (HAS_PCH_LPT(dev_priv)) |
cc391bbb PZ |
1957 | pch_transcoder = TRANSCODER_A; |
1958 | else | |
1959 | pch_transcoder = pipe; | |
1960 | ||
b24e7179 JB |
1961 | /* |
1962 | * A pipe without a PLL won't actually be able to drive bits from | |
1963 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1964 | * need the check. | |
1965 | */ | |
2d1fe073 | 1966 | if (HAS_GMCH_DISPLAY(dev_priv)) |
a65347ba | 1967 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
1968 | assert_dsi_pll_enabled(dev_priv); |
1969 | else | |
1970 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 1971 | else { |
6e3c9717 | 1972 | if (crtc->config->has_pch_encoder) { |
040484af | 1973 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1974 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1975 | assert_fdi_tx_pll_enabled(dev_priv, |
1976 | (enum pipe) cpu_transcoder); | |
040484af JB |
1977 | } |
1978 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1979 | } | |
b24e7179 | 1980 | |
702e7a56 | 1981 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1982 | val = I915_READ(reg); |
7ad25d48 | 1983 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1984 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1985 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1986 | return; |
7ad25d48 | 1987 | } |
00d70b15 CW |
1988 | |
1989 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1990 | POSTING_READ(reg); |
b7792d8b VS |
1991 | |
1992 | /* | |
1993 | * Until the pipe starts DSL will read as 0, which would cause | |
1994 | * an apparent vblank timestamp jump, which messes up also the | |
1995 | * frame count when it's derived from the timestamps. So let's | |
1996 | * wait for the pipe to start properly before we call | |
1997 | * drm_crtc_vblank_on() | |
1998 | */ | |
1999 | if (dev->max_vblank_count == 0 && | |
2000 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2001 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2002 | } |
2003 | ||
2004 | /** | |
309cfea8 | 2005 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2006 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2007 | * |
575f7ab7 VS |
2008 | * Disable the pipe of @crtc, making sure that various hardware |
2009 | * specific requirements are met, if applicable, e.g. plane | |
2010 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2011 | * |
2012 | * Will wait until the pipe has shut down before returning. | |
2013 | */ | |
575f7ab7 | 2014 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2015 | { |
575f7ab7 | 2016 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2017 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2018 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2019 | i915_reg_t reg; |
b24e7179 JB |
2020 | u32 val; |
2021 | ||
9e2ee2dd VS |
2022 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2023 | ||
b24e7179 JB |
2024 | /* |
2025 | * Make sure planes won't keep trying to pump pixels to us, | |
2026 | * or we might hang the display. | |
2027 | */ | |
2028 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2029 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2030 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2031 | |
702e7a56 | 2032 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2033 | val = I915_READ(reg); |
00d70b15 CW |
2034 | if ((val & PIPECONF_ENABLE) == 0) |
2035 | return; | |
2036 | ||
67adc644 VS |
2037 | /* |
2038 | * Double wide has implications for planes | |
2039 | * so best keep it disabled when not needed. | |
2040 | */ | |
6e3c9717 | 2041 | if (crtc->config->double_wide) |
67adc644 VS |
2042 | val &= ~PIPECONF_DOUBLE_WIDE; |
2043 | ||
2044 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2045 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2046 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2047 | val &= ~PIPECONF_ENABLE; |
2048 | ||
2049 | I915_WRITE(reg, val); | |
2050 | if ((val & PIPECONF_ENABLE) == 0) | |
2051 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2052 | } |
2053 | ||
693db184 CW |
2054 | static bool need_vtd_wa(struct drm_device *dev) |
2055 | { | |
2056 | #ifdef CONFIG_INTEL_IOMMU | |
2057 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2058 | return true; | |
2059 | #endif | |
2060 | return false; | |
2061 | } | |
2062 | ||
832be82f VS |
2063 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2064 | { | |
2065 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2066 | } | |
2067 | ||
27ba3910 VS |
2068 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2069 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2070 | { |
2071 | switch (fb_modifier) { | |
2072 | case DRM_FORMAT_MOD_NONE: | |
2073 | return cpp; | |
2074 | case I915_FORMAT_MOD_X_TILED: | |
2075 | if (IS_GEN2(dev_priv)) | |
2076 | return 128; | |
2077 | else | |
2078 | return 512; | |
2079 | case I915_FORMAT_MOD_Y_TILED: | |
2080 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2081 | return 128; | |
2082 | else | |
2083 | return 512; | |
2084 | case I915_FORMAT_MOD_Yf_TILED: | |
2085 | switch (cpp) { | |
2086 | case 1: | |
2087 | return 64; | |
2088 | case 2: | |
2089 | case 4: | |
2090 | return 128; | |
2091 | case 8: | |
2092 | case 16: | |
2093 | return 256; | |
2094 | default: | |
2095 | MISSING_CASE(cpp); | |
2096 | return cpp; | |
2097 | } | |
2098 | break; | |
2099 | default: | |
2100 | MISSING_CASE(fb_modifier); | |
2101 | return cpp; | |
2102 | } | |
2103 | } | |
2104 | ||
832be82f VS |
2105 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2106 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2107 | { |
832be82f VS |
2108 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2109 | return 1; | |
2110 | else | |
2111 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2112 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2113 | } |
2114 | ||
8d0deca8 VS |
2115 | /* Return the tile dimensions in pixel units */ |
2116 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2117 | unsigned int *tile_width, | |
2118 | unsigned int *tile_height, | |
2119 | uint64_t fb_modifier, | |
2120 | unsigned int cpp) | |
2121 | { | |
2122 | unsigned int tile_width_bytes = | |
2123 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2124 | ||
2125 | *tile_width = tile_width_bytes / cpp; | |
2126 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2127 | } | |
2128 | ||
6761dd31 TU |
2129 | unsigned int |
2130 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2131 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2132 | { |
832be82f VS |
2133 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2134 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2135 | ||
2136 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2137 | } |
2138 | ||
1663b9d6 VS |
2139 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2140 | { | |
2141 | unsigned int size = 0; | |
2142 | int i; | |
2143 | ||
2144 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2145 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2146 | ||
2147 | return size; | |
2148 | } | |
2149 | ||
75c82a53 | 2150 | static void |
3465c580 VS |
2151 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2152 | const struct drm_framebuffer *fb, | |
2153 | unsigned int rotation) | |
f64b98cd | 2154 | { |
2d7a215f VS |
2155 | if (intel_rotation_90_or_270(rotation)) { |
2156 | *view = i915_ggtt_view_rotated; | |
2157 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2158 | } else { | |
2159 | *view = i915_ggtt_view_normal; | |
2160 | } | |
2161 | } | |
50470bb0 | 2162 | |
2d7a215f VS |
2163 | static void |
2164 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2165 | struct drm_framebuffer *fb) | |
2166 | { | |
2167 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2168 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2169 | |
d9b3288e VS |
2170 | tile_size = intel_tile_size(dev_priv); |
2171 | ||
2172 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2173 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2174 | fb->modifier[0], cpp); | |
d9b3288e | 2175 | |
1663b9d6 VS |
2176 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2177 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2178 | |
89e3e142 | 2179 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2180 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2181 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2182 | fb->modifier[1], cpp); | |
d9b3288e | 2183 | |
2d7a215f | 2184 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2185 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2186 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2187 | } |
f64b98cd TU |
2188 | } |
2189 | ||
603525d7 | 2190 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2191 | { |
2192 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2193 | return 256 * 1024; | |
985b8bb4 | 2194 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2195 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2196 | return 128 * 1024; |
2197 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2198 | return 4 * 1024; | |
2199 | else | |
44c5905e | 2200 | return 0; |
4e9a86b6 VS |
2201 | } |
2202 | ||
603525d7 VS |
2203 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2204 | uint64_t fb_modifier) | |
2205 | { | |
2206 | switch (fb_modifier) { | |
2207 | case DRM_FORMAT_MOD_NONE: | |
2208 | return intel_linear_alignment(dev_priv); | |
2209 | case I915_FORMAT_MOD_X_TILED: | |
2210 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2211 | return 256 * 1024; | |
2212 | return 0; | |
2213 | case I915_FORMAT_MOD_Y_TILED: | |
2214 | case I915_FORMAT_MOD_Yf_TILED: | |
2215 | return 1 * 1024 * 1024; | |
2216 | default: | |
2217 | MISSING_CASE(fb_modifier); | |
2218 | return 0; | |
2219 | } | |
2220 | } | |
2221 | ||
127bd2ac | 2222 | int |
3465c580 VS |
2223 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2224 | unsigned int rotation) | |
6b95a207 | 2225 | { |
850c4cdc | 2226 | struct drm_device *dev = fb->dev; |
ce453d81 | 2227 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2228 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2229 | struct i915_ggtt_view view; |
6b95a207 KH |
2230 | u32 alignment; |
2231 | int ret; | |
2232 | ||
ebcdd39e MR |
2233 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2234 | ||
603525d7 | 2235 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2236 | |
3465c580 | 2237 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2238 | |
693db184 CW |
2239 | /* Note that the w/a also requires 64 PTE of padding following the |
2240 | * bo. We currently fill all unused PTE with the shadow page and so | |
2241 | * we should always have valid PTE following the scanout preventing | |
2242 | * the VT-d warning. | |
2243 | */ | |
2244 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2245 | alignment = 256 * 1024; | |
2246 | ||
d6dd6843 PZ |
2247 | /* |
2248 | * Global gtt pte registers are special registers which actually forward | |
2249 | * writes to a chunk of system memory. Which means that there is no risk | |
2250 | * that the register values disappear as soon as we call | |
2251 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2252 | * pin/unpin/fence and not more. | |
2253 | */ | |
2254 | intel_runtime_pm_get(dev_priv); | |
2255 | ||
7580d774 ML |
2256 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2257 | &view); | |
48b956c5 | 2258 | if (ret) |
b26a6b35 | 2259 | goto err_pm; |
6b95a207 KH |
2260 | |
2261 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2262 | * fence, whereas 965+ only requires a fence if using | |
2263 | * framebuffer compression. For simplicity, we always install | |
2264 | * a fence as the cost is not that onerous. | |
2265 | */ | |
9807216f VK |
2266 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2267 | ret = i915_gem_object_get_fence(obj); | |
2268 | if (ret == -EDEADLK) { | |
2269 | /* | |
2270 | * -EDEADLK means there are no free fences | |
2271 | * no pending flips. | |
2272 | * | |
2273 | * This is propagated to atomic, but it uses | |
2274 | * -EDEADLK to force a locking recovery, so | |
2275 | * change the returned error to -EBUSY. | |
2276 | */ | |
2277 | ret = -EBUSY; | |
2278 | goto err_unpin; | |
2279 | } else if (ret) | |
2280 | goto err_unpin; | |
1690e1eb | 2281 | |
9807216f VK |
2282 | i915_gem_object_pin_fence(obj); |
2283 | } | |
6b95a207 | 2284 | |
d6dd6843 | 2285 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2286 | return 0; |
48b956c5 CW |
2287 | |
2288 | err_unpin: | |
f64b98cd | 2289 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2290 | err_pm: |
d6dd6843 | 2291 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2292 | return ret; |
6b95a207 KH |
2293 | } |
2294 | ||
3465c580 | 2295 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2296 | { |
82bc3b2d | 2297 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2298 | struct i915_ggtt_view view; |
82bc3b2d | 2299 | |
ebcdd39e MR |
2300 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2301 | ||
3465c580 | 2302 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2303 | |
9807216f VK |
2304 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2305 | i915_gem_object_unpin_fence(obj); | |
2306 | ||
f64b98cd | 2307 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2308 | } |
2309 | ||
29cf9491 VS |
2310 | /* |
2311 | * Adjust the tile offset by moving the difference into | |
2312 | * the x/y offsets. | |
2313 | * | |
2314 | * Input tile dimensions and pitch must already be | |
2315 | * rotated to match x and y, and in pixel units. | |
2316 | */ | |
2317 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2318 | unsigned int tile_width, | |
2319 | unsigned int tile_height, | |
2320 | unsigned int tile_size, | |
2321 | unsigned int pitch_tiles, | |
2322 | u32 old_offset, | |
2323 | u32 new_offset) | |
2324 | { | |
2325 | unsigned int tiles; | |
2326 | ||
2327 | WARN_ON(old_offset & (tile_size - 1)); | |
2328 | WARN_ON(new_offset & (tile_size - 1)); | |
2329 | WARN_ON(new_offset > old_offset); | |
2330 | ||
2331 | tiles = (old_offset - new_offset) / tile_size; | |
2332 | ||
2333 | *y += tiles / pitch_tiles * tile_height; | |
2334 | *x += tiles % pitch_tiles * tile_width; | |
2335 | ||
2336 | return new_offset; | |
2337 | } | |
2338 | ||
8d0deca8 VS |
2339 | /* |
2340 | * Computes the linear offset to the base tile and adjusts | |
2341 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2342 | * | |
2343 | * In the 90/270 rotated case, x and y are assumed | |
2344 | * to be already rotated to match the rotated GTT view, and | |
2345 | * pitch is the tile_height aligned framebuffer height. | |
2346 | */ | |
4f2d9934 VS |
2347 | u32 intel_compute_tile_offset(int *x, int *y, |
2348 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2349 | unsigned int pitch, |
2350 | unsigned int rotation) | |
c2c75131 | 2351 | { |
4f2d9934 VS |
2352 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2353 | uint64_t fb_modifier = fb->modifier[plane]; | |
2354 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2355 | u32 offset, offset_aligned, alignment; |
2356 | ||
2357 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2358 | if (alignment) | |
2359 | alignment--; | |
2360 | ||
b5c65338 | 2361 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2362 | unsigned int tile_size, tile_width, tile_height; |
2363 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2364 | |
d843310d | 2365 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2366 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2367 | fb_modifier, cpp); | |
2368 | ||
2369 | if (intel_rotation_90_or_270(rotation)) { | |
2370 | pitch_tiles = pitch / tile_height; | |
2371 | swap(tile_width, tile_height); | |
2372 | } else { | |
2373 | pitch_tiles = pitch / (tile_width * cpp); | |
2374 | } | |
d843310d VS |
2375 | |
2376 | tile_rows = *y / tile_height; | |
2377 | *y %= tile_height; | |
c2c75131 | 2378 | |
8d0deca8 VS |
2379 | tiles = *x / tile_width; |
2380 | *x %= tile_width; | |
bc752862 | 2381 | |
29cf9491 VS |
2382 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2383 | offset_aligned = offset & ~alignment; | |
bc752862 | 2384 | |
29cf9491 VS |
2385 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2386 | tile_size, pitch_tiles, | |
2387 | offset, offset_aligned); | |
2388 | } else { | |
bc752862 | 2389 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2390 | offset_aligned = offset & ~alignment; |
2391 | ||
4e9a86b6 VS |
2392 | *y = (offset & alignment) / pitch; |
2393 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2394 | } |
29cf9491 VS |
2395 | |
2396 | return offset_aligned; | |
c2c75131 DV |
2397 | } |
2398 | ||
b35d63fa | 2399 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2400 | { |
2401 | switch (format) { | |
2402 | case DISPPLANE_8BPP: | |
2403 | return DRM_FORMAT_C8; | |
2404 | case DISPPLANE_BGRX555: | |
2405 | return DRM_FORMAT_XRGB1555; | |
2406 | case DISPPLANE_BGRX565: | |
2407 | return DRM_FORMAT_RGB565; | |
2408 | default: | |
2409 | case DISPPLANE_BGRX888: | |
2410 | return DRM_FORMAT_XRGB8888; | |
2411 | case DISPPLANE_RGBX888: | |
2412 | return DRM_FORMAT_XBGR8888; | |
2413 | case DISPPLANE_BGRX101010: | |
2414 | return DRM_FORMAT_XRGB2101010; | |
2415 | case DISPPLANE_RGBX101010: | |
2416 | return DRM_FORMAT_XBGR2101010; | |
2417 | } | |
2418 | } | |
2419 | ||
bc8d7dff DL |
2420 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2421 | { | |
2422 | switch (format) { | |
2423 | case PLANE_CTL_FORMAT_RGB_565: | |
2424 | return DRM_FORMAT_RGB565; | |
2425 | default: | |
2426 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2427 | if (rgb_order) { | |
2428 | if (alpha) | |
2429 | return DRM_FORMAT_ABGR8888; | |
2430 | else | |
2431 | return DRM_FORMAT_XBGR8888; | |
2432 | } else { | |
2433 | if (alpha) | |
2434 | return DRM_FORMAT_ARGB8888; | |
2435 | else | |
2436 | return DRM_FORMAT_XRGB8888; | |
2437 | } | |
2438 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2439 | if (rgb_order) | |
2440 | return DRM_FORMAT_XBGR2101010; | |
2441 | else | |
2442 | return DRM_FORMAT_XRGB2101010; | |
2443 | } | |
2444 | } | |
2445 | ||
5724dbd1 | 2446 | static bool |
f6936e29 DV |
2447 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2448 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2449 | { |
2450 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2451 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2452 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2453 | struct drm_i915_gem_object *obj = NULL; |
2454 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2455 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2456 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2457 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2458 | PAGE_SIZE); | |
2459 | ||
2460 | size_aligned -= base_aligned; | |
46f297fb | 2461 | |
ff2652ea CW |
2462 | if (plane_config->size == 0) |
2463 | return false; | |
2464 | ||
3badb49f PZ |
2465 | /* If the FB is too big, just don't use it since fbdev is not very |
2466 | * important and we should probably use that space with FBC or other | |
2467 | * features. */ | |
72e96d64 | 2468 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2469 | return false; |
2470 | ||
12c83d99 TU |
2471 | mutex_lock(&dev->struct_mutex); |
2472 | ||
f37b5c2b DV |
2473 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2474 | base_aligned, | |
2475 | base_aligned, | |
2476 | size_aligned); | |
12c83d99 TU |
2477 | if (!obj) { |
2478 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2479 | return false; |
12c83d99 | 2480 | } |
46f297fb | 2481 | |
49af449b DL |
2482 | obj->tiling_mode = plane_config->tiling; |
2483 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2484 | obj->stride = fb->pitches[0]; |
46f297fb | 2485 | |
6bf129df DL |
2486 | mode_cmd.pixel_format = fb->pixel_format; |
2487 | mode_cmd.width = fb->width; | |
2488 | mode_cmd.height = fb->height; | |
2489 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2490 | mode_cmd.modifier[0] = fb->modifier[0]; |
2491 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2492 | |
6bf129df | 2493 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2494 | &mode_cmd, obj)) { |
46f297fb JB |
2495 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2496 | goto out_unref_obj; | |
2497 | } | |
12c83d99 | 2498 | |
46f297fb | 2499 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2500 | |
f6936e29 | 2501 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2502 | return true; |
46f297fb JB |
2503 | |
2504 | out_unref_obj: | |
2505 | drm_gem_object_unreference(&obj->base); | |
2506 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2507 | return false; |
2508 | } | |
2509 | ||
afd65eb4 MR |
2510 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2511 | static void | |
2512 | update_state_fb(struct drm_plane *plane) | |
2513 | { | |
2514 | if (plane->fb == plane->state->fb) | |
2515 | return; | |
2516 | ||
2517 | if (plane->state->fb) | |
2518 | drm_framebuffer_unreference(plane->state->fb); | |
2519 | plane->state->fb = plane->fb; | |
2520 | if (plane->state->fb) | |
2521 | drm_framebuffer_reference(plane->state->fb); | |
2522 | } | |
2523 | ||
5724dbd1 | 2524 | static void |
f6936e29 DV |
2525 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2526 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2527 | { |
2528 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2529 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2530 | struct drm_crtc *c; |
2531 | struct intel_crtc *i; | |
2ff8fde1 | 2532 | struct drm_i915_gem_object *obj; |
88595ac9 | 2533 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2534 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2535 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2536 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2537 | struct intel_plane_state *intel_state = |
2538 | to_intel_plane_state(plane_state); | |
88595ac9 | 2539 | struct drm_framebuffer *fb; |
484b41dd | 2540 | |
2d14030b | 2541 | if (!plane_config->fb) |
484b41dd JB |
2542 | return; |
2543 | ||
f6936e29 | 2544 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2545 | fb = &plane_config->fb->base; |
2546 | goto valid_fb; | |
f55548b5 | 2547 | } |
484b41dd | 2548 | |
2d14030b | 2549 | kfree(plane_config->fb); |
484b41dd JB |
2550 | |
2551 | /* | |
2552 | * Failed to alloc the obj, check to see if we should share | |
2553 | * an fb with another CRTC instead | |
2554 | */ | |
70e1e0ec | 2555 | for_each_crtc(dev, c) { |
484b41dd JB |
2556 | i = to_intel_crtc(c); |
2557 | ||
2558 | if (c == &intel_crtc->base) | |
2559 | continue; | |
2560 | ||
2ff8fde1 MR |
2561 | if (!i->active) |
2562 | continue; | |
2563 | ||
88595ac9 DV |
2564 | fb = c->primary->fb; |
2565 | if (!fb) | |
484b41dd JB |
2566 | continue; |
2567 | ||
88595ac9 | 2568 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2569 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2570 | drm_framebuffer_reference(fb); |
2571 | goto valid_fb; | |
484b41dd JB |
2572 | } |
2573 | } | |
88595ac9 | 2574 | |
200757f5 MR |
2575 | /* |
2576 | * We've failed to reconstruct the BIOS FB. Current display state | |
2577 | * indicates that the primary plane is visible, but has a NULL FB, | |
2578 | * which will lead to problems later if we don't fix it up. The | |
2579 | * simplest solution is to just disable the primary plane now and | |
2580 | * pretend the BIOS never had it enabled. | |
2581 | */ | |
2582 | to_intel_plane_state(plane_state)->visible = false; | |
2583 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2584 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2585 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2586 | ||
88595ac9 DV |
2587 | return; |
2588 | ||
2589 | valid_fb: | |
f44e2659 VS |
2590 | plane_state->src_x = 0; |
2591 | plane_state->src_y = 0; | |
be5651f2 ML |
2592 | plane_state->src_w = fb->width << 16; |
2593 | plane_state->src_h = fb->height << 16; | |
2594 | ||
f44e2659 VS |
2595 | plane_state->crtc_x = 0; |
2596 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2597 | plane_state->crtc_w = fb->width; |
2598 | plane_state->crtc_h = fb->height; | |
2599 | ||
0a8d8a86 MR |
2600 | intel_state->src.x1 = plane_state->src_x; |
2601 | intel_state->src.y1 = plane_state->src_y; | |
2602 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2603 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2604 | intel_state->dst.x1 = plane_state->crtc_x; | |
2605 | intel_state->dst.y1 = plane_state->crtc_y; | |
2606 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2607 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2608 | ||
88595ac9 DV |
2609 | obj = intel_fb_obj(fb); |
2610 | if (obj->tiling_mode != I915_TILING_NONE) | |
2611 | dev_priv->preserve_bios_swizzle = true; | |
2612 | ||
be5651f2 ML |
2613 | drm_framebuffer_reference(fb); |
2614 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2615 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2616 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2617 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2618 | } |
2619 | ||
a8d201af ML |
2620 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2621 | const struct intel_crtc_state *crtc_state, | |
2622 | const struct intel_plane_state *plane_state) | |
81255565 | 2623 | { |
a8d201af | 2624 | struct drm_device *dev = primary->dev; |
81255565 | 2625 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2626 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2627 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2628 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2629 | int plane = intel_crtc->plane; |
54ea9da8 | 2630 | u32 linear_offset; |
81255565 | 2631 | u32 dspcntr; |
f0f59a00 | 2632 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2633 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2634 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2635 | int x = plane_state->src.x1 >> 16; |
2636 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2637 | |
f45651ba VS |
2638 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2639 | ||
fdd508a6 | 2640 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2641 | |
2642 | if (INTEL_INFO(dev)->gen < 4) { | |
2643 | if (intel_crtc->pipe == PIPE_B) | |
2644 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2645 | ||
2646 | /* pipesrc and dspsize control the size that is scaled from, | |
2647 | * which should always be the user's requested size. | |
2648 | */ | |
2649 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2650 | ((crtc_state->pipe_src_h - 1) << 16) | |
2651 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2652 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2653 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2654 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2655 | ((crtc_state->pipe_src_h - 1) << 16) | |
2656 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2657 | I915_WRITE(PRIMPOS(plane), 0); |
2658 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2659 | } |
81255565 | 2660 | |
57779d06 VS |
2661 | switch (fb->pixel_format) { |
2662 | case DRM_FORMAT_C8: | |
81255565 JB |
2663 | dspcntr |= DISPPLANE_8BPP; |
2664 | break; | |
57779d06 | 2665 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2666 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2667 | break; |
57779d06 VS |
2668 | case DRM_FORMAT_RGB565: |
2669 | dspcntr |= DISPPLANE_BGRX565; | |
2670 | break; | |
2671 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2672 | dspcntr |= DISPPLANE_BGRX888; |
2673 | break; | |
2674 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2675 | dspcntr |= DISPPLANE_RGBX888; |
2676 | break; | |
2677 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2678 | dspcntr |= DISPPLANE_BGRX101010; |
2679 | break; | |
2680 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2681 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2682 | break; |
2683 | default: | |
baba133a | 2684 | BUG(); |
81255565 | 2685 | } |
57779d06 | 2686 | |
f45651ba VS |
2687 | if (INTEL_INFO(dev)->gen >= 4 && |
2688 | obj->tiling_mode != I915_TILING_NONE) | |
2689 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2690 | |
de1aa629 VS |
2691 | if (IS_G4X(dev)) |
2692 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2693 | ||
ac484963 | 2694 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2695 | |
c2c75131 DV |
2696 | if (INTEL_INFO(dev)->gen >= 4) { |
2697 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2698 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2699 | fb->pitches[0], rotation); |
c2c75131 DV |
2700 | linear_offset -= intel_crtc->dspaddr_offset; |
2701 | } else { | |
e506a0c6 | 2702 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2703 | } |
e506a0c6 | 2704 | |
8d0deca8 | 2705 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2706 | dspcntr |= DISPPLANE_ROTATE_180; |
2707 | ||
a8d201af ML |
2708 | x += (crtc_state->pipe_src_w - 1); |
2709 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2710 | |
2711 | /* Finding the last pixel of the last line of the display | |
2712 | data and adding to linear_offset*/ | |
2713 | linear_offset += | |
a8d201af | 2714 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2715 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2716 | } |
2717 | ||
2db3366b PZ |
2718 | intel_crtc->adjusted_x = x; |
2719 | intel_crtc->adjusted_y = y; | |
2720 | ||
48404c1e SJ |
2721 | I915_WRITE(reg, dspcntr); |
2722 | ||
01f2c773 | 2723 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2724 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2725 | I915_WRITE(DSPSURF(plane), |
2726 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2727 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2728 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2729 | } else |
f343c5f6 | 2730 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2731 | POSTING_READ(reg); |
17638cd6 JB |
2732 | } |
2733 | ||
a8d201af ML |
2734 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2735 | struct drm_crtc *crtc) | |
17638cd6 JB |
2736 | { |
2737 | struct drm_device *dev = crtc->dev; | |
2738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2739 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2740 | int plane = intel_crtc->plane; |
f45651ba | 2741 | |
a8d201af ML |
2742 | I915_WRITE(DSPCNTR(plane), 0); |
2743 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2744 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2745 | else |
2746 | I915_WRITE(DSPADDR(plane), 0); | |
2747 | POSTING_READ(DSPCNTR(plane)); | |
2748 | } | |
c9ba6fad | 2749 | |
a8d201af ML |
2750 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2751 | const struct intel_crtc_state *crtc_state, | |
2752 | const struct intel_plane_state *plane_state) | |
2753 | { | |
2754 | struct drm_device *dev = primary->dev; | |
2755 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2756 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2757 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2758 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2759 | int plane = intel_crtc->plane; | |
54ea9da8 | 2760 | u32 linear_offset; |
a8d201af ML |
2761 | u32 dspcntr; |
2762 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2763 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2764 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2765 | int x = plane_state->src.x1 >> 16; |
2766 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2767 | |
f45651ba | 2768 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2769 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2770 | |
2771 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2772 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2773 | |
57779d06 VS |
2774 | switch (fb->pixel_format) { |
2775 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2776 | dspcntr |= DISPPLANE_8BPP; |
2777 | break; | |
57779d06 VS |
2778 | case DRM_FORMAT_RGB565: |
2779 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2780 | break; |
57779d06 | 2781 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2782 | dspcntr |= DISPPLANE_BGRX888; |
2783 | break; | |
2784 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2785 | dspcntr |= DISPPLANE_RGBX888; |
2786 | break; | |
2787 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2788 | dspcntr |= DISPPLANE_BGRX101010; |
2789 | break; | |
2790 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2791 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2792 | break; |
2793 | default: | |
baba133a | 2794 | BUG(); |
17638cd6 JB |
2795 | } |
2796 | ||
2797 | if (obj->tiling_mode != I915_TILING_NONE) | |
2798 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2799 | |
f45651ba | 2800 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2801 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2802 | |
ac484963 | 2803 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2804 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2805 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2806 | fb->pitches[0], rotation); |
c2c75131 | 2807 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2808 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2809 | dspcntr |= DISPPLANE_ROTATE_180; |
2810 | ||
2811 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2812 | x += (crtc_state->pipe_src_w - 1); |
2813 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2814 | |
2815 | /* Finding the last pixel of the last line of the display | |
2816 | data and adding to linear_offset*/ | |
2817 | linear_offset += | |
a8d201af | 2818 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2819 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2820 | } |
2821 | } | |
2822 | ||
2db3366b PZ |
2823 | intel_crtc->adjusted_x = x; |
2824 | intel_crtc->adjusted_y = y; | |
2825 | ||
48404c1e | 2826 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2827 | |
01f2c773 | 2828 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2829 | I915_WRITE(DSPSURF(plane), |
2830 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2831 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2832 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2833 | } else { | |
2834 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2835 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2836 | } | |
17638cd6 | 2837 | POSTING_READ(reg); |
17638cd6 JB |
2838 | } |
2839 | ||
7b49f948 VS |
2840 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2841 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2842 | { |
7b49f948 | 2843 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2844 | return 64; |
7b49f948 VS |
2845 | } else { |
2846 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2847 | ||
27ba3910 | 2848 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2849 | } |
2850 | } | |
2851 | ||
44eb0cb9 MK |
2852 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2853 | struct drm_i915_gem_object *obj, | |
2854 | unsigned int plane) | |
121920fa | 2855 | { |
ce7f1728 | 2856 | struct i915_ggtt_view view; |
dedf278c | 2857 | struct i915_vma *vma; |
44eb0cb9 | 2858 | u64 offset; |
121920fa | 2859 | |
e7941294 | 2860 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 2861 | intel_plane->base.state->rotation); |
121920fa | 2862 | |
ce7f1728 | 2863 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2864 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2865 | view.type)) |
dedf278c TU |
2866 | return -1; |
2867 | ||
44eb0cb9 | 2868 | offset = vma->node.start; |
dedf278c TU |
2869 | |
2870 | if (plane == 1) { | |
7723f47d | 2871 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2872 | PAGE_SIZE; |
2873 | } | |
2874 | ||
44eb0cb9 MK |
2875 | WARN_ON(upper_32_bits(offset)); |
2876 | ||
2877 | return lower_32_bits(offset); | |
121920fa TU |
2878 | } |
2879 | ||
e435d6e5 ML |
2880 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2881 | { | |
2882 | struct drm_device *dev = intel_crtc->base.dev; | |
2883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2884 | ||
2885 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2886 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2887 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2888 | } |
2889 | ||
a1b2278e CK |
2890 | /* |
2891 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2892 | */ | |
0583236e | 2893 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2894 | { |
a1b2278e CK |
2895 | struct intel_crtc_scaler_state *scaler_state; |
2896 | int i; | |
2897 | ||
a1b2278e CK |
2898 | scaler_state = &intel_crtc->config->scaler_state; |
2899 | ||
2900 | /* loop through and disable scalers that aren't in use */ | |
2901 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2902 | if (!scaler_state->scalers[i].in_use) |
2903 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2904 | } |
2905 | } | |
2906 | ||
6156a456 | 2907 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2908 | { |
6156a456 | 2909 | switch (pixel_format) { |
d161cf7a | 2910 | case DRM_FORMAT_C8: |
c34ce3d1 | 2911 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2912 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2913 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2914 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2915 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2916 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2917 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2918 | /* |
2919 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2920 | * to be already pre-multiplied. We need to add a knob (or a different | |
2921 | * DRM_FORMAT) for user-space to configure that. | |
2922 | */ | |
f75fb42a | 2923 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2924 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2925 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2926 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2927 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2928 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2929 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2930 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2931 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2932 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2933 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2934 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2935 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2936 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2937 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2938 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2939 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2940 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2941 | default: |
4249eeef | 2942 | MISSING_CASE(pixel_format); |
70d21f0e | 2943 | } |
8cfcba41 | 2944 | |
c34ce3d1 | 2945 | return 0; |
6156a456 | 2946 | } |
70d21f0e | 2947 | |
6156a456 CK |
2948 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2949 | { | |
6156a456 | 2950 | switch (fb_modifier) { |
30af77c4 | 2951 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2952 | break; |
30af77c4 | 2953 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2954 | return PLANE_CTL_TILED_X; |
b321803d | 2955 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2956 | return PLANE_CTL_TILED_Y; |
b321803d | 2957 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2958 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2959 | default: |
6156a456 | 2960 | MISSING_CASE(fb_modifier); |
70d21f0e | 2961 | } |
8cfcba41 | 2962 | |
c34ce3d1 | 2963 | return 0; |
6156a456 | 2964 | } |
70d21f0e | 2965 | |
6156a456 CK |
2966 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2967 | { | |
3b7a5119 | 2968 | switch (rotation) { |
6156a456 CK |
2969 | case BIT(DRM_ROTATE_0): |
2970 | break; | |
1e8df167 SJ |
2971 | /* |
2972 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
2973 | * while i915 HW rotation is clockwise, thats why this swapping. | |
2974 | */ | |
3b7a5119 | 2975 | case BIT(DRM_ROTATE_90): |
1e8df167 | 2976 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 2977 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 2978 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 2979 | case BIT(DRM_ROTATE_270): |
1e8df167 | 2980 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
2981 | default: |
2982 | MISSING_CASE(rotation); | |
2983 | } | |
2984 | ||
c34ce3d1 | 2985 | return 0; |
6156a456 CK |
2986 | } |
2987 | ||
a8d201af ML |
2988 | static void skylake_update_primary_plane(struct drm_plane *plane, |
2989 | const struct intel_crtc_state *crtc_state, | |
2990 | const struct intel_plane_state *plane_state) | |
6156a456 | 2991 | { |
a8d201af | 2992 | struct drm_device *dev = plane->dev; |
6156a456 | 2993 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2994 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2995 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2996 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
2997 | int pipe = intel_crtc->pipe; |
2998 | u32 plane_ctl, stride_div, stride; | |
2999 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3000 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3001 | int x_offset, y_offset; |
44eb0cb9 | 3002 | u32 surf_addr; |
a8d201af ML |
3003 | int scaler_id = plane_state->scaler_id; |
3004 | int src_x = plane_state->src.x1 >> 16; | |
3005 | int src_y = plane_state->src.y1 >> 16; | |
3006 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3007 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3008 | int dst_x = plane_state->dst.x1; | |
3009 | int dst_y = plane_state->dst.y1; | |
3010 | int dst_w = drm_rect_width(&plane_state->dst); | |
3011 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3012 | |
6156a456 CK |
3013 | plane_ctl = PLANE_CTL_ENABLE | |
3014 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3015 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3016 | ||
3017 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3018 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3019 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3020 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3021 | ||
7b49f948 | 3022 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3023 | fb->pixel_format); |
dedf278c | 3024 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3025 | |
a42e5a23 PZ |
3026 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3027 | ||
3b7a5119 | 3028 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3029 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3030 | ||
3b7a5119 | 3031 | /* stride = Surface height in tiles */ |
832be82f | 3032 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3033 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3034 | x_offset = stride * tile_height - src_y - src_h; |
3035 | y_offset = src_x; | |
6156a456 | 3036 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3037 | } else { |
3038 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3039 | x_offset = src_x; |
3040 | y_offset = src_y; | |
6156a456 | 3041 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3042 | } |
3043 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3044 | |
2db3366b PZ |
3045 | intel_crtc->adjusted_x = x_offset; |
3046 | intel_crtc->adjusted_y = y_offset; | |
3047 | ||
70d21f0e | 3048 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3049 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3050 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3051 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3052 | |
3053 | if (scaler_id >= 0) { | |
3054 | uint32_t ps_ctrl = 0; | |
3055 | ||
3056 | WARN_ON(!dst_w || !dst_h); | |
3057 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3058 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3059 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3060 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3061 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3062 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3063 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3064 | } else { | |
3065 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3066 | } | |
3067 | ||
121920fa | 3068 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3069 | |
3070 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3071 | } | |
3072 | ||
a8d201af ML |
3073 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3074 | struct drm_crtc *crtc) | |
17638cd6 JB |
3075 | { |
3076 | struct drm_device *dev = crtc->dev; | |
3077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3078 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3079 | |
a8d201af ML |
3080 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3081 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3082 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3083 | } | |
29b9bde6 | 3084 | |
a8d201af ML |
3085 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3086 | static int | |
3087 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3088 | int x, int y, enum mode_set_atomic state) | |
3089 | { | |
3090 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3091 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3092 | ||
3093 | return -ENODEV; | |
81255565 JB |
3094 | } |
3095 | ||
7514747d | 3096 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3097 | { |
96a02917 VS |
3098 | struct drm_crtc *crtc; |
3099 | ||
70e1e0ec | 3100 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3101 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3102 | enum plane plane = intel_crtc->plane; | |
3103 | ||
3104 | intel_prepare_page_flip(dev, plane); | |
3105 | intel_finish_page_flip_plane(dev, plane); | |
3106 | } | |
7514747d VS |
3107 | } |
3108 | ||
3109 | static void intel_update_primary_planes(struct drm_device *dev) | |
3110 | { | |
7514747d | 3111 | struct drm_crtc *crtc; |
96a02917 | 3112 | |
70e1e0ec | 3113 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3114 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3115 | struct intel_plane_state *plane_state; | |
96a02917 | 3116 | |
11c22da6 | 3117 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3118 | plane_state = to_intel_plane_state(plane->base.state); |
3119 | ||
a8d201af ML |
3120 | if (plane_state->visible) |
3121 | plane->update_plane(&plane->base, | |
3122 | to_intel_crtc_state(crtc->state), | |
3123 | plane_state); | |
11c22da6 ML |
3124 | |
3125 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3126 | } |
3127 | } | |
3128 | ||
7514747d VS |
3129 | void intel_prepare_reset(struct drm_device *dev) |
3130 | { | |
3131 | /* no reset support for gen2 */ | |
3132 | if (IS_GEN2(dev)) | |
3133 | return; | |
3134 | ||
3135 | /* reset doesn't touch the display */ | |
3136 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3137 | return; | |
3138 | ||
3139 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3140 | /* |
3141 | * Disabling the crtcs gracefully seems nicer. Also the | |
3142 | * g33 docs say we should at least disable all the planes. | |
3143 | */ | |
6b72d486 | 3144 | intel_display_suspend(dev); |
7514747d VS |
3145 | } |
3146 | ||
3147 | void intel_finish_reset(struct drm_device *dev) | |
3148 | { | |
3149 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3150 | ||
3151 | /* | |
3152 | * Flips in the rings will be nuked by the reset, | |
3153 | * so complete all pending flips so that user space | |
3154 | * will get its events and not get stuck. | |
3155 | */ | |
3156 | intel_complete_page_flips(dev); | |
3157 | ||
3158 | /* no reset support for gen2 */ | |
3159 | if (IS_GEN2(dev)) | |
3160 | return; | |
3161 | ||
3162 | /* reset doesn't touch the display */ | |
3163 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3164 | /* | |
3165 | * Flips in the rings have been nuked by the reset, | |
3166 | * so update the base address of all primary | |
3167 | * planes to the the last fb to make sure we're | |
3168 | * showing the correct fb after a reset. | |
11c22da6 ML |
3169 | * |
3170 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3171 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3172 | */ |
3173 | intel_update_primary_planes(dev); | |
3174 | return; | |
3175 | } | |
3176 | ||
3177 | /* | |
3178 | * The display has been reset as well, | |
3179 | * so need a full re-initialization. | |
3180 | */ | |
3181 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3182 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3183 | ||
3184 | intel_modeset_init_hw(dev); | |
3185 | ||
3186 | spin_lock_irq(&dev_priv->irq_lock); | |
3187 | if (dev_priv->display.hpd_irq_setup) | |
3188 | dev_priv->display.hpd_irq_setup(dev); | |
3189 | spin_unlock_irq(&dev_priv->irq_lock); | |
3190 | ||
043e9bda | 3191 | intel_display_resume(dev); |
7514747d VS |
3192 | |
3193 | intel_hpd_init(dev_priv); | |
3194 | ||
3195 | drm_modeset_unlock_all(dev); | |
3196 | } | |
3197 | ||
7d5e3799 CW |
3198 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3199 | { | |
3200 | struct drm_device *dev = crtc->dev; | |
3201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3202 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3203 | bool pending; |
3204 | ||
3205 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3206 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3207 | return false; | |
3208 | ||
5e2d7afc | 3209 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3210 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3211 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3212 | |
3213 | return pending; | |
3214 | } | |
3215 | ||
bfd16b2a ML |
3216 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3217 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3218 | { |
3219 | struct drm_device *dev = crtc->base.dev; | |
3220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3221 | struct intel_crtc_state *pipe_config = |
3222 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3223 | |
bfd16b2a ML |
3224 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3225 | crtc->base.mode = crtc->base.state->mode; | |
3226 | ||
3227 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3228 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3229 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3230 | |
3231 | /* | |
3232 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3233 | * that in compute_mode_changes we check the native mode (not the pfit | |
3234 | * mode) to see if we can flip rather than do a full mode set. In the | |
3235 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3236 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3237 | * sized surface. | |
e30e8f75 GP |
3238 | */ |
3239 | ||
e30e8f75 | 3240 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3241 | ((pipe_config->pipe_src_w - 1) << 16) | |
3242 | (pipe_config->pipe_src_h - 1)); | |
3243 | ||
3244 | /* on skylake this is done by detaching scalers */ | |
3245 | if (INTEL_INFO(dev)->gen >= 9) { | |
3246 | skl_detach_scalers(crtc); | |
3247 | ||
3248 | if (pipe_config->pch_pfit.enabled) | |
3249 | skylake_pfit_enable(crtc); | |
3250 | } else if (HAS_PCH_SPLIT(dev)) { | |
3251 | if (pipe_config->pch_pfit.enabled) | |
3252 | ironlake_pfit_enable(crtc); | |
3253 | else if (old_crtc_state->pch_pfit.enabled) | |
3254 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3255 | } |
e30e8f75 GP |
3256 | } |
3257 | ||
5e84e1a4 ZW |
3258 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3259 | { | |
3260 | struct drm_device *dev = crtc->dev; | |
3261 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3262 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3263 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3264 | i915_reg_t reg; |
3265 | u32 temp; | |
5e84e1a4 ZW |
3266 | |
3267 | /* enable normal train */ | |
3268 | reg = FDI_TX_CTL(pipe); | |
3269 | temp = I915_READ(reg); | |
61e499bf | 3270 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3271 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3272 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3273 | } else { |
3274 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3275 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3276 | } |
5e84e1a4 ZW |
3277 | I915_WRITE(reg, temp); |
3278 | ||
3279 | reg = FDI_RX_CTL(pipe); | |
3280 | temp = I915_READ(reg); | |
3281 | if (HAS_PCH_CPT(dev)) { | |
3282 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3283 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3284 | } else { | |
3285 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3286 | temp |= FDI_LINK_TRAIN_NONE; | |
3287 | } | |
3288 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3289 | ||
3290 | /* wait one idle pattern time */ | |
3291 | POSTING_READ(reg); | |
3292 | udelay(1000); | |
357555c0 JB |
3293 | |
3294 | /* IVB wants error correction enabled */ | |
3295 | if (IS_IVYBRIDGE(dev)) | |
3296 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3297 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3298 | } |
3299 | ||
8db9d77b ZW |
3300 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3301 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3302 | { | |
3303 | struct drm_device *dev = crtc->dev; | |
3304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3305 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3306 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3307 | i915_reg_t reg; |
3308 | u32 temp, tries; | |
8db9d77b | 3309 | |
1c8562f6 | 3310 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3311 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3312 | |
e1a44743 AJ |
3313 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3314 | for train result */ | |
5eddb70b CW |
3315 | reg = FDI_RX_IMR(pipe); |
3316 | temp = I915_READ(reg); | |
e1a44743 AJ |
3317 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3318 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3319 | I915_WRITE(reg, temp); |
3320 | I915_READ(reg); | |
e1a44743 AJ |
3321 | udelay(150); |
3322 | ||
8db9d77b | 3323 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3324 | reg = FDI_TX_CTL(pipe); |
3325 | temp = I915_READ(reg); | |
627eb5a3 | 3326 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3327 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3328 | temp &= ~FDI_LINK_TRAIN_NONE; |
3329 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3330 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3331 | |
5eddb70b CW |
3332 | reg = FDI_RX_CTL(pipe); |
3333 | temp = I915_READ(reg); | |
8db9d77b ZW |
3334 | temp &= ~FDI_LINK_TRAIN_NONE; |
3335 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3336 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3337 | ||
3338 | POSTING_READ(reg); | |
8db9d77b ZW |
3339 | udelay(150); |
3340 | ||
5b2adf89 | 3341 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3342 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3343 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3344 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3345 | |
5eddb70b | 3346 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3347 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3348 | temp = I915_READ(reg); |
8db9d77b ZW |
3349 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3350 | ||
3351 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3352 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3353 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3354 | break; |
3355 | } | |
8db9d77b | 3356 | } |
e1a44743 | 3357 | if (tries == 5) |
5eddb70b | 3358 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3359 | |
3360 | /* Train 2 */ | |
5eddb70b CW |
3361 | reg = FDI_TX_CTL(pipe); |
3362 | temp = I915_READ(reg); | |
8db9d77b ZW |
3363 | temp &= ~FDI_LINK_TRAIN_NONE; |
3364 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3365 | I915_WRITE(reg, temp); |
8db9d77b | 3366 | |
5eddb70b CW |
3367 | reg = FDI_RX_CTL(pipe); |
3368 | temp = I915_READ(reg); | |
8db9d77b ZW |
3369 | temp &= ~FDI_LINK_TRAIN_NONE; |
3370 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3371 | I915_WRITE(reg, temp); |
8db9d77b | 3372 | |
5eddb70b CW |
3373 | POSTING_READ(reg); |
3374 | udelay(150); | |
8db9d77b | 3375 | |
5eddb70b | 3376 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3377 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3378 | temp = I915_READ(reg); |
8db9d77b ZW |
3379 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3380 | ||
3381 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3382 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3383 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3384 | break; | |
3385 | } | |
8db9d77b | 3386 | } |
e1a44743 | 3387 | if (tries == 5) |
5eddb70b | 3388 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3389 | |
3390 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3391 | |
8db9d77b ZW |
3392 | } |
3393 | ||
0206e353 | 3394 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3395 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3396 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3397 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3398 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3399 | }; | |
3400 | ||
3401 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3402 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3403 | { | |
3404 | struct drm_device *dev = crtc->dev; | |
3405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3406 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3407 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3408 | i915_reg_t reg; |
3409 | u32 temp, i, retry; | |
8db9d77b | 3410 | |
e1a44743 AJ |
3411 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3412 | for train result */ | |
5eddb70b CW |
3413 | reg = FDI_RX_IMR(pipe); |
3414 | temp = I915_READ(reg); | |
e1a44743 AJ |
3415 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3416 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3417 | I915_WRITE(reg, temp); |
3418 | ||
3419 | POSTING_READ(reg); | |
e1a44743 AJ |
3420 | udelay(150); |
3421 | ||
8db9d77b | 3422 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3423 | reg = FDI_TX_CTL(pipe); |
3424 | temp = I915_READ(reg); | |
627eb5a3 | 3425 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3426 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3427 | temp &= ~FDI_LINK_TRAIN_NONE; |
3428 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3429 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3430 | /* SNB-B */ | |
3431 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3432 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3433 | |
d74cf324 DV |
3434 | I915_WRITE(FDI_RX_MISC(pipe), |
3435 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3436 | ||
5eddb70b CW |
3437 | reg = FDI_RX_CTL(pipe); |
3438 | temp = I915_READ(reg); | |
8db9d77b ZW |
3439 | if (HAS_PCH_CPT(dev)) { |
3440 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3441 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3442 | } else { | |
3443 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3444 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3445 | } | |
5eddb70b CW |
3446 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3447 | ||
3448 | POSTING_READ(reg); | |
8db9d77b ZW |
3449 | udelay(150); |
3450 | ||
0206e353 | 3451 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3452 | reg = FDI_TX_CTL(pipe); |
3453 | temp = I915_READ(reg); | |
8db9d77b ZW |
3454 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3455 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3456 | I915_WRITE(reg, temp); |
3457 | ||
3458 | POSTING_READ(reg); | |
8db9d77b ZW |
3459 | udelay(500); |
3460 | ||
fa37d39e SP |
3461 | for (retry = 0; retry < 5; retry++) { |
3462 | reg = FDI_RX_IIR(pipe); | |
3463 | temp = I915_READ(reg); | |
3464 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3465 | if (temp & FDI_RX_BIT_LOCK) { | |
3466 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3467 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3468 | break; | |
3469 | } | |
3470 | udelay(50); | |
8db9d77b | 3471 | } |
fa37d39e SP |
3472 | if (retry < 5) |
3473 | break; | |
8db9d77b ZW |
3474 | } |
3475 | if (i == 4) | |
5eddb70b | 3476 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3477 | |
3478 | /* Train 2 */ | |
5eddb70b CW |
3479 | reg = FDI_TX_CTL(pipe); |
3480 | temp = I915_READ(reg); | |
8db9d77b ZW |
3481 | temp &= ~FDI_LINK_TRAIN_NONE; |
3482 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3483 | if (IS_GEN6(dev)) { | |
3484 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3485 | /* SNB-B */ | |
3486 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3487 | } | |
5eddb70b | 3488 | I915_WRITE(reg, temp); |
8db9d77b | 3489 | |
5eddb70b CW |
3490 | reg = FDI_RX_CTL(pipe); |
3491 | temp = I915_READ(reg); | |
8db9d77b ZW |
3492 | if (HAS_PCH_CPT(dev)) { |
3493 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3494 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3495 | } else { | |
3496 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3497 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3498 | } | |
5eddb70b CW |
3499 | I915_WRITE(reg, temp); |
3500 | ||
3501 | POSTING_READ(reg); | |
8db9d77b ZW |
3502 | udelay(150); |
3503 | ||
0206e353 | 3504 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3505 | reg = FDI_TX_CTL(pipe); |
3506 | temp = I915_READ(reg); | |
8db9d77b ZW |
3507 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3508 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3509 | I915_WRITE(reg, temp); |
3510 | ||
3511 | POSTING_READ(reg); | |
8db9d77b ZW |
3512 | udelay(500); |
3513 | ||
fa37d39e SP |
3514 | for (retry = 0; retry < 5; retry++) { |
3515 | reg = FDI_RX_IIR(pipe); | |
3516 | temp = I915_READ(reg); | |
3517 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3518 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3519 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3520 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3521 | break; | |
3522 | } | |
3523 | udelay(50); | |
8db9d77b | 3524 | } |
fa37d39e SP |
3525 | if (retry < 5) |
3526 | break; | |
8db9d77b ZW |
3527 | } |
3528 | if (i == 4) | |
5eddb70b | 3529 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3530 | |
3531 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3532 | } | |
3533 | ||
357555c0 JB |
3534 | /* Manual link training for Ivy Bridge A0 parts */ |
3535 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3536 | { | |
3537 | struct drm_device *dev = crtc->dev; | |
3538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3539 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3540 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3541 | i915_reg_t reg; |
3542 | u32 temp, i, j; | |
357555c0 JB |
3543 | |
3544 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3545 | for train result */ | |
3546 | reg = FDI_RX_IMR(pipe); | |
3547 | temp = I915_READ(reg); | |
3548 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3549 | temp &= ~FDI_RX_BIT_LOCK; | |
3550 | I915_WRITE(reg, temp); | |
3551 | ||
3552 | POSTING_READ(reg); | |
3553 | udelay(150); | |
3554 | ||
01a415fd DV |
3555 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3556 | I915_READ(FDI_RX_IIR(pipe))); | |
3557 | ||
139ccd3f JB |
3558 | /* Try each vswing and preemphasis setting twice before moving on */ |
3559 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3560 | /* disable first in case we need to retry */ | |
3561 | reg = FDI_TX_CTL(pipe); | |
3562 | temp = I915_READ(reg); | |
3563 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3564 | temp &= ~FDI_TX_ENABLE; | |
3565 | I915_WRITE(reg, temp); | |
357555c0 | 3566 | |
139ccd3f JB |
3567 | reg = FDI_RX_CTL(pipe); |
3568 | temp = I915_READ(reg); | |
3569 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3570 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3571 | temp &= ~FDI_RX_ENABLE; | |
3572 | I915_WRITE(reg, temp); | |
357555c0 | 3573 | |
139ccd3f | 3574 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3575 | reg = FDI_TX_CTL(pipe); |
3576 | temp = I915_READ(reg); | |
139ccd3f | 3577 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3578 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3579 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3580 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3581 | temp |= snb_b_fdi_train_param[j/2]; |
3582 | temp |= FDI_COMPOSITE_SYNC; | |
3583 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3584 | |
139ccd3f JB |
3585 | I915_WRITE(FDI_RX_MISC(pipe), |
3586 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3587 | |
139ccd3f | 3588 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3589 | temp = I915_READ(reg); |
139ccd3f JB |
3590 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3591 | temp |= FDI_COMPOSITE_SYNC; | |
3592 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3593 | |
139ccd3f JB |
3594 | POSTING_READ(reg); |
3595 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3596 | |
139ccd3f JB |
3597 | for (i = 0; i < 4; i++) { |
3598 | reg = FDI_RX_IIR(pipe); | |
3599 | temp = I915_READ(reg); | |
3600 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3601 | |
139ccd3f JB |
3602 | if (temp & FDI_RX_BIT_LOCK || |
3603 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3604 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3605 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3606 | i); | |
3607 | break; | |
3608 | } | |
3609 | udelay(1); /* should be 0.5us */ | |
3610 | } | |
3611 | if (i == 4) { | |
3612 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3613 | continue; | |
3614 | } | |
357555c0 | 3615 | |
139ccd3f | 3616 | /* Train 2 */ |
357555c0 JB |
3617 | reg = FDI_TX_CTL(pipe); |
3618 | temp = I915_READ(reg); | |
139ccd3f JB |
3619 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3620 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3621 | I915_WRITE(reg, temp); | |
3622 | ||
3623 | reg = FDI_RX_CTL(pipe); | |
3624 | temp = I915_READ(reg); | |
3625 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3626 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3627 | I915_WRITE(reg, temp); |
3628 | ||
3629 | POSTING_READ(reg); | |
139ccd3f | 3630 | udelay(2); /* should be 1.5us */ |
357555c0 | 3631 | |
139ccd3f JB |
3632 | for (i = 0; i < 4; i++) { |
3633 | reg = FDI_RX_IIR(pipe); | |
3634 | temp = I915_READ(reg); | |
3635 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3636 | |
139ccd3f JB |
3637 | if (temp & FDI_RX_SYMBOL_LOCK || |
3638 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3639 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3640 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3641 | i); | |
3642 | goto train_done; | |
3643 | } | |
3644 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3645 | } |
139ccd3f JB |
3646 | if (i == 4) |
3647 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3648 | } |
357555c0 | 3649 | |
139ccd3f | 3650 | train_done: |
357555c0 JB |
3651 | DRM_DEBUG_KMS("FDI train done.\n"); |
3652 | } | |
3653 | ||
88cefb6c | 3654 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3655 | { |
88cefb6c | 3656 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3657 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3658 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3659 | i915_reg_t reg; |
3660 | u32 temp; | |
c64e311e | 3661 | |
c98e9dcf | 3662 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3663 | reg = FDI_RX_CTL(pipe); |
3664 | temp = I915_READ(reg); | |
627eb5a3 | 3665 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3666 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3667 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3668 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3669 | ||
3670 | POSTING_READ(reg); | |
c98e9dcf JB |
3671 | udelay(200); |
3672 | ||
3673 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3674 | temp = I915_READ(reg); |
3675 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3676 | ||
3677 | POSTING_READ(reg); | |
c98e9dcf JB |
3678 | udelay(200); |
3679 | ||
20749730 PZ |
3680 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3681 | reg = FDI_TX_CTL(pipe); | |
3682 | temp = I915_READ(reg); | |
3683 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3684 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3685 | |
20749730 PZ |
3686 | POSTING_READ(reg); |
3687 | udelay(100); | |
6be4a607 | 3688 | } |
0e23b99d JB |
3689 | } |
3690 | ||
88cefb6c DV |
3691 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3692 | { | |
3693 | struct drm_device *dev = intel_crtc->base.dev; | |
3694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3695 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3696 | i915_reg_t reg; |
3697 | u32 temp; | |
88cefb6c DV |
3698 | |
3699 | /* Switch from PCDclk to Rawclk */ | |
3700 | reg = FDI_RX_CTL(pipe); | |
3701 | temp = I915_READ(reg); | |
3702 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3703 | ||
3704 | /* Disable CPU FDI TX PLL */ | |
3705 | reg = FDI_TX_CTL(pipe); | |
3706 | temp = I915_READ(reg); | |
3707 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3708 | ||
3709 | POSTING_READ(reg); | |
3710 | udelay(100); | |
3711 | ||
3712 | reg = FDI_RX_CTL(pipe); | |
3713 | temp = I915_READ(reg); | |
3714 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3715 | ||
3716 | /* Wait for the clocks to turn off. */ | |
3717 | POSTING_READ(reg); | |
3718 | udelay(100); | |
3719 | } | |
3720 | ||
0fc932b8 JB |
3721 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3722 | { | |
3723 | struct drm_device *dev = crtc->dev; | |
3724 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3726 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3727 | i915_reg_t reg; |
3728 | u32 temp; | |
0fc932b8 JB |
3729 | |
3730 | /* disable CPU FDI tx and PCH FDI rx */ | |
3731 | reg = FDI_TX_CTL(pipe); | |
3732 | temp = I915_READ(reg); | |
3733 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3734 | POSTING_READ(reg); | |
3735 | ||
3736 | reg = FDI_RX_CTL(pipe); | |
3737 | temp = I915_READ(reg); | |
3738 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3739 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3740 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3741 | ||
3742 | POSTING_READ(reg); | |
3743 | udelay(100); | |
3744 | ||
3745 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3746 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3747 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3748 | |
3749 | /* still set train pattern 1 */ | |
3750 | reg = FDI_TX_CTL(pipe); | |
3751 | temp = I915_READ(reg); | |
3752 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3753 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3754 | I915_WRITE(reg, temp); | |
3755 | ||
3756 | reg = FDI_RX_CTL(pipe); | |
3757 | temp = I915_READ(reg); | |
3758 | if (HAS_PCH_CPT(dev)) { | |
3759 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3760 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3761 | } else { | |
3762 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3763 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3764 | } | |
3765 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3766 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3767 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3768 | I915_WRITE(reg, temp); |
3769 | ||
3770 | POSTING_READ(reg); | |
3771 | udelay(100); | |
3772 | } | |
3773 | ||
5dce5b93 CW |
3774 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3775 | { | |
3776 | struct intel_crtc *crtc; | |
3777 | ||
3778 | /* Note that we don't need to be called with mode_config.lock here | |
3779 | * as our list of CRTC objects is static for the lifetime of the | |
3780 | * device and so cannot disappear as we iterate. Similarly, we can | |
3781 | * happily treat the predicates as racy, atomic checks as userspace | |
3782 | * cannot claim and pin a new fb without at least acquring the | |
3783 | * struct_mutex and so serialising with us. | |
3784 | */ | |
d3fcc808 | 3785 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3786 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3787 | continue; | |
3788 | ||
3789 | if (crtc->unpin_work) | |
3790 | intel_wait_for_vblank(dev, crtc->pipe); | |
3791 | ||
3792 | return true; | |
3793 | } | |
3794 | ||
3795 | return false; | |
3796 | } | |
3797 | ||
d6bbafa1 CW |
3798 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3799 | { | |
3800 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3801 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3802 | ||
3803 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3804 | smp_rmb(); | |
3805 | intel_crtc->unpin_work = NULL; | |
3806 | ||
3807 | if (work->event) | |
3808 | drm_send_vblank_event(intel_crtc->base.dev, | |
3809 | intel_crtc->pipe, | |
3810 | work->event); | |
3811 | ||
3812 | drm_crtc_vblank_put(&intel_crtc->base); | |
3813 | ||
3814 | wake_up_all(&dev_priv->pending_flip_queue); | |
3815 | queue_work(dev_priv->wq, &work->work); | |
3816 | ||
3817 | trace_i915_flip_complete(intel_crtc->plane, | |
3818 | work->pending_flip_obj); | |
3819 | } | |
3820 | ||
5008e874 | 3821 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3822 | { |
0f91128d | 3823 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3824 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3825 | long ret; |
e6c3a2a6 | 3826 | |
2c10d571 | 3827 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3828 | |
3829 | ret = wait_event_interruptible_timeout( | |
3830 | dev_priv->pending_flip_queue, | |
3831 | !intel_crtc_has_pending_flip(crtc), | |
3832 | 60*HZ); | |
3833 | ||
3834 | if (ret < 0) | |
3835 | return ret; | |
3836 | ||
3837 | if (ret == 0) { | |
9c787942 | 3838 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3839 | |
5e2d7afc | 3840 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3841 | if (intel_crtc->unpin_work) { |
3842 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3843 | page_flip_completed(intel_crtc); | |
3844 | } | |
5e2d7afc | 3845 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3846 | } |
5bb61643 | 3847 | |
5008e874 | 3848 | return 0; |
e6c3a2a6 CW |
3849 | } |
3850 | ||
060f02d8 VS |
3851 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3852 | { | |
3853 | u32 temp; | |
3854 | ||
3855 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3856 | ||
3857 | mutex_lock(&dev_priv->sb_lock); | |
3858 | ||
3859 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3860 | temp |= SBI_SSCCTL_DISABLE; | |
3861 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3862 | ||
3863 | mutex_unlock(&dev_priv->sb_lock); | |
3864 | } | |
3865 | ||
e615efe4 ED |
3866 | /* Program iCLKIP clock to the desired frequency */ |
3867 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3868 | { | |
64b46a06 | 3869 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 3870 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3871 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3872 | u32 temp; | |
3873 | ||
060f02d8 | 3874 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 3875 | |
64b46a06 VS |
3876 | /* The iCLK virtual clock root frequency is in MHz, |
3877 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3878 | * divisors, it is necessary to divide one by another, so we | |
3879 | * convert the virtual clock precision to KHz here for higher | |
3880 | * precision. | |
3881 | */ | |
3882 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
3883 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3884 | u32 iclk_pi_range = 64; | |
64b46a06 | 3885 | u32 desired_divisor; |
e615efe4 | 3886 | |
64b46a06 VS |
3887 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
3888 | clock << auxdiv); | |
3889 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3890 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 3891 | |
64b46a06 VS |
3892 | /* |
3893 | * Near 20MHz is a corner case which is | |
3894 | * out of range for the 7-bit divisor | |
3895 | */ | |
3896 | if (divsel <= 0x7f) | |
3897 | break; | |
e615efe4 ED |
3898 | } |
3899 | ||
3900 | /* This should not happen with any sane values */ | |
3901 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3902 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3903 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3904 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3905 | ||
3906 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3907 | clock, |
e615efe4 ED |
3908 | auxdiv, |
3909 | divsel, | |
3910 | phasedir, | |
3911 | phaseinc); | |
3912 | ||
060f02d8 VS |
3913 | mutex_lock(&dev_priv->sb_lock); |
3914 | ||
e615efe4 | 3915 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 3916 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3917 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3918 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3919 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3920 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3921 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3922 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3923 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3924 | |
3925 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3926 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3927 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3928 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3929 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3930 | |
3931 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3932 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3933 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3934 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 3935 | |
060f02d8 VS |
3936 | mutex_unlock(&dev_priv->sb_lock); |
3937 | ||
e615efe4 ED |
3938 | /* Wait for initialization time */ |
3939 | udelay(24); | |
3940 | ||
3941 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3942 | } | |
3943 | ||
8802e5b6 VS |
3944 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
3945 | { | |
3946 | u32 divsel, phaseinc, auxdiv; | |
3947 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3948 | u32 iclk_pi_range = 64; | |
3949 | u32 desired_divisor; | |
3950 | u32 temp; | |
3951 | ||
3952 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
3953 | return 0; | |
3954 | ||
3955 | mutex_lock(&dev_priv->sb_lock); | |
3956 | ||
3957 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3958 | if (temp & SBI_SSCCTL_DISABLE) { | |
3959 | mutex_unlock(&dev_priv->sb_lock); | |
3960 | return 0; | |
3961 | } | |
3962 | ||
3963 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
3964 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
3965 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
3966 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
3967 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
3968 | ||
3969 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
3970 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
3971 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
3972 | ||
3973 | mutex_unlock(&dev_priv->sb_lock); | |
3974 | ||
3975 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
3976 | ||
3977 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
3978 | desired_divisor << auxdiv); | |
3979 | } | |
3980 | ||
275f01b2 DV |
3981 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3982 | enum pipe pch_transcoder) | |
3983 | { | |
3984 | struct drm_device *dev = crtc->base.dev; | |
3985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3986 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3987 | |
3988 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3989 | I915_READ(HTOTAL(cpu_transcoder))); | |
3990 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3991 | I915_READ(HBLANK(cpu_transcoder))); | |
3992 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3993 | I915_READ(HSYNC(cpu_transcoder))); | |
3994 | ||
3995 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3996 | I915_READ(VTOTAL(cpu_transcoder))); | |
3997 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3998 | I915_READ(VBLANK(cpu_transcoder))); | |
3999 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4000 | I915_READ(VSYNC(cpu_transcoder))); | |
4001 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4002 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4003 | } | |
4004 | ||
003632d9 | 4005 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4006 | { |
4007 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4008 | uint32_t temp; | |
4009 | ||
4010 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4011 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4012 | return; |
4013 | ||
4014 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4015 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4016 | ||
003632d9 ACO |
4017 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4018 | if (enable) | |
4019 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4020 | ||
4021 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4022 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4023 | POSTING_READ(SOUTH_CHICKEN1); | |
4024 | } | |
4025 | ||
4026 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4027 | { | |
4028 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4029 | |
4030 | switch (intel_crtc->pipe) { | |
4031 | case PIPE_A: | |
4032 | break; | |
4033 | case PIPE_B: | |
6e3c9717 | 4034 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4035 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4036 | else |
003632d9 | 4037 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4038 | |
4039 | break; | |
4040 | case PIPE_C: | |
003632d9 | 4041 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4042 | |
4043 | break; | |
4044 | default: | |
4045 | BUG(); | |
4046 | } | |
4047 | } | |
4048 | ||
c48b5305 VS |
4049 | /* Return which DP Port should be selected for Transcoder DP control */ |
4050 | static enum port | |
4051 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4052 | { | |
4053 | struct drm_device *dev = crtc->dev; | |
4054 | struct intel_encoder *encoder; | |
4055 | ||
4056 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4057 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4058 | encoder->type == INTEL_OUTPUT_EDP) | |
4059 | return enc_to_dig_port(&encoder->base)->port; | |
4060 | } | |
4061 | ||
4062 | return -1; | |
4063 | } | |
4064 | ||
f67a559d JB |
4065 | /* |
4066 | * Enable PCH resources required for PCH ports: | |
4067 | * - PCH PLLs | |
4068 | * - FDI training & RX/TX | |
4069 | * - update transcoder timings | |
4070 | * - DP transcoding bits | |
4071 | * - transcoder | |
4072 | */ | |
4073 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4074 | { |
4075 | struct drm_device *dev = crtc->dev; | |
4076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4078 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4079 | u32 temp; |
2c07245f | 4080 | |
ab9412ba | 4081 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4082 | |
1fbc0d78 DV |
4083 | if (IS_IVYBRIDGE(dev)) |
4084 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4085 | ||
cd986abb DV |
4086 | /* Write the TU size bits before fdi link training, so that error |
4087 | * detection works. */ | |
4088 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4089 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4090 | ||
c98e9dcf | 4091 | /* For PCH output, training FDI link */ |
674cf967 | 4092 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4093 | |
3ad8a208 DV |
4094 | /* We need to program the right clock selection before writing the pixel |
4095 | * mutliplier into the DPLL. */ | |
303b81e0 | 4096 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4097 | u32 sel; |
4b645f14 | 4098 | |
c98e9dcf | 4099 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4100 | temp |= TRANS_DPLL_ENABLE(pipe); |
4101 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4102 | if (intel_crtc->config->shared_dpll == |
4103 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4104 | temp |= sel; |
4105 | else | |
4106 | temp &= ~sel; | |
c98e9dcf | 4107 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4108 | } |
5eddb70b | 4109 | |
3ad8a208 DV |
4110 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4111 | * transcoder, and we actually should do this to not upset any PCH | |
4112 | * transcoder that already use the clock when we share it. | |
4113 | * | |
4114 | * Note that enable_shared_dpll tries to do the right thing, but | |
4115 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4116 | * the right LVDS enable sequence. */ | |
85b3894f | 4117 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4118 | |
d9b6cb56 JB |
4119 | /* set transcoder timing, panel must allow it */ |
4120 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4121 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4122 | |
303b81e0 | 4123 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4124 | |
c98e9dcf | 4125 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4126 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4127 | const struct drm_display_mode *adjusted_mode = |
4128 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4129 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4130 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4131 | temp = I915_READ(reg); |
4132 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4133 | TRANS_DP_SYNC_MASK | |
4134 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4135 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4136 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4137 | |
9c4edaee | 4138 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4139 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4140 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4141 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4142 | |
4143 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4144 | case PORT_B: |
5eddb70b | 4145 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4146 | break; |
c48b5305 | 4147 | case PORT_C: |
5eddb70b | 4148 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4149 | break; |
c48b5305 | 4150 | case PORT_D: |
5eddb70b | 4151 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4152 | break; |
4153 | default: | |
e95d41e1 | 4154 | BUG(); |
32f9d658 | 4155 | } |
2c07245f | 4156 | |
5eddb70b | 4157 | I915_WRITE(reg, temp); |
6be4a607 | 4158 | } |
b52eb4dc | 4159 | |
b8a4f404 | 4160 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4161 | } |
4162 | ||
1507e5bd PZ |
4163 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4164 | { | |
4165 | struct drm_device *dev = crtc->dev; | |
4166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4167 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4168 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4169 | |
ab9412ba | 4170 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4171 | |
8c52b5e8 | 4172 | lpt_program_iclkip(crtc); |
1507e5bd | 4173 | |
0540e488 | 4174 | /* Set transcoder timing. */ |
275f01b2 | 4175 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4176 | |
937bb610 | 4177 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4178 | } |
4179 | ||
a1520318 | 4180 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4181 | { |
4182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4183 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4184 | u32 temp; |
4185 | ||
4186 | temp = I915_READ(dslreg); | |
4187 | udelay(500); | |
4188 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4189 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4190 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4191 | } |
4192 | } | |
4193 | ||
86adf9d7 ML |
4194 | static int |
4195 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4196 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4197 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4198 | { |
86adf9d7 ML |
4199 | struct intel_crtc_scaler_state *scaler_state = |
4200 | &crtc_state->scaler_state; | |
4201 | struct intel_crtc *intel_crtc = | |
4202 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4203 | int need_scaling; |
6156a456 CK |
4204 | |
4205 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4206 | (src_h != dst_w || src_w != dst_h): | |
4207 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4208 | |
4209 | /* | |
4210 | * if plane is being disabled or scaler is no more required or force detach | |
4211 | * - free scaler binded to this plane/crtc | |
4212 | * - in order to do this, update crtc->scaler_usage | |
4213 | * | |
4214 | * Here scaler state in crtc_state is set free so that | |
4215 | * scaler can be assigned to other user. Actual register | |
4216 | * update to free the scaler is done in plane/panel-fit programming. | |
4217 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4218 | */ | |
86adf9d7 | 4219 | if (force_detach || !need_scaling) { |
a1b2278e | 4220 | if (*scaler_id >= 0) { |
86adf9d7 | 4221 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4222 | scaler_state->scalers[*scaler_id].in_use = 0; |
4223 | ||
86adf9d7 ML |
4224 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4225 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4226 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4227 | scaler_state->scaler_users); |
4228 | *scaler_id = -1; | |
4229 | } | |
4230 | return 0; | |
4231 | } | |
4232 | ||
4233 | /* range checks */ | |
4234 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4235 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4236 | ||
4237 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4238 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4239 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4240 | "size is out of scaler range\n", |
86adf9d7 | 4241 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4242 | return -EINVAL; |
4243 | } | |
4244 | ||
86adf9d7 ML |
4245 | /* mark this plane as a scaler user in crtc_state */ |
4246 | scaler_state->scaler_users |= (1 << scaler_user); | |
4247 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4248 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4249 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4250 | scaler_state->scaler_users); | |
4251 | ||
4252 | return 0; | |
4253 | } | |
4254 | ||
4255 | /** | |
4256 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4257 | * | |
4258 | * @state: crtc's scaler state | |
86adf9d7 ML |
4259 | * |
4260 | * Return | |
4261 | * 0 - scaler_usage updated successfully | |
4262 | * error - requested scaling cannot be supported or other error condition | |
4263 | */ | |
e435d6e5 | 4264 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4265 | { |
4266 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4267 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4268 | |
4269 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4270 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4271 | ||
e435d6e5 | 4272 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4273 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4274 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4275 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4276 | } |
4277 | ||
4278 | /** | |
4279 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4280 | * | |
4281 | * @state: crtc's scaler state | |
86adf9d7 ML |
4282 | * @plane_state: atomic plane state to update |
4283 | * | |
4284 | * Return | |
4285 | * 0 - scaler_usage updated successfully | |
4286 | * error - requested scaling cannot be supported or other error condition | |
4287 | */ | |
da20eabd ML |
4288 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4289 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4290 | { |
4291 | ||
4292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4293 | struct intel_plane *intel_plane = |
4294 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4295 | struct drm_framebuffer *fb = plane_state->base.fb; |
4296 | int ret; | |
4297 | ||
4298 | bool force_detach = !fb || !plane_state->visible; | |
4299 | ||
4300 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4301 | intel_plane->base.base.id, intel_crtc->pipe, | |
4302 | drm_plane_index(&intel_plane->base)); | |
4303 | ||
4304 | ret = skl_update_scaler(crtc_state, force_detach, | |
4305 | drm_plane_index(&intel_plane->base), | |
4306 | &plane_state->scaler_id, | |
4307 | plane_state->base.rotation, | |
4308 | drm_rect_width(&plane_state->src) >> 16, | |
4309 | drm_rect_height(&plane_state->src) >> 16, | |
4310 | drm_rect_width(&plane_state->dst), | |
4311 | drm_rect_height(&plane_state->dst)); | |
4312 | ||
4313 | if (ret || plane_state->scaler_id < 0) | |
4314 | return ret; | |
4315 | ||
a1b2278e | 4316 | /* check colorkey */ |
818ed961 | 4317 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4318 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4319 | intel_plane->base.base.id); |
a1b2278e CK |
4320 | return -EINVAL; |
4321 | } | |
4322 | ||
4323 | /* Check src format */ | |
86adf9d7 ML |
4324 | switch (fb->pixel_format) { |
4325 | case DRM_FORMAT_RGB565: | |
4326 | case DRM_FORMAT_XBGR8888: | |
4327 | case DRM_FORMAT_XRGB8888: | |
4328 | case DRM_FORMAT_ABGR8888: | |
4329 | case DRM_FORMAT_ARGB8888: | |
4330 | case DRM_FORMAT_XRGB2101010: | |
4331 | case DRM_FORMAT_XBGR2101010: | |
4332 | case DRM_FORMAT_YUYV: | |
4333 | case DRM_FORMAT_YVYU: | |
4334 | case DRM_FORMAT_UYVY: | |
4335 | case DRM_FORMAT_VYUY: | |
4336 | break; | |
4337 | default: | |
4338 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4339 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4340 | return -EINVAL; | |
a1b2278e CK |
4341 | } |
4342 | ||
a1b2278e CK |
4343 | return 0; |
4344 | } | |
4345 | ||
e435d6e5 ML |
4346 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4347 | { | |
4348 | int i; | |
4349 | ||
4350 | for (i = 0; i < crtc->num_scalers; i++) | |
4351 | skl_detach_scaler(crtc, i); | |
4352 | } | |
4353 | ||
4354 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4355 | { |
4356 | struct drm_device *dev = crtc->base.dev; | |
4357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4358 | int pipe = crtc->pipe; | |
a1b2278e CK |
4359 | struct intel_crtc_scaler_state *scaler_state = |
4360 | &crtc->config->scaler_state; | |
4361 | ||
4362 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4363 | ||
6e3c9717 | 4364 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4365 | int id; |
4366 | ||
4367 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4368 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4369 | return; | |
4370 | } | |
4371 | ||
4372 | id = scaler_state->scaler_id; | |
4373 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4374 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4375 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4376 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4377 | ||
4378 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4379 | } |
4380 | } | |
4381 | ||
b074cec8 JB |
4382 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4383 | { | |
4384 | struct drm_device *dev = crtc->base.dev; | |
4385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4386 | int pipe = crtc->pipe; | |
4387 | ||
6e3c9717 | 4388 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4389 | /* Force use of hard-coded filter coefficients |
4390 | * as some pre-programmed values are broken, | |
4391 | * e.g. x201. | |
4392 | */ | |
4393 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4394 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4395 | PF_PIPE_SEL_IVB(pipe)); | |
4396 | else | |
4397 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4398 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4399 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4400 | } |
4401 | } | |
4402 | ||
20bc8673 | 4403 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4404 | { |
cea165c3 VS |
4405 | struct drm_device *dev = crtc->base.dev; |
4406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4407 | |
6e3c9717 | 4408 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4409 | return; |
4410 | ||
307e4498 ML |
4411 | /* |
4412 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4413 | * This function is called from post_plane_update, which is run after | |
4414 | * a vblank wait. | |
4415 | */ | |
cea165c3 | 4416 | |
d77e4531 | 4417 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4418 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4419 | mutex_lock(&dev_priv->rps.hw_lock); |
4420 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4421 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4422 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4423 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4424 | * mailbox." Moreover, the mailbox may return a bogus state, |
4425 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4426 | */ |
4427 | } else { | |
4428 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4429 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4430 | * is essentially intel_wait_for_vblank. If we don't have this | |
4431 | * and don't wait for vblanks until the end of crtc_enable, then | |
4432 | * the HW state readout code will complain that the expected | |
4433 | * IPS_CTL value is not the one we read. */ | |
4434 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4435 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4436 | } | |
d77e4531 PZ |
4437 | } |
4438 | ||
20bc8673 | 4439 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4440 | { |
4441 | struct drm_device *dev = crtc->base.dev; | |
4442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4443 | ||
6e3c9717 | 4444 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4445 | return; |
4446 | ||
4447 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4448 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4449 | mutex_lock(&dev_priv->rps.hw_lock); |
4450 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4451 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4452 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4453 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4454 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4455 | } else { |
2a114cc1 | 4456 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4457 | POSTING_READ(IPS_CTL); |
4458 | } | |
d77e4531 PZ |
4459 | |
4460 | /* We need to wait for a vblank before we can disable the plane. */ | |
4461 | intel_wait_for_vblank(dev, crtc->pipe); | |
4462 | } | |
4463 | ||
7cac945f | 4464 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4465 | { |
7cac945f | 4466 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4467 | struct drm_device *dev = intel_crtc->base.dev; |
4468 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4469 | ||
4470 | mutex_lock(&dev->struct_mutex); | |
4471 | dev_priv->mm.interruptible = false; | |
4472 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4473 | dev_priv->mm.interruptible = true; | |
4474 | mutex_unlock(&dev->struct_mutex); | |
4475 | } | |
4476 | ||
4477 | /* Let userspace switch the overlay on again. In most cases userspace | |
4478 | * has to recompute where to put it anyway. | |
4479 | */ | |
4480 | } | |
4481 | ||
87d4300a ML |
4482 | /** |
4483 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4484 | * @crtc: the CRTC whose primary plane was just enabled | |
4485 | * | |
4486 | * Performs potentially sleeping operations that must be done after the primary | |
4487 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4488 | * called due to an explicit primary plane update, or due to an implicit | |
4489 | * re-enable that is caused when a sprite plane is updated to no longer | |
4490 | * completely hide the primary plane. | |
4491 | */ | |
4492 | static void | |
4493 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4494 | { |
4495 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4496 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4497 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4498 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4499 | |
87d4300a ML |
4500 | /* |
4501 | * FIXME IPS should be fine as long as one plane is | |
4502 | * enabled, but in practice it seems to have problems | |
4503 | * when going from primary only to sprite only and vice | |
4504 | * versa. | |
4505 | */ | |
a5c4d7bc VS |
4506 | hsw_enable_ips(intel_crtc); |
4507 | ||
f99d7069 | 4508 | /* |
87d4300a ML |
4509 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4510 | * So don't enable underrun reporting before at least some planes | |
4511 | * are enabled. | |
4512 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4513 | * but leave the pipe running. | |
f99d7069 | 4514 | */ |
87d4300a ML |
4515 | if (IS_GEN2(dev)) |
4516 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4517 | ||
aca7b684 VS |
4518 | /* Underruns don't always raise interrupts, so check manually. */ |
4519 | intel_check_cpu_fifo_underruns(dev_priv); | |
4520 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4521 | } |
4522 | ||
2622a081 | 4523 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4524 | static void |
4525 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4526 | { |
4527 | struct drm_device *dev = crtc->dev; | |
4528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4529 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4530 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4531 | |
87d4300a ML |
4532 | /* |
4533 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4534 | * So diasble underrun reporting before all the planes get disabled. | |
4535 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4536 | * but leave the pipe running. | |
4537 | */ | |
4538 | if (IS_GEN2(dev)) | |
4539 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4540 | |
2622a081 VS |
4541 | /* |
4542 | * FIXME IPS should be fine as long as one plane is | |
4543 | * enabled, but in practice it seems to have problems | |
4544 | * when going from primary only to sprite only and vice | |
4545 | * versa. | |
4546 | */ | |
4547 | hsw_disable_ips(intel_crtc); | |
4548 | } | |
4549 | ||
4550 | /* FIXME get rid of this and use pre_plane_update */ | |
4551 | static void | |
4552 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4553 | { | |
4554 | struct drm_device *dev = crtc->dev; | |
4555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4556 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4557 | int pipe = intel_crtc->pipe; | |
4558 | ||
4559 | intel_pre_disable_primary(crtc); | |
4560 | ||
87d4300a ML |
4561 | /* |
4562 | * Vblank time updates from the shadow to live plane control register | |
4563 | * are blocked if the memory self-refresh mode is active at that | |
4564 | * moment. So to make sure the plane gets truly disabled, disable | |
4565 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4566 | * will be checked/applied by the HW only at the next frame start | |
4567 | * event which is after the vblank start event, so we need to have a | |
4568 | * wait-for-vblank between disabling the plane and the pipe. | |
4569 | */ | |
262cd2e1 | 4570 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4571 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4572 | dev_priv->wm.vlv.cxsr = false; |
4573 | intel_wait_for_vblank(dev, pipe); | |
4574 | } | |
87d4300a ML |
4575 | } |
4576 | ||
cd202f69 | 4577 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4578 | { |
cd202f69 ML |
4579 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
4580 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
92826fcd ML |
4581 | struct intel_crtc_state *pipe_config = |
4582 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4583 | struct drm_device *dev = crtc->base.dev; |
cd202f69 ML |
4584 | struct drm_plane *primary = crtc->base.primary; |
4585 | struct drm_plane_state *old_pri_state = | |
4586 | drm_atomic_get_existing_plane_state(old_state, primary); | |
ac21b225 | 4587 | |
cd202f69 | 4588 | intel_frontbuffer_flip(dev, pipe_config->fb_bits); |
ac21b225 | 4589 | |
ab1d3a0e | 4590 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4591 | |
caed361d | 4592 | if (pipe_config->update_wm_post && pipe_config->base.active) |
f015c551 VS |
4593 | intel_update_watermarks(&crtc->base); |
4594 | ||
cd202f69 ML |
4595 | if (old_pri_state) { |
4596 | struct intel_plane_state *primary_state = | |
4597 | to_intel_plane_state(primary->state); | |
4598 | struct intel_plane_state *old_primary_state = | |
4599 | to_intel_plane_state(old_pri_state); | |
4600 | ||
31ae71fc ML |
4601 | intel_fbc_post_update(crtc); |
4602 | ||
cd202f69 ML |
4603 | if (primary_state->visible && |
4604 | (needs_modeset(&pipe_config->base) || | |
4605 | !old_primary_state->visible)) | |
4606 | intel_post_enable_primary(&crtc->base); | |
4607 | } | |
ac21b225 ML |
4608 | } |
4609 | ||
5c74cd73 | 4610 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4611 | { |
5c74cd73 | 4612 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4613 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4614 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1d3a0e ML |
4615 | struct intel_crtc_state *pipe_config = |
4616 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4617 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4618 | struct drm_plane *primary = crtc->base.primary; | |
4619 | struct drm_plane_state *old_pri_state = | |
4620 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4621 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4622 | |
5c74cd73 ML |
4623 | if (old_pri_state) { |
4624 | struct intel_plane_state *primary_state = | |
4625 | to_intel_plane_state(primary->state); | |
4626 | struct intel_plane_state *old_primary_state = | |
4627 | to_intel_plane_state(old_pri_state); | |
4628 | ||
31ae71fc ML |
4629 | intel_fbc_pre_update(crtc); |
4630 | ||
5c74cd73 ML |
4631 | if (old_primary_state->visible && |
4632 | (modeset || !primary_state->visible)) | |
4633 | intel_pre_disable_primary(&crtc->base); | |
4634 | } | |
852eb00d | 4635 | |
ab1d3a0e | 4636 | if (pipe_config->disable_cxsr) { |
852eb00d | 4637 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4638 | |
2622a081 VS |
4639 | /* |
4640 | * Vblank time updates from the shadow to live plane control register | |
4641 | * are blocked if the memory self-refresh mode is active at that | |
4642 | * moment. So to make sure the plane gets truly disabled, disable | |
4643 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4644 | * will be checked/applied by the HW only at the next frame start | |
4645 | * event which is after the vblank start event, so we need to have a | |
4646 | * wait-for-vblank between disabling the plane and the pipe. | |
4647 | */ | |
4648 | if (old_crtc_state->base.active) { | |
2dfd178d | 4649 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4650 | dev_priv->wm.vlv.cxsr = false; |
4651 | intel_wait_for_vblank(dev, crtc->pipe); | |
4652 | } | |
852eb00d | 4653 | } |
92826fcd | 4654 | |
ed4a6a7c MR |
4655 | /* |
4656 | * IVB workaround: must disable low power watermarks for at least | |
4657 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4658 | * when scaling is disabled. | |
4659 | * | |
4660 | * WaCxSRDisabledForSpriteScaling:ivb | |
4661 | */ | |
4662 | if (pipe_config->disable_lp_wm) { | |
4663 | ilk_disable_lp_wm(dev); | |
4664 | intel_wait_for_vblank(dev, crtc->pipe); | |
4665 | } | |
4666 | ||
4667 | /* | |
4668 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4669 | * watermark programming here. | |
4670 | */ | |
4671 | if (needs_modeset(&pipe_config->base)) | |
4672 | return; | |
4673 | ||
4674 | /* | |
4675 | * For platforms that support atomic watermarks, program the | |
4676 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4677 | * will be the intermediate values that are safe for both pre- and | |
4678 | * post- vblank; when vblank happens, the 'active' values will be set | |
4679 | * to the final 'target' values and we'll do this again to get the | |
4680 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4681 | * will be the final target values which will get automatically latched | |
4682 | * at vblank time; no further programming will be necessary. | |
4683 | * | |
4684 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4685 | * we'll continue to update watermarks the old way, if flags tell | |
4686 | * us to. | |
4687 | */ | |
4688 | if (dev_priv->display.initial_watermarks != NULL) | |
4689 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4690 | else if (pipe_config->update_wm_pre) |
92826fcd | 4691 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4692 | } |
4693 | ||
d032ffa0 | 4694 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4695 | { |
4696 | struct drm_device *dev = crtc->dev; | |
4697 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4698 | struct drm_plane *p; |
87d4300a ML |
4699 | int pipe = intel_crtc->pipe; |
4700 | ||
7cac945f | 4701 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4702 | |
d032ffa0 ML |
4703 | drm_for_each_plane_mask(p, dev, plane_mask) |
4704 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4705 | |
f99d7069 DV |
4706 | /* |
4707 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4708 | * to compute the mask of flip planes precisely. For the time being | |
4709 | * consider this a flip to a NULL plane. | |
4710 | */ | |
4711 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4712 | } |
4713 | ||
f67a559d JB |
4714 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4715 | { | |
4716 | struct drm_device *dev = crtc->dev; | |
4717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4718 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4719 | struct intel_encoder *encoder; |
f67a559d | 4720 | int pipe = intel_crtc->pipe; |
b95c5321 ML |
4721 | struct intel_crtc_state *pipe_config = |
4722 | to_intel_crtc_state(crtc->state); | |
f67a559d | 4723 | |
53d9f4e9 | 4724 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4725 | return; |
4726 | ||
b2c0593a VS |
4727 | /* |
4728 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4729 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4730 | * | |
4731 | * On ILK we get an occasional spurious CPU pipe underruns | |
4732 | * between eDP port A enable and vdd enable. Also PCH port | |
4733 | * enable seems to result in the occasional CPU pipe underrun. | |
4734 | * | |
4735 | * Spurious PCH underruns also occur during PCH enabling. | |
4736 | */ | |
4737 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
4738 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
4739 | if (intel_crtc->config->has_pch_encoder) |
4740 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4741 | ||
6e3c9717 | 4742 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4743 | intel_prepare_shared_dpll(intel_crtc); |
4744 | ||
6e3c9717 | 4745 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4746 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4747 | |
4748 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4749 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4750 | |
6e3c9717 | 4751 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4752 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4753 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4754 | } |
4755 | ||
4756 | ironlake_set_pipeconf(crtc); | |
4757 | ||
f67a559d | 4758 | intel_crtc->active = true; |
8664281b | 4759 | |
f6736a1a | 4760 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4761 | if (encoder->pre_enable) |
4762 | encoder->pre_enable(encoder); | |
f67a559d | 4763 | |
6e3c9717 | 4764 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4765 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4766 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4767 | * enabling. */ | |
88cefb6c | 4768 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4769 | } else { |
4770 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4771 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4772 | } | |
f67a559d | 4773 | |
b074cec8 | 4774 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4775 | |
9c54c0dd JB |
4776 | /* |
4777 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4778 | * clocks enabled | |
4779 | */ | |
b95c5321 | 4780 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 4781 | |
1d5bf5d9 ID |
4782 | if (dev_priv->display.initial_watermarks != NULL) |
4783 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4784 | intel_enable_pipe(intel_crtc); |
f67a559d | 4785 | |
6e3c9717 | 4786 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4787 | ironlake_pch_enable(crtc); |
c98e9dcf | 4788 | |
f9b61ff6 DV |
4789 | assert_vblank_disabled(crtc); |
4790 | drm_crtc_vblank_on(crtc); | |
4791 | ||
fa5c73b1 DV |
4792 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4793 | encoder->enable(encoder); | |
61b77ddd DV |
4794 | |
4795 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4796 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4797 | |
4798 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4799 | if (intel_crtc->config->has_pch_encoder) | |
4800 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 4801 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 4802 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
4803 | } |
4804 | ||
42db64ef PZ |
4805 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4806 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4807 | { | |
f5adf94e | 4808 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4809 | } |
4810 | ||
4f771f10 PZ |
4811 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4812 | { | |
4813 | struct drm_device *dev = crtc->dev; | |
4814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4815 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4816 | struct intel_encoder *encoder; | |
99d736a2 | 4817 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 4818 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
4819 | struct intel_crtc_state *pipe_config = |
4820 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4821 | |
53d9f4e9 | 4822 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4823 | return; |
4824 | ||
81b088ca VS |
4825 | if (intel_crtc->config->has_pch_encoder) |
4826 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4827 | false); | |
4828 | ||
8106ddbd | 4829 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
4830 | intel_enable_shared_dpll(intel_crtc); |
4831 | ||
6e3c9717 | 4832 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4833 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 4834 | |
4d1de975 JN |
4835 | if (!intel_crtc->config->has_dsi_encoder) |
4836 | intel_set_pipe_timings(intel_crtc); | |
4837 | ||
bc58be60 | 4838 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 4839 | |
4d1de975 JN |
4840 | if (cpu_transcoder != TRANSCODER_EDP && |
4841 | !transcoder_is_dsi(cpu_transcoder)) { | |
4842 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 4843 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
4844 | } |
4845 | ||
6e3c9717 | 4846 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4847 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4848 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4849 | } |
4850 | ||
4d1de975 JN |
4851 | if (!intel_crtc->config->has_dsi_encoder) |
4852 | haswell_set_pipeconf(crtc); | |
4853 | ||
391bf048 | 4854 | haswell_set_pipemisc(crtc); |
229fca97 | 4855 | |
b95c5321 | 4856 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 4857 | |
4f771f10 | 4858 | intel_crtc->active = true; |
8664281b | 4859 | |
6b698516 DV |
4860 | if (intel_crtc->config->has_pch_encoder) |
4861 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4862 | else | |
4863 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4864 | ||
7d4aefd0 | 4865 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4866 | if (encoder->pre_enable) |
4867 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4868 | } |
4f771f10 | 4869 | |
d2d65408 | 4870 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4871 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4872 | |
a65347ba | 4873 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4874 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4875 | |
1c132b44 | 4876 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4877 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4878 | else |
1c132b44 | 4879 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4880 | |
4881 | /* | |
4882 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4883 | * clocks enabled | |
4884 | */ | |
b95c5321 | 4885 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 4886 | |
1f544388 | 4887 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 4888 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4889 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4890 | |
1d5bf5d9 ID |
4891 | if (dev_priv->display.initial_watermarks != NULL) |
4892 | dev_priv->display.initial_watermarks(pipe_config); | |
4893 | else | |
4894 | intel_update_watermarks(crtc); | |
4d1de975 JN |
4895 | |
4896 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
4897 | if (!intel_crtc->config->has_dsi_encoder) | |
4898 | intel_enable_pipe(intel_crtc); | |
42db64ef | 4899 | |
6e3c9717 | 4900 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4901 | lpt_pch_enable(crtc); |
4f771f10 | 4902 | |
a65347ba | 4903 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4904 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4905 | ||
f9b61ff6 DV |
4906 | assert_vblank_disabled(crtc); |
4907 | drm_crtc_vblank_on(crtc); | |
4908 | ||
8807e55b | 4909 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4910 | encoder->enable(encoder); |
8807e55b JN |
4911 | intel_opregion_notify_encoder(encoder, true); |
4912 | } | |
4f771f10 | 4913 | |
6b698516 DV |
4914 | if (intel_crtc->config->has_pch_encoder) { |
4915 | intel_wait_for_vblank(dev, pipe); | |
4916 | intel_wait_for_vblank(dev, pipe); | |
4917 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
4918 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4919 | true); | |
6b698516 | 4920 | } |
d2d65408 | 4921 | |
e4916946 PZ |
4922 | /* If we change the relative order between pipe/planes enabling, we need |
4923 | * to change the workaround. */ | |
99d736a2 ML |
4924 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4925 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4926 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4927 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4928 | } | |
4f771f10 PZ |
4929 | } |
4930 | ||
bfd16b2a | 4931 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4932 | { |
4933 | struct drm_device *dev = crtc->base.dev; | |
4934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4935 | int pipe = crtc->pipe; | |
4936 | ||
4937 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4938 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 4939 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4940 | I915_WRITE(PF_CTL(pipe), 0); |
4941 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4942 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4943 | } | |
4944 | } | |
4945 | ||
6be4a607 JB |
4946 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4947 | { | |
4948 | struct drm_device *dev = crtc->dev; | |
4949 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4950 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4951 | struct intel_encoder *encoder; |
6be4a607 | 4952 | int pipe = intel_crtc->pipe; |
b52eb4dc | 4953 | |
b2c0593a VS |
4954 | /* |
4955 | * Sometimes spurious CPU pipe underruns happen when the | |
4956 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
4957 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
4958 | */ | |
4959 | if (intel_crtc->config->has_pch_encoder) { | |
4960 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 4961 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 4962 | } |
37ca8d4c | 4963 | |
ea9d758d DV |
4964 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4965 | encoder->disable(encoder); | |
4966 | ||
f9b61ff6 DV |
4967 | drm_crtc_vblank_off(crtc); |
4968 | assert_vblank_disabled(crtc); | |
4969 | ||
575f7ab7 | 4970 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4971 | |
bfd16b2a | 4972 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 4973 | |
b2c0593a | 4974 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
4975 | ironlake_fdi_disable(crtc); |
4976 | ||
bf49ec8c DV |
4977 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4978 | if (encoder->post_disable) | |
4979 | encoder->post_disable(encoder); | |
2c07245f | 4980 | |
6e3c9717 | 4981 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4982 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4983 | |
d925c59a | 4984 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
4985 | i915_reg_t reg; |
4986 | u32 temp; | |
4987 | ||
d925c59a DV |
4988 | /* disable TRANS_DP_CTL */ |
4989 | reg = TRANS_DP_CTL(pipe); | |
4990 | temp = I915_READ(reg); | |
4991 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4992 | TRANS_DP_PORT_SEL_MASK); | |
4993 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4994 | I915_WRITE(reg, temp); | |
4995 | ||
4996 | /* disable DPLL_SEL */ | |
4997 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4998 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4999 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5000 | } |
e3421a18 | 5001 | |
d925c59a DV |
5002 | ironlake_fdi_pll_disable(intel_crtc); |
5003 | } | |
81b088ca | 5004 | |
b2c0593a | 5005 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5006 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5007 | } |
1b3c7a47 | 5008 | |
4f771f10 | 5009 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5010 | { |
4f771f10 PZ |
5011 | struct drm_device *dev = crtc->dev; |
5012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5013 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5014 | struct intel_encoder *encoder; |
6e3c9717 | 5015 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5016 | |
d2d65408 VS |
5017 | if (intel_crtc->config->has_pch_encoder) |
5018 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5019 | false); | |
5020 | ||
8807e55b JN |
5021 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5022 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5023 | encoder->disable(encoder); |
8807e55b | 5024 | } |
4f771f10 | 5025 | |
f9b61ff6 DV |
5026 | drm_crtc_vblank_off(crtc); |
5027 | assert_vblank_disabled(crtc); | |
5028 | ||
4d1de975 JN |
5029 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
5030 | if (!intel_crtc->config->has_dsi_encoder) | |
5031 | intel_disable_pipe(intel_crtc); | |
4f771f10 | 5032 | |
6e3c9717 | 5033 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5034 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5035 | ||
a65347ba | 5036 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5037 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5038 | |
1c132b44 | 5039 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5040 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5041 | else |
bfd16b2a | 5042 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5043 | |
a65347ba | 5044 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5045 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5046 | |
97b040aa ID |
5047 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5048 | if (encoder->post_disable) | |
5049 | encoder->post_disable(encoder); | |
81b088ca | 5050 | |
92966a37 VS |
5051 | if (intel_crtc->config->has_pch_encoder) { |
5052 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5053 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5054 | intel_ddi_fdi_disable(crtc); |
5055 | ||
81b088ca VS |
5056 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5057 | true); | |
92966a37 | 5058 | } |
4f771f10 PZ |
5059 | } |
5060 | ||
2dd24552 JB |
5061 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5062 | { | |
5063 | struct drm_device *dev = crtc->base.dev; | |
5064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5065 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5066 | |
681a8504 | 5067 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5068 | return; |
5069 | ||
2dd24552 | 5070 | /* |
c0b03411 DV |
5071 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5072 | * according to register description and PRM. | |
2dd24552 | 5073 | */ |
c0b03411 DV |
5074 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5075 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5076 | |
b074cec8 JB |
5077 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5078 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5079 | |
5080 | /* Border color in case we don't scale up to the full screen. Black by | |
5081 | * default, change to something else for debugging. */ | |
5082 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5083 | } |
5084 | ||
d05410f9 DA |
5085 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5086 | { | |
5087 | switch (port) { | |
5088 | case PORT_A: | |
6331a704 | 5089 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5090 | case PORT_B: |
6331a704 | 5091 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5092 | case PORT_C: |
6331a704 | 5093 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5094 | case PORT_D: |
6331a704 | 5095 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5096 | case PORT_E: |
6331a704 | 5097 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5098 | default: |
b9fec167 | 5099 | MISSING_CASE(port); |
d05410f9 DA |
5100 | return POWER_DOMAIN_PORT_OTHER; |
5101 | } | |
5102 | } | |
5103 | ||
25f78f58 VS |
5104 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5105 | { | |
5106 | switch (port) { | |
5107 | case PORT_A: | |
5108 | return POWER_DOMAIN_AUX_A; | |
5109 | case PORT_B: | |
5110 | return POWER_DOMAIN_AUX_B; | |
5111 | case PORT_C: | |
5112 | return POWER_DOMAIN_AUX_C; | |
5113 | case PORT_D: | |
5114 | return POWER_DOMAIN_AUX_D; | |
5115 | case PORT_E: | |
5116 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5117 | return POWER_DOMAIN_AUX_D; | |
5118 | default: | |
b9fec167 | 5119 | MISSING_CASE(port); |
25f78f58 VS |
5120 | return POWER_DOMAIN_AUX_A; |
5121 | } | |
5122 | } | |
5123 | ||
319be8ae ID |
5124 | enum intel_display_power_domain |
5125 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5126 | { | |
5127 | struct drm_device *dev = intel_encoder->base.dev; | |
5128 | struct intel_digital_port *intel_dig_port; | |
5129 | ||
5130 | switch (intel_encoder->type) { | |
5131 | case INTEL_OUTPUT_UNKNOWN: | |
5132 | /* Only DDI platforms should ever use this output type */ | |
5133 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5134 | case INTEL_OUTPUT_DISPLAYPORT: | |
5135 | case INTEL_OUTPUT_HDMI: | |
5136 | case INTEL_OUTPUT_EDP: | |
5137 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5138 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5139 | case INTEL_OUTPUT_DP_MST: |
5140 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5141 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5142 | case INTEL_OUTPUT_ANALOG: |
5143 | return POWER_DOMAIN_PORT_CRT; | |
5144 | case INTEL_OUTPUT_DSI: | |
5145 | return POWER_DOMAIN_PORT_DSI; | |
5146 | default: | |
5147 | return POWER_DOMAIN_PORT_OTHER; | |
5148 | } | |
5149 | } | |
5150 | ||
25f78f58 VS |
5151 | enum intel_display_power_domain |
5152 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5153 | { | |
5154 | struct drm_device *dev = intel_encoder->base.dev; | |
5155 | struct intel_digital_port *intel_dig_port; | |
5156 | ||
5157 | switch (intel_encoder->type) { | |
5158 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5159 | case INTEL_OUTPUT_HDMI: |
5160 | /* | |
5161 | * Only DDI platforms should ever use these output types. | |
5162 | * We can get here after the HDMI detect code has already set | |
5163 | * the type of the shared encoder. Since we can't be sure | |
5164 | * what's the status of the given connectors, play safe and | |
5165 | * run the DP detection too. | |
5166 | */ | |
25f78f58 VS |
5167 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5168 | case INTEL_OUTPUT_DISPLAYPORT: | |
5169 | case INTEL_OUTPUT_EDP: | |
5170 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5171 | return port_to_aux_power_domain(intel_dig_port->port); | |
5172 | case INTEL_OUTPUT_DP_MST: | |
5173 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5174 | return port_to_aux_power_domain(intel_dig_port->port); | |
5175 | default: | |
b9fec167 | 5176 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5177 | return POWER_DOMAIN_AUX_A; |
5178 | } | |
5179 | } | |
5180 | ||
74bff5f9 ML |
5181 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5182 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5183 | { |
319be8ae | 5184 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5185 | struct drm_encoder *encoder; |
319be8ae ID |
5186 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5187 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5188 | unsigned long mask; |
74bff5f9 | 5189 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5190 | |
74bff5f9 | 5191 | if (!crtc_state->base.active) |
292b990e ML |
5192 | return 0; |
5193 | ||
77d22dca ID |
5194 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5195 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5196 | if (crtc_state->pch_pfit.enabled || |
5197 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5198 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5199 | ||
74bff5f9 ML |
5200 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5201 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5202 | ||
319be8ae | 5203 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5204 | } |
319be8ae | 5205 | |
15e7ec29 ML |
5206 | if (crtc_state->shared_dpll) |
5207 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5208 | ||
77d22dca ID |
5209 | return mask; |
5210 | } | |
5211 | ||
74bff5f9 ML |
5212 | static unsigned long |
5213 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5214 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5215 | { |
292b990e ML |
5216 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5217 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5218 | enum intel_display_power_domain domain; | |
5219 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5220 | |
292b990e | 5221 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5222 | intel_crtc->enabled_power_domains = new_domains = |
5223 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5224 | |
292b990e ML |
5225 | domains = new_domains & ~old_domains; |
5226 | ||
5227 | for_each_power_domain(domain, domains) | |
5228 | intel_display_power_get(dev_priv, domain); | |
5229 | ||
5230 | return old_domains & ~new_domains; | |
5231 | } | |
5232 | ||
5233 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5234 | unsigned long domains) | |
5235 | { | |
5236 | enum intel_display_power_domain domain; | |
5237 | ||
5238 | for_each_power_domain(domain, domains) | |
5239 | intel_display_power_put(dev_priv, domain); | |
5240 | } | |
77d22dca | 5241 | |
adafdc6f MK |
5242 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5243 | { | |
5244 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5245 | ||
5246 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5247 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5248 | return max_cdclk_freq; | |
5249 | else if (IS_CHERRYVIEW(dev_priv)) | |
5250 | return max_cdclk_freq*95/100; | |
5251 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5252 | return 2*max_cdclk_freq*90/100; | |
5253 | else | |
5254 | return max_cdclk_freq*90/100; | |
5255 | } | |
5256 | ||
560a7ae4 DL |
5257 | static void intel_update_max_cdclk(struct drm_device *dev) |
5258 | { | |
5259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5260 | ||
ef11bdb3 | 5261 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5262 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5263 | ||
5264 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5265 | dev_priv->max_cdclk_freq = 675000; | |
5266 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5267 | dev_priv->max_cdclk_freq = 540000; | |
5268 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5269 | dev_priv->max_cdclk_freq = 450000; | |
5270 | else | |
5271 | dev_priv->max_cdclk_freq = 337500; | |
281c114f MR |
5272 | } else if (IS_BROXTON(dev)) { |
5273 | dev_priv->max_cdclk_freq = 624000; | |
560a7ae4 DL |
5274 | } else if (IS_BROADWELL(dev)) { |
5275 | /* | |
5276 | * FIXME with extra cooling we can allow | |
5277 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5278 | * How can we know if extra cooling is | |
5279 | * available? PCI ID, VTB, something else? | |
5280 | */ | |
5281 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5282 | dev_priv->max_cdclk_freq = 450000; | |
5283 | else if (IS_BDW_ULX(dev)) | |
5284 | dev_priv->max_cdclk_freq = 450000; | |
5285 | else if (IS_BDW_ULT(dev)) | |
5286 | dev_priv->max_cdclk_freq = 540000; | |
5287 | else | |
5288 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5289 | } else if (IS_CHERRYVIEW(dev)) { |
5290 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5291 | } else if (IS_VALLEYVIEW(dev)) { |
5292 | dev_priv->max_cdclk_freq = 400000; | |
5293 | } else { | |
5294 | /* otherwise assume cdclk is fixed */ | |
5295 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5296 | } | |
5297 | ||
adafdc6f MK |
5298 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5299 | ||
560a7ae4 DL |
5300 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5301 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5302 | |
5303 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5304 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5305 | } |
5306 | ||
5307 | static void intel_update_cdclk(struct drm_device *dev) | |
5308 | { | |
5309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5310 | ||
5311 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5312 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5313 | dev_priv->cdclk_freq); | |
5314 | ||
5315 | /* | |
5316 | * Program the gmbus_freq based on the cdclk frequency. | |
5317 | * BSpec erroneously claims we should aim for 4MHz, but | |
5318 | * in fact 1MHz is the correct frequency. | |
5319 | */ | |
666a4537 | 5320 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5321 | /* |
5322 | * Program the gmbus_freq based on the cdclk frequency. | |
5323 | * BSpec erroneously claims we should aim for 4MHz, but | |
5324 | * in fact 1MHz is the correct frequency. | |
5325 | */ | |
5326 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5327 | } | |
5328 | ||
5329 | if (dev_priv->max_cdclk_freq == 0) | |
5330 | intel_update_max_cdclk(dev); | |
5331 | } | |
5332 | ||
70d0c574 | 5333 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5334 | { |
5335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5336 | uint32_t divider; | |
5337 | uint32_t ratio; | |
5338 | uint32_t current_freq; | |
5339 | int ret; | |
5340 | ||
5341 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5342 | switch (frequency) { | |
5343 | case 144000: | |
5344 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5345 | ratio = BXT_DE_PLL_RATIO(60); | |
5346 | break; | |
5347 | case 288000: | |
5348 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5349 | ratio = BXT_DE_PLL_RATIO(60); | |
5350 | break; | |
5351 | case 384000: | |
5352 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5353 | ratio = BXT_DE_PLL_RATIO(60); | |
5354 | break; | |
5355 | case 576000: | |
5356 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5357 | ratio = BXT_DE_PLL_RATIO(60); | |
5358 | break; | |
5359 | case 624000: | |
5360 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5361 | ratio = BXT_DE_PLL_RATIO(65); | |
5362 | break; | |
5363 | case 19200: | |
5364 | /* | |
5365 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5366 | * to suppress GCC warning. | |
5367 | */ | |
5368 | ratio = 0; | |
5369 | divider = 0; | |
5370 | break; | |
5371 | default: | |
5372 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5373 | ||
5374 | return; | |
5375 | } | |
5376 | ||
5377 | mutex_lock(&dev_priv->rps.hw_lock); | |
5378 | /* Inform power controller of upcoming frequency change */ | |
5379 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5380 | 0x80000000); | |
5381 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5382 | ||
5383 | if (ret) { | |
5384 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5385 | ret, frequency); | |
5386 | return; | |
5387 | } | |
5388 | ||
5389 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5390 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5391 | current_freq = current_freq * 500 + 1000; | |
5392 | ||
5393 | /* | |
5394 | * DE PLL has to be disabled when | |
5395 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5396 | * - before setting to 624MHz (PLL needs toggling) | |
5397 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5398 | */ | |
5399 | if (frequency == 19200 || frequency == 624000 || | |
5400 | current_freq == 624000) { | |
5401 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5402 | /* Timeout 200us */ | |
5403 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5404 | 1)) | |
5405 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5406 | } | |
5407 | ||
5408 | if (frequency != 19200) { | |
5409 | uint32_t val; | |
5410 | ||
5411 | val = I915_READ(BXT_DE_PLL_CTL); | |
5412 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5413 | val |= ratio; | |
5414 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5415 | ||
5416 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5417 | /* Timeout 200us */ | |
5418 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5419 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5420 | ||
5421 | val = I915_READ(CDCLK_CTL); | |
5422 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5423 | val |= divider; | |
5424 | /* | |
5425 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5426 | * enable otherwise. | |
5427 | */ | |
5428 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5429 | if (frequency >= 500000) | |
5430 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5431 | ||
5432 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5433 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5434 | val |= (frequency - 1000) / 500; | |
5435 | I915_WRITE(CDCLK_CTL, val); | |
5436 | } | |
5437 | ||
5438 | mutex_lock(&dev_priv->rps.hw_lock); | |
5439 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5440 | DIV_ROUND_UP(frequency, 25000)); | |
5441 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5442 | ||
5443 | if (ret) { | |
5444 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5445 | ret, frequency); | |
5446 | return; | |
5447 | } | |
5448 | ||
a47871bd | 5449 | intel_update_cdclk(dev); |
f8437dd1 VK |
5450 | } |
5451 | ||
5452 | void broxton_init_cdclk(struct drm_device *dev) | |
5453 | { | |
5454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5455 | uint32_t val; | |
5456 | ||
5457 | /* | |
5458 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5459 | * or else the reset will hang because there is no PCH to respond. | |
5460 | * Move the handshake programming to initialization sequence. | |
5461 | * Previously was left up to BIOS. | |
5462 | */ | |
5463 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5464 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5465 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5466 | ||
5467 | /* Enable PG1 for cdclk */ | |
5468 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5469 | ||
5470 | /* check if cd clock is enabled */ | |
5471 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5472 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5473 | return; | |
5474 | } | |
5475 | ||
5476 | /* | |
5477 | * FIXME: | |
5478 | * - The initial CDCLK needs to be read from VBT. | |
5479 | * Need to make this change after VBT has changes for BXT. | |
5480 | * - check if setting the max (or any) cdclk freq is really necessary | |
5481 | * here, it belongs to modeset time | |
5482 | */ | |
5483 | broxton_set_cdclk(dev, 624000); | |
5484 | ||
5485 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5486 | POSTING_READ(DBUF_CTL); |
5487 | ||
f8437dd1 VK |
5488 | udelay(10); |
5489 | ||
5490 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5491 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5492 | } | |
5493 | ||
5494 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5495 | { | |
5496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5497 | ||
5498 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5499 | POSTING_READ(DBUF_CTL); |
5500 | ||
f8437dd1 VK |
5501 | udelay(10); |
5502 | ||
5503 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5504 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5505 | ||
5506 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5507 | broxton_set_cdclk(dev, 19200); | |
5508 | ||
5509 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5510 | } | |
5511 | ||
5d96d8af DL |
5512 | static const struct skl_cdclk_entry { |
5513 | unsigned int freq; | |
5514 | unsigned int vco; | |
5515 | } skl_cdclk_frequencies[] = { | |
5516 | { .freq = 308570, .vco = 8640 }, | |
5517 | { .freq = 337500, .vco = 8100 }, | |
5518 | { .freq = 432000, .vco = 8640 }, | |
5519 | { .freq = 450000, .vco = 8100 }, | |
5520 | { .freq = 540000, .vco = 8100 }, | |
5521 | { .freq = 617140, .vco = 8640 }, | |
5522 | { .freq = 675000, .vco = 8100 }, | |
5523 | }; | |
5524 | ||
5525 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5526 | { | |
5527 | return (freq - 1000) / 500; | |
5528 | } | |
5529 | ||
5530 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5531 | { | |
5532 | unsigned int i; | |
5533 | ||
5534 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5535 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5536 | ||
5537 | if (e->freq == freq) | |
5538 | return e->vco; | |
5539 | } | |
5540 | ||
5541 | return 8100; | |
5542 | } | |
5543 | ||
5544 | static void | |
5545 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5546 | { | |
5547 | unsigned int min_freq; | |
5548 | u32 val; | |
5549 | ||
5550 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5551 | val = I915_READ(CDCLK_CTL); | |
5552 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5553 | val |= CDCLK_FREQ_337_308; | |
5554 | ||
5555 | if (required_vco == 8640) | |
5556 | min_freq = 308570; | |
5557 | else | |
5558 | min_freq = 337500; | |
5559 | ||
5560 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5561 | ||
5562 | I915_WRITE(CDCLK_CTL, val); | |
5563 | POSTING_READ(CDCLK_CTL); | |
5564 | ||
5565 | /* | |
5566 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5567 | * taking into account the VCO required to operate the eDP panel at the | |
5568 | * desired frequency. The usual DP link rates operate with a VCO of | |
5569 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5570 | * The modeset code is responsible for the selection of the exact link | |
5571 | * rate later on, with the constraint of choosing a frequency that | |
5572 | * works with required_vco. | |
5573 | */ | |
5574 | val = I915_READ(DPLL_CTRL1); | |
5575 | ||
5576 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5577 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5578 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5579 | if (required_vco == 8640) | |
5580 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5581 | SKL_DPLL0); | |
5582 | else | |
5583 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5584 | SKL_DPLL0); | |
5585 | ||
5586 | I915_WRITE(DPLL_CTRL1, val); | |
5587 | POSTING_READ(DPLL_CTRL1); | |
5588 | ||
5589 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5590 | ||
5591 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5592 | DRM_ERROR("DPLL0 not locked\n"); | |
5593 | } | |
5594 | ||
5595 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5596 | { | |
5597 | int ret; | |
5598 | u32 val; | |
5599 | ||
5600 | /* inform PCU we want to change CDCLK */ | |
5601 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5602 | mutex_lock(&dev_priv->rps.hw_lock); | |
5603 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5604 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5605 | ||
5606 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5607 | } | |
5608 | ||
5609 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5610 | { | |
5611 | unsigned int i; | |
5612 | ||
5613 | for (i = 0; i < 15; i++) { | |
5614 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5615 | return true; | |
5616 | udelay(10); | |
5617 | } | |
5618 | ||
5619 | return false; | |
5620 | } | |
5621 | ||
5622 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5623 | { | |
560a7ae4 | 5624 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5625 | u32 freq_select, pcu_ack; |
5626 | ||
5627 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5628 | ||
5629 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5630 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5631 | return; | |
5632 | } | |
5633 | ||
5634 | /* set CDCLK_CTL */ | |
5635 | switch(freq) { | |
5636 | case 450000: | |
5637 | case 432000: | |
5638 | freq_select = CDCLK_FREQ_450_432; | |
5639 | pcu_ack = 1; | |
5640 | break; | |
5641 | case 540000: | |
5642 | freq_select = CDCLK_FREQ_540; | |
5643 | pcu_ack = 2; | |
5644 | break; | |
5645 | case 308570: | |
5646 | case 337500: | |
5647 | default: | |
5648 | freq_select = CDCLK_FREQ_337_308; | |
5649 | pcu_ack = 0; | |
5650 | break; | |
5651 | case 617140: | |
5652 | case 675000: | |
5653 | freq_select = CDCLK_FREQ_675_617; | |
5654 | pcu_ack = 3; | |
5655 | break; | |
5656 | } | |
5657 | ||
5658 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5659 | POSTING_READ(CDCLK_CTL); | |
5660 | ||
5661 | /* inform PCU of the change */ | |
5662 | mutex_lock(&dev_priv->rps.hw_lock); | |
5663 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5664 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5665 | |
5666 | intel_update_cdclk(dev); | |
5d96d8af DL |
5667 | } |
5668 | ||
5669 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5670 | { | |
5671 | /* disable DBUF power */ | |
5672 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5673 | POSTING_READ(DBUF_CTL); | |
5674 | ||
5675 | udelay(10); | |
5676 | ||
5677 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5678 | DRM_ERROR("DBuf power disable timeout\n"); | |
5679 | ||
ab96c1ee ID |
5680 | /* disable DPLL0 */ |
5681 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5682 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5683 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5684 | } |
5685 | ||
5686 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5687 | { | |
5d96d8af DL |
5688 | unsigned int required_vco; |
5689 | ||
39d9b85a GW |
5690 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5691 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5692 | /* enable DPLL0 */ | |
5693 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5694 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5695 | } |
5696 | ||
5d96d8af DL |
5697 | /* set CDCLK to the frequency the BIOS chose */ |
5698 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5699 | ||
5700 | /* enable DBUF power */ | |
5701 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5702 | POSTING_READ(DBUF_CTL); | |
5703 | ||
5704 | udelay(10); | |
5705 | ||
5706 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5707 | DRM_ERROR("DBuf power enable timeout\n"); | |
5708 | } | |
5709 | ||
c73666f3 SK |
5710 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5711 | { | |
5712 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5713 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5714 | int freq = dev_priv->skl_boot_cdclk; | |
5715 | ||
f1b391a5 SK |
5716 | /* |
5717 | * check if the pre-os intialized the display | |
5718 | * There is SWF18 scratchpad register defined which is set by the | |
5719 | * pre-os which can be used by the OS drivers to check the status | |
5720 | */ | |
5721 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5722 | goto sanitize; | |
5723 | ||
c73666f3 SK |
5724 | /* Is PLL enabled and locked ? */ |
5725 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5726 | goto sanitize; | |
5727 | ||
5728 | /* DPLL okay; verify the cdclock | |
5729 | * | |
5730 | * Noticed in some instances that the freq selection is correct but | |
5731 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5732 | * enable display. Verify the same as well. | |
5733 | */ | |
5734 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5735 | /* All well; nothing to sanitize */ | |
5736 | return false; | |
5737 | sanitize: | |
5738 | /* | |
5739 | * As of now initialize with max cdclk till | |
5740 | * we get dynamic cdclk support | |
5741 | * */ | |
5742 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5743 | skl_init_cdclk(dev_priv); | |
5744 | ||
5745 | /* we did have to sanitize */ | |
5746 | return true; | |
5747 | } | |
5748 | ||
30a970c6 JB |
5749 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5750 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5751 | { | |
5752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5753 | u32 val, cmd; | |
5754 | ||
164dfd28 VK |
5755 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5756 | != dev_priv->cdclk_freq); | |
d60c4473 | 5757 | |
dfcab17e | 5758 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5759 | cmd = 2; |
dfcab17e | 5760 | else if (cdclk == 266667) |
30a970c6 JB |
5761 | cmd = 1; |
5762 | else | |
5763 | cmd = 0; | |
5764 | ||
5765 | mutex_lock(&dev_priv->rps.hw_lock); | |
5766 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5767 | val &= ~DSPFREQGUAR_MASK; | |
5768 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5769 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5770 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5771 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5772 | 50)) { | |
5773 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5774 | } | |
5775 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5776 | ||
54433e91 VS |
5777 | mutex_lock(&dev_priv->sb_lock); |
5778 | ||
dfcab17e | 5779 | if (cdclk == 400000) { |
6bcda4f0 | 5780 | u32 divider; |
30a970c6 | 5781 | |
6bcda4f0 | 5782 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5783 | |
30a970c6 JB |
5784 | /* adjust cdclk divider */ |
5785 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5786 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5787 | val |= divider; |
5788 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5789 | |
5790 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5791 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5792 | 50)) |
5793 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5794 | } |
5795 | ||
30a970c6 JB |
5796 | /* adjust self-refresh exit latency value */ |
5797 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5798 | val &= ~0x7f; | |
5799 | ||
5800 | /* | |
5801 | * For high bandwidth configs, we set a higher latency in the bunit | |
5802 | * so that the core display fetch happens in time to avoid underruns. | |
5803 | */ | |
dfcab17e | 5804 | if (cdclk == 400000) |
30a970c6 JB |
5805 | val |= 4500 / 250; /* 4.5 usec */ |
5806 | else | |
5807 | val |= 3000 / 250; /* 3.0 usec */ | |
5808 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5809 | |
a580516d | 5810 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5811 | |
b6283055 | 5812 | intel_update_cdclk(dev); |
30a970c6 JB |
5813 | } |
5814 | ||
383c5a6a VS |
5815 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5816 | { | |
5817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5818 | u32 val, cmd; | |
5819 | ||
164dfd28 VK |
5820 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5821 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5822 | |
5823 | switch (cdclk) { | |
383c5a6a VS |
5824 | case 333333: |
5825 | case 320000: | |
383c5a6a | 5826 | case 266667: |
383c5a6a | 5827 | case 200000: |
383c5a6a VS |
5828 | break; |
5829 | default: | |
5f77eeb0 | 5830 | MISSING_CASE(cdclk); |
383c5a6a VS |
5831 | return; |
5832 | } | |
5833 | ||
9d0d3fda VS |
5834 | /* |
5835 | * Specs are full of misinformation, but testing on actual | |
5836 | * hardware has shown that we just need to write the desired | |
5837 | * CCK divider into the Punit register. | |
5838 | */ | |
5839 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5840 | ||
383c5a6a VS |
5841 | mutex_lock(&dev_priv->rps.hw_lock); |
5842 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5843 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5844 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5845 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5846 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5847 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5848 | 50)) { | |
5849 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5850 | } | |
5851 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5852 | ||
b6283055 | 5853 | intel_update_cdclk(dev); |
383c5a6a VS |
5854 | } |
5855 | ||
30a970c6 JB |
5856 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5857 | int max_pixclk) | |
5858 | { | |
6bcda4f0 | 5859 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5860 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5861 | |
30a970c6 JB |
5862 | /* |
5863 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5864 | * 200MHz | |
5865 | * 267MHz | |
29dc7ef3 | 5866 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5867 | * 400MHz (VLV only) |
5868 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5869 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5870 | * |
5871 | * We seem to get an unstable or solid color picture at 200MHz. | |
5872 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5873 | * are off. | |
30a970c6 | 5874 | */ |
6cca3195 VS |
5875 | if (!IS_CHERRYVIEW(dev_priv) && |
5876 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5877 | return 400000; |
6cca3195 | 5878 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5879 | return freq_320; |
e37c67a1 | 5880 | else if (max_pixclk > 0) |
dfcab17e | 5881 | return 266667; |
e37c67a1 VS |
5882 | else |
5883 | return 200000; | |
30a970c6 JB |
5884 | } |
5885 | ||
f8437dd1 VK |
5886 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5887 | int max_pixclk) | |
5888 | { | |
5889 | /* | |
5890 | * FIXME: | |
5891 | * - remove the guardband, it's not needed on BXT | |
5892 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5893 | */ | |
5894 | if (max_pixclk > 576000*9/10) | |
5895 | return 624000; | |
5896 | else if (max_pixclk > 384000*9/10) | |
5897 | return 576000; | |
5898 | else if (max_pixclk > 288000*9/10) | |
5899 | return 384000; | |
5900 | else if (max_pixclk > 144000*9/10) | |
5901 | return 288000; | |
5902 | else | |
5903 | return 144000; | |
5904 | } | |
5905 | ||
e8788cbc | 5906 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
5907 | static int intel_mode_max_pixclk(struct drm_device *dev, |
5908 | struct drm_atomic_state *state) | |
30a970c6 | 5909 | { |
565602d7 ML |
5910 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
5911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5912 | struct drm_crtc *crtc; | |
5913 | struct drm_crtc_state *crtc_state; | |
5914 | unsigned max_pixclk = 0, i; | |
5915 | enum pipe pipe; | |
30a970c6 | 5916 | |
565602d7 ML |
5917 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
5918 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 5919 | |
565602d7 ML |
5920 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5921 | int pixclk = 0; | |
5922 | ||
5923 | if (crtc_state->enable) | |
5924 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 5925 | |
565602d7 | 5926 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
5927 | } |
5928 | ||
565602d7 ML |
5929 | for_each_pipe(dev_priv, pipe) |
5930 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
5931 | ||
30a970c6 JB |
5932 | return max_pixclk; |
5933 | } | |
5934 | ||
27c329ed | 5935 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 5936 | { |
27c329ed ML |
5937 | struct drm_device *dev = state->dev; |
5938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5939 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
5940 | struct intel_atomic_state *intel_state = |
5941 | to_intel_atomic_state(state); | |
30a970c6 | 5942 | |
304603f4 ACO |
5943 | if (max_pixclk < 0) |
5944 | return max_pixclk; | |
30a970c6 | 5945 | |
1a617b77 | 5946 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 5947 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 5948 | |
1a617b77 ML |
5949 | if (!intel_state->active_crtcs) |
5950 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
5951 | ||
27c329ed ML |
5952 | return 0; |
5953 | } | |
304603f4 | 5954 | |
27c329ed ML |
5955 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
5956 | { | |
5957 | struct drm_device *dev = state->dev; | |
5958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5959 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
5960 | struct intel_atomic_state *intel_state = |
5961 | to_intel_atomic_state(state); | |
85a96e7a | 5962 | |
27c329ed ML |
5963 | if (max_pixclk < 0) |
5964 | return max_pixclk; | |
85a96e7a | 5965 | |
1a617b77 | 5966 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 5967 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 5968 | |
1a617b77 ML |
5969 | if (!intel_state->active_crtcs) |
5970 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
5971 | ||
27c329ed | 5972 | return 0; |
30a970c6 JB |
5973 | } |
5974 | ||
1e69cd74 VS |
5975 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5976 | { | |
5977 | unsigned int credits, default_credits; | |
5978 | ||
5979 | if (IS_CHERRYVIEW(dev_priv)) | |
5980 | default_credits = PFI_CREDIT(12); | |
5981 | else | |
5982 | default_credits = PFI_CREDIT(8); | |
5983 | ||
bfa7df01 | 5984 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
5985 | /* CHV suggested value is 31 or 63 */ |
5986 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 5987 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
5988 | else |
5989 | credits = PFI_CREDIT(15); | |
5990 | } else { | |
5991 | credits = default_credits; | |
5992 | } | |
5993 | ||
5994 | /* | |
5995 | * WA - write default credits before re-programming | |
5996 | * FIXME: should we also set the resend bit here? | |
5997 | */ | |
5998 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5999 | default_credits); | |
6000 | ||
6001 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6002 | credits | PFI_CREDIT_RESEND); | |
6003 | ||
6004 | /* | |
6005 | * FIXME is this guaranteed to clear | |
6006 | * immediately or should we poll for it? | |
6007 | */ | |
6008 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6009 | } | |
6010 | ||
27c329ed | 6011 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6012 | { |
a821fc46 | 6013 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6014 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6015 | struct intel_atomic_state *old_intel_state = |
6016 | to_intel_atomic_state(old_state); | |
6017 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6018 | |
27c329ed ML |
6019 | /* |
6020 | * FIXME: We can end up here with all power domains off, yet | |
6021 | * with a CDCLK frequency other than the minimum. To account | |
6022 | * for this take the PIPE-A power domain, which covers the HW | |
6023 | * blocks needed for the following programming. This can be | |
6024 | * removed once it's guaranteed that we get here either with | |
6025 | * the minimum CDCLK set, or the required power domains | |
6026 | * enabled. | |
6027 | */ | |
6028 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6029 | |
27c329ed ML |
6030 | if (IS_CHERRYVIEW(dev)) |
6031 | cherryview_set_cdclk(dev, req_cdclk); | |
6032 | else | |
6033 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6034 | |
27c329ed | 6035 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6036 | |
27c329ed | 6037 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6038 | } |
6039 | ||
89b667f8 JB |
6040 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6041 | { | |
6042 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6043 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6044 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6045 | struct intel_encoder *encoder; | |
b95c5321 ML |
6046 | struct intel_crtc_state *pipe_config = |
6047 | to_intel_crtc_state(crtc->state); | |
89b667f8 | 6048 | int pipe = intel_crtc->pipe; |
89b667f8 | 6049 | |
53d9f4e9 | 6050 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6051 | return; |
6052 | ||
6e3c9717 | 6053 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6054 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6055 | |
6056 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6057 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6058 | |
c14b0485 VS |
6059 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6061 | ||
6062 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6063 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6064 | } | |
6065 | ||
5b18e57c DV |
6066 | i9xx_set_pipeconf(intel_crtc); |
6067 | ||
89b667f8 | 6068 | intel_crtc->active = true; |
89b667f8 | 6069 | |
a72e4c9f | 6070 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6071 | |
89b667f8 JB |
6072 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6073 | if (encoder->pre_pll_enable) | |
6074 | encoder->pre_pll_enable(encoder); | |
6075 | ||
a65347ba | 6076 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6077 | if (IS_CHERRYVIEW(dev)) { |
6078 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6079 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6080 | } else { |
6081 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6082 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6083 | } |
9d556c99 | 6084 | } |
89b667f8 JB |
6085 | |
6086 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6087 | if (encoder->pre_enable) | |
6088 | encoder->pre_enable(encoder); | |
6089 | ||
2dd24552 JB |
6090 | i9xx_pfit_enable(intel_crtc); |
6091 | ||
b95c5321 | 6092 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6093 | |
caed361d | 6094 | intel_update_watermarks(crtc); |
e1fdc473 | 6095 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6096 | |
4b3a9526 VS |
6097 | assert_vblank_disabled(crtc); |
6098 | drm_crtc_vblank_on(crtc); | |
6099 | ||
f9b61ff6 DV |
6100 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6101 | encoder->enable(encoder); | |
89b667f8 JB |
6102 | } |
6103 | ||
f13c2ef3 DV |
6104 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6105 | { | |
6106 | struct drm_device *dev = crtc->base.dev; | |
6107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6108 | ||
6e3c9717 ACO |
6109 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6110 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6111 | } |
6112 | ||
0b8765c6 | 6113 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6114 | { |
6115 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6116 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6117 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6118 | struct intel_encoder *encoder; |
b95c5321 ML |
6119 | struct intel_crtc_state *pipe_config = |
6120 | to_intel_crtc_state(crtc->state); | |
79e53945 | 6121 | int pipe = intel_crtc->pipe; |
79e53945 | 6122 | |
53d9f4e9 | 6123 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6124 | return; |
6125 | ||
f13c2ef3 DV |
6126 | i9xx_set_pll_dividers(intel_crtc); |
6127 | ||
6e3c9717 | 6128 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6129 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6130 | |
6131 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6132 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6133 | |
5b18e57c DV |
6134 | i9xx_set_pipeconf(intel_crtc); |
6135 | ||
f7abfe8b | 6136 | intel_crtc->active = true; |
6b383a7f | 6137 | |
4a3436e8 | 6138 | if (!IS_GEN2(dev)) |
a72e4c9f | 6139 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6140 | |
9d6d9f19 MK |
6141 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6142 | if (encoder->pre_enable) | |
6143 | encoder->pre_enable(encoder); | |
6144 | ||
f6736a1a DV |
6145 | i9xx_enable_pll(intel_crtc); |
6146 | ||
2dd24552 JB |
6147 | i9xx_pfit_enable(intel_crtc); |
6148 | ||
b95c5321 | 6149 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6150 | |
f37fcc2a | 6151 | intel_update_watermarks(crtc); |
e1fdc473 | 6152 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6153 | |
4b3a9526 VS |
6154 | assert_vblank_disabled(crtc); |
6155 | drm_crtc_vblank_on(crtc); | |
6156 | ||
f9b61ff6 DV |
6157 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6158 | encoder->enable(encoder); | |
0b8765c6 | 6159 | } |
79e53945 | 6160 | |
87476d63 DV |
6161 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6162 | { | |
6163 | struct drm_device *dev = crtc->base.dev; | |
6164 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6165 | |
6e3c9717 | 6166 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6167 | return; |
87476d63 | 6168 | |
328d8e82 | 6169 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6170 | |
328d8e82 DV |
6171 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6172 | I915_READ(PFIT_CONTROL)); | |
6173 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6174 | } |
6175 | ||
0b8765c6 JB |
6176 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6177 | { | |
6178 | struct drm_device *dev = crtc->dev; | |
6179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6181 | struct intel_encoder *encoder; |
0b8765c6 | 6182 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6183 | |
6304cd91 VS |
6184 | /* |
6185 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6186 | * wait for planes to fully turn off before disabling the pipe. | |
6187 | */ | |
90e83e53 ACO |
6188 | if (IS_GEN2(dev)) |
6189 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6190 | |
4b3a9526 VS |
6191 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6192 | encoder->disable(encoder); | |
6193 | ||
f9b61ff6 DV |
6194 | drm_crtc_vblank_off(crtc); |
6195 | assert_vblank_disabled(crtc); | |
6196 | ||
575f7ab7 | 6197 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6198 | |
87476d63 | 6199 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6200 | |
89b667f8 JB |
6201 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6202 | if (encoder->post_disable) | |
6203 | encoder->post_disable(encoder); | |
6204 | ||
a65347ba | 6205 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6206 | if (IS_CHERRYVIEW(dev)) |
6207 | chv_disable_pll(dev_priv, pipe); | |
6208 | else if (IS_VALLEYVIEW(dev)) | |
6209 | vlv_disable_pll(dev_priv, pipe); | |
6210 | else | |
1c4e0274 | 6211 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6212 | } |
0b8765c6 | 6213 | |
d6db995f VS |
6214 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6215 | if (encoder->post_pll_disable) | |
6216 | encoder->post_pll_disable(encoder); | |
6217 | ||
4a3436e8 | 6218 | if (!IS_GEN2(dev)) |
a72e4c9f | 6219 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6220 | } |
6221 | ||
b17d48e2 ML |
6222 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6223 | { | |
842e0307 | 6224 | struct intel_encoder *encoder; |
b17d48e2 ML |
6225 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6226 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6227 | enum intel_display_power_domain domain; | |
6228 | unsigned long domains; | |
6229 | ||
6230 | if (!intel_crtc->active) | |
6231 | return; | |
6232 | ||
a539205a | 6233 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6234 | WARN_ON(intel_crtc->unpin_work); |
6235 | ||
2622a081 | 6236 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6237 | |
6238 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6239 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6240 | } |
6241 | ||
b17d48e2 | 6242 | dev_priv->display.crtc_disable(crtc); |
842e0307 ML |
6243 | |
6244 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n", | |
6245 | crtc->base.id); | |
6246 | ||
6247 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6248 | crtc->state->active = false; | |
37d9078b | 6249 | intel_crtc->active = false; |
842e0307 ML |
6250 | crtc->enabled = false; |
6251 | crtc->state->connector_mask = 0; | |
6252 | crtc->state->encoder_mask = 0; | |
6253 | ||
6254 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6255 | encoder->base.crtc = NULL; | |
6256 | ||
58f9c0bc | 6257 | intel_fbc_disable(intel_crtc); |
37d9078b | 6258 | intel_update_watermarks(crtc); |
1f7457b1 | 6259 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6260 | |
6261 | domains = intel_crtc->enabled_power_domains; | |
6262 | for_each_power_domain(domain, domains) | |
6263 | intel_display_power_put(dev_priv, domain); | |
6264 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6265 | |
6266 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6267 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6268 | } |
6269 | ||
6b72d486 ML |
6270 | /* |
6271 | * turn all crtc's off, but do not adjust state | |
6272 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6273 | */ | |
70e0bd74 | 6274 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6275 | { |
e2c8b870 | 6276 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6277 | struct drm_atomic_state *state; |
e2c8b870 | 6278 | int ret; |
70e0bd74 | 6279 | |
e2c8b870 ML |
6280 | state = drm_atomic_helper_suspend(dev); |
6281 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6282 | if (ret) |
6283 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6284 | else |
6285 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6286 | return ret; |
ee7b9f93 JB |
6287 | } |
6288 | ||
ea5b213a | 6289 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6290 | { |
4ef69c7a | 6291 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6292 | |
ea5b213a CW |
6293 | drm_encoder_cleanup(encoder); |
6294 | kfree(intel_encoder); | |
7e7d76c3 JB |
6295 | } |
6296 | ||
0a91ca29 DV |
6297 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6298 | * internal consistency). */ | |
c0ead703 | 6299 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6300 | { |
35dd3c64 ML |
6301 | struct drm_crtc *crtc = connector->base.state->crtc; |
6302 | ||
6303 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6304 | connector->base.base.id, | |
6305 | connector->base.name); | |
6306 | ||
0a91ca29 | 6307 | if (connector->get_hw_state(connector)) { |
e85376cb | 6308 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6309 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6310 | |
35dd3c64 ML |
6311 | I915_STATE_WARN(!crtc, |
6312 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6313 | |
35dd3c64 ML |
6314 | if (!crtc) |
6315 | return; | |
6316 | ||
6317 | I915_STATE_WARN(!crtc->state->active, | |
6318 | "connector is active, but attached crtc isn't\n"); | |
6319 | ||
e85376cb | 6320 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6321 | return; |
6322 | ||
e85376cb | 6323 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6324 | "atomic encoder doesn't match attached encoder\n"); |
6325 | ||
e85376cb | 6326 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6327 | "attached encoder crtc differs from connector crtc\n"); |
6328 | } else { | |
4d688a2a ML |
6329 | I915_STATE_WARN(crtc && crtc->state->active, |
6330 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6331 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6332 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6333 | } |
79e53945 JB |
6334 | } |
6335 | ||
08d9bc92 ACO |
6336 | int intel_connector_init(struct intel_connector *connector) |
6337 | { | |
5350a031 | 6338 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6339 | |
5350a031 | 6340 | if (!connector->base.state) |
08d9bc92 ACO |
6341 | return -ENOMEM; |
6342 | ||
08d9bc92 ACO |
6343 | return 0; |
6344 | } | |
6345 | ||
6346 | struct intel_connector *intel_connector_alloc(void) | |
6347 | { | |
6348 | struct intel_connector *connector; | |
6349 | ||
6350 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6351 | if (!connector) | |
6352 | return NULL; | |
6353 | ||
6354 | if (intel_connector_init(connector) < 0) { | |
6355 | kfree(connector); | |
6356 | return NULL; | |
6357 | } | |
6358 | ||
6359 | return connector; | |
6360 | } | |
6361 | ||
f0947c37 DV |
6362 | /* Simple connector->get_hw_state implementation for encoders that support only |
6363 | * one connector and no cloning and hence the encoder state determines the state | |
6364 | * of the connector. */ | |
6365 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6366 | { |
24929352 | 6367 | enum pipe pipe = 0; |
f0947c37 | 6368 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6369 | |
f0947c37 | 6370 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6371 | } |
6372 | ||
6d293983 | 6373 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6374 | { |
6d293983 ACO |
6375 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6376 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6377 | |
6378 | return 0; | |
6379 | } | |
6380 | ||
6d293983 | 6381 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6382 | struct intel_crtc_state *pipe_config) |
1857e1da | 6383 | { |
6d293983 ACO |
6384 | struct drm_atomic_state *state = pipe_config->base.state; |
6385 | struct intel_crtc *other_crtc; | |
6386 | struct intel_crtc_state *other_crtc_state; | |
6387 | ||
1857e1da DV |
6388 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6389 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6390 | if (pipe_config->fdi_lanes > 4) { | |
6391 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6392 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6393 | return -EINVAL; |
1857e1da DV |
6394 | } |
6395 | ||
bafb6553 | 6396 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6397 | if (pipe_config->fdi_lanes > 2) { |
6398 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6399 | pipe_config->fdi_lanes); | |
6d293983 | 6400 | return -EINVAL; |
1857e1da | 6401 | } else { |
6d293983 | 6402 | return 0; |
1857e1da DV |
6403 | } |
6404 | } | |
6405 | ||
6406 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6407 | return 0; |
1857e1da DV |
6408 | |
6409 | /* Ivybridge 3 pipe is really complicated */ | |
6410 | switch (pipe) { | |
6411 | case PIPE_A: | |
6d293983 | 6412 | return 0; |
1857e1da | 6413 | case PIPE_B: |
6d293983 ACO |
6414 | if (pipe_config->fdi_lanes <= 2) |
6415 | return 0; | |
6416 | ||
6417 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6418 | other_crtc_state = | |
6419 | intel_atomic_get_crtc_state(state, other_crtc); | |
6420 | if (IS_ERR(other_crtc_state)) | |
6421 | return PTR_ERR(other_crtc_state); | |
6422 | ||
6423 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6424 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6425 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6426 | return -EINVAL; |
1857e1da | 6427 | } |
6d293983 | 6428 | return 0; |
1857e1da | 6429 | case PIPE_C: |
251cc67c VS |
6430 | if (pipe_config->fdi_lanes > 2) { |
6431 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6432 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6433 | return -EINVAL; |
251cc67c | 6434 | } |
6d293983 ACO |
6435 | |
6436 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6437 | other_crtc_state = | |
6438 | intel_atomic_get_crtc_state(state, other_crtc); | |
6439 | if (IS_ERR(other_crtc_state)) | |
6440 | return PTR_ERR(other_crtc_state); | |
6441 | ||
6442 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6443 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6444 | return -EINVAL; |
1857e1da | 6445 | } |
6d293983 | 6446 | return 0; |
1857e1da DV |
6447 | default: |
6448 | BUG(); | |
6449 | } | |
6450 | } | |
6451 | ||
e29c22c0 DV |
6452 | #define RETRY 1 |
6453 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6454 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6455 | { |
1857e1da | 6456 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6457 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6458 | int lane, link_bw, fdi_dotclock, ret; |
6459 | bool needs_recompute = false; | |
877d48d5 | 6460 | |
e29c22c0 | 6461 | retry: |
877d48d5 DV |
6462 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6463 | * each output octet as 10 bits. The actual frequency | |
6464 | * is stored as a divider into a 100MHz clock, and the | |
6465 | * mode pixel clock is stored in units of 1KHz. | |
6466 | * Hence the bw of each lane in terms of the mode signal | |
6467 | * is: | |
6468 | */ | |
21a727b3 | 6469 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6470 | |
241bfc38 | 6471 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6472 | |
2bd89a07 | 6473 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6474 | pipe_config->pipe_bpp); |
6475 | ||
6476 | pipe_config->fdi_lanes = lane; | |
6477 | ||
2bd89a07 | 6478 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6479 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6480 | |
e3b247da | 6481 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6482 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6483 | pipe_config->pipe_bpp -= 2*3; |
6484 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6485 | pipe_config->pipe_bpp); | |
6486 | needs_recompute = true; | |
6487 | pipe_config->bw_constrained = true; | |
6488 | ||
6489 | goto retry; | |
6490 | } | |
6491 | ||
6492 | if (needs_recompute) | |
6493 | return RETRY; | |
6494 | ||
6d293983 | 6495 | return ret; |
877d48d5 DV |
6496 | } |
6497 | ||
8cfb3407 VS |
6498 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6499 | struct intel_crtc_state *pipe_config) | |
6500 | { | |
6501 | if (pipe_config->pipe_bpp > 24) | |
6502 | return false; | |
6503 | ||
6504 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 6505 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
6506 | return true; |
6507 | ||
6508 | /* | |
b432e5cf VS |
6509 | * We compare against max which means we must take |
6510 | * the increased cdclk requirement into account when | |
6511 | * calculating the new cdclk. | |
6512 | * | |
6513 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6514 | */ |
6515 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6516 | dev_priv->max_cdclk_freq * 95 / 100; | |
6517 | } | |
6518 | ||
42db64ef | 6519 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6520 | struct intel_crtc_state *pipe_config) |
42db64ef | 6521 | { |
8cfb3407 VS |
6522 | struct drm_device *dev = crtc->base.dev; |
6523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6524 | ||
d330a953 | 6525 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6526 | hsw_crtc_supports_ips(crtc) && |
6527 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6528 | } |
6529 | ||
39acb4aa VS |
6530 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6531 | { | |
6532 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6533 | ||
6534 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6535 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6536 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6537 | } | |
6538 | ||
a43f6e0f | 6539 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6540 | struct intel_crtc_state *pipe_config) |
79e53945 | 6541 | { |
a43f6e0f | 6542 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6543 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6544 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6545 | |
ad3a4479 | 6546 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6547 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6548 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6549 | |
6550 | /* | |
39acb4aa | 6551 | * Enable double wide mode when the dot clock |
cf532bb2 | 6552 | * is > 90% of the (display) core speed. |
cf532bb2 | 6553 | */ |
39acb4aa VS |
6554 | if (intel_crtc_supports_double_wide(crtc) && |
6555 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6556 | clock_limit *= 2; |
cf532bb2 | 6557 | pipe_config->double_wide = true; |
ad3a4479 VS |
6558 | } |
6559 | ||
39acb4aa VS |
6560 | if (adjusted_mode->crtc_clock > clock_limit) { |
6561 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6562 | adjusted_mode->crtc_clock, clock_limit, | |
6563 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6564 | return -EINVAL; |
39acb4aa | 6565 | } |
2c07245f | 6566 | } |
89749350 | 6567 | |
1d1d0e27 VS |
6568 | /* |
6569 | * Pipe horizontal size must be even in: | |
6570 | * - DVO ganged mode | |
6571 | * - LVDS dual channel mode | |
6572 | * - Double wide pipe | |
6573 | */ | |
a93e255f | 6574 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6575 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6576 | pipe_config->pipe_src_w &= ~1; | |
6577 | ||
8693a824 DL |
6578 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6579 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6580 | */ |
6581 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6582 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6583 | return -EINVAL; |
44f46b42 | 6584 | |
f5adf94e | 6585 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6586 | hsw_compute_ips_config(crtc, pipe_config); |
6587 | ||
877d48d5 | 6588 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6589 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6590 | |
cf5a15be | 6591 | return 0; |
79e53945 JB |
6592 | } |
6593 | ||
1652d19e VS |
6594 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6595 | { | |
6596 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6597 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6598 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6599 | uint32_t linkrate; | |
6600 | ||
414355a7 | 6601 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6602 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6603 | |
6604 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6605 | return 540000; | |
6606 | ||
6607 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6608 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6609 | |
71cd8423 DL |
6610 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6611 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6612 | /* vco 8640 */ |
6613 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6614 | case CDCLK_FREQ_450_432: | |
6615 | return 432000; | |
6616 | case CDCLK_FREQ_337_308: | |
6617 | return 308570; | |
6618 | case CDCLK_FREQ_675_617: | |
6619 | return 617140; | |
6620 | default: | |
6621 | WARN(1, "Unknown cd freq selection\n"); | |
6622 | } | |
6623 | } else { | |
6624 | /* vco 8100 */ | |
6625 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6626 | case CDCLK_FREQ_450_432: | |
6627 | return 450000; | |
6628 | case CDCLK_FREQ_337_308: | |
6629 | return 337500; | |
6630 | case CDCLK_FREQ_675_617: | |
6631 | return 675000; | |
6632 | default: | |
6633 | WARN(1, "Unknown cd freq selection\n"); | |
6634 | } | |
6635 | } | |
6636 | ||
6637 | /* error case, do as if DPLL0 isn't enabled */ | |
6638 | return 24000; | |
6639 | } | |
6640 | ||
acd3f3d3 BP |
6641 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6642 | { | |
6643 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6644 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6645 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6646 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6647 | int cdclk; | |
6648 | ||
6649 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6650 | return 19200; | |
6651 | ||
6652 | cdclk = 19200 * pll_ratio / 2; | |
6653 | ||
6654 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6655 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6656 | return cdclk; /* 576MHz or 624MHz */ | |
6657 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6658 | return cdclk * 2 / 3; /* 384MHz */ | |
6659 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6660 | return cdclk / 2; /* 288MHz */ | |
6661 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6662 | return cdclk / 4; /* 144MHz */ | |
6663 | } | |
6664 | ||
6665 | /* error case, do as if DE PLL isn't enabled */ | |
6666 | return 19200; | |
6667 | } | |
6668 | ||
1652d19e VS |
6669 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6670 | { | |
6671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6672 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6673 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6674 | ||
6675 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6676 | return 800000; | |
6677 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6678 | return 450000; | |
6679 | else if (freq == LCPLL_CLK_FREQ_450) | |
6680 | return 450000; | |
6681 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6682 | return 540000; | |
6683 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6684 | return 337500; | |
6685 | else | |
6686 | return 675000; | |
6687 | } | |
6688 | ||
6689 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6690 | { | |
6691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6692 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6693 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6694 | ||
6695 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6696 | return 800000; | |
6697 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6698 | return 450000; | |
6699 | else if (freq == LCPLL_CLK_FREQ_450) | |
6700 | return 450000; | |
6701 | else if (IS_HSW_ULT(dev)) | |
6702 | return 337500; | |
6703 | else | |
6704 | return 540000; | |
79e53945 JB |
6705 | } |
6706 | ||
25eb05fc JB |
6707 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6708 | { | |
bfa7df01 VS |
6709 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6710 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6711 | } |
6712 | ||
b37a6434 VS |
6713 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6714 | { | |
6715 | return 450000; | |
6716 | } | |
6717 | ||
e70236a8 JB |
6718 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6719 | { | |
6720 | return 400000; | |
6721 | } | |
79e53945 | 6722 | |
e70236a8 | 6723 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6724 | { |
e907f170 | 6725 | return 333333; |
e70236a8 | 6726 | } |
79e53945 | 6727 | |
e70236a8 JB |
6728 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6729 | { | |
6730 | return 200000; | |
6731 | } | |
79e53945 | 6732 | |
257a7ffc DV |
6733 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6734 | { | |
6735 | u16 gcfgc = 0; | |
6736 | ||
6737 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6738 | ||
6739 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6740 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6741 | return 266667; |
257a7ffc | 6742 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6743 | return 333333; |
257a7ffc | 6744 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6745 | return 444444; |
257a7ffc DV |
6746 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6747 | return 200000; | |
6748 | default: | |
6749 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6750 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6751 | return 133333; |
257a7ffc | 6752 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6753 | return 166667; |
257a7ffc DV |
6754 | } |
6755 | } | |
6756 | ||
e70236a8 JB |
6757 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6758 | { | |
6759 | u16 gcfgc = 0; | |
79e53945 | 6760 | |
e70236a8 JB |
6761 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6762 | ||
6763 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6764 | return 133333; |
e70236a8 JB |
6765 | else { |
6766 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6767 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6768 | return 333333; |
e70236a8 JB |
6769 | default: |
6770 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6771 | return 190000; | |
79e53945 | 6772 | } |
e70236a8 JB |
6773 | } |
6774 | } | |
6775 | ||
6776 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6777 | { | |
e907f170 | 6778 | return 266667; |
e70236a8 JB |
6779 | } |
6780 | ||
1b1d2716 | 6781 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6782 | { |
6783 | u16 hpllcc = 0; | |
1b1d2716 | 6784 | |
65cd2b3f VS |
6785 | /* |
6786 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6787 | * encoding is different :( | |
6788 | * FIXME is this the right way to detect 852GM/852GMV? | |
6789 | */ | |
6790 | if (dev->pdev->revision == 0x1) | |
6791 | return 133333; | |
6792 | ||
1b1d2716 VS |
6793 | pci_bus_read_config_word(dev->pdev->bus, |
6794 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6795 | ||
e70236a8 JB |
6796 | /* Assume that the hardware is in the high speed state. This |
6797 | * should be the default. | |
6798 | */ | |
6799 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6800 | case GC_CLOCK_133_200: | |
1b1d2716 | 6801 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6802 | case GC_CLOCK_100_200: |
6803 | return 200000; | |
6804 | case GC_CLOCK_166_250: | |
6805 | return 250000; | |
6806 | case GC_CLOCK_100_133: | |
e907f170 | 6807 | return 133333; |
1b1d2716 VS |
6808 | case GC_CLOCK_133_266: |
6809 | case GC_CLOCK_133_266_2: | |
6810 | case GC_CLOCK_166_266: | |
6811 | return 266667; | |
e70236a8 | 6812 | } |
79e53945 | 6813 | |
e70236a8 JB |
6814 | /* Shouldn't happen */ |
6815 | return 0; | |
6816 | } | |
79e53945 | 6817 | |
e70236a8 JB |
6818 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6819 | { | |
e907f170 | 6820 | return 133333; |
79e53945 JB |
6821 | } |
6822 | ||
34edce2f VS |
6823 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6824 | { | |
6825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6826 | static const unsigned int blb_vco[8] = { | |
6827 | [0] = 3200000, | |
6828 | [1] = 4000000, | |
6829 | [2] = 5333333, | |
6830 | [3] = 4800000, | |
6831 | [4] = 6400000, | |
6832 | }; | |
6833 | static const unsigned int pnv_vco[8] = { | |
6834 | [0] = 3200000, | |
6835 | [1] = 4000000, | |
6836 | [2] = 5333333, | |
6837 | [3] = 4800000, | |
6838 | [4] = 2666667, | |
6839 | }; | |
6840 | static const unsigned int cl_vco[8] = { | |
6841 | [0] = 3200000, | |
6842 | [1] = 4000000, | |
6843 | [2] = 5333333, | |
6844 | [3] = 6400000, | |
6845 | [4] = 3333333, | |
6846 | [5] = 3566667, | |
6847 | [6] = 4266667, | |
6848 | }; | |
6849 | static const unsigned int elk_vco[8] = { | |
6850 | [0] = 3200000, | |
6851 | [1] = 4000000, | |
6852 | [2] = 5333333, | |
6853 | [3] = 4800000, | |
6854 | }; | |
6855 | static const unsigned int ctg_vco[8] = { | |
6856 | [0] = 3200000, | |
6857 | [1] = 4000000, | |
6858 | [2] = 5333333, | |
6859 | [3] = 6400000, | |
6860 | [4] = 2666667, | |
6861 | [5] = 4266667, | |
6862 | }; | |
6863 | const unsigned int *vco_table; | |
6864 | unsigned int vco; | |
6865 | uint8_t tmp = 0; | |
6866 | ||
6867 | /* FIXME other chipsets? */ | |
6868 | if (IS_GM45(dev)) | |
6869 | vco_table = ctg_vco; | |
6870 | else if (IS_G4X(dev)) | |
6871 | vco_table = elk_vco; | |
6872 | else if (IS_CRESTLINE(dev)) | |
6873 | vco_table = cl_vco; | |
6874 | else if (IS_PINEVIEW(dev)) | |
6875 | vco_table = pnv_vco; | |
6876 | else if (IS_G33(dev)) | |
6877 | vco_table = blb_vco; | |
6878 | else | |
6879 | return 0; | |
6880 | ||
6881 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6882 | ||
6883 | vco = vco_table[tmp & 0x7]; | |
6884 | if (vco == 0) | |
6885 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6886 | else | |
6887 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6888 | ||
6889 | return vco; | |
6890 | } | |
6891 | ||
6892 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6893 | { | |
6894 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6895 | uint16_t tmp = 0; | |
6896 | ||
6897 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6898 | ||
6899 | cdclk_sel = (tmp >> 12) & 0x1; | |
6900 | ||
6901 | switch (vco) { | |
6902 | case 2666667: | |
6903 | case 4000000: | |
6904 | case 5333333: | |
6905 | return cdclk_sel ? 333333 : 222222; | |
6906 | case 3200000: | |
6907 | return cdclk_sel ? 320000 : 228571; | |
6908 | default: | |
6909 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6910 | return 222222; | |
6911 | } | |
6912 | } | |
6913 | ||
6914 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6915 | { | |
6916 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6917 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6918 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6919 | const uint8_t *div_table; | |
6920 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6921 | uint16_t tmp = 0; | |
6922 | ||
6923 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6924 | ||
6925 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6926 | ||
6927 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6928 | goto fail; | |
6929 | ||
6930 | switch (vco) { | |
6931 | case 3200000: | |
6932 | div_table = div_3200; | |
6933 | break; | |
6934 | case 4000000: | |
6935 | div_table = div_4000; | |
6936 | break; | |
6937 | case 5333333: | |
6938 | div_table = div_5333; | |
6939 | break; | |
6940 | default: | |
6941 | goto fail; | |
6942 | } | |
6943 | ||
6944 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6945 | ||
caf4e252 | 6946 | fail: |
34edce2f VS |
6947 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
6948 | return 200000; | |
6949 | } | |
6950 | ||
6951 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
6952 | { | |
6953 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
6954 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
6955 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
6956 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
6957 | const uint8_t *div_table; | |
6958 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6959 | uint16_t tmp = 0; | |
6960 | ||
6961 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6962 | ||
6963 | cdclk_sel = (tmp >> 4) & 0x7; | |
6964 | ||
6965 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6966 | goto fail; | |
6967 | ||
6968 | switch (vco) { | |
6969 | case 3200000: | |
6970 | div_table = div_3200; | |
6971 | break; | |
6972 | case 4000000: | |
6973 | div_table = div_4000; | |
6974 | break; | |
6975 | case 4800000: | |
6976 | div_table = div_4800; | |
6977 | break; | |
6978 | case 5333333: | |
6979 | div_table = div_5333; | |
6980 | break; | |
6981 | default: | |
6982 | goto fail; | |
6983 | } | |
6984 | ||
6985 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6986 | ||
caf4e252 | 6987 | fail: |
34edce2f VS |
6988 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
6989 | return 190476; | |
6990 | } | |
6991 | ||
2c07245f | 6992 | static void |
a65851af | 6993 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6994 | { |
a65851af VS |
6995 | while (*num > DATA_LINK_M_N_MASK || |
6996 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6997 | *num >>= 1; |
6998 | *den >>= 1; | |
6999 | } | |
7000 | } | |
7001 | ||
a65851af VS |
7002 | static void compute_m_n(unsigned int m, unsigned int n, |
7003 | uint32_t *ret_m, uint32_t *ret_n) | |
7004 | { | |
7005 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7006 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7007 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7008 | } | |
7009 | ||
e69d0bc1 DV |
7010 | void |
7011 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7012 | int pixel_clock, int link_clock, | |
7013 | struct intel_link_m_n *m_n) | |
2c07245f | 7014 | { |
e69d0bc1 | 7015 | m_n->tu = 64; |
a65851af VS |
7016 | |
7017 | compute_m_n(bits_per_pixel * pixel_clock, | |
7018 | link_clock * nlanes * 8, | |
7019 | &m_n->gmch_m, &m_n->gmch_n); | |
7020 | ||
7021 | compute_m_n(pixel_clock, link_clock, | |
7022 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7023 | } |
7024 | ||
a7615030 CW |
7025 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7026 | { | |
d330a953 JN |
7027 | if (i915.panel_use_ssc >= 0) |
7028 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7029 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7030 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7031 | } |
7032 | ||
7429e9d4 | 7033 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7034 | { |
7df00d7a | 7035 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7036 | } |
f47709a9 | 7037 | |
7429e9d4 DV |
7038 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7039 | { | |
7040 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7041 | } |
7042 | ||
f47709a9 | 7043 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7044 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7045 | intel_clock_t *reduced_clock) |
7046 | { | |
f47709a9 | 7047 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7048 | u32 fp, fp2 = 0; |
7049 | ||
7050 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7051 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7052 | if (reduced_clock) |
7429e9d4 | 7053 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7054 | } else { |
190f68c5 | 7055 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7056 | if (reduced_clock) |
7429e9d4 | 7057 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7058 | } |
7059 | ||
190f68c5 | 7060 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7061 | |
f47709a9 | 7062 | crtc->lowfreq_avail = false; |
a93e255f | 7063 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7064 | reduced_clock) { |
190f68c5 | 7065 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7066 | crtc->lowfreq_avail = true; |
a7516a05 | 7067 | } else { |
190f68c5 | 7068 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7069 | } |
7070 | } | |
7071 | ||
5e69f97f CML |
7072 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7073 | pipe) | |
89b667f8 JB |
7074 | { |
7075 | u32 reg_val; | |
7076 | ||
7077 | /* | |
7078 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7079 | * and set it to a reasonable value instead. | |
7080 | */ | |
ab3c759a | 7081 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7082 | reg_val &= 0xffffff00; |
7083 | reg_val |= 0x00000030; | |
ab3c759a | 7084 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7085 | |
ab3c759a | 7086 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7087 | reg_val &= 0x8cffffff; |
7088 | reg_val = 0x8c000000; | |
ab3c759a | 7089 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7090 | |
ab3c759a | 7091 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7092 | reg_val &= 0xffffff00; |
ab3c759a | 7093 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7094 | |
ab3c759a | 7095 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7096 | reg_val &= 0x00ffffff; |
7097 | reg_val |= 0xb0000000; | |
ab3c759a | 7098 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7099 | } |
7100 | ||
b551842d DV |
7101 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7102 | struct intel_link_m_n *m_n) | |
7103 | { | |
7104 | struct drm_device *dev = crtc->base.dev; | |
7105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7106 | int pipe = crtc->pipe; | |
7107 | ||
e3b95f1e DV |
7108 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7109 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7110 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7111 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7112 | } |
7113 | ||
7114 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7115 | struct intel_link_m_n *m_n, |
7116 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7117 | { |
7118 | struct drm_device *dev = crtc->base.dev; | |
7119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7120 | int pipe = crtc->pipe; | |
6e3c9717 | 7121 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7122 | |
7123 | if (INTEL_INFO(dev)->gen >= 5) { | |
7124 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7125 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7126 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7127 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7128 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7129 | * for gen < 8) and if DRRS is supported (to make sure the | |
7130 | * registers are not unnecessarily accessed). | |
7131 | */ | |
44395bfe | 7132 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7133 | crtc->config->has_drrs) { |
f769cd24 VK |
7134 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7135 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7136 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7137 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7138 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7139 | } | |
b551842d | 7140 | } else { |
e3b95f1e DV |
7141 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7142 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7143 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7144 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7145 | } |
7146 | } | |
7147 | ||
fe3cd48d | 7148 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7149 | { |
fe3cd48d R |
7150 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7151 | ||
7152 | if (m_n == M1_N1) { | |
7153 | dp_m_n = &crtc->config->dp_m_n; | |
7154 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7155 | } else if (m_n == M2_N2) { | |
7156 | ||
7157 | /* | |
7158 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7159 | * needs to be programmed into M1_N1. | |
7160 | */ | |
7161 | dp_m_n = &crtc->config->dp_m2_n2; | |
7162 | } else { | |
7163 | DRM_ERROR("Unsupported divider value\n"); | |
7164 | return; | |
7165 | } | |
7166 | ||
6e3c9717 ACO |
7167 | if (crtc->config->has_pch_encoder) |
7168 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7169 | else |
fe3cd48d | 7170 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7171 | } |
7172 | ||
251ac862 DV |
7173 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7174 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7175 | { |
03ed5cbf VS |
7176 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
7177 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
7178 | DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7179 | if (crtc->pipe != PIPE_A) | |
7180 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7181 | |
03ed5cbf VS |
7182 | pipe_config->dpll_hw_state.dpll_md = |
7183 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7184 | } | |
bdd4b6a6 | 7185 | |
03ed5cbf VS |
7186 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7187 | struct intel_crtc_state *pipe_config) | |
7188 | { | |
7189 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
7190 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
7191 | DPLL_VCO_ENABLE; | |
7192 | if (crtc->pipe != PIPE_A) | |
7193 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7194 | ||
7195 | pipe_config->dpll_hw_state.dpll_md = | |
7196 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7197 | } |
7198 | ||
d288f65f | 7199 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7200 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7201 | { |
f47709a9 | 7202 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7203 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7204 | int pipe = crtc->pipe; |
bdd4b6a6 | 7205 | u32 mdiv; |
a0c4da24 | 7206 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7207 | u32 coreclk, reg_val; |
a0c4da24 | 7208 | |
a580516d | 7209 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7210 | |
d288f65f VS |
7211 | bestn = pipe_config->dpll.n; |
7212 | bestm1 = pipe_config->dpll.m1; | |
7213 | bestm2 = pipe_config->dpll.m2; | |
7214 | bestp1 = pipe_config->dpll.p1; | |
7215 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7216 | |
89b667f8 JB |
7217 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7218 | ||
7219 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7220 | if (pipe == PIPE_B) |
5e69f97f | 7221 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7222 | |
7223 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7224 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7225 | |
7226 | /* Disable target IRef on PLL */ | |
ab3c759a | 7227 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7228 | reg_val &= 0x00ffffff; |
ab3c759a | 7229 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7230 | |
7231 | /* Disable fast lock */ | |
ab3c759a | 7232 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7233 | |
7234 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7235 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7236 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7237 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7238 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7239 | |
7240 | /* | |
7241 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7242 | * but we don't support that). | |
7243 | * Note: don't use the DAC post divider as it seems unstable. | |
7244 | */ | |
7245 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7246 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7247 | |
a0c4da24 | 7248 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7249 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7250 | |
89b667f8 | 7251 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7252 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7253 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7254 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7255 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7256 | 0x009f0003); |
89b667f8 | 7257 | else |
ab3c759a | 7258 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7259 | 0x00d0000f); |
7260 | ||
681a8504 | 7261 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7262 | /* Use SSC source */ |
bdd4b6a6 | 7263 | if (pipe == PIPE_A) |
ab3c759a | 7264 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7265 | 0x0df40000); |
7266 | else | |
ab3c759a | 7267 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7268 | 0x0df70000); |
7269 | } else { /* HDMI or VGA */ | |
7270 | /* Use bend source */ | |
bdd4b6a6 | 7271 | if (pipe == PIPE_A) |
ab3c759a | 7272 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7273 | 0x0df70000); |
7274 | else | |
ab3c759a | 7275 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7276 | 0x0df40000); |
7277 | } | |
a0c4da24 | 7278 | |
ab3c759a | 7279 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7280 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7281 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7282 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7283 | coreclk |= 0x01000000; |
ab3c759a | 7284 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7285 | |
ab3c759a | 7286 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7287 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7288 | } |
7289 | ||
d288f65f | 7290 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7291 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7292 | { |
7293 | struct drm_device *dev = crtc->base.dev; | |
7294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7295 | int pipe = crtc->pipe; | |
f0f59a00 | 7296 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7297 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7298 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7299 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7300 | u32 dpio_val; |
9cbe40c1 | 7301 | int vco; |
9d556c99 | 7302 | |
d288f65f VS |
7303 | bestn = pipe_config->dpll.n; |
7304 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7305 | bestm1 = pipe_config->dpll.m1; | |
7306 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7307 | bestp1 = pipe_config->dpll.p1; | |
7308 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7309 | vco = pipe_config->dpll.vco; |
a945ce7e | 7310 | dpio_val = 0; |
9cbe40c1 | 7311 | loopfilter = 0; |
9d556c99 CML |
7312 | |
7313 | /* | |
7314 | * Enable Refclk and SSC | |
7315 | */ | |
a11b0703 | 7316 | I915_WRITE(dpll_reg, |
d288f65f | 7317 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7318 | |
a580516d | 7319 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7320 | |
9d556c99 CML |
7321 | /* p1 and p2 divider */ |
7322 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7323 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7324 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7325 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7326 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7327 | ||
7328 | /* Feedback post-divider - m2 */ | |
7329 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7330 | ||
7331 | /* Feedback refclk divider - n and m1 */ | |
7332 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7333 | DPIO_CHV_M1_DIV_BY_2 | | |
7334 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7335 | ||
7336 | /* M2 fraction division */ | |
25a25dfc | 7337 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7338 | |
7339 | /* M2 fraction division enable */ | |
a945ce7e VP |
7340 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7341 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7342 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7343 | if (bestm2_frac) | |
7344 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7345 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7346 | |
de3a0fde VP |
7347 | /* Program digital lock detect threshold */ |
7348 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7349 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7350 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7351 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7352 | if (!bestm2_frac) | |
7353 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7354 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7355 | ||
9d556c99 | 7356 | /* Loop filter */ |
9cbe40c1 VP |
7357 | if (vco == 5400000) { |
7358 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7359 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7360 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7361 | tribuf_calcntr = 0x9; | |
7362 | } else if (vco <= 6200000) { | |
7363 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7364 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7365 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7366 | tribuf_calcntr = 0x9; | |
7367 | } else if (vco <= 6480000) { | |
7368 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7369 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7370 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7371 | tribuf_calcntr = 0x8; | |
7372 | } else { | |
7373 | /* Not supported. Apply the same limits as in the max case */ | |
7374 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7375 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7376 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7377 | tribuf_calcntr = 0; | |
7378 | } | |
9d556c99 CML |
7379 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7380 | ||
968040b2 | 7381 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7382 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7383 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7384 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7385 | ||
9d556c99 CML |
7386 | /* AFC Recal */ |
7387 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7388 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7389 | DPIO_AFC_RECAL); | |
7390 | ||
a580516d | 7391 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7392 | } |
7393 | ||
d288f65f VS |
7394 | /** |
7395 | * vlv_force_pll_on - forcibly enable just the PLL | |
7396 | * @dev_priv: i915 private structure | |
7397 | * @pipe: pipe PLL to enable | |
7398 | * @dpll: PLL configuration | |
7399 | * | |
7400 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7401 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7402 | * be enabled. | |
7403 | */ | |
3f36b937 TU |
7404 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7405 | const struct dpll *dpll) | |
d288f65f VS |
7406 | { |
7407 | struct intel_crtc *crtc = | |
7408 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7409 | struct intel_crtc_state *pipe_config; |
7410 | ||
7411 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7412 | if (!pipe_config) | |
7413 | return -ENOMEM; | |
7414 | ||
7415 | pipe_config->base.crtc = &crtc->base; | |
7416 | pipe_config->pixel_multiplier = 1; | |
7417 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7418 | |
7419 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7420 | chv_compute_dpll(crtc, pipe_config); |
7421 | chv_prepare_pll(crtc, pipe_config); | |
7422 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7423 | } else { |
3f36b937 TU |
7424 | vlv_compute_dpll(crtc, pipe_config); |
7425 | vlv_prepare_pll(crtc, pipe_config); | |
7426 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7427 | } |
3f36b937 TU |
7428 | |
7429 | kfree(pipe_config); | |
7430 | ||
7431 | return 0; | |
d288f65f VS |
7432 | } |
7433 | ||
7434 | /** | |
7435 | * vlv_force_pll_off - forcibly disable just the PLL | |
7436 | * @dev_priv: i915 private structure | |
7437 | * @pipe: pipe PLL to disable | |
7438 | * | |
7439 | * Disable the PLL for @pipe. To be used in cases where we need | |
7440 | * the PLL enabled even when @pipe is not going to be enabled. | |
7441 | */ | |
7442 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7443 | { | |
7444 | if (IS_CHERRYVIEW(dev)) | |
7445 | chv_disable_pll(to_i915(dev), pipe); | |
7446 | else | |
7447 | vlv_disable_pll(to_i915(dev), pipe); | |
7448 | } | |
7449 | ||
251ac862 DV |
7450 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7451 | struct intel_crtc_state *crtc_state, | |
ceb41007 | 7452 | intel_clock_t *reduced_clock) |
eb1cbe48 | 7453 | { |
f47709a9 | 7454 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7455 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7456 | u32 dpll; |
7457 | bool is_sdvo; | |
190f68c5 | 7458 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7459 | |
190f68c5 | 7460 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7461 | |
a93e255f ACO |
7462 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7463 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7464 | |
7465 | dpll = DPLL_VGA_MODE_DIS; | |
7466 | ||
a93e255f | 7467 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7468 | dpll |= DPLLB_MODE_LVDS; |
7469 | else | |
7470 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7471 | |
ef1b460d | 7472 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7473 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7474 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7475 | } |
198a037f DV |
7476 | |
7477 | if (is_sdvo) | |
4a33e48d | 7478 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7479 | |
190f68c5 | 7480 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7481 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7482 | |
7483 | /* compute bitmask from p1 value */ | |
7484 | if (IS_PINEVIEW(dev)) | |
7485 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7486 | else { | |
7487 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7488 | if (IS_G4X(dev) && reduced_clock) | |
7489 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7490 | } | |
7491 | switch (clock->p2) { | |
7492 | case 5: | |
7493 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7494 | break; | |
7495 | case 7: | |
7496 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7497 | break; | |
7498 | case 10: | |
7499 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7500 | break; | |
7501 | case 14: | |
7502 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7503 | break; | |
7504 | } | |
7505 | if (INTEL_INFO(dev)->gen >= 4) | |
7506 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7507 | ||
190f68c5 | 7508 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7509 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7510 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7511 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7512 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7513 | else | |
7514 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7515 | ||
7516 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7517 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7518 | |
eb1cbe48 | 7519 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7520 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7521 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7522 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7523 | } |
7524 | } | |
7525 | ||
251ac862 DV |
7526 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7527 | struct intel_crtc_state *crtc_state, | |
ceb41007 | 7528 | intel_clock_t *reduced_clock) |
eb1cbe48 | 7529 | { |
f47709a9 | 7530 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7531 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7532 | u32 dpll; |
190f68c5 | 7533 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7534 | |
190f68c5 | 7535 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7536 | |
eb1cbe48 DV |
7537 | dpll = DPLL_VGA_MODE_DIS; |
7538 | ||
a93e255f | 7539 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7540 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7541 | } else { | |
7542 | if (clock->p1 == 2) | |
7543 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7544 | else | |
7545 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7546 | if (clock->p2 == 4) | |
7547 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7548 | } | |
7549 | ||
a93e255f | 7550 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7551 | dpll |= DPLL_DVO_2X_MODE; |
7552 | ||
a93e255f | 7553 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7554 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7555 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7556 | else | |
7557 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7558 | ||
7559 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7560 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7561 | } |
7562 | ||
8a654f3b | 7563 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7564 | { |
7565 | struct drm_device *dev = intel_crtc->base.dev; | |
7566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7567 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7568 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7569 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7570 | uint32_t crtc_vtotal, crtc_vblank_end; |
7571 | int vsyncshift = 0; | |
4d8a62ea DV |
7572 | |
7573 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7574 | * the hw state checker will get angry at the mismatch. */ | |
7575 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7576 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7577 | |
609aeaca | 7578 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7579 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7580 | crtc_vtotal -= 1; |
7581 | crtc_vblank_end -= 1; | |
609aeaca | 7582 | |
409ee761 | 7583 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7584 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7585 | else | |
7586 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7587 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7588 | if (vsyncshift < 0) |
7589 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7590 | } |
7591 | ||
7592 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7593 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7594 | |
fe2b8f9d | 7595 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7596 | (adjusted_mode->crtc_hdisplay - 1) | |
7597 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7598 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7599 | (adjusted_mode->crtc_hblank_start - 1) | |
7600 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7601 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7602 | (adjusted_mode->crtc_hsync_start - 1) | |
7603 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7604 | ||
fe2b8f9d | 7605 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7606 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7607 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7608 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7609 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7610 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7611 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7612 | (adjusted_mode->crtc_vsync_start - 1) | |
7613 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7614 | ||
b5e508d4 PZ |
7615 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7616 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7617 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7618 | * bits. */ | |
7619 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7620 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7621 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7622 | ||
bc58be60 JN |
7623 | } |
7624 | ||
7625 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7626 | { | |
7627 | struct drm_device *dev = intel_crtc->base.dev; | |
7628 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7629 | enum pipe pipe = intel_crtc->pipe; | |
7630 | ||
b0e77b9c PZ |
7631 | /* pipesrc controls the size that is scaled from, which should |
7632 | * always be the user's requested size. | |
7633 | */ | |
7634 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7635 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7636 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7637 | } |
7638 | ||
1bd1bd80 | 7639 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7640 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7641 | { |
7642 | struct drm_device *dev = crtc->base.dev; | |
7643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7644 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7645 | uint32_t tmp; | |
7646 | ||
7647 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7648 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7649 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7650 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7651 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7652 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7653 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7654 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7655 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7656 | |
7657 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7658 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7659 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7660 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7661 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7662 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7663 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7664 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7665 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7666 | |
7667 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7668 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7669 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7670 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7671 | } |
bc58be60 JN |
7672 | } |
7673 | ||
7674 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7675 | struct intel_crtc_state *pipe_config) | |
7676 | { | |
7677 | struct drm_device *dev = crtc->base.dev; | |
7678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7679 | u32 tmp; | |
1bd1bd80 DV |
7680 | |
7681 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7682 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7683 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7684 | ||
2d112de7 ACO |
7685 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7686 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7687 | } |
7688 | ||
f6a83288 | 7689 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7690 | struct intel_crtc_state *pipe_config) |
babea61d | 7691 | { |
2d112de7 ACO |
7692 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7693 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7694 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7695 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7696 | |
2d112de7 ACO |
7697 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7698 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7699 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7700 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7701 | |
2d112de7 | 7702 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7703 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7704 | |
2d112de7 ACO |
7705 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7706 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7707 | |
7708 | mode->hsync = drm_mode_hsync(mode); | |
7709 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7710 | drm_mode_set_name(mode); | |
babea61d JB |
7711 | } |
7712 | ||
84b046f3 DV |
7713 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7714 | { | |
7715 | struct drm_device *dev = intel_crtc->base.dev; | |
7716 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7717 | uint32_t pipeconf; | |
7718 | ||
9f11a9e4 | 7719 | pipeconf = 0; |
84b046f3 | 7720 | |
b6b5d049 VS |
7721 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7722 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7723 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7724 | |
6e3c9717 | 7725 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7726 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7727 | |
ff9ce46e | 7728 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7729 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7730 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7731 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7732 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7733 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7734 | |
6e3c9717 | 7735 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7736 | case 18: |
7737 | pipeconf |= PIPECONF_6BPC; | |
7738 | break; | |
7739 | case 24: | |
7740 | pipeconf |= PIPECONF_8BPC; | |
7741 | break; | |
7742 | case 30: | |
7743 | pipeconf |= PIPECONF_10BPC; | |
7744 | break; | |
7745 | default: | |
7746 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7747 | BUG(); | |
84b046f3 DV |
7748 | } |
7749 | } | |
7750 | ||
7751 | if (HAS_PIPE_CXSR(dev)) { | |
7752 | if (intel_crtc->lowfreq_avail) { | |
7753 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7754 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7755 | } else { | |
7756 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7757 | } |
7758 | } | |
7759 | ||
6e3c9717 | 7760 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7761 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7762 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7763 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7764 | else | |
7765 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7766 | } else | |
84b046f3 DV |
7767 | pipeconf |= PIPECONF_PROGRESSIVE; |
7768 | ||
666a4537 WB |
7769 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7770 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7771 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7772 | |
84b046f3 DV |
7773 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7774 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7775 | } | |
7776 | ||
81c97f52 ACO |
7777 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7778 | struct intel_crtc_state *crtc_state) | |
7779 | { | |
7780 | struct drm_device *dev = crtc->base.dev; | |
7781 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7782 | const intel_limit_t *limit; | |
7783 | int refclk = 48000; | |
7784 | ||
7785 | memset(&crtc_state->dpll_hw_state, 0, | |
7786 | sizeof(crtc_state->dpll_hw_state)); | |
7787 | ||
7788 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7789 | if (intel_panel_use_ssc(dev_priv)) { | |
7790 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7791 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7792 | } | |
7793 | ||
7794 | limit = &intel_limits_i8xx_lvds; | |
7795 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) { | |
7796 | limit = &intel_limits_i8xx_dvo; | |
7797 | } else { | |
7798 | limit = &intel_limits_i8xx_dac; | |
7799 | } | |
7800 | ||
7801 | if (!crtc_state->clock_set && | |
7802 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7803 | refclk, NULL, &crtc_state->dpll)) { | |
7804 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7805 | return -EINVAL; | |
7806 | } | |
7807 | ||
7808 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7809 | ||
7810 | return 0; | |
7811 | } | |
7812 | ||
19ec6693 ACO |
7813 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7814 | struct intel_crtc_state *crtc_state) | |
7815 | { | |
7816 | struct drm_device *dev = crtc->base.dev; | |
7817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7818 | const intel_limit_t *limit; | |
7819 | int refclk = 96000; | |
7820 | ||
7821 | memset(&crtc_state->dpll_hw_state, 0, | |
7822 | sizeof(crtc_state->dpll_hw_state)); | |
7823 | ||
7824 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7825 | if (intel_panel_use_ssc(dev_priv)) { | |
7826 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7827 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7828 | } | |
7829 | ||
7830 | if (intel_is_dual_link_lvds(dev)) | |
7831 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7832 | else | |
7833 | limit = &intel_limits_g4x_single_channel_lvds; | |
7834 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || | |
7835 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
7836 | limit = &intel_limits_g4x_hdmi; | |
7837 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { | |
7838 | limit = &intel_limits_g4x_sdvo; | |
7839 | } else { | |
7840 | /* The option is for other outputs */ | |
7841 | limit = &intel_limits_i9xx_sdvo; | |
7842 | } | |
7843 | ||
7844 | if (!crtc_state->clock_set && | |
7845 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7846 | refclk, NULL, &crtc_state->dpll)) { | |
7847 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7848 | return -EINVAL; | |
7849 | } | |
7850 | ||
7851 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7852 | ||
7853 | return 0; | |
7854 | } | |
7855 | ||
70e8aa21 ACO |
7856 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7857 | struct intel_crtc_state *crtc_state) | |
7858 | { | |
7859 | struct drm_device *dev = crtc->base.dev; | |
7860 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7861 | const intel_limit_t *limit; | |
7862 | int refclk = 96000; | |
7863 | ||
7864 | memset(&crtc_state->dpll_hw_state, 0, | |
7865 | sizeof(crtc_state->dpll_hw_state)); | |
7866 | ||
7867 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7868 | if (intel_panel_use_ssc(dev_priv)) { | |
7869 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7870 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7871 | } | |
7872 | ||
7873 | limit = &intel_limits_pineview_lvds; | |
7874 | } else { | |
7875 | limit = &intel_limits_pineview_sdvo; | |
7876 | } | |
7877 | ||
7878 | if (!crtc_state->clock_set && | |
7879 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7880 | refclk, NULL, &crtc_state->dpll)) { | |
7881 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7882 | return -EINVAL; | |
7883 | } | |
7884 | ||
7885 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7886 | ||
7887 | return 0; | |
7888 | } | |
7889 | ||
190f68c5 ACO |
7890 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7891 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7892 | { |
c7653199 | 7893 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7894 | struct drm_i915_private *dev_priv = dev->dev_private; |
d4906093 | 7895 | const intel_limit_t *limit; |
81c97f52 | 7896 | int refclk = 96000; |
79e53945 | 7897 | |
dd3cd74a ACO |
7898 | memset(&crtc_state->dpll_hw_state, 0, |
7899 | sizeof(crtc_state->dpll_hw_state)); | |
7900 | ||
70e8aa21 ACO |
7901 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
7902 | if (intel_panel_use_ssc(dev_priv)) { | |
7903 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7904 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7905 | } | |
43565a06 | 7906 | |
70e8aa21 ACO |
7907 | limit = &intel_limits_i9xx_lvds; |
7908 | } else { | |
7909 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7910 | } |
79e53945 | 7911 | |
70e8aa21 ACO |
7912 | if (!crtc_state->clock_set && |
7913 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7914 | refclk, NULL, &crtc_state->dpll)) { | |
7915 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7916 | return -EINVAL; | |
f47709a9 | 7917 | } |
7026d4ac | 7918 | |
81c97f52 | 7919 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7920 | |
c8f7a0db | 7921 | return 0; |
f564048e EA |
7922 | } |
7923 | ||
65b3d6a9 ACO |
7924 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7925 | struct intel_crtc_state *crtc_state) | |
7926 | { | |
7927 | int refclk = 100000; | |
7928 | const intel_limit_t *limit = &intel_limits_chv; | |
7929 | ||
7930 | memset(&crtc_state->dpll_hw_state, 0, | |
7931 | sizeof(crtc_state->dpll_hw_state)); | |
7932 | ||
7933 | if (crtc_state->has_dsi_encoder) | |
7934 | return 0; | |
7935 | ||
7936 | if (!crtc_state->clock_set && | |
7937 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7938 | refclk, NULL, &crtc_state->dpll)) { | |
7939 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7940 | return -EINVAL; | |
7941 | } | |
7942 | ||
7943 | chv_compute_dpll(crtc, crtc_state); | |
7944 | ||
7945 | return 0; | |
7946 | } | |
7947 | ||
7948 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7949 | struct intel_crtc_state *crtc_state) | |
7950 | { | |
7951 | int refclk = 100000; | |
7952 | const intel_limit_t *limit = &intel_limits_vlv; | |
7953 | ||
7954 | memset(&crtc_state->dpll_hw_state, 0, | |
7955 | sizeof(crtc_state->dpll_hw_state)); | |
7956 | ||
7957 | if (crtc_state->has_dsi_encoder) | |
7958 | return 0; | |
7959 | ||
7960 | if (!crtc_state->clock_set && | |
7961 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7962 | refclk, NULL, &crtc_state->dpll)) { | |
7963 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7964 | return -EINVAL; | |
7965 | } | |
7966 | ||
7967 | vlv_compute_dpll(crtc, crtc_state); | |
7968 | ||
7969 | return 0; | |
7970 | } | |
7971 | ||
2fa2fe9a | 7972 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7973 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7974 | { |
7975 | struct drm_device *dev = crtc->base.dev; | |
7976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7977 | uint32_t tmp; | |
7978 | ||
dc9e7dec VS |
7979 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7980 | return; | |
7981 | ||
2fa2fe9a | 7982 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7983 | if (!(tmp & PFIT_ENABLE)) |
7984 | return; | |
2fa2fe9a | 7985 | |
06922821 | 7986 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7987 | if (INTEL_INFO(dev)->gen < 4) { |
7988 | if (crtc->pipe != PIPE_B) | |
7989 | return; | |
2fa2fe9a DV |
7990 | } else { |
7991 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7992 | return; | |
7993 | } | |
7994 | ||
06922821 | 7995 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7996 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7997 | if (INTEL_INFO(dev)->gen < 5) | |
7998 | pipe_config->gmch_pfit.lvds_border_bits = | |
7999 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8000 | } | |
8001 | ||
acbec814 | 8002 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8003 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8004 | { |
8005 | struct drm_device *dev = crtc->base.dev; | |
8006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8007 | int pipe = pipe_config->cpu_transcoder; | |
8008 | intel_clock_t clock; | |
8009 | u32 mdiv; | |
662c6ecb | 8010 | int refclk = 100000; |
acbec814 | 8011 | |
f573de5a SK |
8012 | /* In case of MIPI DPLL will not even be used */ |
8013 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8014 | return; | |
8015 | ||
a580516d | 8016 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8017 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8018 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8019 | |
8020 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8021 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8022 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8023 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8024 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8025 | ||
dccbea3b | 8026 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8027 | } |
8028 | ||
5724dbd1 DL |
8029 | static void |
8030 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8031 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8032 | { |
8033 | struct drm_device *dev = crtc->base.dev; | |
8034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8035 | u32 val, base, offset; | |
8036 | int pipe = crtc->pipe, plane = crtc->plane; | |
8037 | int fourcc, pixel_format; | |
6761dd31 | 8038 | unsigned int aligned_height; |
b113d5ee | 8039 | struct drm_framebuffer *fb; |
1b842c89 | 8040 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8041 | |
42a7b088 DL |
8042 | val = I915_READ(DSPCNTR(plane)); |
8043 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8044 | return; | |
8045 | ||
d9806c9f | 8046 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8047 | if (!intel_fb) { |
1ad292b5 JB |
8048 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8049 | return; | |
8050 | } | |
8051 | ||
1b842c89 DL |
8052 | fb = &intel_fb->base; |
8053 | ||
18c5247e DV |
8054 | if (INTEL_INFO(dev)->gen >= 4) { |
8055 | if (val & DISPPLANE_TILED) { | |
49af449b | 8056 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8057 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8058 | } | |
8059 | } | |
1ad292b5 JB |
8060 | |
8061 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8062 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8063 | fb->pixel_format = fourcc; |
8064 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8065 | |
8066 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8067 | if (plane_config->tiling) |
1ad292b5 JB |
8068 | offset = I915_READ(DSPTILEOFF(plane)); |
8069 | else | |
8070 | offset = I915_READ(DSPLINOFF(plane)); | |
8071 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8072 | } else { | |
8073 | base = I915_READ(DSPADDR(plane)); | |
8074 | } | |
8075 | plane_config->base = base; | |
8076 | ||
8077 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8078 | fb->width = ((val >> 16) & 0xfff) + 1; |
8079 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8080 | |
8081 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8082 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8083 | |
b113d5ee | 8084 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8085 | fb->pixel_format, |
8086 | fb->modifier[0]); | |
1ad292b5 | 8087 | |
f37b5c2b | 8088 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8089 | |
2844a921 DL |
8090 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8091 | pipe_name(pipe), plane, fb->width, fb->height, | |
8092 | fb->bits_per_pixel, base, fb->pitches[0], | |
8093 | plane_config->size); | |
1ad292b5 | 8094 | |
2d14030b | 8095 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8096 | } |
8097 | ||
70b23a98 | 8098 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8099 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8100 | { |
8101 | struct drm_device *dev = crtc->base.dev; | |
8102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8103 | int pipe = pipe_config->cpu_transcoder; | |
8104 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8105 | intel_clock_t clock; | |
0d7b6b11 | 8106 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8107 | int refclk = 100000; |
8108 | ||
a580516d | 8109 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8110 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8111 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8112 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8113 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8114 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8115 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8116 | |
8117 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8118 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8119 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8120 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8121 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8122 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8123 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8124 | ||
dccbea3b | 8125 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8126 | } |
8127 | ||
0e8ffe1b | 8128 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8129 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8130 | { |
8131 | struct drm_device *dev = crtc->base.dev; | |
8132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8133 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8134 | uint32_t tmp; |
1729050e | 8135 | bool ret; |
0e8ffe1b | 8136 | |
1729050e ID |
8137 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8138 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8139 | return false; |
8140 | ||
e143a21c | 8141 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8142 | pipe_config->shared_dpll = NULL; |
eccb140b | 8143 | |
1729050e ID |
8144 | ret = false; |
8145 | ||
0e8ffe1b DV |
8146 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8147 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8148 | goto out; |
0e8ffe1b | 8149 | |
666a4537 | 8150 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8151 | switch (tmp & PIPECONF_BPC_MASK) { |
8152 | case PIPECONF_6BPC: | |
8153 | pipe_config->pipe_bpp = 18; | |
8154 | break; | |
8155 | case PIPECONF_8BPC: | |
8156 | pipe_config->pipe_bpp = 24; | |
8157 | break; | |
8158 | case PIPECONF_10BPC: | |
8159 | pipe_config->pipe_bpp = 30; | |
8160 | break; | |
8161 | default: | |
8162 | break; | |
8163 | } | |
8164 | } | |
8165 | ||
666a4537 WB |
8166 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8167 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8168 | pipe_config->limited_color_range = true; |
8169 | ||
282740f7 VS |
8170 | if (INTEL_INFO(dev)->gen < 4) |
8171 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8172 | ||
1bd1bd80 | 8173 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8174 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8175 | |
2fa2fe9a DV |
8176 | i9xx_get_pfit_config(crtc, pipe_config); |
8177 | ||
6c49f241 | 8178 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c VS |
8179 | /* No way to read it out on pipes B and C */ |
8180 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8181 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8182 | else | |
8183 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8184 | pipe_config->pixel_multiplier = |
8185 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8186 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8187 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8188 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8189 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8190 | pipe_config->pixel_multiplier = | |
8191 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8192 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8193 | } else { | |
8194 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8195 | * port and will be fixed up in the encoder->get_config | |
8196 | * function. */ | |
8197 | pipe_config->pixel_multiplier = 1; | |
8198 | } | |
8bcc2795 | 8199 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8200 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8201 | /* |
8202 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8203 | * on 830. Filter it out here so that we don't | |
8204 | * report errors due to that. | |
8205 | */ | |
8206 | if (IS_I830(dev)) | |
8207 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8208 | ||
8bcc2795 DV |
8209 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8210 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8211 | } else { |
8212 | /* Mask out read-only status bits. */ | |
8213 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8214 | DPLL_PORTC_READY_MASK | | |
8215 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8216 | } |
6c49f241 | 8217 | |
70b23a98 VS |
8218 | if (IS_CHERRYVIEW(dev)) |
8219 | chv_crtc_clock_get(crtc, pipe_config); | |
8220 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8221 | vlv_crtc_clock_get(crtc, pipe_config); |
8222 | else | |
8223 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8224 | |
0f64614d VS |
8225 | /* |
8226 | * Normally the dotclock is filled in by the encoder .get_config() | |
8227 | * but in case the pipe is enabled w/o any ports we need a sane | |
8228 | * default. | |
8229 | */ | |
8230 | pipe_config->base.adjusted_mode.crtc_clock = | |
8231 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8232 | ||
1729050e ID |
8233 | ret = true; |
8234 | ||
8235 | out: | |
8236 | intel_display_power_put(dev_priv, power_domain); | |
8237 | ||
8238 | return ret; | |
0e8ffe1b DV |
8239 | } |
8240 | ||
dde86e2d | 8241 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8242 | { |
8243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8244 | struct intel_encoder *encoder; |
74cfd7ac | 8245 | u32 val, final; |
13d83a67 | 8246 | bool has_lvds = false; |
199e5d79 | 8247 | bool has_cpu_edp = false; |
199e5d79 | 8248 | bool has_panel = false; |
99eb6a01 KP |
8249 | bool has_ck505 = false; |
8250 | bool can_ssc = false; | |
13d83a67 JB |
8251 | |
8252 | /* We need to take the global config into account */ | |
b2784e15 | 8253 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8254 | switch (encoder->type) { |
8255 | case INTEL_OUTPUT_LVDS: | |
8256 | has_panel = true; | |
8257 | has_lvds = true; | |
8258 | break; | |
8259 | case INTEL_OUTPUT_EDP: | |
8260 | has_panel = true; | |
2de6905f | 8261 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8262 | has_cpu_edp = true; |
8263 | break; | |
6847d71b PZ |
8264 | default: |
8265 | break; | |
13d83a67 JB |
8266 | } |
8267 | } | |
8268 | ||
99eb6a01 | 8269 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8270 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8271 | can_ssc = has_ck505; |
8272 | } else { | |
8273 | has_ck505 = false; | |
8274 | can_ssc = true; | |
8275 | } | |
8276 | ||
2de6905f ID |
8277 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8278 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8279 | |
8280 | /* Ironlake: try to setup display ref clock before DPLL | |
8281 | * enabling. This is only under driver's control after | |
8282 | * PCH B stepping, previous chipset stepping should be | |
8283 | * ignoring this setting. | |
8284 | */ | |
74cfd7ac CW |
8285 | val = I915_READ(PCH_DREF_CONTROL); |
8286 | ||
8287 | /* As we must carefully and slowly disable/enable each source in turn, | |
8288 | * compute the final state we want first and check if we need to | |
8289 | * make any changes at all. | |
8290 | */ | |
8291 | final = val; | |
8292 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8293 | if (has_ck505) | |
8294 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8295 | else | |
8296 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8297 | ||
8298 | final &= ~DREF_SSC_SOURCE_MASK; | |
8299 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8300 | final &= ~DREF_SSC1_ENABLE; | |
8301 | ||
8302 | if (has_panel) { | |
8303 | final |= DREF_SSC_SOURCE_ENABLE; | |
8304 | ||
8305 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8306 | final |= DREF_SSC1_ENABLE; | |
8307 | ||
8308 | if (has_cpu_edp) { | |
8309 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8310 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8311 | else | |
8312 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8313 | } else | |
8314 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8315 | } else { | |
8316 | final |= DREF_SSC_SOURCE_DISABLE; | |
8317 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8318 | } | |
8319 | ||
8320 | if (final == val) | |
8321 | return; | |
8322 | ||
13d83a67 | 8323 | /* Always enable nonspread source */ |
74cfd7ac | 8324 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8325 | |
99eb6a01 | 8326 | if (has_ck505) |
74cfd7ac | 8327 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8328 | else |
74cfd7ac | 8329 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8330 | |
199e5d79 | 8331 | if (has_panel) { |
74cfd7ac CW |
8332 | val &= ~DREF_SSC_SOURCE_MASK; |
8333 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8334 | |
199e5d79 | 8335 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8336 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8337 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8338 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8339 | } else |
74cfd7ac | 8340 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8341 | |
8342 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8343 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8344 | POSTING_READ(PCH_DREF_CONTROL); |
8345 | udelay(200); | |
8346 | ||
74cfd7ac | 8347 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8348 | |
8349 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8350 | if (has_cpu_edp) { |
99eb6a01 | 8351 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8352 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8353 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8354 | } else |
74cfd7ac | 8355 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8356 | } else |
74cfd7ac | 8357 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8358 | |
74cfd7ac | 8359 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8360 | POSTING_READ(PCH_DREF_CONTROL); |
8361 | udelay(200); | |
8362 | } else { | |
8363 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8364 | ||
74cfd7ac | 8365 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8366 | |
8367 | /* Turn off CPU output */ | |
74cfd7ac | 8368 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8369 | |
74cfd7ac | 8370 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8371 | POSTING_READ(PCH_DREF_CONTROL); |
8372 | udelay(200); | |
8373 | ||
8374 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8375 | val &= ~DREF_SSC_SOURCE_MASK; |
8376 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8377 | |
8378 | /* Turn off SSC1 */ | |
74cfd7ac | 8379 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8380 | |
74cfd7ac | 8381 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8382 | POSTING_READ(PCH_DREF_CONTROL); |
8383 | udelay(200); | |
8384 | } | |
74cfd7ac CW |
8385 | |
8386 | BUG_ON(val != final); | |
13d83a67 JB |
8387 | } |
8388 | ||
f31f2d55 | 8389 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8390 | { |
f31f2d55 | 8391 | uint32_t tmp; |
dde86e2d | 8392 | |
0ff066a9 PZ |
8393 | tmp = I915_READ(SOUTH_CHICKEN2); |
8394 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8395 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8396 | |
0ff066a9 PZ |
8397 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8398 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8399 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8400 | |
0ff066a9 PZ |
8401 | tmp = I915_READ(SOUTH_CHICKEN2); |
8402 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8403 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8404 | |
0ff066a9 PZ |
8405 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8406 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8407 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8408 | } |
8409 | ||
8410 | /* WaMPhyProgramming:hsw */ | |
8411 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8412 | { | |
8413 | uint32_t tmp; | |
dde86e2d PZ |
8414 | |
8415 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8416 | tmp &= ~(0xFF << 24); | |
8417 | tmp |= (0x12 << 24); | |
8418 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8419 | ||
dde86e2d PZ |
8420 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8421 | tmp |= (1 << 11); | |
8422 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8423 | ||
8424 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8425 | tmp |= (1 << 11); | |
8426 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8427 | ||
dde86e2d PZ |
8428 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8429 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8430 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8431 | ||
8432 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8433 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8434 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8435 | ||
0ff066a9 PZ |
8436 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8437 | tmp &= ~(7 << 13); | |
8438 | tmp |= (5 << 13); | |
8439 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8440 | |
0ff066a9 PZ |
8441 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8442 | tmp &= ~(7 << 13); | |
8443 | tmp |= (5 << 13); | |
8444 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8445 | |
8446 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8447 | tmp &= ~0xFF; | |
8448 | tmp |= 0x1C; | |
8449 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8450 | ||
8451 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8452 | tmp &= ~0xFF; | |
8453 | tmp |= 0x1C; | |
8454 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8455 | ||
8456 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8457 | tmp &= ~(0xFF << 16); | |
8458 | tmp |= (0x1C << 16); | |
8459 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8460 | ||
8461 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8462 | tmp &= ~(0xFF << 16); | |
8463 | tmp |= (0x1C << 16); | |
8464 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8465 | ||
0ff066a9 PZ |
8466 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8467 | tmp |= (1 << 27); | |
8468 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8469 | |
0ff066a9 PZ |
8470 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8471 | tmp |= (1 << 27); | |
8472 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8473 | |
0ff066a9 PZ |
8474 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8475 | tmp &= ~(0xF << 28); | |
8476 | tmp |= (4 << 28); | |
8477 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8478 | |
0ff066a9 PZ |
8479 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8480 | tmp &= ~(0xF << 28); | |
8481 | tmp |= (4 << 28); | |
8482 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8483 | } |
8484 | ||
2fa86a1f PZ |
8485 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8486 | * Programming" based on the parameters passed: | |
8487 | * - Sequence to enable CLKOUT_DP | |
8488 | * - Sequence to enable CLKOUT_DP without spread | |
8489 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8490 | */ | |
8491 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8492 | bool with_fdi) | |
f31f2d55 PZ |
8493 | { |
8494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8495 | uint32_t reg, tmp; |
8496 | ||
8497 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8498 | with_spread = true; | |
c2699524 | 8499 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8500 | with_fdi = false; |
f31f2d55 | 8501 | |
a580516d | 8502 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8503 | |
8504 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8505 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8506 | tmp |= SBI_SSCCTL_PATHALT; | |
8507 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8508 | ||
8509 | udelay(24); | |
8510 | ||
2fa86a1f PZ |
8511 | if (with_spread) { |
8512 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8513 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8514 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8515 | |
2fa86a1f PZ |
8516 | if (with_fdi) { |
8517 | lpt_reset_fdi_mphy(dev_priv); | |
8518 | lpt_program_fdi_mphy(dev_priv); | |
8519 | } | |
8520 | } | |
dde86e2d | 8521 | |
c2699524 | 8522 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8523 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8524 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8525 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8526 | |
a580516d | 8527 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8528 | } |
8529 | ||
47701c3b PZ |
8530 | /* Sequence to disable CLKOUT_DP */ |
8531 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8532 | { | |
8533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8534 | uint32_t reg, tmp; | |
8535 | ||
a580516d | 8536 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8537 | |
c2699524 | 8538 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8539 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8540 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8541 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8542 | ||
8543 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8544 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8545 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8546 | tmp |= SBI_SSCCTL_PATHALT; | |
8547 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8548 | udelay(32); | |
8549 | } | |
8550 | tmp |= SBI_SSCCTL_DISABLE; | |
8551 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8552 | } | |
8553 | ||
a580516d | 8554 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8555 | } |
8556 | ||
f7be2c21 VS |
8557 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8558 | ||
8559 | static const uint16_t sscdivintphase[] = { | |
8560 | [BEND_IDX( 50)] = 0x3B23, | |
8561 | [BEND_IDX( 45)] = 0x3B23, | |
8562 | [BEND_IDX( 40)] = 0x3C23, | |
8563 | [BEND_IDX( 35)] = 0x3C23, | |
8564 | [BEND_IDX( 30)] = 0x3D23, | |
8565 | [BEND_IDX( 25)] = 0x3D23, | |
8566 | [BEND_IDX( 20)] = 0x3E23, | |
8567 | [BEND_IDX( 15)] = 0x3E23, | |
8568 | [BEND_IDX( 10)] = 0x3F23, | |
8569 | [BEND_IDX( 5)] = 0x3F23, | |
8570 | [BEND_IDX( 0)] = 0x0025, | |
8571 | [BEND_IDX( -5)] = 0x0025, | |
8572 | [BEND_IDX(-10)] = 0x0125, | |
8573 | [BEND_IDX(-15)] = 0x0125, | |
8574 | [BEND_IDX(-20)] = 0x0225, | |
8575 | [BEND_IDX(-25)] = 0x0225, | |
8576 | [BEND_IDX(-30)] = 0x0325, | |
8577 | [BEND_IDX(-35)] = 0x0325, | |
8578 | [BEND_IDX(-40)] = 0x0425, | |
8579 | [BEND_IDX(-45)] = 0x0425, | |
8580 | [BEND_IDX(-50)] = 0x0525, | |
8581 | }; | |
8582 | ||
8583 | /* | |
8584 | * Bend CLKOUT_DP | |
8585 | * steps -50 to 50 inclusive, in steps of 5 | |
8586 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8587 | * change in clock period = -(steps / 10) * 5.787 ps | |
8588 | */ | |
8589 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8590 | { | |
8591 | uint32_t tmp; | |
8592 | int idx = BEND_IDX(steps); | |
8593 | ||
8594 | if (WARN_ON(steps % 5 != 0)) | |
8595 | return; | |
8596 | ||
8597 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8598 | return; | |
8599 | ||
8600 | mutex_lock(&dev_priv->sb_lock); | |
8601 | ||
8602 | if (steps % 10 != 0) | |
8603 | tmp = 0xAAAAAAAB; | |
8604 | else | |
8605 | tmp = 0x00000000; | |
8606 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8607 | ||
8608 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8609 | tmp &= 0xffff0000; | |
8610 | tmp |= sscdivintphase[idx]; | |
8611 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8612 | ||
8613 | mutex_unlock(&dev_priv->sb_lock); | |
8614 | } | |
8615 | ||
8616 | #undef BEND_IDX | |
8617 | ||
bf8fa3d3 PZ |
8618 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8619 | { | |
bf8fa3d3 PZ |
8620 | struct intel_encoder *encoder; |
8621 | bool has_vga = false; | |
8622 | ||
b2784e15 | 8623 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8624 | switch (encoder->type) { |
8625 | case INTEL_OUTPUT_ANALOG: | |
8626 | has_vga = true; | |
8627 | break; | |
6847d71b PZ |
8628 | default: |
8629 | break; | |
bf8fa3d3 PZ |
8630 | } |
8631 | } | |
8632 | ||
f7be2c21 VS |
8633 | if (has_vga) { |
8634 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8635 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8636 | } else { |
47701c3b | 8637 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8638 | } |
bf8fa3d3 PZ |
8639 | } |
8640 | ||
dde86e2d PZ |
8641 | /* |
8642 | * Initialize reference clocks when the driver loads | |
8643 | */ | |
8644 | void intel_init_pch_refclk(struct drm_device *dev) | |
8645 | { | |
8646 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8647 | ironlake_init_pch_refclk(dev); | |
8648 | else if (HAS_PCH_LPT(dev)) | |
8649 | lpt_init_pch_refclk(dev); | |
8650 | } | |
8651 | ||
6ff93609 | 8652 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8653 | { |
c8203565 | 8654 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8655 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8656 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8657 | uint32_t val; |
8658 | ||
78114071 | 8659 | val = 0; |
c8203565 | 8660 | |
6e3c9717 | 8661 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8662 | case 18: |
dfd07d72 | 8663 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8664 | break; |
8665 | case 24: | |
dfd07d72 | 8666 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8667 | break; |
8668 | case 30: | |
dfd07d72 | 8669 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8670 | break; |
8671 | case 36: | |
dfd07d72 | 8672 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8673 | break; |
8674 | default: | |
cc769b62 PZ |
8675 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8676 | BUG(); | |
c8203565 PZ |
8677 | } |
8678 | ||
6e3c9717 | 8679 | if (intel_crtc->config->dither) |
c8203565 PZ |
8680 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8681 | ||
6e3c9717 | 8682 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8683 | val |= PIPECONF_INTERLACED_ILK; |
8684 | else | |
8685 | val |= PIPECONF_PROGRESSIVE; | |
8686 | ||
6e3c9717 | 8687 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8688 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8689 | |
c8203565 PZ |
8690 | I915_WRITE(PIPECONF(pipe), val); |
8691 | POSTING_READ(PIPECONF(pipe)); | |
8692 | } | |
8693 | ||
6ff93609 | 8694 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8695 | { |
391bf048 | 8696 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
ee2b0b38 | 8697 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8698 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8699 | u32 val = 0; |
ee2b0b38 | 8700 | |
391bf048 | 8701 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8702 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8703 | ||
6e3c9717 | 8704 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8705 | val |= PIPECONF_INTERLACED_ILK; |
8706 | else | |
8707 | val |= PIPECONF_PROGRESSIVE; | |
8708 | ||
702e7a56 PZ |
8709 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8710 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8711 | } |
8712 | ||
391bf048 JN |
8713 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8714 | { | |
8715 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
8716 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
756f85cf | 8717 | |
391bf048 JN |
8718 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8719 | u32 val = 0; | |
756f85cf | 8720 | |
6e3c9717 | 8721 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8722 | case 18: |
8723 | val |= PIPEMISC_DITHER_6_BPC; | |
8724 | break; | |
8725 | case 24: | |
8726 | val |= PIPEMISC_DITHER_8_BPC; | |
8727 | break; | |
8728 | case 30: | |
8729 | val |= PIPEMISC_DITHER_10_BPC; | |
8730 | break; | |
8731 | case 36: | |
8732 | val |= PIPEMISC_DITHER_12_BPC; | |
8733 | break; | |
8734 | default: | |
8735 | /* Case prevented by pipe_config_set_bpp. */ | |
8736 | BUG(); | |
8737 | } | |
8738 | ||
6e3c9717 | 8739 | if (intel_crtc->config->dither) |
756f85cf PZ |
8740 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8741 | ||
391bf048 | 8742 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8743 | } |
ee2b0b38 PZ |
8744 | } |
8745 | ||
d4b1931c PZ |
8746 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8747 | { | |
8748 | /* | |
8749 | * Account for spread spectrum to avoid | |
8750 | * oversubscribing the link. Max center spread | |
8751 | * is 2.5%; use 5% for safety's sake. | |
8752 | */ | |
8753 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8754 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8755 | } |
8756 | ||
7429e9d4 | 8757 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8758 | { |
7429e9d4 | 8759 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8760 | } |
8761 | ||
b75ca6f6 ACO |
8762 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8763 | struct intel_crtc_state *crtc_state, | |
8764 | intel_clock_t *reduced_clock) | |
79e53945 | 8765 | { |
de13a2e3 | 8766 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8767 | struct drm_device *dev = crtc->dev; |
8768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8769 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8770 | struct drm_connector *connector; |
55bb9992 ACO |
8771 | struct drm_connector_state *connector_state; |
8772 | struct intel_encoder *encoder; | |
b75ca6f6 | 8773 | u32 dpll, fp, fp2; |
ceb41007 | 8774 | int factor, i; |
09ede541 | 8775 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8776 | |
da3ced29 | 8777 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8778 | if (connector_state->crtc != crtc_state->base.crtc) |
8779 | continue; | |
8780 | ||
8781 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8782 | ||
8783 | switch (encoder->type) { | |
79e53945 JB |
8784 | case INTEL_OUTPUT_LVDS: |
8785 | is_lvds = true; | |
8786 | break; | |
8787 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8788 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8789 | is_sdvo = true; |
79e53945 | 8790 | break; |
6847d71b PZ |
8791 | default: |
8792 | break; | |
79e53945 JB |
8793 | } |
8794 | } | |
79e53945 | 8795 | |
c1858123 | 8796 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8797 | factor = 21; |
8798 | if (is_lvds) { | |
8799 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8800 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8801 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8802 | factor = 25; |
190f68c5 | 8803 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8804 | factor = 20; |
c1858123 | 8805 | |
b75ca6f6 ACO |
8806 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8807 | ||
190f68c5 | 8808 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8809 | fp |= FP_CB_TUNE; |
8810 | ||
8811 | if (reduced_clock) { | |
8812 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8813 | |
b75ca6f6 ACO |
8814 | if (reduced_clock->m < factor * reduced_clock->n) |
8815 | fp2 |= FP_CB_TUNE; | |
8816 | } else { | |
8817 | fp2 = fp; | |
8818 | } | |
9a7c7890 | 8819 | |
5eddb70b | 8820 | dpll = 0; |
2c07245f | 8821 | |
a07d6787 EA |
8822 | if (is_lvds) |
8823 | dpll |= DPLLB_MODE_LVDS; | |
8824 | else | |
8825 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8826 | |
190f68c5 | 8827 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8828 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8829 | |
8830 | if (is_sdvo) | |
4a33e48d | 8831 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8832 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8833 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8834 | |
a07d6787 | 8835 | /* compute bitmask from p1 value */ |
190f68c5 | 8836 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8837 | /* also FPA1 */ |
190f68c5 | 8838 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8839 | |
190f68c5 | 8840 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8841 | case 5: |
8842 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8843 | break; | |
8844 | case 7: | |
8845 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8846 | break; | |
8847 | case 10: | |
8848 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8849 | break; | |
8850 | case 14: | |
8851 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8852 | break; | |
79e53945 JB |
8853 | } |
8854 | ||
ceb41007 | 8855 | if (is_lvds && intel_panel_use_ssc(dev_priv)) |
43565a06 | 8856 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8857 | else |
8858 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8859 | ||
b75ca6f6 ACO |
8860 | dpll |= DPLL_VCO_ENABLE; |
8861 | ||
8862 | crtc_state->dpll_hw_state.dpll = dpll; | |
8863 | crtc_state->dpll_hw_state.fp0 = fp; | |
8864 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8865 | } |
8866 | ||
190f68c5 ACO |
8867 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8868 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8869 | { |
997c030c ACO |
8870 | struct drm_device *dev = crtc->base.dev; |
8871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
364ee29d | 8872 | intel_clock_t reduced_clock; |
7ed9f894 | 8873 | bool has_reduced_clock = false; |
e2b78267 | 8874 | struct intel_shared_dpll *pll; |
997c030c ACO |
8875 | const intel_limit_t *limit; |
8876 | int refclk = 120000; | |
de13a2e3 | 8877 | |
dd3cd74a ACO |
8878 | memset(&crtc_state->dpll_hw_state, 0, |
8879 | sizeof(crtc_state->dpll_hw_state)); | |
8880 | ||
ded220e2 ACO |
8881 | crtc->lowfreq_avail = false; |
8882 | ||
8883 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8884 | if (!crtc_state->has_pch_encoder) | |
8885 | return 0; | |
79e53945 | 8886 | |
997c030c ACO |
8887 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8888 | if (intel_panel_use_ssc(dev_priv)) { | |
8889 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8890 | dev_priv->vbt.lvds_ssc_freq); | |
8891 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8892 | } | |
8893 | ||
8894 | if (intel_is_dual_link_lvds(dev)) { | |
8895 | if (refclk == 100000) | |
8896 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8897 | else | |
8898 | limit = &intel_limits_ironlake_dual_lvds; | |
8899 | } else { | |
8900 | if (refclk == 100000) | |
8901 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8902 | else | |
8903 | limit = &intel_limits_ironlake_single_lvds; | |
8904 | } | |
8905 | } else { | |
8906 | limit = &intel_limits_ironlake_dac; | |
8907 | } | |
8908 | ||
364ee29d | 8909 | if (!crtc_state->clock_set && |
997c030c ACO |
8910 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8911 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8912 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8913 | return -EINVAL; | |
f47709a9 | 8914 | } |
79e53945 | 8915 | |
b75ca6f6 ACO |
8916 | ironlake_compute_dpll(crtc, crtc_state, |
8917 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 8918 | |
ded220e2 ACO |
8919 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
8920 | if (pll == NULL) { | |
8921 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8922 | pipe_name(crtc->pipe)); | |
8923 | return -EINVAL; | |
3fb37703 | 8924 | } |
79e53945 | 8925 | |
ded220e2 ACO |
8926 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8927 | has_reduced_clock) | |
c7653199 | 8928 | crtc->lowfreq_avail = true; |
e2b78267 | 8929 | |
c8f7a0db | 8930 | return 0; |
79e53945 JB |
8931 | } |
8932 | ||
eb14cb74 VS |
8933 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8934 | struct intel_link_m_n *m_n) | |
8935 | { | |
8936 | struct drm_device *dev = crtc->base.dev; | |
8937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8938 | enum pipe pipe = crtc->pipe; | |
8939 | ||
8940 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8941 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8942 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8943 | & ~TU_SIZE_MASK; | |
8944 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8945 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8946 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8947 | } | |
8948 | ||
8949 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8950 | enum transcoder transcoder, | |
b95af8be VK |
8951 | struct intel_link_m_n *m_n, |
8952 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8953 | { |
8954 | struct drm_device *dev = crtc->base.dev; | |
8955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8956 | enum pipe pipe = crtc->pipe; |
72419203 | 8957 | |
eb14cb74 VS |
8958 | if (INTEL_INFO(dev)->gen >= 5) { |
8959 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8960 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8961 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8962 | & ~TU_SIZE_MASK; | |
8963 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8964 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8965 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8966 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8967 | * gen < 8) and if DRRS is supported (to make sure the | |
8968 | * registers are not unnecessarily read). | |
8969 | */ | |
8970 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8971 | crtc->config->has_drrs) { |
b95af8be VK |
8972 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8973 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8974 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8975 | & ~TU_SIZE_MASK; | |
8976 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8977 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8978 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8979 | } | |
eb14cb74 VS |
8980 | } else { |
8981 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8982 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8983 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8984 | & ~TU_SIZE_MASK; | |
8985 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8986 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8987 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8988 | } | |
8989 | } | |
8990 | ||
8991 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8992 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8993 | { |
681a8504 | 8994 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8995 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8996 | else | |
8997 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8998 | &pipe_config->dp_m_n, |
8999 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9000 | } |
72419203 | 9001 | |
eb14cb74 | 9002 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9003 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9004 | { |
9005 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9006 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9007 | } |
9008 | ||
bd2e244f | 9009 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9010 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9011 | { |
9012 | struct drm_device *dev = crtc->base.dev; | |
9013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9014 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9015 | uint32_t ps_ctrl = 0; | |
9016 | int id = -1; | |
9017 | int i; | |
bd2e244f | 9018 | |
a1b2278e CK |
9019 | /* find scaler attached to this pipe */ |
9020 | for (i = 0; i < crtc->num_scalers; i++) { | |
9021 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9022 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9023 | id = i; | |
9024 | pipe_config->pch_pfit.enabled = true; | |
9025 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9026 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9027 | break; | |
9028 | } | |
9029 | } | |
bd2e244f | 9030 | |
a1b2278e CK |
9031 | scaler_state->scaler_id = id; |
9032 | if (id >= 0) { | |
9033 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9034 | } else { | |
9035 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9036 | } |
9037 | } | |
9038 | ||
5724dbd1 DL |
9039 | static void |
9040 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9041 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9042 | { |
9043 | struct drm_device *dev = crtc->base.dev; | |
9044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9045 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9046 | int pipe = crtc->pipe; |
9047 | int fourcc, pixel_format; | |
6761dd31 | 9048 | unsigned int aligned_height; |
bc8d7dff | 9049 | struct drm_framebuffer *fb; |
1b842c89 | 9050 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9051 | |
d9806c9f | 9052 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9053 | if (!intel_fb) { |
bc8d7dff DL |
9054 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9055 | return; | |
9056 | } | |
9057 | ||
1b842c89 DL |
9058 | fb = &intel_fb->base; |
9059 | ||
bc8d7dff | 9060 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9061 | if (!(val & PLANE_CTL_ENABLE)) |
9062 | goto error; | |
9063 | ||
bc8d7dff DL |
9064 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9065 | fourcc = skl_format_to_fourcc(pixel_format, | |
9066 | val & PLANE_CTL_ORDER_RGBX, | |
9067 | val & PLANE_CTL_ALPHA_MASK); | |
9068 | fb->pixel_format = fourcc; | |
9069 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9070 | ||
40f46283 DL |
9071 | tiling = val & PLANE_CTL_TILED_MASK; |
9072 | switch (tiling) { | |
9073 | case PLANE_CTL_TILED_LINEAR: | |
9074 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9075 | break; | |
9076 | case PLANE_CTL_TILED_X: | |
9077 | plane_config->tiling = I915_TILING_X; | |
9078 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9079 | break; | |
9080 | case PLANE_CTL_TILED_Y: | |
9081 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9082 | break; | |
9083 | case PLANE_CTL_TILED_YF: | |
9084 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9085 | break; | |
9086 | default: | |
9087 | MISSING_CASE(tiling); | |
9088 | goto error; | |
9089 | } | |
9090 | ||
bc8d7dff DL |
9091 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9092 | plane_config->base = base; | |
9093 | ||
9094 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9095 | ||
9096 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9097 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9098 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9099 | ||
9100 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9101 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9102 | fb->pixel_format); |
bc8d7dff DL |
9103 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9104 | ||
9105 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9106 | fb->pixel_format, |
9107 | fb->modifier[0]); | |
bc8d7dff | 9108 | |
f37b5c2b | 9109 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9110 | |
9111 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9112 | pipe_name(pipe), fb->width, fb->height, | |
9113 | fb->bits_per_pixel, base, fb->pitches[0], | |
9114 | plane_config->size); | |
9115 | ||
2d14030b | 9116 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9117 | return; |
9118 | ||
9119 | error: | |
9120 | kfree(fb); | |
9121 | } | |
9122 | ||
2fa2fe9a | 9123 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9124 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9125 | { |
9126 | struct drm_device *dev = crtc->base.dev; | |
9127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9128 | uint32_t tmp; | |
9129 | ||
9130 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9131 | ||
9132 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9133 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9134 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9135 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9136 | |
9137 | /* We currently do not free assignements of panel fitters on | |
9138 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9139 | * differentiates them) so just WARN about this case for now. */ | |
9140 | if (IS_GEN7(dev)) { | |
9141 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9142 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9143 | } | |
2fa2fe9a | 9144 | } |
79e53945 JB |
9145 | } |
9146 | ||
5724dbd1 DL |
9147 | static void |
9148 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9149 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9150 | { |
9151 | struct drm_device *dev = crtc->base.dev; | |
9152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9153 | u32 val, base, offset; | |
aeee5a49 | 9154 | int pipe = crtc->pipe; |
4c6baa59 | 9155 | int fourcc, pixel_format; |
6761dd31 | 9156 | unsigned int aligned_height; |
b113d5ee | 9157 | struct drm_framebuffer *fb; |
1b842c89 | 9158 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9159 | |
42a7b088 DL |
9160 | val = I915_READ(DSPCNTR(pipe)); |
9161 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9162 | return; | |
9163 | ||
d9806c9f | 9164 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9165 | if (!intel_fb) { |
4c6baa59 JB |
9166 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9167 | return; | |
9168 | } | |
9169 | ||
1b842c89 DL |
9170 | fb = &intel_fb->base; |
9171 | ||
18c5247e DV |
9172 | if (INTEL_INFO(dev)->gen >= 4) { |
9173 | if (val & DISPPLANE_TILED) { | |
49af449b | 9174 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9175 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9176 | } | |
9177 | } | |
4c6baa59 JB |
9178 | |
9179 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9180 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9181 | fb->pixel_format = fourcc; |
9182 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9183 | |
aeee5a49 | 9184 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9185 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9186 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9187 | } else { |
49af449b | 9188 | if (plane_config->tiling) |
aeee5a49 | 9189 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9190 | else |
aeee5a49 | 9191 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9192 | } |
9193 | plane_config->base = base; | |
9194 | ||
9195 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9196 | fb->width = ((val >> 16) & 0xfff) + 1; |
9197 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9198 | |
9199 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9200 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9201 | |
b113d5ee | 9202 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9203 | fb->pixel_format, |
9204 | fb->modifier[0]); | |
4c6baa59 | 9205 | |
f37b5c2b | 9206 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9207 | |
2844a921 DL |
9208 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9209 | pipe_name(pipe), fb->width, fb->height, | |
9210 | fb->bits_per_pixel, base, fb->pitches[0], | |
9211 | plane_config->size); | |
b113d5ee | 9212 | |
2d14030b | 9213 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9214 | } |
9215 | ||
0e8ffe1b | 9216 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9217 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9218 | { |
9219 | struct drm_device *dev = crtc->base.dev; | |
9220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9221 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9222 | uint32_t tmp; |
1729050e | 9223 | bool ret; |
0e8ffe1b | 9224 | |
1729050e ID |
9225 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9226 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9227 | return false; |
9228 | ||
e143a21c | 9229 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9230 | pipe_config->shared_dpll = NULL; |
eccb140b | 9231 | |
1729050e | 9232 | ret = false; |
0e8ffe1b DV |
9233 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9234 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9235 | goto out; |
0e8ffe1b | 9236 | |
42571aef VS |
9237 | switch (tmp & PIPECONF_BPC_MASK) { |
9238 | case PIPECONF_6BPC: | |
9239 | pipe_config->pipe_bpp = 18; | |
9240 | break; | |
9241 | case PIPECONF_8BPC: | |
9242 | pipe_config->pipe_bpp = 24; | |
9243 | break; | |
9244 | case PIPECONF_10BPC: | |
9245 | pipe_config->pipe_bpp = 30; | |
9246 | break; | |
9247 | case PIPECONF_12BPC: | |
9248 | pipe_config->pipe_bpp = 36; | |
9249 | break; | |
9250 | default: | |
9251 | break; | |
9252 | } | |
9253 | ||
b5a9fa09 DV |
9254 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9255 | pipe_config->limited_color_range = true; | |
9256 | ||
ab9412ba | 9257 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9258 | struct intel_shared_dpll *pll; |
8106ddbd | 9259 | enum intel_dpll_id pll_id; |
66e985c0 | 9260 | |
88adfff1 DV |
9261 | pipe_config->has_pch_encoder = true; |
9262 | ||
627eb5a3 DV |
9263 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9264 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9265 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9266 | |
9267 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9268 | |
2d1fe073 | 9269 | if (HAS_PCH_IBX(dev_priv)) { |
8106ddbd | 9270 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9271 | } else { |
9272 | tmp = I915_READ(PCH_DPLL_SEL); | |
9273 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9274 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9275 | else |
8106ddbd | 9276 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9277 | } |
66e985c0 | 9278 | |
8106ddbd ACO |
9279 | pipe_config->shared_dpll = |
9280 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9281 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9282 | |
2edd6443 ACO |
9283 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9284 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9285 | |
9286 | tmp = pipe_config->dpll_hw_state.dpll; | |
9287 | pipe_config->pixel_multiplier = | |
9288 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9289 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9290 | |
9291 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9292 | } else { |
9293 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9294 | } |
9295 | ||
1bd1bd80 | 9296 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9297 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9298 | |
2fa2fe9a DV |
9299 | ironlake_get_pfit_config(crtc, pipe_config); |
9300 | ||
1729050e ID |
9301 | ret = true; |
9302 | ||
9303 | out: | |
9304 | intel_display_power_put(dev_priv, power_domain); | |
9305 | ||
9306 | return ret; | |
0e8ffe1b DV |
9307 | } |
9308 | ||
be256dc7 PZ |
9309 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9310 | { | |
9311 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9312 | struct intel_crtc *crtc; |
be256dc7 | 9313 | |
d3fcc808 | 9314 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9315 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9316 | pipe_name(crtc->pipe)); |
9317 | ||
e2c719b7 RC |
9318 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9319 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9320 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9321 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9322 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9323 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9324 | "CPU PWM1 enabled\n"); |
c5107b87 | 9325 | if (IS_HASWELL(dev)) |
e2c719b7 | 9326 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9327 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9328 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9329 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9330 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9331 | "Utility pin enabled\n"); |
e2c719b7 | 9332 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9333 | |
9926ada1 PZ |
9334 | /* |
9335 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9336 | * interrupts remain enabled. We used to check for that, but since it's | |
9337 | * gen-specific and since we only disable LCPLL after we fully disable | |
9338 | * the interrupts, the check below should be enough. | |
9339 | */ | |
e2c719b7 | 9340 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9341 | } |
9342 | ||
9ccd5aeb PZ |
9343 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9344 | { | |
9345 | struct drm_device *dev = dev_priv->dev; | |
9346 | ||
9347 | if (IS_HASWELL(dev)) | |
9348 | return I915_READ(D_COMP_HSW); | |
9349 | else | |
9350 | return I915_READ(D_COMP_BDW); | |
9351 | } | |
9352 | ||
3c4c9b81 PZ |
9353 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9354 | { | |
9355 | struct drm_device *dev = dev_priv->dev; | |
9356 | ||
9357 | if (IS_HASWELL(dev)) { | |
9358 | mutex_lock(&dev_priv->rps.hw_lock); | |
9359 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9360 | val)) | |
f475dadf | 9361 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9362 | mutex_unlock(&dev_priv->rps.hw_lock); |
9363 | } else { | |
9ccd5aeb PZ |
9364 | I915_WRITE(D_COMP_BDW, val); |
9365 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9366 | } |
be256dc7 PZ |
9367 | } |
9368 | ||
9369 | /* | |
9370 | * This function implements pieces of two sequences from BSpec: | |
9371 | * - Sequence for display software to disable LCPLL | |
9372 | * - Sequence for display software to allow package C8+ | |
9373 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9374 | * register. Callers should take care of disabling all the display engine | |
9375 | * functions, doing the mode unset, fixing interrupts, etc. | |
9376 | */ | |
6ff58d53 PZ |
9377 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9378 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9379 | { |
9380 | uint32_t val; | |
9381 | ||
9382 | assert_can_disable_lcpll(dev_priv); | |
9383 | ||
9384 | val = I915_READ(LCPLL_CTL); | |
9385 | ||
9386 | if (switch_to_fclk) { | |
9387 | val |= LCPLL_CD_SOURCE_FCLK; | |
9388 | I915_WRITE(LCPLL_CTL, val); | |
9389 | ||
9390 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9391 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9392 | DRM_ERROR("Switching to FCLK failed\n"); | |
9393 | ||
9394 | val = I915_READ(LCPLL_CTL); | |
9395 | } | |
9396 | ||
9397 | val |= LCPLL_PLL_DISABLE; | |
9398 | I915_WRITE(LCPLL_CTL, val); | |
9399 | POSTING_READ(LCPLL_CTL); | |
9400 | ||
9401 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9402 | DRM_ERROR("LCPLL still locked\n"); | |
9403 | ||
9ccd5aeb | 9404 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9405 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9406 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9407 | ndelay(100); |
9408 | ||
9ccd5aeb PZ |
9409 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9410 | 1)) | |
be256dc7 PZ |
9411 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9412 | ||
9413 | if (allow_power_down) { | |
9414 | val = I915_READ(LCPLL_CTL); | |
9415 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9416 | I915_WRITE(LCPLL_CTL, val); | |
9417 | POSTING_READ(LCPLL_CTL); | |
9418 | } | |
9419 | } | |
9420 | ||
9421 | /* | |
9422 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9423 | * source. | |
9424 | */ | |
6ff58d53 | 9425 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9426 | { |
9427 | uint32_t val; | |
9428 | ||
9429 | val = I915_READ(LCPLL_CTL); | |
9430 | ||
9431 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9432 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9433 | return; | |
9434 | ||
a8a8bd54 PZ |
9435 | /* |
9436 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9437 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9438 | */ |
59bad947 | 9439 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9440 | |
be256dc7 PZ |
9441 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9442 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9443 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9444 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9445 | } |
9446 | ||
9ccd5aeb | 9447 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9448 | val |= D_COMP_COMP_FORCE; |
9449 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9450 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9451 | |
9452 | val = I915_READ(LCPLL_CTL); | |
9453 | val &= ~LCPLL_PLL_DISABLE; | |
9454 | I915_WRITE(LCPLL_CTL, val); | |
9455 | ||
9456 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9457 | DRM_ERROR("LCPLL not locked yet\n"); | |
9458 | ||
9459 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9460 | val = I915_READ(LCPLL_CTL); | |
9461 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9462 | I915_WRITE(LCPLL_CTL, val); | |
9463 | ||
9464 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9465 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9466 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9467 | } | |
215733fa | 9468 | |
59bad947 | 9469 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9470 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9471 | } |
9472 | ||
765dab67 PZ |
9473 | /* |
9474 | * Package states C8 and deeper are really deep PC states that can only be | |
9475 | * reached when all the devices on the system allow it, so even if the graphics | |
9476 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9477 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9478 | * | |
9479 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9480 | * well is disabled and most interrupts are disabled, and these are also | |
9481 | * requirements for runtime PM. When these conditions are met, we manually do | |
9482 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9483 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9484 | * hang the machine. | |
9485 | * | |
9486 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9487 | * the state of some registers, so when we come back from PC8+ we need to | |
9488 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9489 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9490 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9491 | * because of the runtime PM support). | |
9492 | * | |
9493 | * For more, read "Display Sequences for Package C8" on the hardware | |
9494 | * documentation. | |
9495 | */ | |
a14cb6fc | 9496 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9497 | { |
c67a470b PZ |
9498 | struct drm_device *dev = dev_priv->dev; |
9499 | uint32_t val; | |
9500 | ||
c67a470b PZ |
9501 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9502 | ||
c2699524 | 9503 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9504 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9505 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9506 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9507 | } | |
9508 | ||
9509 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9510 | hsw_disable_lcpll(dev_priv, true, true); |
9511 | } | |
9512 | ||
a14cb6fc | 9513 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9514 | { |
9515 | struct drm_device *dev = dev_priv->dev; | |
9516 | uint32_t val; | |
9517 | ||
c67a470b PZ |
9518 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9519 | ||
9520 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9521 | lpt_init_pch_refclk(dev); |
9522 | ||
c2699524 | 9523 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9524 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9525 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9526 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9527 | } | |
c67a470b PZ |
9528 | } |
9529 | ||
27c329ed | 9530 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9531 | { |
a821fc46 | 9532 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9533 | struct intel_atomic_state *old_intel_state = |
9534 | to_intel_atomic_state(old_state); | |
9535 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9536 | |
27c329ed | 9537 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9538 | } |
9539 | ||
b432e5cf | 9540 | /* compute the max rate for new configuration */ |
27c329ed | 9541 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9542 | { |
565602d7 ML |
9543 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9544 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9545 | struct drm_crtc *crtc; | |
9546 | struct drm_crtc_state *cstate; | |
27c329ed | 9547 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9548 | unsigned max_pixel_rate = 0, i; |
9549 | enum pipe pipe; | |
b432e5cf | 9550 | |
565602d7 ML |
9551 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9552 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9553 | |
565602d7 ML |
9554 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9555 | int pixel_rate; | |
27c329ed | 9556 | |
565602d7 ML |
9557 | crtc_state = to_intel_crtc_state(cstate); |
9558 | if (!crtc_state->base.enable) { | |
9559 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9560 | continue; |
565602d7 | 9561 | } |
b432e5cf | 9562 | |
27c329ed | 9563 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9564 | |
9565 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9566 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9567 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9568 | ||
565602d7 | 9569 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9570 | } |
9571 | ||
565602d7 ML |
9572 | for_each_pipe(dev_priv, pipe) |
9573 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9574 | ||
b432e5cf VS |
9575 | return max_pixel_rate; |
9576 | } | |
9577 | ||
9578 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9579 | { | |
9580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9581 | uint32_t val, data; | |
9582 | int ret; | |
9583 | ||
9584 | if (WARN((I915_READ(LCPLL_CTL) & | |
9585 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9586 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9587 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9588 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9589 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9590 | return; | |
9591 | ||
9592 | mutex_lock(&dev_priv->rps.hw_lock); | |
9593 | ret = sandybridge_pcode_write(dev_priv, | |
9594 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9595 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9596 | if (ret) { | |
9597 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9598 | return; | |
9599 | } | |
9600 | ||
9601 | val = I915_READ(LCPLL_CTL); | |
9602 | val |= LCPLL_CD_SOURCE_FCLK; | |
9603 | I915_WRITE(LCPLL_CTL, val); | |
9604 | ||
5ba00178 TU |
9605 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9606 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9607 | DRM_ERROR("Switching to FCLK failed\n"); |
9608 | ||
9609 | val = I915_READ(LCPLL_CTL); | |
9610 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9611 | ||
9612 | switch (cdclk) { | |
9613 | case 450000: | |
9614 | val |= LCPLL_CLK_FREQ_450; | |
9615 | data = 0; | |
9616 | break; | |
9617 | case 540000: | |
9618 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9619 | data = 1; | |
9620 | break; | |
9621 | case 337500: | |
9622 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9623 | data = 2; | |
9624 | break; | |
9625 | case 675000: | |
9626 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9627 | data = 3; | |
9628 | break; | |
9629 | default: | |
9630 | WARN(1, "invalid cdclk frequency\n"); | |
9631 | return; | |
9632 | } | |
9633 | ||
9634 | I915_WRITE(LCPLL_CTL, val); | |
9635 | ||
9636 | val = I915_READ(LCPLL_CTL); | |
9637 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9638 | I915_WRITE(LCPLL_CTL, val); | |
9639 | ||
5ba00178 TU |
9640 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9641 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9642 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9643 | ||
9644 | mutex_lock(&dev_priv->rps.hw_lock); | |
9645 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9646 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9647 | ||
9648 | intel_update_cdclk(dev); | |
9649 | ||
9650 | WARN(cdclk != dev_priv->cdclk_freq, | |
9651 | "cdclk requested %d kHz but got %d kHz\n", | |
9652 | cdclk, dev_priv->cdclk_freq); | |
9653 | } | |
9654 | ||
27c329ed | 9655 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9656 | { |
27c329ed | 9657 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9658 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9659 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9660 | int cdclk; |
9661 | ||
9662 | /* | |
9663 | * FIXME should also account for plane ratio | |
9664 | * once 64bpp pixel formats are supported. | |
9665 | */ | |
27c329ed | 9666 | if (max_pixclk > 540000) |
b432e5cf | 9667 | cdclk = 675000; |
27c329ed | 9668 | else if (max_pixclk > 450000) |
b432e5cf | 9669 | cdclk = 540000; |
27c329ed | 9670 | else if (max_pixclk > 337500) |
b432e5cf VS |
9671 | cdclk = 450000; |
9672 | else | |
9673 | cdclk = 337500; | |
9674 | ||
b432e5cf | 9675 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9676 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9677 | cdclk, dev_priv->max_cdclk_freq); | |
9678 | return -EINVAL; | |
b432e5cf VS |
9679 | } |
9680 | ||
1a617b77 ML |
9681 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9682 | if (!intel_state->active_crtcs) | |
9683 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9684 | |
9685 | return 0; | |
9686 | } | |
9687 | ||
27c329ed | 9688 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9689 | { |
27c329ed | 9690 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9691 | struct intel_atomic_state *old_intel_state = |
9692 | to_intel_atomic_state(old_state); | |
9693 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9694 | |
27c329ed | 9695 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9696 | } |
9697 | ||
190f68c5 ACO |
9698 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9699 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9700 | { |
af3997b5 MK |
9701 | struct intel_encoder *intel_encoder = |
9702 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9703 | ||
9704 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9705 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9706 | return -EINVAL; | |
9707 | } | |
716c2e55 | 9708 | |
c7653199 | 9709 | crtc->lowfreq_avail = false; |
644cef34 | 9710 | |
c8f7a0db | 9711 | return 0; |
79e53945 JB |
9712 | } |
9713 | ||
3760b59c S |
9714 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9715 | enum port port, | |
9716 | struct intel_crtc_state *pipe_config) | |
9717 | { | |
8106ddbd ACO |
9718 | enum intel_dpll_id id; |
9719 | ||
3760b59c S |
9720 | switch (port) { |
9721 | case PORT_A: | |
9722 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 9723 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9724 | break; |
9725 | case PORT_B: | |
9726 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 9727 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9728 | break; |
9729 | case PORT_C: | |
9730 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 9731 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9732 | break; |
9733 | default: | |
9734 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9735 | return; |
3760b59c | 9736 | } |
8106ddbd ACO |
9737 | |
9738 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9739 | } |
9740 | ||
96b7dfb7 S |
9741 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9742 | enum port port, | |
5cec258b | 9743 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9744 | { |
8106ddbd | 9745 | enum intel_dpll_id id; |
a3c988ea | 9746 | u32 temp; |
96b7dfb7 S |
9747 | |
9748 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9749 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9750 | ||
9751 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 9752 | case SKL_DPLL0: |
a3c988ea ACO |
9753 | id = DPLL_ID_SKL_DPLL0; |
9754 | break; | |
96b7dfb7 | 9755 | case SKL_DPLL1: |
8106ddbd | 9756 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
9757 | break; |
9758 | case SKL_DPLL2: | |
8106ddbd | 9759 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
9760 | break; |
9761 | case SKL_DPLL3: | |
8106ddbd | 9762 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 9763 | break; |
8106ddbd ACO |
9764 | default: |
9765 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9766 | return; | |
96b7dfb7 | 9767 | } |
8106ddbd ACO |
9768 | |
9769 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9770 | } |
9771 | ||
7d2c8175 DL |
9772 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9773 | enum port port, | |
5cec258b | 9774 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9775 | { |
8106ddbd ACO |
9776 | enum intel_dpll_id id; |
9777 | ||
7d2c8175 DL |
9778 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
9779 | ||
9780 | switch (pipe_config->ddi_pll_sel) { | |
9781 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 9782 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9783 | break; |
9784 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9785 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9786 | break; |
00490c22 | 9787 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9788 | id = DPLL_ID_SPLL; |
79bd23da | 9789 | break; |
9d16da65 ACO |
9790 | case PORT_CLK_SEL_LCPLL_810: |
9791 | id = DPLL_ID_LCPLL_810; | |
9792 | break; | |
9793 | case PORT_CLK_SEL_LCPLL_1350: | |
9794 | id = DPLL_ID_LCPLL_1350; | |
9795 | break; | |
9796 | case PORT_CLK_SEL_LCPLL_2700: | |
9797 | id = DPLL_ID_LCPLL_2700; | |
9798 | break; | |
8106ddbd ACO |
9799 | default: |
9800 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9801 | /* fall through */ | |
9802 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9803 | return; |
7d2c8175 | 9804 | } |
8106ddbd ACO |
9805 | |
9806 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9807 | } |
9808 | ||
cf30429e JN |
9809 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9810 | struct intel_crtc_state *pipe_config, | |
9811 | unsigned long *power_domain_mask) | |
9812 | { | |
9813 | struct drm_device *dev = crtc->base.dev; | |
9814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9815 | enum intel_display_power_domain power_domain; | |
9816 | u32 tmp; | |
9817 | ||
9818 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; | |
9819 | ||
9820 | /* | |
9821 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9822 | * consistency and less surprising code; it's in always on power). | |
9823 | */ | |
9824 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9825 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9826 | enum pipe trans_edp_pipe; | |
9827 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9828 | default: | |
9829 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9830 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9831 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9832 | trans_edp_pipe = PIPE_A; | |
9833 | break; | |
9834 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9835 | trans_edp_pipe = PIPE_B; | |
9836 | break; | |
9837 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9838 | trans_edp_pipe = PIPE_C; | |
9839 | break; | |
9840 | } | |
9841 | ||
9842 | if (trans_edp_pipe == crtc->pipe) | |
9843 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9844 | } | |
9845 | ||
9846 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9847 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9848 | return false; | |
9849 | *power_domain_mask |= BIT(power_domain); | |
9850 | ||
9851 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9852 | ||
9853 | return tmp & PIPECONF_ENABLE; | |
9854 | } | |
9855 | ||
4d1de975 JN |
9856 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9857 | struct intel_crtc_state *pipe_config, | |
9858 | unsigned long *power_domain_mask) | |
9859 | { | |
9860 | struct drm_device *dev = crtc->base.dev; | |
9861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9862 | enum intel_display_power_domain power_domain; | |
9863 | enum port port; | |
9864 | enum transcoder cpu_transcoder; | |
9865 | u32 tmp; | |
9866 | ||
9867 | pipe_config->has_dsi_encoder = false; | |
9868 | ||
9869 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { | |
9870 | if (port == PORT_A) | |
9871 | cpu_transcoder = TRANSCODER_DSI_A; | |
9872 | else | |
9873 | cpu_transcoder = TRANSCODER_DSI_C; | |
9874 | ||
9875 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9876 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9877 | continue; | |
9878 | *power_domain_mask |= BIT(power_domain); | |
9879 | ||
db18b6a6 ID |
9880 | /* |
9881 | * The PLL needs to be enabled with a valid divider | |
9882 | * configuration, otherwise accessing DSI registers will hang | |
9883 | * the machine. See BSpec North Display Engine | |
9884 | * registers/MIPI[BXT]. We can break out here early, since we | |
9885 | * need the same DSI PLL to be enabled for both DSI ports. | |
9886 | */ | |
9887 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9888 | break; | |
9889 | ||
4d1de975 JN |
9890 | /* XXX: this works for video mode only */ |
9891 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9892 | if (!(tmp & DPI_ENABLE)) | |
9893 | continue; | |
9894 | ||
9895 | tmp = I915_READ(MIPI_CTRL(port)); | |
9896 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9897 | continue; | |
9898 | ||
9899 | pipe_config->cpu_transcoder = cpu_transcoder; | |
9900 | pipe_config->has_dsi_encoder = true; | |
9901 | break; | |
9902 | } | |
9903 | ||
9904 | return pipe_config->has_dsi_encoder; | |
9905 | } | |
9906 | ||
26804afd | 9907 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9908 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9909 | { |
9910 | struct drm_device *dev = crtc->base.dev; | |
9911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9912 | struct intel_shared_dpll *pll; |
26804afd DV |
9913 | enum port port; |
9914 | uint32_t tmp; | |
9915 | ||
9916 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9917 | ||
9918 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9919 | ||
ef11bdb3 | 9920 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9921 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9922 | else if (IS_BROXTON(dev)) |
9923 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9924 | else |
9925 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9926 | |
8106ddbd ACO |
9927 | pll = pipe_config->shared_dpll; |
9928 | if (pll) { | |
2edd6443 ACO |
9929 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9930 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9931 | } |
9932 | ||
26804afd DV |
9933 | /* |
9934 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9935 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9936 | * the PCH transcoder is on. | |
9937 | */ | |
ca370455 DL |
9938 | if (INTEL_INFO(dev)->gen < 9 && |
9939 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9940 | pipe_config->has_pch_encoder = true; |
9941 | ||
9942 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9943 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9944 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9945 | ||
9946 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9947 | } | |
9948 | } | |
9949 | ||
0e8ffe1b | 9950 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9951 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9952 | { |
9953 | struct drm_device *dev = crtc->base.dev; | |
9954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
9955 | enum intel_display_power_domain power_domain; |
9956 | unsigned long power_domain_mask; | |
cf30429e | 9957 | bool active; |
0e8ffe1b | 9958 | |
1729050e ID |
9959 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9960 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9961 | return false; |
1729050e ID |
9962 | power_domain_mask = BIT(power_domain); |
9963 | ||
8106ddbd | 9964 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9965 | |
cf30429e | 9966 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9967 | |
4d1de975 JN |
9968 | if (IS_BROXTON(dev_priv)) { |
9969 | bxt_get_dsi_transcoder_state(crtc, pipe_config, | |
9970 | &power_domain_mask); | |
9971 | WARN_ON(active && pipe_config->has_dsi_encoder); | |
9972 | if (pipe_config->has_dsi_encoder) | |
9973 | active = true; | |
9974 | } | |
9975 | ||
cf30429e | 9976 | if (!active) |
1729050e | 9977 | goto out; |
0e8ffe1b | 9978 | |
4d1de975 JN |
9979 | if (!pipe_config->has_dsi_encoder) { |
9980 | haswell_get_ddi_port_state(crtc, pipe_config); | |
9981 | intel_get_pipe_timings(crtc, pipe_config); | |
9982 | } | |
627eb5a3 | 9983 | |
bc58be60 | 9984 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9985 | |
05dc698c LL |
9986 | pipe_config->gamma_mode = |
9987 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9988 | ||
a1b2278e CK |
9989 | if (INTEL_INFO(dev)->gen >= 9) { |
9990 | skl_init_scalers(dev, crtc, pipe_config); | |
9991 | } | |
9992 | ||
af99ceda CK |
9993 | if (INTEL_INFO(dev)->gen >= 9) { |
9994 | pipe_config->scaler_state.scaler_id = -1; | |
9995 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9996 | } | |
9997 | ||
1729050e ID |
9998 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9999 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10000 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10001 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10002 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10003 | else |
1c132b44 | 10004 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10005 | } |
88adfff1 | 10006 | |
e59150dc JB |
10007 | if (IS_HASWELL(dev)) |
10008 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10009 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10010 | |
4d1de975 JN |
10011 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10012 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10013 | pipe_config->pixel_multiplier = |
10014 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10015 | } else { | |
10016 | pipe_config->pixel_multiplier = 1; | |
10017 | } | |
6c49f241 | 10018 | |
1729050e ID |
10019 | out: |
10020 | for_each_power_domain(power_domain, power_domain_mask) | |
10021 | intel_display_power_put(dev_priv, power_domain); | |
10022 | ||
cf30429e | 10023 | return active; |
0e8ffe1b DV |
10024 | } |
10025 | ||
55a08b3f ML |
10026 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10027 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10028 | { |
10029 | struct drm_device *dev = crtc->dev; | |
10030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10032 | uint32_t cntl = 0, size = 0; |
560b85bb | 10033 | |
55a08b3f ML |
10034 | if (plane_state && plane_state->visible) { |
10035 | unsigned int width = plane_state->base.crtc_w; | |
10036 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10037 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10038 | ||
10039 | switch (stride) { | |
10040 | default: | |
10041 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10042 | width, stride); | |
10043 | stride = 256; | |
10044 | /* fallthrough */ | |
10045 | case 256: | |
10046 | case 512: | |
10047 | case 1024: | |
10048 | case 2048: | |
10049 | break; | |
4b0e333e CW |
10050 | } |
10051 | ||
dc41c154 VS |
10052 | cntl |= CURSOR_ENABLE | |
10053 | CURSOR_GAMMA_ENABLE | | |
10054 | CURSOR_FORMAT_ARGB | | |
10055 | CURSOR_STRIDE(stride); | |
10056 | ||
10057 | size = (height << 12) | width; | |
4b0e333e | 10058 | } |
560b85bb | 10059 | |
dc41c154 VS |
10060 | if (intel_crtc->cursor_cntl != 0 && |
10061 | (intel_crtc->cursor_base != base || | |
10062 | intel_crtc->cursor_size != size || | |
10063 | intel_crtc->cursor_cntl != cntl)) { | |
10064 | /* On these chipsets we can only modify the base/size/stride | |
10065 | * whilst the cursor is disabled. | |
10066 | */ | |
0b87c24e VS |
10067 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10068 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10069 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10070 | } |
560b85bb | 10071 | |
99d1f387 | 10072 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10073 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10074 | intel_crtc->cursor_base = base; |
10075 | } | |
4726e0b0 | 10076 | |
dc41c154 VS |
10077 | if (intel_crtc->cursor_size != size) { |
10078 | I915_WRITE(CURSIZE, size); | |
10079 | intel_crtc->cursor_size = size; | |
4b0e333e | 10080 | } |
560b85bb | 10081 | |
4b0e333e | 10082 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10083 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10084 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10085 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10086 | } |
560b85bb CW |
10087 | } |
10088 | ||
55a08b3f ML |
10089 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10090 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10091 | { |
10092 | struct drm_device *dev = crtc->dev; | |
10093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10094 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10095 | int pipe = intel_crtc->pipe; | |
663f3122 | 10096 | uint32_t cntl = 0; |
4b0e333e | 10097 | |
55a08b3f | 10098 | if (plane_state && plane_state->visible) { |
4b0e333e | 10099 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10100 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10101 | case 64: |
10102 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10103 | break; | |
10104 | case 128: | |
10105 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10106 | break; | |
10107 | case 256: | |
10108 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10109 | break; | |
10110 | default: | |
55a08b3f | 10111 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10112 | return; |
65a21cd6 | 10113 | } |
4b0e333e | 10114 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10115 | |
fc6f93bc | 10116 | if (HAS_DDI(dev)) |
47bf17a7 | 10117 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10118 | |
55a08b3f ML |
10119 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10120 | cntl |= CURSOR_ROTATE_180; | |
10121 | } | |
4398ad45 | 10122 | |
4b0e333e CW |
10123 | if (intel_crtc->cursor_cntl != cntl) { |
10124 | I915_WRITE(CURCNTR(pipe), cntl); | |
10125 | POSTING_READ(CURCNTR(pipe)); | |
10126 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10127 | } |
4b0e333e | 10128 | |
65a21cd6 | 10129 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10130 | I915_WRITE(CURBASE(pipe), base); |
10131 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10132 | |
10133 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10134 | } |
10135 | ||
cda4b7d3 | 10136 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10137 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10138 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10139 | { |
10140 | struct drm_device *dev = crtc->dev; | |
10141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10143 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10144 | u32 base = intel_crtc->cursor_addr; |
10145 | u32 pos = 0; | |
cda4b7d3 | 10146 | |
55a08b3f ML |
10147 | if (plane_state) { |
10148 | int x = plane_state->base.crtc_x; | |
10149 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10150 | |
55a08b3f ML |
10151 | if (x < 0) { |
10152 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10153 | x = -x; | |
10154 | } | |
10155 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10156 | |
55a08b3f ML |
10157 | if (y < 0) { |
10158 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10159 | y = -y; | |
10160 | } | |
10161 | pos |= y << CURSOR_Y_SHIFT; | |
10162 | ||
10163 | /* ILK+ do this automagically */ | |
10164 | if (HAS_GMCH_DISPLAY(dev) && | |
10165 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10166 | base += (plane_state->base.crtc_h * | |
10167 | plane_state->base.crtc_w - 1) * 4; | |
10168 | } | |
cda4b7d3 | 10169 | } |
cda4b7d3 | 10170 | |
5efb3e28 VS |
10171 | I915_WRITE(CURPOS(pipe), pos); |
10172 | ||
8ac54669 | 10173 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10174 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10175 | else |
55a08b3f | 10176 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10177 | } |
10178 | ||
dc41c154 VS |
10179 | static bool cursor_size_ok(struct drm_device *dev, |
10180 | uint32_t width, uint32_t height) | |
10181 | { | |
10182 | if (width == 0 || height == 0) | |
10183 | return false; | |
10184 | ||
10185 | /* | |
10186 | * 845g/865g are special in that they are only limited by | |
10187 | * the width of their cursors, the height is arbitrary up to | |
10188 | * the precision of the register. Everything else requires | |
10189 | * square cursors, limited to a few power-of-two sizes. | |
10190 | */ | |
10191 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10192 | if ((width & 63) != 0) | |
10193 | return false; | |
10194 | ||
10195 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10196 | return false; | |
10197 | ||
10198 | if (height > 1023) | |
10199 | return false; | |
10200 | } else { | |
10201 | switch (width | height) { | |
10202 | case 256: | |
10203 | case 128: | |
10204 | if (IS_GEN2(dev)) | |
10205 | return false; | |
10206 | case 64: | |
10207 | break; | |
10208 | default: | |
10209 | return false; | |
10210 | } | |
10211 | } | |
10212 | ||
10213 | return true; | |
10214 | } | |
10215 | ||
79e53945 JB |
10216 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10217 | static struct drm_display_mode load_detect_mode = { | |
10218 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10219 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10220 | }; | |
10221 | ||
a8bb6818 DV |
10222 | struct drm_framebuffer * |
10223 | __intel_framebuffer_create(struct drm_device *dev, | |
10224 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10225 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10226 | { |
10227 | struct intel_framebuffer *intel_fb; | |
10228 | int ret; | |
10229 | ||
10230 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10231 | if (!intel_fb) |
d2dff872 | 10232 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10233 | |
10234 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10235 | if (ret) |
10236 | goto err; | |
d2dff872 CW |
10237 | |
10238 | return &intel_fb->base; | |
dcb1394e | 10239 | |
dd4916c5 | 10240 | err: |
dd4916c5 | 10241 | kfree(intel_fb); |
dd4916c5 | 10242 | return ERR_PTR(ret); |
d2dff872 CW |
10243 | } |
10244 | ||
b5ea642a | 10245 | static struct drm_framebuffer * |
a8bb6818 DV |
10246 | intel_framebuffer_create(struct drm_device *dev, |
10247 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10248 | struct drm_i915_gem_object *obj) | |
10249 | { | |
10250 | struct drm_framebuffer *fb; | |
10251 | int ret; | |
10252 | ||
10253 | ret = i915_mutex_lock_interruptible(dev); | |
10254 | if (ret) | |
10255 | return ERR_PTR(ret); | |
10256 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10257 | mutex_unlock(&dev->struct_mutex); | |
10258 | ||
10259 | return fb; | |
10260 | } | |
10261 | ||
d2dff872 CW |
10262 | static u32 |
10263 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10264 | { | |
10265 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10266 | return ALIGN(pitch, 64); | |
10267 | } | |
10268 | ||
10269 | static u32 | |
10270 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10271 | { | |
10272 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10273 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10274 | } |
10275 | ||
10276 | static struct drm_framebuffer * | |
10277 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10278 | struct drm_display_mode *mode, | |
10279 | int depth, int bpp) | |
10280 | { | |
dcb1394e | 10281 | struct drm_framebuffer *fb; |
d2dff872 | 10282 | struct drm_i915_gem_object *obj; |
0fed39bd | 10283 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10284 | |
10285 | obj = i915_gem_alloc_object(dev, | |
10286 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10287 | if (obj == NULL) | |
10288 | return ERR_PTR(-ENOMEM); | |
10289 | ||
10290 | mode_cmd.width = mode->hdisplay; | |
10291 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10292 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10293 | bpp); | |
5ca0c34a | 10294 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10295 | |
dcb1394e LW |
10296 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10297 | if (IS_ERR(fb)) | |
10298 | drm_gem_object_unreference_unlocked(&obj->base); | |
10299 | ||
10300 | return fb; | |
d2dff872 CW |
10301 | } |
10302 | ||
10303 | static struct drm_framebuffer * | |
10304 | mode_fits_in_fbdev(struct drm_device *dev, | |
10305 | struct drm_display_mode *mode) | |
10306 | { | |
0695726e | 10307 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10308 | struct drm_i915_private *dev_priv = dev->dev_private; |
10309 | struct drm_i915_gem_object *obj; | |
10310 | struct drm_framebuffer *fb; | |
10311 | ||
4c0e5528 | 10312 | if (!dev_priv->fbdev) |
d2dff872 CW |
10313 | return NULL; |
10314 | ||
4c0e5528 | 10315 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10316 | return NULL; |
10317 | ||
4c0e5528 DV |
10318 | obj = dev_priv->fbdev->fb->obj; |
10319 | BUG_ON(!obj); | |
10320 | ||
8bcd4553 | 10321 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10322 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10323 | fb->bits_per_pixel)) | |
d2dff872 CW |
10324 | return NULL; |
10325 | ||
01f2c773 | 10326 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10327 | return NULL; |
10328 | ||
edde3617 | 10329 | drm_framebuffer_reference(fb); |
d2dff872 | 10330 | return fb; |
4520f53a DV |
10331 | #else |
10332 | return NULL; | |
10333 | #endif | |
d2dff872 CW |
10334 | } |
10335 | ||
d3a40d1b ACO |
10336 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10337 | struct drm_crtc *crtc, | |
10338 | struct drm_display_mode *mode, | |
10339 | struct drm_framebuffer *fb, | |
10340 | int x, int y) | |
10341 | { | |
10342 | struct drm_plane_state *plane_state; | |
10343 | int hdisplay, vdisplay; | |
10344 | int ret; | |
10345 | ||
10346 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10347 | if (IS_ERR(plane_state)) | |
10348 | return PTR_ERR(plane_state); | |
10349 | ||
10350 | if (mode) | |
10351 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10352 | else | |
10353 | hdisplay = vdisplay = 0; | |
10354 | ||
10355 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10356 | if (ret) | |
10357 | return ret; | |
10358 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10359 | plane_state->crtc_x = 0; | |
10360 | plane_state->crtc_y = 0; | |
10361 | plane_state->crtc_w = hdisplay; | |
10362 | plane_state->crtc_h = vdisplay; | |
10363 | plane_state->src_x = x << 16; | |
10364 | plane_state->src_y = y << 16; | |
10365 | plane_state->src_w = hdisplay << 16; | |
10366 | plane_state->src_h = vdisplay << 16; | |
10367 | ||
10368 | return 0; | |
10369 | } | |
10370 | ||
d2434ab7 | 10371 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10372 | struct drm_display_mode *mode, |
51fd371b RC |
10373 | struct intel_load_detect_pipe *old, |
10374 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10375 | { |
10376 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10377 | struct intel_encoder *intel_encoder = |
10378 | intel_attached_encoder(connector); | |
79e53945 | 10379 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10380 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10381 | struct drm_crtc *crtc = NULL; |
10382 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10383 | struct drm_framebuffer *fb; |
51fd371b | 10384 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10385 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10386 | struct drm_connector_state *connector_state; |
4be07317 | 10387 | struct intel_crtc_state *crtc_state; |
51fd371b | 10388 | int ret, i = -1; |
79e53945 | 10389 | |
d2dff872 | 10390 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10391 | connector->base.id, connector->name, |
8e329a03 | 10392 | encoder->base.id, encoder->name); |
d2dff872 | 10393 | |
edde3617 ML |
10394 | old->restore_state = NULL; |
10395 | ||
51fd371b RC |
10396 | retry: |
10397 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10398 | if (ret) | |
ad3c558f | 10399 | goto fail; |
6e9f798d | 10400 | |
79e53945 JB |
10401 | /* |
10402 | * Algorithm gets a little messy: | |
7a5e4805 | 10403 | * |
79e53945 JB |
10404 | * - if the connector already has an assigned crtc, use it (but make |
10405 | * sure it's on first) | |
7a5e4805 | 10406 | * |
79e53945 JB |
10407 | * - try to find the first unused crtc that can drive this connector, |
10408 | * and use that if we find one | |
79e53945 JB |
10409 | */ |
10410 | ||
10411 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10412 | if (connector->state->crtc) { |
10413 | crtc = connector->state->crtc; | |
8261b191 | 10414 | |
51fd371b | 10415 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10416 | if (ret) |
ad3c558f | 10417 | goto fail; |
8261b191 CW |
10418 | |
10419 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10420 | goto found; |
79e53945 JB |
10421 | } |
10422 | ||
10423 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10424 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10425 | i++; |
10426 | if (!(encoder->possible_crtcs & (1 << i))) | |
10427 | continue; | |
edde3617 ML |
10428 | |
10429 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10430 | if (ret) | |
10431 | goto fail; | |
10432 | ||
10433 | if (possible_crtc->state->enable) { | |
10434 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10435 | continue; |
edde3617 | 10436 | } |
a459249c VS |
10437 | |
10438 | crtc = possible_crtc; | |
10439 | break; | |
79e53945 JB |
10440 | } |
10441 | ||
10442 | /* | |
10443 | * If we didn't find an unused CRTC, don't use any. | |
10444 | */ | |
10445 | if (!crtc) { | |
7173188d | 10446 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10447 | goto fail; |
79e53945 JB |
10448 | } |
10449 | ||
edde3617 ML |
10450 | found: |
10451 | intel_crtc = to_intel_crtc(crtc); | |
10452 | ||
4d02e2de DV |
10453 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10454 | if (ret) | |
ad3c558f | 10455 | goto fail; |
79e53945 | 10456 | |
83a57153 | 10457 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10458 | restore_state = drm_atomic_state_alloc(dev); |
10459 | if (!state || !restore_state) { | |
10460 | ret = -ENOMEM; | |
10461 | goto fail; | |
10462 | } | |
83a57153 ACO |
10463 | |
10464 | state->acquire_ctx = ctx; | |
edde3617 | 10465 | restore_state->acquire_ctx = ctx; |
83a57153 | 10466 | |
944b0c76 ACO |
10467 | connector_state = drm_atomic_get_connector_state(state, connector); |
10468 | if (IS_ERR(connector_state)) { | |
10469 | ret = PTR_ERR(connector_state); | |
10470 | goto fail; | |
10471 | } | |
10472 | ||
edde3617 ML |
10473 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10474 | if (ret) | |
10475 | goto fail; | |
944b0c76 | 10476 | |
4be07317 ACO |
10477 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10478 | if (IS_ERR(crtc_state)) { | |
10479 | ret = PTR_ERR(crtc_state); | |
10480 | goto fail; | |
10481 | } | |
10482 | ||
49d6fa21 | 10483 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10484 | |
6492711d CW |
10485 | if (!mode) |
10486 | mode = &load_detect_mode; | |
79e53945 | 10487 | |
d2dff872 CW |
10488 | /* We need a framebuffer large enough to accommodate all accesses |
10489 | * that the plane may generate whilst we perform load detection. | |
10490 | * We can not rely on the fbcon either being present (we get called | |
10491 | * during its initialisation to detect all boot displays, or it may | |
10492 | * not even exist) or that it is large enough to satisfy the | |
10493 | * requested mode. | |
10494 | */ | |
94352cf9 DV |
10495 | fb = mode_fits_in_fbdev(dev, mode); |
10496 | if (fb == NULL) { | |
d2dff872 | 10497 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10498 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10499 | } else |
10500 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10501 | if (IS_ERR(fb)) { |
d2dff872 | 10502 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10503 | goto fail; |
79e53945 | 10504 | } |
79e53945 | 10505 | |
d3a40d1b ACO |
10506 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10507 | if (ret) | |
10508 | goto fail; | |
10509 | ||
edde3617 ML |
10510 | drm_framebuffer_unreference(fb); |
10511 | ||
10512 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10513 | if (ret) | |
10514 | goto fail; | |
10515 | ||
10516 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10517 | if (!ret) | |
10518 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10519 | if (!ret) | |
10520 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10521 | if (ret) { | |
10522 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10523 | goto fail; | |
10524 | } | |
8c7b5ccb | 10525 | |
3ba86073 ML |
10526 | ret = drm_atomic_commit(state); |
10527 | if (ret) { | |
6492711d | 10528 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10529 | goto fail; |
79e53945 | 10530 | } |
edde3617 ML |
10531 | |
10532 | old->restore_state = restore_state; | |
7173188d | 10533 | |
79e53945 | 10534 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10535 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10536 | return true; |
412b61d8 | 10537 | |
ad3c558f | 10538 | fail: |
e5d958ef | 10539 | drm_atomic_state_free(state); |
edde3617 ML |
10540 | drm_atomic_state_free(restore_state); |
10541 | restore_state = state = NULL; | |
83a57153 | 10542 | |
51fd371b RC |
10543 | if (ret == -EDEADLK) { |
10544 | drm_modeset_backoff(ctx); | |
10545 | goto retry; | |
10546 | } | |
10547 | ||
412b61d8 | 10548 | return false; |
79e53945 JB |
10549 | } |
10550 | ||
d2434ab7 | 10551 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10552 | struct intel_load_detect_pipe *old, |
10553 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10554 | { |
d2434ab7 DV |
10555 | struct intel_encoder *intel_encoder = |
10556 | intel_attached_encoder(connector); | |
4ef69c7a | 10557 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10558 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10559 | int ret; |
79e53945 | 10560 | |
d2dff872 | 10561 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10562 | connector->base.id, connector->name, |
8e329a03 | 10563 | encoder->base.id, encoder->name); |
d2dff872 | 10564 | |
edde3617 | 10565 | if (!state) |
0622a53c | 10566 | return; |
79e53945 | 10567 | |
edde3617 ML |
10568 | ret = drm_atomic_commit(state); |
10569 | if (ret) { | |
10570 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10571 | drm_atomic_state_free(state); | |
10572 | } | |
79e53945 JB |
10573 | } |
10574 | ||
da4a1efa | 10575 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10576 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10577 | { |
10578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10579 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10580 | ||
10581 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10582 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10583 | else if (HAS_PCH_SPLIT(dev)) |
10584 | return 120000; | |
10585 | else if (!IS_GEN2(dev)) | |
10586 | return 96000; | |
10587 | else | |
10588 | return 48000; | |
10589 | } | |
10590 | ||
79e53945 | 10591 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10592 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10593 | struct intel_crtc_state *pipe_config) |
79e53945 | 10594 | { |
f1f644dc | 10595 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10596 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10597 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10598 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10599 | u32 fp; |
10600 | intel_clock_t clock; | |
dccbea3b | 10601 | int port_clock; |
da4a1efa | 10602 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10603 | |
10604 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10605 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10606 | else |
293623f7 | 10607 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10608 | |
10609 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10610 | if (IS_PINEVIEW(dev)) { |
10611 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10612 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10613 | } else { |
10614 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10615 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10616 | } | |
10617 | ||
a6c45cf0 | 10618 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10619 | if (IS_PINEVIEW(dev)) |
10620 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10621 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10622 | else |
10623 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10624 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10625 | ||
10626 | switch (dpll & DPLL_MODE_MASK) { | |
10627 | case DPLLB_MODE_DAC_SERIAL: | |
10628 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10629 | 5 : 10; | |
10630 | break; | |
10631 | case DPLLB_MODE_LVDS: | |
10632 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10633 | 7 : 14; | |
10634 | break; | |
10635 | default: | |
28c97730 | 10636 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10637 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10638 | return; |
79e53945 JB |
10639 | } |
10640 | ||
ac58c3f0 | 10641 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10642 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10643 | else |
dccbea3b | 10644 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10645 | } else { |
0fb58223 | 10646 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10647 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10648 | |
10649 | if (is_lvds) { | |
10650 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10651 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10652 | |
10653 | if (lvds & LVDS_CLKB_POWER_UP) | |
10654 | clock.p2 = 7; | |
10655 | else | |
10656 | clock.p2 = 14; | |
79e53945 JB |
10657 | } else { |
10658 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10659 | clock.p1 = 2; | |
10660 | else { | |
10661 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10662 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10663 | } | |
10664 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10665 | clock.p2 = 4; | |
10666 | else | |
10667 | clock.p2 = 2; | |
79e53945 | 10668 | } |
da4a1efa | 10669 | |
dccbea3b | 10670 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10671 | } |
10672 | ||
18442d08 VS |
10673 | /* |
10674 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10675 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10676 | * encoder's get_config() function. |
10677 | */ | |
dccbea3b | 10678 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10679 | } |
10680 | ||
6878da05 VS |
10681 | int intel_dotclock_calculate(int link_freq, |
10682 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10683 | { |
f1f644dc JB |
10684 | /* |
10685 | * The calculation for the data clock is: | |
1041a02f | 10686 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10687 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10688 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10689 | * |
10690 | * and the link clock is simpler: | |
1041a02f | 10691 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10692 | */ |
10693 | ||
6878da05 VS |
10694 | if (!m_n->link_n) |
10695 | return 0; | |
f1f644dc | 10696 | |
6878da05 VS |
10697 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10698 | } | |
f1f644dc | 10699 | |
18442d08 | 10700 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10701 | struct intel_crtc_state *pipe_config) |
6878da05 | 10702 | { |
e3b247da | 10703 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10704 | |
18442d08 VS |
10705 | /* read out port_clock from the DPLL */ |
10706 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10707 | |
f1f644dc | 10708 | /* |
e3b247da VS |
10709 | * In case there is an active pipe without active ports, |
10710 | * we may need some idea for the dotclock anyway. | |
10711 | * Calculate one based on the FDI configuration. | |
79e53945 | 10712 | */ |
2d112de7 | 10713 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10714 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10715 | &pipe_config->fdi_m_n); |
79e53945 JB |
10716 | } |
10717 | ||
10718 | /** Returns the currently programmed mode of the given pipe. */ | |
10719 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10720 | struct drm_crtc *crtc) | |
10721 | { | |
548f245b | 10722 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10723 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10724 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10725 | struct drm_display_mode *mode; |
3f36b937 | 10726 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10727 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10728 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10729 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10730 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10731 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10732 | |
10733 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10734 | if (!mode) | |
10735 | return NULL; | |
10736 | ||
3f36b937 TU |
10737 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10738 | if (!pipe_config) { | |
10739 | kfree(mode); | |
10740 | return NULL; | |
10741 | } | |
10742 | ||
f1f644dc JB |
10743 | /* |
10744 | * Construct a pipe_config sufficient for getting the clock info | |
10745 | * back out of crtc_clock_get. | |
10746 | * | |
10747 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10748 | * to use a real value here instead. | |
10749 | */ | |
3f36b937 TU |
10750 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10751 | pipe_config->pixel_multiplier = 1; | |
10752 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10753 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10754 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10755 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10756 | ||
10757 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10758 | mode->hdisplay = (htot & 0xffff) + 1; |
10759 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10760 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10761 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10762 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10763 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10764 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10765 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10766 | ||
10767 | drm_mode_set_name(mode); | |
79e53945 | 10768 | |
3f36b937 TU |
10769 | kfree(pipe_config); |
10770 | ||
79e53945 JB |
10771 | return mode; |
10772 | } | |
10773 | ||
f047e395 CW |
10774 | void intel_mark_busy(struct drm_device *dev) |
10775 | { | |
c67a470b PZ |
10776 | struct drm_i915_private *dev_priv = dev->dev_private; |
10777 | ||
f62a0076 CW |
10778 | if (dev_priv->mm.busy) |
10779 | return; | |
10780 | ||
43694d69 | 10781 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10782 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10783 | if (INTEL_INFO(dev)->gen >= 6) |
10784 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10785 | dev_priv->mm.busy = true; |
f047e395 CW |
10786 | } |
10787 | ||
10788 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10789 | { |
c67a470b | 10790 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10791 | |
f62a0076 CW |
10792 | if (!dev_priv->mm.busy) |
10793 | return; | |
10794 | ||
10795 | dev_priv->mm.busy = false; | |
10796 | ||
3d13ef2e | 10797 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10798 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10799 | |
43694d69 | 10800 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10801 | } |
10802 | ||
79e53945 JB |
10803 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10804 | { | |
10805 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10806 | struct drm_device *dev = crtc->dev; |
10807 | struct intel_unpin_work *work; | |
67e77c5a | 10808 | |
5e2d7afc | 10809 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10810 | work = intel_crtc->unpin_work; |
10811 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10812 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10813 | |
10814 | if (work) { | |
10815 | cancel_work_sync(&work->work); | |
10816 | kfree(work); | |
10817 | } | |
79e53945 JB |
10818 | |
10819 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10820 | |
79e53945 JB |
10821 | kfree(intel_crtc); |
10822 | } | |
10823 | ||
6b95a207 KH |
10824 | static void intel_unpin_work_fn(struct work_struct *__work) |
10825 | { | |
10826 | struct intel_unpin_work *work = | |
10827 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10828 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10829 | struct drm_device *dev = crtc->base.dev; | |
10830 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10831 | |
b4a98e57 | 10832 | mutex_lock(&dev->struct_mutex); |
3465c580 | 10833 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); |
05394f39 | 10834 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10835 | |
f06cc1b9 | 10836 | if (work->flip_queued_req) |
146d84f0 | 10837 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10838 | mutex_unlock(&dev->struct_mutex); |
10839 | ||
a9ff8714 | 10840 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 10841 | intel_fbc_post_update(crtc); |
89ed88ba | 10842 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10843 | |
a9ff8714 VS |
10844 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10845 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10846 | |
6b95a207 KH |
10847 | kfree(work); |
10848 | } | |
10849 | ||
1afe3e9d | 10850 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10851 | struct drm_crtc *crtc) |
6b95a207 | 10852 | { |
6b95a207 KH |
10853 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10854 | struct intel_unpin_work *work; | |
6b95a207 KH |
10855 | unsigned long flags; |
10856 | ||
10857 | /* Ignore early vblank irqs */ | |
10858 | if (intel_crtc == NULL) | |
10859 | return; | |
10860 | ||
f326038a DV |
10861 | /* |
10862 | * This is called both by irq handlers and the reset code (to complete | |
10863 | * lost pageflips) so needs the full irqsave spinlocks. | |
10864 | */ | |
6b95a207 KH |
10865 | spin_lock_irqsave(&dev->event_lock, flags); |
10866 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10867 | |
10868 | /* Ensure we don't miss a work->pending update ... */ | |
10869 | smp_rmb(); | |
10870 | ||
10871 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10872 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10873 | return; | |
10874 | } | |
10875 | ||
d6bbafa1 | 10876 | page_flip_completed(intel_crtc); |
0af7e4df | 10877 | |
6b95a207 | 10878 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10879 | } |
10880 | ||
1afe3e9d JB |
10881 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10882 | { | |
fbee40df | 10883 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10884 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10885 | ||
49b14a5c | 10886 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10887 | } |
10888 | ||
10889 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10890 | { | |
fbee40df | 10891 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10892 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10893 | ||
49b14a5c | 10894 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10895 | } |
10896 | ||
75f7f3ec VS |
10897 | /* Is 'a' after or equal to 'b'? */ |
10898 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10899 | { | |
10900 | return !((a - b) & 0x80000000); | |
10901 | } | |
10902 | ||
10903 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10904 | { | |
10905 | struct drm_device *dev = crtc->base.dev; | |
10906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10907 | ||
bdfa7542 VS |
10908 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10909 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10910 | return true; | |
10911 | ||
75f7f3ec VS |
10912 | /* |
10913 | * The relevant registers doen't exist on pre-ctg. | |
10914 | * As the flip done interrupt doesn't trigger for mmio | |
10915 | * flips on gmch platforms, a flip count check isn't | |
10916 | * really needed there. But since ctg has the registers, | |
10917 | * include it in the check anyway. | |
10918 | */ | |
10919 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10920 | return true; | |
10921 | ||
e8861675 ML |
10922 | /* |
10923 | * BDW signals flip done immediately if the plane | |
10924 | * is disabled, even if the plane enable is already | |
10925 | * armed to occur at the next vblank :( | |
10926 | */ | |
10927 | ||
75f7f3ec VS |
10928 | /* |
10929 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10930 | * used the same base address. In that case the mmio flip might | |
10931 | * have completed, but the CS hasn't even executed the flip yet. | |
10932 | * | |
10933 | * A flip count check isn't enough as the CS might have updated | |
10934 | * the base address just after start of vblank, but before we | |
10935 | * managed to process the interrupt. This means we'd complete the | |
10936 | * CS flip too soon. | |
10937 | * | |
10938 | * Combining both checks should get us a good enough result. It may | |
10939 | * still happen that the CS flip has been executed, but has not | |
10940 | * yet actually completed. But in case the base address is the same | |
10941 | * anyway, we don't really care. | |
10942 | */ | |
10943 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10944 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10945 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
10946 | crtc->unpin_work->flip_count); |
10947 | } | |
10948 | ||
6b95a207 KH |
10949 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10950 | { | |
fbee40df | 10951 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10952 | struct intel_crtc *intel_crtc = |
10953 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10954 | unsigned long flags; | |
10955 | ||
f326038a DV |
10956 | |
10957 | /* | |
10958 | * This is called both by irq handlers and the reset code (to complete | |
10959 | * lost pageflips) so needs the full irqsave spinlocks. | |
10960 | * | |
10961 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10962 | * generate a page-flip completion irq, i.e. every modeset |
10963 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10964 | */ | |
6b95a207 | 10965 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10966 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10967 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10968 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10969 | } | |
10970 | ||
6042639c | 10971 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
10972 | { |
10973 | /* Ensure that the work item is consistent when activating it ... */ | |
10974 | smp_wmb(); | |
6042639c | 10975 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
10976 | /* and that it is marked active as soon as the irq could fire. */ |
10977 | smp_wmb(); | |
10978 | } | |
10979 | ||
8c9f3aaf JB |
10980 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10981 | struct drm_crtc *crtc, | |
10982 | struct drm_framebuffer *fb, | |
ed8d1975 | 10983 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10984 | struct drm_i915_gem_request *req, |
ed8d1975 | 10985 | uint32_t flags) |
8c9f3aaf | 10986 | { |
4a570db5 | 10987 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 10988 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10989 | u32 flip_mask; |
10990 | int ret; | |
10991 | ||
5fb9de1a | 10992 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10993 | if (ret) |
4fa62c89 | 10994 | return ret; |
8c9f3aaf JB |
10995 | |
10996 | /* Can't queue multiple flips, so wait for the previous | |
10997 | * one to finish before executing the next. | |
10998 | */ | |
10999 | if (intel_crtc->plane) | |
11000 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11001 | else | |
11002 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
11003 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
11004 | intel_ring_emit(engine, MI_NOOP); | |
11005 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
6d90c952 | 11006 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11007 | intel_ring_emit(engine, fb->pitches[0]); |
11008 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11009 | intel_ring_emit(engine, 0); /* aux display base address, unused */ | |
e7d841ca | 11010 | |
6042639c | 11011 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11012 | return 0; |
8c9f3aaf JB |
11013 | } |
11014 | ||
11015 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11016 | struct drm_crtc *crtc, | |
11017 | struct drm_framebuffer *fb, | |
ed8d1975 | 11018 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11019 | struct drm_i915_gem_request *req, |
ed8d1975 | 11020 | uint32_t flags) |
8c9f3aaf | 11021 | { |
4a570db5 | 11022 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 11023 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11024 | u32 flip_mask; |
11025 | int ret; | |
11026 | ||
5fb9de1a | 11027 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11028 | if (ret) |
4fa62c89 | 11029 | return ret; |
8c9f3aaf JB |
11030 | |
11031 | if (intel_crtc->plane) | |
11032 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11033 | else | |
11034 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
11035 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
11036 | intel_ring_emit(engine, MI_NOOP); | |
11037 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | | |
6d90c952 | 11038 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11039 | intel_ring_emit(engine, fb->pitches[0]); |
11040 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11041 | intel_ring_emit(engine, MI_NOOP); | |
6d90c952 | 11042 | |
6042639c | 11043 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11044 | return 0; |
8c9f3aaf JB |
11045 | } |
11046 | ||
11047 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11048 | struct drm_crtc *crtc, | |
11049 | struct drm_framebuffer *fb, | |
ed8d1975 | 11050 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11051 | struct drm_i915_gem_request *req, |
ed8d1975 | 11052 | uint32_t flags) |
8c9f3aaf | 11053 | { |
4a570db5 | 11054 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
11055 | struct drm_i915_private *dev_priv = dev->dev_private; |
11056 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11057 | uint32_t pf, pipesrc; | |
11058 | int ret; | |
11059 | ||
5fb9de1a | 11060 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11061 | if (ret) |
4fa62c89 | 11062 | return ret; |
8c9f3aaf JB |
11063 | |
11064 | /* i965+ uses the linear or tiled offsets from the | |
11065 | * Display Registers (which do not change across a page-flip) | |
11066 | * so we need only reprogram the base address. | |
11067 | */ | |
e2f80391 | 11068 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 11069 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11070 | intel_ring_emit(engine, fb->pitches[0]); |
11071 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset | | |
c2c75131 | 11072 | obj->tiling_mode); |
8c9f3aaf JB |
11073 | |
11074 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11075 | * untested on non-native modes, so ignore it for now. | |
11076 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11077 | */ | |
11078 | pf = 0; | |
11079 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
e2f80391 | 11080 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 11081 | |
6042639c | 11082 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11083 | return 0; |
8c9f3aaf JB |
11084 | } |
11085 | ||
11086 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11087 | struct drm_crtc *crtc, | |
11088 | struct drm_framebuffer *fb, | |
ed8d1975 | 11089 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11090 | struct drm_i915_gem_request *req, |
ed8d1975 | 11091 | uint32_t flags) |
8c9f3aaf | 11092 | { |
4a570db5 | 11093 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
11094 | struct drm_i915_private *dev_priv = dev->dev_private; |
11095 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11096 | uint32_t pf, pipesrc; | |
11097 | int ret; | |
11098 | ||
5fb9de1a | 11099 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11100 | if (ret) |
4fa62c89 | 11101 | return ret; |
8c9f3aaf | 11102 | |
e2f80391 | 11103 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 11104 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11105 | intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); |
11106 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
8c9f3aaf | 11107 | |
dc257cf1 DV |
11108 | /* Contrary to the suggestions in the documentation, |
11109 | * "Enable Panel Fitter" does not seem to be required when page | |
11110 | * flipping with a non-native mode, and worse causes a normal | |
11111 | * modeset to fail. | |
11112 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11113 | */ | |
11114 | pf = 0; | |
8c9f3aaf | 11115 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
e2f80391 | 11116 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 11117 | |
6042639c | 11118 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11119 | return 0; |
8c9f3aaf JB |
11120 | } |
11121 | ||
7c9017e5 JB |
11122 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11123 | struct drm_crtc *crtc, | |
11124 | struct drm_framebuffer *fb, | |
ed8d1975 | 11125 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11126 | struct drm_i915_gem_request *req, |
ed8d1975 | 11127 | uint32_t flags) |
7c9017e5 | 11128 | { |
4a570db5 | 11129 | struct intel_engine_cs *engine = req->engine; |
7c9017e5 | 11130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11131 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11132 | int len, ret; |
11133 | ||
eba905b2 | 11134 | switch (intel_crtc->plane) { |
cb05d8de DV |
11135 | case PLANE_A: |
11136 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11137 | break; | |
11138 | case PLANE_B: | |
11139 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11140 | break; | |
11141 | case PLANE_C: | |
11142 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11143 | break; | |
11144 | default: | |
11145 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11146 | return -ENODEV; |
cb05d8de DV |
11147 | } |
11148 | ||
ffe74d75 | 11149 | len = 4; |
e2f80391 | 11150 | if (engine->id == RCS) { |
ffe74d75 | 11151 | len += 6; |
f476828a DL |
11152 | /* |
11153 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11154 | * 48bits addresses, and we need a NOOP for the batch size to | |
11155 | * stay even. | |
11156 | */ | |
11157 | if (IS_GEN8(dev)) | |
11158 | len += 2; | |
11159 | } | |
ffe74d75 | 11160 | |
f66fab8e VS |
11161 | /* |
11162 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11163 | * "The full packet must be contained within the same cache line." | |
11164 | * | |
11165 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11166 | * cacheline, if we ever start emitting more commands before | |
11167 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11168 | * then do the cacheline alignment, and finally emit the | |
11169 | * MI_DISPLAY_FLIP. | |
11170 | */ | |
bba09b12 | 11171 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11172 | if (ret) |
4fa62c89 | 11173 | return ret; |
f66fab8e | 11174 | |
5fb9de1a | 11175 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11176 | if (ret) |
4fa62c89 | 11177 | return ret; |
7c9017e5 | 11178 | |
ffe74d75 CW |
11179 | /* Unmask the flip-done completion message. Note that the bspec says that |
11180 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11181 | * more than one flip event at any time (or ensure that one flip message | |
11182 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11183 | * Experimentation says that BCS works despite DERRMR masking all | |
11184 | * flip-done completion events and that unmasking all planes at once | |
11185 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11186 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11187 | */ | |
e2f80391 TU |
11188 | if (engine->id == RCS) { |
11189 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
11190 | intel_ring_emit_reg(engine, DERRMR); | |
11191 | intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11192 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11193 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11194 | if (IS_GEN8(dev)) |
e2f80391 | 11195 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11196 | MI_SRM_LRM_GLOBAL_GTT); |
11197 | else | |
e2f80391 | 11198 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM | |
f476828a | 11199 | MI_SRM_LRM_GLOBAL_GTT); |
e2f80391 TU |
11200 | intel_ring_emit_reg(engine, DERRMR); |
11201 | intel_ring_emit(engine, engine->scratch.gtt_offset + 256); | |
f476828a | 11202 | if (IS_GEN8(dev)) { |
e2f80391 TU |
11203 | intel_ring_emit(engine, 0); |
11204 | intel_ring_emit(engine, MI_NOOP); | |
f476828a | 11205 | } |
ffe74d75 CW |
11206 | } |
11207 | ||
e2f80391 TU |
11208 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); |
11209 | intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); | |
11210 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11211 | intel_ring_emit(engine, (MI_NOOP)); | |
e7d841ca | 11212 | |
6042639c | 11213 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11214 | return 0; |
7c9017e5 JB |
11215 | } |
11216 | ||
0bc40be8 | 11217 | static bool use_mmio_flip(struct intel_engine_cs *engine, |
84c33a64 SG |
11218 | struct drm_i915_gem_object *obj) |
11219 | { | |
11220 | /* | |
11221 | * This is not being used for older platforms, because | |
11222 | * non-availability of flip done interrupt forces us to use | |
11223 | * CS flips. Older platforms derive flip done using some clever | |
11224 | * tricks involving the flip_pending status bits and vblank irqs. | |
11225 | * So using MMIO flips there would disrupt this mechanism. | |
11226 | */ | |
11227 | ||
0bc40be8 | 11228 | if (engine == NULL) |
8e09bf83 CW |
11229 | return true; |
11230 | ||
0bc40be8 | 11231 | if (INTEL_INFO(engine->dev)->gen < 5) |
84c33a64 SG |
11232 | return false; |
11233 | ||
11234 | if (i915.use_mmio_flip < 0) | |
11235 | return false; | |
11236 | else if (i915.use_mmio_flip > 0) | |
11237 | return true; | |
14bf993e OM |
11238 | else if (i915.enable_execlists) |
11239 | return true; | |
fd8e058a AG |
11240 | else if (obj->base.dma_buf && |
11241 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11242 | false)) | |
11243 | return true; | |
84c33a64 | 11244 | else |
666796da | 11245 | return engine != i915_gem_request_get_engine(obj->last_write_req); |
84c33a64 SG |
11246 | } |
11247 | ||
6042639c | 11248 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11249 | unsigned int rotation, |
6042639c | 11250 | struct intel_unpin_work *work) |
ff944564 DL |
11251 | { |
11252 | struct drm_device *dev = intel_crtc->base.dev; | |
11253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11254 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11255 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11256 | u32 ctl, stride, tile_height; |
ff944564 DL |
11257 | |
11258 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11259 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11260 | switch (fb->modifier[0]) { |
11261 | case DRM_FORMAT_MOD_NONE: | |
11262 | break; | |
11263 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11264 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11265 | break; |
11266 | case I915_FORMAT_MOD_Y_TILED: | |
11267 | ctl |= PLANE_CTL_TILED_Y; | |
11268 | break; | |
11269 | case I915_FORMAT_MOD_Yf_TILED: | |
11270 | ctl |= PLANE_CTL_TILED_YF; | |
11271 | break; | |
11272 | default: | |
11273 | MISSING_CASE(fb->modifier[0]); | |
11274 | } | |
ff944564 DL |
11275 | |
11276 | /* | |
11277 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11278 | * linear buffers or in number of tiles for tiled buffers. | |
11279 | */ | |
86efe24a TU |
11280 | if (intel_rotation_90_or_270(rotation)) { |
11281 | /* stride = Surface height in tiles */ | |
832be82f | 11282 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11283 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11284 | } else { | |
11285 | stride = fb->pitches[0] / | |
7b49f948 VS |
11286 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11287 | fb->pixel_format); | |
86efe24a | 11288 | } |
ff944564 DL |
11289 | |
11290 | /* | |
11291 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11292 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11293 | */ | |
11294 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11295 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11296 | ||
6042639c | 11297 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11298 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11299 | } | |
11300 | ||
6042639c CW |
11301 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11302 | struct intel_unpin_work *work) | |
84c33a64 SG |
11303 | { |
11304 | struct drm_device *dev = intel_crtc->base.dev; | |
11305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11306 | struct intel_framebuffer *intel_fb = | |
11307 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11308 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11309 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11310 | u32 dspcntr; |
84c33a64 | 11311 | |
84c33a64 SG |
11312 | dspcntr = I915_READ(reg); |
11313 | ||
c5d97472 DL |
11314 | if (obj->tiling_mode != I915_TILING_NONE) |
11315 | dspcntr |= DISPPLANE_TILED; | |
11316 | else | |
11317 | dspcntr &= ~DISPPLANE_TILED; | |
11318 | ||
84c33a64 SG |
11319 | I915_WRITE(reg, dspcntr); |
11320 | ||
6042639c | 11321 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11322 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11323 | } |
11324 | ||
11325 | /* | |
11326 | * XXX: This is the temporary way to update the plane registers until we get | |
11327 | * around to using the usual plane update functions for MMIO flips | |
11328 | */ | |
6042639c | 11329 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11330 | { |
6042639c CW |
11331 | struct intel_crtc *crtc = mmio_flip->crtc; |
11332 | struct intel_unpin_work *work; | |
11333 | ||
11334 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11335 | work = crtc->unpin_work; | |
11336 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11337 | if (work == NULL) | |
11338 | return; | |
ff944564 | 11339 | |
6042639c | 11340 | intel_mark_page_flip_active(work); |
ff944564 | 11341 | |
6042639c | 11342 | intel_pipe_update_start(crtc); |
ff944564 | 11343 | |
6042639c | 11344 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11345 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11346 | else |
11347 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11348 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11349 | |
6042639c | 11350 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11351 | } |
11352 | ||
9362c7c5 | 11353 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11354 | { |
b2cfe0ab CW |
11355 | struct intel_mmio_flip *mmio_flip = |
11356 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11357 | struct intel_framebuffer *intel_fb = |
11358 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11359 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11360 | |
6042639c | 11361 | if (mmio_flip->req) { |
eed29a5b | 11362 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11363 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11364 | false, NULL, |
11365 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11366 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11367 | } | |
84c33a64 | 11368 | |
fd8e058a AG |
11369 | /* For framebuffer backed by dmabuf, wait for fence */ |
11370 | if (obj->base.dma_buf) | |
11371 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11372 | false, false, | |
11373 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11374 | ||
6042639c | 11375 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11376 | kfree(mmio_flip); |
84c33a64 SG |
11377 | } |
11378 | ||
11379 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11380 | struct drm_crtc *crtc, | |
86efe24a | 11381 | struct drm_i915_gem_object *obj) |
84c33a64 | 11382 | { |
b2cfe0ab CW |
11383 | struct intel_mmio_flip *mmio_flip; |
11384 | ||
11385 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11386 | if (mmio_flip == NULL) | |
11387 | return -ENOMEM; | |
84c33a64 | 11388 | |
bcafc4e3 | 11389 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11390 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11391 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11392 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11393 | |
b2cfe0ab CW |
11394 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11395 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11396 | |
84c33a64 SG |
11397 | return 0; |
11398 | } | |
11399 | ||
8c9f3aaf JB |
11400 | static int intel_default_queue_flip(struct drm_device *dev, |
11401 | struct drm_crtc *crtc, | |
11402 | struct drm_framebuffer *fb, | |
ed8d1975 | 11403 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11404 | struct drm_i915_gem_request *req, |
ed8d1975 | 11405 | uint32_t flags) |
8c9f3aaf JB |
11406 | { |
11407 | return -ENODEV; | |
11408 | } | |
11409 | ||
d6bbafa1 CW |
11410 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11411 | struct drm_crtc *crtc) | |
11412 | { | |
11413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11414 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11415 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11416 | u32 addr; | |
11417 | ||
11418 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11419 | return true; | |
11420 | ||
908565c2 CW |
11421 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11422 | return false; | |
11423 | ||
d6bbafa1 CW |
11424 | if (!work->enable_stall_check) |
11425 | return false; | |
11426 | ||
11427 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11428 | if (work->flip_queued_req && |
11429 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11430 | return false; |
11431 | ||
1e3feefd | 11432 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11433 | } |
11434 | ||
1e3feefd | 11435 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11436 | return false; |
11437 | ||
11438 | /* Potential stall - if we see that the flip has happened, | |
11439 | * assume a missed interrupt. */ | |
11440 | if (INTEL_INFO(dev)->gen >= 4) | |
11441 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11442 | else | |
11443 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11444 | ||
11445 | /* There is a potential issue here with a false positive after a flip | |
11446 | * to the same address. We could address this by checking for a | |
11447 | * non-incrementing frame counter. | |
11448 | */ | |
11449 | return addr == work->gtt_offset; | |
11450 | } | |
11451 | ||
11452 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11453 | { | |
11454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11455 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11456 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11457 | struct intel_unpin_work *work; |
f326038a | 11458 | |
6c51d46f | 11459 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11460 | |
11461 | if (crtc == NULL) | |
11462 | return; | |
11463 | ||
f326038a | 11464 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11465 | work = intel_crtc->unpin_work; |
11466 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11467 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11468 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11469 | page_flip_completed(intel_crtc); |
6ad790c0 | 11470 | work = NULL; |
d6bbafa1 | 11471 | } |
6ad790c0 CW |
11472 | if (work != NULL && |
11473 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11474 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11475 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11476 | } |
11477 | ||
6b95a207 KH |
11478 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11479 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11480 | struct drm_pending_vblank_event *event, |
11481 | uint32_t page_flip_flags) | |
6b95a207 KH |
11482 | { |
11483 | struct drm_device *dev = crtc->dev; | |
11484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11485 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11486 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11488 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11489 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11490 | struct intel_unpin_work *work; |
e2f80391 | 11491 | struct intel_engine_cs *engine; |
cf5d8a46 | 11492 | bool mmio_flip; |
91af127f | 11493 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11494 | int ret; |
6b95a207 | 11495 | |
2ff8fde1 MR |
11496 | /* |
11497 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11498 | * check to be safe. In the future we may enable pageflipping from | |
11499 | * a disabled primary plane. | |
11500 | */ | |
11501 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11502 | return -EBUSY; | |
11503 | ||
e6a595d2 | 11504 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11505 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11506 | return -EINVAL; |
11507 | ||
11508 | /* | |
11509 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11510 | * Note that pitch changes could also affect these register. | |
11511 | */ | |
11512 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11513 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11514 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11515 | return -EINVAL; |
11516 | ||
f900db47 CW |
11517 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11518 | goto out_hang; | |
11519 | ||
b14c5679 | 11520 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11521 | if (work == NULL) |
11522 | return -ENOMEM; | |
11523 | ||
6b95a207 | 11524 | work->event = event; |
b4a98e57 | 11525 | work->crtc = crtc; |
ab8d6675 | 11526 | work->old_fb = old_fb; |
6b95a207 KH |
11527 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11528 | ||
87b6b101 | 11529 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11530 | if (ret) |
11531 | goto free_work; | |
11532 | ||
6b95a207 | 11533 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11534 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11535 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11536 | /* Before declaring the flip queue wedged, check if |
11537 | * the hardware completed the operation behind our backs. | |
11538 | */ | |
11539 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11540 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11541 | page_flip_completed(intel_crtc); | |
11542 | } else { | |
11543 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11544 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11545 | |
d6bbafa1 CW |
11546 | drm_crtc_vblank_put(crtc); |
11547 | kfree(work); | |
11548 | return -EBUSY; | |
11549 | } | |
6b95a207 KH |
11550 | } |
11551 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11552 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11553 | |
b4a98e57 CW |
11554 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11555 | flush_workqueue(dev_priv->wq); | |
11556 | ||
75dfca80 | 11557 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11558 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11559 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11560 | |
f4510a27 | 11561 | crtc->primary->fb = fb; |
afd65eb4 | 11562 | update_state_fb(crtc->primary); |
e8216e50 | 11563 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11564 | |
e1f99ce6 | 11565 | work->pending_flip_obj = obj; |
e1f99ce6 | 11566 | |
89ed88ba CW |
11567 | ret = i915_mutex_lock_interruptible(dev); |
11568 | if (ret) | |
11569 | goto cleanup; | |
11570 | ||
b4a98e57 | 11571 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11572 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11573 | |
75f7f3ec | 11574 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11575 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11576 | |
666a4537 | 11577 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4a570db5 | 11578 | engine = &dev_priv->engine[BCS]; |
ab8d6675 | 11579 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 | 11580 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
e2f80391 | 11581 | engine = NULL; |
48bf5b2d | 11582 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
4a570db5 | 11583 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11584 | } else if (INTEL_INFO(dev)->gen >= 7) { |
666796da | 11585 | engine = i915_gem_request_get_engine(obj->last_write_req); |
e2f80391 | 11586 | if (engine == NULL || engine->id != RCS) |
4a570db5 | 11587 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11588 | } else { |
4a570db5 | 11589 | engine = &dev_priv->engine[RCS]; |
4fa62c89 VS |
11590 | } |
11591 | ||
e2f80391 | 11592 | mmio_flip = use_mmio_flip(engine, obj); |
cf5d8a46 CW |
11593 | |
11594 | /* When using CS flips, we want to emit semaphores between rings. | |
11595 | * However, when using mmio flips we will create a task to do the | |
11596 | * synchronisation, so all we want here is to pin the framebuffer | |
11597 | * into the display plane and skip any waits. | |
11598 | */ | |
7580d774 | 11599 | if (!mmio_flip) { |
e2f80391 | 11600 | ret = i915_gem_object_sync(obj, engine, &request); |
7580d774 ML |
11601 | if (ret) |
11602 | goto cleanup_pending; | |
11603 | } | |
11604 | ||
3465c580 | 11605 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
8c9f3aaf JB |
11606 | if (ret) |
11607 | goto cleanup_pending; | |
6b95a207 | 11608 | |
dedf278c TU |
11609 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11610 | obj, 0); | |
11611 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11612 | |
cf5d8a46 | 11613 | if (mmio_flip) { |
86efe24a | 11614 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11615 | if (ret) |
11616 | goto cleanup_unpin; | |
11617 | ||
f06cc1b9 JH |
11618 | i915_gem_request_assign(&work->flip_queued_req, |
11619 | obj->last_write_req); | |
d6bbafa1 | 11620 | } else { |
6258fbe2 | 11621 | if (!request) { |
e2f80391 | 11622 | request = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
11623 | if (IS_ERR(request)) { |
11624 | ret = PTR_ERR(request); | |
6258fbe2 | 11625 | goto cleanup_unpin; |
26827088 | 11626 | } |
6258fbe2 JH |
11627 | } |
11628 | ||
11629 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11630 | page_flip_flags); |
11631 | if (ret) | |
11632 | goto cleanup_unpin; | |
11633 | ||
6258fbe2 | 11634 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11635 | } |
11636 | ||
91af127f | 11637 | if (request) |
75289874 | 11638 | i915_add_request_no_flush(request); |
91af127f | 11639 | |
1e3feefd | 11640 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11641 | work->enable_stall_check = true; |
4fa62c89 | 11642 | |
ab8d6675 | 11643 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11644 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11645 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11646 | |
a9ff8714 VS |
11647 | intel_frontbuffer_flip_prepare(dev, |
11648 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11649 | |
e5510fac JB |
11650 | trace_i915_flip_request(intel_crtc->plane, obj); |
11651 | ||
6b95a207 | 11652 | return 0; |
96b099fd | 11653 | |
4fa62c89 | 11654 | cleanup_unpin: |
3465c580 | 11655 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); |
8c9f3aaf | 11656 | cleanup_pending: |
0aa498d5 | 11657 | if (!IS_ERR_OR_NULL(request)) |
91af127f | 11658 | i915_gem_request_cancel(request); |
b4a98e57 | 11659 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11660 | mutex_unlock(&dev->struct_mutex); |
11661 | cleanup: | |
f4510a27 | 11662 | crtc->primary->fb = old_fb; |
afd65eb4 | 11663 | update_state_fb(crtc->primary); |
89ed88ba CW |
11664 | |
11665 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11666 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11667 | |
5e2d7afc | 11668 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11669 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11670 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11671 | |
87b6b101 | 11672 | drm_crtc_vblank_put(crtc); |
7317c75e | 11673 | free_work: |
96b099fd CW |
11674 | kfree(work); |
11675 | ||
f900db47 | 11676 | if (ret == -EIO) { |
02e0efb5 ML |
11677 | struct drm_atomic_state *state; |
11678 | struct drm_plane_state *plane_state; | |
11679 | ||
f900db47 | 11680 | out_hang: |
02e0efb5 ML |
11681 | state = drm_atomic_state_alloc(dev); |
11682 | if (!state) | |
11683 | return -ENOMEM; | |
11684 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11685 | ||
11686 | retry: | |
11687 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11688 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11689 | if (!ret) { | |
11690 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11691 | ||
11692 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11693 | if (!ret) | |
11694 | ret = drm_atomic_commit(state); | |
11695 | } | |
11696 | ||
11697 | if (ret == -EDEADLK) { | |
11698 | drm_modeset_backoff(state->acquire_ctx); | |
11699 | drm_atomic_state_clear(state); | |
11700 | goto retry; | |
11701 | } | |
11702 | ||
11703 | if (ret) | |
11704 | drm_atomic_state_free(state); | |
11705 | ||
f0d3dad3 | 11706 | if (ret == 0 && event) { |
5e2d7afc | 11707 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11708 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11709 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11710 | } |
f900db47 | 11711 | } |
96b099fd | 11712 | return ret; |
6b95a207 KH |
11713 | } |
11714 | ||
da20eabd ML |
11715 | |
11716 | /** | |
11717 | * intel_wm_need_update - Check whether watermarks need updating | |
11718 | * @plane: drm plane | |
11719 | * @state: new plane state | |
11720 | * | |
11721 | * Check current plane state versus the new one to determine whether | |
11722 | * watermarks need to be recalculated. | |
11723 | * | |
11724 | * Returns true or false. | |
11725 | */ | |
11726 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11727 | struct drm_plane_state *state) | |
11728 | { | |
d21fbe87 MR |
11729 | struct intel_plane_state *new = to_intel_plane_state(state); |
11730 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11731 | ||
11732 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11733 | if (new->visible != cur->visible) |
11734 | return true; | |
11735 | ||
11736 | if (!cur->base.fb || !new->base.fb) | |
11737 | return false; | |
11738 | ||
11739 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11740 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11741 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11742 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11743 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11744 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11745 | return true; |
7809e5ae | 11746 | |
2791a16c | 11747 | return false; |
7809e5ae MR |
11748 | } |
11749 | ||
d21fbe87 MR |
11750 | static bool needs_scaling(struct intel_plane_state *state) |
11751 | { | |
11752 | int src_w = drm_rect_width(&state->src) >> 16; | |
11753 | int src_h = drm_rect_height(&state->src) >> 16; | |
11754 | int dst_w = drm_rect_width(&state->dst); | |
11755 | int dst_h = drm_rect_height(&state->dst); | |
11756 | ||
11757 | return (src_w != dst_w || src_h != dst_h); | |
11758 | } | |
11759 | ||
da20eabd ML |
11760 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11761 | struct drm_plane_state *plane_state) | |
11762 | { | |
ab1d3a0e | 11763 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11764 | struct drm_crtc *crtc = crtc_state->crtc; |
11765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11766 | struct drm_plane *plane = plane_state->plane; | |
11767 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11768 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11769 | struct intel_plane_state *old_plane_state = |
11770 | to_intel_plane_state(plane->state); | |
11771 | int idx = intel_crtc->base.base.id, ret; | |
da20eabd ML |
11772 | bool mode_changed = needs_modeset(crtc_state); |
11773 | bool was_crtc_enabled = crtc->state->active; | |
11774 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11775 | bool turn_off, turn_on, visible, was_visible; |
11776 | struct drm_framebuffer *fb = plane_state->fb; | |
11777 | ||
11778 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11779 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11780 | ret = skl_update_scaler_plane( | |
11781 | to_intel_crtc_state(crtc_state), | |
11782 | to_intel_plane_state(plane_state)); | |
11783 | if (ret) | |
11784 | return ret; | |
11785 | } | |
11786 | ||
da20eabd ML |
11787 | was_visible = old_plane_state->visible; |
11788 | visible = to_intel_plane_state(plane_state)->visible; | |
11789 | ||
11790 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11791 | was_visible = false; | |
11792 | ||
35c08f43 ML |
11793 | /* |
11794 | * Visibility is calculated as if the crtc was on, but | |
11795 | * after scaler setup everything depends on it being off | |
11796 | * when the crtc isn't active. | |
11797 | */ | |
11798 | if (!is_crtc_enabled) | |
11799 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11800 | |
11801 | if (!was_visible && !visible) | |
11802 | return 0; | |
11803 | ||
e8861675 ML |
11804 | if (fb != old_plane_state->base.fb) |
11805 | pipe_config->fb_changed = true; | |
11806 | ||
da20eabd ML |
11807 | turn_off = was_visible && (!visible || mode_changed); |
11808 | turn_on = visible && (!was_visible || mode_changed); | |
11809 | ||
11810 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11811 | plane->base.id, fb ? fb->base.id : -1); | |
11812 | ||
11813 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11814 | plane->base.id, was_visible, visible, | |
11815 | turn_off, turn_on, mode_changed); | |
11816 | ||
caed361d VS |
11817 | if (turn_on) { |
11818 | pipe_config->update_wm_pre = true; | |
11819 | ||
11820 | /* must disable cxsr around plane enable/disable */ | |
11821 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11822 | pipe_config->disable_cxsr = true; | |
11823 | } else if (turn_off) { | |
11824 | pipe_config->update_wm_post = true; | |
92826fcd | 11825 | |
852eb00d | 11826 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11827 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11828 | pipe_config->disable_cxsr = true; |
852eb00d | 11829 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
11830 | /* FIXME bollocks */ |
11831 | pipe_config->update_wm_pre = true; | |
11832 | pipe_config->update_wm_post = true; | |
852eb00d | 11833 | } |
da20eabd | 11834 | |
ed4a6a7c | 11835 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
11836 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
11837 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
11838 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
11839 | ||
8be6ca85 | 11840 | if (visible || was_visible) |
cd202f69 | 11841 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 11842 | |
31ae71fc ML |
11843 | /* |
11844 | * WaCxSRDisabledForSpriteScaling:ivb | |
11845 | * | |
11846 | * cstate->update_wm was already set above, so this flag will | |
11847 | * take effect when we commit and program watermarks. | |
11848 | */ | |
11849 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
11850 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11851 | !needs_scaling(old_plane_state)) | |
11852 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 11853 | |
da20eabd ML |
11854 | return 0; |
11855 | } | |
11856 | ||
6d3a1ce7 ML |
11857 | static bool encoders_cloneable(const struct intel_encoder *a, |
11858 | const struct intel_encoder *b) | |
11859 | { | |
11860 | /* masks could be asymmetric, so check both ways */ | |
11861 | return a == b || (a->cloneable & (1 << b->type) && | |
11862 | b->cloneable & (1 << a->type)); | |
11863 | } | |
11864 | ||
11865 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11866 | struct intel_crtc *crtc, | |
11867 | struct intel_encoder *encoder) | |
11868 | { | |
11869 | struct intel_encoder *source_encoder; | |
11870 | struct drm_connector *connector; | |
11871 | struct drm_connector_state *connector_state; | |
11872 | int i; | |
11873 | ||
11874 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11875 | if (connector_state->crtc != &crtc->base) | |
11876 | continue; | |
11877 | ||
11878 | source_encoder = | |
11879 | to_intel_encoder(connector_state->best_encoder); | |
11880 | if (!encoders_cloneable(encoder, source_encoder)) | |
11881 | return false; | |
11882 | } | |
11883 | ||
11884 | return true; | |
11885 | } | |
11886 | ||
11887 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11888 | struct intel_crtc *crtc) | |
11889 | { | |
11890 | struct intel_encoder *encoder; | |
11891 | struct drm_connector *connector; | |
11892 | struct drm_connector_state *connector_state; | |
11893 | int i; | |
11894 | ||
11895 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11896 | if (connector_state->crtc != &crtc->base) | |
11897 | continue; | |
11898 | ||
11899 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11900 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11901 | return false; | |
11902 | } | |
11903 | ||
11904 | return true; | |
11905 | } | |
11906 | ||
11907 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11908 | struct drm_crtc_state *crtc_state) | |
11909 | { | |
cf5a15be | 11910 | struct drm_device *dev = crtc->dev; |
ad421372 | 11911 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11912 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11913 | struct intel_crtc_state *pipe_config = |
11914 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11915 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11916 | int ret; |
6d3a1ce7 ML |
11917 | bool mode_changed = needs_modeset(crtc_state); |
11918 | ||
11919 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11920 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11921 | return -EINVAL; | |
11922 | } | |
11923 | ||
852eb00d | 11924 | if (mode_changed && !crtc_state->active) |
caed361d | 11925 | pipe_config->update_wm_post = true; |
eddfcbcd | 11926 | |
ad421372 ML |
11927 | if (mode_changed && crtc_state->enable && |
11928 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 11929 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
11930 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
11931 | pipe_config); | |
11932 | if (ret) | |
11933 | return ret; | |
11934 | } | |
11935 | ||
82cf435b LL |
11936 | if (crtc_state->color_mgmt_changed) { |
11937 | ret = intel_color_check(crtc, crtc_state); | |
11938 | if (ret) | |
11939 | return ret; | |
11940 | } | |
11941 | ||
e435d6e5 | 11942 | ret = 0; |
86c8bbbe | 11943 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 11944 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
11945 | if (ret) { |
11946 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
11947 | return ret; | |
11948 | } | |
11949 | } | |
11950 | ||
11951 | if (dev_priv->display.compute_intermediate_wm && | |
11952 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
11953 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
11954 | return 0; | |
11955 | ||
11956 | /* | |
11957 | * Calculate 'intermediate' watermarks that satisfy both the | |
11958 | * old state and the new state. We can program these | |
11959 | * immediately. | |
11960 | */ | |
11961 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
11962 | intel_crtc, | |
11963 | pipe_config); | |
11964 | if (ret) { | |
11965 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 11966 | return ret; |
ed4a6a7c | 11967 | } |
86c8bbbe MR |
11968 | } |
11969 | ||
e435d6e5 ML |
11970 | if (INTEL_INFO(dev)->gen >= 9) { |
11971 | if (mode_changed) | |
11972 | ret = skl_update_scaler_crtc(pipe_config); | |
11973 | ||
11974 | if (!ret) | |
11975 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11976 | pipe_config); | |
11977 | } | |
11978 | ||
11979 | return ret; | |
6d3a1ce7 ML |
11980 | } |
11981 | ||
65b38e0d | 11982 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 11983 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
ea2c67bb MR |
11984 | .atomic_begin = intel_begin_crtc_commit, |
11985 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11986 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11987 | }; |
11988 | ||
d29b2f9d ACO |
11989 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11990 | { | |
11991 | struct intel_connector *connector; | |
11992 | ||
11993 | for_each_intel_connector(dev, connector) { | |
11994 | if (connector->base.encoder) { | |
11995 | connector->base.state->best_encoder = | |
11996 | connector->base.encoder; | |
11997 | connector->base.state->crtc = | |
11998 | connector->base.encoder->crtc; | |
11999 | } else { | |
12000 | connector->base.state->best_encoder = NULL; | |
12001 | connector->base.state->crtc = NULL; | |
12002 | } | |
12003 | } | |
12004 | } | |
12005 | ||
050f7aeb | 12006 | static void |
eba905b2 | 12007 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12008 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12009 | { |
12010 | int bpp = pipe_config->pipe_bpp; | |
12011 | ||
12012 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12013 | connector->base.base.id, | |
c23cc417 | 12014 | connector->base.name); |
050f7aeb DV |
12015 | |
12016 | /* Don't use an invalid EDID bpc value */ | |
12017 | if (connector->base.display_info.bpc && | |
12018 | connector->base.display_info.bpc * 3 < bpp) { | |
12019 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12020 | bpp, connector->base.display_info.bpc*3); | |
12021 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12022 | } | |
12023 | ||
013dd9e0 JN |
12024 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12025 | if (connector->base.display_info.bpc == 0) { | |
12026 | int type = connector->base.connector_type; | |
12027 | int clamp_bpp = 24; | |
12028 | ||
12029 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12030 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12031 | type == DRM_MODE_CONNECTOR_eDP) | |
12032 | clamp_bpp = 18; | |
12033 | ||
12034 | if (bpp > clamp_bpp) { | |
12035 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12036 | bpp, clamp_bpp); | |
12037 | pipe_config->pipe_bpp = clamp_bpp; | |
12038 | } | |
050f7aeb DV |
12039 | } |
12040 | } | |
12041 | ||
4e53c2e0 | 12042 | static int |
050f7aeb | 12043 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12044 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12045 | { |
050f7aeb | 12046 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12047 | struct drm_atomic_state *state; |
da3ced29 ACO |
12048 | struct drm_connector *connector; |
12049 | struct drm_connector_state *connector_state; | |
1486017f | 12050 | int bpp, i; |
4e53c2e0 | 12051 | |
666a4537 | 12052 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12053 | bpp = 10*3; |
d328c9d7 DV |
12054 | else if (INTEL_INFO(dev)->gen >= 5) |
12055 | bpp = 12*3; | |
12056 | else | |
12057 | bpp = 8*3; | |
12058 | ||
4e53c2e0 | 12059 | |
4e53c2e0 DV |
12060 | pipe_config->pipe_bpp = bpp; |
12061 | ||
1486017f ACO |
12062 | state = pipe_config->base.state; |
12063 | ||
4e53c2e0 | 12064 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12065 | for_each_connector_in_state(state, connector, connector_state, i) { |
12066 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12067 | continue; |
12068 | ||
da3ced29 ACO |
12069 | connected_sink_compute_bpp(to_intel_connector(connector), |
12070 | pipe_config); | |
4e53c2e0 DV |
12071 | } |
12072 | ||
12073 | return bpp; | |
12074 | } | |
12075 | ||
644db711 DV |
12076 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12077 | { | |
12078 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12079 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12080 | mode->crtc_clock, |
644db711 DV |
12081 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12082 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12083 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12084 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12085 | } | |
12086 | ||
c0b03411 | 12087 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12088 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12089 | const char *context) |
12090 | { | |
6a60cd87 CK |
12091 | struct drm_device *dev = crtc->base.dev; |
12092 | struct drm_plane *plane; | |
12093 | struct intel_plane *intel_plane; | |
12094 | struct intel_plane_state *state; | |
12095 | struct drm_framebuffer *fb; | |
12096 | ||
12097 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12098 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 | 12099 | |
da205630 | 12100 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12101 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12102 | pipe_config->pipe_bpp, pipe_config->dither); | |
12103 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12104 | pipe_config->has_pch_encoder, | |
12105 | pipe_config->fdi_lanes, | |
12106 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12107 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12108 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12109 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12110 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12111 | pipe_config->lane_count, |
eb14cb74 VS |
12112 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12113 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12114 | pipe_config->dp_m_n.tu); | |
b95af8be | 12115 | |
90a6b7b0 | 12116 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12117 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12118 | pipe_config->lane_count, |
b95af8be VK |
12119 | pipe_config->dp_m2_n2.gmch_m, |
12120 | pipe_config->dp_m2_n2.gmch_n, | |
12121 | pipe_config->dp_m2_n2.link_m, | |
12122 | pipe_config->dp_m2_n2.link_n, | |
12123 | pipe_config->dp_m2_n2.tu); | |
12124 | ||
55072d19 DV |
12125 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12126 | pipe_config->has_audio, | |
12127 | pipe_config->has_infoframe); | |
12128 | ||
c0b03411 | 12129 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12130 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12131 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12132 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12133 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12134 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12135 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12136 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12137 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12138 | crtc->num_scalers, | |
12139 | pipe_config->scaler_state.scaler_users, | |
12140 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12141 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12142 | pipe_config->gmch_pfit.control, | |
12143 | pipe_config->gmch_pfit.pgm_ratios, | |
12144 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12145 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12146 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12147 | pipe_config->pch_pfit.size, |
12148 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12149 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12150 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12151 | |
415ff0f6 | 12152 | if (IS_BROXTON(dev)) { |
05712c15 | 12153 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12154 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12155 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12156 | pipe_config->ddi_pll_sel, |
12157 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12158 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12159 | pipe_config->dpll_hw_state.pll0, |
12160 | pipe_config->dpll_hw_state.pll1, | |
12161 | pipe_config->dpll_hw_state.pll2, | |
12162 | pipe_config->dpll_hw_state.pll3, | |
12163 | pipe_config->dpll_hw_state.pll6, | |
12164 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12165 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12166 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12167 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12168 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12169 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12170 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12171 | pipe_config->ddi_pll_sel, | |
12172 | pipe_config->dpll_hw_state.ctrl1, | |
12173 | pipe_config->dpll_hw_state.cfgcr1, | |
12174 | pipe_config->dpll_hw_state.cfgcr2); | |
12175 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12176 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12177 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12178 | pipe_config->dpll_hw_state.wrpll, |
12179 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12180 | } else { |
12181 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12182 | "fp0: 0x%x, fp1: 0x%x\n", | |
12183 | pipe_config->dpll_hw_state.dpll, | |
12184 | pipe_config->dpll_hw_state.dpll_md, | |
12185 | pipe_config->dpll_hw_state.fp0, | |
12186 | pipe_config->dpll_hw_state.fp1); | |
12187 | } | |
12188 | ||
6a60cd87 CK |
12189 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12190 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12191 | intel_plane = to_intel_plane(plane); | |
12192 | if (intel_plane->pipe != crtc->pipe) | |
12193 | continue; | |
12194 | ||
12195 | state = to_intel_plane_state(plane->state); | |
12196 | fb = state->base.fb; | |
12197 | if (!fb) { | |
12198 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12199 | "disabled, scaler_id = %d\n", | |
12200 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12201 | plane->base.id, intel_plane->pipe, | |
12202 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12203 | drm_plane_index(plane), state->scaler_id); | |
12204 | continue; | |
12205 | } | |
12206 | ||
12207 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12208 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12209 | plane->base.id, intel_plane->pipe, | |
12210 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12211 | drm_plane_index(plane)); | |
12212 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12213 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12214 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12215 | state->scaler_id, | |
12216 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12217 | drm_rect_width(&state->src) >> 16, | |
12218 | drm_rect_height(&state->src) >> 16, | |
12219 | state->dst.x1, state->dst.y1, | |
12220 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12221 | } | |
c0b03411 DV |
12222 | } |
12223 | ||
5448a00d | 12224 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12225 | { |
5448a00d | 12226 | struct drm_device *dev = state->dev; |
da3ced29 | 12227 | struct drm_connector *connector; |
00f0b378 VS |
12228 | unsigned int used_ports = 0; |
12229 | ||
12230 | /* | |
12231 | * Walk the connector list instead of the encoder | |
12232 | * list to detect the problem on ddi platforms | |
12233 | * where there's just one encoder per digital port. | |
12234 | */ | |
0bff4858 VS |
12235 | drm_for_each_connector(connector, dev) { |
12236 | struct drm_connector_state *connector_state; | |
12237 | struct intel_encoder *encoder; | |
12238 | ||
12239 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12240 | if (!connector_state) | |
12241 | connector_state = connector->state; | |
12242 | ||
5448a00d | 12243 | if (!connector_state->best_encoder) |
00f0b378 VS |
12244 | continue; |
12245 | ||
5448a00d ACO |
12246 | encoder = to_intel_encoder(connector_state->best_encoder); |
12247 | ||
12248 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12249 | |
12250 | switch (encoder->type) { | |
12251 | unsigned int port_mask; | |
12252 | case INTEL_OUTPUT_UNKNOWN: | |
12253 | if (WARN_ON(!HAS_DDI(dev))) | |
12254 | break; | |
12255 | case INTEL_OUTPUT_DISPLAYPORT: | |
12256 | case INTEL_OUTPUT_HDMI: | |
12257 | case INTEL_OUTPUT_EDP: | |
12258 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12259 | ||
12260 | /* the same port mustn't appear more than once */ | |
12261 | if (used_ports & port_mask) | |
12262 | return false; | |
12263 | ||
12264 | used_ports |= port_mask; | |
12265 | default: | |
12266 | break; | |
12267 | } | |
12268 | } | |
12269 | ||
12270 | return true; | |
12271 | } | |
12272 | ||
83a57153 ACO |
12273 | static void |
12274 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12275 | { | |
12276 | struct drm_crtc_state tmp_state; | |
663a3640 | 12277 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12278 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12279 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12280 | uint32_t ddi_pll_sel; |
c4e2d043 | 12281 | bool force_thru; |
83a57153 | 12282 | |
7546a384 ACO |
12283 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12284 | * kzalloc'd. Code that depends on any field being zero should be | |
12285 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12286 | * only fields that are know to not cause problems are preserved. */ | |
12287 | ||
83a57153 | 12288 | tmp_state = crtc_state->base; |
663a3640 | 12289 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12290 | shared_dpll = crtc_state->shared_dpll; |
12291 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12292 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12293 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12294 | |
83a57153 | 12295 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12296 | |
83a57153 | 12297 | crtc_state->base = tmp_state; |
663a3640 | 12298 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12299 | crtc_state->shared_dpll = shared_dpll; |
12300 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12301 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12302 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12303 | } |
12304 | ||
548ee15b | 12305 | static int |
b8cecdf5 | 12306 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12307 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12308 | { |
b359283a | 12309 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12310 | struct intel_encoder *encoder; |
da3ced29 | 12311 | struct drm_connector *connector; |
0b901879 | 12312 | struct drm_connector_state *connector_state; |
d328c9d7 | 12313 | int base_bpp, ret = -EINVAL; |
0b901879 | 12314 | int i; |
e29c22c0 | 12315 | bool retry = true; |
ee7b9f93 | 12316 | |
83a57153 | 12317 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12318 | |
e143a21c DV |
12319 | pipe_config->cpu_transcoder = |
12320 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12321 | |
2960bc9c ID |
12322 | /* |
12323 | * Sanitize sync polarity flags based on requested ones. If neither | |
12324 | * positive or negative polarity is requested, treat this as meaning | |
12325 | * negative polarity. | |
12326 | */ | |
2d112de7 | 12327 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12328 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12329 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12330 | |
2d112de7 | 12331 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12332 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12333 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12334 | |
d328c9d7 DV |
12335 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12336 | pipe_config); | |
12337 | if (base_bpp < 0) | |
4e53c2e0 DV |
12338 | goto fail; |
12339 | ||
e41a56be VS |
12340 | /* |
12341 | * Determine the real pipe dimensions. Note that stereo modes can | |
12342 | * increase the actual pipe size due to the frame doubling and | |
12343 | * insertion of additional space for blanks between the frame. This | |
12344 | * is stored in the crtc timings. We use the requested mode to do this | |
12345 | * computation to clearly distinguish it from the adjusted mode, which | |
12346 | * can be changed by the connectors in the below retry loop. | |
12347 | */ | |
2d112de7 | 12348 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12349 | &pipe_config->pipe_src_w, |
12350 | &pipe_config->pipe_src_h); | |
e41a56be | 12351 | |
e29c22c0 | 12352 | encoder_retry: |
ef1b460d | 12353 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12354 | pipe_config->port_clock = 0; |
ef1b460d | 12355 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12356 | |
135c81b8 | 12357 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12358 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12359 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12360 | |
7758a113 DV |
12361 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12362 | * adjust it according to limitations or connector properties, and also | |
12363 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12364 | */ |
da3ced29 | 12365 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12366 | if (connector_state->crtc != crtc) |
7758a113 | 12367 | continue; |
7ae89233 | 12368 | |
0b901879 ACO |
12369 | encoder = to_intel_encoder(connector_state->best_encoder); |
12370 | ||
efea6e8e DV |
12371 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12372 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12373 | goto fail; |
12374 | } | |
ee7b9f93 | 12375 | } |
47f1c6c9 | 12376 | |
ff9a6750 DV |
12377 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12378 | * done afterwards in case the encoder adjusts the mode. */ | |
12379 | if (!pipe_config->port_clock) | |
2d112de7 | 12380 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12381 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12382 | |
a43f6e0f | 12383 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12384 | if (ret < 0) { |
7758a113 DV |
12385 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12386 | goto fail; | |
ee7b9f93 | 12387 | } |
e29c22c0 DV |
12388 | |
12389 | if (ret == RETRY) { | |
12390 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12391 | ret = -EINVAL; | |
12392 | goto fail; | |
12393 | } | |
12394 | ||
12395 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12396 | retry = false; | |
12397 | goto encoder_retry; | |
12398 | } | |
12399 | ||
e8fa4270 DV |
12400 | /* Dithering seems to not pass-through bits correctly when it should, so |
12401 | * only enable it on 6bpc panels. */ | |
12402 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12403 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12404 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12405 | |
7758a113 | 12406 | fail: |
548ee15b | 12407 | return ret; |
ee7b9f93 | 12408 | } |
47f1c6c9 | 12409 | |
ea9d758d | 12410 | static void |
4740b0f2 | 12411 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12412 | { |
0a9ab303 ACO |
12413 | struct drm_crtc *crtc; |
12414 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12415 | int i; |
ea9d758d | 12416 | |
7668851f | 12417 | /* Double check state. */ |
8a75d157 | 12418 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12419 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12420 | |
12421 | /* Update hwmode for vblank functions */ | |
12422 | if (crtc->state->active) | |
12423 | crtc->hwmode = crtc->state->adjusted_mode; | |
12424 | else | |
12425 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12426 | |
12427 | /* | |
12428 | * Update legacy state to satisfy fbc code. This can | |
12429 | * be removed when fbc uses the atomic state. | |
12430 | */ | |
12431 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12432 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12433 | ||
12434 | crtc->primary->fb = plane_state->fb; | |
12435 | crtc->x = plane_state->src_x >> 16; | |
12436 | crtc->y = plane_state->src_y >> 16; | |
12437 | } | |
ea9d758d | 12438 | } |
ea9d758d DV |
12439 | } |
12440 | ||
3bd26263 | 12441 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12442 | { |
3bd26263 | 12443 | int diff; |
f1f644dc JB |
12444 | |
12445 | if (clock1 == clock2) | |
12446 | return true; | |
12447 | ||
12448 | if (!clock1 || !clock2) | |
12449 | return false; | |
12450 | ||
12451 | diff = abs(clock1 - clock2); | |
12452 | ||
12453 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12454 | return true; | |
12455 | ||
12456 | return false; | |
12457 | } | |
12458 | ||
25c5b266 DV |
12459 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12460 | list_for_each_entry((intel_crtc), \ | |
12461 | &(dev)->mode_config.crtc_list, \ | |
12462 | base.head) \ | |
95150bdf | 12463 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12464 | |
cfb23ed6 ML |
12465 | static bool |
12466 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12467 | unsigned int m2, unsigned int n2, | |
12468 | bool exact) | |
12469 | { | |
12470 | if (m == m2 && n == n2) | |
12471 | return true; | |
12472 | ||
12473 | if (exact || !m || !n || !m2 || !n2) | |
12474 | return false; | |
12475 | ||
12476 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12477 | ||
31d10b57 ML |
12478 | if (n > n2) { |
12479 | while (n > n2) { | |
cfb23ed6 ML |
12480 | m2 <<= 1; |
12481 | n2 <<= 1; | |
12482 | } | |
31d10b57 ML |
12483 | } else if (n < n2) { |
12484 | while (n < n2) { | |
cfb23ed6 ML |
12485 | m <<= 1; |
12486 | n <<= 1; | |
12487 | } | |
12488 | } | |
12489 | ||
31d10b57 ML |
12490 | if (n != n2) |
12491 | return false; | |
12492 | ||
12493 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12494 | } |
12495 | ||
12496 | static bool | |
12497 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12498 | struct intel_link_m_n *m2_n2, | |
12499 | bool adjust) | |
12500 | { | |
12501 | if (m_n->tu == m2_n2->tu && | |
12502 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12503 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12504 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12505 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12506 | if (adjust) | |
12507 | *m2_n2 = *m_n; | |
12508 | ||
12509 | return true; | |
12510 | } | |
12511 | ||
12512 | return false; | |
12513 | } | |
12514 | ||
0e8ffe1b | 12515 | static bool |
2fa2fe9a | 12516 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12517 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12518 | struct intel_crtc_state *pipe_config, |
12519 | bool adjust) | |
0e8ffe1b | 12520 | { |
cfb23ed6 ML |
12521 | bool ret = true; |
12522 | ||
12523 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12524 | do { \ | |
12525 | if (!adjust) \ | |
12526 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12527 | else \ | |
12528 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12529 | } while (0) | |
12530 | ||
66e985c0 DV |
12531 | #define PIPE_CONF_CHECK_X(name) \ |
12532 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12533 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12534 | "(expected 0x%08x, found 0x%08x)\n", \ |
12535 | current_config->name, \ | |
12536 | pipe_config->name); \ | |
cfb23ed6 | 12537 | ret = false; \ |
66e985c0 DV |
12538 | } |
12539 | ||
08a24034 DV |
12540 | #define PIPE_CONF_CHECK_I(name) \ |
12541 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12542 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12543 | "(expected %i, found %i)\n", \ |
12544 | current_config->name, \ | |
12545 | pipe_config->name); \ | |
cfb23ed6 ML |
12546 | ret = false; \ |
12547 | } | |
12548 | ||
8106ddbd ACO |
12549 | #define PIPE_CONF_CHECK_P(name) \ |
12550 | if (current_config->name != pipe_config->name) { \ | |
12551 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12552 | "(expected %p, found %p)\n", \ | |
12553 | current_config->name, \ | |
12554 | pipe_config->name); \ | |
12555 | ret = false; \ | |
12556 | } | |
12557 | ||
cfb23ed6 ML |
12558 | #define PIPE_CONF_CHECK_M_N(name) \ |
12559 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12560 | &pipe_config->name,\ | |
12561 | adjust)) { \ | |
12562 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12563 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12564 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12565 | current_config->name.tu, \ | |
12566 | current_config->name.gmch_m, \ | |
12567 | current_config->name.gmch_n, \ | |
12568 | current_config->name.link_m, \ | |
12569 | current_config->name.link_n, \ | |
12570 | pipe_config->name.tu, \ | |
12571 | pipe_config->name.gmch_m, \ | |
12572 | pipe_config->name.gmch_n, \ | |
12573 | pipe_config->name.link_m, \ | |
12574 | pipe_config->name.link_n); \ | |
12575 | ret = false; \ | |
12576 | } | |
12577 | ||
55c561a7 DV |
12578 | /* This is required for BDW+ where there is only one set of registers for |
12579 | * switching between high and low RR. | |
12580 | * This macro can be used whenever a comparison has to be made between one | |
12581 | * hw state and multiple sw state variables. | |
12582 | */ | |
cfb23ed6 ML |
12583 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
12584 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12585 | &pipe_config->name, adjust) && \ | |
12586 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12587 | &pipe_config->name, adjust)) { \ | |
12588 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12589 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12590 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12591 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12592 | current_config->name.tu, \ | |
12593 | current_config->name.gmch_m, \ | |
12594 | current_config->name.gmch_n, \ | |
12595 | current_config->name.link_m, \ | |
12596 | current_config->name.link_n, \ | |
12597 | current_config->alt_name.tu, \ | |
12598 | current_config->alt_name.gmch_m, \ | |
12599 | current_config->alt_name.gmch_n, \ | |
12600 | current_config->alt_name.link_m, \ | |
12601 | current_config->alt_name.link_n, \ | |
12602 | pipe_config->name.tu, \ | |
12603 | pipe_config->name.gmch_m, \ | |
12604 | pipe_config->name.gmch_n, \ | |
12605 | pipe_config->name.link_m, \ | |
12606 | pipe_config->name.link_n); \ | |
12607 | ret = false; \ | |
88adfff1 DV |
12608 | } |
12609 | ||
1bd1bd80 DV |
12610 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12611 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12612 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12613 | "(expected %i, found %i)\n", \ |
12614 | current_config->name & (mask), \ | |
12615 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12616 | ret = false; \ |
1bd1bd80 DV |
12617 | } |
12618 | ||
5e550656 VS |
12619 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12620 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12621 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12622 | "(expected %i, found %i)\n", \ |
12623 | current_config->name, \ | |
12624 | pipe_config->name); \ | |
cfb23ed6 | 12625 | ret = false; \ |
5e550656 VS |
12626 | } |
12627 | ||
bb760063 DV |
12628 | #define PIPE_CONF_QUIRK(quirk) \ |
12629 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12630 | ||
eccb140b DV |
12631 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12632 | ||
08a24034 DV |
12633 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12634 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12635 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12636 | |
eb14cb74 | 12637 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12638 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12639 | |
12640 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12641 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12642 | ||
cfb23ed6 ML |
12643 | if (current_config->has_drrs) |
12644 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12645 | } else | |
12646 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12647 | |
a65347ba JN |
12648 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12649 | ||
2d112de7 ACO |
12650 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12651 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12652 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12653 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12654 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12655 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12656 | |
2d112de7 ACO |
12657 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12658 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12659 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12660 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12661 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12662 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12663 | |
c93f54cf | 12664 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12665 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12666 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12667 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12668 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12669 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12670 | |
9ed109a7 DV |
12671 | PIPE_CONF_CHECK_I(has_audio); |
12672 | ||
2d112de7 | 12673 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12674 | DRM_MODE_FLAG_INTERLACE); |
12675 | ||
bb760063 | 12676 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12677 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12678 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12679 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12680 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12681 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12682 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12683 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12684 | DRM_MODE_FLAG_NVSYNC); |
12685 | } | |
045ac3b5 | 12686 | |
333b8ca8 | 12687 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12688 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12689 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 12690 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 12691 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12692 | |
bfd16b2a ML |
12693 | if (!adjust) { |
12694 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12695 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12696 | ||
12697 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12698 | if (current_config->pch_pfit.enabled) { | |
12699 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12700 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12701 | } | |
2fa2fe9a | 12702 | |
7aefe2b5 ML |
12703 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12704 | } | |
a1b2278e | 12705 | |
e59150dc JB |
12706 | /* BDW+ don't expose a synchronous way to read the state */ |
12707 | if (IS_HASWELL(dev)) | |
12708 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12709 | |
282740f7 VS |
12710 | PIPE_CONF_CHECK_I(double_wide); |
12711 | ||
26804afd DV |
12712 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12713 | ||
8106ddbd | 12714 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 12715 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12716 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12717 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12718 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12719 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12720 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12721 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12722 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12723 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12724 | |
42571aef VS |
12725 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12726 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12727 | ||
2d112de7 | 12728 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12729 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12730 | |
66e985c0 | 12731 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12732 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 12733 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 12734 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12735 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12736 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12737 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12738 | |
cfb23ed6 | 12739 | return ret; |
0e8ffe1b DV |
12740 | } |
12741 | ||
e3b247da VS |
12742 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12743 | const struct intel_crtc_state *pipe_config) | |
12744 | { | |
12745 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12746 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12747 | &pipe_config->fdi_m_n); |
12748 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12749 | ||
12750 | /* | |
12751 | * FDI already provided one idea for the dotclock. | |
12752 | * Yell if the encoder disagrees. | |
12753 | */ | |
12754 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12755 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12756 | fdi_dotclock, dotclock); | |
12757 | } | |
12758 | } | |
12759 | ||
c0ead703 ML |
12760 | static void verify_wm_state(struct drm_crtc *crtc, |
12761 | struct drm_crtc_state *new_state) | |
08db6652 | 12762 | { |
e7c84544 | 12763 | struct drm_device *dev = crtc->dev; |
08db6652 DL |
12764 | struct drm_i915_private *dev_priv = dev->dev_private; |
12765 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
e7c84544 ML |
12766 | struct skl_ddb_entry *hw_entry, *sw_entry; |
12767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12768 | const enum pipe pipe = intel_crtc->pipe; | |
08db6652 DL |
12769 | int plane; |
12770 | ||
e7c84544 | 12771 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
12772 | return; |
12773 | ||
12774 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12775 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12776 | ||
e7c84544 ML |
12777 | /* planes */ |
12778 | for_each_plane(dev_priv, pipe, plane) { | |
12779 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
12780 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
08db6652 | 12781 | |
e7c84544 | 12782 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
08db6652 DL |
12783 | continue; |
12784 | ||
e7c84544 ML |
12785 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
12786 | "(expected (%u,%u), found (%u,%u))\n", | |
12787 | pipe_name(pipe), plane + 1, | |
12788 | sw_entry->start, sw_entry->end, | |
12789 | hw_entry->start, hw_entry->end); | |
12790 | } | |
08db6652 | 12791 | |
e7c84544 ML |
12792 | /* cursor */ |
12793 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
12794 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 | 12795 | |
e7c84544 | 12796 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
08db6652 DL |
12797 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
12798 | "(expected (%u,%u), found (%u,%u))\n", | |
12799 | pipe_name(pipe), | |
12800 | sw_entry->start, sw_entry->end, | |
12801 | hw_entry->start, hw_entry->end); | |
12802 | } | |
12803 | } | |
12804 | ||
91d1b4bd | 12805 | static void |
c0ead703 | 12806 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 12807 | { |
35dd3c64 | 12808 | struct drm_connector *connector; |
8af6cf88 | 12809 | |
e7c84544 | 12810 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
12811 | struct drm_encoder *encoder = connector->encoder; |
12812 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12813 | |
e7c84544 ML |
12814 | if (state->crtc != crtc) |
12815 | continue; | |
12816 | ||
c0ead703 | 12817 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 12818 | |
ad3c558f | 12819 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12820 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12821 | } |
91d1b4bd DV |
12822 | } |
12823 | ||
12824 | static void | |
c0ead703 | 12825 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
12826 | { |
12827 | struct intel_encoder *encoder; | |
12828 | struct intel_connector *connector; | |
8af6cf88 | 12829 | |
b2784e15 | 12830 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12831 | bool enabled = false; |
4d20cd86 | 12832 | enum pipe pipe; |
8af6cf88 DV |
12833 | |
12834 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12835 | encoder->base.base.id, | |
8e329a03 | 12836 | encoder->base.name); |
8af6cf88 | 12837 | |
3a3371ff | 12838 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12839 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12840 | continue; |
12841 | enabled = true; | |
ad3c558f ML |
12842 | |
12843 | I915_STATE_WARN(connector->base.state->crtc != | |
12844 | encoder->base.crtc, | |
12845 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12846 | } |
0e32b39c | 12847 | |
e2c719b7 | 12848 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12849 | "encoder's enabled state mismatch " |
12850 | "(expected %i, found %i)\n", | |
12851 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12852 | |
12853 | if (!encoder->base.crtc) { | |
4d20cd86 | 12854 | bool active; |
7c60d198 | 12855 | |
4d20cd86 ML |
12856 | active = encoder->get_hw_state(encoder, &pipe); |
12857 | I915_STATE_WARN(active, | |
12858 | "encoder detached but still enabled on pipe %c.\n", | |
12859 | pipe_name(pipe)); | |
7c60d198 | 12860 | } |
8af6cf88 | 12861 | } |
91d1b4bd DV |
12862 | } |
12863 | ||
12864 | static void | |
c0ead703 ML |
12865 | verify_crtc_state(struct drm_crtc *crtc, |
12866 | struct drm_crtc_state *old_crtc_state, | |
12867 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 12868 | { |
e7c84544 | 12869 | struct drm_device *dev = crtc->dev; |
fbee40df | 12870 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12871 | struct intel_encoder *encoder; |
e7c84544 ML |
12872 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12873 | struct intel_crtc_state *pipe_config, *sw_config; | |
12874 | struct drm_atomic_state *old_state; | |
12875 | bool active; | |
045ac3b5 | 12876 | |
e7c84544 ML |
12877 | old_state = old_crtc_state->state; |
12878 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); | |
12879 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12880 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12881 | pipe_config->base.crtc = crtc; | |
12882 | pipe_config->base.state = old_state; | |
8af6cf88 | 12883 | |
e7c84544 | 12884 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
8af6cf88 | 12885 | |
e7c84544 | 12886 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 12887 | |
e7c84544 ML |
12888 | /* hw state is inconsistent with the pipe quirk */ |
12889 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12890 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12891 | active = new_crtc_state->active; | |
6c49f241 | 12892 | |
e7c84544 ML |
12893 | I915_STATE_WARN(new_crtc_state->active != active, |
12894 | "crtc active state doesn't match with hw state " | |
12895 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 12896 | |
e7c84544 ML |
12897 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
12898 | "transitional active state does not match atomic hw state " | |
12899 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 12900 | |
e7c84544 ML |
12901 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
12902 | enum pipe pipe; | |
4d20cd86 | 12903 | |
e7c84544 ML |
12904 | active = encoder->get_hw_state(encoder, &pipe); |
12905 | I915_STATE_WARN(active != new_crtc_state->active, | |
12906 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12907 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 12908 | |
e7c84544 ML |
12909 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
12910 | "Encoder connected to wrong pipe %c\n", | |
12911 | pipe_name(pipe)); | |
4d20cd86 | 12912 | |
e7c84544 ML |
12913 | if (active) |
12914 | encoder->get_config(encoder, pipe_config); | |
12915 | } | |
53d9f4e9 | 12916 | |
e7c84544 ML |
12917 | if (!new_crtc_state->active) |
12918 | return; | |
cfb23ed6 | 12919 | |
e7c84544 | 12920 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 12921 | |
e7c84544 ML |
12922 | sw_config = to_intel_crtc_state(crtc->state); |
12923 | if (!intel_pipe_config_compare(dev, sw_config, | |
12924 | pipe_config, false)) { | |
12925 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
12926 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
12927 | "[hw state]"); | |
12928 | intel_dump_pipe_config(intel_crtc, sw_config, | |
12929 | "[sw state]"); | |
8af6cf88 DV |
12930 | } |
12931 | } | |
12932 | ||
91d1b4bd | 12933 | static void |
c0ead703 ML |
12934 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
12935 | struct intel_shared_dpll *pll, | |
12936 | struct drm_crtc *crtc, | |
12937 | struct drm_crtc_state *new_state) | |
91d1b4bd | 12938 | { |
91d1b4bd | 12939 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
12940 | unsigned crtc_mask; |
12941 | bool active; | |
5358901f | 12942 | |
e7c84544 | 12943 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 12944 | |
e7c84544 | 12945 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 12946 | |
e7c84544 | 12947 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12948 | |
e7c84544 ML |
12949 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
12950 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
12951 | "pll in active use but not on in sw tracking\n"); | |
12952 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12953 | "pll is on but not used by any active crtc\n"); | |
12954 | I915_STATE_WARN(pll->on != active, | |
12955 | "pll on state mismatch (expected %i, found %i)\n", | |
12956 | pll->on, active); | |
12957 | } | |
5358901f | 12958 | |
e7c84544 | 12959 | if (!crtc) { |
2dd66ebd | 12960 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
12961 | "more active pll users than references: %x vs %x\n", |
12962 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 12963 | |
e7c84544 ML |
12964 | return; |
12965 | } | |
12966 | ||
12967 | crtc_mask = 1 << drm_crtc_index(crtc); | |
12968 | ||
12969 | if (new_state->active) | |
12970 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
12971 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
12972 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
12973 | else | |
12974 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12975 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
12976 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 12977 | |
e7c84544 ML |
12978 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
12979 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
12980 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 12981 | |
e7c84544 ML |
12982 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
12983 | &dpll_hw_state, | |
12984 | sizeof(dpll_hw_state)), | |
12985 | "pll hw state mismatch\n"); | |
12986 | } | |
12987 | ||
12988 | static void | |
c0ead703 ML |
12989 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
12990 | struct drm_crtc_state *old_crtc_state, | |
12991 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 ML |
12992 | { |
12993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12994 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); | |
12995 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
12996 | ||
12997 | if (new_state->shared_dpll) | |
c0ead703 | 12998 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
12999 | |
13000 | if (old_state->shared_dpll && | |
13001 | old_state->shared_dpll != new_state->shared_dpll) { | |
13002 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13003 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13004 | ||
13005 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13006 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13007 | pipe_name(drm_crtc_index(crtc))); | |
13008 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13009 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13010 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13011 | } |
8af6cf88 DV |
13012 | } |
13013 | ||
e7c84544 | 13014 | static void |
c0ead703 | 13015 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13016 | struct drm_crtc_state *old_state, |
13017 | struct drm_crtc_state *new_state) | |
13018 | { | |
13019 | if (!needs_modeset(new_state) && | |
13020 | !to_intel_crtc_state(new_state)->update_pipe) | |
13021 | return; | |
13022 | ||
c0ead703 ML |
13023 | verify_wm_state(crtc, new_state); |
13024 | verify_connector_state(crtc->dev, crtc); | |
13025 | verify_crtc_state(crtc, old_state, new_state); | |
13026 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13027 | } |
13028 | ||
13029 | static void | |
c0ead703 | 13030 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 ML |
13031 | { |
13032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13033 | int i; | |
13034 | ||
13035 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13036 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13037 | } |
13038 | ||
13039 | static void | |
c0ead703 | 13040 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13041 | { |
c0ead703 ML |
13042 | verify_encoder_state(dev); |
13043 | verify_connector_state(dev, NULL); | |
13044 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13045 | } |
13046 | ||
80715b2f VS |
13047 | static void update_scanline_offset(struct intel_crtc *crtc) |
13048 | { | |
13049 | struct drm_device *dev = crtc->base.dev; | |
13050 | ||
13051 | /* | |
13052 | * The scanline counter increments at the leading edge of hsync. | |
13053 | * | |
13054 | * On most platforms it starts counting from vtotal-1 on the | |
13055 | * first active line. That means the scanline counter value is | |
13056 | * always one less than what we would expect. Ie. just after | |
13057 | * start of vblank, which also occurs at start of hsync (on the | |
13058 | * last active line), the scanline counter will read vblank_start-1. | |
13059 | * | |
13060 | * On gen2 the scanline counter starts counting from 1 instead | |
13061 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13062 | * to keep the value positive), instead of adding one. | |
13063 | * | |
13064 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13065 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13066 | * there's an extra 1 line difference. So we need to add two instead of | |
13067 | * one to the value. | |
13068 | */ | |
13069 | if (IS_GEN2(dev)) { | |
124abe07 | 13070 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13071 | int vtotal; |
13072 | ||
124abe07 VS |
13073 | vtotal = adjusted_mode->crtc_vtotal; |
13074 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13075 | vtotal /= 2; |
13076 | ||
13077 | crtc->scanline_offset = vtotal - 1; | |
13078 | } else if (HAS_DDI(dev) && | |
409ee761 | 13079 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13080 | crtc->scanline_offset = 2; |
13081 | } else | |
13082 | crtc->scanline_offset = 1; | |
13083 | } | |
13084 | ||
ad421372 | 13085 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13086 | { |
225da59b | 13087 | struct drm_device *dev = state->dev; |
ed6739ef | 13088 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13089 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13090 | struct drm_crtc *crtc; |
13091 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13092 | int i; |
ed6739ef ACO |
13093 | |
13094 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13095 | return; |
ed6739ef | 13096 | |
0a9ab303 | 13097 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13098 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13099 | struct intel_shared_dpll *old_dpll = |
13100 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13101 | |
fb1a38a9 | 13102 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13103 | continue; |
13104 | ||
8106ddbd | 13105 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13106 | |
8106ddbd | 13107 | if (!old_dpll) |
fb1a38a9 | 13108 | continue; |
0a9ab303 | 13109 | |
ad421372 ML |
13110 | if (!shared_dpll) |
13111 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13112 | |
8106ddbd | 13113 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13114 | } |
ed6739ef ACO |
13115 | } |
13116 | ||
99d736a2 ML |
13117 | /* |
13118 | * This implements the workaround described in the "notes" section of the mode | |
13119 | * set sequence documentation. When going from no pipes or single pipe to | |
13120 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13121 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13122 | */ | |
13123 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13124 | { | |
13125 | struct drm_crtc_state *crtc_state; | |
13126 | struct intel_crtc *intel_crtc; | |
13127 | struct drm_crtc *crtc; | |
13128 | struct intel_crtc_state *first_crtc_state = NULL; | |
13129 | struct intel_crtc_state *other_crtc_state = NULL; | |
13130 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13131 | int i; | |
13132 | ||
13133 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13134 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13135 | intel_crtc = to_intel_crtc(crtc); | |
13136 | ||
13137 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13138 | continue; | |
13139 | ||
13140 | if (first_crtc_state) { | |
13141 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13142 | break; | |
13143 | } else { | |
13144 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13145 | first_pipe = intel_crtc->pipe; | |
13146 | } | |
13147 | } | |
13148 | ||
13149 | /* No workaround needed? */ | |
13150 | if (!first_crtc_state) | |
13151 | return 0; | |
13152 | ||
13153 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13154 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13155 | struct intel_crtc_state *pipe_config; | |
13156 | ||
13157 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13158 | if (IS_ERR(pipe_config)) | |
13159 | return PTR_ERR(pipe_config); | |
13160 | ||
13161 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13162 | ||
13163 | if (!pipe_config->base.active || | |
13164 | needs_modeset(&pipe_config->base)) | |
13165 | continue; | |
13166 | ||
13167 | /* 2 or more enabled crtcs means no need for w/a */ | |
13168 | if (enabled_pipe != INVALID_PIPE) | |
13169 | return 0; | |
13170 | ||
13171 | enabled_pipe = intel_crtc->pipe; | |
13172 | } | |
13173 | ||
13174 | if (enabled_pipe != INVALID_PIPE) | |
13175 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13176 | else if (other_crtc_state) | |
13177 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13178 | ||
13179 | return 0; | |
13180 | } | |
13181 | ||
27c329ed ML |
13182 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13183 | { | |
13184 | struct drm_crtc *crtc; | |
13185 | struct drm_crtc_state *crtc_state; | |
13186 | int ret = 0; | |
13187 | ||
13188 | /* add all active pipes to the state */ | |
13189 | for_each_crtc(state->dev, crtc) { | |
13190 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13191 | if (IS_ERR(crtc_state)) | |
13192 | return PTR_ERR(crtc_state); | |
13193 | ||
13194 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13195 | continue; | |
13196 | ||
13197 | crtc_state->mode_changed = true; | |
13198 | ||
13199 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13200 | if (ret) | |
13201 | break; | |
13202 | ||
13203 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13204 | if (ret) | |
13205 | break; | |
13206 | } | |
13207 | ||
13208 | return ret; | |
13209 | } | |
13210 | ||
c347a676 | 13211 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13212 | { |
565602d7 ML |
13213 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13214 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13215 | struct drm_crtc *crtc; | |
13216 | struct drm_crtc_state *crtc_state; | |
13217 | int ret = 0, i; | |
054518dd | 13218 | |
b359283a ML |
13219 | if (!check_digital_port_conflicts(state)) { |
13220 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13221 | return -EINVAL; | |
13222 | } | |
13223 | ||
565602d7 ML |
13224 | intel_state->modeset = true; |
13225 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13226 | ||
13227 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13228 | if (crtc_state->active) | |
13229 | intel_state->active_crtcs |= 1 << i; | |
13230 | else | |
13231 | intel_state->active_crtcs &= ~(1 << i); | |
13232 | } | |
13233 | ||
054518dd ACO |
13234 | /* |
13235 | * See if the config requires any additional preparation, e.g. | |
13236 | * to adjust global state with pipes off. We need to do this | |
13237 | * here so we can get the modeset_pipe updated config for the new | |
13238 | * mode set on this crtc. For other crtcs we need to use the | |
13239 | * adjusted_mode bits in the crtc directly. | |
13240 | */ | |
27c329ed | 13241 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13242 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13243 | ||
1a617b77 | 13244 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13245 | ret = intel_modeset_all_pipes(state); |
13246 | ||
13247 | if (ret < 0) | |
054518dd | 13248 | return ret; |
e8788cbc ML |
13249 | |
13250 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13251 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13252 | } else |
1a617b77 | 13253 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13254 | |
ad421372 | 13255 | intel_modeset_clear_plls(state); |
054518dd | 13256 | |
565602d7 | 13257 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13258 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13259 | |
ad421372 | 13260 | return 0; |
c347a676 ACO |
13261 | } |
13262 | ||
aa363136 MR |
13263 | /* |
13264 | * Handle calculation of various watermark data at the end of the atomic check | |
13265 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13266 | * handlers to ensure that all derived state has been updated. | |
13267 | */ | |
13268 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13269 | { | |
13270 | struct drm_device *dev = state->dev; | |
13271 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13272 | struct drm_crtc *crtc; | |
13273 | struct drm_crtc_state *cstate; | |
13274 | struct drm_plane *plane; | |
13275 | struct drm_plane_state *pstate; | |
13276 | ||
13277 | /* | |
13278 | * Calculate watermark configuration details now that derived | |
13279 | * plane/crtc state is all properly updated. | |
13280 | */ | |
13281 | drm_for_each_crtc(crtc, dev) { | |
13282 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13283 | crtc->state; | |
13284 | ||
13285 | if (cstate->active) | |
13286 | intel_state->wm_config.num_pipes_active++; | |
13287 | } | |
13288 | drm_for_each_legacy_plane(plane, dev) { | |
13289 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13290 | plane->state; | |
13291 | ||
13292 | if (!to_intel_plane_state(pstate)->visible) | |
13293 | continue; | |
13294 | ||
13295 | intel_state->wm_config.sprites_enabled = true; | |
13296 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13297 | pstate->crtc_h != pstate->src_h >> 16) | |
13298 | intel_state->wm_config.sprites_scaled = true; | |
13299 | } | |
13300 | } | |
13301 | ||
74c090b1 ML |
13302 | /** |
13303 | * intel_atomic_check - validate state object | |
13304 | * @dev: drm device | |
13305 | * @state: state to validate | |
13306 | */ | |
13307 | static int intel_atomic_check(struct drm_device *dev, | |
13308 | struct drm_atomic_state *state) | |
c347a676 | 13309 | { |
dd8b3bdb | 13310 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13311 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13312 | struct drm_crtc *crtc; |
13313 | struct drm_crtc_state *crtc_state; | |
13314 | int ret, i; | |
61333b60 | 13315 | bool any_ms = false; |
c347a676 | 13316 | |
74c090b1 | 13317 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13318 | if (ret) |
13319 | return ret; | |
13320 | ||
c347a676 | 13321 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13322 | struct intel_crtc_state *pipe_config = |
13323 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13324 | |
13325 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13326 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13327 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13328 | |
61333b60 ML |
13329 | if (!crtc_state->enable) { |
13330 | if (needs_modeset(crtc_state)) | |
13331 | any_ms = true; | |
c347a676 | 13332 | continue; |
61333b60 | 13333 | } |
c347a676 | 13334 | |
26495481 | 13335 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13336 | continue; |
13337 | ||
26495481 DV |
13338 | /* FIXME: For only active_changed we shouldn't need to do any |
13339 | * state recomputation at all. */ | |
13340 | ||
1ed51de9 DV |
13341 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13342 | if (ret) | |
13343 | return ret; | |
b359283a | 13344 | |
cfb23ed6 | 13345 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13346 | if (ret) |
13347 | return ret; | |
13348 | ||
73831236 | 13349 | if (i915.fastboot && |
dd8b3bdb | 13350 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13351 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13352 | pipe_config, true)) { |
26495481 | 13353 | crtc_state->mode_changed = false; |
bfd16b2a | 13354 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13355 | } |
13356 | ||
13357 | if (needs_modeset(crtc_state)) { | |
13358 | any_ms = true; | |
cfb23ed6 ML |
13359 | |
13360 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13361 | if (ret) | |
13362 | return ret; | |
13363 | } | |
61333b60 | 13364 | |
26495481 DV |
13365 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13366 | needs_modeset(crtc_state) ? | |
13367 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13368 | } |
13369 | ||
61333b60 ML |
13370 | if (any_ms) { |
13371 | ret = intel_modeset_checks(state); | |
13372 | ||
13373 | if (ret) | |
13374 | return ret; | |
27c329ed | 13375 | } else |
dd8b3bdb | 13376 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13377 | |
dd8b3bdb | 13378 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13379 | if (ret) |
13380 | return ret; | |
13381 | ||
f51be2e0 | 13382 | intel_fbc_choose_crtc(dev_priv, state); |
aa363136 MR |
13383 | calc_watermark_data(state); |
13384 | ||
13385 | return 0; | |
054518dd ACO |
13386 | } |
13387 | ||
5008e874 ML |
13388 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13389 | struct drm_atomic_state *state, | |
13390 | bool async) | |
13391 | { | |
7580d774 ML |
13392 | struct drm_i915_private *dev_priv = dev->dev_private; |
13393 | struct drm_plane_state *plane_state; | |
5008e874 | 13394 | struct drm_crtc_state *crtc_state; |
7580d774 | 13395 | struct drm_plane *plane; |
5008e874 ML |
13396 | struct drm_crtc *crtc; |
13397 | int i, ret; | |
13398 | ||
13399 | if (async) { | |
13400 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13401 | return -EINVAL; | |
13402 | } | |
13403 | ||
13404 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13405 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13406 | if (ret) | |
13407 | return ret; | |
7580d774 ML |
13408 | |
13409 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13410 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13411 | } |
13412 | ||
f935675f ML |
13413 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13414 | if (ret) | |
13415 | return ret; | |
13416 | ||
5008e874 | 13417 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13418 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13419 | u32 reset_counter; | |
13420 | ||
13421 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13422 | mutex_unlock(&dev->struct_mutex); | |
13423 | ||
13424 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13425 | struct intel_plane_state *intel_plane_state = | |
13426 | to_intel_plane_state(plane_state); | |
13427 | ||
13428 | if (!intel_plane_state->wait_req) | |
13429 | continue; | |
13430 | ||
13431 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13432 | reset_counter, true, | |
13433 | NULL, NULL); | |
13434 | ||
13435 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13436 | if (ret == -EIO) | |
13437 | ret = 0; | |
13438 | ||
13439 | if (ret) | |
13440 | break; | |
13441 | } | |
13442 | ||
13443 | if (!ret) | |
13444 | return 0; | |
13445 | ||
13446 | mutex_lock(&dev->struct_mutex); | |
13447 | drm_atomic_helper_cleanup_planes(dev, state); | |
13448 | } | |
5008e874 | 13449 | |
f935675f | 13450 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13451 | return ret; |
13452 | } | |
13453 | ||
e8861675 ML |
13454 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13455 | struct drm_i915_private *dev_priv, | |
13456 | unsigned crtc_mask) | |
13457 | { | |
13458 | unsigned last_vblank_count[I915_MAX_PIPES]; | |
13459 | enum pipe pipe; | |
13460 | int ret; | |
13461 | ||
13462 | if (!crtc_mask) | |
13463 | return; | |
13464 | ||
13465 | for_each_pipe(dev_priv, pipe) { | |
13466 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13467 | ||
13468 | if (!((1 << pipe) & crtc_mask)) | |
13469 | continue; | |
13470 | ||
13471 | ret = drm_crtc_vblank_get(crtc); | |
13472 | if (WARN_ON(ret != 0)) { | |
13473 | crtc_mask &= ~(1 << pipe); | |
13474 | continue; | |
13475 | } | |
13476 | ||
13477 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); | |
13478 | } | |
13479 | ||
13480 | for_each_pipe(dev_priv, pipe) { | |
13481 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13482 | long lret; | |
13483 | ||
13484 | if (!((1 << pipe) & crtc_mask)) | |
13485 | continue; | |
13486 | ||
13487 | lret = wait_event_timeout(dev->vblank[pipe].queue, | |
13488 | last_vblank_count[pipe] != | |
13489 | drm_crtc_vblank_count(crtc), | |
13490 | msecs_to_jiffies(50)); | |
13491 | ||
13492 | WARN_ON(!lret); | |
13493 | ||
13494 | drm_crtc_vblank_put(crtc); | |
13495 | } | |
13496 | } | |
13497 | ||
13498 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) | |
13499 | { | |
13500 | /* fb updated, need to unpin old fb */ | |
13501 | if (crtc_state->fb_changed) | |
13502 | return true; | |
13503 | ||
13504 | /* wm changes, need vblank before final wm's */ | |
caed361d | 13505 | if (crtc_state->update_wm_post) |
e8861675 ML |
13506 | return true; |
13507 | ||
13508 | /* | |
13509 | * cxsr is re-enabled after vblank. | |
caed361d | 13510 | * This is already handled by crtc_state->update_wm_post, |
e8861675 ML |
13511 | * but added for clarity. |
13512 | */ | |
13513 | if (crtc_state->disable_cxsr) | |
13514 | return true; | |
13515 | ||
13516 | return false; | |
13517 | } | |
13518 | ||
74c090b1 ML |
13519 | /** |
13520 | * intel_atomic_commit - commit validated state object | |
13521 | * @dev: DRM device | |
13522 | * @state: the top-level driver state object | |
13523 | * @async: asynchronous commit | |
13524 | * | |
13525 | * This function commits a top-level state object that has been validated | |
13526 | * with drm_atomic_helper_check(). | |
13527 | * | |
13528 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13529 | * we can only handle plane-related operations and do not yet support | |
13530 | * asynchronous commit. | |
13531 | * | |
13532 | * RETURNS | |
13533 | * Zero for success or -errno. | |
13534 | */ | |
13535 | static int intel_atomic_commit(struct drm_device *dev, | |
13536 | struct drm_atomic_state *state, | |
13537 | bool async) | |
a6778b3c | 13538 | { |
565602d7 | 13539 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13540 | struct drm_i915_private *dev_priv = dev->dev_private; |
29ceb0e6 | 13541 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13542 | struct drm_crtc *crtc; |
ed4a6a7c | 13543 | struct intel_crtc_state *intel_cstate; |
565602d7 ML |
13544 | int ret = 0, i; |
13545 | bool hw_check = intel_state->modeset; | |
33c8df89 | 13546 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
e8861675 | 13547 | unsigned crtc_vblank_mask = 0; |
a6778b3c | 13548 | |
5008e874 | 13549 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13550 | if (ret) { |
13551 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13552 | return ret; |
7580d774 | 13553 | } |
d4afb8cc | 13554 | |
1c5e19f8 | 13555 | drm_atomic_helper_swap_state(dev, state); |
a1475e77 ML |
13556 | dev_priv->wm.config = intel_state->wm_config; |
13557 | intel_shared_dpll_commit(state); | |
1c5e19f8 | 13558 | |
565602d7 ML |
13559 | if (intel_state->modeset) { |
13560 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13561 | sizeof(intel_state->min_pixclk)); | |
13562 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13563 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
33c8df89 ML |
13564 | |
13565 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13566 | } |
13567 | ||
29ceb0e6 | 13568 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13569 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13570 | ||
33c8df89 ML |
13571 | if (needs_modeset(crtc->state) || |
13572 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13573 | hw_check = true; | |
13574 | ||
13575 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13576 | modeset_get_crtc_power_domains(crtc, | |
13577 | to_intel_crtc_state(crtc->state)); | |
13578 | } | |
13579 | ||
61333b60 ML |
13580 | if (!needs_modeset(crtc->state)) |
13581 | continue; | |
13582 | ||
29ceb0e6 | 13583 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13584 | |
29ceb0e6 VS |
13585 | if (old_crtc_state->active) { |
13586 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13587 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13588 | intel_crtc->active = false; |
58f9c0bc | 13589 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13590 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13591 | |
13592 | /* | |
13593 | * Underruns don't always raise | |
13594 | * interrupts, so check manually. | |
13595 | */ | |
13596 | intel_check_cpu_fifo_underruns(dev_priv); | |
13597 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13598 | |
13599 | if (!crtc->state->active) | |
13600 | intel_update_watermarks(crtc); | |
a539205a | 13601 | } |
b8cecdf5 | 13602 | } |
7758a113 | 13603 | |
ea9d758d DV |
13604 | /* Only after disabling all output pipelines that will be changed can we |
13605 | * update the the output configuration. */ | |
4740b0f2 | 13606 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13607 | |
565602d7 | 13608 | if (intel_state->modeset) { |
4740b0f2 | 13609 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13610 | |
13611 | if (dev_priv->display.modeset_commit_cdclk && | |
13612 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13613 | dev_priv->display.modeset_commit_cdclk(state); | |
f6d1973d | 13614 | |
c0ead703 | 13615 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 13616 | } |
47fab737 | 13617 | |
a6778b3c | 13618 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13619 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13620 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13621 | bool modeset = needs_modeset(crtc->state); | |
e8861675 ML |
13622 | struct intel_crtc_state *pipe_config = |
13623 | to_intel_crtc_state(crtc->state); | |
13624 | bool update_pipe = !modeset && pipe_config->update_pipe; | |
9f836f90 | 13625 | |
f6ac4b2a | 13626 | if (modeset && crtc->state->active) { |
a539205a ML |
13627 | update_scanline_offset(to_intel_crtc(crtc)); |
13628 | dev_priv->display.crtc_enable(crtc); | |
13629 | } | |
80715b2f | 13630 | |
f6ac4b2a | 13631 | if (!modeset) |
29ceb0e6 | 13632 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13633 | |
31ae71fc ML |
13634 | if (crtc->state->active && |
13635 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
49227c4a PZ |
13636 | intel_fbc_enable(intel_crtc); |
13637 | ||
6173ee28 ML |
13638 | if (crtc->state->active && |
13639 | (crtc->state->planes_changed || update_pipe)) | |
29ceb0e6 | 13640 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
bfd16b2a | 13641 | |
e8861675 ML |
13642 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13643 | crtc_vblank_mask |= 1 << i; | |
80715b2f | 13644 | } |
a6778b3c | 13645 | |
a6778b3c | 13646 | /* FIXME: add subpixel order */ |
83a57153 | 13647 | |
e8861675 ML |
13648 | if (!state->legacy_cursor_update) |
13649 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
f935675f | 13650 | |
ed4a6a7c MR |
13651 | /* |
13652 | * Now that the vblank has passed, we can go ahead and program the | |
13653 | * optimal watermarks on platforms that need two-step watermark | |
13654 | * programming. | |
13655 | * | |
13656 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13657 | */ | |
29ceb0e6 | 13658 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
ed4a6a7c MR |
13659 | intel_cstate = to_intel_crtc_state(crtc->state); |
13660 | ||
13661 | if (dev_priv->display.optimize_watermarks) | |
13662 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13663 | } | |
13664 | ||
177246a8 MR |
13665 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
13666 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13667 | ||
13668 | if (put_domains[i]) | |
13669 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
f6d1973d | 13670 | |
c0ead703 | 13671 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); |
177246a8 MR |
13672 | } |
13673 | ||
13674 | if (intel_state->modeset) | |
13675 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13676 | ||
f935675f | 13677 | mutex_lock(&dev->struct_mutex); |
d4afb8cc | 13678 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13679 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13680 | |
ee165b1a | 13681 | drm_atomic_state_free(state); |
f30da187 | 13682 | |
75714940 MK |
13683 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13684 | * of triggering bugs in unclaimed access. After we finish | |
13685 | * modesetting, see if an error has been flagged, and if so | |
13686 | * enable debugging for the next modeset - and hope we catch | |
13687 | * the culprit. | |
13688 | * | |
13689 | * XXX note that we assume display power is on at this point. | |
13690 | * This might hold true now but we need to add pm helper to check | |
13691 | * unclaimed only when the hardware is on, as atomic commits | |
13692 | * can happen also when the device is completely off. | |
13693 | */ | |
13694 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13695 | ||
74c090b1 | 13696 | return 0; |
7f27126e JB |
13697 | } |
13698 | ||
c0c36b94 CW |
13699 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13700 | { | |
83a57153 ACO |
13701 | struct drm_device *dev = crtc->dev; |
13702 | struct drm_atomic_state *state; | |
e694eb02 | 13703 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13704 | int ret; |
83a57153 ACO |
13705 | |
13706 | state = drm_atomic_state_alloc(dev); | |
13707 | if (!state) { | |
e694eb02 | 13708 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13709 | crtc->base.id); |
13710 | return; | |
13711 | } | |
13712 | ||
e694eb02 | 13713 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13714 | |
e694eb02 ML |
13715 | retry: |
13716 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13717 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13718 | if (!ret) { | |
13719 | if (!crtc_state->active) | |
13720 | goto out; | |
83a57153 | 13721 | |
e694eb02 | 13722 | crtc_state->mode_changed = true; |
74c090b1 | 13723 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13724 | } |
13725 | ||
e694eb02 ML |
13726 | if (ret == -EDEADLK) { |
13727 | drm_atomic_state_clear(state); | |
13728 | drm_modeset_backoff(state->acquire_ctx); | |
13729 | goto retry; | |
4ed9fb37 | 13730 | } |
4be07317 | 13731 | |
2bfb4627 | 13732 | if (ret) |
e694eb02 | 13733 | out: |
2bfb4627 | 13734 | drm_atomic_state_free(state); |
c0c36b94 CW |
13735 | } |
13736 | ||
25c5b266 DV |
13737 | #undef for_each_intel_crtc_masked |
13738 | ||
f6e5b160 | 13739 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
82cf435b | 13740 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 13741 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13742 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 CW |
13743 | .destroy = intel_crtc_destroy, |
13744 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13745 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13746 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13747 | }; |
13748 | ||
6beb8c23 MR |
13749 | /** |
13750 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13751 | * @plane: drm plane to prepare for | |
13752 | * @fb: framebuffer to prepare for presentation | |
13753 | * | |
13754 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13755 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13756 | * bits. Some older platforms need special physical address handling for | |
13757 | * cursor planes. | |
13758 | * | |
f935675f ML |
13759 | * Must be called with struct_mutex held. |
13760 | * | |
6beb8c23 MR |
13761 | * Returns 0 on success, negative error code on failure. |
13762 | */ | |
13763 | int | |
13764 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13765 | const struct drm_plane_state *new_state) |
465c120c MR |
13766 | { |
13767 | struct drm_device *dev = plane->dev; | |
844f9111 | 13768 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13769 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13770 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13771 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13772 | int ret = 0; |
465c120c | 13773 | |
1ee49399 | 13774 | if (!obj && !old_obj) |
465c120c MR |
13775 | return 0; |
13776 | ||
5008e874 ML |
13777 | if (old_obj) { |
13778 | struct drm_crtc_state *crtc_state = | |
13779 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13780 | ||
13781 | /* Big Hammer, we also need to ensure that any pending | |
13782 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13783 | * current scanout is retired before unpinning the old | |
13784 | * framebuffer. Note that we rely on userspace rendering | |
13785 | * into the buffer attached to the pipe they are waiting | |
13786 | * on. If not, userspace generates a GPU hang with IPEHR | |
13787 | * point to the MI_WAIT_FOR_EVENT. | |
13788 | * | |
13789 | * This should only fail upon a hung GPU, in which case we | |
13790 | * can safely continue. | |
13791 | */ | |
13792 | if (needs_modeset(crtc_state)) | |
13793 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13794 | ||
13795 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13796 | if (ret && ret != -EIO) | |
f935675f | 13797 | return ret; |
5008e874 ML |
13798 | } |
13799 | ||
3c28ff22 AG |
13800 | /* For framebuffer backed by dmabuf, wait for fence */ |
13801 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13802 | long lret; |
13803 | ||
13804 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13805 | false, true, | |
13806 | MAX_SCHEDULE_TIMEOUT); | |
13807 | if (lret == -ERESTARTSYS) | |
13808 | return lret; | |
3c28ff22 | 13809 | |
bcf8be27 | 13810 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13811 | } |
13812 | ||
1ee49399 ML |
13813 | if (!obj) { |
13814 | ret = 0; | |
13815 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13816 | INTEL_INFO(dev)->cursor_needs_physical) { |
13817 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13818 | ret = i915_gem_object_attach_phys(obj, align); | |
13819 | if (ret) | |
13820 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13821 | } else { | |
3465c580 | 13822 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 13823 | } |
465c120c | 13824 | |
7580d774 ML |
13825 | if (ret == 0) { |
13826 | if (obj) { | |
13827 | struct intel_plane_state *plane_state = | |
13828 | to_intel_plane_state(new_state); | |
13829 | ||
13830 | i915_gem_request_assign(&plane_state->wait_req, | |
13831 | obj->last_write_req); | |
13832 | } | |
13833 | ||
a9ff8714 | 13834 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13835 | } |
fdd508a6 | 13836 | |
6beb8c23 MR |
13837 | return ret; |
13838 | } | |
13839 | ||
38f3ce3a MR |
13840 | /** |
13841 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13842 | * @plane: drm plane to clean up for | |
13843 | * @fb: old framebuffer that was on plane | |
13844 | * | |
13845 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13846 | * |
13847 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13848 | */ |
13849 | void | |
13850 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13851 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13852 | { |
13853 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13854 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13855 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13856 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13857 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13858 | |
7580d774 ML |
13859 | old_intel_state = to_intel_plane_state(old_state); |
13860 | ||
1ee49399 | 13861 | if (!obj && !old_obj) |
38f3ce3a MR |
13862 | return; |
13863 | ||
1ee49399 ML |
13864 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13865 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 13866 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 ML |
13867 | |
13868 | /* prepare_fb aborted? */ | |
13869 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13870 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13871 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13872 | |
13873 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
465c120c MR |
13874 | } |
13875 | ||
6156a456 CK |
13876 | int |
13877 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13878 | { | |
13879 | int max_scale; | |
13880 | struct drm_device *dev; | |
13881 | struct drm_i915_private *dev_priv; | |
13882 | int crtc_clock, cdclk; | |
13883 | ||
bf8a0af0 | 13884 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13885 | return DRM_PLANE_HELPER_NO_SCALING; |
13886 | ||
13887 | dev = intel_crtc->base.dev; | |
13888 | dev_priv = dev->dev_private; | |
13889 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13890 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13891 | |
54bf1ce6 | 13892 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13893 | return DRM_PLANE_HELPER_NO_SCALING; |
13894 | ||
13895 | /* | |
13896 | * skl max scale is lower of: | |
13897 | * close to 3 but not 3, -1 is for that purpose | |
13898 | * or | |
13899 | * cdclk/crtc_clock | |
13900 | */ | |
13901 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13902 | ||
13903 | return max_scale; | |
13904 | } | |
13905 | ||
465c120c | 13906 | static int |
3c692a41 | 13907 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13908 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13909 | struct intel_plane_state *state) |
13910 | { | |
2b875c22 MR |
13911 | struct drm_crtc *crtc = state->base.crtc; |
13912 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13913 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13914 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13915 | bool can_position = false; | |
465c120c | 13916 | |
693bdc28 VS |
13917 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
13918 | /* use scaler when colorkey is not required */ | |
13919 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13920 | min_scale = 1; | |
13921 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13922 | } | |
d8106366 | 13923 | can_position = true; |
6156a456 | 13924 | } |
d8106366 | 13925 | |
061e4b8d ML |
13926 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13927 | &state->dst, &state->clip, | |
da20eabd ML |
13928 | min_scale, max_scale, |
13929 | can_position, true, | |
13930 | &state->visible); | |
14af293f GP |
13931 | } |
13932 | ||
613d2b27 ML |
13933 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13934 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13935 | { |
32b7eeec | 13936 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13937 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13938 | struct intel_crtc_state *old_intel_state = |
13939 | to_intel_crtc_state(old_crtc_state); | |
13940 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13941 | |
c34c9ee4 | 13942 | /* Perform vblank evasion around commit operation */ |
62852622 | 13943 | intel_pipe_update_start(intel_crtc); |
0583236e | 13944 | |
bfd16b2a ML |
13945 | if (modeset) |
13946 | return; | |
13947 | ||
20a34e78 ML |
13948 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { |
13949 | intel_color_set_csc(crtc->state); | |
13950 | intel_color_load_luts(crtc->state); | |
13951 | } | |
13952 | ||
bfd16b2a ML |
13953 | if (to_intel_crtc_state(crtc->state)->update_pipe) |
13954 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13955 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13956 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13957 | } |
13958 | ||
613d2b27 ML |
13959 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13960 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13961 | { |
32b7eeec | 13962 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13963 | |
62852622 | 13964 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13965 | } |
13966 | ||
cf4c7c12 | 13967 | /** |
4a3b8769 MR |
13968 | * intel_plane_destroy - destroy a plane |
13969 | * @plane: plane to destroy | |
cf4c7c12 | 13970 | * |
4a3b8769 MR |
13971 | * Common destruction function for all types of planes (primary, cursor, |
13972 | * sprite). | |
cf4c7c12 | 13973 | */ |
4a3b8769 | 13974 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13975 | { |
13976 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13977 | drm_plane_cleanup(plane); | |
13978 | kfree(intel_plane); | |
13979 | } | |
13980 | ||
65a3fea0 | 13981 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13982 | .update_plane = drm_atomic_helper_update_plane, |
13983 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13984 | .destroy = intel_plane_destroy, |
c196e1d6 | 13985 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13986 | .atomic_get_property = intel_plane_atomic_get_property, |
13987 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13988 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13989 | .atomic_destroy_state = intel_plane_destroy_state, | |
13990 | ||
465c120c MR |
13991 | }; |
13992 | ||
13993 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13994 | int pipe) | |
13995 | { | |
fca0ce2a VS |
13996 | struct intel_plane *primary = NULL; |
13997 | struct intel_plane_state *state = NULL; | |
465c120c | 13998 | const uint32_t *intel_primary_formats; |
45e3743a | 13999 | unsigned int num_formats; |
fca0ce2a | 14000 | int ret; |
465c120c MR |
14001 | |
14002 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
fca0ce2a VS |
14003 | if (!primary) |
14004 | goto fail; | |
465c120c | 14005 | |
8e7d688b | 14006 | state = intel_create_plane_state(&primary->base); |
fca0ce2a VS |
14007 | if (!state) |
14008 | goto fail; | |
8e7d688b | 14009 | primary->base.state = &state->base; |
ea2c67bb | 14010 | |
465c120c MR |
14011 | primary->can_scale = false; |
14012 | primary->max_downscale = 1; | |
6156a456 CK |
14013 | if (INTEL_INFO(dev)->gen >= 9) { |
14014 | primary->can_scale = true; | |
af99ceda | 14015 | state->scaler_id = -1; |
6156a456 | 14016 | } |
465c120c MR |
14017 | primary->pipe = pipe; |
14018 | primary->plane = pipe; | |
a9ff8714 | 14019 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14020 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14021 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14022 | primary->plane = !pipe; | |
14023 | ||
6c0fd451 DL |
14024 | if (INTEL_INFO(dev)->gen >= 9) { |
14025 | intel_primary_formats = skl_primary_formats; | |
14026 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14027 | |
14028 | primary->update_plane = skylake_update_primary_plane; | |
14029 | primary->disable_plane = skylake_disable_primary_plane; | |
14030 | } else if (HAS_PCH_SPLIT(dev)) { | |
14031 | intel_primary_formats = i965_primary_formats; | |
14032 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14033 | ||
14034 | primary->update_plane = ironlake_update_primary_plane; | |
14035 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14036 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14037 | intel_primary_formats = i965_primary_formats; |
14038 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14039 | |
14040 | primary->update_plane = i9xx_update_primary_plane; | |
14041 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14042 | } else { |
14043 | intel_primary_formats = i8xx_primary_formats; | |
14044 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14045 | |
14046 | primary->update_plane = i9xx_update_primary_plane; | |
14047 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14048 | } |
14049 | ||
fca0ce2a VS |
14050 | ret = drm_universal_plane_init(dev, &primary->base, 0, |
14051 | &intel_plane_funcs, | |
14052 | intel_primary_formats, num_formats, | |
14053 | DRM_PLANE_TYPE_PRIMARY, NULL); | |
14054 | if (ret) | |
14055 | goto fail; | |
48404c1e | 14056 | |
3b7a5119 SJ |
14057 | if (INTEL_INFO(dev)->gen >= 4) |
14058 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14059 | |
ea2c67bb MR |
14060 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14061 | ||
465c120c | 14062 | return &primary->base; |
fca0ce2a VS |
14063 | |
14064 | fail: | |
14065 | kfree(state); | |
14066 | kfree(primary); | |
14067 | ||
14068 | return NULL; | |
465c120c MR |
14069 | } |
14070 | ||
3b7a5119 SJ |
14071 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14072 | { | |
14073 | if (!dev->mode_config.rotation_property) { | |
14074 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14075 | BIT(DRM_ROTATE_180); | |
14076 | ||
14077 | if (INTEL_INFO(dev)->gen >= 9) | |
14078 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14079 | ||
14080 | dev->mode_config.rotation_property = | |
14081 | drm_mode_create_rotation_property(dev, flags); | |
14082 | } | |
14083 | if (dev->mode_config.rotation_property) | |
14084 | drm_object_attach_property(&plane->base.base, | |
14085 | dev->mode_config.rotation_property, | |
14086 | plane->base.state->rotation); | |
14087 | } | |
14088 | ||
3d7d6510 | 14089 | static int |
852e787c | 14090 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14091 | struct intel_crtc_state *crtc_state, |
852e787c | 14092 | struct intel_plane_state *state) |
3d7d6510 | 14093 | { |
061e4b8d | 14094 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14095 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14096 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14097 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14098 | unsigned stride; |
14099 | int ret; | |
3d7d6510 | 14100 | |
061e4b8d ML |
14101 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14102 | &state->dst, &state->clip, | |
3d7d6510 MR |
14103 | DRM_PLANE_HELPER_NO_SCALING, |
14104 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14105 | true, true, &state->visible); |
757f9a3e GP |
14106 | if (ret) |
14107 | return ret; | |
14108 | ||
757f9a3e GP |
14109 | /* if we want to turn off the cursor ignore width and height */ |
14110 | if (!obj) | |
da20eabd | 14111 | return 0; |
757f9a3e | 14112 | |
757f9a3e | 14113 | /* Check for which cursor types we support */ |
061e4b8d | 14114 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14115 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14116 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14117 | return -EINVAL; |
14118 | } | |
14119 | ||
ea2c67bb MR |
14120 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14121 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14122 | DRM_DEBUG_KMS("buffer is too small\n"); |
14123 | return -ENOMEM; | |
14124 | } | |
14125 | ||
3a656b54 | 14126 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14127 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14128 | return -EINVAL; |
32b7eeec MR |
14129 | } |
14130 | ||
b29ec92c VS |
14131 | /* |
14132 | * There's something wrong with the cursor on CHV pipe C. | |
14133 | * If it straddles the left edge of the screen then | |
14134 | * moving it away from the edge or disabling it often | |
14135 | * results in a pipe underrun, and often that can lead to | |
14136 | * dead pipe (constant underrun reported, and it scans | |
14137 | * out just a solid color). To recover from that, the | |
14138 | * display power well must be turned off and on again. | |
14139 | * Refuse the put the cursor into that compromised position. | |
14140 | */ | |
14141 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14142 | state->visible && state->base.crtc_x < 0) { | |
14143 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14144 | return -EINVAL; | |
14145 | } | |
14146 | ||
da20eabd | 14147 | return 0; |
852e787c | 14148 | } |
3d7d6510 | 14149 | |
a8ad0d8e ML |
14150 | static void |
14151 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14152 | struct drm_crtc *crtc) |
a8ad0d8e | 14153 | { |
f2858021 ML |
14154 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14155 | ||
14156 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14157 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14158 | } |
14159 | ||
f4a2cf29 | 14160 | static void |
55a08b3f ML |
14161 | intel_update_cursor_plane(struct drm_plane *plane, |
14162 | const struct intel_crtc_state *crtc_state, | |
14163 | const struct intel_plane_state *state) | |
852e787c | 14164 | { |
55a08b3f ML |
14165 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14166 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14167 | struct drm_device *dev = plane->dev; |
2b875c22 | 14168 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14169 | uint32_t addr; |
852e787c | 14170 | |
f4a2cf29 | 14171 | if (!obj) |
a912f12f | 14172 | addr = 0; |
f4a2cf29 | 14173 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14174 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14175 | else |
a912f12f | 14176 | addr = obj->phys_handle->busaddr; |
852e787c | 14177 | |
a912f12f | 14178 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14179 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14180 | } |
14181 | ||
3d7d6510 MR |
14182 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14183 | int pipe) | |
14184 | { | |
fca0ce2a VS |
14185 | struct intel_plane *cursor = NULL; |
14186 | struct intel_plane_state *state = NULL; | |
14187 | int ret; | |
3d7d6510 MR |
14188 | |
14189 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
fca0ce2a VS |
14190 | if (!cursor) |
14191 | goto fail; | |
3d7d6510 | 14192 | |
8e7d688b | 14193 | state = intel_create_plane_state(&cursor->base); |
fca0ce2a VS |
14194 | if (!state) |
14195 | goto fail; | |
8e7d688b | 14196 | cursor->base.state = &state->base; |
ea2c67bb | 14197 | |
3d7d6510 MR |
14198 | cursor->can_scale = false; |
14199 | cursor->max_downscale = 1; | |
14200 | cursor->pipe = pipe; | |
14201 | cursor->plane = pipe; | |
a9ff8714 | 14202 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14203 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14204 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14205 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 14206 | |
fca0ce2a VS |
14207 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
14208 | &intel_plane_funcs, | |
14209 | intel_cursor_formats, | |
14210 | ARRAY_SIZE(intel_cursor_formats), | |
14211 | DRM_PLANE_TYPE_CURSOR, NULL); | |
14212 | if (ret) | |
14213 | goto fail; | |
4398ad45 VS |
14214 | |
14215 | if (INTEL_INFO(dev)->gen >= 4) { | |
14216 | if (!dev->mode_config.rotation_property) | |
14217 | dev->mode_config.rotation_property = | |
14218 | drm_mode_create_rotation_property(dev, | |
14219 | BIT(DRM_ROTATE_0) | | |
14220 | BIT(DRM_ROTATE_180)); | |
14221 | if (dev->mode_config.rotation_property) | |
14222 | drm_object_attach_property(&cursor->base.base, | |
14223 | dev->mode_config.rotation_property, | |
8e7d688b | 14224 | state->base.rotation); |
4398ad45 VS |
14225 | } |
14226 | ||
af99ceda CK |
14227 | if (INTEL_INFO(dev)->gen >=9) |
14228 | state->scaler_id = -1; | |
14229 | ||
ea2c67bb MR |
14230 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14231 | ||
3d7d6510 | 14232 | return &cursor->base; |
fca0ce2a VS |
14233 | |
14234 | fail: | |
14235 | kfree(state); | |
14236 | kfree(cursor); | |
14237 | ||
14238 | return NULL; | |
3d7d6510 MR |
14239 | } |
14240 | ||
549e2bfb CK |
14241 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14242 | struct intel_crtc_state *crtc_state) | |
14243 | { | |
14244 | int i; | |
14245 | struct intel_scaler *intel_scaler; | |
14246 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14247 | ||
14248 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14249 | intel_scaler = &scaler_state->scalers[i]; | |
14250 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14251 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14252 | } | |
14253 | ||
14254 | scaler_state->scaler_id = -1; | |
14255 | } | |
14256 | ||
b358d0a6 | 14257 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14258 | { |
fbee40df | 14259 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14260 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14261 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14262 | struct drm_plane *primary = NULL; |
14263 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14264 | int ret; |
79e53945 | 14265 | |
955382f3 | 14266 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14267 | if (intel_crtc == NULL) |
14268 | return; | |
14269 | ||
f5de6e07 ACO |
14270 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14271 | if (!crtc_state) | |
14272 | goto fail; | |
550acefd ACO |
14273 | intel_crtc->config = crtc_state; |
14274 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14275 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14276 | |
549e2bfb CK |
14277 | /* initialize shared scalers */ |
14278 | if (INTEL_INFO(dev)->gen >= 9) { | |
14279 | if (pipe == PIPE_C) | |
14280 | intel_crtc->num_scalers = 1; | |
14281 | else | |
14282 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14283 | ||
14284 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14285 | } | |
14286 | ||
465c120c | 14287 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14288 | if (!primary) |
14289 | goto fail; | |
14290 | ||
14291 | cursor = intel_cursor_plane_create(dev, pipe); | |
14292 | if (!cursor) | |
14293 | goto fail; | |
14294 | ||
465c120c | 14295 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14296 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14297 | if (ret) |
14298 | goto fail; | |
79e53945 | 14299 | |
1f1c2e24 VS |
14300 | /* |
14301 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14302 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14303 | */ |
80824003 JB |
14304 | intel_crtc->pipe = pipe; |
14305 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14306 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14307 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14308 | intel_crtc->plane = !pipe; |
80824003 JB |
14309 | } |
14310 | ||
4b0e333e CW |
14311 | intel_crtc->cursor_base = ~0; |
14312 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14313 | intel_crtc->cursor_size = ~0; |
8d7849db | 14314 | |
852eb00d VS |
14315 | intel_crtc->wm.cxsr_allowed = true; |
14316 | ||
22fd0fab JB |
14317 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14318 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14319 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14320 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14321 | ||
79e53945 | 14322 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14323 | |
8563b1e8 LL |
14324 | intel_color_init(&intel_crtc->base); |
14325 | ||
87b6b101 | 14326 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14327 | return; |
14328 | ||
14329 | fail: | |
14330 | if (primary) | |
14331 | drm_plane_cleanup(primary); | |
14332 | if (cursor) | |
14333 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14334 | kfree(crtc_state); |
3d7d6510 | 14335 | kfree(intel_crtc); |
79e53945 JB |
14336 | } |
14337 | ||
752aa88a JB |
14338 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14339 | { | |
14340 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14341 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14342 | |
51fd371b | 14343 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14344 | |
d3babd3f | 14345 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14346 | return INVALID_PIPE; |
14347 | ||
14348 | return to_intel_crtc(encoder->crtc)->pipe; | |
14349 | } | |
14350 | ||
08d7b3d1 | 14351 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14352 | struct drm_file *file) |
08d7b3d1 | 14353 | { |
08d7b3d1 | 14354 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14355 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14356 | struct intel_crtc *crtc; |
08d7b3d1 | 14357 | |
7707e653 | 14358 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14359 | |
7707e653 | 14360 | if (!drmmode_crtc) { |
08d7b3d1 | 14361 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14362 | return -ENOENT; |
08d7b3d1 CW |
14363 | } |
14364 | ||
7707e653 | 14365 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14366 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14367 | |
c05422d5 | 14368 | return 0; |
08d7b3d1 CW |
14369 | } |
14370 | ||
66a9278e | 14371 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14372 | { |
66a9278e DV |
14373 | struct drm_device *dev = encoder->base.dev; |
14374 | struct intel_encoder *source_encoder; | |
79e53945 | 14375 | int index_mask = 0; |
79e53945 JB |
14376 | int entry = 0; |
14377 | ||
b2784e15 | 14378 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14379 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14380 | index_mask |= (1 << entry); |
14381 | ||
79e53945 JB |
14382 | entry++; |
14383 | } | |
4ef69c7a | 14384 | |
79e53945 JB |
14385 | return index_mask; |
14386 | } | |
14387 | ||
4d302442 CW |
14388 | static bool has_edp_a(struct drm_device *dev) |
14389 | { | |
14390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14391 | ||
14392 | if (!IS_MOBILE(dev)) | |
14393 | return false; | |
14394 | ||
14395 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14396 | return false; | |
14397 | ||
e3589908 | 14398 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14399 | return false; |
14400 | ||
14401 | return true; | |
14402 | } | |
14403 | ||
84b4e042 JB |
14404 | static bool intel_crt_present(struct drm_device *dev) |
14405 | { | |
14406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14407 | ||
884497ed DL |
14408 | if (INTEL_INFO(dev)->gen >= 9) |
14409 | return false; | |
14410 | ||
cf404ce4 | 14411 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14412 | return false; |
14413 | ||
14414 | if (IS_CHERRYVIEW(dev)) | |
14415 | return false; | |
14416 | ||
65e472e4 VS |
14417 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14418 | return false; | |
14419 | ||
70ac54d0 VS |
14420 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14421 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14422 | return false; | |
14423 | ||
e4abb733 | 14424 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14425 | return false; |
14426 | ||
14427 | return true; | |
14428 | } | |
14429 | ||
79e53945 JB |
14430 | static void intel_setup_outputs(struct drm_device *dev) |
14431 | { | |
725e30ad | 14432 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14433 | struct intel_encoder *encoder; |
cb0953d7 | 14434 | bool dpd_is_edp = false; |
79e53945 | 14435 | |
c9093354 | 14436 | intel_lvds_init(dev); |
79e53945 | 14437 | |
84b4e042 | 14438 | if (intel_crt_present(dev)) |
79935fca | 14439 | intel_crt_init(dev); |
cb0953d7 | 14440 | |
c776eb2e VK |
14441 | if (IS_BROXTON(dev)) { |
14442 | /* | |
14443 | * FIXME: Broxton doesn't support port detection via the | |
14444 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14445 | * detect the ports. | |
14446 | */ | |
14447 | intel_ddi_init(dev, PORT_A); | |
14448 | intel_ddi_init(dev, PORT_B); | |
14449 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
14450 | |
14451 | intel_dsi_init(dev); | |
c776eb2e | 14452 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
14453 | int found; |
14454 | ||
de31facd JB |
14455 | /* |
14456 | * Haswell uses DDI functions to detect digital outputs. | |
14457 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14458 | * it's there. | |
14459 | */ | |
77179400 | 14460 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14461 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14462 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14463 | intel_ddi_init(dev, PORT_A); |
14464 | ||
14465 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14466 | * register */ | |
14467 | found = I915_READ(SFUSE_STRAP); | |
14468 | ||
14469 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14470 | intel_ddi_init(dev, PORT_B); | |
14471 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14472 | intel_ddi_init(dev, PORT_C); | |
14473 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14474 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14475 | /* |
14476 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14477 | */ | |
ef11bdb3 | 14478 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14479 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14480 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14481 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14482 | intel_ddi_init(dev, PORT_E); | |
14483 | ||
0e72a5b5 | 14484 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14485 | int found; |
5d8a7752 | 14486 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14487 | |
14488 | if (has_edp_a(dev)) | |
14489 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14490 | |
dc0fa718 | 14491 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14492 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14493 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14494 | if (!found) |
e2debe91 | 14495 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14496 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14497 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14498 | } |
14499 | ||
dc0fa718 | 14500 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14501 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14502 | |
dc0fa718 | 14503 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14504 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14505 | |
5eb08b69 | 14506 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14507 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14508 | |
270b3042 | 14509 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14510 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14511 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14512 | /* |
14513 | * The DP_DETECTED bit is the latched state of the DDC | |
14514 | * SDA pin at boot. However since eDP doesn't require DDC | |
14515 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14516 | * eDP ports may have been muxed to an alternate function. | |
14517 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14518 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14519 | * detect eDP ports. | |
14520 | */ | |
e66eb81d | 14521 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14522 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14523 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14524 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14525 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14526 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14527 | |
e66eb81d | 14528 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14529 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14530 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14531 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14532 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14533 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14534 | |
9418c1f1 | 14535 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14536 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14537 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14538 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14539 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14540 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14541 | } |
14542 | ||
3cfca973 | 14543 | intel_dsi_init(dev); |
09da55dc | 14544 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14545 | bool found = false; |
7d57382e | 14546 | |
e2debe91 | 14547 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14548 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14549 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14550 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14551 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14552 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14553 | } |
27185ae1 | 14554 | |
3fec3d2f | 14555 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14556 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14557 | } |
13520b05 KH |
14558 | |
14559 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14560 | |
e2debe91 | 14561 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14562 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14563 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14564 | } |
27185ae1 | 14565 | |
e2debe91 | 14566 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14567 | |
3fec3d2f | 14568 | if (IS_G4X(dev)) { |
b01f2c3a | 14569 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14570 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14571 | } |
3fec3d2f | 14572 | if (IS_G4X(dev)) |
ab9d7c30 | 14573 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14574 | } |
27185ae1 | 14575 | |
3fec3d2f | 14576 | if (IS_G4X(dev) && |
e7281eab | 14577 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14578 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14579 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14580 | intel_dvo_init(dev); |
14581 | ||
103a196f | 14582 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14583 | intel_tv_init(dev); |
14584 | ||
0bc12bcb | 14585 | intel_psr_init(dev); |
7c8f8a70 | 14586 | |
b2784e15 | 14587 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14588 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14589 | encoder->base.possible_clones = | |
66a9278e | 14590 | intel_encoder_clones(encoder); |
79e53945 | 14591 | } |
47356eb6 | 14592 | |
dde86e2d | 14593 | intel_init_pch_refclk(dev); |
270b3042 DV |
14594 | |
14595 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14596 | } |
14597 | ||
14598 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14599 | { | |
60a5ca01 | 14600 | struct drm_device *dev = fb->dev; |
79e53945 | 14601 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14602 | |
ef2d633e | 14603 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14604 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14605 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14606 | drm_gem_object_unreference(&intel_fb->obj->base); |
14607 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14608 | kfree(intel_fb); |
14609 | } | |
14610 | ||
14611 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14612 | struct drm_file *file, |
79e53945 JB |
14613 | unsigned int *handle) |
14614 | { | |
14615 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14616 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14617 | |
cc917ab4 CW |
14618 | if (obj->userptr.mm) { |
14619 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14620 | return -EINVAL; | |
14621 | } | |
14622 | ||
05394f39 | 14623 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14624 | } |
14625 | ||
86c98588 RV |
14626 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14627 | struct drm_file *file, | |
14628 | unsigned flags, unsigned color, | |
14629 | struct drm_clip_rect *clips, | |
14630 | unsigned num_clips) | |
14631 | { | |
14632 | struct drm_device *dev = fb->dev; | |
14633 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14634 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14635 | ||
14636 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14637 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14638 | mutex_unlock(&dev->struct_mutex); |
14639 | ||
14640 | return 0; | |
14641 | } | |
14642 | ||
79e53945 JB |
14643 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14644 | .destroy = intel_user_framebuffer_destroy, | |
14645 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14646 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14647 | }; |
14648 | ||
b321803d DL |
14649 | static |
14650 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14651 | uint32_t pixel_format) | |
14652 | { | |
14653 | u32 gen = INTEL_INFO(dev)->gen; | |
14654 | ||
14655 | if (gen >= 9) { | |
ac484963 VS |
14656 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14657 | ||
b321803d DL |
14658 | /* "The stride in bytes must not exceed the of the size of 8K |
14659 | * pixels and 32K bytes." | |
14660 | */ | |
ac484963 | 14661 | return min(8192 * cpp, 32768); |
666a4537 | 14662 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14663 | return 32*1024; |
14664 | } else if (gen >= 4) { | |
14665 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14666 | return 16*1024; | |
14667 | else | |
14668 | return 32*1024; | |
14669 | } else if (gen >= 3) { | |
14670 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14671 | return 8*1024; | |
14672 | else | |
14673 | return 16*1024; | |
14674 | } else { | |
14675 | /* XXX DSPC is limited to 4k tiled */ | |
14676 | return 8*1024; | |
14677 | } | |
14678 | } | |
14679 | ||
b5ea642a DV |
14680 | static int intel_framebuffer_init(struct drm_device *dev, |
14681 | struct intel_framebuffer *intel_fb, | |
14682 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14683 | struct drm_i915_gem_object *obj) | |
79e53945 | 14684 | { |
7b49f948 | 14685 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14686 | unsigned int aligned_height; |
79e53945 | 14687 | int ret; |
b321803d | 14688 | u32 pitch_limit, stride_alignment; |
79e53945 | 14689 | |
dd4916c5 DV |
14690 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14691 | ||
2a80eada DV |
14692 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14693 | /* Enforce that fb modifier and tiling mode match, but only for | |
14694 | * X-tiled. This is needed for FBC. */ | |
14695 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14696 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14697 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14698 | return -EINVAL; | |
14699 | } | |
14700 | } else { | |
14701 | if (obj->tiling_mode == I915_TILING_X) | |
14702 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14703 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14704 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14705 | return -EINVAL; | |
14706 | } | |
14707 | } | |
14708 | ||
9a8f0a12 TU |
14709 | /* Passed in modifier sanity checking. */ |
14710 | switch (mode_cmd->modifier[0]) { | |
14711 | case I915_FORMAT_MOD_Y_TILED: | |
14712 | case I915_FORMAT_MOD_Yf_TILED: | |
14713 | if (INTEL_INFO(dev)->gen < 9) { | |
14714 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14715 | mode_cmd->modifier[0]); | |
14716 | return -EINVAL; | |
14717 | } | |
14718 | case DRM_FORMAT_MOD_NONE: | |
14719 | case I915_FORMAT_MOD_X_TILED: | |
14720 | break; | |
14721 | default: | |
c0f40428 JB |
14722 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14723 | mode_cmd->modifier[0]); | |
57cd6508 | 14724 | return -EINVAL; |
c16ed4be | 14725 | } |
57cd6508 | 14726 | |
7b49f948 VS |
14727 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14728 | mode_cmd->modifier[0], | |
b321803d DL |
14729 | mode_cmd->pixel_format); |
14730 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14731 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14732 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14733 | return -EINVAL; |
c16ed4be | 14734 | } |
57cd6508 | 14735 | |
b321803d DL |
14736 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14737 | mode_cmd->pixel_format); | |
a35cdaa0 | 14738 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14739 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14740 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14741 | "tiled" : "linear", |
a35cdaa0 | 14742 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14743 | return -EINVAL; |
c16ed4be | 14744 | } |
5d7bd705 | 14745 | |
2a80eada | 14746 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14747 | mode_cmd->pitches[0] != obj->stride) { |
14748 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14749 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14750 | return -EINVAL; |
c16ed4be | 14751 | } |
5d7bd705 | 14752 | |
57779d06 | 14753 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14754 | switch (mode_cmd->pixel_format) { |
57779d06 | 14755 | case DRM_FORMAT_C8: |
04b3924d VS |
14756 | case DRM_FORMAT_RGB565: |
14757 | case DRM_FORMAT_XRGB8888: | |
14758 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14759 | break; |
14760 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14761 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14762 | DRM_DEBUG("unsupported pixel format: %s\n", |
14763 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14764 | return -EINVAL; |
c16ed4be | 14765 | } |
57779d06 | 14766 | break; |
57779d06 | 14767 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14768 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14769 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14770 | DRM_DEBUG("unsupported pixel format: %s\n", |
14771 | drm_get_format_name(mode_cmd->pixel_format)); | |
14772 | return -EINVAL; | |
14773 | } | |
14774 | break; | |
14775 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14776 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14777 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14778 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14779 | DRM_DEBUG("unsupported pixel format: %s\n", |
14780 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14781 | return -EINVAL; |
c16ed4be | 14782 | } |
b5626747 | 14783 | break; |
7531208b | 14784 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14785 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14786 | DRM_DEBUG("unsupported pixel format: %s\n", |
14787 | drm_get_format_name(mode_cmd->pixel_format)); | |
14788 | return -EINVAL; | |
14789 | } | |
14790 | break; | |
04b3924d VS |
14791 | case DRM_FORMAT_YUYV: |
14792 | case DRM_FORMAT_UYVY: | |
14793 | case DRM_FORMAT_YVYU: | |
14794 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14795 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14796 | DRM_DEBUG("unsupported pixel format: %s\n", |
14797 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14798 | return -EINVAL; |
c16ed4be | 14799 | } |
57cd6508 CW |
14800 | break; |
14801 | default: | |
4ee62c76 VS |
14802 | DRM_DEBUG("unsupported pixel format: %s\n", |
14803 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14804 | return -EINVAL; |
14805 | } | |
14806 | ||
90f9a336 VS |
14807 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14808 | if (mode_cmd->offsets[0] != 0) | |
14809 | return -EINVAL; | |
14810 | ||
ec2c981e | 14811 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14812 | mode_cmd->pixel_format, |
14813 | mode_cmd->modifier[0]); | |
53155c0a DV |
14814 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14815 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14816 | return -EINVAL; | |
14817 | ||
c7d73f6a DV |
14818 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14819 | intel_fb->obj = obj; | |
14820 | ||
2d7a215f VS |
14821 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
14822 | ||
79e53945 JB |
14823 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14824 | if (ret) { | |
14825 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14826 | return ret; | |
14827 | } | |
14828 | ||
0b05e1e0 VS |
14829 | intel_fb->obj->framebuffer_references++; |
14830 | ||
79e53945 JB |
14831 | return 0; |
14832 | } | |
14833 | ||
79e53945 JB |
14834 | static struct drm_framebuffer * |
14835 | intel_user_framebuffer_create(struct drm_device *dev, | |
14836 | struct drm_file *filp, | |
1eb83451 | 14837 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14838 | { |
dcb1394e | 14839 | struct drm_framebuffer *fb; |
05394f39 | 14840 | struct drm_i915_gem_object *obj; |
76dc3769 | 14841 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14842 | |
308e5bcb | 14843 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14844 | mode_cmd.handles[0])); |
c8725226 | 14845 | if (&obj->base == NULL) |
cce13ff7 | 14846 | return ERR_PTR(-ENOENT); |
79e53945 | 14847 | |
92907cbb | 14848 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14849 | if (IS_ERR(fb)) |
14850 | drm_gem_object_unreference_unlocked(&obj->base); | |
14851 | ||
14852 | return fb; | |
79e53945 JB |
14853 | } |
14854 | ||
0695726e | 14855 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14856 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14857 | { |
14858 | } | |
14859 | #endif | |
14860 | ||
79e53945 | 14861 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14862 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14863 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14864 | .atomic_check = intel_atomic_check, |
14865 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14866 | .atomic_state_alloc = intel_atomic_state_alloc, |
14867 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14868 | }; |
14869 | ||
88212941 ID |
14870 | /** |
14871 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14872 | * @dev_priv: device private | |
14873 | */ | |
14874 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14875 | { |
88212941 | 14876 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14877 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14878 | dev_priv->display.get_initial_plane_config = |
14879 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14880 | dev_priv->display.crtc_compute_clock = |
14881 | haswell_crtc_compute_clock; | |
14882 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14883 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14884 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14885 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14886 | dev_priv->display.get_initial_plane_config = |
14887 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14888 | dev_priv->display.crtc_compute_clock = |
14889 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14890 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14891 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14892 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14893 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14894 | dev_priv->display.get_initial_plane_config = |
14895 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14896 | dev_priv->display.crtc_compute_clock = |
14897 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14898 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14899 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14900 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14901 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14902 | dev_priv->display.get_initial_plane_config = |
14903 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14904 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14905 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14906 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14907 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14908 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14909 | dev_priv->display.get_initial_plane_config = | |
14910 | i9xx_get_initial_plane_config; | |
14911 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14912 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14913 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14914 | } else if (IS_G4X(dev_priv)) { |
14915 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14916 | dev_priv->display.get_initial_plane_config = | |
14917 | i9xx_get_initial_plane_config; | |
14918 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14919 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14920 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14921 | } else if (IS_PINEVIEW(dev_priv)) { |
14922 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14923 | dev_priv->display.get_initial_plane_config = | |
14924 | i9xx_get_initial_plane_config; | |
14925 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14926 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14927 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14928 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14929 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14930 | dev_priv->display.get_initial_plane_config = |
14931 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14932 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14933 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14934 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14935 | } else { |
14936 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14937 | dev_priv->display.get_initial_plane_config = | |
14938 | i9xx_get_initial_plane_config; | |
14939 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14940 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14941 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14942 | } |
e70236a8 | 14943 | |
e70236a8 | 14944 | /* Returns the core display clock speed */ |
88212941 | 14945 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
14946 | dev_priv->display.get_display_clock_speed = |
14947 | skylake_get_display_clock_speed; | |
88212941 | 14948 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
14949 | dev_priv->display.get_display_clock_speed = |
14950 | broxton_get_display_clock_speed; | |
88212941 | 14951 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
14952 | dev_priv->display.get_display_clock_speed = |
14953 | broadwell_get_display_clock_speed; | |
88212941 | 14954 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
14955 | dev_priv->display.get_display_clock_speed = |
14956 | haswell_get_display_clock_speed; | |
88212941 | 14957 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
14958 | dev_priv->display.get_display_clock_speed = |
14959 | valleyview_get_display_clock_speed; | |
88212941 | 14960 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
14961 | dev_priv->display.get_display_clock_speed = |
14962 | ilk_get_display_clock_speed; | |
88212941 ID |
14963 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
14964 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
14965 | dev_priv->display.get_display_clock_speed = |
14966 | i945_get_display_clock_speed; | |
88212941 | 14967 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
14968 | dev_priv->display.get_display_clock_speed = |
14969 | gm45_get_display_clock_speed; | |
88212941 | 14970 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
14971 | dev_priv->display.get_display_clock_speed = |
14972 | i965gm_get_display_clock_speed; | |
88212941 | 14973 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
14974 | dev_priv->display.get_display_clock_speed = |
14975 | pnv_get_display_clock_speed; | |
88212941 | 14976 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
14977 | dev_priv->display.get_display_clock_speed = |
14978 | g33_get_display_clock_speed; | |
88212941 | 14979 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
14980 | dev_priv->display.get_display_clock_speed = |
14981 | i915_get_display_clock_speed; | |
88212941 | 14982 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
14983 | dev_priv->display.get_display_clock_speed = |
14984 | i9xx_misc_get_display_clock_speed; | |
88212941 | 14985 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
14986 | dev_priv->display.get_display_clock_speed = |
14987 | i915gm_get_display_clock_speed; | |
88212941 | 14988 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
14989 | dev_priv->display.get_display_clock_speed = |
14990 | i865_get_display_clock_speed; | |
88212941 | 14991 | else if (IS_I85X(dev_priv)) |
e70236a8 | 14992 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14993 | i85x_get_display_clock_speed; |
623e01e5 | 14994 | else { /* 830 */ |
88212941 | 14995 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
14996 | dev_priv->display.get_display_clock_speed = |
14997 | i830_get_display_clock_speed; | |
623e01e5 | 14998 | } |
e70236a8 | 14999 | |
88212941 | 15000 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 15001 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 15002 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 15003 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 15004 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
15005 | /* FIXME: detect B0+ stepping and use auto training */ |
15006 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 15007 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 15008 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
88212941 | 15009 | if (IS_BROADWELL(dev_priv)) { |
27c329ed ML |
15010 | dev_priv->display.modeset_commit_cdclk = |
15011 | broadwell_modeset_commit_cdclk; | |
15012 | dev_priv->display.modeset_calc_cdclk = | |
15013 | broadwell_modeset_calc_cdclk; | |
15014 | } | |
88212941 | 15015 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
15016 | dev_priv->display.modeset_commit_cdclk = |
15017 | valleyview_modeset_commit_cdclk; | |
15018 | dev_priv->display.modeset_calc_cdclk = | |
15019 | valleyview_modeset_calc_cdclk; | |
88212941 | 15020 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed ML |
15021 | dev_priv->display.modeset_commit_cdclk = |
15022 | broxton_modeset_commit_cdclk; | |
15023 | dev_priv->display.modeset_calc_cdclk = | |
15024 | broxton_modeset_calc_cdclk; | |
e70236a8 | 15025 | } |
8c9f3aaf | 15026 | |
88212941 | 15027 | switch (INTEL_INFO(dev_priv)->gen) { |
8c9f3aaf JB |
15028 | case 2: |
15029 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15030 | break; | |
15031 | ||
15032 | case 3: | |
15033 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15034 | break; | |
15035 | ||
15036 | case 4: | |
15037 | case 5: | |
15038 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15039 | break; | |
15040 | ||
15041 | case 6: | |
15042 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15043 | break; | |
7c9017e5 | 15044 | case 7: |
4e0bbc31 | 15045 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15046 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15047 | break; | |
830c81db | 15048 | case 9: |
ba343e02 TU |
15049 | /* Drop through - unsupported since execlist only. */ |
15050 | default: | |
15051 | /* Default just returns -ENODEV to indicate unsupported */ | |
15052 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15053 | } |
e70236a8 JB |
15054 | } |
15055 | ||
b690e96c JB |
15056 | /* |
15057 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15058 | * resume, or other times. This quirk makes sure that's the case for | |
15059 | * affected systems. | |
15060 | */ | |
0206e353 | 15061 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15062 | { |
15063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15064 | ||
15065 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15066 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15067 | } |
15068 | ||
b6b5d049 VS |
15069 | static void quirk_pipeb_force(struct drm_device *dev) |
15070 | { | |
15071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15072 | ||
15073 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15074 | DRM_INFO("applying pipe b force quirk\n"); | |
15075 | } | |
15076 | ||
435793df KP |
15077 | /* |
15078 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15079 | */ | |
15080 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15081 | { | |
15082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15083 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15084 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15085 | } |
15086 | ||
4dca20ef | 15087 | /* |
5a15ab5b CE |
15088 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15089 | * brightness value | |
4dca20ef CE |
15090 | */ |
15091 | static void quirk_invert_brightness(struct drm_device *dev) | |
15092 | { | |
15093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15094 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15095 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15096 | } |
15097 | ||
9c72cc6f SD |
15098 | /* Some VBT's incorrectly indicate no backlight is present */ |
15099 | static void quirk_backlight_present(struct drm_device *dev) | |
15100 | { | |
15101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15102 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15103 | DRM_INFO("applying backlight present quirk\n"); | |
15104 | } | |
15105 | ||
b690e96c JB |
15106 | struct intel_quirk { |
15107 | int device; | |
15108 | int subsystem_vendor; | |
15109 | int subsystem_device; | |
15110 | void (*hook)(struct drm_device *dev); | |
15111 | }; | |
15112 | ||
5f85f176 EE |
15113 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15114 | struct intel_dmi_quirk { | |
15115 | void (*hook)(struct drm_device *dev); | |
15116 | const struct dmi_system_id (*dmi_id_list)[]; | |
15117 | }; | |
15118 | ||
15119 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15120 | { | |
15121 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15122 | return 1; | |
15123 | } | |
15124 | ||
15125 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15126 | { | |
15127 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15128 | { | |
15129 | .callback = intel_dmi_reverse_brightness, | |
15130 | .ident = "NCR Corporation", | |
15131 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15132 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15133 | }, | |
15134 | }, | |
15135 | { } /* terminating entry */ | |
15136 | }, | |
15137 | .hook = quirk_invert_brightness, | |
15138 | }, | |
15139 | }; | |
15140 | ||
c43b5634 | 15141 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15142 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15143 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15144 | ||
b690e96c JB |
15145 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15146 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15147 | ||
5f080c0f VS |
15148 | /* 830 needs to leave pipe A & dpll A up */ |
15149 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15150 | ||
b6b5d049 VS |
15151 | /* 830 needs to leave pipe B & dpll B up */ |
15152 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15153 | ||
435793df KP |
15154 | /* Lenovo U160 cannot use SSC on LVDS */ |
15155 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15156 | |
15157 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15158 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15159 | |
be505f64 AH |
15160 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15161 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15162 | ||
15163 | /* Acer/eMachines G725 */ | |
15164 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15165 | ||
15166 | /* Acer/eMachines e725 */ | |
15167 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15168 | ||
15169 | /* Acer/Packard Bell NCL20 */ | |
15170 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15171 | ||
15172 | /* Acer Aspire 4736Z */ | |
15173 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15174 | |
15175 | /* Acer Aspire 5336 */ | |
15176 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15177 | |
15178 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15179 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15180 | |
dfb3d47b SD |
15181 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15182 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15183 | ||
b2a9601c | 15184 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15185 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15186 | ||
1b9448b0 JN |
15187 | /* Apple Macbook 4,1 */ |
15188 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15189 | ||
d4967d8c SD |
15190 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15191 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15192 | |
15193 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15194 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15195 | |
15196 | /* Dell Chromebook 11 */ | |
15197 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15198 | |
15199 | /* Dell Chromebook 11 (2015 version) */ | |
15200 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15201 | }; |
15202 | ||
15203 | static void intel_init_quirks(struct drm_device *dev) | |
15204 | { | |
15205 | struct pci_dev *d = dev->pdev; | |
15206 | int i; | |
15207 | ||
15208 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15209 | struct intel_quirk *q = &intel_quirks[i]; | |
15210 | ||
15211 | if (d->device == q->device && | |
15212 | (d->subsystem_vendor == q->subsystem_vendor || | |
15213 | q->subsystem_vendor == PCI_ANY_ID) && | |
15214 | (d->subsystem_device == q->subsystem_device || | |
15215 | q->subsystem_device == PCI_ANY_ID)) | |
15216 | q->hook(dev); | |
15217 | } | |
5f85f176 EE |
15218 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15219 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15220 | intel_dmi_quirks[i].hook(dev); | |
15221 | } | |
b690e96c JB |
15222 | } |
15223 | ||
9cce37f4 JB |
15224 | /* Disable the VGA plane that we never use */ |
15225 | static void i915_disable_vga(struct drm_device *dev) | |
15226 | { | |
15227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15228 | u8 sr1; | |
f0f59a00 | 15229 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15230 | |
2b37c616 | 15231 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15232 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15233 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15234 | sr1 = inb(VGA_SR_DATA); |
15235 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15236 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15237 | udelay(300); | |
15238 | ||
01f5a626 | 15239 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15240 | POSTING_READ(vga_reg); |
15241 | } | |
15242 | ||
f817586c DV |
15243 | void intel_modeset_init_hw(struct drm_device *dev) |
15244 | { | |
1a617b77 ML |
15245 | struct drm_i915_private *dev_priv = dev->dev_private; |
15246 | ||
b6283055 | 15247 | intel_update_cdclk(dev); |
1a617b77 ML |
15248 | |
15249 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15250 | ||
f817586c | 15251 | intel_init_clock_gating(dev); |
8090c6b9 | 15252 | intel_enable_gt_powersave(dev); |
f817586c DV |
15253 | } |
15254 | ||
d93c0372 MR |
15255 | /* |
15256 | * Calculate what we think the watermarks should be for the state we've read | |
15257 | * out of the hardware and then immediately program those watermarks so that | |
15258 | * we ensure the hardware settings match our internal state. | |
15259 | * | |
15260 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15261 | * current state (which was constructed during hardware readout) and running it | |
15262 | * through the atomic check code to calculate new watermark values in the | |
15263 | * state object. | |
15264 | */ | |
15265 | static void sanitize_watermarks(struct drm_device *dev) | |
15266 | { | |
15267 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15268 | struct drm_atomic_state *state; | |
15269 | struct drm_crtc *crtc; | |
15270 | struct drm_crtc_state *cstate; | |
15271 | struct drm_modeset_acquire_ctx ctx; | |
15272 | int ret; | |
15273 | int i; | |
15274 | ||
15275 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15276 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15277 | return; |
15278 | ||
15279 | /* | |
15280 | * We need to hold connection_mutex before calling duplicate_state so | |
15281 | * that the connector loop is protected. | |
15282 | */ | |
15283 | drm_modeset_acquire_init(&ctx, 0); | |
15284 | retry: | |
0cd1262d | 15285 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15286 | if (ret == -EDEADLK) { |
15287 | drm_modeset_backoff(&ctx); | |
15288 | goto retry; | |
15289 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15290 | goto fail; |
d93c0372 MR |
15291 | } |
15292 | ||
15293 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15294 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15295 | goto fail; |
d93c0372 | 15296 | |
ed4a6a7c MR |
15297 | /* |
15298 | * Hardware readout is the only time we don't want to calculate | |
15299 | * intermediate watermarks (since we don't trust the current | |
15300 | * watermarks). | |
15301 | */ | |
15302 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15303 | ||
d93c0372 MR |
15304 | ret = intel_atomic_check(dev, state); |
15305 | if (ret) { | |
15306 | /* | |
15307 | * If we fail here, it means that the hardware appears to be | |
15308 | * programmed in a way that shouldn't be possible, given our | |
15309 | * understanding of watermark requirements. This might mean a | |
15310 | * mistake in the hardware readout code or a mistake in the | |
15311 | * watermark calculations for a given platform. Raise a WARN | |
15312 | * so that this is noticeable. | |
15313 | * | |
15314 | * If this actually happens, we'll have to just leave the | |
15315 | * BIOS-programmed watermarks untouched and hope for the best. | |
15316 | */ | |
15317 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15318 | goto fail; |
d93c0372 MR |
15319 | } |
15320 | ||
15321 | /* Write calculated watermark values back */ | |
15322 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15323 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15324 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15325 | ||
ed4a6a7c MR |
15326 | cs->wm.need_postvbl_update = true; |
15327 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15328 | } |
15329 | ||
15330 | drm_atomic_state_free(state); | |
0cd1262d | 15331 | fail: |
d93c0372 MR |
15332 | drm_modeset_drop_locks(&ctx); |
15333 | drm_modeset_acquire_fini(&ctx); | |
15334 | } | |
15335 | ||
79e53945 JB |
15336 | void intel_modeset_init(struct drm_device *dev) |
15337 | { | |
72e96d64 JL |
15338 | struct drm_i915_private *dev_priv = to_i915(dev); |
15339 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1fe47785 | 15340 | int sprite, ret; |
8cc87b75 | 15341 | enum pipe pipe; |
46f297fb | 15342 | struct intel_crtc *crtc; |
79e53945 JB |
15343 | |
15344 | drm_mode_config_init(dev); | |
15345 | ||
15346 | dev->mode_config.min_width = 0; | |
15347 | dev->mode_config.min_height = 0; | |
15348 | ||
019d96cb DA |
15349 | dev->mode_config.preferred_depth = 24; |
15350 | dev->mode_config.prefer_shadow = 1; | |
15351 | ||
25bab385 TU |
15352 | dev->mode_config.allow_fb_modifiers = true; |
15353 | ||
e6ecefaa | 15354 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15355 | |
b690e96c JB |
15356 | intel_init_quirks(dev); |
15357 | ||
1fa61106 ED |
15358 | intel_init_pm(dev); |
15359 | ||
e3c74757 BW |
15360 | if (INTEL_INFO(dev)->num_pipes == 0) |
15361 | return; | |
15362 | ||
69f92f67 LW |
15363 | /* |
15364 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15365 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15366 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15367 | * indicates as much. | |
15368 | */ | |
15369 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15370 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15371 | DREF_SSC1_ENABLE); | |
15372 | ||
15373 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15374 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15375 | bios_lvds_use_ssc ? "en" : "dis", | |
15376 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15377 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15378 | } | |
15379 | } | |
15380 | ||
a6c45cf0 CW |
15381 | if (IS_GEN2(dev)) { |
15382 | dev->mode_config.max_width = 2048; | |
15383 | dev->mode_config.max_height = 2048; | |
15384 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15385 | dev->mode_config.max_width = 4096; |
15386 | dev->mode_config.max_height = 4096; | |
79e53945 | 15387 | } else { |
a6c45cf0 CW |
15388 | dev->mode_config.max_width = 8192; |
15389 | dev->mode_config.max_height = 8192; | |
79e53945 | 15390 | } |
068be561 | 15391 | |
dc41c154 VS |
15392 | if (IS_845G(dev) || IS_I865G(dev)) { |
15393 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15394 | dev->mode_config.cursor_height = 1023; | |
15395 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15396 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15397 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15398 | } else { | |
15399 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15400 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15401 | } | |
15402 | ||
72e96d64 | 15403 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 15404 | |
28c97730 | 15405 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15406 | INTEL_INFO(dev)->num_pipes, |
15407 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15408 | |
055e393f | 15409 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15410 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15411 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15412 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15413 | if (ret) |
06da8da2 | 15414 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15415 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15416 | } |
79e53945 JB |
15417 | } |
15418 | ||
bfa7df01 | 15419 | intel_update_czclk(dev_priv); |
e7dc33f3 | 15420 | intel_update_rawclk(dev_priv); |
bfa7df01 VS |
15421 | intel_update_cdclk(dev); |
15422 | ||
e72f9fbf | 15423 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15424 | |
9cce37f4 JB |
15425 | /* Just disable it once at startup */ |
15426 | i915_disable_vga(dev); | |
79e53945 | 15427 | intel_setup_outputs(dev); |
11be49eb | 15428 | |
6e9f798d | 15429 | drm_modeset_lock_all(dev); |
043e9bda | 15430 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15431 | drm_modeset_unlock_all(dev); |
46f297fb | 15432 | |
d3fcc808 | 15433 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15434 | struct intel_initial_plane_config plane_config = {}; |
15435 | ||
46f297fb JB |
15436 | if (!crtc->active) |
15437 | continue; | |
15438 | ||
46f297fb | 15439 | /* |
46f297fb JB |
15440 | * Note that reserving the BIOS fb up front prevents us |
15441 | * from stuffing other stolen allocations like the ring | |
15442 | * on top. This prevents some ugliness at boot time, and | |
15443 | * can even allow for smooth boot transitions if the BIOS | |
15444 | * fb is large enough for the active pipe configuration. | |
15445 | */ | |
eeebeac5 ML |
15446 | dev_priv->display.get_initial_plane_config(crtc, |
15447 | &plane_config); | |
15448 | ||
15449 | /* | |
15450 | * If the fb is shared between multiple heads, we'll | |
15451 | * just get the first one. | |
15452 | */ | |
15453 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15454 | } |
d93c0372 MR |
15455 | |
15456 | /* | |
15457 | * Make sure hardware watermarks really match the state we read out. | |
15458 | * Note that we need to do this after reconstructing the BIOS fb's | |
15459 | * since the watermark calculation done here will use pstate->fb. | |
15460 | */ | |
15461 | sanitize_watermarks(dev); | |
2c7111db CW |
15462 | } |
15463 | ||
7fad798e DV |
15464 | static void intel_enable_pipe_a(struct drm_device *dev) |
15465 | { | |
15466 | struct intel_connector *connector; | |
15467 | struct drm_connector *crt = NULL; | |
15468 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15469 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15470 | |
15471 | /* We can't just switch on the pipe A, we need to set things up with a | |
15472 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15473 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15474 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15475 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15476 | crt = &connector->base; | |
15477 | break; | |
15478 | } | |
15479 | } | |
15480 | ||
15481 | if (!crt) | |
15482 | return; | |
15483 | ||
208bf9fd | 15484 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15485 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15486 | } |
15487 | ||
fa555837 DV |
15488 | static bool |
15489 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15490 | { | |
7eb552ae BW |
15491 | struct drm_device *dev = crtc->base.dev; |
15492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15493 | u32 val; |
fa555837 | 15494 | |
7eb552ae | 15495 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15496 | return true; |
15497 | ||
649636ef | 15498 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15499 | |
15500 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15501 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15502 | return false; | |
15503 | ||
15504 | return true; | |
15505 | } | |
15506 | ||
02e93c35 VS |
15507 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15508 | { | |
15509 | struct drm_device *dev = crtc->base.dev; | |
15510 | struct intel_encoder *encoder; | |
15511 | ||
15512 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15513 | return true; | |
15514 | ||
15515 | return false; | |
15516 | } | |
15517 | ||
dd756198 VS |
15518 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15519 | { | |
15520 | struct drm_device *dev = encoder->base.dev; | |
15521 | struct intel_connector *connector; | |
15522 | ||
15523 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15524 | return true; | |
15525 | ||
15526 | return false; | |
15527 | } | |
15528 | ||
24929352 DV |
15529 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15530 | { | |
15531 | struct drm_device *dev = crtc->base.dev; | |
15532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4d1de975 | 15533 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15534 | |
24929352 | 15535 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15536 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15537 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15538 | ||
15539 | I915_WRITE(reg, | |
15540 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15541 | } | |
24929352 | 15542 | |
d3eaf884 | 15543 | /* restore vblank interrupts to correct state */ |
9625604c | 15544 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15545 | if (crtc->active) { |
f9cd7b88 VS |
15546 | struct intel_plane *plane; |
15547 | ||
9625604c | 15548 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15549 | |
15550 | /* Disable everything but the primary plane */ | |
15551 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15552 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15553 | continue; | |
15554 | ||
15555 | plane->disable_plane(&plane->base, &crtc->base); | |
15556 | } | |
9625604c | 15557 | } |
d3eaf884 | 15558 | |
24929352 | 15559 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15560 | * disable the crtc (and hence change the state) if it is wrong. Note |
15561 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15562 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15563 | bool plane; |
15564 | ||
24929352 DV |
15565 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15566 | crtc->base.base.id); | |
15567 | ||
15568 | /* Pipe has the wrong plane attached and the plane is active. | |
15569 | * Temporarily change the plane mapping and disable everything | |
15570 | * ... */ | |
15571 | plane = crtc->plane; | |
b70709a6 | 15572 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15573 | crtc->plane = !plane; |
b17d48e2 | 15574 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15575 | crtc->plane = plane; |
24929352 | 15576 | } |
24929352 | 15577 | |
7fad798e DV |
15578 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15579 | crtc->pipe == PIPE_A && !crtc->active) { | |
15580 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15581 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15582 | * call below we restore the pipe to the right state, but leave | |
15583 | * the required bits on. */ | |
15584 | intel_enable_pipe_a(dev); | |
15585 | } | |
15586 | ||
24929352 DV |
15587 | /* Adjust the state of the output pipe according to whether we |
15588 | * have active connectors/encoders. */ | |
842e0307 | 15589 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15590 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15591 | |
a3ed6aad | 15592 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15593 | /* |
15594 | * We start out with underrun reporting disabled to avoid races. | |
15595 | * For correct bookkeeping mark this on active crtcs. | |
15596 | * | |
c5ab3bc0 DV |
15597 | * Also on gmch platforms we dont have any hardware bits to |
15598 | * disable the underrun reporting. Which means we need to start | |
15599 | * out with underrun reporting disabled also on inactive pipes, | |
15600 | * since otherwise we'll complain about the garbage we read when | |
15601 | * e.g. coming up after runtime pm. | |
15602 | * | |
4cc31489 DV |
15603 | * No protection against concurrent access is required - at |
15604 | * worst a fifo underrun happens which also sets this to false. | |
15605 | */ | |
15606 | crtc->cpu_fifo_underrun_disabled = true; | |
15607 | crtc->pch_fifo_underrun_disabled = true; | |
15608 | } | |
24929352 DV |
15609 | } |
15610 | ||
15611 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15612 | { | |
15613 | struct intel_connector *connector; | |
15614 | struct drm_device *dev = encoder->base.dev; | |
15615 | ||
15616 | /* We need to check both for a crtc link (meaning that the | |
15617 | * encoder is active and trying to read from a pipe) and the | |
15618 | * pipe itself being active. */ | |
15619 | bool has_active_crtc = encoder->base.crtc && | |
15620 | to_intel_crtc(encoder->base.crtc)->active; | |
15621 | ||
dd756198 | 15622 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15623 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15624 | encoder->base.base.id, | |
8e329a03 | 15625 | encoder->base.name); |
24929352 DV |
15626 | |
15627 | /* Connector is active, but has no active pipe. This is | |
15628 | * fallout from our resume register restoring. Disable | |
15629 | * the encoder manually again. */ | |
15630 | if (encoder->base.crtc) { | |
15631 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15632 | encoder->base.base.id, | |
8e329a03 | 15633 | encoder->base.name); |
24929352 | 15634 | encoder->disable(encoder); |
a62d1497 VS |
15635 | if (encoder->post_disable) |
15636 | encoder->post_disable(encoder); | |
24929352 | 15637 | } |
7f1950fb | 15638 | encoder->base.crtc = NULL; |
24929352 DV |
15639 | |
15640 | /* Inconsistent output/port/pipe state happens presumably due to | |
15641 | * a bug in one of the get_hw_state functions. Or someplace else | |
15642 | * in our code, like the register restore mess on resume. Clamp | |
15643 | * things to off as a safer default. */ | |
3a3371ff | 15644 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15645 | if (connector->encoder != encoder) |
15646 | continue; | |
7f1950fb EE |
15647 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15648 | connector->base.encoder = NULL; | |
24929352 DV |
15649 | } |
15650 | } | |
15651 | /* Enabled encoders without active connectors will be fixed in | |
15652 | * the crtc fixup. */ | |
15653 | } | |
15654 | ||
04098753 | 15655 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15656 | { |
15657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15658 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15659 | |
04098753 ID |
15660 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15661 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15662 | i915_disable_vga(dev); | |
15663 | } | |
15664 | } | |
15665 | ||
15666 | void i915_redisable_vga(struct drm_device *dev) | |
15667 | { | |
15668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15669 | ||
8dc8a27c PZ |
15670 | /* This function can be called both from intel_modeset_setup_hw_state or |
15671 | * at a very early point in our resume sequence, where the power well | |
15672 | * structures are not yet restored. Since this function is at a very | |
15673 | * paranoid "someone might have enabled VGA while we were not looking" | |
15674 | * level, just check if the power well is enabled instead of trying to | |
15675 | * follow the "don't touch the power well if we don't need it" policy | |
15676 | * the rest of the driver uses. */ | |
6392f847 | 15677 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15678 | return; |
15679 | ||
04098753 | 15680 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15681 | |
15682 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15683 | } |
15684 | ||
f9cd7b88 | 15685 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15686 | { |
f9cd7b88 | 15687 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15688 | |
f9cd7b88 | 15689 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15690 | } |
15691 | ||
f9cd7b88 VS |
15692 | /* FIXME read out full plane state for all planes */ |
15693 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15694 | { |
b26d3ea3 | 15695 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15696 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15697 | to_intel_plane_state(primary->state); |
d032ffa0 | 15698 | |
19b8d387 | 15699 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15700 | primary_get_hw_state(to_intel_plane(primary)); |
15701 | ||
15702 | if (plane_state->visible) | |
15703 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15704 | } |
15705 | ||
30e984df | 15706 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15707 | { |
15708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15709 | enum pipe pipe; | |
24929352 DV |
15710 | struct intel_crtc *crtc; |
15711 | struct intel_encoder *encoder; | |
15712 | struct intel_connector *connector; | |
5358901f | 15713 | int i; |
24929352 | 15714 | |
565602d7 ML |
15715 | dev_priv->active_crtcs = 0; |
15716 | ||
d3fcc808 | 15717 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15718 | struct intel_crtc_state *crtc_state = crtc->config; |
15719 | int pixclk = 0; | |
3b117c8f | 15720 | |
565602d7 ML |
15721 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15722 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15723 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15724 | |
565602d7 ML |
15725 | crtc_state->base.active = crtc_state->base.enable = |
15726 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15727 | ||
15728 | crtc->base.enabled = crtc_state->base.enable; | |
15729 | crtc->active = crtc_state->base.active; | |
15730 | ||
15731 | if (crtc_state->base.active) { | |
15732 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15733 | ||
15734 | if (IS_BROADWELL(dev_priv)) { | |
15735 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15736 | ||
15737 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15738 | if (crtc_state->ips_enabled) | |
15739 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15740 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15741 | IS_CHERRYVIEW(dev_priv) || | |
15742 | IS_BROXTON(dev_priv)) | |
15743 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15744 | else | |
15745 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15746 | } | |
15747 | ||
15748 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15749 | |
f9cd7b88 | 15750 | readout_plane_state(crtc); |
24929352 DV |
15751 | |
15752 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15753 | crtc->base.base.id, | |
15754 | crtc->active ? "enabled" : "disabled"); | |
15755 | } | |
15756 | ||
5358901f DV |
15757 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15758 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15759 | ||
2edd6443 ACO |
15760 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
15761 | &pll->config.hw_state); | |
3e369b76 | 15762 | pll->config.crtc_mask = 0; |
d3fcc808 | 15763 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 15764 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 15765 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15766 | } |
2dd66ebd | 15767 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 15768 | |
1e6f2ddc | 15769 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15770 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
15771 | } |
15772 | ||
b2784e15 | 15773 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15774 | pipe = 0; |
15775 | ||
15776 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15777 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15778 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15779 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15780 | } else { |
15781 | encoder->base.crtc = NULL; | |
15782 | } | |
15783 | ||
6f2bcceb | 15784 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15785 | encoder->base.base.id, |
8e329a03 | 15786 | encoder->base.name, |
24929352 | 15787 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15788 | pipe_name(pipe)); |
24929352 DV |
15789 | } |
15790 | ||
3a3371ff | 15791 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15792 | if (connector->get_hw_state(connector)) { |
15793 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15794 | |
15795 | encoder = connector->encoder; | |
15796 | connector->base.encoder = &encoder->base; | |
15797 | ||
15798 | if (encoder->base.crtc && | |
15799 | encoder->base.crtc->state->active) { | |
15800 | /* | |
15801 | * This has to be done during hardware readout | |
15802 | * because anything calling .crtc_disable may | |
15803 | * rely on the connector_mask being accurate. | |
15804 | */ | |
15805 | encoder->base.crtc->state->connector_mask |= | |
15806 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15807 | encoder->base.crtc->state->encoder_mask |= |
15808 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15809 | } |
15810 | ||
24929352 DV |
15811 | } else { |
15812 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15813 | connector->base.encoder = NULL; | |
15814 | } | |
15815 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15816 | connector->base.base.id, | |
c23cc417 | 15817 | connector->base.name, |
24929352 DV |
15818 | connector->base.encoder ? "enabled" : "disabled"); |
15819 | } | |
7f4c6284 VS |
15820 | |
15821 | for_each_intel_crtc(dev, crtc) { | |
15822 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15823 | ||
15824 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15825 | if (crtc->base.state->active) { | |
15826 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15827 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15828 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15829 | ||
15830 | /* | |
15831 | * The initial mode needs to be set in order to keep | |
15832 | * the atomic core happy. It wants a valid mode if the | |
15833 | * crtc's enabled, so we do the above call. | |
15834 | * | |
15835 | * At this point some state updated by the connectors | |
15836 | * in their ->detect() callback has not run yet, so | |
15837 | * no recalculation can be done yet. | |
15838 | * | |
15839 | * Even if we could do a recalculation and modeset | |
15840 | * right now it would cause a double modeset if | |
15841 | * fbdev or userspace chooses a different initial mode. | |
15842 | * | |
15843 | * If that happens, someone indicated they wanted a | |
15844 | * mode change, which means it's safe to do a full | |
15845 | * recalculation. | |
15846 | */ | |
15847 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15848 | |
15849 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15850 | update_scanline_offset(crtc); | |
7f4c6284 | 15851 | } |
e3b247da VS |
15852 | |
15853 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 15854 | } |
30e984df DV |
15855 | } |
15856 | ||
043e9bda ML |
15857 | /* Scan out the current hw modeset state, |
15858 | * and sanitizes it to the current state | |
15859 | */ | |
15860 | static void | |
15861 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15862 | { |
15863 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15864 | enum pipe pipe; | |
30e984df DV |
15865 | struct intel_crtc *crtc; |
15866 | struct intel_encoder *encoder; | |
35c95375 | 15867 | int i; |
30e984df DV |
15868 | |
15869 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15870 | |
15871 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15872 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15873 | intel_sanitize_encoder(encoder); |
15874 | } | |
15875 | ||
055e393f | 15876 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15877 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15878 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15879 | intel_dump_pipe_config(crtc, crtc->config, |
15880 | "[setup_hw_state]"); | |
24929352 | 15881 | } |
9a935856 | 15882 | |
d29b2f9d ACO |
15883 | intel_modeset_update_connector_atomic_state(dev); |
15884 | ||
35c95375 DV |
15885 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15886 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15887 | ||
2dd66ebd | 15888 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15889 | continue; |
15890 | ||
15891 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15892 | ||
2edd6443 | 15893 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15894 | pll->on = false; |
15895 | } | |
15896 | ||
666a4537 | 15897 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15898 | vlv_wm_get_hw_state(dev); |
15899 | else if (IS_GEN9(dev)) | |
3078999f PB |
15900 | skl_wm_get_hw_state(dev); |
15901 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15902 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15903 | |
15904 | for_each_intel_crtc(dev, crtc) { | |
15905 | unsigned long put_domains; | |
15906 | ||
74bff5f9 | 15907 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15908 | if (WARN_ON(put_domains)) |
15909 | modeset_put_power_domains(dev_priv, put_domains); | |
15910 | } | |
15911 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
15912 | |
15913 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 15914 | } |
7d0bc1ea | 15915 | |
043e9bda ML |
15916 | void intel_display_resume(struct drm_device *dev) |
15917 | { | |
e2c8b870 ML |
15918 | struct drm_i915_private *dev_priv = to_i915(dev); |
15919 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15920 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15921 | int ret; |
e2c8b870 | 15922 | bool setup = false; |
f30da187 | 15923 | |
e2c8b870 | 15924 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 15925 | |
ea49c9ac ML |
15926 | /* |
15927 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15928 | * won't be taken. Unfortunately some probed state like | |
15929 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15930 | * it here for now. | |
15931 | */ | |
15932 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 15933 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15934 | |
e2c8b870 ML |
15935 | retry: |
15936 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 15937 | |
e2c8b870 ML |
15938 | if (ret == 0 && !setup) { |
15939 | setup = true; | |
043e9bda | 15940 | |
e2c8b870 ML |
15941 | intel_modeset_setup_hw_state(dev); |
15942 | i915_redisable_vga(dev); | |
45e2b5f6 | 15943 | } |
8af6cf88 | 15944 | |
e2c8b870 ML |
15945 | if (ret == 0 && state) { |
15946 | struct drm_crtc_state *crtc_state; | |
15947 | struct drm_crtc *crtc; | |
15948 | int i; | |
043e9bda | 15949 | |
e2c8b870 ML |
15950 | state->acquire_ctx = &ctx; |
15951 | ||
15952 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
15953 | /* | |
15954 | * Force recalculation even if we restore | |
15955 | * current state. With fast modeset this may not result | |
15956 | * in a modeset when the state is compatible. | |
15957 | */ | |
15958 | crtc_state->mode_changed = true; | |
15959 | } | |
15960 | ||
15961 | ret = drm_atomic_commit(state); | |
043e9bda ML |
15962 | } |
15963 | ||
e2c8b870 ML |
15964 | if (ret == -EDEADLK) { |
15965 | drm_modeset_backoff(&ctx); | |
15966 | goto retry; | |
15967 | } | |
043e9bda | 15968 | |
e2c8b870 ML |
15969 | drm_modeset_drop_locks(&ctx); |
15970 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 15971 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 15972 | |
e2c8b870 ML |
15973 | if (ret) { |
15974 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15975 | drm_atomic_state_free(state); | |
15976 | } | |
2c7111db CW |
15977 | } |
15978 | ||
15979 | void intel_modeset_gem_init(struct drm_device *dev) | |
15980 | { | |
484b41dd | 15981 | struct drm_crtc *c; |
2ff8fde1 | 15982 | struct drm_i915_gem_object *obj; |
e0d6149b | 15983 | int ret; |
484b41dd | 15984 | |
ae48434c | 15985 | intel_init_gt_powersave(dev); |
ae48434c | 15986 | |
1833b134 | 15987 | intel_modeset_init_hw(dev); |
02e792fb DV |
15988 | |
15989 | intel_setup_overlay(dev); | |
484b41dd JB |
15990 | |
15991 | /* | |
15992 | * Make sure any fbs we allocated at startup are properly | |
15993 | * pinned & fenced. When we do the allocation it's too early | |
15994 | * for this. | |
15995 | */ | |
70e1e0ec | 15996 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15997 | obj = intel_fb_obj(c->primary->fb); |
15998 | if (obj == NULL) | |
484b41dd JB |
15999 | continue; |
16000 | ||
e0d6149b | 16001 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
16002 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
16003 | c->primary->state->rotation); | |
e0d6149b TU |
16004 | mutex_unlock(&dev->struct_mutex); |
16005 | if (ret) { | |
484b41dd JB |
16006 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16007 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
16008 | drm_framebuffer_unreference(c->primary->fb); |
16009 | c->primary->fb = NULL; | |
36750f28 | 16010 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 16011 | update_state_fb(c->primary); |
36750f28 | 16012 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16013 | } |
16014 | } | |
0962c3c9 VS |
16015 | |
16016 | intel_backlight_register(dev); | |
79e53945 JB |
16017 | } |
16018 | ||
4932e2c3 ID |
16019 | void intel_connector_unregister(struct intel_connector *intel_connector) |
16020 | { | |
16021 | struct drm_connector *connector = &intel_connector->base; | |
16022 | ||
16023 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 16024 | drm_connector_unregister(connector); |
4932e2c3 ID |
16025 | } |
16026 | ||
79e53945 JB |
16027 | void intel_modeset_cleanup(struct drm_device *dev) |
16028 | { | |
652c393a | 16029 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 16030 | struct intel_connector *connector; |
652c393a | 16031 | |
2eb5252e ID |
16032 | intel_disable_gt_powersave(dev); |
16033 | ||
0962c3c9 VS |
16034 | intel_backlight_unregister(dev); |
16035 | ||
fd0c0642 DV |
16036 | /* |
16037 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16038 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16039 | * experience fancy races otherwise. |
16040 | */ | |
2aeb7d3a | 16041 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16042 | |
fd0c0642 DV |
16043 | /* |
16044 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16045 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16046 | */ | |
f87ea761 | 16047 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16048 | |
723bfd70 JB |
16049 | intel_unregister_dsm_handler(); |
16050 | ||
c937ab3e | 16051 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16052 | |
1630fe75 CW |
16053 | /* flush any delayed tasks or pending work */ |
16054 | flush_scheduled_work(); | |
16055 | ||
db31af1d | 16056 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16057 | for_each_intel_connector(dev, connector) |
16058 | connector->unregister(connector); | |
d9255d57 | 16059 | |
79e53945 | 16060 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
16061 | |
16062 | intel_cleanup_overlay(dev); | |
ae48434c | 16063 | |
ae48434c | 16064 | intel_cleanup_gt_powersave(dev); |
f5949141 DV |
16065 | |
16066 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16067 | } |
16068 | ||
f1c79df3 ZW |
16069 | /* |
16070 | * Return which encoder is currently attached for connector. | |
16071 | */ | |
df0e9248 | 16072 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16073 | { |
df0e9248 CW |
16074 | return &intel_attached_encoder(connector)->base; |
16075 | } | |
f1c79df3 | 16076 | |
df0e9248 CW |
16077 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16078 | struct intel_encoder *encoder) | |
16079 | { | |
16080 | connector->encoder = encoder; | |
16081 | drm_mode_connector_attach_encoder(&connector->base, | |
16082 | &encoder->base); | |
79e53945 | 16083 | } |
28d52043 DA |
16084 | |
16085 | /* | |
16086 | * set vga decode state - true == enable VGA decode | |
16087 | */ | |
16088 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16089 | { | |
16090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16091 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16092 | u16 gmch_ctrl; |
16093 | ||
75fa041d CW |
16094 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16095 | DRM_ERROR("failed to read control word\n"); | |
16096 | return -EIO; | |
16097 | } | |
16098 | ||
c0cc8a55 CW |
16099 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16100 | return 0; | |
16101 | ||
28d52043 DA |
16102 | if (state) |
16103 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16104 | else | |
16105 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16106 | |
16107 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16108 | DRM_ERROR("failed to write control word\n"); | |
16109 | return -EIO; | |
16110 | } | |
16111 | ||
28d52043 DA |
16112 | return 0; |
16113 | } | |
c4a1d9e4 | 16114 | |
c4a1d9e4 | 16115 | struct intel_display_error_state { |
ff57f1b0 PZ |
16116 | |
16117 | u32 power_well_driver; | |
16118 | ||
63b66e5b CW |
16119 | int num_transcoders; |
16120 | ||
c4a1d9e4 CW |
16121 | struct intel_cursor_error_state { |
16122 | u32 control; | |
16123 | u32 position; | |
16124 | u32 base; | |
16125 | u32 size; | |
52331309 | 16126 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16127 | |
16128 | struct intel_pipe_error_state { | |
ddf9c536 | 16129 | bool power_domain_on; |
c4a1d9e4 | 16130 | u32 source; |
f301b1e1 | 16131 | u32 stat; |
52331309 | 16132 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16133 | |
16134 | struct intel_plane_error_state { | |
16135 | u32 control; | |
16136 | u32 stride; | |
16137 | u32 size; | |
16138 | u32 pos; | |
16139 | u32 addr; | |
16140 | u32 surface; | |
16141 | u32 tile_offset; | |
52331309 | 16142 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16143 | |
16144 | struct intel_transcoder_error_state { | |
ddf9c536 | 16145 | bool power_domain_on; |
63b66e5b CW |
16146 | enum transcoder cpu_transcoder; |
16147 | ||
16148 | u32 conf; | |
16149 | ||
16150 | u32 htotal; | |
16151 | u32 hblank; | |
16152 | u32 hsync; | |
16153 | u32 vtotal; | |
16154 | u32 vblank; | |
16155 | u32 vsync; | |
16156 | } transcoder[4]; | |
c4a1d9e4 CW |
16157 | }; |
16158 | ||
16159 | struct intel_display_error_state * | |
16160 | intel_display_capture_error_state(struct drm_device *dev) | |
16161 | { | |
fbee40df | 16162 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16163 | struct intel_display_error_state *error; |
63b66e5b CW |
16164 | int transcoders[] = { |
16165 | TRANSCODER_A, | |
16166 | TRANSCODER_B, | |
16167 | TRANSCODER_C, | |
16168 | TRANSCODER_EDP, | |
16169 | }; | |
c4a1d9e4 CW |
16170 | int i; |
16171 | ||
63b66e5b CW |
16172 | if (INTEL_INFO(dev)->num_pipes == 0) |
16173 | return NULL; | |
16174 | ||
9d1cb914 | 16175 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16176 | if (error == NULL) |
16177 | return NULL; | |
16178 | ||
190be112 | 16179 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16180 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16181 | ||
055e393f | 16182 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16183 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16184 | __intel_display_power_is_enabled(dev_priv, |
16185 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16186 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16187 | continue; |
16188 | ||
5efb3e28 VS |
16189 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16190 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16191 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16192 | |
16193 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16194 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16195 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16196 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16197 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16198 | } | |
ca291363 PZ |
16199 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16200 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16201 | if (INTEL_INFO(dev)->gen >= 4) { |
16202 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16203 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16204 | } | |
16205 | ||
c4a1d9e4 | 16206 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16207 | |
3abfce77 | 16208 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16209 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16210 | } |
16211 | ||
4d1de975 | 16212 | /* Note: this does not include DSI transcoders. */ |
63b66e5b | 16213 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
2d1fe073 | 16214 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
16215 | error->num_transcoders++; /* Account for eDP. */ |
16216 | ||
16217 | for (i = 0; i < error->num_transcoders; i++) { | |
16218 | enum transcoder cpu_transcoder = transcoders[i]; | |
16219 | ||
ddf9c536 | 16220 | error->transcoder[i].power_domain_on = |
f458ebbc | 16221 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16222 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16223 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16224 | continue; |
16225 | ||
63b66e5b CW |
16226 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16227 | ||
16228 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16229 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16230 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16231 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16232 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16233 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16234 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16235 | } |
16236 | ||
16237 | return error; | |
16238 | } | |
16239 | ||
edc3d884 MK |
16240 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16241 | ||
c4a1d9e4 | 16242 | void |
edc3d884 | 16243 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16244 | struct drm_device *dev, |
16245 | struct intel_display_error_state *error) | |
16246 | { | |
055e393f | 16247 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16248 | int i; |
16249 | ||
63b66e5b CW |
16250 | if (!error) |
16251 | return; | |
16252 | ||
edc3d884 | 16253 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16254 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16255 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16256 | error->power_well_driver); |
055e393f | 16257 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16258 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16259 | err_printf(m, " Power: %s\n", |
87ad3212 | 16260 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16261 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16262 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16263 | |
16264 | err_printf(m, "Plane [%d]:\n", i); | |
16265 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16266 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16267 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16268 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16269 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16270 | } |
4b71a570 | 16271 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16272 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16273 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16274 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16275 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16276 | } |
16277 | ||
edc3d884 MK |
16278 | err_printf(m, "Cursor [%d]:\n", i); |
16279 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16280 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16281 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16282 | } |
63b66e5b CW |
16283 | |
16284 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16285 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16286 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16287 | err_printf(m, " Power: %s\n", |
87ad3212 | 16288 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16289 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16290 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16291 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16292 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16293 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16294 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16295 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16296 | } | |
c4a1d9e4 | 16297 | } |