]>
Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
57822dc6 | 40 | #include "i915_gem_clflush.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
465c120c | 52 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 53 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
54 | DRM_FORMAT_C8, |
55 | DRM_FORMAT_RGB565, | |
465c120c | 56 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 57 | DRM_FORMAT_XRGB8888, |
465c120c MR |
58 | }; |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 61 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
62 | DRM_FORMAT_C8, |
63 | DRM_FORMAT_RGB565, | |
64 | DRM_FORMAT_XRGB8888, | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_XRGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | }; | |
69 | ||
714244e2 BW |
70 | static const uint64_t i9xx_format_modifiers[] = { |
71 | I915_FORMAT_MOD_X_TILED, | |
72 | DRM_FORMAT_MOD_LINEAR, | |
73 | DRM_FORMAT_MOD_INVALID | |
74 | }; | |
75 | ||
6c0fd451 | 76 | static const uint32_t skl_primary_formats[] = { |
67fe7dc5 DL |
77 | DRM_FORMAT_C8, |
78 | DRM_FORMAT_RGB565, | |
79 | DRM_FORMAT_XRGB8888, | |
465c120c | 80 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 81 | DRM_FORMAT_ARGB8888, |
465c120c MR |
82 | DRM_FORMAT_ABGR8888, |
83 | DRM_FORMAT_XRGB2101010, | |
465c120c | 84 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
85 | DRM_FORMAT_YUYV, |
86 | DRM_FORMAT_YVYU, | |
87 | DRM_FORMAT_UYVY, | |
88 | DRM_FORMAT_VYUY, | |
465c120c MR |
89 | }; |
90 | ||
714244e2 BW |
91 | static const uint64_t skl_format_modifiers_noccs[] = { |
92 | I915_FORMAT_MOD_Yf_TILED, | |
93 | I915_FORMAT_MOD_Y_TILED, | |
94 | I915_FORMAT_MOD_X_TILED, | |
95 | DRM_FORMAT_MOD_LINEAR, | |
96 | DRM_FORMAT_MOD_INVALID | |
97 | }; | |
98 | ||
99 | static const uint64_t skl_format_modifiers_ccs[] = { | |
100 | I915_FORMAT_MOD_Yf_TILED_CCS, | |
101 | I915_FORMAT_MOD_Y_TILED_CCS, | |
102 | I915_FORMAT_MOD_Yf_TILED, | |
103 | I915_FORMAT_MOD_Y_TILED, | |
104 | I915_FORMAT_MOD_X_TILED, | |
105 | DRM_FORMAT_MOD_LINEAR, | |
106 | DRM_FORMAT_MOD_INVALID | |
107 | }; | |
108 | ||
3d7d6510 MR |
109 | /* Cursor formats */ |
110 | static const uint32_t intel_cursor_formats[] = { | |
111 | DRM_FORMAT_ARGB8888, | |
112 | }; | |
113 | ||
714244e2 BW |
114 | static const uint64_t cursor_format_modifiers[] = { |
115 | DRM_FORMAT_MOD_LINEAR, | |
116 | DRM_FORMAT_MOD_INVALID | |
117 | }; | |
118 | ||
f1f644dc | 119 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 120 | struct intel_crtc_state *pipe_config); |
18442d08 | 121 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 122 | struct intel_crtc_state *pipe_config); |
f1f644dc | 123 | |
24dbf51a CW |
124 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
125 | struct drm_i915_gem_object *obj, | |
126 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5b18e57c DV |
127 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
128 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 129 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 130 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
131 | struct intel_link_m_n *m_n, |
132 | struct intel_link_m_n *m2_n2); | |
29407aab | 133 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 134 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 135 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 136 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 137 | const struct intel_crtc_state *pipe_config); |
d288f65f | 138 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 139 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
140 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
141 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
1c74eeaf NM |
142 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
143 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
144 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
145 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
146 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
aecd36b8 VS |
147 | static void intel_modeset_setup_hw_state(struct drm_device *dev, |
148 | struct drm_modeset_acquire_ctx *ctx); | |
2622a081 | 149 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 150 | |
d4906093 | 151 | struct intel_limit { |
4c5def93 ACO |
152 | struct { |
153 | int min, max; | |
154 | } dot, vco, n, m, m1, m2, p, p1; | |
155 | ||
156 | struct { | |
157 | int dot_limit; | |
158 | int p2_slow, p2_fast; | |
159 | } p2; | |
d4906093 | 160 | }; |
79e53945 | 161 | |
bfa7df01 | 162 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 163 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
164 | { |
165 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
166 | ||
167 | /* Obtain SKU information */ | |
168 | mutex_lock(&dev_priv->sb_lock); | |
169 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
170 | CCK_FUSE_HPLL_FREQ_MASK; | |
171 | mutex_unlock(&dev_priv->sb_lock); | |
172 | ||
173 | return vco_freq[hpll_freq] * 1000; | |
174 | } | |
175 | ||
c30fec65 VS |
176 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
177 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
178 | { |
179 | u32 val; | |
180 | int divider; | |
181 | ||
bfa7df01 VS |
182 | mutex_lock(&dev_priv->sb_lock); |
183 | val = vlv_cck_read(dev_priv, reg); | |
184 | mutex_unlock(&dev_priv->sb_lock); | |
185 | ||
186 | divider = val & CCK_FREQUENCY_VALUES; | |
187 | ||
188 | WARN((val & CCK_FREQUENCY_STATUS) != | |
189 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
190 | "%s change in progress\n", name); | |
191 | ||
c30fec65 VS |
192 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
193 | } | |
194 | ||
7ff89ca2 VS |
195 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
196 | const char *name, u32 reg) | |
c30fec65 VS |
197 | { |
198 | if (dev_priv->hpll_freq == 0) | |
49cd97a3 | 199 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 VS |
200 | |
201 | return vlv_get_cck_clock(dev_priv, name, reg, | |
202 | dev_priv->hpll_freq); | |
bfa7df01 VS |
203 | } |
204 | ||
bfa7df01 VS |
205 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
206 | { | |
666a4537 | 207 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
208 | return; |
209 | ||
210 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
211 | CCK_CZ_CLOCK_CONTROL); | |
212 | ||
213 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
214 | } | |
215 | ||
021357ac | 216 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
217 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
218 | const struct intel_crtc_state *pipe_config) | |
021357ac | 219 | { |
21a727b3 VS |
220 | if (HAS_DDI(dev_priv)) |
221 | return pipe_config->port_clock; /* SPLL */ | |
222 | else if (IS_GEN5(dev_priv)) | |
223 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 224 | else |
21a727b3 | 225 | return 270000; |
021357ac CW |
226 | } |
227 | ||
1b6f4958 | 228 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 229 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 230 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 231 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
232 | .m = { .min = 96, .max = 140 }, |
233 | .m1 = { .min = 18, .max = 26 }, | |
234 | .m2 = { .min = 6, .max = 16 }, | |
235 | .p = { .min = 4, .max = 128 }, | |
236 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
237 | .p2 = { .dot_limit = 165000, |
238 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
239 | }; |
240 | ||
1b6f4958 | 241 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 242 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 243 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 244 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
245 | .m = { .min = 96, .max = 140 }, |
246 | .m1 = { .min = 18, .max = 26 }, | |
247 | .m2 = { .min = 6, .max = 16 }, | |
248 | .p = { .min = 4, .max = 128 }, | |
249 | .p1 = { .min = 2, .max = 33 }, | |
250 | .p2 = { .dot_limit = 165000, | |
251 | .p2_slow = 4, .p2_fast = 4 }, | |
252 | }; | |
253 | ||
1b6f4958 | 254 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 255 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 256 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 257 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
258 | .m = { .min = 96, .max = 140 }, |
259 | .m1 = { .min = 18, .max = 26 }, | |
260 | .m2 = { .min = 6, .max = 16 }, | |
261 | .p = { .min = 4, .max = 128 }, | |
262 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
263 | .p2 = { .dot_limit = 165000, |
264 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 265 | }; |
273e27ca | 266 | |
1b6f4958 | 267 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
268 | .dot = { .min = 20000, .max = 400000 }, |
269 | .vco = { .min = 1400000, .max = 2800000 }, | |
270 | .n = { .min = 1, .max = 6 }, | |
271 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
272 | .m1 = { .min = 8, .max = 18 }, |
273 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
274 | .p = { .min = 5, .max = 80 }, |
275 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
276 | .p2 = { .dot_limit = 200000, |
277 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
278 | }; |
279 | ||
1b6f4958 | 280 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
281 | .dot = { .min = 20000, .max = 400000 }, |
282 | .vco = { .min = 1400000, .max = 2800000 }, | |
283 | .n = { .min = 1, .max = 6 }, | |
284 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
285 | .m1 = { .min = 8, .max = 18 }, |
286 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
287 | .p = { .min = 7, .max = 98 }, |
288 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
289 | .p2 = { .dot_limit = 112000, |
290 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
291 | }; |
292 | ||
273e27ca | 293 | |
1b6f4958 | 294 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
295 | .dot = { .min = 25000, .max = 270000 }, |
296 | .vco = { .min = 1750000, .max = 3500000}, | |
297 | .n = { .min = 1, .max = 4 }, | |
298 | .m = { .min = 104, .max = 138 }, | |
299 | .m1 = { .min = 17, .max = 23 }, | |
300 | .m2 = { .min = 5, .max = 11 }, | |
301 | .p = { .min = 10, .max = 30 }, | |
302 | .p1 = { .min = 1, .max = 3}, | |
303 | .p2 = { .dot_limit = 270000, | |
304 | .p2_slow = 10, | |
305 | .p2_fast = 10 | |
044c7c41 | 306 | }, |
e4b36699 KP |
307 | }; |
308 | ||
1b6f4958 | 309 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
310 | .dot = { .min = 22000, .max = 400000 }, |
311 | .vco = { .min = 1750000, .max = 3500000}, | |
312 | .n = { .min = 1, .max = 4 }, | |
313 | .m = { .min = 104, .max = 138 }, | |
314 | .m1 = { .min = 16, .max = 23 }, | |
315 | .m2 = { .min = 5, .max = 11 }, | |
316 | .p = { .min = 5, .max = 80 }, | |
317 | .p1 = { .min = 1, .max = 8}, | |
318 | .p2 = { .dot_limit = 165000, | |
319 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
320 | }; |
321 | ||
1b6f4958 | 322 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
323 | .dot = { .min = 20000, .max = 115000 }, |
324 | .vco = { .min = 1750000, .max = 3500000 }, | |
325 | .n = { .min = 1, .max = 3 }, | |
326 | .m = { .min = 104, .max = 138 }, | |
327 | .m1 = { .min = 17, .max = 23 }, | |
328 | .m2 = { .min = 5, .max = 11 }, | |
329 | .p = { .min = 28, .max = 112 }, | |
330 | .p1 = { .min = 2, .max = 8 }, | |
331 | .p2 = { .dot_limit = 0, | |
332 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 333 | }, |
e4b36699 KP |
334 | }; |
335 | ||
1b6f4958 | 336 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
337 | .dot = { .min = 80000, .max = 224000 }, |
338 | .vco = { .min = 1750000, .max = 3500000 }, | |
339 | .n = { .min = 1, .max = 3 }, | |
340 | .m = { .min = 104, .max = 138 }, | |
341 | .m1 = { .min = 17, .max = 23 }, | |
342 | .m2 = { .min = 5, .max = 11 }, | |
343 | .p = { .min = 14, .max = 42 }, | |
344 | .p1 = { .min = 2, .max = 6 }, | |
345 | .p2 = { .dot_limit = 0, | |
346 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 347 | }, |
e4b36699 KP |
348 | }; |
349 | ||
1b6f4958 | 350 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
351 | .dot = { .min = 20000, .max = 400000}, |
352 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 353 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
354 | .n = { .min = 3, .max = 6 }, |
355 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 356 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
357 | .m1 = { .min = 0, .max = 0 }, |
358 | .m2 = { .min = 0, .max = 254 }, | |
359 | .p = { .min = 5, .max = 80 }, | |
360 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
361 | .p2 = { .dot_limit = 200000, |
362 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
363 | }; |
364 | ||
1b6f4958 | 365 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
366 | .dot = { .min = 20000, .max = 400000 }, |
367 | .vco = { .min = 1700000, .max = 3500000 }, | |
368 | .n = { .min = 3, .max = 6 }, | |
369 | .m = { .min = 2, .max = 256 }, | |
370 | .m1 = { .min = 0, .max = 0 }, | |
371 | .m2 = { .min = 0, .max = 254 }, | |
372 | .p = { .min = 7, .max = 112 }, | |
373 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
374 | .p2 = { .dot_limit = 112000, |
375 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
376 | }; |
377 | ||
273e27ca EA |
378 | /* Ironlake / Sandybridge |
379 | * | |
380 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
381 | * the range value for them is (actual_value - 2). | |
382 | */ | |
1b6f4958 | 383 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
384 | .dot = { .min = 25000, .max = 350000 }, |
385 | .vco = { .min = 1760000, .max = 3510000 }, | |
386 | .n = { .min = 1, .max = 5 }, | |
387 | .m = { .min = 79, .max = 127 }, | |
388 | .m1 = { .min = 12, .max = 22 }, | |
389 | .m2 = { .min = 5, .max = 9 }, | |
390 | .p = { .min = 5, .max = 80 }, | |
391 | .p1 = { .min = 1, .max = 8 }, | |
392 | .p2 = { .dot_limit = 225000, | |
393 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
394 | }; |
395 | ||
1b6f4958 | 396 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
397 | .dot = { .min = 25000, .max = 350000 }, |
398 | .vco = { .min = 1760000, .max = 3510000 }, | |
399 | .n = { .min = 1, .max = 3 }, | |
400 | .m = { .min = 79, .max = 118 }, | |
401 | .m1 = { .min = 12, .max = 22 }, | |
402 | .m2 = { .min = 5, .max = 9 }, | |
403 | .p = { .min = 28, .max = 112 }, | |
404 | .p1 = { .min = 2, .max = 8 }, | |
405 | .p2 = { .dot_limit = 225000, | |
406 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
407 | }; |
408 | ||
1b6f4958 | 409 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
410 | .dot = { .min = 25000, .max = 350000 }, |
411 | .vco = { .min = 1760000, .max = 3510000 }, | |
412 | .n = { .min = 1, .max = 3 }, | |
413 | .m = { .min = 79, .max = 127 }, | |
414 | .m1 = { .min = 12, .max = 22 }, | |
415 | .m2 = { .min = 5, .max = 9 }, | |
416 | .p = { .min = 14, .max = 56 }, | |
417 | .p1 = { .min = 2, .max = 8 }, | |
418 | .p2 = { .dot_limit = 225000, | |
419 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
420 | }; |
421 | ||
273e27ca | 422 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 423 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
424 | .dot = { .min = 25000, .max = 350000 }, |
425 | .vco = { .min = 1760000, .max = 3510000 }, | |
426 | .n = { .min = 1, .max = 2 }, | |
427 | .m = { .min = 79, .max = 126 }, | |
428 | .m1 = { .min = 12, .max = 22 }, | |
429 | .m2 = { .min = 5, .max = 9 }, | |
430 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 431 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
432 | .p2 = { .dot_limit = 225000, |
433 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
434 | }; |
435 | ||
1b6f4958 | 436 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
437 | .dot = { .min = 25000, .max = 350000 }, |
438 | .vco = { .min = 1760000, .max = 3510000 }, | |
439 | .n = { .min = 1, .max = 3 }, | |
440 | .m = { .min = 79, .max = 126 }, | |
441 | .m1 = { .min = 12, .max = 22 }, | |
442 | .m2 = { .min = 5, .max = 9 }, | |
443 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 444 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
445 | .p2 = { .dot_limit = 225000, |
446 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
447 | }; |
448 | ||
1b6f4958 | 449 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
450 | /* |
451 | * These are the data rate limits (measured in fast clocks) | |
452 | * since those are the strictest limits we have. The fast | |
453 | * clock and actual rate limits are more relaxed, so checking | |
454 | * them would make no difference. | |
455 | */ | |
456 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 457 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 458 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
459 | .m1 = { .min = 2, .max = 3 }, |
460 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 461 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 462 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
463 | }; |
464 | ||
1b6f4958 | 465 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
466 | /* |
467 | * These are the data rate limits (measured in fast clocks) | |
468 | * since those are the strictest limits we have. The fast | |
469 | * clock and actual rate limits are more relaxed, so checking | |
470 | * them would make no difference. | |
471 | */ | |
472 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 473 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
474 | .n = { .min = 1, .max = 1 }, |
475 | .m1 = { .min = 2, .max = 2 }, | |
476 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
477 | .p1 = { .min = 2, .max = 4 }, | |
478 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
479 | }; | |
480 | ||
1b6f4958 | 481 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
482 | /* FIXME: find real dot limits */ |
483 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 484 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
485 | .n = { .min = 1, .max = 1 }, |
486 | .m1 = { .min = 2, .max = 2 }, | |
487 | /* FIXME: find real m2 limits */ | |
488 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
489 | .p1 = { .min = 2, .max = 4 }, | |
490 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
491 | }; | |
492 | ||
cdba954e ACO |
493 | static bool |
494 | needs_modeset(struct drm_crtc_state *state) | |
495 | { | |
fc596660 | 496 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
497 | } |
498 | ||
dccbea3b ID |
499 | /* |
500 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
501 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
502 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
503 | * The helpers' return value is the rate of the clock that is fed to the | |
504 | * display engine's pipe which can be the above fast dot clock rate or a | |
505 | * divided-down version of it. | |
506 | */ | |
f2b115e6 | 507 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 508 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 509 | { |
2177832f SL |
510 | clock->m = clock->m2 + 2; |
511 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 512 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 513 | return 0; |
fb03ac01 VS |
514 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
515 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
516 | |
517 | return clock->dot; | |
2177832f SL |
518 | } |
519 | ||
7429e9d4 DV |
520 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
521 | { | |
522 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
523 | } | |
524 | ||
9e2c8475 | 525 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 526 | { |
7429e9d4 | 527 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 528 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 529 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 530 | return 0; |
fb03ac01 VS |
531 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
532 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
533 | |
534 | return clock->dot; | |
79e53945 JB |
535 | } |
536 | ||
9e2c8475 | 537 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
538 | { |
539 | clock->m = clock->m1 * clock->m2; | |
540 | clock->p = clock->p1 * clock->p2; | |
541 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 542 | return 0; |
589eca67 ID |
543 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
544 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
545 | |
546 | return clock->dot / 5; | |
589eca67 ID |
547 | } |
548 | ||
9e2c8475 | 549 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
550 | { |
551 | clock->m = clock->m1 * clock->m2; | |
552 | clock->p = clock->p1 * clock->p2; | |
553 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 554 | return 0; |
ef9348c8 CML |
555 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
556 | clock->n << 22); | |
557 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
558 | |
559 | return clock->dot / 5; | |
ef9348c8 CML |
560 | } |
561 | ||
7c04d1d9 | 562 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
563 | /** |
564 | * Returns whether the given set of divisors are valid for a given refclk with | |
565 | * the given connectors. | |
566 | */ | |
567 | ||
e2d214ae | 568 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 569 | const struct intel_limit *limit, |
9e2c8475 | 570 | const struct dpll *clock) |
79e53945 | 571 | { |
f01b7962 VS |
572 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
573 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 574 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 575 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 576 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 577 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 578 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 579 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 580 | |
e2d214ae | 581 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 582 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
583 | if (clock->m1 <= clock->m2) |
584 | INTELPllInvalid("m1 <= m2\n"); | |
585 | ||
e2d214ae | 586 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 587 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
588 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
589 | INTELPllInvalid("p out of range\n"); | |
590 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
591 | INTELPllInvalid("m out of range\n"); | |
592 | } | |
593 | ||
79e53945 | 594 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 595 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
596 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
597 | * connector, etc., rather than just a single range. | |
598 | */ | |
599 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 600 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
601 | |
602 | return true; | |
603 | } | |
604 | ||
3b1429d9 | 605 | static int |
1b6f4958 | 606 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
607 | const struct intel_crtc_state *crtc_state, |
608 | int target) | |
79e53945 | 609 | { |
3b1429d9 | 610 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 611 | |
2d84d2b3 | 612 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 613 | /* |
a210b028 DV |
614 | * For LVDS just rely on its current settings for dual-channel. |
615 | * We haven't figured out how to reliably set up different | |
616 | * single/dual channel state, if we even can. | |
79e53945 | 617 | */ |
1974cad0 | 618 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 619 | return limit->p2.p2_fast; |
79e53945 | 620 | else |
3b1429d9 | 621 | return limit->p2.p2_slow; |
79e53945 JB |
622 | } else { |
623 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 624 | return limit->p2.p2_slow; |
79e53945 | 625 | else |
3b1429d9 | 626 | return limit->p2.p2_fast; |
79e53945 | 627 | } |
3b1429d9 VS |
628 | } |
629 | ||
70e8aa21 ACO |
630 | /* |
631 | * Returns a set of divisors for the desired target clock with the given | |
632 | * refclk, or FALSE. The returned values represent the clock equation: | |
633 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
634 | * | |
635 | * Target and reference clocks are specified in kHz. | |
636 | * | |
637 | * If match_clock is provided, then best_clock P divider must match the P | |
638 | * divider from @match_clock used for LVDS downclocking. | |
639 | */ | |
3b1429d9 | 640 | static bool |
1b6f4958 | 641 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 642 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
643 | int target, int refclk, struct dpll *match_clock, |
644 | struct dpll *best_clock) | |
3b1429d9 VS |
645 | { |
646 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 647 | struct dpll clock; |
3b1429d9 | 648 | int err = target; |
79e53945 | 649 | |
0206e353 | 650 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 651 | |
3b1429d9 VS |
652 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
653 | ||
42158660 ZY |
654 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
655 | clock.m1++) { | |
656 | for (clock.m2 = limit->m2.min; | |
657 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 658 | if (clock.m2 >= clock.m1) |
42158660 ZY |
659 | break; |
660 | for (clock.n = limit->n.min; | |
661 | clock.n <= limit->n.max; clock.n++) { | |
662 | for (clock.p1 = limit->p1.min; | |
663 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
664 | int this_err; |
665 | ||
dccbea3b | 666 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
667 | if (!intel_PLL_is_valid(to_i915(dev), |
668 | limit, | |
ac58c3f0 DV |
669 | &clock)) |
670 | continue; | |
671 | if (match_clock && | |
672 | clock.p != match_clock->p) | |
673 | continue; | |
674 | ||
675 | this_err = abs(clock.dot - target); | |
676 | if (this_err < err) { | |
677 | *best_clock = clock; | |
678 | err = this_err; | |
679 | } | |
680 | } | |
681 | } | |
682 | } | |
683 | } | |
684 | ||
685 | return (err != target); | |
686 | } | |
687 | ||
70e8aa21 ACO |
688 | /* |
689 | * Returns a set of divisors for the desired target clock with the given | |
690 | * refclk, or FALSE. The returned values represent the clock equation: | |
691 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
692 | * | |
693 | * Target and reference clocks are specified in kHz. | |
694 | * | |
695 | * If match_clock is provided, then best_clock P divider must match the P | |
696 | * divider from @match_clock used for LVDS downclocking. | |
697 | */ | |
ac58c3f0 | 698 | static bool |
1b6f4958 | 699 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 700 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
701 | int target, int refclk, struct dpll *match_clock, |
702 | struct dpll *best_clock) | |
79e53945 | 703 | { |
3b1429d9 | 704 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 705 | struct dpll clock; |
79e53945 JB |
706 | int err = target; |
707 | ||
0206e353 | 708 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 709 | |
3b1429d9 VS |
710 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
711 | ||
42158660 ZY |
712 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
713 | clock.m1++) { | |
714 | for (clock.m2 = limit->m2.min; | |
715 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
716 | for (clock.n = limit->n.min; |
717 | clock.n <= limit->n.max; clock.n++) { | |
718 | for (clock.p1 = limit->p1.min; | |
719 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
720 | int this_err; |
721 | ||
dccbea3b | 722 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
723 | if (!intel_PLL_is_valid(to_i915(dev), |
724 | limit, | |
1b894b59 | 725 | &clock)) |
79e53945 | 726 | continue; |
cec2f356 SP |
727 | if (match_clock && |
728 | clock.p != match_clock->p) | |
729 | continue; | |
79e53945 JB |
730 | |
731 | this_err = abs(clock.dot - target); | |
732 | if (this_err < err) { | |
733 | *best_clock = clock; | |
734 | err = this_err; | |
735 | } | |
736 | } | |
737 | } | |
738 | } | |
739 | } | |
740 | ||
741 | return (err != target); | |
742 | } | |
743 | ||
997c030c ACO |
744 | /* |
745 | * Returns a set of divisors for the desired target clock with the given | |
746 | * refclk, or FALSE. The returned values represent the clock equation: | |
747 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
748 | * |
749 | * Target and reference clocks are specified in kHz. | |
750 | * | |
751 | * If match_clock is provided, then best_clock P divider must match the P | |
752 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 753 | */ |
d4906093 | 754 | static bool |
1b6f4958 | 755 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 756 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
757 | int target, int refclk, struct dpll *match_clock, |
758 | struct dpll *best_clock) | |
d4906093 | 759 | { |
3b1429d9 | 760 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 761 | struct dpll clock; |
d4906093 | 762 | int max_n; |
3b1429d9 | 763 | bool found = false; |
6ba770dc AJ |
764 | /* approximately equals target * 0.00585 */ |
765 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
766 | |
767 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
768 | |
769 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
770 | ||
d4906093 | 771 | max_n = limit->n.max; |
f77f13e2 | 772 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 773 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 774 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
775 | for (clock.m1 = limit->m1.max; |
776 | clock.m1 >= limit->m1.min; clock.m1--) { | |
777 | for (clock.m2 = limit->m2.max; | |
778 | clock.m2 >= limit->m2.min; clock.m2--) { | |
779 | for (clock.p1 = limit->p1.max; | |
780 | clock.p1 >= limit->p1.min; clock.p1--) { | |
781 | int this_err; | |
782 | ||
dccbea3b | 783 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
784 | if (!intel_PLL_is_valid(to_i915(dev), |
785 | limit, | |
1b894b59 | 786 | &clock)) |
d4906093 | 787 | continue; |
1b894b59 CW |
788 | |
789 | this_err = abs(clock.dot - target); | |
d4906093 ML |
790 | if (this_err < err_most) { |
791 | *best_clock = clock; | |
792 | err_most = this_err; | |
793 | max_n = clock.n; | |
794 | found = true; | |
795 | } | |
796 | } | |
797 | } | |
798 | } | |
799 | } | |
2c07245f ZW |
800 | return found; |
801 | } | |
802 | ||
d5dd62bd ID |
803 | /* |
804 | * Check if the calculated PLL configuration is more optimal compared to the | |
805 | * best configuration and error found so far. Return the calculated error. | |
806 | */ | |
807 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
808 | const struct dpll *calculated_clock, |
809 | const struct dpll *best_clock, | |
d5dd62bd ID |
810 | unsigned int best_error_ppm, |
811 | unsigned int *error_ppm) | |
812 | { | |
9ca3ba01 ID |
813 | /* |
814 | * For CHV ignore the error and consider only the P value. | |
815 | * Prefer a bigger P value based on HW requirements. | |
816 | */ | |
920a14b2 | 817 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
818 | *error_ppm = 0; |
819 | ||
820 | return calculated_clock->p > best_clock->p; | |
821 | } | |
822 | ||
24be4e46 ID |
823 | if (WARN_ON_ONCE(!target_freq)) |
824 | return false; | |
825 | ||
d5dd62bd ID |
826 | *error_ppm = div_u64(1000000ULL * |
827 | abs(target_freq - calculated_clock->dot), | |
828 | target_freq); | |
829 | /* | |
830 | * Prefer a better P value over a better (smaller) error if the error | |
831 | * is small. Ensure this preference for future configurations too by | |
832 | * setting the error to 0. | |
833 | */ | |
834 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
835 | *error_ppm = 0; | |
836 | ||
837 | return true; | |
838 | } | |
839 | ||
840 | return *error_ppm + 10 < best_error_ppm; | |
841 | } | |
842 | ||
65b3d6a9 ACO |
843 | /* |
844 | * Returns a set of divisors for the desired target clock with the given | |
845 | * refclk, or FALSE. The returned values represent the clock equation: | |
846 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
847 | */ | |
a0c4da24 | 848 | static bool |
1b6f4958 | 849 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 850 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
851 | int target, int refclk, struct dpll *match_clock, |
852 | struct dpll *best_clock) | |
a0c4da24 | 853 | { |
a93e255f | 854 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 855 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 856 | struct dpll clock; |
69e4f900 | 857 | unsigned int bestppm = 1000000; |
27e639bf VS |
858 | /* min update 19.2 MHz */ |
859 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 860 | bool found = false; |
a0c4da24 | 861 | |
6b4bf1c4 VS |
862 | target *= 5; /* fast clock */ |
863 | ||
864 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
865 | |
866 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 867 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 868 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 869 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 870 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 871 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 872 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 873 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 874 | unsigned int ppm; |
69e4f900 | 875 | |
6b4bf1c4 VS |
876 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
877 | refclk * clock.m1); | |
878 | ||
dccbea3b | 879 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 880 | |
e2d214ae TU |
881 | if (!intel_PLL_is_valid(to_i915(dev), |
882 | limit, | |
f01b7962 | 883 | &clock)) |
43b0ac53 VS |
884 | continue; |
885 | ||
d5dd62bd ID |
886 | if (!vlv_PLL_is_optimal(dev, target, |
887 | &clock, | |
888 | best_clock, | |
889 | bestppm, &ppm)) | |
890 | continue; | |
6b4bf1c4 | 891 | |
d5dd62bd ID |
892 | *best_clock = clock; |
893 | bestppm = ppm; | |
894 | found = true; | |
a0c4da24 JB |
895 | } |
896 | } | |
897 | } | |
898 | } | |
a0c4da24 | 899 | |
49e497ef | 900 | return found; |
a0c4da24 | 901 | } |
a4fc5ed6 | 902 | |
65b3d6a9 ACO |
903 | /* |
904 | * Returns a set of divisors for the desired target clock with the given | |
905 | * refclk, or FALSE. The returned values represent the clock equation: | |
906 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
907 | */ | |
ef9348c8 | 908 | static bool |
1b6f4958 | 909 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 910 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
911 | int target, int refclk, struct dpll *match_clock, |
912 | struct dpll *best_clock) | |
ef9348c8 | 913 | { |
a93e255f | 914 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 915 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 916 | unsigned int best_error_ppm; |
9e2c8475 | 917 | struct dpll clock; |
ef9348c8 CML |
918 | uint64_t m2; |
919 | int found = false; | |
920 | ||
921 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 922 | best_error_ppm = 1000000; |
ef9348c8 CML |
923 | |
924 | /* | |
925 | * Based on hardware doc, the n always set to 1, and m1 always | |
926 | * set to 2. If requires to support 200Mhz refclk, we need to | |
927 | * revisit this because n may not 1 anymore. | |
928 | */ | |
929 | clock.n = 1, clock.m1 = 2; | |
930 | target *= 5; /* fast clock */ | |
931 | ||
932 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
933 | for (clock.p2 = limit->p2.p2_fast; | |
934 | clock.p2 >= limit->p2.p2_slow; | |
935 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 936 | unsigned int error_ppm; |
ef9348c8 CML |
937 | |
938 | clock.p = clock.p1 * clock.p2; | |
939 | ||
940 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
941 | clock.n) << 22, refclk * clock.m1); | |
942 | ||
943 | if (m2 > INT_MAX/clock.m1) | |
944 | continue; | |
945 | ||
946 | clock.m2 = m2; | |
947 | ||
dccbea3b | 948 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 949 | |
e2d214ae | 950 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
951 | continue; |
952 | ||
9ca3ba01 ID |
953 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
954 | best_error_ppm, &error_ppm)) | |
955 | continue; | |
956 | ||
957 | *best_clock = clock; | |
958 | best_error_ppm = error_ppm; | |
959 | found = true; | |
ef9348c8 CML |
960 | } |
961 | } | |
962 | ||
963 | return found; | |
964 | } | |
965 | ||
5ab7b0b7 | 966 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 967 | struct dpll *best_clock) |
5ab7b0b7 | 968 | { |
65b3d6a9 | 969 | int refclk = 100000; |
1b6f4958 | 970 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 971 | |
65b3d6a9 | 972 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
973 | target_clock, refclk, NULL, best_clock); |
974 | } | |
975 | ||
525b9311 | 976 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 977 | { |
20ddf665 VS |
978 | /* Be paranoid as we can arrive here with only partial |
979 | * state retrieved from the hardware during setup. | |
980 | * | |
241bfc38 | 981 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
982 | * as Haswell has gained clock readout/fastboot support. |
983 | * | |
66e514c1 | 984 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 985 | * properly reconstruct framebuffers. |
c3d1f436 MR |
986 | * |
987 | * FIXME: The intel_crtc->active here should be switched to | |
988 | * crtc->state->active once we have proper CRTC states wired up | |
989 | * for atomic. | |
20ddf665 | 990 | */ |
525b9311 VS |
991 | return crtc->active && crtc->base.primary->state->fb && |
992 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
993 | } |
994 | ||
a5c961d1 PZ |
995 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
996 | enum pipe pipe) | |
997 | { | |
98187836 | 998 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 999 | |
e2af48c6 | 1000 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1001 | } |
1002 | ||
6315b5d3 | 1003 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 1004 | { |
f0f59a00 | 1005 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1006 | u32 line1, line2; |
1007 | u32 line_mask; | |
1008 | ||
5db94019 | 1009 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
1010 | line_mask = DSL_LINEMASK_GEN2; |
1011 | else | |
1012 | line_mask = DSL_LINEMASK_GEN3; | |
1013 | ||
1014 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1015 | msleep(5); |
fbf49ea2 VS |
1016 | line2 = I915_READ(reg) & line_mask; |
1017 | ||
1018 | return line1 == line2; | |
1019 | } | |
1020 | ||
ab7ad7f6 KP |
1021 | /* |
1022 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1023 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1024 | * |
1025 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1026 | * spinning on the vblank interrupt status bit, since we won't actually | |
1027 | * see an interrupt when the pipe is disabled. | |
1028 | * | |
ab7ad7f6 KP |
1029 | * On Gen4 and above: |
1030 | * wait for the pipe register state bit to turn off | |
1031 | * | |
1032 | * Otherwise: | |
1033 | * wait for the display line value to settle (it usually | |
1034 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1035 | * |
9d0498a2 | 1036 | */ |
575f7ab7 | 1037 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1038 | { |
6315b5d3 | 1039 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1040 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1041 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1042 | |
6315b5d3 | 1043 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1044 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1045 | |
1046 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1047 | if (intel_wait_for_register(dev_priv, |
1048 | reg, I965_PIPECONF_ACTIVE, 0, | |
1049 | 100)) | |
284637d9 | 1050 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1051 | } else { |
ab7ad7f6 | 1052 | /* Wait for the display line to settle */ |
6315b5d3 | 1053 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1054 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1055 | } |
79e53945 JB |
1056 | } |
1057 | ||
b24e7179 | 1058 | /* Only for pre-ILK configs */ |
55607e8a DV |
1059 | void assert_pll(struct drm_i915_private *dev_priv, |
1060 | enum pipe pipe, bool state) | |
b24e7179 | 1061 | { |
b24e7179 JB |
1062 | u32 val; |
1063 | bool cur_state; | |
1064 | ||
649636ef | 1065 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1066 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1067 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1068 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1069 | onoff(state), onoff(cur_state)); |
b24e7179 | 1070 | } |
b24e7179 | 1071 | |
23538ef1 | 1072 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1073 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1074 | { |
1075 | u32 val; | |
1076 | bool cur_state; | |
1077 | ||
a580516d | 1078 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1079 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1080 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1081 | |
1082 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1083 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1084 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1085 | onoff(state), onoff(cur_state)); |
23538ef1 | 1086 | } |
23538ef1 | 1087 | |
040484af JB |
1088 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1089 | enum pipe pipe, bool state) | |
1090 | { | |
040484af | 1091 | bool cur_state; |
ad80a810 PZ |
1092 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1093 | pipe); | |
040484af | 1094 | |
2d1fe073 | 1095 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1096 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1097 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1098 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1099 | } else { |
649636ef | 1100 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1101 | cur_state = !!(val & FDI_TX_ENABLE); |
1102 | } | |
e2c719b7 | 1103 | I915_STATE_WARN(cur_state != state, |
040484af | 1104 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1105 | onoff(state), onoff(cur_state)); |
040484af JB |
1106 | } |
1107 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1108 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1109 | ||
1110 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1111 | enum pipe pipe, bool state) | |
1112 | { | |
040484af JB |
1113 | u32 val; |
1114 | bool cur_state; | |
1115 | ||
649636ef | 1116 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1117 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1118 | I915_STATE_WARN(cur_state != state, |
040484af | 1119 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1120 | onoff(state), onoff(cur_state)); |
040484af JB |
1121 | } |
1122 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1123 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1124 | ||
1125 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1126 | enum pipe pipe) | |
1127 | { | |
040484af JB |
1128 | u32 val; |
1129 | ||
1130 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1131 | if (IS_GEN5(dev_priv)) |
040484af JB |
1132 | return; |
1133 | ||
bf507ef7 | 1134 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1135 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1136 | return; |
1137 | ||
649636ef | 1138 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1139 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1140 | } |
1141 | ||
55607e8a DV |
1142 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1143 | enum pipe pipe, bool state) | |
040484af | 1144 | { |
040484af | 1145 | u32 val; |
55607e8a | 1146 | bool cur_state; |
040484af | 1147 | |
649636ef | 1148 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1149 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1150 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1151 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1152 | onoff(state), onoff(cur_state)); |
040484af JB |
1153 | } |
1154 | ||
4f8036a2 | 1155 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1156 | { |
f0f59a00 | 1157 | i915_reg_t pp_reg; |
ea0760cf JB |
1158 | u32 val; |
1159 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1160 | bool locked = true; |
ea0760cf | 1161 | |
4f8036a2 | 1162 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1163 | return; |
1164 | ||
4f8036a2 | 1165 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1166 | u32 port_sel; |
1167 | ||
44cb734c ID |
1168 | pp_reg = PP_CONTROL(0); |
1169 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1170 | |
1171 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1172 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1173 | panel_pipe = PIPE_B; | |
1174 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1175 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1176 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1177 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1178 | panel_pipe = pipe; |
ea0760cf | 1179 | } else { |
44cb734c | 1180 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1181 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1182 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1183 | } |
1184 | ||
1185 | val = I915_READ(pp_reg); | |
1186 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1187 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1188 | locked = false; |
1189 | ||
e2c719b7 | 1190 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1191 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1192 | pipe_name(pipe)); |
ea0760cf JB |
1193 | } |
1194 | ||
93ce0ba6 JN |
1195 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1196 | enum pipe pipe, bool state) | |
1197 | { | |
93ce0ba6 JN |
1198 | bool cur_state; |
1199 | ||
2a307c2e | 1200 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1201 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1202 | else |
5efb3e28 | 1203 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1204 | |
e2c719b7 | 1205 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1206 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1207 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1208 | } |
1209 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1210 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1211 | ||
b840d907 JB |
1212 | void assert_pipe(struct drm_i915_private *dev_priv, |
1213 | enum pipe pipe, bool state) | |
b24e7179 | 1214 | { |
63d7bbe9 | 1215 | bool cur_state; |
702e7a56 PZ |
1216 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1217 | pipe); | |
4feed0eb | 1218 | enum intel_display_power_domain power_domain; |
b24e7179 | 1219 | |
e56134bc VS |
1220 | /* we keep both pipes enabled on 830 */ |
1221 | if (IS_I830(dev_priv)) | |
8e636784 DV |
1222 | state = true; |
1223 | ||
4feed0eb ID |
1224 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1225 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1226 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1227 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1228 | |
1229 | intel_display_power_put(dev_priv, power_domain); | |
1230 | } else { | |
1231 | cur_state = false; | |
69310161 PZ |
1232 | } |
1233 | ||
e2c719b7 | 1234 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1235 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1236 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1237 | } |
1238 | ||
931872fc CW |
1239 | static void assert_plane(struct drm_i915_private *dev_priv, |
1240 | enum plane plane, bool state) | |
b24e7179 | 1241 | { |
b24e7179 | 1242 | u32 val; |
931872fc | 1243 | bool cur_state; |
b24e7179 | 1244 | |
649636ef | 1245 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1246 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1247 | I915_STATE_WARN(cur_state != state, |
931872fc | 1248 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1249 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1250 | } |
1251 | ||
931872fc CW |
1252 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1253 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1254 | ||
b24e7179 JB |
1255 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1256 | enum pipe pipe) | |
1257 | { | |
649636ef | 1258 | int i; |
b24e7179 | 1259 | |
653e1026 | 1260 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1261 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1262 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1263 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1264 | "plane %c assertion failure, should be disabled but not\n", |
1265 | plane_name(pipe)); | |
19ec1358 | 1266 | return; |
28c05794 | 1267 | } |
19ec1358 | 1268 | |
b24e7179 | 1269 | /* Need to check both planes against the pipe */ |
055e393f | 1270 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1271 | u32 val = I915_READ(DSPCNTR(i)); |
1272 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1273 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1274 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1275 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1276 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1277 | } |
1278 | } | |
1279 | ||
19332d7a JB |
1280 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1281 | enum pipe pipe) | |
1282 | { | |
649636ef | 1283 | int sprite; |
19332d7a | 1284 | |
6315b5d3 | 1285 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1286 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1287 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1288 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1289 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1290 | sprite, pipe_name(pipe)); | |
1291 | } | |
920a14b2 | 1292 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1293 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1294 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1295 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1296 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1297 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1298 | } |
6315b5d3 | 1299 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1300 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1301 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1302 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1303 | plane_name(pipe), pipe_name(pipe)); |
ab33081a | 1304 | } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
649636ef | 1305 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1306 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1307 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1308 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1309 | } |
1310 | } | |
1311 | ||
08c71e5e VS |
1312 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1313 | { | |
e2c719b7 | 1314 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1315 | drm_crtc_vblank_put(crtc); |
1316 | } | |
1317 | ||
7abd4b35 ACO |
1318 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1319 | enum pipe pipe) | |
92f2584a | 1320 | { |
92f2584a JB |
1321 | u32 val; |
1322 | bool enabled; | |
1323 | ||
649636ef | 1324 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1325 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1326 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1327 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1328 | pipe_name(pipe)); | |
92f2584a JB |
1329 | } |
1330 | ||
4e634389 KP |
1331 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1332 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1333 | { |
1334 | if ((val & DP_PORT_EN) == 0) | |
1335 | return false; | |
1336 | ||
2d1fe073 | 1337 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1338 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1339 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1340 | return false; | |
2d1fe073 | 1341 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1342 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1343 | return false; | |
f0575e92 KP |
1344 | } else { |
1345 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1346 | return false; | |
1347 | } | |
1348 | return true; | |
1349 | } | |
1350 | ||
1519b995 KP |
1351 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1352 | enum pipe pipe, u32 val) | |
1353 | { | |
dc0fa718 | 1354 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1355 | return false; |
1356 | ||
2d1fe073 | 1357 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1358 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1359 | return false; |
2d1fe073 | 1360 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1361 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1362 | return false; | |
1519b995 | 1363 | } else { |
dc0fa718 | 1364 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1365 | return false; |
1366 | } | |
1367 | return true; | |
1368 | } | |
1369 | ||
1370 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1371 | enum pipe pipe, u32 val) | |
1372 | { | |
1373 | if ((val & LVDS_PORT_EN) == 0) | |
1374 | return false; | |
1375 | ||
2d1fe073 | 1376 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1377 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1378 | return false; | |
1379 | } else { | |
1380 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1381 | return false; | |
1382 | } | |
1383 | return true; | |
1384 | } | |
1385 | ||
1386 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1387 | enum pipe pipe, u32 val) | |
1388 | { | |
1389 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1390 | return false; | |
2d1fe073 | 1391 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1392 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1393 | return false; | |
1394 | } else { | |
1395 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1396 | return false; | |
1397 | } | |
1398 | return true; | |
1399 | } | |
1400 | ||
291906f1 | 1401 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1402 | enum pipe pipe, i915_reg_t reg, |
1403 | u32 port_sel) | |
291906f1 | 1404 | { |
47a05eca | 1405 | u32 val = I915_READ(reg); |
e2c719b7 | 1406 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1407 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1408 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1409 | |
2d1fe073 | 1410 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1411 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1412 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1413 | } |
1414 | ||
1415 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1416 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1417 | { |
47a05eca | 1418 | u32 val = I915_READ(reg); |
e2c719b7 | 1419 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1420 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1421 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1422 | |
2d1fe073 | 1423 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1424 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1425 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1426 | } |
1427 | ||
1428 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1429 | enum pipe pipe) | |
1430 | { | |
291906f1 | 1431 | u32 val; |
291906f1 | 1432 | |
f0575e92 KP |
1433 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1434 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1435 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1436 | |
649636ef | 1437 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1438 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1439 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1440 | pipe_name(pipe)); |
291906f1 | 1441 | |
649636ef | 1442 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1443 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1444 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1445 | pipe_name(pipe)); |
291906f1 | 1446 | |
e2debe91 PZ |
1447 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1448 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1449 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1450 | } |
1451 | ||
cd2d34d9 VS |
1452 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1453 | const struct intel_crtc_state *pipe_config) | |
1454 | { | |
1455 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1456 | enum pipe pipe = crtc->pipe; | |
1457 | ||
1458 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1459 | POSTING_READ(DPLL(pipe)); | |
1460 | udelay(150); | |
1461 | ||
2c30b43b CW |
1462 | if (intel_wait_for_register(dev_priv, |
1463 | DPLL(pipe), | |
1464 | DPLL_LOCK_VLV, | |
1465 | DPLL_LOCK_VLV, | |
1466 | 1)) | |
cd2d34d9 VS |
1467 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1468 | } | |
1469 | ||
d288f65f | 1470 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1471 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1472 | { |
cd2d34d9 | 1473 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1474 | enum pipe pipe = crtc->pipe; |
87442f73 | 1475 | |
8bd3f301 | 1476 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1477 | |
87442f73 | 1478 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1479 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1480 | |
cd2d34d9 VS |
1481 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1482 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1483 | |
8bd3f301 VS |
1484 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1485 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1486 | } |
1487 | ||
cd2d34d9 VS |
1488 | |
1489 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1490 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1491 | { |
cd2d34d9 | 1492 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1493 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1494 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1495 | u32 tmp; |
1496 | ||
a580516d | 1497 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1498 | |
1499 | /* Enable back the 10bit clock to display controller */ | |
1500 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1501 | tmp |= DPIO_DCLKP_EN; | |
1502 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1503 | ||
54433e91 VS |
1504 | mutex_unlock(&dev_priv->sb_lock); |
1505 | ||
9d556c99 CML |
1506 | /* |
1507 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1508 | */ | |
1509 | udelay(1); | |
1510 | ||
1511 | /* Enable PLL */ | |
d288f65f | 1512 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1513 | |
1514 | /* Check PLL is locked */ | |
6b18826a CW |
1515 | if (intel_wait_for_register(dev_priv, |
1516 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1517 | 1)) | |
9d556c99 | 1518 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1519 | } |
1520 | ||
1521 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1522 | const struct intel_crtc_state *pipe_config) | |
1523 | { | |
1524 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1525 | enum pipe pipe = crtc->pipe; | |
1526 | ||
1527 | assert_pipe_disabled(dev_priv, pipe); | |
1528 | ||
1529 | /* PLL is protected by panel, make sure we can write it */ | |
1530 | assert_panel_unlocked(dev_priv, pipe); | |
1531 | ||
1532 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1533 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1534 | |
c231775c VS |
1535 | if (pipe != PIPE_A) { |
1536 | /* | |
1537 | * WaPixelRepeatModeFixForC0:chv | |
1538 | * | |
1539 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1540 | * the value from DPLLBMD to either pipe B or C. | |
1541 | */ | |
1542 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1543 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1544 | I915_WRITE(CBR4_VLV, 0); | |
1545 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1546 | ||
1547 | /* | |
1548 | * DPLLB VGA mode also seems to cause problems. | |
1549 | * We should always have it disabled. | |
1550 | */ | |
1551 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1552 | } else { | |
1553 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1554 | POSTING_READ(DPLL_MD(pipe)); | |
1555 | } | |
9d556c99 CML |
1556 | } |
1557 | ||
6315b5d3 | 1558 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1559 | { |
1560 | struct intel_crtc *crtc; | |
1561 | int count = 0; | |
1562 | ||
6315b5d3 | 1563 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1564 | count += crtc->base.state->active && |
2d84d2b3 VS |
1565 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1566 | } | |
1c4e0274 VS |
1567 | |
1568 | return count; | |
1569 | } | |
1570 | ||
66e3d5c0 | 1571 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1572 | { |
6315b5d3 | 1573 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1574 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1575 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
bb408dd2 | 1576 | int i; |
63d7bbe9 | 1577 | |
66e3d5c0 | 1578 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1579 | |
63d7bbe9 | 1580 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1581 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1582 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1583 | |
1c4e0274 | 1584 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1585 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1586 | /* |
1587 | * It appears to be important that we don't enable this | |
1588 | * for the current pipe before otherwise configuring the | |
1589 | * PLL. No idea how this should be handled if multiple | |
1590 | * DVO outputs are enabled simultaneosly. | |
1591 | */ | |
1592 | dpll |= DPLL_DVO_2X_MODE; | |
1593 | I915_WRITE(DPLL(!crtc->pipe), | |
1594 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1595 | } | |
66e3d5c0 | 1596 | |
c2b63374 VS |
1597 | /* |
1598 | * Apparently we need to have VGA mode enabled prior to changing | |
1599 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1600 | * dividers, even though the register value does change. | |
1601 | */ | |
1602 | I915_WRITE(reg, 0); | |
1603 | ||
8e7a65aa VS |
1604 | I915_WRITE(reg, dpll); |
1605 | ||
66e3d5c0 DV |
1606 | /* Wait for the clocks to stabilize. */ |
1607 | POSTING_READ(reg); | |
1608 | udelay(150); | |
1609 | ||
6315b5d3 | 1610 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1611 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1612 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1613 | } else { |
1614 | /* The pixel multiplier can only be updated once the | |
1615 | * DPLL is enabled and the clocks are stable. | |
1616 | * | |
1617 | * So write it again. | |
1618 | */ | |
1619 | I915_WRITE(reg, dpll); | |
1620 | } | |
63d7bbe9 JB |
1621 | |
1622 | /* We do this three times for luck */ | |
bb408dd2 VS |
1623 | for (i = 0; i < 3; i++) { |
1624 | I915_WRITE(reg, dpll); | |
1625 | POSTING_READ(reg); | |
1626 | udelay(150); /* wait for warmup */ | |
1627 | } | |
63d7bbe9 JB |
1628 | } |
1629 | ||
1630 | /** | |
50b44a44 | 1631 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1632 | * @dev_priv: i915 private structure |
1633 | * @pipe: pipe PLL to disable | |
1634 | * | |
1635 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1636 | * | |
1637 | * Note! This is for pre-ILK only. | |
1638 | */ | |
1c4e0274 | 1639 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1640 | { |
6315b5d3 | 1641 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1642 | enum pipe pipe = crtc->pipe; |
1643 | ||
1644 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1645 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1646 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1647 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1648 | I915_WRITE(DPLL(PIPE_B), |
1649 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1650 | I915_WRITE(DPLL(PIPE_A), | |
1651 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1652 | } | |
1653 | ||
b6b5d049 | 1654 | /* Don't disable pipe or pipe PLLs if needed */ |
e56134bc | 1655 | if (IS_I830(dev_priv)) |
63d7bbe9 JB |
1656 | return; |
1657 | ||
1658 | /* Make sure the pipe isn't still relying on us */ | |
1659 | assert_pipe_disabled(dev_priv, pipe); | |
1660 | ||
b8afb911 | 1661 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1662 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1663 | } |
1664 | ||
f6071166 JB |
1665 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1666 | { | |
b8afb911 | 1667 | u32 val; |
f6071166 JB |
1668 | |
1669 | /* Make sure the pipe isn't still relying on us */ | |
1670 | assert_pipe_disabled(dev_priv, pipe); | |
1671 | ||
03ed5cbf VS |
1672 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1673 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1674 | if (pipe != PIPE_A) | |
1675 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1676 | ||
f6071166 JB |
1677 | I915_WRITE(DPLL(pipe), val); |
1678 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1679 | } |
1680 | ||
1681 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1682 | { | |
d752048d | 1683 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1684 | u32 val; |
1685 | ||
a11b0703 VS |
1686 | /* Make sure the pipe isn't still relying on us */ |
1687 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1688 | |
60bfe44f VS |
1689 | val = DPLL_SSC_REF_CLK_CHV | |
1690 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1691 | if (pipe != PIPE_A) |
1692 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1693 | |
a11b0703 VS |
1694 | I915_WRITE(DPLL(pipe), val); |
1695 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1696 | |
a580516d | 1697 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1698 | |
1699 | /* Disable 10bit clock to display controller */ | |
1700 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1701 | val &= ~DPIO_DCLKP_EN; | |
1702 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1703 | ||
a580516d | 1704 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1705 | } |
1706 | ||
e4607fcf | 1707 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1708 | struct intel_digital_port *dport, |
1709 | unsigned int expected_mask) | |
89b667f8 JB |
1710 | { |
1711 | u32 port_mask; | |
f0f59a00 | 1712 | i915_reg_t dpll_reg; |
89b667f8 | 1713 | |
e4607fcf CML |
1714 | switch (dport->port) { |
1715 | case PORT_B: | |
89b667f8 | 1716 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1717 | dpll_reg = DPLL(0); |
e4607fcf CML |
1718 | break; |
1719 | case PORT_C: | |
89b667f8 | 1720 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1721 | dpll_reg = DPLL(0); |
9b6de0a1 | 1722 | expected_mask <<= 4; |
00fc31b7 CML |
1723 | break; |
1724 | case PORT_D: | |
1725 | port_mask = DPLL_PORTD_READY_MASK; | |
1726 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1727 | break; |
1728 | default: | |
1729 | BUG(); | |
1730 | } | |
89b667f8 | 1731 | |
370004d3 CW |
1732 | if (intel_wait_for_register(dev_priv, |
1733 | dpll_reg, port_mask, expected_mask, | |
1734 | 1000)) | |
9b6de0a1 VS |
1735 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1736 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1737 | } |
1738 | ||
b8a4f404 PZ |
1739 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1740 | enum pipe pipe) | |
040484af | 1741 | { |
98187836 VS |
1742 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1743 | pipe); | |
f0f59a00 VS |
1744 | i915_reg_t reg; |
1745 | uint32_t val, pipeconf_val; | |
040484af | 1746 | |
040484af | 1747 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1748 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1749 | |
1750 | /* FDI must be feeding us bits for PCH ports */ | |
1751 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1752 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1753 | ||
6e266956 | 1754 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1755 | /* Workaround: Set the timing override bit before enabling the |
1756 | * pch transcoder. */ | |
1757 | reg = TRANS_CHICKEN2(pipe); | |
1758 | val = I915_READ(reg); | |
1759 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1760 | I915_WRITE(reg, val); | |
59c859d6 | 1761 | } |
23670b32 | 1762 | |
ab9412ba | 1763 | reg = PCH_TRANSCONF(pipe); |
040484af | 1764 | val = I915_READ(reg); |
5f7f726d | 1765 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1766 | |
2d1fe073 | 1767 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1768 | /* |
c5de7c6f VS |
1769 | * Make the BPC in transcoder be consistent with |
1770 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1771 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1772 | */ |
dfd07d72 | 1773 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1774 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1775 | val |= PIPECONF_8BPC; |
1776 | else | |
1777 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1778 | } |
5f7f726d PZ |
1779 | |
1780 | val &= ~TRANS_INTERLACE_MASK; | |
1781 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1782 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1783 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1784 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1785 | else | |
1786 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1787 | else |
1788 | val |= TRANS_PROGRESSIVE; | |
1789 | ||
040484af | 1790 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1791 | if (intel_wait_for_register(dev_priv, |
1792 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1793 | 100)) | |
4bb6f1f3 | 1794 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1795 | } |
1796 | ||
8fb033d7 | 1797 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1798 | enum transcoder cpu_transcoder) |
040484af | 1799 | { |
8fb033d7 | 1800 | u32 val, pipeconf_val; |
8fb033d7 | 1801 | |
8fb033d7 | 1802 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1803 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
a2196033 | 1804 | assert_fdi_rx_enabled(dev_priv, PIPE_A); |
8fb033d7 | 1805 | |
223a6fdf | 1806 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1807 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1808 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1809 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1810 | |
25f3ef11 | 1811 | val = TRANS_ENABLE; |
937bb610 | 1812 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1813 | |
9a76b1c6 PZ |
1814 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1815 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1816 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1817 | else |
1818 | val |= TRANS_PROGRESSIVE; | |
1819 | ||
ab9412ba | 1820 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1821 | if (intel_wait_for_register(dev_priv, |
1822 | LPT_TRANSCONF, | |
1823 | TRANS_STATE_ENABLE, | |
1824 | TRANS_STATE_ENABLE, | |
1825 | 100)) | |
937bb610 | 1826 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1827 | } |
1828 | ||
b8a4f404 PZ |
1829 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1830 | enum pipe pipe) | |
040484af | 1831 | { |
f0f59a00 VS |
1832 | i915_reg_t reg; |
1833 | uint32_t val; | |
040484af JB |
1834 | |
1835 | /* FDI relies on the transcoder */ | |
1836 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1837 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1838 | ||
291906f1 JB |
1839 | /* Ports must be off as well */ |
1840 | assert_pch_ports_disabled(dev_priv, pipe); | |
1841 | ||
ab9412ba | 1842 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1843 | val = I915_READ(reg); |
1844 | val &= ~TRANS_ENABLE; | |
1845 | I915_WRITE(reg, val); | |
1846 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1847 | if (intel_wait_for_register(dev_priv, |
1848 | reg, TRANS_STATE_ENABLE, 0, | |
1849 | 50)) | |
4bb6f1f3 | 1850 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1851 | |
6e266956 | 1852 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1853 | /* Workaround: Clear the timing override chicken bit again. */ |
1854 | reg = TRANS_CHICKEN2(pipe); | |
1855 | val = I915_READ(reg); | |
1856 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1857 | I915_WRITE(reg, val); | |
1858 | } | |
040484af JB |
1859 | } |
1860 | ||
b7076546 | 1861 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1862 | { |
8fb033d7 PZ |
1863 | u32 val; |
1864 | ||
ab9412ba | 1865 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1866 | val &= ~TRANS_ENABLE; |
ab9412ba | 1867 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1868 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1869 | if (intel_wait_for_register(dev_priv, |
1870 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1871 | 50)) | |
8a52fd9f | 1872 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1873 | |
1874 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1875 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1876 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1877 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1878 | } |
1879 | ||
a2196033 | 1880 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
65f2130c VS |
1881 | { |
1882 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1883 | ||
1884 | WARN_ON(!crtc->config->has_pch_encoder); | |
1885 | ||
1886 | if (HAS_PCH_LPT(dev_priv)) | |
a2196033 | 1887 | return PIPE_A; |
65f2130c | 1888 | else |
a2196033 | 1889 | return crtc->pipe; |
65f2130c VS |
1890 | } |
1891 | ||
b24e7179 | 1892 | /** |
309cfea8 | 1893 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1894 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1895 | * |
0372264a | 1896 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1897 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1898 | */ |
e1fdc473 | 1899 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1900 | { |
0372264a | 1901 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1902 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1903 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1904 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1905 | i915_reg_t reg; |
b24e7179 JB |
1906 | u32 val; |
1907 | ||
9e2ee2dd VS |
1908 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1909 | ||
58c6eaa2 | 1910 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1911 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1912 | assert_sprites_disabled(dev_priv, pipe); |
1913 | ||
b24e7179 JB |
1914 | /* |
1915 | * A pipe without a PLL won't actually be able to drive bits from | |
1916 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1917 | * need the check. | |
1918 | */ | |
09fa8bb9 | 1919 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1920 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1921 | assert_dsi_pll_enabled(dev_priv); |
1922 | else | |
1923 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1924 | } else { |
6e3c9717 | 1925 | if (crtc->config->has_pch_encoder) { |
040484af | 1926 | /* if driving the PCH, we need FDI enabled */ |
65f2130c | 1927 | assert_fdi_rx_pll_enabled(dev_priv, |
a2196033 | 1928 | intel_crtc_pch_transcoder(crtc)); |
1a240d4d DV |
1929 | assert_fdi_tx_pll_enabled(dev_priv, |
1930 | (enum pipe) cpu_transcoder); | |
040484af JB |
1931 | } |
1932 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1933 | } | |
b24e7179 | 1934 | |
702e7a56 | 1935 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1936 | val = I915_READ(reg); |
7ad25d48 | 1937 | if (val & PIPECONF_ENABLE) { |
e56134bc VS |
1938 | /* we keep both pipes enabled on 830 */ |
1939 | WARN_ON(!IS_I830(dev_priv)); | |
00d70b15 | 1940 | return; |
7ad25d48 | 1941 | } |
00d70b15 CW |
1942 | |
1943 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1944 | POSTING_READ(reg); |
b7792d8b VS |
1945 | |
1946 | /* | |
1947 | * Until the pipe starts DSL will read as 0, which would cause | |
1948 | * an apparent vblank timestamp jump, which messes up also the | |
1949 | * frame count when it's derived from the timestamps. So let's | |
1950 | * wait for the pipe to start properly before we call | |
1951 | * drm_crtc_vblank_on() | |
1952 | */ | |
1953 | if (dev->max_vblank_count == 0 && | |
1954 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1955 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1956 | } |
1957 | ||
1958 | /** | |
309cfea8 | 1959 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 1960 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 1961 | * |
575f7ab7 VS |
1962 | * Disable the pipe of @crtc, making sure that various hardware |
1963 | * specific requirements are met, if applicable, e.g. plane | |
1964 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
1965 | * |
1966 | * Will wait until the pipe has shut down before returning. | |
1967 | */ | |
575f7ab7 | 1968 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1969 | { |
fac5e23e | 1970 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1971 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1972 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1973 | i915_reg_t reg; |
b24e7179 JB |
1974 | u32 val; |
1975 | ||
9e2ee2dd VS |
1976 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
1977 | ||
b24e7179 JB |
1978 | /* |
1979 | * Make sure planes won't keep trying to pump pixels to us, | |
1980 | * or we might hang the display. | |
1981 | */ | |
1982 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1983 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1984 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 1985 | |
702e7a56 | 1986 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1987 | val = I915_READ(reg); |
00d70b15 CW |
1988 | if ((val & PIPECONF_ENABLE) == 0) |
1989 | return; | |
1990 | ||
67adc644 VS |
1991 | /* |
1992 | * Double wide has implications for planes | |
1993 | * so best keep it disabled when not needed. | |
1994 | */ | |
6e3c9717 | 1995 | if (crtc->config->double_wide) |
67adc644 VS |
1996 | val &= ~PIPECONF_DOUBLE_WIDE; |
1997 | ||
1998 | /* Don't disable pipe or pipe PLLs if needed */ | |
e56134bc | 1999 | if (!IS_I830(dev_priv)) |
67adc644 VS |
2000 | val &= ~PIPECONF_ENABLE; |
2001 | ||
2002 | I915_WRITE(reg, val); | |
2003 | if ((val & PIPECONF_ENABLE) == 0) | |
2004 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2005 | } |
2006 | ||
832be82f VS |
2007 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2008 | { | |
2009 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2010 | } | |
2011 | ||
d88c4afd VS |
2012 | static unsigned int |
2013 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) | |
7b49f948 | 2014 | { |
d88c4afd VS |
2015 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2016 | unsigned int cpp = fb->format->cpp[plane]; | |
2017 | ||
2018 | switch (fb->modifier) { | |
2f075565 | 2019 | case DRM_FORMAT_MOD_LINEAR: |
7b49f948 VS |
2020 | return cpp; |
2021 | case I915_FORMAT_MOD_X_TILED: | |
2022 | if (IS_GEN2(dev_priv)) | |
2023 | return 128; | |
2024 | else | |
2025 | return 512; | |
2e2adb05 VS |
2026 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2027 | if (plane == 1) | |
2028 | return 128; | |
2029 | /* fall through */ | |
7b49f948 VS |
2030 | case I915_FORMAT_MOD_Y_TILED: |
2031 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2032 | return 128; | |
2033 | else | |
2034 | return 512; | |
2e2adb05 VS |
2035 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
2036 | if (plane == 1) | |
2037 | return 128; | |
2038 | /* fall through */ | |
7b49f948 VS |
2039 | case I915_FORMAT_MOD_Yf_TILED: |
2040 | switch (cpp) { | |
2041 | case 1: | |
2042 | return 64; | |
2043 | case 2: | |
2044 | case 4: | |
2045 | return 128; | |
2046 | case 8: | |
2047 | case 16: | |
2048 | return 256; | |
2049 | default: | |
2050 | MISSING_CASE(cpp); | |
2051 | return cpp; | |
2052 | } | |
2053 | break; | |
2054 | default: | |
d88c4afd | 2055 | MISSING_CASE(fb->modifier); |
7b49f948 VS |
2056 | return cpp; |
2057 | } | |
2058 | } | |
2059 | ||
d88c4afd VS |
2060 | static unsigned int |
2061 | intel_tile_height(const struct drm_framebuffer *fb, int plane) | |
a57ce0b2 | 2062 | { |
2f075565 | 2063 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
832be82f VS |
2064 | return 1; |
2065 | else | |
d88c4afd VS |
2066 | return intel_tile_size(to_i915(fb->dev)) / |
2067 | intel_tile_width_bytes(fb, plane); | |
6761dd31 TU |
2068 | } |
2069 | ||
8d0deca8 | 2070 | /* Return the tile dimensions in pixel units */ |
d88c4afd | 2071 | static void intel_tile_dims(const struct drm_framebuffer *fb, int plane, |
8d0deca8 | 2072 | unsigned int *tile_width, |
d88c4afd | 2073 | unsigned int *tile_height) |
8d0deca8 | 2074 | { |
d88c4afd VS |
2075 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane); |
2076 | unsigned int cpp = fb->format->cpp[plane]; | |
8d0deca8 VS |
2077 | |
2078 | *tile_width = tile_width_bytes / cpp; | |
d88c4afd | 2079 | *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes; |
8d0deca8 VS |
2080 | } |
2081 | ||
6761dd31 | 2082 | unsigned int |
d88c4afd VS |
2083 | intel_fb_align_height(const struct drm_framebuffer *fb, |
2084 | int plane, unsigned int height) | |
6761dd31 | 2085 | { |
d88c4afd | 2086 | unsigned int tile_height = intel_tile_height(fb, plane); |
832be82f VS |
2087 | |
2088 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2089 | } |
2090 | ||
1663b9d6 VS |
2091 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2092 | { | |
2093 | unsigned int size = 0; | |
2094 | int i; | |
2095 | ||
2096 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2097 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2098 | ||
2099 | return size; | |
2100 | } | |
2101 | ||
75c82a53 | 2102 | static void |
3465c580 VS |
2103 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2104 | const struct drm_framebuffer *fb, | |
2105 | unsigned int rotation) | |
f64b98cd | 2106 | { |
7b92c047 | 2107 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2108 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2109 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2110 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2111 | } |
2112 | } | |
50470bb0 | 2113 | |
fabac484 VS |
2114 | static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv) |
2115 | { | |
2116 | if (IS_I830(dev_priv)) | |
2117 | return 16 * 1024; | |
2118 | else if (IS_I85X(dev_priv)) | |
2119 | return 256; | |
d9e1551e VS |
2120 | else if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
2121 | return 32; | |
fabac484 VS |
2122 | else |
2123 | return 4 * 1024; | |
2124 | } | |
2125 | ||
603525d7 | 2126 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2127 | { |
2128 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2129 | return 256 * 1024; | |
c0f86832 | 2130 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2131 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2132 | return 128 * 1024; |
2133 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2134 | return 4 * 1024; | |
2135 | else | |
44c5905e | 2136 | return 0; |
4e9a86b6 VS |
2137 | } |
2138 | ||
d88c4afd VS |
2139 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
2140 | int plane) | |
603525d7 | 2141 | { |
d88c4afd VS |
2142 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2143 | ||
b90c1ee1 | 2144 | /* AUX_DIST needs only 4K alignment */ |
2e2adb05 | 2145 | if (plane == 1) |
b90c1ee1 VS |
2146 | return 4096; |
2147 | ||
d88c4afd | 2148 | switch (fb->modifier) { |
2f075565 | 2149 | case DRM_FORMAT_MOD_LINEAR: |
603525d7 VS |
2150 | return intel_linear_alignment(dev_priv); |
2151 | case I915_FORMAT_MOD_X_TILED: | |
d88c4afd | 2152 | if (INTEL_GEN(dev_priv) >= 9) |
603525d7 VS |
2153 | return 256 * 1024; |
2154 | return 0; | |
2e2adb05 VS |
2155 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2156 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
603525d7 VS |
2157 | case I915_FORMAT_MOD_Y_TILED: |
2158 | case I915_FORMAT_MOD_Yf_TILED: | |
2159 | return 1 * 1024 * 1024; | |
2160 | default: | |
d88c4afd | 2161 | MISSING_CASE(fb->modifier); |
603525d7 VS |
2162 | return 0; |
2163 | } | |
2164 | } | |
2165 | ||
058d88c4 CW |
2166 | struct i915_vma * |
2167 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2168 | { |
850c4cdc | 2169 | struct drm_device *dev = fb->dev; |
fac5e23e | 2170 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2171 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2172 | struct i915_ggtt_view view; |
058d88c4 | 2173 | struct i915_vma *vma; |
6b95a207 | 2174 | u32 alignment; |
6b95a207 | 2175 | |
ebcdd39e MR |
2176 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2177 | ||
d88c4afd | 2178 | alignment = intel_surf_alignment(fb, 0); |
6b95a207 | 2179 | |
3465c580 | 2180 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2181 | |
693db184 CW |
2182 | /* Note that the w/a also requires 64 PTE of padding following the |
2183 | * bo. We currently fill all unused PTE with the shadow page and so | |
2184 | * we should always have valid PTE following the scanout preventing | |
2185 | * the VT-d warning. | |
2186 | */ | |
48f112fe | 2187 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2188 | alignment = 256 * 1024; |
2189 | ||
d6dd6843 PZ |
2190 | /* |
2191 | * Global gtt pte registers are special registers which actually forward | |
2192 | * writes to a chunk of system memory. Which means that there is no risk | |
2193 | * that the register values disappear as soon as we call | |
2194 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2195 | * pin/unpin/fence and not more. | |
2196 | */ | |
2197 | intel_runtime_pm_get(dev_priv); | |
2198 | ||
9db529aa DV |
2199 | atomic_inc(&dev_priv->gpu_error.pending_fb_pin); |
2200 | ||
058d88c4 | 2201 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2202 | if (IS_ERR(vma)) |
2203 | goto err; | |
6b95a207 | 2204 | |
05a20d09 | 2205 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2206 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2207 | * fence, whereas 965+ only requires a fence if using | |
2208 | * framebuffer compression. For simplicity, we always, when | |
2209 | * possible, install a fence as the cost is not that onerous. | |
2210 | * | |
2211 | * If we fail to fence the tiled scanout, then either the | |
2212 | * modeset will reject the change (which is highly unlikely as | |
2213 | * the affected systems, all but one, do not have unmappable | |
2214 | * space) or we will not be able to enable full powersaving | |
2215 | * techniques (also likely not to apply due to various limits | |
2216 | * FBC and the like impose on the size of the buffer, which | |
2217 | * presumably we violated anyway with this unmappable buffer). | |
2218 | * Anyway, it is presumably better to stumble onwards with | |
2219 | * something and try to run the system in a "less than optimal" | |
2220 | * mode that matches the user configuration. | |
2221 | */ | |
3bd40735 | 2222 | i915_vma_pin_fence(vma); |
9807216f | 2223 | } |
6b95a207 | 2224 | |
be1e3415 | 2225 | i915_vma_get(vma); |
49ef5294 | 2226 | err: |
9db529aa DV |
2227 | atomic_dec(&dev_priv->gpu_error.pending_fb_pin); |
2228 | ||
d6dd6843 | 2229 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2230 | return vma; |
6b95a207 KH |
2231 | } |
2232 | ||
be1e3415 | 2233 | void intel_unpin_fb_vma(struct i915_vma *vma) |
1690e1eb | 2234 | { |
be1e3415 | 2235 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
f64b98cd | 2236 | |
49ef5294 | 2237 | i915_vma_unpin_fence(vma); |
058d88c4 | 2238 | i915_gem_object_unpin_from_display_plane(vma); |
be1e3415 | 2239 | i915_vma_put(vma); |
1690e1eb CW |
2240 | } |
2241 | ||
ef78ec94 VS |
2242 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2243 | unsigned int rotation) | |
2244 | { | |
bd2ef25d | 2245 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2246 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2247 | else | |
2248 | return fb->pitches[plane]; | |
2249 | } | |
2250 | ||
6687c906 VS |
2251 | /* |
2252 | * Convert the x/y offsets into a linear offset. | |
2253 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2254 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2255 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2256 | */ | |
2257 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2258 | const struct intel_plane_state *state, |
2259 | int plane) | |
6687c906 | 2260 | { |
2949056c | 2261 | const struct drm_framebuffer *fb = state->base.fb; |
353c8598 | 2262 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2263 | unsigned int pitch = fb->pitches[plane]; |
2264 | ||
2265 | return y * pitch + x * cpp; | |
2266 | } | |
2267 | ||
2268 | /* | |
2269 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2270 | * specified plane src x/y offsets. The resulting x/y offsets | |
2271 | * specify the start of scanout from the beginning of the gtt mapping. | |
2272 | */ | |
2273 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2274 | const struct intel_plane_state *state, |
2275 | int plane) | |
6687c906 VS |
2276 | |
2277 | { | |
2949056c VS |
2278 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2279 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2280 | |
bd2ef25d | 2281 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2282 | *x += intel_fb->rotated[plane].x; |
2283 | *y += intel_fb->rotated[plane].y; | |
2284 | } else { | |
2285 | *x += intel_fb->normal[plane].x; | |
2286 | *y += intel_fb->normal[plane].y; | |
2287 | } | |
2288 | } | |
2289 | ||
303ba695 VS |
2290 | static u32 __intel_adjust_tile_offset(int *x, int *y, |
2291 | unsigned int tile_width, | |
2292 | unsigned int tile_height, | |
2293 | unsigned int tile_size, | |
2294 | unsigned int pitch_tiles, | |
2295 | u32 old_offset, | |
2296 | u32 new_offset) | |
29cf9491 | 2297 | { |
b9b24038 | 2298 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2299 | unsigned int tiles; |
2300 | ||
2301 | WARN_ON(old_offset & (tile_size - 1)); | |
2302 | WARN_ON(new_offset & (tile_size - 1)); | |
2303 | WARN_ON(new_offset > old_offset); | |
2304 | ||
2305 | tiles = (old_offset - new_offset) / tile_size; | |
2306 | ||
2307 | *y += tiles / pitch_tiles * tile_height; | |
2308 | *x += tiles % pitch_tiles * tile_width; | |
2309 | ||
b9b24038 VS |
2310 | /* minimize x in case it got needlessly big */ |
2311 | *y += *x / pitch_pixels * tile_height; | |
2312 | *x %= pitch_pixels; | |
2313 | ||
29cf9491 VS |
2314 | return new_offset; |
2315 | } | |
2316 | ||
303ba695 VS |
2317 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2318 | const struct drm_framebuffer *fb, int plane, | |
2319 | unsigned int rotation, | |
2320 | u32 old_offset, u32 new_offset) | |
66a2d927 | 2321 | { |
303ba695 | 2322 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
353c8598 | 2323 | unsigned int cpp = fb->format->cpp[plane]; |
66a2d927 VS |
2324 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); |
2325 | ||
2326 | WARN_ON(new_offset > old_offset); | |
2327 | ||
2f075565 | 2328 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
66a2d927 VS |
2329 | unsigned int tile_size, tile_width, tile_height; |
2330 | unsigned int pitch_tiles; | |
2331 | ||
2332 | tile_size = intel_tile_size(dev_priv); | |
d88c4afd | 2333 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
66a2d927 | 2334 | |
bd2ef25d | 2335 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2336 | pitch_tiles = pitch / tile_height; |
2337 | swap(tile_width, tile_height); | |
2338 | } else { | |
2339 | pitch_tiles = pitch / (tile_width * cpp); | |
2340 | } | |
2341 | ||
303ba695 VS |
2342 | __intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2343 | tile_size, pitch_tiles, | |
2344 | old_offset, new_offset); | |
66a2d927 VS |
2345 | } else { |
2346 | old_offset += *y * pitch + *x * cpp; | |
2347 | ||
2348 | *y = (old_offset - new_offset) / pitch; | |
2349 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2350 | } | |
2351 | ||
2352 | return new_offset; | |
2353 | } | |
2354 | ||
303ba695 VS |
2355 | /* |
2356 | * Adjust the tile offset by moving the difference into | |
2357 | * the x/y offsets. | |
2358 | */ | |
2359 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2360 | const struct intel_plane_state *state, int plane, | |
2361 | u32 old_offset, u32 new_offset) | |
2362 | { | |
2363 | return _intel_adjust_tile_offset(x, y, state->base.fb, plane, | |
2364 | state->base.rotation, | |
2365 | old_offset, new_offset); | |
2366 | } | |
2367 | ||
8d0deca8 VS |
2368 | /* |
2369 | * Computes the linear offset to the base tile and adjusts | |
2370 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2371 | * | |
2372 | * In the 90/270 rotated case, x and y are assumed | |
2373 | * to be already rotated to match the rotated GTT view, and | |
2374 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2375 | * |
2376 | * This function is used when computing the derived information | |
2377 | * under intel_framebuffer, so using any of that information | |
2378 | * here is not allowed. Anything under drm_framebuffer can be | |
2379 | * used. This is why the user has to pass in the pitch since it | |
2380 | * is specified in the rotated orientation. | |
8d0deca8 | 2381 | */ |
6687c906 VS |
2382 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2383 | int *x, int *y, | |
2384 | const struct drm_framebuffer *fb, int plane, | |
2385 | unsigned int pitch, | |
2386 | unsigned int rotation, | |
2387 | u32 alignment) | |
c2c75131 | 2388 | { |
bae781b2 | 2389 | uint64_t fb_modifier = fb->modifier; |
353c8598 | 2390 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 | 2391 | u32 offset, offset_aligned; |
29cf9491 | 2392 | |
29cf9491 VS |
2393 | if (alignment) |
2394 | alignment--; | |
2395 | ||
2f075565 | 2396 | if (fb_modifier != DRM_FORMAT_MOD_LINEAR) { |
8d0deca8 VS |
2397 | unsigned int tile_size, tile_width, tile_height; |
2398 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2399 | |
d843310d | 2400 | tile_size = intel_tile_size(dev_priv); |
d88c4afd | 2401 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
8d0deca8 | 2402 | |
bd2ef25d | 2403 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2404 | pitch_tiles = pitch / tile_height; |
2405 | swap(tile_width, tile_height); | |
2406 | } else { | |
2407 | pitch_tiles = pitch / (tile_width * cpp); | |
2408 | } | |
d843310d VS |
2409 | |
2410 | tile_rows = *y / tile_height; | |
2411 | *y %= tile_height; | |
c2c75131 | 2412 | |
8d0deca8 VS |
2413 | tiles = *x / tile_width; |
2414 | *x %= tile_width; | |
bc752862 | 2415 | |
29cf9491 VS |
2416 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2417 | offset_aligned = offset & ~alignment; | |
bc752862 | 2418 | |
303ba695 VS |
2419 | __intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2420 | tile_size, pitch_tiles, | |
2421 | offset, offset_aligned); | |
29cf9491 | 2422 | } else { |
bc752862 | 2423 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2424 | offset_aligned = offset & ~alignment; |
2425 | ||
4e9a86b6 VS |
2426 | *y = (offset & alignment) / pitch; |
2427 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2428 | } |
29cf9491 VS |
2429 | |
2430 | return offset_aligned; | |
c2c75131 DV |
2431 | } |
2432 | ||
6687c906 | 2433 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2434 | const struct intel_plane_state *state, |
2435 | int plane) | |
6687c906 | 2436 | { |
1e7b4fd8 VS |
2437 | struct intel_plane *intel_plane = to_intel_plane(state->base.plane); |
2438 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); | |
2949056c VS |
2439 | const struct drm_framebuffer *fb = state->base.fb; |
2440 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2441 | int pitch = intel_fb_pitch(fb, plane, rotation); |
1e7b4fd8 VS |
2442 | u32 alignment; |
2443 | ||
2444 | if (intel_plane->id == PLANE_CURSOR) | |
2445 | alignment = intel_cursor_alignment(dev_priv); | |
2446 | else | |
2447 | alignment = intel_surf_alignment(fb, plane); | |
6687c906 VS |
2448 | |
2449 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2450 | rotation, alignment); | |
2451 | } | |
2452 | ||
303ba695 VS |
2453 | /* Convert the fb->offset[] into x/y offsets */ |
2454 | static int intel_fb_offset_to_xy(int *x, int *y, | |
2455 | const struct drm_framebuffer *fb, int plane) | |
6687c906 | 2456 | { |
303ba695 | 2457 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
6687c906 | 2458 | |
303ba695 VS |
2459 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR && |
2460 | fb->offsets[plane] % intel_tile_size(dev_priv)) | |
2461 | return -EINVAL; | |
2462 | ||
2463 | *x = 0; | |
2464 | *y = 0; | |
2465 | ||
2466 | _intel_adjust_tile_offset(x, y, | |
2467 | fb, plane, DRM_MODE_ROTATE_0, | |
2468 | fb->offsets[plane], 0); | |
2469 | ||
2470 | return 0; | |
6687c906 VS |
2471 | } |
2472 | ||
72618ebf VS |
2473 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2474 | { | |
2475 | switch (fb_modifier) { | |
2476 | case I915_FORMAT_MOD_X_TILED: | |
2477 | return I915_TILING_X; | |
2478 | case I915_FORMAT_MOD_Y_TILED: | |
2e2adb05 | 2479 | case I915_FORMAT_MOD_Y_TILED_CCS: |
72618ebf VS |
2480 | return I915_TILING_Y; |
2481 | default: | |
2482 | return I915_TILING_NONE; | |
2483 | } | |
2484 | } | |
2485 | ||
bbfb6ce8 VS |
2486 | static const struct drm_format_info ccs_formats[] = { |
2487 | { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2488 | { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2489 | { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2490 | { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2491 | }; | |
2492 | ||
2493 | static const struct drm_format_info * | |
2494 | lookup_format_info(const struct drm_format_info formats[], | |
2495 | int num_formats, u32 format) | |
2496 | { | |
2497 | int i; | |
2498 | ||
2499 | for (i = 0; i < num_formats; i++) { | |
2500 | if (formats[i].format == format) | |
2501 | return &formats[i]; | |
2502 | } | |
2503 | ||
2504 | return NULL; | |
2505 | } | |
2506 | ||
2507 | static const struct drm_format_info * | |
2508 | intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) | |
2509 | { | |
2510 | switch (cmd->modifier[0]) { | |
2511 | case I915_FORMAT_MOD_Y_TILED_CCS: | |
2512 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
2513 | return lookup_format_info(ccs_formats, | |
2514 | ARRAY_SIZE(ccs_formats), | |
2515 | cmd->pixel_format); | |
2516 | default: | |
2517 | return NULL; | |
2518 | } | |
2519 | } | |
2520 | ||
6687c906 VS |
2521 | static int |
2522 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2523 | struct drm_framebuffer *fb) | |
2524 | { | |
2525 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2526 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2527 | u32 gtt_offset_rotated = 0; | |
2528 | unsigned int max_size = 0; | |
bcb0b461 | 2529 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
2530 | unsigned int tile_size = intel_tile_size(dev_priv); |
2531 | ||
2532 | for (i = 0; i < num_planes; i++) { | |
2533 | unsigned int width, height; | |
2534 | unsigned int cpp, size; | |
2535 | u32 offset; | |
2536 | int x, y; | |
303ba695 | 2537 | int ret; |
6687c906 | 2538 | |
353c8598 | 2539 | cpp = fb->format->cpp[i]; |
145fcb11 VS |
2540 | width = drm_framebuffer_plane_width(fb->width, fb, i); |
2541 | height = drm_framebuffer_plane_height(fb->height, fb, i); | |
6687c906 | 2542 | |
303ba695 VS |
2543 | ret = intel_fb_offset_to_xy(&x, &y, fb, i); |
2544 | if (ret) { | |
2545 | DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", | |
2546 | i, fb->offsets[i]); | |
2547 | return ret; | |
2548 | } | |
6687c906 | 2549 | |
2e2adb05 VS |
2550 | if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
2551 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) { | |
2552 | int hsub = fb->format->hsub; | |
2553 | int vsub = fb->format->vsub; | |
2554 | int tile_width, tile_height; | |
2555 | int main_x, main_y; | |
2556 | int ccs_x, ccs_y; | |
2557 | ||
2558 | intel_tile_dims(fb, i, &tile_width, &tile_height); | |
303ba695 VS |
2559 | tile_width *= hsub; |
2560 | tile_height *= vsub; | |
2e2adb05 | 2561 | |
303ba695 VS |
2562 | ccs_x = (x * hsub) % tile_width; |
2563 | ccs_y = (y * vsub) % tile_height; | |
2564 | main_x = intel_fb->normal[0].x % tile_width; | |
2565 | main_y = intel_fb->normal[0].y % tile_height; | |
2e2adb05 VS |
2566 | |
2567 | /* | |
2568 | * CCS doesn't have its own x/y offset register, so the intra CCS tile | |
2569 | * x/y offsets must match between CCS and the main surface. | |
2570 | */ | |
2571 | if (main_x != ccs_x || main_y != ccs_y) { | |
2572 | DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", | |
2573 | main_x, main_y, | |
2574 | ccs_x, ccs_y, | |
2575 | intel_fb->normal[0].x, | |
2576 | intel_fb->normal[0].y, | |
2577 | x, y); | |
2578 | return -EINVAL; | |
2579 | } | |
2580 | } | |
2581 | ||
60d5f2a4 VS |
2582 | /* |
2583 | * The fence (if used) is aligned to the start of the object | |
2584 | * so having the framebuffer wrap around across the edge of the | |
2585 | * fenced region doesn't really work. We have no API to configure | |
2586 | * the fence start offset within the object (nor could we probably | |
2587 | * on gen2/3). So it's just easier if we just require that the | |
2588 | * fb layout agrees with the fence layout. We already check that the | |
2589 | * fb stride matches the fence stride elsewhere. | |
2590 | */ | |
2ec4cf40 | 2591 | if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) && |
60d5f2a4 | 2592 | (x + width) * cpp > fb->pitches[i]) { |
144cc143 VS |
2593 | DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", |
2594 | i, fb->offsets[i]); | |
60d5f2a4 VS |
2595 | return -EINVAL; |
2596 | } | |
2597 | ||
6687c906 VS |
2598 | /* |
2599 | * First pixel of the framebuffer from | |
2600 | * the start of the normal gtt mapping. | |
2601 | */ | |
2602 | intel_fb->normal[i].x = x; | |
2603 | intel_fb->normal[i].y = y; | |
2604 | ||
2605 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
3ca46c0a | 2606 | fb, i, fb->pitches[i], |
c2c446ad | 2607 | DRM_MODE_ROTATE_0, tile_size); |
6687c906 VS |
2608 | offset /= tile_size; |
2609 | ||
2f075565 | 2610 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
6687c906 VS |
2611 | unsigned int tile_width, tile_height; |
2612 | unsigned int pitch_tiles; | |
2613 | struct drm_rect r; | |
2614 | ||
d88c4afd | 2615 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
6687c906 VS |
2616 | |
2617 | rot_info->plane[i].offset = offset; | |
2618 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2619 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2620 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2621 | ||
2622 | intel_fb->rotated[i].pitch = | |
2623 | rot_info->plane[i].height * tile_height; | |
2624 | ||
2625 | /* how many tiles does this plane need */ | |
2626 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2627 | /* | |
2628 | * If the plane isn't horizontally tile aligned, | |
2629 | * we need one more tile. | |
2630 | */ | |
2631 | if (x != 0) | |
2632 | size++; | |
2633 | ||
2634 | /* rotate the x/y offsets to match the GTT view */ | |
2635 | r.x1 = x; | |
2636 | r.y1 = y; | |
2637 | r.x2 = x + width; | |
2638 | r.y2 = y + height; | |
2639 | drm_rect_rotate(&r, | |
2640 | rot_info->plane[i].width * tile_width, | |
2641 | rot_info->plane[i].height * tile_height, | |
c2c446ad | 2642 | DRM_MODE_ROTATE_270); |
6687c906 VS |
2643 | x = r.x1; |
2644 | y = r.y1; | |
2645 | ||
2646 | /* rotate the tile dimensions to match the GTT view */ | |
2647 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2648 | swap(tile_width, tile_height); | |
2649 | ||
2650 | /* | |
2651 | * We only keep the x/y offsets, so push all of the | |
2652 | * gtt offset into the x/y offsets. | |
2653 | */ | |
303ba695 VS |
2654 | __intel_adjust_tile_offset(&x, &y, |
2655 | tile_width, tile_height, | |
2656 | tile_size, pitch_tiles, | |
2657 | gtt_offset_rotated * tile_size, 0); | |
6687c906 VS |
2658 | |
2659 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2660 | ||
2661 | /* | |
2662 | * First pixel of the framebuffer from | |
2663 | * the start of the rotated gtt mapping. | |
2664 | */ | |
2665 | intel_fb->rotated[i].x = x; | |
2666 | intel_fb->rotated[i].y = y; | |
2667 | } else { | |
2668 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2669 | x * cpp, tile_size); | |
2670 | } | |
2671 | ||
2672 | /* how many tiles in total needed in the bo */ | |
2673 | max_size = max(max_size, offset + size); | |
2674 | } | |
2675 | ||
144cc143 VS |
2676 | if (max_size * tile_size > intel_fb->obj->base.size) { |
2677 | DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2678 | max_size * tile_size, intel_fb->obj->base.size); | |
6687c906 VS |
2679 | return -EINVAL; |
2680 | } | |
2681 | ||
2682 | return 0; | |
2683 | } | |
2684 | ||
b35d63fa | 2685 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2686 | { |
2687 | switch (format) { | |
2688 | case DISPPLANE_8BPP: | |
2689 | return DRM_FORMAT_C8; | |
2690 | case DISPPLANE_BGRX555: | |
2691 | return DRM_FORMAT_XRGB1555; | |
2692 | case DISPPLANE_BGRX565: | |
2693 | return DRM_FORMAT_RGB565; | |
2694 | default: | |
2695 | case DISPPLANE_BGRX888: | |
2696 | return DRM_FORMAT_XRGB8888; | |
2697 | case DISPPLANE_RGBX888: | |
2698 | return DRM_FORMAT_XBGR8888; | |
2699 | case DISPPLANE_BGRX101010: | |
2700 | return DRM_FORMAT_XRGB2101010; | |
2701 | case DISPPLANE_RGBX101010: | |
2702 | return DRM_FORMAT_XBGR2101010; | |
2703 | } | |
2704 | } | |
2705 | ||
bc8d7dff DL |
2706 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2707 | { | |
2708 | switch (format) { | |
2709 | case PLANE_CTL_FORMAT_RGB_565: | |
2710 | return DRM_FORMAT_RGB565; | |
2711 | default: | |
2712 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2713 | if (rgb_order) { | |
2714 | if (alpha) | |
2715 | return DRM_FORMAT_ABGR8888; | |
2716 | else | |
2717 | return DRM_FORMAT_XBGR8888; | |
2718 | } else { | |
2719 | if (alpha) | |
2720 | return DRM_FORMAT_ARGB8888; | |
2721 | else | |
2722 | return DRM_FORMAT_XRGB8888; | |
2723 | } | |
2724 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2725 | if (rgb_order) | |
2726 | return DRM_FORMAT_XBGR2101010; | |
2727 | else | |
2728 | return DRM_FORMAT_XRGB2101010; | |
2729 | } | |
2730 | } | |
2731 | ||
5724dbd1 | 2732 | static bool |
f6936e29 DV |
2733 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2734 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2735 | { |
2736 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2737 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2738 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2739 | struct drm_i915_gem_object *obj = NULL; |
2740 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2741 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2742 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2743 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2744 | PAGE_SIZE); | |
2745 | ||
2746 | size_aligned -= base_aligned; | |
46f297fb | 2747 | |
ff2652ea CW |
2748 | if (plane_config->size == 0) |
2749 | return false; | |
2750 | ||
3badb49f PZ |
2751 | /* If the FB is too big, just don't use it since fbdev is not very |
2752 | * important and we should probably use that space with FBC or other | |
2753 | * features. */ | |
72e96d64 | 2754 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2755 | return false; |
2756 | ||
12c83d99 | 2757 | mutex_lock(&dev->struct_mutex); |
187685cb | 2758 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2759 | base_aligned, |
2760 | base_aligned, | |
2761 | size_aligned); | |
24dbf51a CW |
2762 | mutex_unlock(&dev->struct_mutex); |
2763 | if (!obj) | |
484b41dd | 2764 | return false; |
46f297fb | 2765 | |
3e510a8e CW |
2766 | if (plane_config->tiling == I915_TILING_X) |
2767 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2768 | |
438b74a5 | 2769 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
2770 | mode_cmd.width = fb->width; |
2771 | mode_cmd.height = fb->height; | |
2772 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2773 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2774 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2775 | |
24dbf51a | 2776 | if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { |
46f297fb JB |
2777 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2778 | goto out_unref_obj; | |
2779 | } | |
12c83d99 | 2780 | |
484b41dd | 2781 | |
f6936e29 | 2782 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2783 | return true; |
46f297fb JB |
2784 | |
2785 | out_unref_obj: | |
f8c417cd | 2786 | i915_gem_object_put(obj); |
484b41dd JB |
2787 | return false; |
2788 | } | |
2789 | ||
e9728bd8 VS |
2790 | static void |
2791 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
2792 | struct intel_plane_state *plane_state, | |
2793 | bool visible) | |
2794 | { | |
2795 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
2796 | ||
2797 | plane_state->base.visible = visible; | |
2798 | ||
2799 | /* FIXME pre-g4x don't work like this */ | |
2800 | if (visible) { | |
2801 | crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); | |
2802 | crtc_state->active_planes |= BIT(plane->id); | |
2803 | } else { | |
2804 | crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); | |
2805 | crtc_state->active_planes &= ~BIT(plane->id); | |
2806 | } | |
2807 | ||
2808 | DRM_DEBUG_KMS("%s active planes 0x%x\n", | |
2809 | crtc_state->base.crtc->name, | |
2810 | crtc_state->active_planes); | |
2811 | } | |
2812 | ||
5724dbd1 | 2813 | static void |
f6936e29 DV |
2814 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2815 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2816 | { |
2817 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2818 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 2819 | struct drm_crtc *c; |
2ff8fde1 | 2820 | struct drm_i915_gem_object *obj; |
88595ac9 | 2821 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2822 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2823 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2824 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2825 | struct intel_plane_state *intel_state = |
2826 | to_intel_plane_state(plane_state); | |
88595ac9 | 2827 | struct drm_framebuffer *fb; |
484b41dd | 2828 | |
2d14030b | 2829 | if (!plane_config->fb) |
484b41dd JB |
2830 | return; |
2831 | ||
f6936e29 | 2832 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2833 | fb = &plane_config->fb->base; |
2834 | goto valid_fb; | |
f55548b5 | 2835 | } |
484b41dd | 2836 | |
2d14030b | 2837 | kfree(plane_config->fb); |
484b41dd JB |
2838 | |
2839 | /* | |
2840 | * Failed to alloc the obj, check to see if we should share | |
2841 | * an fb with another CRTC instead | |
2842 | */ | |
70e1e0ec | 2843 | for_each_crtc(dev, c) { |
be1e3415 | 2844 | struct intel_plane_state *state; |
484b41dd JB |
2845 | |
2846 | if (c == &intel_crtc->base) | |
2847 | continue; | |
2848 | ||
be1e3415 | 2849 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
2850 | continue; |
2851 | ||
be1e3415 CW |
2852 | state = to_intel_plane_state(c->primary->state); |
2853 | if (!state->vma) | |
484b41dd JB |
2854 | continue; |
2855 | ||
be1e3415 CW |
2856 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
2857 | fb = c->primary->fb; | |
88595ac9 DV |
2858 | drm_framebuffer_reference(fb); |
2859 | goto valid_fb; | |
484b41dd JB |
2860 | } |
2861 | } | |
88595ac9 | 2862 | |
200757f5 MR |
2863 | /* |
2864 | * We've failed to reconstruct the BIOS FB. Current display state | |
2865 | * indicates that the primary plane is visible, but has a NULL FB, | |
2866 | * which will lead to problems later if we don't fix it up. The | |
2867 | * simplest solution is to just disable the primary plane now and | |
2868 | * pretend the BIOS never had it enabled. | |
2869 | */ | |
e9728bd8 VS |
2870 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), |
2871 | to_intel_plane_state(plane_state), | |
2872 | false); | |
2622a081 | 2873 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
72259536 | 2874 | trace_intel_disable_plane(primary, intel_crtc); |
282dbf9b | 2875 | intel_plane->disable_plane(intel_plane, intel_crtc); |
200757f5 | 2876 | |
88595ac9 DV |
2877 | return; |
2878 | ||
2879 | valid_fb: | |
be1e3415 CW |
2880 | mutex_lock(&dev->struct_mutex); |
2881 | intel_state->vma = | |
2882 | intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
2883 | mutex_unlock(&dev->struct_mutex); | |
2884 | if (IS_ERR(intel_state->vma)) { | |
2885 | DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", | |
2886 | intel_crtc->pipe, PTR_ERR(intel_state->vma)); | |
2887 | ||
2888 | intel_state->vma = NULL; | |
2889 | drm_framebuffer_unreference(fb); | |
2890 | return; | |
2891 | } | |
2892 | ||
f44e2659 VS |
2893 | plane_state->src_x = 0; |
2894 | plane_state->src_y = 0; | |
be5651f2 ML |
2895 | plane_state->src_w = fb->width << 16; |
2896 | plane_state->src_h = fb->height << 16; | |
2897 | ||
f44e2659 VS |
2898 | plane_state->crtc_x = 0; |
2899 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2900 | plane_state->crtc_w = fb->width; |
2901 | plane_state->crtc_h = fb->height; | |
2902 | ||
1638d30c RC |
2903 | intel_state->base.src = drm_plane_state_src(plane_state); |
2904 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2905 | |
88595ac9 | 2906 | obj = intel_fb_obj(fb); |
3e510a8e | 2907 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2908 | dev_priv->preserve_bios_swizzle = true; |
2909 | ||
be5651f2 ML |
2910 | drm_framebuffer_reference(fb); |
2911 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2912 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
e9728bd8 VS |
2913 | |
2914 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), | |
2915 | to_intel_plane_state(plane_state), | |
2916 | true); | |
2917 | ||
faf5bf0a CW |
2918 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2919 | &obj->frontbuffer_bits); | |
46f297fb JB |
2920 | } |
2921 | ||
b63a16f6 VS |
2922 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2923 | unsigned int rotation) | |
2924 | { | |
353c8598 | 2925 | int cpp = fb->format->cpp[plane]; |
b63a16f6 | 2926 | |
bae781b2 | 2927 | switch (fb->modifier) { |
2f075565 | 2928 | case DRM_FORMAT_MOD_LINEAR: |
b63a16f6 VS |
2929 | case I915_FORMAT_MOD_X_TILED: |
2930 | switch (cpp) { | |
2931 | case 8: | |
2932 | return 4096; | |
2933 | case 4: | |
2934 | case 2: | |
2935 | case 1: | |
2936 | return 8192; | |
2937 | default: | |
2938 | MISSING_CASE(cpp); | |
2939 | break; | |
2940 | } | |
2941 | break; | |
2e2adb05 VS |
2942 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2943 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
2944 | /* FIXME AUX plane? */ | |
b63a16f6 VS |
2945 | case I915_FORMAT_MOD_Y_TILED: |
2946 | case I915_FORMAT_MOD_Yf_TILED: | |
2947 | switch (cpp) { | |
2948 | case 8: | |
2949 | return 2048; | |
2950 | case 4: | |
2951 | return 4096; | |
2952 | case 2: | |
2953 | case 1: | |
2954 | return 8192; | |
2955 | default: | |
2956 | MISSING_CASE(cpp); | |
2957 | break; | |
2958 | } | |
2959 | break; | |
2960 | default: | |
bae781b2 | 2961 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2962 | } |
2963 | ||
2964 | return 2048; | |
2965 | } | |
2966 | ||
2e2adb05 VS |
2967 | static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, |
2968 | int main_x, int main_y, u32 main_offset) | |
2969 | { | |
2970 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2971 | int hsub = fb->format->hsub; | |
2972 | int vsub = fb->format->vsub; | |
2973 | int aux_x = plane_state->aux.x; | |
2974 | int aux_y = plane_state->aux.y; | |
2975 | u32 aux_offset = plane_state->aux.offset; | |
2976 | u32 alignment = intel_surf_alignment(fb, 1); | |
2977 | ||
2978 | while (aux_offset >= main_offset && aux_y <= main_y) { | |
2979 | int x, y; | |
2980 | ||
2981 | if (aux_x == main_x && aux_y == main_y) | |
2982 | break; | |
2983 | ||
2984 | if (aux_offset == 0) | |
2985 | break; | |
2986 | ||
2987 | x = aux_x / hsub; | |
2988 | y = aux_y / vsub; | |
2989 | aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1, | |
2990 | aux_offset, aux_offset - alignment); | |
2991 | aux_x = x * hsub + aux_x % hsub; | |
2992 | aux_y = y * vsub + aux_y % vsub; | |
2993 | } | |
2994 | ||
2995 | if (aux_x != main_x || aux_y != main_y) | |
2996 | return false; | |
2997 | ||
2998 | plane_state->aux.offset = aux_offset; | |
2999 | plane_state->aux.x = aux_x; | |
3000 | plane_state->aux.y = aux_y; | |
3001 | ||
3002 | return true; | |
3003 | } | |
3004 | ||
b63a16f6 VS |
3005 | static int skl_check_main_surface(struct intel_plane_state *plane_state) |
3006 | { | |
b63a16f6 VS |
3007 | const struct drm_framebuffer *fb = plane_state->base.fb; |
3008 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
3009 | int x = plane_state->base.src.x1 >> 16; |
3010 | int y = plane_state->base.src.y1 >> 16; | |
3011 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
3012 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
3013 | int max_width = skl_max_plane_width(fb, 0, rotation); |
3014 | int max_height = 4096; | |
8d970654 | 3015 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
3016 | |
3017 | if (w > max_width || h > max_height) { | |
3018 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
3019 | w, h, max_width, max_height); | |
3020 | return -EINVAL; | |
3021 | } | |
3022 | ||
3023 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
3024 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
d88c4afd | 3025 | alignment = intel_surf_alignment(fb, 0); |
b63a16f6 | 3026 | |
8d970654 VS |
3027 | /* |
3028 | * AUX surface offset is specified as the distance from the | |
3029 | * main surface offset, and it must be non-negative. Make | |
3030 | * sure that is what we will get. | |
3031 | */ | |
3032 | if (offset > aux_offset) | |
3033 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3034 | offset, aux_offset & ~(alignment - 1)); | |
3035 | ||
b63a16f6 VS |
3036 | /* |
3037 | * When using an X-tiled surface, the plane blows up | |
3038 | * if the x offset + width exceed the stride. | |
3039 | * | |
3040 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
3041 | */ | |
bae781b2 | 3042 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 3043 | int cpp = fb->format->cpp[0]; |
b63a16f6 VS |
3044 | |
3045 | while ((x + w) * cpp > fb->pitches[0]) { | |
3046 | if (offset == 0) { | |
2e2adb05 | 3047 | DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n"); |
b63a16f6 VS |
3048 | return -EINVAL; |
3049 | } | |
3050 | ||
3051 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3052 | offset, offset - alignment); | |
3053 | } | |
3054 | } | |
3055 | ||
2e2adb05 VS |
3056 | /* |
3057 | * CCS AUX surface doesn't have its own x/y offsets, we must make sure | |
3058 | * they match with the main surface x/y offsets. | |
3059 | */ | |
3060 | if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
3061 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { | |
3062 | while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) { | |
3063 | if (offset == 0) | |
3064 | break; | |
3065 | ||
3066 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3067 | offset, offset - alignment); | |
3068 | } | |
3069 | ||
3070 | if (x != plane_state->aux.x || y != plane_state->aux.y) { | |
3071 | DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n"); | |
3072 | return -EINVAL; | |
3073 | } | |
3074 | } | |
3075 | ||
b63a16f6 VS |
3076 | plane_state->main.offset = offset; |
3077 | plane_state->main.x = x; | |
3078 | plane_state->main.y = y; | |
3079 | ||
3080 | return 0; | |
3081 | } | |
3082 | ||
8d970654 VS |
3083 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
3084 | { | |
3085 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3086 | unsigned int rotation = plane_state->base.rotation; | |
3087 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
3088 | int max_height = 4096; | |
cc926387 DV |
3089 | int x = plane_state->base.src.x1 >> 17; |
3090 | int y = plane_state->base.src.y1 >> 17; | |
3091 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
3092 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
3093 | u32 offset; |
3094 | ||
3095 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
3096 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
3097 | ||
3098 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
3099 | if (w > max_width || h > max_height) { | |
3100 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
3101 | w, h, max_width, max_height); | |
3102 | return -EINVAL; | |
3103 | } | |
3104 | ||
3105 | plane_state->aux.offset = offset; | |
3106 | plane_state->aux.x = x; | |
3107 | plane_state->aux.y = y; | |
3108 | ||
3109 | return 0; | |
3110 | } | |
3111 | ||
2e2adb05 VS |
3112 | static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) |
3113 | { | |
3114 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
3115 | struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc); | |
3116 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3117 | int src_x = plane_state->base.src.x1 >> 16; | |
3118 | int src_y = plane_state->base.src.y1 >> 16; | |
3119 | int hsub = fb->format->hsub; | |
3120 | int vsub = fb->format->vsub; | |
3121 | int x = src_x / hsub; | |
3122 | int y = src_y / vsub; | |
3123 | u32 offset; | |
3124 | ||
3125 | switch (plane->id) { | |
3126 | case PLANE_PRIMARY: | |
3127 | case PLANE_SPRITE0: | |
3128 | break; | |
3129 | default: | |
3130 | DRM_DEBUG_KMS("RC support only on plane 1 and 2\n"); | |
3131 | return -EINVAL; | |
3132 | } | |
3133 | ||
3134 | if (crtc->pipe == PIPE_C) { | |
3135 | DRM_DEBUG_KMS("No RC support on pipe C\n"); | |
3136 | return -EINVAL; | |
3137 | } | |
3138 | ||
3139 | if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) { | |
3140 | DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n", | |
3141 | plane_state->base.rotation); | |
3142 | return -EINVAL; | |
3143 | } | |
3144 | ||
3145 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
3146 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
3147 | ||
3148 | plane_state->aux.offset = offset; | |
3149 | plane_state->aux.x = x * hsub + src_x % hsub; | |
3150 | plane_state->aux.y = y * vsub + src_y % vsub; | |
3151 | ||
3152 | return 0; | |
3153 | } | |
3154 | ||
b63a16f6 VS |
3155 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
3156 | { | |
3157 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3158 | unsigned int rotation = plane_state->base.rotation; | |
3159 | int ret; | |
3160 | ||
a5e4c7d0 VS |
3161 | if (!plane_state->base.visible) |
3162 | return 0; | |
3163 | ||
b63a16f6 | 3164 | /* Rotate src coordinates to match rotated GTT view */ |
bd2ef25d | 3165 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 3166 | drm_rect_rotate(&plane_state->base.src, |
da064b47 | 3167 | fb->width << 16, fb->height << 16, |
c2c446ad | 3168 | DRM_MODE_ROTATE_270); |
b63a16f6 | 3169 | |
8d970654 VS |
3170 | /* |
3171 | * Handle the AUX surface first since | |
3172 | * the main surface setup depends on it. | |
3173 | */ | |
438b74a5 | 3174 | if (fb->format->format == DRM_FORMAT_NV12) { |
8d970654 VS |
3175 | ret = skl_check_nv12_aux_surface(plane_state); |
3176 | if (ret) | |
3177 | return ret; | |
2e2adb05 VS |
3178 | } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
3179 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { | |
3180 | ret = skl_check_ccs_aux_surface(plane_state); | |
3181 | if (ret) | |
3182 | return ret; | |
8d970654 VS |
3183 | } else { |
3184 | plane_state->aux.offset = ~0xfff; | |
3185 | plane_state->aux.x = 0; | |
3186 | plane_state->aux.y = 0; | |
3187 | } | |
3188 | ||
b63a16f6 VS |
3189 | ret = skl_check_main_surface(plane_state); |
3190 | if (ret) | |
3191 | return ret; | |
3192 | ||
3193 | return 0; | |
3194 | } | |
3195 | ||
7145f60a VS |
3196 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
3197 | const struct intel_plane_state *plane_state) | |
81255565 | 3198 | { |
7145f60a VS |
3199 | struct drm_i915_private *dev_priv = |
3200 | to_i915(plane_state->base.plane->dev); | |
3201 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3202 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
8d0deca8 | 3203 | unsigned int rotation = plane_state->base.rotation; |
7145f60a | 3204 | u32 dspcntr; |
c9ba6fad | 3205 | |
7145f60a | 3206 | dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; |
f45651ba | 3207 | |
6a4407a6 VS |
3208 | if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || |
3209 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
7145f60a | 3210 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
f45651ba | 3211 | |
6a4407a6 VS |
3212 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
3213 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
f45651ba | 3214 | |
d509e28b VS |
3215 | if (INTEL_GEN(dev_priv) < 4) |
3216 | dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); | |
81255565 | 3217 | |
438b74a5 | 3218 | switch (fb->format->format) { |
57779d06 | 3219 | case DRM_FORMAT_C8: |
81255565 JB |
3220 | dspcntr |= DISPPLANE_8BPP; |
3221 | break; | |
57779d06 | 3222 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3223 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3224 | break; |
57779d06 VS |
3225 | case DRM_FORMAT_RGB565: |
3226 | dspcntr |= DISPPLANE_BGRX565; | |
3227 | break; | |
3228 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3229 | dspcntr |= DISPPLANE_BGRX888; |
3230 | break; | |
3231 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3232 | dspcntr |= DISPPLANE_RGBX888; |
3233 | break; | |
3234 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3235 | dspcntr |= DISPPLANE_BGRX101010; |
3236 | break; | |
3237 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3238 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3239 | break; |
3240 | default: | |
7145f60a VS |
3241 | MISSING_CASE(fb->format->format); |
3242 | return 0; | |
81255565 | 3243 | } |
57779d06 | 3244 | |
72618ebf | 3245 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3246 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3247 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3248 | |
c2c446ad | 3249 | if (rotation & DRM_MODE_ROTATE_180) |
df0cd455 VS |
3250 | dspcntr |= DISPPLANE_ROTATE_180; |
3251 | ||
c2c446ad | 3252 | if (rotation & DRM_MODE_REFLECT_X) |
4ea7be2b VS |
3253 | dspcntr |= DISPPLANE_MIRROR; |
3254 | ||
7145f60a VS |
3255 | return dspcntr; |
3256 | } | |
de1aa629 | 3257 | |
f9407ae1 | 3258 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
5b7fcc44 VS |
3259 | { |
3260 | struct drm_i915_private *dev_priv = | |
3261 | to_i915(plane_state->base.plane->dev); | |
3262 | int src_x = plane_state->base.src.x1 >> 16; | |
3263 | int src_y = plane_state->base.src.y1 >> 16; | |
3264 | u32 offset; | |
81255565 | 3265 | |
5b7fcc44 | 3266 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
e506a0c6 | 3267 | |
5b7fcc44 VS |
3268 | if (INTEL_GEN(dev_priv) >= 4) |
3269 | offset = intel_compute_tile_offset(&src_x, &src_y, | |
3270 | plane_state, 0); | |
3271 | else | |
3272 | offset = 0; | |
3273 | ||
3274 | /* HSW/BDW do this automagically in hardware */ | |
3275 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { | |
3276 | unsigned int rotation = plane_state->base.rotation; | |
3277 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; | |
3278 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3279 | ||
c2c446ad | 3280 | if (rotation & DRM_MODE_ROTATE_180) { |
5b7fcc44 VS |
3281 | src_x += src_w - 1; |
3282 | src_y += src_h - 1; | |
c2c446ad | 3283 | } else if (rotation & DRM_MODE_REFLECT_X) { |
5b7fcc44 VS |
3284 | src_x += src_w - 1; |
3285 | } | |
48404c1e SJ |
3286 | } |
3287 | ||
5b7fcc44 VS |
3288 | plane_state->main.offset = offset; |
3289 | plane_state->main.x = src_x; | |
3290 | plane_state->main.y = src_y; | |
3291 | ||
3292 | return 0; | |
3293 | } | |
3294 | ||
282dbf9b | 3295 | static void i9xx_update_primary_plane(struct intel_plane *primary, |
7145f60a VS |
3296 | const struct intel_crtc_state *crtc_state, |
3297 | const struct intel_plane_state *plane_state) | |
3298 | { | |
282dbf9b VS |
3299 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3300 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3301 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3302 | enum plane plane = primary->plane; | |
7145f60a | 3303 | u32 linear_offset; |
a0864d59 | 3304 | u32 dspcntr = plane_state->ctl; |
7145f60a | 3305 | i915_reg_t reg = DSPCNTR(plane); |
5b7fcc44 VS |
3306 | int x = plane_state->main.x; |
3307 | int y = plane_state->main.y; | |
7145f60a VS |
3308 | unsigned long irqflags; |
3309 | ||
2949056c | 3310 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3311 | |
5b7fcc44 | 3312 | if (INTEL_GEN(dev_priv) >= 4) |
282dbf9b | 3313 | crtc->dspaddr_offset = plane_state->main.offset; |
5b7fcc44 | 3314 | else |
282dbf9b | 3315 | crtc->dspaddr_offset = linear_offset; |
6687c906 | 3316 | |
282dbf9b VS |
3317 | crtc->adjusted_x = x; |
3318 | crtc->adjusted_y = y; | |
2db3366b | 3319 | |
dd584fc0 VS |
3320 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3321 | ||
78587de2 VS |
3322 | if (INTEL_GEN(dev_priv) < 4) { |
3323 | /* pipesrc and dspsize control the size that is scaled from, | |
3324 | * which should always be the user's requested size. | |
3325 | */ | |
dd584fc0 VS |
3326 | I915_WRITE_FW(DSPSIZE(plane), |
3327 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3328 | (crtc_state->pipe_src_w - 1)); | |
3329 | I915_WRITE_FW(DSPPOS(plane), 0); | |
78587de2 | 3330 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
dd584fc0 VS |
3331 | I915_WRITE_FW(PRIMSIZE(plane), |
3332 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3333 | (crtc_state->pipe_src_w - 1)); | |
3334 | I915_WRITE_FW(PRIMPOS(plane), 0); | |
3335 | I915_WRITE_FW(PRIMCNSTALPHA(plane), 0); | |
78587de2 VS |
3336 | } |
3337 | ||
dd584fc0 | 3338 | I915_WRITE_FW(reg, dspcntr); |
48404c1e | 3339 | |
dd584fc0 | 3340 | I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]); |
3ba35e53 VS |
3341 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3342 | I915_WRITE_FW(DSPSURF(plane), | |
3343 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3344 | crtc->dspaddr_offset); |
3ba35e53 VS |
3345 | I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); |
3346 | } else if (INTEL_GEN(dev_priv) >= 4) { | |
dd584fc0 VS |
3347 | I915_WRITE_FW(DSPSURF(plane), |
3348 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3349 | crtc->dspaddr_offset); |
dd584fc0 VS |
3350 | I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); |
3351 | I915_WRITE_FW(DSPLINOFF(plane), linear_offset); | |
bfb81049 | 3352 | } else { |
dd584fc0 VS |
3353 | I915_WRITE_FW(DSPADDR(plane), |
3354 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3355 | crtc->dspaddr_offset); |
bfb81049 | 3356 | } |
dd584fc0 VS |
3357 | POSTING_READ_FW(reg); |
3358 | ||
3359 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
17638cd6 JB |
3360 | } |
3361 | ||
282dbf9b VS |
3362 | static void i9xx_disable_primary_plane(struct intel_plane *primary, |
3363 | struct intel_crtc *crtc) | |
17638cd6 | 3364 | { |
282dbf9b VS |
3365 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3366 | enum plane plane = primary->plane; | |
dd584fc0 VS |
3367 | unsigned long irqflags; |
3368 | ||
3369 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
f45651ba | 3370 | |
dd584fc0 | 3371 | I915_WRITE_FW(DSPCNTR(plane), 0); |
a8d201af | 3372 | if (INTEL_INFO(dev_priv)->gen >= 4) |
dd584fc0 | 3373 | I915_WRITE_FW(DSPSURF(plane), 0); |
a8d201af | 3374 | else |
dd584fc0 VS |
3375 | I915_WRITE_FW(DSPADDR(plane), 0); |
3376 | POSTING_READ_FW(DSPCNTR(plane)); | |
3377 | ||
3378 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3379 | } |
c9ba6fad | 3380 | |
d88c4afd VS |
3381 | static u32 |
3382 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane) | |
b321803d | 3383 | { |
2f075565 | 3384 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
b321803d | 3385 | return 64; |
d88c4afd VS |
3386 | else |
3387 | return intel_tile_width_bytes(fb, plane); | |
b321803d DL |
3388 | } |
3389 | ||
e435d6e5 ML |
3390 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3391 | { | |
3392 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3393 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3394 | |
3395 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3396 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3397 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3398 | } |
3399 | ||
a1b2278e CK |
3400 | /* |
3401 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3402 | */ | |
0583236e | 3403 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3404 | { |
a1b2278e CK |
3405 | struct intel_crtc_scaler_state *scaler_state; |
3406 | int i; | |
3407 | ||
a1b2278e CK |
3408 | scaler_state = &intel_crtc->config->scaler_state; |
3409 | ||
3410 | /* loop through and disable scalers that aren't in use */ | |
3411 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3412 | if (!scaler_state->scalers[i].in_use) |
3413 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3414 | } |
3415 | } | |
3416 | ||
d2196774 VS |
3417 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3418 | unsigned int rotation) | |
3419 | { | |
1b500535 VS |
3420 | u32 stride; |
3421 | ||
3422 | if (plane >= fb->format->num_planes) | |
3423 | return 0; | |
3424 | ||
3425 | stride = intel_fb_pitch(fb, plane, rotation); | |
d2196774 VS |
3426 | |
3427 | /* | |
3428 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3429 | * linear buffers or in number of tiles for tiled buffers. | |
3430 | */ | |
d88c4afd VS |
3431 | if (drm_rotation_90_or_270(rotation)) |
3432 | stride /= intel_tile_height(fb, plane); | |
3433 | else | |
3434 | stride /= intel_fb_stride_alignment(fb, plane); | |
d2196774 VS |
3435 | |
3436 | return stride; | |
3437 | } | |
3438 | ||
2e881264 | 3439 | static u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3440 | { |
6156a456 | 3441 | switch (pixel_format) { |
d161cf7a | 3442 | case DRM_FORMAT_C8: |
c34ce3d1 | 3443 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3444 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3445 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3446 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3447 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3448 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3449 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3450 | /* |
3451 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3452 | * to be already pre-multiplied. We need to add a knob (or a different | |
3453 | * DRM_FORMAT) for user-space to configure that. | |
3454 | */ | |
f75fb42a | 3455 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3456 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3457 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3458 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3459 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3460 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3461 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3462 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3463 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3464 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3465 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3466 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3467 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3468 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3469 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3470 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3471 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3472 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3473 | default: |
4249eeef | 3474 | MISSING_CASE(pixel_format); |
70d21f0e | 3475 | } |
8cfcba41 | 3476 | |
c34ce3d1 | 3477 | return 0; |
6156a456 | 3478 | } |
70d21f0e | 3479 | |
2e881264 | 3480 | static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
6156a456 | 3481 | { |
6156a456 | 3482 | switch (fb_modifier) { |
2f075565 | 3483 | case DRM_FORMAT_MOD_LINEAR: |
70d21f0e | 3484 | break; |
30af77c4 | 3485 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3486 | return PLANE_CTL_TILED_X; |
b321803d | 3487 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3488 | return PLANE_CTL_TILED_Y; |
2e2adb05 VS |
3489 | case I915_FORMAT_MOD_Y_TILED_CCS: |
3490 | return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE; | |
b321803d | 3491 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3492 | return PLANE_CTL_TILED_YF; |
2e2adb05 VS |
3493 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
3494 | return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE; | |
70d21f0e | 3495 | default: |
6156a456 | 3496 | MISSING_CASE(fb_modifier); |
70d21f0e | 3497 | } |
8cfcba41 | 3498 | |
c34ce3d1 | 3499 | return 0; |
6156a456 | 3500 | } |
70d21f0e | 3501 | |
2e881264 | 3502 | static u32 skl_plane_ctl_rotation(unsigned int rotation) |
6156a456 | 3503 | { |
3b7a5119 | 3504 | switch (rotation) { |
c2c446ad | 3505 | case DRM_MODE_ROTATE_0: |
6156a456 | 3506 | break; |
1e8df167 | 3507 | /* |
c2c446ad | 3508 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr |
1e8df167 SJ |
3509 | * while i915 HW rotation is clockwise, thats why this swapping. |
3510 | */ | |
c2c446ad | 3511 | case DRM_MODE_ROTATE_90: |
1e8df167 | 3512 | return PLANE_CTL_ROTATE_270; |
c2c446ad | 3513 | case DRM_MODE_ROTATE_180: |
c34ce3d1 | 3514 | return PLANE_CTL_ROTATE_180; |
c2c446ad | 3515 | case DRM_MODE_ROTATE_270: |
1e8df167 | 3516 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3517 | default: |
3518 | MISSING_CASE(rotation); | |
3519 | } | |
3520 | ||
c34ce3d1 | 3521 | return 0; |
6156a456 CK |
3522 | } |
3523 | ||
2e881264 VS |
3524 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
3525 | const struct intel_plane_state *plane_state) | |
46f788ba VS |
3526 | { |
3527 | struct drm_i915_private *dev_priv = | |
3528 | to_i915(plane_state->base.plane->dev); | |
3529 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3530 | unsigned int rotation = plane_state->base.rotation; | |
2e881264 | 3531 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
46f788ba VS |
3532 | u32 plane_ctl; |
3533 | ||
3534 | plane_ctl = PLANE_CTL_ENABLE; | |
3535 | ||
6602be0e | 3536 | if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) { |
46f788ba VS |
3537 | plane_ctl |= |
3538 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3539 | PLANE_CTL_PIPE_CSC_ENABLE | | |
3540 | PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3541 | } | |
3542 | ||
3543 | plane_ctl |= skl_plane_ctl_format(fb->format->format); | |
3544 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); | |
3545 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3546 | ||
2e881264 VS |
3547 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
3548 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
3549 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
3550 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
3551 | ||
46f788ba VS |
3552 | return plane_ctl; |
3553 | } | |
3554 | ||
282dbf9b | 3555 | static void skylake_update_primary_plane(struct intel_plane *plane, |
a8d201af ML |
3556 | const struct intel_crtc_state *crtc_state, |
3557 | const struct intel_plane_state *plane_state) | |
6156a456 | 3558 | { |
282dbf9b VS |
3559 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
3560 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3561 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3562 | enum plane_id plane_id = plane->id; | |
3563 | enum pipe pipe = plane->pipe; | |
a0864d59 | 3564 | u32 plane_ctl = plane_state->ctl; |
a8d201af | 3565 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3566 | u32 stride = skl_plane_stride(fb, 0, rotation); |
2e2adb05 | 3567 | u32 aux_stride = skl_plane_stride(fb, 1, rotation); |
b63a16f6 | 3568 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3569 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3570 | int src_x = plane_state->main.x; |
3571 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3572 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3573 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3574 | int dst_x = plane_state->base.dst.x1; | |
3575 | int dst_y = plane_state->base.dst.y1; | |
3576 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3577 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
dd584fc0 | 3578 | unsigned long irqflags; |
70d21f0e | 3579 | |
6687c906 VS |
3580 | /* Sizes are 0 based */ |
3581 | src_w--; | |
3582 | src_h--; | |
3583 | dst_w--; | |
3584 | dst_h--; | |
3585 | ||
282dbf9b | 3586 | crtc->dspaddr_offset = surf_addr; |
4c0b8a8b | 3587 | |
282dbf9b VS |
3588 | crtc->adjusted_x = src_x; |
3589 | crtc->adjusted_y = src_y; | |
2db3366b | 3590 | |
dd584fc0 VS |
3591 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3592 | ||
6602be0e | 3593 | if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
dd584fc0 VS |
3594 | I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), |
3595 | PLANE_COLOR_PIPE_GAMMA_ENABLE | | |
3596 | PLANE_COLOR_PIPE_CSC_ENABLE | | |
3597 | PLANE_COLOR_PLANE_GAMMA_DISABLE); | |
78587de2 VS |
3598 | } |
3599 | ||
dd584fc0 VS |
3600 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); |
3601 | I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3602 | I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); | |
3603 | I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
2e2adb05 VS |
3604 | I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), |
3605 | (plane_state->aux.offset - surf_addr) | aux_stride); | |
3606 | I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), | |
3607 | (plane_state->aux.y << 16) | plane_state->aux.x); | |
6156a456 CK |
3608 | |
3609 | if (scaler_id >= 0) { | |
3610 | uint32_t ps_ctrl = 0; | |
3611 | ||
3612 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3613 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 | 3614 | crtc_state->scaler_state.scalers[scaler_id].mode; |
dd584fc0 VS |
3615 | I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
3616 | I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3617 | I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3618 | I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3619 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0); | |
6156a456 | 3620 | } else { |
dd584fc0 | 3621 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3622 | } |
3623 | ||
dd584fc0 VS |
3624 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), |
3625 | intel_plane_ggtt_offset(plane_state) + surf_addr); | |
70d21f0e | 3626 | |
dd584fc0 VS |
3627 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); |
3628 | ||
3629 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
70d21f0e DL |
3630 | } |
3631 | ||
282dbf9b VS |
3632 | static void skylake_disable_primary_plane(struct intel_plane *primary, |
3633 | struct intel_crtc *crtc) | |
17638cd6 | 3634 | { |
282dbf9b VS |
3635 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3636 | enum plane_id plane_id = primary->id; | |
3637 | enum pipe pipe = primary->pipe; | |
dd584fc0 VS |
3638 | unsigned long irqflags; |
3639 | ||
3640 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
62e0fb88 | 3641 | |
dd584fc0 VS |
3642 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); |
3643 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); | |
3644 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); | |
3645 | ||
3646 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3647 | } |
29b9bde6 | 3648 | |
73974893 ML |
3649 | static int |
3650 | __intel_display_resume(struct drm_device *dev, | |
581e49fe ML |
3651 | struct drm_atomic_state *state, |
3652 | struct drm_modeset_acquire_ctx *ctx) | |
73974893 ML |
3653 | { |
3654 | struct drm_crtc_state *crtc_state; | |
3655 | struct drm_crtc *crtc; | |
3656 | int i, ret; | |
11c22da6 | 3657 | |
aecd36b8 | 3658 | intel_modeset_setup_hw_state(dev, ctx); |
29b74b7f | 3659 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3660 | |
3661 | if (!state) | |
3662 | return 0; | |
3663 | ||
aa5e9b47 ML |
3664 | /* |
3665 | * We've duplicated the state, pointers to the old state are invalid. | |
3666 | * | |
3667 | * Don't attempt to use the old state until we commit the duplicated state. | |
3668 | */ | |
3669 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { | |
73974893 ML |
3670 | /* |
3671 | * Force recalculation even if we restore | |
3672 | * current state. With fast modeset this may not result | |
3673 | * in a modeset when the state is compatible. | |
3674 | */ | |
3675 | crtc_state->mode_changed = true; | |
96a02917 | 3676 | } |
73974893 ML |
3677 | |
3678 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
602ae835 VS |
3679 | if (!HAS_GMCH_DISPLAY(to_i915(dev))) |
3680 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
73974893 | 3681 | |
581e49fe | 3682 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
73974893 ML |
3683 | |
3684 | WARN_ON(ret == -EDEADLK); | |
3685 | return ret; | |
96a02917 VS |
3686 | } |
3687 | ||
4ac2ba2f VS |
3688 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3689 | { | |
ae98104b VS |
3690 | return intel_has_gpu_reset(dev_priv) && |
3691 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3692 | } |
3693 | ||
c033666a | 3694 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3695 | { |
73974893 ML |
3696 | struct drm_device *dev = &dev_priv->drm; |
3697 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3698 | struct drm_atomic_state *state; | |
3699 | int ret; | |
3700 | ||
ce87ea15 DV |
3701 | |
3702 | /* reset doesn't touch the display */ | |
4f044a88 | 3703 | if (!i915_modparams.force_reset_modeset_test && |
ce87ea15 DV |
3704 | !gpu_reset_clobbers_display(dev_priv)) |
3705 | return; | |
3706 | ||
9db529aa DV |
3707 | /* We have a modeset vs reset deadlock, defensively unbreak it. */ |
3708 | set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); | |
3709 | wake_up_all(&dev_priv->gpu_error.wait_queue); | |
3710 | ||
3711 | if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { | |
3712 | DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n"); | |
3713 | i915_gem_set_wedged(dev_priv); | |
3714 | } | |
97154ec2 | 3715 | |
73974893 ML |
3716 | /* |
3717 | * Need mode_config.mutex so that we don't | |
3718 | * trample ongoing ->detect() and whatnot. | |
3719 | */ | |
3720 | mutex_lock(&dev->mode_config.mutex); | |
3721 | drm_modeset_acquire_init(ctx, 0); | |
3722 | while (1) { | |
3723 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3724 | if (ret != -EDEADLK) | |
3725 | break; | |
3726 | ||
3727 | drm_modeset_backoff(ctx); | |
3728 | } | |
f98ce92f VS |
3729 | /* |
3730 | * Disabling the crtcs gracefully seems nicer. Also the | |
3731 | * g33 docs say we should at least disable all the planes. | |
3732 | */ | |
73974893 ML |
3733 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3734 | if (IS_ERR(state)) { | |
3735 | ret = PTR_ERR(state); | |
73974893 | 3736 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
1e5a15d6 | 3737 | return; |
73974893 ML |
3738 | } |
3739 | ||
3740 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3741 | if (ret) { | |
3742 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
1e5a15d6 ACO |
3743 | drm_atomic_state_put(state); |
3744 | return; | |
73974893 ML |
3745 | } |
3746 | ||
3747 | dev_priv->modeset_restore_state = state; | |
3748 | state->acquire_ctx = ctx; | |
7514747d VS |
3749 | } |
3750 | ||
c033666a | 3751 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3752 | { |
73974893 ML |
3753 | struct drm_device *dev = &dev_priv->drm; |
3754 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3755 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3756 | int ret; | |
3757 | ||
ce87ea15 | 3758 | /* reset doesn't touch the display */ |
4f044a88 | 3759 | if (!i915_modparams.force_reset_modeset_test && |
ce87ea15 DV |
3760 | !gpu_reset_clobbers_display(dev_priv)) |
3761 | return; | |
3762 | ||
3763 | if (!state) | |
3764 | goto unlock; | |
3765 | ||
73974893 ML |
3766 | dev_priv->modeset_restore_state = NULL; |
3767 | ||
7514747d | 3768 | /* reset doesn't touch the display */ |
4ac2ba2f | 3769 | if (!gpu_reset_clobbers_display(dev_priv)) { |
ce87ea15 DV |
3770 | /* for testing only restore the display */ |
3771 | ret = __intel_display_resume(dev, state, ctx); | |
942d5d0d CW |
3772 | if (ret) |
3773 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
73974893 ML |
3774 | } else { |
3775 | /* | |
3776 | * The display has been reset as well, | |
3777 | * so need a full re-initialization. | |
3778 | */ | |
3779 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3780 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3781 | |
51f59205 | 3782 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3783 | intel_modeset_init_hw(dev); |
7514747d | 3784 | |
73974893 ML |
3785 | spin_lock_irq(&dev_priv->irq_lock); |
3786 | if (dev_priv->display.hpd_irq_setup) | |
3787 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3788 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3789 | |
581e49fe | 3790 | ret = __intel_display_resume(dev, state, ctx); |
73974893 ML |
3791 | if (ret) |
3792 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3793 | |
73974893 ML |
3794 | intel_hpd_init(dev_priv); |
3795 | } | |
7514747d | 3796 | |
ce87ea15 DV |
3797 | drm_atomic_state_put(state); |
3798 | unlock: | |
73974893 ML |
3799 | drm_modeset_drop_locks(ctx); |
3800 | drm_modeset_acquire_fini(ctx); | |
3801 | mutex_unlock(&dev->mode_config.mutex); | |
9db529aa DV |
3802 | |
3803 | clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); | |
7514747d VS |
3804 | } |
3805 | ||
1a15b77b VS |
3806 | static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state, |
3807 | const struct intel_crtc_state *new_crtc_state) | |
e30e8f75 | 3808 | { |
1a15b77b | 3809 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); |
6315b5d3 | 3810 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
e30e8f75 | 3811 | |
bfd16b2a | 3812 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
1a15b77b | 3813 | crtc->base.mode = new_crtc_state->base.mode; |
bfd16b2a | 3814 | |
e30e8f75 GP |
3815 | /* |
3816 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3817 | * that in compute_mode_changes we check the native mode (not the pfit | |
3818 | * mode) to see if we can flip rather than do a full mode set. In the | |
3819 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3820 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3821 | * sized surface. | |
e30e8f75 GP |
3822 | */ |
3823 | ||
e30e8f75 | 3824 | I915_WRITE(PIPESRC(crtc->pipe), |
1a15b77b VS |
3825 | ((new_crtc_state->pipe_src_w - 1) << 16) | |
3826 | (new_crtc_state->pipe_src_h - 1)); | |
bfd16b2a ML |
3827 | |
3828 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3829 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3830 | skl_detach_scalers(crtc); |
3831 | ||
1a15b77b | 3832 | if (new_crtc_state->pch_pfit.enabled) |
bfd16b2a | 3833 | skylake_pfit_enable(crtc); |
6e266956 | 3834 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
1a15b77b | 3835 | if (new_crtc_state->pch_pfit.enabled) |
bfd16b2a ML |
3836 | ironlake_pfit_enable(crtc); |
3837 | else if (old_crtc_state->pch_pfit.enabled) | |
3838 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3839 | } |
e30e8f75 GP |
3840 | } |
3841 | ||
4cbe4b2b | 3842 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 3843 | { |
4cbe4b2b | 3844 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3845 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3846 | int pipe = crtc->pipe; |
f0f59a00 VS |
3847 | i915_reg_t reg; |
3848 | u32 temp; | |
5e84e1a4 ZW |
3849 | |
3850 | /* enable normal train */ | |
3851 | reg = FDI_TX_CTL(pipe); | |
3852 | temp = I915_READ(reg); | |
fd6b8f43 | 3853 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3854 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3855 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3856 | } else { |
3857 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3858 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3859 | } |
5e84e1a4 ZW |
3860 | I915_WRITE(reg, temp); |
3861 | ||
3862 | reg = FDI_RX_CTL(pipe); | |
3863 | temp = I915_READ(reg); | |
6e266956 | 3864 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3865 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3866 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3867 | } else { | |
3868 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3869 | temp |= FDI_LINK_TRAIN_NONE; | |
3870 | } | |
3871 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3872 | ||
3873 | /* wait one idle pattern time */ | |
3874 | POSTING_READ(reg); | |
3875 | udelay(1000); | |
357555c0 JB |
3876 | |
3877 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3878 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3879 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3880 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3881 | } |
3882 | ||
8db9d77b | 3883 | /* The FDI link training functions for ILK/Ibexpeak. */ |
dc4a1094 ACO |
3884 | static void ironlake_fdi_link_train(struct intel_crtc *crtc, |
3885 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3886 | { |
4cbe4b2b | 3887 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3888 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3889 | int pipe = crtc->pipe; |
f0f59a00 VS |
3890 | i915_reg_t reg; |
3891 | u32 temp, tries; | |
8db9d77b | 3892 | |
1c8562f6 | 3893 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3894 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3895 | |
e1a44743 AJ |
3896 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3897 | for train result */ | |
5eddb70b CW |
3898 | reg = FDI_RX_IMR(pipe); |
3899 | temp = I915_READ(reg); | |
e1a44743 AJ |
3900 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3901 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3902 | I915_WRITE(reg, temp); |
3903 | I915_READ(reg); | |
e1a44743 AJ |
3904 | udelay(150); |
3905 | ||
8db9d77b | 3906 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3907 | reg = FDI_TX_CTL(pipe); |
3908 | temp = I915_READ(reg); | |
627eb5a3 | 3909 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3910 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3911 | temp &= ~FDI_LINK_TRAIN_NONE; |
3912 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3913 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3914 | |
5eddb70b CW |
3915 | reg = FDI_RX_CTL(pipe); |
3916 | temp = I915_READ(reg); | |
8db9d77b ZW |
3917 | temp &= ~FDI_LINK_TRAIN_NONE; |
3918 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3919 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3920 | ||
3921 | POSTING_READ(reg); | |
8db9d77b ZW |
3922 | udelay(150); |
3923 | ||
5b2adf89 | 3924 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3925 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3926 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3927 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3928 | |
5eddb70b | 3929 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3930 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3931 | temp = I915_READ(reg); |
8db9d77b ZW |
3932 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3933 | ||
3934 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3935 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3936 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3937 | break; |
3938 | } | |
8db9d77b | 3939 | } |
e1a44743 | 3940 | if (tries == 5) |
5eddb70b | 3941 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3942 | |
3943 | /* Train 2 */ | |
5eddb70b CW |
3944 | reg = FDI_TX_CTL(pipe); |
3945 | temp = I915_READ(reg); | |
8db9d77b ZW |
3946 | temp &= ~FDI_LINK_TRAIN_NONE; |
3947 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3948 | I915_WRITE(reg, temp); |
8db9d77b | 3949 | |
5eddb70b CW |
3950 | reg = FDI_RX_CTL(pipe); |
3951 | temp = I915_READ(reg); | |
8db9d77b ZW |
3952 | temp &= ~FDI_LINK_TRAIN_NONE; |
3953 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3954 | I915_WRITE(reg, temp); |
8db9d77b | 3955 | |
5eddb70b CW |
3956 | POSTING_READ(reg); |
3957 | udelay(150); | |
8db9d77b | 3958 | |
5eddb70b | 3959 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3960 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3961 | temp = I915_READ(reg); |
8db9d77b ZW |
3962 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3963 | ||
3964 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3965 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3966 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3967 | break; | |
3968 | } | |
8db9d77b | 3969 | } |
e1a44743 | 3970 | if (tries == 5) |
5eddb70b | 3971 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3972 | |
3973 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3974 | |
8db9d77b ZW |
3975 | } |
3976 | ||
0206e353 | 3977 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3978 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3979 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3980 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3981 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3982 | }; | |
3983 | ||
3984 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
3985 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
3986 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3987 | { |
4cbe4b2b | 3988 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3989 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3990 | int pipe = crtc->pipe; |
f0f59a00 VS |
3991 | i915_reg_t reg; |
3992 | u32 temp, i, retry; | |
8db9d77b | 3993 | |
e1a44743 AJ |
3994 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3995 | for train result */ | |
5eddb70b CW |
3996 | reg = FDI_RX_IMR(pipe); |
3997 | temp = I915_READ(reg); | |
e1a44743 AJ |
3998 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3999 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
4000 | I915_WRITE(reg, temp); |
4001 | ||
4002 | POSTING_READ(reg); | |
e1a44743 AJ |
4003 | udelay(150); |
4004 | ||
8db9d77b | 4005 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
4006 | reg = FDI_TX_CTL(pipe); |
4007 | temp = I915_READ(reg); | |
627eb5a3 | 4008 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 4009 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
4010 | temp &= ~FDI_LINK_TRAIN_NONE; |
4011 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4012 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
4013 | /* SNB-B */ | |
4014 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 4015 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 4016 | |
d74cf324 DV |
4017 | I915_WRITE(FDI_RX_MISC(pipe), |
4018 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
4019 | ||
5eddb70b CW |
4020 | reg = FDI_RX_CTL(pipe); |
4021 | temp = I915_READ(reg); | |
6e266956 | 4022 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
4023 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4024 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4025 | } else { | |
4026 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4027 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4028 | } | |
5eddb70b CW |
4029 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
4030 | ||
4031 | POSTING_READ(reg); | |
8db9d77b ZW |
4032 | udelay(150); |
4033 | ||
0206e353 | 4034 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
4035 | reg = FDI_TX_CTL(pipe); |
4036 | temp = I915_READ(reg); | |
8db9d77b ZW |
4037 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
4038 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
4039 | I915_WRITE(reg, temp); |
4040 | ||
4041 | POSTING_READ(reg); | |
8db9d77b ZW |
4042 | udelay(500); |
4043 | ||
fa37d39e SP |
4044 | for (retry = 0; retry < 5; retry++) { |
4045 | reg = FDI_RX_IIR(pipe); | |
4046 | temp = I915_READ(reg); | |
4047 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
4048 | if (temp & FDI_RX_BIT_LOCK) { | |
4049 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4050 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
4051 | break; | |
4052 | } | |
4053 | udelay(50); | |
8db9d77b | 4054 | } |
fa37d39e SP |
4055 | if (retry < 5) |
4056 | break; | |
8db9d77b ZW |
4057 | } |
4058 | if (i == 4) | |
5eddb70b | 4059 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
4060 | |
4061 | /* Train 2 */ | |
5eddb70b CW |
4062 | reg = FDI_TX_CTL(pipe); |
4063 | temp = I915_READ(reg); | |
8db9d77b ZW |
4064 | temp &= ~FDI_LINK_TRAIN_NONE; |
4065 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 4066 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
4067 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
4068 | /* SNB-B */ | |
4069 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
4070 | } | |
5eddb70b | 4071 | I915_WRITE(reg, temp); |
8db9d77b | 4072 | |
5eddb70b CW |
4073 | reg = FDI_RX_CTL(pipe); |
4074 | temp = I915_READ(reg); | |
6e266956 | 4075 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
4076 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4077 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
4078 | } else { | |
4079 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4080 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
4081 | } | |
5eddb70b CW |
4082 | I915_WRITE(reg, temp); |
4083 | ||
4084 | POSTING_READ(reg); | |
8db9d77b ZW |
4085 | udelay(150); |
4086 | ||
0206e353 | 4087 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
4088 | reg = FDI_TX_CTL(pipe); |
4089 | temp = I915_READ(reg); | |
8db9d77b ZW |
4090 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
4091 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
4092 | I915_WRITE(reg, temp); |
4093 | ||
4094 | POSTING_READ(reg); | |
8db9d77b ZW |
4095 | udelay(500); |
4096 | ||
fa37d39e SP |
4097 | for (retry = 0; retry < 5; retry++) { |
4098 | reg = FDI_RX_IIR(pipe); | |
4099 | temp = I915_READ(reg); | |
4100 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
4101 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
4102 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4103 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
4104 | break; | |
4105 | } | |
4106 | udelay(50); | |
8db9d77b | 4107 | } |
fa37d39e SP |
4108 | if (retry < 5) |
4109 | break; | |
8db9d77b ZW |
4110 | } |
4111 | if (i == 4) | |
5eddb70b | 4112 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
4113 | |
4114 | DRM_DEBUG_KMS("FDI train done.\n"); | |
4115 | } | |
4116 | ||
357555c0 | 4117 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
4118 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
4119 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 4120 | { |
4cbe4b2b | 4121 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4122 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4123 | int pipe = crtc->pipe; |
f0f59a00 VS |
4124 | i915_reg_t reg; |
4125 | u32 temp, i, j; | |
357555c0 JB |
4126 | |
4127 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
4128 | for train result */ | |
4129 | reg = FDI_RX_IMR(pipe); | |
4130 | temp = I915_READ(reg); | |
4131 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
4132 | temp &= ~FDI_RX_BIT_LOCK; | |
4133 | I915_WRITE(reg, temp); | |
4134 | ||
4135 | POSTING_READ(reg); | |
4136 | udelay(150); | |
4137 | ||
01a415fd DV |
4138 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
4139 | I915_READ(FDI_RX_IIR(pipe))); | |
4140 | ||
139ccd3f JB |
4141 | /* Try each vswing and preemphasis setting twice before moving on */ |
4142 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
4143 | /* disable first in case we need to retry */ | |
4144 | reg = FDI_TX_CTL(pipe); | |
4145 | temp = I915_READ(reg); | |
4146 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
4147 | temp &= ~FDI_TX_ENABLE; | |
4148 | I915_WRITE(reg, temp); | |
357555c0 | 4149 | |
139ccd3f JB |
4150 | reg = FDI_RX_CTL(pipe); |
4151 | temp = I915_READ(reg); | |
4152 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
4153 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4154 | temp &= ~FDI_RX_ENABLE; | |
4155 | I915_WRITE(reg, temp); | |
357555c0 | 4156 | |
139ccd3f | 4157 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
4158 | reg = FDI_TX_CTL(pipe); |
4159 | temp = I915_READ(reg); | |
139ccd3f | 4160 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 4161 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 4162 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 4163 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4164 | temp |= snb_b_fdi_train_param[j/2]; |
4165 | temp |= FDI_COMPOSITE_SYNC; | |
4166 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4167 | |
139ccd3f JB |
4168 | I915_WRITE(FDI_RX_MISC(pipe), |
4169 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4170 | |
139ccd3f | 4171 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4172 | temp = I915_READ(reg); |
139ccd3f JB |
4173 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4174 | temp |= FDI_COMPOSITE_SYNC; | |
4175 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4176 | |
139ccd3f JB |
4177 | POSTING_READ(reg); |
4178 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4179 | |
139ccd3f JB |
4180 | for (i = 0; i < 4; i++) { |
4181 | reg = FDI_RX_IIR(pipe); | |
4182 | temp = I915_READ(reg); | |
4183 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4184 | |
139ccd3f JB |
4185 | if (temp & FDI_RX_BIT_LOCK || |
4186 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4187 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4188 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4189 | i); | |
4190 | break; | |
4191 | } | |
4192 | udelay(1); /* should be 0.5us */ | |
4193 | } | |
4194 | if (i == 4) { | |
4195 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4196 | continue; | |
4197 | } | |
357555c0 | 4198 | |
139ccd3f | 4199 | /* Train 2 */ |
357555c0 JB |
4200 | reg = FDI_TX_CTL(pipe); |
4201 | temp = I915_READ(reg); | |
139ccd3f JB |
4202 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4203 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4204 | I915_WRITE(reg, temp); | |
4205 | ||
4206 | reg = FDI_RX_CTL(pipe); | |
4207 | temp = I915_READ(reg); | |
4208 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4209 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4210 | I915_WRITE(reg, temp); |
4211 | ||
4212 | POSTING_READ(reg); | |
139ccd3f | 4213 | udelay(2); /* should be 1.5us */ |
357555c0 | 4214 | |
139ccd3f JB |
4215 | for (i = 0; i < 4; i++) { |
4216 | reg = FDI_RX_IIR(pipe); | |
4217 | temp = I915_READ(reg); | |
4218 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4219 | |
139ccd3f JB |
4220 | if (temp & FDI_RX_SYMBOL_LOCK || |
4221 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4222 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4223 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4224 | i); | |
4225 | goto train_done; | |
4226 | } | |
4227 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4228 | } |
139ccd3f JB |
4229 | if (i == 4) |
4230 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4231 | } |
357555c0 | 4232 | |
139ccd3f | 4233 | train_done: |
357555c0 JB |
4234 | DRM_DEBUG_KMS("FDI train done.\n"); |
4235 | } | |
4236 | ||
88cefb6c | 4237 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4238 | { |
88cefb6c | 4239 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4240 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4241 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4242 | i915_reg_t reg; |
4243 | u32 temp; | |
c64e311e | 4244 | |
c98e9dcf | 4245 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4246 | reg = FDI_RX_CTL(pipe); |
4247 | temp = I915_READ(reg); | |
627eb5a3 | 4248 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4249 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4250 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4251 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4252 | ||
4253 | POSTING_READ(reg); | |
c98e9dcf JB |
4254 | udelay(200); |
4255 | ||
4256 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4257 | temp = I915_READ(reg); |
4258 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4259 | ||
4260 | POSTING_READ(reg); | |
c98e9dcf JB |
4261 | udelay(200); |
4262 | ||
20749730 PZ |
4263 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4264 | reg = FDI_TX_CTL(pipe); | |
4265 | temp = I915_READ(reg); | |
4266 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4267 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4268 | |
20749730 PZ |
4269 | POSTING_READ(reg); |
4270 | udelay(100); | |
6be4a607 | 4271 | } |
0e23b99d JB |
4272 | } |
4273 | ||
88cefb6c DV |
4274 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4275 | { | |
4276 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4277 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4278 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4279 | i915_reg_t reg; |
4280 | u32 temp; | |
88cefb6c DV |
4281 | |
4282 | /* Switch from PCDclk to Rawclk */ | |
4283 | reg = FDI_RX_CTL(pipe); | |
4284 | temp = I915_READ(reg); | |
4285 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4286 | ||
4287 | /* Disable CPU FDI TX PLL */ | |
4288 | reg = FDI_TX_CTL(pipe); | |
4289 | temp = I915_READ(reg); | |
4290 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4291 | ||
4292 | POSTING_READ(reg); | |
4293 | udelay(100); | |
4294 | ||
4295 | reg = FDI_RX_CTL(pipe); | |
4296 | temp = I915_READ(reg); | |
4297 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4298 | ||
4299 | /* Wait for the clocks to turn off. */ | |
4300 | POSTING_READ(reg); | |
4301 | udelay(100); | |
4302 | } | |
4303 | ||
0fc932b8 JB |
4304 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4305 | { | |
4306 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4307 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4308 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4309 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4310 | i915_reg_t reg; |
4311 | u32 temp; | |
0fc932b8 JB |
4312 | |
4313 | /* disable CPU FDI tx and PCH FDI rx */ | |
4314 | reg = FDI_TX_CTL(pipe); | |
4315 | temp = I915_READ(reg); | |
4316 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4317 | POSTING_READ(reg); | |
4318 | ||
4319 | reg = FDI_RX_CTL(pipe); | |
4320 | temp = I915_READ(reg); | |
4321 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4322 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4323 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4324 | ||
4325 | POSTING_READ(reg); | |
4326 | udelay(100); | |
4327 | ||
4328 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4329 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4330 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4331 | |
4332 | /* still set train pattern 1 */ | |
4333 | reg = FDI_TX_CTL(pipe); | |
4334 | temp = I915_READ(reg); | |
4335 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4336 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4337 | I915_WRITE(reg, temp); | |
4338 | ||
4339 | reg = FDI_RX_CTL(pipe); | |
4340 | temp = I915_READ(reg); | |
6e266956 | 4341 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4342 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4343 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4344 | } else { | |
4345 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4346 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4347 | } | |
4348 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4349 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4350 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4351 | I915_WRITE(reg, temp); |
4352 | ||
4353 | POSTING_READ(reg); | |
4354 | udelay(100); | |
4355 | } | |
4356 | ||
49d73912 | 4357 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 | 4358 | { |
fa05887a DV |
4359 | struct drm_crtc *crtc; |
4360 | bool cleanup_done; | |
4361 | ||
4362 | drm_for_each_crtc(crtc, &dev_priv->drm) { | |
4363 | struct drm_crtc_commit *commit; | |
4364 | spin_lock(&crtc->commit_lock); | |
4365 | commit = list_first_entry_or_null(&crtc->commit_list, | |
4366 | struct drm_crtc_commit, commit_entry); | |
4367 | cleanup_done = commit ? | |
4368 | try_wait_for_completion(&commit->cleanup_done) : true; | |
4369 | spin_unlock(&crtc->commit_lock); | |
4370 | ||
4371 | if (cleanup_done) | |
5dce5b93 CW |
4372 | continue; |
4373 | ||
fa05887a | 4374 | drm_crtc_wait_one_vblank(crtc); |
5dce5b93 CW |
4375 | |
4376 | return true; | |
4377 | } | |
4378 | ||
4379 | return false; | |
4380 | } | |
4381 | ||
b7076546 | 4382 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4383 | { |
4384 | u32 temp; | |
4385 | ||
4386 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4387 | ||
4388 | mutex_lock(&dev_priv->sb_lock); | |
4389 | ||
4390 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4391 | temp |= SBI_SSCCTL_DISABLE; | |
4392 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4393 | ||
4394 | mutex_unlock(&dev_priv->sb_lock); | |
4395 | } | |
4396 | ||
e615efe4 | 4397 | /* Program iCLKIP clock to the desired frequency */ |
0dcdc382 | 4398 | static void lpt_program_iclkip(struct intel_crtc *crtc) |
e615efe4 | 4399 | { |
0dcdc382 ACO |
4400 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4401 | int clock = crtc->config->base.adjusted_mode.crtc_clock; | |
e615efe4 ED |
4402 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4403 | u32 temp; | |
4404 | ||
060f02d8 | 4405 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4406 | |
64b46a06 VS |
4407 | /* The iCLK virtual clock root frequency is in MHz, |
4408 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4409 | * divisors, it is necessary to divide one by another, so we | |
4410 | * convert the virtual clock precision to KHz here for higher | |
4411 | * precision. | |
4412 | */ | |
4413 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4414 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4415 | u32 iclk_pi_range = 64; | |
64b46a06 | 4416 | u32 desired_divisor; |
e615efe4 | 4417 | |
64b46a06 VS |
4418 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4419 | clock << auxdiv); | |
4420 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4421 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4422 | |
64b46a06 VS |
4423 | /* |
4424 | * Near 20MHz is a corner case which is | |
4425 | * out of range for the 7-bit divisor | |
4426 | */ | |
4427 | if (divsel <= 0x7f) | |
4428 | break; | |
e615efe4 ED |
4429 | } |
4430 | ||
4431 | /* This should not happen with any sane values */ | |
4432 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4433 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4434 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4435 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4436 | ||
4437 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4438 | clock, |
e615efe4 ED |
4439 | auxdiv, |
4440 | divsel, | |
4441 | phasedir, | |
4442 | phaseinc); | |
4443 | ||
060f02d8 VS |
4444 | mutex_lock(&dev_priv->sb_lock); |
4445 | ||
e615efe4 | 4446 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4447 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4448 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4449 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4450 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4451 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4452 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4453 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4454 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4455 | |
4456 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4457 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4458 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4459 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4460 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4461 | |
4462 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4463 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4464 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4465 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4466 | |
060f02d8 VS |
4467 | mutex_unlock(&dev_priv->sb_lock); |
4468 | ||
e615efe4 ED |
4469 | /* Wait for initialization time */ |
4470 | udelay(24); | |
4471 | ||
4472 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4473 | } | |
4474 | ||
8802e5b6 VS |
4475 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4476 | { | |
4477 | u32 divsel, phaseinc, auxdiv; | |
4478 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4479 | u32 iclk_pi_range = 64; | |
4480 | u32 desired_divisor; | |
4481 | u32 temp; | |
4482 | ||
4483 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4484 | return 0; | |
4485 | ||
4486 | mutex_lock(&dev_priv->sb_lock); | |
4487 | ||
4488 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4489 | if (temp & SBI_SSCCTL_DISABLE) { | |
4490 | mutex_unlock(&dev_priv->sb_lock); | |
4491 | return 0; | |
4492 | } | |
4493 | ||
4494 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4495 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4496 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4497 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4498 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4499 | ||
4500 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4501 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4502 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4503 | ||
4504 | mutex_unlock(&dev_priv->sb_lock); | |
4505 | ||
4506 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4507 | ||
4508 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4509 | desired_divisor << auxdiv); | |
4510 | } | |
4511 | ||
275f01b2 DV |
4512 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4513 | enum pipe pch_transcoder) | |
4514 | { | |
4515 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4516 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4517 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4518 | |
4519 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4520 | I915_READ(HTOTAL(cpu_transcoder))); | |
4521 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4522 | I915_READ(HBLANK(cpu_transcoder))); | |
4523 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4524 | I915_READ(HSYNC(cpu_transcoder))); | |
4525 | ||
4526 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4527 | I915_READ(VTOTAL(cpu_transcoder))); | |
4528 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4529 | I915_READ(VBLANK(cpu_transcoder))); | |
4530 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4531 | I915_READ(VSYNC(cpu_transcoder))); | |
4532 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4533 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4534 | } | |
4535 | ||
003632d9 | 4536 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4537 | { |
fac5e23e | 4538 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4539 | uint32_t temp; |
4540 | ||
4541 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4542 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4543 | return; |
4544 | ||
4545 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4546 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4547 | ||
003632d9 ACO |
4548 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4549 | if (enable) | |
4550 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4551 | ||
4552 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4553 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4554 | POSTING_READ(SOUTH_CHICKEN1); | |
4555 | } | |
4556 | ||
4557 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4558 | { | |
4559 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4560 | |
4561 | switch (intel_crtc->pipe) { | |
4562 | case PIPE_A: | |
4563 | break; | |
4564 | case PIPE_B: | |
6e3c9717 | 4565 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4566 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4567 | else |
003632d9 | 4568 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4569 | |
4570 | break; | |
4571 | case PIPE_C: | |
003632d9 | 4572 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4573 | |
4574 | break; | |
4575 | default: | |
4576 | BUG(); | |
4577 | } | |
4578 | } | |
4579 | ||
c48b5305 VS |
4580 | /* Return which DP Port should be selected for Transcoder DP control */ |
4581 | static enum port | |
4cbe4b2b | 4582 | intel_trans_dp_port_sel(struct intel_crtc *crtc) |
c48b5305 | 4583 | { |
4cbe4b2b | 4584 | struct drm_device *dev = crtc->base.dev; |
c48b5305 VS |
4585 | struct intel_encoder *encoder; |
4586 | ||
4cbe4b2b | 4587 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
cca0502b | 4588 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4589 | encoder->type == INTEL_OUTPUT_EDP) |
4590 | return enc_to_dig_port(&encoder->base)->port; | |
4591 | } | |
4592 | ||
4593 | return -1; | |
4594 | } | |
4595 | ||
f67a559d JB |
4596 | /* |
4597 | * Enable PCH resources required for PCH ports: | |
4598 | * - PCH PLLs | |
4599 | * - FDI training & RX/TX | |
4600 | * - update transcoder timings | |
4601 | * - DP transcoding bits | |
4602 | * - transcoder | |
4603 | */ | |
2ce42273 | 4604 | static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) |
0e23b99d | 4605 | { |
2ce42273 | 4606 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
4cbe4b2b | 4607 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4608 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4609 | int pipe = crtc->pipe; |
f0f59a00 | 4610 | u32 temp; |
2c07245f | 4611 | |
ab9412ba | 4612 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4613 | |
fd6b8f43 | 4614 | if (IS_IVYBRIDGE(dev_priv)) |
4cbe4b2b | 4615 | ivybridge_update_fdi_bc_bifurcation(crtc); |
1fbc0d78 | 4616 | |
cd986abb DV |
4617 | /* Write the TU size bits before fdi link training, so that error |
4618 | * detection works. */ | |
4619 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4620 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4621 | ||
c98e9dcf | 4622 | /* For PCH output, training FDI link */ |
dc4a1094 | 4623 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 4624 | |
3ad8a208 DV |
4625 | /* We need to program the right clock selection before writing the pixel |
4626 | * mutliplier into the DPLL. */ | |
6e266956 | 4627 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4628 | u32 sel; |
4b645f14 | 4629 | |
c98e9dcf | 4630 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4631 | temp |= TRANS_DPLL_ENABLE(pipe); |
4632 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 4633 | if (crtc_state->shared_dpll == |
8106ddbd | 4634 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
4635 | temp |= sel; |
4636 | else | |
4637 | temp &= ~sel; | |
c98e9dcf | 4638 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4639 | } |
5eddb70b | 4640 | |
3ad8a208 DV |
4641 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4642 | * transcoder, and we actually should do this to not upset any PCH | |
4643 | * transcoder that already use the clock when we share it. | |
4644 | * | |
4645 | * Note that enable_shared_dpll tries to do the right thing, but | |
4646 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4647 | * the right LVDS enable sequence. */ | |
4cbe4b2b | 4648 | intel_enable_shared_dpll(crtc); |
3ad8a208 | 4649 | |
d9b6cb56 JB |
4650 | /* set transcoder timing, panel must allow it */ |
4651 | assert_panel_unlocked(dev_priv, pipe); | |
4cbe4b2b | 4652 | ironlake_pch_transcoder_set_timings(crtc, pipe); |
8db9d77b | 4653 | |
303b81e0 | 4654 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4655 | |
c98e9dcf | 4656 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 4657 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 4658 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 4659 | const struct drm_display_mode *adjusted_mode = |
2ce42273 | 4660 | &crtc_state->base.adjusted_mode; |
dfd07d72 | 4661 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4662 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4663 | temp = I915_READ(reg); |
4664 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4665 | TRANS_DP_SYNC_MASK | |
4666 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4667 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4668 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4669 | |
9c4edaee | 4670 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4671 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4672 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4673 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4674 | |
4675 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4676 | case PORT_B: |
5eddb70b | 4677 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4678 | break; |
c48b5305 | 4679 | case PORT_C: |
5eddb70b | 4680 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4681 | break; |
c48b5305 | 4682 | case PORT_D: |
5eddb70b | 4683 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4684 | break; |
4685 | default: | |
e95d41e1 | 4686 | BUG(); |
32f9d658 | 4687 | } |
2c07245f | 4688 | |
5eddb70b | 4689 | I915_WRITE(reg, temp); |
6be4a607 | 4690 | } |
b52eb4dc | 4691 | |
b8a4f404 | 4692 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4693 | } |
4694 | ||
2ce42273 | 4695 | static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 4696 | { |
2ce42273 | 4697 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
0dcdc382 | 4698 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 4699 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 4700 | |
a2196033 | 4701 | assert_pch_transcoder_disabled(dev_priv, PIPE_A); |
1507e5bd | 4702 | |
8c52b5e8 | 4703 | lpt_program_iclkip(crtc); |
1507e5bd | 4704 | |
0540e488 | 4705 | /* Set transcoder timing. */ |
0dcdc382 | 4706 | ironlake_pch_transcoder_set_timings(crtc, PIPE_A); |
1507e5bd | 4707 | |
937bb610 | 4708 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4709 | } |
4710 | ||
a1520318 | 4711 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4712 | { |
fac5e23e | 4713 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4714 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4715 | u32 temp; |
4716 | ||
4717 | temp = I915_READ(dslreg); | |
4718 | udelay(500); | |
4719 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4720 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4721 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4722 | } |
4723 | } | |
4724 | ||
86adf9d7 ML |
4725 | static int |
4726 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
d96a7d2a | 4727 | unsigned int scaler_user, int *scaler_id, |
86adf9d7 | 4728 | int src_w, int src_h, int dst_w, int dst_h) |
a1b2278e | 4729 | { |
86adf9d7 ML |
4730 | struct intel_crtc_scaler_state *scaler_state = |
4731 | &crtc_state->scaler_state; | |
4732 | struct intel_crtc *intel_crtc = | |
4733 | to_intel_crtc(crtc_state->base.crtc); | |
7f58cbb1 MK |
4734 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
4735 | const struct drm_display_mode *adjusted_mode = | |
4736 | &crtc_state->base.adjusted_mode; | |
a1b2278e | 4737 | int need_scaling; |
6156a456 | 4738 | |
d96a7d2a VS |
4739 | /* |
4740 | * Src coordinates are already rotated by 270 degrees for | |
4741 | * the 90/270 degree plane rotation cases (to match the | |
4742 | * GTT mapping), hence no need to account for rotation here. | |
4743 | */ | |
4744 | need_scaling = src_w != dst_w || src_h != dst_h; | |
a1b2278e | 4745 | |
e5c05931 SS |
4746 | if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) |
4747 | need_scaling = true; | |
4748 | ||
7f58cbb1 MK |
4749 | /* |
4750 | * Scaling/fitting not supported in IF-ID mode in GEN9+ | |
4751 | * TODO: Interlace fetch mode doesn't support YUV420 planar formats. | |
4752 | * Once NV12 is enabled, handle it here while allocating scaler | |
4753 | * for NV12. | |
4754 | */ | |
4755 | if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && | |
4756 | need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4757 | DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n"); | |
4758 | return -EINVAL; | |
4759 | } | |
4760 | ||
a1b2278e CK |
4761 | /* |
4762 | * if plane is being disabled or scaler is no more required or force detach | |
4763 | * - free scaler binded to this plane/crtc | |
4764 | * - in order to do this, update crtc->scaler_usage | |
4765 | * | |
4766 | * Here scaler state in crtc_state is set free so that | |
4767 | * scaler can be assigned to other user. Actual register | |
4768 | * update to free the scaler is done in plane/panel-fit programming. | |
4769 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4770 | */ | |
86adf9d7 | 4771 | if (force_detach || !need_scaling) { |
a1b2278e | 4772 | if (*scaler_id >= 0) { |
86adf9d7 | 4773 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4774 | scaler_state->scalers[*scaler_id].in_use = 0; |
4775 | ||
86adf9d7 ML |
4776 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4777 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4778 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4779 | scaler_state->scaler_users); |
4780 | *scaler_id = -1; | |
4781 | } | |
4782 | return 0; | |
4783 | } | |
4784 | ||
4785 | /* range checks */ | |
4786 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4787 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4788 | ||
4789 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4790 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4791 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4792 | "size is out of scaler range\n", |
86adf9d7 | 4793 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4794 | return -EINVAL; |
4795 | } | |
4796 | ||
86adf9d7 ML |
4797 | /* mark this plane as a scaler user in crtc_state */ |
4798 | scaler_state->scaler_users |= (1 << scaler_user); | |
4799 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4800 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4801 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4802 | scaler_state->scaler_users); | |
4803 | ||
4804 | return 0; | |
4805 | } | |
4806 | ||
4807 | /** | |
4808 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4809 | * | |
4810 | * @state: crtc's scaler state | |
86adf9d7 ML |
4811 | * |
4812 | * Return | |
4813 | * 0 - scaler_usage updated successfully | |
4814 | * error - requested scaling cannot be supported or other error condition | |
4815 | */ | |
e435d6e5 | 4816 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4817 | { |
7c5f93b0 | 4818 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4819 | |
e435d6e5 | 4820 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
d96a7d2a | 4821 | &state->scaler_state.scaler_id, |
86adf9d7 | 4822 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4823 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4824 | } |
4825 | ||
4826 | /** | |
4827 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4828 | * | |
4829 | * @state: crtc's scaler state | |
86adf9d7 ML |
4830 | * @plane_state: atomic plane state to update |
4831 | * | |
4832 | * Return | |
4833 | * 0 - scaler_usage updated successfully | |
4834 | * error - requested scaling cannot be supported or other error condition | |
4835 | */ | |
da20eabd ML |
4836 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4837 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4838 | { |
4839 | ||
da20eabd ML |
4840 | struct intel_plane *intel_plane = |
4841 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4842 | struct drm_framebuffer *fb = plane_state->base.fb; |
4843 | int ret; | |
4844 | ||
936e71e3 | 4845 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4846 | |
86adf9d7 ML |
4847 | ret = skl_update_scaler(crtc_state, force_detach, |
4848 | drm_plane_index(&intel_plane->base), | |
4849 | &plane_state->scaler_id, | |
936e71e3 VS |
4850 | drm_rect_width(&plane_state->base.src) >> 16, |
4851 | drm_rect_height(&plane_state->base.src) >> 16, | |
4852 | drm_rect_width(&plane_state->base.dst), | |
4853 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4854 | |
4855 | if (ret || plane_state->scaler_id < 0) | |
4856 | return ret; | |
4857 | ||
a1b2278e | 4858 | /* check colorkey */ |
818ed961 | 4859 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4860 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4861 | intel_plane->base.base.id, | |
4862 | intel_plane->base.name); | |
a1b2278e CK |
4863 | return -EINVAL; |
4864 | } | |
4865 | ||
4866 | /* Check src format */ | |
438b74a5 | 4867 | switch (fb->format->format) { |
86adf9d7 ML |
4868 | case DRM_FORMAT_RGB565: |
4869 | case DRM_FORMAT_XBGR8888: | |
4870 | case DRM_FORMAT_XRGB8888: | |
4871 | case DRM_FORMAT_ABGR8888: | |
4872 | case DRM_FORMAT_ARGB8888: | |
4873 | case DRM_FORMAT_XRGB2101010: | |
4874 | case DRM_FORMAT_XBGR2101010: | |
4875 | case DRM_FORMAT_YUYV: | |
4876 | case DRM_FORMAT_YVYU: | |
4877 | case DRM_FORMAT_UYVY: | |
4878 | case DRM_FORMAT_VYUY: | |
4879 | break; | |
4880 | default: | |
72660ce0 VS |
4881 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4882 | intel_plane->base.base.id, intel_plane->base.name, | |
438b74a5 | 4883 | fb->base.id, fb->format->format); |
86adf9d7 | 4884 | return -EINVAL; |
a1b2278e CK |
4885 | } |
4886 | ||
a1b2278e CK |
4887 | return 0; |
4888 | } | |
4889 | ||
e435d6e5 ML |
4890 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4891 | { | |
4892 | int i; | |
4893 | ||
4894 | for (i = 0; i < crtc->num_scalers; i++) | |
4895 | skl_detach_scaler(crtc, i); | |
4896 | } | |
4897 | ||
4898 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4899 | { |
4900 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4901 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4902 | int pipe = crtc->pipe; |
a1b2278e CK |
4903 | struct intel_crtc_scaler_state *scaler_state = |
4904 | &crtc->config->scaler_state; | |
4905 | ||
6e3c9717 | 4906 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4907 | int id; |
4908 | ||
c3f8ad57 | 4909 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) |
a1b2278e | 4910 | return; |
a1b2278e CK |
4911 | |
4912 | id = scaler_state->scaler_id; | |
4913 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4914 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4915 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4916 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4917 | } |
4918 | } | |
4919 | ||
b074cec8 JB |
4920 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4921 | { | |
4922 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4923 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4924 | int pipe = crtc->pipe; |
4925 | ||
6e3c9717 | 4926 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4927 | /* Force use of hard-coded filter coefficients |
4928 | * as some pre-programmed values are broken, | |
4929 | * e.g. x201. | |
4930 | */ | |
fd6b8f43 | 4931 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4932 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4933 | PF_PIPE_SEL_IVB(pipe)); | |
4934 | else | |
4935 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4936 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4937 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4938 | } |
4939 | } | |
4940 | ||
20bc8673 | 4941 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4942 | { |
cea165c3 | 4943 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4944 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4945 | |
6e3c9717 | 4946 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4947 | return; |
4948 | ||
307e4498 ML |
4949 | /* |
4950 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4951 | * This function is called from post_plane_update, which is run after | |
4952 | * a vblank wait. | |
4953 | */ | |
cea165c3 | 4954 | |
d77e4531 | 4955 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4956 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 | 4957 | mutex_lock(&dev_priv->rps.hw_lock); |
61843f0e VS |
4958 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, |
4959 | IPS_ENABLE | IPS_PCODE_CONTROL)); | |
2a114cc1 BW |
4960 | mutex_unlock(&dev_priv->rps.hw_lock); |
4961 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4962 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4963 | * mailbox." Moreover, the mailbox may return a bogus state, |
4964 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4965 | */ |
4966 | } else { | |
4967 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4968 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4969 | * is essentially intel_wait_for_vblank. If we don't have this | |
4970 | * and don't wait for vblanks until the end of crtc_enable, then | |
4971 | * the HW state readout code will complain that the expected | |
4972 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4973 | if (intel_wait_for_register(dev_priv, |
4974 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4975 | 50)) | |
2a114cc1 BW |
4976 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4977 | } | |
d77e4531 PZ |
4978 | } |
4979 | ||
20bc8673 | 4980 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4981 | { |
4982 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4983 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4984 | |
6e3c9717 | 4985 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4986 | return; |
4987 | ||
4988 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4989 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4990 | mutex_lock(&dev_priv->rps.hw_lock); |
4991 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4992 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4993 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4994 | if (intel_wait_for_register(dev_priv, |
4995 | IPS_CTL, IPS_ENABLE, 0, | |
4996 | 42)) | |
23d0b130 | 4997 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4998 | } else { |
2a114cc1 | 4999 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
5000 | POSTING_READ(IPS_CTL); |
5001 | } | |
d77e4531 PZ |
5002 | |
5003 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 5004 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
5005 | } |
5006 | ||
7cac945f | 5007 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 5008 | { |
7cac945f | 5009 | if (intel_crtc->overlay) { |
d3eedb1a | 5010 | struct drm_device *dev = intel_crtc->base.dev; |
d3eedb1a VS |
5011 | |
5012 | mutex_lock(&dev->struct_mutex); | |
d3eedb1a | 5013 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
d3eedb1a VS |
5014 | mutex_unlock(&dev->struct_mutex); |
5015 | } | |
5016 | ||
5017 | /* Let userspace switch the overlay on again. In most cases userspace | |
5018 | * has to recompute where to put it anyway. | |
5019 | */ | |
5020 | } | |
5021 | ||
87d4300a ML |
5022 | /** |
5023 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
5024 | * @crtc: the CRTC whose primary plane was just enabled | |
5025 | * | |
5026 | * Performs potentially sleeping operations that must be done after the primary | |
5027 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
5028 | * called due to an explicit primary plane update, or due to an implicit | |
5029 | * re-enable that is caused when a sprite plane is updated to no longer | |
5030 | * completely hide the primary plane. | |
5031 | */ | |
5032 | static void | |
5033 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
5034 | { |
5035 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5036 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
5037 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5038 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 5039 | |
87d4300a ML |
5040 | /* |
5041 | * FIXME IPS should be fine as long as one plane is | |
5042 | * enabled, but in practice it seems to have problems | |
5043 | * when going from primary only to sprite only and vice | |
5044 | * versa. | |
5045 | */ | |
a5c4d7bc VS |
5046 | hsw_enable_ips(intel_crtc); |
5047 | ||
f99d7069 | 5048 | /* |
87d4300a ML |
5049 | * Gen2 reports pipe underruns whenever all planes are disabled. |
5050 | * So don't enable underrun reporting before at least some planes | |
5051 | * are enabled. | |
5052 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5053 | * but leave the pipe running. | |
f99d7069 | 5054 | */ |
5db94019 | 5055 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
5056 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5057 | ||
aca7b684 VS |
5058 | /* Underruns don't always raise interrupts, so check manually. */ |
5059 | intel_check_cpu_fifo_underruns(dev_priv); | |
5060 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
5061 | } |
5062 | ||
2622a081 | 5063 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
5064 | static void |
5065 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
5066 | { |
5067 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5068 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
5069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5070 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 5071 | |
87d4300a ML |
5072 | /* |
5073 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5074 | * So diasble underrun reporting before all the planes get disabled. | |
5075 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5076 | * but leave the pipe running. | |
5077 | */ | |
5db94019 | 5078 | if (IS_GEN2(dev_priv)) |
87d4300a | 5079 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 5080 | |
2622a081 VS |
5081 | /* |
5082 | * FIXME IPS should be fine as long as one plane is | |
5083 | * enabled, but in practice it seems to have problems | |
5084 | * when going from primary only to sprite only and vice | |
5085 | * versa. | |
5086 | */ | |
5087 | hsw_disable_ips(intel_crtc); | |
5088 | } | |
5089 | ||
5090 | /* FIXME get rid of this and use pre_plane_update */ | |
5091 | static void | |
5092 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
5093 | { | |
5094 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5095 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
5096 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5097 | int pipe = intel_crtc->pipe; | |
5098 | ||
5099 | intel_pre_disable_primary(crtc); | |
5100 | ||
87d4300a ML |
5101 | /* |
5102 | * Vblank time updates from the shadow to live plane control register | |
5103 | * are blocked if the memory self-refresh mode is active at that | |
5104 | * moment. So to make sure the plane gets truly disabled, disable | |
5105 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5106 | * will be checked/applied by the HW only at the next frame start | |
5107 | * event which is after the vblank start event, so we need to have a | |
5108 | * wait-for-vblank between disabling the plane and the pipe. | |
5109 | */ | |
11a85d6a VS |
5110 | if (HAS_GMCH_DISPLAY(dev_priv) && |
5111 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 5112 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
5113 | } |
5114 | ||
5a21b665 DV |
5115 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
5116 | { | |
5117 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
5118 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
5119 | struct intel_crtc_state *pipe_config = | |
f9a8c149 VS |
5120 | intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state), |
5121 | crtc); | |
5a21b665 DV |
5122 | struct drm_plane *primary = crtc->base.primary; |
5123 | struct drm_plane_state *old_pri_state = | |
5124 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5125 | ||
5748b6a1 | 5126 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 | 5127 | |
5a21b665 | 5128 | if (pipe_config->update_wm_post && pipe_config->base.active) |
432081bc | 5129 | intel_update_watermarks(crtc); |
5a21b665 DV |
5130 | |
5131 | if (old_pri_state) { | |
5132 | struct intel_plane_state *primary_state = | |
f9a8c149 VS |
5133 | intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state), |
5134 | to_intel_plane(primary)); | |
5a21b665 DV |
5135 | struct intel_plane_state *old_primary_state = |
5136 | to_intel_plane_state(old_pri_state); | |
5137 | ||
5138 | intel_fbc_post_update(crtc); | |
5139 | ||
936e71e3 | 5140 | if (primary_state->base.visible && |
5a21b665 | 5141 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5142 | !old_primary_state->base.visible)) |
5a21b665 DV |
5143 | intel_post_enable_primary(&crtc->base); |
5144 | } | |
5145 | } | |
5146 | ||
aa5e9b47 ML |
5147 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, |
5148 | struct intel_crtc_state *pipe_config) | |
ac21b225 | 5149 | { |
5c74cd73 | 5150 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5151 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5152 | struct drm_i915_private *dev_priv = to_i915(dev); |
5c74cd73 ML |
5153 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5154 | struct drm_plane *primary = crtc->base.primary; | |
5155 | struct drm_plane_state *old_pri_state = | |
5156 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5157 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5158 | struct intel_atomic_state *old_intel_state = |
5159 | to_intel_atomic_state(old_state); | |
ac21b225 | 5160 | |
5c74cd73 ML |
5161 | if (old_pri_state) { |
5162 | struct intel_plane_state *primary_state = | |
f9a8c149 VS |
5163 | intel_atomic_get_new_plane_state(old_intel_state, |
5164 | to_intel_plane(primary)); | |
5c74cd73 ML |
5165 | struct intel_plane_state *old_primary_state = |
5166 | to_intel_plane_state(old_pri_state); | |
5167 | ||
faf68d92 | 5168 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5169 | |
936e71e3 VS |
5170 | if (old_primary_state->base.visible && |
5171 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5172 | intel_pre_disable_primary(&crtc->base); |
5173 | } | |
852eb00d | 5174 | |
5eeb798b VS |
5175 | /* |
5176 | * Vblank time updates from the shadow to live plane control register | |
5177 | * are blocked if the memory self-refresh mode is active at that | |
5178 | * moment. So to make sure the plane gets truly disabled, disable | |
5179 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5180 | * will be checked/applied by the HW only at the next frame start | |
5181 | * event which is after the vblank start event, so we need to have a | |
5182 | * wait-for-vblank between disabling the plane and the pipe. | |
5183 | */ | |
5184 | if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active && | |
5185 | pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) | |
5186 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
92826fcd | 5187 | |
ed4a6a7c MR |
5188 | /* |
5189 | * IVB workaround: must disable low power watermarks for at least | |
5190 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5191 | * when scaling is disabled. | |
5192 | * | |
5193 | * WaCxSRDisabledForSpriteScaling:ivb | |
5194 | */ | |
ddd2b792 | 5195 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5196 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5197 | |
5198 | /* | |
5199 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5200 | * watermark programming here. | |
5201 | */ | |
5202 | if (needs_modeset(&pipe_config->base)) | |
5203 | return; | |
5204 | ||
5205 | /* | |
5206 | * For platforms that support atomic watermarks, program the | |
5207 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5208 | * will be the intermediate values that are safe for both pre- and | |
5209 | * post- vblank; when vblank happens, the 'active' values will be set | |
5210 | * to the final 'target' values and we'll do this again to get the | |
5211 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5212 | * will be the final target values which will get automatically latched | |
5213 | * at vblank time; no further programming will be necessary. | |
5214 | * | |
5215 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5216 | * we'll continue to update watermarks the old way, if flags tell | |
5217 | * us to. | |
5218 | */ | |
5219 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5220 | dev_priv->display.initial_watermarks(old_intel_state, |
5221 | pipe_config); | |
caed361d | 5222 | else if (pipe_config->update_wm_pre) |
432081bc | 5223 | intel_update_watermarks(crtc); |
ac21b225 ML |
5224 | } |
5225 | ||
d032ffa0 | 5226 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5227 | { |
5228 | struct drm_device *dev = crtc->dev; | |
5229 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5230 | struct drm_plane *p; |
87d4300a ML |
5231 | int pipe = intel_crtc->pipe; |
5232 | ||
7cac945f | 5233 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5234 | |
d032ffa0 | 5235 | drm_for_each_plane_mask(p, dev, plane_mask) |
282dbf9b | 5236 | to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc); |
f98551ae | 5237 | |
f99d7069 DV |
5238 | /* |
5239 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5240 | * to compute the mask of flip planes precisely. For the time being | |
5241 | * consider this a flip to a NULL plane. | |
5242 | */ | |
5748b6a1 | 5243 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5244 | } |
5245 | ||
fb1c98b1 | 5246 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5247 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5248 | struct drm_atomic_state *old_state) |
5249 | { | |
aa5e9b47 | 5250 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5251 | struct drm_connector *conn; |
5252 | int i; | |
5253 | ||
aa5e9b47 | 5254 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5255 | struct intel_encoder *encoder = |
5256 | to_intel_encoder(conn_state->best_encoder); | |
5257 | ||
5258 | if (conn_state->crtc != crtc) | |
5259 | continue; | |
5260 | ||
5261 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5262 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5263 | } |
5264 | } | |
5265 | ||
5266 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5267 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5268 | struct drm_atomic_state *old_state) |
5269 | { | |
aa5e9b47 | 5270 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5271 | struct drm_connector *conn; |
5272 | int i; | |
5273 | ||
aa5e9b47 | 5274 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5275 | struct intel_encoder *encoder = |
5276 | to_intel_encoder(conn_state->best_encoder); | |
5277 | ||
5278 | if (conn_state->crtc != crtc) | |
5279 | continue; | |
5280 | ||
5281 | if (encoder->pre_enable) | |
fd6bbda9 | 5282 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5283 | } |
5284 | } | |
5285 | ||
5286 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5287 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5288 | struct drm_atomic_state *old_state) |
5289 | { | |
aa5e9b47 | 5290 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5291 | struct drm_connector *conn; |
5292 | int i; | |
5293 | ||
aa5e9b47 | 5294 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5295 | struct intel_encoder *encoder = |
5296 | to_intel_encoder(conn_state->best_encoder); | |
5297 | ||
5298 | if (conn_state->crtc != crtc) | |
5299 | continue; | |
5300 | ||
fd6bbda9 | 5301 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5302 | intel_opregion_notify_encoder(encoder, true); |
5303 | } | |
5304 | } | |
5305 | ||
5306 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5307 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5308 | struct drm_atomic_state *old_state) |
5309 | { | |
5310 | struct drm_connector_state *old_conn_state; | |
5311 | struct drm_connector *conn; | |
5312 | int i; | |
5313 | ||
aa5e9b47 | 5314 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5315 | struct intel_encoder *encoder = |
5316 | to_intel_encoder(old_conn_state->best_encoder); | |
5317 | ||
5318 | if (old_conn_state->crtc != crtc) | |
5319 | continue; | |
5320 | ||
5321 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5322 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5323 | } |
5324 | } | |
5325 | ||
5326 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5327 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5328 | struct drm_atomic_state *old_state) |
5329 | { | |
5330 | struct drm_connector_state *old_conn_state; | |
5331 | struct drm_connector *conn; | |
5332 | int i; | |
5333 | ||
aa5e9b47 | 5334 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5335 | struct intel_encoder *encoder = |
5336 | to_intel_encoder(old_conn_state->best_encoder); | |
5337 | ||
5338 | if (old_conn_state->crtc != crtc) | |
5339 | continue; | |
5340 | ||
5341 | if (encoder->post_disable) | |
fd6bbda9 | 5342 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5343 | } |
5344 | } | |
5345 | ||
5346 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5347 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5348 | struct drm_atomic_state *old_state) |
5349 | { | |
5350 | struct drm_connector_state *old_conn_state; | |
5351 | struct drm_connector *conn; | |
5352 | int i; | |
5353 | ||
aa5e9b47 | 5354 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5355 | struct intel_encoder *encoder = |
5356 | to_intel_encoder(old_conn_state->best_encoder); | |
5357 | ||
5358 | if (old_conn_state->crtc != crtc) | |
5359 | continue; | |
5360 | ||
5361 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5362 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5363 | } |
5364 | } | |
5365 | ||
4a806558 ML |
5366 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5367 | struct drm_atomic_state *old_state) | |
f67a559d | 5368 | { |
4a806558 | 5369 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5370 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5371 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5372 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5373 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5374 | struct intel_atomic_state *old_intel_state = |
5375 | to_intel_atomic_state(old_state); | |
f67a559d | 5376 | |
53d9f4e9 | 5377 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5378 | return; |
5379 | ||
b2c0593a VS |
5380 | /* |
5381 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5382 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5383 | * | |
5384 | * On ILK we get an occasional spurious CPU pipe underruns | |
5385 | * between eDP port A enable and vdd enable. Also PCH port | |
5386 | * enable seems to result in the occasional CPU pipe underrun. | |
5387 | * | |
5388 | * Spurious PCH underruns also occur during PCH enabling. | |
5389 | */ | |
5390 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5391 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5392 | if (intel_crtc->config->has_pch_encoder) |
5393 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5394 | ||
6e3c9717 | 5395 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5396 | intel_prepare_shared_dpll(intel_crtc); |
5397 | ||
37a5650b | 5398 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5399 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5400 | |
5401 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5402 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5403 | |
6e3c9717 | 5404 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5405 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5406 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5407 | } |
5408 | ||
5409 | ironlake_set_pipeconf(crtc); | |
5410 | ||
f67a559d | 5411 | intel_crtc->active = true; |
8664281b | 5412 | |
fd6bbda9 | 5413 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5414 | |
6e3c9717 | 5415 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5416 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5417 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5418 | * enabling. */ | |
88cefb6c | 5419 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5420 | } else { |
5421 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5422 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5423 | } | |
f67a559d | 5424 | |
b074cec8 | 5425 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5426 | |
9c54c0dd JB |
5427 | /* |
5428 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5429 | * clocks enabled | |
5430 | */ | |
b95c5321 | 5431 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5432 | |
1d5bf5d9 | 5433 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5434 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5435 | intel_enable_pipe(intel_crtc); |
f67a559d | 5436 | |
6e3c9717 | 5437 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5438 | ironlake_pch_enable(pipe_config); |
c98e9dcf | 5439 | |
f9b61ff6 DV |
5440 | assert_vblank_disabled(crtc); |
5441 | drm_crtc_vblank_on(crtc); | |
5442 | ||
fd6bbda9 | 5443 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5444 | |
6e266956 | 5445 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5446 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5447 | |
5448 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5449 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5450 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5451 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5452 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5453 | } |
5454 | ||
42db64ef PZ |
5455 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5456 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5457 | { | |
50a0bc90 | 5458 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5459 | } |
5460 | ||
ed69cd40 ID |
5461 | static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, |
5462 | enum pipe pipe, bool apply) | |
5463 | { | |
5464 | u32 val = I915_READ(CLKGATE_DIS_PSL(pipe)); | |
5465 | u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; | |
5466 | ||
5467 | if (apply) | |
5468 | val |= mask; | |
5469 | else | |
5470 | val &= ~mask; | |
5471 | ||
5472 | I915_WRITE(CLKGATE_DIS_PSL(pipe), val); | |
5473 | } | |
5474 | ||
4a806558 ML |
5475 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5476 | struct drm_atomic_state *old_state) | |
4f771f10 | 5477 | { |
4a806558 | 5478 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5479 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5480 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5481 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5482 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5483 | struct intel_atomic_state *old_intel_state = |
5484 | to_intel_atomic_state(old_state); | |
ed69cd40 | 5485 | bool psl_clkgate_wa; |
4f771f10 | 5486 | |
53d9f4e9 | 5487 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5488 | return; |
5489 | ||
fd6bbda9 | 5490 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5491 | |
8106ddbd | 5492 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5493 | intel_enable_shared_dpll(intel_crtc); |
5494 | ||
37a5650b | 5495 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5496 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5497 | |
d7edc4e5 | 5498 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5499 | intel_set_pipe_timings(intel_crtc); |
5500 | ||
bc58be60 | 5501 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5502 | |
4d1de975 JN |
5503 | if (cpu_transcoder != TRANSCODER_EDP && |
5504 | !transcoder_is_dsi(cpu_transcoder)) { | |
5505 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5506 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5507 | } |
5508 | ||
6e3c9717 | 5509 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5510 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5511 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5512 | } |
5513 | ||
d7edc4e5 | 5514 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5515 | haswell_set_pipeconf(crtc); |
5516 | ||
391bf048 | 5517 | haswell_set_pipemisc(crtc); |
229fca97 | 5518 | |
b95c5321 | 5519 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5520 | |
4f771f10 | 5521 | intel_crtc->active = true; |
8664281b | 5522 | |
fd6bbda9 | 5523 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5524 | |
d7edc4e5 | 5525 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5526 | intel_ddi_enable_pipe_clock(pipe_config); |
4f771f10 | 5527 | |
ed69cd40 ID |
5528 | /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */ |
5529 | psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && | |
5530 | intel_crtc->config->pch_pfit.enabled; | |
5531 | if (psl_clkgate_wa) | |
5532 | glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); | |
5533 | ||
6315b5d3 | 5534 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5535 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5536 | else |
1c132b44 | 5537 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5538 | |
5539 | /* | |
5540 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5541 | * clocks enabled | |
5542 | */ | |
b95c5321 | 5543 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5544 | |
3dc38eea | 5545 | intel_ddi_set_pipe_settings(pipe_config); |
d7edc4e5 | 5546 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5547 | intel_ddi_enable_transcoder_func(pipe_config); |
4f771f10 | 5548 | |
1d5bf5d9 | 5549 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5550 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5551 | |
5552 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5553 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5554 | intel_enable_pipe(intel_crtc); |
42db64ef | 5555 | |
6e3c9717 | 5556 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5557 | lpt_pch_enable(pipe_config); |
4f771f10 | 5558 | |
0037071d | 5559 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5560 | intel_ddi_set_vc_payload_alloc(pipe_config, true); |
0e32b39c | 5561 | |
f9b61ff6 DV |
5562 | assert_vblank_disabled(crtc); |
5563 | drm_crtc_vblank_on(crtc); | |
5564 | ||
fd6bbda9 | 5565 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5566 | |
ed69cd40 ID |
5567 | if (psl_clkgate_wa) { |
5568 | intel_wait_for_vblank(dev_priv, pipe); | |
5569 | glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); | |
5570 | } | |
5571 | ||
e4916946 PZ |
5572 | /* If we change the relative order between pipe/planes enabling, we need |
5573 | * to change the workaround. */ | |
99d736a2 | 5574 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5575 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5576 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5577 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5578 | } |
4f771f10 PZ |
5579 | } |
5580 | ||
bfd16b2a | 5581 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5582 | { |
5583 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5584 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5585 | int pipe = crtc->pipe; |
5586 | ||
5587 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5588 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5589 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5590 | I915_WRITE(PF_CTL(pipe), 0); |
5591 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5592 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5593 | } | |
5594 | } | |
5595 | ||
4a806558 ML |
5596 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5597 | struct drm_atomic_state *old_state) | |
6be4a607 | 5598 | { |
4a806558 | 5599 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5600 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5601 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5602 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5603 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5604 | |
b2c0593a VS |
5605 | /* |
5606 | * Sometimes spurious CPU pipe underruns happen when the | |
5607 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5608 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5609 | */ | |
5610 | if (intel_crtc->config->has_pch_encoder) { | |
5611 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5612 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5613 | } |
37ca8d4c | 5614 | |
fd6bbda9 | 5615 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5616 | |
f9b61ff6 DV |
5617 | drm_crtc_vblank_off(crtc); |
5618 | assert_vblank_disabled(crtc); | |
5619 | ||
575f7ab7 | 5620 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5621 | |
bfd16b2a | 5622 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5623 | |
b2c0593a | 5624 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5625 | ironlake_fdi_disable(crtc); |
5626 | ||
fd6bbda9 | 5627 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5628 | |
6e3c9717 | 5629 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5630 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5631 | |
6e266956 | 5632 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5633 | i915_reg_t reg; |
5634 | u32 temp; | |
5635 | ||
d925c59a DV |
5636 | /* disable TRANS_DP_CTL */ |
5637 | reg = TRANS_DP_CTL(pipe); | |
5638 | temp = I915_READ(reg); | |
5639 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5640 | TRANS_DP_PORT_SEL_MASK); | |
5641 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5642 | I915_WRITE(reg, temp); | |
5643 | ||
5644 | /* disable DPLL_SEL */ | |
5645 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5646 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5647 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5648 | } |
e3421a18 | 5649 | |
d925c59a DV |
5650 | ironlake_fdi_pll_disable(intel_crtc); |
5651 | } | |
81b088ca | 5652 | |
b2c0593a | 5653 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5654 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5655 | } |
1b3c7a47 | 5656 | |
4a806558 ML |
5657 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5658 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5659 | { |
4a806558 | 5660 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5661 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5662 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5663 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5664 | |
fd6bbda9 | 5665 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5666 | |
f9b61ff6 DV |
5667 | drm_crtc_vblank_off(crtc); |
5668 | assert_vblank_disabled(crtc); | |
5669 | ||
4d1de975 | 5670 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5671 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5672 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5673 | |
0037071d | 5674 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5675 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); |
a4bf214f | 5676 | |
d7edc4e5 | 5677 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5678 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5679 | |
6315b5d3 | 5680 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5681 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5682 | else |
bfd16b2a | 5683 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5684 | |
d7edc4e5 | 5685 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5686 | intel_ddi_disable_pipe_clock(intel_crtc->config); |
4f771f10 | 5687 | |
fd6bbda9 | 5688 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
4f771f10 PZ |
5689 | } |
5690 | ||
2dd24552 JB |
5691 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5692 | { | |
5693 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5694 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5695 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5696 | |
681a8504 | 5697 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5698 | return; |
5699 | ||
2dd24552 | 5700 | /* |
c0b03411 DV |
5701 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5702 | * according to register description and PRM. | |
2dd24552 | 5703 | */ |
c0b03411 DV |
5704 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5705 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5706 | |
b074cec8 JB |
5707 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5708 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5709 | |
5710 | /* Border color in case we don't scale up to the full screen. Black by | |
5711 | * default, change to something else for debugging. */ | |
5712 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5713 | } |
5714 | ||
79f255a0 | 5715 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
5716 | { |
5717 | switch (port) { | |
5718 | case PORT_A: | |
6331a704 | 5719 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5720 | case PORT_B: |
6331a704 | 5721 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5722 | case PORT_C: |
6331a704 | 5723 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5724 | case PORT_D: |
6331a704 | 5725 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5726 | case PORT_E: |
6331a704 | 5727 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5728 | default: |
b9fec167 | 5729 | MISSING_CASE(port); |
d05410f9 DA |
5730 | return POWER_DOMAIN_PORT_OTHER; |
5731 | } | |
5732 | } | |
5733 | ||
d8fc70b7 ACO |
5734 | static u64 get_crtc_power_domains(struct drm_crtc *crtc, |
5735 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5736 | { |
319be8ae | 5737 | struct drm_device *dev = crtc->dev; |
37255d8d | 5738 | struct drm_i915_private *dev_priv = to_i915(dev); |
74bff5f9 | 5739 | struct drm_encoder *encoder; |
319be8ae ID |
5740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5741 | enum pipe pipe = intel_crtc->pipe; | |
d8fc70b7 | 5742 | u64 mask; |
74bff5f9 | 5743 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5744 | |
74bff5f9 | 5745 | if (!crtc_state->base.active) |
292b990e ML |
5746 | return 0; |
5747 | ||
77d22dca ID |
5748 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5749 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5750 | if (crtc_state->pch_pfit.enabled || |
5751 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 5752 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 5753 | |
74bff5f9 ML |
5754 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5755 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5756 | ||
79f255a0 | 5757 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 5758 | } |
319be8ae | 5759 | |
37255d8d ML |
5760 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
5761 | mask |= BIT(POWER_DOMAIN_AUDIO); | |
5762 | ||
15e7ec29 | 5763 | if (crtc_state->shared_dpll) |
d8fc70b7 | 5764 | mask |= BIT_ULL(POWER_DOMAIN_PLLS); |
15e7ec29 | 5765 | |
77d22dca ID |
5766 | return mask; |
5767 | } | |
5768 | ||
d2d15016 | 5769 | static u64 |
74bff5f9 ML |
5770 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
5771 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5772 | { |
fac5e23e | 5773 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5775 | enum intel_display_power_domain domain; | |
d8fc70b7 | 5776 | u64 domains, new_domains, old_domains; |
77d22dca | 5777 | |
292b990e | 5778 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5779 | intel_crtc->enabled_power_domains = new_domains = |
5780 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5781 | |
5a21b665 | 5782 | domains = new_domains & ~old_domains; |
292b990e ML |
5783 | |
5784 | for_each_power_domain(domain, domains) | |
5785 | intel_display_power_get(dev_priv, domain); | |
5786 | ||
5a21b665 | 5787 | return old_domains & ~new_domains; |
292b990e ML |
5788 | } |
5789 | ||
5790 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 5791 | u64 domains) |
292b990e ML |
5792 | { |
5793 | enum intel_display_power_domain domain; | |
5794 | ||
5795 | for_each_power_domain(domain, domains) | |
5796 | intel_display_power_put(dev_priv, domain); | |
5797 | } | |
77d22dca | 5798 | |
7ff89ca2 VS |
5799 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
5800 | struct drm_atomic_state *old_state) | |
adafdc6f | 5801 | { |
ff32c54e VS |
5802 | struct intel_atomic_state *old_intel_state = |
5803 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5804 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5805 | struct drm_device *dev = crtc->dev; | |
5806 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5807 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5808 | int pipe = intel_crtc->pipe; | |
adafdc6f | 5809 | |
7ff89ca2 VS |
5810 | if (WARN_ON(intel_crtc->active)) |
5811 | return; | |
adafdc6f | 5812 | |
7ff89ca2 VS |
5813 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5814 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
b2045352 | 5815 | |
7ff89ca2 VS |
5816 | intel_set_pipe_timings(intel_crtc); |
5817 | intel_set_pipe_src_size(intel_crtc); | |
b2045352 | 5818 | |
7ff89ca2 VS |
5819 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
5820 | struct drm_i915_private *dev_priv = to_i915(dev); | |
560a7ae4 | 5821 | |
7ff89ca2 VS |
5822 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
5823 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
5824 | } |
5825 | ||
7ff89ca2 | 5826 | i9xx_set_pipeconf(intel_crtc); |
560a7ae4 | 5827 | |
7ff89ca2 | 5828 | intel_crtc->active = true; |
92891e45 | 5829 | |
7ff89ca2 | 5830 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 5831 | |
7ff89ca2 | 5832 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
5f199dfa | 5833 | |
7ff89ca2 VS |
5834 | if (IS_CHERRYVIEW(dev_priv)) { |
5835 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
5836 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
5837 | } else { | |
5838 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
5839 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
5f199dfa VS |
5840 | } |
5841 | ||
7ff89ca2 | 5842 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
5f199dfa | 5843 | |
7ff89ca2 | 5844 | i9xx_pfit_enable(intel_crtc); |
89b3c3c7 | 5845 | |
7ff89ca2 | 5846 | intel_color_load_luts(&pipe_config->base); |
89b3c3c7 | 5847 | |
ff32c54e VS |
5848 | dev_priv->display.initial_watermarks(old_intel_state, |
5849 | pipe_config); | |
7ff89ca2 VS |
5850 | intel_enable_pipe(intel_crtc); |
5851 | ||
5852 | assert_vblank_disabled(crtc); | |
5853 | drm_crtc_vblank_on(crtc); | |
89b3c3c7 | 5854 | |
7ff89ca2 | 5855 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b3c3c7 ACO |
5856 | } |
5857 | ||
7ff89ca2 | 5858 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
2b73001e | 5859 | { |
7ff89ca2 VS |
5860 | struct drm_device *dev = crtc->base.dev; |
5861 | struct drm_i915_private *dev_priv = to_i915(dev); | |
83d7c81f | 5862 | |
7ff89ca2 VS |
5863 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5864 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
2b73001e VS |
5865 | } |
5866 | ||
7ff89ca2 VS |
5867 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
5868 | struct drm_atomic_state *old_state) | |
2b73001e | 5869 | { |
04548cba VS |
5870 | struct intel_atomic_state *old_intel_state = |
5871 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5872 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5873 | struct drm_device *dev = crtc->dev; | |
5874 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5875 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5876 | enum pipe pipe = intel_crtc->pipe; | |
2b73001e | 5877 | |
7ff89ca2 VS |
5878 | if (WARN_ON(intel_crtc->active)) |
5879 | return; | |
2b73001e | 5880 | |
7ff89ca2 | 5881 | i9xx_set_pll_dividers(intel_crtc); |
2b73001e | 5882 | |
7ff89ca2 VS |
5883 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5884 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
83d7c81f | 5885 | |
7ff89ca2 VS |
5886 | intel_set_pipe_timings(intel_crtc); |
5887 | intel_set_pipe_src_size(intel_crtc); | |
2b73001e | 5888 | |
7ff89ca2 | 5889 | i9xx_set_pipeconf(intel_crtc); |
f8437dd1 | 5890 | |
7ff89ca2 | 5891 | intel_crtc->active = true; |
5f199dfa | 5892 | |
7ff89ca2 VS |
5893 | if (!IS_GEN2(dev_priv)) |
5894 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5f199dfa | 5895 | |
7ff89ca2 | 5896 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f8437dd1 | 5897 | |
7ff89ca2 | 5898 | i9xx_enable_pll(intel_crtc); |
f8437dd1 | 5899 | |
7ff89ca2 | 5900 | i9xx_pfit_enable(intel_crtc); |
f8437dd1 | 5901 | |
7ff89ca2 | 5902 | intel_color_load_luts(&pipe_config->base); |
f8437dd1 | 5903 | |
04548cba VS |
5904 | if (dev_priv->display.initial_watermarks != NULL) |
5905 | dev_priv->display.initial_watermarks(old_intel_state, | |
5906 | intel_crtc->config); | |
5907 | else | |
5908 | intel_update_watermarks(intel_crtc); | |
7ff89ca2 | 5909 | intel_enable_pipe(intel_crtc); |
f8437dd1 | 5910 | |
7ff89ca2 VS |
5911 | assert_vblank_disabled(crtc); |
5912 | drm_crtc_vblank_on(crtc); | |
f8437dd1 | 5913 | |
7ff89ca2 VS |
5914 | intel_encoders_enable(crtc, pipe_config, old_state); |
5915 | } | |
f8437dd1 | 5916 | |
7ff89ca2 VS |
5917 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5918 | { | |
5919 | struct drm_device *dev = crtc->base.dev; | |
5920 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f8437dd1 | 5921 | |
7ff89ca2 | 5922 | if (!crtc->config->gmch_pfit.control) |
f8437dd1 | 5923 | return; |
f8437dd1 | 5924 | |
7ff89ca2 VS |
5925 | assert_pipe_disabled(dev_priv, crtc->pipe); |
5926 | ||
5927 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
5928 | I915_READ(PFIT_CONTROL)); | |
5929 | I915_WRITE(PFIT_CONTROL, 0); | |
f8437dd1 VK |
5930 | } |
5931 | ||
7ff89ca2 VS |
5932 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5933 | struct drm_atomic_state *old_state) | |
f8437dd1 | 5934 | { |
7ff89ca2 VS |
5935 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
5936 | struct drm_device *dev = crtc->dev; | |
5937 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5938 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5939 | int pipe = intel_crtc->pipe; | |
d66a2194 | 5940 | |
d66a2194 | 5941 | /* |
7ff89ca2 VS |
5942 | * On gen2 planes are double buffered but the pipe isn't, so we must |
5943 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 5944 | */ |
7ff89ca2 VS |
5945 | if (IS_GEN2(dev_priv)) |
5946 | intel_wait_for_vblank(dev_priv, pipe); | |
d66a2194 | 5947 | |
7ff89ca2 | 5948 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5949 | |
7ff89ca2 VS |
5950 | drm_crtc_vblank_off(crtc); |
5951 | assert_vblank_disabled(crtc); | |
d66a2194 | 5952 | |
7ff89ca2 | 5953 | intel_disable_pipe(intel_crtc); |
d66a2194 | 5954 | |
7ff89ca2 | 5955 | i9xx_pfit_disable(intel_crtc); |
89b3c3c7 | 5956 | |
7ff89ca2 | 5957 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5958 | |
7ff89ca2 VS |
5959 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
5960 | if (IS_CHERRYVIEW(dev_priv)) | |
5961 | chv_disable_pll(dev_priv, pipe); | |
5962 | else if (IS_VALLEYVIEW(dev_priv)) | |
5963 | vlv_disable_pll(dev_priv, pipe); | |
5964 | else | |
5965 | i9xx_disable_pll(intel_crtc); | |
5966 | } | |
c2e001ef | 5967 | |
7ff89ca2 | 5968 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
89b3c3c7 | 5969 | |
7ff89ca2 VS |
5970 | if (!IS_GEN2(dev_priv)) |
5971 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
ff32c54e VS |
5972 | |
5973 | if (!dev_priv->display.initial_watermarks) | |
5974 | intel_update_watermarks(intel_crtc); | |
2ee0da16 VS |
5975 | |
5976 | /* clock the pipe down to 640x480@60 to potentially save power */ | |
5977 | if (IS_I830(dev_priv)) | |
5978 | i830_enable_pipe(dev_priv, pipe); | |
f8437dd1 VK |
5979 | } |
5980 | ||
da1d0e26 VS |
5981 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, |
5982 | struct drm_modeset_acquire_ctx *ctx) | |
f8437dd1 | 5983 | { |
7ff89ca2 VS |
5984 | struct intel_encoder *encoder; |
5985 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5986 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
5987 | enum intel_display_power_domain domain; | |
d2d15016 | 5988 | u64 domains; |
7ff89ca2 VS |
5989 | struct drm_atomic_state *state; |
5990 | struct intel_crtc_state *crtc_state; | |
5991 | int ret; | |
f8437dd1 | 5992 | |
7ff89ca2 VS |
5993 | if (!intel_crtc->active) |
5994 | return; | |
a8ca4934 | 5995 | |
7ff89ca2 | 5996 | if (crtc->primary->state->visible) { |
7ff89ca2 | 5997 | intel_pre_disable_primary_noatomic(crtc); |
709e05c3 | 5998 | |
7ff89ca2 VS |
5999 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
6000 | crtc->primary->state->visible = false; | |
6001 | } | |
5d96d8af | 6002 | |
7ff89ca2 VS |
6003 | state = drm_atomic_state_alloc(crtc->dev); |
6004 | if (!state) { | |
6005 | DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", | |
6006 | crtc->base.id, crtc->name); | |
1c3f7700 | 6007 | return; |
7ff89ca2 | 6008 | } |
9f7eb31a | 6009 | |
da1d0e26 | 6010 | state->acquire_ctx = ctx; |
ea61791e | 6011 | |
7ff89ca2 VS |
6012 | /* Everything's already locked, -EDEADLK can't happen. */ |
6013 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
6014 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
9f7eb31a | 6015 | |
7ff89ca2 | 6016 | WARN_ON(IS_ERR(crtc_state) || ret); |
5d96d8af | 6017 | |
7ff89ca2 | 6018 | dev_priv->display.crtc_disable(crtc_state, state); |
4a806558 | 6019 | |
0853695c | 6020 | drm_atomic_state_put(state); |
842e0307 | 6021 | |
78108b7c VS |
6022 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6023 | crtc->base.id, crtc->name); | |
842e0307 ML |
6024 | |
6025 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6026 | crtc->state->active = false; | |
37d9078b | 6027 | intel_crtc->active = false; |
842e0307 ML |
6028 | crtc->enabled = false; |
6029 | crtc->state->connector_mask = 0; | |
6030 | crtc->state->encoder_mask = 0; | |
6031 | ||
6032 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6033 | encoder->base.crtc = NULL; | |
6034 | ||
58f9c0bc | 6035 | intel_fbc_disable(intel_crtc); |
432081bc | 6036 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 6037 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6038 | |
6039 | domains = intel_crtc->enabled_power_domains; | |
6040 | for_each_power_domain(domain, domains) | |
6041 | intel_display_power_put(dev_priv, domain); | |
6042 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6043 | |
6044 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
d305e061 | 6045 | dev_priv->min_cdclk[intel_crtc->pipe] = 0; |
b17d48e2 ML |
6046 | } |
6047 | ||
6b72d486 ML |
6048 | /* |
6049 | * turn all crtc's off, but do not adjust state | |
6050 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6051 | */ | |
70e0bd74 | 6052 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6053 | { |
e2c8b870 | 6054 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6055 | struct drm_atomic_state *state; |
e2c8b870 | 6056 | int ret; |
70e0bd74 | 6057 | |
e2c8b870 ML |
6058 | state = drm_atomic_helper_suspend(dev); |
6059 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6060 | if (ret) |
6061 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6062 | else |
6063 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6064 | return ret; |
ee7b9f93 JB |
6065 | } |
6066 | ||
ea5b213a | 6067 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6068 | { |
4ef69c7a | 6069 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6070 | |
ea5b213a CW |
6071 | drm_encoder_cleanup(encoder); |
6072 | kfree(intel_encoder); | |
7e7d76c3 JB |
6073 | } |
6074 | ||
0a91ca29 DV |
6075 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6076 | * internal consistency). */ | |
749d98b8 ML |
6077 | static void intel_connector_verify_state(struct drm_crtc_state *crtc_state, |
6078 | struct drm_connector_state *conn_state) | |
79e53945 | 6079 | { |
749d98b8 | 6080 | struct intel_connector *connector = to_intel_connector(conn_state->connector); |
35dd3c64 ML |
6081 | |
6082 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6083 | connector->base.base.id, | |
6084 | connector->base.name); | |
6085 | ||
0a91ca29 | 6086 | if (connector->get_hw_state(connector)) { |
e85376cb | 6087 | struct intel_encoder *encoder = connector->encoder; |
0a91ca29 | 6088 | |
749d98b8 | 6089 | I915_STATE_WARN(!crtc_state, |
35dd3c64 | 6090 | "connector enabled without attached crtc\n"); |
0a91ca29 | 6091 | |
749d98b8 | 6092 | if (!crtc_state) |
35dd3c64 ML |
6093 | return; |
6094 | ||
749d98b8 | 6095 | I915_STATE_WARN(!crtc_state->active, |
35dd3c64 ML |
6096 | "connector is active, but attached crtc isn't\n"); |
6097 | ||
e85376cb | 6098 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6099 | return; |
6100 | ||
e85376cb | 6101 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6102 | "atomic encoder doesn't match attached encoder\n"); |
6103 | ||
e85376cb | 6104 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6105 | "attached encoder crtc differs from connector crtc\n"); |
6106 | } else { | |
749d98b8 | 6107 | I915_STATE_WARN(crtc_state && crtc_state->active, |
4d688a2a | 6108 | "attached crtc is active, but connector isn't\n"); |
749d98b8 | 6109 | I915_STATE_WARN(!crtc_state && conn_state->best_encoder, |
35dd3c64 | 6110 | "best encoder set without crtc!\n"); |
0a91ca29 | 6111 | } |
79e53945 JB |
6112 | } |
6113 | ||
08d9bc92 ACO |
6114 | int intel_connector_init(struct intel_connector *connector) |
6115 | { | |
11c1a9ec | 6116 | struct intel_digital_connector_state *conn_state; |
08d9bc92 | 6117 | |
11c1a9ec ML |
6118 | /* |
6119 | * Allocate enough memory to hold intel_digital_connector_state, | |
6120 | * This might be a few bytes too many, but for connectors that don't | |
6121 | * need it we'll free the state and allocate a smaller one on the first | |
6122 | * succesful commit anyway. | |
6123 | */ | |
6124 | conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); | |
6125 | if (!conn_state) | |
08d9bc92 ACO |
6126 | return -ENOMEM; |
6127 | ||
11c1a9ec ML |
6128 | __drm_atomic_helper_connector_reset(&connector->base, |
6129 | &conn_state->base); | |
6130 | ||
08d9bc92 ACO |
6131 | return 0; |
6132 | } | |
6133 | ||
6134 | struct intel_connector *intel_connector_alloc(void) | |
6135 | { | |
6136 | struct intel_connector *connector; | |
6137 | ||
6138 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6139 | if (!connector) | |
6140 | return NULL; | |
6141 | ||
6142 | if (intel_connector_init(connector) < 0) { | |
6143 | kfree(connector); | |
6144 | return NULL; | |
6145 | } | |
6146 | ||
6147 | return connector; | |
6148 | } | |
6149 | ||
f0947c37 DV |
6150 | /* Simple connector->get_hw_state implementation for encoders that support only |
6151 | * one connector and no cloning and hence the encoder state determines the state | |
6152 | * of the connector. */ | |
6153 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6154 | { |
24929352 | 6155 | enum pipe pipe = 0; |
f0947c37 | 6156 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6157 | |
f0947c37 | 6158 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6159 | } |
6160 | ||
6d293983 | 6161 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6162 | { |
6d293983 ACO |
6163 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6164 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6165 | |
6166 | return 0; | |
6167 | } | |
6168 | ||
6d293983 | 6169 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6170 | struct intel_crtc_state *pipe_config) |
1857e1da | 6171 | { |
8652744b | 6172 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
6173 | struct drm_atomic_state *state = pipe_config->base.state; |
6174 | struct intel_crtc *other_crtc; | |
6175 | struct intel_crtc_state *other_crtc_state; | |
6176 | ||
1857e1da DV |
6177 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6178 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6179 | if (pipe_config->fdi_lanes > 4) { | |
6180 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6181 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6182 | return -EINVAL; |
1857e1da DV |
6183 | } |
6184 | ||
8652744b | 6185 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
6186 | if (pipe_config->fdi_lanes > 2) { |
6187 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6188 | pipe_config->fdi_lanes); | |
6d293983 | 6189 | return -EINVAL; |
1857e1da | 6190 | } else { |
6d293983 | 6191 | return 0; |
1857e1da DV |
6192 | } |
6193 | } | |
6194 | ||
b7f05d4a | 6195 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 6196 | return 0; |
1857e1da DV |
6197 | |
6198 | /* Ivybridge 3 pipe is really complicated */ | |
6199 | switch (pipe) { | |
6200 | case PIPE_A: | |
6d293983 | 6201 | return 0; |
1857e1da | 6202 | case PIPE_B: |
6d293983 ACO |
6203 | if (pipe_config->fdi_lanes <= 2) |
6204 | return 0; | |
6205 | ||
b91eb5cc | 6206 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
6207 | other_crtc_state = |
6208 | intel_atomic_get_crtc_state(state, other_crtc); | |
6209 | if (IS_ERR(other_crtc_state)) | |
6210 | return PTR_ERR(other_crtc_state); | |
6211 | ||
6212 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6213 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6214 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6215 | return -EINVAL; |
1857e1da | 6216 | } |
6d293983 | 6217 | return 0; |
1857e1da | 6218 | case PIPE_C: |
251cc67c VS |
6219 | if (pipe_config->fdi_lanes > 2) { |
6220 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6221 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6222 | return -EINVAL; |
251cc67c | 6223 | } |
6d293983 | 6224 | |
b91eb5cc | 6225 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
6226 | other_crtc_state = |
6227 | intel_atomic_get_crtc_state(state, other_crtc); | |
6228 | if (IS_ERR(other_crtc_state)) | |
6229 | return PTR_ERR(other_crtc_state); | |
6230 | ||
6231 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6232 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6233 | return -EINVAL; |
1857e1da | 6234 | } |
6d293983 | 6235 | return 0; |
1857e1da DV |
6236 | default: |
6237 | BUG(); | |
6238 | } | |
6239 | } | |
6240 | ||
e29c22c0 DV |
6241 | #define RETRY 1 |
6242 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6243 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6244 | { |
1857e1da | 6245 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6246 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6247 | int lane, link_bw, fdi_dotclock, ret; |
6248 | bool needs_recompute = false; | |
877d48d5 | 6249 | |
e29c22c0 | 6250 | retry: |
877d48d5 DV |
6251 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6252 | * each output octet as 10 bits. The actual frequency | |
6253 | * is stored as a divider into a 100MHz clock, and the | |
6254 | * mode pixel clock is stored in units of 1KHz. | |
6255 | * Hence the bw of each lane in terms of the mode signal | |
6256 | * is: | |
6257 | */ | |
21a727b3 | 6258 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6259 | |
241bfc38 | 6260 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6261 | |
2bd89a07 | 6262 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6263 | pipe_config->pipe_bpp); |
6264 | ||
6265 | pipe_config->fdi_lanes = lane; | |
6266 | ||
2bd89a07 | 6267 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
b31e85ed | 6268 | link_bw, &pipe_config->fdi_m_n, false); |
1857e1da | 6269 | |
e3b247da | 6270 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6271 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 6272 | pipe_config->pipe_bpp -= 2*3; |
7ff89ca2 VS |
6273 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
6274 | pipe_config->pipe_bpp); | |
6275 | needs_recompute = true; | |
6276 | pipe_config->bw_constrained = true; | |
257a7ffc | 6277 | |
7ff89ca2 | 6278 | goto retry; |
257a7ffc | 6279 | } |
79e53945 | 6280 | |
7ff89ca2 VS |
6281 | if (needs_recompute) |
6282 | return RETRY; | |
e70236a8 | 6283 | |
7ff89ca2 | 6284 | return ret; |
e70236a8 JB |
6285 | } |
6286 | ||
7ff89ca2 VS |
6287 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6288 | struct intel_crtc_state *pipe_config) | |
e70236a8 | 6289 | { |
6e644626 VS |
6290 | if (pipe_config->ips_force_disable) |
6291 | return false; | |
6292 | ||
7ff89ca2 VS |
6293 | if (pipe_config->pipe_bpp > 24) |
6294 | return false; | |
e70236a8 | 6295 | |
7ff89ca2 VS |
6296 | /* HSW can handle pixel rate up to cdclk? */ |
6297 | if (IS_HASWELL(dev_priv)) | |
6298 | return true; | |
1b1d2716 | 6299 | |
65cd2b3f | 6300 | /* |
7ff89ca2 VS |
6301 | * We compare against max which means we must take |
6302 | * the increased cdclk requirement into account when | |
6303 | * calculating the new cdclk. | |
6304 | * | |
6305 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 6306 | */ |
7ff89ca2 VS |
6307 | return pipe_config->pixel_rate <= |
6308 | dev_priv->max_cdclk_freq * 95 / 100; | |
e70236a8 | 6309 | } |
79e53945 | 6310 | |
7ff89ca2 VS |
6311 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
6312 | struct intel_crtc_state *pipe_config) | |
6313 | { | |
6314 | struct drm_device *dev = crtc->base.dev; | |
6315 | struct drm_i915_private *dev_priv = to_i915(dev); | |
34edce2f | 6316 | |
4f044a88 | 6317 | pipe_config->ips_enabled = i915_modparams.enable_ips && |
7ff89ca2 VS |
6318 | hsw_crtc_supports_ips(crtc) && |
6319 | pipe_config_supports_ips(dev_priv, pipe_config); | |
34edce2f VS |
6320 | } |
6321 | ||
7ff89ca2 | 6322 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 6323 | { |
7ff89ca2 | 6324 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 6325 | |
7ff89ca2 VS |
6326 | /* GDG double wide on either pipe, otherwise pipe A only */ |
6327 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6328 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
34edce2f VS |
6329 | } |
6330 | ||
ceb99320 VS |
6331 | static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
6332 | { | |
6333 | uint32_t pixel_rate; | |
6334 | ||
6335 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; | |
6336 | ||
6337 | /* | |
6338 | * We only use IF-ID interlacing. If we ever use | |
6339 | * PF-ID we'll need to adjust the pixel_rate here. | |
6340 | */ | |
6341 | ||
6342 | if (pipe_config->pch_pfit.enabled) { | |
6343 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
6344 | uint32_t pfit_size = pipe_config->pch_pfit.size; | |
6345 | ||
6346 | pipe_w = pipe_config->pipe_src_w; | |
6347 | pipe_h = pipe_config->pipe_src_h; | |
6348 | ||
6349 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
6350 | pfit_h = pfit_size & 0xFFFF; | |
6351 | if (pipe_w < pfit_w) | |
6352 | pipe_w = pfit_w; | |
6353 | if (pipe_h < pfit_h) | |
6354 | pipe_h = pfit_h; | |
6355 | ||
6356 | if (WARN_ON(!pfit_w || !pfit_h)) | |
6357 | return pixel_rate; | |
6358 | ||
6359 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
6360 | pfit_w * pfit_h); | |
6361 | } | |
6362 | ||
6363 | return pixel_rate; | |
6364 | } | |
6365 | ||
7ff89ca2 | 6366 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 6367 | { |
7ff89ca2 | 6368 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
34edce2f | 6369 | |
7ff89ca2 VS |
6370 | if (HAS_GMCH_DISPLAY(dev_priv)) |
6371 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ | |
6372 | crtc_state->pixel_rate = | |
6373 | crtc_state->base.adjusted_mode.crtc_clock; | |
6374 | else | |
6375 | crtc_state->pixel_rate = | |
6376 | ilk_pipe_pixel_rate(crtc_state); | |
6377 | } | |
34edce2f | 6378 | |
7ff89ca2 VS |
6379 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6380 | struct intel_crtc_state *pipe_config) | |
6381 | { | |
6382 | struct drm_device *dev = crtc->base.dev; | |
6383 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6384 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6385 | int clock_limit = dev_priv->max_dotclk_freq; | |
34edce2f | 6386 | |
7ff89ca2 VS |
6387 | if (INTEL_GEN(dev_priv) < 4) { |
6388 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 6389 | |
7ff89ca2 VS |
6390 | /* |
6391 | * Enable double wide mode when the dot clock | |
6392 | * is > 90% of the (display) core speed. | |
6393 | */ | |
6394 | if (intel_crtc_supports_double_wide(crtc) && | |
6395 | adjusted_mode->crtc_clock > clock_limit) { | |
6396 | clock_limit = dev_priv->max_dotclk_freq; | |
6397 | pipe_config->double_wide = true; | |
6398 | } | |
34edce2f VS |
6399 | } |
6400 | ||
7ff89ca2 VS |
6401 | if (adjusted_mode->crtc_clock > clock_limit) { |
6402 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6403 | adjusted_mode->crtc_clock, clock_limit, | |
6404 | yesno(pipe_config->double_wide)); | |
6405 | return -EINVAL; | |
6406 | } | |
34edce2f | 6407 | |
25edf915 SS |
6408 | if (pipe_config->ycbcr420 && pipe_config->base.ctm) { |
6409 | /* | |
6410 | * There is only one pipe CSC unit per pipe, and we need that | |
6411 | * for output conversion from RGB->YCBCR. So if CTM is already | |
6412 | * applied we can't support YCBCR420 output. | |
6413 | */ | |
6414 | DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n"); | |
6415 | return -EINVAL; | |
6416 | } | |
6417 | ||
7ff89ca2 VS |
6418 | /* |
6419 | * Pipe horizontal size must be even in: | |
6420 | * - DVO ganged mode | |
6421 | * - LVDS dual channel mode | |
6422 | * - Double wide pipe | |
6423 | */ | |
6424 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6425 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6426 | pipe_config->pipe_src_w &= ~1; | |
34edce2f | 6427 | |
7ff89ca2 VS |
6428 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6429 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6430 | */ | |
6431 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
6432 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6433 | return -EINVAL; | |
34edce2f | 6434 | |
7ff89ca2 | 6435 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 6436 | |
7ff89ca2 VS |
6437 | if (HAS_IPS(dev_priv)) |
6438 | hsw_compute_ips_config(crtc, pipe_config); | |
34edce2f | 6439 | |
7ff89ca2 VS |
6440 | if (pipe_config->has_pch_encoder) |
6441 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
34edce2f | 6442 | |
7ff89ca2 | 6443 | return 0; |
34edce2f VS |
6444 | } |
6445 | ||
2c07245f | 6446 | static void |
a65851af | 6447 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6448 | { |
a65851af VS |
6449 | while (*num > DATA_LINK_M_N_MASK || |
6450 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6451 | *num >>= 1; |
6452 | *den >>= 1; | |
6453 | } | |
6454 | } | |
6455 | ||
a65851af | 6456 | static void compute_m_n(unsigned int m, unsigned int n, |
b31e85ed JN |
6457 | uint32_t *ret_m, uint32_t *ret_n, |
6458 | bool reduce_m_n) | |
a65851af | 6459 | { |
9a86cda0 JN |
6460 | /* |
6461 | * Reduce M/N as much as possible without loss in precision. Several DP | |
6462 | * dongles in particular seem to be fussy about too large *link* M/N | |
6463 | * values. The passed in values are more likely to have the least | |
6464 | * significant bits zero than M after rounding below, so do this first. | |
6465 | */ | |
b31e85ed JN |
6466 | if (reduce_m_n) { |
6467 | while ((m & 1) == 0 && (n & 1) == 0) { | |
6468 | m >>= 1; | |
6469 | n >>= 1; | |
6470 | } | |
9a86cda0 JN |
6471 | } |
6472 | ||
a65851af VS |
6473 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
6474 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6475 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6476 | } | |
6477 | ||
e69d0bc1 DV |
6478 | void |
6479 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6480 | int pixel_clock, int link_clock, | |
b31e85ed JN |
6481 | struct intel_link_m_n *m_n, |
6482 | bool reduce_m_n) | |
2c07245f | 6483 | { |
e69d0bc1 | 6484 | m_n->tu = 64; |
a65851af VS |
6485 | |
6486 | compute_m_n(bits_per_pixel * pixel_clock, | |
6487 | link_clock * nlanes * 8, | |
b31e85ed JN |
6488 | &m_n->gmch_m, &m_n->gmch_n, |
6489 | reduce_m_n); | |
a65851af VS |
6490 | |
6491 | compute_m_n(pixel_clock, link_clock, | |
b31e85ed JN |
6492 | &m_n->link_m, &m_n->link_n, |
6493 | reduce_m_n); | |
2c07245f ZW |
6494 | } |
6495 | ||
a7615030 CW |
6496 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6497 | { | |
4f044a88 MW |
6498 | if (i915_modparams.panel_use_ssc >= 0) |
6499 | return i915_modparams.panel_use_ssc != 0; | |
41aa3448 | 6500 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6501 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6502 | } |
6503 | ||
7429e9d4 | 6504 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6505 | { |
7df00d7a | 6506 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6507 | } |
f47709a9 | 6508 | |
7429e9d4 DV |
6509 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6510 | { | |
6511 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6512 | } |
6513 | ||
f47709a9 | 6514 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6515 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 6516 | struct dpll *reduced_clock) |
a7516a05 | 6517 | { |
9b1e14f4 | 6518 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
6519 | u32 fp, fp2 = 0; |
6520 | ||
9b1e14f4 | 6521 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 6522 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6523 | if (reduced_clock) |
7429e9d4 | 6524 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6525 | } else { |
190f68c5 | 6526 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6527 | if (reduced_clock) |
7429e9d4 | 6528 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6529 | } |
6530 | ||
190f68c5 | 6531 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6532 | |
f47709a9 | 6533 | crtc->lowfreq_avail = false; |
2d84d2b3 | 6534 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6535 | reduced_clock) { |
190f68c5 | 6536 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6537 | crtc->lowfreq_avail = true; |
a7516a05 | 6538 | } else { |
190f68c5 | 6539 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6540 | } |
6541 | } | |
6542 | ||
5e69f97f CML |
6543 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6544 | pipe) | |
89b667f8 JB |
6545 | { |
6546 | u32 reg_val; | |
6547 | ||
6548 | /* | |
6549 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6550 | * and set it to a reasonable value instead. | |
6551 | */ | |
ab3c759a | 6552 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6553 | reg_val &= 0xffffff00; |
6554 | reg_val |= 0x00000030; | |
ab3c759a | 6555 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6556 | |
ab3c759a | 6557 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
ed58570f ID |
6558 | reg_val &= 0x00ffffff; |
6559 | reg_val |= 0x8c000000; | |
ab3c759a | 6560 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6561 | |
ab3c759a | 6562 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6563 | reg_val &= 0xffffff00; |
ab3c759a | 6564 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6565 | |
ab3c759a | 6566 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6567 | reg_val &= 0x00ffffff; |
6568 | reg_val |= 0xb0000000; | |
ab3c759a | 6569 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6570 | } |
6571 | ||
b551842d DV |
6572 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6573 | struct intel_link_m_n *m_n) | |
6574 | { | |
6575 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6576 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
6577 | int pipe = crtc->pipe; |
6578 | ||
e3b95f1e DV |
6579 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6580 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6581 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6582 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6583 | } |
6584 | ||
6585 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6586 | struct intel_link_m_n *m_n, |
6587 | struct intel_link_m_n *m2_n2) | |
b551842d | 6588 | { |
6315b5d3 | 6589 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 6590 | int pipe = crtc->pipe; |
6e3c9717 | 6591 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 6592 | |
6315b5d3 | 6593 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
6594 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6595 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6596 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6597 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6598 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6599 | * for gen < 8) and if DRRS is supported (to make sure the | |
6600 | * registers are not unnecessarily accessed). | |
6601 | */ | |
920a14b2 TU |
6602 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
6603 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
6604 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6605 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6606 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6607 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6608 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6609 | } | |
b551842d | 6610 | } else { |
e3b95f1e DV |
6611 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6612 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6613 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6614 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6615 | } |
6616 | } | |
6617 | ||
fe3cd48d | 6618 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6619 | { |
fe3cd48d R |
6620 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6621 | ||
6622 | if (m_n == M1_N1) { | |
6623 | dp_m_n = &crtc->config->dp_m_n; | |
6624 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6625 | } else if (m_n == M2_N2) { | |
6626 | ||
6627 | /* | |
6628 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6629 | * needs to be programmed into M1_N1. | |
6630 | */ | |
6631 | dp_m_n = &crtc->config->dp_m2_n2; | |
6632 | } else { | |
6633 | DRM_ERROR("Unsupported divider value\n"); | |
6634 | return; | |
6635 | } | |
6636 | ||
6e3c9717 ACO |
6637 | if (crtc->config->has_pch_encoder) |
6638 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6639 | else |
fe3cd48d | 6640 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6641 | } |
6642 | ||
251ac862 DV |
6643 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
6644 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 6645 | { |
03ed5cbf | 6646 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 6647 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6648 | if (crtc->pipe != PIPE_A) |
6649 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 6650 | |
cd2d34d9 | 6651 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6652 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6653 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
6654 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
6655 | ||
03ed5cbf VS |
6656 | pipe_config->dpll_hw_state.dpll_md = |
6657 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6658 | } | |
bdd4b6a6 | 6659 | |
03ed5cbf VS |
6660 | static void chv_compute_dpll(struct intel_crtc *crtc, |
6661 | struct intel_crtc_state *pipe_config) | |
6662 | { | |
6663 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 6664 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6665 | if (crtc->pipe != PIPE_A) |
6666 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6667 | ||
cd2d34d9 | 6668 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6669 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6670 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
6671 | ||
03ed5cbf VS |
6672 | pipe_config->dpll_hw_state.dpll_md = |
6673 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
6674 | } |
6675 | ||
d288f65f | 6676 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6677 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6678 | { |
f47709a9 | 6679 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6680 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6681 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 6682 | u32 mdiv; |
a0c4da24 | 6683 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6684 | u32 coreclk, reg_val; |
a0c4da24 | 6685 | |
cd2d34d9 VS |
6686 | /* Enable Refclk */ |
6687 | I915_WRITE(DPLL(pipe), | |
6688 | pipe_config->dpll_hw_state.dpll & | |
6689 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
6690 | ||
6691 | /* No need to actually set up the DPLL with DSI */ | |
6692 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6693 | return; | |
6694 | ||
a580516d | 6695 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 6696 | |
d288f65f VS |
6697 | bestn = pipe_config->dpll.n; |
6698 | bestm1 = pipe_config->dpll.m1; | |
6699 | bestm2 = pipe_config->dpll.m2; | |
6700 | bestp1 = pipe_config->dpll.p1; | |
6701 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6702 | |
89b667f8 JB |
6703 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6704 | ||
6705 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6706 | if (pipe == PIPE_B) |
5e69f97f | 6707 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6708 | |
6709 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6710 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6711 | |
6712 | /* Disable target IRef on PLL */ | |
ab3c759a | 6713 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6714 | reg_val &= 0x00ffffff; |
ab3c759a | 6715 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6716 | |
6717 | /* Disable fast lock */ | |
ab3c759a | 6718 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6719 | |
6720 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6721 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6722 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6723 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6724 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6725 | |
6726 | /* | |
6727 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6728 | * but we don't support that). | |
6729 | * Note: don't use the DAC post divider as it seems unstable. | |
6730 | */ | |
6731 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6732 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6733 | |
a0c4da24 | 6734 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6735 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6736 | |
89b667f8 | 6737 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6738 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
6739 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
6740 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6741 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6742 | 0x009f0003); |
89b667f8 | 6743 | else |
ab3c759a | 6744 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6745 | 0x00d0000f); |
6746 | ||
37a5650b | 6747 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 6748 | /* Use SSC source */ |
bdd4b6a6 | 6749 | if (pipe == PIPE_A) |
ab3c759a | 6750 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6751 | 0x0df40000); |
6752 | else | |
ab3c759a | 6753 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6754 | 0x0df70000); |
6755 | } else { /* HDMI or VGA */ | |
6756 | /* Use bend source */ | |
bdd4b6a6 | 6757 | if (pipe == PIPE_A) |
ab3c759a | 6758 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6759 | 0x0df70000); |
6760 | else | |
ab3c759a | 6761 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6762 | 0x0df40000); |
6763 | } | |
a0c4da24 | 6764 | |
ab3c759a | 6765 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6766 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 6767 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 6768 | coreclk |= 0x01000000; |
ab3c759a | 6769 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6770 | |
ab3c759a | 6771 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 6772 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
6773 | } |
6774 | ||
d288f65f | 6775 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6776 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6777 | { |
6778 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6779 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6780 | enum pipe pipe = crtc->pipe; |
9d556c99 | 6781 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 6782 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6783 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6784 | u32 dpio_val; |
9cbe40c1 | 6785 | int vco; |
9d556c99 | 6786 | |
cd2d34d9 VS |
6787 | /* Enable Refclk and SSC */ |
6788 | I915_WRITE(DPLL(pipe), | |
6789 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
6790 | ||
6791 | /* No need to actually set up the DPLL with DSI */ | |
6792 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6793 | return; | |
6794 | ||
d288f65f VS |
6795 | bestn = pipe_config->dpll.n; |
6796 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6797 | bestm1 = pipe_config->dpll.m1; | |
6798 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6799 | bestp1 = pipe_config->dpll.p1; | |
6800 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6801 | vco = pipe_config->dpll.vco; |
a945ce7e | 6802 | dpio_val = 0; |
9cbe40c1 | 6803 | loopfilter = 0; |
9d556c99 | 6804 | |
a580516d | 6805 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 6806 | |
9d556c99 CML |
6807 | /* p1 and p2 divider */ |
6808 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6809 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6810 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6811 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6812 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6813 | ||
6814 | /* Feedback post-divider - m2 */ | |
6815 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6816 | ||
6817 | /* Feedback refclk divider - n and m1 */ | |
6818 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6819 | DPIO_CHV_M1_DIV_BY_2 | | |
6820 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6821 | ||
6822 | /* M2 fraction division */ | |
25a25dfc | 6823 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
6824 | |
6825 | /* M2 fraction division enable */ | |
a945ce7e VP |
6826 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6827 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6828 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6829 | if (bestm2_frac) | |
6830 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6831 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6832 | |
de3a0fde VP |
6833 | /* Program digital lock detect threshold */ |
6834 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6835 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6836 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6837 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6838 | if (!bestm2_frac) | |
6839 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6840 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6841 | ||
9d556c99 | 6842 | /* Loop filter */ |
9cbe40c1 VP |
6843 | if (vco == 5400000) { |
6844 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6845 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6846 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6847 | tribuf_calcntr = 0x9; | |
6848 | } else if (vco <= 6200000) { | |
6849 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6850 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6851 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6852 | tribuf_calcntr = 0x9; | |
6853 | } else if (vco <= 6480000) { | |
6854 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6855 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6856 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6857 | tribuf_calcntr = 0x8; | |
6858 | } else { | |
6859 | /* Not supported. Apply the same limits as in the max case */ | |
6860 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6861 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6862 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6863 | tribuf_calcntr = 0; | |
6864 | } | |
9d556c99 CML |
6865 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6866 | ||
968040b2 | 6867 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6868 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6869 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6870 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6871 | ||
9d556c99 CML |
6872 | /* AFC Recal */ |
6873 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6874 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6875 | DPIO_AFC_RECAL); | |
6876 | ||
a580516d | 6877 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
6878 | } |
6879 | ||
d288f65f VS |
6880 | /** |
6881 | * vlv_force_pll_on - forcibly enable just the PLL | |
6882 | * @dev_priv: i915 private structure | |
6883 | * @pipe: pipe PLL to enable | |
6884 | * @dpll: PLL configuration | |
6885 | * | |
6886 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6887 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6888 | * be enabled. | |
6889 | */ | |
30ad9814 | 6890 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 6891 | const struct dpll *dpll) |
d288f65f | 6892 | { |
b91eb5cc | 6893 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
6894 | struct intel_crtc_state *pipe_config; |
6895 | ||
6896 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
6897 | if (!pipe_config) | |
6898 | return -ENOMEM; | |
6899 | ||
6900 | pipe_config->base.crtc = &crtc->base; | |
6901 | pipe_config->pixel_multiplier = 1; | |
6902 | pipe_config->dpll = *dpll; | |
d288f65f | 6903 | |
30ad9814 | 6904 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
6905 | chv_compute_dpll(crtc, pipe_config); |
6906 | chv_prepare_pll(crtc, pipe_config); | |
6907 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 6908 | } else { |
3f36b937 TU |
6909 | vlv_compute_dpll(crtc, pipe_config); |
6910 | vlv_prepare_pll(crtc, pipe_config); | |
6911 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 6912 | } |
3f36b937 TU |
6913 | |
6914 | kfree(pipe_config); | |
6915 | ||
6916 | return 0; | |
d288f65f VS |
6917 | } |
6918 | ||
6919 | /** | |
6920 | * vlv_force_pll_off - forcibly disable just the PLL | |
6921 | * @dev_priv: i915 private structure | |
6922 | * @pipe: pipe PLL to disable | |
6923 | * | |
6924 | * Disable the PLL for @pipe. To be used in cases where we need | |
6925 | * the PLL enabled even when @pipe is not going to be enabled. | |
6926 | */ | |
30ad9814 | 6927 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 6928 | { |
30ad9814 VS |
6929 | if (IS_CHERRYVIEW(dev_priv)) |
6930 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 6931 | else |
30ad9814 | 6932 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
6933 | } |
6934 | ||
251ac862 DV |
6935 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
6936 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6937 | struct dpll *reduced_clock) |
eb1cbe48 | 6938 | { |
9b1e14f4 | 6939 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 6940 | u32 dpll; |
190f68c5 | 6941 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6942 | |
190f68c5 | 6943 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6944 | |
eb1cbe48 DV |
6945 | dpll = DPLL_VGA_MODE_DIS; |
6946 | ||
2d84d2b3 | 6947 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6948 | dpll |= DPLLB_MODE_LVDS; |
6949 | else | |
6950 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6951 | |
73f67aa8 JN |
6952 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
6953 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 6954 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6955 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6956 | } |
198a037f | 6957 | |
3d6e9ee0 VS |
6958 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6959 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 6960 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6961 | |
37a5650b | 6962 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 6963 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6964 | |
6965 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 6966 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
6967 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
6968 | else { | |
6969 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 6970 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
6971 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6972 | } | |
6973 | switch (clock->p2) { | |
6974 | case 5: | |
6975 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6976 | break; | |
6977 | case 7: | |
6978 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6979 | break; | |
6980 | case 10: | |
6981 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6982 | break; | |
6983 | case 14: | |
6984 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6985 | break; | |
6986 | } | |
9b1e14f4 | 6987 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
6988 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
6989 | ||
190f68c5 | 6990 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6991 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 6992 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6993 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6994 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6995 | else | |
6996 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6997 | ||
6998 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6999 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7000 | |
9b1e14f4 | 7001 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 7002 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7003 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7004 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7005 | } |
7006 | } | |
7007 | ||
251ac862 DV |
7008 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7009 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7010 | struct dpll *reduced_clock) |
eb1cbe48 | 7011 | { |
f47709a9 | 7012 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7013 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 7014 | u32 dpll; |
190f68c5 | 7015 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7016 | |
190f68c5 | 7017 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7018 | |
eb1cbe48 DV |
7019 | dpll = DPLL_VGA_MODE_DIS; |
7020 | ||
2d84d2b3 | 7021 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7022 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7023 | } else { | |
7024 | if (clock->p1 == 2) | |
7025 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7026 | else | |
7027 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7028 | if (clock->p2 == 4) | |
7029 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7030 | } | |
7031 | ||
50a0bc90 TU |
7032 | if (!IS_I830(dev_priv) && |
7033 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
7034 | dpll |= DPLL_DVO_2X_MODE; |
7035 | ||
2d84d2b3 | 7036 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7037 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7038 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7039 | else | |
7040 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7041 | ||
7042 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7043 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7044 | } |
7045 | ||
8a654f3b | 7046 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 7047 | { |
6315b5d3 | 7048 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 7049 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7050 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7051 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7052 | uint32_t crtc_vtotal, crtc_vblank_end; |
7053 | int vsyncshift = 0; | |
4d8a62ea DV |
7054 | |
7055 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7056 | * the hw state checker will get angry at the mismatch. */ | |
7057 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7058 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7059 | |
609aeaca | 7060 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7061 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7062 | crtc_vtotal -= 1; |
7063 | crtc_vblank_end -= 1; | |
609aeaca | 7064 | |
2d84d2b3 | 7065 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7066 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7067 | else | |
7068 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7069 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7070 | if (vsyncshift < 0) |
7071 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7072 | } |
7073 | ||
6315b5d3 | 7074 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 7075 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7076 | |
fe2b8f9d | 7077 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7078 | (adjusted_mode->crtc_hdisplay - 1) | |
7079 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7080 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7081 | (adjusted_mode->crtc_hblank_start - 1) | |
7082 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7083 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7084 | (adjusted_mode->crtc_hsync_start - 1) | |
7085 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7086 | ||
fe2b8f9d | 7087 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7088 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7089 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7090 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7091 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7092 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7093 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7094 | (adjusted_mode->crtc_vsync_start - 1) | |
7095 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7096 | ||
b5e508d4 PZ |
7097 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7098 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7099 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7100 | * bits. */ | |
772c2a51 | 7101 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
7102 | (pipe == PIPE_B || pipe == PIPE_C)) |
7103 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7104 | ||
bc58be60 JN |
7105 | } |
7106 | ||
7107 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7108 | { | |
7109 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7110 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
7111 | enum pipe pipe = intel_crtc->pipe; |
7112 | ||
b0e77b9c PZ |
7113 | /* pipesrc controls the size that is scaled from, which should |
7114 | * always be the user's requested size. | |
7115 | */ | |
7116 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7117 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7118 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7119 | } |
7120 | ||
1bd1bd80 | 7121 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7122 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7123 | { |
7124 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7125 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
7126 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7127 | uint32_t tmp; | |
7128 | ||
7129 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7130 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7131 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7132 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7133 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7134 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7135 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7136 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7137 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7138 | |
7139 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7140 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7141 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7142 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7143 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7144 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7145 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7146 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7147 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7148 | |
7149 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7150 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7151 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7152 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7153 | } |
bc58be60 JN |
7154 | } |
7155 | ||
7156 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7157 | struct intel_crtc_state *pipe_config) | |
7158 | { | |
7159 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7160 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 7161 | u32 tmp; |
1bd1bd80 DV |
7162 | |
7163 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7164 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7165 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7166 | ||
2d112de7 ACO |
7167 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7168 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7169 | } |
7170 | ||
f6a83288 | 7171 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7172 | struct intel_crtc_state *pipe_config) |
babea61d | 7173 | { |
2d112de7 ACO |
7174 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7175 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7176 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7177 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7178 | |
2d112de7 ACO |
7179 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7180 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7181 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7182 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7183 | |
2d112de7 | 7184 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7185 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7186 | |
2d112de7 | 7187 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
cd13f5ab ML |
7188 | |
7189 | mode->hsync = drm_mode_hsync(mode); | |
7190 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7191 | drm_mode_set_name(mode); | |
babea61d JB |
7192 | } |
7193 | ||
84b046f3 DV |
7194 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7195 | { | |
6315b5d3 | 7196 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
7197 | uint32_t pipeconf; |
7198 | ||
9f11a9e4 | 7199 | pipeconf = 0; |
84b046f3 | 7200 | |
e56134bc VS |
7201 | /* we keep both pipes enabled on 830 */ |
7202 | if (IS_I830(dev_priv)) | |
b6b5d049 | 7203 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; |
67c72a12 | 7204 | |
6e3c9717 | 7205 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7206 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7207 | |
ff9ce46e | 7208 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
7209 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7210 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 7211 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7212 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7213 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7214 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7215 | |
6e3c9717 | 7216 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7217 | case 18: |
7218 | pipeconf |= PIPECONF_6BPC; | |
7219 | break; | |
7220 | case 24: | |
7221 | pipeconf |= PIPECONF_8BPC; | |
7222 | break; | |
7223 | case 30: | |
7224 | pipeconf |= PIPECONF_10BPC; | |
7225 | break; | |
7226 | default: | |
7227 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7228 | BUG(); | |
84b046f3 DV |
7229 | } |
7230 | } | |
7231 | ||
56b857a5 | 7232 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
7233 | if (intel_crtc->lowfreq_avail) { |
7234 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7235 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7236 | } else { | |
7237 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7238 | } |
7239 | } | |
7240 | ||
6e3c9717 | 7241 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 7242 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 7243 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7244 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7245 | else | |
7246 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7247 | } else | |
84b046f3 DV |
7248 | pipeconf |= PIPECONF_PROGRESSIVE; |
7249 | ||
920a14b2 | 7250 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7251 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 7252 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7253 | |
84b046f3 DV |
7254 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7255 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7256 | } | |
7257 | ||
81c97f52 ACO |
7258 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7259 | struct intel_crtc_state *crtc_state) | |
7260 | { | |
7261 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7262 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7263 | const struct intel_limit *limit; |
81c97f52 ACO |
7264 | int refclk = 48000; |
7265 | ||
7266 | memset(&crtc_state->dpll_hw_state, 0, | |
7267 | sizeof(crtc_state->dpll_hw_state)); | |
7268 | ||
2d84d2b3 | 7269 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7270 | if (intel_panel_use_ssc(dev_priv)) { |
7271 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7272 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7273 | } | |
7274 | ||
7275 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7276 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7277 | limit = &intel_limits_i8xx_dvo; |
7278 | } else { | |
7279 | limit = &intel_limits_i8xx_dac; | |
7280 | } | |
7281 | ||
7282 | if (!crtc_state->clock_set && | |
7283 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7284 | refclk, NULL, &crtc_state->dpll)) { | |
7285 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7286 | return -EINVAL; | |
7287 | } | |
7288 | ||
7289 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7290 | ||
7291 | return 0; | |
7292 | } | |
7293 | ||
19ec6693 ACO |
7294 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7295 | struct intel_crtc_state *crtc_state) | |
7296 | { | |
7297 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7298 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7299 | const struct intel_limit *limit; |
19ec6693 ACO |
7300 | int refclk = 96000; |
7301 | ||
7302 | memset(&crtc_state->dpll_hw_state, 0, | |
7303 | sizeof(crtc_state->dpll_hw_state)); | |
7304 | ||
2d84d2b3 | 7305 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7306 | if (intel_panel_use_ssc(dev_priv)) { |
7307 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7308 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7309 | } | |
7310 | ||
7311 | if (intel_is_dual_link_lvds(dev)) | |
7312 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7313 | else | |
7314 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7315 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7316 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7317 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7318 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7319 | limit = &intel_limits_g4x_sdvo; |
7320 | } else { | |
7321 | /* The option is for other outputs */ | |
7322 | limit = &intel_limits_i9xx_sdvo; | |
7323 | } | |
7324 | ||
7325 | if (!crtc_state->clock_set && | |
7326 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7327 | refclk, NULL, &crtc_state->dpll)) { | |
7328 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7329 | return -EINVAL; | |
7330 | } | |
7331 | ||
7332 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7333 | ||
7334 | return 0; | |
7335 | } | |
7336 | ||
70e8aa21 ACO |
7337 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7338 | struct intel_crtc_state *crtc_state) | |
7339 | { | |
7340 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7341 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7342 | const struct intel_limit *limit; |
70e8aa21 ACO |
7343 | int refclk = 96000; |
7344 | ||
7345 | memset(&crtc_state->dpll_hw_state, 0, | |
7346 | sizeof(crtc_state->dpll_hw_state)); | |
7347 | ||
2d84d2b3 | 7348 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7349 | if (intel_panel_use_ssc(dev_priv)) { |
7350 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7351 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7352 | } | |
7353 | ||
7354 | limit = &intel_limits_pineview_lvds; | |
7355 | } else { | |
7356 | limit = &intel_limits_pineview_sdvo; | |
7357 | } | |
7358 | ||
7359 | if (!crtc_state->clock_set && | |
7360 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7361 | refclk, NULL, &crtc_state->dpll)) { | |
7362 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7363 | return -EINVAL; | |
7364 | } | |
7365 | ||
7366 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7367 | ||
7368 | return 0; | |
7369 | } | |
7370 | ||
190f68c5 ACO |
7371 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7372 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7373 | { |
c7653199 | 7374 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7375 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7376 | const struct intel_limit *limit; |
81c97f52 | 7377 | int refclk = 96000; |
79e53945 | 7378 | |
dd3cd74a ACO |
7379 | memset(&crtc_state->dpll_hw_state, 0, |
7380 | sizeof(crtc_state->dpll_hw_state)); | |
7381 | ||
2d84d2b3 | 7382 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7383 | if (intel_panel_use_ssc(dev_priv)) { |
7384 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7385 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7386 | } | |
43565a06 | 7387 | |
70e8aa21 ACO |
7388 | limit = &intel_limits_i9xx_lvds; |
7389 | } else { | |
7390 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7391 | } |
79e53945 | 7392 | |
70e8aa21 ACO |
7393 | if (!crtc_state->clock_set && |
7394 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7395 | refclk, NULL, &crtc_state->dpll)) { | |
7396 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7397 | return -EINVAL; | |
f47709a9 | 7398 | } |
7026d4ac | 7399 | |
81c97f52 | 7400 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7401 | |
c8f7a0db | 7402 | return 0; |
f564048e EA |
7403 | } |
7404 | ||
65b3d6a9 ACO |
7405 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7406 | struct intel_crtc_state *crtc_state) | |
7407 | { | |
7408 | int refclk = 100000; | |
1b6f4958 | 7409 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7410 | |
7411 | memset(&crtc_state->dpll_hw_state, 0, | |
7412 | sizeof(crtc_state->dpll_hw_state)); | |
7413 | ||
65b3d6a9 ACO |
7414 | if (!crtc_state->clock_set && |
7415 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7416 | refclk, NULL, &crtc_state->dpll)) { | |
7417 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7418 | return -EINVAL; | |
7419 | } | |
7420 | ||
7421 | chv_compute_dpll(crtc, crtc_state); | |
7422 | ||
7423 | return 0; | |
7424 | } | |
7425 | ||
7426 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7427 | struct intel_crtc_state *crtc_state) | |
7428 | { | |
7429 | int refclk = 100000; | |
1b6f4958 | 7430 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7431 | |
7432 | memset(&crtc_state->dpll_hw_state, 0, | |
7433 | sizeof(crtc_state->dpll_hw_state)); | |
7434 | ||
65b3d6a9 ACO |
7435 | if (!crtc_state->clock_set && |
7436 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7437 | refclk, NULL, &crtc_state->dpll)) { | |
7438 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7439 | return -EINVAL; | |
7440 | } | |
7441 | ||
7442 | vlv_compute_dpll(crtc, crtc_state); | |
7443 | ||
7444 | return 0; | |
7445 | } | |
7446 | ||
2fa2fe9a | 7447 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7448 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 7449 | { |
6315b5d3 | 7450 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
7451 | uint32_t tmp; |
7452 | ||
50a0bc90 TU |
7453 | if (INTEL_GEN(dev_priv) <= 3 && |
7454 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
7455 | return; |
7456 | ||
2fa2fe9a | 7457 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7458 | if (!(tmp & PFIT_ENABLE)) |
7459 | return; | |
2fa2fe9a | 7460 | |
06922821 | 7461 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 7462 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
7463 | if (crtc->pipe != PIPE_B) |
7464 | return; | |
2fa2fe9a DV |
7465 | } else { |
7466 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7467 | return; | |
7468 | } | |
7469 | ||
06922821 | 7470 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7471 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7472 | } |
7473 | ||
acbec814 | 7474 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7475 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7476 | { |
7477 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7478 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 7479 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 7480 | struct dpll clock; |
acbec814 | 7481 | u32 mdiv; |
662c6ecb | 7482 | int refclk = 100000; |
acbec814 | 7483 | |
b521973b VS |
7484 | /* In case of DSI, DPLL will not be used */ |
7485 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
7486 | return; |
7487 | ||
a580516d | 7488 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7489 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7490 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7491 | |
7492 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7493 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7494 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7495 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7496 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7497 | ||
dccbea3b | 7498 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7499 | } |
7500 | ||
5724dbd1 DL |
7501 | static void |
7502 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7503 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7504 | { |
7505 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7506 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
7507 | u32 val, base, offset; |
7508 | int pipe = crtc->pipe, plane = crtc->plane; | |
7509 | int fourcc, pixel_format; | |
6761dd31 | 7510 | unsigned int aligned_height; |
b113d5ee | 7511 | struct drm_framebuffer *fb; |
1b842c89 | 7512 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7513 | |
42a7b088 DL |
7514 | val = I915_READ(DSPCNTR(plane)); |
7515 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7516 | return; | |
7517 | ||
d9806c9f | 7518 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7519 | if (!intel_fb) { |
1ad292b5 JB |
7520 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7521 | return; | |
7522 | } | |
7523 | ||
1b842c89 DL |
7524 | fb = &intel_fb->base; |
7525 | ||
d2e9f5fc VS |
7526 | fb->dev = dev; |
7527 | ||
6315b5d3 | 7528 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 7529 | if (val & DISPPLANE_TILED) { |
49af449b | 7530 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 7531 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
7532 | } |
7533 | } | |
1ad292b5 JB |
7534 | |
7535 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7536 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 7537 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 7538 | |
6315b5d3 | 7539 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 7540 | if (plane_config->tiling) |
1ad292b5 JB |
7541 | offset = I915_READ(DSPTILEOFF(plane)); |
7542 | else | |
7543 | offset = I915_READ(DSPLINOFF(plane)); | |
7544 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7545 | } else { | |
7546 | base = I915_READ(DSPADDR(plane)); | |
7547 | } | |
7548 | plane_config->base = base; | |
7549 | ||
7550 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7551 | fb->width = ((val >> 16) & 0xfff) + 1; |
7552 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7553 | |
7554 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7555 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7556 | |
d88c4afd | 7557 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1ad292b5 | 7558 | |
f37b5c2b | 7559 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7560 | |
2844a921 DL |
7561 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7562 | pipe_name(pipe), plane, fb->width, fb->height, | |
272725c7 | 7563 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 7564 | plane_config->size); |
1ad292b5 | 7565 | |
2d14030b | 7566 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7567 | } |
7568 | ||
70b23a98 | 7569 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7570 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7571 | { |
7572 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7573 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
7574 | int pipe = pipe_config->cpu_transcoder; |
7575 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 7576 | struct dpll clock; |
0d7b6b11 | 7577 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
7578 | int refclk = 100000; |
7579 | ||
b521973b VS |
7580 | /* In case of DSI, DPLL will not be used */ |
7581 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7582 | return; | |
7583 | ||
a580516d | 7584 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7585 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7586 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7587 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7588 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 7589 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 7590 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7591 | |
7592 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
7593 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7594 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
7595 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
7596 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7597 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7598 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7599 | ||
dccbea3b | 7600 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
7601 | } |
7602 | ||
0e8ffe1b | 7603 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7604 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 7605 | { |
6315b5d3 | 7606 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 7607 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 7608 | uint32_t tmp; |
1729050e | 7609 | bool ret; |
0e8ffe1b | 7610 | |
1729050e ID |
7611 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
7612 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
7613 | return false; |
7614 | ||
e143a21c | 7615 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 7616 | pipe_config->shared_dpll = NULL; |
eccb140b | 7617 | |
1729050e ID |
7618 | ret = false; |
7619 | ||
0e8ffe1b DV |
7620 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7621 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 7622 | goto out; |
0e8ffe1b | 7623 | |
9beb5fea TU |
7624 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7625 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
7626 | switch (tmp & PIPECONF_BPC_MASK) { |
7627 | case PIPECONF_6BPC: | |
7628 | pipe_config->pipe_bpp = 18; | |
7629 | break; | |
7630 | case PIPECONF_8BPC: | |
7631 | pipe_config->pipe_bpp = 24; | |
7632 | break; | |
7633 | case PIPECONF_10BPC: | |
7634 | pipe_config->pipe_bpp = 30; | |
7635 | break; | |
7636 | default: | |
7637 | break; | |
7638 | } | |
7639 | } | |
7640 | ||
920a14b2 | 7641 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7642 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
7643 | pipe_config->limited_color_range = true; |
7644 | ||
6315b5d3 | 7645 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
7646 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
7647 | ||
1bd1bd80 | 7648 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 7649 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 7650 | |
2fa2fe9a DV |
7651 | i9xx_get_pfit_config(crtc, pipe_config); |
7652 | ||
6315b5d3 | 7653 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 7654 | /* No way to read it out on pipes B and C */ |
920a14b2 | 7655 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
7656 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
7657 | else | |
7658 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
7659 | pipe_config->pixel_multiplier = |
7660 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7661 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7662 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 7663 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 7664 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
7665 | tmp = I915_READ(DPLL(crtc->pipe)); |
7666 | pipe_config->pixel_multiplier = | |
7667 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7668 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7669 | } else { | |
7670 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7671 | * port and will be fixed up in the encoder->get_config | |
7672 | * function. */ | |
7673 | pipe_config->pixel_multiplier = 1; | |
7674 | } | |
8bcc2795 | 7675 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 7676 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
7677 | /* |
7678 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7679 | * on 830. Filter it out here so that we don't | |
7680 | * report errors due to that. | |
7681 | */ | |
50a0bc90 | 7682 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
7683 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
7684 | ||
8bcc2795 DV |
7685 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7686 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7687 | } else { |
7688 | /* Mask out read-only status bits. */ | |
7689 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7690 | DPLL_PORTC_READY_MASK | | |
7691 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7692 | } |
6c49f241 | 7693 | |
920a14b2 | 7694 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 7695 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 7696 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
7697 | vlv_crtc_clock_get(crtc, pipe_config); |
7698 | else | |
7699 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7700 | |
0f64614d VS |
7701 | /* |
7702 | * Normally the dotclock is filled in by the encoder .get_config() | |
7703 | * but in case the pipe is enabled w/o any ports we need a sane | |
7704 | * default. | |
7705 | */ | |
7706 | pipe_config->base.adjusted_mode.crtc_clock = | |
7707 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
7708 | ||
1729050e ID |
7709 | ret = true; |
7710 | ||
7711 | out: | |
7712 | intel_display_power_put(dev_priv, power_domain); | |
7713 | ||
7714 | return ret; | |
0e8ffe1b DV |
7715 | } |
7716 | ||
c39055b0 | 7717 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 7718 | { |
13d83a67 | 7719 | struct intel_encoder *encoder; |
1c1a24d2 | 7720 | int i; |
74cfd7ac | 7721 | u32 val, final; |
13d83a67 | 7722 | bool has_lvds = false; |
199e5d79 | 7723 | bool has_cpu_edp = false; |
199e5d79 | 7724 | bool has_panel = false; |
99eb6a01 KP |
7725 | bool has_ck505 = false; |
7726 | bool can_ssc = false; | |
1c1a24d2 | 7727 | bool using_ssc_source = false; |
13d83a67 JB |
7728 | |
7729 | /* We need to take the global config into account */ | |
c39055b0 | 7730 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
7731 | switch (encoder->type) { |
7732 | case INTEL_OUTPUT_LVDS: | |
7733 | has_panel = true; | |
7734 | has_lvds = true; | |
7735 | break; | |
7736 | case INTEL_OUTPUT_EDP: | |
7737 | has_panel = true; | |
2de6905f | 7738 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7739 | has_cpu_edp = true; |
7740 | break; | |
6847d71b PZ |
7741 | default: |
7742 | break; | |
13d83a67 JB |
7743 | } |
7744 | } | |
7745 | ||
6e266956 | 7746 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 7747 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7748 | can_ssc = has_ck505; |
7749 | } else { | |
7750 | has_ck505 = false; | |
7751 | can_ssc = true; | |
7752 | } | |
7753 | ||
1c1a24d2 L |
7754 | /* Check if any DPLLs are using the SSC source */ |
7755 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
7756 | u32 temp = I915_READ(PCH_DPLL(i)); | |
7757 | ||
7758 | if (!(temp & DPLL_VCO_ENABLE)) | |
7759 | continue; | |
7760 | ||
7761 | if ((temp & PLL_REF_INPUT_MASK) == | |
7762 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7763 | using_ssc_source = true; | |
7764 | break; | |
7765 | } | |
7766 | } | |
7767 | ||
7768 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
7769 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
7770 | |
7771 | /* Ironlake: try to setup display ref clock before DPLL | |
7772 | * enabling. This is only under driver's control after | |
7773 | * PCH B stepping, previous chipset stepping should be | |
7774 | * ignoring this setting. | |
7775 | */ | |
74cfd7ac CW |
7776 | val = I915_READ(PCH_DREF_CONTROL); |
7777 | ||
7778 | /* As we must carefully and slowly disable/enable each source in turn, | |
7779 | * compute the final state we want first and check if we need to | |
7780 | * make any changes at all. | |
7781 | */ | |
7782 | final = val; | |
7783 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7784 | if (has_ck505) | |
7785 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7786 | else | |
7787 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7788 | ||
8c07eb68 | 7789 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 7790 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 7791 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
7792 | |
7793 | if (has_panel) { | |
7794 | final |= DREF_SSC_SOURCE_ENABLE; | |
7795 | ||
7796 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7797 | final |= DREF_SSC1_ENABLE; | |
7798 | ||
7799 | if (has_cpu_edp) { | |
7800 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7801 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7802 | else | |
7803 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7804 | } else | |
7805 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
7806 | } else if (using_ssc_source) { |
7807 | final |= DREF_SSC_SOURCE_ENABLE; | |
7808 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
7809 | } |
7810 | ||
7811 | if (final == val) | |
7812 | return; | |
7813 | ||
13d83a67 | 7814 | /* Always enable nonspread source */ |
74cfd7ac | 7815 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7816 | |
99eb6a01 | 7817 | if (has_ck505) |
74cfd7ac | 7818 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7819 | else |
74cfd7ac | 7820 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7821 | |
199e5d79 | 7822 | if (has_panel) { |
74cfd7ac CW |
7823 | val &= ~DREF_SSC_SOURCE_MASK; |
7824 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7825 | |
199e5d79 | 7826 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7827 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7828 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7829 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7830 | } else |
74cfd7ac | 7831 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7832 | |
7833 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7834 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7835 | POSTING_READ(PCH_DREF_CONTROL); |
7836 | udelay(200); | |
7837 | ||
74cfd7ac | 7838 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7839 | |
7840 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7841 | if (has_cpu_edp) { |
99eb6a01 | 7842 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7843 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7844 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7845 | } else |
74cfd7ac | 7846 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7847 | } else |
74cfd7ac | 7848 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7849 | |
74cfd7ac | 7850 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7851 | POSTING_READ(PCH_DREF_CONTROL); |
7852 | udelay(200); | |
7853 | } else { | |
1c1a24d2 | 7854 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 7855 | |
74cfd7ac | 7856 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7857 | |
7858 | /* Turn off CPU output */ | |
74cfd7ac | 7859 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7860 | |
74cfd7ac | 7861 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7862 | POSTING_READ(PCH_DREF_CONTROL); |
7863 | udelay(200); | |
7864 | ||
1c1a24d2 L |
7865 | if (!using_ssc_source) { |
7866 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 7867 | |
1c1a24d2 L |
7868 | /* Turn off the SSC source */ |
7869 | val &= ~DREF_SSC_SOURCE_MASK; | |
7870 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 7871 | |
1c1a24d2 L |
7872 | /* Turn off SSC1 */ |
7873 | val &= ~DREF_SSC1_ENABLE; | |
7874 | ||
7875 | I915_WRITE(PCH_DREF_CONTROL, val); | |
7876 | POSTING_READ(PCH_DREF_CONTROL); | |
7877 | udelay(200); | |
7878 | } | |
13d83a67 | 7879 | } |
74cfd7ac CW |
7880 | |
7881 | BUG_ON(val != final); | |
13d83a67 JB |
7882 | } |
7883 | ||
f31f2d55 | 7884 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7885 | { |
f31f2d55 | 7886 | uint32_t tmp; |
dde86e2d | 7887 | |
0ff066a9 PZ |
7888 | tmp = I915_READ(SOUTH_CHICKEN2); |
7889 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7890 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7891 | |
cf3598c2 ID |
7892 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
7893 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 7894 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 7895 | |
0ff066a9 PZ |
7896 | tmp = I915_READ(SOUTH_CHICKEN2); |
7897 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7898 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7899 | |
cf3598c2 ID |
7900 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
7901 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 7902 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
7903 | } |
7904 | ||
7905 | /* WaMPhyProgramming:hsw */ | |
7906 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7907 | { | |
7908 | uint32_t tmp; | |
dde86e2d PZ |
7909 | |
7910 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7911 | tmp &= ~(0xFF << 24); | |
7912 | tmp |= (0x12 << 24); | |
7913 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7914 | ||
dde86e2d PZ |
7915 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7916 | tmp |= (1 << 11); | |
7917 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7918 | ||
7919 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7920 | tmp |= (1 << 11); | |
7921 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7922 | ||
dde86e2d PZ |
7923 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7924 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7925 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7926 | ||
7927 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7928 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7929 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7930 | ||
0ff066a9 PZ |
7931 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7932 | tmp &= ~(7 << 13); | |
7933 | tmp |= (5 << 13); | |
7934 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7935 | |
0ff066a9 PZ |
7936 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7937 | tmp &= ~(7 << 13); | |
7938 | tmp |= (5 << 13); | |
7939 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7940 | |
7941 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7942 | tmp &= ~0xFF; | |
7943 | tmp |= 0x1C; | |
7944 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7945 | ||
7946 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7947 | tmp &= ~0xFF; | |
7948 | tmp |= 0x1C; | |
7949 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7950 | ||
7951 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7952 | tmp &= ~(0xFF << 16); | |
7953 | tmp |= (0x1C << 16); | |
7954 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7955 | ||
7956 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7957 | tmp &= ~(0xFF << 16); | |
7958 | tmp |= (0x1C << 16); | |
7959 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7960 | ||
0ff066a9 PZ |
7961 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7962 | tmp |= (1 << 27); | |
7963 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7964 | |
0ff066a9 PZ |
7965 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7966 | tmp |= (1 << 27); | |
7967 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7968 | |
0ff066a9 PZ |
7969 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7970 | tmp &= ~(0xF << 28); | |
7971 | tmp |= (4 << 28); | |
7972 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7973 | |
0ff066a9 PZ |
7974 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7975 | tmp &= ~(0xF << 28); | |
7976 | tmp |= (4 << 28); | |
7977 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7978 | } |
7979 | ||
2fa86a1f PZ |
7980 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7981 | * Programming" based on the parameters passed: | |
7982 | * - Sequence to enable CLKOUT_DP | |
7983 | * - Sequence to enable CLKOUT_DP without spread | |
7984 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7985 | */ | |
c39055b0 ACO |
7986 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
7987 | bool with_spread, bool with_fdi) | |
f31f2d55 | 7988 | { |
2fa86a1f PZ |
7989 | uint32_t reg, tmp; |
7990 | ||
7991 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7992 | with_spread = true; | |
4f8036a2 TU |
7993 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
7994 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 7995 | with_fdi = false; |
f31f2d55 | 7996 | |
a580516d | 7997 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
7998 | |
7999 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8000 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8001 | tmp |= SBI_SSCCTL_PATHALT; | |
8002 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8003 | ||
8004 | udelay(24); | |
8005 | ||
2fa86a1f PZ |
8006 | if (with_spread) { |
8007 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8008 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8009 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8010 | |
2fa86a1f PZ |
8011 | if (with_fdi) { |
8012 | lpt_reset_fdi_mphy(dev_priv); | |
8013 | lpt_program_fdi_mphy(dev_priv); | |
8014 | } | |
8015 | } | |
dde86e2d | 8016 | |
4f8036a2 | 8017 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8018 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8019 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8020 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8021 | |
a580516d | 8022 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8023 | } |
8024 | ||
47701c3b | 8025 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 8026 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 8027 | { |
47701c3b PZ |
8028 | uint32_t reg, tmp; |
8029 | ||
a580516d | 8030 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8031 | |
4f8036a2 | 8032 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8033 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8034 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8035 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8036 | ||
8037 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8038 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8039 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8040 | tmp |= SBI_SSCCTL_PATHALT; | |
8041 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8042 | udelay(32); | |
8043 | } | |
8044 | tmp |= SBI_SSCCTL_DISABLE; | |
8045 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8046 | } | |
8047 | ||
a580516d | 8048 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8049 | } |
8050 | ||
f7be2c21 VS |
8051 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8052 | ||
8053 | static const uint16_t sscdivintphase[] = { | |
8054 | [BEND_IDX( 50)] = 0x3B23, | |
8055 | [BEND_IDX( 45)] = 0x3B23, | |
8056 | [BEND_IDX( 40)] = 0x3C23, | |
8057 | [BEND_IDX( 35)] = 0x3C23, | |
8058 | [BEND_IDX( 30)] = 0x3D23, | |
8059 | [BEND_IDX( 25)] = 0x3D23, | |
8060 | [BEND_IDX( 20)] = 0x3E23, | |
8061 | [BEND_IDX( 15)] = 0x3E23, | |
8062 | [BEND_IDX( 10)] = 0x3F23, | |
8063 | [BEND_IDX( 5)] = 0x3F23, | |
8064 | [BEND_IDX( 0)] = 0x0025, | |
8065 | [BEND_IDX( -5)] = 0x0025, | |
8066 | [BEND_IDX(-10)] = 0x0125, | |
8067 | [BEND_IDX(-15)] = 0x0125, | |
8068 | [BEND_IDX(-20)] = 0x0225, | |
8069 | [BEND_IDX(-25)] = 0x0225, | |
8070 | [BEND_IDX(-30)] = 0x0325, | |
8071 | [BEND_IDX(-35)] = 0x0325, | |
8072 | [BEND_IDX(-40)] = 0x0425, | |
8073 | [BEND_IDX(-45)] = 0x0425, | |
8074 | [BEND_IDX(-50)] = 0x0525, | |
8075 | }; | |
8076 | ||
8077 | /* | |
8078 | * Bend CLKOUT_DP | |
8079 | * steps -50 to 50 inclusive, in steps of 5 | |
8080 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8081 | * change in clock period = -(steps / 10) * 5.787 ps | |
8082 | */ | |
8083 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8084 | { | |
8085 | uint32_t tmp; | |
8086 | int idx = BEND_IDX(steps); | |
8087 | ||
8088 | if (WARN_ON(steps % 5 != 0)) | |
8089 | return; | |
8090 | ||
8091 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8092 | return; | |
8093 | ||
8094 | mutex_lock(&dev_priv->sb_lock); | |
8095 | ||
8096 | if (steps % 10 != 0) | |
8097 | tmp = 0xAAAAAAAB; | |
8098 | else | |
8099 | tmp = 0x00000000; | |
8100 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8101 | ||
8102 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8103 | tmp &= 0xffff0000; | |
8104 | tmp |= sscdivintphase[idx]; | |
8105 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8106 | ||
8107 | mutex_unlock(&dev_priv->sb_lock); | |
8108 | } | |
8109 | ||
8110 | #undef BEND_IDX | |
8111 | ||
c39055b0 | 8112 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 8113 | { |
bf8fa3d3 PZ |
8114 | struct intel_encoder *encoder; |
8115 | bool has_vga = false; | |
8116 | ||
c39055b0 | 8117 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
8118 | switch (encoder->type) { |
8119 | case INTEL_OUTPUT_ANALOG: | |
8120 | has_vga = true; | |
8121 | break; | |
6847d71b PZ |
8122 | default: |
8123 | break; | |
bf8fa3d3 PZ |
8124 | } |
8125 | } | |
8126 | ||
f7be2c21 | 8127 | if (has_vga) { |
c39055b0 ACO |
8128 | lpt_bend_clkout_dp(dev_priv, 0); |
8129 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 8130 | } else { |
c39055b0 | 8131 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 8132 | } |
bf8fa3d3 PZ |
8133 | } |
8134 | ||
dde86e2d PZ |
8135 | /* |
8136 | * Initialize reference clocks when the driver loads | |
8137 | */ | |
c39055b0 | 8138 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 8139 | { |
6e266956 | 8140 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 8141 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 8142 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 8143 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
8144 | } |
8145 | ||
6ff93609 | 8146 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8147 | { |
fac5e23e | 8148 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
8149 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8150 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8151 | uint32_t val; |
8152 | ||
78114071 | 8153 | val = 0; |
c8203565 | 8154 | |
6e3c9717 | 8155 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8156 | case 18: |
dfd07d72 | 8157 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8158 | break; |
8159 | case 24: | |
dfd07d72 | 8160 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8161 | break; |
8162 | case 30: | |
dfd07d72 | 8163 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8164 | break; |
8165 | case 36: | |
dfd07d72 | 8166 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8167 | break; |
8168 | default: | |
cc769b62 PZ |
8169 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8170 | BUG(); | |
c8203565 PZ |
8171 | } |
8172 | ||
6e3c9717 | 8173 | if (intel_crtc->config->dither) |
c8203565 PZ |
8174 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8175 | ||
6e3c9717 | 8176 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8177 | val |= PIPECONF_INTERLACED_ILK; |
8178 | else | |
8179 | val |= PIPECONF_PROGRESSIVE; | |
8180 | ||
6e3c9717 | 8181 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8182 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8183 | |
c8203565 PZ |
8184 | I915_WRITE(PIPECONF(pipe), val); |
8185 | POSTING_READ(PIPECONF(pipe)); | |
8186 | } | |
8187 | ||
6ff93609 | 8188 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8189 | { |
fac5e23e | 8190 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8191 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8192 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8193 | u32 val = 0; |
ee2b0b38 | 8194 | |
391bf048 | 8195 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8196 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8197 | ||
6e3c9717 | 8198 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8199 | val |= PIPECONF_INTERLACED_ILK; |
8200 | else | |
8201 | val |= PIPECONF_PROGRESSIVE; | |
8202 | ||
702e7a56 PZ |
8203 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8204 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8205 | } |
8206 | ||
391bf048 JN |
8207 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8208 | { | |
fac5e23e | 8209 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8210 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b22ca995 | 8211 | struct intel_crtc_state *config = intel_crtc->config; |
756f85cf | 8212 | |
391bf048 JN |
8213 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8214 | u32 val = 0; | |
756f85cf | 8215 | |
6e3c9717 | 8216 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8217 | case 18: |
8218 | val |= PIPEMISC_DITHER_6_BPC; | |
8219 | break; | |
8220 | case 24: | |
8221 | val |= PIPEMISC_DITHER_8_BPC; | |
8222 | break; | |
8223 | case 30: | |
8224 | val |= PIPEMISC_DITHER_10_BPC; | |
8225 | break; | |
8226 | case 36: | |
8227 | val |= PIPEMISC_DITHER_12_BPC; | |
8228 | break; | |
8229 | default: | |
8230 | /* Case prevented by pipe_config_set_bpp. */ | |
8231 | BUG(); | |
8232 | } | |
8233 | ||
6e3c9717 | 8234 | if (intel_crtc->config->dither) |
756f85cf PZ |
8235 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8236 | ||
b22ca995 SS |
8237 | if (config->ycbcr420) { |
8238 | val |= PIPEMISC_OUTPUT_COLORSPACE_YUV | | |
8239 | PIPEMISC_YUV420_ENABLE | | |
8240 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
8241 | } | |
8242 | ||
391bf048 | 8243 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8244 | } |
ee2b0b38 PZ |
8245 | } |
8246 | ||
d4b1931c PZ |
8247 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8248 | { | |
8249 | /* | |
8250 | * Account for spread spectrum to avoid | |
8251 | * oversubscribing the link. Max center spread | |
8252 | * is 2.5%; use 5% for safety's sake. | |
8253 | */ | |
8254 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8255 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8256 | } |
8257 | ||
7429e9d4 | 8258 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8259 | { |
7429e9d4 | 8260 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8261 | } |
8262 | ||
b75ca6f6 ACO |
8263 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8264 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8265 | struct dpll *reduced_clock) |
79e53945 | 8266 | { |
de13a2e3 | 8267 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8268 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8269 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8270 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8271 | int factor; |
79e53945 | 8272 | |
c1858123 | 8273 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8274 | factor = 21; |
3d6e9ee0 | 8275 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8276 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8277 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 8278 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8279 | factor = 25; |
190f68c5 | 8280 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8281 | factor = 20; |
c1858123 | 8282 | |
b75ca6f6 ACO |
8283 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8284 | ||
190f68c5 | 8285 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8286 | fp |= FP_CB_TUNE; |
8287 | ||
8288 | if (reduced_clock) { | |
8289 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8290 | |
b75ca6f6 ACO |
8291 | if (reduced_clock->m < factor * reduced_clock->n) |
8292 | fp2 |= FP_CB_TUNE; | |
8293 | } else { | |
8294 | fp2 = fp; | |
8295 | } | |
9a7c7890 | 8296 | |
5eddb70b | 8297 | dpll = 0; |
2c07245f | 8298 | |
3d6e9ee0 | 8299 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8300 | dpll |= DPLLB_MODE_LVDS; |
8301 | else | |
8302 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8303 | |
190f68c5 | 8304 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8305 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8306 | |
3d6e9ee0 VS |
8307 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8308 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8309 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8310 | |
37a5650b | 8311 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8312 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8313 | |
7d7f8633 VS |
8314 | /* |
8315 | * The high speed IO clock is only really required for | |
8316 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
8317 | * possible to share the DPLL between CRT and HDMI. Enabling | |
8318 | * the clock needlessly does no real harm, except use up a | |
8319 | * bit of power potentially. | |
8320 | * | |
8321 | * We'll limit this to IVB with 3 pipes, since it has only two | |
8322 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
8323 | * driving PCH ports at the same time. On SNB we could do this, | |
8324 | * and potentially avoid enabling the second DPLL, but it's not | |
8325 | * clear if it''s a win or loss power wise. No point in doing | |
8326 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
8327 | */ | |
8328 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
8329 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
8330 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8331 | ||
a07d6787 | 8332 | /* compute bitmask from p1 value */ |
190f68c5 | 8333 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8334 | /* also FPA1 */ |
190f68c5 | 8335 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8336 | |
190f68c5 | 8337 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8338 | case 5: |
8339 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8340 | break; | |
8341 | case 7: | |
8342 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8343 | break; | |
8344 | case 10: | |
8345 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8346 | break; | |
8347 | case 14: | |
8348 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8349 | break; | |
79e53945 JB |
8350 | } |
8351 | ||
3d6e9ee0 VS |
8352 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8353 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8354 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8355 | else |
8356 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8357 | ||
b75ca6f6 ACO |
8358 | dpll |= DPLL_VCO_ENABLE; |
8359 | ||
8360 | crtc_state->dpll_hw_state.dpll = dpll; | |
8361 | crtc_state->dpll_hw_state.fp0 = fp; | |
8362 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8363 | } |
8364 | ||
190f68c5 ACO |
8365 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8366 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8367 | { |
997c030c | 8368 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8369 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8370 | const struct intel_limit *limit; |
997c030c | 8371 | int refclk = 120000; |
de13a2e3 | 8372 | |
dd3cd74a ACO |
8373 | memset(&crtc_state->dpll_hw_state, 0, |
8374 | sizeof(crtc_state->dpll_hw_state)); | |
8375 | ||
ded220e2 ACO |
8376 | crtc->lowfreq_avail = false; |
8377 | ||
8378 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8379 | if (!crtc_state->has_pch_encoder) | |
8380 | return 0; | |
79e53945 | 8381 | |
2d84d2b3 | 8382 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8383 | if (intel_panel_use_ssc(dev_priv)) { |
8384 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8385 | dev_priv->vbt.lvds_ssc_freq); | |
8386 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8387 | } | |
8388 | ||
8389 | if (intel_is_dual_link_lvds(dev)) { | |
8390 | if (refclk == 100000) | |
8391 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8392 | else | |
8393 | limit = &intel_limits_ironlake_dual_lvds; | |
8394 | } else { | |
8395 | if (refclk == 100000) | |
8396 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8397 | else | |
8398 | limit = &intel_limits_ironlake_single_lvds; | |
8399 | } | |
8400 | } else { | |
8401 | limit = &intel_limits_ironlake_dac; | |
8402 | } | |
8403 | ||
364ee29d | 8404 | if (!crtc_state->clock_set && |
997c030c ACO |
8405 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8406 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8407 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8408 | return -EINVAL; | |
f47709a9 | 8409 | } |
79e53945 | 8410 | |
cbaa3315 | 8411 | ironlake_compute_dpll(crtc, crtc_state, NULL); |
66e985c0 | 8412 | |
efd38b68 | 8413 | if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) { |
ded220e2 ACO |
8414 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
8415 | pipe_name(crtc->pipe)); | |
8416 | return -EINVAL; | |
3fb37703 | 8417 | } |
79e53945 | 8418 | |
c8f7a0db | 8419 | return 0; |
79e53945 JB |
8420 | } |
8421 | ||
eb14cb74 VS |
8422 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8423 | struct intel_link_m_n *m_n) | |
8424 | { | |
8425 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8426 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
8427 | enum pipe pipe = crtc->pipe; |
8428 | ||
8429 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8430 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8431 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8432 | & ~TU_SIZE_MASK; | |
8433 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8434 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8435 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8436 | } | |
8437 | ||
8438 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8439 | enum transcoder transcoder, | |
b95af8be VK |
8440 | struct intel_link_m_n *m_n, |
8441 | struct intel_link_m_n *m2_n2) | |
72419203 | 8442 | { |
6315b5d3 | 8443 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 8444 | enum pipe pipe = crtc->pipe; |
72419203 | 8445 | |
6315b5d3 | 8446 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
8447 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
8448 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8449 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8450 | & ~TU_SIZE_MASK; | |
8451 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8452 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8453 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8454 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8455 | * gen < 8) and if DRRS is supported (to make sure the | |
8456 | * registers are not unnecessarily read). | |
8457 | */ | |
6315b5d3 | 8458 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 8459 | crtc->config->has_drrs) { |
b95af8be VK |
8460 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8461 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8462 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8463 | & ~TU_SIZE_MASK; | |
8464 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8465 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8466 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8467 | } | |
eb14cb74 VS |
8468 | } else { |
8469 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8470 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8471 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8472 | & ~TU_SIZE_MASK; | |
8473 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8474 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8475 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8476 | } | |
8477 | } | |
8478 | ||
8479 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8480 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8481 | { |
681a8504 | 8482 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8483 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8484 | else | |
8485 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8486 | &pipe_config->dp_m_n, |
8487 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8488 | } |
72419203 | 8489 | |
eb14cb74 | 8490 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8491 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8492 | { |
8493 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8494 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8495 | } |
8496 | ||
bd2e244f | 8497 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8498 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8499 | { |
8500 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8501 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
8502 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8503 | uint32_t ps_ctrl = 0; | |
8504 | int id = -1; | |
8505 | int i; | |
bd2e244f | 8506 | |
a1b2278e CK |
8507 | /* find scaler attached to this pipe */ |
8508 | for (i = 0; i < crtc->num_scalers; i++) { | |
8509 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8510 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8511 | id = i; | |
8512 | pipe_config->pch_pfit.enabled = true; | |
8513 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8514 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8515 | break; | |
8516 | } | |
8517 | } | |
bd2e244f | 8518 | |
a1b2278e CK |
8519 | scaler_state->scaler_id = id; |
8520 | if (id >= 0) { | |
8521 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8522 | } else { | |
8523 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8524 | } |
8525 | } | |
8526 | ||
5724dbd1 DL |
8527 | static void |
8528 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8529 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8530 | { |
8531 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8532 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 8533 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8534 | int pipe = crtc->pipe; |
8535 | int fourcc, pixel_format; | |
6761dd31 | 8536 | unsigned int aligned_height; |
bc8d7dff | 8537 | struct drm_framebuffer *fb; |
1b842c89 | 8538 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8539 | |
d9806c9f | 8540 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8541 | if (!intel_fb) { |
bc8d7dff DL |
8542 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8543 | return; | |
8544 | } | |
8545 | ||
1b842c89 DL |
8546 | fb = &intel_fb->base; |
8547 | ||
d2e9f5fc VS |
8548 | fb->dev = dev; |
8549 | ||
bc8d7dff | 8550 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8551 | if (!(val & PLANE_CTL_ENABLE)) |
8552 | goto error; | |
8553 | ||
bc8d7dff DL |
8554 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8555 | fourcc = skl_format_to_fourcc(pixel_format, | |
8556 | val & PLANE_CTL_ORDER_RGBX, | |
8557 | val & PLANE_CTL_ALPHA_MASK); | |
2f3f4763 | 8558 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 8559 | |
40f46283 DL |
8560 | tiling = val & PLANE_CTL_TILED_MASK; |
8561 | switch (tiling) { | |
8562 | case PLANE_CTL_TILED_LINEAR: | |
2f075565 | 8563 | fb->modifier = DRM_FORMAT_MOD_LINEAR; |
40f46283 DL |
8564 | break; |
8565 | case PLANE_CTL_TILED_X: | |
8566 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 8567 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
8568 | break; |
8569 | case PLANE_CTL_TILED_Y: | |
2e2adb05 VS |
8570 | if (val & PLANE_CTL_DECOMPRESSION_ENABLE) |
8571 | fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; | |
8572 | else | |
8573 | fb->modifier = I915_FORMAT_MOD_Y_TILED; | |
40f46283 DL |
8574 | break; |
8575 | case PLANE_CTL_TILED_YF: | |
2e2adb05 VS |
8576 | if (val & PLANE_CTL_DECOMPRESSION_ENABLE) |
8577 | fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; | |
8578 | else | |
8579 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; | |
40f46283 DL |
8580 | break; |
8581 | default: | |
8582 | MISSING_CASE(tiling); | |
8583 | goto error; | |
8584 | } | |
8585 | ||
bc8d7dff DL |
8586 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8587 | plane_config->base = base; | |
8588 | ||
8589 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8590 | ||
8591 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8592 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8593 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8594 | ||
8595 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
d88c4afd | 8596 | stride_mult = intel_fb_stride_alignment(fb, 0); |
bc8d7dff DL |
8597 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8598 | ||
d88c4afd | 8599 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
bc8d7dff | 8600 | |
f37b5c2b | 8601 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8602 | |
8603 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8604 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8605 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
bc8d7dff DL |
8606 | plane_config->size); |
8607 | ||
2d14030b | 8608 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8609 | return; |
8610 | ||
8611 | error: | |
d1a3a036 | 8612 | kfree(intel_fb); |
bc8d7dff DL |
8613 | } |
8614 | ||
2fa2fe9a | 8615 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8616 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8617 | { |
8618 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8619 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8620 | uint32_t tmp; |
8621 | ||
8622 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8623 | ||
8624 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8625 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8626 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8627 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8628 | |
8629 | /* We currently do not free assignements of panel fitters on | |
8630 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8631 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 8632 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
8633 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
8634 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8635 | } | |
2fa2fe9a | 8636 | } |
79e53945 JB |
8637 | } |
8638 | ||
5724dbd1 DL |
8639 | static void |
8640 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8641 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8642 | { |
8643 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8644 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 8645 | u32 val, base, offset; |
aeee5a49 | 8646 | int pipe = crtc->pipe; |
4c6baa59 | 8647 | int fourcc, pixel_format; |
6761dd31 | 8648 | unsigned int aligned_height; |
b113d5ee | 8649 | struct drm_framebuffer *fb; |
1b842c89 | 8650 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8651 | |
42a7b088 DL |
8652 | val = I915_READ(DSPCNTR(pipe)); |
8653 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8654 | return; | |
8655 | ||
d9806c9f | 8656 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8657 | if (!intel_fb) { |
4c6baa59 JB |
8658 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8659 | return; | |
8660 | } | |
8661 | ||
1b842c89 DL |
8662 | fb = &intel_fb->base; |
8663 | ||
d2e9f5fc VS |
8664 | fb->dev = dev; |
8665 | ||
6315b5d3 | 8666 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8667 | if (val & DISPPLANE_TILED) { |
49af449b | 8668 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8669 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8670 | } |
8671 | } | |
4c6baa59 JB |
8672 | |
8673 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8674 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 8675 | fb->format = drm_format_info(fourcc); |
4c6baa59 | 8676 | |
aeee5a49 | 8677 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 8678 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 8679 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8680 | } else { |
49af449b | 8681 | if (plane_config->tiling) |
aeee5a49 | 8682 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8683 | else |
aeee5a49 | 8684 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8685 | } |
8686 | plane_config->base = base; | |
8687 | ||
8688 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8689 | fb->width = ((val >> 16) & 0xfff) + 1; |
8690 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8691 | |
8692 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8693 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8694 | |
d88c4afd | 8695 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
4c6baa59 | 8696 | |
f37b5c2b | 8697 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8698 | |
2844a921 DL |
8699 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8700 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8701 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 8702 | plane_config->size); |
b113d5ee | 8703 | |
2d14030b | 8704 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8705 | } |
8706 | ||
0e8ffe1b | 8707 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8708 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8709 | { |
8710 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8711 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8712 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8713 | uint32_t tmp; |
1729050e | 8714 | bool ret; |
0e8ffe1b | 8715 | |
1729050e ID |
8716 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8717 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
8718 | return false; |
8719 | ||
e143a21c | 8720 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8721 | pipe_config->shared_dpll = NULL; |
eccb140b | 8722 | |
1729050e | 8723 | ret = false; |
0e8ffe1b DV |
8724 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8725 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8726 | goto out; |
0e8ffe1b | 8727 | |
42571aef VS |
8728 | switch (tmp & PIPECONF_BPC_MASK) { |
8729 | case PIPECONF_6BPC: | |
8730 | pipe_config->pipe_bpp = 18; | |
8731 | break; | |
8732 | case PIPECONF_8BPC: | |
8733 | pipe_config->pipe_bpp = 24; | |
8734 | break; | |
8735 | case PIPECONF_10BPC: | |
8736 | pipe_config->pipe_bpp = 30; | |
8737 | break; | |
8738 | case PIPECONF_12BPC: | |
8739 | pipe_config->pipe_bpp = 36; | |
8740 | break; | |
8741 | default: | |
8742 | break; | |
8743 | } | |
8744 | ||
b5a9fa09 DV |
8745 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8746 | pipe_config->limited_color_range = true; | |
8747 | ||
ab9412ba | 8748 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 8749 | struct intel_shared_dpll *pll; |
8106ddbd | 8750 | enum intel_dpll_id pll_id; |
66e985c0 | 8751 | |
88adfff1 DV |
8752 | pipe_config->has_pch_encoder = true; |
8753 | ||
627eb5a3 DV |
8754 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8755 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8756 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8757 | |
8758 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8759 | |
2d1fe073 | 8760 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
8761 | /* |
8762 | * The pipe->pch transcoder and pch transcoder->pll | |
8763 | * mapping is fixed. | |
8764 | */ | |
8106ddbd | 8765 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
8766 | } else { |
8767 | tmp = I915_READ(PCH_DPLL_SEL); | |
8768 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 8769 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 8770 | else |
8106ddbd | 8771 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 8772 | } |
66e985c0 | 8773 | |
8106ddbd ACO |
8774 | pipe_config->shared_dpll = |
8775 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
8776 | pll = pipe_config->shared_dpll; | |
66e985c0 | 8777 | |
2edd6443 ACO |
8778 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8779 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8780 | |
8781 | tmp = pipe_config->dpll_hw_state.dpll; | |
8782 | pipe_config->pixel_multiplier = | |
8783 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8784 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8785 | |
8786 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8787 | } else { |
8788 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8789 | } |
8790 | ||
1bd1bd80 | 8791 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8792 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8793 | |
2fa2fe9a DV |
8794 | ironlake_get_pfit_config(crtc, pipe_config); |
8795 | ||
1729050e ID |
8796 | ret = true; |
8797 | ||
8798 | out: | |
8799 | intel_display_power_put(dev_priv, power_domain); | |
8800 | ||
8801 | return ret; | |
0e8ffe1b DV |
8802 | } |
8803 | ||
be256dc7 PZ |
8804 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8805 | { | |
91c8a326 | 8806 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 8807 | struct intel_crtc *crtc; |
be256dc7 | 8808 | |
d3fcc808 | 8809 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8810 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8811 | pipe_name(crtc->pipe)); |
8812 | ||
9c3a16c8 ID |
8813 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)), |
8814 | "Display power well on\n"); | |
e2c719b7 | 8815 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
01403de3 VS |
8816 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
8817 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 8818 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 8819 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 8820 | "CPU PWM1 enabled\n"); |
772c2a51 | 8821 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 8822 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8823 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8824 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8825 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8826 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8827 | "Utility pin enabled\n"); |
e2c719b7 | 8828 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8829 | |
9926ada1 PZ |
8830 | /* |
8831 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8832 | * interrupts remain enabled. We used to check for that, but since it's | |
8833 | * gen-specific and since we only disable LCPLL after we fully disable | |
8834 | * the interrupts, the check below should be enough. | |
8835 | */ | |
e2c719b7 | 8836 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8837 | } |
8838 | ||
9ccd5aeb PZ |
8839 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8840 | { | |
772c2a51 | 8841 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
8842 | return I915_READ(D_COMP_HSW); |
8843 | else | |
8844 | return I915_READ(D_COMP_BDW); | |
8845 | } | |
8846 | ||
3c4c9b81 PZ |
8847 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8848 | { | |
772c2a51 | 8849 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
8850 | mutex_lock(&dev_priv->rps.hw_lock); |
8851 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8852 | val)) | |
79cf219a | 8853 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8854 | mutex_unlock(&dev_priv->rps.hw_lock); |
8855 | } else { | |
9ccd5aeb PZ |
8856 | I915_WRITE(D_COMP_BDW, val); |
8857 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8858 | } |
be256dc7 PZ |
8859 | } |
8860 | ||
8861 | /* | |
8862 | * This function implements pieces of two sequences from BSpec: | |
8863 | * - Sequence for display software to disable LCPLL | |
8864 | * - Sequence for display software to allow package C8+ | |
8865 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8866 | * register. Callers should take care of disabling all the display engine | |
8867 | * functions, doing the mode unset, fixing interrupts, etc. | |
8868 | */ | |
6ff58d53 PZ |
8869 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8870 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8871 | { |
8872 | uint32_t val; | |
8873 | ||
8874 | assert_can_disable_lcpll(dev_priv); | |
8875 | ||
8876 | val = I915_READ(LCPLL_CTL); | |
8877 | ||
8878 | if (switch_to_fclk) { | |
8879 | val |= LCPLL_CD_SOURCE_FCLK; | |
8880 | I915_WRITE(LCPLL_CTL, val); | |
8881 | ||
f53dd63f ID |
8882 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
8883 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
8884 | DRM_ERROR("Switching to FCLK failed\n"); |
8885 | ||
8886 | val = I915_READ(LCPLL_CTL); | |
8887 | } | |
8888 | ||
8889 | val |= LCPLL_PLL_DISABLE; | |
8890 | I915_WRITE(LCPLL_CTL, val); | |
8891 | POSTING_READ(LCPLL_CTL); | |
8892 | ||
24d8441d | 8893 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
8894 | DRM_ERROR("LCPLL still locked\n"); |
8895 | ||
9ccd5aeb | 8896 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8897 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8898 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8899 | ndelay(100); |
8900 | ||
9ccd5aeb PZ |
8901 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8902 | 1)) | |
be256dc7 PZ |
8903 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8904 | ||
8905 | if (allow_power_down) { | |
8906 | val = I915_READ(LCPLL_CTL); | |
8907 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8908 | I915_WRITE(LCPLL_CTL, val); | |
8909 | POSTING_READ(LCPLL_CTL); | |
8910 | } | |
8911 | } | |
8912 | ||
8913 | /* | |
8914 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8915 | * source. | |
8916 | */ | |
6ff58d53 | 8917 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8918 | { |
8919 | uint32_t val; | |
8920 | ||
8921 | val = I915_READ(LCPLL_CTL); | |
8922 | ||
8923 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8924 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8925 | return; | |
8926 | ||
a8a8bd54 PZ |
8927 | /* |
8928 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8929 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8930 | */ |
59bad947 | 8931 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8932 | |
be256dc7 PZ |
8933 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8934 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8935 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8936 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8937 | } |
8938 | ||
9ccd5aeb | 8939 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8940 | val |= D_COMP_COMP_FORCE; |
8941 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8942 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8943 | |
8944 | val = I915_READ(LCPLL_CTL); | |
8945 | val &= ~LCPLL_PLL_DISABLE; | |
8946 | I915_WRITE(LCPLL_CTL, val); | |
8947 | ||
93220c08 CW |
8948 | if (intel_wait_for_register(dev_priv, |
8949 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
8950 | 5)) | |
be256dc7 PZ |
8951 | DRM_ERROR("LCPLL not locked yet\n"); |
8952 | ||
8953 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8954 | val = I915_READ(LCPLL_CTL); | |
8955 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8956 | I915_WRITE(LCPLL_CTL, val); | |
8957 | ||
f53dd63f ID |
8958 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
8959 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
8960 | DRM_ERROR("Switching back to LCPLL failed\n"); |
8961 | } | |
215733fa | 8962 | |
59bad947 | 8963 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 8964 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
8965 | } |
8966 | ||
765dab67 PZ |
8967 | /* |
8968 | * Package states C8 and deeper are really deep PC states that can only be | |
8969 | * reached when all the devices on the system allow it, so even if the graphics | |
8970 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8971 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8972 | * | |
8973 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8974 | * well is disabled and most interrupts are disabled, and these are also | |
8975 | * requirements for runtime PM. When these conditions are met, we manually do | |
8976 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8977 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8978 | * hang the machine. | |
8979 | * | |
8980 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8981 | * the state of some registers, so when we come back from PC8+ we need to | |
8982 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8983 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8984 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8985 | * because of the runtime PM support). | |
8986 | * | |
8987 | * For more, read "Display Sequences for Package C8" on the hardware | |
8988 | * documentation. | |
8989 | */ | |
a14cb6fc | 8990 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8991 | { |
c67a470b PZ |
8992 | uint32_t val; |
8993 | ||
c67a470b PZ |
8994 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8995 | ||
4f8036a2 | 8996 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8997 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8998 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8999 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9000 | } | |
9001 | ||
c39055b0 | 9002 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
9003 | hsw_disable_lcpll(dev_priv, true, true); |
9004 | } | |
9005 | ||
a14cb6fc | 9006 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9007 | { |
c67a470b PZ |
9008 | uint32_t val; |
9009 | ||
c67a470b PZ |
9010 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9011 | ||
9012 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 9013 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 9014 | |
4f8036a2 | 9015 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
9016 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9017 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9018 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9019 | } | |
c67a470b PZ |
9020 | } |
9021 | ||
190f68c5 ACO |
9022 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9023 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9024 | { |
d7edc4e5 | 9025 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
44a126ba PZ |
9026 | struct intel_encoder *encoder = |
9027 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9028 | ||
9029 | if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) { | |
9030 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9031 | pipe_name(crtc->pipe)); | |
af3997b5 | 9032 | return -EINVAL; |
44a126ba | 9033 | } |
af3997b5 | 9034 | } |
716c2e55 | 9035 | |
c7653199 | 9036 | crtc->lowfreq_avail = false; |
644cef34 | 9037 | |
c8f7a0db | 9038 | return 0; |
79e53945 JB |
9039 | } |
9040 | ||
8b0f7e06 KM |
9041 | static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9042 | enum port port, | |
9043 | struct intel_crtc_state *pipe_config) | |
9044 | { | |
9045 | enum intel_dpll_id id; | |
9046 | u32 temp; | |
9047 | ||
9048 | temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); | |
dfbd4508 | 9049 | id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); |
8b0f7e06 KM |
9050 | |
9051 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) | |
9052 | return; | |
9053 | ||
9054 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
9055 | } | |
9056 | ||
3760b59c S |
9057 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9058 | enum port port, | |
9059 | struct intel_crtc_state *pipe_config) | |
9060 | { | |
8106ddbd ACO |
9061 | enum intel_dpll_id id; |
9062 | ||
3760b59c S |
9063 | switch (port) { |
9064 | case PORT_A: | |
08250c4b | 9065 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9066 | break; |
9067 | case PORT_B: | |
08250c4b | 9068 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9069 | break; |
9070 | case PORT_C: | |
08250c4b | 9071 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9072 | break; |
9073 | default: | |
9074 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9075 | return; |
3760b59c | 9076 | } |
8106ddbd ACO |
9077 | |
9078 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9079 | } |
9080 | ||
96b7dfb7 S |
9081 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9082 | enum port port, | |
5cec258b | 9083 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9084 | { |
8106ddbd | 9085 | enum intel_dpll_id id; |
a3c988ea | 9086 | u32 temp; |
96b7dfb7 S |
9087 | |
9088 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 9089 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 9090 | |
c856052a | 9091 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 9092 | return; |
8106ddbd ACO |
9093 | |
9094 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9095 | } |
9096 | ||
7d2c8175 DL |
9097 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9098 | enum port port, | |
5cec258b | 9099 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9100 | { |
8106ddbd | 9101 | enum intel_dpll_id id; |
c856052a | 9102 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 9103 | |
c856052a | 9104 | switch (ddi_pll_sel) { |
7d2c8175 | 9105 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 9106 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9107 | break; |
9108 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9109 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9110 | break; |
00490c22 | 9111 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9112 | id = DPLL_ID_SPLL; |
79bd23da | 9113 | break; |
9d16da65 ACO |
9114 | case PORT_CLK_SEL_LCPLL_810: |
9115 | id = DPLL_ID_LCPLL_810; | |
9116 | break; | |
9117 | case PORT_CLK_SEL_LCPLL_1350: | |
9118 | id = DPLL_ID_LCPLL_1350; | |
9119 | break; | |
9120 | case PORT_CLK_SEL_LCPLL_2700: | |
9121 | id = DPLL_ID_LCPLL_2700; | |
9122 | break; | |
8106ddbd | 9123 | default: |
c856052a | 9124 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
9125 | /* fall through */ |
9126 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9127 | return; |
7d2c8175 | 9128 | } |
8106ddbd ACO |
9129 | |
9130 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9131 | } |
9132 | ||
cf30429e JN |
9133 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9134 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 9135 | u64 *power_domain_mask) |
cf30429e JN |
9136 | { |
9137 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9138 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
9139 | enum intel_display_power_domain power_domain; |
9140 | u32 tmp; | |
9141 | ||
d9a7bc67 ID |
9142 | /* |
9143 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
9144 | * transcoder handled below. | |
9145 | */ | |
cf30429e JN |
9146 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9147 | ||
9148 | /* | |
9149 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9150 | * consistency and less surprising code; it's in always on power). | |
9151 | */ | |
9152 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9153 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9154 | enum pipe trans_edp_pipe; | |
9155 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9156 | default: | |
9157 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9158 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9159 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9160 | trans_edp_pipe = PIPE_A; | |
9161 | break; | |
9162 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9163 | trans_edp_pipe = PIPE_B; | |
9164 | break; | |
9165 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9166 | trans_edp_pipe = PIPE_C; | |
9167 | break; | |
9168 | } | |
9169 | ||
9170 | if (trans_edp_pipe == crtc->pipe) | |
9171 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9172 | } | |
9173 | ||
9174 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9175 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9176 | return false; | |
d8fc70b7 | 9177 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e JN |
9178 | |
9179 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9180 | ||
9181 | return tmp & PIPECONF_ENABLE; | |
9182 | } | |
9183 | ||
4d1de975 JN |
9184 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9185 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 9186 | u64 *power_domain_mask) |
4d1de975 JN |
9187 | { |
9188 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9189 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
9190 | enum intel_display_power_domain power_domain; |
9191 | enum port port; | |
9192 | enum transcoder cpu_transcoder; | |
9193 | u32 tmp; | |
9194 | ||
4d1de975 JN |
9195 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
9196 | if (port == PORT_A) | |
9197 | cpu_transcoder = TRANSCODER_DSI_A; | |
9198 | else | |
9199 | cpu_transcoder = TRANSCODER_DSI_C; | |
9200 | ||
9201 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9202 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9203 | continue; | |
d8fc70b7 | 9204 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 9205 | |
db18b6a6 ID |
9206 | /* |
9207 | * The PLL needs to be enabled with a valid divider | |
9208 | * configuration, otherwise accessing DSI registers will hang | |
9209 | * the machine. See BSpec North Display Engine | |
9210 | * registers/MIPI[BXT]. We can break out here early, since we | |
9211 | * need the same DSI PLL to be enabled for both DSI ports. | |
9212 | */ | |
9213 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9214 | break; | |
9215 | ||
4d1de975 JN |
9216 | /* XXX: this works for video mode only */ |
9217 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9218 | if (!(tmp & DPI_ENABLE)) | |
9219 | continue; | |
9220 | ||
9221 | tmp = I915_READ(MIPI_CTRL(port)); | |
9222 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9223 | continue; | |
9224 | ||
9225 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
9226 | break; |
9227 | } | |
9228 | ||
d7edc4e5 | 9229 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
9230 | } |
9231 | ||
26804afd | 9232 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9233 | struct intel_crtc_state *pipe_config) |
26804afd | 9234 | { |
6315b5d3 | 9235 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 9236 | struct intel_shared_dpll *pll; |
26804afd DV |
9237 | enum port port; |
9238 | uint32_t tmp; | |
9239 | ||
9240 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9241 | ||
9242 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9243 | ||
8b0f7e06 KM |
9244 | if (IS_CANNONLAKE(dev_priv)) |
9245 | cannonlake_get_ddi_pll(dev_priv, port, pipe_config); | |
9246 | else if (IS_GEN9_BC(dev_priv)) | |
96b7dfb7 | 9247 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 9248 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 9249 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
9250 | else |
9251 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9252 | |
8106ddbd ACO |
9253 | pll = pipe_config->shared_dpll; |
9254 | if (pll) { | |
2edd6443 ACO |
9255 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9256 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9257 | } |
9258 | ||
26804afd DV |
9259 | /* |
9260 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9261 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9262 | * the PCH transcoder is on. | |
9263 | */ | |
6315b5d3 | 9264 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 9265 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
9266 | pipe_config->has_pch_encoder = true; |
9267 | ||
9268 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9269 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9270 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9271 | ||
9272 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9273 | } | |
9274 | } | |
9275 | ||
0e8ffe1b | 9276 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9277 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9278 | { |
6315b5d3 | 9279 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9280 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 9281 | u64 power_domain_mask; |
cf30429e | 9282 | bool active; |
0e8ffe1b | 9283 | |
e79dfb51 | 9284 | intel_crtc_init_scalers(crtc, pipe_config); |
5fb9dadf | 9285 | |
1729050e ID |
9286 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9287 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9288 | return false; |
d8fc70b7 | 9289 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 9290 | |
8106ddbd | 9291 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9292 | |
cf30429e | 9293 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9294 | |
cc3f90f0 | 9295 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
9296 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
9297 | WARN_ON(active); | |
9298 | active = true; | |
4d1de975 JN |
9299 | } |
9300 | ||
cf30429e | 9301 | if (!active) |
1729050e | 9302 | goto out; |
0e8ffe1b | 9303 | |
d7edc4e5 | 9304 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
9305 | haswell_get_ddi_port_state(crtc, pipe_config); |
9306 | intel_get_pipe_timings(crtc, pipe_config); | |
9307 | } | |
627eb5a3 | 9308 | |
bc58be60 | 9309 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9310 | |
05dc698c LL |
9311 | pipe_config->gamma_mode = |
9312 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9313 | ||
bd30ca2d | 9314 | if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { |
b22ca995 SS |
9315 | u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); |
9316 | bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV; | |
9317 | ||
bd30ca2d | 9318 | if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) { |
b22ca995 SS |
9319 | bool blend_mode_420 = tmp & |
9320 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
9321 | ||
9322 | pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE; | |
9323 | if (pipe_config->ycbcr420 != clrspace_yuv || | |
9324 | pipe_config->ycbcr420 != blend_mode_420) | |
9325 | DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp); | |
9326 | } else if (clrspace_yuv) { | |
9327 | DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n"); | |
9328 | } | |
9329 | } | |
9330 | ||
1729050e ID |
9331 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9332 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
d8fc70b7 | 9333 | power_domain_mask |= BIT_ULL(power_domain); |
6315b5d3 | 9334 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 9335 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9336 | else |
1c132b44 | 9337 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9338 | } |
88adfff1 | 9339 | |
772c2a51 | 9340 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
9341 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
9342 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9343 | |
4d1de975 JN |
9344 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9345 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9346 | pipe_config->pixel_multiplier = |
9347 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9348 | } else { | |
9349 | pipe_config->pixel_multiplier = 1; | |
9350 | } | |
6c49f241 | 9351 | |
1729050e ID |
9352 | out: |
9353 | for_each_power_domain(power_domain, power_domain_mask) | |
9354 | intel_display_power_put(dev_priv, power_domain); | |
9355 | ||
cf30429e | 9356 | return active; |
0e8ffe1b DV |
9357 | } |
9358 | ||
cd5dcbf1 | 9359 | static u32 intel_cursor_base(const struct intel_plane_state *plane_state) |
1cecc830 VS |
9360 | { |
9361 | struct drm_i915_private *dev_priv = | |
9362 | to_i915(plane_state->base.plane->dev); | |
9363 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
9364 | const struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
9365 | u32 base; | |
9366 | ||
9367 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) | |
9368 | base = obj->phys_handle->busaddr; | |
9369 | else | |
9370 | base = intel_plane_ggtt_offset(plane_state); | |
9371 | ||
1e7b4fd8 VS |
9372 | base += plane_state->main.offset; |
9373 | ||
1cecc830 VS |
9374 | /* ILK+ do this automagically */ |
9375 | if (HAS_GMCH_DISPLAY(dev_priv) && | |
a82256bc | 9376 | plane_state->base.rotation & DRM_MODE_ROTATE_180) |
1cecc830 VS |
9377 | base += (plane_state->base.crtc_h * |
9378 | plane_state->base.crtc_w - 1) * fb->format->cpp[0]; | |
9379 | ||
9380 | return base; | |
9381 | } | |
9382 | ||
ed270223 VS |
9383 | static u32 intel_cursor_position(const struct intel_plane_state *plane_state) |
9384 | { | |
9385 | int x = plane_state->base.crtc_x; | |
9386 | int y = plane_state->base.crtc_y; | |
9387 | u32 pos = 0; | |
9388 | ||
9389 | if (x < 0) { | |
9390 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9391 | x = -x; | |
9392 | } | |
9393 | pos |= x << CURSOR_X_SHIFT; | |
9394 | ||
9395 | if (y < 0) { | |
9396 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9397 | y = -y; | |
9398 | } | |
9399 | pos |= y << CURSOR_Y_SHIFT; | |
9400 | ||
9401 | return pos; | |
9402 | } | |
9403 | ||
3637ecf0 VS |
9404 | static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) |
9405 | { | |
9406 | const struct drm_mode_config *config = | |
9407 | &plane_state->base.plane->dev->mode_config; | |
9408 | int width = plane_state->base.crtc_w; | |
9409 | int height = plane_state->base.crtc_h; | |
9410 | ||
9411 | return width > 0 && width <= config->cursor_width && | |
9412 | height > 0 && height <= config->cursor_height; | |
9413 | } | |
9414 | ||
659056f2 VS |
9415 | static int intel_check_cursor(struct intel_crtc_state *crtc_state, |
9416 | struct intel_plane_state *plane_state) | |
9417 | { | |
9418 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
1e7b4fd8 VS |
9419 | int src_x, src_y; |
9420 | u32 offset; | |
659056f2 VS |
9421 | int ret; |
9422 | ||
9423 | ret = drm_plane_helper_check_state(&plane_state->base, | |
9424 | &plane_state->clip, | |
9425 | DRM_PLANE_HELPER_NO_SCALING, | |
9426 | DRM_PLANE_HELPER_NO_SCALING, | |
9427 | true, true); | |
9428 | if (ret) | |
9429 | return ret; | |
9430 | ||
9431 | if (!fb) | |
9432 | return 0; | |
9433 | ||
9434 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { | |
9435 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); | |
9436 | return -EINVAL; | |
9437 | } | |
9438 | ||
1e7b4fd8 VS |
9439 | src_x = plane_state->base.src_x >> 16; |
9440 | src_y = plane_state->base.src_y >> 16; | |
9441 | ||
9442 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); | |
9443 | offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0); | |
9444 | ||
9445 | if (src_x != 0 || src_y != 0) { | |
9446 | DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n"); | |
9447 | return -EINVAL; | |
9448 | } | |
9449 | ||
9450 | plane_state->main.offset = offset; | |
9451 | ||
659056f2 VS |
9452 | return 0; |
9453 | } | |
9454 | ||
292889e1 VS |
9455 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9456 | const struct intel_plane_state *plane_state) | |
9457 | { | |
1e1bb871 | 9458 | const struct drm_framebuffer *fb = plane_state->base.fb; |
292889e1 | 9459 | |
292889e1 VS |
9460 | return CURSOR_ENABLE | |
9461 | CURSOR_GAMMA_ENABLE | | |
9462 | CURSOR_FORMAT_ARGB | | |
1e1bb871 | 9463 | CURSOR_STRIDE(fb->pitches[0]); |
292889e1 VS |
9464 | } |
9465 | ||
659056f2 VS |
9466 | static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) |
9467 | { | |
659056f2 | 9468 | int width = plane_state->base.crtc_w; |
659056f2 VS |
9469 | |
9470 | /* | |
9471 | * 845g/865g are only limited by the width of their cursors, | |
9472 | * the height is arbitrary up to the precision of the register. | |
9473 | */ | |
3637ecf0 | 9474 | return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); |
659056f2 VS |
9475 | } |
9476 | ||
9477 | static int i845_check_cursor(struct intel_plane *plane, | |
9478 | struct intel_crtc_state *crtc_state, | |
9479 | struct intel_plane_state *plane_state) | |
9480 | { | |
9481 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 VS |
9482 | int ret; |
9483 | ||
9484 | ret = intel_check_cursor(crtc_state, plane_state); | |
9485 | if (ret) | |
9486 | return ret; | |
9487 | ||
9488 | /* if we want to turn off the cursor ignore width and height */ | |
1e1bb871 | 9489 | if (!fb) |
659056f2 VS |
9490 | return 0; |
9491 | ||
9492 | /* Check for which cursor types we support */ | |
9493 | if (!i845_cursor_size_ok(plane_state)) { | |
9494 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9495 | plane_state->base.crtc_w, | |
9496 | plane_state->base.crtc_h); | |
9497 | return -EINVAL; | |
9498 | } | |
9499 | ||
1e1bb871 | 9500 | switch (fb->pitches[0]) { |
292889e1 VS |
9501 | case 256: |
9502 | case 512: | |
9503 | case 1024: | |
9504 | case 2048: | |
9505 | break; | |
1e1bb871 VS |
9506 | default: |
9507 | DRM_DEBUG_KMS("Invalid cursor stride (%u)\n", | |
9508 | fb->pitches[0]); | |
9509 | return -EINVAL; | |
292889e1 VS |
9510 | } |
9511 | ||
659056f2 VS |
9512 | plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); |
9513 | ||
9514 | return 0; | |
292889e1 VS |
9515 | } |
9516 | ||
b2d03b0d VS |
9517 | static void i845_update_cursor(struct intel_plane *plane, |
9518 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9519 | const struct intel_plane_state *plane_state) |
560b85bb | 9520 | { |
cd5dcbf1 | 9521 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
b2d03b0d VS |
9522 | u32 cntl = 0, base = 0, pos = 0, size = 0; |
9523 | unsigned long irqflags; | |
560b85bb | 9524 | |
936e71e3 | 9525 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
9526 | unsigned int width = plane_state->base.crtc_w; |
9527 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 | 9528 | |
a0864d59 | 9529 | cntl = plane_state->ctl; |
dc41c154 | 9530 | size = (height << 12) | width; |
560b85bb | 9531 | |
b2d03b0d VS |
9532 | base = intel_cursor_base(plane_state); |
9533 | pos = intel_cursor_position(plane_state); | |
4b0e333e | 9534 | } |
560b85bb | 9535 | |
b2d03b0d | 9536 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
4726e0b0 | 9537 | |
e11ffddb VS |
9538 | /* On these chipsets we can only modify the base/size/stride |
9539 | * whilst the cursor is disabled. | |
9540 | */ | |
9541 | if (plane->cursor.base != base || | |
9542 | plane->cursor.size != size || | |
9543 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9544 | I915_WRITE_FW(CURCNTR(PIPE_A), 0); |
dd584fc0 | 9545 | I915_WRITE_FW(CURBASE(PIPE_A), base); |
dd584fc0 | 9546 | I915_WRITE_FW(CURSIZE, size); |
b2d03b0d | 9547 | I915_WRITE_FW(CURPOS(PIPE_A), pos); |
dd584fc0 | 9548 | I915_WRITE_FW(CURCNTR(PIPE_A), cntl); |
75343a44 | 9549 | |
e11ffddb VS |
9550 | plane->cursor.base = base; |
9551 | plane->cursor.size = size; | |
9552 | plane->cursor.cntl = cntl; | |
9553 | } else { | |
9554 | I915_WRITE_FW(CURPOS(PIPE_A), pos); | |
560b85bb | 9555 | } |
e11ffddb | 9556 | |
75343a44 | 9557 | POSTING_READ_FW(CURCNTR(PIPE_A)); |
b2d03b0d VS |
9558 | |
9559 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
9560 | } | |
9561 | ||
9562 | static void i845_disable_cursor(struct intel_plane *plane, | |
9563 | struct intel_crtc *crtc) | |
9564 | { | |
9565 | i845_update_cursor(plane, NULL, NULL); | |
560b85bb CW |
9566 | } |
9567 | ||
292889e1 VS |
9568 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9569 | const struct intel_plane_state *plane_state) | |
9570 | { | |
9571 | struct drm_i915_private *dev_priv = | |
9572 | to_i915(plane_state->base.plane->dev); | |
9573 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
292889e1 VS |
9574 | u32 cntl; |
9575 | ||
9576 | cntl = MCURSOR_GAMMA_ENABLE; | |
9577 | ||
9578 | if (HAS_DDI(dev_priv)) | |
9579 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
9580 | ||
d509e28b | 9581 | cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); |
292889e1 VS |
9582 | |
9583 | switch (plane_state->base.crtc_w) { | |
9584 | case 64: | |
9585 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9586 | break; | |
9587 | case 128: | |
9588 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9589 | break; | |
9590 | case 256: | |
9591 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9592 | break; | |
9593 | default: | |
9594 | MISSING_CASE(plane_state->base.crtc_w); | |
9595 | return 0; | |
9596 | } | |
9597 | ||
c2c446ad | 9598 | if (plane_state->base.rotation & DRM_MODE_ROTATE_180) |
292889e1 VS |
9599 | cntl |= CURSOR_ROTATE_180; |
9600 | ||
9601 | return cntl; | |
9602 | } | |
9603 | ||
659056f2 | 9604 | static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) |
65a21cd6 | 9605 | { |
024faac7 VS |
9606 | struct drm_i915_private *dev_priv = |
9607 | to_i915(plane_state->base.plane->dev); | |
659056f2 VS |
9608 | int width = plane_state->base.crtc_w; |
9609 | int height = plane_state->base.crtc_h; | |
4b0e333e | 9610 | |
3637ecf0 | 9611 | if (!intel_cursor_size_ok(plane_state)) |
659056f2 | 9612 | return false; |
4398ad45 | 9613 | |
024faac7 VS |
9614 | /* Cursor width is limited to a few power-of-two sizes */ |
9615 | switch (width) { | |
659056f2 VS |
9616 | case 256: |
9617 | case 128: | |
659056f2 VS |
9618 | case 64: |
9619 | break; | |
9620 | default: | |
9621 | return false; | |
65a21cd6 | 9622 | } |
4b0e333e | 9623 | |
024faac7 VS |
9624 | /* |
9625 | * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor | |
9626 | * height from 8 lines up to the cursor width, when the | |
9627 | * cursor is not rotated. Everything else requires square | |
9628 | * cursors. | |
9629 | */ | |
9630 | if (HAS_CUR_FBC(dev_priv) && | |
a82256bc | 9631 | plane_state->base.rotation & DRM_MODE_ROTATE_0) { |
024faac7 VS |
9632 | if (height < 8 || height > width) |
9633 | return false; | |
9634 | } else { | |
9635 | if (height != width) | |
9636 | return false; | |
9637 | } | |
99d1f387 | 9638 | |
659056f2 | 9639 | return true; |
65a21cd6 JB |
9640 | } |
9641 | ||
659056f2 VS |
9642 | static int i9xx_check_cursor(struct intel_plane *plane, |
9643 | struct intel_crtc_state *crtc_state, | |
9644 | struct intel_plane_state *plane_state) | |
cda4b7d3 | 9645 | { |
659056f2 VS |
9646 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9647 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 | 9648 | enum pipe pipe = plane->pipe; |
659056f2 | 9649 | int ret; |
cda4b7d3 | 9650 | |
659056f2 VS |
9651 | ret = intel_check_cursor(crtc_state, plane_state); |
9652 | if (ret) | |
9653 | return ret; | |
cda4b7d3 | 9654 | |
659056f2 | 9655 | /* if we want to turn off the cursor ignore width and height */ |
1e1bb871 | 9656 | if (!fb) |
659056f2 | 9657 | return 0; |
55a08b3f | 9658 | |
659056f2 VS |
9659 | /* Check for which cursor types we support */ |
9660 | if (!i9xx_cursor_size_ok(plane_state)) { | |
9661 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9662 | plane_state->base.crtc_w, | |
9663 | plane_state->base.crtc_h); | |
9664 | return -EINVAL; | |
cda4b7d3 | 9665 | } |
cda4b7d3 | 9666 | |
1e1bb871 VS |
9667 | if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) { |
9668 | DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n", | |
9669 | fb->pitches[0], plane_state->base.crtc_w); | |
9670 | return -EINVAL; | |
659056f2 | 9671 | } |
dd584fc0 | 9672 | |
659056f2 VS |
9673 | /* |
9674 | * There's something wrong with the cursor on CHV pipe C. | |
9675 | * If it straddles the left edge of the screen then | |
9676 | * moving it away from the edge or disabling it often | |
9677 | * results in a pipe underrun, and often that can lead to | |
9678 | * dead pipe (constant underrun reported, and it scans | |
9679 | * out just a solid color). To recover from that, the | |
9680 | * display power well must be turned off and on again. | |
9681 | * Refuse the put the cursor into that compromised position. | |
9682 | */ | |
9683 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && | |
9684 | plane_state->base.visible && plane_state->base.crtc_x < 0) { | |
9685 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
9686 | return -EINVAL; | |
9687 | } | |
5efb3e28 | 9688 | |
659056f2 | 9689 | plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); |
dd584fc0 | 9690 | |
659056f2 | 9691 | return 0; |
cda4b7d3 CW |
9692 | } |
9693 | ||
b2d03b0d VS |
9694 | static void i9xx_update_cursor(struct intel_plane *plane, |
9695 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9696 | const struct intel_plane_state *plane_state) |
dc41c154 | 9697 | { |
cd5dcbf1 VS |
9698 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9699 | enum pipe pipe = plane->pipe; | |
024faac7 | 9700 | u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; |
b2d03b0d | 9701 | unsigned long irqflags; |
dc41c154 | 9702 | |
b2d03b0d | 9703 | if (plane_state && plane_state->base.visible) { |
a0864d59 | 9704 | cntl = plane_state->ctl; |
dc41c154 | 9705 | |
024faac7 VS |
9706 | if (plane_state->base.crtc_h != plane_state->base.crtc_w) |
9707 | fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1); | |
dc41c154 | 9708 | |
b2d03b0d VS |
9709 | base = intel_cursor_base(plane_state); |
9710 | pos = intel_cursor_position(plane_state); | |
9711 | } | |
9712 | ||
9713 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
9714 | ||
e11ffddb VS |
9715 | /* |
9716 | * On some platforms writing CURCNTR first will also | |
9717 | * cause CURPOS to be armed by the CURBASE write. | |
9718 | * Without the CURCNTR write the CURPOS write would | |
8753d2bc VS |
9719 | * arm itself. Thus we always start the full update |
9720 | * with a CURCNTR write. | |
9721 | * | |
9722 | * On other platforms CURPOS always requires the | |
9723 | * CURBASE write to arm the update. Additonally | |
9724 | * a write to any of the cursor register will cancel | |
9725 | * an already armed cursor update. Thus leaving out | |
9726 | * the CURBASE write after CURPOS could lead to a | |
9727 | * cursor that doesn't appear to move, or even change | |
9728 | * shape. Thus we always write CURBASE. | |
e11ffddb VS |
9729 | * |
9730 | * CURCNTR and CUR_FBC_CTL are always | |
9731 | * armed by the CURBASE write only. | |
9732 | */ | |
9733 | if (plane->cursor.base != base || | |
9734 | plane->cursor.size != fbc_ctl || | |
9735 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9736 | I915_WRITE_FW(CURCNTR(pipe), cntl); |
e11ffddb VS |
9737 | if (HAS_CUR_FBC(dev_priv)) |
9738 | I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); | |
b2d03b0d | 9739 | I915_WRITE_FW(CURPOS(pipe), pos); |
75343a44 VS |
9740 | I915_WRITE_FW(CURBASE(pipe), base); |
9741 | ||
e11ffddb VS |
9742 | plane->cursor.base = base; |
9743 | plane->cursor.size = fbc_ctl; | |
9744 | plane->cursor.cntl = cntl; | |
dc41c154 | 9745 | } else { |
e11ffddb | 9746 | I915_WRITE_FW(CURPOS(pipe), pos); |
8753d2bc | 9747 | I915_WRITE_FW(CURBASE(pipe), base); |
dc41c154 VS |
9748 | } |
9749 | ||
dd584fc0 | 9750 | POSTING_READ_FW(CURBASE(pipe)); |
99d1f387 | 9751 | |
b2d03b0d | 9752 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
65a21cd6 JB |
9753 | } |
9754 | ||
b2d03b0d VS |
9755 | static void i9xx_disable_cursor(struct intel_plane *plane, |
9756 | struct intel_crtc *crtc) | |
cda4b7d3 | 9757 | { |
b2d03b0d | 9758 | i9xx_update_cursor(plane, NULL, NULL); |
dc41c154 VS |
9759 | } |
9760 | ||
dc41c154 | 9761 | |
79e53945 | 9762 | /* VESA 640x480x72Hz mode to set on the pipe */ |
bacdcd55 | 9763 | static const struct drm_display_mode load_detect_mode = { |
79e53945 JB |
9764 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
9765 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9766 | }; | |
9767 | ||
a8bb6818 | 9768 | struct drm_framebuffer * |
24dbf51a CW |
9769 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
9770 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
9771 | { |
9772 | struct intel_framebuffer *intel_fb; | |
9773 | int ret; | |
9774 | ||
9775 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 9776 | if (!intel_fb) |
d2dff872 | 9777 | return ERR_PTR(-ENOMEM); |
d2dff872 | 9778 | |
24dbf51a | 9779 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
9780 | if (ret) |
9781 | goto err; | |
d2dff872 CW |
9782 | |
9783 | return &intel_fb->base; | |
dcb1394e | 9784 | |
dd4916c5 | 9785 | err: |
dd4916c5 | 9786 | kfree(intel_fb); |
dd4916c5 | 9787 | return ERR_PTR(ret); |
d2dff872 CW |
9788 | } |
9789 | ||
9790 | static u32 | |
9791 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9792 | { | |
9793 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9794 | return ALIGN(pitch, 64); | |
9795 | } | |
9796 | ||
9797 | static u32 | |
bacdcd55 | 9798 | intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp) |
d2dff872 CW |
9799 | { |
9800 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9801 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9802 | } |
9803 | ||
9804 | static struct drm_framebuffer * | |
9805 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
bacdcd55 | 9806 | const struct drm_display_mode *mode, |
d2dff872 CW |
9807 | int depth, int bpp) |
9808 | { | |
dcb1394e | 9809 | struct drm_framebuffer *fb; |
d2dff872 | 9810 | struct drm_i915_gem_object *obj; |
0fed39bd | 9811 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 9812 | |
12d79d78 | 9813 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 9814 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
9815 | if (IS_ERR(obj)) |
9816 | return ERR_CAST(obj); | |
d2dff872 CW |
9817 | |
9818 | mode_cmd.width = mode->hdisplay; | |
9819 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9820 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9821 | bpp); | |
5ca0c34a | 9822 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 9823 | |
24dbf51a | 9824 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 9825 | if (IS_ERR(fb)) |
f0cd5182 | 9826 | i915_gem_object_put(obj); |
dcb1394e LW |
9827 | |
9828 | return fb; | |
d2dff872 CW |
9829 | } |
9830 | ||
9831 | static struct drm_framebuffer * | |
9832 | mode_fits_in_fbdev(struct drm_device *dev, | |
bacdcd55 | 9833 | const struct drm_display_mode *mode) |
d2dff872 | 9834 | { |
0695726e | 9835 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 9836 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
9837 | struct drm_i915_gem_object *obj; |
9838 | struct drm_framebuffer *fb; | |
9839 | ||
4c0e5528 | 9840 | if (!dev_priv->fbdev) |
d2dff872 CW |
9841 | return NULL; |
9842 | ||
4c0e5528 | 9843 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9844 | return NULL; |
9845 | ||
4c0e5528 DV |
9846 | obj = dev_priv->fbdev->fb->obj; |
9847 | BUG_ON(!obj); | |
9848 | ||
8bcd4553 | 9849 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 | 9850 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
272725c7 | 9851 | fb->format->cpp[0] * 8)) |
d2dff872 CW |
9852 | return NULL; |
9853 | ||
01f2c773 | 9854 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9855 | return NULL; |
9856 | ||
edde3617 | 9857 | drm_framebuffer_reference(fb); |
d2dff872 | 9858 | return fb; |
4520f53a DV |
9859 | #else |
9860 | return NULL; | |
9861 | #endif | |
d2dff872 CW |
9862 | } |
9863 | ||
d3a40d1b ACO |
9864 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9865 | struct drm_crtc *crtc, | |
bacdcd55 | 9866 | const struct drm_display_mode *mode, |
d3a40d1b ACO |
9867 | struct drm_framebuffer *fb, |
9868 | int x, int y) | |
9869 | { | |
9870 | struct drm_plane_state *plane_state; | |
9871 | int hdisplay, vdisplay; | |
9872 | int ret; | |
9873 | ||
9874 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9875 | if (IS_ERR(plane_state)) | |
9876 | return PTR_ERR(plane_state); | |
9877 | ||
9878 | if (mode) | |
196cd5d3 | 9879 | drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay); |
d3a40d1b ACO |
9880 | else |
9881 | hdisplay = vdisplay = 0; | |
9882 | ||
9883 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9884 | if (ret) | |
9885 | return ret; | |
9886 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9887 | plane_state->crtc_x = 0; | |
9888 | plane_state->crtc_y = 0; | |
9889 | plane_state->crtc_w = hdisplay; | |
9890 | plane_state->crtc_h = vdisplay; | |
9891 | plane_state->src_x = x << 16; | |
9892 | plane_state->src_y = y << 16; | |
9893 | plane_state->src_w = hdisplay << 16; | |
9894 | plane_state->src_h = vdisplay << 16; | |
9895 | ||
9896 | return 0; | |
9897 | } | |
9898 | ||
6c5ed5ae | 9899 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
bacdcd55 | 9900 | const struct drm_display_mode *mode, |
6c5ed5ae ML |
9901 | struct intel_load_detect_pipe *old, |
9902 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9903 | { |
9904 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9905 | struct intel_encoder *intel_encoder = |
9906 | intel_attached_encoder(connector); | |
79e53945 | 9907 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9908 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9909 | struct drm_crtc *crtc = NULL; |
9910 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 9911 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 9912 | struct drm_framebuffer *fb; |
51fd371b | 9913 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 9914 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 9915 | struct drm_connector_state *connector_state; |
4be07317 | 9916 | struct intel_crtc_state *crtc_state; |
51fd371b | 9917 | int ret, i = -1; |
79e53945 | 9918 | |
d2dff872 | 9919 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9920 | connector->base.id, connector->name, |
8e329a03 | 9921 | encoder->base.id, encoder->name); |
d2dff872 | 9922 | |
edde3617 ML |
9923 | old->restore_state = NULL; |
9924 | ||
6c5ed5ae | 9925 | WARN_ON(!drm_modeset_is_locked(&config->connection_mutex)); |
6e9f798d | 9926 | |
79e53945 JB |
9927 | /* |
9928 | * Algorithm gets a little messy: | |
7a5e4805 | 9929 | * |
79e53945 JB |
9930 | * - if the connector already has an assigned crtc, use it (but make |
9931 | * sure it's on first) | |
7a5e4805 | 9932 | * |
79e53945 JB |
9933 | * - try to find the first unused crtc that can drive this connector, |
9934 | * and use that if we find one | |
79e53945 JB |
9935 | */ |
9936 | ||
9937 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
9938 | if (connector->state->crtc) { |
9939 | crtc = connector->state->crtc; | |
8261b191 | 9940 | |
51fd371b | 9941 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 9942 | if (ret) |
ad3c558f | 9943 | goto fail; |
8261b191 CW |
9944 | |
9945 | /* Make sure the crtc and connector are running */ | |
edde3617 | 9946 | goto found; |
79e53945 JB |
9947 | } |
9948 | ||
9949 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9950 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9951 | i++; |
9952 | if (!(encoder->possible_crtcs & (1 << i))) | |
9953 | continue; | |
edde3617 ML |
9954 | |
9955 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
9956 | if (ret) | |
9957 | goto fail; | |
9958 | ||
9959 | if (possible_crtc->state->enable) { | |
9960 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 9961 | continue; |
edde3617 | 9962 | } |
a459249c VS |
9963 | |
9964 | crtc = possible_crtc; | |
9965 | break; | |
79e53945 JB |
9966 | } |
9967 | ||
9968 | /* | |
9969 | * If we didn't find an unused CRTC, don't use any. | |
9970 | */ | |
9971 | if (!crtc) { | |
7173188d | 9972 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
f4bf77b4 | 9973 | ret = -ENODEV; |
ad3c558f | 9974 | goto fail; |
79e53945 JB |
9975 | } |
9976 | ||
edde3617 ML |
9977 | found: |
9978 | intel_crtc = to_intel_crtc(crtc); | |
9979 | ||
4d02e2de DV |
9980 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
9981 | if (ret) | |
ad3c558f | 9982 | goto fail; |
79e53945 | 9983 | |
83a57153 | 9984 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
9985 | restore_state = drm_atomic_state_alloc(dev); |
9986 | if (!state || !restore_state) { | |
9987 | ret = -ENOMEM; | |
9988 | goto fail; | |
9989 | } | |
83a57153 ACO |
9990 | |
9991 | state->acquire_ctx = ctx; | |
edde3617 | 9992 | restore_state->acquire_ctx = ctx; |
83a57153 | 9993 | |
944b0c76 ACO |
9994 | connector_state = drm_atomic_get_connector_state(state, connector); |
9995 | if (IS_ERR(connector_state)) { | |
9996 | ret = PTR_ERR(connector_state); | |
9997 | goto fail; | |
9998 | } | |
9999 | ||
edde3617 ML |
10000 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10001 | if (ret) | |
10002 | goto fail; | |
944b0c76 | 10003 | |
4be07317 ACO |
10004 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10005 | if (IS_ERR(crtc_state)) { | |
10006 | ret = PTR_ERR(crtc_state); | |
10007 | goto fail; | |
10008 | } | |
10009 | ||
49d6fa21 | 10010 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10011 | |
6492711d CW |
10012 | if (!mode) |
10013 | mode = &load_detect_mode; | |
79e53945 | 10014 | |
d2dff872 CW |
10015 | /* We need a framebuffer large enough to accommodate all accesses |
10016 | * that the plane may generate whilst we perform load detection. | |
10017 | * We can not rely on the fbcon either being present (we get called | |
10018 | * during its initialisation to detect all boot displays, or it may | |
10019 | * not even exist) or that it is large enough to satisfy the | |
10020 | * requested mode. | |
10021 | */ | |
94352cf9 DV |
10022 | fb = mode_fits_in_fbdev(dev, mode); |
10023 | if (fb == NULL) { | |
d2dff872 | 10024 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10025 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10026 | } else |
10027 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10028 | if (IS_ERR(fb)) { |
d2dff872 | 10029 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
f4bf77b4 | 10030 | ret = PTR_ERR(fb); |
412b61d8 | 10031 | goto fail; |
79e53945 | 10032 | } |
79e53945 | 10033 | |
d3a40d1b ACO |
10034 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10035 | if (ret) | |
10036 | goto fail; | |
10037 | ||
edde3617 ML |
10038 | drm_framebuffer_unreference(fb); |
10039 | ||
10040 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10041 | if (ret) | |
10042 | goto fail; | |
10043 | ||
10044 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10045 | if (!ret) | |
10046 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10047 | if (!ret) | |
10048 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10049 | if (ret) { | |
10050 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10051 | goto fail; | |
10052 | } | |
8c7b5ccb | 10053 | |
3ba86073 ML |
10054 | ret = drm_atomic_commit(state); |
10055 | if (ret) { | |
6492711d | 10056 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10057 | goto fail; |
79e53945 | 10058 | } |
edde3617 ML |
10059 | |
10060 | old->restore_state = restore_state; | |
7abbd11f | 10061 | drm_atomic_state_put(state); |
7173188d | 10062 | |
79e53945 | 10063 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 10064 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 10065 | return true; |
412b61d8 | 10066 | |
ad3c558f | 10067 | fail: |
7fb71c8f CW |
10068 | if (state) { |
10069 | drm_atomic_state_put(state); | |
10070 | state = NULL; | |
10071 | } | |
10072 | if (restore_state) { | |
10073 | drm_atomic_state_put(restore_state); | |
10074 | restore_state = NULL; | |
10075 | } | |
83a57153 | 10076 | |
6c5ed5ae ML |
10077 | if (ret == -EDEADLK) |
10078 | return ret; | |
51fd371b | 10079 | |
412b61d8 | 10080 | return false; |
79e53945 JB |
10081 | } |
10082 | ||
d2434ab7 | 10083 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10084 | struct intel_load_detect_pipe *old, |
10085 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10086 | { |
d2434ab7 DV |
10087 | struct intel_encoder *intel_encoder = |
10088 | intel_attached_encoder(connector); | |
4ef69c7a | 10089 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10090 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10091 | int ret; |
79e53945 | 10092 | |
d2dff872 | 10093 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10094 | connector->base.id, connector->name, |
8e329a03 | 10095 | encoder->base.id, encoder->name); |
d2dff872 | 10096 | |
edde3617 | 10097 | if (!state) |
0622a53c | 10098 | return; |
79e53945 | 10099 | |
581e49fe | 10100 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
0853695c | 10101 | if (ret) |
edde3617 | 10102 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 10103 | drm_atomic_state_put(state); |
79e53945 JB |
10104 | } |
10105 | ||
da4a1efa | 10106 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10107 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 10108 | { |
fac5e23e | 10109 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
10110 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
10111 | ||
10112 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10113 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 10114 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 10115 | return 120000; |
5db94019 | 10116 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
10117 | return 96000; |
10118 | else | |
10119 | return 48000; | |
10120 | } | |
10121 | ||
79e53945 | 10122 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10123 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10124 | struct intel_crtc_state *pipe_config) |
79e53945 | 10125 | { |
f1f644dc | 10126 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 10127 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 10128 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10129 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10130 | u32 fp; |
9e2c8475 | 10131 | struct dpll clock; |
dccbea3b | 10132 | int port_clock; |
da4a1efa | 10133 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10134 | |
10135 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10136 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10137 | else |
293623f7 | 10138 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10139 | |
10140 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 10141 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
10142 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
10143 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10144 | } else { |
10145 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10146 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10147 | } | |
10148 | ||
5db94019 | 10149 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 10150 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
10151 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
10152 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10153 | else |
10154 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10155 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10156 | ||
10157 | switch (dpll & DPLL_MODE_MASK) { | |
10158 | case DPLLB_MODE_DAC_SERIAL: | |
10159 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10160 | 5 : 10; | |
10161 | break; | |
10162 | case DPLLB_MODE_LVDS: | |
10163 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10164 | 7 : 14; | |
10165 | break; | |
10166 | default: | |
28c97730 | 10167 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10168 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10169 | return; |
79e53945 JB |
10170 | } |
10171 | ||
9b1e14f4 | 10172 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 10173 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10174 | else |
dccbea3b | 10175 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10176 | } else { |
50a0bc90 | 10177 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10178 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10179 | |
10180 | if (is_lvds) { | |
10181 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10182 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10183 | |
10184 | if (lvds & LVDS_CLKB_POWER_UP) | |
10185 | clock.p2 = 7; | |
10186 | else | |
10187 | clock.p2 = 14; | |
79e53945 JB |
10188 | } else { |
10189 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10190 | clock.p1 = 2; | |
10191 | else { | |
10192 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10193 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10194 | } | |
10195 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10196 | clock.p2 = 4; | |
10197 | else | |
10198 | clock.p2 = 2; | |
79e53945 | 10199 | } |
da4a1efa | 10200 | |
dccbea3b | 10201 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10202 | } |
10203 | ||
18442d08 VS |
10204 | /* |
10205 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10206 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10207 | * encoder's get_config() function. |
10208 | */ | |
dccbea3b | 10209 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10210 | } |
10211 | ||
6878da05 VS |
10212 | int intel_dotclock_calculate(int link_freq, |
10213 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10214 | { |
f1f644dc JB |
10215 | /* |
10216 | * The calculation for the data clock is: | |
1041a02f | 10217 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10218 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10219 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10220 | * |
10221 | * and the link clock is simpler: | |
1041a02f | 10222 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10223 | */ |
10224 | ||
6878da05 VS |
10225 | if (!m_n->link_n) |
10226 | return 0; | |
f1f644dc | 10227 | |
3123698f | 10228 | return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); |
6878da05 | 10229 | } |
f1f644dc | 10230 | |
18442d08 | 10231 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10232 | struct intel_crtc_state *pipe_config) |
6878da05 | 10233 | { |
e3b247da | 10234 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10235 | |
18442d08 VS |
10236 | /* read out port_clock from the DPLL */ |
10237 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10238 | |
f1f644dc | 10239 | /* |
e3b247da VS |
10240 | * In case there is an active pipe without active ports, |
10241 | * we may need some idea for the dotclock anyway. | |
10242 | * Calculate one based on the FDI configuration. | |
79e53945 | 10243 | */ |
2d112de7 | 10244 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10245 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10246 | &pipe_config->fdi_m_n); |
79e53945 JB |
10247 | } |
10248 | ||
10249 | /** Returns the currently programmed mode of the given pipe. */ | |
10250 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10251 | struct drm_crtc *crtc) | |
10252 | { | |
fac5e23e | 10253 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 10254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10255 | struct drm_display_mode *mode; |
3f36b937 | 10256 | struct intel_crtc_state *pipe_config; |
293623f7 | 10257 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10258 | |
10259 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10260 | if (!mode) | |
10261 | return NULL; | |
10262 | ||
3f36b937 TU |
10263 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10264 | if (!pipe_config) { | |
10265 | kfree(mode); | |
10266 | return NULL; | |
10267 | } | |
10268 | ||
f1f644dc JB |
10269 | /* |
10270 | * Construct a pipe_config sufficient for getting the clock info | |
10271 | * back out of crtc_clock_get. | |
10272 | * | |
10273 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10274 | * to use a real value here instead. | |
10275 | */ | |
3f36b937 TU |
10276 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10277 | pipe_config->pixel_multiplier = 1; | |
10278 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10279 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10280 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10281 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10282 | ||
d0d37254 VS |
10283 | pipe_config->base.adjusted_mode.crtc_clock = |
10284 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
e30a154b | 10285 | |
d0d37254 | 10286 | intel_get_pipe_timings(intel_crtc, pipe_config); |
79e53945 | 10287 | |
d0d37254 | 10288 | intel_mode_from_pipe_config(mode, pipe_config); |
79e53945 | 10289 | |
3f36b937 TU |
10290 | kfree(pipe_config); |
10291 | ||
79e53945 JB |
10292 | return mode; |
10293 | } | |
10294 | ||
10295 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
10296 | { | |
10297 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10298 | ||
10299 | drm_crtc_cleanup(crtc); | |
10300 | kfree(intel_crtc); | |
10301 | } | |
10302 | ||
5a21b665 DV |
10303 | /** |
10304 | * intel_wm_need_update - Check whether watermarks need updating | |
10305 | * @plane: drm plane | |
10306 | * @state: new plane state | |
10307 | * | |
10308 | * Check current plane state versus the new one to determine whether | |
10309 | * watermarks need to be recalculated. | |
10310 | * | |
10311 | * Returns true or false. | |
10312 | */ | |
10313 | static bool intel_wm_need_update(struct drm_plane *plane, | |
10314 | struct drm_plane_state *state) | |
10315 | { | |
10316 | struct intel_plane_state *new = to_intel_plane_state(state); | |
10317 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
10318 | ||
10319 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 10320 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
10321 | return true; |
10322 | ||
10323 | if (!cur->base.fb || !new->base.fb) | |
10324 | return false; | |
10325 | ||
bae781b2 | 10326 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 10327 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
10328 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
10329 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
10330 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
10331 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
10332 | return true; |
10333 | ||
10334 | return false; | |
10335 | } | |
10336 | ||
b2b55502 | 10337 | static bool needs_scaling(const struct intel_plane_state *state) |
5a21b665 | 10338 | { |
936e71e3 VS |
10339 | int src_w = drm_rect_width(&state->base.src) >> 16; |
10340 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
10341 | int dst_w = drm_rect_width(&state->base.dst); | |
10342 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
10343 | |
10344 | return (src_w != dst_w || src_h != dst_h); | |
10345 | } | |
d21fbe87 | 10346 | |
b2b55502 VS |
10347 | int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, |
10348 | struct drm_crtc_state *crtc_state, | |
10349 | const struct intel_plane_state *old_plane_state, | |
da20eabd ML |
10350 | struct drm_plane_state *plane_state) |
10351 | { | |
ab1d3a0e | 10352 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
10353 | struct drm_crtc *crtc = crtc_state->crtc; |
10354 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e9728bd8 | 10355 | struct intel_plane *plane = to_intel_plane(plane_state->plane); |
da20eabd | 10356 | struct drm_device *dev = crtc->dev; |
ed4a6a7c | 10357 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd | 10358 | bool mode_changed = needs_modeset(crtc_state); |
b2b55502 | 10359 | bool was_crtc_enabled = old_crtc_state->base.active; |
da20eabd | 10360 | bool is_crtc_enabled = crtc_state->active; |
da20eabd ML |
10361 | bool turn_off, turn_on, visible, was_visible; |
10362 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 10363 | int ret; |
da20eabd | 10364 | |
e9728bd8 | 10365 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
da20eabd ML |
10366 | ret = skl_update_scaler_plane( |
10367 | to_intel_crtc_state(crtc_state), | |
10368 | to_intel_plane_state(plane_state)); | |
10369 | if (ret) | |
10370 | return ret; | |
10371 | } | |
10372 | ||
936e71e3 | 10373 | was_visible = old_plane_state->base.visible; |
1d4258db | 10374 | visible = plane_state->visible; |
da20eabd ML |
10375 | |
10376 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
10377 | was_visible = false; | |
10378 | ||
35c08f43 ML |
10379 | /* |
10380 | * Visibility is calculated as if the crtc was on, but | |
10381 | * after scaler setup everything depends on it being off | |
10382 | * when the crtc isn't active. | |
f818ffea VS |
10383 | * |
10384 | * FIXME this is wrong for watermarks. Watermarks should also | |
10385 | * be computed as if the pipe would be active. Perhaps move | |
10386 | * per-plane wm computation to the .check_plane() hook, and | |
10387 | * only combine the results from all planes in the current place? | |
35c08f43 | 10388 | */ |
e9728bd8 | 10389 | if (!is_crtc_enabled) { |
1d4258db | 10390 | plane_state->visible = visible = false; |
e9728bd8 VS |
10391 | to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); |
10392 | } | |
da20eabd ML |
10393 | |
10394 | if (!was_visible && !visible) | |
10395 | return 0; | |
10396 | ||
e8861675 ML |
10397 | if (fb != old_plane_state->base.fb) |
10398 | pipe_config->fb_changed = true; | |
10399 | ||
da20eabd ML |
10400 | turn_off = was_visible && (!visible || mode_changed); |
10401 | turn_on = visible && (!was_visible || mode_changed); | |
10402 | ||
72660ce0 | 10403 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
e9728bd8 VS |
10404 | intel_crtc->base.base.id, intel_crtc->base.name, |
10405 | plane->base.base.id, plane->base.name, | |
72660ce0 | 10406 | fb ? fb->base.id : -1); |
da20eabd | 10407 | |
72660ce0 | 10408 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
e9728bd8 | 10409 | plane->base.base.id, plane->base.name, |
72660ce0 | 10410 | was_visible, visible, |
da20eabd ML |
10411 | turn_off, turn_on, mode_changed); |
10412 | ||
caed361d | 10413 | if (turn_on) { |
04548cba | 10414 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10415 | pipe_config->update_wm_pre = true; |
caed361d VS |
10416 | |
10417 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 10418 | if (plane->id != PLANE_CURSOR) |
caed361d VS |
10419 | pipe_config->disable_cxsr = true; |
10420 | } else if (turn_off) { | |
04548cba | 10421 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10422 | pipe_config->update_wm_post = true; |
92826fcd | 10423 | |
852eb00d | 10424 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 10425 | if (plane->id != PLANE_CURSOR) |
ab1d3a0e | 10426 | pipe_config->disable_cxsr = true; |
e9728bd8 | 10427 | } else if (intel_wm_need_update(&plane->base, plane_state)) { |
04548cba | 10428 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
b4ede6df VS |
10429 | /* FIXME bollocks */ |
10430 | pipe_config->update_wm_pre = true; | |
10431 | pipe_config->update_wm_post = true; | |
10432 | } | |
852eb00d | 10433 | } |
da20eabd | 10434 | |
8be6ca85 | 10435 | if (visible || was_visible) |
e9728bd8 | 10436 | pipe_config->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 10437 | |
31ae71fc ML |
10438 | /* |
10439 | * WaCxSRDisabledForSpriteScaling:ivb | |
10440 | * | |
10441 | * cstate->update_wm was already set above, so this flag will | |
10442 | * take effect when we commit and program watermarks. | |
10443 | */ | |
e9728bd8 | 10444 | if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
10445 | needs_scaling(to_intel_plane_state(plane_state)) && |
10446 | !needs_scaling(old_plane_state)) | |
10447 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 10448 | |
da20eabd ML |
10449 | return 0; |
10450 | } | |
10451 | ||
6d3a1ce7 ML |
10452 | static bool encoders_cloneable(const struct intel_encoder *a, |
10453 | const struct intel_encoder *b) | |
10454 | { | |
10455 | /* masks could be asymmetric, so check both ways */ | |
10456 | return a == b || (a->cloneable & (1 << b->type) && | |
10457 | b->cloneable & (1 << a->type)); | |
10458 | } | |
10459 | ||
10460 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
10461 | struct intel_crtc *crtc, | |
10462 | struct intel_encoder *encoder) | |
10463 | { | |
10464 | struct intel_encoder *source_encoder; | |
10465 | struct drm_connector *connector; | |
10466 | struct drm_connector_state *connector_state; | |
10467 | int i; | |
10468 | ||
aa5e9b47 | 10469 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
6d3a1ce7 ML |
10470 | if (connector_state->crtc != &crtc->base) |
10471 | continue; | |
10472 | ||
10473 | source_encoder = | |
10474 | to_intel_encoder(connector_state->best_encoder); | |
10475 | if (!encoders_cloneable(encoder, source_encoder)) | |
10476 | return false; | |
10477 | } | |
10478 | ||
10479 | return true; | |
10480 | } | |
10481 | ||
6d3a1ce7 ML |
10482 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
10483 | struct drm_crtc_state *crtc_state) | |
10484 | { | |
cf5a15be | 10485 | struct drm_device *dev = crtc->dev; |
fac5e23e | 10486 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 10487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
10488 | struct intel_crtc_state *pipe_config = |
10489 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 10490 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 10491 | int ret; |
6d3a1ce7 ML |
10492 | bool mode_changed = needs_modeset(crtc_state); |
10493 | ||
852eb00d | 10494 | if (mode_changed && !crtc_state->active) |
caed361d | 10495 | pipe_config->update_wm_post = true; |
eddfcbcd | 10496 | |
ad421372 ML |
10497 | if (mode_changed && crtc_state->enable && |
10498 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 10499 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
10500 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
10501 | pipe_config); | |
10502 | if (ret) | |
10503 | return ret; | |
10504 | } | |
10505 | ||
82cf435b LL |
10506 | if (crtc_state->color_mgmt_changed) { |
10507 | ret = intel_color_check(crtc, crtc_state); | |
10508 | if (ret) | |
10509 | return ret; | |
e7852a4b LL |
10510 | |
10511 | /* | |
10512 | * Changing color management on Intel hardware is | |
10513 | * handled as part of planes update. | |
10514 | */ | |
10515 | crtc_state->planes_changed = true; | |
82cf435b LL |
10516 | } |
10517 | ||
e435d6e5 | 10518 | ret = 0; |
86c8bbbe | 10519 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 10520 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
10521 | if (ret) { |
10522 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
10523 | return ret; | |
10524 | } | |
10525 | } | |
10526 | ||
10527 | if (dev_priv->display.compute_intermediate_wm && | |
10528 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
10529 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
10530 | return 0; | |
10531 | ||
10532 | /* | |
10533 | * Calculate 'intermediate' watermarks that satisfy both the | |
10534 | * old state and the new state. We can program these | |
10535 | * immediately. | |
10536 | */ | |
6315b5d3 | 10537 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
10538 | intel_crtc, |
10539 | pipe_config); | |
10540 | if (ret) { | |
10541 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 10542 | return ret; |
ed4a6a7c | 10543 | } |
e3d5457c VS |
10544 | } else if (dev_priv->display.compute_intermediate_wm) { |
10545 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
10546 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
10547 | } |
10548 | ||
6315b5d3 | 10549 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
10550 | if (mode_changed) |
10551 | ret = skl_update_scaler_crtc(pipe_config); | |
10552 | ||
73b0ca8e MK |
10553 | if (!ret) |
10554 | ret = skl_check_pipe_max_pixel_rate(intel_crtc, | |
10555 | pipe_config); | |
e435d6e5 | 10556 | if (!ret) |
6ebc6923 | 10557 | ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, |
e435d6e5 ML |
10558 | pipe_config); |
10559 | } | |
10560 | ||
10561 | return ret; | |
6d3a1ce7 ML |
10562 | } |
10563 | ||
65b38e0d | 10564 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
5a21b665 DV |
10565 | .atomic_begin = intel_begin_crtc_commit, |
10566 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 10567 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
10568 | }; |
10569 | ||
d29b2f9d ACO |
10570 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
10571 | { | |
10572 | struct intel_connector *connector; | |
f9e905ca | 10573 | struct drm_connector_list_iter conn_iter; |
d29b2f9d | 10574 | |
f9e905ca DV |
10575 | drm_connector_list_iter_begin(dev, &conn_iter); |
10576 | for_each_intel_connector_iter(connector, &conn_iter) { | |
8863dc7f DV |
10577 | if (connector->base.state->crtc) |
10578 | drm_connector_unreference(&connector->base); | |
10579 | ||
d29b2f9d ACO |
10580 | if (connector->base.encoder) { |
10581 | connector->base.state->best_encoder = | |
10582 | connector->base.encoder; | |
10583 | connector->base.state->crtc = | |
10584 | connector->base.encoder->crtc; | |
8863dc7f DV |
10585 | |
10586 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
10587 | } else { |
10588 | connector->base.state->best_encoder = NULL; | |
10589 | connector->base.state->crtc = NULL; | |
10590 | } | |
10591 | } | |
f9e905ca | 10592 | drm_connector_list_iter_end(&conn_iter); |
d29b2f9d ACO |
10593 | } |
10594 | ||
050f7aeb | 10595 | static void |
eba905b2 | 10596 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10597 | struct intel_crtc_state *pipe_config) |
050f7aeb | 10598 | { |
6a2a5c5d | 10599 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
10600 | int bpp = pipe_config->pipe_bpp; |
10601 | ||
10602 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
10603 | connector->base.base.id, |
10604 | connector->base.name); | |
050f7aeb DV |
10605 | |
10606 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 10607 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 10608 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
10609 | bpp, info->bpc * 3); |
10610 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
10611 | } |
10612 | ||
196f954e | 10613 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 10614 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
10615 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
10616 | bpp); | |
10617 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
10618 | } |
10619 | } | |
10620 | ||
4e53c2e0 | 10621 | static int |
050f7aeb | 10622 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 10623 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10624 | { |
9beb5fea | 10625 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 10626 | struct drm_atomic_state *state; |
da3ced29 ACO |
10627 | struct drm_connector *connector; |
10628 | struct drm_connector_state *connector_state; | |
1486017f | 10629 | int bpp, i; |
4e53c2e0 | 10630 | |
9beb5fea TU |
10631 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
10632 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 10633 | bpp = 10*3; |
9beb5fea | 10634 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
10635 | bpp = 12*3; |
10636 | else | |
10637 | bpp = 8*3; | |
10638 | ||
4e53c2e0 | 10639 | |
4e53c2e0 DV |
10640 | pipe_config->pipe_bpp = bpp; |
10641 | ||
1486017f ACO |
10642 | state = pipe_config->base.state; |
10643 | ||
4e53c2e0 | 10644 | /* Clamp display bpp to EDID value */ |
aa5e9b47 | 10645 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
da3ced29 | 10646 | if (connector_state->crtc != &crtc->base) |
4e53c2e0 DV |
10647 | continue; |
10648 | ||
da3ced29 ACO |
10649 | connected_sink_compute_bpp(to_intel_connector(connector), |
10650 | pipe_config); | |
4e53c2e0 DV |
10651 | } |
10652 | ||
10653 | return bpp; | |
10654 | } | |
10655 | ||
644db711 DV |
10656 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10657 | { | |
10658 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10659 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10660 | mode->crtc_clock, |
644db711 DV |
10661 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10662 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10663 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10664 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10665 | } | |
10666 | ||
f6982332 TU |
10667 | static inline void |
10668 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 10669 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 10670 | { |
a4309657 TU |
10671 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10672 | id, lane_count, | |
f6982332 TU |
10673 | m_n->gmch_m, m_n->gmch_n, |
10674 | m_n->link_m, m_n->link_n, m_n->tu); | |
10675 | } | |
10676 | ||
c0b03411 | 10677 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10678 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10679 | const char *context) |
10680 | { | |
6a60cd87 | 10681 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 10682 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
10683 | struct drm_plane *plane; |
10684 | struct intel_plane *intel_plane; | |
10685 | struct intel_plane_state *state; | |
10686 | struct drm_framebuffer *fb; | |
10687 | ||
66766e4f TU |
10688 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
10689 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 10690 | |
2c89429e TU |
10691 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
10692 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 10693 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
10694 | |
10695 | if (pipe_config->has_pch_encoder) | |
10696 | intel_dump_m_n_config(pipe_config, "fdi", | |
10697 | pipe_config->fdi_lanes, | |
10698 | &pipe_config->fdi_m_n); | |
f6982332 | 10699 | |
b22ca995 SS |
10700 | if (pipe_config->ycbcr420) |
10701 | DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n"); | |
10702 | ||
f6982332 | 10703 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
a4309657 TU |
10704 | intel_dump_m_n_config(pipe_config, "dp m_n", |
10705 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
10706 | if (pipe_config->has_drrs) |
10707 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
10708 | pipe_config->lane_count, | |
10709 | &pipe_config->dp_m2_n2); | |
f6982332 | 10710 | } |
b95af8be | 10711 | |
55072d19 | 10712 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 10713 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 10714 | |
c0b03411 | 10715 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10716 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10717 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10718 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10719 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
a7d1b3f4 | 10720 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", |
2c89429e | 10721 | pipe_config->port_clock, |
a7d1b3f4 VS |
10722 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
10723 | pipe_config->pixel_rate); | |
dd2f616d TU |
10724 | |
10725 | if (INTEL_GEN(dev_priv) >= 9) | |
10726 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
10727 | crtc->num_scalers, | |
10728 | pipe_config->scaler_state.scaler_users, | |
10729 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
10730 | |
10731 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
10732 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
10733 | pipe_config->gmch_pfit.control, | |
10734 | pipe_config->gmch_pfit.pgm_ratios, | |
10735 | pipe_config->gmch_pfit.lvds_border_bits); | |
10736 | else | |
10737 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
10738 | pipe_config->pch_pfit.pos, | |
10739 | pipe_config->pch_pfit.size, | |
08c4d7fc | 10740 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 10741 | |
2c89429e TU |
10742 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
10743 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 10744 | |
f50b79f0 | 10745 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 10746 | |
6a60cd87 CK |
10747 | DRM_DEBUG_KMS("planes on this crtc\n"); |
10748 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 10749 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
10750 | intel_plane = to_intel_plane(plane); |
10751 | if (intel_plane->pipe != crtc->pipe) | |
10752 | continue; | |
10753 | ||
10754 | state = to_intel_plane_state(plane->state); | |
10755 | fb = state->base.fb; | |
10756 | if (!fb) { | |
1d577e02 VS |
10757 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
10758 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
10759 | continue; |
10760 | } | |
10761 | ||
dd2f616d TU |
10762 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
10763 | plane->base.id, plane->name, | |
b3c11ac2 | 10764 | fb->base.id, fb->width, fb->height, |
438b74a5 | 10765 | drm_get_format_name(fb->format->format, &format_name)); |
dd2f616d TU |
10766 | if (INTEL_GEN(dev_priv) >= 9) |
10767 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
10768 | state->scaler_id, | |
10769 | state->base.src.x1 >> 16, | |
10770 | state->base.src.y1 >> 16, | |
10771 | drm_rect_width(&state->base.src) >> 16, | |
10772 | drm_rect_height(&state->base.src) >> 16, | |
10773 | state->base.dst.x1, state->base.dst.y1, | |
10774 | drm_rect_width(&state->base.dst), | |
10775 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 10776 | } |
c0b03411 DV |
10777 | } |
10778 | ||
5448a00d | 10779 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 10780 | { |
5448a00d | 10781 | struct drm_device *dev = state->dev; |
da3ced29 | 10782 | struct drm_connector *connector; |
2fd96b41 | 10783 | struct drm_connector_list_iter conn_iter; |
00f0b378 | 10784 | unsigned int used_ports = 0; |
477321e0 | 10785 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
10786 | |
10787 | /* | |
10788 | * Walk the connector list instead of the encoder | |
10789 | * list to detect the problem on ddi platforms | |
10790 | * where there's just one encoder per digital port. | |
10791 | */ | |
2fd96b41 GP |
10792 | drm_connector_list_iter_begin(dev, &conn_iter); |
10793 | drm_for_each_connector_iter(connector, &conn_iter) { | |
0bff4858 VS |
10794 | struct drm_connector_state *connector_state; |
10795 | struct intel_encoder *encoder; | |
10796 | ||
10797 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
10798 | if (!connector_state) | |
10799 | connector_state = connector->state; | |
10800 | ||
5448a00d | 10801 | if (!connector_state->best_encoder) |
00f0b378 VS |
10802 | continue; |
10803 | ||
5448a00d ACO |
10804 | encoder = to_intel_encoder(connector_state->best_encoder); |
10805 | ||
10806 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
10807 | |
10808 | switch (encoder->type) { | |
10809 | unsigned int port_mask; | |
10810 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 10811 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 10812 | break; |
cca0502b | 10813 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
10814 | case INTEL_OUTPUT_HDMI: |
10815 | case INTEL_OUTPUT_EDP: | |
10816 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10817 | ||
10818 | /* the same port mustn't appear more than once */ | |
10819 | if (used_ports & port_mask) | |
10820 | return false; | |
10821 | ||
10822 | used_ports |= port_mask; | |
477321e0 VS |
10823 | break; |
10824 | case INTEL_OUTPUT_DP_MST: | |
10825 | used_mst_ports |= | |
10826 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
10827 | break; | |
00f0b378 VS |
10828 | default: |
10829 | break; | |
10830 | } | |
10831 | } | |
2fd96b41 | 10832 | drm_connector_list_iter_end(&conn_iter); |
00f0b378 | 10833 | |
477321e0 VS |
10834 | /* can't mix MST and SST/HDMI on the same port */ |
10835 | if (used_ports & used_mst_ports) | |
10836 | return false; | |
10837 | ||
00f0b378 VS |
10838 | return true; |
10839 | } | |
10840 | ||
83a57153 ACO |
10841 | static void |
10842 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
10843 | { | |
ff32c54e VS |
10844 | struct drm_i915_private *dev_priv = |
10845 | to_i915(crtc_state->base.crtc->dev); | |
663a3640 | 10846 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 10847 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 10848 | struct intel_shared_dpll *shared_dpll; |
ff32c54e | 10849 | struct intel_crtc_wm_state wm_state; |
6e644626 | 10850 | bool force_thru, ips_force_disable; |
83a57153 | 10851 | |
7546a384 ACO |
10852 | /* FIXME: before the switch to atomic started, a new pipe_config was |
10853 | * kzalloc'd. Code that depends on any field being zero should be | |
10854 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
10855 | * only fields that are know to not cause problems are preserved. */ | |
10856 | ||
663a3640 | 10857 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
10858 | shared_dpll = crtc_state->shared_dpll; |
10859 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 10860 | force_thru = crtc_state->pch_pfit.force_thru; |
6e644626 | 10861 | ips_force_disable = crtc_state->ips_force_disable; |
04548cba VS |
10862 | if (IS_G4X(dev_priv) || |
10863 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10864 | wm_state = crtc_state->wm; |
4978cc93 | 10865 | |
d2fa80a5 CW |
10866 | /* Keep base drm_crtc_state intact, only clear our extended struct */ |
10867 | BUILD_BUG_ON(offsetof(struct intel_crtc_state, base)); | |
10868 | memset(&crtc_state->base + 1, 0, | |
10869 | sizeof(*crtc_state) - sizeof(crtc_state->base)); | |
4978cc93 | 10870 | |
663a3640 | 10871 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
10872 | crtc_state->shared_dpll = shared_dpll; |
10873 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 10874 | crtc_state->pch_pfit.force_thru = force_thru; |
6e644626 | 10875 | crtc_state->ips_force_disable = ips_force_disable; |
04548cba VS |
10876 | if (IS_G4X(dev_priv) || |
10877 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10878 | crtc_state->wm = wm_state; |
83a57153 ACO |
10879 | } |
10880 | ||
548ee15b | 10881 | static int |
b8cecdf5 | 10882 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 10883 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 10884 | { |
b359283a | 10885 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 10886 | struct intel_encoder *encoder; |
da3ced29 | 10887 | struct drm_connector *connector; |
0b901879 | 10888 | struct drm_connector_state *connector_state; |
d328c9d7 | 10889 | int base_bpp, ret = -EINVAL; |
0b901879 | 10890 | int i; |
e29c22c0 | 10891 | bool retry = true; |
ee7b9f93 | 10892 | |
83a57153 | 10893 | clear_intel_crtc_state(pipe_config); |
7758a113 | 10894 | |
e143a21c DV |
10895 | pipe_config->cpu_transcoder = |
10896 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 10897 | |
2960bc9c ID |
10898 | /* |
10899 | * Sanitize sync polarity flags based on requested ones. If neither | |
10900 | * positive or negative polarity is requested, treat this as meaning | |
10901 | * negative polarity. | |
10902 | */ | |
2d112de7 | 10903 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10904 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10905 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10906 | |
2d112de7 | 10907 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10908 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10909 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10910 | |
d328c9d7 DV |
10911 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
10912 | pipe_config); | |
10913 | if (base_bpp < 0) | |
4e53c2e0 DV |
10914 | goto fail; |
10915 | ||
e41a56be VS |
10916 | /* |
10917 | * Determine the real pipe dimensions. Note that stereo modes can | |
10918 | * increase the actual pipe size due to the frame doubling and | |
10919 | * insertion of additional space for blanks between the frame. This | |
10920 | * is stored in the crtc timings. We use the requested mode to do this | |
10921 | * computation to clearly distinguish it from the adjusted mode, which | |
10922 | * can be changed by the connectors in the below retry loop. | |
10923 | */ | |
196cd5d3 | 10924 | drm_mode_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10925 | &pipe_config->pipe_src_w, |
10926 | &pipe_config->pipe_src_h); | |
e41a56be | 10927 | |
aa5e9b47 | 10928 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
253c84c8 VS |
10929 | if (connector_state->crtc != crtc) |
10930 | continue; | |
10931 | ||
10932 | encoder = to_intel_encoder(connector_state->best_encoder); | |
10933 | ||
e25148d0 VS |
10934 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
10935 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
10936 | goto fail; | |
10937 | } | |
10938 | ||
253c84c8 VS |
10939 | /* |
10940 | * Determine output_types before calling the .compute_config() | |
10941 | * hooks so that the hooks can use this information safely. | |
10942 | */ | |
10943 | pipe_config->output_types |= 1 << encoder->type; | |
10944 | } | |
10945 | ||
e29c22c0 | 10946 | encoder_retry: |
ef1b460d | 10947 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10948 | pipe_config->port_clock = 0; |
ef1b460d | 10949 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10950 | |
135c81b8 | 10951 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10952 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10953 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10954 | |
7758a113 DV |
10955 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10956 | * adjust it according to limitations or connector properties, and also | |
10957 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10958 | */ |
aa5e9b47 | 10959 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 10960 | if (connector_state->crtc != crtc) |
7758a113 | 10961 | continue; |
7ae89233 | 10962 | |
0b901879 ACO |
10963 | encoder = to_intel_encoder(connector_state->best_encoder); |
10964 | ||
0a478c27 | 10965 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 10966 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
10967 | goto fail; |
10968 | } | |
ee7b9f93 | 10969 | } |
47f1c6c9 | 10970 | |
ff9a6750 DV |
10971 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10972 | * done afterwards in case the encoder adjusts the mode. */ | |
10973 | if (!pipe_config->port_clock) | |
2d112de7 | 10974 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10975 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10976 | |
a43f6e0f | 10977 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10978 | if (ret < 0) { |
7758a113 DV |
10979 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10980 | goto fail; | |
ee7b9f93 | 10981 | } |
e29c22c0 DV |
10982 | |
10983 | if (ret == RETRY) { | |
10984 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10985 | ret = -EINVAL; | |
10986 | goto fail; | |
10987 | } | |
10988 | ||
10989 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10990 | retry = false; | |
10991 | goto encoder_retry; | |
10992 | } | |
10993 | ||
e8fa4270 | 10994 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
10995 | * only enable it on 6bpc panels and when its not a compliance |
10996 | * test requesting 6bpc video pattern. | |
10997 | */ | |
10998 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
10999 | !pipe_config->dither_force_disable; | |
62f0ace5 | 11000 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11001 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11002 | |
7758a113 | 11003 | fail: |
548ee15b | 11004 | return ret; |
ee7b9f93 | 11005 | } |
47f1c6c9 | 11006 | |
ea9d758d | 11007 | static void |
4740b0f2 | 11008 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 11009 | { |
0a9ab303 | 11010 | struct drm_crtc *crtc; |
aa5e9b47 | 11011 | struct drm_crtc_state *new_crtc_state; |
8a75d157 | 11012 | int i; |
ea9d758d | 11013 | |
7668851f | 11014 | /* Double check state. */ |
aa5e9b47 ML |
11015 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
11016 | to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state); | |
fc467a22 | 11017 | |
61067a5e ML |
11018 | /* |
11019 | * Update legacy state to satisfy fbc code. This can | |
11020 | * be removed when fbc uses the atomic state. | |
11021 | */ | |
11022 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
11023 | struct drm_plane_state *plane_state = crtc->primary->state; | |
11024 | ||
11025 | crtc->primary->fb = plane_state->fb; | |
11026 | crtc->x = plane_state->src_x >> 16; | |
11027 | crtc->y = plane_state->src_y >> 16; | |
11028 | } | |
ea9d758d | 11029 | } |
ea9d758d DV |
11030 | } |
11031 | ||
3bd26263 | 11032 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11033 | { |
3bd26263 | 11034 | int diff; |
f1f644dc JB |
11035 | |
11036 | if (clock1 == clock2) | |
11037 | return true; | |
11038 | ||
11039 | if (!clock1 || !clock2) | |
11040 | return false; | |
11041 | ||
11042 | diff = abs(clock1 - clock2); | |
11043 | ||
11044 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11045 | return true; | |
11046 | ||
11047 | return false; | |
11048 | } | |
11049 | ||
cfb23ed6 ML |
11050 | static bool |
11051 | intel_compare_m_n(unsigned int m, unsigned int n, | |
11052 | unsigned int m2, unsigned int n2, | |
11053 | bool exact) | |
11054 | { | |
11055 | if (m == m2 && n == n2) | |
11056 | return true; | |
11057 | ||
11058 | if (exact || !m || !n || !m2 || !n2) | |
11059 | return false; | |
11060 | ||
11061 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
11062 | ||
31d10b57 ML |
11063 | if (n > n2) { |
11064 | while (n > n2) { | |
cfb23ed6 ML |
11065 | m2 <<= 1; |
11066 | n2 <<= 1; | |
11067 | } | |
31d10b57 ML |
11068 | } else if (n < n2) { |
11069 | while (n < n2) { | |
cfb23ed6 ML |
11070 | m <<= 1; |
11071 | n <<= 1; | |
11072 | } | |
11073 | } | |
11074 | ||
31d10b57 ML |
11075 | if (n != n2) |
11076 | return false; | |
11077 | ||
11078 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
11079 | } |
11080 | ||
11081 | static bool | |
11082 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
11083 | struct intel_link_m_n *m2_n2, | |
11084 | bool adjust) | |
11085 | { | |
11086 | if (m_n->tu == m2_n2->tu && | |
11087 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
11088 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
11089 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
11090 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
11091 | if (adjust) | |
11092 | *m2_n2 = *m_n; | |
11093 | ||
11094 | return true; | |
11095 | } | |
11096 | ||
11097 | return false; | |
11098 | } | |
11099 | ||
4e8048f8 TU |
11100 | static void __printf(3, 4) |
11101 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
11102 | { | |
11103 | char *level; | |
11104 | unsigned int category; | |
11105 | struct va_format vaf; | |
11106 | va_list args; | |
11107 | ||
11108 | if (adjust) { | |
11109 | level = KERN_DEBUG; | |
11110 | category = DRM_UT_KMS; | |
11111 | } else { | |
11112 | level = KERN_ERR; | |
11113 | category = DRM_UT_NONE; | |
11114 | } | |
11115 | ||
11116 | va_start(args, format); | |
11117 | vaf.fmt = format; | |
11118 | vaf.va = &args; | |
11119 | ||
11120 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
11121 | ||
11122 | va_end(args); | |
11123 | } | |
11124 | ||
0e8ffe1b | 11125 | static bool |
6315b5d3 | 11126 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 11127 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
11128 | struct intel_crtc_state *pipe_config, |
11129 | bool adjust) | |
0e8ffe1b | 11130 | { |
cfb23ed6 ML |
11131 | bool ret = true; |
11132 | ||
66e985c0 DV |
11133 | #define PIPE_CONF_CHECK_X(name) \ |
11134 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11135 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
11136 | "(expected 0x%08x, found 0x%08x)\n", \ |
11137 | current_config->name, \ | |
11138 | pipe_config->name); \ | |
cfb23ed6 | 11139 | ret = false; \ |
66e985c0 DV |
11140 | } |
11141 | ||
08a24034 DV |
11142 | #define PIPE_CONF_CHECK_I(name) \ |
11143 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11144 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
11145 | "(expected %i, found %i)\n", \ |
11146 | current_config->name, \ | |
11147 | pipe_config->name); \ | |
cfb23ed6 ML |
11148 | ret = false; \ |
11149 | } | |
11150 | ||
8106ddbd ACO |
11151 | #define PIPE_CONF_CHECK_P(name) \ |
11152 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11153 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
11154 | "(expected %p, found %p)\n", \ |
11155 | current_config->name, \ | |
11156 | pipe_config->name); \ | |
11157 | ret = false; \ | |
11158 | } | |
11159 | ||
cfb23ed6 ML |
11160 | #define PIPE_CONF_CHECK_M_N(name) \ |
11161 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11162 | &pipe_config->name,\ | |
11163 | adjust)) { \ | |
4e8048f8 | 11164 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11165 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11166 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11167 | current_config->name.tu, \ | |
11168 | current_config->name.gmch_m, \ | |
11169 | current_config->name.gmch_n, \ | |
11170 | current_config->name.link_m, \ | |
11171 | current_config->name.link_n, \ | |
11172 | pipe_config->name.tu, \ | |
11173 | pipe_config->name.gmch_m, \ | |
11174 | pipe_config->name.gmch_n, \ | |
11175 | pipe_config->name.link_m, \ | |
11176 | pipe_config->name.link_n); \ | |
11177 | ret = false; \ | |
11178 | } | |
11179 | ||
55c561a7 DV |
11180 | /* This is required for BDW+ where there is only one set of registers for |
11181 | * switching between high and low RR. | |
11182 | * This macro can be used whenever a comparison has to be made between one | |
11183 | * hw state and multiple sw state variables. | |
11184 | */ | |
cfb23ed6 ML |
11185 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
11186 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11187 | &pipe_config->name, adjust) && \ | |
11188 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
11189 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 11190 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11191 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11192 | "or tu %i gmch %i/%i link %i/%i, " \ | |
11193 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11194 | current_config->name.tu, \ | |
11195 | current_config->name.gmch_m, \ | |
11196 | current_config->name.gmch_n, \ | |
11197 | current_config->name.link_m, \ | |
11198 | current_config->name.link_n, \ | |
11199 | current_config->alt_name.tu, \ | |
11200 | current_config->alt_name.gmch_m, \ | |
11201 | current_config->alt_name.gmch_n, \ | |
11202 | current_config->alt_name.link_m, \ | |
11203 | current_config->alt_name.link_n, \ | |
11204 | pipe_config->name.tu, \ | |
11205 | pipe_config->name.gmch_m, \ | |
11206 | pipe_config->name.gmch_n, \ | |
11207 | pipe_config->name.link_m, \ | |
11208 | pipe_config->name.link_n); \ | |
11209 | ret = false; \ | |
88adfff1 DV |
11210 | } |
11211 | ||
1bd1bd80 DV |
11212 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11213 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
11214 | pipe_config_err(adjust, __stringify(name), \ |
11215 | "(%x) (expected %i, found %i)\n", \ | |
11216 | (mask), \ | |
1bd1bd80 DV |
11217 | current_config->name & (mask), \ |
11218 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 11219 | ret = false; \ |
1bd1bd80 DV |
11220 | } |
11221 | ||
5e550656 VS |
11222 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11223 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 11224 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
11225 | "(expected %i, found %i)\n", \ |
11226 | current_config->name, \ | |
11227 | pipe_config->name); \ | |
cfb23ed6 | 11228 | ret = false; \ |
5e550656 VS |
11229 | } |
11230 | ||
bb760063 DV |
11231 | #define PIPE_CONF_QUIRK(quirk) \ |
11232 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11233 | ||
eccb140b DV |
11234 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11235 | ||
08a24034 DV |
11236 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11237 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 11238 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 11239 | |
90a6b7b0 | 11240 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 11241 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 11242 | |
6315b5d3 | 11243 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
11244 | PIPE_CONF_CHECK_M_N(dp_m_n); |
11245 | ||
cfb23ed6 ML |
11246 | if (current_config->has_drrs) |
11247 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
11248 | } else | |
11249 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 11250 | |
253c84c8 | 11251 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 11252 | |
2d112de7 ACO |
11253 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11254 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11255 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11256 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11257 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11258 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11259 | |
2d112de7 ACO |
11260 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11261 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11262 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11263 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11264 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11265 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11266 | |
c93f54cf | 11267 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11268 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 11269 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 11270 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 11271 | PIPE_CONF_CHECK_I(limited_color_range); |
15953637 SS |
11272 | |
11273 | PIPE_CONF_CHECK_I(hdmi_scrambling); | |
11274 | PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio); | |
e43823ec | 11275 | PIPE_CONF_CHECK_I(has_infoframe); |
60436fd4 | 11276 | PIPE_CONF_CHECK_I(ycbcr420); |
6c49f241 | 11277 | |
9ed109a7 DV |
11278 | PIPE_CONF_CHECK_I(has_audio); |
11279 | ||
2d112de7 | 11280 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11281 | DRM_MODE_FLAG_INTERLACE); |
11282 | ||
bb760063 | 11283 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11284 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11285 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11286 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11287 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11288 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11289 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11290 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11291 | DRM_MODE_FLAG_NVSYNC); |
11292 | } | |
045ac3b5 | 11293 | |
333b8ca8 | 11294 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 11295 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 11296 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 11297 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 11298 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 11299 | |
bfd16b2a ML |
11300 | if (!adjust) { |
11301 | PIPE_CONF_CHECK_I(pipe_src_w); | |
11302 | PIPE_CONF_CHECK_I(pipe_src_h); | |
11303 | ||
11304 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
11305 | if (current_config->pch_pfit.enabled) { | |
11306 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
11307 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
11308 | } | |
2fa2fe9a | 11309 | |
7aefe2b5 | 11310 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 11311 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
7aefe2b5 | 11312 | } |
a1b2278e | 11313 | |
e59150dc | 11314 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 11315 | if (IS_HASWELL(dev_priv)) |
e59150dc | 11316 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 11317 | |
282740f7 VS |
11318 | PIPE_CONF_CHECK_I(double_wide); |
11319 | ||
8106ddbd | 11320 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 11321 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11322 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11323 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11324 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11325 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 11326 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
11327 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11328 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11329 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11330 | |
47eacbab VS |
11331 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
11332 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
11333 | ||
9beb5fea | 11334 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
11335 | PIPE_CONF_CHECK_I(pipe_bpp); |
11336 | ||
2d112de7 | 11337 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11338 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11339 | |
66e985c0 | 11340 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11341 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 11342 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 11343 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11344 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11345 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11346 | |
cfb23ed6 | 11347 | return ret; |
0e8ffe1b DV |
11348 | } |
11349 | ||
e3b247da VS |
11350 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
11351 | const struct intel_crtc_state *pipe_config) | |
11352 | { | |
11353 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 11354 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
11355 | &pipe_config->fdi_m_n); |
11356 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
11357 | ||
11358 | /* | |
11359 | * FDI already provided one idea for the dotclock. | |
11360 | * Yell if the encoder disagrees. | |
11361 | */ | |
11362 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
11363 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
11364 | fdi_dotclock, dotclock); | |
11365 | } | |
11366 | } | |
11367 | ||
c0ead703 ML |
11368 | static void verify_wm_state(struct drm_crtc *crtc, |
11369 | struct drm_crtc_state *new_state) | |
08db6652 | 11370 | { |
6315b5d3 | 11371 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 11372 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 11373 | struct skl_pipe_wm hw_wm, *sw_wm; |
11374 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
11375 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
11376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11377 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 11378 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 11379 | |
6315b5d3 | 11380 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
11381 | return; |
11382 | ||
3de8a14c | 11383 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 11384 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 11385 | |
08db6652 DL |
11386 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
11387 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11388 | ||
e7c84544 | 11389 | /* planes */ |
8b364b41 | 11390 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 11391 | hw_plane_wm = &hw_wm.planes[plane]; |
11392 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 11393 | |
3de8a14c | 11394 | /* Watermarks */ |
11395 | for (level = 0; level <= max_level; level++) { | |
11396 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11397 | &sw_plane_wm->wm[level])) | |
11398 | continue; | |
11399 | ||
11400 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11401 | pipe_name(pipe), plane + 1, level, | |
11402 | sw_plane_wm->wm[level].plane_en, | |
11403 | sw_plane_wm->wm[level].plane_res_b, | |
11404 | sw_plane_wm->wm[level].plane_res_l, | |
11405 | hw_plane_wm->wm[level].plane_en, | |
11406 | hw_plane_wm->wm[level].plane_res_b, | |
11407 | hw_plane_wm->wm[level].plane_res_l); | |
11408 | } | |
08db6652 | 11409 | |
3de8a14c | 11410 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
11411 | &sw_plane_wm->trans_wm)) { | |
11412 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11413 | pipe_name(pipe), plane + 1, | |
11414 | sw_plane_wm->trans_wm.plane_en, | |
11415 | sw_plane_wm->trans_wm.plane_res_b, | |
11416 | sw_plane_wm->trans_wm.plane_res_l, | |
11417 | hw_plane_wm->trans_wm.plane_en, | |
11418 | hw_plane_wm->trans_wm.plane_res_b, | |
11419 | hw_plane_wm->trans_wm.plane_res_l); | |
11420 | } | |
11421 | ||
11422 | /* DDB */ | |
11423 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
11424 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
11425 | ||
11426 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 11427 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 11428 | pipe_name(pipe), plane + 1, |
11429 | sw_ddb_entry->start, sw_ddb_entry->end, | |
11430 | hw_ddb_entry->start, hw_ddb_entry->end); | |
11431 | } | |
e7c84544 | 11432 | } |
08db6652 | 11433 | |
27082493 L |
11434 | /* |
11435 | * cursor | |
11436 | * If the cursor plane isn't active, we may not have updated it's ddb | |
11437 | * allocation. In that case since the ddb allocation will be updated | |
11438 | * once the plane becomes visible, we can skip this check | |
11439 | */ | |
cd5dcbf1 | 11440 | if (1) { |
3de8a14c | 11441 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
11442 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
11443 | ||
11444 | /* Watermarks */ | |
11445 | for (level = 0; level <= max_level; level++) { | |
11446 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11447 | &sw_plane_wm->wm[level])) | |
11448 | continue; | |
11449 | ||
11450 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11451 | pipe_name(pipe), level, | |
11452 | sw_plane_wm->wm[level].plane_en, | |
11453 | sw_plane_wm->wm[level].plane_res_b, | |
11454 | sw_plane_wm->wm[level].plane_res_l, | |
11455 | hw_plane_wm->wm[level].plane_en, | |
11456 | hw_plane_wm->wm[level].plane_res_b, | |
11457 | hw_plane_wm->wm[level].plane_res_l); | |
11458 | } | |
11459 | ||
11460 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
11461 | &sw_plane_wm->trans_wm)) { | |
11462 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11463 | pipe_name(pipe), | |
11464 | sw_plane_wm->trans_wm.plane_en, | |
11465 | sw_plane_wm->trans_wm.plane_res_b, | |
11466 | sw_plane_wm->trans_wm.plane_res_l, | |
11467 | hw_plane_wm->trans_wm.plane_en, | |
11468 | hw_plane_wm->trans_wm.plane_res_b, | |
11469 | hw_plane_wm->trans_wm.plane_res_l); | |
11470 | } | |
11471 | ||
11472 | /* DDB */ | |
11473 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
11474 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 11475 | |
3de8a14c | 11476 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 11477 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 11478 | pipe_name(pipe), |
3de8a14c | 11479 | sw_ddb_entry->start, sw_ddb_entry->end, |
11480 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 11481 | } |
08db6652 DL |
11482 | } |
11483 | } | |
11484 | ||
91d1b4bd | 11485 | static void |
677100ce ML |
11486 | verify_connector_state(struct drm_device *dev, |
11487 | struct drm_atomic_state *state, | |
11488 | struct drm_crtc *crtc) | |
8af6cf88 | 11489 | { |
35dd3c64 | 11490 | struct drm_connector *connector; |
aa5e9b47 | 11491 | struct drm_connector_state *new_conn_state; |
677100ce | 11492 | int i; |
8af6cf88 | 11493 | |
aa5e9b47 | 11494 | for_each_new_connector_in_state(state, connector, new_conn_state, i) { |
35dd3c64 | 11495 | struct drm_encoder *encoder = connector->encoder; |
749d98b8 | 11496 | struct drm_crtc_state *crtc_state = NULL; |
ad3c558f | 11497 | |
aa5e9b47 | 11498 | if (new_conn_state->crtc != crtc) |
e7c84544 ML |
11499 | continue; |
11500 | ||
749d98b8 ML |
11501 | if (crtc) |
11502 | crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); | |
11503 | ||
11504 | intel_connector_verify_state(crtc_state, new_conn_state); | |
8af6cf88 | 11505 | |
aa5e9b47 | 11506 | I915_STATE_WARN(new_conn_state->best_encoder != encoder, |
35dd3c64 | 11507 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 11508 | } |
91d1b4bd DV |
11509 | } |
11510 | ||
11511 | static void | |
86b04268 | 11512 | verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state) |
91d1b4bd DV |
11513 | { |
11514 | struct intel_encoder *encoder; | |
86b04268 DV |
11515 | struct drm_connector *connector; |
11516 | struct drm_connector_state *old_conn_state, *new_conn_state; | |
11517 | int i; | |
8af6cf88 | 11518 | |
b2784e15 | 11519 | for_each_intel_encoder(dev, encoder) { |
86b04268 | 11520 | bool enabled = false, found = false; |
4d20cd86 | 11521 | enum pipe pipe; |
8af6cf88 DV |
11522 | |
11523 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11524 | encoder->base.base.id, | |
8e329a03 | 11525 | encoder->base.name); |
8af6cf88 | 11526 | |
86b04268 DV |
11527 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, |
11528 | new_conn_state, i) { | |
11529 | if (old_conn_state->best_encoder == &encoder->base) | |
11530 | found = true; | |
11531 | ||
11532 | if (new_conn_state->best_encoder != &encoder->base) | |
8af6cf88 | 11533 | continue; |
86b04268 | 11534 | found = enabled = true; |
ad3c558f | 11535 | |
86b04268 | 11536 | I915_STATE_WARN(new_conn_state->crtc != |
ad3c558f ML |
11537 | encoder->base.crtc, |
11538 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 11539 | } |
86b04268 DV |
11540 | |
11541 | if (!found) | |
11542 | continue; | |
0e32b39c | 11543 | |
e2c719b7 | 11544 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11545 | "encoder's enabled state mismatch " |
11546 | "(expected %i, found %i)\n", | |
11547 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
11548 | |
11549 | if (!encoder->base.crtc) { | |
4d20cd86 | 11550 | bool active; |
7c60d198 | 11551 | |
4d20cd86 ML |
11552 | active = encoder->get_hw_state(encoder, &pipe); |
11553 | I915_STATE_WARN(active, | |
11554 | "encoder detached but still enabled on pipe %c.\n", | |
11555 | pipe_name(pipe)); | |
7c60d198 | 11556 | } |
8af6cf88 | 11557 | } |
91d1b4bd DV |
11558 | } |
11559 | ||
11560 | static void | |
c0ead703 ML |
11561 | verify_crtc_state(struct drm_crtc *crtc, |
11562 | struct drm_crtc_state *old_crtc_state, | |
11563 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 11564 | { |
e7c84544 | 11565 | struct drm_device *dev = crtc->dev; |
fac5e23e | 11566 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 11567 | struct intel_encoder *encoder; |
e7c84544 ML |
11568 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11569 | struct intel_crtc_state *pipe_config, *sw_config; | |
11570 | struct drm_atomic_state *old_state; | |
11571 | bool active; | |
045ac3b5 | 11572 | |
e7c84544 | 11573 | old_state = old_crtc_state->state; |
ec2dc6a0 | 11574 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
11575 | pipe_config = to_intel_crtc_state(old_crtc_state); |
11576 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
11577 | pipe_config->base.crtc = crtc; | |
11578 | pipe_config->base.state = old_state; | |
8af6cf88 | 11579 | |
78108b7c | 11580 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 11581 | |
e7c84544 | 11582 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 11583 | |
e56134bc VS |
11584 | /* we keep both pipes enabled on 830 */ |
11585 | if (IS_I830(dev_priv)) | |
e7c84544 | 11586 | active = new_crtc_state->active; |
6c49f241 | 11587 | |
e7c84544 ML |
11588 | I915_STATE_WARN(new_crtc_state->active != active, |
11589 | "crtc active state doesn't match with hw state " | |
11590 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 11591 | |
e7c84544 ML |
11592 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
11593 | "transitional active state does not match atomic hw state " | |
11594 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 11595 | |
e7c84544 ML |
11596 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
11597 | enum pipe pipe; | |
4d20cd86 | 11598 | |
e7c84544 ML |
11599 | active = encoder->get_hw_state(encoder, &pipe); |
11600 | I915_STATE_WARN(active != new_crtc_state->active, | |
11601 | "[ENCODER:%i] active %i with crtc active %i\n", | |
11602 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 11603 | |
e7c84544 ML |
11604 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
11605 | "Encoder connected to wrong pipe %c\n", | |
11606 | pipe_name(pipe)); | |
4d20cd86 | 11607 | |
253c84c8 VS |
11608 | if (active) { |
11609 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 11610 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 11611 | } |
e7c84544 | 11612 | } |
53d9f4e9 | 11613 | |
a7d1b3f4 VS |
11614 | intel_crtc_compute_pixel_rate(pipe_config); |
11615 | ||
e7c84544 ML |
11616 | if (!new_crtc_state->active) |
11617 | return; | |
cfb23ed6 | 11618 | |
e7c84544 | 11619 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 11620 | |
749d98b8 | 11621 | sw_config = to_intel_crtc_state(new_crtc_state); |
6315b5d3 | 11622 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
11623 | pipe_config, false)) { |
11624 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
11625 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
11626 | "[hw state]"); | |
11627 | intel_dump_pipe_config(intel_crtc, sw_config, | |
11628 | "[sw state]"); | |
8af6cf88 DV |
11629 | } |
11630 | } | |
11631 | ||
91d1b4bd | 11632 | static void |
c0ead703 ML |
11633 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
11634 | struct intel_shared_dpll *pll, | |
11635 | struct drm_crtc *crtc, | |
11636 | struct drm_crtc_state *new_state) | |
91d1b4bd | 11637 | { |
91d1b4bd | 11638 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
11639 | unsigned crtc_mask; |
11640 | bool active; | |
5358901f | 11641 | |
e7c84544 | 11642 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 11643 | |
e7c84544 | 11644 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 11645 | |
e7c84544 | 11646 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 11647 | |
e7c84544 ML |
11648 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
11649 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
11650 | "pll in active use but not on in sw tracking\n"); | |
11651 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
11652 | "pll is on but not used by any active crtc\n"); | |
11653 | I915_STATE_WARN(pll->on != active, | |
11654 | "pll on state mismatch (expected %i, found %i)\n", | |
11655 | pll->on, active); | |
11656 | } | |
5358901f | 11657 | |
e7c84544 | 11658 | if (!crtc) { |
2c42e535 | 11659 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 11660 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 11661 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 11662 | |
e7c84544 ML |
11663 | return; |
11664 | } | |
11665 | ||
11666 | crtc_mask = 1 << drm_crtc_index(crtc); | |
11667 | ||
11668 | if (new_state->active) | |
11669 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
11670 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
11671 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
11672 | else | |
11673 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11674 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
11675 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 11676 | |
2c42e535 | 11677 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 11678 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 11679 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 11680 | |
2c42e535 | 11681 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
11682 | &dpll_hw_state, |
11683 | sizeof(dpll_hw_state)), | |
11684 | "pll hw state mismatch\n"); | |
11685 | } | |
11686 | ||
11687 | static void | |
c0ead703 ML |
11688 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
11689 | struct drm_crtc_state *old_crtc_state, | |
11690 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 11691 | { |
fac5e23e | 11692 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11693 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
11694 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
11695 | ||
11696 | if (new_state->shared_dpll) | |
c0ead703 | 11697 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
11698 | |
11699 | if (old_state->shared_dpll && | |
11700 | old_state->shared_dpll != new_state->shared_dpll) { | |
11701 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
11702 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
11703 | ||
11704 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11705 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
11706 | pipe_name(drm_crtc_index(crtc))); | |
2c42e535 | 11707 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 ML |
11708 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
11709 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 11710 | } |
8af6cf88 DV |
11711 | } |
11712 | ||
e7c84544 | 11713 | static void |
c0ead703 | 11714 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
11715 | struct drm_atomic_state *state, |
11716 | struct drm_crtc_state *old_state, | |
11717 | struct drm_crtc_state *new_state) | |
e7c84544 | 11718 | { |
5a21b665 DV |
11719 | if (!needs_modeset(new_state) && |
11720 | !to_intel_crtc_state(new_state)->update_pipe) | |
11721 | return; | |
11722 | ||
c0ead703 | 11723 | verify_wm_state(crtc, new_state); |
677100ce | 11724 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
11725 | verify_crtc_state(crtc, old_state, new_state); |
11726 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
11727 | } |
11728 | ||
11729 | static void | |
c0ead703 | 11730 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 11731 | { |
fac5e23e | 11732 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11733 | int i; |
11734 | ||
11735 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 11736 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
11737 | } |
11738 | ||
11739 | static void | |
677100ce ML |
11740 | intel_modeset_verify_disabled(struct drm_device *dev, |
11741 | struct drm_atomic_state *state) | |
e7c84544 | 11742 | { |
86b04268 | 11743 | verify_encoder_state(dev, state); |
677100ce | 11744 | verify_connector_state(dev, state, NULL); |
c0ead703 | 11745 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
11746 | } |
11747 | ||
80715b2f VS |
11748 | static void update_scanline_offset(struct intel_crtc *crtc) |
11749 | { | |
4f8036a2 | 11750 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
11751 | |
11752 | /* | |
11753 | * The scanline counter increments at the leading edge of hsync. | |
11754 | * | |
11755 | * On most platforms it starts counting from vtotal-1 on the | |
11756 | * first active line. That means the scanline counter value is | |
11757 | * always one less than what we would expect. Ie. just after | |
11758 | * start of vblank, which also occurs at start of hsync (on the | |
11759 | * last active line), the scanline counter will read vblank_start-1. | |
11760 | * | |
11761 | * On gen2 the scanline counter starts counting from 1 instead | |
11762 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11763 | * to keep the value positive), instead of adding one. | |
11764 | * | |
11765 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11766 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11767 | * there's an extra 1 line difference. So we need to add two instead of | |
11768 | * one to the value. | |
ec1b4ee2 VS |
11769 | * |
11770 | * On VLV/CHV DSI the scanline counter would appear to increment | |
11771 | * approx. 1/3 of a scanline before start of vblank. Unfortunately | |
11772 | * that means we can't tell whether we're in vblank or not while | |
11773 | * we're on that particular line. We must still set scanline_offset | |
11774 | * to 1 so that the vblank timestamps come out correct when we query | |
11775 | * the scanline counter from within the vblank interrupt handler. | |
11776 | * However if queried just before the start of vblank we'll get an | |
11777 | * answer that's slightly in the future. | |
80715b2f | 11778 | */ |
4f8036a2 | 11779 | if (IS_GEN2(dev_priv)) { |
124abe07 | 11780 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11781 | int vtotal; |
11782 | ||
124abe07 VS |
11783 | vtotal = adjusted_mode->crtc_vtotal; |
11784 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
11785 | vtotal /= 2; |
11786 | ||
11787 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 11788 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 11789 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11790 | crtc->scanline_offset = 2; |
11791 | } else | |
11792 | crtc->scanline_offset = 1; | |
11793 | } | |
11794 | ||
ad421372 | 11795 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 11796 | { |
225da59b | 11797 | struct drm_device *dev = state->dev; |
ed6739ef | 11798 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 11799 | struct drm_crtc *crtc; |
aa5e9b47 | 11800 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
0a9ab303 | 11801 | int i; |
ed6739ef ACO |
11802 | |
11803 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 11804 | return; |
ed6739ef | 11805 | |
aa5e9b47 | 11806 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
fb1a38a9 | 11807 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd | 11808 | struct intel_shared_dpll *old_dpll = |
aa5e9b47 | 11809 | to_intel_crtc_state(old_crtc_state)->shared_dpll; |
0a9ab303 | 11810 | |
aa5e9b47 | 11811 | if (!needs_modeset(new_crtc_state)) |
225da59b ACO |
11812 | continue; |
11813 | ||
aa5e9b47 | 11814 | to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 11815 | |
8106ddbd | 11816 | if (!old_dpll) |
fb1a38a9 | 11817 | continue; |
0a9ab303 | 11818 | |
a1c414ee | 11819 | intel_release_shared_dpll(old_dpll, intel_crtc, state); |
ad421372 | 11820 | } |
ed6739ef ACO |
11821 | } |
11822 | ||
99d736a2 ML |
11823 | /* |
11824 | * This implements the workaround described in the "notes" section of the mode | |
11825 | * set sequence documentation. When going from no pipes or single pipe to | |
11826 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
11827 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
11828 | */ | |
11829 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
11830 | { | |
11831 | struct drm_crtc_state *crtc_state; | |
11832 | struct intel_crtc *intel_crtc; | |
11833 | struct drm_crtc *crtc; | |
11834 | struct intel_crtc_state *first_crtc_state = NULL; | |
11835 | struct intel_crtc_state *other_crtc_state = NULL; | |
11836 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
11837 | int i; | |
11838 | ||
11839 | /* look at all crtc's that are going to be enabled in during modeset */ | |
aa5e9b47 | 11840 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
99d736a2 ML |
11841 | intel_crtc = to_intel_crtc(crtc); |
11842 | ||
11843 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
11844 | continue; | |
11845 | ||
11846 | if (first_crtc_state) { | |
11847 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
11848 | break; | |
11849 | } else { | |
11850 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
11851 | first_pipe = intel_crtc->pipe; | |
11852 | } | |
11853 | } | |
11854 | ||
11855 | /* No workaround needed? */ | |
11856 | if (!first_crtc_state) | |
11857 | return 0; | |
11858 | ||
11859 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
11860 | for_each_intel_crtc(state->dev, intel_crtc) { | |
11861 | struct intel_crtc_state *pipe_config; | |
11862 | ||
11863 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
11864 | if (IS_ERR(pipe_config)) | |
11865 | return PTR_ERR(pipe_config); | |
11866 | ||
11867 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
11868 | ||
11869 | if (!pipe_config->base.active || | |
11870 | needs_modeset(&pipe_config->base)) | |
11871 | continue; | |
11872 | ||
11873 | /* 2 or more enabled crtcs means no need for w/a */ | |
11874 | if (enabled_pipe != INVALID_PIPE) | |
11875 | return 0; | |
11876 | ||
11877 | enabled_pipe = intel_crtc->pipe; | |
11878 | } | |
11879 | ||
11880 | if (enabled_pipe != INVALID_PIPE) | |
11881 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
11882 | else if (other_crtc_state) | |
11883 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
11884 | ||
11885 | return 0; | |
11886 | } | |
11887 | ||
8d96561a VS |
11888 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
11889 | { | |
11890 | struct drm_crtc *crtc; | |
11891 | ||
11892 | /* Add all pipes to the state */ | |
11893 | for_each_crtc(state->dev, crtc) { | |
11894 | struct drm_crtc_state *crtc_state; | |
11895 | ||
11896 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
11897 | if (IS_ERR(crtc_state)) | |
11898 | return PTR_ERR(crtc_state); | |
11899 | } | |
11900 | ||
11901 | return 0; | |
11902 | } | |
11903 | ||
27c329ed ML |
11904 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
11905 | { | |
11906 | struct drm_crtc *crtc; | |
27c329ed | 11907 | |
8d96561a VS |
11908 | /* |
11909 | * Add all pipes to the state, and force | |
11910 | * a modeset on all the active ones. | |
11911 | */ | |
27c329ed | 11912 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
11913 | struct drm_crtc_state *crtc_state; |
11914 | int ret; | |
11915 | ||
27c329ed ML |
11916 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
11917 | if (IS_ERR(crtc_state)) | |
11918 | return PTR_ERR(crtc_state); | |
11919 | ||
11920 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
11921 | continue; | |
11922 | ||
11923 | crtc_state->mode_changed = true; | |
11924 | ||
11925 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
11926 | if (ret) | |
9780aad5 | 11927 | return ret; |
27c329ed ML |
11928 | |
11929 | ret = drm_atomic_add_affected_planes(state, crtc); | |
11930 | if (ret) | |
9780aad5 | 11931 | return ret; |
27c329ed ML |
11932 | } |
11933 | ||
9780aad5 | 11934 | return 0; |
27c329ed ML |
11935 | } |
11936 | ||
c347a676 | 11937 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 11938 | { |
565602d7 | 11939 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 11940 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 | 11941 | struct drm_crtc *crtc; |
aa5e9b47 | 11942 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
565602d7 | 11943 | int ret = 0, i; |
054518dd | 11944 | |
b359283a ML |
11945 | if (!check_digital_port_conflicts(state)) { |
11946 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
11947 | return -EINVAL; | |
11948 | } | |
11949 | ||
565602d7 ML |
11950 | intel_state->modeset = true; |
11951 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
bb0f4aab VS |
11952 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
11953 | intel_state->cdclk.actual = dev_priv->cdclk.actual; | |
565602d7 | 11954 | |
aa5e9b47 ML |
11955 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
11956 | if (new_crtc_state->active) | |
565602d7 ML |
11957 | intel_state->active_crtcs |= 1 << i; |
11958 | else | |
11959 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 | 11960 | |
aa5e9b47 | 11961 | if (old_crtc_state->active != new_crtc_state->active) |
8b4a7d05 | 11962 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); |
565602d7 ML |
11963 | } |
11964 | ||
054518dd ACO |
11965 | /* |
11966 | * See if the config requires any additional preparation, e.g. | |
11967 | * to adjust global state with pipes off. We need to do this | |
11968 | * here so we can get the modeset_pipe updated config for the new | |
11969 | * mode set on this crtc. For other crtcs we need to use the | |
11970 | * adjusted_mode bits in the crtc directly. | |
11971 | */ | |
27c329ed | 11972 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed | 11973 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
11974 | if (ret < 0) |
11975 | return ret; | |
27c329ed | 11976 | |
8d96561a | 11977 | /* |
bb0f4aab | 11978 | * Writes to dev_priv->cdclk.logical must protected by |
8d96561a VS |
11979 | * holding all the crtc locks, even if we don't end up |
11980 | * touching the hardware | |
11981 | */ | |
bb0f4aab VS |
11982 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical, |
11983 | &intel_state->cdclk.logical)) { | |
8d96561a VS |
11984 | ret = intel_lock_all_pipes(state); |
11985 | if (ret < 0) | |
11986 | return ret; | |
11987 | } | |
11988 | ||
11989 | /* All pipes must be switched off while we change the cdclk. */ | |
bb0f4aab VS |
11990 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual, |
11991 | &intel_state->cdclk.actual)) { | |
27c329ed | 11992 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
11993 | if (ret < 0) |
11994 | return ret; | |
11995 | } | |
e8788cbc | 11996 | |
bb0f4aab VS |
11997 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", |
11998 | intel_state->cdclk.logical.cdclk, | |
11999 | intel_state->cdclk.actual.cdclk); | |
e0ca7a6b | 12000 | } else { |
bb0f4aab | 12001 | to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12002 | } |
054518dd | 12003 | |
ad421372 | 12004 | intel_modeset_clear_plls(state); |
054518dd | 12005 | |
565602d7 | 12006 | if (IS_HASWELL(dev_priv)) |
ad421372 | 12007 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 12008 | |
ad421372 | 12009 | return 0; |
c347a676 ACO |
12010 | } |
12011 | ||
aa363136 MR |
12012 | /* |
12013 | * Handle calculation of various watermark data at the end of the atomic check | |
12014 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
12015 | * handlers to ensure that all derived state has been updated. | |
12016 | */ | |
55994c2c | 12017 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
12018 | { |
12019 | struct drm_device *dev = state->dev; | |
98d39494 | 12020 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
12021 | |
12022 | /* Is there platform-specific watermark information to calculate? */ | |
12023 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
12024 | return dev_priv->display.compute_global_watermarks(state); |
12025 | ||
12026 | return 0; | |
aa363136 MR |
12027 | } |
12028 | ||
74c090b1 ML |
12029 | /** |
12030 | * intel_atomic_check - validate state object | |
12031 | * @dev: drm device | |
12032 | * @state: state to validate | |
12033 | */ | |
12034 | static int intel_atomic_check(struct drm_device *dev, | |
12035 | struct drm_atomic_state *state) | |
c347a676 | 12036 | { |
dd8b3bdb | 12037 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 12038 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 | 12039 | struct drm_crtc *crtc; |
aa5e9b47 | 12040 | struct drm_crtc_state *old_crtc_state, *crtc_state; |
c347a676 | 12041 | int ret, i; |
61333b60 | 12042 | bool any_ms = false; |
c347a676 | 12043 | |
74c090b1 | 12044 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
12045 | if (ret) |
12046 | return ret; | |
12047 | ||
aa5e9b47 | 12048 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) { |
cfb23ed6 ML |
12049 | struct intel_crtc_state *pipe_config = |
12050 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
12051 | |
12052 | /* Catch I915_MODE_FLAG_INHERITED */ | |
aa5e9b47 | 12053 | if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags) |
1ed51de9 | 12054 | crtc_state->mode_changed = true; |
cfb23ed6 | 12055 | |
af4a879e | 12056 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
12057 | continue; |
12058 | ||
af4a879e DV |
12059 | if (!crtc_state->enable) { |
12060 | any_ms = true; | |
cfb23ed6 | 12061 | continue; |
af4a879e | 12062 | } |
cfb23ed6 | 12063 | |
26495481 DV |
12064 | /* FIXME: For only active_changed we shouldn't need to do any |
12065 | * state recomputation at all. */ | |
12066 | ||
1ed51de9 DV |
12067 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12068 | if (ret) | |
12069 | return ret; | |
b359283a | 12070 | |
cfb23ed6 | 12071 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
12072 | if (ret) { |
12073 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12074 | pipe_config, "[failed]"); | |
c347a676 | 12075 | return ret; |
25aa1c39 | 12076 | } |
c347a676 | 12077 | |
4f044a88 | 12078 | if (i915_modparams.fastboot && |
6315b5d3 | 12079 | intel_pipe_config_compare(dev_priv, |
aa5e9b47 | 12080 | to_intel_crtc_state(old_crtc_state), |
1ed51de9 | 12081 | pipe_config, true)) { |
26495481 | 12082 | crtc_state->mode_changed = false; |
aa5e9b47 | 12083 | pipe_config->update_pipe = true; |
26495481 DV |
12084 | } |
12085 | ||
af4a879e | 12086 | if (needs_modeset(crtc_state)) |
26495481 | 12087 | any_ms = true; |
cfb23ed6 | 12088 | |
af4a879e DV |
12089 | ret = drm_atomic_add_affected_planes(state, crtc); |
12090 | if (ret) | |
12091 | return ret; | |
61333b60 | 12092 | |
26495481 DV |
12093 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12094 | needs_modeset(crtc_state) ? | |
12095 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
12096 | } |
12097 | ||
61333b60 ML |
12098 | if (any_ms) { |
12099 | ret = intel_modeset_checks(state); | |
12100 | ||
12101 | if (ret) | |
12102 | return ret; | |
e0ca7a6b | 12103 | } else { |
bb0f4aab | 12104 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12105 | } |
76305b1a | 12106 | |
dd8b3bdb | 12107 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
12108 | if (ret) |
12109 | return ret; | |
12110 | ||
f51be2e0 | 12111 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 12112 | return calc_watermark_data(state); |
054518dd ACO |
12113 | } |
12114 | ||
5008e874 | 12115 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 12116 | struct drm_atomic_state *state) |
5008e874 | 12117 | { |
fd70075f | 12118 | return drm_atomic_helper_prepare_planes(dev, state); |
5008e874 ML |
12119 | } |
12120 | ||
a2991414 ML |
12121 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
12122 | { | |
12123 | struct drm_device *dev = crtc->base.dev; | |
12124 | ||
12125 | if (!dev->max_vblank_count) | |
ca814b25 | 12126 | return drm_crtc_accurate_vblank_count(&crtc->base); |
a2991414 ML |
12127 | |
12128 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
12129 | } | |
12130 | ||
896e5bb0 L |
12131 | static void intel_update_crtc(struct drm_crtc *crtc, |
12132 | struct drm_atomic_state *state, | |
12133 | struct drm_crtc_state *old_crtc_state, | |
b44d5c0c | 12134 | struct drm_crtc_state *new_crtc_state) |
896e5bb0 L |
12135 | { |
12136 | struct drm_device *dev = crtc->dev; | |
12137 | struct drm_i915_private *dev_priv = to_i915(dev); | |
12138 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
aa5e9b47 ML |
12139 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); |
12140 | bool modeset = needs_modeset(new_crtc_state); | |
896e5bb0 L |
12141 | |
12142 | if (modeset) { | |
12143 | update_scanline_offset(intel_crtc); | |
12144 | dev_priv->display.crtc_enable(pipe_config, state); | |
12145 | } else { | |
aa5e9b47 ML |
12146 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12147 | pipe_config); | |
896e5bb0 L |
12148 | } |
12149 | ||
12150 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12151 | intel_fbc_enable( | |
12152 | intel_crtc, pipe_config, | |
12153 | to_intel_plane_state(crtc->primary->state)); | |
12154 | } | |
12155 | ||
12156 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
896e5bb0 L |
12157 | } |
12158 | ||
b44d5c0c | 12159 | static void intel_update_crtcs(struct drm_atomic_state *state) |
896e5bb0 L |
12160 | { |
12161 | struct drm_crtc *crtc; | |
aa5e9b47 | 12162 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
896e5bb0 L |
12163 | int i; |
12164 | ||
aa5e9b47 ML |
12165 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
12166 | if (!new_crtc_state->active) | |
896e5bb0 L |
12167 | continue; |
12168 | ||
12169 | intel_update_crtc(crtc, state, old_crtc_state, | |
b44d5c0c | 12170 | new_crtc_state); |
896e5bb0 L |
12171 | } |
12172 | } | |
12173 | ||
b44d5c0c | 12174 | static void skl_update_crtcs(struct drm_atomic_state *state) |
27082493 | 12175 | { |
0f0f74bc | 12176 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
12177 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
12178 | struct drm_crtc *crtc; | |
ce0ba283 | 12179 | struct intel_crtc *intel_crtc; |
aa5e9b47 | 12180 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
ce0ba283 | 12181 | struct intel_crtc_state *cstate; |
27082493 L |
12182 | unsigned int updated = 0; |
12183 | bool progress; | |
12184 | enum pipe pipe; | |
5eff503b ML |
12185 | int i; |
12186 | ||
12187 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
12188 | ||
aa5e9b47 | 12189 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) |
5eff503b | 12190 | /* ignore allocations for crtc's that have been turned off. */ |
aa5e9b47 | 12191 | if (new_crtc_state->active) |
5eff503b | 12192 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; |
27082493 L |
12193 | |
12194 | /* | |
12195 | * Whenever the number of active pipes changes, we need to make sure we | |
12196 | * update the pipes in the right order so that their ddb allocations | |
12197 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
12198 | * cause pipe underruns and other bad stuff. | |
12199 | */ | |
12200 | do { | |
27082493 L |
12201 | progress = false; |
12202 | ||
aa5e9b47 | 12203 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
27082493 L |
12204 | bool vbl_wait = false; |
12205 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
12206 | |
12207 | intel_crtc = to_intel_crtc(crtc); | |
21794813 | 12208 | cstate = to_intel_crtc_state(new_crtc_state); |
ce0ba283 | 12209 | pipe = intel_crtc->pipe; |
27082493 | 12210 | |
5eff503b | 12211 | if (updated & cmask || !cstate->base.active) |
27082493 | 12212 | continue; |
5eff503b ML |
12213 | |
12214 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
12215 | continue; |
12216 | ||
12217 | updated |= cmask; | |
5eff503b | 12218 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
12219 | |
12220 | /* | |
12221 | * If this is an already active pipe, it's DDB changed, | |
12222 | * and this isn't the last pipe that needs updating | |
12223 | * then we need to wait for a vblank to pass for the | |
12224 | * new ddb allocation to take effect. | |
12225 | */ | |
ce0ba283 | 12226 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 12227 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
aa5e9b47 | 12228 | !new_crtc_state->active_changed && |
27082493 L |
12229 | intel_state->wm_results.dirty_pipes != updated) |
12230 | vbl_wait = true; | |
12231 | ||
12232 | intel_update_crtc(crtc, state, old_crtc_state, | |
b44d5c0c | 12233 | new_crtc_state); |
27082493 L |
12234 | |
12235 | if (vbl_wait) | |
0f0f74bc | 12236 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
12237 | |
12238 | progress = true; | |
12239 | } | |
12240 | } while (progress); | |
12241 | } | |
12242 | ||
ba318c61 CW |
12243 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
12244 | { | |
12245 | struct intel_atomic_state *state, *next; | |
12246 | struct llist_node *freed; | |
12247 | ||
12248 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
12249 | llist_for_each_entry_safe(state, next, freed, freed) | |
12250 | drm_atomic_state_put(&state->base); | |
12251 | } | |
12252 | ||
12253 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
12254 | { | |
12255 | struct drm_i915_private *dev_priv = | |
12256 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
12257 | ||
12258 | intel_atomic_helper_free_state(dev_priv); | |
12259 | } | |
12260 | ||
9db529aa DV |
12261 | static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) |
12262 | { | |
12263 | struct wait_queue_entry wait_fence, wait_reset; | |
12264 | struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); | |
12265 | ||
12266 | init_wait_entry(&wait_fence, 0); | |
12267 | init_wait_entry(&wait_reset, 0); | |
12268 | for (;;) { | |
12269 | prepare_to_wait(&intel_state->commit_ready.wait, | |
12270 | &wait_fence, TASK_UNINTERRUPTIBLE); | |
12271 | prepare_to_wait(&dev_priv->gpu_error.wait_queue, | |
12272 | &wait_reset, TASK_UNINTERRUPTIBLE); | |
12273 | ||
12274 | ||
12275 | if (i915_sw_fence_done(&intel_state->commit_ready) | |
12276 | || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags)) | |
12277 | break; | |
12278 | ||
12279 | schedule(); | |
12280 | } | |
12281 | finish_wait(&intel_state->commit_ready.wait, &wait_fence); | |
12282 | finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset); | |
12283 | } | |
12284 | ||
94f05024 | 12285 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 12286 | { |
94f05024 | 12287 | struct drm_device *dev = state->dev; |
565602d7 | 12288 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12289 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa5e9b47 | 12290 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
7580d774 | 12291 | struct drm_crtc *crtc; |
5a21b665 | 12292 | struct intel_crtc_state *intel_cstate; |
d8fc70b7 | 12293 | u64 put_domains[I915_MAX_PIPES] = {}; |
e95433c7 | 12294 | int i; |
a6778b3c | 12295 | |
9db529aa | 12296 | intel_atomic_commit_fence_wait(intel_state); |
42b062b0 | 12297 | |
ea0000f0 DV |
12298 | drm_atomic_helper_wait_for_dependencies(state); |
12299 | ||
c3b32658 | 12300 | if (intel_state->modeset) |
5a21b665 | 12301 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 12302 | |
aa5e9b47 | 12303 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
a539205a ML |
12304 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12305 | ||
aa5e9b47 ML |
12306 | if (needs_modeset(new_crtc_state) || |
12307 | to_intel_crtc_state(new_crtc_state)->update_pipe) { | |
5a21b665 DV |
12308 | |
12309 | put_domains[to_intel_crtc(crtc)->pipe] = | |
12310 | modeset_get_crtc_power_domains(crtc, | |
aa5e9b47 | 12311 | to_intel_crtc_state(new_crtc_state)); |
5a21b665 DV |
12312 | } |
12313 | ||
aa5e9b47 | 12314 | if (!needs_modeset(new_crtc_state)) |
61333b60 ML |
12315 | continue; |
12316 | ||
aa5e9b47 ML |
12317 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12318 | to_intel_crtc_state(new_crtc_state)); | |
460da916 | 12319 | |
29ceb0e6 VS |
12320 | if (old_crtc_state->active) { |
12321 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 12322 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 12323 | intel_crtc->active = false; |
58f9c0bc | 12324 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 12325 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
12326 | |
12327 | /* | |
12328 | * Underruns don't always raise | |
12329 | * interrupts, so check manually. | |
12330 | */ | |
12331 | intel_check_cpu_fifo_underruns(dev_priv); | |
12332 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 12333 | |
21794813 | 12334 | if (!new_crtc_state->active) { |
e62929b3 ML |
12335 | /* |
12336 | * Make sure we don't call initial_watermarks | |
12337 | * for ILK-style watermark updates. | |
ff32c54e VS |
12338 | * |
12339 | * No clue what this is supposed to achieve. | |
e62929b3 | 12340 | */ |
ff32c54e | 12341 | if (INTEL_GEN(dev_priv) >= 9) |
e62929b3 | 12342 | dev_priv->display.initial_watermarks(intel_state, |
21794813 | 12343 | to_intel_crtc_state(new_crtc_state)); |
e62929b3 | 12344 | } |
a539205a | 12345 | } |
b8cecdf5 | 12346 | } |
7758a113 | 12347 | |
ea9d758d DV |
12348 | /* Only after disabling all output pipelines that will be changed can we |
12349 | * update the the output configuration. */ | |
4740b0f2 | 12350 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 12351 | |
565602d7 | 12352 | if (intel_state->modeset) { |
4740b0f2 | 12353 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 | 12354 | |
b0587e4d | 12355 | intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
f6d1973d | 12356 | |
656d1b89 L |
12357 | /* |
12358 | * SKL workaround: bspec recommends we disable the SAGV when we | |
12359 | * have more then one pipe enabled | |
12360 | */ | |
56feca91 | 12361 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 12362 | intel_disable_sagv(dev_priv); |
656d1b89 | 12363 | |
677100ce | 12364 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 12365 | } |
47fab737 | 12366 | |
896e5bb0 | 12367 | /* Complete the events for pipes that have now been disabled */ |
aa5e9b47 ML |
12368 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12369 | bool modeset = needs_modeset(new_crtc_state); | |
80715b2f | 12370 | |
1f7528c4 | 12371 | /* Complete events for now disable pipes here. */ |
aa5e9b47 | 12372 | if (modeset && !new_crtc_state->active && new_crtc_state->event) { |
1f7528c4 | 12373 | spin_lock_irq(&dev->event_lock); |
aa5e9b47 | 12374 | drm_crtc_send_vblank_event(crtc, new_crtc_state->event); |
1f7528c4 DV |
12375 | spin_unlock_irq(&dev->event_lock); |
12376 | ||
aa5e9b47 | 12377 | new_crtc_state->event = NULL; |
1f7528c4 | 12378 | } |
177246a8 MR |
12379 | } |
12380 | ||
896e5bb0 | 12381 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
b44d5c0c | 12382 | dev_priv->display.update_crtcs(state); |
896e5bb0 | 12383 | |
94f05024 DV |
12384 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
12385 | * already, but still need the state for the delayed optimization. To | |
12386 | * fix this: | |
12387 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
12388 | * - schedule that vblank worker _before_ calling hw_done | |
12389 | * - at the start of commit_tail, cancel it _synchrously | |
12390 | * - switch over to the vblank wait helper in the core after that since | |
12391 | * we don't need out special handling any more. | |
12392 | */ | |
b44d5c0c | 12393 | drm_atomic_helper_wait_for_flip_done(dev, state); |
5a21b665 DV |
12394 | |
12395 | /* | |
12396 | * Now that the vblank has passed, we can go ahead and program the | |
12397 | * optimal watermarks on platforms that need two-step watermark | |
12398 | * programming. | |
12399 | * | |
12400 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
12401 | */ | |
aa5e9b47 ML |
12402 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12403 | intel_cstate = to_intel_crtc_state(new_crtc_state); | |
5a21b665 DV |
12404 | |
12405 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
12406 | dev_priv->display.optimize_watermarks(intel_state, |
12407 | intel_cstate); | |
5a21b665 DV |
12408 | } |
12409 | ||
aa5e9b47 | 12410 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
5a21b665 DV |
12411 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); |
12412 | ||
12413 | if (put_domains[i]) | |
12414 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
12415 | ||
aa5e9b47 | 12416 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); |
5a21b665 DV |
12417 | } |
12418 | ||
56feca91 | 12419 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 12420 | intel_enable_sagv(dev_priv); |
656d1b89 | 12421 | |
94f05024 DV |
12422 | drm_atomic_helper_commit_hw_done(state); |
12423 | ||
d5553c09 CW |
12424 | if (intel_state->modeset) { |
12425 | /* As one of the primary mmio accessors, KMS has a high | |
12426 | * likelihood of triggering bugs in unclaimed access. After we | |
12427 | * finish modesetting, see if an error has been flagged, and if | |
12428 | * so enable debugging for the next modeset - and hope we catch | |
12429 | * the culprit. | |
12430 | */ | |
12431 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
5a21b665 | 12432 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
d5553c09 | 12433 | } |
5a21b665 | 12434 | |
5a21b665 | 12435 | drm_atomic_helper_cleanup_planes(dev, state); |
5a21b665 | 12436 | |
ea0000f0 DV |
12437 | drm_atomic_helper_commit_cleanup_done(state); |
12438 | ||
0853695c | 12439 | drm_atomic_state_put(state); |
f30da187 | 12440 | |
ba318c61 | 12441 | intel_atomic_helper_free_state(dev_priv); |
94f05024 DV |
12442 | } |
12443 | ||
12444 | static void intel_atomic_commit_work(struct work_struct *work) | |
12445 | { | |
c004a90b CW |
12446 | struct drm_atomic_state *state = |
12447 | container_of(work, struct drm_atomic_state, commit_work); | |
12448 | ||
94f05024 DV |
12449 | intel_atomic_commit_tail(state); |
12450 | } | |
12451 | ||
c004a90b CW |
12452 | static int __i915_sw_fence_call |
12453 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
12454 | enum i915_sw_fence_notify notify) | |
12455 | { | |
12456 | struct intel_atomic_state *state = | |
12457 | container_of(fence, struct intel_atomic_state, commit_ready); | |
12458 | ||
12459 | switch (notify) { | |
12460 | case FENCE_COMPLETE: | |
42b062b0 | 12461 | /* we do blocking waits in the worker, nothing to do here */ |
c004a90b | 12462 | break; |
c004a90b | 12463 | case FENCE_FREE: |
eb955eee CW |
12464 | { |
12465 | struct intel_atomic_helper *helper = | |
12466 | &to_i915(state->base.dev)->atomic_helper; | |
12467 | ||
12468 | if (llist_add(&state->freed, &helper->free_list)) | |
12469 | schedule_work(&helper->free_work); | |
12470 | break; | |
12471 | } | |
c004a90b CW |
12472 | } |
12473 | ||
12474 | return NOTIFY_DONE; | |
12475 | } | |
12476 | ||
6c9c1b38 DV |
12477 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
12478 | { | |
aa5e9b47 | 12479 | struct drm_plane_state *old_plane_state, *new_plane_state; |
6c9c1b38 | 12480 | struct drm_plane *plane; |
6c9c1b38 DV |
12481 | int i; |
12482 | ||
aa5e9b47 | 12483 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) |
faf5bf0a | 12484 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), |
aa5e9b47 | 12485 | intel_fb_obj(new_plane_state->fb), |
faf5bf0a | 12486 | to_intel_plane(plane)->frontbuffer_bit); |
6c9c1b38 DV |
12487 | } |
12488 | ||
94f05024 DV |
12489 | /** |
12490 | * intel_atomic_commit - commit validated state object | |
12491 | * @dev: DRM device | |
12492 | * @state: the top-level driver state object | |
12493 | * @nonblock: nonblocking commit | |
12494 | * | |
12495 | * This function commits a top-level state object that has been validated | |
12496 | * with drm_atomic_helper_check(). | |
12497 | * | |
94f05024 DV |
12498 | * RETURNS |
12499 | * Zero for success or -errno. | |
12500 | */ | |
12501 | static int intel_atomic_commit(struct drm_device *dev, | |
12502 | struct drm_atomic_state *state, | |
12503 | bool nonblock) | |
12504 | { | |
12505 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 12506 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
12507 | int ret = 0; |
12508 | ||
c004a90b CW |
12509 | drm_atomic_state_get(state); |
12510 | i915_sw_fence_init(&intel_state->commit_ready, | |
12511 | intel_atomic_commit_ready); | |
94f05024 | 12512 | |
440df938 VS |
12513 | /* |
12514 | * The intel_legacy_cursor_update() fast path takes care | |
12515 | * of avoiding the vblank waits for simple cursor | |
12516 | * movement and flips. For cursor on/off and size changes, | |
12517 | * we want to perform the vblank waits so that watermark | |
12518 | * updates happen during the correct frames. Gen9+ have | |
12519 | * double buffered watermarks and so shouldn't need this. | |
12520 | * | |
3cf50c63 ML |
12521 | * Unset state->legacy_cursor_update before the call to |
12522 | * drm_atomic_helper_setup_commit() because otherwise | |
12523 | * drm_atomic_helper_wait_for_flip_done() is a noop and | |
12524 | * we get FIFO underruns because we didn't wait | |
12525 | * for vblank. | |
440df938 VS |
12526 | * |
12527 | * FIXME doing watermarks and fb cleanup from a vblank worker | |
12528 | * (assuming we had any) would solve these problems. | |
12529 | */ | |
213f1bd0 ML |
12530 | if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) { |
12531 | struct intel_crtc_state *new_crtc_state; | |
12532 | struct intel_crtc *crtc; | |
12533 | int i; | |
12534 | ||
12535 | for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i) | |
12536 | if (new_crtc_state->wm.need_postvbl_update || | |
12537 | new_crtc_state->update_wm_post) | |
12538 | state->legacy_cursor_update = false; | |
12539 | } | |
440df938 | 12540 | |
3cf50c63 ML |
12541 | ret = intel_atomic_prepare_commit(dev, state); |
12542 | if (ret) { | |
12543 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
12544 | i915_sw_fence_commit(&intel_state->commit_ready); | |
12545 | return ret; | |
12546 | } | |
12547 | ||
12548 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
12549 | if (!ret) | |
12550 | ret = drm_atomic_helper_swap_state(state, true); | |
12551 | ||
0806f4ee ML |
12552 | if (ret) { |
12553 | i915_sw_fence_commit(&intel_state->commit_ready); | |
12554 | ||
0806f4ee | 12555 | drm_atomic_helper_cleanup_planes(dev, state); |
0806f4ee ML |
12556 | return ret; |
12557 | } | |
94f05024 | 12558 | dev_priv->wm.distrust_bios_wm = false; |
3c0fb588 | 12559 | intel_shared_dpll_swap_state(state); |
6c9c1b38 | 12560 | intel_atomic_track_fbs(state); |
94f05024 | 12561 | |
c3b32658 | 12562 | if (intel_state->modeset) { |
d305e061 VS |
12563 | memcpy(dev_priv->min_cdclk, intel_state->min_cdclk, |
12564 | sizeof(intel_state->min_cdclk)); | |
c3b32658 | 12565 | dev_priv->active_crtcs = intel_state->active_crtcs; |
bb0f4aab VS |
12566 | dev_priv->cdclk.logical = intel_state->cdclk.logical; |
12567 | dev_priv->cdclk.actual = intel_state->cdclk.actual; | |
c3b32658 ML |
12568 | } |
12569 | ||
0853695c | 12570 | drm_atomic_state_get(state); |
42b062b0 | 12571 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); |
c004a90b CW |
12572 | |
12573 | i915_sw_fence_commit(&intel_state->commit_ready); | |
42b062b0 DV |
12574 | if (nonblock) |
12575 | queue_work(system_unbound_wq, &state->commit_work); | |
12576 | else | |
94f05024 | 12577 | intel_atomic_commit_tail(state); |
42b062b0 | 12578 | |
75714940 | 12579 | |
74c090b1 | 12580 | return 0; |
7f27126e JB |
12581 | } |
12582 | ||
f6e5b160 | 12583 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
3fab2f09 | 12584 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 12585 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 | 12586 | .destroy = intel_crtc_destroy, |
4c01ded5 | 12587 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
12588 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12589 | .atomic_destroy_state = intel_crtc_destroy_state, | |
8c6b709d | 12590 | .set_crc_source = intel_crtc_set_crc_source, |
f6e5b160 CW |
12591 | }; |
12592 | ||
74d290f8 CW |
12593 | struct wait_rps_boost { |
12594 | struct wait_queue_entry wait; | |
12595 | ||
12596 | struct drm_crtc *crtc; | |
12597 | struct drm_i915_gem_request *request; | |
12598 | }; | |
12599 | ||
12600 | static int do_rps_boost(struct wait_queue_entry *_wait, | |
12601 | unsigned mode, int sync, void *key) | |
12602 | { | |
12603 | struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait); | |
12604 | struct drm_i915_gem_request *rq = wait->request; | |
12605 | ||
12606 | gen6_rps_boost(rq, NULL); | |
12607 | i915_gem_request_put(rq); | |
12608 | ||
12609 | drm_crtc_vblank_put(wait->crtc); | |
12610 | ||
12611 | list_del(&wait->wait.entry); | |
12612 | kfree(wait); | |
12613 | return 1; | |
12614 | } | |
12615 | ||
12616 | static void add_rps_boost_after_vblank(struct drm_crtc *crtc, | |
12617 | struct dma_fence *fence) | |
12618 | { | |
12619 | struct wait_rps_boost *wait; | |
12620 | ||
12621 | if (!dma_fence_is_i915(fence)) | |
12622 | return; | |
12623 | ||
12624 | if (INTEL_GEN(to_i915(crtc->dev)) < 6) | |
12625 | return; | |
12626 | ||
12627 | if (drm_crtc_vblank_get(crtc)) | |
12628 | return; | |
12629 | ||
12630 | wait = kmalloc(sizeof(*wait), GFP_KERNEL); | |
12631 | if (!wait) { | |
12632 | drm_crtc_vblank_put(crtc); | |
12633 | return; | |
12634 | } | |
12635 | ||
12636 | wait->request = to_request(dma_fence_get(fence)); | |
12637 | wait->crtc = crtc; | |
12638 | ||
12639 | wait->wait.func = do_rps_boost; | |
12640 | wait->wait.flags = 0; | |
12641 | ||
12642 | add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait); | |
12643 | } | |
12644 | ||
6beb8c23 MR |
12645 | /** |
12646 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12647 | * @plane: drm plane to prepare for | |
12648 | * @fb: framebuffer to prepare for presentation | |
12649 | * | |
12650 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12651 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12652 | * bits. Some older platforms need special physical address handling for | |
12653 | * cursor planes. | |
12654 | * | |
f935675f ML |
12655 | * Must be called with struct_mutex held. |
12656 | * | |
6beb8c23 MR |
12657 | * Returns 0 on success, negative error code on failure. |
12658 | */ | |
12659 | int | |
12660 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 12661 | struct drm_plane_state *new_state) |
465c120c | 12662 | { |
c004a90b CW |
12663 | struct intel_atomic_state *intel_state = |
12664 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 12665 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 12666 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 12667 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 12668 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 12669 | int ret; |
465c120c | 12670 | |
5008e874 ML |
12671 | if (old_obj) { |
12672 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
12673 | drm_atomic_get_existing_crtc_state(new_state->state, |
12674 | plane->state->crtc); | |
5008e874 ML |
12675 | |
12676 | /* Big Hammer, we also need to ensure that any pending | |
12677 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
12678 | * current scanout is retired before unpinning the old | |
12679 | * framebuffer. Note that we rely on userspace rendering | |
12680 | * into the buffer attached to the pipe they are waiting | |
12681 | * on. If not, userspace generates a GPU hang with IPEHR | |
12682 | * point to the MI_WAIT_FOR_EVENT. | |
12683 | * | |
12684 | * This should only fail upon a hung GPU, in which case we | |
12685 | * can safely continue. | |
12686 | */ | |
c004a90b CW |
12687 | if (needs_modeset(crtc_state)) { |
12688 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
12689 | old_obj->resv, NULL, | |
12690 | false, 0, | |
12691 | GFP_KERNEL); | |
12692 | if (ret < 0) | |
12693 | return ret; | |
f4457ae7 | 12694 | } |
5008e874 ML |
12695 | } |
12696 | ||
c004a90b CW |
12697 | if (new_state->fence) { /* explicit fencing */ |
12698 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
12699 | new_state->fence, | |
12700 | I915_FENCE_TIMEOUT, | |
12701 | GFP_KERNEL); | |
12702 | if (ret < 0) | |
12703 | return ret; | |
12704 | } | |
12705 | ||
c37efb99 CW |
12706 | if (!obj) |
12707 | return 0; | |
12708 | ||
4d3088c7 | 12709 | ret = i915_gem_object_pin_pages(obj); |
fd70075f CW |
12710 | if (ret) |
12711 | return ret; | |
12712 | ||
4d3088c7 CW |
12713 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
12714 | if (ret) { | |
12715 | i915_gem_object_unpin_pages(obj); | |
12716 | return ret; | |
12717 | } | |
12718 | ||
fd70075f CW |
12719 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12720 | INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
12721 | const int align = intel_cursor_alignment(dev_priv); | |
12722 | ||
12723 | ret = i915_gem_object_attach_phys(obj, align); | |
12724 | } else { | |
12725 | struct i915_vma *vma; | |
12726 | ||
12727 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
12728 | if (!IS_ERR(vma)) | |
12729 | to_intel_plane_state(new_state)->vma = vma; | |
12730 | else | |
12731 | ret = PTR_ERR(vma); | |
12732 | } | |
12733 | ||
12734 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
12735 | ||
12736 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4d3088c7 | 12737 | i915_gem_object_unpin_pages(obj); |
fd70075f CW |
12738 | if (ret) |
12739 | return ret; | |
12740 | ||
c004a90b | 12741 | if (!new_state->fence) { /* implicit fencing */ |
74d290f8 CW |
12742 | struct dma_fence *fence; |
12743 | ||
c004a90b CW |
12744 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, |
12745 | obj->resv, NULL, | |
12746 | false, I915_FENCE_TIMEOUT, | |
12747 | GFP_KERNEL); | |
12748 | if (ret < 0) | |
12749 | return ret; | |
74d290f8 CW |
12750 | |
12751 | fence = reservation_object_get_excl_rcu(obj->resv); | |
12752 | if (fence) { | |
12753 | add_rps_boost_after_vblank(new_state->crtc, fence); | |
12754 | dma_fence_put(fence); | |
12755 | } | |
12756 | } else { | |
12757 | add_rps_boost_after_vblank(new_state->crtc, new_state->fence); | |
c004a90b | 12758 | } |
5a21b665 | 12759 | |
d07f0e59 | 12760 | return 0; |
6beb8c23 MR |
12761 | } |
12762 | ||
38f3ce3a MR |
12763 | /** |
12764 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12765 | * @plane: drm plane to clean up for | |
12766 | * @fb: old framebuffer that was on plane | |
12767 | * | |
12768 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
12769 | * |
12770 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
12771 | */ |
12772 | void | |
12773 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 12774 | struct drm_plane_state *old_state) |
38f3ce3a | 12775 | { |
be1e3415 | 12776 | struct i915_vma *vma; |
38f3ce3a | 12777 | |
be1e3415 CW |
12778 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
12779 | vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); | |
fd70075f CW |
12780 | if (vma) { |
12781 | mutex_lock(&plane->dev->struct_mutex); | |
be1e3415 | 12782 | intel_unpin_fb_vma(vma); |
fd70075f CW |
12783 | mutex_unlock(&plane->dev->struct_mutex); |
12784 | } | |
465c120c MR |
12785 | } |
12786 | ||
6156a456 CK |
12787 | int |
12788 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
12789 | { | |
5b7280f0 | 12790 | struct drm_i915_private *dev_priv; |
6156a456 | 12791 | int max_scale; |
5b7280f0 | 12792 | int crtc_clock, max_dotclk; |
6156a456 | 12793 | |
bf8a0af0 | 12794 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
12795 | return DRM_PLANE_HELPER_NO_SCALING; |
12796 | ||
5b7280f0 ACO |
12797 | dev_priv = to_i915(intel_crtc->base.dev); |
12798 | ||
6156a456 | 12799 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
5b7280f0 ACO |
12800 | max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; |
12801 | ||
12802 | if (IS_GEMINILAKE(dev_priv)) | |
12803 | max_dotclk *= 2; | |
6156a456 | 12804 | |
5b7280f0 | 12805 | if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) |
6156a456 CK |
12806 | return DRM_PLANE_HELPER_NO_SCALING; |
12807 | ||
12808 | /* | |
12809 | * skl max scale is lower of: | |
12810 | * close to 3 but not 3, -1 is for that purpose | |
12811 | * or | |
12812 | * cdclk/crtc_clock | |
12813 | */ | |
5b7280f0 ACO |
12814 | max_scale = min((1 << 16) * 3 - 1, |
12815 | (1 << 8) * ((max_dotclk << 8) / crtc_clock)); | |
6156a456 CK |
12816 | |
12817 | return max_scale; | |
12818 | } | |
12819 | ||
465c120c | 12820 | static int |
282dbf9b | 12821 | intel_check_primary_plane(struct intel_plane *plane, |
061e4b8d | 12822 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
12823 | struct intel_plane_state *state) |
12824 | { | |
282dbf9b | 12825 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
2b875c22 | 12826 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 12827 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
12828 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
12829 | bool can_position = false; | |
b63a16f6 | 12830 | int ret; |
465c120c | 12831 | |
b63a16f6 | 12832 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
12833 | /* use scaler when colorkey is not required */ |
12834 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
12835 | min_scale = 1; | |
12836 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
12837 | } | |
d8106366 | 12838 | can_position = true; |
6156a456 | 12839 | } |
d8106366 | 12840 | |
cc926387 DV |
12841 | ret = drm_plane_helper_check_state(&state->base, |
12842 | &state->clip, | |
12843 | min_scale, max_scale, | |
12844 | can_position, true); | |
b63a16f6 VS |
12845 | if (ret) |
12846 | return ret; | |
12847 | ||
cc926387 | 12848 | if (!state->base.fb) |
b63a16f6 VS |
12849 | return 0; |
12850 | ||
12851 | if (INTEL_GEN(dev_priv) >= 9) { | |
12852 | ret = skl_check_plane_surface(state); | |
12853 | if (ret) | |
12854 | return ret; | |
a0864d59 VS |
12855 | |
12856 | state->ctl = skl_plane_ctl(crtc_state, state); | |
12857 | } else { | |
5b7fcc44 VS |
12858 | ret = i9xx_check_plane_surface(state); |
12859 | if (ret) | |
12860 | return ret; | |
12861 | ||
a0864d59 | 12862 | state->ctl = i9xx_plane_ctl(crtc_state, state); |
b63a16f6 VS |
12863 | } |
12864 | ||
12865 | return 0; | |
14af293f GP |
12866 | } |
12867 | ||
5a21b665 DV |
12868 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
12869 | struct drm_crtc_state *old_crtc_state) | |
12870 | { | |
12871 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 12872 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 12873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ccf010fb | 12874 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 12875 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
12876 | struct intel_atomic_state *old_intel_state = |
12877 | to_intel_atomic_state(old_crtc_state->state); | |
d3a8fb32 VS |
12878 | struct intel_crtc_state *intel_cstate = |
12879 | intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc); | |
12880 | bool modeset = needs_modeset(&intel_cstate->base); | |
5a21b665 | 12881 | |
567f0792 ML |
12882 | if (!modeset && |
12883 | (intel_cstate->base.color_mgmt_changed || | |
12884 | intel_cstate->update_pipe)) { | |
5c857e60 VS |
12885 | intel_color_set_csc(&intel_cstate->base); |
12886 | intel_color_load_luts(&intel_cstate->base); | |
567f0792 ML |
12887 | } |
12888 | ||
5a21b665 | 12889 | /* Perform vblank evasion around commit operation */ |
d3a8fb32 | 12890 | intel_pipe_update_start(intel_cstate); |
5a21b665 DV |
12891 | |
12892 | if (modeset) | |
e62929b3 | 12893 | goto out; |
5a21b665 | 12894 | |
ccf010fb | 12895 | if (intel_cstate->update_pipe) |
1a15b77b | 12896 | intel_update_pipe_config(old_intel_cstate, intel_cstate); |
ccf010fb | 12897 | else if (INTEL_GEN(dev_priv) >= 9) |
5a21b665 | 12898 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 12899 | |
e62929b3 | 12900 | out: |
ccf010fb ML |
12901 | if (dev_priv->display.atomic_update_watermarks) |
12902 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
12903 | intel_cstate); | |
5a21b665 DV |
12904 | } |
12905 | ||
12906 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
12907 | struct drm_crtc_state *old_crtc_state) | |
12908 | { | |
12909 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d3a8fb32 VS |
12910 | struct intel_atomic_state *old_intel_state = |
12911 | to_intel_atomic_state(old_crtc_state->state); | |
12912 | struct intel_crtc_state *new_crtc_state = | |
12913 | intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc); | |
5a21b665 | 12914 | |
d3a8fb32 | 12915 | intel_pipe_update_end(new_crtc_state); |
5a21b665 DV |
12916 | } |
12917 | ||
cf4c7c12 | 12918 | /** |
4a3b8769 MR |
12919 | * intel_plane_destroy - destroy a plane |
12920 | * @plane: plane to destroy | |
cf4c7c12 | 12921 | * |
4a3b8769 MR |
12922 | * Common destruction function for all types of planes (primary, cursor, |
12923 | * sprite). | |
cf4c7c12 | 12924 | */ |
4a3b8769 | 12925 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 12926 | { |
465c120c | 12927 | drm_plane_cleanup(plane); |
69ae561f | 12928 | kfree(to_intel_plane(plane)); |
465c120c MR |
12929 | } |
12930 | ||
714244e2 BW |
12931 | static bool i8xx_mod_supported(uint32_t format, uint64_t modifier) |
12932 | { | |
12933 | switch (format) { | |
12934 | case DRM_FORMAT_C8: | |
12935 | case DRM_FORMAT_RGB565: | |
12936 | case DRM_FORMAT_XRGB1555: | |
12937 | case DRM_FORMAT_XRGB8888: | |
12938 | return modifier == DRM_FORMAT_MOD_LINEAR || | |
12939 | modifier == I915_FORMAT_MOD_X_TILED; | |
12940 | default: | |
12941 | return false; | |
12942 | } | |
12943 | } | |
12944 | ||
12945 | static bool i965_mod_supported(uint32_t format, uint64_t modifier) | |
12946 | { | |
12947 | switch (format) { | |
12948 | case DRM_FORMAT_C8: | |
12949 | case DRM_FORMAT_RGB565: | |
12950 | case DRM_FORMAT_XRGB8888: | |
12951 | case DRM_FORMAT_XBGR8888: | |
12952 | case DRM_FORMAT_XRGB2101010: | |
12953 | case DRM_FORMAT_XBGR2101010: | |
12954 | return modifier == DRM_FORMAT_MOD_LINEAR || | |
12955 | modifier == I915_FORMAT_MOD_X_TILED; | |
12956 | default: | |
12957 | return false; | |
12958 | } | |
12959 | } | |
12960 | ||
12961 | static bool skl_mod_supported(uint32_t format, uint64_t modifier) | |
12962 | { | |
12963 | switch (format) { | |
12964 | case DRM_FORMAT_XRGB8888: | |
12965 | case DRM_FORMAT_XBGR8888: | |
12966 | case DRM_FORMAT_ARGB8888: | |
12967 | case DRM_FORMAT_ABGR8888: | |
12968 | if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS || | |
12969 | modifier == I915_FORMAT_MOD_Y_TILED_CCS) | |
12970 | return true; | |
12971 | /* fall through */ | |
12972 | case DRM_FORMAT_RGB565: | |
12973 | case DRM_FORMAT_XRGB2101010: | |
12974 | case DRM_FORMAT_XBGR2101010: | |
12975 | case DRM_FORMAT_YUYV: | |
12976 | case DRM_FORMAT_YVYU: | |
12977 | case DRM_FORMAT_UYVY: | |
12978 | case DRM_FORMAT_VYUY: | |
12979 | if (modifier == I915_FORMAT_MOD_Yf_TILED) | |
12980 | return true; | |
12981 | /* fall through */ | |
12982 | case DRM_FORMAT_C8: | |
12983 | if (modifier == DRM_FORMAT_MOD_LINEAR || | |
12984 | modifier == I915_FORMAT_MOD_X_TILED || | |
12985 | modifier == I915_FORMAT_MOD_Y_TILED) | |
12986 | return true; | |
12987 | /* fall through */ | |
12988 | default: | |
12989 | return false; | |
12990 | } | |
12991 | } | |
12992 | ||
12993 | static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane, | |
12994 | uint32_t format, | |
12995 | uint64_t modifier) | |
12996 | { | |
12997 | struct drm_i915_private *dev_priv = to_i915(plane->dev); | |
12998 | ||
12999 | if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) | |
13000 | return false; | |
13001 | ||
13002 | if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL && | |
13003 | modifier != DRM_FORMAT_MOD_LINEAR) | |
13004 | return false; | |
13005 | ||
13006 | if (INTEL_GEN(dev_priv) >= 9) | |
13007 | return skl_mod_supported(format, modifier); | |
13008 | else if (INTEL_GEN(dev_priv) >= 4) | |
13009 | return i965_mod_supported(format, modifier); | |
13010 | else | |
13011 | return i8xx_mod_supported(format, modifier); | |
13012 | ||
13013 | unreachable(); | |
13014 | } | |
13015 | ||
13016 | static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane, | |
13017 | uint32_t format, | |
13018 | uint64_t modifier) | |
13019 | { | |
13020 | if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) | |
13021 | return false; | |
13022 | ||
13023 | return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888; | |
13024 | } | |
13025 | ||
13026 | static struct drm_plane_funcs intel_plane_funcs = { | |
70a101f8 MR |
13027 | .update_plane = drm_atomic_helper_update_plane, |
13028 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13029 | .destroy = intel_plane_destroy, |
a98b3431 MR |
13030 | .atomic_get_property = intel_plane_atomic_get_property, |
13031 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13032 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13033 | .atomic_destroy_state = intel_plane_destroy_state, | |
714244e2 | 13034 | .format_mod_supported = intel_primary_plane_format_mod_supported, |
465c120c MR |
13035 | }; |
13036 | ||
f79f2692 ML |
13037 | static int |
13038 | intel_legacy_cursor_update(struct drm_plane *plane, | |
13039 | struct drm_crtc *crtc, | |
13040 | struct drm_framebuffer *fb, | |
13041 | int crtc_x, int crtc_y, | |
13042 | unsigned int crtc_w, unsigned int crtc_h, | |
13043 | uint32_t src_x, uint32_t src_y, | |
34a2ab5e DV |
13044 | uint32_t src_w, uint32_t src_h, |
13045 | struct drm_modeset_acquire_ctx *ctx) | |
f79f2692 ML |
13046 | { |
13047 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
13048 | int ret; | |
13049 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
13050 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13051 | struct drm_framebuffer *old_fb; | |
13052 | struct drm_crtc_state *crtc_state = crtc->state; | |
fd70075f | 13053 | struct i915_vma *old_vma, *vma; |
f79f2692 ML |
13054 | |
13055 | /* | |
13056 | * When crtc is inactive or there is a modeset pending, | |
13057 | * wait for it to complete in the slowpath | |
13058 | */ | |
13059 | if (!crtc_state->active || needs_modeset(crtc_state) || | |
13060 | to_intel_crtc_state(crtc_state)->update_pipe) | |
13061 | goto slow; | |
13062 | ||
13063 | old_plane_state = plane->state; | |
669c9215 ML |
13064 | /* |
13065 | * Don't do an async update if there is an outstanding commit modifying | |
13066 | * the plane. This prevents our async update's changes from getting | |
13067 | * overridden by a previous synchronous update's state. | |
13068 | */ | |
13069 | if (old_plane_state->commit && | |
13070 | !try_wait_for_completion(&old_plane_state->commit->hw_done)) | |
13071 | goto slow; | |
f79f2692 ML |
13072 | |
13073 | /* | |
13074 | * If any parameters change that may affect watermarks, | |
13075 | * take the slowpath. Only changing fb or position should be | |
13076 | * in the fastpath. | |
13077 | */ | |
13078 | if (old_plane_state->crtc != crtc || | |
13079 | old_plane_state->src_w != src_w || | |
13080 | old_plane_state->src_h != src_h || | |
13081 | old_plane_state->crtc_w != crtc_w || | |
13082 | old_plane_state->crtc_h != crtc_h || | |
a5509abd | 13083 | !old_plane_state->fb != !fb) |
f79f2692 ML |
13084 | goto slow; |
13085 | ||
13086 | new_plane_state = intel_plane_duplicate_state(plane); | |
13087 | if (!new_plane_state) | |
13088 | return -ENOMEM; | |
13089 | ||
13090 | drm_atomic_set_fb_for_plane(new_plane_state, fb); | |
13091 | ||
13092 | new_plane_state->src_x = src_x; | |
13093 | new_plane_state->src_y = src_y; | |
13094 | new_plane_state->src_w = src_w; | |
13095 | new_plane_state->src_h = src_h; | |
13096 | new_plane_state->crtc_x = crtc_x; | |
13097 | new_plane_state->crtc_y = crtc_y; | |
13098 | new_plane_state->crtc_w = crtc_w; | |
13099 | new_plane_state->crtc_h = crtc_h; | |
13100 | ||
13101 | ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), | |
b2b55502 VS |
13102 | to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */ |
13103 | to_intel_plane_state(plane->state), | |
f79f2692 ML |
13104 | to_intel_plane_state(new_plane_state)); |
13105 | if (ret) | |
13106 | goto out_free; | |
13107 | ||
f79f2692 ML |
13108 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
13109 | if (ret) | |
13110 | goto out_free; | |
13111 | ||
13112 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
fabac484 | 13113 | int align = intel_cursor_alignment(dev_priv); |
f79f2692 ML |
13114 | |
13115 | ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align); | |
13116 | if (ret) { | |
13117 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13118 | goto out_unlock; | |
13119 | } | |
13120 | } else { | |
f79f2692 ML |
13121 | vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); |
13122 | if (IS_ERR(vma)) { | |
13123 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13124 | ||
13125 | ret = PTR_ERR(vma); | |
13126 | goto out_unlock; | |
13127 | } | |
be1e3415 CW |
13128 | |
13129 | to_intel_plane_state(new_plane_state)->vma = vma; | |
f79f2692 ML |
13130 | } |
13131 | ||
13132 | old_fb = old_plane_state->fb; | |
13133 | ||
13134 | i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), | |
13135 | intel_plane->frontbuffer_bit); | |
13136 | ||
13137 | /* Swap plane state */ | |
669c9215 | 13138 | plane->state = new_plane_state; |
f79f2692 | 13139 | |
72259536 VS |
13140 | if (plane->state->visible) { |
13141 | trace_intel_update_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 13142 | intel_plane->update_plane(intel_plane, |
a5509abd VS |
13143 | to_intel_crtc_state(crtc->state), |
13144 | to_intel_plane_state(plane->state)); | |
72259536 VS |
13145 | } else { |
13146 | trace_intel_disable_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 13147 | intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc)); |
72259536 | 13148 | } |
f79f2692 | 13149 | |
669c9215 | 13150 | old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma); |
fd70075f CW |
13151 | if (old_vma) |
13152 | intel_unpin_fb_vma(old_vma); | |
f79f2692 ML |
13153 | |
13154 | out_unlock: | |
13155 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
13156 | out_free: | |
669c9215 ML |
13157 | if (ret) |
13158 | intel_plane_destroy_state(plane, new_plane_state); | |
13159 | else | |
13160 | intel_plane_destroy_state(plane, old_plane_state); | |
f79f2692 ML |
13161 | return ret; |
13162 | ||
f79f2692 ML |
13163 | slow: |
13164 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
13165 | crtc_x, crtc_y, crtc_w, crtc_h, | |
34a2ab5e | 13166 | src_x, src_y, src_w, src_h, ctx); |
f79f2692 ML |
13167 | } |
13168 | ||
13169 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
13170 | .update_plane = intel_legacy_cursor_update, | |
13171 | .disable_plane = drm_atomic_helper_disable_plane, | |
13172 | .destroy = intel_plane_destroy, | |
f79f2692 ML |
13173 | .atomic_get_property = intel_plane_atomic_get_property, |
13174 | .atomic_set_property = intel_plane_atomic_set_property, | |
13175 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
13176 | .atomic_destroy_state = intel_plane_destroy_state, | |
714244e2 | 13177 | .format_mod_supported = intel_cursor_plane_format_mod_supported, |
f79f2692 ML |
13178 | }; |
13179 | ||
b079bd17 | 13180 | static struct intel_plane * |
580503c7 | 13181 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 13182 | { |
fca0ce2a VS |
13183 | struct intel_plane *primary = NULL; |
13184 | struct intel_plane_state *state = NULL; | |
465c120c | 13185 | const uint32_t *intel_primary_formats; |
93ca7e00 | 13186 | unsigned int supported_rotations; |
45e3743a | 13187 | unsigned int num_formats; |
714244e2 | 13188 | const uint64_t *modifiers; |
fca0ce2a | 13189 | int ret; |
465c120c MR |
13190 | |
13191 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
13192 | if (!primary) { |
13193 | ret = -ENOMEM; | |
fca0ce2a | 13194 | goto fail; |
b079bd17 | 13195 | } |
465c120c | 13196 | |
8e7d688b | 13197 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
13198 | if (!state) { |
13199 | ret = -ENOMEM; | |
fca0ce2a | 13200 | goto fail; |
b079bd17 VS |
13201 | } |
13202 | ||
8e7d688b | 13203 | primary->base.state = &state->base; |
ea2c67bb | 13204 | |
465c120c MR |
13205 | primary->can_scale = false; |
13206 | primary->max_downscale = 1; | |
580503c7 | 13207 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 13208 | primary->can_scale = true; |
af99ceda | 13209 | state->scaler_id = -1; |
6156a456 | 13210 | } |
465c120c | 13211 | primary->pipe = pipe; |
e3c566df VS |
13212 | /* |
13213 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
13214 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
13215 | */ | |
13216 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
13217 | primary->plane = (enum plane) !pipe; | |
13218 | else | |
13219 | primary->plane = (enum plane) pipe; | |
b14e5848 | 13220 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 13221 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13222 | primary->check_plane = intel_check_primary_plane; |
465c120c | 13223 | |
714244e2 | 13224 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { |
6c0fd451 DL |
13225 | intel_primary_formats = skl_primary_formats; |
13226 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
714244e2 BW |
13227 | modifiers = skl_format_modifiers_ccs; |
13228 | ||
13229 | primary->update_plane = skylake_update_primary_plane; | |
13230 | primary->disable_plane = skylake_disable_primary_plane; | |
13231 | } else if (INTEL_GEN(dev_priv) >= 9) { | |
13232 | intel_primary_formats = skl_primary_formats; | |
13233 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13234 | if (pipe < PIPE_C) | |
13235 | modifiers = skl_format_modifiers_ccs; | |
13236 | else | |
13237 | modifiers = skl_format_modifiers_noccs; | |
a8d201af ML |
13238 | |
13239 | primary->update_plane = skylake_update_primary_plane; | |
13240 | primary->disable_plane = skylake_disable_primary_plane; | |
580503c7 | 13241 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
13242 | intel_primary_formats = i965_primary_formats; |
13243 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
714244e2 | 13244 | modifiers = i9xx_format_modifiers; |
a8d201af ML |
13245 | |
13246 | primary->update_plane = i9xx_update_primary_plane; | |
13247 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13248 | } else { |
13249 | intel_primary_formats = i8xx_primary_formats; | |
13250 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
714244e2 | 13251 | modifiers = i9xx_format_modifiers; |
a8d201af ML |
13252 | |
13253 | primary->update_plane = i9xx_update_primary_plane; | |
13254 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13255 | } |
13256 | ||
580503c7 VS |
13257 | if (INTEL_GEN(dev_priv) >= 9) |
13258 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
13259 | 0, &intel_plane_funcs, | |
38573dc1 | 13260 | intel_primary_formats, num_formats, |
714244e2 | 13261 | modifiers, |
38573dc1 VS |
13262 | DRM_PLANE_TYPE_PRIMARY, |
13263 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 13264 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
13265 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13266 | 0, &intel_plane_funcs, | |
38573dc1 | 13267 | intel_primary_formats, num_formats, |
714244e2 | 13268 | modifiers, |
38573dc1 VS |
13269 | DRM_PLANE_TYPE_PRIMARY, |
13270 | "primary %c", pipe_name(pipe)); | |
13271 | else | |
580503c7 VS |
13272 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13273 | 0, &intel_plane_funcs, | |
38573dc1 | 13274 | intel_primary_formats, num_formats, |
714244e2 | 13275 | modifiers, |
38573dc1 VS |
13276 | DRM_PLANE_TYPE_PRIMARY, |
13277 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
13278 | if (ret) |
13279 | goto fail; | |
48404c1e | 13280 | |
5481e27f | 13281 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 | 13282 | supported_rotations = |
c2c446ad RF |
13283 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | |
13284 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; | |
4ea7be2b VS |
13285 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
13286 | supported_rotations = | |
c2c446ad RF |
13287 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | |
13288 | DRM_MODE_REFLECT_X; | |
5481e27f | 13289 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 | 13290 | supported_rotations = |
c2c446ad | 13291 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; |
93ca7e00 | 13292 | } else { |
c2c446ad | 13293 | supported_rotations = DRM_MODE_ROTATE_0; |
93ca7e00 VS |
13294 | } |
13295 | ||
5481e27f | 13296 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13297 | drm_plane_create_rotation_property(&primary->base, |
c2c446ad | 13298 | DRM_MODE_ROTATE_0, |
93ca7e00 | 13299 | supported_rotations); |
48404c1e | 13300 | |
ea2c67bb MR |
13301 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13302 | ||
b079bd17 | 13303 | return primary; |
fca0ce2a VS |
13304 | |
13305 | fail: | |
13306 | kfree(state); | |
13307 | kfree(primary); | |
13308 | ||
b079bd17 | 13309 | return ERR_PTR(ret); |
465c120c MR |
13310 | } |
13311 | ||
b079bd17 | 13312 | static struct intel_plane * |
b2d03b0d VS |
13313 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, |
13314 | enum pipe pipe) | |
3d7d6510 | 13315 | { |
fca0ce2a VS |
13316 | struct intel_plane *cursor = NULL; |
13317 | struct intel_plane_state *state = NULL; | |
13318 | int ret; | |
3d7d6510 MR |
13319 | |
13320 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
13321 | if (!cursor) { |
13322 | ret = -ENOMEM; | |
fca0ce2a | 13323 | goto fail; |
b079bd17 | 13324 | } |
3d7d6510 | 13325 | |
8e7d688b | 13326 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
13327 | if (!state) { |
13328 | ret = -ENOMEM; | |
fca0ce2a | 13329 | goto fail; |
b079bd17 VS |
13330 | } |
13331 | ||
8e7d688b | 13332 | cursor->base.state = &state->base; |
ea2c67bb | 13333 | |
3d7d6510 MR |
13334 | cursor->can_scale = false; |
13335 | cursor->max_downscale = 1; | |
13336 | cursor->pipe = pipe; | |
13337 | cursor->plane = pipe; | |
b14e5848 | 13338 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 13339 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
b2d03b0d VS |
13340 | |
13341 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { | |
13342 | cursor->update_plane = i845_update_cursor; | |
13343 | cursor->disable_plane = i845_disable_cursor; | |
659056f2 | 13344 | cursor->check_plane = i845_check_cursor; |
b2d03b0d VS |
13345 | } else { |
13346 | cursor->update_plane = i9xx_update_cursor; | |
13347 | cursor->disable_plane = i9xx_disable_cursor; | |
659056f2 | 13348 | cursor->check_plane = i9xx_check_cursor; |
b2d03b0d | 13349 | } |
3d7d6510 | 13350 | |
cd5dcbf1 VS |
13351 | cursor->cursor.base = ~0; |
13352 | cursor->cursor.cntl = ~0; | |
024faac7 VS |
13353 | |
13354 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) | |
13355 | cursor->cursor.size = ~0; | |
3d7d6510 | 13356 | |
580503c7 | 13357 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
f79f2692 | 13358 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
13359 | intel_cursor_formats, |
13360 | ARRAY_SIZE(intel_cursor_formats), | |
714244e2 BW |
13361 | cursor_format_modifiers, |
13362 | DRM_PLANE_TYPE_CURSOR, | |
38573dc1 | 13363 | "cursor %c", pipe_name(pipe)); |
fca0ce2a VS |
13364 | if (ret) |
13365 | goto fail; | |
4398ad45 | 13366 | |
5481e27f | 13367 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13368 | drm_plane_create_rotation_property(&cursor->base, |
c2c446ad RF |
13369 | DRM_MODE_ROTATE_0, |
13370 | DRM_MODE_ROTATE_0 | | |
13371 | DRM_MODE_ROTATE_180); | |
4398ad45 | 13372 | |
580503c7 | 13373 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
13374 | state->scaler_id = -1; |
13375 | ||
ea2c67bb MR |
13376 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13377 | ||
b079bd17 | 13378 | return cursor; |
fca0ce2a VS |
13379 | |
13380 | fail: | |
13381 | kfree(state); | |
13382 | kfree(cursor); | |
13383 | ||
b079bd17 | 13384 | return ERR_PTR(ret); |
3d7d6510 MR |
13385 | } |
13386 | ||
1c74eeaf NM |
13387 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
13388 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 13389 | { |
65edccce VS |
13390 | struct intel_crtc_scaler_state *scaler_state = |
13391 | &crtc_state->scaler_state; | |
1c74eeaf | 13392 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
549e2bfb | 13393 | int i; |
549e2bfb | 13394 | |
1c74eeaf NM |
13395 | crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; |
13396 | if (!crtc->num_scalers) | |
13397 | return; | |
13398 | ||
65edccce VS |
13399 | for (i = 0; i < crtc->num_scalers; i++) { |
13400 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
13401 | ||
13402 | scaler->in_use = 0; | |
13403 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
13404 | } |
13405 | ||
13406 | scaler_state->scaler_id = -1; | |
13407 | } | |
13408 | ||
5ab0d85b | 13409 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
13410 | { |
13411 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 13412 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
13413 | struct intel_plane *primary = NULL; |
13414 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 13415 | int sprite, ret; |
79e53945 | 13416 | |
955382f3 | 13417 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
13418 | if (!intel_crtc) |
13419 | return -ENOMEM; | |
79e53945 | 13420 | |
f5de6e07 | 13421 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
13422 | if (!crtc_state) { |
13423 | ret = -ENOMEM; | |
f5de6e07 | 13424 | goto fail; |
b079bd17 | 13425 | } |
550acefd ACO |
13426 | intel_crtc->config = crtc_state; |
13427 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13428 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13429 | |
580503c7 | 13430 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
13431 | if (IS_ERR(primary)) { |
13432 | ret = PTR_ERR(primary); | |
3d7d6510 | 13433 | goto fail; |
b079bd17 | 13434 | } |
d97d7b48 | 13435 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 13436 | |
a81d6fa0 | 13437 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
13438 | struct intel_plane *plane; |
13439 | ||
580503c7 | 13440 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 13441 | if (IS_ERR(plane)) { |
b079bd17 VS |
13442 | ret = PTR_ERR(plane); |
13443 | goto fail; | |
13444 | } | |
d97d7b48 | 13445 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
13446 | } |
13447 | ||
580503c7 | 13448 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 13449 | if (IS_ERR(cursor)) { |
b079bd17 | 13450 | ret = PTR_ERR(cursor); |
3d7d6510 | 13451 | goto fail; |
b079bd17 | 13452 | } |
d97d7b48 | 13453 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 13454 | |
5ab0d85b | 13455 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
13456 | &primary->base, &cursor->base, |
13457 | &intel_crtc_funcs, | |
4d5d72b7 | 13458 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
13459 | if (ret) |
13460 | goto fail; | |
79e53945 | 13461 | |
80824003 | 13462 | intel_crtc->pipe = pipe; |
e3c566df | 13463 | intel_crtc->plane = primary->plane; |
80824003 | 13464 | |
1c74eeaf NM |
13465 | /* initialize shared scalers */ |
13466 | intel_crtc_init_scalers(intel_crtc, crtc_state); | |
13467 | ||
22fd0fab JB |
13468 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13469 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
13470 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
13471 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 13472 | |
79e53945 | 13473 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13474 | |
8563b1e8 LL |
13475 | intel_color_init(&intel_crtc->base); |
13476 | ||
87b6b101 | 13477 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
13478 | |
13479 | return 0; | |
3d7d6510 MR |
13480 | |
13481 | fail: | |
b079bd17 VS |
13482 | /* |
13483 | * drm_mode_config_cleanup() will free up any | |
13484 | * crtcs/planes already initialized. | |
13485 | */ | |
f5de6e07 | 13486 | kfree(crtc_state); |
3d7d6510 | 13487 | kfree(intel_crtc); |
b079bd17 VS |
13488 | |
13489 | return ret; | |
79e53945 JB |
13490 | } |
13491 | ||
752aa88a JB |
13492 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13493 | { | |
6e9f798d | 13494 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13495 | |
51fd371b | 13496 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13497 | |
51ec53da | 13498 | if (!connector->base.state->crtc) |
752aa88a JB |
13499 | return INVALID_PIPE; |
13500 | ||
51ec53da | 13501 | return to_intel_crtc(connector->base.state->crtc)->pipe; |
752aa88a JB |
13502 | } |
13503 | ||
08d7b3d1 | 13504 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13505 | struct drm_file *file) |
08d7b3d1 | 13506 | { |
08d7b3d1 | 13507 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13508 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13509 | struct intel_crtc *crtc; |
08d7b3d1 | 13510 | |
7707e653 | 13511 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 13512 | if (!drmmode_crtc) |
3f2c2057 | 13513 | return -ENOENT; |
08d7b3d1 | 13514 | |
7707e653 | 13515 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13516 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13517 | |
c05422d5 | 13518 | return 0; |
08d7b3d1 CW |
13519 | } |
13520 | ||
66a9278e | 13521 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13522 | { |
66a9278e DV |
13523 | struct drm_device *dev = encoder->base.dev; |
13524 | struct intel_encoder *source_encoder; | |
79e53945 | 13525 | int index_mask = 0; |
79e53945 JB |
13526 | int entry = 0; |
13527 | ||
b2784e15 | 13528 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13529 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13530 | index_mask |= (1 << entry); |
13531 | ||
79e53945 JB |
13532 | entry++; |
13533 | } | |
4ef69c7a | 13534 | |
79e53945 JB |
13535 | return index_mask; |
13536 | } | |
13537 | ||
646d5772 | 13538 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 13539 | { |
646d5772 | 13540 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
13541 | return false; |
13542 | ||
13543 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13544 | return false; | |
13545 | ||
5db94019 | 13546 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13547 | return false; |
13548 | ||
13549 | return true; | |
13550 | } | |
13551 | ||
6315b5d3 | 13552 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 13553 | { |
6315b5d3 | 13554 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
13555 | return false; |
13556 | ||
50a0bc90 | 13557 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
13558 | return false; |
13559 | ||
920a14b2 | 13560 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
13561 | return false; |
13562 | ||
4f8036a2 TU |
13563 | if (HAS_PCH_LPT_H(dev_priv) && |
13564 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
13565 | return false; |
13566 | ||
70ac54d0 | 13567 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 13568 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
13569 | return false; |
13570 | ||
e4abb733 | 13571 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
13572 | return false; |
13573 | ||
13574 | return true; | |
13575 | } | |
13576 | ||
8090ba8c ID |
13577 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
13578 | { | |
13579 | int pps_num; | |
13580 | int pps_idx; | |
13581 | ||
13582 | if (HAS_DDI(dev_priv)) | |
13583 | return; | |
13584 | /* | |
13585 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
13586 | * everywhere where registers can be write protected. | |
13587 | */ | |
13588 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13589 | pps_num = 2; | |
13590 | else | |
13591 | pps_num = 1; | |
13592 | ||
13593 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
13594 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
13595 | ||
13596 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
13597 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
13598 | } | |
13599 | } | |
13600 | ||
44cb734c ID |
13601 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
13602 | { | |
cc3f90f0 | 13603 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
13604 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
13605 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13606 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
13607 | else | |
13608 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
13609 | |
13610 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
13611 | } |
13612 | ||
c39055b0 | 13613 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 13614 | { |
4ef69c7a | 13615 | struct intel_encoder *encoder; |
cb0953d7 | 13616 | bool dpd_is_edp = false; |
79e53945 | 13617 | |
44cb734c ID |
13618 | intel_pps_init(dev_priv); |
13619 | ||
97a824e1 ID |
13620 | /* |
13621 | * intel_edp_init_connector() depends on this completing first, to | |
13622 | * prevent the registeration of both eDP and LVDS and the incorrect | |
13623 | * sharing of the PPS. | |
13624 | */ | |
c39055b0 | 13625 | intel_lvds_init(dev_priv); |
79e53945 | 13626 | |
6315b5d3 | 13627 | if (intel_crt_present(dev_priv)) |
c39055b0 | 13628 | intel_crt_init(dev_priv); |
cb0953d7 | 13629 | |
cc3f90f0 | 13630 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
13631 | /* |
13632 | * FIXME: Broxton doesn't support port detection via the | |
13633 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13634 | * detect the ports. | |
13635 | */ | |
c39055b0 ACO |
13636 | intel_ddi_init(dev_priv, PORT_A); |
13637 | intel_ddi_init(dev_priv, PORT_B); | |
13638 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 13639 | |
c39055b0 | 13640 | intel_dsi_init(dev_priv); |
4f8036a2 | 13641 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
13642 | int found; |
13643 | ||
de31facd JB |
13644 | /* |
13645 | * Haswell uses DDI functions to detect digital outputs. | |
13646 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13647 | * it's there. | |
13648 | */ | |
77179400 | 13649 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 13650 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 13651 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 13652 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
13653 | |
13654 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13655 | * register */ | |
13656 | found = I915_READ(SFUSE_STRAP); | |
13657 | ||
13658 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 13659 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 13660 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 13661 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 13662 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 13663 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
13664 | /* |
13665 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
13666 | */ | |
b976dc53 | 13667 | if (IS_GEN9_BC(dev_priv) && |
2800e4c2 RV |
13668 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
13669 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
13670 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 13671 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 13672 | |
6e266956 | 13673 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 13674 | int found; |
7b91bf7f | 13675 | dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); |
270b3042 | 13676 | |
646d5772 | 13677 | if (has_edp_a(dev_priv)) |
c39055b0 | 13678 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 13679 | |
dc0fa718 | 13680 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13681 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 13682 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 13683 | if (!found) |
c39055b0 | 13684 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 13685 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 13686 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13687 | } |
13688 | ||
dc0fa718 | 13689 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 13690 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 13691 | |
dc0fa718 | 13692 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 13693 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 13694 | |
5eb08b69 | 13695 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 13696 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 13697 | |
270b3042 | 13698 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 13699 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 13700 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 13701 | bool has_edp, has_port; |
457c52d8 | 13702 | |
e17ac6db VS |
13703 | /* |
13704 | * The DP_DETECTED bit is the latched state of the DDC | |
13705 | * SDA pin at boot. However since eDP doesn't require DDC | |
13706 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13707 | * eDP ports may have been muxed to an alternate function. | |
13708 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13709 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13710 | * detect eDP ports. | |
22f35042 VS |
13711 | * |
13712 | * Sadly the straps seem to be missing sometimes even for HDMI | |
13713 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
13714 | * and VBT for the presence of the port. Additionally we can't | |
13715 | * trust the port type the VBT declares as we've seen at least | |
13716 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 13717 | */ |
7b91bf7f | 13718 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); |
22f35042 VS |
13719 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
13720 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 13721 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 13722 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13723 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 13724 | |
7b91bf7f | 13725 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); |
22f35042 VS |
13726 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
13727 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 13728 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 13729 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13730 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 13731 | |
920a14b2 | 13732 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
13733 | /* |
13734 | * eDP not supported on port D, | |
13735 | * so no need to worry about it | |
13736 | */ | |
13737 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
13738 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 13739 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 13740 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 13741 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
13742 | } |
13743 | ||
c39055b0 | 13744 | intel_dsi_init(dev_priv); |
5db94019 | 13745 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 13746 | bool found = false; |
7d57382e | 13747 | |
e2debe91 | 13748 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13749 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 13750 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 13751 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 13752 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 13753 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13754 | } |
27185ae1 | 13755 | |
9beb5fea | 13756 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 13757 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 13758 | } |
13520b05 KH |
13759 | |
13760 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13761 | |
e2debe91 | 13762 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13763 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 13764 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 13765 | } |
27185ae1 | 13766 | |
e2debe91 | 13767 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13768 | |
9beb5fea | 13769 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 13770 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 13771 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13772 | } |
9beb5fea | 13773 | if (IS_G4X(dev_priv)) |
c39055b0 | 13774 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 13775 | } |
27185ae1 | 13776 | |
9beb5fea | 13777 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 13778 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 13779 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 13780 | intel_dvo_init(dev_priv); |
79e53945 | 13781 | |
56b857a5 | 13782 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 13783 | intel_tv_init(dev_priv); |
79e53945 | 13784 | |
c39055b0 | 13785 | intel_psr_init(dev_priv); |
7c8f8a70 | 13786 | |
c39055b0 | 13787 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
13788 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13789 | encoder->base.possible_clones = | |
66a9278e | 13790 | intel_encoder_clones(encoder); |
79e53945 | 13791 | } |
47356eb6 | 13792 | |
c39055b0 | 13793 | intel_init_pch_refclk(dev_priv); |
270b3042 | 13794 | |
c39055b0 | 13795 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
13796 | } |
13797 | ||
13798 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13799 | { | |
13800 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 13801 | |
ef2d633e | 13802 | drm_framebuffer_cleanup(fb); |
70001cd2 | 13803 | |
dd689287 CW |
13804 | i915_gem_object_lock(intel_fb->obj); |
13805 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
13806 | i915_gem_object_unlock(intel_fb->obj); | |
13807 | ||
f8c417cd | 13808 | i915_gem_object_put(intel_fb->obj); |
70001cd2 | 13809 | |
79e53945 JB |
13810 | kfree(intel_fb); |
13811 | } | |
13812 | ||
13813 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13814 | struct drm_file *file, |
79e53945 JB |
13815 | unsigned int *handle) |
13816 | { | |
13817 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13818 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13819 | |
cc917ab4 CW |
13820 | if (obj->userptr.mm) { |
13821 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
13822 | return -EINVAL; | |
13823 | } | |
13824 | ||
05394f39 | 13825 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13826 | } |
13827 | ||
86c98588 RV |
13828 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
13829 | struct drm_file *file, | |
13830 | unsigned flags, unsigned color, | |
13831 | struct drm_clip_rect *clips, | |
13832 | unsigned num_clips) | |
13833 | { | |
5a97bcc6 | 13834 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 13835 | |
5a97bcc6 | 13836 | i915_gem_object_flush_if_display(obj); |
d59b21ec | 13837 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
86c98588 RV |
13838 | |
13839 | return 0; | |
13840 | } | |
13841 | ||
79e53945 JB |
13842 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
13843 | .destroy = intel_user_framebuffer_destroy, | |
13844 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 13845 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
13846 | }; |
13847 | ||
b321803d | 13848 | static |
920a14b2 TU |
13849 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
13850 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 13851 | { |
24dbf51a | 13852 | u32 gen = INTEL_GEN(dev_priv); |
b321803d DL |
13853 | |
13854 | if (gen >= 9) { | |
ac484963 VS |
13855 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
13856 | ||
b321803d DL |
13857 | /* "The stride in bytes must not exceed the of the size of 8K |
13858 | * pixels and 32K bytes." | |
13859 | */ | |
ac484963 | 13860 | return min(8192 * cpp, 32768); |
6401c37d | 13861 | } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) { |
b321803d DL |
13862 | return 32*1024; |
13863 | } else if (gen >= 4) { | |
13864 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13865 | return 16*1024; | |
13866 | else | |
13867 | return 32*1024; | |
13868 | } else if (gen >= 3) { | |
13869 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13870 | return 8*1024; | |
13871 | else | |
13872 | return 16*1024; | |
13873 | } else { | |
13874 | /* XXX DSPC is limited to 4k tiled */ | |
13875 | return 8*1024; | |
13876 | } | |
13877 | } | |
13878 | ||
24dbf51a CW |
13879 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
13880 | struct drm_i915_gem_object *obj, | |
13881 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 13882 | { |
24dbf51a | 13883 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2e2adb05 | 13884 | struct drm_framebuffer *fb = &intel_fb->base; |
b3c11ac2 | 13885 | struct drm_format_name_buf format_name; |
2e2adb05 | 13886 | u32 pitch_limit; |
dd689287 | 13887 | unsigned int tiling, stride; |
24dbf51a | 13888 | int ret = -EINVAL; |
2e2adb05 | 13889 | int i; |
79e53945 | 13890 | |
dd689287 CW |
13891 | i915_gem_object_lock(obj); |
13892 | obj->framebuffer_references++; | |
13893 | tiling = i915_gem_object_get_tiling(obj); | |
13894 | stride = i915_gem_object_get_stride(obj); | |
13895 | i915_gem_object_unlock(obj); | |
dd4916c5 | 13896 | |
2a80eada | 13897 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
13898 | /* |
13899 | * If there's a fence, enforce that | |
13900 | * the fb modifier and tiling mode match. | |
13901 | */ | |
13902 | if (tiling != I915_TILING_NONE && | |
13903 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13904 | DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n"); |
24dbf51a | 13905 | goto err; |
2a80eada DV |
13906 | } |
13907 | } else { | |
c2ff7370 | 13908 | if (tiling == I915_TILING_X) { |
2a80eada | 13909 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 13910 | } else if (tiling == I915_TILING_Y) { |
144cc143 | 13911 | DRM_DEBUG_KMS("No Y tiling for legacy addfb\n"); |
24dbf51a | 13912 | goto err; |
2a80eada DV |
13913 | } |
13914 | } | |
13915 | ||
9a8f0a12 TU |
13916 | /* Passed in modifier sanity checking. */ |
13917 | switch (mode_cmd->modifier[0]) { | |
2e2adb05 VS |
13918 | case I915_FORMAT_MOD_Y_TILED_CCS: |
13919 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
13920 | switch (mode_cmd->pixel_format) { | |
13921 | case DRM_FORMAT_XBGR8888: | |
13922 | case DRM_FORMAT_ABGR8888: | |
13923 | case DRM_FORMAT_XRGB8888: | |
13924 | case DRM_FORMAT_ARGB8888: | |
13925 | break; | |
13926 | default: | |
13927 | DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n"); | |
13928 | goto err; | |
13929 | } | |
13930 | /* fall through */ | |
9a8f0a12 TU |
13931 | case I915_FORMAT_MOD_Y_TILED: |
13932 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 13933 | if (INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
13934 | DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", |
13935 | mode_cmd->modifier[0]); | |
24dbf51a | 13936 | goto err; |
9a8f0a12 | 13937 | } |
2f075565 | 13938 | case DRM_FORMAT_MOD_LINEAR: |
9a8f0a12 TU |
13939 | case I915_FORMAT_MOD_X_TILED: |
13940 | break; | |
13941 | default: | |
144cc143 VS |
13942 | DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n", |
13943 | mode_cmd->modifier[0]); | |
24dbf51a | 13944 | goto err; |
c16ed4be | 13945 | } |
57cd6508 | 13946 | |
c2ff7370 VS |
13947 | /* |
13948 | * gen2/3 display engine uses the fence if present, | |
13949 | * so the tiling mode must match the fb modifier exactly. | |
13950 | */ | |
13951 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
13952 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13953 | DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); |
9aceb5c1 | 13954 | goto err; |
c2ff7370 VS |
13955 | } |
13956 | ||
920a14b2 | 13957 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 13958 | mode_cmd->pixel_format); |
a35cdaa0 | 13959 | if (mode_cmd->pitches[0] > pitch_limit) { |
144cc143 | 13960 | DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n", |
2f075565 | 13961 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? |
144cc143 VS |
13962 | "tiled" : "linear", |
13963 | mode_cmd->pitches[0], pitch_limit); | |
24dbf51a | 13964 | goto err; |
c16ed4be | 13965 | } |
5d7bd705 | 13966 | |
c2ff7370 VS |
13967 | /* |
13968 | * If there's a fence, enforce that | |
13969 | * the fb pitch and fence stride match. | |
13970 | */ | |
144cc143 VS |
13971 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
13972 | DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n", | |
13973 | mode_cmd->pitches[0], stride); | |
24dbf51a | 13974 | goto err; |
c16ed4be | 13975 | } |
5d7bd705 | 13976 | |
57779d06 | 13977 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13978 | switch (mode_cmd->pixel_format) { |
57779d06 | 13979 | case DRM_FORMAT_C8: |
04b3924d VS |
13980 | case DRM_FORMAT_RGB565: |
13981 | case DRM_FORMAT_XRGB8888: | |
13982 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13983 | break; |
13984 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 13985 | if (INTEL_GEN(dev_priv) > 3) { |
144cc143 VS |
13986 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13987 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13988 | goto err; |
c16ed4be | 13989 | } |
57779d06 | 13990 | break; |
57779d06 | 13991 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 13992 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 13993 | INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
13994 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13995 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13996 | goto err; |
6c0fd451 DL |
13997 | } |
13998 | break; | |
13999 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14000 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14001 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 14002 | if (INTEL_GEN(dev_priv) < 4) { |
144cc143 VS |
14003 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14004 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14005 | goto err; |
c16ed4be | 14006 | } |
b5626747 | 14007 | break; |
7531208b | 14008 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 14009 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
144cc143 VS |
14010 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14011 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14012 | goto err; |
7531208b DL |
14013 | } |
14014 | break; | |
04b3924d VS |
14015 | case DRM_FORMAT_YUYV: |
14016 | case DRM_FORMAT_UYVY: | |
14017 | case DRM_FORMAT_YVYU: | |
14018 | case DRM_FORMAT_VYUY: | |
ab33081a | 14019 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
144cc143 VS |
14020 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14021 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14022 | goto err; |
c16ed4be | 14023 | } |
57cd6508 CW |
14024 | break; |
14025 | default: | |
144cc143 VS |
14026 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14027 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14028 | goto err; |
57cd6508 CW |
14029 | } |
14030 | ||
90f9a336 VS |
14031 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14032 | if (mode_cmd->offsets[0] != 0) | |
24dbf51a | 14033 | goto err; |
90f9a336 | 14034 | |
2e2adb05 | 14035 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); |
d88c4afd | 14036 | |
2e2adb05 VS |
14037 | for (i = 0; i < fb->format->num_planes; i++) { |
14038 | u32 stride_alignment; | |
14039 | ||
14040 | if (mode_cmd->handles[i] != mode_cmd->handles[0]) { | |
14041 | DRM_DEBUG_KMS("bad plane %d handle\n", i); | |
37875d6b | 14042 | goto err; |
2e2adb05 VS |
14043 | } |
14044 | ||
14045 | stride_alignment = intel_fb_stride_alignment(fb, i); | |
14046 | ||
14047 | /* | |
14048 | * Display WA #0531: skl,bxt,kbl,glk | |
14049 | * | |
14050 | * Render decompression and plane width > 3840 | |
14051 | * combined with horizontal panning requires the | |
14052 | * plane stride to be a multiple of 4. We'll just | |
14053 | * require the entire fb to accommodate that to avoid | |
14054 | * potential runtime errors at plane configuration time. | |
14055 | */ | |
14056 | if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && | |
14057 | (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
14058 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) | |
14059 | stride_alignment *= 4; | |
14060 | ||
14061 | if (fb->pitches[i] & (stride_alignment - 1)) { | |
14062 | DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", | |
14063 | i, fb->pitches[i], stride_alignment); | |
14064 | goto err; | |
14065 | } | |
d88c4afd VS |
14066 | } |
14067 | ||
c7d73f6a DV |
14068 | intel_fb->obj = obj; |
14069 | ||
2e2adb05 | 14070 | ret = intel_fill_fb_info(dev_priv, fb); |
6687c906 | 14071 | if (ret) |
9aceb5c1 | 14072 | goto err; |
2d7a215f | 14073 | |
2e2adb05 | 14074 | ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); |
79e53945 JB |
14075 | if (ret) { |
14076 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
24dbf51a | 14077 | goto err; |
79e53945 JB |
14078 | } |
14079 | ||
79e53945 | 14080 | return 0; |
24dbf51a CW |
14081 | |
14082 | err: | |
dd689287 CW |
14083 | i915_gem_object_lock(obj); |
14084 | obj->framebuffer_references--; | |
14085 | i915_gem_object_unlock(obj); | |
24dbf51a | 14086 | return ret; |
79e53945 JB |
14087 | } |
14088 | ||
79e53945 JB |
14089 | static struct drm_framebuffer * |
14090 | intel_user_framebuffer_create(struct drm_device *dev, | |
14091 | struct drm_file *filp, | |
1eb83451 | 14092 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14093 | { |
dcb1394e | 14094 | struct drm_framebuffer *fb; |
05394f39 | 14095 | struct drm_i915_gem_object *obj; |
76dc3769 | 14096 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14097 | |
03ac0642 CW |
14098 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
14099 | if (!obj) | |
cce13ff7 | 14100 | return ERR_PTR(-ENOENT); |
79e53945 | 14101 | |
24dbf51a | 14102 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 14103 | if (IS_ERR(fb)) |
f0cd5182 | 14104 | i915_gem_object_put(obj); |
dcb1394e LW |
14105 | |
14106 | return fb; | |
79e53945 JB |
14107 | } |
14108 | ||
778e23a9 CW |
14109 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
14110 | { | |
14111 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
14112 | ||
14113 | drm_atomic_state_default_release(state); | |
14114 | ||
14115 | i915_sw_fence_fini(&intel_state->commit_ready); | |
14116 | ||
14117 | kfree(state); | |
14118 | } | |
14119 | ||
79e53945 | 14120 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14121 | .fb_create = intel_user_framebuffer_create, |
bbfb6ce8 | 14122 | .get_format_info = intel_get_format_info, |
0632fef6 | 14123 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14124 | .atomic_check = intel_atomic_check, |
14125 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14126 | .atomic_state_alloc = intel_atomic_state_alloc, |
14127 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 14128 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
14129 | }; |
14130 | ||
88212941 ID |
14131 | /** |
14132 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14133 | * @dev_priv: device private | |
14134 | */ | |
14135 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14136 | { |
7ff89ca2 VS |
14137 | intel_init_cdclk_hooks(dev_priv); |
14138 | ||
88212941 | 14139 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14140 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14141 | dev_priv->display.get_initial_plane_config = |
14142 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14143 | dev_priv->display.crtc_compute_clock = |
14144 | haswell_crtc_compute_clock; | |
14145 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14146 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14147 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14148 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14149 | dev_priv->display.get_initial_plane_config = |
14150 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14151 | dev_priv->display.crtc_compute_clock = |
14152 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14153 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14154 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14155 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14156 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14157 | dev_priv->display.get_initial_plane_config = |
14158 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14159 | dev_priv->display.crtc_compute_clock = |
14160 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14161 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14162 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14163 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14164 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14165 | dev_priv->display.get_initial_plane_config = |
14166 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14167 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14168 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14169 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14170 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14171 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14172 | dev_priv->display.get_initial_plane_config = | |
14173 | i9xx_get_initial_plane_config; | |
14174 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14175 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14176 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14177 | } else if (IS_G4X(dev_priv)) { |
14178 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14179 | dev_priv->display.get_initial_plane_config = | |
14180 | i9xx_get_initial_plane_config; | |
14181 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14182 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14183 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14184 | } else if (IS_PINEVIEW(dev_priv)) { |
14185 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14186 | dev_priv->display.get_initial_plane_config = | |
14187 | i9xx_get_initial_plane_config; | |
14188 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14189 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14190 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14191 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14192 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14193 | dev_priv->display.get_initial_plane_config = |
14194 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14195 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14196 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14197 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14198 | } else { |
14199 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14200 | dev_priv->display.get_initial_plane_config = | |
14201 | i9xx_get_initial_plane_config; | |
14202 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14203 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14204 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14205 | } |
e70236a8 | 14206 | |
88212941 | 14207 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14208 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14209 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14210 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14211 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14212 | /* FIXME: detect B0+ stepping and use auto training */ |
14213 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14214 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14215 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14216 | } |
14217 | ||
bd30ca2d | 14218 | if (INTEL_GEN(dev_priv) >= 9) |
27082493 L |
14219 | dev_priv->display.update_crtcs = skl_update_crtcs; |
14220 | else | |
14221 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
e70236a8 JB |
14222 | } |
14223 | ||
435793df KP |
14224 | /* |
14225 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14226 | */ | |
14227 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14228 | { | |
fac5e23e | 14229 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 14230 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 14231 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14232 | } |
14233 | ||
4dca20ef | 14234 | /* |
5a15ab5b CE |
14235 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14236 | * brightness value | |
4dca20ef CE |
14237 | */ |
14238 | static void quirk_invert_brightness(struct drm_device *dev) | |
14239 | { | |
fac5e23e | 14240 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 14241 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 14242 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14243 | } |
14244 | ||
9c72cc6f SD |
14245 | /* Some VBT's incorrectly indicate no backlight is present */ |
14246 | static void quirk_backlight_present(struct drm_device *dev) | |
14247 | { | |
fac5e23e | 14248 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
14249 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
14250 | DRM_INFO("applying backlight present quirk\n"); | |
14251 | } | |
14252 | ||
c99a259b MN |
14253 | /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms |
14254 | * which is 300 ms greater than eDP spec T12 min. | |
14255 | */ | |
14256 | static void quirk_increase_t12_delay(struct drm_device *dev) | |
14257 | { | |
14258 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14259 | ||
14260 | dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY; | |
14261 | DRM_INFO("Applying T12 delay quirk\n"); | |
14262 | } | |
14263 | ||
b690e96c JB |
14264 | struct intel_quirk { |
14265 | int device; | |
14266 | int subsystem_vendor; | |
14267 | int subsystem_device; | |
14268 | void (*hook)(struct drm_device *dev); | |
14269 | }; | |
14270 | ||
5f85f176 EE |
14271 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14272 | struct intel_dmi_quirk { | |
14273 | void (*hook)(struct drm_device *dev); | |
14274 | const struct dmi_system_id (*dmi_id_list)[]; | |
14275 | }; | |
14276 | ||
14277 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14278 | { | |
14279 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14280 | return 1; | |
14281 | } | |
14282 | ||
14283 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14284 | { | |
14285 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14286 | { | |
14287 | .callback = intel_dmi_reverse_brightness, | |
14288 | .ident = "NCR Corporation", | |
14289 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14290 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14291 | }, | |
14292 | }, | |
14293 | { } /* terminating entry */ | |
14294 | }, | |
14295 | .hook = quirk_invert_brightness, | |
14296 | }, | |
14297 | }; | |
14298 | ||
c43b5634 | 14299 | static struct intel_quirk intel_quirks[] = { |
435793df KP |
14300 | /* Lenovo U160 cannot use SSC on LVDS */ |
14301 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14302 | |
14303 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14304 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14305 | |
be505f64 AH |
14306 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14307 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14308 | ||
14309 | /* Acer/eMachines G725 */ | |
14310 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14311 | ||
14312 | /* Acer/eMachines e725 */ | |
14313 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14314 | ||
14315 | /* Acer/Packard Bell NCL20 */ | |
14316 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14317 | ||
14318 | /* Acer Aspire 4736Z */ | |
14319 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14320 | |
14321 | /* Acer Aspire 5336 */ | |
14322 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14323 | |
14324 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14325 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14326 | |
dfb3d47b SD |
14327 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14328 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14329 | ||
b2a9601c | 14330 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14331 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14332 | ||
1b9448b0 JN |
14333 | /* Apple Macbook 4,1 */ |
14334 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
14335 | ||
d4967d8c SD |
14336 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14337 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14338 | |
14339 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14340 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14341 | |
14342 | /* Dell Chromebook 11 */ | |
14343 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
14344 | |
14345 | /* Dell Chromebook 11 (2015 version) */ | |
14346 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
c99a259b MN |
14347 | |
14348 | /* Toshiba Satellite P50-C-18C */ | |
14349 | { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay }, | |
b690e96c JB |
14350 | }; |
14351 | ||
14352 | static void intel_init_quirks(struct drm_device *dev) | |
14353 | { | |
14354 | struct pci_dev *d = dev->pdev; | |
14355 | int i; | |
14356 | ||
14357 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14358 | struct intel_quirk *q = &intel_quirks[i]; | |
14359 | ||
14360 | if (d->device == q->device && | |
14361 | (d->subsystem_vendor == q->subsystem_vendor || | |
14362 | q->subsystem_vendor == PCI_ANY_ID) && | |
14363 | (d->subsystem_device == q->subsystem_device || | |
14364 | q->subsystem_device == PCI_ANY_ID)) | |
14365 | q->hook(dev); | |
14366 | } | |
5f85f176 EE |
14367 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14368 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14369 | intel_dmi_quirks[i].hook(dev); | |
14370 | } | |
b690e96c JB |
14371 | } |
14372 | ||
9cce37f4 | 14373 | /* Disable the VGA plane that we never use */ |
29b74b7f | 14374 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 14375 | { |
52a05c30 | 14376 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 14377 | u8 sr1; |
920a14b2 | 14378 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 14379 | |
2b37c616 | 14380 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 14381 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14382 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14383 | sr1 = inb(VGA_SR_DATA); |
14384 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 14385 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
14386 | udelay(300); |
14387 | ||
01f5a626 | 14388 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14389 | POSTING_READ(vga_reg); |
14390 | } | |
14391 | ||
f817586c DV |
14392 | void intel_modeset_init_hw(struct drm_device *dev) |
14393 | { | |
fac5e23e | 14394 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 14395 | |
4c75b940 | 14396 | intel_update_cdclk(dev_priv); |
bb0f4aab | 14397 | dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; |
1a617b77 | 14398 | |
46f16e63 | 14399 | intel_init_clock_gating(dev_priv); |
f817586c DV |
14400 | } |
14401 | ||
d93c0372 MR |
14402 | /* |
14403 | * Calculate what we think the watermarks should be for the state we've read | |
14404 | * out of the hardware and then immediately program those watermarks so that | |
14405 | * we ensure the hardware settings match our internal state. | |
14406 | * | |
14407 | * We can calculate what we think WM's should be by creating a duplicate of the | |
14408 | * current state (which was constructed during hardware readout) and running it | |
14409 | * through the atomic check code to calculate new watermark values in the | |
14410 | * state object. | |
14411 | */ | |
14412 | static void sanitize_watermarks(struct drm_device *dev) | |
14413 | { | |
14414 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14415 | struct drm_atomic_state *state; | |
ccf010fb | 14416 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
14417 | struct drm_crtc *crtc; |
14418 | struct drm_crtc_state *cstate; | |
14419 | struct drm_modeset_acquire_ctx ctx; | |
14420 | int ret; | |
14421 | int i; | |
14422 | ||
14423 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 14424 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
14425 | return; |
14426 | ||
14427 | /* | |
14428 | * We need to hold connection_mutex before calling duplicate_state so | |
14429 | * that the connector loop is protected. | |
14430 | */ | |
14431 | drm_modeset_acquire_init(&ctx, 0); | |
14432 | retry: | |
0cd1262d | 14433 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
14434 | if (ret == -EDEADLK) { |
14435 | drm_modeset_backoff(&ctx); | |
14436 | goto retry; | |
14437 | } else if (WARN_ON(ret)) { | |
0cd1262d | 14438 | goto fail; |
d93c0372 MR |
14439 | } |
14440 | ||
14441 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
14442 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 14443 | goto fail; |
d93c0372 | 14444 | |
ccf010fb ML |
14445 | intel_state = to_intel_atomic_state(state); |
14446 | ||
ed4a6a7c MR |
14447 | /* |
14448 | * Hardware readout is the only time we don't want to calculate | |
14449 | * intermediate watermarks (since we don't trust the current | |
14450 | * watermarks). | |
14451 | */ | |
602ae835 VS |
14452 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14453 | intel_state->skip_intermediate_wm = true; | |
ed4a6a7c | 14454 | |
d93c0372 MR |
14455 | ret = intel_atomic_check(dev, state); |
14456 | if (ret) { | |
14457 | /* | |
14458 | * If we fail here, it means that the hardware appears to be | |
14459 | * programmed in a way that shouldn't be possible, given our | |
14460 | * understanding of watermark requirements. This might mean a | |
14461 | * mistake in the hardware readout code or a mistake in the | |
14462 | * watermark calculations for a given platform. Raise a WARN | |
14463 | * so that this is noticeable. | |
14464 | * | |
14465 | * If this actually happens, we'll have to just leave the | |
14466 | * BIOS-programmed watermarks untouched and hope for the best. | |
14467 | */ | |
14468 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 14469 | goto put_state; |
d93c0372 MR |
14470 | } |
14471 | ||
14472 | /* Write calculated watermark values back */ | |
aa5e9b47 | 14473 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
d93c0372 MR |
14474 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); |
14475 | ||
ed4a6a7c | 14476 | cs->wm.need_postvbl_update = true; |
ccf010fb | 14477 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
14478 | } |
14479 | ||
b9a1b717 | 14480 | put_state: |
0853695c | 14481 | drm_atomic_state_put(state); |
0cd1262d | 14482 | fail: |
d93c0372 MR |
14483 | drm_modeset_drop_locks(&ctx); |
14484 | drm_modeset_acquire_fini(&ctx); | |
14485 | } | |
14486 | ||
b079bd17 | 14487 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 14488 | { |
72e96d64 JL |
14489 | struct drm_i915_private *dev_priv = to_i915(dev); |
14490 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 14491 | enum pipe pipe; |
46f297fb | 14492 | struct intel_crtc *crtc; |
79e53945 JB |
14493 | |
14494 | drm_mode_config_init(dev); | |
14495 | ||
14496 | dev->mode_config.min_width = 0; | |
14497 | dev->mode_config.min_height = 0; | |
14498 | ||
019d96cb DA |
14499 | dev->mode_config.preferred_depth = 24; |
14500 | dev->mode_config.prefer_shadow = 1; | |
14501 | ||
25bab385 TU |
14502 | dev->mode_config.allow_fb_modifiers = true; |
14503 | ||
e6ecefaa | 14504 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14505 | |
400c19d9 | 14506 | init_llist_head(&dev_priv->atomic_helper.free_list); |
eb955eee | 14507 | INIT_WORK(&dev_priv->atomic_helper.free_work, |
ba318c61 | 14508 | intel_atomic_helper_free_state_worker); |
eb955eee | 14509 | |
b690e96c JB |
14510 | intel_init_quirks(dev); |
14511 | ||
62d75df7 | 14512 | intel_init_pm(dev_priv); |
1fa61106 | 14513 | |
b7f05d4a | 14514 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 14515 | return 0; |
e3c74757 | 14516 | |
69f92f67 LW |
14517 | /* |
14518 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14519 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14520 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14521 | * indicates as much. | |
14522 | */ | |
6e266956 | 14523 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
14524 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
14525 | DREF_SSC1_ENABLE); | |
14526 | ||
14527 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14528 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14529 | bios_lvds_use_ssc ? "en" : "dis", | |
14530 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14531 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14532 | } | |
14533 | } | |
14534 | ||
5db94019 | 14535 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
14536 | dev->mode_config.max_width = 2048; |
14537 | dev->mode_config.max_height = 2048; | |
5db94019 | 14538 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
14539 | dev->mode_config.max_width = 4096; |
14540 | dev->mode_config.max_height = 4096; | |
79e53945 | 14541 | } else { |
a6c45cf0 CW |
14542 | dev->mode_config.max_width = 8192; |
14543 | dev->mode_config.max_height = 8192; | |
79e53945 | 14544 | } |
068be561 | 14545 | |
2a307c2e JN |
14546 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
14547 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 14548 | dev->mode_config.cursor_height = 1023; |
5db94019 | 14549 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
14550 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14551 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14552 | } else { | |
14553 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14554 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14555 | } | |
14556 | ||
72e96d64 | 14557 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 14558 | |
28c97730 | 14559 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
14560 | INTEL_INFO(dev_priv)->num_pipes, |
14561 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14562 | |
055e393f | 14563 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
14564 | int ret; |
14565 | ||
5ab0d85b | 14566 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
14567 | if (ret) { |
14568 | drm_mode_config_cleanup(dev); | |
14569 | return ret; | |
14570 | } | |
79e53945 JB |
14571 | } |
14572 | ||
e72f9fbf | 14573 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14574 | |
5be6e334 VS |
14575 | intel_update_czclk(dev_priv); |
14576 | intel_modeset_init_hw(dev); | |
14577 | ||
b2045352 | 14578 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 14579 | intel_update_max_cdclk(dev_priv); |
b2045352 | 14580 | |
9cce37f4 | 14581 | /* Just disable it once at startup */ |
29b74b7f | 14582 | i915_disable_vga(dev_priv); |
c39055b0 | 14583 | intel_setup_outputs(dev_priv); |
11be49eb | 14584 | |
6e9f798d | 14585 | drm_modeset_lock_all(dev); |
aecd36b8 | 14586 | intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); |
6e9f798d | 14587 | drm_modeset_unlock_all(dev); |
46f297fb | 14588 | |
d3fcc808 | 14589 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14590 | struct intel_initial_plane_config plane_config = {}; |
14591 | ||
46f297fb JB |
14592 | if (!crtc->active) |
14593 | continue; | |
14594 | ||
46f297fb | 14595 | /* |
46f297fb JB |
14596 | * Note that reserving the BIOS fb up front prevents us |
14597 | * from stuffing other stolen allocations like the ring | |
14598 | * on top. This prevents some ugliness at boot time, and | |
14599 | * can even allow for smooth boot transitions if the BIOS | |
14600 | * fb is large enough for the active pipe configuration. | |
14601 | */ | |
eeebeac5 ML |
14602 | dev_priv->display.get_initial_plane_config(crtc, |
14603 | &plane_config); | |
14604 | ||
14605 | /* | |
14606 | * If the fb is shared between multiple heads, we'll | |
14607 | * just get the first one. | |
14608 | */ | |
14609 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 14610 | } |
d93c0372 MR |
14611 | |
14612 | /* | |
14613 | * Make sure hardware watermarks really match the state we read out. | |
14614 | * Note that we need to do this after reconstructing the BIOS fb's | |
14615 | * since the watermark calculation done here will use pstate->fb. | |
14616 | */ | |
602ae835 VS |
14617 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14618 | sanitize_watermarks(dev); | |
b079bd17 VS |
14619 | |
14620 | return 0; | |
2c7111db CW |
14621 | } |
14622 | ||
2ee0da16 VS |
14623 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
14624 | { | |
14625 | /* 640x480@60Hz, ~25175 kHz */ | |
14626 | struct dpll clock = { | |
14627 | .m1 = 18, | |
14628 | .m2 = 7, | |
14629 | .p1 = 13, | |
14630 | .p2 = 4, | |
14631 | .n = 2, | |
14632 | }; | |
14633 | u32 dpll, fp; | |
14634 | int i; | |
14635 | ||
14636 | WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154); | |
14637 | ||
14638 | DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n", | |
14639 | pipe_name(pipe), clock.vco, clock.dot); | |
14640 | ||
14641 | fp = i9xx_dpll_compute_fp(&clock); | |
14642 | dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) | | |
14643 | DPLL_VGA_MODE_DIS | | |
14644 | ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | | |
14645 | PLL_P2_DIVIDE_BY_4 | | |
14646 | PLL_REF_INPUT_DREFCLK | | |
14647 | DPLL_VCO_ENABLE; | |
14648 | ||
14649 | I915_WRITE(FP0(pipe), fp); | |
14650 | I915_WRITE(FP1(pipe), fp); | |
14651 | ||
14652 | I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14653 | I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14654 | I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); | |
14655 | I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14656 | I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14657 | I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); | |
14658 | I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); | |
14659 | ||
14660 | /* | |
14661 | * Apparently we need to have VGA mode enabled prior to changing | |
14662 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
14663 | * dividers, even though the register value does change. | |
14664 | */ | |
14665 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); | |
14666 | I915_WRITE(DPLL(pipe), dpll); | |
14667 | ||
14668 | /* Wait for the clocks to stabilize. */ | |
14669 | POSTING_READ(DPLL(pipe)); | |
14670 | udelay(150); | |
14671 | ||
14672 | /* The pixel multiplier can only be updated once the | |
14673 | * DPLL is enabled and the clocks are stable. | |
14674 | * | |
14675 | * So write it again. | |
14676 | */ | |
14677 | I915_WRITE(DPLL(pipe), dpll); | |
14678 | ||
14679 | /* We do this three times for luck */ | |
14680 | for (i = 0; i < 3 ; i++) { | |
14681 | I915_WRITE(DPLL(pipe), dpll); | |
14682 | POSTING_READ(DPLL(pipe)); | |
14683 | udelay(150); /* wait for warmup */ | |
14684 | } | |
14685 | ||
14686 | I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); | |
14687 | POSTING_READ(PIPECONF(pipe)); | |
14688 | } | |
14689 | ||
14690 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) | |
14691 | { | |
14692 | DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n", | |
14693 | pipe_name(pipe)); | |
14694 | ||
14695 | assert_plane_disabled(dev_priv, PLANE_A); | |
14696 | assert_plane_disabled(dev_priv, PLANE_B); | |
14697 | ||
14698 | I915_WRITE(PIPECONF(pipe), 0); | |
14699 | POSTING_READ(PIPECONF(pipe)); | |
14700 | ||
14701 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) | |
14702 | DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe)); | |
14703 | ||
14704 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); | |
14705 | POSTING_READ(DPLL(pipe)); | |
14706 | } | |
14707 | ||
fa555837 DV |
14708 | static bool |
14709 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14710 | { | |
b7f05d4a | 14711 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 14712 | u32 val; |
fa555837 | 14713 | |
b7f05d4a | 14714 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
14715 | return true; |
14716 | ||
649636ef | 14717 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
14718 | |
14719 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14720 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14721 | return false; | |
14722 | ||
14723 | return true; | |
14724 | } | |
14725 | ||
02e93c35 VS |
14726 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
14727 | { | |
14728 | struct drm_device *dev = crtc->base.dev; | |
14729 | struct intel_encoder *encoder; | |
14730 | ||
14731 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
14732 | return true; | |
14733 | ||
14734 | return false; | |
14735 | } | |
14736 | ||
496b0fc3 ML |
14737 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
14738 | { | |
14739 | struct drm_device *dev = encoder->base.dev; | |
14740 | struct intel_connector *connector; | |
14741 | ||
14742 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
14743 | return connector; | |
14744 | ||
14745 | return NULL; | |
14746 | } | |
14747 | ||
a168f5b3 VS |
14748 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
14749 | enum transcoder pch_transcoder) | |
14750 | { | |
14751 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
14752 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
14753 | } | |
14754 | ||
aecd36b8 VS |
14755 | static void intel_sanitize_crtc(struct intel_crtc *crtc, |
14756 | struct drm_modeset_acquire_ctx *ctx) | |
24929352 DV |
14757 | { |
14758 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 14759 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 14760 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 14761 | |
24929352 | 14762 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
14763 | if (!transcoder_is_dsi(cpu_transcoder)) { |
14764 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
14765 | ||
14766 | I915_WRITE(reg, | |
14767 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
14768 | } | |
24929352 | 14769 | |
d3eaf884 | 14770 | /* restore vblank interrupts to correct state */ |
9625604c | 14771 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 14772 | if (crtc->active) { |
f9cd7b88 VS |
14773 | struct intel_plane *plane; |
14774 | ||
9625604c | 14775 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
14776 | |
14777 | /* Disable everything but the primary plane */ | |
14778 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
14779 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
14780 | continue; | |
14781 | ||
72259536 | 14782 | trace_intel_disable_plane(&plane->base, crtc); |
282dbf9b | 14783 | plane->disable_plane(plane, crtc); |
f9cd7b88 | 14784 | } |
9625604c | 14785 | } |
d3eaf884 | 14786 | |
24929352 | 14787 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14788 | * disable the crtc (and hence change the state) if it is wrong. Note |
14789 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 14790 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
14791 | bool plane; |
14792 | ||
78108b7c VS |
14793 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
14794 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
14795 | |
14796 | /* Pipe has the wrong plane attached and the plane is active. | |
14797 | * Temporarily change the plane mapping and disable everything | |
14798 | * ... */ | |
14799 | plane = crtc->plane; | |
1d4258db | 14800 | crtc->base.primary->state->visible = true; |
24929352 | 14801 | crtc->plane = !plane; |
da1d0e26 | 14802 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14803 | crtc->plane = plane; |
24929352 | 14804 | } |
24929352 DV |
14805 | |
14806 | /* Adjust the state of the output pipe according to whether we | |
14807 | * have active connectors/encoders. */ | |
842e0307 | 14808 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
da1d0e26 | 14809 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14810 | |
49cff963 | 14811 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
14812 | /* |
14813 | * We start out with underrun reporting disabled to avoid races. | |
14814 | * For correct bookkeeping mark this on active crtcs. | |
14815 | * | |
c5ab3bc0 DV |
14816 | * Also on gmch platforms we dont have any hardware bits to |
14817 | * disable the underrun reporting. Which means we need to start | |
14818 | * out with underrun reporting disabled also on inactive pipes, | |
14819 | * since otherwise we'll complain about the garbage we read when | |
14820 | * e.g. coming up after runtime pm. | |
14821 | * | |
4cc31489 DV |
14822 | * No protection against concurrent access is required - at |
14823 | * worst a fifo underrun happens which also sets this to false. | |
14824 | */ | |
14825 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
14826 | /* |
14827 | * We track the PCH trancoder underrun reporting state | |
14828 | * within the crtc. With crtc for pipe A housing the underrun | |
14829 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
14830 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
14831 | * and marking underrun reporting as disabled for the non-existing | |
14832 | * PCH transcoders B and C would prevent enabling the south | |
14833 | * error interrupt (see cpt_can_enable_serr_int()). | |
14834 | */ | |
14835 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
14836 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 14837 | } |
24929352 DV |
14838 | } |
14839 | ||
14840 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14841 | { | |
14842 | struct intel_connector *connector; | |
24929352 DV |
14843 | |
14844 | /* We need to check both for a crtc link (meaning that the | |
14845 | * encoder is active and trying to read from a pipe) and the | |
14846 | * pipe itself being active. */ | |
14847 | bool has_active_crtc = encoder->base.crtc && | |
14848 | to_intel_crtc(encoder->base.crtc)->active; | |
14849 | ||
496b0fc3 ML |
14850 | connector = intel_encoder_find_connector(encoder); |
14851 | if (connector && !has_active_crtc) { | |
24929352 DV |
14852 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
14853 | encoder->base.base.id, | |
8e329a03 | 14854 | encoder->base.name); |
24929352 DV |
14855 | |
14856 | /* Connector is active, but has no active pipe. This is | |
14857 | * fallout from our resume register restoring. Disable | |
14858 | * the encoder manually again. */ | |
14859 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
14860 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
14861 | ||
24929352 DV |
14862 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
14863 | encoder->base.base.id, | |
8e329a03 | 14864 | encoder->base.name); |
fd6bbda9 | 14865 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 14866 | if (encoder->post_disable) |
fd6bbda9 | 14867 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 14868 | } |
7f1950fb | 14869 | encoder->base.crtc = NULL; |
24929352 DV |
14870 | |
14871 | /* Inconsistent output/port/pipe state happens presumably due to | |
14872 | * a bug in one of the get_hw_state functions. Or someplace else | |
14873 | * in our code, like the register restore mess on resume. Clamp | |
14874 | * things to off as a safer default. */ | |
fd6bbda9 ML |
14875 | |
14876 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14877 | connector->base.encoder = NULL; | |
24929352 DV |
14878 | } |
14879 | /* Enabled encoders without active connectors will be fixed in | |
14880 | * the crtc fixup. */ | |
14881 | } | |
14882 | ||
29b74b7f | 14883 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 14884 | { |
920a14b2 | 14885 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 14886 | |
04098753 ID |
14887 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14888 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 14889 | i915_disable_vga(dev_priv); |
04098753 ID |
14890 | } |
14891 | } | |
14892 | ||
29b74b7f | 14893 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 14894 | { |
8dc8a27c PZ |
14895 | /* This function can be called both from intel_modeset_setup_hw_state or |
14896 | * at a very early point in our resume sequence, where the power well | |
14897 | * structures are not yet restored. Since this function is at a very | |
14898 | * paranoid "someone might have enabled VGA while we were not looking" | |
14899 | * level, just check if the power well is enabled instead of trying to | |
14900 | * follow the "don't touch the power well if we don't need it" policy | |
14901 | * the rest of the driver uses. */ | |
6392f847 | 14902 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14903 | return; |
14904 | ||
29b74b7f | 14905 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
14906 | |
14907 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
14908 | } |
14909 | ||
f9cd7b88 | 14910 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 14911 | { |
f9cd7b88 | 14912 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 14913 | |
f9cd7b88 | 14914 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
14915 | } |
14916 | ||
f9cd7b88 VS |
14917 | /* FIXME read out full plane state for all planes */ |
14918 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 14919 | { |
e9728bd8 VS |
14920 | struct intel_plane *primary = to_intel_plane(crtc->base.primary); |
14921 | bool visible; | |
d032ffa0 | 14922 | |
e9728bd8 | 14923 | visible = crtc->active && primary_get_hw_state(primary); |
b26d3ea3 | 14924 | |
e9728bd8 VS |
14925 | intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), |
14926 | to_intel_plane_state(primary->base.state), | |
14927 | visible); | |
98ec7739 VS |
14928 | } |
14929 | ||
30e984df | 14930 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 14931 | { |
fac5e23e | 14932 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 14933 | enum pipe pipe; |
24929352 DV |
14934 | struct intel_crtc *crtc; |
14935 | struct intel_encoder *encoder; | |
14936 | struct intel_connector *connector; | |
f9e905ca | 14937 | struct drm_connector_list_iter conn_iter; |
5358901f | 14938 | int i; |
24929352 | 14939 | |
565602d7 ML |
14940 | dev_priv->active_crtcs = 0; |
14941 | ||
d3fcc808 | 14942 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
14943 | struct intel_crtc_state *crtc_state = |
14944 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 14945 | |
ec2dc6a0 | 14946 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
14947 | memset(crtc_state, 0, sizeof(*crtc_state)); |
14948 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 14949 | |
565602d7 ML |
14950 | crtc_state->base.active = crtc_state->base.enable = |
14951 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
14952 | ||
14953 | crtc->base.enabled = crtc_state->base.enable; | |
14954 | crtc->active = crtc_state->base.active; | |
14955 | ||
aca1ebf4 | 14956 | if (crtc_state->base.active) |
565602d7 ML |
14957 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
14958 | ||
f9cd7b88 | 14959 | readout_plane_state(crtc); |
24929352 | 14960 | |
78108b7c VS |
14961 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
14962 | crtc->base.base.id, crtc->base.name, | |
a8cd6da0 | 14963 | enableddisabled(crtc_state->base.active)); |
24929352 DV |
14964 | } |
14965 | ||
5358901f DV |
14966 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14967 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14968 | ||
2edd6443 | 14969 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
2c42e535 ACO |
14970 | &pll->state.hw_state); |
14971 | pll->state.crtc_mask = 0; | |
d3fcc808 | 14972 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
14973 | struct intel_crtc_state *crtc_state = |
14974 | to_intel_crtc_state(crtc->base.state); | |
14975 | ||
14976 | if (crtc_state->base.active && | |
14977 | crtc_state->shared_dpll == pll) | |
2c42e535 | 14978 | pll->state.crtc_mask |= 1 << crtc->pipe; |
5358901f | 14979 | } |
2c42e535 | 14980 | pll->active_mask = pll->state.crtc_mask; |
5358901f | 14981 | |
1e6f2ddc | 14982 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
2c42e535 | 14983 | pll->name, pll->state.crtc_mask, pll->on); |
5358901f DV |
14984 | } |
14985 | ||
b2784e15 | 14986 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14987 | pipe = 0; |
14988 | ||
14989 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
14990 | struct intel_crtc_state *crtc_state; |
14991 | ||
98187836 | 14992 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 14993 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 14994 | |
045ac3b5 | 14995 | encoder->base.crtc = &crtc->base; |
a8cd6da0 VS |
14996 | crtc_state->output_types |= 1 << encoder->type; |
14997 | encoder->get_config(encoder, crtc_state); | |
24929352 DV |
14998 | } else { |
14999 | encoder->base.crtc = NULL; | |
15000 | } | |
15001 | ||
6f2bcceb | 15002 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
15003 | encoder->base.base.id, encoder->base.name, |
15004 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 15005 | pipe_name(pipe)); |
24929352 DV |
15006 | } |
15007 | ||
f9e905ca DV |
15008 | drm_connector_list_iter_begin(dev, &conn_iter); |
15009 | for_each_intel_connector_iter(connector, &conn_iter) { | |
24929352 DV |
15010 | if (connector->get_hw_state(connector)) { |
15011 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15012 | |
15013 | encoder = connector->encoder; | |
15014 | connector->base.encoder = &encoder->base; | |
15015 | ||
15016 | if (encoder->base.crtc && | |
15017 | encoder->base.crtc->state->active) { | |
15018 | /* | |
15019 | * This has to be done during hardware readout | |
15020 | * because anything calling .crtc_disable may | |
15021 | * rely on the connector_mask being accurate. | |
15022 | */ | |
15023 | encoder->base.crtc->state->connector_mask |= | |
15024 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15025 | encoder->base.crtc->state->encoder_mask |= |
15026 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15027 | } |
15028 | ||
24929352 DV |
15029 | } else { |
15030 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15031 | connector->base.encoder = NULL; | |
15032 | } | |
15033 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
15034 | connector->base.base.id, connector->base.name, |
15035 | enableddisabled(connector->base.encoder)); | |
24929352 | 15036 | } |
f9e905ca | 15037 | drm_connector_list_iter_end(&conn_iter); |
7f4c6284 VS |
15038 | |
15039 | for_each_intel_crtc(dev, crtc) { | |
a8cd6da0 VS |
15040 | struct intel_crtc_state *crtc_state = |
15041 | to_intel_crtc_state(crtc->base.state); | |
d305e061 | 15042 | int min_cdclk = 0; |
aca1ebf4 | 15043 | |
7f4c6284 | 15044 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
a8cd6da0 VS |
15045 | if (crtc_state->base.active) { |
15046 | intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); | |
15047 | intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); | |
7f4c6284 VS |
15048 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
15049 | ||
15050 | /* | |
15051 | * The initial mode needs to be set in order to keep | |
15052 | * the atomic core happy. It wants a valid mode if the | |
15053 | * crtc's enabled, so we do the above call. | |
15054 | * | |
7800fb69 DV |
15055 | * But we don't set all the derived state fully, hence |
15056 | * set a flag to indicate that a full recalculation is | |
15057 | * needed on the next commit. | |
7f4c6284 | 15058 | */ |
a8cd6da0 | 15059 | crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; |
9eca6832 | 15060 | |
a7d1b3f4 VS |
15061 | intel_crtc_compute_pixel_rate(crtc_state); |
15062 | ||
9c61de4c | 15063 | if (dev_priv->display.modeset_calc_cdclk) { |
d305e061 | 15064 | min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); |
9c61de4c VS |
15065 | if (WARN_ON(min_cdclk < 0)) |
15066 | min_cdclk = 0; | |
15067 | } | |
aca1ebf4 | 15068 | |
5caa0fea DV |
15069 | drm_calc_timestamping_constants(&crtc->base, |
15070 | &crtc_state->base.adjusted_mode); | |
9eca6832 | 15071 | update_scanline_offset(crtc); |
7f4c6284 | 15072 | } |
e3b247da | 15073 | |
d305e061 | 15074 | dev_priv->min_cdclk[crtc->pipe] = min_cdclk; |
aca1ebf4 | 15075 | |
a8cd6da0 | 15076 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 15077 | } |
30e984df DV |
15078 | } |
15079 | ||
62b69566 ACO |
15080 | static void |
15081 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
15082 | { | |
15083 | struct intel_encoder *encoder; | |
15084 | ||
15085 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
15086 | u64 get_domains; | |
15087 | enum intel_display_power_domain domain; | |
15088 | ||
15089 | if (!encoder->get_power_domains) | |
15090 | continue; | |
15091 | ||
15092 | get_domains = encoder->get_power_domains(encoder); | |
15093 | for_each_power_domain(domain, get_domains) | |
15094 | intel_display_power_get(dev_priv, domain); | |
15095 | } | |
15096 | } | |
15097 | ||
043e9bda ML |
15098 | /* Scan out the current hw modeset state, |
15099 | * and sanitizes it to the current state | |
15100 | */ | |
15101 | static void | |
aecd36b8 VS |
15102 | intel_modeset_setup_hw_state(struct drm_device *dev, |
15103 | struct drm_modeset_acquire_ctx *ctx) | |
30e984df | 15104 | { |
fac5e23e | 15105 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 15106 | enum pipe pipe; |
30e984df DV |
15107 | struct intel_crtc *crtc; |
15108 | struct intel_encoder *encoder; | |
35c95375 | 15109 | int i; |
30e984df DV |
15110 | |
15111 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15112 | |
15113 | /* HW state is read out, now we need to sanitize this mess. */ | |
62b69566 ACO |
15114 | get_encoder_power_domains(dev_priv); |
15115 | ||
b2784e15 | 15116 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15117 | intel_sanitize_encoder(encoder); |
15118 | } | |
15119 | ||
055e393f | 15120 | for_each_pipe(dev_priv, pipe) { |
98187836 | 15121 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 15122 | |
aecd36b8 | 15123 | intel_sanitize_crtc(crtc, ctx); |
6e3c9717 ACO |
15124 | intel_dump_pipe_config(crtc, crtc->config, |
15125 | "[setup_hw_state]"); | |
24929352 | 15126 | } |
9a935856 | 15127 | |
d29b2f9d ACO |
15128 | intel_modeset_update_connector_atomic_state(dev); |
15129 | ||
35c95375 DV |
15130 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15131 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15132 | ||
2dd66ebd | 15133 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15134 | continue; |
15135 | ||
15136 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15137 | ||
2edd6443 | 15138 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15139 | pll->on = false; |
15140 | } | |
15141 | ||
04548cba VS |
15142 | if (IS_G4X(dev_priv)) { |
15143 | g4x_wm_get_hw_state(dev); | |
15144 | g4x_wm_sanitize(dev_priv); | |
15145 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
6eb1a681 | 15146 | vlv_wm_get_hw_state(dev); |
602ae835 | 15147 | vlv_wm_sanitize(dev_priv); |
a029fa4d | 15148 | } else if (INTEL_GEN(dev_priv) >= 9) { |
3078999f | 15149 | skl_wm_get_hw_state(dev); |
602ae835 | 15150 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
243e6a44 | 15151 | ilk_wm_get_hw_state(dev); |
602ae835 | 15152 | } |
292b990e ML |
15153 | |
15154 | for_each_intel_crtc(dev, crtc) { | |
d8fc70b7 | 15155 | u64 put_domains; |
292b990e | 15156 | |
74bff5f9 | 15157 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15158 | if (WARN_ON(put_domains)) |
15159 | modeset_put_power_domains(dev_priv, put_domains); | |
15160 | } | |
15161 | intel_display_set_init_power(dev_priv, false); | |
010cf73d | 15162 | |
8d8c386c ID |
15163 | intel_power_domains_verify_state(dev_priv); |
15164 | ||
010cf73d | 15165 | intel_fbc_init_pipe_state(dev_priv); |
043e9bda | 15166 | } |
7d0bc1ea | 15167 | |
043e9bda ML |
15168 | void intel_display_resume(struct drm_device *dev) |
15169 | { | |
e2c8b870 ML |
15170 | struct drm_i915_private *dev_priv = to_i915(dev); |
15171 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15172 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15173 | int ret; |
f30da187 | 15174 | |
e2c8b870 | 15175 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
15176 | if (state) |
15177 | state->acquire_ctx = &ctx; | |
043e9bda | 15178 | |
e2c8b870 | 15179 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15180 | |
73974893 ML |
15181 | while (1) { |
15182 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
15183 | if (ret != -EDEADLK) | |
15184 | break; | |
043e9bda | 15185 | |
e2c8b870 | 15186 | drm_modeset_backoff(&ctx); |
e2c8b870 | 15187 | } |
043e9bda | 15188 | |
73974893 | 15189 | if (!ret) |
581e49fe | 15190 | ret = __intel_display_resume(dev, state, &ctx); |
73974893 | 15191 | |
2503a0fe | 15192 | intel_enable_ipc(dev_priv); |
e2c8b870 ML |
15193 | drm_modeset_drop_locks(&ctx); |
15194 | drm_modeset_acquire_fini(&ctx); | |
043e9bda | 15195 | |
0853695c | 15196 | if (ret) |
e2c8b870 | 15197 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
3c5e37f1 CW |
15198 | if (state) |
15199 | drm_atomic_state_put(state); | |
2c7111db CW |
15200 | } |
15201 | ||
15202 | void intel_modeset_gem_init(struct drm_device *dev) | |
15203 | { | |
dc97997a | 15204 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15205 | |
dc97997a | 15206 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15207 | |
1ee8da6d | 15208 | intel_setup_overlay(dev_priv); |
1ebaa0b9 CW |
15209 | } |
15210 | ||
15211 | int intel_connector_register(struct drm_connector *connector) | |
15212 | { | |
15213 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
15214 | int ret; | |
15215 | ||
15216 | ret = intel_backlight_device_register(intel_connector); | |
15217 | if (ret) | |
15218 | goto err; | |
15219 | ||
15220 | return 0; | |
0962c3c9 | 15221 | |
1ebaa0b9 CW |
15222 | err: |
15223 | return ret; | |
79e53945 JB |
15224 | } |
15225 | ||
c191eca1 | 15226 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 15227 | { |
e63d87c0 | 15228 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 15229 | |
e63d87c0 | 15230 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 15231 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
15232 | } |
15233 | ||
79e53945 JB |
15234 | void intel_modeset_cleanup(struct drm_device *dev) |
15235 | { | |
fac5e23e | 15236 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 15237 | |
eb955eee CW |
15238 | flush_work(&dev_priv->atomic_helper.free_work); |
15239 | WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); | |
15240 | ||
dc97997a | 15241 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 15242 | |
fd0c0642 DV |
15243 | /* |
15244 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15245 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15246 | * experience fancy races otherwise. |
15247 | */ | |
2aeb7d3a | 15248 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15249 | |
fd0c0642 DV |
15250 | /* |
15251 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15252 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15253 | */ | |
f87ea761 | 15254 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15255 | |
4f256d82 DV |
15256 | /* poll work can call into fbdev, hence clean that up afterwards */ |
15257 | intel_fbdev_fini(dev_priv); | |
15258 | ||
723bfd70 JB |
15259 | intel_unregister_dsm_handler(); |
15260 | ||
c937ab3e | 15261 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15262 | |
1630fe75 CW |
15263 | /* flush any delayed tasks or pending work */ |
15264 | flush_scheduled_work(); | |
15265 | ||
79e53945 | 15266 | drm_mode_config_cleanup(dev); |
4d7bb011 | 15267 | |
1ee8da6d | 15268 | intel_cleanup_overlay(dev_priv); |
ae48434c | 15269 | |
dc97997a | 15270 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 15271 | |
40196446 | 15272 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
15273 | } |
15274 | ||
df0e9248 CW |
15275 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15276 | struct intel_encoder *encoder) | |
15277 | { | |
15278 | connector->encoder = encoder; | |
15279 | drm_mode_connector_attach_encoder(&connector->base, | |
15280 | &encoder->base); | |
79e53945 | 15281 | } |
28d52043 DA |
15282 | |
15283 | /* | |
15284 | * set vga decode state - true == enable VGA decode | |
15285 | */ | |
6315b5d3 | 15286 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 15287 | { |
6315b5d3 | 15288 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15289 | u16 gmch_ctrl; |
15290 | ||
75fa041d CW |
15291 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15292 | DRM_ERROR("failed to read control word\n"); | |
15293 | return -EIO; | |
15294 | } | |
15295 | ||
c0cc8a55 CW |
15296 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15297 | return 0; | |
15298 | ||
28d52043 DA |
15299 | if (state) |
15300 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15301 | else | |
15302 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15303 | |
15304 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15305 | DRM_ERROR("failed to write control word\n"); | |
15306 | return -EIO; | |
15307 | } | |
15308 | ||
28d52043 DA |
15309 | return 0; |
15310 | } | |
c4a1d9e4 | 15311 | |
98a2f411 CW |
15312 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
15313 | ||
c4a1d9e4 | 15314 | struct intel_display_error_state { |
ff57f1b0 PZ |
15315 | |
15316 | u32 power_well_driver; | |
15317 | ||
63b66e5b CW |
15318 | int num_transcoders; |
15319 | ||
c4a1d9e4 CW |
15320 | struct intel_cursor_error_state { |
15321 | u32 control; | |
15322 | u32 position; | |
15323 | u32 base; | |
15324 | u32 size; | |
52331309 | 15325 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15326 | |
15327 | struct intel_pipe_error_state { | |
ddf9c536 | 15328 | bool power_domain_on; |
c4a1d9e4 | 15329 | u32 source; |
f301b1e1 | 15330 | u32 stat; |
52331309 | 15331 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15332 | |
15333 | struct intel_plane_error_state { | |
15334 | u32 control; | |
15335 | u32 stride; | |
15336 | u32 size; | |
15337 | u32 pos; | |
15338 | u32 addr; | |
15339 | u32 surface; | |
15340 | u32 tile_offset; | |
52331309 | 15341 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15342 | |
15343 | struct intel_transcoder_error_state { | |
ddf9c536 | 15344 | bool power_domain_on; |
63b66e5b CW |
15345 | enum transcoder cpu_transcoder; |
15346 | ||
15347 | u32 conf; | |
15348 | ||
15349 | u32 htotal; | |
15350 | u32 hblank; | |
15351 | u32 hsync; | |
15352 | u32 vtotal; | |
15353 | u32 vblank; | |
15354 | u32 vsync; | |
15355 | } transcoder[4]; | |
c4a1d9e4 CW |
15356 | }; |
15357 | ||
15358 | struct intel_display_error_state * | |
c033666a | 15359 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 15360 | { |
c4a1d9e4 | 15361 | struct intel_display_error_state *error; |
63b66e5b CW |
15362 | int transcoders[] = { |
15363 | TRANSCODER_A, | |
15364 | TRANSCODER_B, | |
15365 | TRANSCODER_C, | |
15366 | TRANSCODER_EDP, | |
15367 | }; | |
c4a1d9e4 CW |
15368 | int i; |
15369 | ||
c033666a | 15370 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
15371 | return NULL; |
15372 | ||
9d1cb914 | 15373 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15374 | if (error == NULL) |
15375 | return NULL; | |
15376 | ||
c033666a | 15377 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
9c3a16c8 ID |
15378 | error->power_well_driver = |
15379 | I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)); | |
ff57f1b0 | 15380 | |
055e393f | 15381 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15382 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15383 | __intel_display_power_is_enabled(dev_priv, |
15384 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15385 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15386 | continue; |
15387 | ||
5efb3e28 VS |
15388 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15389 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15390 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15391 | |
15392 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15393 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 15394 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 15395 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15396 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15397 | } | |
c033666a | 15398 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 15399 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 15400 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
15401 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
15402 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15403 | } | |
15404 | ||
c4a1d9e4 | 15405 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15406 | |
c033666a | 15407 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 15408 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15409 | } |
15410 | ||
4d1de975 | 15411 | /* Note: this does not include DSI transcoders. */ |
c033666a | 15412 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 15413 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
15414 | error->num_transcoders++; /* Account for eDP. */ |
15415 | ||
15416 | for (i = 0; i < error->num_transcoders; i++) { | |
15417 | enum transcoder cpu_transcoder = transcoders[i]; | |
15418 | ||
ddf9c536 | 15419 | error->transcoder[i].power_domain_on = |
f458ebbc | 15420 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15421 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15422 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15423 | continue; |
15424 | ||
63b66e5b CW |
15425 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15426 | ||
15427 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15428 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15429 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15430 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15431 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15432 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15433 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15434 | } |
15435 | ||
15436 | return error; | |
15437 | } | |
15438 | ||
edc3d884 MK |
15439 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15440 | ||
c4a1d9e4 | 15441 | void |
edc3d884 | 15442 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15443 | struct intel_display_error_state *error) |
15444 | { | |
5a4c6f1b | 15445 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
15446 | int i; |
15447 | ||
63b66e5b CW |
15448 | if (!error) |
15449 | return; | |
15450 | ||
b7f05d4a | 15451 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 15452 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 15453 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15454 | error->power_well_driver); |
055e393f | 15455 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15456 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 15457 | err_printf(m, " Power: %s\n", |
87ad3212 | 15458 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 15459 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15460 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15461 | |
15462 | err_printf(m, "Plane [%d]:\n", i); | |
15463 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15464 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 15465 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
15466 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15467 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15468 | } |
772c2a51 | 15469 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 15470 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 15471 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
15472 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15473 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15474 | } |
15475 | ||
edc3d884 MK |
15476 | err_printf(m, "Cursor [%d]:\n", i); |
15477 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15478 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15479 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15480 | } |
63b66e5b CW |
15481 | |
15482 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15483 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15484 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15485 | err_printf(m, " Power: %s\n", |
87ad3212 | 15486 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15487 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15488 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15489 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15490 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15491 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15492 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15493 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15494 | } | |
c4a1d9e4 | 15495 | } |
98a2f411 CW |
15496 | |
15497 | #endif |