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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
57822dc6 | 40 | #include "i915_gem_clflush.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
5a21b665 DV |
52 | static bool is_mmio_work(struct intel_flip_work *work) |
53 | { | |
54 | return work->mmio_work.func; | |
55 | } | |
56 | ||
465c120c | 57 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 58 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
59 | DRM_FORMAT_C8, |
60 | DRM_FORMAT_RGB565, | |
465c120c | 61 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 62 | DRM_FORMAT_XRGB8888, |
465c120c MR |
63 | }; |
64 | ||
65 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 66 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
70 | DRM_FORMAT_XBGR8888, | |
71 | DRM_FORMAT_XRGB2101010, | |
72 | DRM_FORMAT_XBGR2101010, | |
73 | }; | |
74 | ||
75 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
76 | DRM_FORMAT_C8, |
77 | DRM_FORMAT_RGB565, | |
78 | DRM_FORMAT_XRGB8888, | |
465c120c | 79 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 80 | DRM_FORMAT_ARGB8888, |
465c120c MR |
81 | DRM_FORMAT_ABGR8888, |
82 | DRM_FORMAT_XRGB2101010, | |
465c120c | 83 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
84 | DRM_FORMAT_YUYV, |
85 | DRM_FORMAT_YVYU, | |
86 | DRM_FORMAT_UYVY, | |
87 | DRM_FORMAT_VYUY, | |
465c120c MR |
88 | }; |
89 | ||
3d7d6510 MR |
90 | /* Cursor formats */ |
91 | static const uint32_t intel_cursor_formats[] = { | |
92 | DRM_FORMAT_ARGB8888, | |
93 | }; | |
94 | ||
f1f644dc | 95 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 96 | struct intel_crtc_state *pipe_config); |
18442d08 | 97 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 98 | struct intel_crtc_state *pipe_config); |
f1f644dc | 99 | |
24dbf51a CW |
100 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
101 | struct drm_i915_gem_object *obj, | |
102 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
1c74eeaf NM |
118 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
119 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
120 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
121 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
122 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 123 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 124 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 125 | |
d4906093 | 126 | struct intel_limit { |
4c5def93 ACO |
127 | struct { |
128 | int min, max; | |
129 | } dot, vco, n, m, m1, m2, p, p1; | |
130 | ||
131 | struct { | |
132 | int dot_limit; | |
133 | int p2_slow, p2_fast; | |
134 | } p2; | |
d4906093 | 135 | }; |
79e53945 | 136 | |
bfa7df01 | 137 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 138 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
139 | { |
140 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
141 | ||
142 | /* Obtain SKU information */ | |
143 | mutex_lock(&dev_priv->sb_lock); | |
144 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
145 | CCK_FUSE_HPLL_FREQ_MASK; | |
146 | mutex_unlock(&dev_priv->sb_lock); | |
147 | ||
148 | return vco_freq[hpll_freq] * 1000; | |
149 | } | |
150 | ||
c30fec65 VS |
151 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
152 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
153 | { |
154 | u32 val; | |
155 | int divider; | |
156 | ||
bfa7df01 VS |
157 | mutex_lock(&dev_priv->sb_lock); |
158 | val = vlv_cck_read(dev_priv, reg); | |
159 | mutex_unlock(&dev_priv->sb_lock); | |
160 | ||
161 | divider = val & CCK_FREQUENCY_VALUES; | |
162 | ||
163 | WARN((val & CCK_FREQUENCY_STATUS) != | |
164 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
165 | "%s change in progress\n", name); | |
166 | ||
c30fec65 VS |
167 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
168 | } | |
169 | ||
7ff89ca2 VS |
170 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
171 | const char *name, u32 reg) | |
c30fec65 VS |
172 | { |
173 | if (dev_priv->hpll_freq == 0) | |
49cd97a3 | 174 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 VS |
175 | |
176 | return vlv_get_cck_clock(dev_priv, name, reg, | |
177 | dev_priv->hpll_freq); | |
bfa7df01 VS |
178 | } |
179 | ||
bfa7df01 VS |
180 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
181 | { | |
666a4537 | 182 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
183 | return; |
184 | ||
185 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
186 | CCK_CZ_CLOCK_CONTROL); | |
187 | ||
188 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
189 | } | |
190 | ||
021357ac | 191 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
192 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
193 | const struct intel_crtc_state *pipe_config) | |
021357ac | 194 | { |
21a727b3 VS |
195 | if (HAS_DDI(dev_priv)) |
196 | return pipe_config->port_clock; /* SPLL */ | |
197 | else if (IS_GEN5(dev_priv)) | |
198 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 199 | else |
21a727b3 | 200 | return 270000; |
021357ac CW |
201 | } |
202 | ||
1b6f4958 | 203 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 204 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 205 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 206 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
207 | .m = { .min = 96, .max = 140 }, |
208 | .m1 = { .min = 18, .max = 26 }, | |
209 | .m2 = { .min = 6, .max = 16 }, | |
210 | .p = { .min = 4, .max = 128 }, | |
211 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
212 | .p2 = { .dot_limit = 165000, |
213 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
214 | }; |
215 | ||
1b6f4958 | 216 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 217 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 218 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 219 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
220 | .m = { .min = 96, .max = 140 }, |
221 | .m1 = { .min = 18, .max = 26 }, | |
222 | .m2 = { .min = 6, .max = 16 }, | |
223 | .p = { .min = 4, .max = 128 }, | |
224 | .p1 = { .min = 2, .max = 33 }, | |
225 | .p2 = { .dot_limit = 165000, | |
226 | .p2_slow = 4, .p2_fast = 4 }, | |
227 | }; | |
228 | ||
1b6f4958 | 229 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 230 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 231 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 232 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
233 | .m = { .min = 96, .max = 140 }, |
234 | .m1 = { .min = 18, .max = 26 }, | |
235 | .m2 = { .min = 6, .max = 16 }, | |
236 | .p = { .min = 4, .max = 128 }, | |
237 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
238 | .p2 = { .dot_limit = 165000, |
239 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 240 | }; |
273e27ca | 241 | |
1b6f4958 | 242 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
243 | .dot = { .min = 20000, .max = 400000 }, |
244 | .vco = { .min = 1400000, .max = 2800000 }, | |
245 | .n = { .min = 1, .max = 6 }, | |
246 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
247 | .m1 = { .min = 8, .max = 18 }, |
248 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
249 | .p = { .min = 5, .max = 80 }, |
250 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
251 | .p2 = { .dot_limit = 200000, |
252 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
253 | }; |
254 | ||
1b6f4958 | 255 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
256 | .dot = { .min = 20000, .max = 400000 }, |
257 | .vco = { .min = 1400000, .max = 2800000 }, | |
258 | .n = { .min = 1, .max = 6 }, | |
259 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
260 | .m1 = { .min = 8, .max = 18 }, |
261 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
262 | .p = { .min = 7, .max = 98 }, |
263 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
264 | .p2 = { .dot_limit = 112000, |
265 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
266 | }; |
267 | ||
273e27ca | 268 | |
1b6f4958 | 269 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
270 | .dot = { .min = 25000, .max = 270000 }, |
271 | .vco = { .min = 1750000, .max = 3500000}, | |
272 | .n = { .min = 1, .max = 4 }, | |
273 | .m = { .min = 104, .max = 138 }, | |
274 | .m1 = { .min = 17, .max = 23 }, | |
275 | .m2 = { .min = 5, .max = 11 }, | |
276 | .p = { .min = 10, .max = 30 }, | |
277 | .p1 = { .min = 1, .max = 3}, | |
278 | .p2 = { .dot_limit = 270000, | |
279 | .p2_slow = 10, | |
280 | .p2_fast = 10 | |
044c7c41 | 281 | }, |
e4b36699 KP |
282 | }; |
283 | ||
1b6f4958 | 284 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
285 | .dot = { .min = 22000, .max = 400000 }, |
286 | .vco = { .min = 1750000, .max = 3500000}, | |
287 | .n = { .min = 1, .max = 4 }, | |
288 | .m = { .min = 104, .max = 138 }, | |
289 | .m1 = { .min = 16, .max = 23 }, | |
290 | .m2 = { .min = 5, .max = 11 }, | |
291 | .p = { .min = 5, .max = 80 }, | |
292 | .p1 = { .min = 1, .max = 8}, | |
293 | .p2 = { .dot_limit = 165000, | |
294 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
295 | }; |
296 | ||
1b6f4958 | 297 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
298 | .dot = { .min = 20000, .max = 115000 }, |
299 | .vco = { .min = 1750000, .max = 3500000 }, | |
300 | .n = { .min = 1, .max = 3 }, | |
301 | .m = { .min = 104, .max = 138 }, | |
302 | .m1 = { .min = 17, .max = 23 }, | |
303 | .m2 = { .min = 5, .max = 11 }, | |
304 | .p = { .min = 28, .max = 112 }, | |
305 | .p1 = { .min = 2, .max = 8 }, | |
306 | .p2 = { .dot_limit = 0, | |
307 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 308 | }, |
e4b36699 KP |
309 | }; |
310 | ||
1b6f4958 | 311 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
312 | .dot = { .min = 80000, .max = 224000 }, |
313 | .vco = { .min = 1750000, .max = 3500000 }, | |
314 | .n = { .min = 1, .max = 3 }, | |
315 | .m = { .min = 104, .max = 138 }, | |
316 | .m1 = { .min = 17, .max = 23 }, | |
317 | .m2 = { .min = 5, .max = 11 }, | |
318 | .p = { .min = 14, .max = 42 }, | |
319 | .p1 = { .min = 2, .max = 6 }, | |
320 | .p2 = { .dot_limit = 0, | |
321 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 322 | }, |
e4b36699 KP |
323 | }; |
324 | ||
1b6f4958 | 325 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
326 | .dot = { .min = 20000, .max = 400000}, |
327 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 328 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
329 | .n = { .min = 3, .max = 6 }, |
330 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 331 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
332 | .m1 = { .min = 0, .max = 0 }, |
333 | .m2 = { .min = 0, .max = 254 }, | |
334 | .p = { .min = 5, .max = 80 }, | |
335 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
336 | .p2 = { .dot_limit = 200000, |
337 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
338 | }; |
339 | ||
1b6f4958 | 340 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
341 | .dot = { .min = 20000, .max = 400000 }, |
342 | .vco = { .min = 1700000, .max = 3500000 }, | |
343 | .n = { .min = 3, .max = 6 }, | |
344 | .m = { .min = 2, .max = 256 }, | |
345 | .m1 = { .min = 0, .max = 0 }, | |
346 | .m2 = { .min = 0, .max = 254 }, | |
347 | .p = { .min = 7, .max = 112 }, | |
348 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
349 | .p2 = { .dot_limit = 112000, |
350 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
351 | }; |
352 | ||
273e27ca EA |
353 | /* Ironlake / Sandybridge |
354 | * | |
355 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
356 | * the range value for them is (actual_value - 2). | |
357 | */ | |
1b6f4958 | 358 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
359 | .dot = { .min = 25000, .max = 350000 }, |
360 | .vco = { .min = 1760000, .max = 3510000 }, | |
361 | .n = { .min = 1, .max = 5 }, | |
362 | .m = { .min = 79, .max = 127 }, | |
363 | .m1 = { .min = 12, .max = 22 }, | |
364 | .m2 = { .min = 5, .max = 9 }, | |
365 | .p = { .min = 5, .max = 80 }, | |
366 | .p1 = { .min = 1, .max = 8 }, | |
367 | .p2 = { .dot_limit = 225000, | |
368 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
369 | }; |
370 | ||
1b6f4958 | 371 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
372 | .dot = { .min = 25000, .max = 350000 }, |
373 | .vco = { .min = 1760000, .max = 3510000 }, | |
374 | .n = { .min = 1, .max = 3 }, | |
375 | .m = { .min = 79, .max = 118 }, | |
376 | .m1 = { .min = 12, .max = 22 }, | |
377 | .m2 = { .min = 5, .max = 9 }, | |
378 | .p = { .min = 28, .max = 112 }, | |
379 | .p1 = { .min = 2, .max = 8 }, | |
380 | .p2 = { .dot_limit = 225000, | |
381 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
382 | }; |
383 | ||
1b6f4958 | 384 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
385 | .dot = { .min = 25000, .max = 350000 }, |
386 | .vco = { .min = 1760000, .max = 3510000 }, | |
387 | .n = { .min = 1, .max = 3 }, | |
388 | .m = { .min = 79, .max = 127 }, | |
389 | .m1 = { .min = 12, .max = 22 }, | |
390 | .m2 = { .min = 5, .max = 9 }, | |
391 | .p = { .min = 14, .max = 56 }, | |
392 | .p1 = { .min = 2, .max = 8 }, | |
393 | .p2 = { .dot_limit = 225000, | |
394 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
395 | }; |
396 | ||
273e27ca | 397 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 398 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
399 | .dot = { .min = 25000, .max = 350000 }, |
400 | .vco = { .min = 1760000, .max = 3510000 }, | |
401 | .n = { .min = 1, .max = 2 }, | |
402 | .m = { .min = 79, .max = 126 }, | |
403 | .m1 = { .min = 12, .max = 22 }, | |
404 | .m2 = { .min = 5, .max = 9 }, | |
405 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 406 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
407 | .p2 = { .dot_limit = 225000, |
408 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
409 | }; |
410 | ||
1b6f4958 | 411 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
412 | .dot = { .min = 25000, .max = 350000 }, |
413 | .vco = { .min = 1760000, .max = 3510000 }, | |
414 | .n = { .min = 1, .max = 3 }, | |
415 | .m = { .min = 79, .max = 126 }, | |
416 | .m1 = { .min = 12, .max = 22 }, | |
417 | .m2 = { .min = 5, .max = 9 }, | |
418 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 419 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
420 | .p2 = { .dot_limit = 225000, |
421 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
422 | }; |
423 | ||
1b6f4958 | 424 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
425 | /* |
426 | * These are the data rate limits (measured in fast clocks) | |
427 | * since those are the strictest limits we have. The fast | |
428 | * clock and actual rate limits are more relaxed, so checking | |
429 | * them would make no difference. | |
430 | */ | |
431 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 432 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 433 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
434 | .m1 = { .min = 2, .max = 3 }, |
435 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 436 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 437 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
438 | }; |
439 | ||
1b6f4958 | 440 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
441 | /* |
442 | * These are the data rate limits (measured in fast clocks) | |
443 | * since those are the strictest limits we have. The fast | |
444 | * clock and actual rate limits are more relaxed, so checking | |
445 | * them would make no difference. | |
446 | */ | |
447 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 448 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
449 | .n = { .min = 1, .max = 1 }, |
450 | .m1 = { .min = 2, .max = 2 }, | |
451 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
452 | .p1 = { .min = 2, .max = 4 }, | |
453 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
454 | }; | |
455 | ||
1b6f4958 | 456 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
457 | /* FIXME: find real dot limits */ |
458 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 459 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
460 | .n = { .min = 1, .max = 1 }, |
461 | .m1 = { .min = 2, .max = 2 }, | |
462 | /* FIXME: find real m2 limits */ | |
463 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
464 | .p1 = { .min = 2, .max = 4 }, | |
465 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
466 | }; | |
467 | ||
cdba954e ACO |
468 | static bool |
469 | needs_modeset(struct drm_crtc_state *state) | |
470 | { | |
fc596660 | 471 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
472 | } |
473 | ||
dccbea3b ID |
474 | /* |
475 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
476 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
477 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
478 | * The helpers' return value is the rate of the clock that is fed to the | |
479 | * display engine's pipe which can be the above fast dot clock rate or a | |
480 | * divided-down version of it. | |
481 | */ | |
f2b115e6 | 482 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 483 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 484 | { |
2177832f SL |
485 | clock->m = clock->m2 + 2; |
486 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 487 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 488 | return 0; |
fb03ac01 VS |
489 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
490 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
491 | |
492 | return clock->dot; | |
2177832f SL |
493 | } |
494 | ||
7429e9d4 DV |
495 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
496 | { | |
497 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
498 | } | |
499 | ||
9e2c8475 | 500 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 501 | { |
7429e9d4 | 502 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 503 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 504 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 505 | return 0; |
fb03ac01 VS |
506 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
507 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
508 | |
509 | return clock->dot; | |
79e53945 JB |
510 | } |
511 | ||
9e2c8475 | 512 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
513 | { |
514 | clock->m = clock->m1 * clock->m2; | |
515 | clock->p = clock->p1 * clock->p2; | |
516 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 517 | return 0; |
589eca67 ID |
518 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
519 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
520 | |
521 | return clock->dot / 5; | |
589eca67 ID |
522 | } |
523 | ||
9e2c8475 | 524 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
525 | { |
526 | clock->m = clock->m1 * clock->m2; | |
527 | clock->p = clock->p1 * clock->p2; | |
528 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 529 | return 0; |
ef9348c8 CML |
530 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
531 | clock->n << 22); | |
532 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
533 | |
534 | return clock->dot / 5; | |
ef9348c8 CML |
535 | } |
536 | ||
7c04d1d9 | 537 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
538 | /** |
539 | * Returns whether the given set of divisors are valid for a given refclk with | |
540 | * the given connectors. | |
541 | */ | |
542 | ||
e2d214ae | 543 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 544 | const struct intel_limit *limit, |
9e2c8475 | 545 | const struct dpll *clock) |
79e53945 | 546 | { |
f01b7962 VS |
547 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
548 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 549 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 550 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 551 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 552 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 553 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 554 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 555 | |
e2d214ae | 556 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 557 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
558 | if (clock->m1 <= clock->m2) |
559 | INTELPllInvalid("m1 <= m2\n"); | |
560 | ||
e2d214ae | 561 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 562 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
563 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
564 | INTELPllInvalid("p out of range\n"); | |
565 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
566 | INTELPllInvalid("m out of range\n"); | |
567 | } | |
568 | ||
79e53945 | 569 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 570 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
571 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
572 | * connector, etc., rather than just a single range. | |
573 | */ | |
574 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 575 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
576 | |
577 | return true; | |
578 | } | |
579 | ||
3b1429d9 | 580 | static int |
1b6f4958 | 581 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
582 | const struct intel_crtc_state *crtc_state, |
583 | int target) | |
79e53945 | 584 | { |
3b1429d9 | 585 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 586 | |
2d84d2b3 | 587 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 588 | /* |
a210b028 DV |
589 | * For LVDS just rely on its current settings for dual-channel. |
590 | * We haven't figured out how to reliably set up different | |
591 | * single/dual channel state, if we even can. | |
79e53945 | 592 | */ |
1974cad0 | 593 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 594 | return limit->p2.p2_fast; |
79e53945 | 595 | else |
3b1429d9 | 596 | return limit->p2.p2_slow; |
79e53945 JB |
597 | } else { |
598 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 599 | return limit->p2.p2_slow; |
79e53945 | 600 | else |
3b1429d9 | 601 | return limit->p2.p2_fast; |
79e53945 | 602 | } |
3b1429d9 VS |
603 | } |
604 | ||
70e8aa21 ACO |
605 | /* |
606 | * Returns a set of divisors for the desired target clock with the given | |
607 | * refclk, or FALSE. The returned values represent the clock equation: | |
608 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
609 | * | |
610 | * Target and reference clocks are specified in kHz. | |
611 | * | |
612 | * If match_clock is provided, then best_clock P divider must match the P | |
613 | * divider from @match_clock used for LVDS downclocking. | |
614 | */ | |
3b1429d9 | 615 | static bool |
1b6f4958 | 616 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 617 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
618 | int target, int refclk, struct dpll *match_clock, |
619 | struct dpll *best_clock) | |
3b1429d9 VS |
620 | { |
621 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 622 | struct dpll clock; |
3b1429d9 | 623 | int err = target; |
79e53945 | 624 | |
0206e353 | 625 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 626 | |
3b1429d9 VS |
627 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
628 | ||
42158660 ZY |
629 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
630 | clock.m1++) { | |
631 | for (clock.m2 = limit->m2.min; | |
632 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 633 | if (clock.m2 >= clock.m1) |
42158660 ZY |
634 | break; |
635 | for (clock.n = limit->n.min; | |
636 | clock.n <= limit->n.max; clock.n++) { | |
637 | for (clock.p1 = limit->p1.min; | |
638 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
639 | int this_err; |
640 | ||
dccbea3b | 641 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
642 | if (!intel_PLL_is_valid(to_i915(dev), |
643 | limit, | |
ac58c3f0 DV |
644 | &clock)) |
645 | continue; | |
646 | if (match_clock && | |
647 | clock.p != match_clock->p) | |
648 | continue; | |
649 | ||
650 | this_err = abs(clock.dot - target); | |
651 | if (this_err < err) { | |
652 | *best_clock = clock; | |
653 | err = this_err; | |
654 | } | |
655 | } | |
656 | } | |
657 | } | |
658 | } | |
659 | ||
660 | return (err != target); | |
661 | } | |
662 | ||
70e8aa21 ACO |
663 | /* |
664 | * Returns a set of divisors for the desired target clock with the given | |
665 | * refclk, or FALSE. The returned values represent the clock equation: | |
666 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
667 | * | |
668 | * Target and reference clocks are specified in kHz. | |
669 | * | |
670 | * If match_clock is provided, then best_clock P divider must match the P | |
671 | * divider from @match_clock used for LVDS downclocking. | |
672 | */ | |
ac58c3f0 | 673 | static bool |
1b6f4958 | 674 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 675 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
676 | int target, int refclk, struct dpll *match_clock, |
677 | struct dpll *best_clock) | |
79e53945 | 678 | { |
3b1429d9 | 679 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 680 | struct dpll clock; |
79e53945 JB |
681 | int err = target; |
682 | ||
0206e353 | 683 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 684 | |
3b1429d9 VS |
685 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
686 | ||
42158660 ZY |
687 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
688 | clock.m1++) { | |
689 | for (clock.m2 = limit->m2.min; | |
690 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
691 | for (clock.n = limit->n.min; |
692 | clock.n <= limit->n.max; clock.n++) { | |
693 | for (clock.p1 = limit->p1.min; | |
694 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
695 | int this_err; |
696 | ||
dccbea3b | 697 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
698 | if (!intel_PLL_is_valid(to_i915(dev), |
699 | limit, | |
1b894b59 | 700 | &clock)) |
79e53945 | 701 | continue; |
cec2f356 SP |
702 | if (match_clock && |
703 | clock.p != match_clock->p) | |
704 | continue; | |
79e53945 JB |
705 | |
706 | this_err = abs(clock.dot - target); | |
707 | if (this_err < err) { | |
708 | *best_clock = clock; | |
709 | err = this_err; | |
710 | } | |
711 | } | |
712 | } | |
713 | } | |
714 | } | |
715 | ||
716 | return (err != target); | |
717 | } | |
718 | ||
997c030c ACO |
719 | /* |
720 | * Returns a set of divisors for the desired target clock with the given | |
721 | * refclk, or FALSE. The returned values represent the clock equation: | |
722 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
723 | * |
724 | * Target and reference clocks are specified in kHz. | |
725 | * | |
726 | * If match_clock is provided, then best_clock P divider must match the P | |
727 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 728 | */ |
d4906093 | 729 | static bool |
1b6f4958 | 730 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 731 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
732 | int target, int refclk, struct dpll *match_clock, |
733 | struct dpll *best_clock) | |
d4906093 | 734 | { |
3b1429d9 | 735 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 736 | struct dpll clock; |
d4906093 | 737 | int max_n; |
3b1429d9 | 738 | bool found = false; |
6ba770dc AJ |
739 | /* approximately equals target * 0.00585 */ |
740 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
741 | |
742 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
743 | |
744 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
745 | ||
d4906093 | 746 | max_n = limit->n.max; |
f77f13e2 | 747 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 748 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 749 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
750 | for (clock.m1 = limit->m1.max; |
751 | clock.m1 >= limit->m1.min; clock.m1--) { | |
752 | for (clock.m2 = limit->m2.max; | |
753 | clock.m2 >= limit->m2.min; clock.m2--) { | |
754 | for (clock.p1 = limit->p1.max; | |
755 | clock.p1 >= limit->p1.min; clock.p1--) { | |
756 | int this_err; | |
757 | ||
dccbea3b | 758 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
759 | if (!intel_PLL_is_valid(to_i915(dev), |
760 | limit, | |
1b894b59 | 761 | &clock)) |
d4906093 | 762 | continue; |
1b894b59 CW |
763 | |
764 | this_err = abs(clock.dot - target); | |
d4906093 ML |
765 | if (this_err < err_most) { |
766 | *best_clock = clock; | |
767 | err_most = this_err; | |
768 | max_n = clock.n; | |
769 | found = true; | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
774 | } | |
2c07245f ZW |
775 | return found; |
776 | } | |
777 | ||
d5dd62bd ID |
778 | /* |
779 | * Check if the calculated PLL configuration is more optimal compared to the | |
780 | * best configuration and error found so far. Return the calculated error. | |
781 | */ | |
782 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
783 | const struct dpll *calculated_clock, |
784 | const struct dpll *best_clock, | |
d5dd62bd ID |
785 | unsigned int best_error_ppm, |
786 | unsigned int *error_ppm) | |
787 | { | |
9ca3ba01 ID |
788 | /* |
789 | * For CHV ignore the error and consider only the P value. | |
790 | * Prefer a bigger P value based on HW requirements. | |
791 | */ | |
920a14b2 | 792 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
793 | *error_ppm = 0; |
794 | ||
795 | return calculated_clock->p > best_clock->p; | |
796 | } | |
797 | ||
24be4e46 ID |
798 | if (WARN_ON_ONCE(!target_freq)) |
799 | return false; | |
800 | ||
d5dd62bd ID |
801 | *error_ppm = div_u64(1000000ULL * |
802 | abs(target_freq - calculated_clock->dot), | |
803 | target_freq); | |
804 | /* | |
805 | * Prefer a better P value over a better (smaller) error if the error | |
806 | * is small. Ensure this preference for future configurations too by | |
807 | * setting the error to 0. | |
808 | */ | |
809 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
810 | *error_ppm = 0; | |
811 | ||
812 | return true; | |
813 | } | |
814 | ||
815 | return *error_ppm + 10 < best_error_ppm; | |
816 | } | |
817 | ||
65b3d6a9 ACO |
818 | /* |
819 | * Returns a set of divisors for the desired target clock with the given | |
820 | * refclk, or FALSE. The returned values represent the clock equation: | |
821 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
822 | */ | |
a0c4da24 | 823 | static bool |
1b6f4958 | 824 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 825 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
826 | int target, int refclk, struct dpll *match_clock, |
827 | struct dpll *best_clock) | |
a0c4da24 | 828 | { |
a93e255f | 829 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 830 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 831 | struct dpll clock; |
69e4f900 | 832 | unsigned int bestppm = 1000000; |
27e639bf VS |
833 | /* min update 19.2 MHz */ |
834 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 835 | bool found = false; |
a0c4da24 | 836 | |
6b4bf1c4 VS |
837 | target *= 5; /* fast clock */ |
838 | ||
839 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
840 | |
841 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 842 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 843 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 844 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 845 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 846 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 847 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 848 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 849 | unsigned int ppm; |
69e4f900 | 850 | |
6b4bf1c4 VS |
851 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
852 | refclk * clock.m1); | |
853 | ||
dccbea3b | 854 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 855 | |
e2d214ae TU |
856 | if (!intel_PLL_is_valid(to_i915(dev), |
857 | limit, | |
f01b7962 | 858 | &clock)) |
43b0ac53 VS |
859 | continue; |
860 | ||
d5dd62bd ID |
861 | if (!vlv_PLL_is_optimal(dev, target, |
862 | &clock, | |
863 | best_clock, | |
864 | bestppm, &ppm)) | |
865 | continue; | |
6b4bf1c4 | 866 | |
d5dd62bd ID |
867 | *best_clock = clock; |
868 | bestppm = ppm; | |
869 | found = true; | |
a0c4da24 JB |
870 | } |
871 | } | |
872 | } | |
873 | } | |
a0c4da24 | 874 | |
49e497ef | 875 | return found; |
a0c4da24 | 876 | } |
a4fc5ed6 | 877 | |
65b3d6a9 ACO |
878 | /* |
879 | * Returns a set of divisors for the desired target clock with the given | |
880 | * refclk, or FALSE. The returned values represent the clock equation: | |
881 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
882 | */ | |
ef9348c8 | 883 | static bool |
1b6f4958 | 884 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 885 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
886 | int target, int refclk, struct dpll *match_clock, |
887 | struct dpll *best_clock) | |
ef9348c8 | 888 | { |
a93e255f | 889 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 890 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 891 | unsigned int best_error_ppm; |
9e2c8475 | 892 | struct dpll clock; |
ef9348c8 CML |
893 | uint64_t m2; |
894 | int found = false; | |
895 | ||
896 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 897 | best_error_ppm = 1000000; |
ef9348c8 CML |
898 | |
899 | /* | |
900 | * Based on hardware doc, the n always set to 1, and m1 always | |
901 | * set to 2. If requires to support 200Mhz refclk, we need to | |
902 | * revisit this because n may not 1 anymore. | |
903 | */ | |
904 | clock.n = 1, clock.m1 = 2; | |
905 | target *= 5; /* fast clock */ | |
906 | ||
907 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
908 | for (clock.p2 = limit->p2.p2_fast; | |
909 | clock.p2 >= limit->p2.p2_slow; | |
910 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 911 | unsigned int error_ppm; |
ef9348c8 CML |
912 | |
913 | clock.p = clock.p1 * clock.p2; | |
914 | ||
915 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
916 | clock.n) << 22, refclk * clock.m1); | |
917 | ||
918 | if (m2 > INT_MAX/clock.m1) | |
919 | continue; | |
920 | ||
921 | clock.m2 = m2; | |
922 | ||
dccbea3b | 923 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 924 | |
e2d214ae | 925 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
926 | continue; |
927 | ||
9ca3ba01 ID |
928 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
929 | best_error_ppm, &error_ppm)) | |
930 | continue; | |
931 | ||
932 | *best_clock = clock; | |
933 | best_error_ppm = error_ppm; | |
934 | found = true; | |
ef9348c8 CML |
935 | } |
936 | } | |
937 | ||
938 | return found; | |
939 | } | |
940 | ||
5ab7b0b7 | 941 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 942 | struct dpll *best_clock) |
5ab7b0b7 | 943 | { |
65b3d6a9 | 944 | int refclk = 100000; |
1b6f4958 | 945 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 946 | |
65b3d6a9 | 947 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
948 | target_clock, refclk, NULL, best_clock); |
949 | } | |
950 | ||
525b9311 | 951 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 952 | { |
20ddf665 VS |
953 | /* Be paranoid as we can arrive here with only partial |
954 | * state retrieved from the hardware during setup. | |
955 | * | |
241bfc38 | 956 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
957 | * as Haswell has gained clock readout/fastboot support. |
958 | * | |
66e514c1 | 959 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 960 | * properly reconstruct framebuffers. |
c3d1f436 MR |
961 | * |
962 | * FIXME: The intel_crtc->active here should be switched to | |
963 | * crtc->state->active once we have proper CRTC states wired up | |
964 | * for atomic. | |
20ddf665 | 965 | */ |
525b9311 VS |
966 | return crtc->active && crtc->base.primary->state->fb && |
967 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
968 | } |
969 | ||
a5c961d1 PZ |
970 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
971 | enum pipe pipe) | |
972 | { | |
98187836 | 973 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 974 | |
e2af48c6 | 975 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
976 | } |
977 | ||
6315b5d3 | 978 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 979 | { |
f0f59a00 | 980 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
981 | u32 line1, line2; |
982 | u32 line_mask; | |
983 | ||
5db94019 | 984 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
985 | line_mask = DSL_LINEMASK_GEN2; |
986 | else | |
987 | line_mask = DSL_LINEMASK_GEN3; | |
988 | ||
989 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 990 | msleep(5); |
fbf49ea2 VS |
991 | line2 = I915_READ(reg) & line_mask; |
992 | ||
993 | return line1 == line2; | |
994 | } | |
995 | ||
ab7ad7f6 KP |
996 | /* |
997 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 998 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
999 | * |
1000 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1001 | * spinning on the vblank interrupt status bit, since we won't actually | |
1002 | * see an interrupt when the pipe is disabled. | |
1003 | * | |
ab7ad7f6 KP |
1004 | * On Gen4 and above: |
1005 | * wait for the pipe register state bit to turn off | |
1006 | * | |
1007 | * Otherwise: | |
1008 | * wait for the display line value to settle (it usually | |
1009 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1010 | * |
9d0498a2 | 1011 | */ |
575f7ab7 | 1012 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1013 | { |
6315b5d3 | 1014 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1015 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1016 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1017 | |
6315b5d3 | 1018 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1019 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1020 | |
1021 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1022 | if (intel_wait_for_register(dev_priv, |
1023 | reg, I965_PIPECONF_ACTIVE, 0, | |
1024 | 100)) | |
284637d9 | 1025 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1026 | } else { |
ab7ad7f6 | 1027 | /* Wait for the display line to settle */ |
6315b5d3 | 1028 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1029 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1030 | } |
79e53945 JB |
1031 | } |
1032 | ||
b24e7179 | 1033 | /* Only for pre-ILK configs */ |
55607e8a DV |
1034 | void assert_pll(struct drm_i915_private *dev_priv, |
1035 | enum pipe pipe, bool state) | |
b24e7179 | 1036 | { |
b24e7179 JB |
1037 | u32 val; |
1038 | bool cur_state; | |
1039 | ||
649636ef | 1040 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1041 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1042 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1043 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1044 | onoff(state), onoff(cur_state)); |
b24e7179 | 1045 | } |
b24e7179 | 1046 | |
23538ef1 | 1047 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1048 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1049 | { |
1050 | u32 val; | |
1051 | bool cur_state; | |
1052 | ||
a580516d | 1053 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1054 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1055 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1056 | |
1057 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1058 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1059 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1060 | onoff(state), onoff(cur_state)); |
23538ef1 | 1061 | } |
23538ef1 | 1062 | |
040484af JB |
1063 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1064 | enum pipe pipe, bool state) | |
1065 | { | |
040484af | 1066 | bool cur_state; |
ad80a810 PZ |
1067 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1068 | pipe); | |
040484af | 1069 | |
2d1fe073 | 1070 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1071 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1072 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1073 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1074 | } else { |
649636ef | 1075 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1076 | cur_state = !!(val & FDI_TX_ENABLE); |
1077 | } | |
e2c719b7 | 1078 | I915_STATE_WARN(cur_state != state, |
040484af | 1079 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1080 | onoff(state), onoff(cur_state)); |
040484af JB |
1081 | } |
1082 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1083 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1084 | ||
1085 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1086 | enum pipe pipe, bool state) | |
1087 | { | |
040484af JB |
1088 | u32 val; |
1089 | bool cur_state; | |
1090 | ||
649636ef | 1091 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1092 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1093 | I915_STATE_WARN(cur_state != state, |
040484af | 1094 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1095 | onoff(state), onoff(cur_state)); |
040484af JB |
1096 | } |
1097 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1098 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1099 | ||
1100 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1101 | enum pipe pipe) | |
1102 | { | |
040484af JB |
1103 | u32 val; |
1104 | ||
1105 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1106 | if (IS_GEN5(dev_priv)) |
040484af JB |
1107 | return; |
1108 | ||
bf507ef7 | 1109 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1110 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1111 | return; |
1112 | ||
649636ef | 1113 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1114 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1115 | } |
1116 | ||
55607e8a DV |
1117 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1118 | enum pipe pipe, bool state) | |
040484af | 1119 | { |
040484af | 1120 | u32 val; |
55607e8a | 1121 | bool cur_state; |
040484af | 1122 | |
649636ef | 1123 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1124 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1125 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1126 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1127 | onoff(state), onoff(cur_state)); |
040484af JB |
1128 | } |
1129 | ||
4f8036a2 | 1130 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1131 | { |
f0f59a00 | 1132 | i915_reg_t pp_reg; |
ea0760cf JB |
1133 | u32 val; |
1134 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1135 | bool locked = true; |
ea0760cf | 1136 | |
4f8036a2 | 1137 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1138 | return; |
1139 | ||
4f8036a2 | 1140 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1141 | u32 port_sel; |
1142 | ||
44cb734c ID |
1143 | pp_reg = PP_CONTROL(0); |
1144 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1145 | |
1146 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1147 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1148 | panel_pipe = PIPE_B; | |
1149 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1150 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1151 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1152 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1153 | panel_pipe = pipe; |
ea0760cf | 1154 | } else { |
44cb734c | 1155 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1156 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1157 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1158 | } |
1159 | ||
1160 | val = I915_READ(pp_reg); | |
1161 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1162 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1163 | locked = false; |
1164 | ||
e2c719b7 | 1165 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1166 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1167 | pipe_name(pipe)); |
ea0760cf JB |
1168 | } |
1169 | ||
93ce0ba6 JN |
1170 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1171 | enum pipe pipe, bool state) | |
1172 | { | |
93ce0ba6 JN |
1173 | bool cur_state; |
1174 | ||
2a307c2e | 1175 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1176 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1177 | else |
5efb3e28 | 1178 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1179 | |
e2c719b7 | 1180 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1181 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1182 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1183 | } |
1184 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1185 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1186 | ||
b840d907 JB |
1187 | void assert_pipe(struct drm_i915_private *dev_priv, |
1188 | enum pipe pipe, bool state) | |
b24e7179 | 1189 | { |
63d7bbe9 | 1190 | bool cur_state; |
702e7a56 PZ |
1191 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1192 | pipe); | |
4feed0eb | 1193 | enum intel_display_power_domain power_domain; |
b24e7179 | 1194 | |
b6b5d049 VS |
1195 | /* if we need the pipe quirk it must be always on */ |
1196 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1197 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1198 | state = true; |
1199 | ||
4feed0eb ID |
1200 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1201 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1202 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1203 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1204 | |
1205 | intel_display_power_put(dev_priv, power_domain); | |
1206 | } else { | |
1207 | cur_state = false; | |
69310161 PZ |
1208 | } |
1209 | ||
e2c719b7 | 1210 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1211 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1212 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1213 | } |
1214 | ||
931872fc CW |
1215 | static void assert_plane(struct drm_i915_private *dev_priv, |
1216 | enum plane plane, bool state) | |
b24e7179 | 1217 | { |
b24e7179 | 1218 | u32 val; |
931872fc | 1219 | bool cur_state; |
b24e7179 | 1220 | |
649636ef | 1221 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1222 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1223 | I915_STATE_WARN(cur_state != state, |
931872fc | 1224 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1225 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1226 | } |
1227 | ||
931872fc CW |
1228 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1229 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1230 | ||
b24e7179 JB |
1231 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1232 | enum pipe pipe) | |
1233 | { | |
649636ef | 1234 | int i; |
b24e7179 | 1235 | |
653e1026 | 1236 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1237 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1238 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1239 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1240 | "plane %c assertion failure, should be disabled but not\n", |
1241 | plane_name(pipe)); | |
19ec1358 | 1242 | return; |
28c05794 | 1243 | } |
19ec1358 | 1244 | |
b24e7179 | 1245 | /* Need to check both planes against the pipe */ |
055e393f | 1246 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1247 | u32 val = I915_READ(DSPCNTR(i)); |
1248 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1249 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1250 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1251 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1252 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1253 | } |
1254 | } | |
1255 | ||
19332d7a JB |
1256 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1257 | enum pipe pipe) | |
1258 | { | |
649636ef | 1259 | int sprite; |
19332d7a | 1260 | |
6315b5d3 | 1261 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1262 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1263 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1264 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1265 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1266 | sprite, pipe_name(pipe)); | |
1267 | } | |
920a14b2 | 1268 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1269 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1270 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1271 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1272 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1273 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1274 | } |
6315b5d3 | 1275 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1276 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1277 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1278 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1279 | plane_name(pipe), pipe_name(pipe)); |
ab33081a | 1280 | } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
649636ef | 1281 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1282 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1283 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1284 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1285 | } |
1286 | } | |
1287 | ||
08c71e5e VS |
1288 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1289 | { | |
e2c719b7 | 1290 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1291 | drm_crtc_vblank_put(crtc); |
1292 | } | |
1293 | ||
7abd4b35 ACO |
1294 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe) | |
92f2584a | 1296 | { |
92f2584a JB |
1297 | u32 val; |
1298 | bool enabled; | |
1299 | ||
649636ef | 1300 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1301 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1302 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1303 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1304 | pipe_name(pipe)); | |
92f2584a JB |
1305 | } |
1306 | ||
4e634389 KP |
1307 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1308 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1309 | { |
1310 | if ((val & DP_PORT_EN) == 0) | |
1311 | return false; | |
1312 | ||
2d1fe073 | 1313 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1314 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1315 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1316 | return false; | |
2d1fe073 | 1317 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1318 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1319 | return false; | |
f0575e92 KP |
1320 | } else { |
1321 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1322 | return false; | |
1323 | } | |
1324 | return true; | |
1325 | } | |
1326 | ||
1519b995 KP |
1327 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1328 | enum pipe pipe, u32 val) | |
1329 | { | |
dc0fa718 | 1330 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1331 | return false; |
1332 | ||
2d1fe073 | 1333 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1334 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1335 | return false; |
2d1fe073 | 1336 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1337 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1338 | return false; | |
1519b995 | 1339 | } else { |
dc0fa718 | 1340 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1341 | return false; |
1342 | } | |
1343 | return true; | |
1344 | } | |
1345 | ||
1346 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1347 | enum pipe pipe, u32 val) | |
1348 | { | |
1349 | if ((val & LVDS_PORT_EN) == 0) | |
1350 | return false; | |
1351 | ||
2d1fe073 | 1352 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1353 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1354 | return false; | |
1355 | } else { | |
1356 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1357 | return false; | |
1358 | } | |
1359 | return true; | |
1360 | } | |
1361 | ||
1362 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1363 | enum pipe pipe, u32 val) | |
1364 | { | |
1365 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1366 | return false; | |
2d1fe073 | 1367 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1368 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1369 | return false; | |
1370 | } else { | |
1371 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1372 | return false; | |
1373 | } | |
1374 | return true; | |
1375 | } | |
1376 | ||
291906f1 | 1377 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1378 | enum pipe pipe, i915_reg_t reg, |
1379 | u32 port_sel) | |
291906f1 | 1380 | { |
47a05eca | 1381 | u32 val = I915_READ(reg); |
e2c719b7 | 1382 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1383 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1384 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1385 | |
2d1fe073 | 1386 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1387 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1388 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1389 | } |
1390 | ||
1391 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1392 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1393 | { |
47a05eca | 1394 | u32 val = I915_READ(reg); |
e2c719b7 | 1395 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1396 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1397 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1398 | |
2d1fe073 | 1399 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1400 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1401 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1402 | } |
1403 | ||
1404 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1405 | enum pipe pipe) | |
1406 | { | |
291906f1 | 1407 | u32 val; |
291906f1 | 1408 | |
f0575e92 KP |
1409 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1410 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1411 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1412 | |
649636ef | 1413 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1414 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1415 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1416 | pipe_name(pipe)); |
291906f1 | 1417 | |
649636ef | 1418 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1419 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1420 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1421 | pipe_name(pipe)); |
291906f1 | 1422 | |
e2debe91 PZ |
1423 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1424 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1425 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1426 | } |
1427 | ||
cd2d34d9 VS |
1428 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1429 | const struct intel_crtc_state *pipe_config) | |
1430 | { | |
1431 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1432 | enum pipe pipe = crtc->pipe; | |
1433 | ||
1434 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1435 | POSTING_READ(DPLL(pipe)); | |
1436 | udelay(150); | |
1437 | ||
2c30b43b CW |
1438 | if (intel_wait_for_register(dev_priv, |
1439 | DPLL(pipe), | |
1440 | DPLL_LOCK_VLV, | |
1441 | DPLL_LOCK_VLV, | |
1442 | 1)) | |
cd2d34d9 VS |
1443 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1444 | } | |
1445 | ||
d288f65f | 1446 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1447 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1448 | { |
cd2d34d9 | 1449 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1450 | enum pipe pipe = crtc->pipe; |
87442f73 | 1451 | |
8bd3f301 | 1452 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1453 | |
87442f73 | 1454 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1455 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1456 | |
cd2d34d9 VS |
1457 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1458 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1459 | |
8bd3f301 VS |
1460 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1461 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1462 | } |
1463 | ||
cd2d34d9 VS |
1464 | |
1465 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1466 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1467 | { |
cd2d34d9 | 1468 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1469 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1470 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1471 | u32 tmp; |
1472 | ||
a580516d | 1473 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1474 | |
1475 | /* Enable back the 10bit clock to display controller */ | |
1476 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1477 | tmp |= DPIO_DCLKP_EN; | |
1478 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1479 | ||
54433e91 VS |
1480 | mutex_unlock(&dev_priv->sb_lock); |
1481 | ||
9d556c99 CML |
1482 | /* |
1483 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1484 | */ | |
1485 | udelay(1); | |
1486 | ||
1487 | /* Enable PLL */ | |
d288f65f | 1488 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1489 | |
1490 | /* Check PLL is locked */ | |
6b18826a CW |
1491 | if (intel_wait_for_register(dev_priv, |
1492 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1493 | 1)) | |
9d556c99 | 1494 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1495 | } |
1496 | ||
1497 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1498 | const struct intel_crtc_state *pipe_config) | |
1499 | { | |
1500 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1501 | enum pipe pipe = crtc->pipe; | |
1502 | ||
1503 | assert_pipe_disabled(dev_priv, pipe); | |
1504 | ||
1505 | /* PLL is protected by panel, make sure we can write it */ | |
1506 | assert_panel_unlocked(dev_priv, pipe); | |
1507 | ||
1508 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1509 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1510 | |
c231775c VS |
1511 | if (pipe != PIPE_A) { |
1512 | /* | |
1513 | * WaPixelRepeatModeFixForC0:chv | |
1514 | * | |
1515 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1516 | * the value from DPLLBMD to either pipe B or C. | |
1517 | */ | |
1518 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1519 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1520 | I915_WRITE(CBR4_VLV, 0); | |
1521 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1522 | ||
1523 | /* | |
1524 | * DPLLB VGA mode also seems to cause problems. | |
1525 | * We should always have it disabled. | |
1526 | */ | |
1527 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1528 | } else { | |
1529 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1530 | POSTING_READ(DPLL_MD(pipe)); | |
1531 | } | |
9d556c99 CML |
1532 | } |
1533 | ||
6315b5d3 | 1534 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1535 | { |
1536 | struct intel_crtc *crtc; | |
1537 | int count = 0; | |
1538 | ||
6315b5d3 | 1539 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1540 | count += crtc->base.state->active && |
2d84d2b3 VS |
1541 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1542 | } | |
1c4e0274 VS |
1543 | |
1544 | return count; | |
1545 | } | |
1546 | ||
66e3d5c0 | 1547 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1548 | { |
6315b5d3 | 1549 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1550 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1551 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1552 | |
66e3d5c0 | 1553 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1554 | |
63d7bbe9 | 1555 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1556 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1557 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1558 | |
1c4e0274 | 1559 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1560 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1561 | /* |
1562 | * It appears to be important that we don't enable this | |
1563 | * for the current pipe before otherwise configuring the | |
1564 | * PLL. No idea how this should be handled if multiple | |
1565 | * DVO outputs are enabled simultaneosly. | |
1566 | */ | |
1567 | dpll |= DPLL_DVO_2X_MODE; | |
1568 | I915_WRITE(DPLL(!crtc->pipe), | |
1569 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1570 | } | |
66e3d5c0 | 1571 | |
c2b63374 VS |
1572 | /* |
1573 | * Apparently we need to have VGA mode enabled prior to changing | |
1574 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1575 | * dividers, even though the register value does change. | |
1576 | */ | |
1577 | I915_WRITE(reg, 0); | |
1578 | ||
8e7a65aa VS |
1579 | I915_WRITE(reg, dpll); |
1580 | ||
66e3d5c0 DV |
1581 | /* Wait for the clocks to stabilize. */ |
1582 | POSTING_READ(reg); | |
1583 | udelay(150); | |
1584 | ||
6315b5d3 | 1585 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1586 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1587 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1588 | } else { |
1589 | /* The pixel multiplier can only be updated once the | |
1590 | * DPLL is enabled and the clocks are stable. | |
1591 | * | |
1592 | * So write it again. | |
1593 | */ | |
1594 | I915_WRITE(reg, dpll); | |
1595 | } | |
63d7bbe9 JB |
1596 | |
1597 | /* We do this three times for luck */ | |
66e3d5c0 | 1598 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1599 | POSTING_READ(reg); |
1600 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1601 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1602 | POSTING_READ(reg); |
1603 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1604 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1605 | POSTING_READ(reg); |
1606 | udelay(150); /* wait for warmup */ | |
1607 | } | |
1608 | ||
1609 | /** | |
50b44a44 | 1610 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1611 | * @dev_priv: i915 private structure |
1612 | * @pipe: pipe PLL to disable | |
1613 | * | |
1614 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1615 | * | |
1616 | * Note! This is for pre-ILK only. | |
1617 | */ | |
1c4e0274 | 1618 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1619 | { |
6315b5d3 | 1620 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1621 | enum pipe pipe = crtc->pipe; |
1622 | ||
1623 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1624 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1625 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1626 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1627 | I915_WRITE(DPLL(PIPE_B), |
1628 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1629 | I915_WRITE(DPLL(PIPE_A), | |
1630 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1631 | } | |
1632 | ||
b6b5d049 VS |
1633 | /* Don't disable pipe or pipe PLLs if needed */ |
1634 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1635 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1636 | return; |
1637 | ||
1638 | /* Make sure the pipe isn't still relying on us */ | |
1639 | assert_pipe_disabled(dev_priv, pipe); | |
1640 | ||
b8afb911 | 1641 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1642 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1643 | } |
1644 | ||
f6071166 JB |
1645 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1646 | { | |
b8afb911 | 1647 | u32 val; |
f6071166 JB |
1648 | |
1649 | /* Make sure the pipe isn't still relying on us */ | |
1650 | assert_pipe_disabled(dev_priv, pipe); | |
1651 | ||
03ed5cbf VS |
1652 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1653 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1654 | if (pipe != PIPE_A) | |
1655 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1656 | ||
f6071166 JB |
1657 | I915_WRITE(DPLL(pipe), val); |
1658 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1659 | } |
1660 | ||
1661 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1662 | { | |
d752048d | 1663 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1664 | u32 val; |
1665 | ||
a11b0703 VS |
1666 | /* Make sure the pipe isn't still relying on us */ |
1667 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1668 | |
60bfe44f VS |
1669 | val = DPLL_SSC_REF_CLK_CHV | |
1670 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1671 | if (pipe != PIPE_A) |
1672 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1673 | |
a11b0703 VS |
1674 | I915_WRITE(DPLL(pipe), val); |
1675 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1676 | |
a580516d | 1677 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1678 | |
1679 | /* Disable 10bit clock to display controller */ | |
1680 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1681 | val &= ~DPIO_DCLKP_EN; | |
1682 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1683 | ||
a580516d | 1684 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1685 | } |
1686 | ||
e4607fcf | 1687 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1688 | struct intel_digital_port *dport, |
1689 | unsigned int expected_mask) | |
89b667f8 JB |
1690 | { |
1691 | u32 port_mask; | |
f0f59a00 | 1692 | i915_reg_t dpll_reg; |
89b667f8 | 1693 | |
e4607fcf CML |
1694 | switch (dport->port) { |
1695 | case PORT_B: | |
89b667f8 | 1696 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1697 | dpll_reg = DPLL(0); |
e4607fcf CML |
1698 | break; |
1699 | case PORT_C: | |
89b667f8 | 1700 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1701 | dpll_reg = DPLL(0); |
9b6de0a1 | 1702 | expected_mask <<= 4; |
00fc31b7 CML |
1703 | break; |
1704 | case PORT_D: | |
1705 | port_mask = DPLL_PORTD_READY_MASK; | |
1706 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1707 | break; |
1708 | default: | |
1709 | BUG(); | |
1710 | } | |
89b667f8 | 1711 | |
370004d3 CW |
1712 | if (intel_wait_for_register(dev_priv, |
1713 | dpll_reg, port_mask, expected_mask, | |
1714 | 1000)) | |
9b6de0a1 VS |
1715 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1716 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1717 | } |
1718 | ||
b8a4f404 PZ |
1719 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1720 | enum pipe pipe) | |
040484af | 1721 | { |
98187836 VS |
1722 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1723 | pipe); | |
f0f59a00 VS |
1724 | i915_reg_t reg; |
1725 | uint32_t val, pipeconf_val; | |
040484af | 1726 | |
040484af | 1727 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1728 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1729 | |
1730 | /* FDI must be feeding us bits for PCH ports */ | |
1731 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1732 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1733 | ||
6e266956 | 1734 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1735 | /* Workaround: Set the timing override bit before enabling the |
1736 | * pch transcoder. */ | |
1737 | reg = TRANS_CHICKEN2(pipe); | |
1738 | val = I915_READ(reg); | |
1739 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1740 | I915_WRITE(reg, val); | |
59c859d6 | 1741 | } |
23670b32 | 1742 | |
ab9412ba | 1743 | reg = PCH_TRANSCONF(pipe); |
040484af | 1744 | val = I915_READ(reg); |
5f7f726d | 1745 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1746 | |
2d1fe073 | 1747 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1748 | /* |
c5de7c6f VS |
1749 | * Make the BPC in transcoder be consistent with |
1750 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1751 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1752 | */ |
dfd07d72 | 1753 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1754 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1755 | val |= PIPECONF_8BPC; |
1756 | else | |
1757 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1758 | } |
5f7f726d PZ |
1759 | |
1760 | val &= ~TRANS_INTERLACE_MASK; | |
1761 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1762 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1763 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1764 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1765 | else | |
1766 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1767 | else |
1768 | val |= TRANS_PROGRESSIVE; | |
1769 | ||
040484af | 1770 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1771 | if (intel_wait_for_register(dev_priv, |
1772 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1773 | 100)) | |
4bb6f1f3 | 1774 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1775 | } |
1776 | ||
8fb033d7 | 1777 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1778 | enum transcoder cpu_transcoder) |
040484af | 1779 | { |
8fb033d7 | 1780 | u32 val, pipeconf_val; |
8fb033d7 | 1781 | |
8fb033d7 | 1782 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1783 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1784 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1785 | |
223a6fdf | 1786 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1787 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1788 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1789 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1790 | |
25f3ef11 | 1791 | val = TRANS_ENABLE; |
937bb610 | 1792 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1793 | |
9a76b1c6 PZ |
1794 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1795 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1796 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1797 | else |
1798 | val |= TRANS_PROGRESSIVE; | |
1799 | ||
ab9412ba | 1800 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1801 | if (intel_wait_for_register(dev_priv, |
1802 | LPT_TRANSCONF, | |
1803 | TRANS_STATE_ENABLE, | |
1804 | TRANS_STATE_ENABLE, | |
1805 | 100)) | |
937bb610 | 1806 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1807 | } |
1808 | ||
b8a4f404 PZ |
1809 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1810 | enum pipe pipe) | |
040484af | 1811 | { |
f0f59a00 VS |
1812 | i915_reg_t reg; |
1813 | uint32_t val; | |
040484af JB |
1814 | |
1815 | /* FDI relies on the transcoder */ | |
1816 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1817 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1818 | ||
291906f1 JB |
1819 | /* Ports must be off as well */ |
1820 | assert_pch_ports_disabled(dev_priv, pipe); | |
1821 | ||
ab9412ba | 1822 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1823 | val = I915_READ(reg); |
1824 | val &= ~TRANS_ENABLE; | |
1825 | I915_WRITE(reg, val); | |
1826 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1827 | if (intel_wait_for_register(dev_priv, |
1828 | reg, TRANS_STATE_ENABLE, 0, | |
1829 | 50)) | |
4bb6f1f3 | 1830 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1831 | |
6e266956 | 1832 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1833 | /* Workaround: Clear the timing override chicken bit again. */ |
1834 | reg = TRANS_CHICKEN2(pipe); | |
1835 | val = I915_READ(reg); | |
1836 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1837 | I915_WRITE(reg, val); | |
1838 | } | |
040484af JB |
1839 | } |
1840 | ||
b7076546 | 1841 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1842 | { |
8fb033d7 PZ |
1843 | u32 val; |
1844 | ||
ab9412ba | 1845 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1846 | val &= ~TRANS_ENABLE; |
ab9412ba | 1847 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1848 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1849 | if (intel_wait_for_register(dev_priv, |
1850 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1851 | 50)) | |
8a52fd9f | 1852 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1853 | |
1854 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1855 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1856 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1857 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1858 | } |
1859 | ||
65f2130c VS |
1860 | enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
1861 | { | |
1862 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1863 | ||
1864 | WARN_ON(!crtc->config->has_pch_encoder); | |
1865 | ||
1866 | if (HAS_PCH_LPT(dev_priv)) | |
1867 | return TRANSCODER_A; | |
1868 | else | |
1869 | return (enum transcoder) crtc->pipe; | |
1870 | } | |
1871 | ||
b24e7179 | 1872 | /** |
309cfea8 | 1873 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1874 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1875 | * |
0372264a | 1876 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1877 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1878 | */ |
e1fdc473 | 1879 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1880 | { |
0372264a | 1881 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1882 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1883 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1884 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1885 | i915_reg_t reg; |
b24e7179 JB |
1886 | u32 val; |
1887 | ||
9e2ee2dd VS |
1888 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1889 | ||
58c6eaa2 | 1890 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1891 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1892 | assert_sprites_disabled(dev_priv, pipe); |
1893 | ||
b24e7179 JB |
1894 | /* |
1895 | * A pipe without a PLL won't actually be able to drive bits from | |
1896 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1897 | * need the check. | |
1898 | */ | |
09fa8bb9 | 1899 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1900 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1901 | assert_dsi_pll_enabled(dev_priv); |
1902 | else | |
1903 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1904 | } else { |
6e3c9717 | 1905 | if (crtc->config->has_pch_encoder) { |
040484af | 1906 | /* if driving the PCH, we need FDI enabled */ |
65f2130c VS |
1907 | assert_fdi_rx_pll_enabled(dev_priv, |
1908 | (enum pipe) intel_crtc_pch_transcoder(crtc)); | |
1a240d4d DV |
1909 | assert_fdi_tx_pll_enabled(dev_priv, |
1910 | (enum pipe) cpu_transcoder); | |
040484af JB |
1911 | } |
1912 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1913 | } | |
b24e7179 | 1914 | |
702e7a56 | 1915 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1916 | val = I915_READ(reg); |
7ad25d48 | 1917 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1918 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1919 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1920 | return; |
7ad25d48 | 1921 | } |
00d70b15 CW |
1922 | |
1923 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1924 | POSTING_READ(reg); |
b7792d8b VS |
1925 | |
1926 | /* | |
1927 | * Until the pipe starts DSL will read as 0, which would cause | |
1928 | * an apparent vblank timestamp jump, which messes up also the | |
1929 | * frame count when it's derived from the timestamps. So let's | |
1930 | * wait for the pipe to start properly before we call | |
1931 | * drm_crtc_vblank_on() | |
1932 | */ | |
1933 | if (dev->max_vblank_count == 0 && | |
1934 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1935 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1936 | } |
1937 | ||
1938 | /** | |
309cfea8 | 1939 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 1940 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 1941 | * |
575f7ab7 VS |
1942 | * Disable the pipe of @crtc, making sure that various hardware |
1943 | * specific requirements are met, if applicable, e.g. plane | |
1944 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
1945 | * |
1946 | * Will wait until the pipe has shut down before returning. | |
1947 | */ | |
575f7ab7 | 1948 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1949 | { |
fac5e23e | 1950 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1951 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1952 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1953 | i915_reg_t reg; |
b24e7179 JB |
1954 | u32 val; |
1955 | ||
9e2ee2dd VS |
1956 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
1957 | ||
b24e7179 JB |
1958 | /* |
1959 | * Make sure planes won't keep trying to pump pixels to us, | |
1960 | * or we might hang the display. | |
1961 | */ | |
1962 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1963 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1964 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 1965 | |
702e7a56 | 1966 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1967 | val = I915_READ(reg); |
00d70b15 CW |
1968 | if ((val & PIPECONF_ENABLE) == 0) |
1969 | return; | |
1970 | ||
67adc644 VS |
1971 | /* |
1972 | * Double wide has implications for planes | |
1973 | * so best keep it disabled when not needed. | |
1974 | */ | |
6e3c9717 | 1975 | if (crtc->config->double_wide) |
67adc644 VS |
1976 | val &= ~PIPECONF_DOUBLE_WIDE; |
1977 | ||
1978 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
1979 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
1980 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
1981 | val &= ~PIPECONF_ENABLE; |
1982 | ||
1983 | I915_WRITE(reg, val); | |
1984 | if ((val & PIPECONF_ENABLE) == 0) | |
1985 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
1986 | } |
1987 | ||
832be82f VS |
1988 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
1989 | { | |
1990 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
1991 | } | |
1992 | ||
d88c4afd VS |
1993 | static unsigned int |
1994 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) | |
7b49f948 | 1995 | { |
d88c4afd VS |
1996 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
1997 | unsigned int cpp = fb->format->cpp[plane]; | |
1998 | ||
1999 | switch (fb->modifier) { | |
2f075565 | 2000 | case DRM_FORMAT_MOD_LINEAR: |
7b49f948 VS |
2001 | return cpp; |
2002 | case I915_FORMAT_MOD_X_TILED: | |
2003 | if (IS_GEN2(dev_priv)) | |
2004 | return 128; | |
2005 | else | |
2006 | return 512; | |
2007 | case I915_FORMAT_MOD_Y_TILED: | |
2008 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2009 | return 128; | |
2010 | else | |
2011 | return 512; | |
2012 | case I915_FORMAT_MOD_Yf_TILED: | |
2013 | switch (cpp) { | |
2014 | case 1: | |
2015 | return 64; | |
2016 | case 2: | |
2017 | case 4: | |
2018 | return 128; | |
2019 | case 8: | |
2020 | case 16: | |
2021 | return 256; | |
2022 | default: | |
2023 | MISSING_CASE(cpp); | |
2024 | return cpp; | |
2025 | } | |
2026 | break; | |
2027 | default: | |
d88c4afd | 2028 | MISSING_CASE(fb->modifier); |
7b49f948 VS |
2029 | return cpp; |
2030 | } | |
2031 | } | |
2032 | ||
d88c4afd VS |
2033 | static unsigned int |
2034 | intel_tile_height(const struct drm_framebuffer *fb, int plane) | |
a57ce0b2 | 2035 | { |
2f075565 | 2036 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
832be82f VS |
2037 | return 1; |
2038 | else | |
d88c4afd VS |
2039 | return intel_tile_size(to_i915(fb->dev)) / |
2040 | intel_tile_width_bytes(fb, plane); | |
6761dd31 TU |
2041 | } |
2042 | ||
8d0deca8 | 2043 | /* Return the tile dimensions in pixel units */ |
d88c4afd | 2044 | static void intel_tile_dims(const struct drm_framebuffer *fb, int plane, |
8d0deca8 | 2045 | unsigned int *tile_width, |
d88c4afd | 2046 | unsigned int *tile_height) |
8d0deca8 | 2047 | { |
d88c4afd VS |
2048 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane); |
2049 | unsigned int cpp = fb->format->cpp[plane]; | |
8d0deca8 VS |
2050 | |
2051 | *tile_width = tile_width_bytes / cpp; | |
d88c4afd | 2052 | *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes; |
8d0deca8 VS |
2053 | } |
2054 | ||
6761dd31 | 2055 | unsigned int |
d88c4afd VS |
2056 | intel_fb_align_height(const struct drm_framebuffer *fb, |
2057 | int plane, unsigned int height) | |
6761dd31 | 2058 | { |
d88c4afd | 2059 | unsigned int tile_height = intel_tile_height(fb, plane); |
832be82f VS |
2060 | |
2061 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2062 | } |
2063 | ||
1663b9d6 VS |
2064 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2065 | { | |
2066 | unsigned int size = 0; | |
2067 | int i; | |
2068 | ||
2069 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2070 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2071 | ||
2072 | return size; | |
2073 | } | |
2074 | ||
75c82a53 | 2075 | static void |
3465c580 VS |
2076 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2077 | const struct drm_framebuffer *fb, | |
2078 | unsigned int rotation) | |
f64b98cd | 2079 | { |
7b92c047 | 2080 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2081 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2082 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2083 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2084 | } |
2085 | } | |
50470bb0 | 2086 | |
fabac484 VS |
2087 | static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv) |
2088 | { | |
2089 | if (IS_I830(dev_priv)) | |
2090 | return 16 * 1024; | |
2091 | else if (IS_I85X(dev_priv)) | |
2092 | return 256; | |
d9e1551e VS |
2093 | else if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
2094 | return 32; | |
fabac484 VS |
2095 | else |
2096 | return 4 * 1024; | |
2097 | } | |
2098 | ||
603525d7 | 2099 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2100 | { |
2101 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2102 | return 256 * 1024; | |
c0f86832 | 2103 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2104 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2105 | return 128 * 1024; |
2106 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2107 | return 4 * 1024; | |
2108 | else | |
44c5905e | 2109 | return 0; |
4e9a86b6 VS |
2110 | } |
2111 | ||
d88c4afd VS |
2112 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
2113 | int plane) | |
603525d7 | 2114 | { |
d88c4afd VS |
2115 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2116 | ||
b90c1ee1 VS |
2117 | /* AUX_DIST needs only 4K alignment */ |
2118 | if (fb->format->format == DRM_FORMAT_NV12 && plane == 1) | |
2119 | return 4096; | |
2120 | ||
d88c4afd | 2121 | switch (fb->modifier) { |
2f075565 | 2122 | case DRM_FORMAT_MOD_LINEAR: |
603525d7 VS |
2123 | return intel_linear_alignment(dev_priv); |
2124 | case I915_FORMAT_MOD_X_TILED: | |
d88c4afd | 2125 | if (INTEL_GEN(dev_priv) >= 9) |
603525d7 VS |
2126 | return 256 * 1024; |
2127 | return 0; | |
2128 | case I915_FORMAT_MOD_Y_TILED: | |
2129 | case I915_FORMAT_MOD_Yf_TILED: | |
2130 | return 1 * 1024 * 1024; | |
2131 | default: | |
d88c4afd | 2132 | MISSING_CASE(fb->modifier); |
603525d7 VS |
2133 | return 0; |
2134 | } | |
2135 | } | |
2136 | ||
058d88c4 CW |
2137 | struct i915_vma * |
2138 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2139 | { |
850c4cdc | 2140 | struct drm_device *dev = fb->dev; |
fac5e23e | 2141 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2142 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2143 | struct i915_ggtt_view view; |
058d88c4 | 2144 | struct i915_vma *vma; |
6b95a207 | 2145 | u32 alignment; |
6b95a207 | 2146 | |
ebcdd39e MR |
2147 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2148 | ||
d88c4afd | 2149 | alignment = intel_surf_alignment(fb, 0); |
6b95a207 | 2150 | |
3465c580 | 2151 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2152 | |
693db184 CW |
2153 | /* Note that the w/a also requires 64 PTE of padding following the |
2154 | * bo. We currently fill all unused PTE with the shadow page and so | |
2155 | * we should always have valid PTE following the scanout preventing | |
2156 | * the VT-d warning. | |
2157 | */ | |
48f112fe | 2158 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2159 | alignment = 256 * 1024; |
2160 | ||
d6dd6843 PZ |
2161 | /* |
2162 | * Global gtt pte registers are special registers which actually forward | |
2163 | * writes to a chunk of system memory. Which means that there is no risk | |
2164 | * that the register values disappear as soon as we call | |
2165 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2166 | * pin/unpin/fence and not more. | |
2167 | */ | |
2168 | intel_runtime_pm_get(dev_priv); | |
2169 | ||
058d88c4 | 2170 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2171 | if (IS_ERR(vma)) |
2172 | goto err; | |
6b95a207 | 2173 | |
05a20d09 | 2174 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2175 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2176 | * fence, whereas 965+ only requires a fence if using | |
2177 | * framebuffer compression. For simplicity, we always, when | |
2178 | * possible, install a fence as the cost is not that onerous. | |
2179 | * | |
2180 | * If we fail to fence the tiled scanout, then either the | |
2181 | * modeset will reject the change (which is highly unlikely as | |
2182 | * the affected systems, all but one, do not have unmappable | |
2183 | * space) or we will not be able to enable full powersaving | |
2184 | * techniques (also likely not to apply due to various limits | |
2185 | * FBC and the like impose on the size of the buffer, which | |
2186 | * presumably we violated anyway with this unmappable buffer). | |
2187 | * Anyway, it is presumably better to stumble onwards with | |
2188 | * something and try to run the system in a "less than optimal" | |
2189 | * mode that matches the user configuration. | |
2190 | */ | |
2191 | if (i915_vma_get_fence(vma) == 0) | |
2192 | i915_vma_pin_fence(vma); | |
9807216f | 2193 | } |
6b95a207 | 2194 | |
be1e3415 | 2195 | i915_vma_get(vma); |
49ef5294 | 2196 | err: |
d6dd6843 | 2197 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2198 | return vma; |
6b95a207 KH |
2199 | } |
2200 | ||
be1e3415 | 2201 | void intel_unpin_fb_vma(struct i915_vma *vma) |
1690e1eb | 2202 | { |
be1e3415 | 2203 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
f64b98cd | 2204 | |
49ef5294 | 2205 | i915_vma_unpin_fence(vma); |
058d88c4 | 2206 | i915_gem_object_unpin_from_display_plane(vma); |
be1e3415 | 2207 | i915_vma_put(vma); |
1690e1eb CW |
2208 | } |
2209 | ||
ef78ec94 VS |
2210 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2211 | unsigned int rotation) | |
2212 | { | |
bd2ef25d | 2213 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2214 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2215 | else | |
2216 | return fb->pitches[plane]; | |
2217 | } | |
2218 | ||
6687c906 VS |
2219 | /* |
2220 | * Convert the x/y offsets into a linear offset. | |
2221 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2222 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2223 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2224 | */ | |
2225 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2226 | const struct intel_plane_state *state, |
2227 | int plane) | |
6687c906 | 2228 | { |
2949056c | 2229 | const struct drm_framebuffer *fb = state->base.fb; |
353c8598 | 2230 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2231 | unsigned int pitch = fb->pitches[plane]; |
2232 | ||
2233 | return y * pitch + x * cpp; | |
2234 | } | |
2235 | ||
2236 | /* | |
2237 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2238 | * specified plane src x/y offsets. The resulting x/y offsets | |
2239 | * specify the start of scanout from the beginning of the gtt mapping. | |
2240 | */ | |
2241 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2242 | const struct intel_plane_state *state, |
2243 | int plane) | |
6687c906 VS |
2244 | |
2245 | { | |
2949056c VS |
2246 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2247 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2248 | |
bd2ef25d | 2249 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2250 | *x += intel_fb->rotated[plane].x; |
2251 | *y += intel_fb->rotated[plane].y; | |
2252 | } else { | |
2253 | *x += intel_fb->normal[plane].x; | |
2254 | *y += intel_fb->normal[plane].y; | |
2255 | } | |
2256 | } | |
2257 | ||
29cf9491 | 2258 | /* |
29cf9491 VS |
2259 | * Input tile dimensions and pitch must already be |
2260 | * rotated to match x and y, and in pixel units. | |
2261 | */ | |
66a2d927 VS |
2262 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2263 | unsigned int tile_width, | |
2264 | unsigned int tile_height, | |
2265 | unsigned int tile_size, | |
2266 | unsigned int pitch_tiles, | |
2267 | u32 old_offset, | |
2268 | u32 new_offset) | |
29cf9491 | 2269 | { |
b9b24038 | 2270 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2271 | unsigned int tiles; |
2272 | ||
2273 | WARN_ON(old_offset & (tile_size - 1)); | |
2274 | WARN_ON(new_offset & (tile_size - 1)); | |
2275 | WARN_ON(new_offset > old_offset); | |
2276 | ||
2277 | tiles = (old_offset - new_offset) / tile_size; | |
2278 | ||
2279 | *y += tiles / pitch_tiles * tile_height; | |
2280 | *x += tiles % pitch_tiles * tile_width; | |
2281 | ||
b9b24038 VS |
2282 | /* minimize x in case it got needlessly big */ |
2283 | *y += *x / pitch_pixels * tile_height; | |
2284 | *x %= pitch_pixels; | |
2285 | ||
29cf9491 VS |
2286 | return new_offset; |
2287 | } | |
2288 | ||
66a2d927 VS |
2289 | /* |
2290 | * Adjust the tile offset by moving the difference into | |
2291 | * the x/y offsets. | |
2292 | */ | |
2293 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2294 | const struct intel_plane_state *state, int plane, | |
2295 | u32 old_offset, u32 new_offset) | |
2296 | { | |
2297 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2298 | const struct drm_framebuffer *fb = state->base.fb; | |
353c8598 | 2299 | unsigned int cpp = fb->format->cpp[plane]; |
66a2d927 VS |
2300 | unsigned int rotation = state->base.rotation; |
2301 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2302 | ||
2303 | WARN_ON(new_offset > old_offset); | |
2304 | ||
2f075565 | 2305 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
66a2d927 VS |
2306 | unsigned int tile_size, tile_width, tile_height; |
2307 | unsigned int pitch_tiles; | |
2308 | ||
2309 | tile_size = intel_tile_size(dev_priv); | |
d88c4afd | 2310 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
66a2d927 | 2311 | |
bd2ef25d | 2312 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2313 | pitch_tiles = pitch / tile_height; |
2314 | swap(tile_width, tile_height); | |
2315 | } else { | |
2316 | pitch_tiles = pitch / (tile_width * cpp); | |
2317 | } | |
2318 | ||
2319 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2320 | tile_size, pitch_tiles, | |
2321 | old_offset, new_offset); | |
2322 | } else { | |
2323 | old_offset += *y * pitch + *x * cpp; | |
2324 | ||
2325 | *y = (old_offset - new_offset) / pitch; | |
2326 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2327 | } | |
2328 | ||
2329 | return new_offset; | |
2330 | } | |
2331 | ||
8d0deca8 VS |
2332 | /* |
2333 | * Computes the linear offset to the base tile and adjusts | |
2334 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2335 | * | |
2336 | * In the 90/270 rotated case, x and y are assumed | |
2337 | * to be already rotated to match the rotated GTT view, and | |
2338 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2339 | * |
2340 | * This function is used when computing the derived information | |
2341 | * under intel_framebuffer, so using any of that information | |
2342 | * here is not allowed. Anything under drm_framebuffer can be | |
2343 | * used. This is why the user has to pass in the pitch since it | |
2344 | * is specified in the rotated orientation. | |
8d0deca8 | 2345 | */ |
6687c906 VS |
2346 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2347 | int *x, int *y, | |
2348 | const struct drm_framebuffer *fb, int plane, | |
2349 | unsigned int pitch, | |
2350 | unsigned int rotation, | |
2351 | u32 alignment) | |
c2c75131 | 2352 | { |
bae781b2 | 2353 | uint64_t fb_modifier = fb->modifier; |
353c8598 | 2354 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 | 2355 | u32 offset, offset_aligned; |
29cf9491 | 2356 | |
29cf9491 VS |
2357 | if (alignment) |
2358 | alignment--; | |
2359 | ||
2f075565 | 2360 | if (fb_modifier != DRM_FORMAT_MOD_LINEAR) { |
8d0deca8 VS |
2361 | unsigned int tile_size, tile_width, tile_height; |
2362 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2363 | |
d843310d | 2364 | tile_size = intel_tile_size(dev_priv); |
d88c4afd | 2365 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
8d0deca8 | 2366 | |
bd2ef25d | 2367 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2368 | pitch_tiles = pitch / tile_height; |
2369 | swap(tile_width, tile_height); | |
2370 | } else { | |
2371 | pitch_tiles = pitch / (tile_width * cpp); | |
2372 | } | |
d843310d VS |
2373 | |
2374 | tile_rows = *y / tile_height; | |
2375 | *y %= tile_height; | |
c2c75131 | 2376 | |
8d0deca8 VS |
2377 | tiles = *x / tile_width; |
2378 | *x %= tile_width; | |
bc752862 | 2379 | |
29cf9491 VS |
2380 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2381 | offset_aligned = offset & ~alignment; | |
bc752862 | 2382 | |
66a2d927 VS |
2383 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2384 | tile_size, pitch_tiles, | |
2385 | offset, offset_aligned); | |
29cf9491 | 2386 | } else { |
bc752862 | 2387 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2388 | offset_aligned = offset & ~alignment; |
2389 | ||
4e9a86b6 VS |
2390 | *y = (offset & alignment) / pitch; |
2391 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2392 | } |
29cf9491 VS |
2393 | |
2394 | return offset_aligned; | |
c2c75131 DV |
2395 | } |
2396 | ||
6687c906 | 2397 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2398 | const struct intel_plane_state *state, |
2399 | int plane) | |
6687c906 | 2400 | { |
1e7b4fd8 VS |
2401 | struct intel_plane *intel_plane = to_intel_plane(state->base.plane); |
2402 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); | |
2949056c VS |
2403 | const struct drm_framebuffer *fb = state->base.fb; |
2404 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2405 | int pitch = intel_fb_pitch(fb, plane, rotation); |
1e7b4fd8 VS |
2406 | u32 alignment; |
2407 | ||
2408 | if (intel_plane->id == PLANE_CURSOR) | |
2409 | alignment = intel_cursor_alignment(dev_priv); | |
2410 | else | |
2411 | alignment = intel_surf_alignment(fb, plane); | |
6687c906 VS |
2412 | |
2413 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2414 | rotation, alignment); | |
2415 | } | |
2416 | ||
2417 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2418 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2419 | const struct drm_framebuffer *fb, int plane) | |
2420 | { | |
353c8598 | 2421 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2422 | unsigned int pitch = fb->pitches[plane]; |
2423 | u32 linear_offset = fb->offsets[plane]; | |
2424 | ||
2425 | *y = linear_offset / pitch; | |
2426 | *x = linear_offset % pitch / cpp; | |
2427 | } | |
2428 | ||
72618ebf VS |
2429 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2430 | { | |
2431 | switch (fb_modifier) { | |
2432 | case I915_FORMAT_MOD_X_TILED: | |
2433 | return I915_TILING_X; | |
2434 | case I915_FORMAT_MOD_Y_TILED: | |
2435 | return I915_TILING_Y; | |
2436 | default: | |
2437 | return I915_TILING_NONE; | |
2438 | } | |
2439 | } | |
2440 | ||
6687c906 VS |
2441 | static int |
2442 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2443 | struct drm_framebuffer *fb) | |
2444 | { | |
2445 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2446 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2447 | u32 gtt_offset_rotated = 0; | |
2448 | unsigned int max_size = 0; | |
bcb0b461 | 2449 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
2450 | unsigned int tile_size = intel_tile_size(dev_priv); |
2451 | ||
2452 | for (i = 0; i < num_planes; i++) { | |
2453 | unsigned int width, height; | |
2454 | unsigned int cpp, size; | |
2455 | u32 offset; | |
2456 | int x, y; | |
2457 | ||
353c8598 | 2458 | cpp = fb->format->cpp[i]; |
145fcb11 VS |
2459 | width = drm_framebuffer_plane_width(fb->width, fb, i); |
2460 | height = drm_framebuffer_plane_height(fb->height, fb, i); | |
6687c906 VS |
2461 | |
2462 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2463 | ||
60d5f2a4 VS |
2464 | /* |
2465 | * The fence (if used) is aligned to the start of the object | |
2466 | * so having the framebuffer wrap around across the edge of the | |
2467 | * fenced region doesn't really work. We have no API to configure | |
2468 | * the fence start offset within the object (nor could we probably | |
2469 | * on gen2/3). So it's just easier if we just require that the | |
2470 | * fb layout agrees with the fence layout. We already check that the | |
2471 | * fb stride matches the fence stride elsewhere. | |
2472 | */ | |
2473 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2474 | (x + width) * cpp > fb->pitches[i]) { | |
144cc143 VS |
2475 | DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", |
2476 | i, fb->offsets[i]); | |
60d5f2a4 VS |
2477 | return -EINVAL; |
2478 | } | |
2479 | ||
6687c906 VS |
2480 | /* |
2481 | * First pixel of the framebuffer from | |
2482 | * the start of the normal gtt mapping. | |
2483 | */ | |
2484 | intel_fb->normal[i].x = x; | |
2485 | intel_fb->normal[i].y = y; | |
2486 | ||
2487 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
3ca46c0a | 2488 | fb, i, fb->pitches[i], |
c2c446ad | 2489 | DRM_MODE_ROTATE_0, tile_size); |
6687c906 VS |
2490 | offset /= tile_size; |
2491 | ||
2f075565 | 2492 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
6687c906 VS |
2493 | unsigned int tile_width, tile_height; |
2494 | unsigned int pitch_tiles; | |
2495 | struct drm_rect r; | |
2496 | ||
d88c4afd | 2497 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
6687c906 VS |
2498 | |
2499 | rot_info->plane[i].offset = offset; | |
2500 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2501 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2502 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2503 | ||
2504 | intel_fb->rotated[i].pitch = | |
2505 | rot_info->plane[i].height * tile_height; | |
2506 | ||
2507 | /* how many tiles does this plane need */ | |
2508 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2509 | /* | |
2510 | * If the plane isn't horizontally tile aligned, | |
2511 | * we need one more tile. | |
2512 | */ | |
2513 | if (x != 0) | |
2514 | size++; | |
2515 | ||
2516 | /* rotate the x/y offsets to match the GTT view */ | |
2517 | r.x1 = x; | |
2518 | r.y1 = y; | |
2519 | r.x2 = x + width; | |
2520 | r.y2 = y + height; | |
2521 | drm_rect_rotate(&r, | |
2522 | rot_info->plane[i].width * tile_width, | |
2523 | rot_info->plane[i].height * tile_height, | |
c2c446ad | 2524 | DRM_MODE_ROTATE_270); |
6687c906 VS |
2525 | x = r.x1; |
2526 | y = r.y1; | |
2527 | ||
2528 | /* rotate the tile dimensions to match the GTT view */ | |
2529 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2530 | swap(tile_width, tile_height); | |
2531 | ||
2532 | /* | |
2533 | * We only keep the x/y offsets, so push all of the | |
2534 | * gtt offset into the x/y offsets. | |
2535 | */ | |
46a1bd28 ACO |
2536 | _intel_adjust_tile_offset(&x, &y, |
2537 | tile_width, tile_height, | |
2538 | tile_size, pitch_tiles, | |
66a2d927 | 2539 | gtt_offset_rotated * tile_size, 0); |
6687c906 VS |
2540 | |
2541 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2542 | ||
2543 | /* | |
2544 | * First pixel of the framebuffer from | |
2545 | * the start of the rotated gtt mapping. | |
2546 | */ | |
2547 | intel_fb->rotated[i].x = x; | |
2548 | intel_fb->rotated[i].y = y; | |
2549 | } else { | |
2550 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2551 | x * cpp, tile_size); | |
2552 | } | |
2553 | ||
2554 | /* how many tiles in total needed in the bo */ | |
2555 | max_size = max(max_size, offset + size); | |
2556 | } | |
2557 | ||
144cc143 VS |
2558 | if (max_size * tile_size > intel_fb->obj->base.size) { |
2559 | DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2560 | max_size * tile_size, intel_fb->obj->base.size); | |
6687c906 VS |
2561 | return -EINVAL; |
2562 | } | |
2563 | ||
2564 | return 0; | |
2565 | } | |
2566 | ||
b35d63fa | 2567 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2568 | { |
2569 | switch (format) { | |
2570 | case DISPPLANE_8BPP: | |
2571 | return DRM_FORMAT_C8; | |
2572 | case DISPPLANE_BGRX555: | |
2573 | return DRM_FORMAT_XRGB1555; | |
2574 | case DISPPLANE_BGRX565: | |
2575 | return DRM_FORMAT_RGB565; | |
2576 | default: | |
2577 | case DISPPLANE_BGRX888: | |
2578 | return DRM_FORMAT_XRGB8888; | |
2579 | case DISPPLANE_RGBX888: | |
2580 | return DRM_FORMAT_XBGR8888; | |
2581 | case DISPPLANE_BGRX101010: | |
2582 | return DRM_FORMAT_XRGB2101010; | |
2583 | case DISPPLANE_RGBX101010: | |
2584 | return DRM_FORMAT_XBGR2101010; | |
2585 | } | |
2586 | } | |
2587 | ||
bc8d7dff DL |
2588 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2589 | { | |
2590 | switch (format) { | |
2591 | case PLANE_CTL_FORMAT_RGB_565: | |
2592 | return DRM_FORMAT_RGB565; | |
2593 | default: | |
2594 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2595 | if (rgb_order) { | |
2596 | if (alpha) | |
2597 | return DRM_FORMAT_ABGR8888; | |
2598 | else | |
2599 | return DRM_FORMAT_XBGR8888; | |
2600 | } else { | |
2601 | if (alpha) | |
2602 | return DRM_FORMAT_ARGB8888; | |
2603 | else | |
2604 | return DRM_FORMAT_XRGB8888; | |
2605 | } | |
2606 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2607 | if (rgb_order) | |
2608 | return DRM_FORMAT_XBGR2101010; | |
2609 | else | |
2610 | return DRM_FORMAT_XRGB2101010; | |
2611 | } | |
2612 | } | |
2613 | ||
5724dbd1 | 2614 | static bool |
f6936e29 DV |
2615 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2616 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2617 | { |
2618 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2619 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2620 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2621 | struct drm_i915_gem_object *obj = NULL; |
2622 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2623 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2624 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2625 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2626 | PAGE_SIZE); | |
2627 | ||
2628 | size_aligned -= base_aligned; | |
46f297fb | 2629 | |
ff2652ea CW |
2630 | if (plane_config->size == 0) |
2631 | return false; | |
2632 | ||
3badb49f PZ |
2633 | /* If the FB is too big, just don't use it since fbdev is not very |
2634 | * important and we should probably use that space with FBC or other | |
2635 | * features. */ | |
72e96d64 | 2636 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2637 | return false; |
2638 | ||
12c83d99 | 2639 | mutex_lock(&dev->struct_mutex); |
187685cb | 2640 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2641 | base_aligned, |
2642 | base_aligned, | |
2643 | size_aligned); | |
24dbf51a CW |
2644 | mutex_unlock(&dev->struct_mutex); |
2645 | if (!obj) | |
484b41dd | 2646 | return false; |
46f297fb | 2647 | |
3e510a8e CW |
2648 | if (plane_config->tiling == I915_TILING_X) |
2649 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2650 | |
438b74a5 | 2651 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
2652 | mode_cmd.width = fb->width; |
2653 | mode_cmd.height = fb->height; | |
2654 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2655 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2656 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2657 | |
24dbf51a | 2658 | if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { |
46f297fb JB |
2659 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2660 | goto out_unref_obj; | |
2661 | } | |
12c83d99 | 2662 | |
484b41dd | 2663 | |
f6936e29 | 2664 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2665 | return true; |
46f297fb JB |
2666 | |
2667 | out_unref_obj: | |
f8c417cd | 2668 | i915_gem_object_put(obj); |
484b41dd JB |
2669 | return false; |
2670 | } | |
2671 | ||
5a21b665 DV |
2672 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2673 | static void | |
2674 | update_state_fb(struct drm_plane *plane) | |
2675 | { | |
2676 | if (plane->fb == plane->state->fb) | |
2677 | return; | |
2678 | ||
2679 | if (plane->state->fb) | |
2680 | drm_framebuffer_unreference(plane->state->fb); | |
2681 | plane->state->fb = plane->fb; | |
2682 | if (plane->state->fb) | |
2683 | drm_framebuffer_reference(plane->state->fb); | |
2684 | } | |
2685 | ||
e9728bd8 VS |
2686 | static void |
2687 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
2688 | struct intel_plane_state *plane_state, | |
2689 | bool visible) | |
2690 | { | |
2691 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
2692 | ||
2693 | plane_state->base.visible = visible; | |
2694 | ||
2695 | /* FIXME pre-g4x don't work like this */ | |
2696 | if (visible) { | |
2697 | crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); | |
2698 | crtc_state->active_planes |= BIT(plane->id); | |
2699 | } else { | |
2700 | crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); | |
2701 | crtc_state->active_planes &= ~BIT(plane->id); | |
2702 | } | |
2703 | ||
2704 | DRM_DEBUG_KMS("%s active planes 0x%x\n", | |
2705 | crtc_state->base.crtc->name, | |
2706 | crtc_state->active_planes); | |
2707 | } | |
2708 | ||
5724dbd1 | 2709 | static void |
f6936e29 DV |
2710 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2711 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2712 | { |
2713 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2714 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 2715 | struct drm_crtc *c; |
2ff8fde1 | 2716 | struct drm_i915_gem_object *obj; |
88595ac9 | 2717 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2718 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2719 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2720 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2721 | struct intel_plane_state *intel_state = |
2722 | to_intel_plane_state(plane_state); | |
88595ac9 | 2723 | struct drm_framebuffer *fb; |
484b41dd | 2724 | |
2d14030b | 2725 | if (!plane_config->fb) |
484b41dd JB |
2726 | return; |
2727 | ||
f6936e29 | 2728 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2729 | fb = &plane_config->fb->base; |
2730 | goto valid_fb; | |
f55548b5 | 2731 | } |
484b41dd | 2732 | |
2d14030b | 2733 | kfree(plane_config->fb); |
484b41dd JB |
2734 | |
2735 | /* | |
2736 | * Failed to alloc the obj, check to see if we should share | |
2737 | * an fb with another CRTC instead | |
2738 | */ | |
70e1e0ec | 2739 | for_each_crtc(dev, c) { |
be1e3415 | 2740 | struct intel_plane_state *state; |
484b41dd JB |
2741 | |
2742 | if (c == &intel_crtc->base) | |
2743 | continue; | |
2744 | ||
be1e3415 | 2745 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
2746 | continue; |
2747 | ||
be1e3415 CW |
2748 | state = to_intel_plane_state(c->primary->state); |
2749 | if (!state->vma) | |
484b41dd JB |
2750 | continue; |
2751 | ||
be1e3415 CW |
2752 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
2753 | fb = c->primary->fb; | |
88595ac9 DV |
2754 | drm_framebuffer_reference(fb); |
2755 | goto valid_fb; | |
484b41dd JB |
2756 | } |
2757 | } | |
88595ac9 | 2758 | |
200757f5 MR |
2759 | /* |
2760 | * We've failed to reconstruct the BIOS FB. Current display state | |
2761 | * indicates that the primary plane is visible, but has a NULL FB, | |
2762 | * which will lead to problems later if we don't fix it up. The | |
2763 | * simplest solution is to just disable the primary plane now and | |
2764 | * pretend the BIOS never had it enabled. | |
2765 | */ | |
e9728bd8 VS |
2766 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), |
2767 | to_intel_plane_state(plane_state), | |
2768 | false); | |
2622a081 | 2769 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
72259536 | 2770 | trace_intel_disable_plane(primary, intel_crtc); |
282dbf9b | 2771 | intel_plane->disable_plane(intel_plane, intel_crtc); |
200757f5 | 2772 | |
88595ac9 DV |
2773 | return; |
2774 | ||
2775 | valid_fb: | |
be1e3415 CW |
2776 | mutex_lock(&dev->struct_mutex); |
2777 | intel_state->vma = | |
2778 | intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
2779 | mutex_unlock(&dev->struct_mutex); | |
2780 | if (IS_ERR(intel_state->vma)) { | |
2781 | DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", | |
2782 | intel_crtc->pipe, PTR_ERR(intel_state->vma)); | |
2783 | ||
2784 | intel_state->vma = NULL; | |
2785 | drm_framebuffer_unreference(fb); | |
2786 | return; | |
2787 | } | |
2788 | ||
f44e2659 VS |
2789 | plane_state->src_x = 0; |
2790 | plane_state->src_y = 0; | |
be5651f2 ML |
2791 | plane_state->src_w = fb->width << 16; |
2792 | plane_state->src_h = fb->height << 16; | |
2793 | ||
f44e2659 VS |
2794 | plane_state->crtc_x = 0; |
2795 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2796 | plane_state->crtc_w = fb->width; |
2797 | plane_state->crtc_h = fb->height; | |
2798 | ||
1638d30c RC |
2799 | intel_state->base.src = drm_plane_state_src(plane_state); |
2800 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2801 | |
88595ac9 | 2802 | obj = intel_fb_obj(fb); |
3e510a8e | 2803 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2804 | dev_priv->preserve_bios_swizzle = true; |
2805 | ||
be5651f2 ML |
2806 | drm_framebuffer_reference(fb); |
2807 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2808 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
e9728bd8 VS |
2809 | |
2810 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), | |
2811 | to_intel_plane_state(plane_state), | |
2812 | true); | |
2813 | ||
faf5bf0a CW |
2814 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2815 | &obj->frontbuffer_bits); | |
46f297fb JB |
2816 | } |
2817 | ||
b63a16f6 VS |
2818 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2819 | unsigned int rotation) | |
2820 | { | |
353c8598 | 2821 | int cpp = fb->format->cpp[plane]; |
b63a16f6 | 2822 | |
bae781b2 | 2823 | switch (fb->modifier) { |
2f075565 | 2824 | case DRM_FORMAT_MOD_LINEAR: |
b63a16f6 VS |
2825 | case I915_FORMAT_MOD_X_TILED: |
2826 | switch (cpp) { | |
2827 | case 8: | |
2828 | return 4096; | |
2829 | case 4: | |
2830 | case 2: | |
2831 | case 1: | |
2832 | return 8192; | |
2833 | default: | |
2834 | MISSING_CASE(cpp); | |
2835 | break; | |
2836 | } | |
2837 | break; | |
2838 | case I915_FORMAT_MOD_Y_TILED: | |
2839 | case I915_FORMAT_MOD_Yf_TILED: | |
2840 | switch (cpp) { | |
2841 | case 8: | |
2842 | return 2048; | |
2843 | case 4: | |
2844 | return 4096; | |
2845 | case 2: | |
2846 | case 1: | |
2847 | return 8192; | |
2848 | default: | |
2849 | MISSING_CASE(cpp); | |
2850 | break; | |
2851 | } | |
2852 | break; | |
2853 | default: | |
bae781b2 | 2854 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2855 | } |
2856 | ||
2857 | return 2048; | |
2858 | } | |
2859 | ||
2860 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2861 | { | |
b63a16f6 VS |
2862 | const struct drm_framebuffer *fb = plane_state->base.fb; |
2863 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2864 | int x = plane_state->base.src.x1 >> 16; |
2865 | int y = plane_state->base.src.y1 >> 16; | |
2866 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2867 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2868 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2869 | int max_height = 4096; | |
8d970654 | 2870 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2871 | |
2872 | if (w > max_width || h > max_height) { | |
2873 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2874 | w, h, max_width, max_height); | |
2875 | return -EINVAL; | |
2876 | } | |
2877 | ||
2878 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2879 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
d88c4afd | 2880 | alignment = intel_surf_alignment(fb, 0); |
b63a16f6 | 2881 | |
8d970654 VS |
2882 | /* |
2883 | * AUX surface offset is specified as the distance from the | |
2884 | * main surface offset, and it must be non-negative. Make | |
2885 | * sure that is what we will get. | |
2886 | */ | |
2887 | if (offset > aux_offset) | |
2888 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2889 | offset, aux_offset & ~(alignment - 1)); | |
2890 | ||
b63a16f6 VS |
2891 | /* |
2892 | * When using an X-tiled surface, the plane blows up | |
2893 | * if the x offset + width exceed the stride. | |
2894 | * | |
2895 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2896 | */ | |
bae781b2 | 2897 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 2898 | int cpp = fb->format->cpp[0]; |
b63a16f6 VS |
2899 | |
2900 | while ((x + w) * cpp > fb->pitches[0]) { | |
2901 | if (offset == 0) { | |
2902 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2903 | return -EINVAL; | |
2904 | } | |
2905 | ||
2906 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2907 | offset, offset - alignment); | |
2908 | } | |
2909 | } | |
2910 | ||
2911 | plane_state->main.offset = offset; | |
2912 | plane_state->main.x = x; | |
2913 | plane_state->main.y = y; | |
2914 | ||
2915 | return 0; | |
2916 | } | |
2917 | ||
8d970654 VS |
2918 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2919 | { | |
2920 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2921 | unsigned int rotation = plane_state->base.rotation; | |
2922 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2923 | int max_height = 4096; | |
cc926387 DV |
2924 | int x = plane_state->base.src.x1 >> 17; |
2925 | int y = plane_state->base.src.y1 >> 17; | |
2926 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2927 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2928 | u32 offset; |
2929 | ||
2930 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2931 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2932 | ||
2933 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2934 | if (w > max_width || h > max_height) { | |
2935 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2936 | w, h, max_width, max_height); | |
2937 | return -EINVAL; | |
2938 | } | |
2939 | ||
2940 | plane_state->aux.offset = offset; | |
2941 | plane_state->aux.x = x; | |
2942 | plane_state->aux.y = y; | |
2943 | ||
2944 | return 0; | |
2945 | } | |
2946 | ||
b63a16f6 VS |
2947 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2948 | { | |
2949 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2950 | unsigned int rotation = plane_state->base.rotation; | |
2951 | int ret; | |
2952 | ||
a5e4c7d0 VS |
2953 | if (!plane_state->base.visible) |
2954 | return 0; | |
2955 | ||
b63a16f6 | 2956 | /* Rotate src coordinates to match rotated GTT view */ |
bd2ef25d | 2957 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 2958 | drm_rect_rotate(&plane_state->base.src, |
da064b47 | 2959 | fb->width << 16, fb->height << 16, |
c2c446ad | 2960 | DRM_MODE_ROTATE_270); |
b63a16f6 | 2961 | |
8d970654 VS |
2962 | /* |
2963 | * Handle the AUX surface first since | |
2964 | * the main surface setup depends on it. | |
2965 | */ | |
438b74a5 | 2966 | if (fb->format->format == DRM_FORMAT_NV12) { |
8d970654 VS |
2967 | ret = skl_check_nv12_aux_surface(plane_state); |
2968 | if (ret) | |
2969 | return ret; | |
2970 | } else { | |
2971 | plane_state->aux.offset = ~0xfff; | |
2972 | plane_state->aux.x = 0; | |
2973 | plane_state->aux.y = 0; | |
2974 | } | |
2975 | ||
b63a16f6 VS |
2976 | ret = skl_check_main_surface(plane_state); |
2977 | if (ret) | |
2978 | return ret; | |
2979 | ||
2980 | return 0; | |
2981 | } | |
2982 | ||
7145f60a VS |
2983 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
2984 | const struct intel_plane_state *plane_state) | |
81255565 | 2985 | { |
7145f60a VS |
2986 | struct drm_i915_private *dev_priv = |
2987 | to_i915(plane_state->base.plane->dev); | |
2988 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
2989 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
8d0deca8 | 2990 | unsigned int rotation = plane_state->base.rotation; |
7145f60a | 2991 | u32 dspcntr; |
c9ba6fad | 2992 | |
7145f60a | 2993 | dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; |
f45651ba | 2994 | |
6a4407a6 VS |
2995 | if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || |
2996 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
7145f60a | 2997 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
f45651ba | 2998 | |
6a4407a6 VS |
2999 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
3000 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
f45651ba | 3001 | |
d509e28b VS |
3002 | if (INTEL_GEN(dev_priv) < 4) |
3003 | dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); | |
81255565 | 3004 | |
438b74a5 | 3005 | switch (fb->format->format) { |
57779d06 | 3006 | case DRM_FORMAT_C8: |
81255565 JB |
3007 | dspcntr |= DISPPLANE_8BPP; |
3008 | break; | |
57779d06 | 3009 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3010 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3011 | break; |
57779d06 VS |
3012 | case DRM_FORMAT_RGB565: |
3013 | dspcntr |= DISPPLANE_BGRX565; | |
3014 | break; | |
3015 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3016 | dspcntr |= DISPPLANE_BGRX888; |
3017 | break; | |
3018 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3019 | dspcntr |= DISPPLANE_RGBX888; |
3020 | break; | |
3021 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3022 | dspcntr |= DISPPLANE_BGRX101010; |
3023 | break; | |
3024 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3025 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3026 | break; |
3027 | default: | |
7145f60a VS |
3028 | MISSING_CASE(fb->format->format); |
3029 | return 0; | |
81255565 | 3030 | } |
57779d06 | 3031 | |
72618ebf | 3032 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3033 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3034 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3035 | |
c2c446ad | 3036 | if (rotation & DRM_MODE_ROTATE_180) |
df0cd455 VS |
3037 | dspcntr |= DISPPLANE_ROTATE_180; |
3038 | ||
c2c446ad | 3039 | if (rotation & DRM_MODE_REFLECT_X) |
4ea7be2b VS |
3040 | dspcntr |= DISPPLANE_MIRROR; |
3041 | ||
7145f60a VS |
3042 | return dspcntr; |
3043 | } | |
de1aa629 | 3044 | |
f9407ae1 | 3045 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
5b7fcc44 VS |
3046 | { |
3047 | struct drm_i915_private *dev_priv = | |
3048 | to_i915(plane_state->base.plane->dev); | |
3049 | int src_x = plane_state->base.src.x1 >> 16; | |
3050 | int src_y = plane_state->base.src.y1 >> 16; | |
3051 | u32 offset; | |
81255565 | 3052 | |
5b7fcc44 | 3053 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
e506a0c6 | 3054 | |
5b7fcc44 VS |
3055 | if (INTEL_GEN(dev_priv) >= 4) |
3056 | offset = intel_compute_tile_offset(&src_x, &src_y, | |
3057 | plane_state, 0); | |
3058 | else | |
3059 | offset = 0; | |
3060 | ||
3061 | /* HSW/BDW do this automagically in hardware */ | |
3062 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { | |
3063 | unsigned int rotation = plane_state->base.rotation; | |
3064 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; | |
3065 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3066 | ||
c2c446ad | 3067 | if (rotation & DRM_MODE_ROTATE_180) { |
5b7fcc44 VS |
3068 | src_x += src_w - 1; |
3069 | src_y += src_h - 1; | |
c2c446ad | 3070 | } else if (rotation & DRM_MODE_REFLECT_X) { |
5b7fcc44 VS |
3071 | src_x += src_w - 1; |
3072 | } | |
48404c1e SJ |
3073 | } |
3074 | ||
5b7fcc44 VS |
3075 | plane_state->main.offset = offset; |
3076 | plane_state->main.x = src_x; | |
3077 | plane_state->main.y = src_y; | |
3078 | ||
3079 | return 0; | |
3080 | } | |
3081 | ||
282dbf9b | 3082 | static void i9xx_update_primary_plane(struct intel_plane *primary, |
7145f60a VS |
3083 | const struct intel_crtc_state *crtc_state, |
3084 | const struct intel_plane_state *plane_state) | |
3085 | { | |
282dbf9b VS |
3086 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3087 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3088 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3089 | enum plane plane = primary->plane; | |
7145f60a | 3090 | u32 linear_offset; |
a0864d59 | 3091 | u32 dspcntr = plane_state->ctl; |
7145f60a | 3092 | i915_reg_t reg = DSPCNTR(plane); |
5b7fcc44 VS |
3093 | int x = plane_state->main.x; |
3094 | int y = plane_state->main.y; | |
7145f60a VS |
3095 | unsigned long irqflags; |
3096 | ||
2949056c | 3097 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3098 | |
5b7fcc44 | 3099 | if (INTEL_GEN(dev_priv) >= 4) |
282dbf9b | 3100 | crtc->dspaddr_offset = plane_state->main.offset; |
5b7fcc44 | 3101 | else |
282dbf9b | 3102 | crtc->dspaddr_offset = linear_offset; |
6687c906 | 3103 | |
282dbf9b VS |
3104 | crtc->adjusted_x = x; |
3105 | crtc->adjusted_y = y; | |
2db3366b | 3106 | |
dd584fc0 VS |
3107 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3108 | ||
78587de2 VS |
3109 | if (INTEL_GEN(dev_priv) < 4) { |
3110 | /* pipesrc and dspsize control the size that is scaled from, | |
3111 | * which should always be the user's requested size. | |
3112 | */ | |
dd584fc0 VS |
3113 | I915_WRITE_FW(DSPSIZE(plane), |
3114 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3115 | (crtc_state->pipe_src_w - 1)); | |
3116 | I915_WRITE_FW(DSPPOS(plane), 0); | |
78587de2 | 3117 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
dd584fc0 VS |
3118 | I915_WRITE_FW(PRIMSIZE(plane), |
3119 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3120 | (crtc_state->pipe_src_w - 1)); | |
3121 | I915_WRITE_FW(PRIMPOS(plane), 0); | |
3122 | I915_WRITE_FW(PRIMCNSTALPHA(plane), 0); | |
78587de2 VS |
3123 | } |
3124 | ||
dd584fc0 | 3125 | I915_WRITE_FW(reg, dspcntr); |
48404c1e | 3126 | |
dd584fc0 | 3127 | I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]); |
3ba35e53 VS |
3128 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3129 | I915_WRITE_FW(DSPSURF(plane), | |
3130 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3131 | crtc->dspaddr_offset); |
3ba35e53 VS |
3132 | I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); |
3133 | } else if (INTEL_GEN(dev_priv) >= 4) { | |
dd584fc0 VS |
3134 | I915_WRITE_FW(DSPSURF(plane), |
3135 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3136 | crtc->dspaddr_offset); |
dd584fc0 VS |
3137 | I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); |
3138 | I915_WRITE_FW(DSPLINOFF(plane), linear_offset); | |
bfb81049 | 3139 | } else { |
dd584fc0 VS |
3140 | I915_WRITE_FW(DSPADDR(plane), |
3141 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3142 | crtc->dspaddr_offset); |
bfb81049 | 3143 | } |
dd584fc0 VS |
3144 | POSTING_READ_FW(reg); |
3145 | ||
3146 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
17638cd6 JB |
3147 | } |
3148 | ||
282dbf9b VS |
3149 | static void i9xx_disable_primary_plane(struct intel_plane *primary, |
3150 | struct intel_crtc *crtc) | |
17638cd6 | 3151 | { |
282dbf9b VS |
3152 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3153 | enum plane plane = primary->plane; | |
dd584fc0 VS |
3154 | unsigned long irqflags; |
3155 | ||
3156 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
f45651ba | 3157 | |
dd584fc0 | 3158 | I915_WRITE_FW(DSPCNTR(plane), 0); |
a8d201af | 3159 | if (INTEL_INFO(dev_priv)->gen >= 4) |
dd584fc0 | 3160 | I915_WRITE_FW(DSPSURF(plane), 0); |
a8d201af | 3161 | else |
dd584fc0 VS |
3162 | I915_WRITE_FW(DSPADDR(plane), 0); |
3163 | POSTING_READ_FW(DSPCNTR(plane)); | |
3164 | ||
3165 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3166 | } |
c9ba6fad | 3167 | |
d88c4afd VS |
3168 | static u32 |
3169 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane) | |
b321803d | 3170 | { |
2f075565 | 3171 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
b321803d | 3172 | return 64; |
d88c4afd VS |
3173 | else |
3174 | return intel_tile_width_bytes(fb, plane); | |
b321803d DL |
3175 | } |
3176 | ||
e435d6e5 ML |
3177 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3178 | { | |
3179 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3180 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3181 | |
3182 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3183 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3184 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3185 | } |
3186 | ||
a1b2278e CK |
3187 | /* |
3188 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3189 | */ | |
0583236e | 3190 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3191 | { |
a1b2278e CK |
3192 | struct intel_crtc_scaler_state *scaler_state; |
3193 | int i; | |
3194 | ||
a1b2278e CK |
3195 | scaler_state = &intel_crtc->config->scaler_state; |
3196 | ||
3197 | /* loop through and disable scalers that aren't in use */ | |
3198 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3199 | if (!scaler_state->scalers[i].in_use) |
3200 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3201 | } |
3202 | } | |
3203 | ||
d2196774 VS |
3204 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3205 | unsigned int rotation) | |
3206 | { | |
1b500535 VS |
3207 | u32 stride; |
3208 | ||
3209 | if (plane >= fb->format->num_planes) | |
3210 | return 0; | |
3211 | ||
3212 | stride = intel_fb_pitch(fb, plane, rotation); | |
d2196774 VS |
3213 | |
3214 | /* | |
3215 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3216 | * linear buffers or in number of tiles for tiled buffers. | |
3217 | */ | |
d88c4afd VS |
3218 | if (drm_rotation_90_or_270(rotation)) |
3219 | stride /= intel_tile_height(fb, plane); | |
3220 | else | |
3221 | stride /= intel_fb_stride_alignment(fb, plane); | |
d2196774 VS |
3222 | |
3223 | return stride; | |
3224 | } | |
3225 | ||
2e881264 | 3226 | static u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3227 | { |
6156a456 | 3228 | switch (pixel_format) { |
d161cf7a | 3229 | case DRM_FORMAT_C8: |
c34ce3d1 | 3230 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3231 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3232 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3233 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3234 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3235 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3236 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3237 | /* |
3238 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3239 | * to be already pre-multiplied. We need to add a knob (or a different | |
3240 | * DRM_FORMAT) for user-space to configure that. | |
3241 | */ | |
f75fb42a | 3242 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3243 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3244 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3245 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3246 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3247 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3248 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3249 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3250 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3251 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3252 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3253 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3254 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3255 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3256 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3257 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3258 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3259 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3260 | default: |
4249eeef | 3261 | MISSING_CASE(pixel_format); |
70d21f0e | 3262 | } |
8cfcba41 | 3263 | |
c34ce3d1 | 3264 | return 0; |
6156a456 | 3265 | } |
70d21f0e | 3266 | |
2e881264 | 3267 | static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
6156a456 | 3268 | { |
6156a456 | 3269 | switch (fb_modifier) { |
2f075565 | 3270 | case DRM_FORMAT_MOD_LINEAR: |
70d21f0e | 3271 | break; |
30af77c4 | 3272 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3273 | return PLANE_CTL_TILED_X; |
b321803d | 3274 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3275 | return PLANE_CTL_TILED_Y; |
b321803d | 3276 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3277 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3278 | default: |
6156a456 | 3279 | MISSING_CASE(fb_modifier); |
70d21f0e | 3280 | } |
8cfcba41 | 3281 | |
c34ce3d1 | 3282 | return 0; |
6156a456 | 3283 | } |
70d21f0e | 3284 | |
2e881264 | 3285 | static u32 skl_plane_ctl_rotation(unsigned int rotation) |
6156a456 | 3286 | { |
3b7a5119 | 3287 | switch (rotation) { |
c2c446ad | 3288 | case DRM_MODE_ROTATE_0: |
6156a456 | 3289 | break; |
1e8df167 | 3290 | /* |
c2c446ad | 3291 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr |
1e8df167 SJ |
3292 | * while i915 HW rotation is clockwise, thats why this swapping. |
3293 | */ | |
c2c446ad | 3294 | case DRM_MODE_ROTATE_90: |
1e8df167 | 3295 | return PLANE_CTL_ROTATE_270; |
c2c446ad | 3296 | case DRM_MODE_ROTATE_180: |
c34ce3d1 | 3297 | return PLANE_CTL_ROTATE_180; |
c2c446ad | 3298 | case DRM_MODE_ROTATE_270: |
1e8df167 | 3299 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3300 | default: |
3301 | MISSING_CASE(rotation); | |
3302 | } | |
3303 | ||
c34ce3d1 | 3304 | return 0; |
6156a456 CK |
3305 | } |
3306 | ||
2e881264 VS |
3307 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
3308 | const struct intel_plane_state *plane_state) | |
46f788ba VS |
3309 | { |
3310 | struct drm_i915_private *dev_priv = | |
3311 | to_i915(plane_state->base.plane->dev); | |
3312 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3313 | unsigned int rotation = plane_state->base.rotation; | |
2e881264 | 3314 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
46f788ba VS |
3315 | u32 plane_ctl; |
3316 | ||
3317 | plane_ctl = PLANE_CTL_ENABLE; | |
3318 | ||
3319 | if (!IS_GEMINILAKE(dev_priv)) { | |
3320 | plane_ctl |= | |
3321 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3322 | PLANE_CTL_PIPE_CSC_ENABLE | | |
3323 | PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3324 | } | |
3325 | ||
3326 | plane_ctl |= skl_plane_ctl_format(fb->format->format); | |
3327 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); | |
3328 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3329 | ||
2e881264 VS |
3330 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
3331 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
3332 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
3333 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
3334 | ||
46f788ba VS |
3335 | return plane_ctl; |
3336 | } | |
3337 | ||
282dbf9b | 3338 | static void skylake_update_primary_plane(struct intel_plane *plane, |
a8d201af ML |
3339 | const struct intel_crtc_state *crtc_state, |
3340 | const struct intel_plane_state *plane_state) | |
6156a456 | 3341 | { |
282dbf9b VS |
3342 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
3343 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3344 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3345 | enum plane_id plane_id = plane->id; | |
3346 | enum pipe pipe = plane->pipe; | |
a0864d59 | 3347 | u32 plane_ctl = plane_state->ctl; |
a8d201af | 3348 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3349 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3350 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3351 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3352 | int src_x = plane_state->main.x; |
3353 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3354 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3355 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3356 | int dst_x = plane_state->base.dst.x1; | |
3357 | int dst_y = plane_state->base.dst.y1; | |
3358 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3359 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
dd584fc0 | 3360 | unsigned long irqflags; |
70d21f0e | 3361 | |
6687c906 VS |
3362 | /* Sizes are 0 based */ |
3363 | src_w--; | |
3364 | src_h--; | |
3365 | dst_w--; | |
3366 | dst_h--; | |
3367 | ||
282dbf9b | 3368 | crtc->dspaddr_offset = surf_addr; |
4c0b8a8b | 3369 | |
282dbf9b VS |
3370 | crtc->adjusted_x = src_x; |
3371 | crtc->adjusted_y = src_y; | |
2db3366b | 3372 | |
dd584fc0 VS |
3373 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3374 | ||
78587de2 | 3375 | if (IS_GEMINILAKE(dev_priv)) { |
dd584fc0 VS |
3376 | I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), |
3377 | PLANE_COLOR_PIPE_GAMMA_ENABLE | | |
3378 | PLANE_COLOR_PIPE_CSC_ENABLE | | |
3379 | PLANE_COLOR_PLANE_GAMMA_DISABLE); | |
78587de2 VS |
3380 | } |
3381 | ||
dd584fc0 VS |
3382 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); |
3383 | I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3384 | I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); | |
3385 | I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
6156a456 CK |
3386 | |
3387 | if (scaler_id >= 0) { | |
3388 | uint32_t ps_ctrl = 0; | |
3389 | ||
3390 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3391 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 | 3392 | crtc_state->scaler_state.scalers[scaler_id].mode; |
dd584fc0 VS |
3393 | I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
3394 | I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3395 | I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3396 | I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3397 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0); | |
6156a456 | 3398 | } else { |
dd584fc0 | 3399 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3400 | } |
3401 | ||
dd584fc0 VS |
3402 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), |
3403 | intel_plane_ggtt_offset(plane_state) + surf_addr); | |
70d21f0e | 3404 | |
dd584fc0 VS |
3405 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); |
3406 | ||
3407 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
70d21f0e DL |
3408 | } |
3409 | ||
282dbf9b VS |
3410 | static void skylake_disable_primary_plane(struct intel_plane *primary, |
3411 | struct intel_crtc *crtc) | |
17638cd6 | 3412 | { |
282dbf9b VS |
3413 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3414 | enum plane_id plane_id = primary->id; | |
3415 | enum pipe pipe = primary->pipe; | |
dd584fc0 VS |
3416 | unsigned long irqflags; |
3417 | ||
3418 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
62e0fb88 | 3419 | |
dd584fc0 VS |
3420 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); |
3421 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); | |
3422 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); | |
3423 | ||
3424 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3425 | } |
29b9bde6 | 3426 | |
5a21b665 DV |
3427 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3428 | { | |
3429 | struct intel_crtc *crtc; | |
3430 | ||
91c8a326 | 3431 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3432 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3433 | } | |
3434 | ||
7514747d VS |
3435 | static void intel_update_primary_planes(struct drm_device *dev) |
3436 | { | |
7514747d | 3437 | struct drm_crtc *crtc; |
96a02917 | 3438 | |
70e1e0ec | 3439 | for_each_crtc(dev, crtc) { |
11c22da6 | 3440 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3441 | struct intel_plane_state *plane_state = |
3442 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3443 | |
72259536 VS |
3444 | if (plane_state->base.visible) { |
3445 | trace_intel_update_plane(&plane->base, | |
3446 | to_intel_crtc(crtc)); | |
3447 | ||
282dbf9b | 3448 | plane->update_plane(plane, |
a8d201af ML |
3449 | to_intel_crtc_state(crtc->state), |
3450 | plane_state); | |
72259536 | 3451 | } |
73974893 ML |
3452 | } |
3453 | } | |
3454 | ||
3455 | static int | |
3456 | __intel_display_resume(struct drm_device *dev, | |
581e49fe ML |
3457 | struct drm_atomic_state *state, |
3458 | struct drm_modeset_acquire_ctx *ctx) | |
73974893 ML |
3459 | { |
3460 | struct drm_crtc_state *crtc_state; | |
3461 | struct drm_crtc *crtc; | |
3462 | int i, ret; | |
11c22da6 | 3463 | |
73974893 | 3464 | intel_modeset_setup_hw_state(dev); |
29b74b7f | 3465 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3466 | |
3467 | if (!state) | |
3468 | return 0; | |
3469 | ||
aa5e9b47 ML |
3470 | /* |
3471 | * We've duplicated the state, pointers to the old state are invalid. | |
3472 | * | |
3473 | * Don't attempt to use the old state until we commit the duplicated state. | |
3474 | */ | |
3475 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { | |
73974893 ML |
3476 | /* |
3477 | * Force recalculation even if we restore | |
3478 | * current state. With fast modeset this may not result | |
3479 | * in a modeset when the state is compatible. | |
3480 | */ | |
3481 | crtc_state->mode_changed = true; | |
96a02917 | 3482 | } |
73974893 ML |
3483 | |
3484 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
602ae835 VS |
3485 | if (!HAS_GMCH_DISPLAY(to_i915(dev))) |
3486 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
73974893 | 3487 | |
581e49fe | 3488 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
73974893 ML |
3489 | |
3490 | WARN_ON(ret == -EDEADLK); | |
3491 | return ret; | |
96a02917 VS |
3492 | } |
3493 | ||
4ac2ba2f VS |
3494 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3495 | { | |
ae98104b VS |
3496 | return intel_has_gpu_reset(dev_priv) && |
3497 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3498 | } |
3499 | ||
c033666a | 3500 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3501 | { |
73974893 ML |
3502 | struct drm_device *dev = &dev_priv->drm; |
3503 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3504 | struct drm_atomic_state *state; | |
3505 | int ret; | |
3506 | ||
73974893 ML |
3507 | /* |
3508 | * Need mode_config.mutex so that we don't | |
3509 | * trample ongoing ->detect() and whatnot. | |
3510 | */ | |
3511 | mutex_lock(&dev->mode_config.mutex); | |
3512 | drm_modeset_acquire_init(ctx, 0); | |
3513 | while (1) { | |
3514 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3515 | if (ret != -EDEADLK) | |
3516 | break; | |
3517 | ||
3518 | drm_modeset_backoff(ctx); | |
3519 | } | |
3520 | ||
3521 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3522 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3523 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3524 | return; |
3525 | ||
f98ce92f VS |
3526 | /* |
3527 | * Disabling the crtcs gracefully seems nicer. Also the | |
3528 | * g33 docs say we should at least disable all the planes. | |
3529 | */ | |
73974893 ML |
3530 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3531 | if (IS_ERR(state)) { | |
3532 | ret = PTR_ERR(state); | |
73974893 | 3533 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
1e5a15d6 | 3534 | return; |
73974893 ML |
3535 | } |
3536 | ||
3537 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3538 | if (ret) { | |
3539 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
1e5a15d6 ACO |
3540 | drm_atomic_state_put(state); |
3541 | return; | |
73974893 ML |
3542 | } |
3543 | ||
3544 | dev_priv->modeset_restore_state = state; | |
3545 | state->acquire_ctx = ctx; | |
7514747d VS |
3546 | } |
3547 | ||
c033666a | 3548 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3549 | { |
73974893 ML |
3550 | struct drm_device *dev = &dev_priv->drm; |
3551 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3552 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3553 | int ret; | |
3554 | ||
5a21b665 DV |
3555 | /* |
3556 | * Flips in the rings will be nuked by the reset, | |
3557 | * so complete all pending flips so that user space | |
3558 | * will get its events and not get stuck. | |
3559 | */ | |
3560 | intel_complete_page_flips(dev_priv); | |
3561 | ||
73974893 ML |
3562 | dev_priv->modeset_restore_state = NULL; |
3563 | ||
7514747d | 3564 | /* reset doesn't touch the display */ |
4ac2ba2f | 3565 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3566 | if (!state) { |
3567 | /* | |
3568 | * Flips in the rings have been nuked by the reset, | |
3569 | * so update the base address of all primary | |
3570 | * planes to the the last fb to make sure we're | |
3571 | * showing the correct fb after a reset. | |
3572 | * | |
3573 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3574 | * CS-based flips (which might get lost in gpu resets) any more. | |
3575 | */ | |
3576 | intel_update_primary_planes(dev); | |
3577 | } else { | |
581e49fe | 3578 | ret = __intel_display_resume(dev, state, ctx); |
522a63de ML |
3579 | if (ret) |
3580 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3581 | } | |
73974893 ML |
3582 | } else { |
3583 | /* | |
3584 | * The display has been reset as well, | |
3585 | * so need a full re-initialization. | |
3586 | */ | |
3587 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3588 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3589 | |
51f59205 | 3590 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3591 | intel_modeset_init_hw(dev); |
7514747d | 3592 | |
73974893 ML |
3593 | spin_lock_irq(&dev_priv->irq_lock); |
3594 | if (dev_priv->display.hpd_irq_setup) | |
3595 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3596 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3597 | |
581e49fe | 3598 | ret = __intel_display_resume(dev, state, ctx); |
73974893 ML |
3599 | if (ret) |
3600 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3601 | |
73974893 ML |
3602 | intel_hpd_init(dev_priv); |
3603 | } | |
7514747d | 3604 | |
0853695c CW |
3605 | if (state) |
3606 | drm_atomic_state_put(state); | |
73974893 ML |
3607 | drm_modeset_drop_locks(ctx); |
3608 | drm_modeset_acquire_fini(ctx); | |
3609 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3610 | } |
3611 | ||
8af29b0c CW |
3612 | static bool abort_flip_on_reset(struct intel_crtc *crtc) |
3613 | { | |
3614 | struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; | |
3615 | ||
8c185eca | 3616 | if (i915_reset_backoff(error)) |
8af29b0c CW |
3617 | return true; |
3618 | ||
3619 | if (crtc->reset_count != i915_reset_count(error)) | |
3620 | return true; | |
3621 | ||
3622 | return false; | |
3623 | } | |
3624 | ||
7d5e3799 CW |
3625 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3626 | { | |
5a21b665 DV |
3627 | struct drm_device *dev = crtc->dev; |
3628 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5a21b665 DV |
3629 | bool pending; |
3630 | ||
8af29b0c | 3631 | if (abort_flip_on_reset(intel_crtc)) |
5a21b665 DV |
3632 | return false; |
3633 | ||
3634 | spin_lock_irq(&dev->event_lock); | |
3635 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3636 | spin_unlock_irq(&dev->event_lock); | |
3637 | ||
3638 | return pending; | |
7d5e3799 CW |
3639 | } |
3640 | ||
bfd16b2a ML |
3641 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3642 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3643 | { |
6315b5d3 | 3644 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3645 | struct intel_crtc_state *pipe_config = |
3646 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3647 | |
bfd16b2a ML |
3648 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3649 | crtc->base.mode = crtc->base.state->mode; | |
3650 | ||
e30e8f75 GP |
3651 | /* |
3652 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3653 | * that in compute_mode_changes we check the native mode (not the pfit | |
3654 | * mode) to see if we can flip rather than do a full mode set. In the | |
3655 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3656 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3657 | * sized surface. | |
e30e8f75 GP |
3658 | */ |
3659 | ||
e30e8f75 | 3660 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3661 | ((pipe_config->pipe_src_w - 1) << 16) | |
3662 | (pipe_config->pipe_src_h - 1)); | |
3663 | ||
3664 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3665 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3666 | skl_detach_scalers(crtc); |
3667 | ||
3668 | if (pipe_config->pch_pfit.enabled) | |
3669 | skylake_pfit_enable(crtc); | |
6e266956 | 3670 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3671 | if (pipe_config->pch_pfit.enabled) |
3672 | ironlake_pfit_enable(crtc); | |
3673 | else if (old_crtc_state->pch_pfit.enabled) | |
3674 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3675 | } |
e30e8f75 GP |
3676 | } |
3677 | ||
4cbe4b2b | 3678 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 3679 | { |
4cbe4b2b | 3680 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3681 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3682 | int pipe = crtc->pipe; |
f0f59a00 VS |
3683 | i915_reg_t reg; |
3684 | u32 temp; | |
5e84e1a4 ZW |
3685 | |
3686 | /* enable normal train */ | |
3687 | reg = FDI_TX_CTL(pipe); | |
3688 | temp = I915_READ(reg); | |
fd6b8f43 | 3689 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3690 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3691 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3692 | } else { |
3693 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3694 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3695 | } |
5e84e1a4 ZW |
3696 | I915_WRITE(reg, temp); |
3697 | ||
3698 | reg = FDI_RX_CTL(pipe); | |
3699 | temp = I915_READ(reg); | |
6e266956 | 3700 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3701 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3702 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3703 | } else { | |
3704 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3705 | temp |= FDI_LINK_TRAIN_NONE; | |
3706 | } | |
3707 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3708 | ||
3709 | /* wait one idle pattern time */ | |
3710 | POSTING_READ(reg); | |
3711 | udelay(1000); | |
357555c0 JB |
3712 | |
3713 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3714 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3715 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3716 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3717 | } |
3718 | ||
8db9d77b | 3719 | /* The FDI link training functions for ILK/Ibexpeak. */ |
dc4a1094 ACO |
3720 | static void ironlake_fdi_link_train(struct intel_crtc *crtc, |
3721 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3722 | { |
4cbe4b2b | 3723 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3724 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3725 | int pipe = crtc->pipe; |
f0f59a00 VS |
3726 | i915_reg_t reg; |
3727 | u32 temp, tries; | |
8db9d77b | 3728 | |
1c8562f6 | 3729 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3730 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3731 | |
e1a44743 AJ |
3732 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3733 | for train result */ | |
5eddb70b CW |
3734 | reg = FDI_RX_IMR(pipe); |
3735 | temp = I915_READ(reg); | |
e1a44743 AJ |
3736 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3737 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3738 | I915_WRITE(reg, temp); |
3739 | I915_READ(reg); | |
e1a44743 AJ |
3740 | udelay(150); |
3741 | ||
8db9d77b | 3742 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3743 | reg = FDI_TX_CTL(pipe); |
3744 | temp = I915_READ(reg); | |
627eb5a3 | 3745 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3746 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3747 | temp &= ~FDI_LINK_TRAIN_NONE; |
3748 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3749 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3750 | |
5eddb70b CW |
3751 | reg = FDI_RX_CTL(pipe); |
3752 | temp = I915_READ(reg); | |
8db9d77b ZW |
3753 | temp &= ~FDI_LINK_TRAIN_NONE; |
3754 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3755 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3756 | ||
3757 | POSTING_READ(reg); | |
8db9d77b ZW |
3758 | udelay(150); |
3759 | ||
5b2adf89 | 3760 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3761 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3762 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3763 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3764 | |
5eddb70b | 3765 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3766 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3767 | temp = I915_READ(reg); |
8db9d77b ZW |
3768 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3769 | ||
3770 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3771 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3772 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3773 | break; |
3774 | } | |
8db9d77b | 3775 | } |
e1a44743 | 3776 | if (tries == 5) |
5eddb70b | 3777 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3778 | |
3779 | /* Train 2 */ | |
5eddb70b CW |
3780 | reg = FDI_TX_CTL(pipe); |
3781 | temp = I915_READ(reg); | |
8db9d77b ZW |
3782 | temp &= ~FDI_LINK_TRAIN_NONE; |
3783 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3784 | I915_WRITE(reg, temp); |
8db9d77b | 3785 | |
5eddb70b CW |
3786 | reg = FDI_RX_CTL(pipe); |
3787 | temp = I915_READ(reg); | |
8db9d77b ZW |
3788 | temp &= ~FDI_LINK_TRAIN_NONE; |
3789 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3790 | I915_WRITE(reg, temp); |
8db9d77b | 3791 | |
5eddb70b CW |
3792 | POSTING_READ(reg); |
3793 | udelay(150); | |
8db9d77b | 3794 | |
5eddb70b | 3795 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3796 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3797 | temp = I915_READ(reg); |
8db9d77b ZW |
3798 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3799 | ||
3800 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3801 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3802 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3803 | break; | |
3804 | } | |
8db9d77b | 3805 | } |
e1a44743 | 3806 | if (tries == 5) |
5eddb70b | 3807 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3808 | |
3809 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3810 | |
8db9d77b ZW |
3811 | } |
3812 | ||
0206e353 | 3813 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3814 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3815 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3816 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3817 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3818 | }; | |
3819 | ||
3820 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
3821 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
3822 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3823 | { |
4cbe4b2b | 3824 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3825 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3826 | int pipe = crtc->pipe; |
f0f59a00 VS |
3827 | i915_reg_t reg; |
3828 | u32 temp, i, retry; | |
8db9d77b | 3829 | |
e1a44743 AJ |
3830 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3831 | for train result */ | |
5eddb70b CW |
3832 | reg = FDI_RX_IMR(pipe); |
3833 | temp = I915_READ(reg); | |
e1a44743 AJ |
3834 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3835 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3836 | I915_WRITE(reg, temp); |
3837 | ||
3838 | POSTING_READ(reg); | |
e1a44743 AJ |
3839 | udelay(150); |
3840 | ||
8db9d77b | 3841 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3842 | reg = FDI_TX_CTL(pipe); |
3843 | temp = I915_READ(reg); | |
627eb5a3 | 3844 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3845 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3846 | temp &= ~FDI_LINK_TRAIN_NONE; |
3847 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3848 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3849 | /* SNB-B */ | |
3850 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3851 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3852 | |
d74cf324 DV |
3853 | I915_WRITE(FDI_RX_MISC(pipe), |
3854 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3855 | ||
5eddb70b CW |
3856 | reg = FDI_RX_CTL(pipe); |
3857 | temp = I915_READ(reg); | |
6e266956 | 3858 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3859 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3860 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3861 | } else { | |
3862 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3863 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3864 | } | |
5eddb70b CW |
3865 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3866 | ||
3867 | POSTING_READ(reg); | |
8db9d77b ZW |
3868 | udelay(150); |
3869 | ||
0206e353 | 3870 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3871 | reg = FDI_TX_CTL(pipe); |
3872 | temp = I915_READ(reg); | |
8db9d77b ZW |
3873 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3874 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3875 | I915_WRITE(reg, temp); |
3876 | ||
3877 | POSTING_READ(reg); | |
8db9d77b ZW |
3878 | udelay(500); |
3879 | ||
fa37d39e SP |
3880 | for (retry = 0; retry < 5; retry++) { |
3881 | reg = FDI_RX_IIR(pipe); | |
3882 | temp = I915_READ(reg); | |
3883 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3884 | if (temp & FDI_RX_BIT_LOCK) { | |
3885 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3886 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3887 | break; | |
3888 | } | |
3889 | udelay(50); | |
8db9d77b | 3890 | } |
fa37d39e SP |
3891 | if (retry < 5) |
3892 | break; | |
8db9d77b ZW |
3893 | } |
3894 | if (i == 4) | |
5eddb70b | 3895 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3896 | |
3897 | /* Train 2 */ | |
5eddb70b CW |
3898 | reg = FDI_TX_CTL(pipe); |
3899 | temp = I915_READ(reg); | |
8db9d77b ZW |
3900 | temp &= ~FDI_LINK_TRAIN_NONE; |
3901 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3902 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3903 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3904 | /* SNB-B */ | |
3905 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3906 | } | |
5eddb70b | 3907 | I915_WRITE(reg, temp); |
8db9d77b | 3908 | |
5eddb70b CW |
3909 | reg = FDI_RX_CTL(pipe); |
3910 | temp = I915_READ(reg); | |
6e266956 | 3911 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3912 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3913 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3914 | } else { | |
3915 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3916 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3917 | } | |
5eddb70b CW |
3918 | I915_WRITE(reg, temp); |
3919 | ||
3920 | POSTING_READ(reg); | |
8db9d77b ZW |
3921 | udelay(150); |
3922 | ||
0206e353 | 3923 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3924 | reg = FDI_TX_CTL(pipe); |
3925 | temp = I915_READ(reg); | |
8db9d77b ZW |
3926 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3927 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3928 | I915_WRITE(reg, temp); |
3929 | ||
3930 | POSTING_READ(reg); | |
8db9d77b ZW |
3931 | udelay(500); |
3932 | ||
fa37d39e SP |
3933 | for (retry = 0; retry < 5; retry++) { |
3934 | reg = FDI_RX_IIR(pipe); | |
3935 | temp = I915_READ(reg); | |
3936 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3937 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3938 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3939 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3940 | break; | |
3941 | } | |
3942 | udelay(50); | |
8db9d77b | 3943 | } |
fa37d39e SP |
3944 | if (retry < 5) |
3945 | break; | |
8db9d77b ZW |
3946 | } |
3947 | if (i == 4) | |
5eddb70b | 3948 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3949 | |
3950 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3951 | } | |
3952 | ||
357555c0 | 3953 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
3954 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
3955 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 3956 | { |
4cbe4b2b | 3957 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3958 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3959 | int pipe = crtc->pipe; |
f0f59a00 VS |
3960 | i915_reg_t reg; |
3961 | u32 temp, i, j; | |
357555c0 JB |
3962 | |
3963 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3964 | for train result */ | |
3965 | reg = FDI_RX_IMR(pipe); | |
3966 | temp = I915_READ(reg); | |
3967 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3968 | temp &= ~FDI_RX_BIT_LOCK; | |
3969 | I915_WRITE(reg, temp); | |
3970 | ||
3971 | POSTING_READ(reg); | |
3972 | udelay(150); | |
3973 | ||
01a415fd DV |
3974 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3975 | I915_READ(FDI_RX_IIR(pipe))); | |
3976 | ||
139ccd3f JB |
3977 | /* Try each vswing and preemphasis setting twice before moving on */ |
3978 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3979 | /* disable first in case we need to retry */ | |
3980 | reg = FDI_TX_CTL(pipe); | |
3981 | temp = I915_READ(reg); | |
3982 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3983 | temp &= ~FDI_TX_ENABLE; | |
3984 | I915_WRITE(reg, temp); | |
357555c0 | 3985 | |
139ccd3f JB |
3986 | reg = FDI_RX_CTL(pipe); |
3987 | temp = I915_READ(reg); | |
3988 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3989 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3990 | temp &= ~FDI_RX_ENABLE; | |
3991 | I915_WRITE(reg, temp); | |
357555c0 | 3992 | |
139ccd3f | 3993 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3994 | reg = FDI_TX_CTL(pipe); |
3995 | temp = I915_READ(reg); | |
139ccd3f | 3996 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3997 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 3998 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3999 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4000 | temp |= snb_b_fdi_train_param[j/2]; |
4001 | temp |= FDI_COMPOSITE_SYNC; | |
4002 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4003 | |
139ccd3f JB |
4004 | I915_WRITE(FDI_RX_MISC(pipe), |
4005 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4006 | |
139ccd3f | 4007 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4008 | temp = I915_READ(reg); |
139ccd3f JB |
4009 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4010 | temp |= FDI_COMPOSITE_SYNC; | |
4011 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4012 | |
139ccd3f JB |
4013 | POSTING_READ(reg); |
4014 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4015 | |
139ccd3f JB |
4016 | for (i = 0; i < 4; i++) { |
4017 | reg = FDI_RX_IIR(pipe); | |
4018 | temp = I915_READ(reg); | |
4019 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4020 | |
139ccd3f JB |
4021 | if (temp & FDI_RX_BIT_LOCK || |
4022 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4023 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4024 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4025 | i); | |
4026 | break; | |
4027 | } | |
4028 | udelay(1); /* should be 0.5us */ | |
4029 | } | |
4030 | if (i == 4) { | |
4031 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4032 | continue; | |
4033 | } | |
357555c0 | 4034 | |
139ccd3f | 4035 | /* Train 2 */ |
357555c0 JB |
4036 | reg = FDI_TX_CTL(pipe); |
4037 | temp = I915_READ(reg); | |
139ccd3f JB |
4038 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4039 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4040 | I915_WRITE(reg, temp); | |
4041 | ||
4042 | reg = FDI_RX_CTL(pipe); | |
4043 | temp = I915_READ(reg); | |
4044 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4045 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4046 | I915_WRITE(reg, temp); |
4047 | ||
4048 | POSTING_READ(reg); | |
139ccd3f | 4049 | udelay(2); /* should be 1.5us */ |
357555c0 | 4050 | |
139ccd3f JB |
4051 | for (i = 0; i < 4; i++) { |
4052 | reg = FDI_RX_IIR(pipe); | |
4053 | temp = I915_READ(reg); | |
4054 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4055 | |
139ccd3f JB |
4056 | if (temp & FDI_RX_SYMBOL_LOCK || |
4057 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4058 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4059 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4060 | i); | |
4061 | goto train_done; | |
4062 | } | |
4063 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4064 | } |
139ccd3f JB |
4065 | if (i == 4) |
4066 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4067 | } |
357555c0 | 4068 | |
139ccd3f | 4069 | train_done: |
357555c0 JB |
4070 | DRM_DEBUG_KMS("FDI train done.\n"); |
4071 | } | |
4072 | ||
88cefb6c | 4073 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4074 | { |
88cefb6c | 4075 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4076 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4077 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4078 | i915_reg_t reg; |
4079 | u32 temp; | |
c64e311e | 4080 | |
c98e9dcf | 4081 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4082 | reg = FDI_RX_CTL(pipe); |
4083 | temp = I915_READ(reg); | |
627eb5a3 | 4084 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4085 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4086 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4087 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4088 | ||
4089 | POSTING_READ(reg); | |
c98e9dcf JB |
4090 | udelay(200); |
4091 | ||
4092 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4093 | temp = I915_READ(reg); |
4094 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4095 | ||
4096 | POSTING_READ(reg); | |
c98e9dcf JB |
4097 | udelay(200); |
4098 | ||
20749730 PZ |
4099 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4100 | reg = FDI_TX_CTL(pipe); | |
4101 | temp = I915_READ(reg); | |
4102 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4103 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4104 | |
20749730 PZ |
4105 | POSTING_READ(reg); |
4106 | udelay(100); | |
6be4a607 | 4107 | } |
0e23b99d JB |
4108 | } |
4109 | ||
88cefb6c DV |
4110 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4111 | { | |
4112 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4113 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4114 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4115 | i915_reg_t reg; |
4116 | u32 temp; | |
88cefb6c DV |
4117 | |
4118 | /* Switch from PCDclk to Rawclk */ | |
4119 | reg = FDI_RX_CTL(pipe); | |
4120 | temp = I915_READ(reg); | |
4121 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4122 | ||
4123 | /* Disable CPU FDI TX PLL */ | |
4124 | reg = FDI_TX_CTL(pipe); | |
4125 | temp = I915_READ(reg); | |
4126 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4127 | ||
4128 | POSTING_READ(reg); | |
4129 | udelay(100); | |
4130 | ||
4131 | reg = FDI_RX_CTL(pipe); | |
4132 | temp = I915_READ(reg); | |
4133 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4134 | ||
4135 | /* Wait for the clocks to turn off. */ | |
4136 | POSTING_READ(reg); | |
4137 | udelay(100); | |
4138 | } | |
4139 | ||
0fc932b8 JB |
4140 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4141 | { | |
4142 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4143 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4144 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4145 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4146 | i915_reg_t reg; |
4147 | u32 temp; | |
0fc932b8 JB |
4148 | |
4149 | /* disable CPU FDI tx and PCH FDI rx */ | |
4150 | reg = FDI_TX_CTL(pipe); | |
4151 | temp = I915_READ(reg); | |
4152 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4153 | POSTING_READ(reg); | |
4154 | ||
4155 | reg = FDI_RX_CTL(pipe); | |
4156 | temp = I915_READ(reg); | |
4157 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4158 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4159 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4160 | ||
4161 | POSTING_READ(reg); | |
4162 | udelay(100); | |
4163 | ||
4164 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4165 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4166 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4167 | |
4168 | /* still set train pattern 1 */ | |
4169 | reg = FDI_TX_CTL(pipe); | |
4170 | temp = I915_READ(reg); | |
4171 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4172 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4173 | I915_WRITE(reg, temp); | |
4174 | ||
4175 | reg = FDI_RX_CTL(pipe); | |
4176 | temp = I915_READ(reg); | |
6e266956 | 4177 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4178 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4179 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4180 | } else { | |
4181 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4182 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4183 | } | |
4184 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4185 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4186 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4187 | I915_WRITE(reg, temp); |
4188 | ||
4189 | POSTING_READ(reg); | |
4190 | udelay(100); | |
4191 | } | |
4192 | ||
49d73912 | 4193 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 CW |
4194 | { |
4195 | struct intel_crtc *crtc; | |
4196 | ||
4197 | /* Note that we don't need to be called with mode_config.lock here | |
4198 | * as our list of CRTC objects is static for the lifetime of the | |
4199 | * device and so cannot disappear as we iterate. Similarly, we can | |
4200 | * happily treat the predicates as racy, atomic checks as userspace | |
4201 | * cannot claim and pin a new fb without at least acquring the | |
4202 | * struct_mutex and so serialising with us. | |
4203 | */ | |
49d73912 | 4204 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
5dce5b93 CW |
4205 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4206 | continue; | |
4207 | ||
5a21b665 | 4208 | if (crtc->flip_work) |
0f0f74bc | 4209 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
5dce5b93 CW |
4210 | |
4211 | return true; | |
4212 | } | |
4213 | ||
4214 | return false; | |
4215 | } | |
4216 | ||
5a21b665 | 4217 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4218 | { |
4219 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4220 | struct intel_flip_work *work = intel_crtc->flip_work; |
4221 | ||
4222 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4223 | |
4224 | if (work->event) | |
560ce1dc | 4225 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4226 | |
4227 | drm_crtc_vblank_put(&intel_crtc->base); | |
4228 | ||
5a21b665 | 4229 | wake_up_all(&dev_priv->pending_flip_queue); |
5a21b665 DV |
4230 | trace_i915_flip_complete(intel_crtc->plane, |
4231 | work->pending_flip_obj); | |
05c41f92 AR |
4232 | |
4233 | queue_work(dev_priv->wq, &work->unpin_work); | |
d6bbafa1 CW |
4234 | } |
4235 | ||
5008e874 | 4236 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4237 | { |
0f91128d | 4238 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4239 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4240 | long ret; |
e6c3a2a6 | 4241 | |
2c10d571 | 4242 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4243 | |
4244 | ret = wait_event_interruptible_timeout( | |
4245 | dev_priv->pending_flip_queue, | |
4246 | !intel_crtc_has_pending_flip(crtc), | |
4247 | 60*HZ); | |
4248 | ||
4249 | if (ret < 0) | |
4250 | return ret; | |
4251 | ||
5a21b665 DV |
4252 | if (ret == 0) { |
4253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4254 | struct intel_flip_work *work; | |
4255 | ||
4256 | spin_lock_irq(&dev->event_lock); | |
4257 | work = intel_crtc->flip_work; | |
4258 | if (work && !is_mmio_work(work)) { | |
4259 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4260 | page_flip_completed(intel_crtc); | |
4261 | } | |
4262 | spin_unlock_irq(&dev->event_lock); | |
4263 | } | |
5bb61643 | 4264 | |
5008e874 | 4265 | return 0; |
e6c3a2a6 CW |
4266 | } |
4267 | ||
b7076546 | 4268 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4269 | { |
4270 | u32 temp; | |
4271 | ||
4272 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4273 | ||
4274 | mutex_lock(&dev_priv->sb_lock); | |
4275 | ||
4276 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4277 | temp |= SBI_SSCCTL_DISABLE; | |
4278 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4279 | ||
4280 | mutex_unlock(&dev_priv->sb_lock); | |
4281 | } | |
4282 | ||
e615efe4 | 4283 | /* Program iCLKIP clock to the desired frequency */ |
0dcdc382 | 4284 | static void lpt_program_iclkip(struct intel_crtc *crtc) |
e615efe4 | 4285 | { |
0dcdc382 ACO |
4286 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4287 | int clock = crtc->config->base.adjusted_mode.crtc_clock; | |
e615efe4 ED |
4288 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4289 | u32 temp; | |
4290 | ||
060f02d8 | 4291 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4292 | |
64b46a06 VS |
4293 | /* The iCLK virtual clock root frequency is in MHz, |
4294 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4295 | * divisors, it is necessary to divide one by another, so we | |
4296 | * convert the virtual clock precision to KHz here for higher | |
4297 | * precision. | |
4298 | */ | |
4299 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4300 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4301 | u32 iclk_pi_range = 64; | |
64b46a06 | 4302 | u32 desired_divisor; |
e615efe4 | 4303 | |
64b46a06 VS |
4304 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4305 | clock << auxdiv); | |
4306 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4307 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4308 | |
64b46a06 VS |
4309 | /* |
4310 | * Near 20MHz is a corner case which is | |
4311 | * out of range for the 7-bit divisor | |
4312 | */ | |
4313 | if (divsel <= 0x7f) | |
4314 | break; | |
e615efe4 ED |
4315 | } |
4316 | ||
4317 | /* This should not happen with any sane values */ | |
4318 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4319 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4320 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4321 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4322 | ||
4323 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4324 | clock, |
e615efe4 ED |
4325 | auxdiv, |
4326 | divsel, | |
4327 | phasedir, | |
4328 | phaseinc); | |
4329 | ||
060f02d8 VS |
4330 | mutex_lock(&dev_priv->sb_lock); |
4331 | ||
e615efe4 | 4332 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4333 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4334 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4335 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4336 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4337 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4338 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4339 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4340 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4341 | |
4342 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4343 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4344 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4345 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4346 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4347 | |
4348 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4349 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4350 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4351 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4352 | |
060f02d8 VS |
4353 | mutex_unlock(&dev_priv->sb_lock); |
4354 | ||
e615efe4 ED |
4355 | /* Wait for initialization time */ |
4356 | udelay(24); | |
4357 | ||
4358 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4359 | } | |
4360 | ||
8802e5b6 VS |
4361 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4362 | { | |
4363 | u32 divsel, phaseinc, auxdiv; | |
4364 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4365 | u32 iclk_pi_range = 64; | |
4366 | u32 desired_divisor; | |
4367 | u32 temp; | |
4368 | ||
4369 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4370 | return 0; | |
4371 | ||
4372 | mutex_lock(&dev_priv->sb_lock); | |
4373 | ||
4374 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4375 | if (temp & SBI_SSCCTL_DISABLE) { | |
4376 | mutex_unlock(&dev_priv->sb_lock); | |
4377 | return 0; | |
4378 | } | |
4379 | ||
4380 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4381 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4382 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4383 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4384 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4385 | ||
4386 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4387 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4388 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4389 | ||
4390 | mutex_unlock(&dev_priv->sb_lock); | |
4391 | ||
4392 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4393 | ||
4394 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4395 | desired_divisor << auxdiv); | |
4396 | } | |
4397 | ||
275f01b2 DV |
4398 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4399 | enum pipe pch_transcoder) | |
4400 | { | |
4401 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4402 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4403 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4404 | |
4405 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4406 | I915_READ(HTOTAL(cpu_transcoder))); | |
4407 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4408 | I915_READ(HBLANK(cpu_transcoder))); | |
4409 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4410 | I915_READ(HSYNC(cpu_transcoder))); | |
4411 | ||
4412 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4413 | I915_READ(VTOTAL(cpu_transcoder))); | |
4414 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4415 | I915_READ(VBLANK(cpu_transcoder))); | |
4416 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4417 | I915_READ(VSYNC(cpu_transcoder))); | |
4418 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4419 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4420 | } | |
4421 | ||
003632d9 | 4422 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4423 | { |
fac5e23e | 4424 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4425 | uint32_t temp; |
4426 | ||
4427 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4428 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4429 | return; |
4430 | ||
4431 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4432 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4433 | ||
003632d9 ACO |
4434 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4435 | if (enable) | |
4436 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4437 | ||
4438 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4439 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4440 | POSTING_READ(SOUTH_CHICKEN1); | |
4441 | } | |
4442 | ||
4443 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4444 | { | |
4445 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4446 | |
4447 | switch (intel_crtc->pipe) { | |
4448 | case PIPE_A: | |
4449 | break; | |
4450 | case PIPE_B: | |
6e3c9717 | 4451 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4452 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4453 | else |
003632d9 | 4454 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4455 | |
4456 | break; | |
4457 | case PIPE_C: | |
003632d9 | 4458 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4459 | |
4460 | break; | |
4461 | default: | |
4462 | BUG(); | |
4463 | } | |
4464 | } | |
4465 | ||
c48b5305 VS |
4466 | /* Return which DP Port should be selected for Transcoder DP control */ |
4467 | static enum port | |
4cbe4b2b | 4468 | intel_trans_dp_port_sel(struct intel_crtc *crtc) |
c48b5305 | 4469 | { |
4cbe4b2b | 4470 | struct drm_device *dev = crtc->base.dev; |
c48b5305 VS |
4471 | struct intel_encoder *encoder; |
4472 | ||
4cbe4b2b | 4473 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
cca0502b | 4474 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4475 | encoder->type == INTEL_OUTPUT_EDP) |
4476 | return enc_to_dig_port(&encoder->base)->port; | |
4477 | } | |
4478 | ||
4479 | return -1; | |
4480 | } | |
4481 | ||
f67a559d JB |
4482 | /* |
4483 | * Enable PCH resources required for PCH ports: | |
4484 | * - PCH PLLs | |
4485 | * - FDI training & RX/TX | |
4486 | * - update transcoder timings | |
4487 | * - DP transcoding bits | |
4488 | * - transcoder | |
4489 | */ | |
2ce42273 | 4490 | static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) |
0e23b99d | 4491 | { |
2ce42273 | 4492 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
4cbe4b2b | 4493 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4494 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4495 | int pipe = crtc->pipe; |
f0f59a00 | 4496 | u32 temp; |
2c07245f | 4497 | |
ab9412ba | 4498 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4499 | |
fd6b8f43 | 4500 | if (IS_IVYBRIDGE(dev_priv)) |
4cbe4b2b | 4501 | ivybridge_update_fdi_bc_bifurcation(crtc); |
1fbc0d78 | 4502 | |
cd986abb DV |
4503 | /* Write the TU size bits before fdi link training, so that error |
4504 | * detection works. */ | |
4505 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4506 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4507 | ||
c98e9dcf | 4508 | /* For PCH output, training FDI link */ |
dc4a1094 | 4509 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 4510 | |
3ad8a208 DV |
4511 | /* We need to program the right clock selection before writing the pixel |
4512 | * mutliplier into the DPLL. */ | |
6e266956 | 4513 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4514 | u32 sel; |
4b645f14 | 4515 | |
c98e9dcf | 4516 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4517 | temp |= TRANS_DPLL_ENABLE(pipe); |
4518 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 4519 | if (crtc_state->shared_dpll == |
8106ddbd | 4520 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
4521 | temp |= sel; |
4522 | else | |
4523 | temp &= ~sel; | |
c98e9dcf | 4524 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4525 | } |
5eddb70b | 4526 | |
3ad8a208 DV |
4527 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4528 | * transcoder, and we actually should do this to not upset any PCH | |
4529 | * transcoder that already use the clock when we share it. | |
4530 | * | |
4531 | * Note that enable_shared_dpll tries to do the right thing, but | |
4532 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4533 | * the right LVDS enable sequence. */ | |
4cbe4b2b | 4534 | intel_enable_shared_dpll(crtc); |
3ad8a208 | 4535 | |
d9b6cb56 JB |
4536 | /* set transcoder timing, panel must allow it */ |
4537 | assert_panel_unlocked(dev_priv, pipe); | |
4cbe4b2b | 4538 | ironlake_pch_transcoder_set_timings(crtc, pipe); |
8db9d77b | 4539 | |
303b81e0 | 4540 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4541 | |
c98e9dcf | 4542 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 4543 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 4544 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 4545 | const struct drm_display_mode *adjusted_mode = |
2ce42273 | 4546 | &crtc_state->base.adjusted_mode; |
dfd07d72 | 4547 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4548 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4549 | temp = I915_READ(reg); |
4550 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4551 | TRANS_DP_SYNC_MASK | |
4552 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4553 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4554 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4555 | |
9c4edaee | 4556 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4557 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4558 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4559 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4560 | |
4561 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4562 | case PORT_B: |
5eddb70b | 4563 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4564 | break; |
c48b5305 | 4565 | case PORT_C: |
5eddb70b | 4566 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4567 | break; |
c48b5305 | 4568 | case PORT_D: |
5eddb70b | 4569 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4570 | break; |
4571 | default: | |
e95d41e1 | 4572 | BUG(); |
32f9d658 | 4573 | } |
2c07245f | 4574 | |
5eddb70b | 4575 | I915_WRITE(reg, temp); |
6be4a607 | 4576 | } |
b52eb4dc | 4577 | |
b8a4f404 | 4578 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4579 | } |
4580 | ||
2ce42273 | 4581 | static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 4582 | { |
2ce42273 | 4583 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
0dcdc382 | 4584 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 4585 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 4586 | |
ab9412ba | 4587 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4588 | |
8c52b5e8 | 4589 | lpt_program_iclkip(crtc); |
1507e5bd | 4590 | |
0540e488 | 4591 | /* Set transcoder timing. */ |
0dcdc382 | 4592 | ironlake_pch_transcoder_set_timings(crtc, PIPE_A); |
1507e5bd | 4593 | |
937bb610 | 4594 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4595 | } |
4596 | ||
a1520318 | 4597 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4598 | { |
fac5e23e | 4599 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4600 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4601 | u32 temp; |
4602 | ||
4603 | temp = I915_READ(dslreg); | |
4604 | udelay(500); | |
4605 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4606 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4607 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4608 | } |
4609 | } | |
4610 | ||
86adf9d7 ML |
4611 | static int |
4612 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4613 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4614 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4615 | { |
86adf9d7 ML |
4616 | struct intel_crtc_scaler_state *scaler_state = |
4617 | &crtc_state->scaler_state; | |
4618 | struct intel_crtc *intel_crtc = | |
4619 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4620 | int need_scaling; |
6156a456 | 4621 | |
bd2ef25d | 4622 | need_scaling = drm_rotation_90_or_270(rotation) ? |
6156a456 CK |
4623 | (src_h != dst_w || src_w != dst_h): |
4624 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4625 | |
4626 | /* | |
4627 | * if plane is being disabled or scaler is no more required or force detach | |
4628 | * - free scaler binded to this plane/crtc | |
4629 | * - in order to do this, update crtc->scaler_usage | |
4630 | * | |
4631 | * Here scaler state in crtc_state is set free so that | |
4632 | * scaler can be assigned to other user. Actual register | |
4633 | * update to free the scaler is done in plane/panel-fit programming. | |
4634 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4635 | */ | |
86adf9d7 | 4636 | if (force_detach || !need_scaling) { |
a1b2278e | 4637 | if (*scaler_id >= 0) { |
86adf9d7 | 4638 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4639 | scaler_state->scalers[*scaler_id].in_use = 0; |
4640 | ||
86adf9d7 ML |
4641 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4642 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4643 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4644 | scaler_state->scaler_users); |
4645 | *scaler_id = -1; | |
4646 | } | |
4647 | return 0; | |
4648 | } | |
4649 | ||
4650 | /* range checks */ | |
4651 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4652 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4653 | ||
4654 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4655 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4656 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4657 | "size is out of scaler range\n", |
86adf9d7 | 4658 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4659 | return -EINVAL; |
4660 | } | |
4661 | ||
86adf9d7 ML |
4662 | /* mark this plane as a scaler user in crtc_state */ |
4663 | scaler_state->scaler_users |= (1 << scaler_user); | |
4664 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4665 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4666 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4667 | scaler_state->scaler_users); | |
4668 | ||
4669 | return 0; | |
4670 | } | |
4671 | ||
4672 | /** | |
4673 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4674 | * | |
4675 | * @state: crtc's scaler state | |
86adf9d7 ML |
4676 | * |
4677 | * Return | |
4678 | * 0 - scaler_usage updated successfully | |
4679 | * error - requested scaling cannot be supported or other error condition | |
4680 | */ | |
e435d6e5 | 4681 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4682 | { |
7c5f93b0 | 4683 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4684 | |
e435d6e5 | 4685 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
c2c446ad | 4686 | &state->scaler_state.scaler_id, DRM_MODE_ROTATE_0, |
86adf9d7 | 4687 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4688 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4689 | } |
4690 | ||
4691 | /** | |
4692 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4693 | * | |
4694 | * @state: crtc's scaler state | |
86adf9d7 ML |
4695 | * @plane_state: atomic plane state to update |
4696 | * | |
4697 | * Return | |
4698 | * 0 - scaler_usage updated successfully | |
4699 | * error - requested scaling cannot be supported or other error condition | |
4700 | */ | |
da20eabd ML |
4701 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4702 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4703 | { |
4704 | ||
da20eabd ML |
4705 | struct intel_plane *intel_plane = |
4706 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4707 | struct drm_framebuffer *fb = plane_state->base.fb; |
4708 | int ret; | |
4709 | ||
936e71e3 | 4710 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4711 | |
86adf9d7 ML |
4712 | ret = skl_update_scaler(crtc_state, force_detach, |
4713 | drm_plane_index(&intel_plane->base), | |
4714 | &plane_state->scaler_id, | |
4715 | plane_state->base.rotation, | |
936e71e3 VS |
4716 | drm_rect_width(&plane_state->base.src) >> 16, |
4717 | drm_rect_height(&plane_state->base.src) >> 16, | |
4718 | drm_rect_width(&plane_state->base.dst), | |
4719 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4720 | |
4721 | if (ret || plane_state->scaler_id < 0) | |
4722 | return ret; | |
4723 | ||
a1b2278e | 4724 | /* check colorkey */ |
818ed961 | 4725 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4726 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4727 | intel_plane->base.base.id, | |
4728 | intel_plane->base.name); | |
a1b2278e CK |
4729 | return -EINVAL; |
4730 | } | |
4731 | ||
4732 | /* Check src format */ | |
438b74a5 | 4733 | switch (fb->format->format) { |
86adf9d7 ML |
4734 | case DRM_FORMAT_RGB565: |
4735 | case DRM_FORMAT_XBGR8888: | |
4736 | case DRM_FORMAT_XRGB8888: | |
4737 | case DRM_FORMAT_ABGR8888: | |
4738 | case DRM_FORMAT_ARGB8888: | |
4739 | case DRM_FORMAT_XRGB2101010: | |
4740 | case DRM_FORMAT_XBGR2101010: | |
4741 | case DRM_FORMAT_YUYV: | |
4742 | case DRM_FORMAT_YVYU: | |
4743 | case DRM_FORMAT_UYVY: | |
4744 | case DRM_FORMAT_VYUY: | |
4745 | break; | |
4746 | default: | |
72660ce0 VS |
4747 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4748 | intel_plane->base.base.id, intel_plane->base.name, | |
438b74a5 | 4749 | fb->base.id, fb->format->format); |
86adf9d7 | 4750 | return -EINVAL; |
a1b2278e CK |
4751 | } |
4752 | ||
a1b2278e CK |
4753 | return 0; |
4754 | } | |
4755 | ||
e435d6e5 ML |
4756 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4757 | { | |
4758 | int i; | |
4759 | ||
4760 | for (i = 0; i < crtc->num_scalers; i++) | |
4761 | skl_detach_scaler(crtc, i); | |
4762 | } | |
4763 | ||
4764 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4765 | { |
4766 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4767 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4768 | int pipe = crtc->pipe; |
a1b2278e CK |
4769 | struct intel_crtc_scaler_state *scaler_state = |
4770 | &crtc->config->scaler_state; | |
4771 | ||
6e3c9717 | 4772 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4773 | int id; |
4774 | ||
c3f8ad57 | 4775 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) |
a1b2278e | 4776 | return; |
a1b2278e CK |
4777 | |
4778 | id = scaler_state->scaler_id; | |
4779 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4780 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4781 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4782 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4783 | } |
4784 | } | |
4785 | ||
b074cec8 JB |
4786 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4787 | { | |
4788 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4789 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4790 | int pipe = crtc->pipe; |
4791 | ||
6e3c9717 | 4792 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4793 | /* Force use of hard-coded filter coefficients |
4794 | * as some pre-programmed values are broken, | |
4795 | * e.g. x201. | |
4796 | */ | |
fd6b8f43 | 4797 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4798 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4799 | PF_PIPE_SEL_IVB(pipe)); | |
4800 | else | |
4801 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4802 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4803 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4804 | } |
4805 | } | |
4806 | ||
20bc8673 | 4807 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4808 | { |
cea165c3 | 4809 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4810 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4811 | |
6e3c9717 | 4812 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4813 | return; |
4814 | ||
307e4498 ML |
4815 | /* |
4816 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4817 | * This function is called from post_plane_update, which is run after | |
4818 | * a vblank wait. | |
4819 | */ | |
cea165c3 | 4820 | |
d77e4531 | 4821 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4822 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4823 | mutex_lock(&dev_priv->rps.hw_lock); |
4824 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4825 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4826 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4827 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4828 | * mailbox." Moreover, the mailbox may return a bogus state, |
4829 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4830 | */ |
4831 | } else { | |
4832 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4833 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4834 | * is essentially intel_wait_for_vblank. If we don't have this | |
4835 | * and don't wait for vblanks until the end of crtc_enable, then | |
4836 | * the HW state readout code will complain that the expected | |
4837 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4838 | if (intel_wait_for_register(dev_priv, |
4839 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4840 | 50)) | |
2a114cc1 BW |
4841 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4842 | } | |
d77e4531 PZ |
4843 | } |
4844 | ||
20bc8673 | 4845 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4846 | { |
4847 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4848 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4849 | |
6e3c9717 | 4850 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4851 | return; |
4852 | ||
4853 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4854 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4855 | mutex_lock(&dev_priv->rps.hw_lock); |
4856 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4857 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4858 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4859 | if (intel_wait_for_register(dev_priv, |
4860 | IPS_CTL, IPS_ENABLE, 0, | |
4861 | 42)) | |
23d0b130 | 4862 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4863 | } else { |
2a114cc1 | 4864 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4865 | POSTING_READ(IPS_CTL); |
4866 | } | |
d77e4531 PZ |
4867 | |
4868 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4869 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4870 | } |
4871 | ||
7cac945f | 4872 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4873 | { |
7cac945f | 4874 | if (intel_crtc->overlay) { |
d3eedb1a | 4875 | struct drm_device *dev = intel_crtc->base.dev; |
d3eedb1a VS |
4876 | |
4877 | mutex_lock(&dev->struct_mutex); | |
d3eedb1a | 4878 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
d3eedb1a VS |
4879 | mutex_unlock(&dev->struct_mutex); |
4880 | } | |
4881 | ||
4882 | /* Let userspace switch the overlay on again. In most cases userspace | |
4883 | * has to recompute where to put it anyway. | |
4884 | */ | |
4885 | } | |
4886 | ||
87d4300a ML |
4887 | /** |
4888 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4889 | * @crtc: the CRTC whose primary plane was just enabled | |
4890 | * | |
4891 | * Performs potentially sleeping operations that must be done after the primary | |
4892 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4893 | * called due to an explicit primary plane update, or due to an implicit | |
4894 | * re-enable that is caused when a sprite plane is updated to no longer | |
4895 | * completely hide the primary plane. | |
4896 | */ | |
4897 | static void | |
4898 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4899 | { |
4900 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4901 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4902 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4903 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4904 | |
87d4300a ML |
4905 | /* |
4906 | * FIXME IPS should be fine as long as one plane is | |
4907 | * enabled, but in practice it seems to have problems | |
4908 | * when going from primary only to sprite only and vice | |
4909 | * versa. | |
4910 | */ | |
a5c4d7bc VS |
4911 | hsw_enable_ips(intel_crtc); |
4912 | ||
f99d7069 | 4913 | /* |
87d4300a ML |
4914 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4915 | * So don't enable underrun reporting before at least some planes | |
4916 | * are enabled. | |
4917 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4918 | * but leave the pipe running. | |
f99d7069 | 4919 | */ |
5db94019 | 4920 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4921 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4922 | ||
aca7b684 VS |
4923 | /* Underruns don't always raise interrupts, so check manually. */ |
4924 | intel_check_cpu_fifo_underruns(dev_priv); | |
4925 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4926 | } |
4927 | ||
2622a081 | 4928 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4929 | static void |
4930 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4931 | { |
4932 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4933 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4934 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4935 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4936 | |
87d4300a ML |
4937 | /* |
4938 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4939 | * So diasble underrun reporting before all the planes get disabled. | |
4940 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4941 | * but leave the pipe running. | |
4942 | */ | |
5db94019 | 4943 | if (IS_GEN2(dev_priv)) |
87d4300a | 4944 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 4945 | |
2622a081 VS |
4946 | /* |
4947 | * FIXME IPS should be fine as long as one plane is | |
4948 | * enabled, but in practice it seems to have problems | |
4949 | * when going from primary only to sprite only and vice | |
4950 | * versa. | |
4951 | */ | |
4952 | hsw_disable_ips(intel_crtc); | |
4953 | } | |
4954 | ||
4955 | /* FIXME get rid of this and use pre_plane_update */ | |
4956 | static void | |
4957 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4958 | { | |
4959 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4960 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4962 | int pipe = intel_crtc->pipe; | |
4963 | ||
4964 | intel_pre_disable_primary(crtc); | |
4965 | ||
87d4300a ML |
4966 | /* |
4967 | * Vblank time updates from the shadow to live plane control register | |
4968 | * are blocked if the memory self-refresh mode is active at that | |
4969 | * moment. So to make sure the plane gets truly disabled, disable | |
4970 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4971 | * will be checked/applied by the HW only at the next frame start | |
4972 | * event which is after the vblank start event, so we need to have a | |
4973 | * wait-for-vblank between disabling the plane and the pipe. | |
4974 | */ | |
11a85d6a VS |
4975 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4976 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 4977 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
4978 | } |
4979 | ||
5a21b665 DV |
4980 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4981 | { | |
4982 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4983 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4984 | struct intel_crtc_state *pipe_config = | |
4985 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
4986 | struct drm_plane *primary = crtc->base.primary; |
4987 | struct drm_plane_state *old_pri_state = | |
4988 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4989 | ||
5748b6a1 | 4990 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 | 4991 | |
5a21b665 | 4992 | if (pipe_config->update_wm_post && pipe_config->base.active) |
432081bc | 4993 | intel_update_watermarks(crtc); |
5a21b665 DV |
4994 | |
4995 | if (old_pri_state) { | |
4996 | struct intel_plane_state *primary_state = | |
4997 | to_intel_plane_state(primary->state); | |
4998 | struct intel_plane_state *old_primary_state = | |
4999 | to_intel_plane_state(old_pri_state); | |
5000 | ||
5001 | intel_fbc_post_update(crtc); | |
5002 | ||
936e71e3 | 5003 | if (primary_state->base.visible && |
5a21b665 | 5004 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5005 | !old_primary_state->base.visible)) |
5a21b665 DV |
5006 | intel_post_enable_primary(&crtc->base); |
5007 | } | |
5008 | } | |
5009 | ||
aa5e9b47 ML |
5010 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, |
5011 | struct intel_crtc_state *pipe_config) | |
ac21b225 | 5012 | { |
5c74cd73 | 5013 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5014 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5015 | struct drm_i915_private *dev_priv = to_i915(dev); |
5c74cd73 ML |
5016 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5017 | struct drm_plane *primary = crtc->base.primary; | |
5018 | struct drm_plane_state *old_pri_state = | |
5019 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5020 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5021 | struct intel_atomic_state *old_intel_state = |
5022 | to_intel_atomic_state(old_state); | |
ac21b225 | 5023 | |
5c74cd73 ML |
5024 | if (old_pri_state) { |
5025 | struct intel_plane_state *primary_state = | |
5026 | to_intel_plane_state(primary->state); | |
5027 | struct intel_plane_state *old_primary_state = | |
5028 | to_intel_plane_state(old_pri_state); | |
5029 | ||
faf68d92 | 5030 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5031 | |
936e71e3 VS |
5032 | if (old_primary_state->base.visible && |
5033 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5034 | intel_pre_disable_primary(&crtc->base); |
5035 | } | |
852eb00d | 5036 | |
5eeb798b VS |
5037 | /* |
5038 | * Vblank time updates from the shadow to live plane control register | |
5039 | * are blocked if the memory self-refresh mode is active at that | |
5040 | * moment. So to make sure the plane gets truly disabled, disable | |
5041 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5042 | * will be checked/applied by the HW only at the next frame start | |
5043 | * event which is after the vblank start event, so we need to have a | |
5044 | * wait-for-vblank between disabling the plane and the pipe. | |
5045 | */ | |
5046 | if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active && | |
5047 | pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) | |
5048 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
92826fcd | 5049 | |
ed4a6a7c MR |
5050 | /* |
5051 | * IVB workaround: must disable low power watermarks for at least | |
5052 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5053 | * when scaling is disabled. | |
5054 | * | |
5055 | * WaCxSRDisabledForSpriteScaling:ivb | |
5056 | */ | |
ddd2b792 | 5057 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5058 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5059 | |
5060 | /* | |
5061 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5062 | * watermark programming here. | |
5063 | */ | |
5064 | if (needs_modeset(&pipe_config->base)) | |
5065 | return; | |
5066 | ||
5067 | /* | |
5068 | * For platforms that support atomic watermarks, program the | |
5069 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5070 | * will be the intermediate values that are safe for both pre- and | |
5071 | * post- vblank; when vblank happens, the 'active' values will be set | |
5072 | * to the final 'target' values and we'll do this again to get the | |
5073 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5074 | * will be the final target values which will get automatically latched | |
5075 | * at vblank time; no further programming will be necessary. | |
5076 | * | |
5077 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5078 | * we'll continue to update watermarks the old way, if flags tell | |
5079 | * us to. | |
5080 | */ | |
5081 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5082 | dev_priv->display.initial_watermarks(old_intel_state, |
5083 | pipe_config); | |
caed361d | 5084 | else if (pipe_config->update_wm_pre) |
432081bc | 5085 | intel_update_watermarks(crtc); |
ac21b225 ML |
5086 | } |
5087 | ||
d032ffa0 | 5088 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5089 | { |
5090 | struct drm_device *dev = crtc->dev; | |
5091 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5092 | struct drm_plane *p; |
87d4300a ML |
5093 | int pipe = intel_crtc->pipe; |
5094 | ||
7cac945f | 5095 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5096 | |
d032ffa0 | 5097 | drm_for_each_plane_mask(p, dev, plane_mask) |
282dbf9b | 5098 | to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc); |
f98551ae | 5099 | |
f99d7069 DV |
5100 | /* |
5101 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5102 | * to compute the mask of flip planes precisely. For the time being | |
5103 | * consider this a flip to a NULL plane. | |
5104 | */ | |
5748b6a1 | 5105 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5106 | } |
5107 | ||
fb1c98b1 | 5108 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5109 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5110 | struct drm_atomic_state *old_state) |
5111 | { | |
aa5e9b47 | 5112 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5113 | struct drm_connector *conn; |
5114 | int i; | |
5115 | ||
aa5e9b47 | 5116 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5117 | struct intel_encoder *encoder = |
5118 | to_intel_encoder(conn_state->best_encoder); | |
5119 | ||
5120 | if (conn_state->crtc != crtc) | |
5121 | continue; | |
5122 | ||
5123 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5124 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5125 | } |
5126 | } | |
5127 | ||
5128 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5129 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5130 | struct drm_atomic_state *old_state) |
5131 | { | |
aa5e9b47 | 5132 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5133 | struct drm_connector *conn; |
5134 | int i; | |
5135 | ||
aa5e9b47 | 5136 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5137 | struct intel_encoder *encoder = |
5138 | to_intel_encoder(conn_state->best_encoder); | |
5139 | ||
5140 | if (conn_state->crtc != crtc) | |
5141 | continue; | |
5142 | ||
5143 | if (encoder->pre_enable) | |
fd6bbda9 | 5144 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5145 | } |
5146 | } | |
5147 | ||
5148 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5149 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5150 | struct drm_atomic_state *old_state) |
5151 | { | |
aa5e9b47 | 5152 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5153 | struct drm_connector *conn; |
5154 | int i; | |
5155 | ||
aa5e9b47 | 5156 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5157 | struct intel_encoder *encoder = |
5158 | to_intel_encoder(conn_state->best_encoder); | |
5159 | ||
5160 | if (conn_state->crtc != crtc) | |
5161 | continue; | |
5162 | ||
fd6bbda9 | 5163 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5164 | intel_opregion_notify_encoder(encoder, true); |
5165 | } | |
5166 | } | |
5167 | ||
5168 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5169 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5170 | struct drm_atomic_state *old_state) |
5171 | { | |
5172 | struct drm_connector_state *old_conn_state; | |
5173 | struct drm_connector *conn; | |
5174 | int i; | |
5175 | ||
aa5e9b47 | 5176 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5177 | struct intel_encoder *encoder = |
5178 | to_intel_encoder(old_conn_state->best_encoder); | |
5179 | ||
5180 | if (old_conn_state->crtc != crtc) | |
5181 | continue; | |
5182 | ||
5183 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5184 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5185 | } |
5186 | } | |
5187 | ||
5188 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5189 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5190 | struct drm_atomic_state *old_state) |
5191 | { | |
5192 | struct drm_connector_state *old_conn_state; | |
5193 | struct drm_connector *conn; | |
5194 | int i; | |
5195 | ||
aa5e9b47 | 5196 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5197 | struct intel_encoder *encoder = |
5198 | to_intel_encoder(old_conn_state->best_encoder); | |
5199 | ||
5200 | if (old_conn_state->crtc != crtc) | |
5201 | continue; | |
5202 | ||
5203 | if (encoder->post_disable) | |
fd6bbda9 | 5204 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5205 | } |
5206 | } | |
5207 | ||
5208 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5209 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5210 | struct drm_atomic_state *old_state) |
5211 | { | |
5212 | struct drm_connector_state *old_conn_state; | |
5213 | struct drm_connector *conn; | |
5214 | int i; | |
5215 | ||
aa5e9b47 | 5216 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5217 | struct intel_encoder *encoder = |
5218 | to_intel_encoder(old_conn_state->best_encoder); | |
5219 | ||
5220 | if (old_conn_state->crtc != crtc) | |
5221 | continue; | |
5222 | ||
5223 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5224 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5225 | } |
5226 | } | |
5227 | ||
4a806558 ML |
5228 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5229 | struct drm_atomic_state *old_state) | |
f67a559d | 5230 | { |
4a806558 | 5231 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5232 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5233 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5234 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5235 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5236 | struct intel_atomic_state *old_intel_state = |
5237 | to_intel_atomic_state(old_state); | |
f67a559d | 5238 | |
53d9f4e9 | 5239 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5240 | return; |
5241 | ||
b2c0593a VS |
5242 | /* |
5243 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5244 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5245 | * | |
5246 | * On ILK we get an occasional spurious CPU pipe underruns | |
5247 | * between eDP port A enable and vdd enable. Also PCH port | |
5248 | * enable seems to result in the occasional CPU pipe underrun. | |
5249 | * | |
5250 | * Spurious PCH underruns also occur during PCH enabling. | |
5251 | */ | |
5252 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5253 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5254 | if (intel_crtc->config->has_pch_encoder) |
5255 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5256 | ||
6e3c9717 | 5257 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5258 | intel_prepare_shared_dpll(intel_crtc); |
5259 | ||
37a5650b | 5260 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5261 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5262 | |
5263 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5264 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5265 | |
6e3c9717 | 5266 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5267 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5268 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5269 | } |
5270 | ||
5271 | ironlake_set_pipeconf(crtc); | |
5272 | ||
f67a559d | 5273 | intel_crtc->active = true; |
8664281b | 5274 | |
fd6bbda9 | 5275 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5276 | |
6e3c9717 | 5277 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5278 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5279 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5280 | * enabling. */ | |
88cefb6c | 5281 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5282 | } else { |
5283 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5284 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5285 | } | |
f67a559d | 5286 | |
b074cec8 | 5287 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5288 | |
9c54c0dd JB |
5289 | /* |
5290 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5291 | * clocks enabled | |
5292 | */ | |
b95c5321 | 5293 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5294 | |
1d5bf5d9 | 5295 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5296 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5297 | intel_enable_pipe(intel_crtc); |
f67a559d | 5298 | |
6e3c9717 | 5299 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5300 | ironlake_pch_enable(pipe_config); |
c98e9dcf | 5301 | |
f9b61ff6 DV |
5302 | assert_vblank_disabled(crtc); |
5303 | drm_crtc_vblank_on(crtc); | |
5304 | ||
fd6bbda9 | 5305 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5306 | |
6e266956 | 5307 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5308 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5309 | |
5310 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5311 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5312 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5313 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5314 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5315 | } |
5316 | ||
42db64ef PZ |
5317 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5318 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5319 | { | |
50a0bc90 | 5320 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5321 | } |
5322 | ||
4a806558 ML |
5323 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5324 | struct drm_atomic_state *old_state) | |
4f771f10 | 5325 | { |
4a806558 | 5326 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5327 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5329 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5330 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5331 | struct intel_atomic_state *old_intel_state = |
5332 | to_intel_atomic_state(old_state); | |
4f771f10 | 5333 | |
53d9f4e9 | 5334 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5335 | return; |
5336 | ||
81b088ca VS |
5337 | if (intel_crtc->config->has_pch_encoder) |
5338 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5339 | false); | |
5340 | ||
fd6bbda9 | 5341 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5342 | |
8106ddbd | 5343 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5344 | intel_enable_shared_dpll(intel_crtc); |
5345 | ||
37a5650b | 5346 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5347 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5348 | |
d7edc4e5 | 5349 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5350 | intel_set_pipe_timings(intel_crtc); |
5351 | ||
bc58be60 | 5352 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5353 | |
4d1de975 JN |
5354 | if (cpu_transcoder != TRANSCODER_EDP && |
5355 | !transcoder_is_dsi(cpu_transcoder)) { | |
5356 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5357 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5358 | } |
5359 | ||
6e3c9717 | 5360 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5361 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5362 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5363 | } |
5364 | ||
d7edc4e5 | 5365 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5366 | haswell_set_pipeconf(crtc); |
5367 | ||
391bf048 | 5368 | haswell_set_pipemisc(crtc); |
229fca97 | 5369 | |
b95c5321 | 5370 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5371 | |
4f771f10 | 5372 | intel_crtc->active = true; |
8664281b | 5373 | |
6b698516 DV |
5374 | if (intel_crtc->config->has_pch_encoder) |
5375 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5376 | else | |
5377 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5378 | ||
fd6bbda9 | 5379 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5380 | |
d2d65408 | 5381 | if (intel_crtc->config->has_pch_encoder) |
dc4a1094 | 5382 | dev_priv->display.fdi_link_train(intel_crtc, pipe_config); |
4fe9467d | 5383 | |
d7edc4e5 | 5384 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5385 | intel_ddi_enable_pipe_clock(pipe_config); |
4f771f10 | 5386 | |
6315b5d3 | 5387 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5388 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5389 | else |
1c132b44 | 5390 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5391 | |
5392 | /* | |
5393 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5394 | * clocks enabled | |
5395 | */ | |
b95c5321 | 5396 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5397 | |
3dc38eea | 5398 | intel_ddi_set_pipe_settings(pipe_config); |
d7edc4e5 | 5399 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5400 | intel_ddi_enable_transcoder_func(pipe_config); |
4f771f10 | 5401 | |
1d5bf5d9 | 5402 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5403 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5404 | |
5405 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5406 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5407 | intel_enable_pipe(intel_crtc); |
42db64ef | 5408 | |
6e3c9717 | 5409 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5410 | lpt_pch_enable(pipe_config); |
4f771f10 | 5411 | |
0037071d | 5412 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5413 | intel_ddi_set_vc_payload_alloc(pipe_config, true); |
0e32b39c | 5414 | |
f9b61ff6 DV |
5415 | assert_vblank_disabled(crtc); |
5416 | drm_crtc_vblank_on(crtc); | |
5417 | ||
fd6bbda9 | 5418 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5419 | |
6b698516 | 5420 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5421 | intel_wait_for_vblank(dev_priv, pipe); |
5422 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5423 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
d2d65408 VS |
5424 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5425 | true); | |
6b698516 | 5426 | } |
d2d65408 | 5427 | |
e4916946 PZ |
5428 | /* If we change the relative order between pipe/planes enabling, we need |
5429 | * to change the workaround. */ | |
99d736a2 | 5430 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5431 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5432 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5433 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5434 | } |
4f771f10 PZ |
5435 | } |
5436 | ||
bfd16b2a | 5437 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5438 | { |
5439 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5440 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5441 | int pipe = crtc->pipe; |
5442 | ||
5443 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5444 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5445 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5446 | I915_WRITE(PF_CTL(pipe), 0); |
5447 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5448 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5449 | } | |
5450 | } | |
5451 | ||
4a806558 ML |
5452 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5453 | struct drm_atomic_state *old_state) | |
6be4a607 | 5454 | { |
4a806558 | 5455 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5456 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5457 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5458 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5459 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5460 | |
b2c0593a VS |
5461 | /* |
5462 | * Sometimes spurious CPU pipe underruns happen when the | |
5463 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5464 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5465 | */ | |
5466 | if (intel_crtc->config->has_pch_encoder) { | |
5467 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5468 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5469 | } |
37ca8d4c | 5470 | |
fd6bbda9 | 5471 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5472 | |
f9b61ff6 DV |
5473 | drm_crtc_vblank_off(crtc); |
5474 | assert_vblank_disabled(crtc); | |
5475 | ||
575f7ab7 | 5476 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5477 | |
bfd16b2a | 5478 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5479 | |
b2c0593a | 5480 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5481 | ironlake_fdi_disable(crtc); |
5482 | ||
fd6bbda9 | 5483 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5484 | |
6e3c9717 | 5485 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5486 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5487 | |
6e266956 | 5488 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5489 | i915_reg_t reg; |
5490 | u32 temp; | |
5491 | ||
d925c59a DV |
5492 | /* disable TRANS_DP_CTL */ |
5493 | reg = TRANS_DP_CTL(pipe); | |
5494 | temp = I915_READ(reg); | |
5495 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5496 | TRANS_DP_PORT_SEL_MASK); | |
5497 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5498 | I915_WRITE(reg, temp); | |
5499 | ||
5500 | /* disable DPLL_SEL */ | |
5501 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5502 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5503 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5504 | } |
e3421a18 | 5505 | |
d925c59a DV |
5506 | ironlake_fdi_pll_disable(intel_crtc); |
5507 | } | |
81b088ca | 5508 | |
b2c0593a | 5509 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5510 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5511 | } |
1b3c7a47 | 5512 | |
4a806558 ML |
5513 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5514 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5515 | { |
4a806558 | 5516 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5517 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5518 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5519 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5520 | |
d2d65408 VS |
5521 | if (intel_crtc->config->has_pch_encoder) |
5522 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5523 | false); | |
5524 | ||
fd6bbda9 | 5525 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5526 | |
f9b61ff6 DV |
5527 | drm_crtc_vblank_off(crtc); |
5528 | assert_vblank_disabled(crtc); | |
5529 | ||
4d1de975 | 5530 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5531 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5532 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5533 | |
0037071d | 5534 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5535 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); |
a4bf214f | 5536 | |
d7edc4e5 | 5537 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5538 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5539 | |
6315b5d3 | 5540 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5541 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5542 | else |
bfd16b2a | 5543 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5544 | |
d7edc4e5 | 5545 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5546 | intel_ddi_disable_pipe_clock(intel_crtc->config); |
4f771f10 | 5547 | |
fd6bbda9 | 5548 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5549 | |
b7076546 | 5550 | if (old_crtc_state->has_pch_encoder) |
81b088ca VS |
5551 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5552 | true); | |
4f771f10 PZ |
5553 | } |
5554 | ||
2dd24552 JB |
5555 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5556 | { | |
5557 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5558 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5559 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5560 | |
681a8504 | 5561 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5562 | return; |
5563 | ||
2dd24552 | 5564 | /* |
c0b03411 DV |
5565 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5566 | * according to register description and PRM. | |
2dd24552 | 5567 | */ |
c0b03411 DV |
5568 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5569 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5570 | |
b074cec8 JB |
5571 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5572 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5573 | |
5574 | /* Border color in case we don't scale up to the full screen. Black by | |
5575 | * default, change to something else for debugging. */ | |
5576 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5577 | } |
5578 | ||
79f255a0 | 5579 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
5580 | { |
5581 | switch (port) { | |
5582 | case PORT_A: | |
6331a704 | 5583 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5584 | case PORT_B: |
6331a704 | 5585 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5586 | case PORT_C: |
6331a704 | 5587 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5588 | case PORT_D: |
6331a704 | 5589 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5590 | case PORT_E: |
6331a704 | 5591 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5592 | default: |
b9fec167 | 5593 | MISSING_CASE(port); |
d05410f9 DA |
5594 | return POWER_DOMAIN_PORT_OTHER; |
5595 | } | |
5596 | } | |
5597 | ||
d8fc70b7 ACO |
5598 | static u64 get_crtc_power_domains(struct drm_crtc *crtc, |
5599 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5600 | { |
319be8ae | 5601 | struct drm_device *dev = crtc->dev; |
37255d8d | 5602 | struct drm_i915_private *dev_priv = to_i915(dev); |
74bff5f9 | 5603 | struct drm_encoder *encoder; |
319be8ae ID |
5604 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5605 | enum pipe pipe = intel_crtc->pipe; | |
d8fc70b7 | 5606 | u64 mask; |
74bff5f9 | 5607 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5608 | |
74bff5f9 | 5609 | if (!crtc_state->base.active) |
292b990e ML |
5610 | return 0; |
5611 | ||
77d22dca ID |
5612 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5613 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5614 | if (crtc_state->pch_pfit.enabled || |
5615 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 5616 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 5617 | |
74bff5f9 ML |
5618 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5619 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5620 | ||
79f255a0 | 5621 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 5622 | } |
319be8ae | 5623 | |
37255d8d ML |
5624 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
5625 | mask |= BIT(POWER_DOMAIN_AUDIO); | |
5626 | ||
15e7ec29 | 5627 | if (crtc_state->shared_dpll) |
d8fc70b7 | 5628 | mask |= BIT_ULL(POWER_DOMAIN_PLLS); |
15e7ec29 | 5629 | |
77d22dca ID |
5630 | return mask; |
5631 | } | |
5632 | ||
d2d15016 | 5633 | static u64 |
74bff5f9 ML |
5634 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
5635 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5636 | { |
fac5e23e | 5637 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5638 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5639 | enum intel_display_power_domain domain; | |
d8fc70b7 | 5640 | u64 domains, new_domains, old_domains; |
77d22dca | 5641 | |
292b990e | 5642 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5643 | intel_crtc->enabled_power_domains = new_domains = |
5644 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5645 | |
5a21b665 | 5646 | domains = new_domains & ~old_domains; |
292b990e ML |
5647 | |
5648 | for_each_power_domain(domain, domains) | |
5649 | intel_display_power_get(dev_priv, domain); | |
5650 | ||
5a21b665 | 5651 | return old_domains & ~new_domains; |
292b990e ML |
5652 | } |
5653 | ||
5654 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 5655 | u64 domains) |
292b990e ML |
5656 | { |
5657 | enum intel_display_power_domain domain; | |
5658 | ||
5659 | for_each_power_domain(domain, domains) | |
5660 | intel_display_power_put(dev_priv, domain); | |
5661 | } | |
77d22dca | 5662 | |
7ff89ca2 VS |
5663 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
5664 | struct drm_atomic_state *old_state) | |
adafdc6f | 5665 | { |
ff32c54e VS |
5666 | struct intel_atomic_state *old_intel_state = |
5667 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5668 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5669 | struct drm_device *dev = crtc->dev; | |
5670 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5671 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5672 | int pipe = intel_crtc->pipe; | |
adafdc6f | 5673 | |
7ff89ca2 VS |
5674 | if (WARN_ON(intel_crtc->active)) |
5675 | return; | |
adafdc6f | 5676 | |
7ff89ca2 VS |
5677 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5678 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
b2045352 | 5679 | |
7ff89ca2 VS |
5680 | intel_set_pipe_timings(intel_crtc); |
5681 | intel_set_pipe_src_size(intel_crtc); | |
b2045352 | 5682 | |
7ff89ca2 VS |
5683 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
5684 | struct drm_i915_private *dev_priv = to_i915(dev); | |
560a7ae4 | 5685 | |
7ff89ca2 VS |
5686 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
5687 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
5688 | } |
5689 | ||
7ff89ca2 | 5690 | i9xx_set_pipeconf(intel_crtc); |
560a7ae4 | 5691 | |
7ff89ca2 | 5692 | intel_crtc->active = true; |
92891e45 | 5693 | |
7ff89ca2 | 5694 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 5695 | |
7ff89ca2 | 5696 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
5f199dfa | 5697 | |
7ff89ca2 VS |
5698 | if (IS_CHERRYVIEW(dev_priv)) { |
5699 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
5700 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
5701 | } else { | |
5702 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
5703 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
5f199dfa VS |
5704 | } |
5705 | ||
7ff89ca2 | 5706 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
5f199dfa | 5707 | |
7ff89ca2 | 5708 | i9xx_pfit_enable(intel_crtc); |
89b3c3c7 | 5709 | |
7ff89ca2 | 5710 | intel_color_load_luts(&pipe_config->base); |
89b3c3c7 | 5711 | |
ff32c54e VS |
5712 | dev_priv->display.initial_watermarks(old_intel_state, |
5713 | pipe_config); | |
7ff89ca2 VS |
5714 | intel_enable_pipe(intel_crtc); |
5715 | ||
5716 | assert_vblank_disabled(crtc); | |
5717 | drm_crtc_vblank_on(crtc); | |
89b3c3c7 | 5718 | |
7ff89ca2 | 5719 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b3c3c7 ACO |
5720 | } |
5721 | ||
7ff89ca2 | 5722 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
2b73001e | 5723 | { |
7ff89ca2 VS |
5724 | struct drm_device *dev = crtc->base.dev; |
5725 | struct drm_i915_private *dev_priv = to_i915(dev); | |
83d7c81f | 5726 | |
7ff89ca2 VS |
5727 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5728 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
2b73001e VS |
5729 | } |
5730 | ||
7ff89ca2 VS |
5731 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
5732 | struct drm_atomic_state *old_state) | |
2b73001e | 5733 | { |
04548cba VS |
5734 | struct intel_atomic_state *old_intel_state = |
5735 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5736 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5737 | struct drm_device *dev = crtc->dev; | |
5738 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5739 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5740 | enum pipe pipe = intel_crtc->pipe; | |
2b73001e | 5741 | |
7ff89ca2 VS |
5742 | if (WARN_ON(intel_crtc->active)) |
5743 | return; | |
2b73001e | 5744 | |
7ff89ca2 | 5745 | i9xx_set_pll_dividers(intel_crtc); |
2b73001e | 5746 | |
7ff89ca2 VS |
5747 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5748 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
83d7c81f | 5749 | |
7ff89ca2 VS |
5750 | intel_set_pipe_timings(intel_crtc); |
5751 | intel_set_pipe_src_size(intel_crtc); | |
2b73001e | 5752 | |
7ff89ca2 | 5753 | i9xx_set_pipeconf(intel_crtc); |
f8437dd1 | 5754 | |
7ff89ca2 | 5755 | intel_crtc->active = true; |
5f199dfa | 5756 | |
7ff89ca2 VS |
5757 | if (!IS_GEN2(dev_priv)) |
5758 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5f199dfa | 5759 | |
7ff89ca2 | 5760 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f8437dd1 | 5761 | |
7ff89ca2 | 5762 | i9xx_enable_pll(intel_crtc); |
f8437dd1 | 5763 | |
7ff89ca2 | 5764 | i9xx_pfit_enable(intel_crtc); |
f8437dd1 | 5765 | |
7ff89ca2 | 5766 | intel_color_load_luts(&pipe_config->base); |
f8437dd1 | 5767 | |
04548cba VS |
5768 | if (dev_priv->display.initial_watermarks != NULL) |
5769 | dev_priv->display.initial_watermarks(old_intel_state, | |
5770 | intel_crtc->config); | |
5771 | else | |
5772 | intel_update_watermarks(intel_crtc); | |
7ff89ca2 | 5773 | intel_enable_pipe(intel_crtc); |
f8437dd1 | 5774 | |
7ff89ca2 VS |
5775 | assert_vblank_disabled(crtc); |
5776 | drm_crtc_vblank_on(crtc); | |
f8437dd1 | 5777 | |
7ff89ca2 VS |
5778 | intel_encoders_enable(crtc, pipe_config, old_state); |
5779 | } | |
f8437dd1 | 5780 | |
7ff89ca2 VS |
5781 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5782 | { | |
5783 | struct drm_device *dev = crtc->base.dev; | |
5784 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f8437dd1 | 5785 | |
7ff89ca2 | 5786 | if (!crtc->config->gmch_pfit.control) |
f8437dd1 | 5787 | return; |
f8437dd1 | 5788 | |
7ff89ca2 VS |
5789 | assert_pipe_disabled(dev_priv, crtc->pipe); |
5790 | ||
5791 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
5792 | I915_READ(PFIT_CONTROL)); | |
5793 | I915_WRITE(PFIT_CONTROL, 0); | |
f8437dd1 VK |
5794 | } |
5795 | ||
7ff89ca2 VS |
5796 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5797 | struct drm_atomic_state *old_state) | |
f8437dd1 | 5798 | { |
7ff89ca2 VS |
5799 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
5800 | struct drm_device *dev = crtc->dev; | |
5801 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5803 | int pipe = intel_crtc->pipe; | |
d66a2194 | 5804 | |
d66a2194 | 5805 | /* |
7ff89ca2 VS |
5806 | * On gen2 planes are double buffered but the pipe isn't, so we must |
5807 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 5808 | */ |
7ff89ca2 VS |
5809 | if (IS_GEN2(dev_priv)) |
5810 | intel_wait_for_vblank(dev_priv, pipe); | |
d66a2194 | 5811 | |
7ff89ca2 | 5812 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5813 | |
7ff89ca2 VS |
5814 | drm_crtc_vblank_off(crtc); |
5815 | assert_vblank_disabled(crtc); | |
d66a2194 | 5816 | |
7ff89ca2 | 5817 | intel_disable_pipe(intel_crtc); |
d66a2194 | 5818 | |
7ff89ca2 | 5819 | i9xx_pfit_disable(intel_crtc); |
89b3c3c7 | 5820 | |
7ff89ca2 | 5821 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5822 | |
7ff89ca2 VS |
5823 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
5824 | if (IS_CHERRYVIEW(dev_priv)) | |
5825 | chv_disable_pll(dev_priv, pipe); | |
5826 | else if (IS_VALLEYVIEW(dev_priv)) | |
5827 | vlv_disable_pll(dev_priv, pipe); | |
5828 | else | |
5829 | i9xx_disable_pll(intel_crtc); | |
5830 | } | |
c2e001ef | 5831 | |
7ff89ca2 | 5832 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
89b3c3c7 | 5833 | |
7ff89ca2 VS |
5834 | if (!IS_GEN2(dev_priv)) |
5835 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
ff32c54e VS |
5836 | |
5837 | if (!dev_priv->display.initial_watermarks) | |
5838 | intel_update_watermarks(intel_crtc); | |
f8437dd1 VK |
5839 | } |
5840 | ||
7ff89ca2 | 5841 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
f8437dd1 | 5842 | { |
7ff89ca2 VS |
5843 | struct intel_encoder *encoder; |
5844 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5845 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
5846 | enum intel_display_power_domain domain; | |
d2d15016 | 5847 | u64 domains; |
7ff89ca2 VS |
5848 | struct drm_atomic_state *state; |
5849 | struct intel_crtc_state *crtc_state; | |
5850 | int ret; | |
f8437dd1 | 5851 | |
7ff89ca2 VS |
5852 | if (!intel_crtc->active) |
5853 | return; | |
a8ca4934 | 5854 | |
7ff89ca2 VS |
5855 | if (crtc->primary->state->visible) { |
5856 | WARN_ON(intel_crtc->flip_work); | |
5d96d8af | 5857 | |
7ff89ca2 | 5858 | intel_pre_disable_primary_noatomic(crtc); |
709e05c3 | 5859 | |
7ff89ca2 VS |
5860 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
5861 | crtc->primary->state->visible = false; | |
5862 | } | |
5d96d8af | 5863 | |
7ff89ca2 VS |
5864 | state = drm_atomic_state_alloc(crtc->dev); |
5865 | if (!state) { | |
5866 | DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", | |
5867 | crtc->base.id, crtc->name); | |
1c3f7700 | 5868 | return; |
7ff89ca2 | 5869 | } |
9f7eb31a | 5870 | |
7ff89ca2 | 5871 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; |
ea61791e | 5872 | |
7ff89ca2 VS |
5873 | /* Everything's already locked, -EDEADLK can't happen. */ |
5874 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
5875 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
9f7eb31a | 5876 | |
7ff89ca2 | 5877 | WARN_ON(IS_ERR(crtc_state) || ret); |
5d96d8af | 5878 | |
7ff89ca2 | 5879 | dev_priv->display.crtc_disable(crtc_state, state); |
4a806558 | 5880 | |
0853695c | 5881 | drm_atomic_state_put(state); |
842e0307 | 5882 | |
78108b7c VS |
5883 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
5884 | crtc->base.id, crtc->name); | |
842e0307 ML |
5885 | |
5886 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
5887 | crtc->state->active = false; | |
37d9078b | 5888 | intel_crtc->active = false; |
842e0307 ML |
5889 | crtc->enabled = false; |
5890 | crtc->state->connector_mask = 0; | |
5891 | crtc->state->encoder_mask = 0; | |
5892 | ||
5893 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
5894 | encoder->base.crtc = NULL; | |
5895 | ||
58f9c0bc | 5896 | intel_fbc_disable(intel_crtc); |
432081bc | 5897 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 5898 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
5899 | |
5900 | domains = intel_crtc->enabled_power_domains; | |
5901 | for_each_power_domain(domain, domains) | |
5902 | intel_display_power_put(dev_priv, domain); | |
5903 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
5904 | |
5905 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
5906 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
5907 | } |
5908 | ||
6b72d486 ML |
5909 | /* |
5910 | * turn all crtc's off, but do not adjust state | |
5911 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
5912 | */ | |
70e0bd74 | 5913 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 5914 | { |
e2c8b870 | 5915 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 5916 | struct drm_atomic_state *state; |
e2c8b870 | 5917 | int ret; |
70e0bd74 | 5918 | |
e2c8b870 ML |
5919 | state = drm_atomic_helper_suspend(dev); |
5920 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
5921 | if (ret) |
5922 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
5923 | else |
5924 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 5925 | return ret; |
ee7b9f93 JB |
5926 | } |
5927 | ||
ea5b213a | 5928 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5929 | { |
4ef69c7a | 5930 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5931 | |
ea5b213a CW |
5932 | drm_encoder_cleanup(encoder); |
5933 | kfree(intel_encoder); | |
7e7d76c3 JB |
5934 | } |
5935 | ||
0a91ca29 DV |
5936 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5937 | * internal consistency). */ | |
749d98b8 ML |
5938 | static void intel_connector_verify_state(struct drm_crtc_state *crtc_state, |
5939 | struct drm_connector_state *conn_state) | |
79e53945 | 5940 | { |
749d98b8 | 5941 | struct intel_connector *connector = to_intel_connector(conn_state->connector); |
35dd3c64 ML |
5942 | |
5943 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5944 | connector->base.base.id, | |
5945 | connector->base.name); | |
5946 | ||
0a91ca29 | 5947 | if (connector->get_hw_state(connector)) { |
e85376cb | 5948 | struct intel_encoder *encoder = connector->encoder; |
0a91ca29 | 5949 | |
749d98b8 | 5950 | I915_STATE_WARN(!crtc_state, |
35dd3c64 | 5951 | "connector enabled without attached crtc\n"); |
0a91ca29 | 5952 | |
749d98b8 | 5953 | if (!crtc_state) |
35dd3c64 ML |
5954 | return; |
5955 | ||
749d98b8 | 5956 | I915_STATE_WARN(!crtc_state->active, |
35dd3c64 ML |
5957 | "connector is active, but attached crtc isn't\n"); |
5958 | ||
e85376cb | 5959 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
5960 | return; |
5961 | ||
e85376cb | 5962 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
5963 | "atomic encoder doesn't match attached encoder\n"); |
5964 | ||
e85376cb | 5965 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
5966 | "attached encoder crtc differs from connector crtc\n"); |
5967 | } else { | |
749d98b8 | 5968 | I915_STATE_WARN(crtc_state && crtc_state->active, |
4d688a2a | 5969 | "attached crtc is active, but connector isn't\n"); |
749d98b8 | 5970 | I915_STATE_WARN(!crtc_state && conn_state->best_encoder, |
35dd3c64 | 5971 | "best encoder set without crtc!\n"); |
0a91ca29 | 5972 | } |
79e53945 JB |
5973 | } |
5974 | ||
08d9bc92 ACO |
5975 | int intel_connector_init(struct intel_connector *connector) |
5976 | { | |
5350a031 | 5977 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 5978 | |
5350a031 | 5979 | if (!connector->base.state) |
08d9bc92 ACO |
5980 | return -ENOMEM; |
5981 | ||
08d9bc92 ACO |
5982 | return 0; |
5983 | } | |
5984 | ||
5985 | struct intel_connector *intel_connector_alloc(void) | |
5986 | { | |
5987 | struct intel_connector *connector; | |
5988 | ||
5989 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
5990 | if (!connector) | |
5991 | return NULL; | |
5992 | ||
5993 | if (intel_connector_init(connector) < 0) { | |
5994 | kfree(connector); | |
5995 | return NULL; | |
5996 | } | |
5997 | ||
5998 | return connector; | |
5999 | } | |
6000 | ||
f0947c37 DV |
6001 | /* Simple connector->get_hw_state implementation for encoders that support only |
6002 | * one connector and no cloning and hence the encoder state determines the state | |
6003 | * of the connector. */ | |
6004 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6005 | { |
24929352 | 6006 | enum pipe pipe = 0; |
f0947c37 | 6007 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6008 | |
f0947c37 | 6009 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6010 | } |
6011 | ||
6d293983 | 6012 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6013 | { |
6d293983 ACO |
6014 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6015 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6016 | |
6017 | return 0; | |
6018 | } | |
6019 | ||
6d293983 | 6020 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6021 | struct intel_crtc_state *pipe_config) |
1857e1da | 6022 | { |
8652744b | 6023 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
6024 | struct drm_atomic_state *state = pipe_config->base.state; |
6025 | struct intel_crtc *other_crtc; | |
6026 | struct intel_crtc_state *other_crtc_state; | |
6027 | ||
1857e1da DV |
6028 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6029 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6030 | if (pipe_config->fdi_lanes > 4) { | |
6031 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6032 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6033 | return -EINVAL; |
1857e1da DV |
6034 | } |
6035 | ||
8652744b | 6036 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
6037 | if (pipe_config->fdi_lanes > 2) { |
6038 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6039 | pipe_config->fdi_lanes); | |
6d293983 | 6040 | return -EINVAL; |
1857e1da | 6041 | } else { |
6d293983 | 6042 | return 0; |
1857e1da DV |
6043 | } |
6044 | } | |
6045 | ||
b7f05d4a | 6046 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 6047 | return 0; |
1857e1da DV |
6048 | |
6049 | /* Ivybridge 3 pipe is really complicated */ | |
6050 | switch (pipe) { | |
6051 | case PIPE_A: | |
6d293983 | 6052 | return 0; |
1857e1da | 6053 | case PIPE_B: |
6d293983 ACO |
6054 | if (pipe_config->fdi_lanes <= 2) |
6055 | return 0; | |
6056 | ||
b91eb5cc | 6057 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
6058 | other_crtc_state = |
6059 | intel_atomic_get_crtc_state(state, other_crtc); | |
6060 | if (IS_ERR(other_crtc_state)) | |
6061 | return PTR_ERR(other_crtc_state); | |
6062 | ||
6063 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6064 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6065 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6066 | return -EINVAL; |
1857e1da | 6067 | } |
6d293983 | 6068 | return 0; |
1857e1da | 6069 | case PIPE_C: |
251cc67c VS |
6070 | if (pipe_config->fdi_lanes > 2) { |
6071 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6072 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6073 | return -EINVAL; |
251cc67c | 6074 | } |
6d293983 | 6075 | |
b91eb5cc | 6076 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
6077 | other_crtc_state = |
6078 | intel_atomic_get_crtc_state(state, other_crtc); | |
6079 | if (IS_ERR(other_crtc_state)) | |
6080 | return PTR_ERR(other_crtc_state); | |
6081 | ||
6082 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6083 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6084 | return -EINVAL; |
1857e1da | 6085 | } |
6d293983 | 6086 | return 0; |
1857e1da DV |
6087 | default: |
6088 | BUG(); | |
6089 | } | |
6090 | } | |
6091 | ||
e29c22c0 DV |
6092 | #define RETRY 1 |
6093 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6094 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6095 | { |
1857e1da | 6096 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6097 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6098 | int lane, link_bw, fdi_dotclock, ret; |
6099 | bool needs_recompute = false; | |
877d48d5 | 6100 | |
e29c22c0 | 6101 | retry: |
877d48d5 DV |
6102 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6103 | * each output octet as 10 bits. The actual frequency | |
6104 | * is stored as a divider into a 100MHz clock, and the | |
6105 | * mode pixel clock is stored in units of 1KHz. | |
6106 | * Hence the bw of each lane in terms of the mode signal | |
6107 | * is: | |
6108 | */ | |
21a727b3 | 6109 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6110 | |
241bfc38 | 6111 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6112 | |
2bd89a07 | 6113 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6114 | pipe_config->pipe_bpp); |
6115 | ||
6116 | pipe_config->fdi_lanes = lane; | |
6117 | ||
2bd89a07 | 6118 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6119 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6120 | |
e3b247da | 6121 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6122 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 6123 | pipe_config->pipe_bpp -= 2*3; |
7ff89ca2 VS |
6124 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
6125 | pipe_config->pipe_bpp); | |
6126 | needs_recompute = true; | |
6127 | pipe_config->bw_constrained = true; | |
257a7ffc | 6128 | |
7ff89ca2 | 6129 | goto retry; |
257a7ffc | 6130 | } |
79e53945 | 6131 | |
7ff89ca2 VS |
6132 | if (needs_recompute) |
6133 | return RETRY; | |
e70236a8 | 6134 | |
7ff89ca2 | 6135 | return ret; |
e70236a8 JB |
6136 | } |
6137 | ||
7ff89ca2 VS |
6138 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6139 | struct intel_crtc_state *pipe_config) | |
e70236a8 | 6140 | { |
7ff89ca2 VS |
6141 | if (pipe_config->pipe_bpp > 24) |
6142 | return false; | |
e70236a8 | 6143 | |
7ff89ca2 VS |
6144 | /* HSW can handle pixel rate up to cdclk? */ |
6145 | if (IS_HASWELL(dev_priv)) | |
6146 | return true; | |
1b1d2716 | 6147 | |
65cd2b3f | 6148 | /* |
7ff89ca2 VS |
6149 | * We compare against max which means we must take |
6150 | * the increased cdclk requirement into account when | |
6151 | * calculating the new cdclk. | |
6152 | * | |
6153 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 6154 | */ |
7ff89ca2 VS |
6155 | return pipe_config->pixel_rate <= |
6156 | dev_priv->max_cdclk_freq * 95 / 100; | |
e70236a8 | 6157 | } |
79e53945 | 6158 | |
7ff89ca2 VS |
6159 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
6160 | struct intel_crtc_state *pipe_config) | |
6161 | { | |
6162 | struct drm_device *dev = crtc->base.dev; | |
6163 | struct drm_i915_private *dev_priv = to_i915(dev); | |
34edce2f | 6164 | |
7ff89ca2 VS |
6165 | pipe_config->ips_enabled = i915.enable_ips && |
6166 | hsw_crtc_supports_ips(crtc) && | |
6167 | pipe_config_supports_ips(dev_priv, pipe_config); | |
34edce2f VS |
6168 | } |
6169 | ||
7ff89ca2 | 6170 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 6171 | { |
7ff89ca2 | 6172 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 6173 | |
7ff89ca2 VS |
6174 | /* GDG double wide on either pipe, otherwise pipe A only */ |
6175 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6176 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
34edce2f VS |
6177 | } |
6178 | ||
ceb99320 VS |
6179 | static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
6180 | { | |
6181 | uint32_t pixel_rate; | |
6182 | ||
6183 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; | |
6184 | ||
6185 | /* | |
6186 | * We only use IF-ID interlacing. If we ever use | |
6187 | * PF-ID we'll need to adjust the pixel_rate here. | |
6188 | */ | |
6189 | ||
6190 | if (pipe_config->pch_pfit.enabled) { | |
6191 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
6192 | uint32_t pfit_size = pipe_config->pch_pfit.size; | |
6193 | ||
6194 | pipe_w = pipe_config->pipe_src_w; | |
6195 | pipe_h = pipe_config->pipe_src_h; | |
6196 | ||
6197 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
6198 | pfit_h = pfit_size & 0xFFFF; | |
6199 | if (pipe_w < pfit_w) | |
6200 | pipe_w = pfit_w; | |
6201 | if (pipe_h < pfit_h) | |
6202 | pipe_h = pfit_h; | |
6203 | ||
6204 | if (WARN_ON(!pfit_w || !pfit_h)) | |
6205 | return pixel_rate; | |
6206 | ||
6207 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
6208 | pfit_w * pfit_h); | |
6209 | } | |
6210 | ||
6211 | return pixel_rate; | |
6212 | } | |
6213 | ||
7ff89ca2 | 6214 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 6215 | { |
7ff89ca2 | 6216 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
34edce2f | 6217 | |
7ff89ca2 VS |
6218 | if (HAS_GMCH_DISPLAY(dev_priv)) |
6219 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ | |
6220 | crtc_state->pixel_rate = | |
6221 | crtc_state->base.adjusted_mode.crtc_clock; | |
6222 | else | |
6223 | crtc_state->pixel_rate = | |
6224 | ilk_pipe_pixel_rate(crtc_state); | |
6225 | } | |
34edce2f | 6226 | |
7ff89ca2 VS |
6227 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6228 | struct intel_crtc_state *pipe_config) | |
6229 | { | |
6230 | struct drm_device *dev = crtc->base.dev; | |
6231 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6232 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6233 | int clock_limit = dev_priv->max_dotclk_freq; | |
34edce2f | 6234 | |
7ff89ca2 VS |
6235 | if (INTEL_GEN(dev_priv) < 4) { |
6236 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 6237 | |
7ff89ca2 VS |
6238 | /* |
6239 | * Enable double wide mode when the dot clock | |
6240 | * is > 90% of the (display) core speed. | |
6241 | */ | |
6242 | if (intel_crtc_supports_double_wide(crtc) && | |
6243 | adjusted_mode->crtc_clock > clock_limit) { | |
6244 | clock_limit = dev_priv->max_dotclk_freq; | |
6245 | pipe_config->double_wide = true; | |
6246 | } | |
34edce2f VS |
6247 | } |
6248 | ||
7ff89ca2 VS |
6249 | if (adjusted_mode->crtc_clock > clock_limit) { |
6250 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6251 | adjusted_mode->crtc_clock, clock_limit, | |
6252 | yesno(pipe_config->double_wide)); | |
6253 | return -EINVAL; | |
6254 | } | |
34edce2f | 6255 | |
7ff89ca2 VS |
6256 | /* |
6257 | * Pipe horizontal size must be even in: | |
6258 | * - DVO ganged mode | |
6259 | * - LVDS dual channel mode | |
6260 | * - Double wide pipe | |
6261 | */ | |
6262 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6263 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6264 | pipe_config->pipe_src_w &= ~1; | |
34edce2f | 6265 | |
7ff89ca2 VS |
6266 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6267 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6268 | */ | |
6269 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
6270 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6271 | return -EINVAL; | |
34edce2f | 6272 | |
7ff89ca2 | 6273 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 6274 | |
7ff89ca2 VS |
6275 | if (HAS_IPS(dev_priv)) |
6276 | hsw_compute_ips_config(crtc, pipe_config); | |
34edce2f | 6277 | |
7ff89ca2 VS |
6278 | if (pipe_config->has_pch_encoder) |
6279 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
34edce2f | 6280 | |
7ff89ca2 | 6281 | return 0; |
34edce2f VS |
6282 | } |
6283 | ||
2c07245f | 6284 | static void |
a65851af | 6285 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6286 | { |
a65851af VS |
6287 | while (*num > DATA_LINK_M_N_MASK || |
6288 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6289 | *num >>= 1; |
6290 | *den >>= 1; | |
6291 | } | |
6292 | } | |
6293 | ||
a65851af VS |
6294 | static void compute_m_n(unsigned int m, unsigned int n, |
6295 | uint32_t *ret_m, uint32_t *ret_n) | |
6296 | { | |
9a86cda0 JN |
6297 | /* |
6298 | * Reduce M/N as much as possible without loss in precision. Several DP | |
6299 | * dongles in particular seem to be fussy about too large *link* M/N | |
6300 | * values. The passed in values are more likely to have the least | |
6301 | * significant bits zero than M after rounding below, so do this first. | |
6302 | */ | |
6303 | while ((m & 1) == 0 && (n & 1) == 0) { | |
6304 | m >>= 1; | |
6305 | n >>= 1; | |
6306 | } | |
6307 | ||
a65851af VS |
6308 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
6309 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6310 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6311 | } | |
6312 | ||
e69d0bc1 DV |
6313 | void |
6314 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6315 | int pixel_clock, int link_clock, | |
6316 | struct intel_link_m_n *m_n) | |
2c07245f | 6317 | { |
e69d0bc1 | 6318 | m_n->tu = 64; |
a65851af VS |
6319 | |
6320 | compute_m_n(bits_per_pixel * pixel_clock, | |
6321 | link_clock * nlanes * 8, | |
6322 | &m_n->gmch_m, &m_n->gmch_n); | |
6323 | ||
6324 | compute_m_n(pixel_clock, link_clock, | |
6325 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6326 | } |
6327 | ||
a7615030 CW |
6328 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6329 | { | |
d330a953 JN |
6330 | if (i915.panel_use_ssc >= 0) |
6331 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6332 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6333 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6334 | } |
6335 | ||
7429e9d4 | 6336 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6337 | { |
7df00d7a | 6338 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6339 | } |
f47709a9 | 6340 | |
7429e9d4 DV |
6341 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6342 | { | |
6343 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6344 | } |
6345 | ||
f47709a9 | 6346 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6347 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 6348 | struct dpll *reduced_clock) |
a7516a05 | 6349 | { |
9b1e14f4 | 6350 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
6351 | u32 fp, fp2 = 0; |
6352 | ||
9b1e14f4 | 6353 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 6354 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6355 | if (reduced_clock) |
7429e9d4 | 6356 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6357 | } else { |
190f68c5 | 6358 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6359 | if (reduced_clock) |
7429e9d4 | 6360 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6361 | } |
6362 | ||
190f68c5 | 6363 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6364 | |
f47709a9 | 6365 | crtc->lowfreq_avail = false; |
2d84d2b3 | 6366 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6367 | reduced_clock) { |
190f68c5 | 6368 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6369 | crtc->lowfreq_avail = true; |
a7516a05 | 6370 | } else { |
190f68c5 | 6371 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6372 | } |
6373 | } | |
6374 | ||
5e69f97f CML |
6375 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6376 | pipe) | |
89b667f8 JB |
6377 | { |
6378 | u32 reg_val; | |
6379 | ||
6380 | /* | |
6381 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6382 | * and set it to a reasonable value instead. | |
6383 | */ | |
ab3c759a | 6384 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6385 | reg_val &= 0xffffff00; |
6386 | reg_val |= 0x00000030; | |
ab3c759a | 6387 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6388 | |
ab3c759a | 6389 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
ed58570f ID |
6390 | reg_val &= 0x00ffffff; |
6391 | reg_val |= 0x8c000000; | |
ab3c759a | 6392 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6393 | |
ab3c759a | 6394 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6395 | reg_val &= 0xffffff00; |
ab3c759a | 6396 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6397 | |
ab3c759a | 6398 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6399 | reg_val &= 0x00ffffff; |
6400 | reg_val |= 0xb0000000; | |
ab3c759a | 6401 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6402 | } |
6403 | ||
b551842d DV |
6404 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6405 | struct intel_link_m_n *m_n) | |
6406 | { | |
6407 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6408 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
6409 | int pipe = crtc->pipe; |
6410 | ||
e3b95f1e DV |
6411 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6412 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6413 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6414 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6415 | } |
6416 | ||
6417 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6418 | struct intel_link_m_n *m_n, |
6419 | struct intel_link_m_n *m2_n2) | |
b551842d | 6420 | { |
6315b5d3 | 6421 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 6422 | int pipe = crtc->pipe; |
6e3c9717 | 6423 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 6424 | |
6315b5d3 | 6425 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
6426 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6427 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6428 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6429 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6430 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6431 | * for gen < 8) and if DRRS is supported (to make sure the | |
6432 | * registers are not unnecessarily accessed). | |
6433 | */ | |
920a14b2 TU |
6434 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
6435 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
6436 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6437 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6438 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6439 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6440 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6441 | } | |
b551842d | 6442 | } else { |
e3b95f1e DV |
6443 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6444 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6445 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6446 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6447 | } |
6448 | } | |
6449 | ||
fe3cd48d | 6450 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6451 | { |
fe3cd48d R |
6452 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6453 | ||
6454 | if (m_n == M1_N1) { | |
6455 | dp_m_n = &crtc->config->dp_m_n; | |
6456 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6457 | } else if (m_n == M2_N2) { | |
6458 | ||
6459 | /* | |
6460 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6461 | * needs to be programmed into M1_N1. | |
6462 | */ | |
6463 | dp_m_n = &crtc->config->dp_m2_n2; | |
6464 | } else { | |
6465 | DRM_ERROR("Unsupported divider value\n"); | |
6466 | return; | |
6467 | } | |
6468 | ||
6e3c9717 ACO |
6469 | if (crtc->config->has_pch_encoder) |
6470 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6471 | else |
fe3cd48d | 6472 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6473 | } |
6474 | ||
251ac862 DV |
6475 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
6476 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 6477 | { |
03ed5cbf | 6478 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 6479 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6480 | if (crtc->pipe != PIPE_A) |
6481 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 6482 | |
cd2d34d9 | 6483 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6484 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6485 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
6486 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
6487 | ||
03ed5cbf VS |
6488 | pipe_config->dpll_hw_state.dpll_md = |
6489 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6490 | } | |
bdd4b6a6 | 6491 | |
03ed5cbf VS |
6492 | static void chv_compute_dpll(struct intel_crtc *crtc, |
6493 | struct intel_crtc_state *pipe_config) | |
6494 | { | |
6495 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 6496 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6497 | if (crtc->pipe != PIPE_A) |
6498 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6499 | ||
cd2d34d9 | 6500 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6501 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6502 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
6503 | ||
03ed5cbf VS |
6504 | pipe_config->dpll_hw_state.dpll_md = |
6505 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
6506 | } |
6507 | ||
d288f65f | 6508 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6509 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6510 | { |
f47709a9 | 6511 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6512 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6513 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 6514 | u32 mdiv; |
a0c4da24 | 6515 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6516 | u32 coreclk, reg_val; |
a0c4da24 | 6517 | |
cd2d34d9 VS |
6518 | /* Enable Refclk */ |
6519 | I915_WRITE(DPLL(pipe), | |
6520 | pipe_config->dpll_hw_state.dpll & | |
6521 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
6522 | ||
6523 | /* No need to actually set up the DPLL with DSI */ | |
6524 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6525 | return; | |
6526 | ||
a580516d | 6527 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 6528 | |
d288f65f VS |
6529 | bestn = pipe_config->dpll.n; |
6530 | bestm1 = pipe_config->dpll.m1; | |
6531 | bestm2 = pipe_config->dpll.m2; | |
6532 | bestp1 = pipe_config->dpll.p1; | |
6533 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6534 | |
89b667f8 JB |
6535 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6536 | ||
6537 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6538 | if (pipe == PIPE_B) |
5e69f97f | 6539 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6540 | |
6541 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6542 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6543 | |
6544 | /* Disable target IRef on PLL */ | |
ab3c759a | 6545 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6546 | reg_val &= 0x00ffffff; |
ab3c759a | 6547 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6548 | |
6549 | /* Disable fast lock */ | |
ab3c759a | 6550 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6551 | |
6552 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6553 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6554 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6555 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6556 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6557 | |
6558 | /* | |
6559 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6560 | * but we don't support that). | |
6561 | * Note: don't use the DAC post divider as it seems unstable. | |
6562 | */ | |
6563 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6564 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6565 | |
a0c4da24 | 6566 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6567 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6568 | |
89b667f8 | 6569 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6570 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
6571 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
6572 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6573 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6574 | 0x009f0003); |
89b667f8 | 6575 | else |
ab3c759a | 6576 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6577 | 0x00d0000f); |
6578 | ||
37a5650b | 6579 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 6580 | /* Use SSC source */ |
bdd4b6a6 | 6581 | if (pipe == PIPE_A) |
ab3c759a | 6582 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6583 | 0x0df40000); |
6584 | else | |
ab3c759a | 6585 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6586 | 0x0df70000); |
6587 | } else { /* HDMI or VGA */ | |
6588 | /* Use bend source */ | |
bdd4b6a6 | 6589 | if (pipe == PIPE_A) |
ab3c759a | 6590 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6591 | 0x0df70000); |
6592 | else | |
ab3c759a | 6593 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6594 | 0x0df40000); |
6595 | } | |
a0c4da24 | 6596 | |
ab3c759a | 6597 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6598 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 6599 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 6600 | coreclk |= 0x01000000; |
ab3c759a | 6601 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6602 | |
ab3c759a | 6603 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 6604 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
6605 | } |
6606 | ||
d288f65f | 6607 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6608 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6609 | { |
6610 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6611 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6612 | enum pipe pipe = crtc->pipe; |
9d556c99 | 6613 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 6614 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6615 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6616 | u32 dpio_val; |
9cbe40c1 | 6617 | int vco; |
9d556c99 | 6618 | |
cd2d34d9 VS |
6619 | /* Enable Refclk and SSC */ |
6620 | I915_WRITE(DPLL(pipe), | |
6621 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
6622 | ||
6623 | /* No need to actually set up the DPLL with DSI */ | |
6624 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6625 | return; | |
6626 | ||
d288f65f VS |
6627 | bestn = pipe_config->dpll.n; |
6628 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6629 | bestm1 = pipe_config->dpll.m1; | |
6630 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6631 | bestp1 = pipe_config->dpll.p1; | |
6632 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6633 | vco = pipe_config->dpll.vco; |
a945ce7e | 6634 | dpio_val = 0; |
9cbe40c1 | 6635 | loopfilter = 0; |
9d556c99 | 6636 | |
a580516d | 6637 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 6638 | |
9d556c99 CML |
6639 | /* p1 and p2 divider */ |
6640 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6641 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6642 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6643 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6644 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6645 | ||
6646 | /* Feedback post-divider - m2 */ | |
6647 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6648 | ||
6649 | /* Feedback refclk divider - n and m1 */ | |
6650 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6651 | DPIO_CHV_M1_DIV_BY_2 | | |
6652 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6653 | ||
6654 | /* M2 fraction division */ | |
25a25dfc | 6655 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
6656 | |
6657 | /* M2 fraction division enable */ | |
a945ce7e VP |
6658 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6659 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6660 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6661 | if (bestm2_frac) | |
6662 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6663 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6664 | |
de3a0fde VP |
6665 | /* Program digital lock detect threshold */ |
6666 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6667 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6668 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6669 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6670 | if (!bestm2_frac) | |
6671 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6672 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6673 | ||
9d556c99 | 6674 | /* Loop filter */ |
9cbe40c1 VP |
6675 | if (vco == 5400000) { |
6676 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6677 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6678 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6679 | tribuf_calcntr = 0x9; | |
6680 | } else if (vco <= 6200000) { | |
6681 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6682 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6683 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6684 | tribuf_calcntr = 0x9; | |
6685 | } else if (vco <= 6480000) { | |
6686 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6687 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6688 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6689 | tribuf_calcntr = 0x8; | |
6690 | } else { | |
6691 | /* Not supported. Apply the same limits as in the max case */ | |
6692 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6693 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6694 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6695 | tribuf_calcntr = 0; | |
6696 | } | |
9d556c99 CML |
6697 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6698 | ||
968040b2 | 6699 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6700 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6701 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6702 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6703 | ||
9d556c99 CML |
6704 | /* AFC Recal */ |
6705 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6706 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6707 | DPIO_AFC_RECAL); | |
6708 | ||
a580516d | 6709 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
6710 | } |
6711 | ||
d288f65f VS |
6712 | /** |
6713 | * vlv_force_pll_on - forcibly enable just the PLL | |
6714 | * @dev_priv: i915 private structure | |
6715 | * @pipe: pipe PLL to enable | |
6716 | * @dpll: PLL configuration | |
6717 | * | |
6718 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6719 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6720 | * be enabled. | |
6721 | */ | |
30ad9814 | 6722 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 6723 | const struct dpll *dpll) |
d288f65f | 6724 | { |
b91eb5cc | 6725 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
6726 | struct intel_crtc_state *pipe_config; |
6727 | ||
6728 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
6729 | if (!pipe_config) | |
6730 | return -ENOMEM; | |
6731 | ||
6732 | pipe_config->base.crtc = &crtc->base; | |
6733 | pipe_config->pixel_multiplier = 1; | |
6734 | pipe_config->dpll = *dpll; | |
d288f65f | 6735 | |
30ad9814 | 6736 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
6737 | chv_compute_dpll(crtc, pipe_config); |
6738 | chv_prepare_pll(crtc, pipe_config); | |
6739 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 6740 | } else { |
3f36b937 TU |
6741 | vlv_compute_dpll(crtc, pipe_config); |
6742 | vlv_prepare_pll(crtc, pipe_config); | |
6743 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 6744 | } |
3f36b937 TU |
6745 | |
6746 | kfree(pipe_config); | |
6747 | ||
6748 | return 0; | |
d288f65f VS |
6749 | } |
6750 | ||
6751 | /** | |
6752 | * vlv_force_pll_off - forcibly disable just the PLL | |
6753 | * @dev_priv: i915 private structure | |
6754 | * @pipe: pipe PLL to disable | |
6755 | * | |
6756 | * Disable the PLL for @pipe. To be used in cases where we need | |
6757 | * the PLL enabled even when @pipe is not going to be enabled. | |
6758 | */ | |
30ad9814 | 6759 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 6760 | { |
30ad9814 VS |
6761 | if (IS_CHERRYVIEW(dev_priv)) |
6762 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 6763 | else |
30ad9814 | 6764 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
6765 | } |
6766 | ||
251ac862 DV |
6767 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
6768 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6769 | struct dpll *reduced_clock) |
eb1cbe48 | 6770 | { |
9b1e14f4 | 6771 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 6772 | u32 dpll; |
190f68c5 | 6773 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6774 | |
190f68c5 | 6775 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6776 | |
eb1cbe48 DV |
6777 | dpll = DPLL_VGA_MODE_DIS; |
6778 | ||
2d84d2b3 | 6779 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6780 | dpll |= DPLLB_MODE_LVDS; |
6781 | else | |
6782 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6783 | |
73f67aa8 JN |
6784 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
6785 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 6786 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6787 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6788 | } |
198a037f | 6789 | |
3d6e9ee0 VS |
6790 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6791 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 6792 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6793 | |
37a5650b | 6794 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 6795 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6796 | |
6797 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 6798 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
6799 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
6800 | else { | |
6801 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 6802 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
6803 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6804 | } | |
6805 | switch (clock->p2) { | |
6806 | case 5: | |
6807 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6808 | break; | |
6809 | case 7: | |
6810 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6811 | break; | |
6812 | case 10: | |
6813 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6814 | break; | |
6815 | case 14: | |
6816 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6817 | break; | |
6818 | } | |
9b1e14f4 | 6819 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
6820 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
6821 | ||
190f68c5 | 6822 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6823 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 6824 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6825 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6826 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6827 | else | |
6828 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6829 | ||
6830 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6831 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6832 | |
9b1e14f4 | 6833 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 6834 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6835 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6836 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6837 | } |
6838 | } | |
6839 | ||
251ac862 DV |
6840 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
6841 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6842 | struct dpll *reduced_clock) |
eb1cbe48 | 6843 | { |
f47709a9 | 6844 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6845 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 6846 | u32 dpll; |
190f68c5 | 6847 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6848 | |
190f68c5 | 6849 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6850 | |
eb1cbe48 DV |
6851 | dpll = DPLL_VGA_MODE_DIS; |
6852 | ||
2d84d2b3 | 6853 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6854 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6855 | } else { | |
6856 | if (clock->p1 == 2) | |
6857 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6858 | else | |
6859 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6860 | if (clock->p2 == 4) | |
6861 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6862 | } | |
6863 | ||
50a0bc90 TU |
6864 | if (!IS_I830(dev_priv) && |
6865 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
6866 | dpll |= DPLL_DVO_2X_MODE; |
6867 | ||
2d84d2b3 | 6868 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6869 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6870 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6871 | else | |
6872 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6873 | ||
6874 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6875 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6876 | } |
6877 | ||
8a654f3b | 6878 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 6879 | { |
6315b5d3 | 6880 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 6881 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 6882 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 6883 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6884 | uint32_t crtc_vtotal, crtc_vblank_end; |
6885 | int vsyncshift = 0; | |
4d8a62ea DV |
6886 | |
6887 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6888 | * the hw state checker will get angry at the mismatch. */ | |
6889 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6890 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6891 | |
609aeaca | 6892 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6893 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6894 | crtc_vtotal -= 1; |
6895 | crtc_vblank_end -= 1; | |
609aeaca | 6896 | |
2d84d2b3 | 6897 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6898 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6899 | else | |
6900 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6901 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6902 | if (vsyncshift < 0) |
6903 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6904 | } |
6905 | ||
6315b5d3 | 6906 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 6907 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6908 | |
fe2b8f9d | 6909 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6910 | (adjusted_mode->crtc_hdisplay - 1) | |
6911 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6912 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6913 | (adjusted_mode->crtc_hblank_start - 1) | |
6914 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6915 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6916 | (adjusted_mode->crtc_hsync_start - 1) | |
6917 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6918 | ||
fe2b8f9d | 6919 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6920 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6921 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6922 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6923 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6924 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6925 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6926 | (adjusted_mode->crtc_vsync_start - 1) | |
6927 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6928 | ||
b5e508d4 PZ |
6929 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6930 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6931 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6932 | * bits. */ | |
772c2a51 | 6933 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
6934 | (pipe == PIPE_B || pipe == PIPE_C)) |
6935 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6936 | ||
bc58be60 JN |
6937 | } |
6938 | ||
6939 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
6940 | { | |
6941 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 6942 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
6943 | enum pipe pipe = intel_crtc->pipe; |
6944 | ||
b0e77b9c PZ |
6945 | /* pipesrc controls the size that is scaled from, which should |
6946 | * always be the user's requested size. | |
6947 | */ | |
6948 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6949 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6950 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6951 | } |
6952 | ||
1bd1bd80 | 6953 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6954 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6955 | { |
6956 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6957 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
6958 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
6959 | uint32_t tmp; | |
6960 | ||
6961 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6962 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6963 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6964 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6965 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6966 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6967 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6968 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6969 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6970 | |
6971 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6972 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6973 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6974 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6975 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6976 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6977 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6978 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6979 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6980 | |
6981 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6982 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6983 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6984 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 6985 | } |
bc58be60 JN |
6986 | } |
6987 | ||
6988 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
6989 | struct intel_crtc_state *pipe_config) | |
6990 | { | |
6991 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6992 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 6993 | u32 tmp; |
1bd1bd80 DV |
6994 | |
6995 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6996 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6997 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6998 | ||
2d112de7 ACO |
6999 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7000 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7001 | } |
7002 | ||
f6a83288 | 7003 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7004 | struct intel_crtc_state *pipe_config) |
babea61d | 7005 | { |
2d112de7 ACO |
7006 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7007 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7008 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7009 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7010 | |
2d112de7 ACO |
7011 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7012 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7013 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7014 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7015 | |
2d112de7 | 7016 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7017 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7018 | |
2d112de7 | 7019 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
cd13f5ab ML |
7020 | |
7021 | mode->hsync = drm_mode_hsync(mode); | |
7022 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7023 | drm_mode_set_name(mode); | |
babea61d JB |
7024 | } |
7025 | ||
84b046f3 DV |
7026 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7027 | { | |
6315b5d3 | 7028 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
7029 | uint32_t pipeconf; |
7030 | ||
9f11a9e4 | 7031 | pipeconf = 0; |
84b046f3 | 7032 | |
b6b5d049 VS |
7033 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7034 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7035 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7036 | |
6e3c9717 | 7037 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7038 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7039 | |
ff9ce46e | 7040 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
7041 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7042 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 7043 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7044 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7045 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7046 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7047 | |
6e3c9717 | 7048 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7049 | case 18: |
7050 | pipeconf |= PIPECONF_6BPC; | |
7051 | break; | |
7052 | case 24: | |
7053 | pipeconf |= PIPECONF_8BPC; | |
7054 | break; | |
7055 | case 30: | |
7056 | pipeconf |= PIPECONF_10BPC; | |
7057 | break; | |
7058 | default: | |
7059 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7060 | BUG(); | |
84b046f3 DV |
7061 | } |
7062 | } | |
7063 | ||
56b857a5 | 7064 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
7065 | if (intel_crtc->lowfreq_avail) { |
7066 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7067 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7068 | } else { | |
7069 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7070 | } |
7071 | } | |
7072 | ||
6e3c9717 | 7073 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 7074 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 7075 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7076 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7077 | else | |
7078 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7079 | } else | |
84b046f3 DV |
7080 | pipeconf |= PIPECONF_PROGRESSIVE; |
7081 | ||
920a14b2 | 7082 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7083 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 7084 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7085 | |
84b046f3 DV |
7086 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7087 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7088 | } | |
7089 | ||
81c97f52 ACO |
7090 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7091 | struct intel_crtc_state *crtc_state) | |
7092 | { | |
7093 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7094 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7095 | const struct intel_limit *limit; |
81c97f52 ACO |
7096 | int refclk = 48000; |
7097 | ||
7098 | memset(&crtc_state->dpll_hw_state, 0, | |
7099 | sizeof(crtc_state->dpll_hw_state)); | |
7100 | ||
2d84d2b3 | 7101 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7102 | if (intel_panel_use_ssc(dev_priv)) { |
7103 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7104 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7105 | } | |
7106 | ||
7107 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7108 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7109 | limit = &intel_limits_i8xx_dvo; |
7110 | } else { | |
7111 | limit = &intel_limits_i8xx_dac; | |
7112 | } | |
7113 | ||
7114 | if (!crtc_state->clock_set && | |
7115 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7116 | refclk, NULL, &crtc_state->dpll)) { | |
7117 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7118 | return -EINVAL; | |
7119 | } | |
7120 | ||
7121 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7122 | ||
7123 | return 0; | |
7124 | } | |
7125 | ||
19ec6693 ACO |
7126 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7127 | struct intel_crtc_state *crtc_state) | |
7128 | { | |
7129 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7130 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7131 | const struct intel_limit *limit; |
19ec6693 ACO |
7132 | int refclk = 96000; |
7133 | ||
7134 | memset(&crtc_state->dpll_hw_state, 0, | |
7135 | sizeof(crtc_state->dpll_hw_state)); | |
7136 | ||
2d84d2b3 | 7137 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7138 | if (intel_panel_use_ssc(dev_priv)) { |
7139 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7140 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7141 | } | |
7142 | ||
7143 | if (intel_is_dual_link_lvds(dev)) | |
7144 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7145 | else | |
7146 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7147 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7148 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7149 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7150 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7151 | limit = &intel_limits_g4x_sdvo; |
7152 | } else { | |
7153 | /* The option is for other outputs */ | |
7154 | limit = &intel_limits_i9xx_sdvo; | |
7155 | } | |
7156 | ||
7157 | if (!crtc_state->clock_set && | |
7158 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7159 | refclk, NULL, &crtc_state->dpll)) { | |
7160 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7161 | return -EINVAL; | |
7162 | } | |
7163 | ||
7164 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7165 | ||
7166 | return 0; | |
7167 | } | |
7168 | ||
70e8aa21 ACO |
7169 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7170 | struct intel_crtc_state *crtc_state) | |
7171 | { | |
7172 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7173 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7174 | const struct intel_limit *limit; |
70e8aa21 ACO |
7175 | int refclk = 96000; |
7176 | ||
7177 | memset(&crtc_state->dpll_hw_state, 0, | |
7178 | sizeof(crtc_state->dpll_hw_state)); | |
7179 | ||
2d84d2b3 | 7180 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7181 | if (intel_panel_use_ssc(dev_priv)) { |
7182 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7183 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7184 | } | |
7185 | ||
7186 | limit = &intel_limits_pineview_lvds; | |
7187 | } else { | |
7188 | limit = &intel_limits_pineview_sdvo; | |
7189 | } | |
7190 | ||
7191 | if (!crtc_state->clock_set && | |
7192 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7193 | refclk, NULL, &crtc_state->dpll)) { | |
7194 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7195 | return -EINVAL; | |
7196 | } | |
7197 | ||
7198 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7199 | ||
7200 | return 0; | |
7201 | } | |
7202 | ||
190f68c5 ACO |
7203 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7204 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7205 | { |
c7653199 | 7206 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7207 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7208 | const struct intel_limit *limit; |
81c97f52 | 7209 | int refclk = 96000; |
79e53945 | 7210 | |
dd3cd74a ACO |
7211 | memset(&crtc_state->dpll_hw_state, 0, |
7212 | sizeof(crtc_state->dpll_hw_state)); | |
7213 | ||
2d84d2b3 | 7214 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7215 | if (intel_panel_use_ssc(dev_priv)) { |
7216 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7217 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7218 | } | |
43565a06 | 7219 | |
70e8aa21 ACO |
7220 | limit = &intel_limits_i9xx_lvds; |
7221 | } else { | |
7222 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7223 | } |
79e53945 | 7224 | |
70e8aa21 ACO |
7225 | if (!crtc_state->clock_set && |
7226 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7227 | refclk, NULL, &crtc_state->dpll)) { | |
7228 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7229 | return -EINVAL; | |
f47709a9 | 7230 | } |
7026d4ac | 7231 | |
81c97f52 | 7232 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7233 | |
c8f7a0db | 7234 | return 0; |
f564048e EA |
7235 | } |
7236 | ||
65b3d6a9 ACO |
7237 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7238 | struct intel_crtc_state *crtc_state) | |
7239 | { | |
7240 | int refclk = 100000; | |
1b6f4958 | 7241 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7242 | |
7243 | memset(&crtc_state->dpll_hw_state, 0, | |
7244 | sizeof(crtc_state->dpll_hw_state)); | |
7245 | ||
65b3d6a9 ACO |
7246 | if (!crtc_state->clock_set && |
7247 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7248 | refclk, NULL, &crtc_state->dpll)) { | |
7249 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7250 | return -EINVAL; | |
7251 | } | |
7252 | ||
7253 | chv_compute_dpll(crtc, crtc_state); | |
7254 | ||
7255 | return 0; | |
7256 | } | |
7257 | ||
7258 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7259 | struct intel_crtc_state *crtc_state) | |
7260 | { | |
7261 | int refclk = 100000; | |
1b6f4958 | 7262 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7263 | |
7264 | memset(&crtc_state->dpll_hw_state, 0, | |
7265 | sizeof(crtc_state->dpll_hw_state)); | |
7266 | ||
65b3d6a9 ACO |
7267 | if (!crtc_state->clock_set && |
7268 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7269 | refclk, NULL, &crtc_state->dpll)) { | |
7270 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7271 | return -EINVAL; | |
7272 | } | |
7273 | ||
7274 | vlv_compute_dpll(crtc, crtc_state); | |
7275 | ||
7276 | return 0; | |
7277 | } | |
7278 | ||
2fa2fe9a | 7279 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7280 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 7281 | { |
6315b5d3 | 7282 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
7283 | uint32_t tmp; |
7284 | ||
50a0bc90 TU |
7285 | if (INTEL_GEN(dev_priv) <= 3 && |
7286 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
7287 | return; |
7288 | ||
2fa2fe9a | 7289 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7290 | if (!(tmp & PFIT_ENABLE)) |
7291 | return; | |
2fa2fe9a | 7292 | |
06922821 | 7293 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 7294 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
7295 | if (crtc->pipe != PIPE_B) |
7296 | return; | |
2fa2fe9a DV |
7297 | } else { |
7298 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7299 | return; | |
7300 | } | |
7301 | ||
06922821 | 7302 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7303 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7304 | } |
7305 | ||
acbec814 | 7306 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7307 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7308 | { |
7309 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7310 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 7311 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 7312 | struct dpll clock; |
acbec814 | 7313 | u32 mdiv; |
662c6ecb | 7314 | int refclk = 100000; |
acbec814 | 7315 | |
b521973b VS |
7316 | /* In case of DSI, DPLL will not be used */ |
7317 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
7318 | return; |
7319 | ||
a580516d | 7320 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7321 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7322 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7323 | |
7324 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7325 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7326 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7327 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7328 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7329 | ||
dccbea3b | 7330 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7331 | } |
7332 | ||
5724dbd1 DL |
7333 | static void |
7334 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7335 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7336 | { |
7337 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7338 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
7339 | u32 val, base, offset; |
7340 | int pipe = crtc->pipe, plane = crtc->plane; | |
7341 | int fourcc, pixel_format; | |
6761dd31 | 7342 | unsigned int aligned_height; |
b113d5ee | 7343 | struct drm_framebuffer *fb; |
1b842c89 | 7344 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7345 | |
42a7b088 DL |
7346 | val = I915_READ(DSPCNTR(plane)); |
7347 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7348 | return; | |
7349 | ||
d9806c9f | 7350 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7351 | if (!intel_fb) { |
1ad292b5 JB |
7352 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7353 | return; | |
7354 | } | |
7355 | ||
1b842c89 DL |
7356 | fb = &intel_fb->base; |
7357 | ||
d2e9f5fc VS |
7358 | fb->dev = dev; |
7359 | ||
6315b5d3 | 7360 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 7361 | if (val & DISPPLANE_TILED) { |
49af449b | 7362 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 7363 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
7364 | } |
7365 | } | |
1ad292b5 JB |
7366 | |
7367 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7368 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 7369 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 7370 | |
6315b5d3 | 7371 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 7372 | if (plane_config->tiling) |
1ad292b5 JB |
7373 | offset = I915_READ(DSPTILEOFF(plane)); |
7374 | else | |
7375 | offset = I915_READ(DSPLINOFF(plane)); | |
7376 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7377 | } else { | |
7378 | base = I915_READ(DSPADDR(plane)); | |
7379 | } | |
7380 | plane_config->base = base; | |
7381 | ||
7382 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7383 | fb->width = ((val >> 16) & 0xfff) + 1; |
7384 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7385 | |
7386 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7387 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7388 | |
d88c4afd | 7389 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1ad292b5 | 7390 | |
f37b5c2b | 7391 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7392 | |
2844a921 DL |
7393 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7394 | pipe_name(pipe), plane, fb->width, fb->height, | |
272725c7 | 7395 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 7396 | plane_config->size); |
1ad292b5 | 7397 | |
2d14030b | 7398 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7399 | } |
7400 | ||
70b23a98 | 7401 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7402 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7403 | { |
7404 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7405 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
7406 | int pipe = pipe_config->cpu_transcoder; |
7407 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 7408 | struct dpll clock; |
0d7b6b11 | 7409 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
7410 | int refclk = 100000; |
7411 | ||
b521973b VS |
7412 | /* In case of DSI, DPLL will not be used */ |
7413 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7414 | return; | |
7415 | ||
a580516d | 7416 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7417 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7418 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7419 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7420 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 7421 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 7422 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7423 | |
7424 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
7425 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7426 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
7427 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
7428 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7429 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7430 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7431 | ||
dccbea3b | 7432 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
7433 | } |
7434 | ||
0e8ffe1b | 7435 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7436 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 7437 | { |
6315b5d3 | 7438 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 7439 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 7440 | uint32_t tmp; |
1729050e | 7441 | bool ret; |
0e8ffe1b | 7442 | |
1729050e ID |
7443 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
7444 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
7445 | return false; |
7446 | ||
e143a21c | 7447 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 7448 | pipe_config->shared_dpll = NULL; |
eccb140b | 7449 | |
1729050e ID |
7450 | ret = false; |
7451 | ||
0e8ffe1b DV |
7452 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7453 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 7454 | goto out; |
0e8ffe1b | 7455 | |
9beb5fea TU |
7456 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7457 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
7458 | switch (tmp & PIPECONF_BPC_MASK) { |
7459 | case PIPECONF_6BPC: | |
7460 | pipe_config->pipe_bpp = 18; | |
7461 | break; | |
7462 | case PIPECONF_8BPC: | |
7463 | pipe_config->pipe_bpp = 24; | |
7464 | break; | |
7465 | case PIPECONF_10BPC: | |
7466 | pipe_config->pipe_bpp = 30; | |
7467 | break; | |
7468 | default: | |
7469 | break; | |
7470 | } | |
7471 | } | |
7472 | ||
920a14b2 | 7473 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7474 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
7475 | pipe_config->limited_color_range = true; |
7476 | ||
6315b5d3 | 7477 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
7478 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
7479 | ||
1bd1bd80 | 7480 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 7481 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 7482 | |
2fa2fe9a DV |
7483 | i9xx_get_pfit_config(crtc, pipe_config); |
7484 | ||
6315b5d3 | 7485 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 7486 | /* No way to read it out on pipes B and C */ |
920a14b2 | 7487 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
7488 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
7489 | else | |
7490 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
7491 | pipe_config->pixel_multiplier = |
7492 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7493 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7494 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 7495 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 7496 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
7497 | tmp = I915_READ(DPLL(crtc->pipe)); |
7498 | pipe_config->pixel_multiplier = | |
7499 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7500 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7501 | } else { | |
7502 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7503 | * port and will be fixed up in the encoder->get_config | |
7504 | * function. */ | |
7505 | pipe_config->pixel_multiplier = 1; | |
7506 | } | |
8bcc2795 | 7507 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 7508 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
7509 | /* |
7510 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7511 | * on 830. Filter it out here so that we don't | |
7512 | * report errors due to that. | |
7513 | */ | |
50a0bc90 | 7514 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
7515 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
7516 | ||
8bcc2795 DV |
7517 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7518 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7519 | } else { |
7520 | /* Mask out read-only status bits. */ | |
7521 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7522 | DPLL_PORTC_READY_MASK | | |
7523 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7524 | } |
6c49f241 | 7525 | |
920a14b2 | 7526 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 7527 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 7528 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
7529 | vlv_crtc_clock_get(crtc, pipe_config); |
7530 | else | |
7531 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7532 | |
0f64614d VS |
7533 | /* |
7534 | * Normally the dotclock is filled in by the encoder .get_config() | |
7535 | * but in case the pipe is enabled w/o any ports we need a sane | |
7536 | * default. | |
7537 | */ | |
7538 | pipe_config->base.adjusted_mode.crtc_clock = | |
7539 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
7540 | ||
1729050e ID |
7541 | ret = true; |
7542 | ||
7543 | out: | |
7544 | intel_display_power_put(dev_priv, power_domain); | |
7545 | ||
7546 | return ret; | |
0e8ffe1b DV |
7547 | } |
7548 | ||
c39055b0 | 7549 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 7550 | { |
13d83a67 | 7551 | struct intel_encoder *encoder; |
1c1a24d2 | 7552 | int i; |
74cfd7ac | 7553 | u32 val, final; |
13d83a67 | 7554 | bool has_lvds = false; |
199e5d79 | 7555 | bool has_cpu_edp = false; |
199e5d79 | 7556 | bool has_panel = false; |
99eb6a01 KP |
7557 | bool has_ck505 = false; |
7558 | bool can_ssc = false; | |
1c1a24d2 | 7559 | bool using_ssc_source = false; |
13d83a67 JB |
7560 | |
7561 | /* We need to take the global config into account */ | |
c39055b0 | 7562 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
7563 | switch (encoder->type) { |
7564 | case INTEL_OUTPUT_LVDS: | |
7565 | has_panel = true; | |
7566 | has_lvds = true; | |
7567 | break; | |
7568 | case INTEL_OUTPUT_EDP: | |
7569 | has_panel = true; | |
2de6905f | 7570 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7571 | has_cpu_edp = true; |
7572 | break; | |
6847d71b PZ |
7573 | default: |
7574 | break; | |
13d83a67 JB |
7575 | } |
7576 | } | |
7577 | ||
6e266956 | 7578 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 7579 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7580 | can_ssc = has_ck505; |
7581 | } else { | |
7582 | has_ck505 = false; | |
7583 | can_ssc = true; | |
7584 | } | |
7585 | ||
1c1a24d2 L |
7586 | /* Check if any DPLLs are using the SSC source */ |
7587 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
7588 | u32 temp = I915_READ(PCH_DPLL(i)); | |
7589 | ||
7590 | if (!(temp & DPLL_VCO_ENABLE)) | |
7591 | continue; | |
7592 | ||
7593 | if ((temp & PLL_REF_INPUT_MASK) == | |
7594 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7595 | using_ssc_source = true; | |
7596 | break; | |
7597 | } | |
7598 | } | |
7599 | ||
7600 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
7601 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
7602 | |
7603 | /* Ironlake: try to setup display ref clock before DPLL | |
7604 | * enabling. This is only under driver's control after | |
7605 | * PCH B stepping, previous chipset stepping should be | |
7606 | * ignoring this setting. | |
7607 | */ | |
74cfd7ac CW |
7608 | val = I915_READ(PCH_DREF_CONTROL); |
7609 | ||
7610 | /* As we must carefully and slowly disable/enable each source in turn, | |
7611 | * compute the final state we want first and check if we need to | |
7612 | * make any changes at all. | |
7613 | */ | |
7614 | final = val; | |
7615 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7616 | if (has_ck505) | |
7617 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7618 | else | |
7619 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7620 | ||
8c07eb68 | 7621 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 7622 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 7623 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
7624 | |
7625 | if (has_panel) { | |
7626 | final |= DREF_SSC_SOURCE_ENABLE; | |
7627 | ||
7628 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7629 | final |= DREF_SSC1_ENABLE; | |
7630 | ||
7631 | if (has_cpu_edp) { | |
7632 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7633 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7634 | else | |
7635 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7636 | } else | |
7637 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
7638 | } else if (using_ssc_source) { |
7639 | final |= DREF_SSC_SOURCE_ENABLE; | |
7640 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
7641 | } |
7642 | ||
7643 | if (final == val) | |
7644 | return; | |
7645 | ||
13d83a67 | 7646 | /* Always enable nonspread source */ |
74cfd7ac | 7647 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7648 | |
99eb6a01 | 7649 | if (has_ck505) |
74cfd7ac | 7650 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7651 | else |
74cfd7ac | 7652 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7653 | |
199e5d79 | 7654 | if (has_panel) { |
74cfd7ac CW |
7655 | val &= ~DREF_SSC_SOURCE_MASK; |
7656 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7657 | |
199e5d79 | 7658 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7659 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7660 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7661 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7662 | } else |
74cfd7ac | 7663 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7664 | |
7665 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7666 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7667 | POSTING_READ(PCH_DREF_CONTROL); |
7668 | udelay(200); | |
7669 | ||
74cfd7ac | 7670 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7671 | |
7672 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7673 | if (has_cpu_edp) { |
99eb6a01 | 7674 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7675 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7676 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7677 | } else |
74cfd7ac | 7678 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7679 | } else |
74cfd7ac | 7680 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7681 | |
74cfd7ac | 7682 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7683 | POSTING_READ(PCH_DREF_CONTROL); |
7684 | udelay(200); | |
7685 | } else { | |
1c1a24d2 | 7686 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 7687 | |
74cfd7ac | 7688 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7689 | |
7690 | /* Turn off CPU output */ | |
74cfd7ac | 7691 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7692 | |
74cfd7ac | 7693 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7694 | POSTING_READ(PCH_DREF_CONTROL); |
7695 | udelay(200); | |
7696 | ||
1c1a24d2 L |
7697 | if (!using_ssc_source) { |
7698 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 7699 | |
1c1a24d2 L |
7700 | /* Turn off the SSC source */ |
7701 | val &= ~DREF_SSC_SOURCE_MASK; | |
7702 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 7703 | |
1c1a24d2 L |
7704 | /* Turn off SSC1 */ |
7705 | val &= ~DREF_SSC1_ENABLE; | |
7706 | ||
7707 | I915_WRITE(PCH_DREF_CONTROL, val); | |
7708 | POSTING_READ(PCH_DREF_CONTROL); | |
7709 | udelay(200); | |
7710 | } | |
13d83a67 | 7711 | } |
74cfd7ac CW |
7712 | |
7713 | BUG_ON(val != final); | |
13d83a67 JB |
7714 | } |
7715 | ||
f31f2d55 | 7716 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7717 | { |
f31f2d55 | 7718 | uint32_t tmp; |
dde86e2d | 7719 | |
0ff066a9 PZ |
7720 | tmp = I915_READ(SOUTH_CHICKEN2); |
7721 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7722 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7723 | |
cf3598c2 ID |
7724 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
7725 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 7726 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 7727 | |
0ff066a9 PZ |
7728 | tmp = I915_READ(SOUTH_CHICKEN2); |
7729 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7730 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7731 | |
cf3598c2 ID |
7732 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
7733 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 7734 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
7735 | } |
7736 | ||
7737 | /* WaMPhyProgramming:hsw */ | |
7738 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7739 | { | |
7740 | uint32_t tmp; | |
dde86e2d PZ |
7741 | |
7742 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7743 | tmp &= ~(0xFF << 24); | |
7744 | tmp |= (0x12 << 24); | |
7745 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7746 | ||
dde86e2d PZ |
7747 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7748 | tmp |= (1 << 11); | |
7749 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7750 | ||
7751 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7752 | tmp |= (1 << 11); | |
7753 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7754 | ||
dde86e2d PZ |
7755 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7756 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7757 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7758 | ||
7759 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7760 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7761 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7762 | ||
0ff066a9 PZ |
7763 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7764 | tmp &= ~(7 << 13); | |
7765 | tmp |= (5 << 13); | |
7766 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7767 | |
0ff066a9 PZ |
7768 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7769 | tmp &= ~(7 << 13); | |
7770 | tmp |= (5 << 13); | |
7771 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7772 | |
7773 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7774 | tmp &= ~0xFF; | |
7775 | tmp |= 0x1C; | |
7776 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7777 | ||
7778 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7779 | tmp &= ~0xFF; | |
7780 | tmp |= 0x1C; | |
7781 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7782 | ||
7783 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7784 | tmp &= ~(0xFF << 16); | |
7785 | tmp |= (0x1C << 16); | |
7786 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7787 | ||
7788 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7789 | tmp &= ~(0xFF << 16); | |
7790 | tmp |= (0x1C << 16); | |
7791 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7792 | ||
0ff066a9 PZ |
7793 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7794 | tmp |= (1 << 27); | |
7795 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7796 | |
0ff066a9 PZ |
7797 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7798 | tmp |= (1 << 27); | |
7799 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7800 | |
0ff066a9 PZ |
7801 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7802 | tmp &= ~(0xF << 28); | |
7803 | tmp |= (4 << 28); | |
7804 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7805 | |
0ff066a9 PZ |
7806 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7807 | tmp &= ~(0xF << 28); | |
7808 | tmp |= (4 << 28); | |
7809 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7810 | } |
7811 | ||
2fa86a1f PZ |
7812 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7813 | * Programming" based on the parameters passed: | |
7814 | * - Sequence to enable CLKOUT_DP | |
7815 | * - Sequence to enable CLKOUT_DP without spread | |
7816 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7817 | */ | |
c39055b0 ACO |
7818 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
7819 | bool with_spread, bool with_fdi) | |
f31f2d55 | 7820 | { |
2fa86a1f PZ |
7821 | uint32_t reg, tmp; |
7822 | ||
7823 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7824 | with_spread = true; | |
4f8036a2 TU |
7825 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
7826 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 7827 | with_fdi = false; |
f31f2d55 | 7828 | |
a580516d | 7829 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
7830 | |
7831 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7832 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7833 | tmp |= SBI_SSCCTL_PATHALT; | |
7834 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7835 | ||
7836 | udelay(24); | |
7837 | ||
2fa86a1f PZ |
7838 | if (with_spread) { |
7839 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7840 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7841 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7842 | |
2fa86a1f PZ |
7843 | if (with_fdi) { |
7844 | lpt_reset_fdi_mphy(dev_priv); | |
7845 | lpt_program_fdi_mphy(dev_priv); | |
7846 | } | |
7847 | } | |
dde86e2d | 7848 | |
4f8036a2 | 7849 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
7850 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7851 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7852 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 7853 | |
a580516d | 7854 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
7855 | } |
7856 | ||
47701c3b | 7857 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 7858 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 7859 | { |
47701c3b PZ |
7860 | uint32_t reg, tmp; |
7861 | ||
a580516d | 7862 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 7863 | |
4f8036a2 | 7864 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
7865 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7866 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7867 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7868 | ||
7869 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7870 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7871 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7872 | tmp |= SBI_SSCCTL_PATHALT; | |
7873 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7874 | udelay(32); | |
7875 | } | |
7876 | tmp |= SBI_SSCCTL_DISABLE; | |
7877 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7878 | } | |
7879 | ||
a580516d | 7880 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
7881 | } |
7882 | ||
f7be2c21 VS |
7883 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
7884 | ||
7885 | static const uint16_t sscdivintphase[] = { | |
7886 | [BEND_IDX( 50)] = 0x3B23, | |
7887 | [BEND_IDX( 45)] = 0x3B23, | |
7888 | [BEND_IDX( 40)] = 0x3C23, | |
7889 | [BEND_IDX( 35)] = 0x3C23, | |
7890 | [BEND_IDX( 30)] = 0x3D23, | |
7891 | [BEND_IDX( 25)] = 0x3D23, | |
7892 | [BEND_IDX( 20)] = 0x3E23, | |
7893 | [BEND_IDX( 15)] = 0x3E23, | |
7894 | [BEND_IDX( 10)] = 0x3F23, | |
7895 | [BEND_IDX( 5)] = 0x3F23, | |
7896 | [BEND_IDX( 0)] = 0x0025, | |
7897 | [BEND_IDX( -5)] = 0x0025, | |
7898 | [BEND_IDX(-10)] = 0x0125, | |
7899 | [BEND_IDX(-15)] = 0x0125, | |
7900 | [BEND_IDX(-20)] = 0x0225, | |
7901 | [BEND_IDX(-25)] = 0x0225, | |
7902 | [BEND_IDX(-30)] = 0x0325, | |
7903 | [BEND_IDX(-35)] = 0x0325, | |
7904 | [BEND_IDX(-40)] = 0x0425, | |
7905 | [BEND_IDX(-45)] = 0x0425, | |
7906 | [BEND_IDX(-50)] = 0x0525, | |
7907 | }; | |
7908 | ||
7909 | /* | |
7910 | * Bend CLKOUT_DP | |
7911 | * steps -50 to 50 inclusive, in steps of 5 | |
7912 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
7913 | * change in clock period = -(steps / 10) * 5.787 ps | |
7914 | */ | |
7915 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
7916 | { | |
7917 | uint32_t tmp; | |
7918 | int idx = BEND_IDX(steps); | |
7919 | ||
7920 | if (WARN_ON(steps % 5 != 0)) | |
7921 | return; | |
7922 | ||
7923 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
7924 | return; | |
7925 | ||
7926 | mutex_lock(&dev_priv->sb_lock); | |
7927 | ||
7928 | if (steps % 10 != 0) | |
7929 | tmp = 0xAAAAAAAB; | |
7930 | else | |
7931 | tmp = 0x00000000; | |
7932 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
7933 | ||
7934 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
7935 | tmp &= 0xffff0000; | |
7936 | tmp |= sscdivintphase[idx]; | |
7937 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
7938 | ||
7939 | mutex_unlock(&dev_priv->sb_lock); | |
7940 | } | |
7941 | ||
7942 | #undef BEND_IDX | |
7943 | ||
c39055b0 | 7944 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 7945 | { |
bf8fa3d3 PZ |
7946 | struct intel_encoder *encoder; |
7947 | bool has_vga = false; | |
7948 | ||
c39055b0 | 7949 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
7950 | switch (encoder->type) { |
7951 | case INTEL_OUTPUT_ANALOG: | |
7952 | has_vga = true; | |
7953 | break; | |
6847d71b PZ |
7954 | default: |
7955 | break; | |
bf8fa3d3 PZ |
7956 | } |
7957 | } | |
7958 | ||
f7be2c21 | 7959 | if (has_vga) { |
c39055b0 ACO |
7960 | lpt_bend_clkout_dp(dev_priv, 0); |
7961 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 7962 | } else { |
c39055b0 | 7963 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 7964 | } |
bf8fa3d3 PZ |
7965 | } |
7966 | ||
dde86e2d PZ |
7967 | /* |
7968 | * Initialize reference clocks when the driver loads | |
7969 | */ | |
c39055b0 | 7970 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 7971 | { |
6e266956 | 7972 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 7973 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 7974 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 7975 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
7976 | } |
7977 | ||
6ff93609 | 7978 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7979 | { |
fac5e23e | 7980 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
7981 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7982 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7983 | uint32_t val; |
7984 | ||
78114071 | 7985 | val = 0; |
c8203565 | 7986 | |
6e3c9717 | 7987 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7988 | case 18: |
dfd07d72 | 7989 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7990 | break; |
7991 | case 24: | |
dfd07d72 | 7992 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7993 | break; |
7994 | case 30: | |
dfd07d72 | 7995 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7996 | break; |
7997 | case 36: | |
dfd07d72 | 7998 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7999 | break; |
8000 | default: | |
cc769b62 PZ |
8001 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8002 | BUG(); | |
c8203565 PZ |
8003 | } |
8004 | ||
6e3c9717 | 8005 | if (intel_crtc->config->dither) |
c8203565 PZ |
8006 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8007 | ||
6e3c9717 | 8008 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8009 | val |= PIPECONF_INTERLACED_ILK; |
8010 | else | |
8011 | val |= PIPECONF_PROGRESSIVE; | |
8012 | ||
6e3c9717 | 8013 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8014 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8015 | |
c8203565 PZ |
8016 | I915_WRITE(PIPECONF(pipe), val); |
8017 | POSTING_READ(PIPECONF(pipe)); | |
8018 | } | |
8019 | ||
6ff93609 | 8020 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8021 | { |
fac5e23e | 8022 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8023 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8024 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8025 | u32 val = 0; |
ee2b0b38 | 8026 | |
391bf048 | 8027 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8028 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8029 | ||
6e3c9717 | 8030 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8031 | val |= PIPECONF_INTERLACED_ILK; |
8032 | else | |
8033 | val |= PIPECONF_PROGRESSIVE; | |
8034 | ||
702e7a56 PZ |
8035 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8036 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8037 | } |
8038 | ||
391bf048 JN |
8039 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8040 | { | |
fac5e23e | 8041 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8043 | |
391bf048 JN |
8044 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8045 | u32 val = 0; | |
756f85cf | 8046 | |
6e3c9717 | 8047 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8048 | case 18: |
8049 | val |= PIPEMISC_DITHER_6_BPC; | |
8050 | break; | |
8051 | case 24: | |
8052 | val |= PIPEMISC_DITHER_8_BPC; | |
8053 | break; | |
8054 | case 30: | |
8055 | val |= PIPEMISC_DITHER_10_BPC; | |
8056 | break; | |
8057 | case 36: | |
8058 | val |= PIPEMISC_DITHER_12_BPC; | |
8059 | break; | |
8060 | default: | |
8061 | /* Case prevented by pipe_config_set_bpp. */ | |
8062 | BUG(); | |
8063 | } | |
8064 | ||
6e3c9717 | 8065 | if (intel_crtc->config->dither) |
756f85cf PZ |
8066 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8067 | ||
391bf048 | 8068 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8069 | } |
ee2b0b38 PZ |
8070 | } |
8071 | ||
d4b1931c PZ |
8072 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8073 | { | |
8074 | /* | |
8075 | * Account for spread spectrum to avoid | |
8076 | * oversubscribing the link. Max center spread | |
8077 | * is 2.5%; use 5% for safety's sake. | |
8078 | */ | |
8079 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8080 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8081 | } |
8082 | ||
7429e9d4 | 8083 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8084 | { |
7429e9d4 | 8085 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8086 | } |
8087 | ||
b75ca6f6 ACO |
8088 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8089 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8090 | struct dpll *reduced_clock) |
79e53945 | 8091 | { |
de13a2e3 | 8092 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8093 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8094 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8095 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8096 | int factor; |
79e53945 | 8097 | |
c1858123 | 8098 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8099 | factor = 21; |
3d6e9ee0 | 8100 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8101 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8102 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 8103 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8104 | factor = 25; |
190f68c5 | 8105 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8106 | factor = 20; |
c1858123 | 8107 | |
b75ca6f6 ACO |
8108 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8109 | ||
190f68c5 | 8110 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8111 | fp |= FP_CB_TUNE; |
8112 | ||
8113 | if (reduced_clock) { | |
8114 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8115 | |
b75ca6f6 ACO |
8116 | if (reduced_clock->m < factor * reduced_clock->n) |
8117 | fp2 |= FP_CB_TUNE; | |
8118 | } else { | |
8119 | fp2 = fp; | |
8120 | } | |
9a7c7890 | 8121 | |
5eddb70b | 8122 | dpll = 0; |
2c07245f | 8123 | |
3d6e9ee0 | 8124 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8125 | dpll |= DPLLB_MODE_LVDS; |
8126 | else | |
8127 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8128 | |
190f68c5 | 8129 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8130 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8131 | |
3d6e9ee0 VS |
8132 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8133 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8134 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8135 | |
37a5650b | 8136 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8137 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8138 | |
7d7f8633 VS |
8139 | /* |
8140 | * The high speed IO clock is only really required for | |
8141 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
8142 | * possible to share the DPLL between CRT and HDMI. Enabling | |
8143 | * the clock needlessly does no real harm, except use up a | |
8144 | * bit of power potentially. | |
8145 | * | |
8146 | * We'll limit this to IVB with 3 pipes, since it has only two | |
8147 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
8148 | * driving PCH ports at the same time. On SNB we could do this, | |
8149 | * and potentially avoid enabling the second DPLL, but it's not | |
8150 | * clear if it''s a win or loss power wise. No point in doing | |
8151 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
8152 | */ | |
8153 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
8154 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
8155 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8156 | ||
a07d6787 | 8157 | /* compute bitmask from p1 value */ |
190f68c5 | 8158 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8159 | /* also FPA1 */ |
190f68c5 | 8160 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8161 | |
190f68c5 | 8162 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8163 | case 5: |
8164 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8165 | break; | |
8166 | case 7: | |
8167 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8168 | break; | |
8169 | case 10: | |
8170 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8171 | break; | |
8172 | case 14: | |
8173 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8174 | break; | |
79e53945 JB |
8175 | } |
8176 | ||
3d6e9ee0 VS |
8177 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8178 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8179 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8180 | else |
8181 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8182 | ||
b75ca6f6 ACO |
8183 | dpll |= DPLL_VCO_ENABLE; |
8184 | ||
8185 | crtc_state->dpll_hw_state.dpll = dpll; | |
8186 | crtc_state->dpll_hw_state.fp0 = fp; | |
8187 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8188 | } |
8189 | ||
190f68c5 ACO |
8190 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8191 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8192 | { |
997c030c | 8193 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8194 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8195 | const struct intel_limit *limit; |
997c030c | 8196 | int refclk = 120000; |
de13a2e3 | 8197 | |
dd3cd74a ACO |
8198 | memset(&crtc_state->dpll_hw_state, 0, |
8199 | sizeof(crtc_state->dpll_hw_state)); | |
8200 | ||
ded220e2 ACO |
8201 | crtc->lowfreq_avail = false; |
8202 | ||
8203 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8204 | if (!crtc_state->has_pch_encoder) | |
8205 | return 0; | |
79e53945 | 8206 | |
2d84d2b3 | 8207 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8208 | if (intel_panel_use_ssc(dev_priv)) { |
8209 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8210 | dev_priv->vbt.lvds_ssc_freq); | |
8211 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8212 | } | |
8213 | ||
8214 | if (intel_is_dual_link_lvds(dev)) { | |
8215 | if (refclk == 100000) | |
8216 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8217 | else | |
8218 | limit = &intel_limits_ironlake_dual_lvds; | |
8219 | } else { | |
8220 | if (refclk == 100000) | |
8221 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8222 | else | |
8223 | limit = &intel_limits_ironlake_single_lvds; | |
8224 | } | |
8225 | } else { | |
8226 | limit = &intel_limits_ironlake_dac; | |
8227 | } | |
8228 | ||
364ee29d | 8229 | if (!crtc_state->clock_set && |
997c030c ACO |
8230 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8231 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8232 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8233 | return -EINVAL; | |
f47709a9 | 8234 | } |
79e53945 | 8235 | |
cbaa3315 | 8236 | ironlake_compute_dpll(crtc, crtc_state, NULL); |
66e985c0 | 8237 | |
efd38b68 | 8238 | if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) { |
ded220e2 ACO |
8239 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
8240 | pipe_name(crtc->pipe)); | |
8241 | return -EINVAL; | |
3fb37703 | 8242 | } |
79e53945 | 8243 | |
c8f7a0db | 8244 | return 0; |
79e53945 JB |
8245 | } |
8246 | ||
eb14cb74 VS |
8247 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8248 | struct intel_link_m_n *m_n) | |
8249 | { | |
8250 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8251 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
8252 | enum pipe pipe = crtc->pipe; |
8253 | ||
8254 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8255 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8256 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8257 | & ~TU_SIZE_MASK; | |
8258 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8259 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8260 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8261 | } | |
8262 | ||
8263 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8264 | enum transcoder transcoder, | |
b95af8be VK |
8265 | struct intel_link_m_n *m_n, |
8266 | struct intel_link_m_n *m2_n2) | |
72419203 | 8267 | { |
6315b5d3 | 8268 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 8269 | enum pipe pipe = crtc->pipe; |
72419203 | 8270 | |
6315b5d3 | 8271 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
8272 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
8273 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8274 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8275 | & ~TU_SIZE_MASK; | |
8276 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8277 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8278 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8279 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8280 | * gen < 8) and if DRRS is supported (to make sure the | |
8281 | * registers are not unnecessarily read). | |
8282 | */ | |
6315b5d3 | 8283 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 8284 | crtc->config->has_drrs) { |
b95af8be VK |
8285 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8286 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8287 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8288 | & ~TU_SIZE_MASK; | |
8289 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8290 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8291 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8292 | } | |
eb14cb74 VS |
8293 | } else { |
8294 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8295 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8296 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8297 | & ~TU_SIZE_MASK; | |
8298 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8299 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8300 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8301 | } | |
8302 | } | |
8303 | ||
8304 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8305 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8306 | { |
681a8504 | 8307 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8308 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8309 | else | |
8310 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8311 | &pipe_config->dp_m_n, |
8312 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8313 | } |
72419203 | 8314 | |
eb14cb74 | 8315 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8316 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8317 | { |
8318 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8319 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8320 | } |
8321 | ||
bd2e244f | 8322 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8323 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8324 | { |
8325 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8326 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
8327 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8328 | uint32_t ps_ctrl = 0; | |
8329 | int id = -1; | |
8330 | int i; | |
bd2e244f | 8331 | |
a1b2278e CK |
8332 | /* find scaler attached to this pipe */ |
8333 | for (i = 0; i < crtc->num_scalers; i++) { | |
8334 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8335 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8336 | id = i; | |
8337 | pipe_config->pch_pfit.enabled = true; | |
8338 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8339 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8340 | break; | |
8341 | } | |
8342 | } | |
bd2e244f | 8343 | |
a1b2278e CK |
8344 | scaler_state->scaler_id = id; |
8345 | if (id >= 0) { | |
8346 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8347 | } else { | |
8348 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8349 | } |
8350 | } | |
8351 | ||
5724dbd1 DL |
8352 | static void |
8353 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8354 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8355 | { |
8356 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8357 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 8358 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8359 | int pipe = crtc->pipe; |
8360 | int fourcc, pixel_format; | |
6761dd31 | 8361 | unsigned int aligned_height; |
bc8d7dff | 8362 | struct drm_framebuffer *fb; |
1b842c89 | 8363 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8364 | |
d9806c9f | 8365 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8366 | if (!intel_fb) { |
bc8d7dff DL |
8367 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8368 | return; | |
8369 | } | |
8370 | ||
1b842c89 DL |
8371 | fb = &intel_fb->base; |
8372 | ||
d2e9f5fc VS |
8373 | fb->dev = dev; |
8374 | ||
bc8d7dff | 8375 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8376 | if (!(val & PLANE_CTL_ENABLE)) |
8377 | goto error; | |
8378 | ||
bc8d7dff DL |
8379 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8380 | fourcc = skl_format_to_fourcc(pixel_format, | |
8381 | val & PLANE_CTL_ORDER_RGBX, | |
8382 | val & PLANE_CTL_ALPHA_MASK); | |
2f3f4763 | 8383 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 8384 | |
40f46283 DL |
8385 | tiling = val & PLANE_CTL_TILED_MASK; |
8386 | switch (tiling) { | |
8387 | case PLANE_CTL_TILED_LINEAR: | |
2f075565 | 8388 | fb->modifier = DRM_FORMAT_MOD_LINEAR; |
40f46283 DL |
8389 | break; |
8390 | case PLANE_CTL_TILED_X: | |
8391 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 8392 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
8393 | break; |
8394 | case PLANE_CTL_TILED_Y: | |
bae781b2 | 8395 | fb->modifier = I915_FORMAT_MOD_Y_TILED; |
40f46283 DL |
8396 | break; |
8397 | case PLANE_CTL_TILED_YF: | |
bae781b2 | 8398 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; |
40f46283 DL |
8399 | break; |
8400 | default: | |
8401 | MISSING_CASE(tiling); | |
8402 | goto error; | |
8403 | } | |
8404 | ||
bc8d7dff DL |
8405 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8406 | plane_config->base = base; | |
8407 | ||
8408 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8409 | ||
8410 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8411 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8412 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8413 | ||
8414 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
d88c4afd | 8415 | stride_mult = intel_fb_stride_alignment(fb, 0); |
bc8d7dff DL |
8416 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8417 | ||
d88c4afd | 8418 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
bc8d7dff | 8419 | |
f37b5c2b | 8420 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8421 | |
8422 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8423 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8424 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
bc8d7dff DL |
8425 | plane_config->size); |
8426 | ||
2d14030b | 8427 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8428 | return; |
8429 | ||
8430 | error: | |
d1a3a036 | 8431 | kfree(intel_fb); |
bc8d7dff DL |
8432 | } |
8433 | ||
2fa2fe9a | 8434 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8435 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8436 | { |
8437 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8438 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8439 | uint32_t tmp; |
8440 | ||
8441 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8442 | ||
8443 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8444 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8445 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8446 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8447 | |
8448 | /* We currently do not free assignements of panel fitters on | |
8449 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8450 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 8451 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
8452 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
8453 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8454 | } | |
2fa2fe9a | 8455 | } |
79e53945 JB |
8456 | } |
8457 | ||
5724dbd1 DL |
8458 | static void |
8459 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8460 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8461 | { |
8462 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8463 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 8464 | u32 val, base, offset; |
aeee5a49 | 8465 | int pipe = crtc->pipe; |
4c6baa59 | 8466 | int fourcc, pixel_format; |
6761dd31 | 8467 | unsigned int aligned_height; |
b113d5ee | 8468 | struct drm_framebuffer *fb; |
1b842c89 | 8469 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8470 | |
42a7b088 DL |
8471 | val = I915_READ(DSPCNTR(pipe)); |
8472 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8473 | return; | |
8474 | ||
d9806c9f | 8475 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8476 | if (!intel_fb) { |
4c6baa59 JB |
8477 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8478 | return; | |
8479 | } | |
8480 | ||
1b842c89 DL |
8481 | fb = &intel_fb->base; |
8482 | ||
d2e9f5fc VS |
8483 | fb->dev = dev; |
8484 | ||
6315b5d3 | 8485 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8486 | if (val & DISPPLANE_TILED) { |
49af449b | 8487 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8488 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8489 | } |
8490 | } | |
4c6baa59 JB |
8491 | |
8492 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8493 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 8494 | fb->format = drm_format_info(fourcc); |
4c6baa59 | 8495 | |
aeee5a49 | 8496 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 8497 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 8498 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8499 | } else { |
49af449b | 8500 | if (plane_config->tiling) |
aeee5a49 | 8501 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8502 | else |
aeee5a49 | 8503 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8504 | } |
8505 | plane_config->base = base; | |
8506 | ||
8507 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8508 | fb->width = ((val >> 16) & 0xfff) + 1; |
8509 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8510 | |
8511 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8512 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8513 | |
d88c4afd | 8514 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
4c6baa59 | 8515 | |
f37b5c2b | 8516 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8517 | |
2844a921 DL |
8518 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8519 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8520 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 8521 | plane_config->size); |
b113d5ee | 8522 | |
2d14030b | 8523 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8524 | } |
8525 | ||
0e8ffe1b | 8526 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8527 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8528 | { |
8529 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8530 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8531 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8532 | uint32_t tmp; |
1729050e | 8533 | bool ret; |
0e8ffe1b | 8534 | |
1729050e ID |
8535 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8536 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
8537 | return false; |
8538 | ||
e143a21c | 8539 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8540 | pipe_config->shared_dpll = NULL; |
eccb140b | 8541 | |
1729050e | 8542 | ret = false; |
0e8ffe1b DV |
8543 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8544 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8545 | goto out; |
0e8ffe1b | 8546 | |
42571aef VS |
8547 | switch (tmp & PIPECONF_BPC_MASK) { |
8548 | case PIPECONF_6BPC: | |
8549 | pipe_config->pipe_bpp = 18; | |
8550 | break; | |
8551 | case PIPECONF_8BPC: | |
8552 | pipe_config->pipe_bpp = 24; | |
8553 | break; | |
8554 | case PIPECONF_10BPC: | |
8555 | pipe_config->pipe_bpp = 30; | |
8556 | break; | |
8557 | case PIPECONF_12BPC: | |
8558 | pipe_config->pipe_bpp = 36; | |
8559 | break; | |
8560 | default: | |
8561 | break; | |
8562 | } | |
8563 | ||
b5a9fa09 DV |
8564 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8565 | pipe_config->limited_color_range = true; | |
8566 | ||
ab9412ba | 8567 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 8568 | struct intel_shared_dpll *pll; |
8106ddbd | 8569 | enum intel_dpll_id pll_id; |
66e985c0 | 8570 | |
88adfff1 DV |
8571 | pipe_config->has_pch_encoder = true; |
8572 | ||
627eb5a3 DV |
8573 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8574 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8575 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8576 | |
8577 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8578 | |
2d1fe073 | 8579 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
8580 | /* |
8581 | * The pipe->pch transcoder and pch transcoder->pll | |
8582 | * mapping is fixed. | |
8583 | */ | |
8106ddbd | 8584 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
8585 | } else { |
8586 | tmp = I915_READ(PCH_DPLL_SEL); | |
8587 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 8588 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 8589 | else |
8106ddbd | 8590 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 8591 | } |
66e985c0 | 8592 | |
8106ddbd ACO |
8593 | pipe_config->shared_dpll = |
8594 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
8595 | pll = pipe_config->shared_dpll; | |
66e985c0 | 8596 | |
2edd6443 ACO |
8597 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8598 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8599 | |
8600 | tmp = pipe_config->dpll_hw_state.dpll; | |
8601 | pipe_config->pixel_multiplier = | |
8602 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8603 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8604 | |
8605 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8606 | } else { |
8607 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8608 | } |
8609 | ||
1bd1bd80 | 8610 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8611 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8612 | |
2fa2fe9a DV |
8613 | ironlake_get_pfit_config(crtc, pipe_config); |
8614 | ||
1729050e ID |
8615 | ret = true; |
8616 | ||
8617 | out: | |
8618 | intel_display_power_put(dev_priv, power_domain); | |
8619 | ||
8620 | return ret; | |
0e8ffe1b DV |
8621 | } |
8622 | ||
be256dc7 PZ |
8623 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8624 | { | |
91c8a326 | 8625 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 8626 | struct intel_crtc *crtc; |
be256dc7 | 8627 | |
d3fcc808 | 8628 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8629 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8630 | pipe_name(crtc->pipe)); |
8631 | ||
e2c719b7 RC |
8632 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8633 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
8634 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
8635 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 8636 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 8637 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 8638 | "CPU PWM1 enabled\n"); |
772c2a51 | 8639 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 8640 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8641 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8642 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8643 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8644 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8645 | "Utility pin enabled\n"); |
e2c719b7 | 8646 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8647 | |
9926ada1 PZ |
8648 | /* |
8649 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8650 | * interrupts remain enabled. We used to check for that, but since it's | |
8651 | * gen-specific and since we only disable LCPLL after we fully disable | |
8652 | * the interrupts, the check below should be enough. | |
8653 | */ | |
e2c719b7 | 8654 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8655 | } |
8656 | ||
9ccd5aeb PZ |
8657 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8658 | { | |
772c2a51 | 8659 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
8660 | return I915_READ(D_COMP_HSW); |
8661 | else | |
8662 | return I915_READ(D_COMP_BDW); | |
8663 | } | |
8664 | ||
3c4c9b81 PZ |
8665 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8666 | { | |
772c2a51 | 8667 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
8668 | mutex_lock(&dev_priv->rps.hw_lock); |
8669 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8670 | val)) | |
79cf219a | 8671 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8672 | mutex_unlock(&dev_priv->rps.hw_lock); |
8673 | } else { | |
9ccd5aeb PZ |
8674 | I915_WRITE(D_COMP_BDW, val); |
8675 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8676 | } |
be256dc7 PZ |
8677 | } |
8678 | ||
8679 | /* | |
8680 | * This function implements pieces of two sequences from BSpec: | |
8681 | * - Sequence for display software to disable LCPLL | |
8682 | * - Sequence for display software to allow package C8+ | |
8683 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8684 | * register. Callers should take care of disabling all the display engine | |
8685 | * functions, doing the mode unset, fixing interrupts, etc. | |
8686 | */ | |
6ff58d53 PZ |
8687 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8688 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8689 | { |
8690 | uint32_t val; | |
8691 | ||
8692 | assert_can_disable_lcpll(dev_priv); | |
8693 | ||
8694 | val = I915_READ(LCPLL_CTL); | |
8695 | ||
8696 | if (switch_to_fclk) { | |
8697 | val |= LCPLL_CD_SOURCE_FCLK; | |
8698 | I915_WRITE(LCPLL_CTL, val); | |
8699 | ||
f53dd63f ID |
8700 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
8701 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
8702 | DRM_ERROR("Switching to FCLK failed\n"); |
8703 | ||
8704 | val = I915_READ(LCPLL_CTL); | |
8705 | } | |
8706 | ||
8707 | val |= LCPLL_PLL_DISABLE; | |
8708 | I915_WRITE(LCPLL_CTL, val); | |
8709 | POSTING_READ(LCPLL_CTL); | |
8710 | ||
24d8441d | 8711 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
8712 | DRM_ERROR("LCPLL still locked\n"); |
8713 | ||
9ccd5aeb | 8714 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8715 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8716 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8717 | ndelay(100); |
8718 | ||
9ccd5aeb PZ |
8719 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8720 | 1)) | |
be256dc7 PZ |
8721 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8722 | ||
8723 | if (allow_power_down) { | |
8724 | val = I915_READ(LCPLL_CTL); | |
8725 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8726 | I915_WRITE(LCPLL_CTL, val); | |
8727 | POSTING_READ(LCPLL_CTL); | |
8728 | } | |
8729 | } | |
8730 | ||
8731 | /* | |
8732 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8733 | * source. | |
8734 | */ | |
6ff58d53 | 8735 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8736 | { |
8737 | uint32_t val; | |
8738 | ||
8739 | val = I915_READ(LCPLL_CTL); | |
8740 | ||
8741 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8742 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8743 | return; | |
8744 | ||
a8a8bd54 PZ |
8745 | /* |
8746 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8747 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8748 | */ |
59bad947 | 8749 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8750 | |
be256dc7 PZ |
8751 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8752 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8753 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8754 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8755 | } |
8756 | ||
9ccd5aeb | 8757 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8758 | val |= D_COMP_COMP_FORCE; |
8759 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8760 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8761 | |
8762 | val = I915_READ(LCPLL_CTL); | |
8763 | val &= ~LCPLL_PLL_DISABLE; | |
8764 | I915_WRITE(LCPLL_CTL, val); | |
8765 | ||
93220c08 CW |
8766 | if (intel_wait_for_register(dev_priv, |
8767 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
8768 | 5)) | |
be256dc7 PZ |
8769 | DRM_ERROR("LCPLL not locked yet\n"); |
8770 | ||
8771 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8772 | val = I915_READ(LCPLL_CTL); | |
8773 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8774 | I915_WRITE(LCPLL_CTL, val); | |
8775 | ||
f53dd63f ID |
8776 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
8777 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
8778 | DRM_ERROR("Switching back to LCPLL failed\n"); |
8779 | } | |
215733fa | 8780 | |
59bad947 | 8781 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 8782 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
8783 | } |
8784 | ||
765dab67 PZ |
8785 | /* |
8786 | * Package states C8 and deeper are really deep PC states that can only be | |
8787 | * reached when all the devices on the system allow it, so even if the graphics | |
8788 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8789 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8790 | * | |
8791 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8792 | * well is disabled and most interrupts are disabled, and these are also | |
8793 | * requirements for runtime PM. When these conditions are met, we manually do | |
8794 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8795 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8796 | * hang the machine. | |
8797 | * | |
8798 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8799 | * the state of some registers, so when we come back from PC8+ we need to | |
8800 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8801 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8802 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8803 | * because of the runtime PM support). | |
8804 | * | |
8805 | * For more, read "Display Sequences for Package C8" on the hardware | |
8806 | * documentation. | |
8807 | */ | |
a14cb6fc | 8808 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8809 | { |
c67a470b PZ |
8810 | uint32_t val; |
8811 | ||
c67a470b PZ |
8812 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8813 | ||
4f8036a2 | 8814 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8815 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8816 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8817 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8818 | } | |
8819 | ||
c39055b0 | 8820 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
8821 | hsw_disable_lcpll(dev_priv, true, true); |
8822 | } | |
8823 | ||
a14cb6fc | 8824 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8825 | { |
c67a470b PZ |
8826 | uint32_t val; |
8827 | ||
c67a470b PZ |
8828 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8829 | ||
8830 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 8831 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 8832 | |
4f8036a2 | 8833 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8834 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8835 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8836 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8837 | } | |
c67a470b PZ |
8838 | } |
8839 | ||
190f68c5 ACO |
8840 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8841 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8842 | { |
d7edc4e5 | 8843 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
44a126ba PZ |
8844 | struct intel_encoder *encoder = |
8845 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
8846 | ||
8847 | if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) { | |
8848 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8849 | pipe_name(crtc->pipe)); | |
af3997b5 | 8850 | return -EINVAL; |
44a126ba | 8851 | } |
af3997b5 | 8852 | } |
716c2e55 | 8853 | |
c7653199 | 8854 | crtc->lowfreq_avail = false; |
644cef34 | 8855 | |
c8f7a0db | 8856 | return 0; |
79e53945 JB |
8857 | } |
8858 | ||
3760b59c S |
8859 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
8860 | enum port port, | |
8861 | struct intel_crtc_state *pipe_config) | |
8862 | { | |
8106ddbd ACO |
8863 | enum intel_dpll_id id; |
8864 | ||
3760b59c S |
8865 | switch (port) { |
8866 | case PORT_A: | |
08250c4b | 8867 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
8868 | break; |
8869 | case PORT_B: | |
08250c4b | 8870 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
8871 | break; |
8872 | case PORT_C: | |
08250c4b | 8873 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
8874 | break; |
8875 | default: | |
8876 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 8877 | return; |
3760b59c | 8878 | } |
8106ddbd ACO |
8879 | |
8880 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
8881 | } |
8882 | ||
96b7dfb7 S |
8883 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8884 | enum port port, | |
5cec258b | 8885 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8886 | { |
8106ddbd | 8887 | enum intel_dpll_id id; |
a3c988ea | 8888 | u32 temp; |
96b7dfb7 S |
8889 | |
8890 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 8891 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 8892 | |
c856052a | 8893 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 8894 | return; |
8106ddbd ACO |
8895 | |
8896 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
8897 | } |
8898 | ||
7d2c8175 DL |
8899 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8900 | enum port port, | |
5cec258b | 8901 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 8902 | { |
8106ddbd | 8903 | enum intel_dpll_id id; |
c856052a | 8904 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 8905 | |
c856052a | 8906 | switch (ddi_pll_sel) { |
7d2c8175 | 8907 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 8908 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
8909 | break; |
8910 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 8911 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 8912 | break; |
00490c22 | 8913 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 8914 | id = DPLL_ID_SPLL; |
79bd23da | 8915 | break; |
9d16da65 ACO |
8916 | case PORT_CLK_SEL_LCPLL_810: |
8917 | id = DPLL_ID_LCPLL_810; | |
8918 | break; | |
8919 | case PORT_CLK_SEL_LCPLL_1350: | |
8920 | id = DPLL_ID_LCPLL_1350; | |
8921 | break; | |
8922 | case PORT_CLK_SEL_LCPLL_2700: | |
8923 | id = DPLL_ID_LCPLL_2700; | |
8924 | break; | |
8106ddbd | 8925 | default: |
c856052a | 8926 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
8927 | /* fall through */ |
8928 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 8929 | return; |
7d2c8175 | 8930 | } |
8106ddbd ACO |
8931 | |
8932 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
8933 | } |
8934 | ||
cf30429e JN |
8935 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
8936 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8937 | u64 *power_domain_mask) |
cf30429e JN |
8938 | { |
8939 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8940 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
8941 | enum intel_display_power_domain power_domain; |
8942 | u32 tmp; | |
8943 | ||
d9a7bc67 ID |
8944 | /* |
8945 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
8946 | * transcoder handled below. | |
8947 | */ | |
cf30429e JN |
8948 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8949 | ||
8950 | /* | |
8951 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
8952 | * consistency and less surprising code; it's in always on power). | |
8953 | */ | |
8954 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
8955 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8956 | enum pipe trans_edp_pipe; | |
8957 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8958 | default: | |
8959 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8960 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8961 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8962 | trans_edp_pipe = PIPE_A; | |
8963 | break; | |
8964 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8965 | trans_edp_pipe = PIPE_B; | |
8966 | break; | |
8967 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8968 | trans_edp_pipe = PIPE_C; | |
8969 | break; | |
8970 | } | |
8971 | ||
8972 | if (trans_edp_pipe == crtc->pipe) | |
8973 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8974 | } | |
8975 | ||
8976 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
8977 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
8978 | return false; | |
d8fc70b7 | 8979 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e JN |
8980 | |
8981 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
8982 | ||
8983 | return tmp & PIPECONF_ENABLE; | |
8984 | } | |
8985 | ||
4d1de975 JN |
8986 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
8987 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8988 | u64 *power_domain_mask) |
4d1de975 JN |
8989 | { |
8990 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8991 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
8992 | enum intel_display_power_domain power_domain; |
8993 | enum port port; | |
8994 | enum transcoder cpu_transcoder; | |
8995 | u32 tmp; | |
8996 | ||
4d1de975 JN |
8997 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
8998 | if (port == PORT_A) | |
8999 | cpu_transcoder = TRANSCODER_DSI_A; | |
9000 | else | |
9001 | cpu_transcoder = TRANSCODER_DSI_C; | |
9002 | ||
9003 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9004 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9005 | continue; | |
d8fc70b7 | 9006 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 9007 | |
db18b6a6 ID |
9008 | /* |
9009 | * The PLL needs to be enabled with a valid divider | |
9010 | * configuration, otherwise accessing DSI registers will hang | |
9011 | * the machine. See BSpec North Display Engine | |
9012 | * registers/MIPI[BXT]. We can break out here early, since we | |
9013 | * need the same DSI PLL to be enabled for both DSI ports. | |
9014 | */ | |
9015 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9016 | break; | |
9017 | ||
4d1de975 JN |
9018 | /* XXX: this works for video mode only */ |
9019 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9020 | if (!(tmp & DPI_ENABLE)) | |
9021 | continue; | |
9022 | ||
9023 | tmp = I915_READ(MIPI_CTRL(port)); | |
9024 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9025 | continue; | |
9026 | ||
9027 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
9028 | break; |
9029 | } | |
9030 | ||
d7edc4e5 | 9031 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
9032 | } |
9033 | ||
26804afd | 9034 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9035 | struct intel_crtc_state *pipe_config) |
26804afd | 9036 | { |
6315b5d3 | 9037 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 9038 | struct intel_shared_dpll *pll; |
26804afd DV |
9039 | enum port port; |
9040 | uint32_t tmp; | |
9041 | ||
9042 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9043 | ||
9044 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9045 | ||
b976dc53 | 9046 | if (IS_GEN9_BC(dev_priv)) |
96b7dfb7 | 9047 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 9048 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 9049 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
9050 | else |
9051 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9052 | |
8106ddbd ACO |
9053 | pll = pipe_config->shared_dpll; |
9054 | if (pll) { | |
2edd6443 ACO |
9055 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9056 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9057 | } |
9058 | ||
26804afd DV |
9059 | /* |
9060 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9061 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9062 | * the PCH transcoder is on. | |
9063 | */ | |
6315b5d3 | 9064 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 9065 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
9066 | pipe_config->has_pch_encoder = true; |
9067 | ||
9068 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9069 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9070 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9071 | ||
9072 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9073 | } | |
9074 | } | |
9075 | ||
0e8ffe1b | 9076 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9077 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9078 | { |
6315b5d3 | 9079 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9080 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 9081 | u64 power_domain_mask; |
cf30429e | 9082 | bool active; |
0e8ffe1b | 9083 | |
1729050e ID |
9084 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9085 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9086 | return false; |
d8fc70b7 | 9087 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 9088 | |
8106ddbd | 9089 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9090 | |
cf30429e | 9091 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9092 | |
cc3f90f0 | 9093 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
9094 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
9095 | WARN_ON(active); | |
9096 | active = true; | |
4d1de975 JN |
9097 | } |
9098 | ||
cf30429e | 9099 | if (!active) |
1729050e | 9100 | goto out; |
0e8ffe1b | 9101 | |
d7edc4e5 | 9102 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
9103 | haswell_get_ddi_port_state(crtc, pipe_config); |
9104 | intel_get_pipe_timings(crtc, pipe_config); | |
9105 | } | |
627eb5a3 | 9106 | |
bc58be60 | 9107 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9108 | |
05dc698c LL |
9109 | pipe_config->gamma_mode = |
9110 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9111 | ||
6315b5d3 | 9112 | if (INTEL_GEN(dev_priv) >= 9) { |
1c74eeaf | 9113 | intel_crtc_init_scalers(crtc, pipe_config); |
a1b2278e | 9114 | |
af99ceda CK |
9115 | pipe_config->scaler_state.scaler_id = -1; |
9116 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9117 | } | |
9118 | ||
1729050e ID |
9119 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9120 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
d8fc70b7 | 9121 | power_domain_mask |= BIT_ULL(power_domain); |
6315b5d3 | 9122 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 9123 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9124 | else |
1c132b44 | 9125 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9126 | } |
88adfff1 | 9127 | |
772c2a51 | 9128 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
9129 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
9130 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9131 | |
4d1de975 JN |
9132 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9133 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9134 | pipe_config->pixel_multiplier = |
9135 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9136 | } else { | |
9137 | pipe_config->pixel_multiplier = 1; | |
9138 | } | |
6c49f241 | 9139 | |
1729050e ID |
9140 | out: |
9141 | for_each_power_domain(power_domain, power_domain_mask) | |
9142 | intel_display_power_put(dev_priv, power_domain); | |
9143 | ||
cf30429e | 9144 | return active; |
0e8ffe1b DV |
9145 | } |
9146 | ||
cd5dcbf1 | 9147 | static u32 intel_cursor_base(const struct intel_plane_state *plane_state) |
1cecc830 VS |
9148 | { |
9149 | struct drm_i915_private *dev_priv = | |
9150 | to_i915(plane_state->base.plane->dev); | |
9151 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
9152 | const struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
9153 | u32 base; | |
9154 | ||
9155 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) | |
9156 | base = obj->phys_handle->busaddr; | |
9157 | else | |
9158 | base = intel_plane_ggtt_offset(plane_state); | |
9159 | ||
1e7b4fd8 VS |
9160 | base += plane_state->main.offset; |
9161 | ||
1cecc830 VS |
9162 | /* ILK+ do this automagically */ |
9163 | if (HAS_GMCH_DISPLAY(dev_priv) && | |
a82256bc | 9164 | plane_state->base.rotation & DRM_MODE_ROTATE_180) |
1cecc830 VS |
9165 | base += (plane_state->base.crtc_h * |
9166 | plane_state->base.crtc_w - 1) * fb->format->cpp[0]; | |
9167 | ||
9168 | return base; | |
9169 | } | |
9170 | ||
ed270223 VS |
9171 | static u32 intel_cursor_position(const struct intel_plane_state *plane_state) |
9172 | { | |
9173 | int x = plane_state->base.crtc_x; | |
9174 | int y = plane_state->base.crtc_y; | |
9175 | u32 pos = 0; | |
9176 | ||
9177 | if (x < 0) { | |
9178 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9179 | x = -x; | |
9180 | } | |
9181 | pos |= x << CURSOR_X_SHIFT; | |
9182 | ||
9183 | if (y < 0) { | |
9184 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9185 | y = -y; | |
9186 | } | |
9187 | pos |= y << CURSOR_Y_SHIFT; | |
9188 | ||
9189 | return pos; | |
9190 | } | |
9191 | ||
3637ecf0 VS |
9192 | static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) |
9193 | { | |
9194 | const struct drm_mode_config *config = | |
9195 | &plane_state->base.plane->dev->mode_config; | |
9196 | int width = plane_state->base.crtc_w; | |
9197 | int height = plane_state->base.crtc_h; | |
9198 | ||
9199 | return width > 0 && width <= config->cursor_width && | |
9200 | height > 0 && height <= config->cursor_height; | |
9201 | } | |
9202 | ||
659056f2 VS |
9203 | static int intel_check_cursor(struct intel_crtc_state *crtc_state, |
9204 | struct intel_plane_state *plane_state) | |
9205 | { | |
9206 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
1e7b4fd8 VS |
9207 | int src_x, src_y; |
9208 | u32 offset; | |
659056f2 VS |
9209 | int ret; |
9210 | ||
9211 | ret = drm_plane_helper_check_state(&plane_state->base, | |
9212 | &plane_state->clip, | |
9213 | DRM_PLANE_HELPER_NO_SCALING, | |
9214 | DRM_PLANE_HELPER_NO_SCALING, | |
9215 | true, true); | |
9216 | if (ret) | |
9217 | return ret; | |
9218 | ||
9219 | if (!fb) | |
9220 | return 0; | |
9221 | ||
9222 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { | |
9223 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); | |
9224 | return -EINVAL; | |
9225 | } | |
9226 | ||
1e7b4fd8 VS |
9227 | src_x = plane_state->base.src_x >> 16; |
9228 | src_y = plane_state->base.src_y >> 16; | |
9229 | ||
9230 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); | |
9231 | offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0); | |
9232 | ||
9233 | if (src_x != 0 || src_y != 0) { | |
9234 | DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n"); | |
9235 | return -EINVAL; | |
9236 | } | |
9237 | ||
9238 | plane_state->main.offset = offset; | |
9239 | ||
659056f2 VS |
9240 | return 0; |
9241 | } | |
9242 | ||
292889e1 VS |
9243 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9244 | const struct intel_plane_state *plane_state) | |
9245 | { | |
1e1bb871 | 9246 | const struct drm_framebuffer *fb = plane_state->base.fb; |
292889e1 | 9247 | |
292889e1 VS |
9248 | return CURSOR_ENABLE | |
9249 | CURSOR_GAMMA_ENABLE | | |
9250 | CURSOR_FORMAT_ARGB | | |
1e1bb871 | 9251 | CURSOR_STRIDE(fb->pitches[0]); |
292889e1 VS |
9252 | } |
9253 | ||
659056f2 VS |
9254 | static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) |
9255 | { | |
659056f2 | 9256 | int width = plane_state->base.crtc_w; |
659056f2 VS |
9257 | |
9258 | /* | |
9259 | * 845g/865g are only limited by the width of their cursors, | |
9260 | * the height is arbitrary up to the precision of the register. | |
9261 | */ | |
3637ecf0 | 9262 | return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); |
659056f2 VS |
9263 | } |
9264 | ||
9265 | static int i845_check_cursor(struct intel_plane *plane, | |
9266 | struct intel_crtc_state *crtc_state, | |
9267 | struct intel_plane_state *plane_state) | |
9268 | { | |
9269 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 VS |
9270 | int ret; |
9271 | ||
9272 | ret = intel_check_cursor(crtc_state, plane_state); | |
9273 | if (ret) | |
9274 | return ret; | |
9275 | ||
9276 | /* if we want to turn off the cursor ignore width and height */ | |
1e1bb871 | 9277 | if (!fb) |
659056f2 VS |
9278 | return 0; |
9279 | ||
9280 | /* Check for which cursor types we support */ | |
9281 | if (!i845_cursor_size_ok(plane_state)) { | |
9282 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9283 | plane_state->base.crtc_w, | |
9284 | plane_state->base.crtc_h); | |
9285 | return -EINVAL; | |
9286 | } | |
9287 | ||
1e1bb871 | 9288 | switch (fb->pitches[0]) { |
292889e1 VS |
9289 | case 256: |
9290 | case 512: | |
9291 | case 1024: | |
9292 | case 2048: | |
9293 | break; | |
1e1bb871 VS |
9294 | default: |
9295 | DRM_DEBUG_KMS("Invalid cursor stride (%u)\n", | |
9296 | fb->pitches[0]); | |
9297 | return -EINVAL; | |
292889e1 VS |
9298 | } |
9299 | ||
659056f2 VS |
9300 | plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); |
9301 | ||
9302 | return 0; | |
292889e1 VS |
9303 | } |
9304 | ||
b2d03b0d VS |
9305 | static void i845_update_cursor(struct intel_plane *plane, |
9306 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9307 | const struct intel_plane_state *plane_state) |
560b85bb | 9308 | { |
cd5dcbf1 | 9309 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
b2d03b0d VS |
9310 | u32 cntl = 0, base = 0, pos = 0, size = 0; |
9311 | unsigned long irqflags; | |
560b85bb | 9312 | |
936e71e3 | 9313 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
9314 | unsigned int width = plane_state->base.crtc_w; |
9315 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 | 9316 | |
a0864d59 | 9317 | cntl = plane_state->ctl; |
dc41c154 | 9318 | size = (height << 12) | width; |
560b85bb | 9319 | |
b2d03b0d VS |
9320 | base = intel_cursor_base(plane_state); |
9321 | pos = intel_cursor_position(plane_state); | |
4b0e333e | 9322 | } |
560b85bb | 9323 | |
b2d03b0d | 9324 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
4726e0b0 | 9325 | |
e11ffddb VS |
9326 | /* On these chipsets we can only modify the base/size/stride |
9327 | * whilst the cursor is disabled. | |
9328 | */ | |
9329 | if (plane->cursor.base != base || | |
9330 | plane->cursor.size != size || | |
9331 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9332 | I915_WRITE_FW(CURCNTR(PIPE_A), 0); |
dd584fc0 | 9333 | I915_WRITE_FW(CURBASE(PIPE_A), base); |
dd584fc0 | 9334 | I915_WRITE_FW(CURSIZE, size); |
b2d03b0d | 9335 | I915_WRITE_FW(CURPOS(PIPE_A), pos); |
dd584fc0 | 9336 | I915_WRITE_FW(CURCNTR(PIPE_A), cntl); |
75343a44 | 9337 | |
e11ffddb VS |
9338 | plane->cursor.base = base; |
9339 | plane->cursor.size = size; | |
9340 | plane->cursor.cntl = cntl; | |
9341 | } else { | |
9342 | I915_WRITE_FW(CURPOS(PIPE_A), pos); | |
560b85bb | 9343 | } |
e11ffddb | 9344 | |
75343a44 | 9345 | POSTING_READ_FW(CURCNTR(PIPE_A)); |
b2d03b0d VS |
9346 | |
9347 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
9348 | } | |
9349 | ||
9350 | static void i845_disable_cursor(struct intel_plane *plane, | |
9351 | struct intel_crtc *crtc) | |
9352 | { | |
9353 | i845_update_cursor(plane, NULL, NULL); | |
560b85bb CW |
9354 | } |
9355 | ||
292889e1 VS |
9356 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9357 | const struct intel_plane_state *plane_state) | |
9358 | { | |
9359 | struct drm_i915_private *dev_priv = | |
9360 | to_i915(plane_state->base.plane->dev); | |
9361 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
292889e1 VS |
9362 | u32 cntl; |
9363 | ||
9364 | cntl = MCURSOR_GAMMA_ENABLE; | |
9365 | ||
9366 | if (HAS_DDI(dev_priv)) | |
9367 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
9368 | ||
d509e28b | 9369 | cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); |
292889e1 VS |
9370 | |
9371 | switch (plane_state->base.crtc_w) { | |
9372 | case 64: | |
9373 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9374 | break; | |
9375 | case 128: | |
9376 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9377 | break; | |
9378 | case 256: | |
9379 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9380 | break; | |
9381 | default: | |
9382 | MISSING_CASE(plane_state->base.crtc_w); | |
9383 | return 0; | |
9384 | } | |
9385 | ||
c2c446ad | 9386 | if (plane_state->base.rotation & DRM_MODE_ROTATE_180) |
292889e1 VS |
9387 | cntl |= CURSOR_ROTATE_180; |
9388 | ||
9389 | return cntl; | |
9390 | } | |
9391 | ||
659056f2 | 9392 | static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) |
65a21cd6 | 9393 | { |
024faac7 VS |
9394 | struct drm_i915_private *dev_priv = |
9395 | to_i915(plane_state->base.plane->dev); | |
659056f2 VS |
9396 | int width = plane_state->base.crtc_w; |
9397 | int height = plane_state->base.crtc_h; | |
4b0e333e | 9398 | |
3637ecf0 | 9399 | if (!intel_cursor_size_ok(plane_state)) |
659056f2 | 9400 | return false; |
4398ad45 | 9401 | |
024faac7 VS |
9402 | /* Cursor width is limited to a few power-of-two sizes */ |
9403 | switch (width) { | |
659056f2 VS |
9404 | case 256: |
9405 | case 128: | |
659056f2 VS |
9406 | case 64: |
9407 | break; | |
9408 | default: | |
9409 | return false; | |
65a21cd6 | 9410 | } |
4b0e333e | 9411 | |
024faac7 VS |
9412 | /* |
9413 | * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor | |
9414 | * height from 8 lines up to the cursor width, when the | |
9415 | * cursor is not rotated. Everything else requires square | |
9416 | * cursors. | |
9417 | */ | |
9418 | if (HAS_CUR_FBC(dev_priv) && | |
a82256bc | 9419 | plane_state->base.rotation & DRM_MODE_ROTATE_0) { |
024faac7 VS |
9420 | if (height < 8 || height > width) |
9421 | return false; | |
9422 | } else { | |
9423 | if (height != width) | |
9424 | return false; | |
9425 | } | |
99d1f387 | 9426 | |
659056f2 | 9427 | return true; |
65a21cd6 JB |
9428 | } |
9429 | ||
659056f2 VS |
9430 | static int i9xx_check_cursor(struct intel_plane *plane, |
9431 | struct intel_crtc_state *crtc_state, | |
9432 | struct intel_plane_state *plane_state) | |
cda4b7d3 | 9433 | { |
659056f2 VS |
9434 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9435 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 | 9436 | enum pipe pipe = plane->pipe; |
659056f2 | 9437 | int ret; |
cda4b7d3 | 9438 | |
659056f2 VS |
9439 | ret = intel_check_cursor(crtc_state, plane_state); |
9440 | if (ret) | |
9441 | return ret; | |
cda4b7d3 | 9442 | |
659056f2 | 9443 | /* if we want to turn off the cursor ignore width and height */ |
1e1bb871 | 9444 | if (!fb) |
659056f2 | 9445 | return 0; |
55a08b3f | 9446 | |
659056f2 VS |
9447 | /* Check for which cursor types we support */ |
9448 | if (!i9xx_cursor_size_ok(plane_state)) { | |
9449 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9450 | plane_state->base.crtc_w, | |
9451 | plane_state->base.crtc_h); | |
9452 | return -EINVAL; | |
cda4b7d3 | 9453 | } |
cda4b7d3 | 9454 | |
1e1bb871 VS |
9455 | if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) { |
9456 | DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n", | |
9457 | fb->pitches[0], plane_state->base.crtc_w); | |
9458 | return -EINVAL; | |
659056f2 | 9459 | } |
dd584fc0 | 9460 | |
659056f2 VS |
9461 | /* |
9462 | * There's something wrong with the cursor on CHV pipe C. | |
9463 | * If it straddles the left edge of the screen then | |
9464 | * moving it away from the edge or disabling it often | |
9465 | * results in a pipe underrun, and often that can lead to | |
9466 | * dead pipe (constant underrun reported, and it scans | |
9467 | * out just a solid color). To recover from that, the | |
9468 | * display power well must be turned off and on again. | |
9469 | * Refuse the put the cursor into that compromised position. | |
9470 | */ | |
9471 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && | |
9472 | plane_state->base.visible && plane_state->base.crtc_x < 0) { | |
9473 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
9474 | return -EINVAL; | |
9475 | } | |
5efb3e28 | 9476 | |
659056f2 | 9477 | plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); |
dd584fc0 | 9478 | |
659056f2 | 9479 | return 0; |
cda4b7d3 CW |
9480 | } |
9481 | ||
b2d03b0d VS |
9482 | static void i9xx_update_cursor(struct intel_plane *plane, |
9483 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9484 | const struct intel_plane_state *plane_state) |
dc41c154 | 9485 | { |
cd5dcbf1 VS |
9486 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9487 | enum pipe pipe = plane->pipe; | |
024faac7 | 9488 | u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; |
b2d03b0d | 9489 | unsigned long irqflags; |
dc41c154 | 9490 | |
b2d03b0d | 9491 | if (plane_state && plane_state->base.visible) { |
a0864d59 | 9492 | cntl = plane_state->ctl; |
dc41c154 | 9493 | |
024faac7 VS |
9494 | if (plane_state->base.crtc_h != plane_state->base.crtc_w) |
9495 | fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1); | |
dc41c154 | 9496 | |
b2d03b0d VS |
9497 | base = intel_cursor_base(plane_state); |
9498 | pos = intel_cursor_position(plane_state); | |
9499 | } | |
9500 | ||
9501 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
9502 | ||
e11ffddb VS |
9503 | /* |
9504 | * On some platforms writing CURCNTR first will also | |
9505 | * cause CURPOS to be armed by the CURBASE write. | |
9506 | * Without the CURCNTR write the CURPOS write would | |
9507 | * arm itself. | |
9508 | * | |
9509 | * CURCNTR and CUR_FBC_CTL are always | |
9510 | * armed by the CURBASE write only. | |
9511 | */ | |
9512 | if (plane->cursor.base != base || | |
9513 | plane->cursor.size != fbc_ctl || | |
9514 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9515 | I915_WRITE_FW(CURCNTR(pipe), cntl); |
e11ffddb VS |
9516 | if (HAS_CUR_FBC(dev_priv)) |
9517 | I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); | |
b2d03b0d | 9518 | I915_WRITE_FW(CURPOS(pipe), pos); |
75343a44 VS |
9519 | I915_WRITE_FW(CURBASE(pipe), base); |
9520 | ||
e11ffddb VS |
9521 | plane->cursor.base = base; |
9522 | plane->cursor.size = fbc_ctl; | |
9523 | plane->cursor.cntl = cntl; | |
dc41c154 | 9524 | } else { |
e11ffddb | 9525 | I915_WRITE_FW(CURPOS(pipe), pos); |
dc41c154 VS |
9526 | } |
9527 | ||
dd584fc0 | 9528 | POSTING_READ_FW(CURBASE(pipe)); |
99d1f387 | 9529 | |
b2d03b0d | 9530 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
65a21cd6 JB |
9531 | } |
9532 | ||
b2d03b0d VS |
9533 | static void i9xx_disable_cursor(struct intel_plane *plane, |
9534 | struct intel_crtc *crtc) | |
cda4b7d3 | 9535 | { |
b2d03b0d | 9536 | i9xx_update_cursor(plane, NULL, NULL); |
dc41c154 VS |
9537 | } |
9538 | ||
dc41c154 | 9539 | |
79e53945 JB |
9540 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9541 | static struct drm_display_mode load_detect_mode = { | |
9542 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9543 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9544 | }; | |
9545 | ||
a8bb6818 | 9546 | struct drm_framebuffer * |
24dbf51a CW |
9547 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
9548 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
9549 | { |
9550 | struct intel_framebuffer *intel_fb; | |
9551 | int ret; | |
9552 | ||
9553 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 9554 | if (!intel_fb) |
d2dff872 | 9555 | return ERR_PTR(-ENOMEM); |
d2dff872 | 9556 | |
24dbf51a | 9557 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
9558 | if (ret) |
9559 | goto err; | |
d2dff872 CW |
9560 | |
9561 | return &intel_fb->base; | |
dcb1394e | 9562 | |
dd4916c5 | 9563 | err: |
dd4916c5 | 9564 | kfree(intel_fb); |
dd4916c5 | 9565 | return ERR_PTR(ret); |
d2dff872 CW |
9566 | } |
9567 | ||
9568 | static u32 | |
9569 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9570 | { | |
9571 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9572 | return ALIGN(pitch, 64); | |
9573 | } | |
9574 | ||
9575 | static u32 | |
9576 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9577 | { | |
9578 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9579 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9580 | } |
9581 | ||
9582 | static struct drm_framebuffer * | |
9583 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9584 | struct drm_display_mode *mode, | |
9585 | int depth, int bpp) | |
9586 | { | |
dcb1394e | 9587 | struct drm_framebuffer *fb; |
d2dff872 | 9588 | struct drm_i915_gem_object *obj; |
0fed39bd | 9589 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 9590 | |
12d79d78 | 9591 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 9592 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
9593 | if (IS_ERR(obj)) |
9594 | return ERR_CAST(obj); | |
d2dff872 CW |
9595 | |
9596 | mode_cmd.width = mode->hdisplay; | |
9597 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9598 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9599 | bpp); | |
5ca0c34a | 9600 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 9601 | |
24dbf51a | 9602 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 9603 | if (IS_ERR(fb)) |
f0cd5182 | 9604 | i915_gem_object_put(obj); |
dcb1394e LW |
9605 | |
9606 | return fb; | |
d2dff872 CW |
9607 | } |
9608 | ||
9609 | static struct drm_framebuffer * | |
9610 | mode_fits_in_fbdev(struct drm_device *dev, | |
9611 | struct drm_display_mode *mode) | |
9612 | { | |
0695726e | 9613 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 9614 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
9615 | struct drm_i915_gem_object *obj; |
9616 | struct drm_framebuffer *fb; | |
9617 | ||
4c0e5528 | 9618 | if (!dev_priv->fbdev) |
d2dff872 CW |
9619 | return NULL; |
9620 | ||
4c0e5528 | 9621 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9622 | return NULL; |
9623 | ||
4c0e5528 DV |
9624 | obj = dev_priv->fbdev->fb->obj; |
9625 | BUG_ON(!obj); | |
9626 | ||
8bcd4553 | 9627 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 | 9628 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
272725c7 | 9629 | fb->format->cpp[0] * 8)) |
d2dff872 CW |
9630 | return NULL; |
9631 | ||
01f2c773 | 9632 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9633 | return NULL; |
9634 | ||
edde3617 | 9635 | drm_framebuffer_reference(fb); |
d2dff872 | 9636 | return fb; |
4520f53a DV |
9637 | #else |
9638 | return NULL; | |
9639 | #endif | |
d2dff872 CW |
9640 | } |
9641 | ||
d3a40d1b ACO |
9642 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9643 | struct drm_crtc *crtc, | |
9644 | struct drm_display_mode *mode, | |
9645 | struct drm_framebuffer *fb, | |
9646 | int x, int y) | |
9647 | { | |
9648 | struct drm_plane_state *plane_state; | |
9649 | int hdisplay, vdisplay; | |
9650 | int ret; | |
9651 | ||
9652 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9653 | if (IS_ERR(plane_state)) | |
9654 | return PTR_ERR(plane_state); | |
9655 | ||
9656 | if (mode) | |
196cd5d3 | 9657 | drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay); |
d3a40d1b ACO |
9658 | else |
9659 | hdisplay = vdisplay = 0; | |
9660 | ||
9661 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9662 | if (ret) | |
9663 | return ret; | |
9664 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9665 | plane_state->crtc_x = 0; | |
9666 | plane_state->crtc_y = 0; | |
9667 | plane_state->crtc_w = hdisplay; | |
9668 | plane_state->crtc_h = vdisplay; | |
9669 | plane_state->src_x = x << 16; | |
9670 | plane_state->src_y = y << 16; | |
9671 | plane_state->src_w = hdisplay << 16; | |
9672 | plane_state->src_h = vdisplay << 16; | |
9673 | ||
9674 | return 0; | |
9675 | } | |
9676 | ||
6c5ed5ae ML |
9677 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
9678 | struct drm_display_mode *mode, | |
9679 | struct intel_load_detect_pipe *old, | |
9680 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9681 | { |
9682 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9683 | struct intel_encoder *intel_encoder = |
9684 | intel_attached_encoder(connector); | |
79e53945 | 9685 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9686 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9687 | struct drm_crtc *crtc = NULL; |
9688 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 9689 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 9690 | struct drm_framebuffer *fb; |
51fd371b | 9691 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 9692 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 9693 | struct drm_connector_state *connector_state; |
4be07317 | 9694 | struct intel_crtc_state *crtc_state; |
51fd371b | 9695 | int ret, i = -1; |
79e53945 | 9696 | |
d2dff872 | 9697 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9698 | connector->base.id, connector->name, |
8e329a03 | 9699 | encoder->base.id, encoder->name); |
d2dff872 | 9700 | |
edde3617 ML |
9701 | old->restore_state = NULL; |
9702 | ||
6c5ed5ae | 9703 | WARN_ON(!drm_modeset_is_locked(&config->connection_mutex)); |
6e9f798d | 9704 | |
79e53945 JB |
9705 | /* |
9706 | * Algorithm gets a little messy: | |
7a5e4805 | 9707 | * |
79e53945 JB |
9708 | * - if the connector already has an assigned crtc, use it (but make |
9709 | * sure it's on first) | |
7a5e4805 | 9710 | * |
79e53945 JB |
9711 | * - try to find the first unused crtc that can drive this connector, |
9712 | * and use that if we find one | |
79e53945 JB |
9713 | */ |
9714 | ||
9715 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
9716 | if (connector->state->crtc) { |
9717 | crtc = connector->state->crtc; | |
8261b191 | 9718 | |
51fd371b | 9719 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 9720 | if (ret) |
ad3c558f | 9721 | goto fail; |
8261b191 CW |
9722 | |
9723 | /* Make sure the crtc and connector are running */ | |
edde3617 | 9724 | goto found; |
79e53945 JB |
9725 | } |
9726 | ||
9727 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9728 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9729 | i++; |
9730 | if (!(encoder->possible_crtcs & (1 << i))) | |
9731 | continue; | |
edde3617 ML |
9732 | |
9733 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
9734 | if (ret) | |
9735 | goto fail; | |
9736 | ||
9737 | if (possible_crtc->state->enable) { | |
9738 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 9739 | continue; |
edde3617 | 9740 | } |
a459249c VS |
9741 | |
9742 | crtc = possible_crtc; | |
9743 | break; | |
79e53945 JB |
9744 | } |
9745 | ||
9746 | /* | |
9747 | * If we didn't find an unused CRTC, don't use any. | |
9748 | */ | |
9749 | if (!crtc) { | |
7173188d | 9750 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
f4bf77b4 | 9751 | ret = -ENODEV; |
ad3c558f | 9752 | goto fail; |
79e53945 JB |
9753 | } |
9754 | ||
edde3617 ML |
9755 | found: |
9756 | intel_crtc = to_intel_crtc(crtc); | |
9757 | ||
4d02e2de DV |
9758 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
9759 | if (ret) | |
ad3c558f | 9760 | goto fail; |
79e53945 | 9761 | |
83a57153 | 9762 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
9763 | restore_state = drm_atomic_state_alloc(dev); |
9764 | if (!state || !restore_state) { | |
9765 | ret = -ENOMEM; | |
9766 | goto fail; | |
9767 | } | |
83a57153 ACO |
9768 | |
9769 | state->acquire_ctx = ctx; | |
edde3617 | 9770 | restore_state->acquire_ctx = ctx; |
83a57153 | 9771 | |
944b0c76 ACO |
9772 | connector_state = drm_atomic_get_connector_state(state, connector); |
9773 | if (IS_ERR(connector_state)) { | |
9774 | ret = PTR_ERR(connector_state); | |
9775 | goto fail; | |
9776 | } | |
9777 | ||
edde3617 ML |
9778 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
9779 | if (ret) | |
9780 | goto fail; | |
944b0c76 | 9781 | |
4be07317 ACO |
9782 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9783 | if (IS_ERR(crtc_state)) { | |
9784 | ret = PTR_ERR(crtc_state); | |
9785 | goto fail; | |
9786 | } | |
9787 | ||
49d6fa21 | 9788 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 9789 | |
6492711d CW |
9790 | if (!mode) |
9791 | mode = &load_detect_mode; | |
79e53945 | 9792 | |
d2dff872 CW |
9793 | /* We need a framebuffer large enough to accommodate all accesses |
9794 | * that the plane may generate whilst we perform load detection. | |
9795 | * We can not rely on the fbcon either being present (we get called | |
9796 | * during its initialisation to detect all boot displays, or it may | |
9797 | * not even exist) or that it is large enough to satisfy the | |
9798 | * requested mode. | |
9799 | */ | |
94352cf9 DV |
9800 | fb = mode_fits_in_fbdev(dev, mode); |
9801 | if (fb == NULL) { | |
d2dff872 | 9802 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 9803 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
9804 | } else |
9805 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9806 | if (IS_ERR(fb)) { |
d2dff872 | 9807 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
f4bf77b4 | 9808 | ret = PTR_ERR(fb); |
412b61d8 | 9809 | goto fail; |
79e53945 | 9810 | } |
79e53945 | 9811 | |
d3a40d1b ACO |
9812 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
9813 | if (ret) | |
9814 | goto fail; | |
9815 | ||
edde3617 ML |
9816 | drm_framebuffer_unreference(fb); |
9817 | ||
9818 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
9819 | if (ret) | |
9820 | goto fail; | |
9821 | ||
9822 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
9823 | if (!ret) | |
9824 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
9825 | if (!ret) | |
9826 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
9827 | if (ret) { | |
9828 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
9829 | goto fail; | |
9830 | } | |
8c7b5ccb | 9831 | |
3ba86073 ML |
9832 | ret = drm_atomic_commit(state); |
9833 | if (ret) { | |
6492711d | 9834 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 9835 | goto fail; |
79e53945 | 9836 | } |
edde3617 ML |
9837 | |
9838 | old->restore_state = restore_state; | |
7abbd11f | 9839 | drm_atomic_state_put(state); |
7173188d | 9840 | |
79e53945 | 9841 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 9842 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 9843 | return true; |
412b61d8 | 9844 | |
ad3c558f | 9845 | fail: |
7fb71c8f CW |
9846 | if (state) { |
9847 | drm_atomic_state_put(state); | |
9848 | state = NULL; | |
9849 | } | |
9850 | if (restore_state) { | |
9851 | drm_atomic_state_put(restore_state); | |
9852 | restore_state = NULL; | |
9853 | } | |
83a57153 | 9854 | |
6c5ed5ae ML |
9855 | if (ret == -EDEADLK) |
9856 | return ret; | |
51fd371b | 9857 | |
412b61d8 | 9858 | return false; |
79e53945 JB |
9859 | } |
9860 | ||
d2434ab7 | 9861 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9862 | struct intel_load_detect_pipe *old, |
9863 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9864 | { |
d2434ab7 DV |
9865 | struct intel_encoder *intel_encoder = |
9866 | intel_attached_encoder(connector); | |
4ef69c7a | 9867 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 9868 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 9869 | int ret; |
79e53945 | 9870 | |
d2dff872 | 9871 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9872 | connector->base.id, connector->name, |
8e329a03 | 9873 | encoder->base.id, encoder->name); |
d2dff872 | 9874 | |
edde3617 | 9875 | if (!state) |
0622a53c | 9876 | return; |
79e53945 | 9877 | |
581e49fe | 9878 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
0853695c | 9879 | if (ret) |
edde3617 | 9880 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 9881 | drm_atomic_state_put(state); |
79e53945 JB |
9882 | } |
9883 | ||
da4a1efa | 9884 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9885 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 9886 | { |
fac5e23e | 9887 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
9888 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
9889 | ||
9890 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9891 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 9892 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 9893 | return 120000; |
5db94019 | 9894 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
9895 | return 96000; |
9896 | else | |
9897 | return 48000; | |
9898 | } | |
9899 | ||
79e53945 | 9900 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9901 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9902 | struct intel_crtc_state *pipe_config) |
79e53945 | 9903 | { |
f1f644dc | 9904 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9905 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 9906 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9907 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 9908 | u32 fp; |
9e2c8475 | 9909 | struct dpll clock; |
dccbea3b | 9910 | int port_clock; |
da4a1efa | 9911 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9912 | |
9913 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9914 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9915 | else |
293623f7 | 9916 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9917 | |
9918 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 9919 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
9920 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
9921 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9922 | } else { |
9923 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9924 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9925 | } | |
9926 | ||
5db94019 | 9927 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 9928 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
9929 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
9930 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9931 | else |
9932 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9933 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9934 | ||
9935 | switch (dpll & DPLL_MODE_MASK) { | |
9936 | case DPLLB_MODE_DAC_SERIAL: | |
9937 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9938 | 5 : 10; | |
9939 | break; | |
9940 | case DPLLB_MODE_LVDS: | |
9941 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9942 | 7 : 14; | |
9943 | break; | |
9944 | default: | |
28c97730 | 9945 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9946 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9947 | return; |
79e53945 JB |
9948 | } |
9949 | ||
9b1e14f4 | 9950 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 9951 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 9952 | else |
dccbea3b | 9953 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 9954 | } else { |
50a0bc90 | 9955 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9956 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9957 | |
9958 | if (is_lvds) { | |
9959 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9960 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9961 | |
9962 | if (lvds & LVDS_CLKB_POWER_UP) | |
9963 | clock.p2 = 7; | |
9964 | else | |
9965 | clock.p2 = 14; | |
79e53945 JB |
9966 | } else { |
9967 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9968 | clock.p1 = 2; | |
9969 | else { | |
9970 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9971 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9972 | } | |
9973 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9974 | clock.p2 = 4; | |
9975 | else | |
9976 | clock.p2 = 2; | |
79e53945 | 9977 | } |
da4a1efa | 9978 | |
dccbea3b | 9979 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
9980 | } |
9981 | ||
18442d08 VS |
9982 | /* |
9983 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9984 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9985 | * encoder's get_config() function. |
9986 | */ | |
dccbea3b | 9987 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
9988 | } |
9989 | ||
6878da05 VS |
9990 | int intel_dotclock_calculate(int link_freq, |
9991 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9992 | { |
f1f644dc JB |
9993 | /* |
9994 | * The calculation for the data clock is: | |
1041a02f | 9995 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9996 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9997 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9998 | * |
9999 | * and the link clock is simpler: | |
1041a02f | 10000 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10001 | */ |
10002 | ||
6878da05 VS |
10003 | if (!m_n->link_n) |
10004 | return 0; | |
f1f644dc | 10005 | |
6878da05 VS |
10006 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10007 | } | |
f1f644dc | 10008 | |
18442d08 | 10009 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10010 | struct intel_crtc_state *pipe_config) |
6878da05 | 10011 | { |
e3b247da | 10012 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10013 | |
18442d08 VS |
10014 | /* read out port_clock from the DPLL */ |
10015 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10016 | |
f1f644dc | 10017 | /* |
e3b247da VS |
10018 | * In case there is an active pipe without active ports, |
10019 | * we may need some idea for the dotclock anyway. | |
10020 | * Calculate one based on the FDI configuration. | |
79e53945 | 10021 | */ |
2d112de7 | 10022 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10023 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10024 | &pipe_config->fdi_m_n); |
79e53945 JB |
10025 | } |
10026 | ||
10027 | /** Returns the currently programmed mode of the given pipe. */ | |
10028 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10029 | struct drm_crtc *crtc) | |
10030 | { | |
fac5e23e | 10031 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 10032 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10033 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10034 | struct drm_display_mode *mode; |
3f36b937 | 10035 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10036 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10037 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10038 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10039 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10040 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10041 | |
10042 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10043 | if (!mode) | |
10044 | return NULL; | |
10045 | ||
3f36b937 TU |
10046 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10047 | if (!pipe_config) { | |
10048 | kfree(mode); | |
10049 | return NULL; | |
10050 | } | |
10051 | ||
f1f644dc JB |
10052 | /* |
10053 | * Construct a pipe_config sufficient for getting the clock info | |
10054 | * back out of crtc_clock_get. | |
10055 | * | |
10056 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10057 | * to use a real value here instead. | |
10058 | */ | |
3f36b937 TU |
10059 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10060 | pipe_config->pixel_multiplier = 1; | |
10061 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10062 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10063 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10064 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10065 | ||
10066 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10067 | mode->hdisplay = (htot & 0xffff) + 1; |
10068 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10069 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10070 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10071 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10072 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10073 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10074 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10075 | ||
10076 | drm_mode_set_name(mode); | |
79e53945 | 10077 | |
3f36b937 TU |
10078 | kfree(pipe_config); |
10079 | ||
79e53945 JB |
10080 | return mode; |
10081 | } | |
10082 | ||
10083 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
10084 | { | |
10085 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 10086 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 10087 | struct intel_flip_work *work; |
67e77c5a | 10088 | |
5e2d7afc | 10089 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
10090 | work = intel_crtc->flip_work; |
10091 | intel_crtc->flip_work = NULL; | |
10092 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 10093 | |
5a21b665 | 10094 | if (work) { |
51cbaf01 ML |
10095 | cancel_work_sync(&work->mmio_work); |
10096 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 10097 | kfree(work); |
67e77c5a | 10098 | } |
79e53945 JB |
10099 | |
10100 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10101 | |
79e53945 JB |
10102 | kfree(intel_crtc); |
10103 | } | |
10104 | ||
6b95a207 KH |
10105 | static void intel_unpin_work_fn(struct work_struct *__work) |
10106 | { | |
51cbaf01 ML |
10107 | struct intel_flip_work *work = |
10108 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
10109 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10110 | struct drm_device *dev = crtc->base.dev; | |
10111 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 10112 | |
5a21b665 DV |
10113 | if (is_mmio_work(work)) |
10114 | flush_work(&work->mmio_work); | |
03f476e1 | 10115 | |
5a21b665 | 10116 | mutex_lock(&dev->struct_mutex); |
be1e3415 | 10117 | intel_unpin_fb_vma(work->old_vma); |
f8c417cd | 10118 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 10119 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 10120 | |
e8a261ea CW |
10121 | i915_gem_request_put(work->flip_queued_req); |
10122 | ||
5748b6a1 CW |
10123 | intel_frontbuffer_flip_complete(to_i915(dev), |
10124 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
10125 | intel_fbc_post_update(crtc); |
10126 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 10127 | |
5a21b665 DV |
10128 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10129 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 10130 | |
5a21b665 DV |
10131 | kfree(work); |
10132 | } | |
d9e86c0e | 10133 | |
5a21b665 DV |
10134 | /* Is 'a' after or equal to 'b'? */ |
10135 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10136 | { | |
10137 | return !((a - b) & 0x80000000); | |
10138 | } | |
143f73b3 | 10139 | |
5a21b665 DV |
10140 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
10141 | struct intel_flip_work *work) | |
10142 | { | |
10143 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10144 | struct drm_i915_private *dev_priv = to_i915(dev); |
143f73b3 | 10145 | |
8af29b0c | 10146 | if (abort_flip_on_reset(crtc)) |
5a21b665 | 10147 | return true; |
143f73b3 | 10148 | |
5a21b665 DV |
10149 | /* |
10150 | * The relevant registers doen't exist on pre-ctg. | |
10151 | * As the flip done interrupt doesn't trigger for mmio | |
10152 | * flips on gmch platforms, a flip count check isn't | |
10153 | * really needed there. But since ctg has the registers, | |
10154 | * include it in the check anyway. | |
10155 | */ | |
9beb5fea | 10156 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
5a21b665 | 10157 | return true; |
b4a98e57 | 10158 | |
5a21b665 DV |
10159 | /* |
10160 | * BDW signals flip done immediately if the plane | |
10161 | * is disabled, even if the plane enable is already | |
10162 | * armed to occur at the next vblank :( | |
10163 | */ | |
f99d7069 | 10164 | |
5a21b665 DV |
10165 | /* |
10166 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10167 | * used the same base address. In that case the mmio flip might | |
10168 | * have completed, but the CS hasn't even executed the flip yet. | |
10169 | * | |
10170 | * A flip count check isn't enough as the CS might have updated | |
10171 | * the base address just after start of vblank, but before we | |
10172 | * managed to process the interrupt. This means we'd complete the | |
10173 | * CS flip too soon. | |
10174 | * | |
10175 | * Combining both checks should get us a good enough result. It may | |
10176 | * still happen that the CS flip has been executed, but has not | |
10177 | * yet actually completed. But in case the base address is the same | |
10178 | * anyway, we don't really care. | |
10179 | */ | |
10180 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10181 | crtc->flip_work->gtt_offset && | |
10182 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
10183 | crtc->flip_work->flip_count); | |
10184 | } | |
b4a98e57 | 10185 | |
5a21b665 DV |
10186 | static bool |
10187 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
10188 | struct intel_flip_work *work) | |
10189 | { | |
10190 | /* | |
10191 | * MMIO work completes when vblank is different from | |
10192 | * flip_queued_vblank. | |
10193 | * | |
10194 | * Reset counter value doesn't matter, this is handled by | |
10195 | * i915_wait_request finishing early, so no need to handle | |
10196 | * reset here. | |
10197 | */ | |
10198 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
10199 | } |
10200 | ||
51cbaf01 ML |
10201 | |
10202 | static bool pageflip_finished(struct intel_crtc *crtc, | |
10203 | struct intel_flip_work *work) | |
10204 | { | |
10205 | if (!atomic_read(&work->pending)) | |
10206 | return false; | |
10207 | ||
10208 | smp_rmb(); | |
10209 | ||
5a21b665 DV |
10210 | if (is_mmio_work(work)) |
10211 | return __pageflip_finished_mmio(crtc, work); | |
10212 | else | |
10213 | return __pageflip_finished_cs(crtc, work); | |
10214 | } | |
10215 | ||
10216 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
10217 | { | |
91c8a326 | 10218 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10219 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
10220 | struct intel_flip_work *work; |
10221 | unsigned long flags; | |
10222 | ||
10223 | /* Ignore early vblank irqs */ | |
10224 | if (!crtc) | |
10225 | return; | |
10226 | ||
51cbaf01 | 10227 | /* |
5a21b665 DV |
10228 | * This is called both by irq handlers and the reset code (to complete |
10229 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 10230 | */ |
5a21b665 | 10231 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 10232 | work = crtc->flip_work; |
5a21b665 DV |
10233 | |
10234 | if (work != NULL && | |
10235 | !is_mmio_work(work) && | |
e2af48c6 VS |
10236 | pageflip_finished(crtc, work)) |
10237 | page_flip_completed(crtc); | |
5a21b665 DV |
10238 | |
10239 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
10240 | } |
10241 | ||
51cbaf01 | 10242 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 10243 | { |
91c8a326 | 10244 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10245 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
51cbaf01 | 10246 | struct intel_flip_work *work; |
6b95a207 KH |
10247 | unsigned long flags; |
10248 | ||
5251f04e ML |
10249 | /* Ignore early vblank irqs */ |
10250 | if (!crtc) | |
10251 | return; | |
f326038a DV |
10252 | |
10253 | /* | |
10254 | * This is called both by irq handlers and the reset code (to complete | |
10255 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 10256 | */ |
6b95a207 | 10257 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 10258 | work = crtc->flip_work; |
5251f04e | 10259 | |
5a21b665 DV |
10260 | if (work != NULL && |
10261 | is_mmio_work(work) && | |
e2af48c6 VS |
10262 | pageflip_finished(crtc, work)) |
10263 | page_flip_completed(crtc); | |
5251f04e | 10264 | |
6b95a207 KH |
10265 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10266 | } | |
10267 | ||
5a21b665 DV |
10268 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
10269 | struct intel_flip_work *work) | |
84c33a64 | 10270 | { |
5a21b665 | 10271 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 10272 | |
5a21b665 DV |
10273 | /* Ensure that the work item is consistent when activating it ... */ |
10274 | smp_mb__before_atomic(); | |
10275 | atomic_set(&work->pending, 1); | |
10276 | } | |
a6747b73 | 10277 | |
5a21b665 DV |
10278 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10279 | struct drm_crtc *crtc, | |
10280 | struct drm_framebuffer *fb, | |
10281 | struct drm_i915_gem_object *obj, | |
10282 | struct drm_i915_gem_request *req, | |
10283 | uint32_t flags) | |
10284 | { | |
5a21b665 | 10285 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10286 | u32 flip_mask, *cs; |
143f73b3 | 10287 | |
73dec95e TU |
10288 | cs = intel_ring_begin(req, 6); |
10289 | if (IS_ERR(cs)) | |
10290 | return PTR_ERR(cs); | |
143f73b3 | 10291 | |
5a21b665 DV |
10292 | /* Can't queue multiple flips, so wait for the previous |
10293 | * one to finish before executing the next. | |
10294 | */ | |
10295 | if (intel_crtc->plane) | |
10296 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10297 | else | |
10298 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
73dec95e TU |
10299 | *cs++ = MI_WAIT_FOR_EVENT | flip_mask; |
10300 | *cs++ = MI_NOOP; | |
10301 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); | |
10302 | *cs++ = fb->pitches[0]; | |
10303 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10304 | *cs++ = 0; /* aux display base address, unused */ | |
143f73b3 | 10305 | |
5a21b665 DV |
10306 | return 0; |
10307 | } | |
84c33a64 | 10308 | |
5a21b665 DV |
10309 | static int intel_gen3_queue_flip(struct drm_device *dev, |
10310 | struct drm_crtc *crtc, | |
10311 | struct drm_framebuffer *fb, | |
10312 | struct drm_i915_gem_object *obj, | |
10313 | struct drm_i915_gem_request *req, | |
10314 | uint32_t flags) | |
10315 | { | |
5a21b665 | 10316 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10317 | u32 flip_mask, *cs; |
d55dbd06 | 10318 | |
73dec95e TU |
10319 | cs = intel_ring_begin(req, 6); |
10320 | if (IS_ERR(cs)) | |
10321 | return PTR_ERR(cs); | |
d55dbd06 | 10322 | |
5a21b665 DV |
10323 | if (intel_crtc->plane) |
10324 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10325 | else | |
10326 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
73dec95e TU |
10327 | *cs++ = MI_WAIT_FOR_EVENT | flip_mask; |
10328 | *cs++ = MI_NOOP; | |
10329 | *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); | |
10330 | *cs++ = fb->pitches[0]; | |
10331 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10332 | *cs++ = MI_NOOP; | |
fd8e058a | 10333 | |
5a21b665 DV |
10334 | return 0; |
10335 | } | |
84c33a64 | 10336 | |
5a21b665 DV |
10337 | static int intel_gen4_queue_flip(struct drm_device *dev, |
10338 | struct drm_crtc *crtc, | |
10339 | struct drm_framebuffer *fb, | |
10340 | struct drm_i915_gem_object *obj, | |
10341 | struct drm_i915_gem_request *req, | |
10342 | uint32_t flags) | |
10343 | { | |
fac5e23e | 10344 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10346 | u32 pf, pipesrc, *cs; |
143f73b3 | 10347 | |
73dec95e TU |
10348 | cs = intel_ring_begin(req, 4); |
10349 | if (IS_ERR(cs)) | |
10350 | return PTR_ERR(cs); | |
143f73b3 | 10351 | |
5a21b665 DV |
10352 | /* i965+ uses the linear or tiled offsets from the |
10353 | * Display Registers (which do not change across a page-flip) | |
10354 | * so we need only reprogram the base address. | |
10355 | */ | |
73dec95e TU |
10356 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); |
10357 | *cs++ = fb->pitches[0]; | |
10358 | *cs++ = intel_crtc->flip_work->gtt_offset | | |
10359 | intel_fb_modifier_to_tiling(fb->modifier); | |
5a21b665 DV |
10360 | |
10361 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10362 | * untested on non-native modes, so ignore it for now. | |
10363 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10364 | */ | |
10365 | pf = 0; | |
10366 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
73dec95e | 10367 | *cs++ = pf | pipesrc; |
143f73b3 | 10368 | |
5a21b665 | 10369 | return 0; |
8c9f3aaf JB |
10370 | } |
10371 | ||
5a21b665 DV |
10372 | static int intel_gen6_queue_flip(struct drm_device *dev, |
10373 | struct drm_crtc *crtc, | |
10374 | struct drm_framebuffer *fb, | |
10375 | struct drm_i915_gem_object *obj, | |
10376 | struct drm_i915_gem_request *req, | |
10377 | uint32_t flags) | |
da20eabd | 10378 | { |
fac5e23e | 10379 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10381 | u32 pf, pipesrc, *cs; |
d21fbe87 | 10382 | |
73dec95e TU |
10383 | cs = intel_ring_begin(req, 4); |
10384 | if (IS_ERR(cs)) | |
10385 | return PTR_ERR(cs); | |
92826fcd | 10386 | |
73dec95e TU |
10387 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); |
10388 | *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); | |
10389 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
92826fcd | 10390 | |
5a21b665 DV |
10391 | /* Contrary to the suggestions in the documentation, |
10392 | * "Enable Panel Fitter" does not seem to be required when page | |
10393 | * flipping with a non-native mode, and worse causes a normal | |
10394 | * modeset to fail. | |
10395 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10396 | */ | |
10397 | pf = 0; | |
10398 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
73dec95e | 10399 | *cs++ = pf | pipesrc; |
7809e5ae | 10400 | |
5a21b665 | 10401 | return 0; |
7809e5ae MR |
10402 | } |
10403 | ||
5a21b665 DV |
10404 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10405 | struct drm_crtc *crtc, | |
10406 | struct drm_framebuffer *fb, | |
10407 | struct drm_i915_gem_object *obj, | |
10408 | struct drm_i915_gem_request *req, | |
10409 | uint32_t flags) | |
d21fbe87 | 10410 | { |
5db94019 | 10411 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10412 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10413 | u32 *cs, plane_bit = 0; |
5a21b665 | 10414 | int len, ret; |
d21fbe87 | 10415 | |
5a21b665 DV |
10416 | switch (intel_crtc->plane) { |
10417 | case PLANE_A: | |
10418 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10419 | break; | |
10420 | case PLANE_B: | |
10421 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10422 | break; | |
10423 | case PLANE_C: | |
10424 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10425 | break; | |
10426 | default: | |
10427 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
10428 | return -ENODEV; | |
10429 | } | |
10430 | ||
10431 | len = 4; | |
b5321f30 | 10432 | if (req->engine->id == RCS) { |
5a21b665 DV |
10433 | len += 6; |
10434 | /* | |
10435 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10436 | * 48bits addresses, and we need a NOOP for the batch size to | |
10437 | * stay even. | |
10438 | */ | |
5db94019 | 10439 | if (IS_GEN8(dev_priv)) |
5a21b665 DV |
10440 | len += 2; |
10441 | } | |
10442 | ||
10443 | /* | |
10444 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10445 | * "The full packet must be contained within the same cache line." | |
10446 | * | |
10447 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10448 | * cacheline, if we ever start emitting more commands before | |
10449 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10450 | * then do the cacheline alignment, and finally emit the | |
10451 | * MI_DISPLAY_FLIP. | |
10452 | */ | |
10453 | ret = intel_ring_cacheline_align(req); | |
10454 | if (ret) | |
10455 | return ret; | |
10456 | ||
73dec95e TU |
10457 | cs = intel_ring_begin(req, len); |
10458 | if (IS_ERR(cs)) | |
10459 | return PTR_ERR(cs); | |
5a21b665 DV |
10460 | |
10461 | /* Unmask the flip-done completion message. Note that the bspec says that | |
10462 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10463 | * more than one flip event at any time (or ensure that one flip message | |
10464 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10465 | * Experimentation says that BCS works despite DERRMR masking all | |
10466 | * flip-done completion events and that unmasking all planes at once | |
10467 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10468 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10469 | */ | |
b5321f30 | 10470 | if (req->engine->id == RCS) { |
73dec95e TU |
10471 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
10472 | *cs++ = i915_mmio_reg_offset(DERRMR); | |
10473 | *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10474 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10475 | DERRMR_PIPEC_PRI_FLIP_DONE); | |
5db94019 | 10476 | if (IS_GEN8(dev_priv)) |
73dec95e TU |
10477 | *cs++ = MI_STORE_REGISTER_MEM_GEN8 | |
10478 | MI_SRM_LRM_GLOBAL_GTT; | |
5a21b665 | 10479 | else |
73dec95e TU |
10480 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; |
10481 | *cs++ = i915_mmio_reg_offset(DERRMR); | |
10482 | *cs++ = i915_ggtt_offset(req->engine->scratch) + 256; | |
5db94019 | 10483 | if (IS_GEN8(dev_priv)) { |
73dec95e TU |
10484 | *cs++ = 0; |
10485 | *cs++ = MI_NOOP; | |
5a21b665 DV |
10486 | } |
10487 | } | |
10488 | ||
73dec95e TU |
10489 | *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit; |
10490 | *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); | |
10491 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10492 | *cs++ = MI_NOOP; | |
5a21b665 DV |
10493 | |
10494 | return 0; | |
10495 | } | |
10496 | ||
10497 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
10498 | struct drm_i915_gem_object *obj) | |
10499 | { | |
10500 | /* | |
10501 | * This is not being used for older platforms, because | |
10502 | * non-availability of flip done interrupt forces us to use | |
10503 | * CS flips. Older platforms derive flip done using some clever | |
10504 | * tricks involving the flip_pending status bits and vblank irqs. | |
10505 | * So using MMIO flips there would disrupt this mechanism. | |
10506 | */ | |
10507 | ||
10508 | if (engine == NULL) | |
10509 | return true; | |
10510 | ||
10511 | if (INTEL_GEN(engine->i915) < 5) | |
10512 | return false; | |
10513 | ||
10514 | if (i915.use_mmio_flip < 0) | |
10515 | return false; | |
10516 | else if (i915.use_mmio_flip > 0) | |
10517 | return true; | |
10518 | else if (i915.enable_execlists) | |
10519 | return true; | |
c37efb99 | 10520 | |
d07f0e59 | 10521 | return engine != i915_gem_object_last_write_engine(obj); |
5a21b665 DV |
10522 | } |
10523 | ||
10524 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
10525 | unsigned int rotation, | |
10526 | struct intel_flip_work *work) | |
10527 | { | |
10528 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 10529 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
10530 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
10531 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 10532 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
10533 | |
10534 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10535 | ctl &= ~PLANE_CTL_TILED_MASK; | |
bae781b2 | 10536 | switch (fb->modifier) { |
2f075565 | 10537 | case DRM_FORMAT_MOD_LINEAR: |
5a21b665 DV |
10538 | break; |
10539 | case I915_FORMAT_MOD_X_TILED: | |
10540 | ctl |= PLANE_CTL_TILED_X; | |
10541 | break; | |
10542 | case I915_FORMAT_MOD_Y_TILED: | |
10543 | ctl |= PLANE_CTL_TILED_Y; | |
10544 | break; | |
10545 | case I915_FORMAT_MOD_Yf_TILED: | |
10546 | ctl |= PLANE_CTL_TILED_YF; | |
10547 | break; | |
10548 | default: | |
bae781b2 | 10549 | MISSING_CASE(fb->modifier); |
5a21b665 DV |
10550 | } |
10551 | ||
5a21b665 DV |
10552 | /* |
10553 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10554 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10555 | */ | |
10556 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10557 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10558 | ||
10559 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
10560 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10561 | } | |
10562 | ||
10563 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
10564 | struct intel_flip_work *work) | |
10565 | { | |
10566 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 10567 | struct drm_i915_private *dev_priv = to_i915(dev); |
72618ebf | 10568 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
5a21b665 DV |
10569 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
10570 | u32 dspcntr; | |
10571 | ||
10572 | dspcntr = I915_READ(reg); | |
10573 | ||
bae781b2 | 10574 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
5a21b665 DV |
10575 | dspcntr |= DISPPLANE_TILED; |
10576 | else | |
10577 | dspcntr &= ~DISPPLANE_TILED; | |
10578 | ||
10579 | I915_WRITE(reg, dspcntr); | |
10580 | ||
10581 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
10582 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
10583 | } | |
10584 | ||
10585 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
10586 | { | |
10587 | struct intel_flip_work *work = | |
10588 | container_of(w, struct intel_flip_work, mmio_work); | |
10589 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
10590 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
10591 | struct intel_framebuffer *intel_fb = | |
10592 | to_intel_framebuffer(crtc->base.primary->fb); | |
10593 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10594 | ||
d07f0e59 | 10595 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); |
5a21b665 DV |
10596 | |
10597 | intel_pipe_update_start(crtc); | |
10598 | ||
10599 | if (INTEL_GEN(dev_priv) >= 9) | |
10600 | skl_do_mmio_flip(crtc, work->rotation, work); | |
10601 | else | |
10602 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10603 | ilk_do_mmio_flip(crtc, work); | |
10604 | ||
10605 | intel_pipe_update_end(crtc, work); | |
10606 | } | |
10607 | ||
10608 | static int intel_default_queue_flip(struct drm_device *dev, | |
10609 | struct drm_crtc *crtc, | |
10610 | struct drm_framebuffer *fb, | |
10611 | struct drm_i915_gem_object *obj, | |
10612 | struct drm_i915_gem_request *req, | |
10613 | uint32_t flags) | |
10614 | { | |
10615 | return -ENODEV; | |
10616 | } | |
10617 | ||
10618 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
10619 | struct intel_crtc *intel_crtc, | |
10620 | struct intel_flip_work *work) | |
10621 | { | |
10622 | u32 addr, vblank; | |
10623 | ||
10624 | if (!atomic_read(&work->pending)) | |
10625 | return false; | |
10626 | ||
10627 | smp_rmb(); | |
10628 | ||
10629 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
10630 | if (work->flip_ready_vblank == 0) { | |
10631 | if (work->flip_queued_req && | |
f69a02c9 | 10632 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
10633 | return false; |
10634 | ||
10635 | work->flip_ready_vblank = vblank; | |
10636 | } | |
10637 | ||
10638 | if (vblank - work->flip_ready_vblank < 3) | |
10639 | return false; | |
10640 | ||
10641 | /* Potential stall - if we see that the flip has happened, | |
10642 | * assume a missed interrupt. */ | |
10643 | if (INTEL_GEN(dev_priv) >= 4) | |
10644 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10645 | else | |
10646 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10647 | ||
10648 | /* There is a potential issue here with a false positive after a flip | |
10649 | * to the same address. We could address this by checking for a | |
10650 | * non-incrementing frame counter. | |
10651 | */ | |
10652 | return addr == work->gtt_offset; | |
10653 | } | |
10654 | ||
10655 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
10656 | { | |
91c8a326 | 10657 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10658 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
10659 | struct intel_flip_work *work; |
10660 | ||
10661 | WARN_ON(!in_interrupt()); | |
10662 | ||
10663 | if (crtc == NULL) | |
10664 | return; | |
10665 | ||
10666 | spin_lock(&dev->event_lock); | |
e2af48c6 | 10667 | work = crtc->flip_work; |
5a21b665 DV |
10668 | |
10669 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 10670 | __pageflip_stall_check_cs(dev_priv, crtc, work)) { |
5a21b665 DV |
10671 | WARN_ONCE(1, |
10672 | "Kicking stuck page flip: queued at %d, now %d\n", | |
e2af48c6 VS |
10673 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); |
10674 | page_flip_completed(crtc); | |
5a21b665 DV |
10675 | work = NULL; |
10676 | } | |
10677 | ||
10678 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 10679 | intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) |
5a21b665 DV |
10680 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
10681 | spin_unlock(&dev->event_lock); | |
10682 | } | |
10683 | ||
4c01ded5 | 10684 | __maybe_unused |
5a21b665 DV |
10685 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10686 | struct drm_framebuffer *fb, | |
10687 | struct drm_pending_vblank_event *event, | |
10688 | uint32_t page_flip_flags) | |
10689 | { | |
10690 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10691 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
10692 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
10693 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
10694 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10695 | struct drm_plane *primary = crtc->primary; | |
10696 | enum pipe pipe = intel_crtc->pipe; | |
10697 | struct intel_flip_work *work; | |
10698 | struct intel_engine_cs *engine; | |
10699 | bool mmio_flip; | |
8e637178 | 10700 | struct drm_i915_gem_request *request; |
058d88c4 | 10701 | struct i915_vma *vma; |
5a21b665 DV |
10702 | int ret; |
10703 | ||
10704 | /* | |
10705 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10706 | * check to be safe. In the future we may enable pageflipping from | |
10707 | * a disabled primary plane. | |
10708 | */ | |
10709 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10710 | return -EBUSY; | |
10711 | ||
10712 | /* Can't change pixel format via MI display flips. */ | |
dbd4d576 | 10713 | if (fb->format != crtc->primary->fb->format) |
5a21b665 DV |
10714 | return -EINVAL; |
10715 | ||
10716 | /* | |
10717 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10718 | * Note that pitch changes could also affect these register. | |
10719 | */ | |
6315b5d3 | 10720 | if (INTEL_GEN(dev_priv) > 3 && |
5a21b665 DV |
10721 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10722 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
10723 | return -EINVAL; | |
10724 | ||
10725 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
10726 | goto out_hang; | |
10727 | ||
10728 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
10729 | if (work == NULL) | |
10730 | return -ENOMEM; | |
10731 | ||
10732 | work->event = event; | |
10733 | work->crtc = crtc; | |
10734 | work->old_fb = old_fb; | |
10735 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
10736 | ||
10737 | ret = drm_crtc_vblank_get(crtc); | |
10738 | if (ret) | |
10739 | goto free_work; | |
10740 | ||
10741 | /* We borrow the event spin lock for protecting flip_work */ | |
10742 | spin_lock_irq(&dev->event_lock); | |
10743 | if (intel_crtc->flip_work) { | |
10744 | /* Before declaring the flip queue wedged, check if | |
10745 | * the hardware completed the operation behind our backs. | |
10746 | */ | |
10747 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
10748 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10749 | page_flip_completed(intel_crtc); | |
10750 | } else { | |
10751 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
10752 | spin_unlock_irq(&dev->event_lock); | |
10753 | ||
10754 | drm_crtc_vblank_put(crtc); | |
10755 | kfree(work); | |
10756 | return -EBUSY; | |
10757 | } | |
10758 | } | |
10759 | intel_crtc->flip_work = work; | |
10760 | spin_unlock_irq(&dev->event_lock); | |
10761 | ||
10762 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
10763 | flush_workqueue(dev_priv->wq); | |
10764 | ||
10765 | /* Reference the objects for the scheduled work. */ | |
10766 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
10767 | |
10768 | crtc->primary->fb = fb; | |
10769 | update_state_fb(crtc->primary); | |
faf68d92 | 10770 | |
25dc556a | 10771 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
10772 | |
10773 | ret = i915_mutex_lock_interruptible(dev); | |
10774 | if (ret) | |
10775 | goto cleanup; | |
10776 | ||
8af29b0c | 10777 | intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); |
8c185eca | 10778 | if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) { |
5a21b665 | 10779 | ret = -EIO; |
ddbb271a | 10780 | goto unlock; |
5a21b665 DV |
10781 | } |
10782 | ||
10783 | atomic_inc(&intel_crtc->unpin_work_count); | |
10784 | ||
9beb5fea | 10785 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
5a21b665 DV |
10786 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
10787 | ||
920a14b2 | 10788 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3b3f1650 | 10789 | engine = dev_priv->engine[BCS]; |
bae781b2 | 10790 | if (fb->modifier != old_fb->modifier) |
5a21b665 DV |
10791 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10792 | engine = NULL; | |
fd6b8f43 | 10793 | } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { |
3b3f1650 | 10794 | engine = dev_priv->engine[BCS]; |
6315b5d3 | 10795 | } else if (INTEL_GEN(dev_priv) >= 7) { |
d07f0e59 | 10796 | engine = i915_gem_object_last_write_engine(obj); |
5a21b665 | 10797 | if (engine == NULL || engine->id != RCS) |
3b3f1650 | 10798 | engine = dev_priv->engine[BCS]; |
5a21b665 | 10799 | } else { |
3b3f1650 | 10800 | engine = dev_priv->engine[RCS]; |
5a21b665 DV |
10801 | } |
10802 | ||
10803 | mmio_flip = use_mmio_flip(engine, obj); | |
10804 | ||
058d88c4 CW |
10805 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
10806 | if (IS_ERR(vma)) { | |
10807 | ret = PTR_ERR(vma); | |
5a21b665 | 10808 | goto cleanup_pending; |
058d88c4 | 10809 | } |
5a21b665 | 10810 | |
be1e3415 CW |
10811 | work->old_vma = to_intel_plane_state(primary->state)->vma; |
10812 | to_intel_plane_state(primary->state)->vma = vma; | |
10813 | ||
10814 | work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset; | |
5a21b665 DV |
10815 | work->rotation = crtc->primary->state->rotation; |
10816 | ||
1f061316 PZ |
10817 | /* |
10818 | * There's the potential that the next frame will not be compatible with | |
10819 | * FBC, so we want to call pre_update() before the actual page flip. | |
10820 | * The problem is that pre_update() caches some information about the fb | |
10821 | * object, so we want to do this only after the object is pinned. Let's | |
10822 | * be on the safe side and do this immediately before scheduling the | |
10823 | * flip. | |
10824 | */ | |
10825 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
10826 | to_intel_plane_state(primary->state)); | |
10827 | ||
5a21b665 DV |
10828 | if (mmio_flip) { |
10829 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
6277c8d0 | 10830 | queue_work(system_unbound_wq, &work->mmio_work); |
5a21b665 | 10831 | } else { |
e8a9c58f CW |
10832 | request = i915_gem_request_alloc(engine, |
10833 | dev_priv->kernel_context); | |
8e637178 CW |
10834 | if (IS_ERR(request)) { |
10835 | ret = PTR_ERR(request); | |
10836 | goto cleanup_unpin; | |
10837 | } | |
10838 | ||
a2bc4695 | 10839 | ret = i915_gem_request_await_object(request, obj, false); |
8e637178 CW |
10840 | if (ret) |
10841 | goto cleanup_request; | |
10842 | ||
5a21b665 DV |
10843 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
10844 | page_flip_flags); | |
10845 | if (ret) | |
8e637178 | 10846 | goto cleanup_request; |
5a21b665 DV |
10847 | |
10848 | intel_mark_page_flip_active(intel_crtc, work); | |
10849 | ||
8e637178 | 10850 | work->flip_queued_req = i915_gem_request_get(request); |
e642c85b | 10851 | i915_add_request(request); |
5a21b665 DV |
10852 | } |
10853 | ||
92117f0b | 10854 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); |
5a21b665 DV |
10855 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, |
10856 | to_intel_plane(primary)->frontbuffer_bit); | |
10857 | mutex_unlock(&dev->struct_mutex); | |
10858 | ||
5748b6a1 | 10859 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
10860 | to_intel_plane(primary)->frontbuffer_bit); |
10861 | ||
10862 | trace_i915_flip_request(intel_crtc->plane, obj); | |
10863 | ||
10864 | return 0; | |
10865 | ||
8e637178 | 10866 | cleanup_request: |
e642c85b | 10867 | i915_add_request(request); |
5a21b665 | 10868 | cleanup_unpin: |
be1e3415 CW |
10869 | to_intel_plane_state(primary->state)->vma = work->old_vma; |
10870 | intel_unpin_fb_vma(vma); | |
5a21b665 | 10871 | cleanup_pending: |
5a21b665 | 10872 | atomic_dec(&intel_crtc->unpin_work_count); |
ddbb271a | 10873 | unlock: |
5a21b665 DV |
10874 | mutex_unlock(&dev->struct_mutex); |
10875 | cleanup: | |
10876 | crtc->primary->fb = old_fb; | |
10877 | update_state_fb(crtc->primary); | |
10878 | ||
f0cd5182 | 10879 | i915_gem_object_put(obj); |
5a21b665 DV |
10880 | drm_framebuffer_unreference(work->old_fb); |
10881 | ||
10882 | spin_lock_irq(&dev->event_lock); | |
10883 | intel_crtc->flip_work = NULL; | |
10884 | spin_unlock_irq(&dev->event_lock); | |
10885 | ||
10886 | drm_crtc_vblank_put(crtc); | |
10887 | free_work: | |
10888 | kfree(work); | |
10889 | ||
10890 | if (ret == -EIO) { | |
10891 | struct drm_atomic_state *state; | |
10892 | struct drm_plane_state *plane_state; | |
10893 | ||
10894 | out_hang: | |
10895 | state = drm_atomic_state_alloc(dev); | |
10896 | if (!state) | |
10897 | return -ENOMEM; | |
b260ac3e | 10898 | state->acquire_ctx = dev->mode_config.acquire_ctx; |
5a21b665 DV |
10899 | |
10900 | retry: | |
10901 | plane_state = drm_atomic_get_plane_state(state, primary); | |
10902 | ret = PTR_ERR_OR_ZERO(plane_state); | |
10903 | if (!ret) { | |
10904 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10905 | ||
10906 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
10907 | if (!ret) | |
10908 | ret = drm_atomic_commit(state); | |
10909 | } | |
10910 | ||
10911 | if (ret == -EDEADLK) { | |
10912 | drm_modeset_backoff(state->acquire_ctx); | |
10913 | drm_atomic_state_clear(state); | |
10914 | goto retry; | |
10915 | } | |
10916 | ||
0853695c | 10917 | drm_atomic_state_put(state); |
5a21b665 DV |
10918 | |
10919 | if (ret == 0 && event) { | |
10920 | spin_lock_irq(&dev->event_lock); | |
10921 | drm_crtc_send_vblank_event(crtc, event); | |
10922 | spin_unlock_irq(&dev->event_lock); | |
10923 | } | |
10924 | } | |
10925 | return ret; | |
10926 | } | |
10927 | ||
10928 | ||
10929 | /** | |
10930 | * intel_wm_need_update - Check whether watermarks need updating | |
10931 | * @plane: drm plane | |
10932 | * @state: new plane state | |
10933 | * | |
10934 | * Check current plane state versus the new one to determine whether | |
10935 | * watermarks need to be recalculated. | |
10936 | * | |
10937 | * Returns true or false. | |
10938 | */ | |
10939 | static bool intel_wm_need_update(struct drm_plane *plane, | |
10940 | struct drm_plane_state *state) | |
10941 | { | |
10942 | struct intel_plane_state *new = to_intel_plane_state(state); | |
10943 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
10944 | ||
10945 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 10946 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
10947 | return true; |
10948 | ||
10949 | if (!cur->base.fb || !new->base.fb) | |
10950 | return false; | |
10951 | ||
bae781b2 | 10952 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 10953 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
10954 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
10955 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
10956 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
10957 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
10958 | return true; |
10959 | ||
10960 | return false; | |
10961 | } | |
10962 | ||
10963 | static bool needs_scaling(struct intel_plane_state *state) | |
10964 | { | |
936e71e3 VS |
10965 | int src_w = drm_rect_width(&state->base.src) >> 16; |
10966 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
10967 | int dst_w = drm_rect_width(&state->base.dst); | |
10968 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
10969 | |
10970 | return (src_w != dst_w || src_h != dst_h); | |
10971 | } | |
d21fbe87 | 10972 | |
da20eabd ML |
10973 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
10974 | struct drm_plane_state *plane_state) | |
10975 | { | |
ab1d3a0e | 10976 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
10977 | struct drm_crtc *crtc = crtc_state->crtc; |
10978 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e9728bd8 | 10979 | struct intel_plane *plane = to_intel_plane(plane_state->plane); |
da20eabd | 10980 | struct drm_device *dev = crtc->dev; |
ed4a6a7c | 10981 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd | 10982 | struct intel_plane_state *old_plane_state = |
e9728bd8 | 10983 | to_intel_plane_state(plane->base.state); |
da20eabd ML |
10984 | bool mode_changed = needs_modeset(crtc_state); |
10985 | bool was_crtc_enabled = crtc->state->active; | |
10986 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
10987 | bool turn_off, turn_on, visible, was_visible; |
10988 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 10989 | int ret; |
da20eabd | 10990 | |
e9728bd8 | 10991 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
da20eabd ML |
10992 | ret = skl_update_scaler_plane( |
10993 | to_intel_crtc_state(crtc_state), | |
10994 | to_intel_plane_state(plane_state)); | |
10995 | if (ret) | |
10996 | return ret; | |
10997 | } | |
10998 | ||
936e71e3 | 10999 | was_visible = old_plane_state->base.visible; |
1d4258db | 11000 | visible = plane_state->visible; |
da20eabd ML |
11001 | |
11002 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11003 | was_visible = false; | |
11004 | ||
35c08f43 ML |
11005 | /* |
11006 | * Visibility is calculated as if the crtc was on, but | |
11007 | * after scaler setup everything depends on it being off | |
11008 | * when the crtc isn't active. | |
f818ffea VS |
11009 | * |
11010 | * FIXME this is wrong for watermarks. Watermarks should also | |
11011 | * be computed as if the pipe would be active. Perhaps move | |
11012 | * per-plane wm computation to the .check_plane() hook, and | |
11013 | * only combine the results from all planes in the current place? | |
35c08f43 | 11014 | */ |
e9728bd8 | 11015 | if (!is_crtc_enabled) { |
1d4258db | 11016 | plane_state->visible = visible = false; |
e9728bd8 VS |
11017 | to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); |
11018 | } | |
da20eabd ML |
11019 | |
11020 | if (!was_visible && !visible) | |
11021 | return 0; | |
11022 | ||
e8861675 ML |
11023 | if (fb != old_plane_state->base.fb) |
11024 | pipe_config->fb_changed = true; | |
11025 | ||
da20eabd ML |
11026 | turn_off = was_visible && (!visible || mode_changed); |
11027 | turn_on = visible && (!was_visible || mode_changed); | |
11028 | ||
72660ce0 | 11029 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
e9728bd8 VS |
11030 | intel_crtc->base.base.id, intel_crtc->base.name, |
11031 | plane->base.base.id, plane->base.name, | |
72660ce0 | 11032 | fb ? fb->base.id : -1); |
da20eabd | 11033 | |
72660ce0 | 11034 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
e9728bd8 | 11035 | plane->base.base.id, plane->base.name, |
72660ce0 | 11036 | was_visible, visible, |
da20eabd ML |
11037 | turn_off, turn_on, mode_changed); |
11038 | ||
caed361d | 11039 | if (turn_on) { |
04548cba | 11040 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 11041 | pipe_config->update_wm_pre = true; |
caed361d VS |
11042 | |
11043 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 11044 | if (plane->id != PLANE_CURSOR) |
caed361d VS |
11045 | pipe_config->disable_cxsr = true; |
11046 | } else if (turn_off) { | |
04548cba | 11047 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 11048 | pipe_config->update_wm_post = true; |
92826fcd | 11049 | |
852eb00d | 11050 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 11051 | if (plane->id != PLANE_CURSOR) |
ab1d3a0e | 11052 | pipe_config->disable_cxsr = true; |
e9728bd8 | 11053 | } else if (intel_wm_need_update(&plane->base, plane_state)) { |
04548cba | 11054 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
b4ede6df VS |
11055 | /* FIXME bollocks */ |
11056 | pipe_config->update_wm_pre = true; | |
11057 | pipe_config->update_wm_post = true; | |
11058 | } | |
852eb00d | 11059 | } |
da20eabd | 11060 | |
8be6ca85 | 11061 | if (visible || was_visible) |
e9728bd8 | 11062 | pipe_config->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 11063 | |
31ae71fc ML |
11064 | /* |
11065 | * WaCxSRDisabledForSpriteScaling:ivb | |
11066 | * | |
11067 | * cstate->update_wm was already set above, so this flag will | |
11068 | * take effect when we commit and program watermarks. | |
11069 | */ | |
e9728bd8 | 11070 | if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
11071 | needs_scaling(to_intel_plane_state(plane_state)) && |
11072 | !needs_scaling(old_plane_state)) | |
11073 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 11074 | |
da20eabd ML |
11075 | return 0; |
11076 | } | |
11077 | ||
6d3a1ce7 ML |
11078 | static bool encoders_cloneable(const struct intel_encoder *a, |
11079 | const struct intel_encoder *b) | |
11080 | { | |
11081 | /* masks could be asymmetric, so check both ways */ | |
11082 | return a == b || (a->cloneable & (1 << b->type) && | |
11083 | b->cloneable & (1 << a->type)); | |
11084 | } | |
11085 | ||
11086 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11087 | struct intel_crtc *crtc, | |
11088 | struct intel_encoder *encoder) | |
11089 | { | |
11090 | struct intel_encoder *source_encoder; | |
11091 | struct drm_connector *connector; | |
11092 | struct drm_connector_state *connector_state; | |
11093 | int i; | |
11094 | ||
aa5e9b47 | 11095 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
6d3a1ce7 ML |
11096 | if (connector_state->crtc != &crtc->base) |
11097 | continue; | |
11098 | ||
11099 | source_encoder = | |
11100 | to_intel_encoder(connector_state->best_encoder); | |
11101 | if (!encoders_cloneable(encoder, source_encoder)) | |
11102 | return false; | |
11103 | } | |
11104 | ||
11105 | return true; | |
11106 | } | |
11107 | ||
6d3a1ce7 ML |
11108 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
11109 | struct drm_crtc_state *crtc_state) | |
11110 | { | |
cf5a15be | 11111 | struct drm_device *dev = crtc->dev; |
fac5e23e | 11112 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 11113 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11114 | struct intel_crtc_state *pipe_config = |
11115 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11116 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11117 | int ret; |
6d3a1ce7 ML |
11118 | bool mode_changed = needs_modeset(crtc_state); |
11119 | ||
852eb00d | 11120 | if (mode_changed && !crtc_state->active) |
caed361d | 11121 | pipe_config->update_wm_post = true; |
eddfcbcd | 11122 | |
ad421372 ML |
11123 | if (mode_changed && crtc_state->enable && |
11124 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 11125 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
11126 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
11127 | pipe_config); | |
11128 | if (ret) | |
11129 | return ret; | |
11130 | } | |
11131 | ||
82cf435b LL |
11132 | if (crtc_state->color_mgmt_changed) { |
11133 | ret = intel_color_check(crtc, crtc_state); | |
11134 | if (ret) | |
11135 | return ret; | |
e7852a4b LL |
11136 | |
11137 | /* | |
11138 | * Changing color management on Intel hardware is | |
11139 | * handled as part of planes update. | |
11140 | */ | |
11141 | crtc_state->planes_changed = true; | |
82cf435b LL |
11142 | } |
11143 | ||
e435d6e5 | 11144 | ret = 0; |
86c8bbbe | 11145 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 11146 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
11147 | if (ret) { |
11148 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
11149 | return ret; | |
11150 | } | |
11151 | } | |
11152 | ||
11153 | if (dev_priv->display.compute_intermediate_wm && | |
11154 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
11155 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
11156 | return 0; | |
11157 | ||
11158 | /* | |
11159 | * Calculate 'intermediate' watermarks that satisfy both the | |
11160 | * old state and the new state. We can program these | |
11161 | * immediately. | |
11162 | */ | |
6315b5d3 | 11163 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
11164 | intel_crtc, |
11165 | pipe_config); | |
11166 | if (ret) { | |
11167 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 11168 | return ret; |
ed4a6a7c | 11169 | } |
e3d5457c VS |
11170 | } else if (dev_priv->display.compute_intermediate_wm) { |
11171 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
11172 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
11173 | } |
11174 | ||
6315b5d3 | 11175 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
11176 | if (mode_changed) |
11177 | ret = skl_update_scaler_crtc(pipe_config); | |
11178 | ||
11179 | if (!ret) | |
6ebc6923 | 11180 | ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, |
e435d6e5 ML |
11181 | pipe_config); |
11182 | } | |
11183 | ||
11184 | return ret; | |
6d3a1ce7 ML |
11185 | } |
11186 | ||
65b38e0d | 11187 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
5a21b665 DV |
11188 | .atomic_begin = intel_begin_crtc_commit, |
11189 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11190 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11191 | }; |
11192 | ||
d29b2f9d ACO |
11193 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11194 | { | |
11195 | struct intel_connector *connector; | |
f9e905ca | 11196 | struct drm_connector_list_iter conn_iter; |
d29b2f9d | 11197 | |
f9e905ca DV |
11198 | drm_connector_list_iter_begin(dev, &conn_iter); |
11199 | for_each_intel_connector_iter(connector, &conn_iter) { | |
8863dc7f DV |
11200 | if (connector->base.state->crtc) |
11201 | drm_connector_unreference(&connector->base); | |
11202 | ||
d29b2f9d ACO |
11203 | if (connector->base.encoder) { |
11204 | connector->base.state->best_encoder = | |
11205 | connector->base.encoder; | |
11206 | connector->base.state->crtc = | |
11207 | connector->base.encoder->crtc; | |
8863dc7f DV |
11208 | |
11209 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
11210 | } else { |
11211 | connector->base.state->best_encoder = NULL; | |
11212 | connector->base.state->crtc = NULL; | |
11213 | } | |
11214 | } | |
f9e905ca | 11215 | drm_connector_list_iter_end(&conn_iter); |
d29b2f9d ACO |
11216 | } |
11217 | ||
050f7aeb | 11218 | static void |
eba905b2 | 11219 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11220 | struct intel_crtc_state *pipe_config) |
050f7aeb | 11221 | { |
6a2a5c5d | 11222 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
11223 | int bpp = pipe_config->pipe_bpp; |
11224 | ||
11225 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
11226 | connector->base.base.id, |
11227 | connector->base.name); | |
050f7aeb DV |
11228 | |
11229 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 11230 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 11231 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
11232 | bpp, info->bpc * 3); |
11233 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
11234 | } |
11235 | ||
196f954e | 11236 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 11237 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
11238 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
11239 | bpp); | |
11240 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
11241 | } |
11242 | } | |
11243 | ||
4e53c2e0 | 11244 | static int |
050f7aeb | 11245 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11246 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11247 | { |
9beb5fea | 11248 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 11249 | struct drm_atomic_state *state; |
da3ced29 ACO |
11250 | struct drm_connector *connector; |
11251 | struct drm_connector_state *connector_state; | |
1486017f | 11252 | int bpp, i; |
4e53c2e0 | 11253 | |
9beb5fea TU |
11254 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
11255 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 11256 | bpp = 10*3; |
9beb5fea | 11257 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
11258 | bpp = 12*3; |
11259 | else | |
11260 | bpp = 8*3; | |
11261 | ||
4e53c2e0 | 11262 | |
4e53c2e0 DV |
11263 | pipe_config->pipe_bpp = bpp; |
11264 | ||
1486017f ACO |
11265 | state = pipe_config->base.state; |
11266 | ||
4e53c2e0 | 11267 | /* Clamp display bpp to EDID value */ |
aa5e9b47 | 11268 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
da3ced29 | 11269 | if (connector_state->crtc != &crtc->base) |
4e53c2e0 DV |
11270 | continue; |
11271 | ||
da3ced29 ACO |
11272 | connected_sink_compute_bpp(to_intel_connector(connector), |
11273 | pipe_config); | |
4e53c2e0 DV |
11274 | } |
11275 | ||
11276 | return bpp; | |
11277 | } | |
11278 | ||
644db711 DV |
11279 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11280 | { | |
11281 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11282 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11283 | mode->crtc_clock, |
644db711 DV |
11284 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11285 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11286 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11287 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11288 | } | |
11289 | ||
f6982332 TU |
11290 | static inline void |
11291 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 11292 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 11293 | { |
a4309657 TU |
11294 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11295 | id, lane_count, | |
f6982332 TU |
11296 | m_n->gmch_m, m_n->gmch_n, |
11297 | m_n->link_m, m_n->link_n, m_n->tu); | |
11298 | } | |
11299 | ||
c0b03411 | 11300 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11301 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11302 | const char *context) |
11303 | { | |
6a60cd87 | 11304 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 11305 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
11306 | struct drm_plane *plane; |
11307 | struct intel_plane *intel_plane; | |
11308 | struct intel_plane_state *state; | |
11309 | struct drm_framebuffer *fb; | |
11310 | ||
66766e4f TU |
11311 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
11312 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 11313 | |
2c89429e TU |
11314 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
11315 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 11316 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
11317 | |
11318 | if (pipe_config->has_pch_encoder) | |
11319 | intel_dump_m_n_config(pipe_config, "fdi", | |
11320 | pipe_config->fdi_lanes, | |
11321 | &pipe_config->fdi_m_n); | |
f6982332 TU |
11322 | |
11323 | if (intel_crtc_has_dp_encoder(pipe_config)) { | |
a4309657 TU |
11324 | intel_dump_m_n_config(pipe_config, "dp m_n", |
11325 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
11326 | if (pipe_config->has_drrs) |
11327 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
11328 | pipe_config->lane_count, | |
11329 | &pipe_config->dp_m2_n2); | |
f6982332 | 11330 | } |
b95af8be | 11331 | |
55072d19 | 11332 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 11333 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 11334 | |
c0b03411 | 11335 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11336 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11337 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11338 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11339 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
a7d1b3f4 | 11340 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", |
2c89429e | 11341 | pipe_config->port_clock, |
a7d1b3f4 VS |
11342 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
11343 | pipe_config->pixel_rate); | |
dd2f616d TU |
11344 | |
11345 | if (INTEL_GEN(dev_priv) >= 9) | |
11346 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
11347 | crtc->num_scalers, | |
11348 | pipe_config->scaler_state.scaler_users, | |
11349 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
11350 | |
11351 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
11352 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
11353 | pipe_config->gmch_pfit.control, | |
11354 | pipe_config->gmch_pfit.pgm_ratios, | |
11355 | pipe_config->gmch_pfit.lvds_border_bits); | |
11356 | else | |
11357 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
11358 | pipe_config->pch_pfit.pos, | |
11359 | pipe_config->pch_pfit.size, | |
08c4d7fc | 11360 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 11361 | |
2c89429e TU |
11362 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
11363 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 11364 | |
f50b79f0 | 11365 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 11366 | |
6a60cd87 CK |
11367 | DRM_DEBUG_KMS("planes on this crtc\n"); |
11368 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 11369 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
11370 | intel_plane = to_intel_plane(plane); |
11371 | if (intel_plane->pipe != crtc->pipe) | |
11372 | continue; | |
11373 | ||
11374 | state = to_intel_plane_state(plane->state); | |
11375 | fb = state->base.fb; | |
11376 | if (!fb) { | |
1d577e02 VS |
11377 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
11378 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
11379 | continue; |
11380 | } | |
11381 | ||
dd2f616d TU |
11382 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
11383 | plane->base.id, plane->name, | |
b3c11ac2 | 11384 | fb->base.id, fb->width, fb->height, |
438b74a5 | 11385 | drm_get_format_name(fb->format->format, &format_name)); |
dd2f616d TU |
11386 | if (INTEL_GEN(dev_priv) >= 9) |
11387 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
11388 | state->scaler_id, | |
11389 | state->base.src.x1 >> 16, | |
11390 | state->base.src.y1 >> 16, | |
11391 | drm_rect_width(&state->base.src) >> 16, | |
11392 | drm_rect_height(&state->base.src) >> 16, | |
11393 | state->base.dst.x1, state->base.dst.y1, | |
11394 | drm_rect_width(&state->base.dst), | |
11395 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 11396 | } |
c0b03411 DV |
11397 | } |
11398 | ||
5448a00d | 11399 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11400 | { |
5448a00d | 11401 | struct drm_device *dev = state->dev; |
da3ced29 | 11402 | struct drm_connector *connector; |
00f0b378 | 11403 | unsigned int used_ports = 0; |
477321e0 | 11404 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
11405 | |
11406 | /* | |
11407 | * Walk the connector list instead of the encoder | |
11408 | * list to detect the problem on ddi platforms | |
11409 | * where there's just one encoder per digital port. | |
11410 | */ | |
0bff4858 VS |
11411 | drm_for_each_connector(connector, dev) { |
11412 | struct drm_connector_state *connector_state; | |
11413 | struct intel_encoder *encoder; | |
11414 | ||
11415 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
11416 | if (!connector_state) | |
11417 | connector_state = connector->state; | |
11418 | ||
5448a00d | 11419 | if (!connector_state->best_encoder) |
00f0b378 VS |
11420 | continue; |
11421 | ||
5448a00d ACO |
11422 | encoder = to_intel_encoder(connector_state->best_encoder); |
11423 | ||
11424 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11425 | |
11426 | switch (encoder->type) { | |
11427 | unsigned int port_mask; | |
11428 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 11429 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 11430 | break; |
cca0502b | 11431 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
11432 | case INTEL_OUTPUT_HDMI: |
11433 | case INTEL_OUTPUT_EDP: | |
11434 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11435 | ||
11436 | /* the same port mustn't appear more than once */ | |
11437 | if (used_ports & port_mask) | |
11438 | return false; | |
11439 | ||
11440 | used_ports |= port_mask; | |
477321e0 VS |
11441 | break; |
11442 | case INTEL_OUTPUT_DP_MST: | |
11443 | used_mst_ports |= | |
11444 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
11445 | break; | |
00f0b378 VS |
11446 | default: |
11447 | break; | |
11448 | } | |
11449 | } | |
11450 | ||
477321e0 VS |
11451 | /* can't mix MST and SST/HDMI on the same port */ |
11452 | if (used_ports & used_mst_ports) | |
11453 | return false; | |
11454 | ||
00f0b378 VS |
11455 | return true; |
11456 | } | |
11457 | ||
83a57153 ACO |
11458 | static void |
11459 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11460 | { | |
ff32c54e VS |
11461 | struct drm_i915_private *dev_priv = |
11462 | to_i915(crtc_state->base.crtc->dev); | |
663a3640 | 11463 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 11464 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 11465 | struct intel_shared_dpll *shared_dpll; |
ff32c54e | 11466 | struct intel_crtc_wm_state wm_state; |
c4e2d043 | 11467 | bool force_thru; |
83a57153 | 11468 | |
7546a384 ACO |
11469 | /* FIXME: before the switch to atomic started, a new pipe_config was |
11470 | * kzalloc'd. Code that depends on any field being zero should be | |
11471 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
11472 | * only fields that are know to not cause problems are preserved. */ | |
11473 | ||
663a3640 | 11474 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
11475 | shared_dpll = crtc_state->shared_dpll; |
11476 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 11477 | force_thru = crtc_state->pch_pfit.force_thru; |
04548cba VS |
11478 | if (IS_G4X(dev_priv) || |
11479 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 11480 | wm_state = crtc_state->wm; |
4978cc93 | 11481 | |
d2fa80a5 CW |
11482 | /* Keep base drm_crtc_state intact, only clear our extended struct */ |
11483 | BUILD_BUG_ON(offsetof(struct intel_crtc_state, base)); | |
11484 | memset(&crtc_state->base + 1, 0, | |
11485 | sizeof(*crtc_state) - sizeof(crtc_state->base)); | |
4978cc93 | 11486 | |
663a3640 | 11487 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
11488 | crtc_state->shared_dpll = shared_dpll; |
11489 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 11490 | crtc_state->pch_pfit.force_thru = force_thru; |
04548cba VS |
11491 | if (IS_G4X(dev_priv) || |
11492 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 11493 | crtc_state->wm = wm_state; |
83a57153 ACO |
11494 | } |
11495 | ||
548ee15b | 11496 | static int |
b8cecdf5 | 11497 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 11498 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 11499 | { |
b359283a | 11500 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 11501 | struct intel_encoder *encoder; |
da3ced29 | 11502 | struct drm_connector *connector; |
0b901879 | 11503 | struct drm_connector_state *connector_state; |
d328c9d7 | 11504 | int base_bpp, ret = -EINVAL; |
0b901879 | 11505 | int i; |
e29c22c0 | 11506 | bool retry = true; |
ee7b9f93 | 11507 | |
83a57153 | 11508 | clear_intel_crtc_state(pipe_config); |
7758a113 | 11509 | |
e143a21c DV |
11510 | pipe_config->cpu_transcoder = |
11511 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 11512 | |
2960bc9c ID |
11513 | /* |
11514 | * Sanitize sync polarity flags based on requested ones. If neither | |
11515 | * positive or negative polarity is requested, treat this as meaning | |
11516 | * negative polarity. | |
11517 | */ | |
2d112de7 | 11518 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11519 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11520 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11521 | |
2d112de7 | 11522 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11523 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11524 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11525 | |
d328c9d7 DV |
11526 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11527 | pipe_config); | |
11528 | if (base_bpp < 0) | |
4e53c2e0 DV |
11529 | goto fail; |
11530 | ||
e41a56be VS |
11531 | /* |
11532 | * Determine the real pipe dimensions. Note that stereo modes can | |
11533 | * increase the actual pipe size due to the frame doubling and | |
11534 | * insertion of additional space for blanks between the frame. This | |
11535 | * is stored in the crtc timings. We use the requested mode to do this | |
11536 | * computation to clearly distinguish it from the adjusted mode, which | |
11537 | * can be changed by the connectors in the below retry loop. | |
11538 | */ | |
196cd5d3 | 11539 | drm_mode_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11540 | &pipe_config->pipe_src_w, |
11541 | &pipe_config->pipe_src_h); | |
e41a56be | 11542 | |
aa5e9b47 | 11543 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
253c84c8 VS |
11544 | if (connector_state->crtc != crtc) |
11545 | continue; | |
11546 | ||
11547 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11548 | ||
e25148d0 VS |
11549 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
11550 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11551 | goto fail; | |
11552 | } | |
11553 | ||
253c84c8 VS |
11554 | /* |
11555 | * Determine output_types before calling the .compute_config() | |
11556 | * hooks so that the hooks can use this information safely. | |
11557 | */ | |
11558 | pipe_config->output_types |= 1 << encoder->type; | |
11559 | } | |
11560 | ||
e29c22c0 | 11561 | encoder_retry: |
ef1b460d | 11562 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11563 | pipe_config->port_clock = 0; |
ef1b460d | 11564 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11565 | |
135c81b8 | 11566 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11567 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11568 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11569 | |
7758a113 DV |
11570 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11571 | * adjust it according to limitations or connector properties, and also | |
11572 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11573 | */ |
aa5e9b47 | 11574 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 11575 | if (connector_state->crtc != crtc) |
7758a113 | 11576 | continue; |
7ae89233 | 11577 | |
0b901879 ACO |
11578 | encoder = to_intel_encoder(connector_state->best_encoder); |
11579 | ||
0a478c27 | 11580 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 11581 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
11582 | goto fail; |
11583 | } | |
ee7b9f93 | 11584 | } |
47f1c6c9 | 11585 | |
ff9a6750 DV |
11586 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11587 | * done afterwards in case the encoder adjusts the mode. */ | |
11588 | if (!pipe_config->port_clock) | |
2d112de7 | 11589 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11590 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11591 | |
a43f6e0f | 11592 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11593 | if (ret < 0) { |
7758a113 DV |
11594 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11595 | goto fail; | |
ee7b9f93 | 11596 | } |
e29c22c0 DV |
11597 | |
11598 | if (ret == RETRY) { | |
11599 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11600 | ret = -EINVAL; | |
11601 | goto fail; | |
11602 | } | |
11603 | ||
11604 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11605 | retry = false; | |
11606 | goto encoder_retry; | |
11607 | } | |
11608 | ||
e8fa4270 | 11609 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
11610 | * only enable it on 6bpc panels and when its not a compliance |
11611 | * test requesting 6bpc video pattern. | |
11612 | */ | |
11613 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
11614 | !pipe_config->dither_force_disable; | |
62f0ace5 | 11615 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11616 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11617 | |
7758a113 | 11618 | fail: |
548ee15b | 11619 | return ret; |
ee7b9f93 | 11620 | } |
47f1c6c9 | 11621 | |
ea9d758d | 11622 | static void |
4740b0f2 | 11623 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 11624 | { |
0a9ab303 | 11625 | struct drm_crtc *crtc; |
aa5e9b47 | 11626 | struct drm_crtc_state *new_crtc_state; |
8a75d157 | 11627 | int i; |
ea9d758d | 11628 | |
7668851f | 11629 | /* Double check state. */ |
aa5e9b47 ML |
11630 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
11631 | to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state); | |
fc467a22 | 11632 | |
61067a5e ML |
11633 | /* |
11634 | * Update legacy state to satisfy fbc code. This can | |
11635 | * be removed when fbc uses the atomic state. | |
11636 | */ | |
11637 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
11638 | struct drm_plane_state *plane_state = crtc->primary->state; | |
11639 | ||
11640 | crtc->primary->fb = plane_state->fb; | |
11641 | crtc->x = plane_state->src_x >> 16; | |
11642 | crtc->y = plane_state->src_y >> 16; | |
11643 | } | |
ea9d758d | 11644 | } |
ea9d758d DV |
11645 | } |
11646 | ||
3bd26263 | 11647 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11648 | { |
3bd26263 | 11649 | int diff; |
f1f644dc JB |
11650 | |
11651 | if (clock1 == clock2) | |
11652 | return true; | |
11653 | ||
11654 | if (!clock1 || !clock2) | |
11655 | return false; | |
11656 | ||
11657 | diff = abs(clock1 - clock2); | |
11658 | ||
11659 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11660 | return true; | |
11661 | ||
11662 | return false; | |
11663 | } | |
11664 | ||
cfb23ed6 ML |
11665 | static bool |
11666 | intel_compare_m_n(unsigned int m, unsigned int n, | |
11667 | unsigned int m2, unsigned int n2, | |
11668 | bool exact) | |
11669 | { | |
11670 | if (m == m2 && n == n2) | |
11671 | return true; | |
11672 | ||
11673 | if (exact || !m || !n || !m2 || !n2) | |
11674 | return false; | |
11675 | ||
11676 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
11677 | ||
31d10b57 ML |
11678 | if (n > n2) { |
11679 | while (n > n2) { | |
cfb23ed6 ML |
11680 | m2 <<= 1; |
11681 | n2 <<= 1; | |
11682 | } | |
31d10b57 ML |
11683 | } else if (n < n2) { |
11684 | while (n < n2) { | |
cfb23ed6 ML |
11685 | m <<= 1; |
11686 | n <<= 1; | |
11687 | } | |
11688 | } | |
11689 | ||
31d10b57 ML |
11690 | if (n != n2) |
11691 | return false; | |
11692 | ||
11693 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
11694 | } |
11695 | ||
11696 | static bool | |
11697 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
11698 | struct intel_link_m_n *m2_n2, | |
11699 | bool adjust) | |
11700 | { | |
11701 | if (m_n->tu == m2_n2->tu && | |
11702 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
11703 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
11704 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
11705 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
11706 | if (adjust) | |
11707 | *m2_n2 = *m_n; | |
11708 | ||
11709 | return true; | |
11710 | } | |
11711 | ||
11712 | return false; | |
11713 | } | |
11714 | ||
4e8048f8 TU |
11715 | static void __printf(3, 4) |
11716 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
11717 | { | |
11718 | char *level; | |
11719 | unsigned int category; | |
11720 | struct va_format vaf; | |
11721 | va_list args; | |
11722 | ||
11723 | if (adjust) { | |
11724 | level = KERN_DEBUG; | |
11725 | category = DRM_UT_KMS; | |
11726 | } else { | |
11727 | level = KERN_ERR; | |
11728 | category = DRM_UT_NONE; | |
11729 | } | |
11730 | ||
11731 | va_start(args, format); | |
11732 | vaf.fmt = format; | |
11733 | vaf.va = &args; | |
11734 | ||
11735 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
11736 | ||
11737 | va_end(args); | |
11738 | } | |
11739 | ||
0e8ffe1b | 11740 | static bool |
6315b5d3 | 11741 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 11742 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
11743 | struct intel_crtc_state *pipe_config, |
11744 | bool adjust) | |
0e8ffe1b | 11745 | { |
cfb23ed6 ML |
11746 | bool ret = true; |
11747 | ||
66e985c0 DV |
11748 | #define PIPE_CONF_CHECK_X(name) \ |
11749 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11750 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
11751 | "(expected 0x%08x, found 0x%08x)\n", \ |
11752 | current_config->name, \ | |
11753 | pipe_config->name); \ | |
cfb23ed6 | 11754 | ret = false; \ |
66e985c0 DV |
11755 | } |
11756 | ||
08a24034 DV |
11757 | #define PIPE_CONF_CHECK_I(name) \ |
11758 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11759 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
11760 | "(expected %i, found %i)\n", \ |
11761 | current_config->name, \ | |
11762 | pipe_config->name); \ | |
cfb23ed6 ML |
11763 | ret = false; \ |
11764 | } | |
11765 | ||
8106ddbd ACO |
11766 | #define PIPE_CONF_CHECK_P(name) \ |
11767 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11768 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
11769 | "(expected %p, found %p)\n", \ |
11770 | current_config->name, \ | |
11771 | pipe_config->name); \ | |
11772 | ret = false; \ | |
11773 | } | |
11774 | ||
cfb23ed6 ML |
11775 | #define PIPE_CONF_CHECK_M_N(name) \ |
11776 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11777 | &pipe_config->name,\ | |
11778 | adjust)) { \ | |
4e8048f8 | 11779 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11780 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11781 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11782 | current_config->name.tu, \ | |
11783 | current_config->name.gmch_m, \ | |
11784 | current_config->name.gmch_n, \ | |
11785 | current_config->name.link_m, \ | |
11786 | current_config->name.link_n, \ | |
11787 | pipe_config->name.tu, \ | |
11788 | pipe_config->name.gmch_m, \ | |
11789 | pipe_config->name.gmch_n, \ | |
11790 | pipe_config->name.link_m, \ | |
11791 | pipe_config->name.link_n); \ | |
11792 | ret = false; \ | |
11793 | } | |
11794 | ||
55c561a7 DV |
11795 | /* This is required for BDW+ where there is only one set of registers for |
11796 | * switching between high and low RR. | |
11797 | * This macro can be used whenever a comparison has to be made between one | |
11798 | * hw state and multiple sw state variables. | |
11799 | */ | |
cfb23ed6 ML |
11800 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
11801 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11802 | &pipe_config->name, adjust) && \ | |
11803 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
11804 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 11805 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11806 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11807 | "or tu %i gmch %i/%i link %i/%i, " \ | |
11808 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11809 | current_config->name.tu, \ | |
11810 | current_config->name.gmch_m, \ | |
11811 | current_config->name.gmch_n, \ | |
11812 | current_config->name.link_m, \ | |
11813 | current_config->name.link_n, \ | |
11814 | current_config->alt_name.tu, \ | |
11815 | current_config->alt_name.gmch_m, \ | |
11816 | current_config->alt_name.gmch_n, \ | |
11817 | current_config->alt_name.link_m, \ | |
11818 | current_config->alt_name.link_n, \ | |
11819 | pipe_config->name.tu, \ | |
11820 | pipe_config->name.gmch_m, \ | |
11821 | pipe_config->name.gmch_n, \ | |
11822 | pipe_config->name.link_m, \ | |
11823 | pipe_config->name.link_n); \ | |
11824 | ret = false; \ | |
88adfff1 DV |
11825 | } |
11826 | ||
1bd1bd80 DV |
11827 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11828 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
11829 | pipe_config_err(adjust, __stringify(name), \ |
11830 | "(%x) (expected %i, found %i)\n", \ | |
11831 | (mask), \ | |
1bd1bd80 DV |
11832 | current_config->name & (mask), \ |
11833 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 11834 | ret = false; \ |
1bd1bd80 DV |
11835 | } |
11836 | ||
5e550656 VS |
11837 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11838 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 11839 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
11840 | "(expected %i, found %i)\n", \ |
11841 | current_config->name, \ | |
11842 | pipe_config->name); \ | |
cfb23ed6 | 11843 | ret = false; \ |
5e550656 VS |
11844 | } |
11845 | ||
bb760063 DV |
11846 | #define PIPE_CONF_QUIRK(quirk) \ |
11847 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11848 | ||
eccb140b DV |
11849 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11850 | ||
08a24034 DV |
11851 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11852 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 11853 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 11854 | |
90a6b7b0 | 11855 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 11856 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 11857 | |
6315b5d3 | 11858 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
11859 | PIPE_CONF_CHECK_M_N(dp_m_n); |
11860 | ||
cfb23ed6 ML |
11861 | if (current_config->has_drrs) |
11862 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
11863 | } else | |
11864 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 11865 | |
253c84c8 | 11866 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 11867 | |
2d112de7 ACO |
11868 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11869 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11870 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11871 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11872 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11873 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11874 | |
2d112de7 ACO |
11875 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11876 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11877 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11878 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11879 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11880 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11881 | |
c93f54cf | 11882 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11883 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 11884 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 11885 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 11886 | PIPE_CONF_CHECK_I(limited_color_range); |
15953637 SS |
11887 | |
11888 | PIPE_CONF_CHECK_I(hdmi_scrambling); | |
11889 | PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio); | |
e43823ec | 11890 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11891 | |
9ed109a7 DV |
11892 | PIPE_CONF_CHECK_I(has_audio); |
11893 | ||
2d112de7 | 11894 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11895 | DRM_MODE_FLAG_INTERLACE); |
11896 | ||
bb760063 | 11897 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11898 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11899 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11900 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11901 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11902 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11903 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11904 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11905 | DRM_MODE_FLAG_NVSYNC); |
11906 | } | |
045ac3b5 | 11907 | |
333b8ca8 | 11908 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 11909 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 11910 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 11911 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 11912 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 11913 | |
bfd16b2a ML |
11914 | if (!adjust) { |
11915 | PIPE_CONF_CHECK_I(pipe_src_w); | |
11916 | PIPE_CONF_CHECK_I(pipe_src_h); | |
11917 | ||
11918 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
11919 | if (current_config->pch_pfit.enabled) { | |
11920 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
11921 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
11922 | } | |
2fa2fe9a | 11923 | |
7aefe2b5 | 11924 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 11925 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
7aefe2b5 | 11926 | } |
a1b2278e | 11927 | |
e59150dc | 11928 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 11929 | if (IS_HASWELL(dev_priv)) |
e59150dc | 11930 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 11931 | |
282740f7 VS |
11932 | PIPE_CONF_CHECK_I(double_wide); |
11933 | ||
8106ddbd | 11934 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 11935 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11936 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11937 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11938 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11939 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 11940 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
11941 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11942 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11943 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11944 | |
47eacbab VS |
11945 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
11946 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
11947 | ||
9beb5fea | 11948 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
11949 | PIPE_CONF_CHECK_I(pipe_bpp); |
11950 | ||
2d112de7 | 11951 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11952 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11953 | |
66e985c0 | 11954 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11955 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 11956 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 11957 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11958 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11959 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11960 | |
cfb23ed6 | 11961 | return ret; |
0e8ffe1b DV |
11962 | } |
11963 | ||
e3b247da VS |
11964 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
11965 | const struct intel_crtc_state *pipe_config) | |
11966 | { | |
11967 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 11968 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
11969 | &pipe_config->fdi_m_n); |
11970 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
11971 | ||
11972 | /* | |
11973 | * FDI already provided one idea for the dotclock. | |
11974 | * Yell if the encoder disagrees. | |
11975 | */ | |
11976 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
11977 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
11978 | fdi_dotclock, dotclock); | |
11979 | } | |
11980 | } | |
11981 | ||
c0ead703 ML |
11982 | static void verify_wm_state(struct drm_crtc *crtc, |
11983 | struct drm_crtc_state *new_state) | |
08db6652 | 11984 | { |
6315b5d3 | 11985 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 11986 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 11987 | struct skl_pipe_wm hw_wm, *sw_wm; |
11988 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
11989 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
11990 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11991 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 11992 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 11993 | |
6315b5d3 | 11994 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
11995 | return; |
11996 | ||
3de8a14c | 11997 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 11998 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 11999 | |
08db6652 DL |
12000 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
12001 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12002 | ||
e7c84544 | 12003 | /* planes */ |
8b364b41 | 12004 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 12005 | hw_plane_wm = &hw_wm.planes[plane]; |
12006 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 12007 | |
3de8a14c | 12008 | /* Watermarks */ |
12009 | for (level = 0; level <= max_level; level++) { | |
12010 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
12011 | &sw_plane_wm->wm[level])) | |
12012 | continue; | |
12013 | ||
12014 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
12015 | pipe_name(pipe), plane + 1, level, | |
12016 | sw_plane_wm->wm[level].plane_en, | |
12017 | sw_plane_wm->wm[level].plane_res_b, | |
12018 | sw_plane_wm->wm[level].plane_res_l, | |
12019 | hw_plane_wm->wm[level].plane_en, | |
12020 | hw_plane_wm->wm[level].plane_res_b, | |
12021 | hw_plane_wm->wm[level].plane_res_l); | |
12022 | } | |
08db6652 | 12023 | |
3de8a14c | 12024 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
12025 | &sw_plane_wm->trans_wm)) { | |
12026 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
12027 | pipe_name(pipe), plane + 1, | |
12028 | sw_plane_wm->trans_wm.plane_en, | |
12029 | sw_plane_wm->trans_wm.plane_res_b, | |
12030 | sw_plane_wm->trans_wm.plane_res_l, | |
12031 | hw_plane_wm->trans_wm.plane_en, | |
12032 | hw_plane_wm->trans_wm.plane_res_b, | |
12033 | hw_plane_wm->trans_wm.plane_res_l); | |
12034 | } | |
12035 | ||
12036 | /* DDB */ | |
12037 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
12038 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
12039 | ||
12040 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 12041 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 12042 | pipe_name(pipe), plane + 1, |
12043 | sw_ddb_entry->start, sw_ddb_entry->end, | |
12044 | hw_ddb_entry->start, hw_ddb_entry->end); | |
12045 | } | |
e7c84544 | 12046 | } |
08db6652 | 12047 | |
27082493 L |
12048 | /* |
12049 | * cursor | |
12050 | * If the cursor plane isn't active, we may not have updated it's ddb | |
12051 | * allocation. In that case since the ddb allocation will be updated | |
12052 | * once the plane becomes visible, we can skip this check | |
12053 | */ | |
cd5dcbf1 | 12054 | if (1) { |
3de8a14c | 12055 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
12056 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
12057 | ||
12058 | /* Watermarks */ | |
12059 | for (level = 0; level <= max_level; level++) { | |
12060 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
12061 | &sw_plane_wm->wm[level])) | |
12062 | continue; | |
12063 | ||
12064 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
12065 | pipe_name(pipe), level, | |
12066 | sw_plane_wm->wm[level].plane_en, | |
12067 | sw_plane_wm->wm[level].plane_res_b, | |
12068 | sw_plane_wm->wm[level].plane_res_l, | |
12069 | hw_plane_wm->wm[level].plane_en, | |
12070 | hw_plane_wm->wm[level].plane_res_b, | |
12071 | hw_plane_wm->wm[level].plane_res_l); | |
12072 | } | |
12073 | ||
12074 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
12075 | &sw_plane_wm->trans_wm)) { | |
12076 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
12077 | pipe_name(pipe), | |
12078 | sw_plane_wm->trans_wm.plane_en, | |
12079 | sw_plane_wm->trans_wm.plane_res_b, | |
12080 | sw_plane_wm->trans_wm.plane_res_l, | |
12081 | hw_plane_wm->trans_wm.plane_en, | |
12082 | hw_plane_wm->trans_wm.plane_res_b, | |
12083 | hw_plane_wm->trans_wm.plane_res_l); | |
12084 | } | |
12085 | ||
12086 | /* DDB */ | |
12087 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
12088 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 12089 | |
3de8a14c | 12090 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 12091 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 12092 | pipe_name(pipe), |
3de8a14c | 12093 | sw_ddb_entry->start, sw_ddb_entry->end, |
12094 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 12095 | } |
08db6652 DL |
12096 | } |
12097 | } | |
12098 | ||
91d1b4bd | 12099 | static void |
677100ce ML |
12100 | verify_connector_state(struct drm_device *dev, |
12101 | struct drm_atomic_state *state, | |
12102 | struct drm_crtc *crtc) | |
8af6cf88 | 12103 | { |
35dd3c64 | 12104 | struct drm_connector *connector; |
aa5e9b47 | 12105 | struct drm_connector_state *new_conn_state; |
677100ce | 12106 | int i; |
8af6cf88 | 12107 | |
aa5e9b47 | 12108 | for_each_new_connector_in_state(state, connector, new_conn_state, i) { |
35dd3c64 | 12109 | struct drm_encoder *encoder = connector->encoder; |
749d98b8 | 12110 | struct drm_crtc_state *crtc_state = NULL; |
ad3c558f | 12111 | |
aa5e9b47 | 12112 | if (new_conn_state->crtc != crtc) |
e7c84544 ML |
12113 | continue; |
12114 | ||
749d98b8 ML |
12115 | if (crtc) |
12116 | crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); | |
12117 | ||
12118 | intel_connector_verify_state(crtc_state, new_conn_state); | |
8af6cf88 | 12119 | |
aa5e9b47 | 12120 | I915_STATE_WARN(new_conn_state->best_encoder != encoder, |
35dd3c64 | 12121 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12122 | } |
91d1b4bd DV |
12123 | } |
12124 | ||
12125 | static void | |
86b04268 | 12126 | verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state) |
91d1b4bd DV |
12127 | { |
12128 | struct intel_encoder *encoder; | |
86b04268 DV |
12129 | struct drm_connector *connector; |
12130 | struct drm_connector_state *old_conn_state, *new_conn_state; | |
12131 | int i; | |
8af6cf88 | 12132 | |
b2784e15 | 12133 | for_each_intel_encoder(dev, encoder) { |
86b04268 | 12134 | bool enabled = false, found = false; |
4d20cd86 | 12135 | enum pipe pipe; |
8af6cf88 DV |
12136 | |
12137 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12138 | encoder->base.base.id, | |
8e329a03 | 12139 | encoder->base.name); |
8af6cf88 | 12140 | |
86b04268 DV |
12141 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, |
12142 | new_conn_state, i) { | |
12143 | if (old_conn_state->best_encoder == &encoder->base) | |
12144 | found = true; | |
12145 | ||
12146 | if (new_conn_state->best_encoder != &encoder->base) | |
8af6cf88 | 12147 | continue; |
86b04268 | 12148 | found = enabled = true; |
ad3c558f | 12149 | |
86b04268 | 12150 | I915_STATE_WARN(new_conn_state->crtc != |
ad3c558f ML |
12151 | encoder->base.crtc, |
12152 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12153 | } |
86b04268 DV |
12154 | |
12155 | if (!found) | |
12156 | continue; | |
0e32b39c | 12157 | |
e2c719b7 | 12158 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12159 | "encoder's enabled state mismatch " |
12160 | "(expected %i, found %i)\n", | |
12161 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12162 | |
12163 | if (!encoder->base.crtc) { | |
4d20cd86 | 12164 | bool active; |
7c60d198 | 12165 | |
4d20cd86 ML |
12166 | active = encoder->get_hw_state(encoder, &pipe); |
12167 | I915_STATE_WARN(active, | |
12168 | "encoder detached but still enabled on pipe %c.\n", | |
12169 | pipe_name(pipe)); | |
7c60d198 | 12170 | } |
8af6cf88 | 12171 | } |
91d1b4bd DV |
12172 | } |
12173 | ||
12174 | static void | |
c0ead703 ML |
12175 | verify_crtc_state(struct drm_crtc *crtc, |
12176 | struct drm_crtc_state *old_crtc_state, | |
12177 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 12178 | { |
e7c84544 | 12179 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12180 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 12181 | struct intel_encoder *encoder; |
e7c84544 ML |
12182 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12183 | struct intel_crtc_state *pipe_config, *sw_config; | |
12184 | struct drm_atomic_state *old_state; | |
12185 | bool active; | |
045ac3b5 | 12186 | |
e7c84544 | 12187 | old_state = old_crtc_state->state; |
ec2dc6a0 | 12188 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
12189 | pipe_config = to_intel_crtc_state(old_crtc_state); |
12190 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12191 | pipe_config->base.crtc = crtc; | |
12192 | pipe_config->base.state = old_state; | |
8af6cf88 | 12193 | |
78108b7c | 12194 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 12195 | |
e7c84544 | 12196 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 12197 | |
e7c84544 ML |
12198 | /* hw state is inconsistent with the pipe quirk */ |
12199 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12200 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12201 | active = new_crtc_state->active; | |
6c49f241 | 12202 | |
e7c84544 ML |
12203 | I915_STATE_WARN(new_crtc_state->active != active, |
12204 | "crtc active state doesn't match with hw state " | |
12205 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 12206 | |
e7c84544 ML |
12207 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
12208 | "transitional active state does not match atomic hw state " | |
12209 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 12210 | |
e7c84544 ML |
12211 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
12212 | enum pipe pipe; | |
4d20cd86 | 12213 | |
e7c84544 ML |
12214 | active = encoder->get_hw_state(encoder, &pipe); |
12215 | I915_STATE_WARN(active != new_crtc_state->active, | |
12216 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12217 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 12218 | |
e7c84544 ML |
12219 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
12220 | "Encoder connected to wrong pipe %c\n", | |
12221 | pipe_name(pipe)); | |
4d20cd86 | 12222 | |
253c84c8 VS |
12223 | if (active) { |
12224 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 12225 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 12226 | } |
e7c84544 | 12227 | } |
53d9f4e9 | 12228 | |
a7d1b3f4 VS |
12229 | intel_crtc_compute_pixel_rate(pipe_config); |
12230 | ||
e7c84544 ML |
12231 | if (!new_crtc_state->active) |
12232 | return; | |
cfb23ed6 | 12233 | |
e7c84544 | 12234 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 12235 | |
749d98b8 | 12236 | sw_config = to_intel_crtc_state(new_crtc_state); |
6315b5d3 | 12237 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
12238 | pipe_config, false)) { |
12239 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
12240 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
12241 | "[hw state]"); | |
12242 | intel_dump_pipe_config(intel_crtc, sw_config, | |
12243 | "[sw state]"); | |
8af6cf88 DV |
12244 | } |
12245 | } | |
12246 | ||
91d1b4bd | 12247 | static void |
c0ead703 ML |
12248 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
12249 | struct intel_shared_dpll *pll, | |
12250 | struct drm_crtc *crtc, | |
12251 | struct drm_crtc_state *new_state) | |
91d1b4bd | 12252 | { |
91d1b4bd | 12253 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
12254 | unsigned crtc_mask; |
12255 | bool active; | |
5358901f | 12256 | |
e7c84544 | 12257 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 12258 | |
e7c84544 | 12259 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 12260 | |
e7c84544 | 12261 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12262 | |
e7c84544 ML |
12263 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
12264 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
12265 | "pll in active use but not on in sw tracking\n"); | |
12266 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12267 | "pll is on but not used by any active crtc\n"); | |
12268 | I915_STATE_WARN(pll->on != active, | |
12269 | "pll on state mismatch (expected %i, found %i)\n", | |
12270 | pll->on, active); | |
12271 | } | |
5358901f | 12272 | |
e7c84544 | 12273 | if (!crtc) { |
2c42e535 | 12274 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 12275 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 12276 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 12277 | |
e7c84544 ML |
12278 | return; |
12279 | } | |
12280 | ||
12281 | crtc_mask = 1 << drm_crtc_index(crtc); | |
12282 | ||
12283 | if (new_state->active) | |
12284 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
12285 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
12286 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
12287 | else | |
12288 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12289 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
12290 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 12291 | |
2c42e535 | 12292 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 12293 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 12294 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 12295 | |
2c42e535 | 12296 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
12297 | &dpll_hw_state, |
12298 | sizeof(dpll_hw_state)), | |
12299 | "pll hw state mismatch\n"); | |
12300 | } | |
12301 | ||
12302 | static void | |
c0ead703 ML |
12303 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
12304 | struct drm_crtc_state *old_crtc_state, | |
12305 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 12306 | { |
fac5e23e | 12307 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
12308 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
12309 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
12310 | ||
12311 | if (new_state->shared_dpll) | |
c0ead703 | 12312 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
12313 | |
12314 | if (old_state->shared_dpll && | |
12315 | old_state->shared_dpll != new_state->shared_dpll) { | |
12316 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
12317 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
12318 | ||
12319 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12320 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
12321 | pipe_name(drm_crtc_index(crtc))); | |
2c42e535 | 12322 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 ML |
12323 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
12324 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 12325 | } |
8af6cf88 DV |
12326 | } |
12327 | ||
e7c84544 | 12328 | static void |
c0ead703 | 12329 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
12330 | struct drm_atomic_state *state, |
12331 | struct drm_crtc_state *old_state, | |
12332 | struct drm_crtc_state *new_state) | |
e7c84544 | 12333 | { |
5a21b665 DV |
12334 | if (!needs_modeset(new_state) && |
12335 | !to_intel_crtc_state(new_state)->update_pipe) | |
12336 | return; | |
12337 | ||
c0ead703 | 12338 | verify_wm_state(crtc, new_state); |
677100ce | 12339 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
12340 | verify_crtc_state(crtc, old_state, new_state); |
12341 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
12342 | } |
12343 | ||
12344 | static void | |
c0ead703 | 12345 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 12346 | { |
fac5e23e | 12347 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
12348 | int i; |
12349 | ||
12350 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 12351 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
12352 | } |
12353 | ||
12354 | static void | |
677100ce ML |
12355 | intel_modeset_verify_disabled(struct drm_device *dev, |
12356 | struct drm_atomic_state *state) | |
e7c84544 | 12357 | { |
86b04268 | 12358 | verify_encoder_state(dev, state); |
677100ce | 12359 | verify_connector_state(dev, state, NULL); |
c0ead703 | 12360 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
12361 | } |
12362 | ||
80715b2f VS |
12363 | static void update_scanline_offset(struct intel_crtc *crtc) |
12364 | { | |
4f8036a2 | 12365 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
12366 | |
12367 | /* | |
12368 | * The scanline counter increments at the leading edge of hsync. | |
12369 | * | |
12370 | * On most platforms it starts counting from vtotal-1 on the | |
12371 | * first active line. That means the scanline counter value is | |
12372 | * always one less than what we would expect. Ie. just after | |
12373 | * start of vblank, which also occurs at start of hsync (on the | |
12374 | * last active line), the scanline counter will read vblank_start-1. | |
12375 | * | |
12376 | * On gen2 the scanline counter starts counting from 1 instead | |
12377 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12378 | * to keep the value positive), instead of adding one. | |
12379 | * | |
12380 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12381 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12382 | * there's an extra 1 line difference. So we need to add two instead of | |
12383 | * one to the value. | |
12384 | */ | |
4f8036a2 | 12385 | if (IS_GEN2(dev_priv)) { |
124abe07 | 12386 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12387 | int vtotal; |
12388 | ||
124abe07 VS |
12389 | vtotal = adjusted_mode->crtc_vtotal; |
12390 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
12391 | vtotal /= 2; |
12392 | ||
12393 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 12394 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 12395 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12396 | crtc->scanline_offset = 2; |
12397 | } else | |
12398 | crtc->scanline_offset = 1; | |
12399 | } | |
12400 | ||
ad421372 | 12401 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12402 | { |
225da59b | 12403 | struct drm_device *dev = state->dev; |
ed6739ef | 12404 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 12405 | struct drm_crtc *crtc; |
aa5e9b47 | 12406 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
0a9ab303 | 12407 | int i; |
ed6739ef ACO |
12408 | |
12409 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12410 | return; |
ed6739ef | 12411 | |
aa5e9b47 | 12412 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
fb1a38a9 | 12413 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd | 12414 | struct intel_shared_dpll *old_dpll = |
aa5e9b47 | 12415 | to_intel_crtc_state(old_crtc_state)->shared_dpll; |
0a9ab303 | 12416 | |
aa5e9b47 | 12417 | if (!needs_modeset(new_crtc_state)) |
225da59b ACO |
12418 | continue; |
12419 | ||
aa5e9b47 | 12420 | to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 12421 | |
8106ddbd | 12422 | if (!old_dpll) |
fb1a38a9 | 12423 | continue; |
0a9ab303 | 12424 | |
a1c414ee | 12425 | intel_release_shared_dpll(old_dpll, intel_crtc, state); |
ad421372 | 12426 | } |
ed6739ef ACO |
12427 | } |
12428 | ||
99d736a2 ML |
12429 | /* |
12430 | * This implements the workaround described in the "notes" section of the mode | |
12431 | * set sequence documentation. When going from no pipes or single pipe to | |
12432 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12433 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12434 | */ | |
12435 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12436 | { | |
12437 | struct drm_crtc_state *crtc_state; | |
12438 | struct intel_crtc *intel_crtc; | |
12439 | struct drm_crtc *crtc; | |
12440 | struct intel_crtc_state *first_crtc_state = NULL; | |
12441 | struct intel_crtc_state *other_crtc_state = NULL; | |
12442 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12443 | int i; | |
12444 | ||
12445 | /* look at all crtc's that are going to be enabled in during modeset */ | |
aa5e9b47 | 12446 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
99d736a2 ML |
12447 | intel_crtc = to_intel_crtc(crtc); |
12448 | ||
12449 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12450 | continue; | |
12451 | ||
12452 | if (first_crtc_state) { | |
12453 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
12454 | break; | |
12455 | } else { | |
12456 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
12457 | first_pipe = intel_crtc->pipe; | |
12458 | } | |
12459 | } | |
12460 | ||
12461 | /* No workaround needed? */ | |
12462 | if (!first_crtc_state) | |
12463 | return 0; | |
12464 | ||
12465 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
12466 | for_each_intel_crtc(state->dev, intel_crtc) { | |
12467 | struct intel_crtc_state *pipe_config; | |
12468 | ||
12469 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12470 | if (IS_ERR(pipe_config)) | |
12471 | return PTR_ERR(pipe_config); | |
12472 | ||
12473 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
12474 | ||
12475 | if (!pipe_config->base.active || | |
12476 | needs_modeset(&pipe_config->base)) | |
12477 | continue; | |
12478 | ||
12479 | /* 2 or more enabled crtcs means no need for w/a */ | |
12480 | if (enabled_pipe != INVALID_PIPE) | |
12481 | return 0; | |
12482 | ||
12483 | enabled_pipe = intel_crtc->pipe; | |
12484 | } | |
12485 | ||
12486 | if (enabled_pipe != INVALID_PIPE) | |
12487 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
12488 | else if (other_crtc_state) | |
12489 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
12490 | ||
12491 | return 0; | |
12492 | } | |
12493 | ||
8d96561a VS |
12494 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
12495 | { | |
12496 | struct drm_crtc *crtc; | |
12497 | ||
12498 | /* Add all pipes to the state */ | |
12499 | for_each_crtc(state->dev, crtc) { | |
12500 | struct drm_crtc_state *crtc_state; | |
12501 | ||
12502 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
12503 | if (IS_ERR(crtc_state)) | |
12504 | return PTR_ERR(crtc_state); | |
12505 | } | |
12506 | ||
12507 | return 0; | |
12508 | } | |
12509 | ||
27c329ed ML |
12510 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
12511 | { | |
12512 | struct drm_crtc *crtc; | |
27c329ed | 12513 | |
8d96561a VS |
12514 | /* |
12515 | * Add all pipes to the state, and force | |
12516 | * a modeset on all the active ones. | |
12517 | */ | |
27c329ed | 12518 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
12519 | struct drm_crtc_state *crtc_state; |
12520 | int ret; | |
12521 | ||
27c329ed ML |
12522 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
12523 | if (IS_ERR(crtc_state)) | |
12524 | return PTR_ERR(crtc_state); | |
12525 | ||
12526 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
12527 | continue; | |
12528 | ||
12529 | crtc_state->mode_changed = true; | |
12530 | ||
12531 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12532 | if (ret) | |
9780aad5 | 12533 | return ret; |
27c329ed ML |
12534 | |
12535 | ret = drm_atomic_add_affected_planes(state, crtc); | |
12536 | if (ret) | |
9780aad5 | 12537 | return ret; |
27c329ed ML |
12538 | } |
12539 | ||
9780aad5 | 12540 | return 0; |
27c329ed ML |
12541 | } |
12542 | ||
c347a676 | 12543 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 12544 | { |
565602d7 | 12545 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12546 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 | 12547 | struct drm_crtc *crtc; |
aa5e9b47 | 12548 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
565602d7 | 12549 | int ret = 0, i; |
054518dd | 12550 | |
b359283a ML |
12551 | if (!check_digital_port_conflicts(state)) { |
12552 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
12553 | return -EINVAL; | |
12554 | } | |
12555 | ||
565602d7 ML |
12556 | intel_state->modeset = true; |
12557 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
bb0f4aab VS |
12558 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
12559 | intel_state->cdclk.actual = dev_priv->cdclk.actual; | |
565602d7 | 12560 | |
aa5e9b47 ML |
12561 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
12562 | if (new_crtc_state->active) | |
565602d7 ML |
12563 | intel_state->active_crtcs |= 1 << i; |
12564 | else | |
12565 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 | 12566 | |
aa5e9b47 | 12567 | if (old_crtc_state->active != new_crtc_state->active) |
8b4a7d05 | 12568 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); |
565602d7 ML |
12569 | } |
12570 | ||
054518dd ACO |
12571 | /* |
12572 | * See if the config requires any additional preparation, e.g. | |
12573 | * to adjust global state with pipes off. We need to do this | |
12574 | * here so we can get the modeset_pipe updated config for the new | |
12575 | * mode set on this crtc. For other crtcs we need to use the | |
12576 | * adjusted_mode bits in the crtc directly. | |
12577 | */ | |
27c329ed | 12578 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed | 12579 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
12580 | if (ret < 0) |
12581 | return ret; | |
27c329ed | 12582 | |
8d96561a | 12583 | /* |
bb0f4aab | 12584 | * Writes to dev_priv->cdclk.logical must protected by |
8d96561a VS |
12585 | * holding all the crtc locks, even if we don't end up |
12586 | * touching the hardware | |
12587 | */ | |
bb0f4aab VS |
12588 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical, |
12589 | &intel_state->cdclk.logical)) { | |
8d96561a VS |
12590 | ret = intel_lock_all_pipes(state); |
12591 | if (ret < 0) | |
12592 | return ret; | |
12593 | } | |
12594 | ||
12595 | /* All pipes must be switched off while we change the cdclk. */ | |
bb0f4aab VS |
12596 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual, |
12597 | &intel_state->cdclk.actual)) { | |
27c329ed | 12598 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
12599 | if (ret < 0) |
12600 | return ret; | |
12601 | } | |
e8788cbc | 12602 | |
bb0f4aab VS |
12603 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", |
12604 | intel_state->cdclk.logical.cdclk, | |
12605 | intel_state->cdclk.actual.cdclk); | |
e0ca7a6b | 12606 | } else { |
bb0f4aab | 12607 | to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12608 | } |
054518dd | 12609 | |
ad421372 | 12610 | intel_modeset_clear_plls(state); |
054518dd | 12611 | |
565602d7 | 12612 | if (IS_HASWELL(dev_priv)) |
ad421372 | 12613 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 12614 | |
ad421372 | 12615 | return 0; |
c347a676 ACO |
12616 | } |
12617 | ||
aa363136 MR |
12618 | /* |
12619 | * Handle calculation of various watermark data at the end of the atomic check | |
12620 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
12621 | * handlers to ensure that all derived state has been updated. | |
12622 | */ | |
55994c2c | 12623 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
12624 | { |
12625 | struct drm_device *dev = state->dev; | |
98d39494 | 12626 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
12627 | |
12628 | /* Is there platform-specific watermark information to calculate? */ | |
12629 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
12630 | return dev_priv->display.compute_global_watermarks(state); |
12631 | ||
12632 | return 0; | |
aa363136 MR |
12633 | } |
12634 | ||
74c090b1 ML |
12635 | /** |
12636 | * intel_atomic_check - validate state object | |
12637 | * @dev: drm device | |
12638 | * @state: state to validate | |
12639 | */ | |
12640 | static int intel_atomic_check(struct drm_device *dev, | |
12641 | struct drm_atomic_state *state) | |
c347a676 | 12642 | { |
dd8b3bdb | 12643 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 12644 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 | 12645 | struct drm_crtc *crtc; |
aa5e9b47 | 12646 | struct drm_crtc_state *old_crtc_state, *crtc_state; |
c347a676 | 12647 | int ret, i; |
61333b60 | 12648 | bool any_ms = false; |
c347a676 | 12649 | |
74c090b1 | 12650 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
12651 | if (ret) |
12652 | return ret; | |
12653 | ||
aa5e9b47 | 12654 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) { |
cfb23ed6 ML |
12655 | struct intel_crtc_state *pipe_config = |
12656 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
12657 | |
12658 | /* Catch I915_MODE_FLAG_INHERITED */ | |
aa5e9b47 | 12659 | if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags) |
1ed51de9 | 12660 | crtc_state->mode_changed = true; |
cfb23ed6 | 12661 | |
af4a879e | 12662 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
12663 | continue; |
12664 | ||
af4a879e DV |
12665 | if (!crtc_state->enable) { |
12666 | any_ms = true; | |
cfb23ed6 | 12667 | continue; |
af4a879e | 12668 | } |
cfb23ed6 | 12669 | |
26495481 DV |
12670 | /* FIXME: For only active_changed we shouldn't need to do any |
12671 | * state recomputation at all. */ | |
12672 | ||
1ed51de9 DV |
12673 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12674 | if (ret) | |
12675 | return ret; | |
b359283a | 12676 | |
cfb23ed6 | 12677 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
12678 | if (ret) { |
12679 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12680 | pipe_config, "[failed]"); | |
c347a676 | 12681 | return ret; |
25aa1c39 | 12682 | } |
c347a676 | 12683 | |
73831236 | 12684 | if (i915.fastboot && |
6315b5d3 | 12685 | intel_pipe_config_compare(dev_priv, |
aa5e9b47 | 12686 | to_intel_crtc_state(old_crtc_state), |
1ed51de9 | 12687 | pipe_config, true)) { |
26495481 | 12688 | crtc_state->mode_changed = false; |
aa5e9b47 | 12689 | pipe_config->update_pipe = true; |
26495481 DV |
12690 | } |
12691 | ||
af4a879e | 12692 | if (needs_modeset(crtc_state)) |
26495481 | 12693 | any_ms = true; |
cfb23ed6 | 12694 | |
af4a879e DV |
12695 | ret = drm_atomic_add_affected_planes(state, crtc); |
12696 | if (ret) | |
12697 | return ret; | |
61333b60 | 12698 | |
26495481 DV |
12699 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12700 | needs_modeset(crtc_state) ? | |
12701 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
12702 | } |
12703 | ||
61333b60 ML |
12704 | if (any_ms) { |
12705 | ret = intel_modeset_checks(state); | |
12706 | ||
12707 | if (ret) | |
12708 | return ret; | |
e0ca7a6b | 12709 | } else { |
bb0f4aab | 12710 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12711 | } |
76305b1a | 12712 | |
dd8b3bdb | 12713 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
12714 | if (ret) |
12715 | return ret; | |
12716 | ||
f51be2e0 | 12717 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 12718 | return calc_watermark_data(state); |
054518dd ACO |
12719 | } |
12720 | ||
5008e874 | 12721 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 12722 | struct drm_atomic_state *state) |
5008e874 | 12723 | { |
fac5e23e | 12724 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 ML |
12725 | struct drm_crtc_state *crtc_state; |
12726 | struct drm_crtc *crtc; | |
12727 | int i, ret; | |
12728 | ||
aa5e9b47 | 12729 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
5a21b665 | 12730 | if (state->legacy_cursor_update) |
a6747b73 ML |
12731 | continue; |
12732 | ||
5a21b665 DV |
12733 | ret = intel_crtc_wait_for_pending_flips(crtc); |
12734 | if (ret) | |
12735 | return ret; | |
5008e874 | 12736 | |
5a21b665 DV |
12737 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
12738 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
12739 | } |
12740 | ||
f935675f ML |
12741 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
12742 | if (ret) | |
12743 | return ret; | |
12744 | ||
5008e874 | 12745 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 12746 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 12747 | |
5008e874 ML |
12748 | return ret; |
12749 | } | |
12750 | ||
a2991414 ML |
12751 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
12752 | { | |
12753 | struct drm_device *dev = crtc->base.dev; | |
12754 | ||
12755 | if (!dev->max_vblank_count) | |
12756 | return drm_accurate_vblank_count(&crtc->base); | |
12757 | ||
12758 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
12759 | } | |
12760 | ||
5a21b665 DV |
12761 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
12762 | struct drm_i915_private *dev_priv, | |
12763 | unsigned crtc_mask) | |
e8861675 | 12764 | { |
5a21b665 DV |
12765 | unsigned last_vblank_count[I915_MAX_PIPES]; |
12766 | enum pipe pipe; | |
12767 | int ret; | |
e8861675 | 12768 | |
5a21b665 DV |
12769 | if (!crtc_mask) |
12770 | return; | |
e8861675 | 12771 | |
5a21b665 | 12772 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12773 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12774 | pipe); | |
e8861675 | 12775 | |
5a21b665 | 12776 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
12777 | continue; |
12778 | ||
e2af48c6 | 12779 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
12780 | if (WARN_ON(ret != 0)) { |
12781 | crtc_mask &= ~(1 << pipe); | |
12782 | continue; | |
e8861675 ML |
12783 | } |
12784 | ||
e2af48c6 | 12785 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
12786 | } |
12787 | ||
5a21b665 | 12788 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12789 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12790 | pipe); | |
5a21b665 | 12791 | long lret; |
e8861675 | 12792 | |
5a21b665 DV |
12793 | if (!((1 << pipe) & crtc_mask)) |
12794 | continue; | |
d55dbd06 | 12795 | |
5a21b665 DV |
12796 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
12797 | last_vblank_count[pipe] != | |
e2af48c6 | 12798 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 12799 | msecs_to_jiffies(50)); |
d55dbd06 | 12800 | |
5a21b665 | 12801 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 12802 | |
e2af48c6 | 12803 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
12804 | } |
12805 | } | |
12806 | ||
5a21b665 | 12807 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 12808 | { |
5a21b665 DV |
12809 | /* fb updated, need to unpin old fb */ |
12810 | if (crtc_state->fb_changed) | |
12811 | return true; | |
a6747b73 | 12812 | |
5a21b665 DV |
12813 | /* wm changes, need vblank before final wm's */ |
12814 | if (crtc_state->update_wm_post) | |
12815 | return true; | |
a6747b73 | 12816 | |
5eeb798b | 12817 | if (crtc_state->wm.need_postvbl_update) |
5a21b665 | 12818 | return true; |
a6747b73 | 12819 | |
5a21b665 | 12820 | return false; |
e8861675 ML |
12821 | } |
12822 | ||
896e5bb0 L |
12823 | static void intel_update_crtc(struct drm_crtc *crtc, |
12824 | struct drm_atomic_state *state, | |
12825 | struct drm_crtc_state *old_crtc_state, | |
aa5e9b47 | 12826 | struct drm_crtc_state *new_crtc_state, |
896e5bb0 L |
12827 | unsigned int *crtc_vblank_mask) |
12828 | { | |
12829 | struct drm_device *dev = crtc->dev; | |
12830 | struct drm_i915_private *dev_priv = to_i915(dev); | |
12831 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
aa5e9b47 ML |
12832 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); |
12833 | bool modeset = needs_modeset(new_crtc_state); | |
896e5bb0 L |
12834 | |
12835 | if (modeset) { | |
12836 | update_scanline_offset(intel_crtc); | |
12837 | dev_priv->display.crtc_enable(pipe_config, state); | |
12838 | } else { | |
aa5e9b47 ML |
12839 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12840 | pipe_config); | |
896e5bb0 L |
12841 | } |
12842 | ||
12843 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12844 | intel_fbc_enable( | |
12845 | intel_crtc, pipe_config, | |
12846 | to_intel_plane_state(crtc->primary->state)); | |
12847 | } | |
12848 | ||
12849 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
12850 | ||
12851 | if (needs_vblank_wait(pipe_config)) | |
12852 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
12853 | } | |
12854 | ||
12855 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
12856 | unsigned int *crtc_vblank_mask) | |
12857 | { | |
12858 | struct drm_crtc *crtc; | |
aa5e9b47 | 12859 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
896e5bb0 L |
12860 | int i; |
12861 | ||
aa5e9b47 ML |
12862 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
12863 | if (!new_crtc_state->active) | |
896e5bb0 L |
12864 | continue; |
12865 | ||
12866 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 12867 | new_crtc_state, crtc_vblank_mask); |
896e5bb0 L |
12868 | } |
12869 | } | |
12870 | ||
27082493 L |
12871 | static void skl_update_crtcs(struct drm_atomic_state *state, |
12872 | unsigned int *crtc_vblank_mask) | |
12873 | { | |
0f0f74bc | 12874 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
12875 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
12876 | struct drm_crtc *crtc; | |
ce0ba283 | 12877 | struct intel_crtc *intel_crtc; |
aa5e9b47 | 12878 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
ce0ba283 | 12879 | struct intel_crtc_state *cstate; |
27082493 L |
12880 | unsigned int updated = 0; |
12881 | bool progress; | |
12882 | enum pipe pipe; | |
5eff503b ML |
12883 | int i; |
12884 | ||
12885 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
12886 | ||
aa5e9b47 | 12887 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) |
5eff503b | 12888 | /* ignore allocations for crtc's that have been turned off. */ |
aa5e9b47 | 12889 | if (new_crtc_state->active) |
5eff503b | 12890 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; |
27082493 L |
12891 | |
12892 | /* | |
12893 | * Whenever the number of active pipes changes, we need to make sure we | |
12894 | * update the pipes in the right order so that their ddb allocations | |
12895 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
12896 | * cause pipe underruns and other bad stuff. | |
12897 | */ | |
12898 | do { | |
27082493 L |
12899 | progress = false; |
12900 | ||
aa5e9b47 | 12901 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
27082493 L |
12902 | bool vbl_wait = false; |
12903 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
12904 | |
12905 | intel_crtc = to_intel_crtc(crtc); | |
12906 | cstate = to_intel_crtc_state(crtc->state); | |
12907 | pipe = intel_crtc->pipe; | |
27082493 | 12908 | |
5eff503b | 12909 | if (updated & cmask || !cstate->base.active) |
27082493 | 12910 | continue; |
5eff503b ML |
12911 | |
12912 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
12913 | continue; |
12914 | ||
12915 | updated |= cmask; | |
5eff503b | 12916 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
12917 | |
12918 | /* | |
12919 | * If this is an already active pipe, it's DDB changed, | |
12920 | * and this isn't the last pipe that needs updating | |
12921 | * then we need to wait for a vblank to pass for the | |
12922 | * new ddb allocation to take effect. | |
12923 | */ | |
ce0ba283 | 12924 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 12925 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
aa5e9b47 | 12926 | !new_crtc_state->active_changed && |
27082493 L |
12927 | intel_state->wm_results.dirty_pipes != updated) |
12928 | vbl_wait = true; | |
12929 | ||
12930 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 12931 | new_crtc_state, crtc_vblank_mask); |
27082493 L |
12932 | |
12933 | if (vbl_wait) | |
0f0f74bc | 12934 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
12935 | |
12936 | progress = true; | |
12937 | } | |
12938 | } while (progress); | |
12939 | } | |
12940 | ||
ba318c61 CW |
12941 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
12942 | { | |
12943 | struct intel_atomic_state *state, *next; | |
12944 | struct llist_node *freed; | |
12945 | ||
12946 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
12947 | llist_for_each_entry_safe(state, next, freed, freed) | |
12948 | drm_atomic_state_put(&state->base); | |
12949 | } | |
12950 | ||
12951 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
12952 | { | |
12953 | struct drm_i915_private *dev_priv = | |
12954 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
12955 | ||
12956 | intel_atomic_helper_free_state(dev_priv); | |
12957 | } | |
12958 | ||
94f05024 | 12959 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 12960 | { |
94f05024 | 12961 | struct drm_device *dev = state->dev; |
565602d7 | 12962 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12963 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa5e9b47 | 12964 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
7580d774 | 12965 | struct drm_crtc *crtc; |
5a21b665 | 12966 | struct intel_crtc_state *intel_cstate; |
5a21b665 | 12967 | bool hw_check = intel_state->modeset; |
d8fc70b7 | 12968 | u64 put_domains[I915_MAX_PIPES] = {}; |
5a21b665 | 12969 | unsigned crtc_vblank_mask = 0; |
e95433c7 | 12970 | int i; |
a6778b3c | 12971 | |
ea0000f0 DV |
12972 | drm_atomic_helper_wait_for_dependencies(state); |
12973 | ||
c3b32658 | 12974 | if (intel_state->modeset) |
5a21b665 | 12975 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 12976 | |
aa5e9b47 | 12977 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
a539205a ML |
12978 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12979 | ||
aa5e9b47 ML |
12980 | if (needs_modeset(new_crtc_state) || |
12981 | to_intel_crtc_state(new_crtc_state)->update_pipe) { | |
5a21b665 DV |
12982 | hw_check = true; |
12983 | ||
12984 | put_domains[to_intel_crtc(crtc)->pipe] = | |
12985 | modeset_get_crtc_power_domains(crtc, | |
aa5e9b47 | 12986 | to_intel_crtc_state(new_crtc_state)); |
5a21b665 DV |
12987 | } |
12988 | ||
aa5e9b47 | 12989 | if (!needs_modeset(new_crtc_state)) |
61333b60 ML |
12990 | continue; |
12991 | ||
aa5e9b47 ML |
12992 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12993 | to_intel_crtc_state(new_crtc_state)); | |
460da916 | 12994 | |
29ceb0e6 VS |
12995 | if (old_crtc_state->active) { |
12996 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 12997 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 12998 | intel_crtc->active = false; |
58f9c0bc | 12999 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13000 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13001 | |
13002 | /* | |
13003 | * Underruns don't always raise | |
13004 | * interrupts, so check manually. | |
13005 | */ | |
13006 | intel_check_cpu_fifo_underruns(dev_priv); | |
13007 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 13008 | |
e62929b3 ML |
13009 | if (!crtc->state->active) { |
13010 | /* | |
13011 | * Make sure we don't call initial_watermarks | |
13012 | * for ILK-style watermark updates. | |
ff32c54e VS |
13013 | * |
13014 | * No clue what this is supposed to achieve. | |
e62929b3 | 13015 | */ |
ff32c54e | 13016 | if (INTEL_GEN(dev_priv) >= 9) |
e62929b3 ML |
13017 | dev_priv->display.initial_watermarks(intel_state, |
13018 | to_intel_crtc_state(crtc->state)); | |
e62929b3 | 13019 | } |
a539205a | 13020 | } |
b8cecdf5 | 13021 | } |
7758a113 | 13022 | |
ea9d758d DV |
13023 | /* Only after disabling all output pipelines that will be changed can we |
13024 | * update the the output configuration. */ | |
4740b0f2 | 13025 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13026 | |
565602d7 | 13027 | if (intel_state->modeset) { |
4740b0f2 | 13028 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 | 13029 | |
b0587e4d | 13030 | intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
f6d1973d | 13031 | |
656d1b89 L |
13032 | /* |
13033 | * SKL workaround: bspec recommends we disable the SAGV when we | |
13034 | * have more then one pipe enabled | |
13035 | */ | |
56feca91 | 13036 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 13037 | intel_disable_sagv(dev_priv); |
656d1b89 | 13038 | |
677100ce | 13039 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 13040 | } |
47fab737 | 13041 | |
896e5bb0 | 13042 | /* Complete the events for pipes that have now been disabled */ |
aa5e9b47 ML |
13043 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
13044 | bool modeset = needs_modeset(new_crtc_state); | |
80715b2f | 13045 | |
1f7528c4 | 13046 | /* Complete events for now disable pipes here. */ |
aa5e9b47 | 13047 | if (modeset && !new_crtc_state->active && new_crtc_state->event) { |
1f7528c4 | 13048 | spin_lock_irq(&dev->event_lock); |
aa5e9b47 | 13049 | drm_crtc_send_vblank_event(crtc, new_crtc_state->event); |
1f7528c4 DV |
13050 | spin_unlock_irq(&dev->event_lock); |
13051 | ||
aa5e9b47 | 13052 | new_crtc_state->event = NULL; |
1f7528c4 | 13053 | } |
177246a8 MR |
13054 | } |
13055 | ||
896e5bb0 L |
13056 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
13057 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
13058 | ||
94f05024 DV |
13059 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
13060 | * already, but still need the state for the delayed optimization. To | |
13061 | * fix this: | |
13062 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
13063 | * - schedule that vblank worker _before_ calling hw_done | |
13064 | * - at the start of commit_tail, cancel it _synchrously | |
13065 | * - switch over to the vblank wait helper in the core after that since | |
13066 | * we don't need out special handling any more. | |
13067 | */ | |
5a21b665 DV |
13068 | if (!state->legacy_cursor_update) |
13069 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
13070 | ||
13071 | /* | |
13072 | * Now that the vblank has passed, we can go ahead and program the | |
13073 | * optimal watermarks on platforms that need two-step watermark | |
13074 | * programming. | |
13075 | * | |
13076 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13077 | */ | |
aa5e9b47 ML |
13078 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
13079 | intel_cstate = to_intel_crtc_state(new_crtc_state); | |
5a21b665 DV |
13080 | |
13081 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
13082 | dev_priv->display.optimize_watermarks(intel_state, |
13083 | intel_cstate); | |
5a21b665 DV |
13084 | } |
13085 | ||
aa5e9b47 | 13086 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
5a21b665 DV |
13087 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); |
13088 | ||
13089 | if (put_domains[i]) | |
13090 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13091 | ||
aa5e9b47 | 13092 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); |
5a21b665 DV |
13093 | } |
13094 | ||
56feca91 | 13095 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 13096 | intel_enable_sagv(dev_priv); |
656d1b89 | 13097 | |
94f05024 DV |
13098 | drm_atomic_helper_commit_hw_done(state); |
13099 | ||
5a21b665 DV |
13100 | if (intel_state->modeset) |
13101 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13102 | ||
13103 | mutex_lock(&dev->struct_mutex); | |
13104 | drm_atomic_helper_cleanup_planes(dev, state); | |
13105 | mutex_unlock(&dev->struct_mutex); | |
13106 | ||
ea0000f0 DV |
13107 | drm_atomic_helper_commit_cleanup_done(state); |
13108 | ||
0853695c | 13109 | drm_atomic_state_put(state); |
f30da187 | 13110 | |
75714940 MK |
13111 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13112 | * of triggering bugs in unclaimed access. After we finish | |
13113 | * modesetting, see if an error has been flagged, and if so | |
13114 | * enable debugging for the next modeset - and hope we catch | |
13115 | * the culprit. | |
13116 | * | |
13117 | * XXX note that we assume display power is on at this point. | |
13118 | * This might hold true now but we need to add pm helper to check | |
13119 | * unclaimed only when the hardware is on, as atomic commits | |
13120 | * can happen also when the device is completely off. | |
13121 | */ | |
13122 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
ba318c61 CW |
13123 | |
13124 | intel_atomic_helper_free_state(dev_priv); | |
94f05024 DV |
13125 | } |
13126 | ||
13127 | static void intel_atomic_commit_work(struct work_struct *work) | |
13128 | { | |
c004a90b CW |
13129 | struct drm_atomic_state *state = |
13130 | container_of(work, struct drm_atomic_state, commit_work); | |
13131 | ||
94f05024 DV |
13132 | intel_atomic_commit_tail(state); |
13133 | } | |
13134 | ||
c004a90b CW |
13135 | static int __i915_sw_fence_call |
13136 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
13137 | enum i915_sw_fence_notify notify) | |
13138 | { | |
13139 | struct intel_atomic_state *state = | |
13140 | container_of(fence, struct intel_atomic_state, commit_ready); | |
13141 | ||
13142 | switch (notify) { | |
13143 | case FENCE_COMPLETE: | |
13144 | if (state->base.commit_work.func) | |
13145 | queue_work(system_unbound_wq, &state->base.commit_work); | |
13146 | break; | |
13147 | ||
13148 | case FENCE_FREE: | |
eb955eee CW |
13149 | { |
13150 | struct intel_atomic_helper *helper = | |
13151 | &to_i915(state->base.dev)->atomic_helper; | |
13152 | ||
13153 | if (llist_add(&state->freed, &helper->free_list)) | |
13154 | schedule_work(&helper->free_work); | |
13155 | break; | |
13156 | } | |
c004a90b CW |
13157 | } |
13158 | ||
13159 | return NOTIFY_DONE; | |
13160 | } | |
13161 | ||
6c9c1b38 DV |
13162 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
13163 | { | |
aa5e9b47 | 13164 | struct drm_plane_state *old_plane_state, *new_plane_state; |
6c9c1b38 | 13165 | struct drm_plane *plane; |
6c9c1b38 DV |
13166 | int i; |
13167 | ||
aa5e9b47 | 13168 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) |
faf5bf0a | 13169 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), |
aa5e9b47 | 13170 | intel_fb_obj(new_plane_state->fb), |
faf5bf0a | 13171 | to_intel_plane(plane)->frontbuffer_bit); |
6c9c1b38 DV |
13172 | } |
13173 | ||
94f05024 DV |
13174 | /** |
13175 | * intel_atomic_commit - commit validated state object | |
13176 | * @dev: DRM device | |
13177 | * @state: the top-level driver state object | |
13178 | * @nonblock: nonblocking commit | |
13179 | * | |
13180 | * This function commits a top-level state object that has been validated | |
13181 | * with drm_atomic_helper_check(). | |
13182 | * | |
94f05024 DV |
13183 | * RETURNS |
13184 | * Zero for success or -errno. | |
13185 | */ | |
13186 | static int intel_atomic_commit(struct drm_device *dev, | |
13187 | struct drm_atomic_state *state, | |
13188 | bool nonblock) | |
13189 | { | |
13190 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 13191 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
13192 | int ret = 0; |
13193 | ||
94f05024 DV |
13194 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
13195 | if (ret) | |
13196 | return ret; | |
13197 | ||
c004a90b CW |
13198 | drm_atomic_state_get(state); |
13199 | i915_sw_fence_init(&intel_state->commit_ready, | |
13200 | intel_atomic_commit_ready); | |
94f05024 | 13201 | |
d07f0e59 | 13202 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
13203 | if (ret) { |
13204 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 13205 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
13206 | return ret; |
13207 | } | |
13208 | ||
440df938 VS |
13209 | /* |
13210 | * The intel_legacy_cursor_update() fast path takes care | |
13211 | * of avoiding the vblank waits for simple cursor | |
13212 | * movement and flips. For cursor on/off and size changes, | |
13213 | * we want to perform the vblank waits so that watermark | |
13214 | * updates happen during the correct frames. Gen9+ have | |
13215 | * double buffered watermarks and so shouldn't need this. | |
13216 | * | |
13217 | * Do this after drm_atomic_helper_setup_commit() and | |
13218 | * intel_atomic_prepare_commit() because we still want | |
13219 | * to skip the flip and fb cleanup waits. Although that | |
13220 | * does risk yanking the mapping from under the display | |
13221 | * engine. | |
13222 | * | |
13223 | * FIXME doing watermarks and fb cleanup from a vblank worker | |
13224 | * (assuming we had any) would solve these problems. | |
13225 | */ | |
13226 | if (INTEL_GEN(dev_priv) < 9) | |
13227 | state->legacy_cursor_update = false; | |
13228 | ||
94f05024 DV |
13229 | drm_atomic_helper_swap_state(state, true); |
13230 | dev_priv->wm.distrust_bios_wm = false; | |
3c0fb588 | 13231 | intel_shared_dpll_swap_state(state); |
6c9c1b38 | 13232 | intel_atomic_track_fbs(state); |
94f05024 | 13233 | |
c3b32658 ML |
13234 | if (intel_state->modeset) { |
13235 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13236 | sizeof(intel_state->min_pixclk)); | |
13237 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
bb0f4aab VS |
13238 | dev_priv->cdclk.logical = intel_state->cdclk.logical; |
13239 | dev_priv->cdclk.actual = intel_state->cdclk.actual; | |
c3b32658 ML |
13240 | } |
13241 | ||
0853695c | 13242 | drm_atomic_state_get(state); |
c004a90b CW |
13243 | INIT_WORK(&state->commit_work, |
13244 | nonblock ? intel_atomic_commit_work : NULL); | |
13245 | ||
13246 | i915_sw_fence_commit(&intel_state->commit_ready); | |
13247 | if (!nonblock) { | |
13248 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 13249 | intel_atomic_commit_tail(state); |
c004a90b | 13250 | } |
75714940 | 13251 | |
74c090b1 | 13252 | return 0; |
7f27126e JB |
13253 | } |
13254 | ||
c0c36b94 CW |
13255 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13256 | { | |
83a57153 ACO |
13257 | struct drm_device *dev = crtc->dev; |
13258 | struct drm_atomic_state *state; | |
e694eb02 | 13259 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13260 | int ret; |
83a57153 ACO |
13261 | |
13262 | state = drm_atomic_state_alloc(dev); | |
13263 | if (!state) { | |
78108b7c VS |
13264 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
13265 | crtc->base.id, crtc->name); | |
83a57153 ACO |
13266 | return; |
13267 | } | |
13268 | ||
b260ac3e | 13269 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; |
83a57153 | 13270 | |
e694eb02 ML |
13271 | retry: |
13272 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13273 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13274 | if (!ret) { | |
13275 | if (!crtc_state->active) | |
13276 | goto out; | |
83a57153 | 13277 | |
e694eb02 | 13278 | crtc_state->mode_changed = true; |
74c090b1 | 13279 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13280 | } |
13281 | ||
e694eb02 ML |
13282 | if (ret == -EDEADLK) { |
13283 | drm_atomic_state_clear(state); | |
13284 | drm_modeset_backoff(state->acquire_ctx); | |
13285 | goto retry; | |
4ed9fb37 | 13286 | } |
4be07317 | 13287 | |
e694eb02 | 13288 | out: |
0853695c | 13289 | drm_atomic_state_put(state); |
c0c36b94 CW |
13290 | } |
13291 | ||
f6e5b160 | 13292 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
3fab2f09 | 13293 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 13294 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13295 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 13296 | .destroy = intel_crtc_destroy, |
4c01ded5 | 13297 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
13298 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13299 | .atomic_destroy_state = intel_crtc_destroy_state, | |
8c6b709d | 13300 | .set_crc_source = intel_crtc_set_crc_source, |
f6e5b160 CW |
13301 | }; |
13302 | ||
6beb8c23 MR |
13303 | /** |
13304 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13305 | * @plane: drm plane to prepare for | |
13306 | * @fb: framebuffer to prepare for presentation | |
13307 | * | |
13308 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13309 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13310 | * bits. Some older platforms need special physical address handling for | |
13311 | * cursor planes. | |
13312 | * | |
f935675f ML |
13313 | * Must be called with struct_mutex held. |
13314 | * | |
6beb8c23 MR |
13315 | * Returns 0 on success, negative error code on failure. |
13316 | */ | |
13317 | int | |
13318 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 13319 | struct drm_plane_state *new_state) |
465c120c | 13320 | { |
c004a90b CW |
13321 | struct intel_atomic_state *intel_state = |
13322 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 13323 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 13324 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13325 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13326 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 13327 | int ret; |
465c120c | 13328 | |
57822dc6 CW |
13329 | if (obj) { |
13330 | if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
13331 | INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
fabac484 | 13332 | const int align = intel_cursor_alignment(dev_priv); |
57822dc6 CW |
13333 | |
13334 | ret = i915_gem_object_attach_phys(obj, align); | |
13335 | if (ret) { | |
13336 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13337 | return ret; | |
13338 | } | |
13339 | } else { | |
13340 | struct i915_vma *vma; | |
13341 | ||
13342 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
13343 | if (IS_ERR(vma)) { | |
13344 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13345 | return PTR_ERR(vma); | |
13346 | } | |
13347 | ||
13348 | to_intel_plane_state(new_state)->vma = vma; | |
13349 | } | |
13350 | } | |
13351 | ||
1ee49399 | 13352 | if (!obj && !old_obj) |
465c120c MR |
13353 | return 0; |
13354 | ||
5008e874 ML |
13355 | if (old_obj) { |
13356 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
13357 | drm_atomic_get_existing_crtc_state(new_state->state, |
13358 | plane->state->crtc); | |
5008e874 ML |
13359 | |
13360 | /* Big Hammer, we also need to ensure that any pending | |
13361 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13362 | * current scanout is retired before unpinning the old | |
13363 | * framebuffer. Note that we rely on userspace rendering | |
13364 | * into the buffer attached to the pipe they are waiting | |
13365 | * on. If not, userspace generates a GPU hang with IPEHR | |
13366 | * point to the MI_WAIT_FOR_EVENT. | |
13367 | * | |
13368 | * This should only fail upon a hung GPU, in which case we | |
13369 | * can safely continue. | |
13370 | */ | |
c004a90b CW |
13371 | if (needs_modeset(crtc_state)) { |
13372 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
13373 | old_obj->resv, NULL, | |
13374 | false, 0, | |
13375 | GFP_KERNEL); | |
13376 | if (ret < 0) | |
13377 | return ret; | |
f4457ae7 | 13378 | } |
5008e874 ML |
13379 | } |
13380 | ||
c004a90b CW |
13381 | if (new_state->fence) { /* explicit fencing */ |
13382 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
13383 | new_state->fence, | |
13384 | I915_FENCE_TIMEOUT, | |
13385 | GFP_KERNEL); | |
13386 | if (ret < 0) | |
13387 | return ret; | |
13388 | } | |
13389 | ||
c37efb99 CW |
13390 | if (!obj) |
13391 | return 0; | |
13392 | ||
c004a90b CW |
13393 | if (!new_state->fence) { /* implicit fencing */ |
13394 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
13395 | obj->resv, NULL, | |
13396 | false, I915_FENCE_TIMEOUT, | |
13397 | GFP_KERNEL); | |
13398 | if (ret < 0) | |
13399 | return ret; | |
6b5e90f5 CW |
13400 | |
13401 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
c004a90b | 13402 | } |
5a21b665 | 13403 | |
d07f0e59 | 13404 | return 0; |
6beb8c23 MR |
13405 | } |
13406 | ||
38f3ce3a MR |
13407 | /** |
13408 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13409 | * @plane: drm plane to clean up for | |
13410 | * @fb: old framebuffer that was on plane | |
13411 | * | |
13412 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13413 | * |
13414 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13415 | */ |
13416 | void | |
13417 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 13418 | struct drm_plane_state *old_state) |
38f3ce3a | 13419 | { |
be1e3415 | 13420 | struct i915_vma *vma; |
38f3ce3a | 13421 | |
be1e3415 CW |
13422 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
13423 | vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); | |
13424 | if (vma) | |
13425 | intel_unpin_fb_vma(vma); | |
465c120c MR |
13426 | } |
13427 | ||
6156a456 CK |
13428 | int |
13429 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13430 | { | |
5b7280f0 | 13431 | struct drm_i915_private *dev_priv; |
6156a456 | 13432 | int max_scale; |
5b7280f0 | 13433 | int crtc_clock, max_dotclk; |
6156a456 | 13434 | |
bf8a0af0 | 13435 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13436 | return DRM_PLANE_HELPER_NO_SCALING; |
13437 | ||
5b7280f0 ACO |
13438 | dev_priv = to_i915(intel_crtc->base.dev); |
13439 | ||
6156a456 | 13440 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
5b7280f0 ACO |
13441 | max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; |
13442 | ||
13443 | if (IS_GEMINILAKE(dev_priv)) | |
13444 | max_dotclk *= 2; | |
6156a456 | 13445 | |
5b7280f0 | 13446 | if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) |
6156a456 CK |
13447 | return DRM_PLANE_HELPER_NO_SCALING; |
13448 | ||
13449 | /* | |
13450 | * skl max scale is lower of: | |
13451 | * close to 3 but not 3, -1 is for that purpose | |
13452 | * or | |
13453 | * cdclk/crtc_clock | |
13454 | */ | |
5b7280f0 ACO |
13455 | max_scale = min((1 << 16) * 3 - 1, |
13456 | (1 << 8) * ((max_dotclk << 8) / crtc_clock)); | |
6156a456 CK |
13457 | |
13458 | return max_scale; | |
13459 | } | |
13460 | ||
465c120c | 13461 | static int |
282dbf9b | 13462 | intel_check_primary_plane(struct intel_plane *plane, |
061e4b8d | 13463 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13464 | struct intel_plane_state *state) |
13465 | { | |
282dbf9b | 13466 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
2b875c22 | 13467 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 13468 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13469 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13470 | bool can_position = false; | |
b63a16f6 | 13471 | int ret; |
465c120c | 13472 | |
b63a16f6 | 13473 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
13474 | /* use scaler when colorkey is not required */ |
13475 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13476 | min_scale = 1; | |
13477 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13478 | } | |
d8106366 | 13479 | can_position = true; |
6156a456 | 13480 | } |
d8106366 | 13481 | |
cc926387 DV |
13482 | ret = drm_plane_helper_check_state(&state->base, |
13483 | &state->clip, | |
13484 | min_scale, max_scale, | |
13485 | can_position, true); | |
b63a16f6 VS |
13486 | if (ret) |
13487 | return ret; | |
13488 | ||
cc926387 | 13489 | if (!state->base.fb) |
b63a16f6 VS |
13490 | return 0; |
13491 | ||
13492 | if (INTEL_GEN(dev_priv) >= 9) { | |
13493 | ret = skl_check_plane_surface(state); | |
13494 | if (ret) | |
13495 | return ret; | |
a0864d59 VS |
13496 | |
13497 | state->ctl = skl_plane_ctl(crtc_state, state); | |
13498 | } else { | |
5b7fcc44 VS |
13499 | ret = i9xx_check_plane_surface(state); |
13500 | if (ret) | |
13501 | return ret; | |
13502 | ||
a0864d59 | 13503 | state->ctl = i9xx_plane_ctl(crtc_state, state); |
b63a16f6 VS |
13504 | } |
13505 | ||
13506 | return 0; | |
14af293f GP |
13507 | } |
13508 | ||
5a21b665 DV |
13509 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13510 | struct drm_crtc_state *old_crtc_state) | |
13511 | { | |
13512 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 13513 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 13514 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
13515 | struct intel_crtc_state *intel_cstate = |
13516 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 13517 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 13518 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
13519 | struct intel_atomic_state *old_intel_state = |
13520 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
13521 | bool modeset = needs_modeset(crtc->state); |
13522 | ||
567f0792 ML |
13523 | if (!modeset && |
13524 | (intel_cstate->base.color_mgmt_changed || | |
13525 | intel_cstate->update_pipe)) { | |
13526 | intel_color_set_csc(crtc->state); | |
13527 | intel_color_load_luts(crtc->state); | |
13528 | } | |
13529 | ||
5a21b665 DV |
13530 | /* Perform vblank evasion around commit operation */ |
13531 | intel_pipe_update_start(intel_crtc); | |
13532 | ||
13533 | if (modeset) | |
e62929b3 | 13534 | goto out; |
5a21b665 | 13535 | |
ccf010fb ML |
13536 | if (intel_cstate->update_pipe) |
13537 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
13538 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 13539 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 13540 | |
e62929b3 | 13541 | out: |
ccf010fb ML |
13542 | if (dev_priv->display.atomic_update_watermarks) |
13543 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
13544 | intel_cstate); | |
5a21b665 DV |
13545 | } |
13546 | ||
13547 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
13548 | struct drm_crtc_state *old_crtc_state) | |
13549 | { | |
13550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13551 | ||
13552 | intel_pipe_update_end(intel_crtc, NULL); | |
13553 | } | |
13554 | ||
cf4c7c12 | 13555 | /** |
4a3b8769 MR |
13556 | * intel_plane_destroy - destroy a plane |
13557 | * @plane: plane to destroy | |
cf4c7c12 | 13558 | * |
4a3b8769 MR |
13559 | * Common destruction function for all types of planes (primary, cursor, |
13560 | * sprite). | |
cf4c7c12 | 13561 | */ |
4a3b8769 | 13562 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 13563 | { |
465c120c | 13564 | drm_plane_cleanup(plane); |
69ae561f | 13565 | kfree(to_intel_plane(plane)); |
465c120c MR |
13566 | } |
13567 | ||
65a3fea0 | 13568 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13569 | .update_plane = drm_atomic_helper_update_plane, |
13570 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13571 | .destroy = intel_plane_destroy, |
c196e1d6 | 13572 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13573 | .atomic_get_property = intel_plane_atomic_get_property, |
13574 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13575 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13576 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
13577 | }; |
13578 | ||
f79f2692 ML |
13579 | static int |
13580 | intel_legacy_cursor_update(struct drm_plane *plane, | |
13581 | struct drm_crtc *crtc, | |
13582 | struct drm_framebuffer *fb, | |
13583 | int crtc_x, int crtc_y, | |
13584 | unsigned int crtc_w, unsigned int crtc_h, | |
13585 | uint32_t src_x, uint32_t src_y, | |
34a2ab5e DV |
13586 | uint32_t src_w, uint32_t src_h, |
13587 | struct drm_modeset_acquire_ctx *ctx) | |
f79f2692 ML |
13588 | { |
13589 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
13590 | int ret; | |
13591 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
13592 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13593 | struct drm_framebuffer *old_fb; | |
13594 | struct drm_crtc_state *crtc_state = crtc->state; | |
be1e3415 | 13595 | struct i915_vma *old_vma; |
f79f2692 ML |
13596 | |
13597 | /* | |
13598 | * When crtc is inactive or there is a modeset pending, | |
13599 | * wait for it to complete in the slowpath | |
13600 | */ | |
13601 | if (!crtc_state->active || needs_modeset(crtc_state) || | |
13602 | to_intel_crtc_state(crtc_state)->update_pipe) | |
13603 | goto slow; | |
13604 | ||
13605 | old_plane_state = plane->state; | |
13606 | ||
13607 | /* | |
13608 | * If any parameters change that may affect watermarks, | |
13609 | * take the slowpath. Only changing fb or position should be | |
13610 | * in the fastpath. | |
13611 | */ | |
13612 | if (old_plane_state->crtc != crtc || | |
13613 | old_plane_state->src_w != src_w || | |
13614 | old_plane_state->src_h != src_h || | |
13615 | old_plane_state->crtc_w != crtc_w || | |
13616 | old_plane_state->crtc_h != crtc_h || | |
a5509abd | 13617 | !old_plane_state->fb != !fb) |
f79f2692 ML |
13618 | goto slow; |
13619 | ||
13620 | new_plane_state = intel_plane_duplicate_state(plane); | |
13621 | if (!new_plane_state) | |
13622 | return -ENOMEM; | |
13623 | ||
13624 | drm_atomic_set_fb_for_plane(new_plane_state, fb); | |
13625 | ||
13626 | new_plane_state->src_x = src_x; | |
13627 | new_plane_state->src_y = src_y; | |
13628 | new_plane_state->src_w = src_w; | |
13629 | new_plane_state->src_h = src_h; | |
13630 | new_plane_state->crtc_x = crtc_x; | |
13631 | new_plane_state->crtc_y = crtc_y; | |
13632 | new_plane_state->crtc_w = crtc_w; | |
13633 | new_plane_state->crtc_h = crtc_h; | |
13634 | ||
13635 | ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), | |
13636 | to_intel_plane_state(new_plane_state)); | |
13637 | if (ret) | |
13638 | goto out_free; | |
13639 | ||
f79f2692 ML |
13640 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
13641 | if (ret) | |
13642 | goto out_free; | |
13643 | ||
13644 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
fabac484 | 13645 | int align = intel_cursor_alignment(dev_priv); |
f79f2692 ML |
13646 | |
13647 | ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align); | |
13648 | if (ret) { | |
13649 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13650 | goto out_unlock; | |
13651 | } | |
13652 | } else { | |
13653 | struct i915_vma *vma; | |
13654 | ||
13655 | vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); | |
13656 | if (IS_ERR(vma)) { | |
13657 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13658 | ||
13659 | ret = PTR_ERR(vma); | |
13660 | goto out_unlock; | |
13661 | } | |
be1e3415 CW |
13662 | |
13663 | to_intel_plane_state(new_plane_state)->vma = vma; | |
f79f2692 ML |
13664 | } |
13665 | ||
13666 | old_fb = old_plane_state->fb; | |
be1e3415 | 13667 | old_vma = to_intel_plane_state(old_plane_state)->vma; |
f79f2692 ML |
13668 | |
13669 | i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), | |
13670 | intel_plane->frontbuffer_bit); | |
13671 | ||
13672 | /* Swap plane state */ | |
13673 | new_plane_state->fence = old_plane_state->fence; | |
13674 | *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state); | |
13675 | new_plane_state->fence = NULL; | |
13676 | new_plane_state->fb = old_fb; | |
be1e3415 | 13677 | to_intel_plane_state(new_plane_state)->vma = old_vma; |
f79f2692 | 13678 | |
72259536 VS |
13679 | if (plane->state->visible) { |
13680 | trace_intel_update_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 13681 | intel_plane->update_plane(intel_plane, |
a5509abd VS |
13682 | to_intel_crtc_state(crtc->state), |
13683 | to_intel_plane_state(plane->state)); | |
72259536 VS |
13684 | } else { |
13685 | trace_intel_disable_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 13686 | intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc)); |
72259536 | 13687 | } |
f79f2692 ML |
13688 | |
13689 | intel_cleanup_plane_fb(plane, new_plane_state); | |
13690 | ||
13691 | out_unlock: | |
13692 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
13693 | out_free: | |
13694 | intel_plane_destroy_state(plane, new_plane_state); | |
13695 | return ret; | |
13696 | ||
f79f2692 ML |
13697 | slow: |
13698 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
13699 | crtc_x, crtc_y, crtc_w, crtc_h, | |
34a2ab5e | 13700 | src_x, src_y, src_w, src_h, ctx); |
f79f2692 ML |
13701 | } |
13702 | ||
13703 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
13704 | .update_plane = intel_legacy_cursor_update, | |
13705 | .disable_plane = drm_atomic_helper_disable_plane, | |
13706 | .destroy = intel_plane_destroy, | |
13707 | .set_property = drm_atomic_helper_plane_set_property, | |
13708 | .atomic_get_property = intel_plane_atomic_get_property, | |
13709 | .atomic_set_property = intel_plane_atomic_set_property, | |
13710 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
13711 | .atomic_destroy_state = intel_plane_destroy_state, | |
13712 | }; | |
13713 | ||
b079bd17 | 13714 | static struct intel_plane * |
580503c7 | 13715 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 13716 | { |
fca0ce2a VS |
13717 | struct intel_plane *primary = NULL; |
13718 | struct intel_plane_state *state = NULL; | |
465c120c | 13719 | const uint32_t *intel_primary_formats; |
93ca7e00 | 13720 | unsigned int supported_rotations; |
45e3743a | 13721 | unsigned int num_formats; |
fca0ce2a | 13722 | int ret; |
465c120c MR |
13723 | |
13724 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
13725 | if (!primary) { |
13726 | ret = -ENOMEM; | |
fca0ce2a | 13727 | goto fail; |
b079bd17 | 13728 | } |
465c120c | 13729 | |
8e7d688b | 13730 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
13731 | if (!state) { |
13732 | ret = -ENOMEM; | |
fca0ce2a | 13733 | goto fail; |
b079bd17 VS |
13734 | } |
13735 | ||
8e7d688b | 13736 | primary->base.state = &state->base; |
ea2c67bb | 13737 | |
465c120c MR |
13738 | primary->can_scale = false; |
13739 | primary->max_downscale = 1; | |
580503c7 | 13740 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 13741 | primary->can_scale = true; |
af99ceda | 13742 | state->scaler_id = -1; |
6156a456 | 13743 | } |
465c120c | 13744 | primary->pipe = pipe; |
e3c566df VS |
13745 | /* |
13746 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
13747 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
13748 | */ | |
13749 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
13750 | primary->plane = (enum plane) !pipe; | |
13751 | else | |
13752 | primary->plane = (enum plane) pipe; | |
b14e5848 | 13753 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 13754 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13755 | primary->check_plane = intel_check_primary_plane; |
465c120c | 13756 | |
580503c7 | 13757 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
13758 | intel_primary_formats = skl_primary_formats; |
13759 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
13760 | |
13761 | primary->update_plane = skylake_update_primary_plane; | |
13762 | primary->disable_plane = skylake_disable_primary_plane; | |
580503c7 | 13763 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
13764 | intel_primary_formats = i965_primary_formats; |
13765 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
13766 | |
13767 | primary->update_plane = i9xx_update_primary_plane; | |
13768 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13769 | } else { |
13770 | intel_primary_formats = i8xx_primary_formats; | |
13771 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
13772 | |
13773 | primary->update_plane = i9xx_update_primary_plane; | |
13774 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13775 | } |
13776 | ||
580503c7 VS |
13777 | if (INTEL_GEN(dev_priv) >= 9) |
13778 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
13779 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13780 | intel_primary_formats, num_formats, |
13781 | DRM_PLANE_TYPE_PRIMARY, | |
13782 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 13783 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
13784 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13785 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13786 | intel_primary_formats, num_formats, |
13787 | DRM_PLANE_TYPE_PRIMARY, | |
13788 | "primary %c", pipe_name(pipe)); | |
13789 | else | |
580503c7 VS |
13790 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13791 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13792 | intel_primary_formats, num_formats, |
13793 | DRM_PLANE_TYPE_PRIMARY, | |
13794 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
13795 | if (ret) |
13796 | goto fail; | |
48404c1e | 13797 | |
5481e27f | 13798 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 | 13799 | supported_rotations = |
c2c446ad RF |
13800 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | |
13801 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; | |
4ea7be2b VS |
13802 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
13803 | supported_rotations = | |
c2c446ad RF |
13804 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | |
13805 | DRM_MODE_REFLECT_X; | |
5481e27f | 13806 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 | 13807 | supported_rotations = |
c2c446ad | 13808 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; |
93ca7e00 | 13809 | } else { |
c2c446ad | 13810 | supported_rotations = DRM_MODE_ROTATE_0; |
93ca7e00 VS |
13811 | } |
13812 | ||
5481e27f | 13813 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13814 | drm_plane_create_rotation_property(&primary->base, |
c2c446ad | 13815 | DRM_MODE_ROTATE_0, |
93ca7e00 | 13816 | supported_rotations); |
48404c1e | 13817 | |
ea2c67bb MR |
13818 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13819 | ||
b079bd17 | 13820 | return primary; |
fca0ce2a VS |
13821 | |
13822 | fail: | |
13823 | kfree(state); | |
13824 | kfree(primary); | |
13825 | ||
b079bd17 | 13826 | return ERR_PTR(ret); |
465c120c MR |
13827 | } |
13828 | ||
b079bd17 | 13829 | static struct intel_plane * |
b2d03b0d VS |
13830 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, |
13831 | enum pipe pipe) | |
3d7d6510 | 13832 | { |
fca0ce2a VS |
13833 | struct intel_plane *cursor = NULL; |
13834 | struct intel_plane_state *state = NULL; | |
13835 | int ret; | |
3d7d6510 MR |
13836 | |
13837 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
13838 | if (!cursor) { |
13839 | ret = -ENOMEM; | |
fca0ce2a | 13840 | goto fail; |
b079bd17 | 13841 | } |
3d7d6510 | 13842 | |
8e7d688b | 13843 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
13844 | if (!state) { |
13845 | ret = -ENOMEM; | |
fca0ce2a | 13846 | goto fail; |
b079bd17 VS |
13847 | } |
13848 | ||
8e7d688b | 13849 | cursor->base.state = &state->base; |
ea2c67bb | 13850 | |
3d7d6510 MR |
13851 | cursor->can_scale = false; |
13852 | cursor->max_downscale = 1; | |
13853 | cursor->pipe = pipe; | |
13854 | cursor->plane = pipe; | |
b14e5848 | 13855 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 13856 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
b2d03b0d VS |
13857 | |
13858 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { | |
13859 | cursor->update_plane = i845_update_cursor; | |
13860 | cursor->disable_plane = i845_disable_cursor; | |
659056f2 | 13861 | cursor->check_plane = i845_check_cursor; |
b2d03b0d VS |
13862 | } else { |
13863 | cursor->update_plane = i9xx_update_cursor; | |
13864 | cursor->disable_plane = i9xx_disable_cursor; | |
659056f2 | 13865 | cursor->check_plane = i9xx_check_cursor; |
b2d03b0d | 13866 | } |
3d7d6510 | 13867 | |
cd5dcbf1 VS |
13868 | cursor->cursor.base = ~0; |
13869 | cursor->cursor.cntl = ~0; | |
024faac7 VS |
13870 | |
13871 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) | |
13872 | cursor->cursor.size = ~0; | |
3d7d6510 | 13873 | |
580503c7 | 13874 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
f79f2692 | 13875 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
13876 | intel_cursor_formats, |
13877 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
13878 | DRM_PLANE_TYPE_CURSOR, |
13879 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
13880 | if (ret) |
13881 | goto fail; | |
4398ad45 | 13882 | |
5481e27f | 13883 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13884 | drm_plane_create_rotation_property(&cursor->base, |
c2c446ad RF |
13885 | DRM_MODE_ROTATE_0, |
13886 | DRM_MODE_ROTATE_0 | | |
13887 | DRM_MODE_ROTATE_180); | |
4398ad45 | 13888 | |
580503c7 | 13889 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
13890 | state->scaler_id = -1; |
13891 | ||
ea2c67bb MR |
13892 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13893 | ||
b079bd17 | 13894 | return cursor; |
fca0ce2a VS |
13895 | |
13896 | fail: | |
13897 | kfree(state); | |
13898 | kfree(cursor); | |
13899 | ||
b079bd17 | 13900 | return ERR_PTR(ret); |
3d7d6510 MR |
13901 | } |
13902 | ||
1c74eeaf NM |
13903 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
13904 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 13905 | { |
65edccce VS |
13906 | struct intel_crtc_scaler_state *scaler_state = |
13907 | &crtc_state->scaler_state; | |
1c74eeaf | 13908 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
549e2bfb | 13909 | int i; |
549e2bfb | 13910 | |
1c74eeaf NM |
13911 | crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; |
13912 | if (!crtc->num_scalers) | |
13913 | return; | |
13914 | ||
65edccce VS |
13915 | for (i = 0; i < crtc->num_scalers; i++) { |
13916 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
13917 | ||
13918 | scaler->in_use = 0; | |
13919 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
13920 | } |
13921 | ||
13922 | scaler_state->scaler_id = -1; | |
13923 | } | |
13924 | ||
5ab0d85b | 13925 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
13926 | { |
13927 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 13928 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
13929 | struct intel_plane *primary = NULL; |
13930 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 13931 | int sprite, ret; |
79e53945 | 13932 | |
955382f3 | 13933 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
13934 | if (!intel_crtc) |
13935 | return -ENOMEM; | |
79e53945 | 13936 | |
f5de6e07 | 13937 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
13938 | if (!crtc_state) { |
13939 | ret = -ENOMEM; | |
f5de6e07 | 13940 | goto fail; |
b079bd17 | 13941 | } |
550acefd ACO |
13942 | intel_crtc->config = crtc_state; |
13943 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13944 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13945 | |
580503c7 | 13946 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
13947 | if (IS_ERR(primary)) { |
13948 | ret = PTR_ERR(primary); | |
3d7d6510 | 13949 | goto fail; |
b079bd17 | 13950 | } |
d97d7b48 | 13951 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 13952 | |
a81d6fa0 | 13953 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
13954 | struct intel_plane *plane; |
13955 | ||
580503c7 | 13956 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 13957 | if (IS_ERR(plane)) { |
b079bd17 VS |
13958 | ret = PTR_ERR(plane); |
13959 | goto fail; | |
13960 | } | |
d97d7b48 | 13961 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
13962 | } |
13963 | ||
580503c7 | 13964 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 13965 | if (IS_ERR(cursor)) { |
b079bd17 | 13966 | ret = PTR_ERR(cursor); |
3d7d6510 | 13967 | goto fail; |
b079bd17 | 13968 | } |
d97d7b48 | 13969 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 13970 | |
5ab0d85b | 13971 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
13972 | &primary->base, &cursor->base, |
13973 | &intel_crtc_funcs, | |
4d5d72b7 | 13974 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
13975 | if (ret) |
13976 | goto fail; | |
79e53945 | 13977 | |
80824003 | 13978 | intel_crtc->pipe = pipe; |
e3c566df | 13979 | intel_crtc->plane = primary->plane; |
80824003 | 13980 | |
1c74eeaf NM |
13981 | /* initialize shared scalers */ |
13982 | intel_crtc_init_scalers(intel_crtc, crtc_state); | |
13983 | ||
22fd0fab JB |
13984 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13985 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
13986 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
13987 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 13988 | |
79e53945 | 13989 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13990 | |
8563b1e8 LL |
13991 | intel_color_init(&intel_crtc->base); |
13992 | ||
87b6b101 | 13993 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
13994 | |
13995 | return 0; | |
3d7d6510 MR |
13996 | |
13997 | fail: | |
b079bd17 VS |
13998 | /* |
13999 | * drm_mode_config_cleanup() will free up any | |
14000 | * crtcs/planes already initialized. | |
14001 | */ | |
f5de6e07 | 14002 | kfree(crtc_state); |
3d7d6510 | 14003 | kfree(intel_crtc); |
b079bd17 VS |
14004 | |
14005 | return ret; | |
79e53945 JB |
14006 | } |
14007 | ||
752aa88a JB |
14008 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14009 | { | |
6e9f798d | 14010 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14011 | |
51fd371b | 14012 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14013 | |
51ec53da | 14014 | if (!connector->base.state->crtc) |
752aa88a JB |
14015 | return INVALID_PIPE; |
14016 | ||
51ec53da | 14017 | return to_intel_crtc(connector->base.state->crtc)->pipe; |
752aa88a JB |
14018 | } |
14019 | ||
08d7b3d1 | 14020 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14021 | struct drm_file *file) |
08d7b3d1 | 14022 | { |
08d7b3d1 | 14023 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14024 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14025 | struct intel_crtc *crtc; |
08d7b3d1 | 14026 | |
7707e653 | 14027 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 14028 | if (!drmmode_crtc) |
3f2c2057 | 14029 | return -ENOENT; |
08d7b3d1 | 14030 | |
7707e653 | 14031 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14032 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14033 | |
c05422d5 | 14034 | return 0; |
08d7b3d1 CW |
14035 | } |
14036 | ||
66a9278e | 14037 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14038 | { |
66a9278e DV |
14039 | struct drm_device *dev = encoder->base.dev; |
14040 | struct intel_encoder *source_encoder; | |
79e53945 | 14041 | int index_mask = 0; |
79e53945 JB |
14042 | int entry = 0; |
14043 | ||
b2784e15 | 14044 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14045 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14046 | index_mask |= (1 << entry); |
14047 | ||
79e53945 JB |
14048 | entry++; |
14049 | } | |
4ef69c7a | 14050 | |
79e53945 JB |
14051 | return index_mask; |
14052 | } | |
14053 | ||
646d5772 | 14054 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 14055 | { |
646d5772 | 14056 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
14057 | return false; |
14058 | ||
14059 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14060 | return false; | |
14061 | ||
5db94019 | 14062 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14063 | return false; |
14064 | ||
14065 | return true; | |
14066 | } | |
14067 | ||
6315b5d3 | 14068 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 14069 | { |
6315b5d3 | 14070 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
14071 | return false; |
14072 | ||
50a0bc90 | 14073 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
14074 | return false; |
14075 | ||
920a14b2 | 14076 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
14077 | return false; |
14078 | ||
4f8036a2 TU |
14079 | if (HAS_PCH_LPT_H(dev_priv) && |
14080 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
14081 | return false; |
14082 | ||
70ac54d0 | 14083 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 14084 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
14085 | return false; |
14086 | ||
e4abb733 | 14087 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14088 | return false; |
14089 | ||
14090 | return true; | |
14091 | } | |
14092 | ||
8090ba8c ID |
14093 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
14094 | { | |
14095 | int pps_num; | |
14096 | int pps_idx; | |
14097 | ||
14098 | if (HAS_DDI(dev_priv)) | |
14099 | return; | |
14100 | /* | |
14101 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
14102 | * everywhere where registers can be write protected. | |
14103 | */ | |
14104 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14105 | pps_num = 2; | |
14106 | else | |
14107 | pps_num = 1; | |
14108 | ||
14109 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
14110 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
14111 | ||
14112 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
14113 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
14114 | } | |
14115 | } | |
14116 | ||
44cb734c ID |
14117 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
14118 | { | |
cc3f90f0 | 14119 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
14120 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
14121 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14122 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
14123 | else | |
14124 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
14125 | |
14126 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
14127 | } |
14128 | ||
c39055b0 | 14129 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 14130 | { |
4ef69c7a | 14131 | struct intel_encoder *encoder; |
cb0953d7 | 14132 | bool dpd_is_edp = false; |
79e53945 | 14133 | |
44cb734c ID |
14134 | intel_pps_init(dev_priv); |
14135 | ||
97a824e1 ID |
14136 | /* |
14137 | * intel_edp_init_connector() depends on this completing first, to | |
14138 | * prevent the registeration of both eDP and LVDS and the incorrect | |
14139 | * sharing of the PPS. | |
14140 | */ | |
c39055b0 | 14141 | intel_lvds_init(dev_priv); |
79e53945 | 14142 | |
6315b5d3 | 14143 | if (intel_crt_present(dev_priv)) |
c39055b0 | 14144 | intel_crt_init(dev_priv); |
cb0953d7 | 14145 | |
cc3f90f0 | 14146 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
14147 | /* |
14148 | * FIXME: Broxton doesn't support port detection via the | |
14149 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14150 | * detect the ports. | |
14151 | */ | |
c39055b0 ACO |
14152 | intel_ddi_init(dev_priv, PORT_A); |
14153 | intel_ddi_init(dev_priv, PORT_B); | |
14154 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 14155 | |
c39055b0 | 14156 | intel_dsi_init(dev_priv); |
4f8036a2 | 14157 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
14158 | int found; |
14159 | ||
de31facd JB |
14160 | /* |
14161 | * Haswell uses DDI functions to detect digital outputs. | |
14162 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14163 | * it's there. | |
14164 | */ | |
77179400 | 14165 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14166 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 14167 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 14168 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
14169 | |
14170 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14171 | * register */ | |
14172 | found = I915_READ(SFUSE_STRAP); | |
14173 | ||
14174 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 14175 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 14176 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 14177 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 14178 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 14179 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
14180 | /* |
14181 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14182 | */ | |
b976dc53 | 14183 | if (IS_GEN9_BC(dev_priv) && |
2800e4c2 RV |
14184 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14185 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14186 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 14187 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 14188 | |
6e266956 | 14189 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 14190 | int found; |
dd11bc10 | 14191 | dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); |
270b3042 | 14192 | |
646d5772 | 14193 | if (has_edp_a(dev_priv)) |
c39055b0 | 14194 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 14195 | |
dc0fa718 | 14196 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14197 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 14198 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 14199 | if (!found) |
c39055b0 | 14200 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 14201 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 14202 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14203 | } |
14204 | ||
dc0fa718 | 14205 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 14206 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 14207 | |
dc0fa718 | 14208 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 14209 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 14210 | |
5eb08b69 | 14211 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 14212 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 14213 | |
270b3042 | 14214 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 14215 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 14216 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 14217 | bool has_edp, has_port; |
457c52d8 | 14218 | |
e17ac6db VS |
14219 | /* |
14220 | * The DP_DETECTED bit is the latched state of the DDC | |
14221 | * SDA pin at boot. However since eDP doesn't require DDC | |
14222 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14223 | * eDP ports may have been muxed to an alternate function. | |
14224 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14225 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14226 | * detect eDP ports. | |
22f35042 VS |
14227 | * |
14228 | * Sadly the straps seem to be missing sometimes even for HDMI | |
14229 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
14230 | * and VBT for the presence of the port. Additionally we can't | |
14231 | * trust the port type the VBT declares as we've seen at least | |
14232 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 14233 | */ |
dd11bc10 | 14234 | has_edp = intel_dp_is_edp(dev_priv, PORT_B); |
22f35042 VS |
14235 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
14236 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 14237 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 14238 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 14239 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 14240 | |
dd11bc10 | 14241 | has_edp = intel_dp_is_edp(dev_priv, PORT_C); |
22f35042 VS |
14242 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
14243 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 14244 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 14245 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 14246 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 14247 | |
920a14b2 | 14248 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
14249 | /* |
14250 | * eDP not supported on port D, | |
14251 | * so no need to worry about it | |
14252 | */ | |
14253 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
14254 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 14255 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 14256 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 14257 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
14258 | } |
14259 | ||
c39055b0 | 14260 | intel_dsi_init(dev_priv); |
5db94019 | 14261 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 14262 | bool found = false; |
7d57382e | 14263 | |
e2debe91 | 14264 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14265 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 14266 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 14267 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 14268 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 14269 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14270 | } |
27185ae1 | 14271 | |
9beb5fea | 14272 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 14273 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 14274 | } |
13520b05 KH |
14275 | |
14276 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14277 | |
e2debe91 | 14278 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14279 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 14280 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14281 | } |
27185ae1 | 14282 | |
e2debe91 | 14283 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14284 | |
9beb5fea | 14285 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 14286 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 14287 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14288 | } |
9beb5fea | 14289 | if (IS_G4X(dev_priv)) |
c39055b0 | 14290 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 14291 | } |
27185ae1 | 14292 | |
9beb5fea | 14293 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 14294 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 14295 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 14296 | intel_dvo_init(dev_priv); |
79e53945 | 14297 | |
56b857a5 | 14298 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 14299 | intel_tv_init(dev_priv); |
79e53945 | 14300 | |
c39055b0 | 14301 | intel_psr_init(dev_priv); |
7c8f8a70 | 14302 | |
c39055b0 | 14303 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
14304 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14305 | encoder->base.possible_clones = | |
66a9278e | 14306 | intel_encoder_clones(encoder); |
79e53945 | 14307 | } |
47356eb6 | 14308 | |
c39055b0 | 14309 | intel_init_pch_refclk(dev_priv); |
270b3042 | 14310 | |
c39055b0 | 14311 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
14312 | } |
14313 | ||
14314 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14315 | { | |
14316 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 14317 | |
ef2d633e | 14318 | drm_framebuffer_cleanup(fb); |
70001cd2 | 14319 | |
dd689287 CW |
14320 | i915_gem_object_lock(intel_fb->obj); |
14321 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
14322 | i915_gem_object_unlock(intel_fb->obj); | |
14323 | ||
f8c417cd | 14324 | i915_gem_object_put(intel_fb->obj); |
70001cd2 | 14325 | |
79e53945 JB |
14326 | kfree(intel_fb); |
14327 | } | |
14328 | ||
14329 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14330 | struct drm_file *file, |
79e53945 JB |
14331 | unsigned int *handle) |
14332 | { | |
14333 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14334 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14335 | |
cc917ab4 CW |
14336 | if (obj->userptr.mm) { |
14337 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14338 | return -EINVAL; | |
14339 | } | |
14340 | ||
05394f39 | 14341 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14342 | } |
14343 | ||
86c98588 RV |
14344 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14345 | struct drm_file *file, | |
14346 | unsigned flags, unsigned color, | |
14347 | struct drm_clip_rect *clips, | |
14348 | unsigned num_clips) | |
14349 | { | |
5a97bcc6 | 14350 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 14351 | |
5a97bcc6 | 14352 | i915_gem_object_flush_if_display(obj); |
d59b21ec | 14353 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
86c98588 RV |
14354 | |
14355 | return 0; | |
14356 | } | |
14357 | ||
79e53945 JB |
14358 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14359 | .destroy = intel_user_framebuffer_destroy, | |
14360 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14361 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14362 | }; |
14363 | ||
b321803d | 14364 | static |
920a14b2 TU |
14365 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
14366 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 14367 | { |
24dbf51a | 14368 | u32 gen = INTEL_GEN(dev_priv); |
b321803d DL |
14369 | |
14370 | if (gen >= 9) { | |
ac484963 VS |
14371 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14372 | ||
b321803d DL |
14373 | /* "The stride in bytes must not exceed the of the size of 8K |
14374 | * pixels and 32K bytes." | |
14375 | */ | |
ac484963 | 14376 | return min(8192 * cpp, 32768); |
6401c37d | 14377 | } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) { |
b321803d DL |
14378 | return 32*1024; |
14379 | } else if (gen >= 4) { | |
14380 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14381 | return 16*1024; | |
14382 | else | |
14383 | return 32*1024; | |
14384 | } else if (gen >= 3) { | |
14385 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14386 | return 8*1024; | |
14387 | else | |
14388 | return 16*1024; | |
14389 | } else { | |
14390 | /* XXX DSPC is limited to 4k tiled */ | |
14391 | return 8*1024; | |
14392 | } | |
14393 | } | |
14394 | ||
24dbf51a CW |
14395 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
14396 | struct drm_i915_gem_object *obj, | |
14397 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 14398 | { |
24dbf51a | 14399 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
b3c11ac2 | 14400 | struct drm_format_name_buf format_name; |
dd689287 CW |
14401 | u32 pitch_limit, stride_alignment; |
14402 | unsigned int tiling, stride; | |
24dbf51a | 14403 | int ret = -EINVAL; |
79e53945 | 14404 | |
dd689287 CW |
14405 | i915_gem_object_lock(obj); |
14406 | obj->framebuffer_references++; | |
14407 | tiling = i915_gem_object_get_tiling(obj); | |
14408 | stride = i915_gem_object_get_stride(obj); | |
14409 | i915_gem_object_unlock(obj); | |
dd4916c5 | 14410 | |
2a80eada | 14411 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
14412 | /* |
14413 | * If there's a fence, enforce that | |
14414 | * the fb modifier and tiling mode match. | |
14415 | */ | |
14416 | if (tiling != I915_TILING_NONE && | |
14417 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 14418 | DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n"); |
24dbf51a | 14419 | goto err; |
2a80eada DV |
14420 | } |
14421 | } else { | |
c2ff7370 | 14422 | if (tiling == I915_TILING_X) { |
2a80eada | 14423 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 14424 | } else if (tiling == I915_TILING_Y) { |
144cc143 | 14425 | DRM_DEBUG_KMS("No Y tiling for legacy addfb\n"); |
24dbf51a | 14426 | goto err; |
2a80eada DV |
14427 | } |
14428 | } | |
14429 | ||
9a8f0a12 TU |
14430 | /* Passed in modifier sanity checking. */ |
14431 | switch (mode_cmd->modifier[0]) { | |
14432 | case I915_FORMAT_MOD_Y_TILED: | |
14433 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 14434 | if (INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
14435 | DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", |
14436 | mode_cmd->modifier[0]); | |
24dbf51a | 14437 | goto err; |
9a8f0a12 | 14438 | } |
2f075565 | 14439 | case DRM_FORMAT_MOD_LINEAR: |
9a8f0a12 TU |
14440 | case I915_FORMAT_MOD_X_TILED: |
14441 | break; | |
14442 | default: | |
144cc143 VS |
14443 | DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n", |
14444 | mode_cmd->modifier[0]); | |
24dbf51a | 14445 | goto err; |
c16ed4be | 14446 | } |
57cd6508 | 14447 | |
c2ff7370 VS |
14448 | /* |
14449 | * gen2/3 display engine uses the fence if present, | |
14450 | * so the tiling mode must match the fb modifier exactly. | |
14451 | */ | |
14452 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
14453 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 14454 | DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); |
9aceb5c1 | 14455 | goto err; |
c2ff7370 VS |
14456 | } |
14457 | ||
920a14b2 | 14458 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 14459 | mode_cmd->pixel_format); |
a35cdaa0 | 14460 | if (mode_cmd->pitches[0] > pitch_limit) { |
144cc143 | 14461 | DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n", |
2f075565 | 14462 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? |
144cc143 VS |
14463 | "tiled" : "linear", |
14464 | mode_cmd->pitches[0], pitch_limit); | |
24dbf51a | 14465 | goto err; |
c16ed4be | 14466 | } |
5d7bd705 | 14467 | |
c2ff7370 VS |
14468 | /* |
14469 | * If there's a fence, enforce that | |
14470 | * the fb pitch and fence stride match. | |
14471 | */ | |
144cc143 VS |
14472 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
14473 | DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n", | |
14474 | mode_cmd->pitches[0], stride); | |
24dbf51a | 14475 | goto err; |
c16ed4be | 14476 | } |
5d7bd705 | 14477 | |
57779d06 | 14478 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14479 | switch (mode_cmd->pixel_format) { |
57779d06 | 14480 | case DRM_FORMAT_C8: |
04b3924d VS |
14481 | case DRM_FORMAT_RGB565: |
14482 | case DRM_FORMAT_XRGB8888: | |
14483 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14484 | break; |
14485 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 14486 | if (INTEL_GEN(dev_priv) > 3) { |
144cc143 VS |
14487 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14488 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14489 | goto err; |
c16ed4be | 14490 | } |
57779d06 | 14491 | break; |
57779d06 | 14492 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 14493 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 14494 | INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
14495 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14496 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14497 | goto err; |
6c0fd451 DL |
14498 | } |
14499 | break; | |
14500 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14501 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14502 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 14503 | if (INTEL_GEN(dev_priv) < 4) { |
144cc143 VS |
14504 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14505 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14506 | goto err; |
c16ed4be | 14507 | } |
b5626747 | 14508 | break; |
7531208b | 14509 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 14510 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
144cc143 VS |
14511 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14512 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14513 | goto err; |
7531208b DL |
14514 | } |
14515 | break; | |
04b3924d VS |
14516 | case DRM_FORMAT_YUYV: |
14517 | case DRM_FORMAT_UYVY: | |
14518 | case DRM_FORMAT_YVYU: | |
14519 | case DRM_FORMAT_VYUY: | |
ab33081a | 14520 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
144cc143 VS |
14521 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14522 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14523 | goto err; |
c16ed4be | 14524 | } |
57cd6508 CW |
14525 | break; |
14526 | default: | |
144cc143 VS |
14527 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14528 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14529 | goto err; |
57cd6508 CW |
14530 | } |
14531 | ||
90f9a336 VS |
14532 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14533 | if (mode_cmd->offsets[0] != 0) | |
24dbf51a | 14534 | goto err; |
90f9a336 | 14535 | |
24dbf51a CW |
14536 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, |
14537 | &intel_fb->base, mode_cmd); | |
d88c4afd VS |
14538 | |
14539 | stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0); | |
14540 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
144cc143 VS |
14541 | DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n", |
14542 | mode_cmd->pitches[0], stride_alignment); | |
d88c4afd VS |
14543 | goto err; |
14544 | } | |
14545 | ||
c7d73f6a DV |
14546 | intel_fb->obj = obj; |
14547 | ||
6687c906 VS |
14548 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
14549 | if (ret) | |
9aceb5c1 | 14550 | goto err; |
2d7a215f | 14551 | |
24dbf51a CW |
14552 | ret = drm_framebuffer_init(obj->base.dev, |
14553 | &intel_fb->base, | |
14554 | &intel_fb_funcs); | |
79e53945 JB |
14555 | if (ret) { |
14556 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
24dbf51a | 14557 | goto err; |
79e53945 JB |
14558 | } |
14559 | ||
79e53945 | 14560 | return 0; |
24dbf51a CW |
14561 | |
14562 | err: | |
dd689287 CW |
14563 | i915_gem_object_lock(obj); |
14564 | obj->framebuffer_references--; | |
14565 | i915_gem_object_unlock(obj); | |
24dbf51a | 14566 | return ret; |
79e53945 JB |
14567 | } |
14568 | ||
79e53945 JB |
14569 | static struct drm_framebuffer * |
14570 | intel_user_framebuffer_create(struct drm_device *dev, | |
14571 | struct drm_file *filp, | |
1eb83451 | 14572 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14573 | { |
dcb1394e | 14574 | struct drm_framebuffer *fb; |
05394f39 | 14575 | struct drm_i915_gem_object *obj; |
76dc3769 | 14576 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14577 | |
03ac0642 CW |
14578 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
14579 | if (!obj) | |
cce13ff7 | 14580 | return ERR_PTR(-ENOENT); |
79e53945 | 14581 | |
24dbf51a | 14582 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 14583 | if (IS_ERR(fb)) |
f0cd5182 | 14584 | i915_gem_object_put(obj); |
dcb1394e LW |
14585 | |
14586 | return fb; | |
79e53945 JB |
14587 | } |
14588 | ||
778e23a9 CW |
14589 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
14590 | { | |
14591 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
14592 | ||
14593 | drm_atomic_state_default_release(state); | |
14594 | ||
14595 | i915_sw_fence_fini(&intel_state->commit_ready); | |
14596 | ||
14597 | kfree(state); | |
14598 | } | |
14599 | ||
79e53945 | 14600 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14601 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14602 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14603 | .atomic_check = intel_atomic_check, |
14604 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14605 | .atomic_state_alloc = intel_atomic_state_alloc, |
14606 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 14607 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
14608 | }; |
14609 | ||
88212941 ID |
14610 | /** |
14611 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14612 | * @dev_priv: device private | |
14613 | */ | |
14614 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14615 | { |
7ff89ca2 VS |
14616 | intel_init_cdclk_hooks(dev_priv); |
14617 | ||
88212941 | 14618 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14619 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14620 | dev_priv->display.get_initial_plane_config = |
14621 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14622 | dev_priv->display.crtc_compute_clock = |
14623 | haswell_crtc_compute_clock; | |
14624 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14625 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14626 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14627 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14628 | dev_priv->display.get_initial_plane_config = |
14629 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14630 | dev_priv->display.crtc_compute_clock = |
14631 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14632 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14633 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14634 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14635 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14636 | dev_priv->display.get_initial_plane_config = |
14637 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14638 | dev_priv->display.crtc_compute_clock = |
14639 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14640 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14641 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14642 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14643 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14644 | dev_priv->display.get_initial_plane_config = |
14645 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14646 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14647 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14648 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14649 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14650 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14651 | dev_priv->display.get_initial_plane_config = | |
14652 | i9xx_get_initial_plane_config; | |
14653 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14654 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14655 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14656 | } else if (IS_G4X(dev_priv)) { |
14657 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14658 | dev_priv->display.get_initial_plane_config = | |
14659 | i9xx_get_initial_plane_config; | |
14660 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14661 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14662 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14663 | } else if (IS_PINEVIEW(dev_priv)) { |
14664 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14665 | dev_priv->display.get_initial_plane_config = | |
14666 | i9xx_get_initial_plane_config; | |
14667 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14668 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14669 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14670 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14671 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14672 | dev_priv->display.get_initial_plane_config = |
14673 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14674 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14675 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14676 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14677 | } else { |
14678 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14679 | dev_priv->display.get_initial_plane_config = | |
14680 | i9xx_get_initial_plane_config; | |
14681 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14682 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14683 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14684 | } |
e70236a8 | 14685 | |
88212941 | 14686 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14687 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14688 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14689 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14690 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14691 | /* FIXME: detect B0+ stepping and use auto training */ |
14692 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14693 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14694 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14695 | } |
14696 | ||
27082493 L |
14697 | if (dev_priv->info.gen >= 9) |
14698 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
14699 | else | |
14700 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
14701 | ||
5a21b665 DV |
14702 | switch (INTEL_INFO(dev_priv)->gen) { |
14703 | case 2: | |
14704 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14705 | break; | |
14706 | ||
14707 | case 3: | |
14708 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14709 | break; | |
14710 | ||
14711 | case 4: | |
14712 | case 5: | |
14713 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14714 | break; | |
14715 | ||
14716 | case 6: | |
14717 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14718 | break; | |
14719 | case 7: | |
14720 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
14721 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
14722 | break; | |
14723 | case 9: | |
14724 | /* Drop through - unsupported since execlist only. */ | |
14725 | default: | |
14726 | /* Default just returns -ENODEV to indicate unsupported */ | |
14727 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
14728 | } | |
e70236a8 JB |
14729 | } |
14730 | ||
b690e96c JB |
14731 | /* |
14732 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14733 | * resume, or other times. This quirk makes sure that's the case for | |
14734 | * affected systems. | |
14735 | */ | |
0206e353 | 14736 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 14737 | { |
fac5e23e | 14738 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
14739 | |
14740 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14741 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14742 | } |
14743 | ||
b6b5d049 VS |
14744 | static void quirk_pipeb_force(struct drm_device *dev) |
14745 | { | |
fac5e23e | 14746 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
14747 | |
14748 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14749 | DRM_INFO("applying pipe b force quirk\n"); | |
14750 | } | |
14751 | ||
435793df KP |
14752 | /* |
14753 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14754 | */ | |
14755 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14756 | { | |
fac5e23e | 14757 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 14758 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 14759 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14760 | } |
14761 | ||
4dca20ef | 14762 | /* |
5a15ab5b CE |
14763 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14764 | * brightness value | |
4dca20ef CE |
14765 | */ |
14766 | static void quirk_invert_brightness(struct drm_device *dev) | |
14767 | { | |
fac5e23e | 14768 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 14769 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 14770 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14771 | } |
14772 | ||
9c72cc6f SD |
14773 | /* Some VBT's incorrectly indicate no backlight is present */ |
14774 | static void quirk_backlight_present(struct drm_device *dev) | |
14775 | { | |
fac5e23e | 14776 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
14777 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
14778 | DRM_INFO("applying backlight present quirk\n"); | |
14779 | } | |
14780 | ||
b690e96c JB |
14781 | struct intel_quirk { |
14782 | int device; | |
14783 | int subsystem_vendor; | |
14784 | int subsystem_device; | |
14785 | void (*hook)(struct drm_device *dev); | |
14786 | }; | |
14787 | ||
5f85f176 EE |
14788 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14789 | struct intel_dmi_quirk { | |
14790 | void (*hook)(struct drm_device *dev); | |
14791 | const struct dmi_system_id (*dmi_id_list)[]; | |
14792 | }; | |
14793 | ||
14794 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14795 | { | |
14796 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14797 | return 1; | |
14798 | } | |
14799 | ||
14800 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14801 | { | |
14802 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14803 | { | |
14804 | .callback = intel_dmi_reverse_brightness, | |
14805 | .ident = "NCR Corporation", | |
14806 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14807 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14808 | }, | |
14809 | }, | |
14810 | { } /* terminating entry */ | |
14811 | }, | |
14812 | .hook = quirk_invert_brightness, | |
14813 | }, | |
14814 | }; | |
14815 | ||
c43b5634 | 14816 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14817 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14818 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14819 | ||
b690e96c JB |
14820 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14821 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14822 | ||
5f080c0f VS |
14823 | /* 830 needs to leave pipe A & dpll A up */ |
14824 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14825 | ||
b6b5d049 VS |
14826 | /* 830 needs to leave pipe B & dpll B up */ |
14827 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14828 | ||
435793df KP |
14829 | /* Lenovo U160 cannot use SSC on LVDS */ |
14830 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14831 | |
14832 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14833 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14834 | |
be505f64 AH |
14835 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14836 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14837 | ||
14838 | /* Acer/eMachines G725 */ | |
14839 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14840 | ||
14841 | /* Acer/eMachines e725 */ | |
14842 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14843 | ||
14844 | /* Acer/Packard Bell NCL20 */ | |
14845 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14846 | ||
14847 | /* Acer Aspire 4736Z */ | |
14848 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14849 | |
14850 | /* Acer Aspire 5336 */ | |
14851 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14852 | |
14853 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14854 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14855 | |
dfb3d47b SD |
14856 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14857 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14858 | ||
b2a9601c | 14859 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14860 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14861 | ||
1b9448b0 JN |
14862 | /* Apple Macbook 4,1 */ |
14863 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
14864 | ||
d4967d8c SD |
14865 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14866 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14867 | |
14868 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14869 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14870 | |
14871 | /* Dell Chromebook 11 */ | |
14872 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
14873 | |
14874 | /* Dell Chromebook 11 (2015 version) */ | |
14875 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14876 | }; |
14877 | ||
14878 | static void intel_init_quirks(struct drm_device *dev) | |
14879 | { | |
14880 | struct pci_dev *d = dev->pdev; | |
14881 | int i; | |
14882 | ||
14883 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14884 | struct intel_quirk *q = &intel_quirks[i]; | |
14885 | ||
14886 | if (d->device == q->device && | |
14887 | (d->subsystem_vendor == q->subsystem_vendor || | |
14888 | q->subsystem_vendor == PCI_ANY_ID) && | |
14889 | (d->subsystem_device == q->subsystem_device || | |
14890 | q->subsystem_device == PCI_ANY_ID)) | |
14891 | q->hook(dev); | |
14892 | } | |
5f85f176 EE |
14893 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14894 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14895 | intel_dmi_quirks[i].hook(dev); | |
14896 | } | |
b690e96c JB |
14897 | } |
14898 | ||
9cce37f4 | 14899 | /* Disable the VGA plane that we never use */ |
29b74b7f | 14900 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 14901 | { |
52a05c30 | 14902 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 14903 | u8 sr1; |
920a14b2 | 14904 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 14905 | |
2b37c616 | 14906 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 14907 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14908 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14909 | sr1 = inb(VGA_SR_DATA); |
14910 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 14911 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
14912 | udelay(300); |
14913 | ||
01f5a626 | 14914 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14915 | POSTING_READ(vga_reg); |
14916 | } | |
14917 | ||
f817586c DV |
14918 | void intel_modeset_init_hw(struct drm_device *dev) |
14919 | { | |
fac5e23e | 14920 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 14921 | |
4c75b940 | 14922 | intel_update_cdclk(dev_priv); |
bb0f4aab | 14923 | dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; |
1a617b77 | 14924 | |
46f16e63 | 14925 | intel_init_clock_gating(dev_priv); |
f817586c DV |
14926 | } |
14927 | ||
d93c0372 MR |
14928 | /* |
14929 | * Calculate what we think the watermarks should be for the state we've read | |
14930 | * out of the hardware and then immediately program those watermarks so that | |
14931 | * we ensure the hardware settings match our internal state. | |
14932 | * | |
14933 | * We can calculate what we think WM's should be by creating a duplicate of the | |
14934 | * current state (which was constructed during hardware readout) and running it | |
14935 | * through the atomic check code to calculate new watermark values in the | |
14936 | * state object. | |
14937 | */ | |
14938 | static void sanitize_watermarks(struct drm_device *dev) | |
14939 | { | |
14940 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14941 | struct drm_atomic_state *state; | |
ccf010fb | 14942 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
14943 | struct drm_crtc *crtc; |
14944 | struct drm_crtc_state *cstate; | |
14945 | struct drm_modeset_acquire_ctx ctx; | |
14946 | int ret; | |
14947 | int i; | |
14948 | ||
14949 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 14950 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
14951 | return; |
14952 | ||
14953 | /* | |
14954 | * We need to hold connection_mutex before calling duplicate_state so | |
14955 | * that the connector loop is protected. | |
14956 | */ | |
14957 | drm_modeset_acquire_init(&ctx, 0); | |
14958 | retry: | |
0cd1262d | 14959 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
14960 | if (ret == -EDEADLK) { |
14961 | drm_modeset_backoff(&ctx); | |
14962 | goto retry; | |
14963 | } else if (WARN_ON(ret)) { | |
0cd1262d | 14964 | goto fail; |
d93c0372 MR |
14965 | } |
14966 | ||
14967 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
14968 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 14969 | goto fail; |
d93c0372 | 14970 | |
ccf010fb ML |
14971 | intel_state = to_intel_atomic_state(state); |
14972 | ||
ed4a6a7c MR |
14973 | /* |
14974 | * Hardware readout is the only time we don't want to calculate | |
14975 | * intermediate watermarks (since we don't trust the current | |
14976 | * watermarks). | |
14977 | */ | |
602ae835 VS |
14978 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14979 | intel_state->skip_intermediate_wm = true; | |
ed4a6a7c | 14980 | |
d93c0372 MR |
14981 | ret = intel_atomic_check(dev, state); |
14982 | if (ret) { | |
14983 | /* | |
14984 | * If we fail here, it means that the hardware appears to be | |
14985 | * programmed in a way that shouldn't be possible, given our | |
14986 | * understanding of watermark requirements. This might mean a | |
14987 | * mistake in the hardware readout code or a mistake in the | |
14988 | * watermark calculations for a given platform. Raise a WARN | |
14989 | * so that this is noticeable. | |
14990 | * | |
14991 | * If this actually happens, we'll have to just leave the | |
14992 | * BIOS-programmed watermarks untouched and hope for the best. | |
14993 | */ | |
14994 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 14995 | goto put_state; |
d93c0372 MR |
14996 | } |
14997 | ||
14998 | /* Write calculated watermark values back */ | |
aa5e9b47 | 14999 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
d93c0372 MR |
15000 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); |
15001 | ||
ed4a6a7c | 15002 | cs->wm.need_postvbl_update = true; |
ccf010fb | 15003 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
15004 | } |
15005 | ||
b9a1b717 | 15006 | put_state: |
0853695c | 15007 | drm_atomic_state_put(state); |
0cd1262d | 15008 | fail: |
d93c0372 MR |
15009 | drm_modeset_drop_locks(&ctx); |
15010 | drm_modeset_acquire_fini(&ctx); | |
15011 | } | |
15012 | ||
b079bd17 | 15013 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 15014 | { |
72e96d64 JL |
15015 | struct drm_i915_private *dev_priv = to_i915(dev); |
15016 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 15017 | enum pipe pipe; |
46f297fb | 15018 | struct intel_crtc *crtc; |
79e53945 JB |
15019 | |
15020 | drm_mode_config_init(dev); | |
15021 | ||
15022 | dev->mode_config.min_width = 0; | |
15023 | dev->mode_config.min_height = 0; | |
15024 | ||
019d96cb DA |
15025 | dev->mode_config.preferred_depth = 24; |
15026 | dev->mode_config.prefer_shadow = 1; | |
15027 | ||
25bab385 TU |
15028 | dev->mode_config.allow_fb_modifiers = true; |
15029 | ||
e6ecefaa | 15030 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15031 | |
400c19d9 | 15032 | init_llist_head(&dev_priv->atomic_helper.free_list); |
eb955eee | 15033 | INIT_WORK(&dev_priv->atomic_helper.free_work, |
ba318c61 | 15034 | intel_atomic_helper_free_state_worker); |
eb955eee | 15035 | |
b690e96c JB |
15036 | intel_init_quirks(dev); |
15037 | ||
62d75df7 | 15038 | intel_init_pm(dev_priv); |
1fa61106 | 15039 | |
b7f05d4a | 15040 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 15041 | return 0; |
e3c74757 | 15042 | |
69f92f67 LW |
15043 | /* |
15044 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15045 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15046 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15047 | * indicates as much. | |
15048 | */ | |
6e266956 | 15049 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
15050 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
15051 | DREF_SSC1_ENABLE); | |
15052 | ||
15053 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15054 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15055 | bios_lvds_use_ssc ? "en" : "dis", | |
15056 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15057 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15058 | } | |
15059 | } | |
15060 | ||
5db94019 | 15061 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
15062 | dev->mode_config.max_width = 2048; |
15063 | dev->mode_config.max_height = 2048; | |
5db94019 | 15064 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
15065 | dev->mode_config.max_width = 4096; |
15066 | dev->mode_config.max_height = 4096; | |
79e53945 | 15067 | } else { |
a6c45cf0 CW |
15068 | dev->mode_config.max_width = 8192; |
15069 | dev->mode_config.max_height = 8192; | |
79e53945 | 15070 | } |
068be561 | 15071 | |
2a307c2e JN |
15072 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
15073 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 15074 | dev->mode_config.cursor_height = 1023; |
5db94019 | 15075 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
15076 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15077 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15078 | } else { | |
15079 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15080 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15081 | } | |
15082 | ||
72e96d64 | 15083 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 15084 | |
28c97730 | 15085 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
15086 | INTEL_INFO(dev_priv)->num_pipes, |
15087 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15088 | |
055e393f | 15089 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
15090 | int ret; |
15091 | ||
5ab0d85b | 15092 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
15093 | if (ret) { |
15094 | drm_mode_config_cleanup(dev); | |
15095 | return ret; | |
15096 | } | |
79e53945 JB |
15097 | } |
15098 | ||
e72f9fbf | 15099 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15100 | |
5be6e334 VS |
15101 | intel_update_czclk(dev_priv); |
15102 | intel_modeset_init_hw(dev); | |
15103 | ||
b2045352 | 15104 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 15105 | intel_update_max_cdclk(dev_priv); |
b2045352 | 15106 | |
9cce37f4 | 15107 | /* Just disable it once at startup */ |
29b74b7f | 15108 | i915_disable_vga(dev_priv); |
c39055b0 | 15109 | intel_setup_outputs(dev_priv); |
11be49eb | 15110 | |
6e9f798d | 15111 | drm_modeset_lock_all(dev); |
043e9bda | 15112 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15113 | drm_modeset_unlock_all(dev); |
46f297fb | 15114 | |
d3fcc808 | 15115 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15116 | struct intel_initial_plane_config plane_config = {}; |
15117 | ||
46f297fb JB |
15118 | if (!crtc->active) |
15119 | continue; | |
15120 | ||
46f297fb | 15121 | /* |
46f297fb JB |
15122 | * Note that reserving the BIOS fb up front prevents us |
15123 | * from stuffing other stolen allocations like the ring | |
15124 | * on top. This prevents some ugliness at boot time, and | |
15125 | * can even allow for smooth boot transitions if the BIOS | |
15126 | * fb is large enough for the active pipe configuration. | |
15127 | */ | |
eeebeac5 ML |
15128 | dev_priv->display.get_initial_plane_config(crtc, |
15129 | &plane_config); | |
15130 | ||
15131 | /* | |
15132 | * If the fb is shared between multiple heads, we'll | |
15133 | * just get the first one. | |
15134 | */ | |
15135 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15136 | } |
d93c0372 MR |
15137 | |
15138 | /* | |
15139 | * Make sure hardware watermarks really match the state we read out. | |
15140 | * Note that we need to do this after reconstructing the BIOS fb's | |
15141 | * since the watermark calculation done here will use pstate->fb. | |
15142 | */ | |
602ae835 VS |
15143 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
15144 | sanitize_watermarks(dev); | |
b079bd17 VS |
15145 | |
15146 | return 0; | |
2c7111db CW |
15147 | } |
15148 | ||
7fad798e DV |
15149 | static void intel_enable_pipe_a(struct drm_device *dev) |
15150 | { | |
15151 | struct intel_connector *connector; | |
f9e905ca | 15152 | struct drm_connector_list_iter conn_iter; |
7fad798e DV |
15153 | struct drm_connector *crt = NULL; |
15154 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15155 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
6c5ed5ae | 15156 | int ret; |
7fad798e DV |
15157 | |
15158 | /* We can't just switch on the pipe A, we need to set things up with a | |
15159 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15160 | * by enabling the load detect pipe once. */ | |
f9e905ca DV |
15161 | drm_connector_list_iter_begin(dev, &conn_iter); |
15162 | for_each_intel_connector_iter(connector, &conn_iter) { | |
7fad798e DV |
15163 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15164 | crt = &connector->base; | |
15165 | break; | |
15166 | } | |
15167 | } | |
f9e905ca | 15168 | drm_connector_list_iter_end(&conn_iter); |
7fad798e DV |
15169 | |
15170 | if (!crt) | |
15171 | return; | |
15172 | ||
6c5ed5ae ML |
15173 | ret = intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx); |
15174 | WARN(ret < 0, "All modeset mutexes are locked, but intel_get_load_detect_pipe failed\n"); | |
15175 | ||
15176 | if (ret > 0) | |
49172fee | 15177 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15178 | } |
15179 | ||
fa555837 DV |
15180 | static bool |
15181 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15182 | { | |
b7f05d4a | 15183 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 15184 | u32 val; |
fa555837 | 15185 | |
b7f05d4a | 15186 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
15187 | return true; |
15188 | ||
649636ef | 15189 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15190 | |
15191 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15192 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15193 | return false; | |
15194 | ||
15195 | return true; | |
15196 | } | |
15197 | ||
02e93c35 VS |
15198 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15199 | { | |
15200 | struct drm_device *dev = crtc->base.dev; | |
15201 | struct intel_encoder *encoder; | |
15202 | ||
15203 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15204 | return true; | |
15205 | ||
15206 | return false; | |
15207 | } | |
15208 | ||
496b0fc3 ML |
15209 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
15210 | { | |
15211 | struct drm_device *dev = encoder->base.dev; | |
15212 | struct intel_connector *connector; | |
15213 | ||
15214 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15215 | return connector; | |
15216 | ||
15217 | return NULL; | |
15218 | } | |
15219 | ||
a168f5b3 VS |
15220 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
15221 | enum transcoder pch_transcoder) | |
15222 | { | |
15223 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
15224 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
15225 | } | |
15226 | ||
24929352 DV |
15227 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15228 | { | |
15229 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 15230 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 15231 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15232 | |
24929352 | 15233 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15234 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15235 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15236 | ||
15237 | I915_WRITE(reg, | |
15238 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15239 | } | |
24929352 | 15240 | |
d3eaf884 | 15241 | /* restore vblank interrupts to correct state */ |
9625604c | 15242 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15243 | if (crtc->active) { |
f9cd7b88 VS |
15244 | struct intel_plane *plane; |
15245 | ||
9625604c | 15246 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15247 | |
15248 | /* Disable everything but the primary plane */ | |
15249 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15250 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15251 | continue; | |
15252 | ||
72259536 | 15253 | trace_intel_disable_plane(&plane->base, crtc); |
282dbf9b | 15254 | plane->disable_plane(plane, crtc); |
f9cd7b88 | 15255 | } |
9625604c | 15256 | } |
d3eaf884 | 15257 | |
24929352 | 15258 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15259 | * disable the crtc (and hence change the state) if it is wrong. Note |
15260 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 15261 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
15262 | bool plane; |
15263 | ||
78108b7c VS |
15264 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
15265 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
15266 | |
15267 | /* Pipe has the wrong plane attached and the plane is active. | |
15268 | * Temporarily change the plane mapping and disable everything | |
15269 | * ... */ | |
15270 | plane = crtc->plane; | |
1d4258db | 15271 | crtc->base.primary->state->visible = true; |
24929352 | 15272 | crtc->plane = !plane; |
b17d48e2 | 15273 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15274 | crtc->plane = plane; |
24929352 | 15275 | } |
24929352 | 15276 | |
7fad798e DV |
15277 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15278 | crtc->pipe == PIPE_A && !crtc->active) { | |
15279 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15280 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15281 | * call below we restore the pipe to the right state, but leave | |
15282 | * the required bits on. */ | |
15283 | intel_enable_pipe_a(dev); | |
15284 | } | |
15285 | ||
24929352 DV |
15286 | /* Adjust the state of the output pipe according to whether we |
15287 | * have active connectors/encoders. */ | |
842e0307 | 15288 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15289 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15290 | |
49cff963 | 15291 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
15292 | /* |
15293 | * We start out with underrun reporting disabled to avoid races. | |
15294 | * For correct bookkeeping mark this on active crtcs. | |
15295 | * | |
c5ab3bc0 DV |
15296 | * Also on gmch platforms we dont have any hardware bits to |
15297 | * disable the underrun reporting. Which means we need to start | |
15298 | * out with underrun reporting disabled also on inactive pipes, | |
15299 | * since otherwise we'll complain about the garbage we read when | |
15300 | * e.g. coming up after runtime pm. | |
15301 | * | |
4cc31489 DV |
15302 | * No protection against concurrent access is required - at |
15303 | * worst a fifo underrun happens which also sets this to false. | |
15304 | */ | |
15305 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
15306 | /* |
15307 | * We track the PCH trancoder underrun reporting state | |
15308 | * within the crtc. With crtc for pipe A housing the underrun | |
15309 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
15310 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
15311 | * and marking underrun reporting as disabled for the non-existing | |
15312 | * PCH transcoders B and C would prevent enabling the south | |
15313 | * error interrupt (see cpt_can_enable_serr_int()). | |
15314 | */ | |
15315 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
15316 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 15317 | } |
24929352 DV |
15318 | } |
15319 | ||
15320 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15321 | { | |
15322 | struct intel_connector *connector; | |
24929352 DV |
15323 | |
15324 | /* We need to check both for a crtc link (meaning that the | |
15325 | * encoder is active and trying to read from a pipe) and the | |
15326 | * pipe itself being active. */ | |
15327 | bool has_active_crtc = encoder->base.crtc && | |
15328 | to_intel_crtc(encoder->base.crtc)->active; | |
15329 | ||
496b0fc3 ML |
15330 | connector = intel_encoder_find_connector(encoder); |
15331 | if (connector && !has_active_crtc) { | |
24929352 DV |
15332 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15333 | encoder->base.base.id, | |
8e329a03 | 15334 | encoder->base.name); |
24929352 DV |
15335 | |
15336 | /* Connector is active, but has no active pipe. This is | |
15337 | * fallout from our resume register restoring. Disable | |
15338 | * the encoder manually again. */ | |
15339 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
15340 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
15341 | ||
24929352 DV |
15342 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
15343 | encoder->base.base.id, | |
8e329a03 | 15344 | encoder->base.name); |
fd6bbda9 | 15345 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 15346 | if (encoder->post_disable) |
fd6bbda9 | 15347 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 15348 | } |
7f1950fb | 15349 | encoder->base.crtc = NULL; |
24929352 DV |
15350 | |
15351 | /* Inconsistent output/port/pipe state happens presumably due to | |
15352 | * a bug in one of the get_hw_state functions. Or someplace else | |
15353 | * in our code, like the register restore mess on resume. Clamp | |
15354 | * things to off as a safer default. */ | |
fd6bbda9 ML |
15355 | |
15356 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15357 | connector->base.encoder = NULL; | |
24929352 DV |
15358 | } |
15359 | /* Enabled encoders without active connectors will be fixed in | |
15360 | * the crtc fixup. */ | |
15361 | } | |
15362 | ||
29b74b7f | 15363 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 15364 | { |
920a14b2 | 15365 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 15366 | |
04098753 ID |
15367 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15368 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 15369 | i915_disable_vga(dev_priv); |
04098753 ID |
15370 | } |
15371 | } | |
15372 | ||
29b74b7f | 15373 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 15374 | { |
8dc8a27c PZ |
15375 | /* This function can be called both from intel_modeset_setup_hw_state or |
15376 | * at a very early point in our resume sequence, where the power well | |
15377 | * structures are not yet restored. Since this function is at a very | |
15378 | * paranoid "someone might have enabled VGA while we were not looking" | |
15379 | * level, just check if the power well is enabled instead of trying to | |
15380 | * follow the "don't touch the power well if we don't need it" policy | |
15381 | * the rest of the driver uses. */ | |
6392f847 | 15382 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15383 | return; |
15384 | ||
29b74b7f | 15385 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
15386 | |
15387 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15388 | } |
15389 | ||
f9cd7b88 | 15390 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15391 | { |
f9cd7b88 | 15392 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15393 | |
f9cd7b88 | 15394 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15395 | } |
15396 | ||
f9cd7b88 VS |
15397 | /* FIXME read out full plane state for all planes */ |
15398 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15399 | { |
e9728bd8 VS |
15400 | struct intel_plane *primary = to_intel_plane(crtc->base.primary); |
15401 | bool visible; | |
d032ffa0 | 15402 | |
e9728bd8 | 15403 | visible = crtc->active && primary_get_hw_state(primary); |
b26d3ea3 | 15404 | |
e9728bd8 VS |
15405 | intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), |
15406 | to_intel_plane_state(primary->base.state), | |
15407 | visible); | |
98ec7739 VS |
15408 | } |
15409 | ||
30e984df | 15410 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 15411 | { |
fac5e23e | 15412 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 15413 | enum pipe pipe; |
24929352 DV |
15414 | struct intel_crtc *crtc; |
15415 | struct intel_encoder *encoder; | |
15416 | struct intel_connector *connector; | |
f9e905ca | 15417 | struct drm_connector_list_iter conn_iter; |
5358901f | 15418 | int i; |
24929352 | 15419 | |
565602d7 ML |
15420 | dev_priv->active_crtcs = 0; |
15421 | ||
d3fcc808 | 15422 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
15423 | struct intel_crtc_state *crtc_state = |
15424 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 15425 | |
ec2dc6a0 | 15426 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
15427 | memset(crtc_state, 0, sizeof(*crtc_state)); |
15428 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15429 | |
565602d7 ML |
15430 | crtc_state->base.active = crtc_state->base.enable = |
15431 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15432 | ||
15433 | crtc->base.enabled = crtc_state->base.enable; | |
15434 | crtc->active = crtc_state->base.active; | |
15435 | ||
aca1ebf4 | 15436 | if (crtc_state->base.active) |
565602d7 ML |
15437 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
15438 | ||
f9cd7b88 | 15439 | readout_plane_state(crtc); |
24929352 | 15440 | |
78108b7c VS |
15441 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
15442 | crtc->base.base.id, crtc->base.name, | |
a8cd6da0 | 15443 | enableddisabled(crtc_state->base.active)); |
24929352 DV |
15444 | } |
15445 | ||
5358901f DV |
15446 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15447 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15448 | ||
2edd6443 | 15449 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
2c42e535 ACO |
15450 | &pll->state.hw_state); |
15451 | pll->state.crtc_mask = 0; | |
d3fcc808 | 15452 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
15453 | struct intel_crtc_state *crtc_state = |
15454 | to_intel_crtc_state(crtc->base.state); | |
15455 | ||
15456 | if (crtc_state->base.active && | |
15457 | crtc_state->shared_dpll == pll) | |
2c42e535 | 15458 | pll->state.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15459 | } |
2c42e535 | 15460 | pll->active_mask = pll->state.crtc_mask; |
5358901f | 15461 | |
1e6f2ddc | 15462 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
2c42e535 | 15463 | pll->name, pll->state.crtc_mask, pll->on); |
5358901f DV |
15464 | } |
15465 | ||
b2784e15 | 15466 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15467 | pipe = 0; |
15468 | ||
15469 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
15470 | struct intel_crtc_state *crtc_state; |
15471 | ||
98187836 | 15472 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 15473 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 15474 | |
045ac3b5 | 15475 | encoder->base.crtc = &crtc->base; |
a8cd6da0 VS |
15476 | crtc_state->output_types |= 1 << encoder->type; |
15477 | encoder->get_config(encoder, crtc_state); | |
24929352 DV |
15478 | } else { |
15479 | encoder->base.crtc = NULL; | |
15480 | } | |
15481 | ||
6f2bcceb | 15482 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
15483 | encoder->base.base.id, encoder->base.name, |
15484 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 15485 | pipe_name(pipe)); |
24929352 DV |
15486 | } |
15487 | ||
f9e905ca DV |
15488 | drm_connector_list_iter_begin(dev, &conn_iter); |
15489 | for_each_intel_connector_iter(connector, &conn_iter) { | |
24929352 DV |
15490 | if (connector->get_hw_state(connector)) { |
15491 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15492 | |
15493 | encoder = connector->encoder; | |
15494 | connector->base.encoder = &encoder->base; | |
15495 | ||
15496 | if (encoder->base.crtc && | |
15497 | encoder->base.crtc->state->active) { | |
15498 | /* | |
15499 | * This has to be done during hardware readout | |
15500 | * because anything calling .crtc_disable may | |
15501 | * rely on the connector_mask being accurate. | |
15502 | */ | |
15503 | encoder->base.crtc->state->connector_mask |= | |
15504 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15505 | encoder->base.crtc->state->encoder_mask |= |
15506 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15507 | } |
15508 | ||
24929352 DV |
15509 | } else { |
15510 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15511 | connector->base.encoder = NULL; | |
15512 | } | |
15513 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
15514 | connector->base.base.id, connector->base.name, |
15515 | enableddisabled(connector->base.encoder)); | |
24929352 | 15516 | } |
f9e905ca | 15517 | drm_connector_list_iter_end(&conn_iter); |
7f4c6284 VS |
15518 | |
15519 | for_each_intel_crtc(dev, crtc) { | |
a8cd6da0 VS |
15520 | struct intel_crtc_state *crtc_state = |
15521 | to_intel_crtc_state(crtc->base.state); | |
aca1ebf4 VS |
15522 | int pixclk = 0; |
15523 | ||
7f4c6284 | 15524 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
a8cd6da0 VS |
15525 | if (crtc_state->base.active) { |
15526 | intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); | |
15527 | intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); | |
7f4c6284 VS |
15528 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
15529 | ||
15530 | /* | |
15531 | * The initial mode needs to be set in order to keep | |
15532 | * the atomic core happy. It wants a valid mode if the | |
15533 | * crtc's enabled, so we do the above call. | |
15534 | * | |
7800fb69 DV |
15535 | * But we don't set all the derived state fully, hence |
15536 | * set a flag to indicate that a full recalculation is | |
15537 | * needed on the next commit. | |
7f4c6284 | 15538 | */ |
a8cd6da0 | 15539 | crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; |
9eca6832 | 15540 | |
a7d1b3f4 VS |
15541 | intel_crtc_compute_pixel_rate(crtc_state); |
15542 | ||
15543 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || | |
15544 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15545 | pixclk = crtc_state->pixel_rate; | |
aca1ebf4 VS |
15546 | else |
15547 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15548 | ||
15549 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
a8cd6da0 | 15550 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
aca1ebf4 VS |
15551 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
15552 | ||
5caa0fea DV |
15553 | drm_calc_timestamping_constants(&crtc->base, |
15554 | &crtc_state->base.adjusted_mode); | |
9eca6832 | 15555 | update_scanline_offset(crtc); |
7f4c6284 | 15556 | } |
e3b247da | 15557 | |
aca1ebf4 VS |
15558 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
15559 | ||
a8cd6da0 | 15560 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 15561 | } |
30e984df DV |
15562 | } |
15563 | ||
62b69566 ACO |
15564 | static void |
15565 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
15566 | { | |
15567 | struct intel_encoder *encoder; | |
15568 | ||
15569 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
15570 | u64 get_domains; | |
15571 | enum intel_display_power_domain domain; | |
15572 | ||
15573 | if (!encoder->get_power_domains) | |
15574 | continue; | |
15575 | ||
15576 | get_domains = encoder->get_power_domains(encoder); | |
15577 | for_each_power_domain(domain, get_domains) | |
15578 | intel_display_power_get(dev_priv, domain); | |
15579 | } | |
15580 | } | |
15581 | ||
043e9bda ML |
15582 | /* Scan out the current hw modeset state, |
15583 | * and sanitizes it to the current state | |
15584 | */ | |
15585 | static void | |
15586 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 15587 | { |
fac5e23e | 15588 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 15589 | enum pipe pipe; |
30e984df DV |
15590 | struct intel_crtc *crtc; |
15591 | struct intel_encoder *encoder; | |
35c95375 | 15592 | int i; |
30e984df DV |
15593 | |
15594 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15595 | |
15596 | /* HW state is read out, now we need to sanitize this mess. */ | |
62b69566 ACO |
15597 | get_encoder_power_domains(dev_priv); |
15598 | ||
b2784e15 | 15599 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15600 | intel_sanitize_encoder(encoder); |
15601 | } | |
15602 | ||
055e393f | 15603 | for_each_pipe(dev_priv, pipe) { |
98187836 | 15604 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 15605 | |
24929352 | 15606 | intel_sanitize_crtc(crtc); |
6e3c9717 ACO |
15607 | intel_dump_pipe_config(crtc, crtc->config, |
15608 | "[setup_hw_state]"); | |
24929352 | 15609 | } |
9a935856 | 15610 | |
d29b2f9d ACO |
15611 | intel_modeset_update_connector_atomic_state(dev); |
15612 | ||
35c95375 DV |
15613 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15614 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15615 | ||
2dd66ebd | 15616 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15617 | continue; |
15618 | ||
15619 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15620 | ||
2edd6443 | 15621 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15622 | pll->on = false; |
15623 | } | |
15624 | ||
04548cba VS |
15625 | if (IS_G4X(dev_priv)) { |
15626 | g4x_wm_get_hw_state(dev); | |
15627 | g4x_wm_sanitize(dev_priv); | |
15628 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
6eb1a681 | 15629 | vlv_wm_get_hw_state(dev); |
602ae835 VS |
15630 | vlv_wm_sanitize(dev_priv); |
15631 | } else if (IS_GEN9(dev_priv)) { | |
3078999f | 15632 | skl_wm_get_hw_state(dev); |
602ae835 | 15633 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
243e6a44 | 15634 | ilk_wm_get_hw_state(dev); |
602ae835 | 15635 | } |
292b990e ML |
15636 | |
15637 | for_each_intel_crtc(dev, crtc) { | |
d8fc70b7 | 15638 | u64 put_domains; |
292b990e | 15639 | |
74bff5f9 | 15640 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15641 | if (WARN_ON(put_domains)) |
15642 | modeset_put_power_domains(dev_priv, put_domains); | |
15643 | } | |
15644 | intel_display_set_init_power(dev_priv, false); | |
010cf73d | 15645 | |
8d8c386c ID |
15646 | intel_power_domains_verify_state(dev_priv); |
15647 | ||
010cf73d | 15648 | intel_fbc_init_pipe_state(dev_priv); |
043e9bda | 15649 | } |
7d0bc1ea | 15650 | |
043e9bda ML |
15651 | void intel_display_resume(struct drm_device *dev) |
15652 | { | |
e2c8b870 ML |
15653 | struct drm_i915_private *dev_priv = to_i915(dev); |
15654 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15655 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15656 | int ret; |
f30da187 | 15657 | |
e2c8b870 | 15658 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
15659 | if (state) |
15660 | state->acquire_ctx = &ctx; | |
043e9bda | 15661 | |
e2c8b870 | 15662 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15663 | |
73974893 ML |
15664 | while (1) { |
15665 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
15666 | if (ret != -EDEADLK) | |
15667 | break; | |
043e9bda | 15668 | |
e2c8b870 | 15669 | drm_modeset_backoff(&ctx); |
e2c8b870 | 15670 | } |
043e9bda | 15671 | |
73974893 | 15672 | if (!ret) |
581e49fe | 15673 | ret = __intel_display_resume(dev, state, &ctx); |
73974893 | 15674 | |
e2c8b870 ML |
15675 | drm_modeset_drop_locks(&ctx); |
15676 | drm_modeset_acquire_fini(&ctx); | |
043e9bda | 15677 | |
0853695c | 15678 | if (ret) |
e2c8b870 | 15679 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
3c5e37f1 CW |
15680 | if (state) |
15681 | drm_atomic_state_put(state); | |
2c7111db CW |
15682 | } |
15683 | ||
15684 | void intel_modeset_gem_init(struct drm_device *dev) | |
15685 | { | |
dc97997a | 15686 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15687 | |
dc97997a | 15688 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15689 | |
1ee8da6d | 15690 | intel_setup_overlay(dev_priv); |
1ebaa0b9 CW |
15691 | } |
15692 | ||
15693 | int intel_connector_register(struct drm_connector *connector) | |
15694 | { | |
15695 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
15696 | int ret; | |
15697 | ||
15698 | ret = intel_backlight_device_register(intel_connector); | |
15699 | if (ret) | |
15700 | goto err; | |
15701 | ||
15702 | return 0; | |
0962c3c9 | 15703 | |
1ebaa0b9 CW |
15704 | err: |
15705 | return ret; | |
79e53945 JB |
15706 | } |
15707 | ||
c191eca1 | 15708 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 15709 | { |
e63d87c0 | 15710 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 15711 | |
e63d87c0 | 15712 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 15713 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
15714 | } |
15715 | ||
79e53945 JB |
15716 | void intel_modeset_cleanup(struct drm_device *dev) |
15717 | { | |
fac5e23e | 15718 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 15719 | |
eb955eee CW |
15720 | flush_work(&dev_priv->atomic_helper.free_work); |
15721 | WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); | |
15722 | ||
dc97997a | 15723 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 15724 | |
fd0c0642 DV |
15725 | /* |
15726 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15727 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15728 | * experience fancy races otherwise. |
15729 | */ | |
2aeb7d3a | 15730 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15731 | |
fd0c0642 DV |
15732 | /* |
15733 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15734 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15735 | */ | |
f87ea761 | 15736 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15737 | |
723bfd70 JB |
15738 | intel_unregister_dsm_handler(); |
15739 | ||
c937ab3e | 15740 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15741 | |
1630fe75 CW |
15742 | /* flush any delayed tasks or pending work */ |
15743 | flush_scheduled_work(); | |
15744 | ||
79e53945 | 15745 | drm_mode_config_cleanup(dev); |
4d7bb011 | 15746 | |
1ee8da6d | 15747 | intel_cleanup_overlay(dev_priv); |
ae48434c | 15748 | |
dc97997a | 15749 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 15750 | |
40196446 | 15751 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
15752 | } |
15753 | ||
df0e9248 CW |
15754 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15755 | struct intel_encoder *encoder) | |
15756 | { | |
15757 | connector->encoder = encoder; | |
15758 | drm_mode_connector_attach_encoder(&connector->base, | |
15759 | &encoder->base); | |
79e53945 | 15760 | } |
28d52043 DA |
15761 | |
15762 | /* | |
15763 | * set vga decode state - true == enable VGA decode | |
15764 | */ | |
6315b5d3 | 15765 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 15766 | { |
6315b5d3 | 15767 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15768 | u16 gmch_ctrl; |
15769 | ||
75fa041d CW |
15770 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15771 | DRM_ERROR("failed to read control word\n"); | |
15772 | return -EIO; | |
15773 | } | |
15774 | ||
c0cc8a55 CW |
15775 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15776 | return 0; | |
15777 | ||
28d52043 DA |
15778 | if (state) |
15779 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15780 | else | |
15781 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15782 | |
15783 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15784 | DRM_ERROR("failed to write control word\n"); | |
15785 | return -EIO; | |
15786 | } | |
15787 | ||
28d52043 DA |
15788 | return 0; |
15789 | } | |
c4a1d9e4 | 15790 | |
98a2f411 CW |
15791 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
15792 | ||
c4a1d9e4 | 15793 | struct intel_display_error_state { |
ff57f1b0 PZ |
15794 | |
15795 | u32 power_well_driver; | |
15796 | ||
63b66e5b CW |
15797 | int num_transcoders; |
15798 | ||
c4a1d9e4 CW |
15799 | struct intel_cursor_error_state { |
15800 | u32 control; | |
15801 | u32 position; | |
15802 | u32 base; | |
15803 | u32 size; | |
52331309 | 15804 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15805 | |
15806 | struct intel_pipe_error_state { | |
ddf9c536 | 15807 | bool power_domain_on; |
c4a1d9e4 | 15808 | u32 source; |
f301b1e1 | 15809 | u32 stat; |
52331309 | 15810 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15811 | |
15812 | struct intel_plane_error_state { | |
15813 | u32 control; | |
15814 | u32 stride; | |
15815 | u32 size; | |
15816 | u32 pos; | |
15817 | u32 addr; | |
15818 | u32 surface; | |
15819 | u32 tile_offset; | |
52331309 | 15820 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15821 | |
15822 | struct intel_transcoder_error_state { | |
ddf9c536 | 15823 | bool power_domain_on; |
63b66e5b CW |
15824 | enum transcoder cpu_transcoder; |
15825 | ||
15826 | u32 conf; | |
15827 | ||
15828 | u32 htotal; | |
15829 | u32 hblank; | |
15830 | u32 hsync; | |
15831 | u32 vtotal; | |
15832 | u32 vblank; | |
15833 | u32 vsync; | |
15834 | } transcoder[4]; | |
c4a1d9e4 CW |
15835 | }; |
15836 | ||
15837 | struct intel_display_error_state * | |
c033666a | 15838 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 15839 | { |
c4a1d9e4 | 15840 | struct intel_display_error_state *error; |
63b66e5b CW |
15841 | int transcoders[] = { |
15842 | TRANSCODER_A, | |
15843 | TRANSCODER_B, | |
15844 | TRANSCODER_C, | |
15845 | TRANSCODER_EDP, | |
15846 | }; | |
c4a1d9e4 CW |
15847 | int i; |
15848 | ||
c033666a | 15849 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
15850 | return NULL; |
15851 | ||
9d1cb914 | 15852 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15853 | if (error == NULL) |
15854 | return NULL; | |
15855 | ||
c033666a | 15856 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
15857 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15858 | ||
055e393f | 15859 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15860 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15861 | __intel_display_power_is_enabled(dev_priv, |
15862 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15863 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15864 | continue; |
15865 | ||
5efb3e28 VS |
15866 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15867 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15868 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15869 | |
15870 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15871 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 15872 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 15873 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15874 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15875 | } | |
c033666a | 15876 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 15877 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 15878 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
15879 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
15880 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15881 | } | |
15882 | ||
c4a1d9e4 | 15883 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15884 | |
c033666a | 15885 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 15886 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15887 | } |
15888 | ||
4d1de975 | 15889 | /* Note: this does not include DSI transcoders. */ |
c033666a | 15890 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 15891 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
15892 | error->num_transcoders++; /* Account for eDP. */ |
15893 | ||
15894 | for (i = 0; i < error->num_transcoders; i++) { | |
15895 | enum transcoder cpu_transcoder = transcoders[i]; | |
15896 | ||
ddf9c536 | 15897 | error->transcoder[i].power_domain_on = |
f458ebbc | 15898 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15899 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15900 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15901 | continue; |
15902 | ||
63b66e5b CW |
15903 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15904 | ||
15905 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15906 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15907 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15908 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15909 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15910 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15911 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15912 | } |
15913 | ||
15914 | return error; | |
15915 | } | |
15916 | ||
edc3d884 MK |
15917 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15918 | ||
c4a1d9e4 | 15919 | void |
edc3d884 | 15920 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15921 | struct intel_display_error_state *error) |
15922 | { | |
5a4c6f1b | 15923 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
15924 | int i; |
15925 | ||
63b66e5b CW |
15926 | if (!error) |
15927 | return; | |
15928 | ||
b7f05d4a | 15929 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 15930 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 15931 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15932 | error->power_well_driver); |
055e393f | 15933 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15934 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 15935 | err_printf(m, " Power: %s\n", |
87ad3212 | 15936 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 15937 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15938 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15939 | |
15940 | err_printf(m, "Plane [%d]:\n", i); | |
15941 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15942 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 15943 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
15944 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15945 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15946 | } |
772c2a51 | 15947 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 15948 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 15949 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
15950 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15951 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15952 | } |
15953 | ||
edc3d884 MK |
15954 | err_printf(m, "Cursor [%d]:\n", i); |
15955 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15956 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15957 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15958 | } |
63b66e5b CW |
15959 | |
15960 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15961 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15962 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15963 | err_printf(m, " Power: %s\n", |
87ad3212 | 15964 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15965 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15966 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15967 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15968 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15969 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15970 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15971 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15972 | } | |
c4a1d9e4 | 15973 | } |
98a2f411 CW |
15974 | |
15975 | #endif |