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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
c37efb99 | 39 | #include "i915_gem_dmabuf.h" |
db18b6a6 | 40 | #include "intel_dsi.h" |
e5510fac | 41 | #include "i915_trace.h" |
319c1d42 | 42 | #include <drm/drm_atomic.h> |
c196e1d6 | 43 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
44 | #include <drm/drm_dp_helper.h> |
45 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
46 | #include <drm/drm_plane_helper.h> |
47 | #include <drm/drm_rect.h> | |
c0f372b3 | 48 | #include <linux/dma_remapping.h> |
fd8e058a | 49 | #include <linux/reservation.h> |
79e53945 | 50 | |
5a21b665 DV |
51 | static bool is_mmio_work(struct intel_flip_work *work) |
52 | { | |
53 | return work->mmio_work.func; | |
54 | } | |
55 | ||
465c120c | 56 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 57 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
465c120c | 60 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 61 | DRM_FORMAT_XRGB8888, |
465c120c MR |
62 | }; |
63 | ||
64 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 65 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
66 | DRM_FORMAT_C8, |
67 | DRM_FORMAT_RGB565, | |
68 | DRM_FORMAT_XRGB8888, | |
69 | DRM_FORMAT_XBGR8888, | |
70 | DRM_FORMAT_XRGB2101010, | |
71 | DRM_FORMAT_XBGR2101010, | |
72 | }; | |
73 | ||
74 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
75 | DRM_FORMAT_C8, |
76 | DRM_FORMAT_RGB565, | |
77 | DRM_FORMAT_XRGB8888, | |
465c120c | 78 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 79 | DRM_FORMAT_ARGB8888, |
465c120c MR |
80 | DRM_FORMAT_ABGR8888, |
81 | DRM_FORMAT_XRGB2101010, | |
465c120c | 82 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
83 | DRM_FORMAT_YUYV, |
84 | DRM_FORMAT_YVYU, | |
85 | DRM_FORMAT_UYVY, | |
86 | DRM_FORMAT_VYUY, | |
465c120c MR |
87 | }; |
88 | ||
3d7d6510 MR |
89 | /* Cursor formats */ |
90 | static const uint32_t intel_cursor_formats[] = { | |
91 | DRM_FORMAT_ARGB8888, | |
92 | }; | |
93 | ||
f1f644dc | 94 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 95 | struct intel_crtc_state *pipe_config); |
18442d08 | 96 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 97 | struct intel_crtc_state *pipe_config); |
f1f644dc | 98 | |
eb1bfe80 JB |
99 | static int intel_framebuffer_init(struct drm_device *dev, |
100 | struct intel_framebuffer *ifb, | |
101 | struct drm_mode_fb_cmd2 *mode_cmd, | |
102 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
118 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
119 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
120 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
121 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
122 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 123 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 124 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 125 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
324513c0 | 126 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 127 | |
d4906093 | 128 | struct intel_limit { |
4c5def93 ACO |
129 | struct { |
130 | int min, max; | |
131 | } dot, vco, n, m, m1, m2, p, p1; | |
132 | ||
133 | struct { | |
134 | int dot_limit; | |
135 | int p2_slow, p2_fast; | |
136 | } p2; | |
d4906093 | 137 | }; |
79e53945 | 138 | |
bfa7df01 VS |
139 | /* returns HPLL frequency in kHz */ |
140 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
141 | { | |
142 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
143 | ||
144 | /* Obtain SKU information */ | |
145 | mutex_lock(&dev_priv->sb_lock); | |
146 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
147 | CCK_FUSE_HPLL_FREQ_MASK; | |
148 | mutex_unlock(&dev_priv->sb_lock); | |
149 | ||
150 | return vco_freq[hpll_freq] * 1000; | |
151 | } | |
152 | ||
c30fec65 VS |
153 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
154 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
155 | { |
156 | u32 val; | |
157 | int divider; | |
158 | ||
bfa7df01 VS |
159 | mutex_lock(&dev_priv->sb_lock); |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
c30fec65 VS |
169 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
170 | } | |
171 | ||
172 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
173 | const char *name, u32 reg) | |
174 | { | |
175 | if (dev_priv->hpll_freq == 0) | |
176 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
177 | ||
178 | return vlv_get_cck_clock(dev_priv, name, reg, | |
179 | dev_priv->hpll_freq); | |
bfa7df01 VS |
180 | } |
181 | ||
e7dc33f3 VS |
182 | static int |
183 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 184 | { |
e7dc33f3 VS |
185 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
186 | } | |
d2acd215 | 187 | |
e7dc33f3 VS |
188 | static int |
189 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
190 | { | |
19ab4ed3 | 191 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
192 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
193 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
194 | } |
195 | ||
e7dc33f3 VS |
196 | static int |
197 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 198 | { |
79e50a4f JN |
199 | uint32_t clkcfg; |
200 | ||
e7dc33f3 | 201 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
202 | clkcfg = I915_READ(CLKCFG); |
203 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
204 | case CLKCFG_FSB_400: | |
e7dc33f3 | 205 | return 100000; |
79e50a4f | 206 | case CLKCFG_FSB_533: |
e7dc33f3 | 207 | return 133333; |
79e50a4f | 208 | case CLKCFG_FSB_667: |
e7dc33f3 | 209 | return 166667; |
79e50a4f | 210 | case CLKCFG_FSB_800: |
e7dc33f3 | 211 | return 200000; |
79e50a4f | 212 | case CLKCFG_FSB_1067: |
e7dc33f3 | 213 | return 266667; |
79e50a4f | 214 | case CLKCFG_FSB_1333: |
e7dc33f3 | 215 | return 333333; |
79e50a4f JN |
216 | /* these two are just a guess; one of them might be right */ |
217 | case CLKCFG_FSB_1600: | |
218 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 219 | return 400000; |
79e50a4f | 220 | default: |
e7dc33f3 | 221 | return 133333; |
79e50a4f JN |
222 | } |
223 | } | |
224 | ||
19ab4ed3 | 225 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
226 | { |
227 | if (HAS_PCH_SPLIT(dev_priv)) | |
228 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
229 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
230 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
231 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
232 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
233 | else | |
234 | return; /* no rawclk on other platforms, or no need to know it */ | |
235 | ||
236 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
237 | } | |
238 | ||
bfa7df01 VS |
239 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
240 | { | |
666a4537 | 241 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
242 | return; |
243 | ||
244 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
245 | CCK_CZ_CLOCK_CONTROL); | |
246 | ||
247 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
248 | } | |
249 | ||
021357ac | 250 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
251 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
252 | const struct intel_crtc_state *pipe_config) | |
021357ac | 253 | { |
21a727b3 VS |
254 | if (HAS_DDI(dev_priv)) |
255 | return pipe_config->port_clock; /* SPLL */ | |
256 | else if (IS_GEN5(dev_priv)) | |
257 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 258 | else |
21a727b3 | 259 | return 270000; |
021357ac CW |
260 | } |
261 | ||
1b6f4958 | 262 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 263 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 264 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 265 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
266 | .m = { .min = 96, .max = 140 }, |
267 | .m1 = { .min = 18, .max = 26 }, | |
268 | .m2 = { .min = 6, .max = 16 }, | |
269 | .p = { .min = 4, .max = 128 }, | |
270 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
271 | .p2 = { .dot_limit = 165000, |
272 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
273 | }; |
274 | ||
1b6f4958 | 275 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 276 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 277 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 278 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
279 | .m = { .min = 96, .max = 140 }, |
280 | .m1 = { .min = 18, .max = 26 }, | |
281 | .m2 = { .min = 6, .max = 16 }, | |
282 | .p = { .min = 4, .max = 128 }, | |
283 | .p1 = { .min = 2, .max = 33 }, | |
284 | .p2 = { .dot_limit = 165000, | |
285 | .p2_slow = 4, .p2_fast = 4 }, | |
286 | }; | |
287 | ||
1b6f4958 | 288 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 289 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 290 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 291 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
292 | .m = { .min = 96, .max = 140 }, |
293 | .m1 = { .min = 18, .max = 26 }, | |
294 | .m2 = { .min = 6, .max = 16 }, | |
295 | .p = { .min = 4, .max = 128 }, | |
296 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
297 | .p2 = { .dot_limit = 165000, |
298 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 299 | }; |
273e27ca | 300 | |
1b6f4958 | 301 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
302 | .dot = { .min = 20000, .max = 400000 }, |
303 | .vco = { .min = 1400000, .max = 2800000 }, | |
304 | .n = { .min = 1, .max = 6 }, | |
305 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
306 | .m1 = { .min = 8, .max = 18 }, |
307 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
308 | .p = { .min = 5, .max = 80 }, |
309 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
310 | .p2 = { .dot_limit = 200000, |
311 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
312 | }; |
313 | ||
1b6f4958 | 314 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
315 | .dot = { .min = 20000, .max = 400000 }, |
316 | .vco = { .min = 1400000, .max = 2800000 }, | |
317 | .n = { .min = 1, .max = 6 }, | |
318 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
319 | .m1 = { .min = 8, .max = 18 }, |
320 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
321 | .p = { .min = 7, .max = 98 }, |
322 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
323 | .p2 = { .dot_limit = 112000, |
324 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
325 | }; |
326 | ||
273e27ca | 327 | |
1b6f4958 | 328 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
329 | .dot = { .min = 25000, .max = 270000 }, |
330 | .vco = { .min = 1750000, .max = 3500000}, | |
331 | .n = { .min = 1, .max = 4 }, | |
332 | .m = { .min = 104, .max = 138 }, | |
333 | .m1 = { .min = 17, .max = 23 }, | |
334 | .m2 = { .min = 5, .max = 11 }, | |
335 | .p = { .min = 10, .max = 30 }, | |
336 | .p1 = { .min = 1, .max = 3}, | |
337 | .p2 = { .dot_limit = 270000, | |
338 | .p2_slow = 10, | |
339 | .p2_fast = 10 | |
044c7c41 | 340 | }, |
e4b36699 KP |
341 | }; |
342 | ||
1b6f4958 | 343 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
344 | .dot = { .min = 22000, .max = 400000 }, |
345 | .vco = { .min = 1750000, .max = 3500000}, | |
346 | .n = { .min = 1, .max = 4 }, | |
347 | .m = { .min = 104, .max = 138 }, | |
348 | .m1 = { .min = 16, .max = 23 }, | |
349 | .m2 = { .min = 5, .max = 11 }, | |
350 | .p = { .min = 5, .max = 80 }, | |
351 | .p1 = { .min = 1, .max = 8}, | |
352 | .p2 = { .dot_limit = 165000, | |
353 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
354 | }; |
355 | ||
1b6f4958 | 356 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
357 | .dot = { .min = 20000, .max = 115000 }, |
358 | .vco = { .min = 1750000, .max = 3500000 }, | |
359 | .n = { .min = 1, .max = 3 }, | |
360 | .m = { .min = 104, .max = 138 }, | |
361 | .m1 = { .min = 17, .max = 23 }, | |
362 | .m2 = { .min = 5, .max = 11 }, | |
363 | .p = { .min = 28, .max = 112 }, | |
364 | .p1 = { .min = 2, .max = 8 }, | |
365 | .p2 = { .dot_limit = 0, | |
366 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 367 | }, |
e4b36699 KP |
368 | }; |
369 | ||
1b6f4958 | 370 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
371 | .dot = { .min = 80000, .max = 224000 }, |
372 | .vco = { .min = 1750000, .max = 3500000 }, | |
373 | .n = { .min = 1, .max = 3 }, | |
374 | .m = { .min = 104, .max = 138 }, | |
375 | .m1 = { .min = 17, .max = 23 }, | |
376 | .m2 = { .min = 5, .max = 11 }, | |
377 | .p = { .min = 14, .max = 42 }, | |
378 | .p1 = { .min = 2, .max = 6 }, | |
379 | .p2 = { .dot_limit = 0, | |
380 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 381 | }, |
e4b36699 KP |
382 | }; |
383 | ||
1b6f4958 | 384 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
385 | .dot = { .min = 20000, .max = 400000}, |
386 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 387 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
388 | .n = { .min = 3, .max = 6 }, |
389 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 390 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
391 | .m1 = { .min = 0, .max = 0 }, |
392 | .m2 = { .min = 0, .max = 254 }, | |
393 | .p = { .min = 5, .max = 80 }, | |
394 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
395 | .p2 = { .dot_limit = 200000, |
396 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
397 | }; |
398 | ||
1b6f4958 | 399 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
400 | .dot = { .min = 20000, .max = 400000 }, |
401 | .vco = { .min = 1700000, .max = 3500000 }, | |
402 | .n = { .min = 3, .max = 6 }, | |
403 | .m = { .min = 2, .max = 256 }, | |
404 | .m1 = { .min = 0, .max = 0 }, | |
405 | .m2 = { .min = 0, .max = 254 }, | |
406 | .p = { .min = 7, .max = 112 }, | |
407 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
408 | .p2 = { .dot_limit = 112000, |
409 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
410 | }; |
411 | ||
273e27ca EA |
412 | /* Ironlake / Sandybridge |
413 | * | |
414 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
415 | * the range value for them is (actual_value - 2). | |
416 | */ | |
1b6f4958 | 417 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
418 | .dot = { .min = 25000, .max = 350000 }, |
419 | .vco = { .min = 1760000, .max = 3510000 }, | |
420 | .n = { .min = 1, .max = 5 }, | |
421 | .m = { .min = 79, .max = 127 }, | |
422 | .m1 = { .min = 12, .max = 22 }, | |
423 | .m2 = { .min = 5, .max = 9 }, | |
424 | .p = { .min = 5, .max = 80 }, | |
425 | .p1 = { .min = 1, .max = 8 }, | |
426 | .p2 = { .dot_limit = 225000, | |
427 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
428 | }; |
429 | ||
1b6f4958 | 430 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
431 | .dot = { .min = 25000, .max = 350000 }, |
432 | .vco = { .min = 1760000, .max = 3510000 }, | |
433 | .n = { .min = 1, .max = 3 }, | |
434 | .m = { .min = 79, .max = 118 }, | |
435 | .m1 = { .min = 12, .max = 22 }, | |
436 | .m2 = { .min = 5, .max = 9 }, | |
437 | .p = { .min = 28, .max = 112 }, | |
438 | .p1 = { .min = 2, .max = 8 }, | |
439 | .p2 = { .dot_limit = 225000, | |
440 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
441 | }; |
442 | ||
1b6f4958 | 443 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
444 | .dot = { .min = 25000, .max = 350000 }, |
445 | .vco = { .min = 1760000, .max = 3510000 }, | |
446 | .n = { .min = 1, .max = 3 }, | |
447 | .m = { .min = 79, .max = 127 }, | |
448 | .m1 = { .min = 12, .max = 22 }, | |
449 | .m2 = { .min = 5, .max = 9 }, | |
450 | .p = { .min = 14, .max = 56 }, | |
451 | .p1 = { .min = 2, .max = 8 }, | |
452 | .p2 = { .dot_limit = 225000, | |
453 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
454 | }; |
455 | ||
273e27ca | 456 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 457 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
458 | .dot = { .min = 25000, .max = 350000 }, |
459 | .vco = { .min = 1760000, .max = 3510000 }, | |
460 | .n = { .min = 1, .max = 2 }, | |
461 | .m = { .min = 79, .max = 126 }, | |
462 | .m1 = { .min = 12, .max = 22 }, | |
463 | .m2 = { .min = 5, .max = 9 }, | |
464 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 465 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
466 | .p2 = { .dot_limit = 225000, |
467 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
468 | }; |
469 | ||
1b6f4958 | 470 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
471 | .dot = { .min = 25000, .max = 350000 }, |
472 | .vco = { .min = 1760000, .max = 3510000 }, | |
473 | .n = { .min = 1, .max = 3 }, | |
474 | .m = { .min = 79, .max = 126 }, | |
475 | .m1 = { .min = 12, .max = 22 }, | |
476 | .m2 = { .min = 5, .max = 9 }, | |
477 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 478 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
479 | .p2 = { .dot_limit = 225000, |
480 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
481 | }; |
482 | ||
1b6f4958 | 483 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
484 | /* |
485 | * These are the data rate limits (measured in fast clocks) | |
486 | * since those are the strictest limits we have. The fast | |
487 | * clock and actual rate limits are more relaxed, so checking | |
488 | * them would make no difference. | |
489 | */ | |
490 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 491 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 492 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
493 | .m1 = { .min = 2, .max = 3 }, |
494 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 495 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 496 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
497 | }; |
498 | ||
1b6f4958 | 499 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
500 | /* |
501 | * These are the data rate limits (measured in fast clocks) | |
502 | * since those are the strictest limits we have. The fast | |
503 | * clock and actual rate limits are more relaxed, so checking | |
504 | * them would make no difference. | |
505 | */ | |
506 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 507 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
508 | .n = { .min = 1, .max = 1 }, |
509 | .m1 = { .min = 2, .max = 2 }, | |
510 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
511 | .p1 = { .min = 2, .max = 4 }, | |
512 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
513 | }; | |
514 | ||
1b6f4958 | 515 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
516 | /* FIXME: find real dot limits */ |
517 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 518 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
519 | .n = { .min = 1, .max = 1 }, |
520 | .m1 = { .min = 2, .max = 2 }, | |
521 | /* FIXME: find real m2 limits */ | |
522 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
523 | .p1 = { .min = 2, .max = 4 }, | |
524 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
525 | }; | |
526 | ||
cdba954e ACO |
527 | static bool |
528 | needs_modeset(struct drm_crtc_state *state) | |
529 | { | |
fc596660 | 530 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
531 | } |
532 | ||
e0638cdf PZ |
533 | /** |
534 | * Returns whether any output on the specified pipe is of the specified type | |
535 | */ | |
4093561b | 536 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 537 | { |
409ee761 | 538 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
539 | struct intel_encoder *encoder; |
540 | ||
409ee761 | 541 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
542 | if (encoder->type == type) |
543 | return true; | |
544 | ||
545 | return false; | |
546 | } | |
547 | ||
d0737e1d ACO |
548 | /** |
549 | * Returns whether any output on the specified pipe will have the specified | |
550 | * type after a staged modeset is complete, i.e., the same as | |
551 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
552 | * encoder->crtc. | |
553 | */ | |
a93e255f ACO |
554 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
555 | int type) | |
d0737e1d | 556 | { |
a93e255f | 557 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 558 | struct drm_connector *connector; |
a93e255f | 559 | struct drm_connector_state *connector_state; |
d0737e1d | 560 | struct intel_encoder *encoder; |
a93e255f ACO |
561 | int i, num_connectors = 0; |
562 | ||
da3ced29 | 563 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
564 | if (connector_state->crtc != crtc_state->base.crtc) |
565 | continue; | |
566 | ||
567 | num_connectors++; | |
d0737e1d | 568 | |
a93e255f ACO |
569 | encoder = to_intel_encoder(connector_state->best_encoder); |
570 | if (encoder->type == type) | |
d0737e1d | 571 | return true; |
a93e255f ACO |
572 | } |
573 | ||
574 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
575 | |
576 | return false; | |
577 | } | |
578 | ||
dccbea3b ID |
579 | /* |
580 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
581 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
582 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
583 | * The helpers' return value is the rate of the clock that is fed to the | |
584 | * display engine's pipe which can be the above fast dot clock rate or a | |
585 | * divided-down version of it. | |
586 | */ | |
f2b115e6 | 587 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 588 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 589 | { |
2177832f SL |
590 | clock->m = clock->m2 + 2; |
591 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 592 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 593 | return 0; |
fb03ac01 VS |
594 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
595 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
596 | |
597 | return clock->dot; | |
2177832f SL |
598 | } |
599 | ||
7429e9d4 DV |
600 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
601 | { | |
602 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
603 | } | |
604 | ||
9e2c8475 | 605 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 606 | { |
7429e9d4 | 607 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 608 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 609 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 610 | return 0; |
fb03ac01 VS |
611 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
612 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
613 | |
614 | return clock->dot; | |
79e53945 JB |
615 | } |
616 | ||
9e2c8475 | 617 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
618 | { |
619 | clock->m = clock->m1 * clock->m2; | |
620 | clock->p = clock->p1 * clock->p2; | |
621 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 622 | return 0; |
589eca67 ID |
623 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
624 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
625 | |
626 | return clock->dot / 5; | |
589eca67 ID |
627 | } |
628 | ||
9e2c8475 | 629 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
630 | { |
631 | clock->m = clock->m1 * clock->m2; | |
632 | clock->p = clock->p1 * clock->p2; | |
633 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 634 | return 0; |
ef9348c8 CML |
635 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
636 | clock->n << 22); | |
637 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
638 | |
639 | return clock->dot / 5; | |
ef9348c8 CML |
640 | } |
641 | ||
7c04d1d9 | 642 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
643 | /** |
644 | * Returns whether the given set of divisors are valid for a given refclk with | |
645 | * the given connectors. | |
646 | */ | |
647 | ||
1b894b59 | 648 | static bool intel_PLL_is_valid(struct drm_device *dev, |
1b6f4958 | 649 | const struct intel_limit *limit, |
9e2c8475 | 650 | const struct dpll *clock) |
79e53945 | 651 | { |
f01b7962 VS |
652 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
653 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 654 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 655 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 656 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 657 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 658 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 659 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 660 | |
666a4537 WB |
661 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
662 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
663 | if (clock->m1 <= clock->m2) |
664 | INTELPllInvalid("m1 <= m2\n"); | |
665 | ||
666a4537 | 666 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
667 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
668 | INTELPllInvalid("p out of range\n"); | |
669 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
670 | INTELPllInvalid("m out of range\n"); | |
671 | } | |
672 | ||
79e53945 | 673 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 674 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
675 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
676 | * connector, etc., rather than just a single range. | |
677 | */ | |
678 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 679 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
680 | |
681 | return true; | |
682 | } | |
683 | ||
3b1429d9 | 684 | static int |
1b6f4958 | 685 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
686 | const struct intel_crtc_state *crtc_state, |
687 | int target) | |
79e53945 | 688 | { |
3b1429d9 | 689 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 690 | |
a93e255f | 691 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 692 | /* |
a210b028 DV |
693 | * For LVDS just rely on its current settings for dual-channel. |
694 | * We haven't figured out how to reliably set up different | |
695 | * single/dual channel state, if we even can. | |
79e53945 | 696 | */ |
1974cad0 | 697 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 698 | return limit->p2.p2_fast; |
79e53945 | 699 | else |
3b1429d9 | 700 | return limit->p2.p2_slow; |
79e53945 JB |
701 | } else { |
702 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 703 | return limit->p2.p2_slow; |
79e53945 | 704 | else |
3b1429d9 | 705 | return limit->p2.p2_fast; |
79e53945 | 706 | } |
3b1429d9 VS |
707 | } |
708 | ||
70e8aa21 ACO |
709 | /* |
710 | * Returns a set of divisors for the desired target clock with the given | |
711 | * refclk, or FALSE. The returned values represent the clock equation: | |
712 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
713 | * | |
714 | * Target and reference clocks are specified in kHz. | |
715 | * | |
716 | * If match_clock is provided, then best_clock P divider must match the P | |
717 | * divider from @match_clock used for LVDS downclocking. | |
718 | */ | |
3b1429d9 | 719 | static bool |
1b6f4958 | 720 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 721 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
722 | int target, int refclk, struct dpll *match_clock, |
723 | struct dpll *best_clock) | |
3b1429d9 VS |
724 | { |
725 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 726 | struct dpll clock; |
3b1429d9 | 727 | int err = target; |
79e53945 | 728 | |
0206e353 | 729 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 730 | |
3b1429d9 VS |
731 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
732 | ||
42158660 ZY |
733 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
734 | clock.m1++) { | |
735 | for (clock.m2 = limit->m2.min; | |
736 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 737 | if (clock.m2 >= clock.m1) |
42158660 ZY |
738 | break; |
739 | for (clock.n = limit->n.min; | |
740 | clock.n <= limit->n.max; clock.n++) { | |
741 | for (clock.p1 = limit->p1.min; | |
742 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
743 | int this_err; |
744 | ||
dccbea3b | 745 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
746 | if (!intel_PLL_is_valid(dev, limit, |
747 | &clock)) | |
748 | continue; | |
749 | if (match_clock && | |
750 | clock.p != match_clock->p) | |
751 | continue; | |
752 | ||
753 | this_err = abs(clock.dot - target); | |
754 | if (this_err < err) { | |
755 | *best_clock = clock; | |
756 | err = this_err; | |
757 | } | |
758 | } | |
759 | } | |
760 | } | |
761 | } | |
762 | ||
763 | return (err != target); | |
764 | } | |
765 | ||
70e8aa21 ACO |
766 | /* |
767 | * Returns a set of divisors for the desired target clock with the given | |
768 | * refclk, or FALSE. The returned values represent the clock equation: | |
769 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
770 | * | |
771 | * Target and reference clocks are specified in kHz. | |
772 | * | |
773 | * If match_clock is provided, then best_clock P divider must match the P | |
774 | * divider from @match_clock used for LVDS downclocking. | |
775 | */ | |
ac58c3f0 | 776 | static bool |
1b6f4958 | 777 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 778 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
779 | int target, int refclk, struct dpll *match_clock, |
780 | struct dpll *best_clock) | |
79e53945 | 781 | { |
3b1429d9 | 782 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 783 | struct dpll clock; |
79e53945 JB |
784 | int err = target; |
785 | ||
0206e353 | 786 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 787 | |
3b1429d9 VS |
788 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
789 | ||
42158660 ZY |
790 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
791 | clock.m1++) { | |
792 | for (clock.m2 = limit->m2.min; | |
793 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
794 | for (clock.n = limit->n.min; |
795 | clock.n <= limit->n.max; clock.n++) { | |
796 | for (clock.p1 = limit->p1.min; | |
797 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
798 | int this_err; |
799 | ||
dccbea3b | 800 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
801 | if (!intel_PLL_is_valid(dev, limit, |
802 | &clock)) | |
79e53945 | 803 | continue; |
cec2f356 SP |
804 | if (match_clock && |
805 | clock.p != match_clock->p) | |
806 | continue; | |
79e53945 JB |
807 | |
808 | this_err = abs(clock.dot - target); | |
809 | if (this_err < err) { | |
810 | *best_clock = clock; | |
811 | err = this_err; | |
812 | } | |
813 | } | |
814 | } | |
815 | } | |
816 | } | |
817 | ||
818 | return (err != target); | |
819 | } | |
820 | ||
997c030c ACO |
821 | /* |
822 | * Returns a set of divisors for the desired target clock with the given | |
823 | * refclk, or FALSE. The returned values represent the clock equation: | |
824 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
825 | * |
826 | * Target and reference clocks are specified in kHz. | |
827 | * | |
828 | * If match_clock is provided, then best_clock P divider must match the P | |
829 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 830 | */ |
d4906093 | 831 | static bool |
1b6f4958 | 832 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 833 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
834 | int target, int refclk, struct dpll *match_clock, |
835 | struct dpll *best_clock) | |
d4906093 | 836 | { |
3b1429d9 | 837 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 838 | struct dpll clock; |
d4906093 | 839 | int max_n; |
3b1429d9 | 840 | bool found = false; |
6ba770dc AJ |
841 | /* approximately equals target * 0.00585 */ |
842 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
843 | |
844 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
845 | |
846 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
847 | ||
d4906093 | 848 | max_n = limit->n.max; |
f77f13e2 | 849 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 850 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 851 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
852 | for (clock.m1 = limit->m1.max; |
853 | clock.m1 >= limit->m1.min; clock.m1--) { | |
854 | for (clock.m2 = limit->m2.max; | |
855 | clock.m2 >= limit->m2.min; clock.m2--) { | |
856 | for (clock.p1 = limit->p1.max; | |
857 | clock.p1 >= limit->p1.min; clock.p1--) { | |
858 | int this_err; | |
859 | ||
dccbea3b | 860 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
861 | if (!intel_PLL_is_valid(dev, limit, |
862 | &clock)) | |
d4906093 | 863 | continue; |
1b894b59 CW |
864 | |
865 | this_err = abs(clock.dot - target); | |
d4906093 ML |
866 | if (this_err < err_most) { |
867 | *best_clock = clock; | |
868 | err_most = this_err; | |
869 | max_n = clock.n; | |
870 | found = true; | |
871 | } | |
872 | } | |
873 | } | |
874 | } | |
875 | } | |
2c07245f ZW |
876 | return found; |
877 | } | |
878 | ||
d5dd62bd ID |
879 | /* |
880 | * Check if the calculated PLL configuration is more optimal compared to the | |
881 | * best configuration and error found so far. Return the calculated error. | |
882 | */ | |
883 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
884 | const struct dpll *calculated_clock, |
885 | const struct dpll *best_clock, | |
d5dd62bd ID |
886 | unsigned int best_error_ppm, |
887 | unsigned int *error_ppm) | |
888 | { | |
9ca3ba01 ID |
889 | /* |
890 | * For CHV ignore the error and consider only the P value. | |
891 | * Prefer a bigger P value based on HW requirements. | |
892 | */ | |
893 | if (IS_CHERRYVIEW(dev)) { | |
894 | *error_ppm = 0; | |
895 | ||
896 | return calculated_clock->p > best_clock->p; | |
897 | } | |
898 | ||
24be4e46 ID |
899 | if (WARN_ON_ONCE(!target_freq)) |
900 | return false; | |
901 | ||
d5dd62bd ID |
902 | *error_ppm = div_u64(1000000ULL * |
903 | abs(target_freq - calculated_clock->dot), | |
904 | target_freq); | |
905 | /* | |
906 | * Prefer a better P value over a better (smaller) error if the error | |
907 | * is small. Ensure this preference for future configurations too by | |
908 | * setting the error to 0. | |
909 | */ | |
910 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
911 | *error_ppm = 0; | |
912 | ||
913 | return true; | |
914 | } | |
915 | ||
916 | return *error_ppm + 10 < best_error_ppm; | |
917 | } | |
918 | ||
65b3d6a9 ACO |
919 | /* |
920 | * Returns a set of divisors for the desired target clock with the given | |
921 | * refclk, or FALSE. The returned values represent the clock equation: | |
922 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
923 | */ | |
a0c4da24 | 924 | static bool |
1b6f4958 | 925 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 926 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
927 | int target, int refclk, struct dpll *match_clock, |
928 | struct dpll *best_clock) | |
a0c4da24 | 929 | { |
a93e255f | 930 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 931 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 932 | struct dpll clock; |
69e4f900 | 933 | unsigned int bestppm = 1000000; |
27e639bf VS |
934 | /* min update 19.2 MHz */ |
935 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 936 | bool found = false; |
a0c4da24 | 937 | |
6b4bf1c4 VS |
938 | target *= 5; /* fast clock */ |
939 | ||
940 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
941 | |
942 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 943 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 944 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 945 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 946 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 947 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 948 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 949 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 950 | unsigned int ppm; |
69e4f900 | 951 | |
6b4bf1c4 VS |
952 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
953 | refclk * clock.m1); | |
954 | ||
dccbea3b | 955 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 956 | |
f01b7962 VS |
957 | if (!intel_PLL_is_valid(dev, limit, |
958 | &clock)) | |
43b0ac53 VS |
959 | continue; |
960 | ||
d5dd62bd ID |
961 | if (!vlv_PLL_is_optimal(dev, target, |
962 | &clock, | |
963 | best_clock, | |
964 | bestppm, &ppm)) | |
965 | continue; | |
6b4bf1c4 | 966 | |
d5dd62bd ID |
967 | *best_clock = clock; |
968 | bestppm = ppm; | |
969 | found = true; | |
a0c4da24 JB |
970 | } |
971 | } | |
972 | } | |
973 | } | |
a0c4da24 | 974 | |
49e497ef | 975 | return found; |
a0c4da24 | 976 | } |
a4fc5ed6 | 977 | |
65b3d6a9 ACO |
978 | /* |
979 | * Returns a set of divisors for the desired target clock with the given | |
980 | * refclk, or FALSE. The returned values represent the clock equation: | |
981 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
982 | */ | |
ef9348c8 | 983 | static bool |
1b6f4958 | 984 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 985 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
986 | int target, int refclk, struct dpll *match_clock, |
987 | struct dpll *best_clock) | |
ef9348c8 | 988 | { |
a93e255f | 989 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 990 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 991 | unsigned int best_error_ppm; |
9e2c8475 | 992 | struct dpll clock; |
ef9348c8 CML |
993 | uint64_t m2; |
994 | int found = false; | |
995 | ||
996 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 997 | best_error_ppm = 1000000; |
ef9348c8 CML |
998 | |
999 | /* | |
1000 | * Based on hardware doc, the n always set to 1, and m1 always | |
1001 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1002 | * revisit this because n may not 1 anymore. | |
1003 | */ | |
1004 | clock.n = 1, clock.m1 = 2; | |
1005 | target *= 5; /* fast clock */ | |
1006 | ||
1007 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1008 | for (clock.p2 = limit->p2.p2_fast; | |
1009 | clock.p2 >= limit->p2.p2_slow; | |
1010 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1011 | unsigned int error_ppm; |
ef9348c8 CML |
1012 | |
1013 | clock.p = clock.p1 * clock.p2; | |
1014 | ||
1015 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1016 | clock.n) << 22, refclk * clock.m1); | |
1017 | ||
1018 | if (m2 > INT_MAX/clock.m1) | |
1019 | continue; | |
1020 | ||
1021 | clock.m2 = m2; | |
1022 | ||
dccbea3b | 1023 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1024 | |
1025 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1026 | continue; | |
1027 | ||
9ca3ba01 ID |
1028 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1029 | best_error_ppm, &error_ppm)) | |
1030 | continue; | |
1031 | ||
1032 | *best_clock = clock; | |
1033 | best_error_ppm = error_ppm; | |
1034 | found = true; | |
ef9348c8 CML |
1035 | } |
1036 | } | |
1037 | ||
1038 | return found; | |
1039 | } | |
1040 | ||
5ab7b0b7 | 1041 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 1042 | struct dpll *best_clock) |
5ab7b0b7 | 1043 | { |
65b3d6a9 | 1044 | int refclk = 100000; |
1b6f4958 | 1045 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1046 | |
65b3d6a9 | 1047 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1048 | target_clock, refclk, NULL, best_clock); |
1049 | } | |
1050 | ||
20ddf665 VS |
1051 | bool intel_crtc_active(struct drm_crtc *crtc) |
1052 | { | |
1053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1054 | ||
1055 | /* Be paranoid as we can arrive here with only partial | |
1056 | * state retrieved from the hardware during setup. | |
1057 | * | |
241bfc38 | 1058 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1059 | * as Haswell has gained clock readout/fastboot support. |
1060 | * | |
66e514c1 | 1061 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1062 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1063 | * |
1064 | * FIXME: The intel_crtc->active here should be switched to | |
1065 | * crtc->state->active once we have proper CRTC states wired up | |
1066 | * for atomic. | |
20ddf665 | 1067 | */ |
c3d1f436 | 1068 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1069 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1070 | } |
1071 | ||
a5c961d1 PZ |
1072 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1073 | enum pipe pipe) | |
1074 | { | |
1075 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1076 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1077 | ||
6e3c9717 | 1078 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1079 | } |
1080 | ||
fbf49ea2 VS |
1081 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1082 | { | |
1083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1084 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1085 | u32 line1, line2; |
1086 | u32 line_mask; | |
1087 | ||
1088 | if (IS_GEN2(dev)) | |
1089 | line_mask = DSL_LINEMASK_GEN2; | |
1090 | else | |
1091 | line_mask = DSL_LINEMASK_GEN3; | |
1092 | ||
1093 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1094 | msleep(5); |
fbf49ea2 VS |
1095 | line2 = I915_READ(reg) & line_mask; |
1096 | ||
1097 | return line1 == line2; | |
1098 | } | |
1099 | ||
ab7ad7f6 KP |
1100 | /* |
1101 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1102 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1103 | * |
1104 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1105 | * spinning on the vblank interrupt status bit, since we won't actually | |
1106 | * see an interrupt when the pipe is disabled. | |
1107 | * | |
ab7ad7f6 KP |
1108 | * On Gen4 and above: |
1109 | * wait for the pipe register state bit to turn off | |
1110 | * | |
1111 | * Otherwise: | |
1112 | * wait for the display line value to settle (it usually | |
1113 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1114 | * |
9d0498a2 | 1115 | */ |
575f7ab7 | 1116 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1117 | { |
575f7ab7 | 1118 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1119 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1120 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1121 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1122 | |
1123 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1124 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1125 | |
1126 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1127 | if (intel_wait_for_register(dev_priv, |
1128 | reg, I965_PIPECONF_ACTIVE, 0, | |
1129 | 100)) | |
284637d9 | 1130 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1131 | } else { |
ab7ad7f6 | 1132 | /* Wait for the display line to settle */ |
fbf49ea2 | 1133 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1134 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1135 | } |
79e53945 JB |
1136 | } |
1137 | ||
b24e7179 | 1138 | /* Only for pre-ILK configs */ |
55607e8a DV |
1139 | void assert_pll(struct drm_i915_private *dev_priv, |
1140 | enum pipe pipe, bool state) | |
b24e7179 | 1141 | { |
b24e7179 JB |
1142 | u32 val; |
1143 | bool cur_state; | |
1144 | ||
649636ef | 1145 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1146 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1147 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1148 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1149 | onoff(state), onoff(cur_state)); |
b24e7179 | 1150 | } |
b24e7179 | 1151 | |
23538ef1 | 1152 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1153 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1154 | { |
1155 | u32 val; | |
1156 | bool cur_state; | |
1157 | ||
a580516d | 1158 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1159 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1160 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1161 | |
1162 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1163 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1164 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1165 | onoff(state), onoff(cur_state)); |
23538ef1 | 1166 | } |
23538ef1 | 1167 | |
040484af JB |
1168 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1169 | enum pipe pipe, bool state) | |
1170 | { | |
040484af | 1171 | bool cur_state; |
ad80a810 PZ |
1172 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1173 | pipe); | |
040484af | 1174 | |
2d1fe073 | 1175 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1176 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1177 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1178 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1179 | } else { |
649636ef | 1180 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1181 | cur_state = !!(val & FDI_TX_ENABLE); |
1182 | } | |
e2c719b7 | 1183 | I915_STATE_WARN(cur_state != state, |
040484af | 1184 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1185 | onoff(state), onoff(cur_state)); |
040484af JB |
1186 | } |
1187 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1188 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1189 | ||
1190 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1191 | enum pipe pipe, bool state) | |
1192 | { | |
040484af JB |
1193 | u32 val; |
1194 | bool cur_state; | |
1195 | ||
649636ef | 1196 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1197 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1198 | I915_STATE_WARN(cur_state != state, |
040484af | 1199 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1200 | onoff(state), onoff(cur_state)); |
040484af JB |
1201 | } |
1202 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1203 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1204 | ||
1205 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1206 | enum pipe pipe) | |
1207 | { | |
040484af JB |
1208 | u32 val; |
1209 | ||
1210 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1211 | if (IS_GEN5(dev_priv)) |
040484af JB |
1212 | return; |
1213 | ||
bf507ef7 | 1214 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1215 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1216 | return; |
1217 | ||
649636ef | 1218 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1219 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1220 | } |
1221 | ||
55607e8a DV |
1222 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1223 | enum pipe pipe, bool state) | |
040484af | 1224 | { |
040484af | 1225 | u32 val; |
55607e8a | 1226 | bool cur_state; |
040484af | 1227 | |
649636ef | 1228 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1229 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1230 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1231 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1232 | onoff(state), onoff(cur_state)); |
040484af JB |
1233 | } |
1234 | ||
b680c37a DV |
1235 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1236 | enum pipe pipe) | |
ea0760cf | 1237 | { |
bedd4dba | 1238 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1239 | i915_reg_t pp_reg; |
ea0760cf JB |
1240 | u32 val; |
1241 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1242 | bool locked = true; |
ea0760cf | 1243 | |
bedd4dba JN |
1244 | if (WARN_ON(HAS_DDI(dev))) |
1245 | return; | |
1246 | ||
1247 | if (HAS_PCH_SPLIT(dev)) { | |
1248 | u32 port_sel; | |
1249 | ||
ea0760cf | 1250 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1251 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1252 | ||
1253 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1254 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1255 | panel_pipe = PIPE_B; | |
1256 | /* XXX: else fix for eDP */ | |
666a4537 | 1257 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1258 | /* presumably write lock depends on pipe, not port select */ |
1259 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1260 | panel_pipe = pipe; | |
ea0760cf JB |
1261 | } else { |
1262 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1263 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1264 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1265 | } |
1266 | ||
1267 | val = I915_READ(pp_reg); | |
1268 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1269 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1270 | locked = false; |
1271 | ||
e2c719b7 | 1272 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1273 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1274 | pipe_name(pipe)); |
ea0760cf JB |
1275 | } |
1276 | ||
93ce0ba6 JN |
1277 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1278 | enum pipe pipe, bool state) | |
1279 | { | |
1280 | struct drm_device *dev = dev_priv->dev; | |
1281 | bool cur_state; | |
1282 | ||
d9d82081 | 1283 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1284 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1285 | else |
5efb3e28 | 1286 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1287 | |
e2c719b7 | 1288 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1289 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1290 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1291 | } |
1292 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1293 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1294 | ||
b840d907 JB |
1295 | void assert_pipe(struct drm_i915_private *dev_priv, |
1296 | enum pipe pipe, bool state) | |
b24e7179 | 1297 | { |
63d7bbe9 | 1298 | bool cur_state; |
702e7a56 PZ |
1299 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1300 | pipe); | |
4feed0eb | 1301 | enum intel_display_power_domain power_domain; |
b24e7179 | 1302 | |
b6b5d049 VS |
1303 | /* if we need the pipe quirk it must be always on */ |
1304 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1305 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1306 | state = true; |
1307 | ||
4feed0eb ID |
1308 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1309 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1310 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1311 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1312 | |
1313 | intel_display_power_put(dev_priv, power_domain); | |
1314 | } else { | |
1315 | cur_state = false; | |
69310161 PZ |
1316 | } |
1317 | ||
e2c719b7 | 1318 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1319 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1320 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1321 | } |
1322 | ||
931872fc CW |
1323 | static void assert_plane(struct drm_i915_private *dev_priv, |
1324 | enum plane plane, bool state) | |
b24e7179 | 1325 | { |
b24e7179 | 1326 | u32 val; |
931872fc | 1327 | bool cur_state; |
b24e7179 | 1328 | |
649636ef | 1329 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1330 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1331 | I915_STATE_WARN(cur_state != state, |
931872fc | 1332 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1333 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1334 | } |
1335 | ||
931872fc CW |
1336 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1337 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1338 | ||
b24e7179 JB |
1339 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1340 | enum pipe pipe) | |
1341 | { | |
653e1026 | 1342 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1343 | int i; |
b24e7179 | 1344 | |
653e1026 VS |
1345 | /* Primary planes are fixed to pipes on gen4+ */ |
1346 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1347 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1348 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1349 | "plane %c assertion failure, should be disabled but not\n", |
1350 | plane_name(pipe)); | |
19ec1358 | 1351 | return; |
28c05794 | 1352 | } |
19ec1358 | 1353 | |
b24e7179 | 1354 | /* Need to check both planes against the pipe */ |
055e393f | 1355 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1356 | u32 val = I915_READ(DSPCNTR(i)); |
1357 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1358 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1359 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1360 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1361 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1362 | } |
1363 | } | |
1364 | ||
19332d7a JB |
1365 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1366 | enum pipe pipe) | |
1367 | { | |
20674eef | 1368 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1369 | int sprite; |
19332d7a | 1370 | |
7feb8b88 | 1371 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1372 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1373 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1374 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1375 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1376 | sprite, pipe_name(pipe)); | |
1377 | } | |
666a4537 | 1378 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1379 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1380 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1381 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1382 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1383 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1384 | } |
1385 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1386 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1387 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1388 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1389 | plane_name(pipe), pipe_name(pipe)); |
1390 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1391 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1392 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1393 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1394 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1395 | } |
1396 | } | |
1397 | ||
08c71e5e VS |
1398 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1399 | { | |
e2c719b7 | 1400 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1401 | drm_crtc_vblank_put(crtc); |
1402 | } | |
1403 | ||
7abd4b35 ACO |
1404 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1405 | enum pipe pipe) | |
92f2584a | 1406 | { |
92f2584a JB |
1407 | u32 val; |
1408 | bool enabled; | |
1409 | ||
649636ef | 1410 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1411 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1412 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1413 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1414 | pipe_name(pipe)); | |
92f2584a JB |
1415 | } |
1416 | ||
4e634389 KP |
1417 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1418 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1419 | { |
1420 | if ((val & DP_PORT_EN) == 0) | |
1421 | return false; | |
1422 | ||
2d1fe073 | 1423 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1424 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1425 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1426 | return false; | |
2d1fe073 | 1427 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1428 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1429 | return false; | |
f0575e92 KP |
1430 | } else { |
1431 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1432 | return false; | |
1433 | } | |
1434 | return true; | |
1435 | } | |
1436 | ||
1519b995 KP |
1437 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1438 | enum pipe pipe, u32 val) | |
1439 | { | |
dc0fa718 | 1440 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1441 | return false; |
1442 | ||
2d1fe073 | 1443 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1444 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1445 | return false; |
2d1fe073 | 1446 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1447 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1448 | return false; | |
1519b995 | 1449 | } else { |
dc0fa718 | 1450 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1451 | return false; |
1452 | } | |
1453 | return true; | |
1454 | } | |
1455 | ||
1456 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1457 | enum pipe pipe, u32 val) | |
1458 | { | |
1459 | if ((val & LVDS_PORT_EN) == 0) | |
1460 | return false; | |
1461 | ||
2d1fe073 | 1462 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1463 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1464 | return false; | |
1465 | } else { | |
1466 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1467 | return false; | |
1468 | } | |
1469 | return true; | |
1470 | } | |
1471 | ||
1472 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1473 | enum pipe pipe, u32 val) | |
1474 | { | |
1475 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1476 | return false; | |
2d1fe073 | 1477 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1478 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1479 | return false; | |
1480 | } else { | |
1481 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1482 | return false; | |
1483 | } | |
1484 | return true; | |
1485 | } | |
1486 | ||
291906f1 | 1487 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1488 | enum pipe pipe, i915_reg_t reg, |
1489 | u32 port_sel) | |
291906f1 | 1490 | { |
47a05eca | 1491 | u32 val = I915_READ(reg); |
e2c719b7 | 1492 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1493 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1494 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1495 | |
2d1fe073 | 1496 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1497 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1498 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1499 | } |
1500 | ||
1501 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1502 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1503 | { |
47a05eca | 1504 | u32 val = I915_READ(reg); |
e2c719b7 | 1505 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1506 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1507 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1508 | |
2d1fe073 | 1509 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1510 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1511 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1512 | } |
1513 | ||
1514 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1515 | enum pipe pipe) | |
1516 | { | |
291906f1 | 1517 | u32 val; |
291906f1 | 1518 | |
f0575e92 KP |
1519 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1520 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1521 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1522 | |
649636ef | 1523 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1524 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1525 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1526 | pipe_name(pipe)); |
291906f1 | 1527 | |
649636ef | 1528 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1529 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1530 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1531 | pipe_name(pipe)); |
291906f1 | 1532 | |
e2debe91 PZ |
1533 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1534 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1535 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1536 | } |
1537 | ||
cd2d34d9 VS |
1538 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1539 | const struct intel_crtc_state *pipe_config) | |
1540 | { | |
1541 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1542 | enum pipe pipe = crtc->pipe; | |
1543 | ||
1544 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1545 | POSTING_READ(DPLL(pipe)); | |
1546 | udelay(150); | |
1547 | ||
2c30b43b CW |
1548 | if (intel_wait_for_register(dev_priv, |
1549 | DPLL(pipe), | |
1550 | DPLL_LOCK_VLV, | |
1551 | DPLL_LOCK_VLV, | |
1552 | 1)) | |
cd2d34d9 VS |
1553 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1554 | } | |
1555 | ||
d288f65f | 1556 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1557 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1558 | { |
cd2d34d9 | 1559 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1560 | enum pipe pipe = crtc->pipe; |
87442f73 | 1561 | |
8bd3f301 | 1562 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1563 | |
87442f73 | 1564 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1565 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1566 | |
cd2d34d9 VS |
1567 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1568 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1569 | |
8bd3f301 VS |
1570 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1571 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1572 | } |
1573 | ||
cd2d34d9 VS |
1574 | |
1575 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1576 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1577 | { |
cd2d34d9 | 1578 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1579 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1580 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1581 | u32 tmp; |
1582 | ||
a580516d | 1583 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1584 | |
1585 | /* Enable back the 10bit clock to display controller */ | |
1586 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1587 | tmp |= DPIO_DCLKP_EN; | |
1588 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1589 | ||
54433e91 VS |
1590 | mutex_unlock(&dev_priv->sb_lock); |
1591 | ||
9d556c99 CML |
1592 | /* |
1593 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1594 | */ | |
1595 | udelay(1); | |
1596 | ||
1597 | /* Enable PLL */ | |
d288f65f | 1598 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1599 | |
1600 | /* Check PLL is locked */ | |
6b18826a CW |
1601 | if (intel_wait_for_register(dev_priv, |
1602 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1603 | 1)) | |
9d556c99 | 1604 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1605 | } |
1606 | ||
1607 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1608 | const struct intel_crtc_state *pipe_config) | |
1609 | { | |
1610 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1611 | enum pipe pipe = crtc->pipe; | |
1612 | ||
1613 | assert_pipe_disabled(dev_priv, pipe); | |
1614 | ||
1615 | /* PLL is protected by panel, make sure we can write it */ | |
1616 | assert_panel_unlocked(dev_priv, pipe); | |
1617 | ||
1618 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1619 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1620 | |
c231775c VS |
1621 | if (pipe != PIPE_A) { |
1622 | /* | |
1623 | * WaPixelRepeatModeFixForC0:chv | |
1624 | * | |
1625 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1626 | * the value from DPLLBMD to either pipe B or C. | |
1627 | */ | |
1628 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1629 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1630 | I915_WRITE(CBR4_VLV, 0); | |
1631 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1632 | ||
1633 | /* | |
1634 | * DPLLB VGA mode also seems to cause problems. | |
1635 | * We should always have it disabled. | |
1636 | */ | |
1637 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1638 | } else { | |
1639 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1640 | POSTING_READ(DPLL_MD(pipe)); | |
1641 | } | |
9d556c99 CML |
1642 | } |
1643 | ||
1c4e0274 VS |
1644 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1645 | { | |
1646 | struct intel_crtc *crtc; | |
1647 | int count = 0; | |
1648 | ||
1649 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1650 | count += crtc->base.state->active && |
409ee761 | 1651 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1652 | |
1653 | return count; | |
1654 | } | |
1655 | ||
66e3d5c0 | 1656 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1657 | { |
66e3d5c0 DV |
1658 | struct drm_device *dev = crtc->base.dev; |
1659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1660 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1661 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1662 | |
66e3d5c0 | 1663 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1664 | |
63d7bbe9 | 1665 | /* PLL is protected by panel, make sure we can write it */ |
66e3d5c0 DV |
1666 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1667 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1668 | |
1c4e0274 VS |
1669 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1670 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1671 | /* | |
1672 | * It appears to be important that we don't enable this | |
1673 | * for the current pipe before otherwise configuring the | |
1674 | * PLL. No idea how this should be handled if multiple | |
1675 | * DVO outputs are enabled simultaneosly. | |
1676 | */ | |
1677 | dpll |= DPLL_DVO_2X_MODE; | |
1678 | I915_WRITE(DPLL(!crtc->pipe), | |
1679 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1680 | } | |
66e3d5c0 | 1681 | |
c2b63374 VS |
1682 | /* |
1683 | * Apparently we need to have VGA mode enabled prior to changing | |
1684 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1685 | * dividers, even though the register value does change. | |
1686 | */ | |
1687 | I915_WRITE(reg, 0); | |
1688 | ||
8e7a65aa VS |
1689 | I915_WRITE(reg, dpll); |
1690 | ||
66e3d5c0 DV |
1691 | /* Wait for the clocks to stabilize. */ |
1692 | POSTING_READ(reg); | |
1693 | udelay(150); | |
1694 | ||
1695 | if (INTEL_INFO(dev)->gen >= 4) { | |
1696 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1697 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1698 | } else { |
1699 | /* The pixel multiplier can only be updated once the | |
1700 | * DPLL is enabled and the clocks are stable. | |
1701 | * | |
1702 | * So write it again. | |
1703 | */ | |
1704 | I915_WRITE(reg, dpll); | |
1705 | } | |
63d7bbe9 JB |
1706 | |
1707 | /* We do this three times for luck */ | |
66e3d5c0 | 1708 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1709 | POSTING_READ(reg); |
1710 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1711 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1712 | POSTING_READ(reg); |
1713 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1714 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1715 | POSTING_READ(reg); |
1716 | udelay(150); /* wait for warmup */ | |
1717 | } | |
1718 | ||
1719 | /** | |
50b44a44 | 1720 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1721 | * @dev_priv: i915 private structure |
1722 | * @pipe: pipe PLL to disable | |
1723 | * | |
1724 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1725 | * | |
1726 | * Note! This is for pre-ILK only. | |
1727 | */ | |
1c4e0274 | 1728 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1729 | { |
1c4e0274 VS |
1730 | struct drm_device *dev = crtc->base.dev; |
1731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1732 | enum pipe pipe = crtc->pipe; | |
1733 | ||
1734 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1735 | if (IS_I830(dev) && | |
409ee761 | 1736 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1737 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1738 | I915_WRITE(DPLL(PIPE_B), |
1739 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1740 | I915_WRITE(DPLL(PIPE_A), | |
1741 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1742 | } | |
1743 | ||
b6b5d049 VS |
1744 | /* Don't disable pipe or pipe PLLs if needed */ |
1745 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1746 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1747 | return; |
1748 | ||
1749 | /* Make sure the pipe isn't still relying on us */ | |
1750 | assert_pipe_disabled(dev_priv, pipe); | |
1751 | ||
b8afb911 | 1752 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1753 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1754 | } |
1755 | ||
f6071166 JB |
1756 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1757 | { | |
b8afb911 | 1758 | u32 val; |
f6071166 JB |
1759 | |
1760 | /* Make sure the pipe isn't still relying on us */ | |
1761 | assert_pipe_disabled(dev_priv, pipe); | |
1762 | ||
03ed5cbf VS |
1763 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1764 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1765 | if (pipe != PIPE_A) | |
1766 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1767 | ||
f6071166 JB |
1768 | I915_WRITE(DPLL(pipe), val); |
1769 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1770 | } |
1771 | ||
1772 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1773 | { | |
d752048d | 1774 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1775 | u32 val; |
1776 | ||
a11b0703 VS |
1777 | /* Make sure the pipe isn't still relying on us */ |
1778 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1779 | |
60bfe44f VS |
1780 | val = DPLL_SSC_REF_CLK_CHV | |
1781 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1782 | if (pipe != PIPE_A) |
1783 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1784 | |
a11b0703 VS |
1785 | I915_WRITE(DPLL(pipe), val); |
1786 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1787 | |
a580516d | 1788 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1789 | |
1790 | /* Disable 10bit clock to display controller */ | |
1791 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1792 | val &= ~DPIO_DCLKP_EN; | |
1793 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1794 | ||
a580516d | 1795 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1796 | } |
1797 | ||
e4607fcf | 1798 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1799 | struct intel_digital_port *dport, |
1800 | unsigned int expected_mask) | |
89b667f8 JB |
1801 | { |
1802 | u32 port_mask; | |
f0f59a00 | 1803 | i915_reg_t dpll_reg; |
89b667f8 | 1804 | |
e4607fcf CML |
1805 | switch (dport->port) { |
1806 | case PORT_B: | |
89b667f8 | 1807 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1808 | dpll_reg = DPLL(0); |
e4607fcf CML |
1809 | break; |
1810 | case PORT_C: | |
89b667f8 | 1811 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1812 | dpll_reg = DPLL(0); |
9b6de0a1 | 1813 | expected_mask <<= 4; |
00fc31b7 CML |
1814 | break; |
1815 | case PORT_D: | |
1816 | port_mask = DPLL_PORTD_READY_MASK; | |
1817 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1818 | break; |
1819 | default: | |
1820 | BUG(); | |
1821 | } | |
89b667f8 | 1822 | |
370004d3 CW |
1823 | if (intel_wait_for_register(dev_priv, |
1824 | dpll_reg, port_mask, expected_mask, | |
1825 | 1000)) | |
9b6de0a1 VS |
1826 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1827 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1828 | } |
1829 | ||
b8a4f404 PZ |
1830 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1831 | enum pipe pipe) | |
040484af | 1832 | { |
23670b32 | 1833 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1834 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1835 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1836 | i915_reg_t reg; |
1837 | uint32_t val, pipeconf_val; | |
040484af | 1838 | |
040484af | 1839 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1840 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1841 | |
1842 | /* FDI must be feeding us bits for PCH ports */ | |
1843 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1844 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1845 | ||
23670b32 DV |
1846 | if (HAS_PCH_CPT(dev)) { |
1847 | /* Workaround: Set the timing override bit before enabling the | |
1848 | * pch transcoder. */ | |
1849 | reg = TRANS_CHICKEN2(pipe); | |
1850 | val = I915_READ(reg); | |
1851 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1852 | I915_WRITE(reg, val); | |
59c859d6 | 1853 | } |
23670b32 | 1854 | |
ab9412ba | 1855 | reg = PCH_TRANSCONF(pipe); |
040484af | 1856 | val = I915_READ(reg); |
5f7f726d | 1857 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1858 | |
2d1fe073 | 1859 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1860 | /* |
c5de7c6f VS |
1861 | * Make the BPC in transcoder be consistent with |
1862 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1863 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1864 | */ |
dfd07d72 | 1865 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1866 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1867 | val |= PIPECONF_8BPC; | |
1868 | else | |
1869 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1870 | } |
5f7f726d PZ |
1871 | |
1872 | val &= ~TRANS_INTERLACE_MASK; | |
1873 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1874 | if (HAS_PCH_IBX(dev_priv) && |
409ee761 | 1875 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1876 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1877 | else | |
1878 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1879 | else |
1880 | val |= TRANS_PROGRESSIVE; | |
1881 | ||
040484af | 1882 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1883 | if (intel_wait_for_register(dev_priv, |
1884 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1885 | 100)) | |
4bb6f1f3 | 1886 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1887 | } |
1888 | ||
8fb033d7 | 1889 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1890 | enum transcoder cpu_transcoder) |
040484af | 1891 | { |
8fb033d7 | 1892 | u32 val, pipeconf_val; |
8fb033d7 | 1893 | |
8fb033d7 | 1894 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1895 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1896 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1897 | |
223a6fdf | 1898 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1899 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1900 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1901 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1902 | |
25f3ef11 | 1903 | val = TRANS_ENABLE; |
937bb610 | 1904 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1905 | |
9a76b1c6 PZ |
1906 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1907 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1908 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1909 | else |
1910 | val |= TRANS_PROGRESSIVE; | |
1911 | ||
ab9412ba | 1912 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1913 | if (intel_wait_for_register(dev_priv, |
1914 | LPT_TRANSCONF, | |
1915 | TRANS_STATE_ENABLE, | |
1916 | TRANS_STATE_ENABLE, | |
1917 | 100)) | |
937bb610 | 1918 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1919 | } |
1920 | ||
b8a4f404 PZ |
1921 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1922 | enum pipe pipe) | |
040484af | 1923 | { |
23670b32 | 1924 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
1925 | i915_reg_t reg; |
1926 | uint32_t val; | |
040484af JB |
1927 | |
1928 | /* FDI relies on the transcoder */ | |
1929 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1930 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1931 | ||
291906f1 JB |
1932 | /* Ports must be off as well */ |
1933 | assert_pch_ports_disabled(dev_priv, pipe); | |
1934 | ||
ab9412ba | 1935 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1936 | val = I915_READ(reg); |
1937 | val &= ~TRANS_ENABLE; | |
1938 | I915_WRITE(reg, val); | |
1939 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1940 | if (intel_wait_for_register(dev_priv, |
1941 | reg, TRANS_STATE_ENABLE, 0, | |
1942 | 50)) | |
4bb6f1f3 | 1943 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1944 | |
c465613b | 1945 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1946 | /* Workaround: Clear the timing override chicken bit again. */ |
1947 | reg = TRANS_CHICKEN2(pipe); | |
1948 | val = I915_READ(reg); | |
1949 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1950 | I915_WRITE(reg, val); | |
1951 | } | |
040484af JB |
1952 | } |
1953 | ||
ab4d966c | 1954 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1955 | { |
8fb033d7 PZ |
1956 | u32 val; |
1957 | ||
ab9412ba | 1958 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1959 | val &= ~TRANS_ENABLE; |
ab9412ba | 1960 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1961 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1962 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1963 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1964 | |
1965 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1966 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1967 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1968 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1969 | } |
1970 | ||
b24e7179 | 1971 | /** |
309cfea8 | 1972 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1973 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1974 | * |
0372264a | 1975 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1976 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1977 | */ |
e1fdc473 | 1978 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1979 | { |
0372264a PZ |
1980 | struct drm_device *dev = crtc->base.dev; |
1981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1982 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 1983 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1984 | enum pipe pch_transcoder; |
f0f59a00 | 1985 | i915_reg_t reg; |
b24e7179 JB |
1986 | u32 val; |
1987 | ||
9e2ee2dd VS |
1988 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1989 | ||
58c6eaa2 | 1990 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1991 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1992 | assert_sprites_disabled(dev_priv, pipe); |
1993 | ||
2d1fe073 | 1994 | if (HAS_PCH_LPT(dev_priv)) |
cc391bbb PZ |
1995 | pch_transcoder = TRANSCODER_A; |
1996 | else | |
1997 | pch_transcoder = pipe; | |
1998 | ||
b24e7179 JB |
1999 | /* |
2000 | * A pipe without a PLL won't actually be able to drive bits from | |
2001 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2002 | * need the check. | |
2003 | */ | |
2d1fe073 | 2004 | if (HAS_GMCH_DISPLAY(dev_priv)) |
a65347ba | 2005 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2006 | assert_dsi_pll_enabled(dev_priv); |
2007 | else | |
2008 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2009 | else { |
6e3c9717 | 2010 | if (crtc->config->has_pch_encoder) { |
040484af | 2011 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2012 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2013 | assert_fdi_tx_pll_enabled(dev_priv, |
2014 | (enum pipe) cpu_transcoder); | |
040484af JB |
2015 | } |
2016 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2017 | } | |
b24e7179 | 2018 | |
702e7a56 | 2019 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2020 | val = I915_READ(reg); |
7ad25d48 | 2021 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2022 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2023 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2024 | return; |
7ad25d48 | 2025 | } |
00d70b15 CW |
2026 | |
2027 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2028 | POSTING_READ(reg); |
b7792d8b VS |
2029 | |
2030 | /* | |
2031 | * Until the pipe starts DSL will read as 0, which would cause | |
2032 | * an apparent vblank timestamp jump, which messes up also the | |
2033 | * frame count when it's derived from the timestamps. So let's | |
2034 | * wait for the pipe to start properly before we call | |
2035 | * drm_crtc_vblank_on() | |
2036 | */ | |
2037 | if (dev->max_vblank_count == 0 && | |
2038 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2039 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2040 | } |
2041 | ||
2042 | /** | |
309cfea8 | 2043 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2044 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2045 | * |
575f7ab7 VS |
2046 | * Disable the pipe of @crtc, making sure that various hardware |
2047 | * specific requirements are met, if applicable, e.g. plane | |
2048 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2049 | * |
2050 | * Will wait until the pipe has shut down before returning. | |
2051 | */ | |
575f7ab7 | 2052 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2053 | { |
575f7ab7 | 2054 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2055 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2056 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2057 | i915_reg_t reg; |
b24e7179 JB |
2058 | u32 val; |
2059 | ||
9e2ee2dd VS |
2060 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2061 | ||
b24e7179 JB |
2062 | /* |
2063 | * Make sure planes won't keep trying to pump pixels to us, | |
2064 | * or we might hang the display. | |
2065 | */ | |
2066 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2067 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2068 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2069 | |
702e7a56 | 2070 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2071 | val = I915_READ(reg); |
00d70b15 CW |
2072 | if ((val & PIPECONF_ENABLE) == 0) |
2073 | return; | |
2074 | ||
67adc644 VS |
2075 | /* |
2076 | * Double wide has implications for planes | |
2077 | * so best keep it disabled when not needed. | |
2078 | */ | |
6e3c9717 | 2079 | if (crtc->config->double_wide) |
67adc644 VS |
2080 | val &= ~PIPECONF_DOUBLE_WIDE; |
2081 | ||
2082 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2083 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2084 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2085 | val &= ~PIPECONF_ENABLE; |
2086 | ||
2087 | I915_WRITE(reg, val); | |
2088 | if ((val & PIPECONF_ENABLE) == 0) | |
2089 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2090 | } |
2091 | ||
693db184 CW |
2092 | static bool need_vtd_wa(struct drm_device *dev) |
2093 | { | |
2094 | #ifdef CONFIG_INTEL_IOMMU | |
2095 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2096 | return true; | |
2097 | #endif | |
2098 | return false; | |
2099 | } | |
2100 | ||
832be82f VS |
2101 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2102 | { | |
2103 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2104 | } | |
2105 | ||
27ba3910 VS |
2106 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2107 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2108 | { |
2109 | switch (fb_modifier) { | |
2110 | case DRM_FORMAT_MOD_NONE: | |
2111 | return cpp; | |
2112 | case I915_FORMAT_MOD_X_TILED: | |
2113 | if (IS_GEN2(dev_priv)) | |
2114 | return 128; | |
2115 | else | |
2116 | return 512; | |
2117 | case I915_FORMAT_MOD_Y_TILED: | |
2118 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2119 | return 128; | |
2120 | else | |
2121 | return 512; | |
2122 | case I915_FORMAT_MOD_Yf_TILED: | |
2123 | switch (cpp) { | |
2124 | case 1: | |
2125 | return 64; | |
2126 | case 2: | |
2127 | case 4: | |
2128 | return 128; | |
2129 | case 8: | |
2130 | case 16: | |
2131 | return 256; | |
2132 | default: | |
2133 | MISSING_CASE(cpp); | |
2134 | return cpp; | |
2135 | } | |
2136 | break; | |
2137 | default: | |
2138 | MISSING_CASE(fb_modifier); | |
2139 | return cpp; | |
2140 | } | |
2141 | } | |
2142 | ||
832be82f VS |
2143 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2144 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2145 | { |
832be82f VS |
2146 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2147 | return 1; | |
2148 | else | |
2149 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2150 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2151 | } |
2152 | ||
8d0deca8 VS |
2153 | /* Return the tile dimensions in pixel units */ |
2154 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2155 | unsigned int *tile_width, | |
2156 | unsigned int *tile_height, | |
2157 | uint64_t fb_modifier, | |
2158 | unsigned int cpp) | |
2159 | { | |
2160 | unsigned int tile_width_bytes = | |
2161 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2162 | ||
2163 | *tile_width = tile_width_bytes / cpp; | |
2164 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2165 | } | |
2166 | ||
6761dd31 TU |
2167 | unsigned int |
2168 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2169 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2170 | { |
832be82f VS |
2171 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2172 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2173 | ||
2174 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2175 | } |
2176 | ||
1663b9d6 VS |
2177 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2178 | { | |
2179 | unsigned int size = 0; | |
2180 | int i; | |
2181 | ||
2182 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2183 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2184 | ||
2185 | return size; | |
2186 | } | |
2187 | ||
75c82a53 | 2188 | static void |
3465c580 VS |
2189 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2190 | const struct drm_framebuffer *fb, | |
2191 | unsigned int rotation) | |
f64b98cd | 2192 | { |
2d7a215f VS |
2193 | if (intel_rotation_90_or_270(rotation)) { |
2194 | *view = i915_ggtt_view_rotated; | |
2195 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2196 | } else { | |
2197 | *view = i915_ggtt_view_normal; | |
2198 | } | |
2199 | } | |
50470bb0 | 2200 | |
2d7a215f VS |
2201 | static void |
2202 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2203 | struct drm_framebuffer *fb) | |
2204 | { | |
2205 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2206 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2207 | |
d9b3288e VS |
2208 | tile_size = intel_tile_size(dev_priv); |
2209 | ||
2210 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2211 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2212 | fb->modifier[0], cpp); | |
d9b3288e | 2213 | |
1663b9d6 VS |
2214 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2215 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2216 | |
89e3e142 | 2217 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2218 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2219 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2220 | fb->modifier[1], cpp); | |
d9b3288e | 2221 | |
2d7a215f | 2222 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2223 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2224 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2225 | } |
f64b98cd TU |
2226 | } |
2227 | ||
603525d7 | 2228 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2229 | { |
2230 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2231 | return 256 * 1024; | |
985b8bb4 | 2232 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2233 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2234 | return 128 * 1024; |
2235 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2236 | return 4 * 1024; | |
2237 | else | |
44c5905e | 2238 | return 0; |
4e9a86b6 VS |
2239 | } |
2240 | ||
603525d7 VS |
2241 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2242 | uint64_t fb_modifier) | |
2243 | { | |
2244 | switch (fb_modifier) { | |
2245 | case DRM_FORMAT_MOD_NONE: | |
2246 | return intel_linear_alignment(dev_priv); | |
2247 | case I915_FORMAT_MOD_X_TILED: | |
2248 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2249 | return 256 * 1024; | |
2250 | return 0; | |
2251 | case I915_FORMAT_MOD_Y_TILED: | |
2252 | case I915_FORMAT_MOD_Yf_TILED: | |
2253 | return 1 * 1024 * 1024; | |
2254 | default: | |
2255 | MISSING_CASE(fb_modifier); | |
2256 | return 0; | |
2257 | } | |
2258 | } | |
2259 | ||
127bd2ac | 2260 | int |
3465c580 VS |
2261 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2262 | unsigned int rotation) | |
6b95a207 | 2263 | { |
850c4cdc | 2264 | struct drm_device *dev = fb->dev; |
ce453d81 | 2265 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2266 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2267 | struct i915_ggtt_view view; |
6b95a207 KH |
2268 | u32 alignment; |
2269 | int ret; | |
2270 | ||
ebcdd39e MR |
2271 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2272 | ||
603525d7 | 2273 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2274 | |
3465c580 | 2275 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2276 | |
693db184 CW |
2277 | /* Note that the w/a also requires 64 PTE of padding following the |
2278 | * bo. We currently fill all unused PTE with the shadow page and so | |
2279 | * we should always have valid PTE following the scanout preventing | |
2280 | * the VT-d warning. | |
2281 | */ | |
2282 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2283 | alignment = 256 * 1024; | |
2284 | ||
d6dd6843 PZ |
2285 | /* |
2286 | * Global gtt pte registers are special registers which actually forward | |
2287 | * writes to a chunk of system memory. Which means that there is no risk | |
2288 | * that the register values disappear as soon as we call | |
2289 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2290 | * pin/unpin/fence and not more. | |
2291 | */ | |
2292 | intel_runtime_pm_get(dev_priv); | |
2293 | ||
7580d774 ML |
2294 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2295 | &view); | |
48b956c5 | 2296 | if (ret) |
b26a6b35 | 2297 | goto err_pm; |
6b95a207 KH |
2298 | |
2299 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2300 | * fence, whereas 965+ only requires a fence if using | |
2301 | * framebuffer compression. For simplicity, we always install | |
2302 | * a fence as the cost is not that onerous. | |
2303 | */ | |
9807216f VK |
2304 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2305 | ret = i915_gem_object_get_fence(obj); | |
2306 | if (ret == -EDEADLK) { | |
2307 | /* | |
2308 | * -EDEADLK means there are no free fences | |
2309 | * no pending flips. | |
2310 | * | |
2311 | * This is propagated to atomic, but it uses | |
2312 | * -EDEADLK to force a locking recovery, so | |
2313 | * change the returned error to -EBUSY. | |
2314 | */ | |
2315 | ret = -EBUSY; | |
2316 | goto err_unpin; | |
2317 | } else if (ret) | |
2318 | goto err_unpin; | |
1690e1eb | 2319 | |
9807216f VK |
2320 | i915_gem_object_pin_fence(obj); |
2321 | } | |
6b95a207 | 2322 | |
d6dd6843 | 2323 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2324 | return 0; |
48b956c5 CW |
2325 | |
2326 | err_unpin: | |
f64b98cd | 2327 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2328 | err_pm: |
d6dd6843 | 2329 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2330 | return ret; |
6b95a207 KH |
2331 | } |
2332 | ||
fb4b8ce1 | 2333 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2334 | { |
82bc3b2d | 2335 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2336 | struct i915_ggtt_view view; |
82bc3b2d | 2337 | |
ebcdd39e MR |
2338 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2339 | ||
3465c580 | 2340 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2341 | |
9807216f VK |
2342 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2343 | i915_gem_object_unpin_fence(obj); | |
2344 | ||
f64b98cd | 2345 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2346 | } |
2347 | ||
29cf9491 VS |
2348 | /* |
2349 | * Adjust the tile offset by moving the difference into | |
2350 | * the x/y offsets. | |
2351 | * | |
2352 | * Input tile dimensions and pitch must already be | |
2353 | * rotated to match x and y, and in pixel units. | |
2354 | */ | |
2355 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2356 | unsigned int tile_width, | |
2357 | unsigned int tile_height, | |
2358 | unsigned int tile_size, | |
2359 | unsigned int pitch_tiles, | |
2360 | u32 old_offset, | |
2361 | u32 new_offset) | |
2362 | { | |
2363 | unsigned int tiles; | |
2364 | ||
2365 | WARN_ON(old_offset & (tile_size - 1)); | |
2366 | WARN_ON(new_offset & (tile_size - 1)); | |
2367 | WARN_ON(new_offset > old_offset); | |
2368 | ||
2369 | tiles = (old_offset - new_offset) / tile_size; | |
2370 | ||
2371 | *y += tiles / pitch_tiles * tile_height; | |
2372 | *x += tiles % pitch_tiles * tile_width; | |
2373 | ||
2374 | return new_offset; | |
2375 | } | |
2376 | ||
8d0deca8 VS |
2377 | /* |
2378 | * Computes the linear offset to the base tile and adjusts | |
2379 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2380 | * | |
2381 | * In the 90/270 rotated case, x and y are assumed | |
2382 | * to be already rotated to match the rotated GTT view, and | |
2383 | * pitch is the tile_height aligned framebuffer height. | |
2384 | */ | |
4f2d9934 VS |
2385 | u32 intel_compute_tile_offset(int *x, int *y, |
2386 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2387 | unsigned int pitch, |
2388 | unsigned int rotation) | |
c2c75131 | 2389 | { |
4f2d9934 VS |
2390 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2391 | uint64_t fb_modifier = fb->modifier[plane]; | |
2392 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2393 | u32 offset, offset_aligned, alignment; |
2394 | ||
2395 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2396 | if (alignment) | |
2397 | alignment--; | |
2398 | ||
b5c65338 | 2399 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2400 | unsigned int tile_size, tile_width, tile_height; |
2401 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2402 | |
d843310d | 2403 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2404 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2405 | fb_modifier, cpp); | |
2406 | ||
2407 | if (intel_rotation_90_or_270(rotation)) { | |
2408 | pitch_tiles = pitch / tile_height; | |
2409 | swap(tile_width, tile_height); | |
2410 | } else { | |
2411 | pitch_tiles = pitch / (tile_width * cpp); | |
2412 | } | |
d843310d VS |
2413 | |
2414 | tile_rows = *y / tile_height; | |
2415 | *y %= tile_height; | |
c2c75131 | 2416 | |
8d0deca8 VS |
2417 | tiles = *x / tile_width; |
2418 | *x %= tile_width; | |
bc752862 | 2419 | |
29cf9491 VS |
2420 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2421 | offset_aligned = offset & ~alignment; | |
bc752862 | 2422 | |
29cf9491 VS |
2423 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2424 | tile_size, pitch_tiles, | |
2425 | offset, offset_aligned); | |
2426 | } else { | |
bc752862 | 2427 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2428 | offset_aligned = offset & ~alignment; |
2429 | ||
4e9a86b6 VS |
2430 | *y = (offset & alignment) / pitch; |
2431 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2432 | } |
29cf9491 VS |
2433 | |
2434 | return offset_aligned; | |
c2c75131 DV |
2435 | } |
2436 | ||
b35d63fa | 2437 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2438 | { |
2439 | switch (format) { | |
2440 | case DISPPLANE_8BPP: | |
2441 | return DRM_FORMAT_C8; | |
2442 | case DISPPLANE_BGRX555: | |
2443 | return DRM_FORMAT_XRGB1555; | |
2444 | case DISPPLANE_BGRX565: | |
2445 | return DRM_FORMAT_RGB565; | |
2446 | default: | |
2447 | case DISPPLANE_BGRX888: | |
2448 | return DRM_FORMAT_XRGB8888; | |
2449 | case DISPPLANE_RGBX888: | |
2450 | return DRM_FORMAT_XBGR8888; | |
2451 | case DISPPLANE_BGRX101010: | |
2452 | return DRM_FORMAT_XRGB2101010; | |
2453 | case DISPPLANE_RGBX101010: | |
2454 | return DRM_FORMAT_XBGR2101010; | |
2455 | } | |
2456 | } | |
2457 | ||
bc8d7dff DL |
2458 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2459 | { | |
2460 | switch (format) { | |
2461 | case PLANE_CTL_FORMAT_RGB_565: | |
2462 | return DRM_FORMAT_RGB565; | |
2463 | default: | |
2464 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2465 | if (rgb_order) { | |
2466 | if (alpha) | |
2467 | return DRM_FORMAT_ABGR8888; | |
2468 | else | |
2469 | return DRM_FORMAT_XBGR8888; | |
2470 | } else { | |
2471 | if (alpha) | |
2472 | return DRM_FORMAT_ARGB8888; | |
2473 | else | |
2474 | return DRM_FORMAT_XRGB8888; | |
2475 | } | |
2476 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2477 | if (rgb_order) | |
2478 | return DRM_FORMAT_XBGR2101010; | |
2479 | else | |
2480 | return DRM_FORMAT_XRGB2101010; | |
2481 | } | |
2482 | } | |
2483 | ||
5724dbd1 | 2484 | static bool |
f6936e29 DV |
2485 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2486 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2487 | { |
2488 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2489 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2490 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2491 | struct drm_i915_gem_object *obj = NULL; |
2492 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2493 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2494 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2495 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2496 | PAGE_SIZE); | |
2497 | ||
2498 | size_aligned -= base_aligned; | |
46f297fb | 2499 | |
ff2652ea CW |
2500 | if (plane_config->size == 0) |
2501 | return false; | |
2502 | ||
3badb49f PZ |
2503 | /* If the FB is too big, just don't use it since fbdev is not very |
2504 | * important and we should probably use that space with FBC or other | |
2505 | * features. */ | |
72e96d64 | 2506 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2507 | return false; |
2508 | ||
12c83d99 TU |
2509 | mutex_lock(&dev->struct_mutex); |
2510 | ||
f37b5c2b DV |
2511 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2512 | base_aligned, | |
2513 | base_aligned, | |
2514 | size_aligned); | |
12c83d99 TU |
2515 | if (!obj) { |
2516 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2517 | return false; |
12c83d99 | 2518 | } |
46f297fb | 2519 | |
49af449b DL |
2520 | obj->tiling_mode = plane_config->tiling; |
2521 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2522 | obj->stride = fb->pitches[0]; |
46f297fb | 2523 | |
6bf129df DL |
2524 | mode_cmd.pixel_format = fb->pixel_format; |
2525 | mode_cmd.width = fb->width; | |
2526 | mode_cmd.height = fb->height; | |
2527 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2528 | mode_cmd.modifier[0] = fb->modifier[0]; |
2529 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2530 | |
6bf129df | 2531 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2532 | &mode_cmd, obj)) { |
46f297fb JB |
2533 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2534 | goto out_unref_obj; | |
2535 | } | |
12c83d99 | 2536 | |
46f297fb | 2537 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2538 | |
f6936e29 | 2539 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2540 | return true; |
46f297fb JB |
2541 | |
2542 | out_unref_obj: | |
2543 | drm_gem_object_unreference(&obj->base); | |
2544 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2545 | return false; |
2546 | } | |
2547 | ||
5a21b665 DV |
2548 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2549 | static void | |
2550 | update_state_fb(struct drm_plane *plane) | |
2551 | { | |
2552 | if (plane->fb == plane->state->fb) | |
2553 | return; | |
2554 | ||
2555 | if (plane->state->fb) | |
2556 | drm_framebuffer_unreference(plane->state->fb); | |
2557 | plane->state->fb = plane->fb; | |
2558 | if (plane->state->fb) | |
2559 | drm_framebuffer_reference(plane->state->fb); | |
2560 | } | |
2561 | ||
5724dbd1 | 2562 | static void |
f6936e29 DV |
2563 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2564 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2565 | { |
2566 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2567 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2568 | struct drm_crtc *c; |
2569 | struct intel_crtc *i; | |
2ff8fde1 | 2570 | struct drm_i915_gem_object *obj; |
88595ac9 | 2571 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2572 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2573 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2574 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2575 | struct intel_plane_state *intel_state = |
2576 | to_intel_plane_state(plane_state); | |
88595ac9 | 2577 | struct drm_framebuffer *fb; |
484b41dd | 2578 | |
2d14030b | 2579 | if (!plane_config->fb) |
484b41dd JB |
2580 | return; |
2581 | ||
f6936e29 | 2582 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2583 | fb = &plane_config->fb->base; |
2584 | goto valid_fb; | |
f55548b5 | 2585 | } |
484b41dd | 2586 | |
2d14030b | 2587 | kfree(plane_config->fb); |
484b41dd JB |
2588 | |
2589 | /* | |
2590 | * Failed to alloc the obj, check to see if we should share | |
2591 | * an fb with another CRTC instead | |
2592 | */ | |
70e1e0ec | 2593 | for_each_crtc(dev, c) { |
484b41dd JB |
2594 | i = to_intel_crtc(c); |
2595 | ||
2596 | if (c == &intel_crtc->base) | |
2597 | continue; | |
2598 | ||
2ff8fde1 MR |
2599 | if (!i->active) |
2600 | continue; | |
2601 | ||
88595ac9 DV |
2602 | fb = c->primary->fb; |
2603 | if (!fb) | |
484b41dd JB |
2604 | continue; |
2605 | ||
88595ac9 | 2606 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2607 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2608 | drm_framebuffer_reference(fb); |
2609 | goto valid_fb; | |
484b41dd JB |
2610 | } |
2611 | } | |
88595ac9 | 2612 | |
200757f5 MR |
2613 | /* |
2614 | * We've failed to reconstruct the BIOS FB. Current display state | |
2615 | * indicates that the primary plane is visible, but has a NULL FB, | |
2616 | * which will lead to problems later if we don't fix it up. The | |
2617 | * simplest solution is to just disable the primary plane now and | |
2618 | * pretend the BIOS never had it enabled. | |
2619 | */ | |
2620 | to_intel_plane_state(plane_state)->visible = false; | |
2621 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2622 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2623 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2624 | ||
88595ac9 DV |
2625 | return; |
2626 | ||
2627 | valid_fb: | |
f44e2659 VS |
2628 | plane_state->src_x = 0; |
2629 | plane_state->src_y = 0; | |
be5651f2 ML |
2630 | plane_state->src_w = fb->width << 16; |
2631 | plane_state->src_h = fb->height << 16; | |
2632 | ||
f44e2659 VS |
2633 | plane_state->crtc_x = 0; |
2634 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2635 | plane_state->crtc_w = fb->width; |
2636 | plane_state->crtc_h = fb->height; | |
2637 | ||
0a8d8a86 MR |
2638 | intel_state->src.x1 = plane_state->src_x; |
2639 | intel_state->src.y1 = plane_state->src_y; | |
2640 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2641 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2642 | intel_state->dst.x1 = plane_state->crtc_x; | |
2643 | intel_state->dst.y1 = plane_state->crtc_y; | |
2644 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2645 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2646 | ||
88595ac9 DV |
2647 | obj = intel_fb_obj(fb); |
2648 | if (obj->tiling_mode != I915_TILING_NONE) | |
2649 | dev_priv->preserve_bios_swizzle = true; | |
2650 | ||
be5651f2 ML |
2651 | drm_framebuffer_reference(fb); |
2652 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2653 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2654 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2655 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2656 | } |
2657 | ||
a8d201af ML |
2658 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2659 | const struct intel_crtc_state *crtc_state, | |
2660 | const struct intel_plane_state *plane_state) | |
81255565 | 2661 | { |
a8d201af | 2662 | struct drm_device *dev = primary->dev; |
81255565 | 2663 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2664 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2665 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2666 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2667 | int plane = intel_crtc->plane; |
54ea9da8 | 2668 | u32 linear_offset; |
81255565 | 2669 | u32 dspcntr; |
f0f59a00 | 2670 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2671 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2672 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2673 | int x = plane_state->src.x1 >> 16; |
2674 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2675 | |
f45651ba VS |
2676 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2677 | ||
fdd508a6 | 2678 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2679 | |
2680 | if (INTEL_INFO(dev)->gen < 4) { | |
2681 | if (intel_crtc->pipe == PIPE_B) | |
2682 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2683 | ||
2684 | /* pipesrc and dspsize control the size that is scaled from, | |
2685 | * which should always be the user's requested size. | |
2686 | */ | |
2687 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2688 | ((crtc_state->pipe_src_h - 1) << 16) | |
2689 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2690 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2691 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2692 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2693 | ((crtc_state->pipe_src_h - 1) << 16) | |
2694 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2695 | I915_WRITE(PRIMPOS(plane), 0); |
2696 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2697 | } |
81255565 | 2698 | |
57779d06 VS |
2699 | switch (fb->pixel_format) { |
2700 | case DRM_FORMAT_C8: | |
81255565 JB |
2701 | dspcntr |= DISPPLANE_8BPP; |
2702 | break; | |
57779d06 | 2703 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2704 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2705 | break; |
57779d06 VS |
2706 | case DRM_FORMAT_RGB565: |
2707 | dspcntr |= DISPPLANE_BGRX565; | |
2708 | break; | |
2709 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2710 | dspcntr |= DISPPLANE_BGRX888; |
2711 | break; | |
2712 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2713 | dspcntr |= DISPPLANE_RGBX888; |
2714 | break; | |
2715 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2716 | dspcntr |= DISPPLANE_BGRX101010; |
2717 | break; | |
2718 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2719 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2720 | break; |
2721 | default: | |
baba133a | 2722 | BUG(); |
81255565 | 2723 | } |
57779d06 | 2724 | |
f45651ba VS |
2725 | if (INTEL_INFO(dev)->gen >= 4 && |
2726 | obj->tiling_mode != I915_TILING_NONE) | |
2727 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2728 | |
de1aa629 VS |
2729 | if (IS_G4X(dev)) |
2730 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2731 | ||
ac484963 | 2732 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2733 | |
c2c75131 DV |
2734 | if (INTEL_INFO(dev)->gen >= 4) { |
2735 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2736 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2737 | fb->pitches[0], rotation); |
c2c75131 DV |
2738 | linear_offset -= intel_crtc->dspaddr_offset; |
2739 | } else { | |
e506a0c6 | 2740 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2741 | } |
e506a0c6 | 2742 | |
8d0deca8 | 2743 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2744 | dspcntr |= DISPPLANE_ROTATE_180; |
2745 | ||
a8d201af ML |
2746 | x += (crtc_state->pipe_src_w - 1); |
2747 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2748 | |
2749 | /* Finding the last pixel of the last line of the display | |
2750 | data and adding to linear_offset*/ | |
2751 | linear_offset += | |
a8d201af | 2752 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2753 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2754 | } |
2755 | ||
2db3366b PZ |
2756 | intel_crtc->adjusted_x = x; |
2757 | intel_crtc->adjusted_y = y; | |
2758 | ||
48404c1e SJ |
2759 | I915_WRITE(reg, dspcntr); |
2760 | ||
01f2c773 | 2761 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2762 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2763 | I915_WRITE(DSPSURF(plane), |
2764 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2765 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2766 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2767 | } else |
f343c5f6 | 2768 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2769 | POSTING_READ(reg); |
17638cd6 JB |
2770 | } |
2771 | ||
a8d201af ML |
2772 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2773 | struct drm_crtc *crtc) | |
17638cd6 JB |
2774 | { |
2775 | struct drm_device *dev = crtc->dev; | |
2776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2778 | int plane = intel_crtc->plane; |
f45651ba | 2779 | |
a8d201af ML |
2780 | I915_WRITE(DSPCNTR(plane), 0); |
2781 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2782 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2783 | else |
2784 | I915_WRITE(DSPADDR(plane), 0); | |
2785 | POSTING_READ(DSPCNTR(plane)); | |
2786 | } | |
c9ba6fad | 2787 | |
a8d201af ML |
2788 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2789 | const struct intel_crtc_state *crtc_state, | |
2790 | const struct intel_plane_state *plane_state) | |
2791 | { | |
2792 | struct drm_device *dev = primary->dev; | |
2793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2794 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2795 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2796 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2797 | int plane = intel_crtc->plane; | |
54ea9da8 | 2798 | u32 linear_offset; |
a8d201af ML |
2799 | u32 dspcntr; |
2800 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2801 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2802 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2803 | int x = plane_state->src.x1 >> 16; |
2804 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2805 | |
f45651ba | 2806 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2807 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2808 | |
2809 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2810 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2811 | |
57779d06 VS |
2812 | switch (fb->pixel_format) { |
2813 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2814 | dspcntr |= DISPPLANE_8BPP; |
2815 | break; | |
57779d06 VS |
2816 | case DRM_FORMAT_RGB565: |
2817 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2818 | break; |
57779d06 | 2819 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2820 | dspcntr |= DISPPLANE_BGRX888; |
2821 | break; | |
2822 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2823 | dspcntr |= DISPPLANE_RGBX888; |
2824 | break; | |
2825 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2826 | dspcntr |= DISPPLANE_BGRX101010; |
2827 | break; | |
2828 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2829 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2830 | break; |
2831 | default: | |
baba133a | 2832 | BUG(); |
17638cd6 JB |
2833 | } |
2834 | ||
2835 | if (obj->tiling_mode != I915_TILING_NONE) | |
2836 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2837 | |
f45651ba | 2838 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2839 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2840 | |
ac484963 | 2841 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2842 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2843 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2844 | fb->pitches[0], rotation); |
c2c75131 | 2845 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2846 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2847 | dspcntr |= DISPPLANE_ROTATE_180; |
2848 | ||
2849 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2850 | x += (crtc_state->pipe_src_w - 1); |
2851 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2852 | |
2853 | /* Finding the last pixel of the last line of the display | |
2854 | data and adding to linear_offset*/ | |
2855 | linear_offset += | |
a8d201af | 2856 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2857 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2858 | } |
2859 | } | |
2860 | ||
2db3366b PZ |
2861 | intel_crtc->adjusted_x = x; |
2862 | intel_crtc->adjusted_y = y; | |
2863 | ||
48404c1e | 2864 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2865 | |
01f2c773 | 2866 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2867 | I915_WRITE(DSPSURF(plane), |
2868 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2869 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2870 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2871 | } else { | |
2872 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2873 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2874 | } | |
17638cd6 | 2875 | POSTING_READ(reg); |
17638cd6 JB |
2876 | } |
2877 | ||
7b49f948 VS |
2878 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2879 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2880 | { |
7b49f948 | 2881 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2882 | return 64; |
7b49f948 VS |
2883 | } else { |
2884 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2885 | ||
27ba3910 | 2886 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2887 | } |
2888 | } | |
2889 | ||
44eb0cb9 MK |
2890 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2891 | struct drm_i915_gem_object *obj, | |
2892 | unsigned int plane) | |
121920fa | 2893 | { |
ce7f1728 | 2894 | struct i915_ggtt_view view; |
dedf278c | 2895 | struct i915_vma *vma; |
44eb0cb9 | 2896 | u64 offset; |
121920fa | 2897 | |
e7941294 | 2898 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 2899 | intel_plane->base.state->rotation); |
121920fa | 2900 | |
ce7f1728 | 2901 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2902 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2903 | view.type)) |
dedf278c TU |
2904 | return -1; |
2905 | ||
44eb0cb9 | 2906 | offset = vma->node.start; |
dedf278c TU |
2907 | |
2908 | if (plane == 1) { | |
7723f47d | 2909 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2910 | PAGE_SIZE; |
2911 | } | |
2912 | ||
44eb0cb9 MK |
2913 | WARN_ON(upper_32_bits(offset)); |
2914 | ||
2915 | return lower_32_bits(offset); | |
121920fa TU |
2916 | } |
2917 | ||
e435d6e5 ML |
2918 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2919 | { | |
2920 | struct drm_device *dev = intel_crtc->base.dev; | |
2921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2922 | ||
2923 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2924 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2925 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2926 | } |
2927 | ||
a1b2278e CK |
2928 | /* |
2929 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2930 | */ | |
0583236e | 2931 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2932 | { |
a1b2278e CK |
2933 | struct intel_crtc_scaler_state *scaler_state; |
2934 | int i; | |
2935 | ||
a1b2278e CK |
2936 | scaler_state = &intel_crtc->config->scaler_state; |
2937 | ||
2938 | /* loop through and disable scalers that aren't in use */ | |
2939 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2940 | if (!scaler_state->scalers[i].in_use) |
2941 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2942 | } |
2943 | } | |
2944 | ||
6156a456 | 2945 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2946 | { |
6156a456 | 2947 | switch (pixel_format) { |
d161cf7a | 2948 | case DRM_FORMAT_C8: |
c34ce3d1 | 2949 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2950 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2951 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2952 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2953 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2954 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2955 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2956 | /* |
2957 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2958 | * to be already pre-multiplied. We need to add a knob (or a different | |
2959 | * DRM_FORMAT) for user-space to configure that. | |
2960 | */ | |
f75fb42a | 2961 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2962 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2963 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2964 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2965 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2966 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2967 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2968 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2969 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2970 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2971 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2972 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2973 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2974 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2975 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2976 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2977 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2978 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2979 | default: |
4249eeef | 2980 | MISSING_CASE(pixel_format); |
70d21f0e | 2981 | } |
8cfcba41 | 2982 | |
c34ce3d1 | 2983 | return 0; |
6156a456 | 2984 | } |
70d21f0e | 2985 | |
6156a456 CK |
2986 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2987 | { | |
6156a456 | 2988 | switch (fb_modifier) { |
30af77c4 | 2989 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2990 | break; |
30af77c4 | 2991 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2992 | return PLANE_CTL_TILED_X; |
b321803d | 2993 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2994 | return PLANE_CTL_TILED_Y; |
b321803d | 2995 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2996 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2997 | default: |
6156a456 | 2998 | MISSING_CASE(fb_modifier); |
70d21f0e | 2999 | } |
8cfcba41 | 3000 | |
c34ce3d1 | 3001 | return 0; |
6156a456 | 3002 | } |
70d21f0e | 3003 | |
6156a456 CK |
3004 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3005 | { | |
3b7a5119 | 3006 | switch (rotation) { |
6156a456 CK |
3007 | case BIT(DRM_ROTATE_0): |
3008 | break; | |
1e8df167 SJ |
3009 | /* |
3010 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3011 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3012 | */ | |
3b7a5119 | 3013 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3014 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3015 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3016 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3017 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3018 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3019 | default: |
3020 | MISSING_CASE(rotation); | |
3021 | } | |
3022 | ||
c34ce3d1 | 3023 | return 0; |
6156a456 CK |
3024 | } |
3025 | ||
a8d201af ML |
3026 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3027 | const struct intel_crtc_state *crtc_state, | |
3028 | const struct intel_plane_state *plane_state) | |
6156a456 | 3029 | { |
a8d201af | 3030 | struct drm_device *dev = plane->dev; |
6156a456 | 3031 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3032 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3033 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3034 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3035 | int pipe = intel_crtc->pipe; |
3036 | u32 plane_ctl, stride_div, stride; | |
3037 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3038 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3039 | int x_offset, y_offset; |
44eb0cb9 | 3040 | u32 surf_addr; |
a8d201af ML |
3041 | int scaler_id = plane_state->scaler_id; |
3042 | int src_x = plane_state->src.x1 >> 16; | |
3043 | int src_y = plane_state->src.y1 >> 16; | |
3044 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3045 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3046 | int dst_x = plane_state->dst.x1; | |
3047 | int dst_y = plane_state->dst.y1; | |
3048 | int dst_w = drm_rect_width(&plane_state->dst); | |
3049 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3050 | |
6156a456 CK |
3051 | plane_ctl = PLANE_CTL_ENABLE | |
3052 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3053 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3054 | ||
3055 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3056 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3057 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3058 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3059 | ||
7b49f948 | 3060 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3061 | fb->pixel_format); |
dedf278c | 3062 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3063 | |
a42e5a23 PZ |
3064 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3065 | ||
3b7a5119 | 3066 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3067 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3068 | ||
3b7a5119 | 3069 | /* stride = Surface height in tiles */ |
832be82f | 3070 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3071 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3072 | x_offset = stride * tile_height - src_y - src_h; |
3073 | y_offset = src_x; | |
6156a456 | 3074 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3075 | } else { |
3076 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3077 | x_offset = src_x; |
3078 | y_offset = src_y; | |
6156a456 | 3079 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3080 | } |
3081 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3082 | |
2db3366b PZ |
3083 | intel_crtc->adjusted_x = x_offset; |
3084 | intel_crtc->adjusted_y = y_offset; | |
3085 | ||
70d21f0e | 3086 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3087 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3088 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3089 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3090 | |
3091 | if (scaler_id >= 0) { | |
3092 | uint32_t ps_ctrl = 0; | |
3093 | ||
3094 | WARN_ON(!dst_w || !dst_h); | |
3095 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3096 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3097 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3098 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3099 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3100 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3101 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3102 | } else { | |
3103 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3104 | } | |
3105 | ||
121920fa | 3106 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3107 | |
3108 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3109 | } | |
3110 | ||
a8d201af ML |
3111 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3112 | struct drm_crtc *crtc) | |
17638cd6 JB |
3113 | { |
3114 | struct drm_device *dev = crtc->dev; | |
3115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3116 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3117 | |
a8d201af ML |
3118 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3119 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3120 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3121 | } | |
29b9bde6 | 3122 | |
a8d201af ML |
3123 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3124 | static int | |
3125 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3126 | int x, int y, enum mode_set_atomic state) | |
3127 | { | |
3128 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3129 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3130 | ||
3131 | return -ENODEV; | |
81255565 JB |
3132 | } |
3133 | ||
5a21b665 DV |
3134 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3135 | { | |
3136 | struct intel_crtc *crtc; | |
3137 | ||
3138 | for_each_intel_crtc(dev_priv->dev, crtc) | |
3139 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); | |
3140 | } | |
3141 | ||
7514747d VS |
3142 | static void intel_update_primary_planes(struct drm_device *dev) |
3143 | { | |
7514747d | 3144 | struct drm_crtc *crtc; |
96a02917 | 3145 | |
70e1e0ec | 3146 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3147 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3148 | struct intel_plane_state *plane_state; | |
96a02917 | 3149 | |
11c22da6 | 3150 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3151 | plane_state = to_intel_plane_state(plane->base.state); |
3152 | ||
a8d201af ML |
3153 | if (plane_state->visible) |
3154 | plane->update_plane(&plane->base, | |
3155 | to_intel_crtc_state(crtc->state), | |
3156 | plane_state); | |
11c22da6 ML |
3157 | |
3158 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3159 | } |
3160 | } | |
3161 | ||
c033666a | 3162 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d VS |
3163 | { |
3164 | /* no reset support for gen2 */ | |
c033666a | 3165 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3166 | return; |
3167 | ||
3168 | /* reset doesn't touch the display */ | |
c033666a | 3169 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
7514747d VS |
3170 | return; |
3171 | ||
c033666a | 3172 | drm_modeset_lock_all(dev_priv->dev); |
f98ce92f VS |
3173 | /* |
3174 | * Disabling the crtcs gracefully seems nicer. Also the | |
3175 | * g33 docs say we should at least disable all the planes. | |
3176 | */ | |
c033666a | 3177 | intel_display_suspend(dev_priv->dev); |
7514747d VS |
3178 | } |
3179 | ||
c033666a | 3180 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3181 | { |
5a21b665 DV |
3182 | /* |
3183 | * Flips in the rings will be nuked by the reset, | |
3184 | * so complete all pending flips so that user space | |
3185 | * will get its events and not get stuck. | |
3186 | */ | |
3187 | intel_complete_page_flips(dev_priv); | |
3188 | ||
7514747d | 3189 | /* no reset support for gen2 */ |
c033666a | 3190 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3191 | return; |
3192 | ||
3193 | /* reset doesn't touch the display */ | |
c033666a | 3194 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
7514747d VS |
3195 | /* |
3196 | * Flips in the rings have been nuked by the reset, | |
3197 | * so update the base address of all primary | |
3198 | * planes to the the last fb to make sure we're | |
3199 | * showing the correct fb after a reset. | |
11c22da6 ML |
3200 | * |
3201 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3202 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d | 3203 | */ |
c033666a | 3204 | intel_update_primary_planes(dev_priv->dev); |
7514747d VS |
3205 | return; |
3206 | } | |
3207 | ||
3208 | /* | |
3209 | * The display has been reset as well, | |
3210 | * so need a full re-initialization. | |
3211 | */ | |
3212 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3213 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3214 | ||
c033666a | 3215 | intel_modeset_init_hw(dev_priv->dev); |
7514747d VS |
3216 | |
3217 | spin_lock_irq(&dev_priv->irq_lock); | |
3218 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 3219 | dev_priv->display.hpd_irq_setup(dev_priv); |
7514747d VS |
3220 | spin_unlock_irq(&dev_priv->irq_lock); |
3221 | ||
c033666a | 3222 | intel_display_resume(dev_priv->dev); |
7514747d VS |
3223 | |
3224 | intel_hpd_init(dev_priv); | |
3225 | ||
c033666a | 3226 | drm_modeset_unlock_all(dev_priv->dev); |
7514747d VS |
3227 | } |
3228 | ||
7d5e3799 CW |
3229 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3230 | { | |
5a21b665 DV |
3231 | struct drm_device *dev = crtc->dev; |
3232 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3233 | unsigned reset_counter; | |
3234 | bool pending; | |
3235 | ||
3236 | reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error); | |
3237 | if (intel_crtc->reset_counter != reset_counter) | |
3238 | return false; | |
3239 | ||
3240 | spin_lock_irq(&dev->event_lock); | |
3241 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3242 | spin_unlock_irq(&dev->event_lock); | |
3243 | ||
3244 | return pending; | |
7d5e3799 CW |
3245 | } |
3246 | ||
bfd16b2a ML |
3247 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3248 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3249 | { |
3250 | struct drm_device *dev = crtc->base.dev; | |
3251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3252 | struct intel_crtc_state *pipe_config = |
3253 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3254 | |
bfd16b2a ML |
3255 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3256 | crtc->base.mode = crtc->base.state->mode; | |
3257 | ||
3258 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3259 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3260 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3261 | |
3262 | /* | |
3263 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3264 | * that in compute_mode_changes we check the native mode (not the pfit | |
3265 | * mode) to see if we can flip rather than do a full mode set. In the | |
3266 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3267 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3268 | * sized surface. | |
e30e8f75 GP |
3269 | */ |
3270 | ||
e30e8f75 | 3271 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3272 | ((pipe_config->pipe_src_w - 1) << 16) | |
3273 | (pipe_config->pipe_src_h - 1)); | |
3274 | ||
3275 | /* on skylake this is done by detaching scalers */ | |
3276 | if (INTEL_INFO(dev)->gen >= 9) { | |
3277 | skl_detach_scalers(crtc); | |
3278 | ||
3279 | if (pipe_config->pch_pfit.enabled) | |
3280 | skylake_pfit_enable(crtc); | |
3281 | } else if (HAS_PCH_SPLIT(dev)) { | |
3282 | if (pipe_config->pch_pfit.enabled) | |
3283 | ironlake_pfit_enable(crtc); | |
3284 | else if (old_crtc_state->pch_pfit.enabled) | |
3285 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3286 | } |
e30e8f75 GP |
3287 | } |
3288 | ||
5e84e1a4 ZW |
3289 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3290 | { | |
3291 | struct drm_device *dev = crtc->dev; | |
3292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3293 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3294 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3295 | i915_reg_t reg; |
3296 | u32 temp; | |
5e84e1a4 ZW |
3297 | |
3298 | /* enable normal train */ | |
3299 | reg = FDI_TX_CTL(pipe); | |
3300 | temp = I915_READ(reg); | |
61e499bf | 3301 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3302 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3303 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3304 | } else { |
3305 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3306 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3307 | } |
5e84e1a4 ZW |
3308 | I915_WRITE(reg, temp); |
3309 | ||
3310 | reg = FDI_RX_CTL(pipe); | |
3311 | temp = I915_READ(reg); | |
3312 | if (HAS_PCH_CPT(dev)) { | |
3313 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3314 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3315 | } else { | |
3316 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3317 | temp |= FDI_LINK_TRAIN_NONE; | |
3318 | } | |
3319 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3320 | ||
3321 | /* wait one idle pattern time */ | |
3322 | POSTING_READ(reg); | |
3323 | udelay(1000); | |
357555c0 JB |
3324 | |
3325 | /* IVB wants error correction enabled */ | |
3326 | if (IS_IVYBRIDGE(dev)) | |
3327 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3328 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3329 | } |
3330 | ||
8db9d77b ZW |
3331 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3332 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3333 | { | |
3334 | struct drm_device *dev = crtc->dev; | |
3335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3336 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3337 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3338 | i915_reg_t reg; |
3339 | u32 temp, tries; | |
8db9d77b | 3340 | |
1c8562f6 | 3341 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3342 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3343 | |
e1a44743 AJ |
3344 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3345 | for train result */ | |
5eddb70b CW |
3346 | reg = FDI_RX_IMR(pipe); |
3347 | temp = I915_READ(reg); | |
e1a44743 AJ |
3348 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3349 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3350 | I915_WRITE(reg, temp); |
3351 | I915_READ(reg); | |
e1a44743 AJ |
3352 | udelay(150); |
3353 | ||
8db9d77b | 3354 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3355 | reg = FDI_TX_CTL(pipe); |
3356 | temp = I915_READ(reg); | |
627eb5a3 | 3357 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3358 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3359 | temp &= ~FDI_LINK_TRAIN_NONE; |
3360 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3361 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3362 | |
5eddb70b CW |
3363 | reg = FDI_RX_CTL(pipe); |
3364 | temp = I915_READ(reg); | |
8db9d77b ZW |
3365 | temp &= ~FDI_LINK_TRAIN_NONE; |
3366 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3367 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3368 | ||
3369 | POSTING_READ(reg); | |
8db9d77b ZW |
3370 | udelay(150); |
3371 | ||
5b2adf89 | 3372 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3373 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3374 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3375 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3376 | |
5eddb70b | 3377 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3378 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3379 | temp = I915_READ(reg); |
8db9d77b ZW |
3380 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3381 | ||
3382 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3383 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3384 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3385 | break; |
3386 | } | |
8db9d77b | 3387 | } |
e1a44743 | 3388 | if (tries == 5) |
5eddb70b | 3389 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3390 | |
3391 | /* Train 2 */ | |
5eddb70b CW |
3392 | reg = FDI_TX_CTL(pipe); |
3393 | temp = I915_READ(reg); | |
8db9d77b ZW |
3394 | temp &= ~FDI_LINK_TRAIN_NONE; |
3395 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3396 | I915_WRITE(reg, temp); |
8db9d77b | 3397 | |
5eddb70b CW |
3398 | reg = FDI_RX_CTL(pipe); |
3399 | temp = I915_READ(reg); | |
8db9d77b ZW |
3400 | temp &= ~FDI_LINK_TRAIN_NONE; |
3401 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3402 | I915_WRITE(reg, temp); |
8db9d77b | 3403 | |
5eddb70b CW |
3404 | POSTING_READ(reg); |
3405 | udelay(150); | |
8db9d77b | 3406 | |
5eddb70b | 3407 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3408 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3409 | temp = I915_READ(reg); |
8db9d77b ZW |
3410 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3411 | ||
3412 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3413 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3414 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3415 | break; | |
3416 | } | |
8db9d77b | 3417 | } |
e1a44743 | 3418 | if (tries == 5) |
5eddb70b | 3419 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3420 | |
3421 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3422 | |
8db9d77b ZW |
3423 | } |
3424 | ||
0206e353 | 3425 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3426 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3427 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3428 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3429 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3430 | }; | |
3431 | ||
3432 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3433 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3434 | { | |
3435 | struct drm_device *dev = crtc->dev; | |
3436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3437 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3438 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3439 | i915_reg_t reg; |
3440 | u32 temp, i, retry; | |
8db9d77b | 3441 | |
e1a44743 AJ |
3442 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3443 | for train result */ | |
5eddb70b CW |
3444 | reg = FDI_RX_IMR(pipe); |
3445 | temp = I915_READ(reg); | |
e1a44743 AJ |
3446 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3447 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3448 | I915_WRITE(reg, temp); |
3449 | ||
3450 | POSTING_READ(reg); | |
e1a44743 AJ |
3451 | udelay(150); |
3452 | ||
8db9d77b | 3453 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3454 | reg = FDI_TX_CTL(pipe); |
3455 | temp = I915_READ(reg); | |
627eb5a3 | 3456 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3457 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3458 | temp &= ~FDI_LINK_TRAIN_NONE; |
3459 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3460 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3461 | /* SNB-B */ | |
3462 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3463 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3464 | |
d74cf324 DV |
3465 | I915_WRITE(FDI_RX_MISC(pipe), |
3466 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3467 | ||
5eddb70b CW |
3468 | reg = FDI_RX_CTL(pipe); |
3469 | temp = I915_READ(reg); | |
8db9d77b ZW |
3470 | if (HAS_PCH_CPT(dev)) { |
3471 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3472 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3473 | } else { | |
3474 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3475 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3476 | } | |
5eddb70b CW |
3477 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3478 | ||
3479 | POSTING_READ(reg); | |
8db9d77b ZW |
3480 | udelay(150); |
3481 | ||
0206e353 | 3482 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3483 | reg = FDI_TX_CTL(pipe); |
3484 | temp = I915_READ(reg); | |
8db9d77b ZW |
3485 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3486 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3487 | I915_WRITE(reg, temp); |
3488 | ||
3489 | POSTING_READ(reg); | |
8db9d77b ZW |
3490 | udelay(500); |
3491 | ||
fa37d39e SP |
3492 | for (retry = 0; retry < 5; retry++) { |
3493 | reg = FDI_RX_IIR(pipe); | |
3494 | temp = I915_READ(reg); | |
3495 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3496 | if (temp & FDI_RX_BIT_LOCK) { | |
3497 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3498 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3499 | break; | |
3500 | } | |
3501 | udelay(50); | |
8db9d77b | 3502 | } |
fa37d39e SP |
3503 | if (retry < 5) |
3504 | break; | |
8db9d77b ZW |
3505 | } |
3506 | if (i == 4) | |
5eddb70b | 3507 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3508 | |
3509 | /* Train 2 */ | |
5eddb70b CW |
3510 | reg = FDI_TX_CTL(pipe); |
3511 | temp = I915_READ(reg); | |
8db9d77b ZW |
3512 | temp &= ~FDI_LINK_TRAIN_NONE; |
3513 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3514 | if (IS_GEN6(dev)) { | |
3515 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3516 | /* SNB-B */ | |
3517 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3518 | } | |
5eddb70b | 3519 | I915_WRITE(reg, temp); |
8db9d77b | 3520 | |
5eddb70b CW |
3521 | reg = FDI_RX_CTL(pipe); |
3522 | temp = I915_READ(reg); | |
8db9d77b ZW |
3523 | if (HAS_PCH_CPT(dev)) { |
3524 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3525 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3526 | } else { | |
3527 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3528 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3529 | } | |
5eddb70b CW |
3530 | I915_WRITE(reg, temp); |
3531 | ||
3532 | POSTING_READ(reg); | |
8db9d77b ZW |
3533 | udelay(150); |
3534 | ||
0206e353 | 3535 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3536 | reg = FDI_TX_CTL(pipe); |
3537 | temp = I915_READ(reg); | |
8db9d77b ZW |
3538 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3539 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3540 | I915_WRITE(reg, temp); |
3541 | ||
3542 | POSTING_READ(reg); | |
8db9d77b ZW |
3543 | udelay(500); |
3544 | ||
fa37d39e SP |
3545 | for (retry = 0; retry < 5; retry++) { |
3546 | reg = FDI_RX_IIR(pipe); | |
3547 | temp = I915_READ(reg); | |
3548 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3549 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3550 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3551 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3552 | break; | |
3553 | } | |
3554 | udelay(50); | |
8db9d77b | 3555 | } |
fa37d39e SP |
3556 | if (retry < 5) |
3557 | break; | |
8db9d77b ZW |
3558 | } |
3559 | if (i == 4) | |
5eddb70b | 3560 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3561 | |
3562 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3563 | } | |
3564 | ||
357555c0 JB |
3565 | /* Manual link training for Ivy Bridge A0 parts */ |
3566 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3567 | { | |
3568 | struct drm_device *dev = crtc->dev; | |
3569 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3570 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3571 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3572 | i915_reg_t reg; |
3573 | u32 temp, i, j; | |
357555c0 JB |
3574 | |
3575 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3576 | for train result */ | |
3577 | reg = FDI_RX_IMR(pipe); | |
3578 | temp = I915_READ(reg); | |
3579 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3580 | temp &= ~FDI_RX_BIT_LOCK; | |
3581 | I915_WRITE(reg, temp); | |
3582 | ||
3583 | POSTING_READ(reg); | |
3584 | udelay(150); | |
3585 | ||
01a415fd DV |
3586 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3587 | I915_READ(FDI_RX_IIR(pipe))); | |
3588 | ||
139ccd3f JB |
3589 | /* Try each vswing and preemphasis setting twice before moving on */ |
3590 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3591 | /* disable first in case we need to retry */ | |
3592 | reg = FDI_TX_CTL(pipe); | |
3593 | temp = I915_READ(reg); | |
3594 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3595 | temp &= ~FDI_TX_ENABLE; | |
3596 | I915_WRITE(reg, temp); | |
357555c0 | 3597 | |
139ccd3f JB |
3598 | reg = FDI_RX_CTL(pipe); |
3599 | temp = I915_READ(reg); | |
3600 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3601 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3602 | temp &= ~FDI_RX_ENABLE; | |
3603 | I915_WRITE(reg, temp); | |
357555c0 | 3604 | |
139ccd3f | 3605 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3606 | reg = FDI_TX_CTL(pipe); |
3607 | temp = I915_READ(reg); | |
139ccd3f | 3608 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3609 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3610 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3611 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3612 | temp |= snb_b_fdi_train_param[j/2]; |
3613 | temp |= FDI_COMPOSITE_SYNC; | |
3614 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3615 | |
139ccd3f JB |
3616 | I915_WRITE(FDI_RX_MISC(pipe), |
3617 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3618 | |
139ccd3f | 3619 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3620 | temp = I915_READ(reg); |
139ccd3f JB |
3621 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3622 | temp |= FDI_COMPOSITE_SYNC; | |
3623 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3624 | |
139ccd3f JB |
3625 | POSTING_READ(reg); |
3626 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3627 | |
139ccd3f JB |
3628 | for (i = 0; i < 4; i++) { |
3629 | reg = FDI_RX_IIR(pipe); | |
3630 | temp = I915_READ(reg); | |
3631 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3632 | |
139ccd3f JB |
3633 | if (temp & FDI_RX_BIT_LOCK || |
3634 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3635 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3636 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3637 | i); | |
3638 | break; | |
3639 | } | |
3640 | udelay(1); /* should be 0.5us */ | |
3641 | } | |
3642 | if (i == 4) { | |
3643 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3644 | continue; | |
3645 | } | |
357555c0 | 3646 | |
139ccd3f | 3647 | /* Train 2 */ |
357555c0 JB |
3648 | reg = FDI_TX_CTL(pipe); |
3649 | temp = I915_READ(reg); | |
139ccd3f JB |
3650 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3651 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3652 | I915_WRITE(reg, temp); | |
3653 | ||
3654 | reg = FDI_RX_CTL(pipe); | |
3655 | temp = I915_READ(reg); | |
3656 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3657 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3658 | I915_WRITE(reg, temp); |
3659 | ||
3660 | POSTING_READ(reg); | |
139ccd3f | 3661 | udelay(2); /* should be 1.5us */ |
357555c0 | 3662 | |
139ccd3f JB |
3663 | for (i = 0; i < 4; i++) { |
3664 | reg = FDI_RX_IIR(pipe); | |
3665 | temp = I915_READ(reg); | |
3666 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3667 | |
139ccd3f JB |
3668 | if (temp & FDI_RX_SYMBOL_LOCK || |
3669 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3670 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3671 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3672 | i); | |
3673 | goto train_done; | |
3674 | } | |
3675 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3676 | } |
139ccd3f JB |
3677 | if (i == 4) |
3678 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3679 | } |
357555c0 | 3680 | |
139ccd3f | 3681 | train_done: |
357555c0 JB |
3682 | DRM_DEBUG_KMS("FDI train done.\n"); |
3683 | } | |
3684 | ||
88cefb6c | 3685 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3686 | { |
88cefb6c | 3687 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3688 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3689 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3690 | i915_reg_t reg; |
3691 | u32 temp; | |
c64e311e | 3692 | |
c98e9dcf | 3693 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3694 | reg = FDI_RX_CTL(pipe); |
3695 | temp = I915_READ(reg); | |
627eb5a3 | 3696 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3697 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3698 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3699 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3700 | ||
3701 | POSTING_READ(reg); | |
c98e9dcf JB |
3702 | udelay(200); |
3703 | ||
3704 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3705 | temp = I915_READ(reg); |
3706 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3707 | ||
3708 | POSTING_READ(reg); | |
c98e9dcf JB |
3709 | udelay(200); |
3710 | ||
20749730 PZ |
3711 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3712 | reg = FDI_TX_CTL(pipe); | |
3713 | temp = I915_READ(reg); | |
3714 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3715 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3716 | |
20749730 PZ |
3717 | POSTING_READ(reg); |
3718 | udelay(100); | |
6be4a607 | 3719 | } |
0e23b99d JB |
3720 | } |
3721 | ||
88cefb6c DV |
3722 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3723 | { | |
3724 | struct drm_device *dev = intel_crtc->base.dev; | |
3725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3726 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3727 | i915_reg_t reg; |
3728 | u32 temp; | |
88cefb6c DV |
3729 | |
3730 | /* Switch from PCDclk to Rawclk */ | |
3731 | reg = FDI_RX_CTL(pipe); | |
3732 | temp = I915_READ(reg); | |
3733 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3734 | ||
3735 | /* Disable CPU FDI TX PLL */ | |
3736 | reg = FDI_TX_CTL(pipe); | |
3737 | temp = I915_READ(reg); | |
3738 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3739 | ||
3740 | POSTING_READ(reg); | |
3741 | udelay(100); | |
3742 | ||
3743 | reg = FDI_RX_CTL(pipe); | |
3744 | temp = I915_READ(reg); | |
3745 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3746 | ||
3747 | /* Wait for the clocks to turn off. */ | |
3748 | POSTING_READ(reg); | |
3749 | udelay(100); | |
3750 | } | |
3751 | ||
0fc932b8 JB |
3752 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3753 | { | |
3754 | struct drm_device *dev = crtc->dev; | |
3755 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3756 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3757 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3758 | i915_reg_t reg; |
3759 | u32 temp; | |
0fc932b8 JB |
3760 | |
3761 | /* disable CPU FDI tx and PCH FDI rx */ | |
3762 | reg = FDI_TX_CTL(pipe); | |
3763 | temp = I915_READ(reg); | |
3764 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3765 | POSTING_READ(reg); | |
3766 | ||
3767 | reg = FDI_RX_CTL(pipe); | |
3768 | temp = I915_READ(reg); | |
3769 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3770 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3771 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3772 | ||
3773 | POSTING_READ(reg); | |
3774 | udelay(100); | |
3775 | ||
3776 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3777 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3778 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3779 | |
3780 | /* still set train pattern 1 */ | |
3781 | reg = FDI_TX_CTL(pipe); | |
3782 | temp = I915_READ(reg); | |
3783 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3784 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3785 | I915_WRITE(reg, temp); | |
3786 | ||
3787 | reg = FDI_RX_CTL(pipe); | |
3788 | temp = I915_READ(reg); | |
3789 | if (HAS_PCH_CPT(dev)) { | |
3790 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3791 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3792 | } else { | |
3793 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3794 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3795 | } | |
3796 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3797 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3798 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3799 | I915_WRITE(reg, temp); |
3800 | ||
3801 | POSTING_READ(reg); | |
3802 | udelay(100); | |
3803 | } | |
3804 | ||
5dce5b93 CW |
3805 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3806 | { | |
3807 | struct intel_crtc *crtc; | |
3808 | ||
3809 | /* Note that we don't need to be called with mode_config.lock here | |
3810 | * as our list of CRTC objects is static for the lifetime of the | |
3811 | * device and so cannot disappear as we iterate. Similarly, we can | |
3812 | * happily treat the predicates as racy, atomic checks as userspace | |
3813 | * cannot claim and pin a new fb without at least acquring the | |
3814 | * struct_mutex and so serialising with us. | |
3815 | */ | |
d3fcc808 | 3816 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3817 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3818 | continue; | |
3819 | ||
5a21b665 | 3820 | if (crtc->flip_work) |
5dce5b93 CW |
3821 | intel_wait_for_vblank(dev, crtc->pipe); |
3822 | ||
3823 | return true; | |
3824 | } | |
3825 | ||
3826 | return false; | |
3827 | } | |
3828 | ||
5a21b665 | 3829 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
3830 | { |
3831 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
3832 | struct intel_flip_work *work = intel_crtc->flip_work; |
3833 | ||
3834 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
3835 | |
3836 | if (work->event) | |
560ce1dc | 3837 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
3838 | |
3839 | drm_crtc_vblank_put(&intel_crtc->base); | |
3840 | ||
5a21b665 | 3841 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 3842 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
3843 | |
3844 | trace_i915_flip_complete(intel_crtc->plane, | |
3845 | work->pending_flip_obj); | |
d6bbafa1 CW |
3846 | } |
3847 | ||
5008e874 | 3848 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3849 | { |
0f91128d | 3850 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3851 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3852 | long ret; |
e6c3a2a6 | 3853 | |
2c10d571 | 3854 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3855 | |
3856 | ret = wait_event_interruptible_timeout( | |
3857 | dev_priv->pending_flip_queue, | |
3858 | !intel_crtc_has_pending_flip(crtc), | |
3859 | 60*HZ); | |
3860 | ||
3861 | if (ret < 0) | |
3862 | return ret; | |
3863 | ||
5a21b665 DV |
3864 | if (ret == 0) { |
3865 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3866 | struct intel_flip_work *work; | |
3867 | ||
3868 | spin_lock_irq(&dev->event_lock); | |
3869 | work = intel_crtc->flip_work; | |
3870 | if (work && !is_mmio_work(work)) { | |
3871 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3872 | page_flip_completed(intel_crtc); | |
3873 | } | |
3874 | spin_unlock_irq(&dev->event_lock); | |
3875 | } | |
5bb61643 | 3876 | |
5008e874 | 3877 | return 0; |
e6c3a2a6 CW |
3878 | } |
3879 | ||
060f02d8 VS |
3880 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3881 | { | |
3882 | u32 temp; | |
3883 | ||
3884 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3885 | ||
3886 | mutex_lock(&dev_priv->sb_lock); | |
3887 | ||
3888 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3889 | temp |= SBI_SSCCTL_DISABLE; | |
3890 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3891 | ||
3892 | mutex_unlock(&dev_priv->sb_lock); | |
3893 | } | |
3894 | ||
e615efe4 ED |
3895 | /* Program iCLKIP clock to the desired frequency */ |
3896 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3897 | { | |
64b46a06 | 3898 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 3899 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3900 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3901 | u32 temp; | |
3902 | ||
060f02d8 | 3903 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 3904 | |
64b46a06 VS |
3905 | /* The iCLK virtual clock root frequency is in MHz, |
3906 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3907 | * divisors, it is necessary to divide one by another, so we | |
3908 | * convert the virtual clock precision to KHz here for higher | |
3909 | * precision. | |
3910 | */ | |
3911 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
3912 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3913 | u32 iclk_pi_range = 64; | |
64b46a06 | 3914 | u32 desired_divisor; |
e615efe4 | 3915 | |
64b46a06 VS |
3916 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
3917 | clock << auxdiv); | |
3918 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3919 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 3920 | |
64b46a06 VS |
3921 | /* |
3922 | * Near 20MHz is a corner case which is | |
3923 | * out of range for the 7-bit divisor | |
3924 | */ | |
3925 | if (divsel <= 0x7f) | |
3926 | break; | |
e615efe4 ED |
3927 | } |
3928 | ||
3929 | /* This should not happen with any sane values */ | |
3930 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3931 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3932 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3933 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3934 | ||
3935 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3936 | clock, |
e615efe4 ED |
3937 | auxdiv, |
3938 | divsel, | |
3939 | phasedir, | |
3940 | phaseinc); | |
3941 | ||
060f02d8 VS |
3942 | mutex_lock(&dev_priv->sb_lock); |
3943 | ||
e615efe4 | 3944 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 3945 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3946 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3947 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3948 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3949 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3950 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3951 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3952 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3953 | |
3954 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3955 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3956 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3957 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3958 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3959 | |
3960 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3961 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3962 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3963 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 3964 | |
060f02d8 VS |
3965 | mutex_unlock(&dev_priv->sb_lock); |
3966 | ||
e615efe4 ED |
3967 | /* Wait for initialization time */ |
3968 | udelay(24); | |
3969 | ||
3970 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3971 | } | |
3972 | ||
8802e5b6 VS |
3973 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
3974 | { | |
3975 | u32 divsel, phaseinc, auxdiv; | |
3976 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3977 | u32 iclk_pi_range = 64; | |
3978 | u32 desired_divisor; | |
3979 | u32 temp; | |
3980 | ||
3981 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
3982 | return 0; | |
3983 | ||
3984 | mutex_lock(&dev_priv->sb_lock); | |
3985 | ||
3986 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3987 | if (temp & SBI_SSCCTL_DISABLE) { | |
3988 | mutex_unlock(&dev_priv->sb_lock); | |
3989 | return 0; | |
3990 | } | |
3991 | ||
3992 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
3993 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
3994 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
3995 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
3996 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
3997 | ||
3998 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
3999 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4000 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4001 | ||
4002 | mutex_unlock(&dev_priv->sb_lock); | |
4003 | ||
4004 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4005 | ||
4006 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4007 | desired_divisor << auxdiv); | |
4008 | } | |
4009 | ||
275f01b2 DV |
4010 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4011 | enum pipe pch_transcoder) | |
4012 | { | |
4013 | struct drm_device *dev = crtc->base.dev; | |
4014 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4015 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4016 | |
4017 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4018 | I915_READ(HTOTAL(cpu_transcoder))); | |
4019 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4020 | I915_READ(HBLANK(cpu_transcoder))); | |
4021 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4022 | I915_READ(HSYNC(cpu_transcoder))); | |
4023 | ||
4024 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4025 | I915_READ(VTOTAL(cpu_transcoder))); | |
4026 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4027 | I915_READ(VBLANK(cpu_transcoder))); | |
4028 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4029 | I915_READ(VSYNC(cpu_transcoder))); | |
4030 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4031 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4032 | } | |
4033 | ||
003632d9 | 4034 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4035 | { |
4036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4037 | uint32_t temp; | |
4038 | ||
4039 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4040 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4041 | return; |
4042 | ||
4043 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4044 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4045 | ||
003632d9 ACO |
4046 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4047 | if (enable) | |
4048 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4049 | ||
4050 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4051 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4052 | POSTING_READ(SOUTH_CHICKEN1); | |
4053 | } | |
4054 | ||
4055 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4056 | { | |
4057 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4058 | |
4059 | switch (intel_crtc->pipe) { | |
4060 | case PIPE_A: | |
4061 | break; | |
4062 | case PIPE_B: | |
6e3c9717 | 4063 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4064 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4065 | else |
003632d9 | 4066 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4067 | |
4068 | break; | |
4069 | case PIPE_C: | |
003632d9 | 4070 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4071 | |
4072 | break; | |
4073 | default: | |
4074 | BUG(); | |
4075 | } | |
4076 | } | |
4077 | ||
c48b5305 VS |
4078 | /* Return which DP Port should be selected for Transcoder DP control */ |
4079 | static enum port | |
4080 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4081 | { | |
4082 | struct drm_device *dev = crtc->dev; | |
4083 | struct intel_encoder *encoder; | |
4084 | ||
4085 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4086 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4087 | encoder->type == INTEL_OUTPUT_EDP) | |
4088 | return enc_to_dig_port(&encoder->base)->port; | |
4089 | } | |
4090 | ||
4091 | return -1; | |
4092 | } | |
4093 | ||
f67a559d JB |
4094 | /* |
4095 | * Enable PCH resources required for PCH ports: | |
4096 | * - PCH PLLs | |
4097 | * - FDI training & RX/TX | |
4098 | * - update transcoder timings | |
4099 | * - DP transcoding bits | |
4100 | * - transcoder | |
4101 | */ | |
4102 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4103 | { |
4104 | struct drm_device *dev = crtc->dev; | |
4105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4106 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4107 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4108 | u32 temp; |
2c07245f | 4109 | |
ab9412ba | 4110 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4111 | |
1fbc0d78 DV |
4112 | if (IS_IVYBRIDGE(dev)) |
4113 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4114 | ||
cd986abb DV |
4115 | /* Write the TU size bits before fdi link training, so that error |
4116 | * detection works. */ | |
4117 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4118 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4119 | ||
c98e9dcf | 4120 | /* For PCH output, training FDI link */ |
674cf967 | 4121 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4122 | |
3ad8a208 DV |
4123 | /* We need to program the right clock selection before writing the pixel |
4124 | * mutliplier into the DPLL. */ | |
303b81e0 | 4125 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4126 | u32 sel; |
4b645f14 | 4127 | |
c98e9dcf | 4128 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4129 | temp |= TRANS_DPLL_ENABLE(pipe); |
4130 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4131 | if (intel_crtc->config->shared_dpll == |
4132 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4133 | temp |= sel; |
4134 | else | |
4135 | temp &= ~sel; | |
c98e9dcf | 4136 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4137 | } |
5eddb70b | 4138 | |
3ad8a208 DV |
4139 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4140 | * transcoder, and we actually should do this to not upset any PCH | |
4141 | * transcoder that already use the clock when we share it. | |
4142 | * | |
4143 | * Note that enable_shared_dpll tries to do the right thing, but | |
4144 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4145 | * the right LVDS enable sequence. */ | |
85b3894f | 4146 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4147 | |
d9b6cb56 JB |
4148 | /* set transcoder timing, panel must allow it */ |
4149 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4150 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4151 | |
303b81e0 | 4152 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4153 | |
c98e9dcf | 4154 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4155 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4156 | const struct drm_display_mode *adjusted_mode = |
4157 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4158 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4159 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4160 | temp = I915_READ(reg); |
4161 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4162 | TRANS_DP_SYNC_MASK | |
4163 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4164 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4165 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4166 | |
9c4edaee | 4167 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4168 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4169 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4170 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4171 | |
4172 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4173 | case PORT_B: |
5eddb70b | 4174 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4175 | break; |
c48b5305 | 4176 | case PORT_C: |
5eddb70b | 4177 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4178 | break; |
c48b5305 | 4179 | case PORT_D: |
5eddb70b | 4180 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4181 | break; |
4182 | default: | |
e95d41e1 | 4183 | BUG(); |
32f9d658 | 4184 | } |
2c07245f | 4185 | |
5eddb70b | 4186 | I915_WRITE(reg, temp); |
6be4a607 | 4187 | } |
b52eb4dc | 4188 | |
b8a4f404 | 4189 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4190 | } |
4191 | ||
1507e5bd PZ |
4192 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4193 | { | |
4194 | struct drm_device *dev = crtc->dev; | |
4195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4197 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4198 | |
ab9412ba | 4199 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4200 | |
8c52b5e8 | 4201 | lpt_program_iclkip(crtc); |
1507e5bd | 4202 | |
0540e488 | 4203 | /* Set transcoder timing. */ |
275f01b2 | 4204 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4205 | |
937bb610 | 4206 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4207 | } |
4208 | ||
a1520318 | 4209 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4210 | { |
4211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4212 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4213 | u32 temp; |
4214 | ||
4215 | temp = I915_READ(dslreg); | |
4216 | udelay(500); | |
4217 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4218 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4219 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4220 | } |
4221 | } | |
4222 | ||
86adf9d7 ML |
4223 | static int |
4224 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4225 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4226 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4227 | { |
86adf9d7 ML |
4228 | struct intel_crtc_scaler_state *scaler_state = |
4229 | &crtc_state->scaler_state; | |
4230 | struct intel_crtc *intel_crtc = | |
4231 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4232 | int need_scaling; |
6156a456 CK |
4233 | |
4234 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4235 | (src_h != dst_w || src_w != dst_h): | |
4236 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4237 | |
4238 | /* | |
4239 | * if plane is being disabled or scaler is no more required or force detach | |
4240 | * - free scaler binded to this plane/crtc | |
4241 | * - in order to do this, update crtc->scaler_usage | |
4242 | * | |
4243 | * Here scaler state in crtc_state is set free so that | |
4244 | * scaler can be assigned to other user. Actual register | |
4245 | * update to free the scaler is done in plane/panel-fit programming. | |
4246 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4247 | */ | |
86adf9d7 | 4248 | if (force_detach || !need_scaling) { |
a1b2278e | 4249 | if (*scaler_id >= 0) { |
86adf9d7 | 4250 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4251 | scaler_state->scalers[*scaler_id].in_use = 0; |
4252 | ||
86adf9d7 ML |
4253 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4254 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4255 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4256 | scaler_state->scaler_users); |
4257 | *scaler_id = -1; | |
4258 | } | |
4259 | return 0; | |
4260 | } | |
4261 | ||
4262 | /* range checks */ | |
4263 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4264 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4265 | ||
4266 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4267 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4268 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4269 | "size is out of scaler range\n", |
86adf9d7 | 4270 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4271 | return -EINVAL; |
4272 | } | |
4273 | ||
86adf9d7 ML |
4274 | /* mark this plane as a scaler user in crtc_state */ |
4275 | scaler_state->scaler_users |= (1 << scaler_user); | |
4276 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4277 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4278 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4279 | scaler_state->scaler_users); | |
4280 | ||
4281 | return 0; | |
4282 | } | |
4283 | ||
4284 | /** | |
4285 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4286 | * | |
4287 | * @state: crtc's scaler state | |
86adf9d7 ML |
4288 | * |
4289 | * Return | |
4290 | * 0 - scaler_usage updated successfully | |
4291 | * error - requested scaling cannot be supported or other error condition | |
4292 | */ | |
e435d6e5 | 4293 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4294 | { |
4295 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4296 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4297 | |
78108b7c VS |
4298 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n", |
4299 | intel_crtc->base.base.id, intel_crtc->base.name, | |
4300 | intel_crtc->pipe, SKL_CRTC_INDEX); | |
86adf9d7 | 4301 | |
e435d6e5 | 4302 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4303 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4304 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4305 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4306 | } |
4307 | ||
4308 | /** | |
4309 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4310 | * | |
4311 | * @state: crtc's scaler state | |
86adf9d7 ML |
4312 | * @plane_state: atomic plane state to update |
4313 | * | |
4314 | * Return | |
4315 | * 0 - scaler_usage updated successfully | |
4316 | * error - requested scaling cannot be supported or other error condition | |
4317 | */ | |
da20eabd ML |
4318 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4319 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4320 | { |
4321 | ||
4322 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4323 | struct intel_plane *intel_plane = |
4324 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4325 | struct drm_framebuffer *fb = plane_state->base.fb; |
4326 | int ret; | |
4327 | ||
4328 | bool force_detach = !fb || !plane_state->visible; | |
4329 | ||
72660ce0 VS |
4330 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n", |
4331 | intel_plane->base.base.id, intel_plane->base.name, | |
4332 | intel_crtc->pipe, drm_plane_index(&intel_plane->base)); | |
86adf9d7 ML |
4333 | |
4334 | ret = skl_update_scaler(crtc_state, force_detach, | |
4335 | drm_plane_index(&intel_plane->base), | |
4336 | &plane_state->scaler_id, | |
4337 | plane_state->base.rotation, | |
4338 | drm_rect_width(&plane_state->src) >> 16, | |
4339 | drm_rect_height(&plane_state->src) >> 16, | |
4340 | drm_rect_width(&plane_state->dst), | |
4341 | drm_rect_height(&plane_state->dst)); | |
4342 | ||
4343 | if (ret || plane_state->scaler_id < 0) | |
4344 | return ret; | |
4345 | ||
a1b2278e | 4346 | /* check colorkey */ |
818ed961 | 4347 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4348 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4349 | intel_plane->base.base.id, | |
4350 | intel_plane->base.name); | |
a1b2278e CK |
4351 | return -EINVAL; |
4352 | } | |
4353 | ||
4354 | /* Check src format */ | |
86adf9d7 ML |
4355 | switch (fb->pixel_format) { |
4356 | case DRM_FORMAT_RGB565: | |
4357 | case DRM_FORMAT_XBGR8888: | |
4358 | case DRM_FORMAT_XRGB8888: | |
4359 | case DRM_FORMAT_ABGR8888: | |
4360 | case DRM_FORMAT_ARGB8888: | |
4361 | case DRM_FORMAT_XRGB2101010: | |
4362 | case DRM_FORMAT_XBGR2101010: | |
4363 | case DRM_FORMAT_YUYV: | |
4364 | case DRM_FORMAT_YVYU: | |
4365 | case DRM_FORMAT_UYVY: | |
4366 | case DRM_FORMAT_VYUY: | |
4367 | break; | |
4368 | default: | |
72660ce0 VS |
4369 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4370 | intel_plane->base.base.id, intel_plane->base.name, | |
4371 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4372 | return -EINVAL; |
a1b2278e CK |
4373 | } |
4374 | ||
a1b2278e CK |
4375 | return 0; |
4376 | } | |
4377 | ||
e435d6e5 ML |
4378 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4379 | { | |
4380 | int i; | |
4381 | ||
4382 | for (i = 0; i < crtc->num_scalers; i++) | |
4383 | skl_detach_scaler(crtc, i); | |
4384 | } | |
4385 | ||
4386 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4387 | { |
4388 | struct drm_device *dev = crtc->base.dev; | |
4389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4390 | int pipe = crtc->pipe; | |
a1b2278e CK |
4391 | struct intel_crtc_scaler_state *scaler_state = |
4392 | &crtc->config->scaler_state; | |
4393 | ||
4394 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4395 | ||
6e3c9717 | 4396 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4397 | int id; |
4398 | ||
4399 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4400 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4401 | return; | |
4402 | } | |
4403 | ||
4404 | id = scaler_state->scaler_id; | |
4405 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4406 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4407 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4408 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4409 | ||
4410 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4411 | } |
4412 | } | |
4413 | ||
b074cec8 JB |
4414 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4415 | { | |
4416 | struct drm_device *dev = crtc->base.dev; | |
4417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4418 | int pipe = crtc->pipe; | |
4419 | ||
6e3c9717 | 4420 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4421 | /* Force use of hard-coded filter coefficients |
4422 | * as some pre-programmed values are broken, | |
4423 | * e.g. x201. | |
4424 | */ | |
4425 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4426 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4427 | PF_PIPE_SEL_IVB(pipe)); | |
4428 | else | |
4429 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4430 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4431 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4432 | } |
4433 | } | |
4434 | ||
20bc8673 | 4435 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4436 | { |
cea165c3 VS |
4437 | struct drm_device *dev = crtc->base.dev; |
4438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4439 | |
6e3c9717 | 4440 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4441 | return; |
4442 | ||
307e4498 ML |
4443 | /* |
4444 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4445 | * This function is called from post_plane_update, which is run after | |
4446 | * a vblank wait. | |
4447 | */ | |
cea165c3 | 4448 | |
d77e4531 | 4449 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4450 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4451 | mutex_lock(&dev_priv->rps.hw_lock); |
4452 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4453 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4454 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4455 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4456 | * mailbox." Moreover, the mailbox may return a bogus state, |
4457 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4458 | */ |
4459 | } else { | |
4460 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4461 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4462 | * is essentially intel_wait_for_vblank. If we don't have this | |
4463 | * and don't wait for vblanks until the end of crtc_enable, then | |
4464 | * the HW state readout code will complain that the expected | |
4465 | * IPS_CTL value is not the one we read. */ | |
4466 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4467 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4468 | } | |
d77e4531 PZ |
4469 | } |
4470 | ||
20bc8673 | 4471 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4472 | { |
4473 | struct drm_device *dev = crtc->base.dev; | |
4474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4475 | ||
6e3c9717 | 4476 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4477 | return; |
4478 | ||
4479 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4480 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4481 | mutex_lock(&dev_priv->rps.hw_lock); |
4482 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4483 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4484 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4485 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4486 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4487 | } else { |
2a114cc1 | 4488 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4489 | POSTING_READ(IPS_CTL); |
4490 | } | |
d77e4531 PZ |
4491 | |
4492 | /* We need to wait for a vblank before we can disable the plane. */ | |
4493 | intel_wait_for_vblank(dev, crtc->pipe); | |
4494 | } | |
4495 | ||
7cac945f | 4496 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4497 | { |
7cac945f | 4498 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4499 | struct drm_device *dev = intel_crtc->base.dev; |
4500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4501 | ||
4502 | mutex_lock(&dev->struct_mutex); | |
4503 | dev_priv->mm.interruptible = false; | |
4504 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4505 | dev_priv->mm.interruptible = true; | |
4506 | mutex_unlock(&dev->struct_mutex); | |
4507 | } | |
4508 | ||
4509 | /* Let userspace switch the overlay on again. In most cases userspace | |
4510 | * has to recompute where to put it anyway. | |
4511 | */ | |
4512 | } | |
4513 | ||
87d4300a ML |
4514 | /** |
4515 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4516 | * @crtc: the CRTC whose primary plane was just enabled | |
4517 | * | |
4518 | * Performs potentially sleeping operations that must be done after the primary | |
4519 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4520 | * called due to an explicit primary plane update, or due to an implicit | |
4521 | * re-enable that is caused when a sprite plane is updated to no longer | |
4522 | * completely hide the primary plane. | |
4523 | */ | |
4524 | static void | |
4525 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4526 | { |
4527 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4528 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4529 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4530 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4531 | |
87d4300a ML |
4532 | /* |
4533 | * FIXME IPS should be fine as long as one plane is | |
4534 | * enabled, but in practice it seems to have problems | |
4535 | * when going from primary only to sprite only and vice | |
4536 | * versa. | |
4537 | */ | |
a5c4d7bc VS |
4538 | hsw_enable_ips(intel_crtc); |
4539 | ||
f99d7069 | 4540 | /* |
87d4300a ML |
4541 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4542 | * So don't enable underrun reporting before at least some planes | |
4543 | * are enabled. | |
4544 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4545 | * but leave the pipe running. | |
f99d7069 | 4546 | */ |
87d4300a ML |
4547 | if (IS_GEN2(dev)) |
4548 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4549 | ||
aca7b684 VS |
4550 | /* Underruns don't always raise interrupts, so check manually. */ |
4551 | intel_check_cpu_fifo_underruns(dev_priv); | |
4552 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4553 | } |
4554 | ||
2622a081 | 4555 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4556 | static void |
4557 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4558 | { |
4559 | struct drm_device *dev = crtc->dev; | |
4560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4561 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4562 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4563 | |
87d4300a ML |
4564 | /* |
4565 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4566 | * So diasble underrun reporting before all the planes get disabled. | |
4567 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4568 | * but leave the pipe running. | |
4569 | */ | |
4570 | if (IS_GEN2(dev)) | |
4571 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4572 | |
2622a081 VS |
4573 | /* |
4574 | * FIXME IPS should be fine as long as one plane is | |
4575 | * enabled, but in practice it seems to have problems | |
4576 | * when going from primary only to sprite only and vice | |
4577 | * versa. | |
4578 | */ | |
4579 | hsw_disable_ips(intel_crtc); | |
4580 | } | |
4581 | ||
4582 | /* FIXME get rid of this and use pre_plane_update */ | |
4583 | static void | |
4584 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4585 | { | |
4586 | struct drm_device *dev = crtc->dev; | |
4587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4589 | int pipe = intel_crtc->pipe; | |
4590 | ||
4591 | intel_pre_disable_primary(crtc); | |
4592 | ||
87d4300a ML |
4593 | /* |
4594 | * Vblank time updates from the shadow to live plane control register | |
4595 | * are blocked if the memory self-refresh mode is active at that | |
4596 | * moment. So to make sure the plane gets truly disabled, disable | |
4597 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4598 | * will be checked/applied by the HW only at the next frame start | |
4599 | * event which is after the vblank start event, so we need to have a | |
4600 | * wait-for-vblank between disabling the plane and the pipe. | |
4601 | */ | |
262cd2e1 | 4602 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4603 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4604 | dev_priv->wm.vlv.cxsr = false; |
4605 | intel_wait_for_vblank(dev, pipe); | |
4606 | } | |
87d4300a ML |
4607 | } |
4608 | ||
5a21b665 DV |
4609 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4610 | { | |
4611 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4612 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4613 | struct intel_crtc_state *pipe_config = | |
4614 | to_intel_crtc_state(crtc->base.state); | |
4615 | struct drm_device *dev = crtc->base.dev; | |
4616 | struct drm_plane *primary = crtc->base.primary; | |
4617 | struct drm_plane_state *old_pri_state = | |
4618 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4619 | ||
4620 | intel_frontbuffer_flip(dev, pipe_config->fb_bits); | |
4621 | ||
4622 | crtc->wm.cxsr_allowed = true; | |
4623 | ||
4624 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
4625 | intel_update_watermarks(&crtc->base); | |
4626 | ||
4627 | if (old_pri_state) { | |
4628 | struct intel_plane_state *primary_state = | |
4629 | to_intel_plane_state(primary->state); | |
4630 | struct intel_plane_state *old_primary_state = | |
4631 | to_intel_plane_state(old_pri_state); | |
4632 | ||
4633 | intel_fbc_post_update(crtc); | |
4634 | ||
4635 | if (primary_state->visible && | |
4636 | (needs_modeset(&pipe_config->base) || | |
4637 | !old_primary_state->visible)) | |
4638 | intel_post_enable_primary(&crtc->base); | |
4639 | } | |
4640 | } | |
4641 | ||
5c74cd73 | 4642 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4643 | { |
5c74cd73 | 4644 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4645 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4646 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1d3a0e ML |
4647 | struct intel_crtc_state *pipe_config = |
4648 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4649 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4650 | struct drm_plane *primary = crtc->base.primary; | |
4651 | struct drm_plane_state *old_pri_state = | |
4652 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4653 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4654 | |
5c74cd73 ML |
4655 | if (old_pri_state) { |
4656 | struct intel_plane_state *primary_state = | |
4657 | to_intel_plane_state(primary->state); | |
4658 | struct intel_plane_state *old_primary_state = | |
4659 | to_intel_plane_state(old_pri_state); | |
4660 | ||
faf68d92 | 4661 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 4662 | |
5c74cd73 ML |
4663 | if (old_primary_state->visible && |
4664 | (modeset || !primary_state->visible)) | |
4665 | intel_pre_disable_primary(&crtc->base); | |
4666 | } | |
852eb00d | 4667 | |
a4015f9a | 4668 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) { |
852eb00d | 4669 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4670 | |
2622a081 VS |
4671 | /* |
4672 | * Vblank time updates from the shadow to live plane control register | |
4673 | * are blocked if the memory self-refresh mode is active at that | |
4674 | * moment. So to make sure the plane gets truly disabled, disable | |
4675 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4676 | * will be checked/applied by the HW only at the next frame start | |
4677 | * event which is after the vblank start event, so we need to have a | |
4678 | * wait-for-vblank between disabling the plane and the pipe. | |
4679 | */ | |
4680 | if (old_crtc_state->base.active) { | |
2dfd178d | 4681 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4682 | dev_priv->wm.vlv.cxsr = false; |
4683 | intel_wait_for_vblank(dev, crtc->pipe); | |
4684 | } | |
852eb00d | 4685 | } |
92826fcd | 4686 | |
ed4a6a7c MR |
4687 | /* |
4688 | * IVB workaround: must disable low power watermarks for at least | |
4689 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4690 | * when scaling is disabled. | |
4691 | * | |
4692 | * WaCxSRDisabledForSpriteScaling:ivb | |
4693 | */ | |
4694 | if (pipe_config->disable_lp_wm) { | |
4695 | ilk_disable_lp_wm(dev); | |
4696 | intel_wait_for_vblank(dev, crtc->pipe); | |
4697 | } | |
4698 | ||
4699 | /* | |
4700 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4701 | * watermark programming here. | |
4702 | */ | |
4703 | if (needs_modeset(&pipe_config->base)) | |
4704 | return; | |
4705 | ||
4706 | /* | |
4707 | * For platforms that support atomic watermarks, program the | |
4708 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4709 | * will be the intermediate values that are safe for both pre- and | |
4710 | * post- vblank; when vblank happens, the 'active' values will be set | |
4711 | * to the final 'target' values and we'll do this again to get the | |
4712 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4713 | * will be the final target values which will get automatically latched | |
4714 | * at vblank time; no further programming will be necessary. | |
4715 | * | |
4716 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4717 | * we'll continue to update watermarks the old way, if flags tell | |
4718 | * us to. | |
4719 | */ | |
4720 | if (dev_priv->display.initial_watermarks != NULL) | |
4721 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4722 | else if (pipe_config->update_wm_pre) |
92826fcd | 4723 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4724 | } |
4725 | ||
d032ffa0 | 4726 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4727 | { |
4728 | struct drm_device *dev = crtc->dev; | |
4729 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4730 | struct drm_plane *p; |
87d4300a ML |
4731 | int pipe = intel_crtc->pipe; |
4732 | ||
7cac945f | 4733 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4734 | |
d032ffa0 ML |
4735 | drm_for_each_plane_mask(p, dev, plane_mask) |
4736 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4737 | |
f99d7069 DV |
4738 | /* |
4739 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4740 | * to compute the mask of flip planes precisely. For the time being | |
4741 | * consider this a flip to a NULL plane. | |
4742 | */ | |
4743 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4744 | } |
4745 | ||
f67a559d JB |
4746 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4747 | { | |
4748 | struct drm_device *dev = crtc->dev; | |
4749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4750 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4751 | struct intel_encoder *encoder; |
f67a559d | 4752 | int pipe = intel_crtc->pipe; |
b95c5321 ML |
4753 | struct intel_crtc_state *pipe_config = |
4754 | to_intel_crtc_state(crtc->state); | |
f67a559d | 4755 | |
53d9f4e9 | 4756 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4757 | return; |
4758 | ||
b2c0593a VS |
4759 | /* |
4760 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4761 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4762 | * | |
4763 | * On ILK we get an occasional spurious CPU pipe underruns | |
4764 | * between eDP port A enable and vdd enable. Also PCH port | |
4765 | * enable seems to result in the occasional CPU pipe underrun. | |
4766 | * | |
4767 | * Spurious PCH underruns also occur during PCH enabling. | |
4768 | */ | |
4769 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
4770 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
4771 | if (intel_crtc->config->has_pch_encoder) |
4772 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4773 | ||
6e3c9717 | 4774 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4775 | intel_prepare_shared_dpll(intel_crtc); |
4776 | ||
6e3c9717 | 4777 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4778 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4779 | |
4780 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4781 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4782 | |
6e3c9717 | 4783 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4784 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4785 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4786 | } |
4787 | ||
4788 | ironlake_set_pipeconf(crtc); | |
4789 | ||
f67a559d | 4790 | intel_crtc->active = true; |
8664281b | 4791 | |
f6736a1a | 4792 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4793 | if (encoder->pre_enable) |
4794 | encoder->pre_enable(encoder); | |
f67a559d | 4795 | |
6e3c9717 | 4796 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4797 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4798 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4799 | * enabling. */ | |
88cefb6c | 4800 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4801 | } else { |
4802 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4803 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4804 | } | |
f67a559d | 4805 | |
b074cec8 | 4806 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4807 | |
9c54c0dd JB |
4808 | /* |
4809 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4810 | * clocks enabled | |
4811 | */ | |
b95c5321 | 4812 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 4813 | |
1d5bf5d9 ID |
4814 | if (dev_priv->display.initial_watermarks != NULL) |
4815 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4816 | intel_enable_pipe(intel_crtc); |
f67a559d | 4817 | |
6e3c9717 | 4818 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4819 | ironlake_pch_enable(crtc); |
c98e9dcf | 4820 | |
f9b61ff6 DV |
4821 | assert_vblank_disabled(crtc); |
4822 | drm_crtc_vblank_on(crtc); | |
4823 | ||
fa5c73b1 DV |
4824 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4825 | encoder->enable(encoder); | |
61b77ddd DV |
4826 | |
4827 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4828 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4829 | |
4830 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4831 | if (intel_crtc->config->has_pch_encoder) | |
4832 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 4833 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 4834 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
4835 | } |
4836 | ||
42db64ef PZ |
4837 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4838 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4839 | { | |
f5adf94e | 4840 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4841 | } |
4842 | ||
4f771f10 PZ |
4843 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4844 | { | |
4845 | struct drm_device *dev = crtc->dev; | |
4846 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4848 | struct intel_encoder *encoder; | |
99d736a2 | 4849 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 4850 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
4851 | struct intel_crtc_state *pipe_config = |
4852 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4853 | |
53d9f4e9 | 4854 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4855 | return; |
4856 | ||
81b088ca VS |
4857 | if (intel_crtc->config->has_pch_encoder) |
4858 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4859 | false); | |
4860 | ||
95a7a2ae ID |
4861 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4862 | if (encoder->pre_pll_enable) | |
4863 | encoder->pre_pll_enable(encoder); | |
4864 | ||
8106ddbd | 4865 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
4866 | intel_enable_shared_dpll(intel_crtc); |
4867 | ||
6e3c9717 | 4868 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4869 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 4870 | |
4d1de975 JN |
4871 | if (!intel_crtc->config->has_dsi_encoder) |
4872 | intel_set_pipe_timings(intel_crtc); | |
4873 | ||
bc58be60 | 4874 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 4875 | |
4d1de975 JN |
4876 | if (cpu_transcoder != TRANSCODER_EDP && |
4877 | !transcoder_is_dsi(cpu_transcoder)) { | |
4878 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 4879 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
4880 | } |
4881 | ||
6e3c9717 | 4882 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4883 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4884 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4885 | } |
4886 | ||
4d1de975 JN |
4887 | if (!intel_crtc->config->has_dsi_encoder) |
4888 | haswell_set_pipeconf(crtc); | |
4889 | ||
391bf048 | 4890 | haswell_set_pipemisc(crtc); |
229fca97 | 4891 | |
b95c5321 | 4892 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 4893 | |
4f771f10 | 4894 | intel_crtc->active = true; |
8664281b | 4895 | |
6b698516 DV |
4896 | if (intel_crtc->config->has_pch_encoder) |
4897 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4898 | else | |
4899 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4900 | ||
7d4aefd0 | 4901 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4902 | if (encoder->pre_enable) |
4903 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4904 | } |
4f771f10 | 4905 | |
d2d65408 | 4906 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4907 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4908 | |
a65347ba | 4909 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4910 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4911 | |
1c132b44 | 4912 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4913 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4914 | else |
1c132b44 | 4915 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4916 | |
4917 | /* | |
4918 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4919 | * clocks enabled | |
4920 | */ | |
b95c5321 | 4921 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 4922 | |
1f544388 | 4923 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 4924 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4925 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4926 | |
1d5bf5d9 ID |
4927 | if (dev_priv->display.initial_watermarks != NULL) |
4928 | dev_priv->display.initial_watermarks(pipe_config); | |
4929 | else | |
4930 | intel_update_watermarks(crtc); | |
4d1de975 JN |
4931 | |
4932 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
4933 | if (!intel_crtc->config->has_dsi_encoder) | |
4934 | intel_enable_pipe(intel_crtc); | |
42db64ef | 4935 | |
6e3c9717 | 4936 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4937 | lpt_pch_enable(crtc); |
4f771f10 | 4938 | |
a65347ba | 4939 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4940 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4941 | ||
f9b61ff6 DV |
4942 | assert_vblank_disabled(crtc); |
4943 | drm_crtc_vblank_on(crtc); | |
4944 | ||
8807e55b | 4945 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4946 | encoder->enable(encoder); |
8807e55b JN |
4947 | intel_opregion_notify_encoder(encoder, true); |
4948 | } | |
4f771f10 | 4949 | |
6b698516 DV |
4950 | if (intel_crtc->config->has_pch_encoder) { |
4951 | intel_wait_for_vblank(dev, pipe); | |
4952 | intel_wait_for_vblank(dev, pipe); | |
4953 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
4954 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4955 | true); | |
6b698516 | 4956 | } |
d2d65408 | 4957 | |
e4916946 PZ |
4958 | /* If we change the relative order between pipe/planes enabling, we need |
4959 | * to change the workaround. */ | |
99d736a2 ML |
4960 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4961 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4962 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4963 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4964 | } | |
4f771f10 PZ |
4965 | } |
4966 | ||
bfd16b2a | 4967 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4968 | { |
4969 | struct drm_device *dev = crtc->base.dev; | |
4970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4971 | int pipe = crtc->pipe; | |
4972 | ||
4973 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4974 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 4975 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4976 | I915_WRITE(PF_CTL(pipe), 0); |
4977 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4978 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4979 | } | |
4980 | } | |
4981 | ||
6be4a607 JB |
4982 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4983 | { | |
4984 | struct drm_device *dev = crtc->dev; | |
4985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4986 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4987 | struct intel_encoder *encoder; |
6be4a607 | 4988 | int pipe = intel_crtc->pipe; |
b52eb4dc | 4989 | |
b2c0593a VS |
4990 | /* |
4991 | * Sometimes spurious CPU pipe underruns happen when the | |
4992 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
4993 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
4994 | */ | |
4995 | if (intel_crtc->config->has_pch_encoder) { | |
4996 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 4997 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 4998 | } |
37ca8d4c | 4999 | |
ea9d758d DV |
5000 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5001 | encoder->disable(encoder); | |
5002 | ||
f9b61ff6 DV |
5003 | drm_crtc_vblank_off(crtc); |
5004 | assert_vblank_disabled(crtc); | |
5005 | ||
575f7ab7 | 5006 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5007 | |
bfd16b2a | 5008 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5009 | |
b2c0593a | 5010 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5011 | ironlake_fdi_disable(crtc); |
5012 | ||
bf49ec8c DV |
5013 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5014 | if (encoder->post_disable) | |
5015 | encoder->post_disable(encoder); | |
2c07245f | 5016 | |
6e3c9717 | 5017 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5018 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5019 | |
d925c59a | 5020 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5021 | i915_reg_t reg; |
5022 | u32 temp; | |
5023 | ||
d925c59a DV |
5024 | /* disable TRANS_DP_CTL */ |
5025 | reg = TRANS_DP_CTL(pipe); | |
5026 | temp = I915_READ(reg); | |
5027 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5028 | TRANS_DP_PORT_SEL_MASK); | |
5029 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5030 | I915_WRITE(reg, temp); | |
5031 | ||
5032 | /* disable DPLL_SEL */ | |
5033 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5034 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5035 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5036 | } |
e3421a18 | 5037 | |
d925c59a DV |
5038 | ironlake_fdi_pll_disable(intel_crtc); |
5039 | } | |
81b088ca | 5040 | |
b2c0593a | 5041 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5042 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5043 | } |
1b3c7a47 | 5044 | |
4f771f10 | 5045 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5046 | { |
4f771f10 PZ |
5047 | struct drm_device *dev = crtc->dev; |
5048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5050 | struct intel_encoder *encoder; |
6e3c9717 | 5051 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5052 | |
d2d65408 VS |
5053 | if (intel_crtc->config->has_pch_encoder) |
5054 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5055 | false); | |
5056 | ||
8807e55b JN |
5057 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5058 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5059 | encoder->disable(encoder); |
8807e55b | 5060 | } |
4f771f10 | 5061 | |
f9b61ff6 DV |
5062 | drm_crtc_vblank_off(crtc); |
5063 | assert_vblank_disabled(crtc); | |
5064 | ||
4d1de975 JN |
5065 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
5066 | if (!intel_crtc->config->has_dsi_encoder) | |
5067 | intel_disable_pipe(intel_crtc); | |
4f771f10 | 5068 | |
6e3c9717 | 5069 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5070 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5071 | ||
a65347ba | 5072 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5073 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5074 | |
1c132b44 | 5075 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5076 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5077 | else |
bfd16b2a | 5078 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5079 | |
a65347ba | 5080 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5081 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5082 | |
97b040aa ID |
5083 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5084 | if (encoder->post_disable) | |
5085 | encoder->post_disable(encoder); | |
81b088ca | 5086 | |
92966a37 VS |
5087 | if (intel_crtc->config->has_pch_encoder) { |
5088 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5089 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5090 | intel_ddi_fdi_disable(crtc); |
5091 | ||
81b088ca VS |
5092 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5093 | true); | |
92966a37 | 5094 | } |
4f771f10 PZ |
5095 | } |
5096 | ||
2dd24552 JB |
5097 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5098 | { | |
5099 | struct drm_device *dev = crtc->base.dev; | |
5100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5101 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5102 | |
681a8504 | 5103 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5104 | return; |
5105 | ||
2dd24552 | 5106 | /* |
c0b03411 DV |
5107 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5108 | * according to register description and PRM. | |
2dd24552 | 5109 | */ |
c0b03411 DV |
5110 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5111 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5112 | |
b074cec8 JB |
5113 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5114 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5115 | |
5116 | /* Border color in case we don't scale up to the full screen. Black by | |
5117 | * default, change to something else for debugging. */ | |
5118 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5119 | } |
5120 | ||
d05410f9 DA |
5121 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5122 | { | |
5123 | switch (port) { | |
5124 | case PORT_A: | |
6331a704 | 5125 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5126 | case PORT_B: |
6331a704 | 5127 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5128 | case PORT_C: |
6331a704 | 5129 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5130 | case PORT_D: |
6331a704 | 5131 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5132 | case PORT_E: |
6331a704 | 5133 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5134 | default: |
b9fec167 | 5135 | MISSING_CASE(port); |
d05410f9 DA |
5136 | return POWER_DOMAIN_PORT_OTHER; |
5137 | } | |
5138 | } | |
5139 | ||
25f78f58 VS |
5140 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5141 | { | |
5142 | switch (port) { | |
5143 | case PORT_A: | |
5144 | return POWER_DOMAIN_AUX_A; | |
5145 | case PORT_B: | |
5146 | return POWER_DOMAIN_AUX_B; | |
5147 | case PORT_C: | |
5148 | return POWER_DOMAIN_AUX_C; | |
5149 | case PORT_D: | |
5150 | return POWER_DOMAIN_AUX_D; | |
5151 | case PORT_E: | |
5152 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5153 | return POWER_DOMAIN_AUX_D; | |
5154 | default: | |
b9fec167 | 5155 | MISSING_CASE(port); |
25f78f58 VS |
5156 | return POWER_DOMAIN_AUX_A; |
5157 | } | |
5158 | } | |
5159 | ||
319be8ae ID |
5160 | enum intel_display_power_domain |
5161 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5162 | { | |
5163 | struct drm_device *dev = intel_encoder->base.dev; | |
5164 | struct intel_digital_port *intel_dig_port; | |
5165 | ||
5166 | switch (intel_encoder->type) { | |
5167 | case INTEL_OUTPUT_UNKNOWN: | |
5168 | /* Only DDI platforms should ever use this output type */ | |
5169 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5170 | case INTEL_OUTPUT_DISPLAYPORT: | |
5171 | case INTEL_OUTPUT_HDMI: | |
5172 | case INTEL_OUTPUT_EDP: | |
5173 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5174 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5175 | case INTEL_OUTPUT_DP_MST: |
5176 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5177 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5178 | case INTEL_OUTPUT_ANALOG: |
5179 | return POWER_DOMAIN_PORT_CRT; | |
5180 | case INTEL_OUTPUT_DSI: | |
5181 | return POWER_DOMAIN_PORT_DSI; | |
5182 | default: | |
5183 | return POWER_DOMAIN_PORT_OTHER; | |
5184 | } | |
5185 | } | |
5186 | ||
25f78f58 VS |
5187 | enum intel_display_power_domain |
5188 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5189 | { | |
5190 | struct drm_device *dev = intel_encoder->base.dev; | |
5191 | struct intel_digital_port *intel_dig_port; | |
5192 | ||
5193 | switch (intel_encoder->type) { | |
5194 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5195 | case INTEL_OUTPUT_HDMI: |
5196 | /* | |
5197 | * Only DDI platforms should ever use these output types. | |
5198 | * We can get here after the HDMI detect code has already set | |
5199 | * the type of the shared encoder. Since we can't be sure | |
5200 | * what's the status of the given connectors, play safe and | |
5201 | * run the DP detection too. | |
5202 | */ | |
25f78f58 VS |
5203 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5204 | case INTEL_OUTPUT_DISPLAYPORT: | |
5205 | case INTEL_OUTPUT_EDP: | |
5206 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5207 | return port_to_aux_power_domain(intel_dig_port->port); | |
5208 | case INTEL_OUTPUT_DP_MST: | |
5209 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5210 | return port_to_aux_power_domain(intel_dig_port->port); | |
5211 | default: | |
b9fec167 | 5212 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5213 | return POWER_DOMAIN_AUX_A; |
5214 | } | |
5215 | } | |
5216 | ||
74bff5f9 ML |
5217 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5218 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5219 | { |
319be8ae | 5220 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5221 | struct drm_encoder *encoder; |
319be8ae ID |
5222 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5223 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5224 | unsigned long mask; |
74bff5f9 | 5225 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5226 | |
74bff5f9 | 5227 | if (!crtc_state->base.active) |
292b990e ML |
5228 | return 0; |
5229 | ||
77d22dca ID |
5230 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5231 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5232 | if (crtc_state->pch_pfit.enabled || |
5233 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5234 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5235 | ||
74bff5f9 ML |
5236 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5237 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5238 | ||
319be8ae | 5239 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5240 | } |
319be8ae | 5241 | |
15e7ec29 ML |
5242 | if (crtc_state->shared_dpll) |
5243 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5244 | ||
77d22dca ID |
5245 | return mask; |
5246 | } | |
5247 | ||
74bff5f9 ML |
5248 | static unsigned long |
5249 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5250 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5251 | { |
292b990e ML |
5252 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5254 | enum intel_display_power_domain domain; | |
5a21b665 | 5255 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5256 | |
292b990e | 5257 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5258 | intel_crtc->enabled_power_domains = new_domains = |
5259 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5260 | |
5a21b665 | 5261 | domains = new_domains & ~old_domains; |
292b990e ML |
5262 | |
5263 | for_each_power_domain(domain, domains) | |
5264 | intel_display_power_get(dev_priv, domain); | |
5265 | ||
5a21b665 | 5266 | return old_domains & ~new_domains; |
292b990e ML |
5267 | } |
5268 | ||
5269 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5270 | unsigned long domains) | |
5271 | { | |
5272 | enum intel_display_power_domain domain; | |
5273 | ||
5274 | for_each_power_domain(domain, domains) | |
5275 | intel_display_power_put(dev_priv, domain); | |
5276 | } | |
77d22dca | 5277 | |
adafdc6f MK |
5278 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5279 | { | |
5280 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5281 | ||
5282 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5283 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5284 | return max_cdclk_freq; | |
5285 | else if (IS_CHERRYVIEW(dev_priv)) | |
5286 | return max_cdclk_freq*95/100; | |
5287 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5288 | return 2*max_cdclk_freq*90/100; | |
5289 | else | |
5290 | return max_cdclk_freq*90/100; | |
5291 | } | |
5292 | ||
b2045352 VS |
5293 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5294 | ||
560a7ae4 DL |
5295 | static void intel_update_max_cdclk(struct drm_device *dev) |
5296 | { | |
5297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5298 | ||
ef11bdb3 | 5299 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 | 5300 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5301 | int max_cdclk, vco; |
5302 | ||
5303 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5304 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5305 | |
b2045352 VS |
5306 | /* |
5307 | * Use the lower (vco 8640) cdclk values as a | |
5308 | * first guess. skl_calc_cdclk() will correct it | |
5309 | * if the preferred vco is 8100 instead. | |
5310 | */ | |
560a7ae4 | 5311 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5312 | max_cdclk = 617143; |
560a7ae4 | 5313 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5314 | max_cdclk = 540000; |
560a7ae4 | 5315 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5316 | max_cdclk = 432000; |
560a7ae4 | 5317 | else |
487ed2e4 | 5318 | max_cdclk = 308571; |
b2045352 VS |
5319 | |
5320 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
281c114f MR |
5321 | } else if (IS_BROXTON(dev)) { |
5322 | dev_priv->max_cdclk_freq = 624000; | |
560a7ae4 DL |
5323 | } else if (IS_BROADWELL(dev)) { |
5324 | /* | |
5325 | * FIXME with extra cooling we can allow | |
5326 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5327 | * How can we know if extra cooling is | |
5328 | * available? PCI ID, VTB, something else? | |
5329 | */ | |
5330 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5331 | dev_priv->max_cdclk_freq = 450000; | |
5332 | else if (IS_BDW_ULX(dev)) | |
5333 | dev_priv->max_cdclk_freq = 450000; | |
5334 | else if (IS_BDW_ULT(dev)) | |
5335 | dev_priv->max_cdclk_freq = 540000; | |
5336 | else | |
5337 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5338 | } else if (IS_CHERRYVIEW(dev)) { |
5339 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5340 | } else if (IS_VALLEYVIEW(dev)) { |
5341 | dev_priv->max_cdclk_freq = 400000; | |
5342 | } else { | |
5343 | /* otherwise assume cdclk is fixed */ | |
5344 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5345 | } | |
5346 | ||
adafdc6f MK |
5347 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5348 | ||
560a7ae4 DL |
5349 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5350 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5351 | |
5352 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5353 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5354 | } |
5355 | ||
5356 | static void intel_update_cdclk(struct drm_device *dev) | |
5357 | { | |
5358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5359 | ||
5360 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
2f2a121a | 5361 | |
83d7c81f | 5362 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5363 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5364 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5365 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5366 | else |
5367 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5368 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5369 | |
5370 | /* | |
b5d99ff9 VS |
5371 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5372 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5373 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5374 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5375 | */ |
b5d99ff9 | 5376 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5377 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5378 | } |
5379 | ||
92891e45 VS |
5380 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5381 | static int skl_cdclk_decimal(int cdclk) | |
5382 | { | |
5383 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5384 | } | |
5385 | ||
5f199dfa VS |
5386 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5387 | { | |
5388 | int ratio; | |
5389 | ||
5390 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5391 | return 0; | |
5392 | ||
5393 | switch (cdclk) { | |
5394 | default: | |
5395 | MISSING_CASE(cdclk); | |
5396 | case 144000: | |
5397 | case 288000: | |
5398 | case 384000: | |
5399 | case 576000: | |
5400 | ratio = 60; | |
5401 | break; | |
5402 | case 624000: | |
5403 | ratio = 65; | |
5404 | break; | |
5405 | } | |
5406 | ||
5407 | return dev_priv->cdclk_pll.ref * ratio; | |
5408 | } | |
5409 | ||
2b73001e VS |
5410 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5411 | { | |
5412 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5413 | ||
5414 | /* Timeout 200us */ | |
5415 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) | |
5416 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); | |
83d7c81f VS |
5417 | |
5418 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5419 | } |
5420 | ||
5f199dfa | 5421 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5422 | { |
5f199dfa | 5423 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5424 | u32 val; |
5425 | ||
5426 | val = I915_READ(BXT_DE_PLL_CTL); | |
5427 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5428 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5429 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5430 | ||
5431 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5432 | ||
5433 | /* Timeout 200us */ | |
5434 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) | |
5435 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
83d7c81f | 5436 | |
5f199dfa | 5437 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5438 | } |
5439 | ||
324513c0 | 5440 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5441 | { |
5f199dfa VS |
5442 | u32 val, divider; |
5443 | int vco, ret; | |
f8437dd1 | 5444 | |
5f199dfa VS |
5445 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
5446 | ||
5447 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5448 | ||
5449 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5450 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5451 | case 8: | |
f8437dd1 | 5452 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5453 | break; |
5f199dfa | 5454 | case 4: |
f8437dd1 | 5455 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 5456 | break; |
5f199dfa | 5457 | case 3: |
f8437dd1 | 5458 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 5459 | break; |
5f199dfa | 5460 | case 2: |
f8437dd1 | 5461 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
5462 | break; |
5463 | default: | |
5f199dfa VS |
5464 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
5465 | WARN_ON(vco != 0); | |
f8437dd1 | 5466 | |
5f199dfa VS |
5467 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
5468 | break; | |
f8437dd1 VK |
5469 | } |
5470 | ||
f8437dd1 | 5471 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 5472 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
5473 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
5474 | 0x80000000); | |
5475 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5476 | ||
5477 | if (ret) { | |
5478 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 5479 | ret, cdclk); |
f8437dd1 VK |
5480 | return; |
5481 | } | |
5482 | ||
5f199dfa VS |
5483 | if (dev_priv->cdclk_pll.vco != 0 && |
5484 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 5485 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 5486 | |
5f199dfa VS |
5487 | if (dev_priv->cdclk_pll.vco != vco) |
5488 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 5489 | |
5f199dfa VS |
5490 | val = divider | skl_cdclk_decimal(cdclk); |
5491 | /* | |
5492 | * FIXME if only the cd2x divider needs changing, it could be done | |
5493 | * without shutting off the pipe (if only one pipe is active). | |
5494 | */ | |
5495 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
5496 | /* | |
5497 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5498 | * enable otherwise. | |
5499 | */ | |
5500 | if (cdclk >= 500000) | |
5501 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5502 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
5503 | |
5504 | mutex_lock(&dev_priv->rps.hw_lock); | |
5505 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 5506 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
5507 | mutex_unlock(&dev_priv->rps.hw_lock); |
5508 | ||
5509 | if (ret) { | |
5510 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 5511 | ret, cdclk); |
f8437dd1 VK |
5512 | return; |
5513 | } | |
5514 | ||
c6c4696f | 5515 | intel_update_cdclk(dev_priv->dev); |
f8437dd1 VK |
5516 | } |
5517 | ||
d66a2194 | 5518 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5519 | { |
d66a2194 ID |
5520 | u32 cdctl, expected; |
5521 | ||
089c6fd5 | 5522 | intel_update_cdclk(dev_priv->dev); |
f8437dd1 | 5523 | |
d66a2194 ID |
5524 | if (dev_priv->cdclk_pll.vco == 0 || |
5525 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
5526 | goto sanitize; | |
5527 | ||
5528 | /* DPLL okay; verify the cdclock | |
5529 | * | |
5530 | * Some BIOS versions leave an incorrect decimal frequency value and | |
5531 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
5532 | * so sanitize this register. | |
5533 | */ | |
5534 | cdctl = I915_READ(CDCLK_CTL); | |
5535 | /* | |
5536 | * Let's ignore the pipe field, since BIOS could have configured the | |
5537 | * dividers both synching to an active pipe, or asynchronously | |
5538 | * (PIPE_NONE). | |
5539 | */ | |
5540 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
5541 | ||
5542 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
5543 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5544 | /* | |
5545 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5546 | * enable otherwise. | |
5547 | */ | |
5548 | if (dev_priv->cdclk_freq >= 500000) | |
5549 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5550 | ||
5551 | if (cdctl == expected) | |
5552 | /* All well; nothing to sanitize */ | |
5553 | return; | |
5554 | ||
5555 | sanitize: | |
5556 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
5557 | ||
5558 | /* force cdclk programming */ | |
5559 | dev_priv->cdclk_freq = 0; | |
5560 | ||
5561 | /* force full PLL disable + enable */ | |
5562 | dev_priv->cdclk_pll.vco = -1; | |
5563 | } | |
5564 | ||
324513c0 | 5565 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 ID |
5566 | { |
5567 | bxt_sanitize_cdclk(dev_priv); | |
5568 | ||
5569 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 5570 | return; |
c2e001ef | 5571 | |
f8437dd1 VK |
5572 | /* |
5573 | * FIXME: | |
5574 | * - The initial CDCLK needs to be read from VBT. | |
5575 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 5576 | */ |
324513c0 | 5577 | bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); |
f8437dd1 VK |
5578 | } |
5579 | ||
324513c0 | 5580 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5581 | { |
324513c0 | 5582 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
5583 | } |
5584 | ||
a8ca4934 VS |
5585 | static int skl_calc_cdclk(int max_pixclk, int vco) |
5586 | { | |
63911d72 | 5587 | if (vco == 8640000) { |
a8ca4934 | 5588 | if (max_pixclk > 540000) |
487ed2e4 | 5589 | return 617143; |
a8ca4934 VS |
5590 | else if (max_pixclk > 432000) |
5591 | return 540000; | |
487ed2e4 | 5592 | else if (max_pixclk > 308571) |
a8ca4934 VS |
5593 | return 432000; |
5594 | else | |
487ed2e4 | 5595 | return 308571; |
a8ca4934 | 5596 | } else { |
a8ca4934 VS |
5597 | if (max_pixclk > 540000) |
5598 | return 675000; | |
5599 | else if (max_pixclk > 450000) | |
5600 | return 540000; | |
5601 | else if (max_pixclk > 337500) | |
5602 | return 450000; | |
5603 | else | |
5604 | return 337500; | |
5605 | } | |
5606 | } | |
5607 | ||
ea61791e VS |
5608 | static void |
5609 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 5610 | { |
ea61791e | 5611 | u32 val; |
5d96d8af | 5612 | |
709e05c3 | 5613 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 5614 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 5615 | |
ea61791e | 5616 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 5617 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 5618 | return; |
5d96d8af | 5619 | |
1c3f7700 ID |
5620 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
5621 | return; | |
9f7eb31a | 5622 | |
ea61791e VS |
5623 | val = I915_READ(DPLL_CTRL1); |
5624 | ||
1c3f7700 ID |
5625 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
5626 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5627 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
5628 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
5629 | return; | |
9f7eb31a | 5630 | |
ea61791e VS |
5631 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
5632 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
5633 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
5634 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
5635 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 5636 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
5637 | break; |
5638 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
5639 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 5640 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
5641 | break; |
5642 | default: | |
5643 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
5644 | break; |
5645 | } | |
5d96d8af DL |
5646 | } |
5647 | ||
b2045352 VS |
5648 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
5649 | { | |
5650 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
5651 | ||
5652 | dev_priv->skl_preferred_vco_freq = vco; | |
5653 | ||
5654 | if (changed) | |
5655 | intel_update_max_cdclk(dev_priv->dev); | |
5656 | } | |
5657 | ||
5d96d8af | 5658 | static void |
3861fc60 | 5659 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 5660 | { |
a8ca4934 | 5661 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
5662 | u32 val; |
5663 | ||
63911d72 | 5664 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 5665 | |
5d96d8af | 5666 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 5667 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
5668 | I915_WRITE(CDCLK_CTL, val); |
5669 | POSTING_READ(CDCLK_CTL); | |
5670 | ||
5671 | /* | |
5672 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5673 | * taking into account the VCO required to operate the eDP panel at the | |
5674 | * desired frequency. The usual DP link rates operate with a VCO of | |
5675 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5676 | * The modeset code is responsible for the selection of the exact link | |
5677 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 5678 | * works with vco. |
5d96d8af DL |
5679 | */ |
5680 | val = I915_READ(DPLL_CTRL1); | |
5681 | ||
5682 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5683 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5684 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 5685 | if (vco == 8640000) |
5d96d8af DL |
5686 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
5687 | SKL_DPLL0); | |
5688 | else | |
5689 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5690 | SKL_DPLL0); | |
5691 | ||
5692 | I915_WRITE(DPLL_CTRL1, val); | |
5693 | POSTING_READ(DPLL_CTRL1); | |
5694 | ||
5695 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5696 | ||
5697 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5698 | DRM_ERROR("DPLL0 not locked\n"); | |
1cd593e0 | 5699 | |
63911d72 | 5700 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
5701 | |
5702 | /* We'll want to keep using the current vco from now on. */ | |
5703 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
5704 | } |
5705 | ||
430e05de VS |
5706 | static void |
5707 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
5708 | { | |
5709 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5710 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5711 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
1cd593e0 | 5712 | |
63911d72 | 5713 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
5714 | } |
5715 | ||
5d96d8af DL |
5716 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
5717 | { | |
5718 | int ret; | |
5719 | u32 val; | |
5720 | ||
5721 | /* inform PCU we want to change CDCLK */ | |
5722 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5723 | mutex_lock(&dev_priv->rps.hw_lock); | |
5724 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5725 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5726 | ||
5727 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5728 | } | |
5729 | ||
5730 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5731 | { | |
5732 | unsigned int i; | |
5733 | ||
5734 | for (i = 0; i < 15; i++) { | |
5735 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5736 | return true; | |
5737 | udelay(10); | |
5738 | } | |
5739 | ||
5740 | return false; | |
5741 | } | |
5742 | ||
1cd593e0 | 5743 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af | 5744 | { |
560a7ae4 | 5745 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5746 | u32 freq_select, pcu_ack; |
5747 | ||
1cd593e0 VS |
5748 | WARN_ON((cdclk == 24000) != (vco == 0)); |
5749 | ||
63911d72 | 5750 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
5751 | |
5752 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5753 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5754 | return; | |
5755 | } | |
5756 | ||
5757 | /* set CDCLK_CTL */ | |
9ef56154 | 5758 | switch (cdclk) { |
5d96d8af DL |
5759 | case 450000: |
5760 | case 432000: | |
5761 | freq_select = CDCLK_FREQ_450_432; | |
5762 | pcu_ack = 1; | |
5763 | break; | |
5764 | case 540000: | |
5765 | freq_select = CDCLK_FREQ_540; | |
5766 | pcu_ack = 2; | |
5767 | break; | |
487ed2e4 | 5768 | case 308571: |
5d96d8af DL |
5769 | case 337500: |
5770 | default: | |
5771 | freq_select = CDCLK_FREQ_337_308; | |
5772 | pcu_ack = 0; | |
5773 | break; | |
487ed2e4 | 5774 | case 617143: |
5d96d8af DL |
5775 | case 675000: |
5776 | freq_select = CDCLK_FREQ_675_617; | |
5777 | pcu_ack = 3; | |
5778 | break; | |
5779 | } | |
5780 | ||
63911d72 VS |
5781 | if (dev_priv->cdclk_pll.vco != 0 && |
5782 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
5783 | skl_dpll0_disable(dev_priv); |
5784 | ||
63911d72 | 5785 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
5786 | skl_dpll0_enable(dev_priv, vco); |
5787 | ||
9ef56154 | 5788 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
5789 | POSTING_READ(CDCLK_CTL); |
5790 | ||
5791 | /* inform PCU of the change */ | |
5792 | mutex_lock(&dev_priv->rps.hw_lock); | |
5793 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5794 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5795 | |
5796 | intel_update_cdclk(dev); | |
5d96d8af DL |
5797 | } |
5798 | ||
9f7eb31a VS |
5799 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
5800 | ||
5d96d8af DL |
5801 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
5802 | { | |
709e05c3 | 5803 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
5804 | } |
5805 | ||
5806 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5807 | { | |
9f7eb31a VS |
5808 | int cdclk, vco; |
5809 | ||
5810 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 5811 | |
63911d72 | 5812 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
5813 | /* |
5814 | * Use the current vco as our initial | |
5815 | * guess as to what the preferred vco is. | |
5816 | */ | |
5817 | if (dev_priv->skl_preferred_vco_freq == 0) | |
5818 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 5819 | dev_priv->cdclk_pll.vco); |
70c2c184 | 5820 | return; |
1cd593e0 | 5821 | } |
5d96d8af | 5822 | |
70c2c184 VS |
5823 | vco = dev_priv->skl_preferred_vco_freq; |
5824 | if (vco == 0) | |
63911d72 | 5825 | vco = 8100000; |
70c2c184 | 5826 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 5827 | |
70c2c184 | 5828 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
5829 | } |
5830 | ||
9f7eb31a | 5831 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 5832 | { |
09492498 | 5833 | uint32_t cdctl, expected; |
c73666f3 | 5834 | |
f1b391a5 SK |
5835 | /* |
5836 | * check if the pre-os intialized the display | |
5837 | * There is SWF18 scratchpad register defined which is set by the | |
5838 | * pre-os which can be used by the OS drivers to check the status | |
5839 | */ | |
5840 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5841 | goto sanitize; | |
5842 | ||
1c3f7700 | 5843 | intel_update_cdclk(dev_priv->dev); |
c73666f3 | 5844 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
5845 | if (dev_priv->cdclk_pll.vco == 0 || |
5846 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
5847 | goto sanitize; |
5848 | ||
5849 | /* DPLL okay; verify the cdclock | |
5850 | * | |
5851 | * Noticed in some instances that the freq selection is correct but | |
5852 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5853 | * enable display. Verify the same as well. | |
5854 | */ | |
09492498 VS |
5855 | cdctl = I915_READ(CDCLK_CTL); |
5856 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
5857 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5858 | if (cdctl == expected) | |
c73666f3 | 5859 | /* All well; nothing to sanitize */ |
9f7eb31a | 5860 | return; |
c89e39f3 | 5861 | |
9f7eb31a VS |
5862 | sanitize: |
5863 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 5864 | |
9f7eb31a VS |
5865 | /* force cdclk programming */ |
5866 | dev_priv->cdclk_freq = 0; | |
5867 | /* force full PLL disable + enable */ | |
63911d72 | 5868 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
5869 | } |
5870 | ||
30a970c6 JB |
5871 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5872 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5873 | { | |
5874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5875 | u32 val, cmd; | |
5876 | ||
164dfd28 VK |
5877 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5878 | != dev_priv->cdclk_freq); | |
d60c4473 | 5879 | |
dfcab17e | 5880 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5881 | cmd = 2; |
dfcab17e | 5882 | else if (cdclk == 266667) |
30a970c6 JB |
5883 | cmd = 1; |
5884 | else | |
5885 | cmd = 0; | |
5886 | ||
5887 | mutex_lock(&dev_priv->rps.hw_lock); | |
5888 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5889 | val &= ~DSPFREQGUAR_MASK; | |
5890 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5891 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5892 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5893 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5894 | 50)) { | |
5895 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5896 | } | |
5897 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5898 | ||
54433e91 VS |
5899 | mutex_lock(&dev_priv->sb_lock); |
5900 | ||
dfcab17e | 5901 | if (cdclk == 400000) { |
6bcda4f0 | 5902 | u32 divider; |
30a970c6 | 5903 | |
6bcda4f0 | 5904 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5905 | |
30a970c6 JB |
5906 | /* adjust cdclk divider */ |
5907 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5908 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5909 | val |= divider; |
5910 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5911 | |
5912 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5913 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5914 | 50)) |
5915 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5916 | } |
5917 | ||
30a970c6 JB |
5918 | /* adjust self-refresh exit latency value */ |
5919 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5920 | val &= ~0x7f; | |
5921 | ||
5922 | /* | |
5923 | * For high bandwidth configs, we set a higher latency in the bunit | |
5924 | * so that the core display fetch happens in time to avoid underruns. | |
5925 | */ | |
dfcab17e | 5926 | if (cdclk == 400000) |
30a970c6 JB |
5927 | val |= 4500 / 250; /* 4.5 usec */ |
5928 | else | |
5929 | val |= 3000 / 250; /* 3.0 usec */ | |
5930 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5931 | |
a580516d | 5932 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5933 | |
b6283055 | 5934 | intel_update_cdclk(dev); |
30a970c6 JB |
5935 | } |
5936 | ||
383c5a6a VS |
5937 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5938 | { | |
5939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5940 | u32 val, cmd; | |
5941 | ||
164dfd28 VK |
5942 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5943 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5944 | |
5945 | switch (cdclk) { | |
383c5a6a VS |
5946 | case 333333: |
5947 | case 320000: | |
383c5a6a | 5948 | case 266667: |
383c5a6a | 5949 | case 200000: |
383c5a6a VS |
5950 | break; |
5951 | default: | |
5f77eeb0 | 5952 | MISSING_CASE(cdclk); |
383c5a6a VS |
5953 | return; |
5954 | } | |
5955 | ||
9d0d3fda VS |
5956 | /* |
5957 | * Specs are full of misinformation, but testing on actual | |
5958 | * hardware has shown that we just need to write the desired | |
5959 | * CCK divider into the Punit register. | |
5960 | */ | |
5961 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5962 | ||
383c5a6a VS |
5963 | mutex_lock(&dev_priv->rps.hw_lock); |
5964 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5965 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5966 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5967 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5968 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5969 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5970 | 50)) { | |
5971 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5972 | } | |
5973 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5974 | ||
b6283055 | 5975 | intel_update_cdclk(dev); |
383c5a6a VS |
5976 | } |
5977 | ||
30a970c6 JB |
5978 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5979 | int max_pixclk) | |
5980 | { | |
6bcda4f0 | 5981 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5982 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5983 | |
30a970c6 JB |
5984 | /* |
5985 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5986 | * 200MHz | |
5987 | * 267MHz | |
29dc7ef3 | 5988 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5989 | * 400MHz (VLV only) |
5990 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5991 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5992 | * |
5993 | * We seem to get an unstable or solid color picture at 200MHz. | |
5994 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5995 | * are off. | |
30a970c6 | 5996 | */ |
6cca3195 VS |
5997 | if (!IS_CHERRYVIEW(dev_priv) && |
5998 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5999 | return 400000; |
6cca3195 | 6000 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6001 | return freq_320; |
e37c67a1 | 6002 | else if (max_pixclk > 0) |
dfcab17e | 6003 | return 266667; |
e37c67a1 VS |
6004 | else |
6005 | return 200000; | |
30a970c6 JB |
6006 | } |
6007 | ||
324513c0 | 6008 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 6009 | { |
760e1477 | 6010 | if (max_pixclk > 576000) |
f8437dd1 | 6011 | return 624000; |
760e1477 | 6012 | else if (max_pixclk > 384000) |
f8437dd1 | 6013 | return 576000; |
760e1477 | 6014 | else if (max_pixclk > 288000) |
f8437dd1 | 6015 | return 384000; |
760e1477 | 6016 | else if (max_pixclk > 144000) |
f8437dd1 VK |
6017 | return 288000; |
6018 | else | |
6019 | return 144000; | |
6020 | } | |
6021 | ||
e8788cbc | 6022 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6023 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6024 | struct drm_atomic_state *state) | |
30a970c6 | 6025 | { |
565602d7 ML |
6026 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
6027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6028 | struct drm_crtc *crtc; | |
6029 | struct drm_crtc_state *crtc_state; | |
6030 | unsigned max_pixclk = 0, i; | |
6031 | enum pipe pipe; | |
30a970c6 | 6032 | |
565602d7 ML |
6033 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6034 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6035 | |
565602d7 ML |
6036 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6037 | int pixclk = 0; | |
6038 | ||
6039 | if (crtc_state->enable) | |
6040 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6041 | |
565602d7 | 6042 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6043 | } |
6044 | ||
565602d7 ML |
6045 | for_each_pipe(dev_priv, pipe) |
6046 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6047 | ||
30a970c6 JB |
6048 | return max_pixclk; |
6049 | } | |
6050 | ||
27c329ed | 6051 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6052 | { |
27c329ed ML |
6053 | struct drm_device *dev = state->dev; |
6054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6055 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6056 | struct intel_atomic_state *intel_state = |
6057 | to_intel_atomic_state(state); | |
30a970c6 | 6058 | |
1a617b77 | 6059 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6060 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6061 | |
1a617b77 ML |
6062 | if (!intel_state->active_crtcs) |
6063 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6064 | ||
27c329ed ML |
6065 | return 0; |
6066 | } | |
304603f4 | 6067 | |
324513c0 | 6068 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6069 | { |
4e5ca60f | 6070 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6071 | struct intel_atomic_state *intel_state = |
6072 | to_intel_atomic_state(state); | |
85a96e7a | 6073 | |
1a617b77 | 6074 | intel_state->cdclk = intel_state->dev_cdclk = |
324513c0 | 6075 | bxt_calc_cdclk(max_pixclk); |
85a96e7a | 6076 | |
1a617b77 | 6077 | if (!intel_state->active_crtcs) |
324513c0 | 6078 | intel_state->dev_cdclk = bxt_calc_cdclk(0); |
1a617b77 | 6079 | |
27c329ed | 6080 | return 0; |
30a970c6 JB |
6081 | } |
6082 | ||
1e69cd74 VS |
6083 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6084 | { | |
6085 | unsigned int credits, default_credits; | |
6086 | ||
6087 | if (IS_CHERRYVIEW(dev_priv)) | |
6088 | default_credits = PFI_CREDIT(12); | |
6089 | else | |
6090 | default_credits = PFI_CREDIT(8); | |
6091 | ||
bfa7df01 | 6092 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6093 | /* CHV suggested value is 31 or 63 */ |
6094 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6095 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6096 | else |
6097 | credits = PFI_CREDIT(15); | |
6098 | } else { | |
6099 | credits = default_credits; | |
6100 | } | |
6101 | ||
6102 | /* | |
6103 | * WA - write default credits before re-programming | |
6104 | * FIXME: should we also set the resend bit here? | |
6105 | */ | |
6106 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6107 | default_credits); | |
6108 | ||
6109 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6110 | credits | PFI_CREDIT_RESEND); | |
6111 | ||
6112 | /* | |
6113 | * FIXME is this guaranteed to clear | |
6114 | * immediately or should we poll for it? | |
6115 | */ | |
6116 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6117 | } | |
6118 | ||
27c329ed | 6119 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6120 | { |
a821fc46 | 6121 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6122 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6123 | struct intel_atomic_state *old_intel_state = |
6124 | to_intel_atomic_state(old_state); | |
6125 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6126 | |
27c329ed ML |
6127 | /* |
6128 | * FIXME: We can end up here with all power domains off, yet | |
6129 | * with a CDCLK frequency other than the minimum. To account | |
6130 | * for this take the PIPE-A power domain, which covers the HW | |
6131 | * blocks needed for the following programming. This can be | |
6132 | * removed once it's guaranteed that we get here either with | |
6133 | * the minimum CDCLK set, or the required power domains | |
6134 | * enabled. | |
6135 | */ | |
6136 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6137 | |
27c329ed ML |
6138 | if (IS_CHERRYVIEW(dev)) |
6139 | cherryview_set_cdclk(dev, req_cdclk); | |
6140 | else | |
6141 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6142 | |
27c329ed | 6143 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6144 | |
27c329ed | 6145 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6146 | } |
6147 | ||
89b667f8 JB |
6148 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6149 | { | |
6150 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6151 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6152 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6153 | struct intel_encoder *encoder; | |
b95c5321 ML |
6154 | struct intel_crtc_state *pipe_config = |
6155 | to_intel_crtc_state(crtc->state); | |
89b667f8 | 6156 | int pipe = intel_crtc->pipe; |
89b667f8 | 6157 | |
53d9f4e9 | 6158 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6159 | return; |
6160 | ||
6e3c9717 | 6161 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6162 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6163 | |
6164 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6165 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6166 | |
c14b0485 VS |
6167 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6169 | ||
6170 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6171 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6172 | } | |
6173 | ||
5b18e57c DV |
6174 | i9xx_set_pipeconf(intel_crtc); |
6175 | ||
89b667f8 | 6176 | intel_crtc->active = true; |
89b667f8 | 6177 | |
a72e4c9f | 6178 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6179 | |
89b667f8 JB |
6180 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6181 | if (encoder->pre_pll_enable) | |
6182 | encoder->pre_pll_enable(encoder); | |
6183 | ||
cd2d34d9 VS |
6184 | if (IS_CHERRYVIEW(dev)) { |
6185 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6186 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6187 | } else { | |
6188 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6189 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6190 | } |
89b667f8 JB |
6191 | |
6192 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6193 | if (encoder->pre_enable) | |
6194 | encoder->pre_enable(encoder); | |
6195 | ||
2dd24552 JB |
6196 | i9xx_pfit_enable(intel_crtc); |
6197 | ||
b95c5321 | 6198 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6199 | |
caed361d | 6200 | intel_update_watermarks(crtc); |
e1fdc473 | 6201 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6202 | |
4b3a9526 VS |
6203 | assert_vblank_disabled(crtc); |
6204 | drm_crtc_vblank_on(crtc); | |
6205 | ||
f9b61ff6 DV |
6206 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6207 | encoder->enable(encoder); | |
89b667f8 JB |
6208 | } |
6209 | ||
f13c2ef3 DV |
6210 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6211 | { | |
6212 | struct drm_device *dev = crtc->base.dev; | |
6213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6214 | ||
6e3c9717 ACO |
6215 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6216 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6217 | } |
6218 | ||
0b8765c6 | 6219 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6220 | { |
6221 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6222 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6223 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6224 | struct intel_encoder *encoder; |
b95c5321 ML |
6225 | struct intel_crtc_state *pipe_config = |
6226 | to_intel_crtc_state(crtc->state); | |
cd2d34d9 | 6227 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6228 | |
53d9f4e9 | 6229 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6230 | return; |
6231 | ||
f13c2ef3 DV |
6232 | i9xx_set_pll_dividers(intel_crtc); |
6233 | ||
6e3c9717 | 6234 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6235 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6236 | |
6237 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6238 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6239 | |
5b18e57c DV |
6240 | i9xx_set_pipeconf(intel_crtc); |
6241 | ||
f7abfe8b | 6242 | intel_crtc->active = true; |
6b383a7f | 6243 | |
4a3436e8 | 6244 | if (!IS_GEN2(dev)) |
a72e4c9f | 6245 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6246 | |
9d6d9f19 MK |
6247 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6248 | if (encoder->pre_enable) | |
6249 | encoder->pre_enable(encoder); | |
6250 | ||
f6736a1a DV |
6251 | i9xx_enable_pll(intel_crtc); |
6252 | ||
2dd24552 JB |
6253 | i9xx_pfit_enable(intel_crtc); |
6254 | ||
b95c5321 | 6255 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6256 | |
f37fcc2a | 6257 | intel_update_watermarks(crtc); |
e1fdc473 | 6258 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6259 | |
4b3a9526 VS |
6260 | assert_vblank_disabled(crtc); |
6261 | drm_crtc_vblank_on(crtc); | |
6262 | ||
f9b61ff6 DV |
6263 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6264 | encoder->enable(encoder); | |
0b8765c6 | 6265 | } |
79e53945 | 6266 | |
87476d63 DV |
6267 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6268 | { | |
6269 | struct drm_device *dev = crtc->base.dev; | |
6270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6271 | |
6e3c9717 | 6272 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6273 | return; |
87476d63 | 6274 | |
328d8e82 | 6275 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6276 | |
328d8e82 DV |
6277 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6278 | I915_READ(PFIT_CONTROL)); | |
6279 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6280 | } |
6281 | ||
0b8765c6 JB |
6282 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6283 | { | |
6284 | struct drm_device *dev = crtc->dev; | |
6285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6286 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6287 | struct intel_encoder *encoder; |
0b8765c6 | 6288 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6289 | |
6304cd91 VS |
6290 | /* |
6291 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6292 | * wait for planes to fully turn off before disabling the pipe. | |
6293 | */ | |
90e83e53 ACO |
6294 | if (IS_GEN2(dev)) |
6295 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6296 | |
4b3a9526 VS |
6297 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6298 | encoder->disable(encoder); | |
6299 | ||
f9b61ff6 DV |
6300 | drm_crtc_vblank_off(crtc); |
6301 | assert_vblank_disabled(crtc); | |
6302 | ||
575f7ab7 | 6303 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6304 | |
87476d63 | 6305 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6306 | |
89b667f8 JB |
6307 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6308 | if (encoder->post_disable) | |
6309 | encoder->post_disable(encoder); | |
6310 | ||
a65347ba | 6311 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6312 | if (IS_CHERRYVIEW(dev)) |
6313 | chv_disable_pll(dev_priv, pipe); | |
6314 | else if (IS_VALLEYVIEW(dev)) | |
6315 | vlv_disable_pll(dev_priv, pipe); | |
6316 | else | |
1c4e0274 | 6317 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6318 | } |
0b8765c6 | 6319 | |
d6db995f VS |
6320 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6321 | if (encoder->post_pll_disable) | |
6322 | encoder->post_pll_disable(encoder); | |
6323 | ||
4a3436e8 | 6324 | if (!IS_GEN2(dev)) |
a72e4c9f | 6325 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6326 | } |
6327 | ||
b17d48e2 ML |
6328 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6329 | { | |
842e0307 | 6330 | struct intel_encoder *encoder; |
b17d48e2 ML |
6331 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6332 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6333 | enum intel_display_power_domain domain; | |
6334 | unsigned long domains; | |
6335 | ||
6336 | if (!intel_crtc->active) | |
6337 | return; | |
6338 | ||
a539205a | 6339 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
5a21b665 | 6340 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6341 | |
2622a081 | 6342 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6343 | |
6344 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6345 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6346 | } |
6347 | ||
b17d48e2 | 6348 | dev_priv->display.crtc_disable(crtc); |
842e0307 | 6349 | |
78108b7c VS |
6350 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6351 | crtc->base.id, crtc->name); | |
842e0307 ML |
6352 | |
6353 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6354 | crtc->state->active = false; | |
37d9078b | 6355 | intel_crtc->active = false; |
842e0307 ML |
6356 | crtc->enabled = false; |
6357 | crtc->state->connector_mask = 0; | |
6358 | crtc->state->encoder_mask = 0; | |
6359 | ||
6360 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6361 | encoder->base.crtc = NULL; | |
6362 | ||
58f9c0bc | 6363 | intel_fbc_disable(intel_crtc); |
37d9078b | 6364 | intel_update_watermarks(crtc); |
1f7457b1 | 6365 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6366 | |
6367 | domains = intel_crtc->enabled_power_domains; | |
6368 | for_each_power_domain(domain, domains) | |
6369 | intel_display_power_put(dev_priv, domain); | |
6370 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6371 | |
6372 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6373 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6374 | } |
6375 | ||
6b72d486 ML |
6376 | /* |
6377 | * turn all crtc's off, but do not adjust state | |
6378 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6379 | */ | |
70e0bd74 | 6380 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6381 | { |
e2c8b870 | 6382 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6383 | struct drm_atomic_state *state; |
e2c8b870 | 6384 | int ret; |
70e0bd74 | 6385 | |
e2c8b870 ML |
6386 | state = drm_atomic_helper_suspend(dev); |
6387 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6388 | if (ret) |
6389 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6390 | else |
6391 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6392 | return ret; |
ee7b9f93 JB |
6393 | } |
6394 | ||
ea5b213a | 6395 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6396 | { |
4ef69c7a | 6397 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6398 | |
ea5b213a CW |
6399 | drm_encoder_cleanup(encoder); |
6400 | kfree(intel_encoder); | |
7e7d76c3 JB |
6401 | } |
6402 | ||
0a91ca29 DV |
6403 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6404 | * internal consistency). */ | |
5a21b665 | 6405 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6406 | { |
5a21b665 | 6407 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6408 | |
6409 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6410 | connector->base.base.id, | |
6411 | connector->base.name); | |
6412 | ||
0a91ca29 | 6413 | if (connector->get_hw_state(connector)) { |
e85376cb | 6414 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6415 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6416 | |
35dd3c64 ML |
6417 | I915_STATE_WARN(!crtc, |
6418 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6419 | |
35dd3c64 ML |
6420 | if (!crtc) |
6421 | return; | |
6422 | ||
6423 | I915_STATE_WARN(!crtc->state->active, | |
6424 | "connector is active, but attached crtc isn't\n"); | |
6425 | ||
e85376cb | 6426 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6427 | return; |
6428 | ||
e85376cb | 6429 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6430 | "atomic encoder doesn't match attached encoder\n"); |
6431 | ||
e85376cb | 6432 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6433 | "attached encoder crtc differs from connector crtc\n"); |
6434 | } else { | |
4d688a2a ML |
6435 | I915_STATE_WARN(crtc && crtc->state->active, |
6436 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 6437 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 6438 | "best encoder set without crtc!\n"); |
0a91ca29 | 6439 | } |
79e53945 JB |
6440 | } |
6441 | ||
08d9bc92 ACO |
6442 | int intel_connector_init(struct intel_connector *connector) |
6443 | { | |
5350a031 | 6444 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6445 | |
5350a031 | 6446 | if (!connector->base.state) |
08d9bc92 ACO |
6447 | return -ENOMEM; |
6448 | ||
08d9bc92 ACO |
6449 | return 0; |
6450 | } | |
6451 | ||
6452 | struct intel_connector *intel_connector_alloc(void) | |
6453 | { | |
6454 | struct intel_connector *connector; | |
6455 | ||
6456 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6457 | if (!connector) | |
6458 | return NULL; | |
6459 | ||
6460 | if (intel_connector_init(connector) < 0) { | |
6461 | kfree(connector); | |
6462 | return NULL; | |
6463 | } | |
6464 | ||
6465 | return connector; | |
6466 | } | |
6467 | ||
f0947c37 DV |
6468 | /* Simple connector->get_hw_state implementation for encoders that support only |
6469 | * one connector and no cloning and hence the encoder state determines the state | |
6470 | * of the connector. */ | |
6471 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6472 | { |
24929352 | 6473 | enum pipe pipe = 0; |
f0947c37 | 6474 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6475 | |
f0947c37 | 6476 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6477 | } |
6478 | ||
6d293983 | 6479 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6480 | { |
6d293983 ACO |
6481 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6482 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6483 | |
6484 | return 0; | |
6485 | } | |
6486 | ||
6d293983 | 6487 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6488 | struct intel_crtc_state *pipe_config) |
1857e1da | 6489 | { |
6d293983 ACO |
6490 | struct drm_atomic_state *state = pipe_config->base.state; |
6491 | struct intel_crtc *other_crtc; | |
6492 | struct intel_crtc_state *other_crtc_state; | |
6493 | ||
1857e1da DV |
6494 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6495 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6496 | if (pipe_config->fdi_lanes > 4) { | |
6497 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6498 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6499 | return -EINVAL; |
1857e1da DV |
6500 | } |
6501 | ||
bafb6553 | 6502 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6503 | if (pipe_config->fdi_lanes > 2) { |
6504 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6505 | pipe_config->fdi_lanes); | |
6d293983 | 6506 | return -EINVAL; |
1857e1da | 6507 | } else { |
6d293983 | 6508 | return 0; |
1857e1da DV |
6509 | } |
6510 | } | |
6511 | ||
6512 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6513 | return 0; |
1857e1da DV |
6514 | |
6515 | /* Ivybridge 3 pipe is really complicated */ | |
6516 | switch (pipe) { | |
6517 | case PIPE_A: | |
6d293983 | 6518 | return 0; |
1857e1da | 6519 | case PIPE_B: |
6d293983 ACO |
6520 | if (pipe_config->fdi_lanes <= 2) |
6521 | return 0; | |
6522 | ||
6523 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6524 | other_crtc_state = | |
6525 | intel_atomic_get_crtc_state(state, other_crtc); | |
6526 | if (IS_ERR(other_crtc_state)) | |
6527 | return PTR_ERR(other_crtc_state); | |
6528 | ||
6529 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6530 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6531 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6532 | return -EINVAL; |
1857e1da | 6533 | } |
6d293983 | 6534 | return 0; |
1857e1da | 6535 | case PIPE_C: |
251cc67c VS |
6536 | if (pipe_config->fdi_lanes > 2) { |
6537 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6538 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6539 | return -EINVAL; |
251cc67c | 6540 | } |
6d293983 ACO |
6541 | |
6542 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6543 | other_crtc_state = | |
6544 | intel_atomic_get_crtc_state(state, other_crtc); | |
6545 | if (IS_ERR(other_crtc_state)) | |
6546 | return PTR_ERR(other_crtc_state); | |
6547 | ||
6548 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6549 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6550 | return -EINVAL; |
1857e1da | 6551 | } |
6d293983 | 6552 | return 0; |
1857e1da DV |
6553 | default: |
6554 | BUG(); | |
6555 | } | |
6556 | } | |
6557 | ||
e29c22c0 DV |
6558 | #define RETRY 1 |
6559 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6560 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6561 | { |
1857e1da | 6562 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6563 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6564 | int lane, link_bw, fdi_dotclock, ret; |
6565 | bool needs_recompute = false; | |
877d48d5 | 6566 | |
e29c22c0 | 6567 | retry: |
877d48d5 DV |
6568 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6569 | * each output octet as 10 bits. The actual frequency | |
6570 | * is stored as a divider into a 100MHz clock, and the | |
6571 | * mode pixel clock is stored in units of 1KHz. | |
6572 | * Hence the bw of each lane in terms of the mode signal | |
6573 | * is: | |
6574 | */ | |
21a727b3 | 6575 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6576 | |
241bfc38 | 6577 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6578 | |
2bd89a07 | 6579 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6580 | pipe_config->pipe_bpp); |
6581 | ||
6582 | pipe_config->fdi_lanes = lane; | |
6583 | ||
2bd89a07 | 6584 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6585 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6586 | |
e3b247da | 6587 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6588 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6589 | pipe_config->pipe_bpp -= 2*3; |
6590 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6591 | pipe_config->pipe_bpp); | |
6592 | needs_recompute = true; | |
6593 | pipe_config->bw_constrained = true; | |
6594 | ||
6595 | goto retry; | |
6596 | } | |
6597 | ||
6598 | if (needs_recompute) | |
6599 | return RETRY; | |
6600 | ||
6d293983 | 6601 | return ret; |
877d48d5 DV |
6602 | } |
6603 | ||
8cfb3407 VS |
6604 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6605 | struct intel_crtc_state *pipe_config) | |
6606 | { | |
6607 | if (pipe_config->pipe_bpp > 24) | |
6608 | return false; | |
6609 | ||
6610 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 6611 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
6612 | return true; |
6613 | ||
6614 | /* | |
b432e5cf VS |
6615 | * We compare against max which means we must take |
6616 | * the increased cdclk requirement into account when | |
6617 | * calculating the new cdclk. | |
6618 | * | |
6619 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6620 | */ |
6621 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6622 | dev_priv->max_cdclk_freq * 95 / 100; | |
6623 | } | |
6624 | ||
42db64ef | 6625 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6626 | struct intel_crtc_state *pipe_config) |
42db64ef | 6627 | { |
8cfb3407 VS |
6628 | struct drm_device *dev = crtc->base.dev; |
6629 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6630 | ||
d330a953 | 6631 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6632 | hsw_crtc_supports_ips(crtc) && |
6633 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6634 | } |
6635 | ||
39acb4aa VS |
6636 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6637 | { | |
6638 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6639 | ||
6640 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6641 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6642 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6643 | } | |
6644 | ||
a43f6e0f | 6645 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6646 | struct intel_crtc_state *pipe_config) |
79e53945 | 6647 | { |
a43f6e0f | 6648 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6649 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6650 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 6651 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 6652 | |
cf532bb2 | 6653 | if (INTEL_INFO(dev)->gen < 4) { |
f3261156 | 6654 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6655 | |
6656 | /* | |
39acb4aa | 6657 | * Enable double wide mode when the dot clock |
cf532bb2 | 6658 | * is > 90% of the (display) core speed. |
cf532bb2 | 6659 | */ |
39acb4aa VS |
6660 | if (intel_crtc_supports_double_wide(crtc) && |
6661 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 6662 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 6663 | pipe_config->double_wide = true; |
ad3a4479 | 6664 | } |
f3261156 | 6665 | } |
ad3a4479 | 6666 | |
f3261156 VS |
6667 | if (adjusted_mode->crtc_clock > clock_limit) { |
6668 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6669 | adjusted_mode->crtc_clock, clock_limit, | |
6670 | yesno(pipe_config->double_wide)); | |
6671 | return -EINVAL; | |
2c07245f | 6672 | } |
89749350 | 6673 | |
1d1d0e27 VS |
6674 | /* |
6675 | * Pipe horizontal size must be even in: | |
6676 | * - DVO ganged mode | |
6677 | * - LVDS dual channel mode | |
6678 | * - Double wide pipe | |
6679 | */ | |
a93e255f | 6680 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6681 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6682 | pipe_config->pipe_src_w &= ~1; | |
6683 | ||
8693a824 DL |
6684 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6685 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6686 | */ |
6687 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6688 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6689 | return -EINVAL; |
44f46b42 | 6690 | |
f5adf94e | 6691 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6692 | hsw_compute_ips_config(crtc, pipe_config); |
6693 | ||
877d48d5 | 6694 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6695 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6696 | |
cf5a15be | 6697 | return 0; |
79e53945 JB |
6698 | } |
6699 | ||
1652d19e VS |
6700 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6701 | { | |
6702 | struct drm_i915_private *dev_priv = to_i915(dev); | |
ea61791e | 6703 | uint32_t cdctl; |
1652d19e | 6704 | |
ea61791e | 6705 | skl_dpll0_update(dev_priv); |
1652d19e | 6706 | |
63911d72 | 6707 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 6708 | return dev_priv->cdclk_pll.ref; |
1652d19e | 6709 | |
ea61791e | 6710 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 6711 | |
63911d72 | 6712 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
6713 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6714 | case CDCLK_FREQ_450_432: | |
6715 | return 432000; | |
6716 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 6717 | return 308571; |
ea61791e VS |
6718 | case CDCLK_FREQ_540: |
6719 | return 540000; | |
1652d19e | 6720 | case CDCLK_FREQ_675_617: |
487ed2e4 | 6721 | return 617143; |
1652d19e | 6722 | default: |
ea61791e | 6723 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6724 | } |
6725 | } else { | |
1652d19e VS |
6726 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6727 | case CDCLK_FREQ_450_432: | |
6728 | return 450000; | |
6729 | case CDCLK_FREQ_337_308: | |
6730 | return 337500; | |
ea61791e VS |
6731 | case CDCLK_FREQ_540: |
6732 | return 540000; | |
1652d19e VS |
6733 | case CDCLK_FREQ_675_617: |
6734 | return 675000; | |
6735 | default: | |
ea61791e | 6736 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6737 | } |
6738 | } | |
6739 | ||
709e05c3 | 6740 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
6741 | } |
6742 | ||
83d7c81f VS |
6743 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
6744 | { | |
6745 | u32 val; | |
6746 | ||
6747 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 6748 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
6749 | |
6750 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 6751 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 6752 | return; |
83d7c81f | 6753 | |
1c3f7700 ID |
6754 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
6755 | return; | |
83d7c81f VS |
6756 | |
6757 | val = I915_READ(BXT_DE_PLL_CTL); | |
6758 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
6759 | dev_priv->cdclk_pll.ref; | |
6760 | } | |
6761 | ||
acd3f3d3 BP |
6762 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6763 | { | |
6764 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f5986242 VS |
6765 | u32 divider; |
6766 | int div, vco; | |
acd3f3d3 | 6767 | |
83d7c81f VS |
6768 | bxt_de_pll_update(dev_priv); |
6769 | ||
f5986242 VS |
6770 | vco = dev_priv->cdclk_pll.vco; |
6771 | if (vco == 0) | |
6772 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 6773 | |
f5986242 | 6774 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 6775 | |
f5986242 | 6776 | switch (divider) { |
acd3f3d3 | 6777 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
6778 | div = 2; |
6779 | break; | |
acd3f3d3 | 6780 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
f5986242 VS |
6781 | div = 3; |
6782 | break; | |
acd3f3d3 | 6783 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
6784 | div = 4; |
6785 | break; | |
acd3f3d3 | 6786 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
6787 | div = 8; |
6788 | break; | |
6789 | default: | |
6790 | MISSING_CASE(divider); | |
6791 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
6792 | } |
6793 | ||
f5986242 | 6794 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
6795 | } |
6796 | ||
1652d19e VS |
6797 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6798 | { | |
6799 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6800 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6801 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6802 | ||
6803 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6804 | return 800000; | |
6805 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6806 | return 450000; | |
6807 | else if (freq == LCPLL_CLK_FREQ_450) | |
6808 | return 450000; | |
6809 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6810 | return 540000; | |
6811 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6812 | return 337500; | |
6813 | else | |
6814 | return 675000; | |
6815 | } | |
6816 | ||
6817 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6818 | { | |
6819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6820 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6821 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6822 | ||
6823 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6824 | return 800000; | |
6825 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6826 | return 450000; | |
6827 | else if (freq == LCPLL_CLK_FREQ_450) | |
6828 | return 450000; | |
6829 | else if (IS_HSW_ULT(dev)) | |
6830 | return 337500; | |
6831 | else | |
6832 | return 540000; | |
79e53945 JB |
6833 | } |
6834 | ||
25eb05fc JB |
6835 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6836 | { | |
bfa7df01 VS |
6837 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6838 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6839 | } |
6840 | ||
b37a6434 VS |
6841 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6842 | { | |
6843 | return 450000; | |
6844 | } | |
6845 | ||
e70236a8 JB |
6846 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6847 | { | |
6848 | return 400000; | |
6849 | } | |
79e53945 | 6850 | |
e70236a8 | 6851 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6852 | { |
e907f170 | 6853 | return 333333; |
e70236a8 | 6854 | } |
79e53945 | 6855 | |
e70236a8 JB |
6856 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6857 | { | |
6858 | return 200000; | |
6859 | } | |
79e53945 | 6860 | |
257a7ffc DV |
6861 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6862 | { | |
6863 | u16 gcfgc = 0; | |
6864 | ||
6865 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6866 | ||
6867 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6868 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6869 | return 266667; |
257a7ffc | 6870 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6871 | return 333333; |
257a7ffc | 6872 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6873 | return 444444; |
257a7ffc DV |
6874 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6875 | return 200000; | |
6876 | default: | |
6877 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6878 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6879 | return 133333; |
257a7ffc | 6880 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6881 | return 166667; |
257a7ffc DV |
6882 | } |
6883 | } | |
6884 | ||
e70236a8 JB |
6885 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6886 | { | |
6887 | u16 gcfgc = 0; | |
79e53945 | 6888 | |
e70236a8 JB |
6889 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6890 | ||
6891 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6892 | return 133333; |
e70236a8 JB |
6893 | else { |
6894 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6895 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6896 | return 333333; |
e70236a8 JB |
6897 | default: |
6898 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6899 | return 190000; | |
79e53945 | 6900 | } |
e70236a8 JB |
6901 | } |
6902 | } | |
6903 | ||
6904 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6905 | { | |
e907f170 | 6906 | return 266667; |
e70236a8 JB |
6907 | } |
6908 | ||
1b1d2716 | 6909 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6910 | { |
6911 | u16 hpllcc = 0; | |
1b1d2716 | 6912 | |
65cd2b3f VS |
6913 | /* |
6914 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6915 | * encoding is different :( | |
6916 | * FIXME is this the right way to detect 852GM/852GMV? | |
6917 | */ | |
6918 | if (dev->pdev->revision == 0x1) | |
6919 | return 133333; | |
6920 | ||
1b1d2716 VS |
6921 | pci_bus_read_config_word(dev->pdev->bus, |
6922 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6923 | ||
e70236a8 JB |
6924 | /* Assume that the hardware is in the high speed state. This |
6925 | * should be the default. | |
6926 | */ | |
6927 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6928 | case GC_CLOCK_133_200: | |
1b1d2716 | 6929 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6930 | case GC_CLOCK_100_200: |
6931 | return 200000; | |
6932 | case GC_CLOCK_166_250: | |
6933 | return 250000; | |
6934 | case GC_CLOCK_100_133: | |
e907f170 | 6935 | return 133333; |
1b1d2716 VS |
6936 | case GC_CLOCK_133_266: |
6937 | case GC_CLOCK_133_266_2: | |
6938 | case GC_CLOCK_166_266: | |
6939 | return 266667; | |
e70236a8 | 6940 | } |
79e53945 | 6941 | |
e70236a8 JB |
6942 | /* Shouldn't happen */ |
6943 | return 0; | |
6944 | } | |
79e53945 | 6945 | |
e70236a8 JB |
6946 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6947 | { | |
e907f170 | 6948 | return 133333; |
79e53945 JB |
6949 | } |
6950 | ||
34edce2f VS |
6951 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6952 | { | |
6953 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6954 | static const unsigned int blb_vco[8] = { | |
6955 | [0] = 3200000, | |
6956 | [1] = 4000000, | |
6957 | [2] = 5333333, | |
6958 | [3] = 4800000, | |
6959 | [4] = 6400000, | |
6960 | }; | |
6961 | static const unsigned int pnv_vco[8] = { | |
6962 | [0] = 3200000, | |
6963 | [1] = 4000000, | |
6964 | [2] = 5333333, | |
6965 | [3] = 4800000, | |
6966 | [4] = 2666667, | |
6967 | }; | |
6968 | static const unsigned int cl_vco[8] = { | |
6969 | [0] = 3200000, | |
6970 | [1] = 4000000, | |
6971 | [2] = 5333333, | |
6972 | [3] = 6400000, | |
6973 | [4] = 3333333, | |
6974 | [5] = 3566667, | |
6975 | [6] = 4266667, | |
6976 | }; | |
6977 | static const unsigned int elk_vco[8] = { | |
6978 | [0] = 3200000, | |
6979 | [1] = 4000000, | |
6980 | [2] = 5333333, | |
6981 | [3] = 4800000, | |
6982 | }; | |
6983 | static const unsigned int ctg_vco[8] = { | |
6984 | [0] = 3200000, | |
6985 | [1] = 4000000, | |
6986 | [2] = 5333333, | |
6987 | [3] = 6400000, | |
6988 | [4] = 2666667, | |
6989 | [5] = 4266667, | |
6990 | }; | |
6991 | const unsigned int *vco_table; | |
6992 | unsigned int vco; | |
6993 | uint8_t tmp = 0; | |
6994 | ||
6995 | /* FIXME other chipsets? */ | |
6996 | if (IS_GM45(dev)) | |
6997 | vco_table = ctg_vco; | |
6998 | else if (IS_G4X(dev)) | |
6999 | vco_table = elk_vco; | |
7000 | else if (IS_CRESTLINE(dev)) | |
7001 | vco_table = cl_vco; | |
7002 | else if (IS_PINEVIEW(dev)) | |
7003 | vco_table = pnv_vco; | |
7004 | else if (IS_G33(dev)) | |
7005 | vco_table = blb_vco; | |
7006 | else | |
7007 | return 0; | |
7008 | ||
7009 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7010 | ||
7011 | vco = vco_table[tmp & 0x7]; | |
7012 | if (vco == 0) | |
7013 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7014 | else | |
7015 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7016 | ||
7017 | return vco; | |
7018 | } | |
7019 | ||
7020 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7021 | { | |
7022 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7023 | uint16_t tmp = 0; | |
7024 | ||
7025 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7026 | ||
7027 | cdclk_sel = (tmp >> 12) & 0x1; | |
7028 | ||
7029 | switch (vco) { | |
7030 | case 2666667: | |
7031 | case 4000000: | |
7032 | case 5333333: | |
7033 | return cdclk_sel ? 333333 : 222222; | |
7034 | case 3200000: | |
7035 | return cdclk_sel ? 320000 : 228571; | |
7036 | default: | |
7037 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7038 | return 222222; | |
7039 | } | |
7040 | } | |
7041 | ||
7042 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7043 | { | |
7044 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7045 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7046 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7047 | const uint8_t *div_table; | |
7048 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7049 | uint16_t tmp = 0; | |
7050 | ||
7051 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7052 | ||
7053 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7054 | ||
7055 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7056 | goto fail; | |
7057 | ||
7058 | switch (vco) { | |
7059 | case 3200000: | |
7060 | div_table = div_3200; | |
7061 | break; | |
7062 | case 4000000: | |
7063 | div_table = div_4000; | |
7064 | break; | |
7065 | case 5333333: | |
7066 | div_table = div_5333; | |
7067 | break; | |
7068 | default: | |
7069 | goto fail; | |
7070 | } | |
7071 | ||
7072 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7073 | ||
caf4e252 | 7074 | fail: |
34edce2f VS |
7075 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7076 | return 200000; | |
7077 | } | |
7078 | ||
7079 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7080 | { | |
7081 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7082 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7083 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7084 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7085 | const uint8_t *div_table; | |
7086 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7087 | uint16_t tmp = 0; | |
7088 | ||
7089 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7090 | ||
7091 | cdclk_sel = (tmp >> 4) & 0x7; | |
7092 | ||
7093 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7094 | goto fail; | |
7095 | ||
7096 | switch (vco) { | |
7097 | case 3200000: | |
7098 | div_table = div_3200; | |
7099 | break; | |
7100 | case 4000000: | |
7101 | div_table = div_4000; | |
7102 | break; | |
7103 | case 4800000: | |
7104 | div_table = div_4800; | |
7105 | break; | |
7106 | case 5333333: | |
7107 | div_table = div_5333; | |
7108 | break; | |
7109 | default: | |
7110 | goto fail; | |
7111 | } | |
7112 | ||
7113 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7114 | ||
caf4e252 | 7115 | fail: |
34edce2f VS |
7116 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7117 | return 190476; | |
7118 | } | |
7119 | ||
2c07245f | 7120 | static void |
a65851af | 7121 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7122 | { |
a65851af VS |
7123 | while (*num > DATA_LINK_M_N_MASK || |
7124 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7125 | *num >>= 1; |
7126 | *den >>= 1; | |
7127 | } | |
7128 | } | |
7129 | ||
a65851af VS |
7130 | static void compute_m_n(unsigned int m, unsigned int n, |
7131 | uint32_t *ret_m, uint32_t *ret_n) | |
7132 | { | |
7133 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7134 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7135 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7136 | } | |
7137 | ||
e69d0bc1 DV |
7138 | void |
7139 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7140 | int pixel_clock, int link_clock, | |
7141 | struct intel_link_m_n *m_n) | |
2c07245f | 7142 | { |
e69d0bc1 | 7143 | m_n->tu = 64; |
a65851af VS |
7144 | |
7145 | compute_m_n(bits_per_pixel * pixel_clock, | |
7146 | link_clock * nlanes * 8, | |
7147 | &m_n->gmch_m, &m_n->gmch_n); | |
7148 | ||
7149 | compute_m_n(pixel_clock, link_clock, | |
7150 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7151 | } |
7152 | ||
a7615030 CW |
7153 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7154 | { | |
d330a953 JN |
7155 | if (i915.panel_use_ssc >= 0) |
7156 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7157 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7158 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7159 | } |
7160 | ||
7429e9d4 | 7161 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7162 | { |
7df00d7a | 7163 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7164 | } |
f47709a9 | 7165 | |
7429e9d4 DV |
7166 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7167 | { | |
7168 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7169 | } |
7170 | ||
f47709a9 | 7171 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7172 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7173 | struct dpll *reduced_clock) |
a7516a05 | 7174 | { |
f47709a9 | 7175 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7176 | u32 fp, fp2 = 0; |
7177 | ||
7178 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7179 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7180 | if (reduced_clock) |
7429e9d4 | 7181 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7182 | } else { |
190f68c5 | 7183 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7184 | if (reduced_clock) |
7429e9d4 | 7185 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7186 | } |
7187 | ||
190f68c5 | 7188 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7189 | |
f47709a9 | 7190 | crtc->lowfreq_avail = false; |
a93e255f | 7191 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7192 | reduced_clock) { |
190f68c5 | 7193 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7194 | crtc->lowfreq_avail = true; |
a7516a05 | 7195 | } else { |
190f68c5 | 7196 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7197 | } |
7198 | } | |
7199 | ||
5e69f97f CML |
7200 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7201 | pipe) | |
89b667f8 JB |
7202 | { |
7203 | u32 reg_val; | |
7204 | ||
7205 | /* | |
7206 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7207 | * and set it to a reasonable value instead. | |
7208 | */ | |
ab3c759a | 7209 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7210 | reg_val &= 0xffffff00; |
7211 | reg_val |= 0x00000030; | |
ab3c759a | 7212 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7213 | |
ab3c759a | 7214 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7215 | reg_val &= 0x8cffffff; |
7216 | reg_val = 0x8c000000; | |
ab3c759a | 7217 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7218 | |
ab3c759a | 7219 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7220 | reg_val &= 0xffffff00; |
ab3c759a | 7221 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7222 | |
ab3c759a | 7223 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7224 | reg_val &= 0x00ffffff; |
7225 | reg_val |= 0xb0000000; | |
ab3c759a | 7226 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7227 | } |
7228 | ||
b551842d DV |
7229 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7230 | struct intel_link_m_n *m_n) | |
7231 | { | |
7232 | struct drm_device *dev = crtc->base.dev; | |
7233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7234 | int pipe = crtc->pipe; | |
7235 | ||
e3b95f1e DV |
7236 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7237 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7238 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7239 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7240 | } |
7241 | ||
7242 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7243 | struct intel_link_m_n *m_n, |
7244 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7245 | { |
7246 | struct drm_device *dev = crtc->base.dev; | |
7247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7248 | int pipe = crtc->pipe; | |
6e3c9717 | 7249 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7250 | |
7251 | if (INTEL_INFO(dev)->gen >= 5) { | |
7252 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7253 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7254 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7255 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7256 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7257 | * for gen < 8) and if DRRS is supported (to make sure the | |
7258 | * registers are not unnecessarily accessed). | |
7259 | */ | |
44395bfe | 7260 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7261 | crtc->config->has_drrs) { |
f769cd24 VK |
7262 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7263 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7264 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7265 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7266 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7267 | } | |
b551842d | 7268 | } else { |
e3b95f1e DV |
7269 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7270 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7271 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7272 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7273 | } |
7274 | } | |
7275 | ||
fe3cd48d | 7276 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7277 | { |
fe3cd48d R |
7278 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7279 | ||
7280 | if (m_n == M1_N1) { | |
7281 | dp_m_n = &crtc->config->dp_m_n; | |
7282 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7283 | } else if (m_n == M2_N2) { | |
7284 | ||
7285 | /* | |
7286 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7287 | * needs to be programmed into M1_N1. | |
7288 | */ | |
7289 | dp_m_n = &crtc->config->dp_m2_n2; | |
7290 | } else { | |
7291 | DRM_ERROR("Unsupported divider value\n"); | |
7292 | return; | |
7293 | } | |
7294 | ||
6e3c9717 ACO |
7295 | if (crtc->config->has_pch_encoder) |
7296 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7297 | else |
fe3cd48d | 7298 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7299 | } |
7300 | ||
251ac862 DV |
7301 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7302 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7303 | { |
03ed5cbf | 7304 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7305 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7306 | if (crtc->pipe != PIPE_A) |
7307 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7308 | |
cd2d34d9 | 7309 | /* DPLL not used with DSI, but still need the rest set up */ |
187a1c07 | 7310 | if (!pipe_config->has_dsi_encoder) |
cd2d34d9 VS |
7311 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7312 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7313 | ||
03ed5cbf VS |
7314 | pipe_config->dpll_hw_state.dpll_md = |
7315 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7316 | } | |
bdd4b6a6 | 7317 | |
03ed5cbf VS |
7318 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7319 | struct intel_crtc_state *pipe_config) | |
7320 | { | |
7321 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7322 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7323 | if (crtc->pipe != PIPE_A) |
7324 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7325 | ||
cd2d34d9 | 7326 | /* DPLL not used with DSI, but still need the rest set up */ |
187a1c07 | 7327 | if (!pipe_config->has_dsi_encoder) |
cd2d34d9 VS |
7328 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7329 | ||
03ed5cbf VS |
7330 | pipe_config->dpll_hw_state.dpll_md = |
7331 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7332 | } |
7333 | ||
d288f65f | 7334 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7335 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7336 | { |
f47709a9 | 7337 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7338 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd2d34d9 | 7339 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7340 | u32 mdiv; |
a0c4da24 | 7341 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7342 | u32 coreclk, reg_val; |
a0c4da24 | 7343 | |
cd2d34d9 VS |
7344 | /* Enable Refclk */ |
7345 | I915_WRITE(DPLL(pipe), | |
7346 | pipe_config->dpll_hw_state.dpll & | |
7347 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7348 | ||
7349 | /* No need to actually set up the DPLL with DSI */ | |
7350 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7351 | return; | |
7352 | ||
a580516d | 7353 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7354 | |
d288f65f VS |
7355 | bestn = pipe_config->dpll.n; |
7356 | bestm1 = pipe_config->dpll.m1; | |
7357 | bestm2 = pipe_config->dpll.m2; | |
7358 | bestp1 = pipe_config->dpll.p1; | |
7359 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7360 | |
89b667f8 JB |
7361 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7362 | ||
7363 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7364 | if (pipe == PIPE_B) |
5e69f97f | 7365 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7366 | |
7367 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7368 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7369 | |
7370 | /* Disable target IRef on PLL */ | |
ab3c759a | 7371 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7372 | reg_val &= 0x00ffffff; |
ab3c759a | 7373 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7374 | |
7375 | /* Disable fast lock */ | |
ab3c759a | 7376 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7377 | |
7378 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7379 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7380 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7381 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7382 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7383 | |
7384 | /* | |
7385 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7386 | * but we don't support that). | |
7387 | * Note: don't use the DAC post divider as it seems unstable. | |
7388 | */ | |
7389 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7390 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7391 | |
a0c4da24 | 7392 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7393 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7394 | |
89b667f8 | 7395 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7396 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7397 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7398 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7399 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7400 | 0x009f0003); |
89b667f8 | 7401 | else |
ab3c759a | 7402 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7403 | 0x00d0000f); |
7404 | ||
681a8504 | 7405 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7406 | /* Use SSC source */ |
bdd4b6a6 | 7407 | if (pipe == PIPE_A) |
ab3c759a | 7408 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7409 | 0x0df40000); |
7410 | else | |
ab3c759a | 7411 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7412 | 0x0df70000); |
7413 | } else { /* HDMI or VGA */ | |
7414 | /* Use bend source */ | |
bdd4b6a6 | 7415 | if (pipe == PIPE_A) |
ab3c759a | 7416 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7417 | 0x0df70000); |
7418 | else | |
ab3c759a | 7419 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7420 | 0x0df40000); |
7421 | } | |
a0c4da24 | 7422 | |
ab3c759a | 7423 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7424 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7425 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7426 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7427 | coreclk |= 0x01000000; |
ab3c759a | 7428 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7429 | |
ab3c759a | 7430 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7431 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7432 | } |
7433 | ||
d288f65f | 7434 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7435 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7436 | { |
7437 | struct drm_device *dev = crtc->base.dev; | |
7438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cd2d34d9 | 7439 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7440 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7441 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7442 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7443 | u32 dpio_val; |
9cbe40c1 | 7444 | int vco; |
9d556c99 | 7445 | |
cd2d34d9 VS |
7446 | /* Enable Refclk and SSC */ |
7447 | I915_WRITE(DPLL(pipe), | |
7448 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7449 | ||
7450 | /* No need to actually set up the DPLL with DSI */ | |
7451 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7452 | return; | |
7453 | ||
d288f65f VS |
7454 | bestn = pipe_config->dpll.n; |
7455 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7456 | bestm1 = pipe_config->dpll.m1; | |
7457 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7458 | bestp1 = pipe_config->dpll.p1; | |
7459 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7460 | vco = pipe_config->dpll.vco; |
a945ce7e | 7461 | dpio_val = 0; |
9cbe40c1 | 7462 | loopfilter = 0; |
9d556c99 | 7463 | |
a580516d | 7464 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7465 | |
9d556c99 CML |
7466 | /* p1 and p2 divider */ |
7467 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7468 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7469 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7470 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7471 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7472 | ||
7473 | /* Feedback post-divider - m2 */ | |
7474 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7475 | ||
7476 | /* Feedback refclk divider - n and m1 */ | |
7477 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7478 | DPIO_CHV_M1_DIV_BY_2 | | |
7479 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7480 | ||
7481 | /* M2 fraction division */ | |
25a25dfc | 7482 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7483 | |
7484 | /* M2 fraction division enable */ | |
a945ce7e VP |
7485 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7486 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7487 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7488 | if (bestm2_frac) | |
7489 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7490 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7491 | |
de3a0fde VP |
7492 | /* Program digital lock detect threshold */ |
7493 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7494 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7495 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7496 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7497 | if (!bestm2_frac) | |
7498 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7499 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7500 | ||
9d556c99 | 7501 | /* Loop filter */ |
9cbe40c1 VP |
7502 | if (vco == 5400000) { |
7503 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7504 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7505 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7506 | tribuf_calcntr = 0x9; | |
7507 | } else if (vco <= 6200000) { | |
7508 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7509 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7510 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7511 | tribuf_calcntr = 0x9; | |
7512 | } else if (vco <= 6480000) { | |
7513 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7514 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7515 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7516 | tribuf_calcntr = 0x8; | |
7517 | } else { | |
7518 | /* Not supported. Apply the same limits as in the max case */ | |
7519 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7520 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7521 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7522 | tribuf_calcntr = 0; | |
7523 | } | |
9d556c99 CML |
7524 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7525 | ||
968040b2 | 7526 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7527 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7528 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7529 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7530 | ||
9d556c99 CML |
7531 | /* AFC Recal */ |
7532 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7533 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7534 | DPIO_AFC_RECAL); | |
7535 | ||
a580516d | 7536 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7537 | } |
7538 | ||
d288f65f VS |
7539 | /** |
7540 | * vlv_force_pll_on - forcibly enable just the PLL | |
7541 | * @dev_priv: i915 private structure | |
7542 | * @pipe: pipe PLL to enable | |
7543 | * @dpll: PLL configuration | |
7544 | * | |
7545 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7546 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7547 | * be enabled. | |
7548 | */ | |
3f36b937 TU |
7549 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7550 | const struct dpll *dpll) | |
d288f65f VS |
7551 | { |
7552 | struct intel_crtc *crtc = | |
7553 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7554 | struct intel_crtc_state *pipe_config; |
7555 | ||
7556 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7557 | if (!pipe_config) | |
7558 | return -ENOMEM; | |
7559 | ||
7560 | pipe_config->base.crtc = &crtc->base; | |
7561 | pipe_config->pixel_multiplier = 1; | |
7562 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7563 | |
7564 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7565 | chv_compute_dpll(crtc, pipe_config); |
7566 | chv_prepare_pll(crtc, pipe_config); | |
7567 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7568 | } else { |
3f36b937 TU |
7569 | vlv_compute_dpll(crtc, pipe_config); |
7570 | vlv_prepare_pll(crtc, pipe_config); | |
7571 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7572 | } |
3f36b937 TU |
7573 | |
7574 | kfree(pipe_config); | |
7575 | ||
7576 | return 0; | |
d288f65f VS |
7577 | } |
7578 | ||
7579 | /** | |
7580 | * vlv_force_pll_off - forcibly disable just the PLL | |
7581 | * @dev_priv: i915 private structure | |
7582 | * @pipe: pipe PLL to disable | |
7583 | * | |
7584 | * Disable the PLL for @pipe. To be used in cases where we need | |
7585 | * the PLL enabled even when @pipe is not going to be enabled. | |
7586 | */ | |
7587 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7588 | { | |
7589 | if (IS_CHERRYVIEW(dev)) | |
7590 | chv_disable_pll(to_i915(dev), pipe); | |
7591 | else | |
7592 | vlv_disable_pll(to_i915(dev), pipe); | |
7593 | } | |
7594 | ||
251ac862 DV |
7595 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7596 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7597 | struct dpll *reduced_clock) |
eb1cbe48 | 7598 | { |
f47709a9 | 7599 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7600 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7601 | u32 dpll; |
7602 | bool is_sdvo; | |
190f68c5 | 7603 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7604 | |
190f68c5 | 7605 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7606 | |
a93e255f ACO |
7607 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7608 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7609 | |
7610 | dpll = DPLL_VGA_MODE_DIS; | |
7611 | ||
a93e255f | 7612 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7613 | dpll |= DPLLB_MODE_LVDS; |
7614 | else | |
7615 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7616 | |
ef1b460d | 7617 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7618 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7619 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7620 | } |
198a037f DV |
7621 | |
7622 | if (is_sdvo) | |
4a33e48d | 7623 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7624 | |
190f68c5 | 7625 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7626 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7627 | |
7628 | /* compute bitmask from p1 value */ | |
7629 | if (IS_PINEVIEW(dev)) | |
7630 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7631 | else { | |
7632 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7633 | if (IS_G4X(dev) && reduced_clock) | |
7634 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7635 | } | |
7636 | switch (clock->p2) { | |
7637 | case 5: | |
7638 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7639 | break; | |
7640 | case 7: | |
7641 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7642 | break; | |
7643 | case 10: | |
7644 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7645 | break; | |
7646 | case 14: | |
7647 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7648 | break; | |
7649 | } | |
7650 | if (INTEL_INFO(dev)->gen >= 4) | |
7651 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7652 | ||
190f68c5 | 7653 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7654 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7655 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7656 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7657 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7658 | else | |
7659 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7660 | ||
7661 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7662 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7663 | |
eb1cbe48 | 7664 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7665 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7666 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7667 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7668 | } |
7669 | } | |
7670 | ||
251ac862 DV |
7671 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7672 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7673 | struct dpll *reduced_clock) |
eb1cbe48 | 7674 | { |
f47709a9 | 7675 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7676 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7677 | u32 dpll; |
190f68c5 | 7678 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7679 | |
190f68c5 | 7680 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7681 | |
eb1cbe48 DV |
7682 | dpll = DPLL_VGA_MODE_DIS; |
7683 | ||
a93e255f | 7684 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7685 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7686 | } else { | |
7687 | if (clock->p1 == 2) | |
7688 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7689 | else | |
7690 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7691 | if (clock->p2 == 4) | |
7692 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7693 | } | |
7694 | ||
a93e255f | 7695 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7696 | dpll |= DPLL_DVO_2X_MODE; |
7697 | ||
a93e255f | 7698 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7699 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7700 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7701 | else | |
7702 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7703 | ||
7704 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7705 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7706 | } |
7707 | ||
8a654f3b | 7708 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7709 | { |
7710 | struct drm_device *dev = intel_crtc->base.dev; | |
7711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7712 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7713 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7714 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7715 | uint32_t crtc_vtotal, crtc_vblank_end; |
7716 | int vsyncshift = 0; | |
4d8a62ea DV |
7717 | |
7718 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7719 | * the hw state checker will get angry at the mismatch. */ | |
7720 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7721 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7722 | |
609aeaca | 7723 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7724 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7725 | crtc_vtotal -= 1; |
7726 | crtc_vblank_end -= 1; | |
609aeaca | 7727 | |
409ee761 | 7728 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7729 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7730 | else | |
7731 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7732 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7733 | if (vsyncshift < 0) |
7734 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7735 | } |
7736 | ||
7737 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7738 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7739 | |
fe2b8f9d | 7740 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7741 | (adjusted_mode->crtc_hdisplay - 1) | |
7742 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7743 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7744 | (adjusted_mode->crtc_hblank_start - 1) | |
7745 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7746 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7747 | (adjusted_mode->crtc_hsync_start - 1) | |
7748 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7749 | ||
fe2b8f9d | 7750 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7751 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7752 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7753 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7754 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7755 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7756 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7757 | (adjusted_mode->crtc_vsync_start - 1) | |
7758 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7759 | ||
b5e508d4 PZ |
7760 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7761 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7762 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7763 | * bits. */ | |
7764 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7765 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7766 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7767 | ||
bc58be60 JN |
7768 | } |
7769 | ||
7770 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7771 | { | |
7772 | struct drm_device *dev = intel_crtc->base.dev; | |
7773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7774 | enum pipe pipe = intel_crtc->pipe; | |
7775 | ||
b0e77b9c PZ |
7776 | /* pipesrc controls the size that is scaled from, which should |
7777 | * always be the user's requested size. | |
7778 | */ | |
7779 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7780 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7781 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7782 | } |
7783 | ||
1bd1bd80 | 7784 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7785 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7786 | { |
7787 | struct drm_device *dev = crtc->base.dev; | |
7788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7789 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7790 | uint32_t tmp; | |
7791 | ||
7792 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7793 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7794 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7795 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7796 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7797 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7798 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7799 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7800 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7801 | |
7802 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7803 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7804 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7805 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7806 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7807 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7808 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7809 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7810 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7811 | |
7812 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7813 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7814 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7815 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7816 | } |
bc58be60 JN |
7817 | } |
7818 | ||
7819 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7820 | struct intel_crtc_state *pipe_config) | |
7821 | { | |
7822 | struct drm_device *dev = crtc->base.dev; | |
7823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7824 | u32 tmp; | |
1bd1bd80 DV |
7825 | |
7826 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7827 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7828 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7829 | ||
2d112de7 ACO |
7830 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7831 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7832 | } |
7833 | ||
f6a83288 | 7834 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7835 | struct intel_crtc_state *pipe_config) |
babea61d | 7836 | { |
2d112de7 ACO |
7837 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7838 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7839 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7840 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7841 | |
2d112de7 ACO |
7842 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7843 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7844 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7845 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7846 | |
2d112de7 | 7847 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7848 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7849 | |
2d112de7 ACO |
7850 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7851 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7852 | |
7853 | mode->hsync = drm_mode_hsync(mode); | |
7854 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7855 | drm_mode_set_name(mode); | |
babea61d JB |
7856 | } |
7857 | ||
84b046f3 DV |
7858 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7859 | { | |
7860 | struct drm_device *dev = intel_crtc->base.dev; | |
7861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7862 | uint32_t pipeconf; | |
7863 | ||
9f11a9e4 | 7864 | pipeconf = 0; |
84b046f3 | 7865 | |
b6b5d049 VS |
7866 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7867 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7868 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7869 | |
6e3c9717 | 7870 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7871 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7872 | |
ff9ce46e | 7873 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7874 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7875 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7876 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7877 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7878 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7879 | |
6e3c9717 | 7880 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7881 | case 18: |
7882 | pipeconf |= PIPECONF_6BPC; | |
7883 | break; | |
7884 | case 24: | |
7885 | pipeconf |= PIPECONF_8BPC; | |
7886 | break; | |
7887 | case 30: | |
7888 | pipeconf |= PIPECONF_10BPC; | |
7889 | break; | |
7890 | default: | |
7891 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7892 | BUG(); | |
84b046f3 DV |
7893 | } |
7894 | } | |
7895 | ||
7896 | if (HAS_PIPE_CXSR(dev)) { | |
7897 | if (intel_crtc->lowfreq_avail) { | |
7898 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7899 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7900 | } else { | |
7901 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7902 | } |
7903 | } | |
7904 | ||
6e3c9717 | 7905 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7906 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7907 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7908 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7909 | else | |
7910 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7911 | } else | |
84b046f3 DV |
7912 | pipeconf |= PIPECONF_PROGRESSIVE; |
7913 | ||
666a4537 WB |
7914 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7915 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7916 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7917 | |
84b046f3 DV |
7918 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7919 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7920 | } | |
7921 | ||
81c97f52 ACO |
7922 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7923 | struct intel_crtc_state *crtc_state) | |
7924 | { | |
7925 | struct drm_device *dev = crtc->base.dev; | |
7926 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 7927 | const struct intel_limit *limit; |
81c97f52 ACO |
7928 | int refclk = 48000; |
7929 | ||
7930 | memset(&crtc_state->dpll_hw_state, 0, | |
7931 | sizeof(crtc_state->dpll_hw_state)); | |
7932 | ||
7933 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7934 | if (intel_panel_use_ssc(dev_priv)) { | |
7935 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7936 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7937 | } | |
7938 | ||
7939 | limit = &intel_limits_i8xx_lvds; | |
7940 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) { | |
7941 | limit = &intel_limits_i8xx_dvo; | |
7942 | } else { | |
7943 | limit = &intel_limits_i8xx_dac; | |
7944 | } | |
7945 | ||
7946 | if (!crtc_state->clock_set && | |
7947 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7948 | refclk, NULL, &crtc_state->dpll)) { | |
7949 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7950 | return -EINVAL; | |
7951 | } | |
7952 | ||
7953 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7954 | ||
7955 | return 0; | |
7956 | } | |
7957 | ||
19ec6693 ACO |
7958 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7959 | struct intel_crtc_state *crtc_state) | |
7960 | { | |
7961 | struct drm_device *dev = crtc->base.dev; | |
7962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 7963 | const struct intel_limit *limit; |
19ec6693 ACO |
7964 | int refclk = 96000; |
7965 | ||
7966 | memset(&crtc_state->dpll_hw_state, 0, | |
7967 | sizeof(crtc_state->dpll_hw_state)); | |
7968 | ||
7969 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7970 | if (intel_panel_use_ssc(dev_priv)) { | |
7971 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7972 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7973 | } | |
7974 | ||
7975 | if (intel_is_dual_link_lvds(dev)) | |
7976 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7977 | else | |
7978 | limit = &intel_limits_g4x_single_channel_lvds; | |
7979 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || | |
7980 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
7981 | limit = &intel_limits_g4x_hdmi; | |
7982 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { | |
7983 | limit = &intel_limits_g4x_sdvo; | |
7984 | } else { | |
7985 | /* The option is for other outputs */ | |
7986 | limit = &intel_limits_i9xx_sdvo; | |
7987 | } | |
7988 | ||
7989 | if (!crtc_state->clock_set && | |
7990 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7991 | refclk, NULL, &crtc_state->dpll)) { | |
7992 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7993 | return -EINVAL; | |
7994 | } | |
7995 | ||
7996 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7997 | ||
7998 | return 0; | |
7999 | } | |
8000 | ||
70e8aa21 ACO |
8001 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
8002 | struct intel_crtc_state *crtc_state) | |
8003 | { | |
8004 | struct drm_device *dev = crtc->base.dev; | |
8005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 8006 | const struct intel_limit *limit; |
70e8aa21 ACO |
8007 | int refclk = 96000; |
8008 | ||
8009 | memset(&crtc_state->dpll_hw_state, 0, | |
8010 | sizeof(crtc_state->dpll_hw_state)); | |
8011 | ||
8012 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
8013 | if (intel_panel_use_ssc(dev_priv)) { | |
8014 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8015 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8016 | } | |
8017 | ||
8018 | limit = &intel_limits_pineview_lvds; | |
8019 | } else { | |
8020 | limit = &intel_limits_pineview_sdvo; | |
8021 | } | |
8022 | ||
8023 | if (!crtc_state->clock_set && | |
8024 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8025 | refclk, NULL, &crtc_state->dpll)) { | |
8026 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8027 | return -EINVAL; | |
8028 | } | |
8029 | ||
8030 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8031 | ||
8032 | return 0; | |
8033 | } | |
8034 | ||
190f68c5 ACO |
8035 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8036 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8037 | { |
c7653199 | 8038 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8039 | struct drm_i915_private *dev_priv = dev->dev_private; |
1b6f4958 | 8040 | const struct intel_limit *limit; |
81c97f52 | 8041 | int refclk = 96000; |
79e53945 | 8042 | |
dd3cd74a ACO |
8043 | memset(&crtc_state->dpll_hw_state, 0, |
8044 | sizeof(crtc_state->dpll_hw_state)); | |
8045 | ||
70e8aa21 ACO |
8046 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8047 | if (intel_panel_use_ssc(dev_priv)) { | |
8048 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8049 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8050 | } | |
43565a06 | 8051 | |
70e8aa21 ACO |
8052 | limit = &intel_limits_i9xx_lvds; |
8053 | } else { | |
8054 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8055 | } |
79e53945 | 8056 | |
70e8aa21 ACO |
8057 | if (!crtc_state->clock_set && |
8058 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8059 | refclk, NULL, &crtc_state->dpll)) { | |
8060 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8061 | return -EINVAL; | |
f47709a9 | 8062 | } |
7026d4ac | 8063 | |
81c97f52 | 8064 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8065 | |
c8f7a0db | 8066 | return 0; |
f564048e EA |
8067 | } |
8068 | ||
65b3d6a9 ACO |
8069 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8070 | struct intel_crtc_state *crtc_state) | |
8071 | { | |
8072 | int refclk = 100000; | |
1b6f4958 | 8073 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8074 | |
8075 | memset(&crtc_state->dpll_hw_state, 0, | |
8076 | sizeof(crtc_state->dpll_hw_state)); | |
8077 | ||
65b3d6a9 ACO |
8078 | if (!crtc_state->clock_set && |
8079 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8080 | refclk, NULL, &crtc_state->dpll)) { | |
8081 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8082 | return -EINVAL; | |
8083 | } | |
8084 | ||
8085 | chv_compute_dpll(crtc, crtc_state); | |
8086 | ||
8087 | return 0; | |
8088 | } | |
8089 | ||
8090 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8091 | struct intel_crtc_state *crtc_state) | |
8092 | { | |
8093 | int refclk = 100000; | |
1b6f4958 | 8094 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8095 | |
8096 | memset(&crtc_state->dpll_hw_state, 0, | |
8097 | sizeof(crtc_state->dpll_hw_state)); | |
8098 | ||
65b3d6a9 ACO |
8099 | if (!crtc_state->clock_set && |
8100 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8101 | refclk, NULL, &crtc_state->dpll)) { | |
8102 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8103 | return -EINVAL; | |
8104 | } | |
8105 | ||
8106 | vlv_compute_dpll(crtc, crtc_state); | |
8107 | ||
8108 | return 0; | |
8109 | } | |
8110 | ||
2fa2fe9a | 8111 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8112 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8113 | { |
8114 | struct drm_device *dev = crtc->base.dev; | |
8115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8116 | uint32_t tmp; | |
8117 | ||
dc9e7dec VS |
8118 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8119 | return; | |
8120 | ||
2fa2fe9a | 8121 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8122 | if (!(tmp & PFIT_ENABLE)) |
8123 | return; | |
2fa2fe9a | 8124 | |
06922821 | 8125 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8126 | if (INTEL_INFO(dev)->gen < 4) { |
8127 | if (crtc->pipe != PIPE_B) | |
8128 | return; | |
2fa2fe9a DV |
8129 | } else { |
8130 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8131 | return; | |
8132 | } | |
8133 | ||
06922821 | 8134 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8135 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8136 | } |
8137 | ||
acbec814 | 8138 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8139 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8140 | { |
8141 | struct drm_device *dev = crtc->base.dev; | |
8142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8143 | int pipe = pipe_config->cpu_transcoder; | |
9e2c8475 | 8144 | struct dpll clock; |
acbec814 | 8145 | u32 mdiv; |
662c6ecb | 8146 | int refclk = 100000; |
acbec814 | 8147 | |
b521973b VS |
8148 | /* In case of DSI, DPLL will not be used */ |
8149 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8150 | return; |
8151 | ||
a580516d | 8152 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8153 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8154 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8155 | |
8156 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8157 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8158 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8159 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8160 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8161 | ||
dccbea3b | 8162 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8163 | } |
8164 | ||
5724dbd1 DL |
8165 | static void |
8166 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8167 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8168 | { |
8169 | struct drm_device *dev = crtc->base.dev; | |
8170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8171 | u32 val, base, offset; | |
8172 | int pipe = crtc->pipe, plane = crtc->plane; | |
8173 | int fourcc, pixel_format; | |
6761dd31 | 8174 | unsigned int aligned_height; |
b113d5ee | 8175 | struct drm_framebuffer *fb; |
1b842c89 | 8176 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8177 | |
42a7b088 DL |
8178 | val = I915_READ(DSPCNTR(plane)); |
8179 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8180 | return; | |
8181 | ||
d9806c9f | 8182 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8183 | if (!intel_fb) { |
1ad292b5 JB |
8184 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8185 | return; | |
8186 | } | |
8187 | ||
1b842c89 DL |
8188 | fb = &intel_fb->base; |
8189 | ||
18c5247e DV |
8190 | if (INTEL_INFO(dev)->gen >= 4) { |
8191 | if (val & DISPPLANE_TILED) { | |
49af449b | 8192 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8193 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8194 | } | |
8195 | } | |
1ad292b5 JB |
8196 | |
8197 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8198 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8199 | fb->pixel_format = fourcc; |
8200 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8201 | |
8202 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8203 | if (plane_config->tiling) |
1ad292b5 JB |
8204 | offset = I915_READ(DSPTILEOFF(plane)); |
8205 | else | |
8206 | offset = I915_READ(DSPLINOFF(plane)); | |
8207 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8208 | } else { | |
8209 | base = I915_READ(DSPADDR(plane)); | |
8210 | } | |
8211 | plane_config->base = base; | |
8212 | ||
8213 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8214 | fb->width = ((val >> 16) & 0xfff) + 1; |
8215 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8216 | |
8217 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8218 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8219 | |
b113d5ee | 8220 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8221 | fb->pixel_format, |
8222 | fb->modifier[0]); | |
1ad292b5 | 8223 | |
f37b5c2b | 8224 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8225 | |
2844a921 DL |
8226 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8227 | pipe_name(pipe), plane, fb->width, fb->height, | |
8228 | fb->bits_per_pixel, base, fb->pitches[0], | |
8229 | plane_config->size); | |
1ad292b5 | 8230 | |
2d14030b | 8231 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8232 | } |
8233 | ||
70b23a98 | 8234 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8235 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8236 | { |
8237 | struct drm_device *dev = crtc->base.dev; | |
8238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8239 | int pipe = pipe_config->cpu_transcoder; | |
8240 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8241 | struct dpll clock; |
0d7b6b11 | 8242 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8243 | int refclk = 100000; |
8244 | ||
b521973b VS |
8245 | /* In case of DSI, DPLL will not be used */ |
8246 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8247 | return; | |
8248 | ||
a580516d | 8249 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8250 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8251 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8252 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8253 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8254 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8255 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8256 | |
8257 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8258 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8259 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8260 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8261 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8262 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8263 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8264 | ||
dccbea3b | 8265 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8266 | } |
8267 | ||
0e8ffe1b | 8268 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8269 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8270 | { |
8271 | struct drm_device *dev = crtc->base.dev; | |
8272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8273 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8274 | uint32_t tmp; |
1729050e | 8275 | bool ret; |
0e8ffe1b | 8276 | |
1729050e ID |
8277 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8278 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8279 | return false; |
8280 | ||
e143a21c | 8281 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8282 | pipe_config->shared_dpll = NULL; |
eccb140b | 8283 | |
1729050e ID |
8284 | ret = false; |
8285 | ||
0e8ffe1b DV |
8286 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8287 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8288 | goto out; |
0e8ffe1b | 8289 | |
666a4537 | 8290 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8291 | switch (tmp & PIPECONF_BPC_MASK) { |
8292 | case PIPECONF_6BPC: | |
8293 | pipe_config->pipe_bpp = 18; | |
8294 | break; | |
8295 | case PIPECONF_8BPC: | |
8296 | pipe_config->pipe_bpp = 24; | |
8297 | break; | |
8298 | case PIPECONF_10BPC: | |
8299 | pipe_config->pipe_bpp = 30; | |
8300 | break; | |
8301 | default: | |
8302 | break; | |
8303 | } | |
8304 | } | |
8305 | ||
666a4537 WB |
8306 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8307 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8308 | pipe_config->limited_color_range = true; |
8309 | ||
282740f7 VS |
8310 | if (INTEL_INFO(dev)->gen < 4) |
8311 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8312 | ||
1bd1bd80 | 8313 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8314 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8315 | |
2fa2fe9a DV |
8316 | i9xx_get_pfit_config(crtc, pipe_config); |
8317 | ||
6c49f241 | 8318 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c VS |
8319 | /* No way to read it out on pipes B and C */ |
8320 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8321 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8322 | else | |
8323 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8324 | pipe_config->pixel_multiplier = |
8325 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8326 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8327 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8328 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8329 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8330 | pipe_config->pixel_multiplier = | |
8331 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8332 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8333 | } else { | |
8334 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8335 | * port and will be fixed up in the encoder->get_config | |
8336 | * function. */ | |
8337 | pipe_config->pixel_multiplier = 1; | |
8338 | } | |
8bcc2795 | 8339 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8340 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8341 | /* |
8342 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8343 | * on 830. Filter it out here so that we don't | |
8344 | * report errors due to that. | |
8345 | */ | |
8346 | if (IS_I830(dev)) | |
8347 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8348 | ||
8bcc2795 DV |
8349 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8350 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8351 | } else { |
8352 | /* Mask out read-only status bits. */ | |
8353 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8354 | DPLL_PORTC_READY_MASK | | |
8355 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8356 | } |
6c49f241 | 8357 | |
70b23a98 VS |
8358 | if (IS_CHERRYVIEW(dev)) |
8359 | chv_crtc_clock_get(crtc, pipe_config); | |
8360 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8361 | vlv_crtc_clock_get(crtc, pipe_config); |
8362 | else | |
8363 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8364 | |
0f64614d VS |
8365 | /* |
8366 | * Normally the dotclock is filled in by the encoder .get_config() | |
8367 | * but in case the pipe is enabled w/o any ports we need a sane | |
8368 | * default. | |
8369 | */ | |
8370 | pipe_config->base.adjusted_mode.crtc_clock = | |
8371 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8372 | ||
1729050e ID |
8373 | ret = true; |
8374 | ||
8375 | out: | |
8376 | intel_display_power_put(dev_priv, power_domain); | |
8377 | ||
8378 | return ret; | |
0e8ffe1b DV |
8379 | } |
8380 | ||
dde86e2d | 8381 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8382 | { |
8383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8384 | struct intel_encoder *encoder; |
1c1a24d2 | 8385 | int i; |
74cfd7ac | 8386 | u32 val, final; |
13d83a67 | 8387 | bool has_lvds = false; |
199e5d79 | 8388 | bool has_cpu_edp = false; |
199e5d79 | 8389 | bool has_panel = false; |
99eb6a01 KP |
8390 | bool has_ck505 = false; |
8391 | bool can_ssc = false; | |
1c1a24d2 | 8392 | bool using_ssc_source = false; |
13d83a67 JB |
8393 | |
8394 | /* We need to take the global config into account */ | |
b2784e15 | 8395 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8396 | switch (encoder->type) { |
8397 | case INTEL_OUTPUT_LVDS: | |
8398 | has_panel = true; | |
8399 | has_lvds = true; | |
8400 | break; | |
8401 | case INTEL_OUTPUT_EDP: | |
8402 | has_panel = true; | |
2de6905f | 8403 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8404 | has_cpu_edp = true; |
8405 | break; | |
6847d71b PZ |
8406 | default: |
8407 | break; | |
13d83a67 JB |
8408 | } |
8409 | } | |
8410 | ||
99eb6a01 | 8411 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8412 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8413 | can_ssc = has_ck505; |
8414 | } else { | |
8415 | has_ck505 = false; | |
8416 | can_ssc = true; | |
8417 | } | |
8418 | ||
1c1a24d2 L |
8419 | /* Check if any DPLLs are using the SSC source */ |
8420 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8421 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8422 | ||
8423 | if (!(temp & DPLL_VCO_ENABLE)) | |
8424 | continue; | |
8425 | ||
8426 | if ((temp & PLL_REF_INPUT_MASK) == | |
8427 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8428 | using_ssc_source = true; | |
8429 | break; | |
8430 | } | |
8431 | } | |
8432 | ||
8433 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
8434 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
8435 | |
8436 | /* Ironlake: try to setup display ref clock before DPLL | |
8437 | * enabling. This is only under driver's control after | |
8438 | * PCH B stepping, previous chipset stepping should be | |
8439 | * ignoring this setting. | |
8440 | */ | |
74cfd7ac CW |
8441 | val = I915_READ(PCH_DREF_CONTROL); |
8442 | ||
8443 | /* As we must carefully and slowly disable/enable each source in turn, | |
8444 | * compute the final state we want first and check if we need to | |
8445 | * make any changes at all. | |
8446 | */ | |
8447 | final = val; | |
8448 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8449 | if (has_ck505) | |
8450 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8451 | else | |
8452 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8453 | ||
8c07eb68 | 8454 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 8455 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 8456 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
8457 | |
8458 | if (has_panel) { | |
8459 | final |= DREF_SSC_SOURCE_ENABLE; | |
8460 | ||
8461 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8462 | final |= DREF_SSC1_ENABLE; | |
8463 | ||
8464 | if (has_cpu_edp) { | |
8465 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8466 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8467 | else | |
8468 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8469 | } else | |
8470 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
8471 | } else if (using_ssc_source) { |
8472 | final |= DREF_SSC_SOURCE_ENABLE; | |
8473 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
8474 | } |
8475 | ||
8476 | if (final == val) | |
8477 | return; | |
8478 | ||
13d83a67 | 8479 | /* Always enable nonspread source */ |
74cfd7ac | 8480 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8481 | |
99eb6a01 | 8482 | if (has_ck505) |
74cfd7ac | 8483 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8484 | else |
74cfd7ac | 8485 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8486 | |
199e5d79 | 8487 | if (has_panel) { |
74cfd7ac CW |
8488 | val &= ~DREF_SSC_SOURCE_MASK; |
8489 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8490 | |
199e5d79 | 8491 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8492 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8493 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8494 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8495 | } else |
74cfd7ac | 8496 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8497 | |
8498 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8499 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8500 | POSTING_READ(PCH_DREF_CONTROL); |
8501 | udelay(200); | |
8502 | ||
74cfd7ac | 8503 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8504 | |
8505 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8506 | if (has_cpu_edp) { |
99eb6a01 | 8507 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8508 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8509 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8510 | } else |
74cfd7ac | 8511 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8512 | } else |
74cfd7ac | 8513 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8514 | |
74cfd7ac | 8515 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8516 | POSTING_READ(PCH_DREF_CONTROL); |
8517 | udelay(200); | |
8518 | } else { | |
1c1a24d2 | 8519 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 8520 | |
74cfd7ac | 8521 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8522 | |
8523 | /* Turn off CPU output */ | |
74cfd7ac | 8524 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8525 | |
74cfd7ac | 8526 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8527 | POSTING_READ(PCH_DREF_CONTROL); |
8528 | udelay(200); | |
8529 | ||
1c1a24d2 L |
8530 | if (!using_ssc_source) { |
8531 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 8532 | |
1c1a24d2 L |
8533 | /* Turn off the SSC source */ |
8534 | val &= ~DREF_SSC_SOURCE_MASK; | |
8535 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 8536 | |
1c1a24d2 L |
8537 | /* Turn off SSC1 */ |
8538 | val &= ~DREF_SSC1_ENABLE; | |
8539 | ||
8540 | I915_WRITE(PCH_DREF_CONTROL, val); | |
8541 | POSTING_READ(PCH_DREF_CONTROL); | |
8542 | udelay(200); | |
8543 | } | |
13d83a67 | 8544 | } |
74cfd7ac CW |
8545 | |
8546 | BUG_ON(val != final); | |
13d83a67 JB |
8547 | } |
8548 | ||
f31f2d55 | 8549 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8550 | { |
f31f2d55 | 8551 | uint32_t tmp; |
dde86e2d | 8552 | |
0ff066a9 PZ |
8553 | tmp = I915_READ(SOUTH_CHICKEN2); |
8554 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8555 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8556 | |
cf3598c2 ID |
8557 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
8558 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 8559 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 8560 | |
0ff066a9 PZ |
8561 | tmp = I915_READ(SOUTH_CHICKEN2); |
8562 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8563 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8564 | |
cf3598c2 ID |
8565 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
8566 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 8567 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
8568 | } |
8569 | ||
8570 | /* WaMPhyProgramming:hsw */ | |
8571 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8572 | { | |
8573 | uint32_t tmp; | |
dde86e2d PZ |
8574 | |
8575 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8576 | tmp &= ~(0xFF << 24); | |
8577 | tmp |= (0x12 << 24); | |
8578 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8579 | ||
dde86e2d PZ |
8580 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8581 | tmp |= (1 << 11); | |
8582 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8583 | ||
8584 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8585 | tmp |= (1 << 11); | |
8586 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8587 | ||
dde86e2d PZ |
8588 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8589 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8590 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8591 | ||
8592 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8593 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8594 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8595 | ||
0ff066a9 PZ |
8596 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8597 | tmp &= ~(7 << 13); | |
8598 | tmp |= (5 << 13); | |
8599 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8600 | |
0ff066a9 PZ |
8601 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8602 | tmp &= ~(7 << 13); | |
8603 | tmp |= (5 << 13); | |
8604 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8605 | |
8606 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8607 | tmp &= ~0xFF; | |
8608 | tmp |= 0x1C; | |
8609 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8610 | ||
8611 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8612 | tmp &= ~0xFF; | |
8613 | tmp |= 0x1C; | |
8614 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8615 | ||
8616 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8617 | tmp &= ~(0xFF << 16); | |
8618 | tmp |= (0x1C << 16); | |
8619 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8620 | ||
8621 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8622 | tmp &= ~(0xFF << 16); | |
8623 | tmp |= (0x1C << 16); | |
8624 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8625 | ||
0ff066a9 PZ |
8626 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8627 | tmp |= (1 << 27); | |
8628 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8629 | |
0ff066a9 PZ |
8630 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8631 | tmp |= (1 << 27); | |
8632 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8633 | |
0ff066a9 PZ |
8634 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8635 | tmp &= ~(0xF << 28); | |
8636 | tmp |= (4 << 28); | |
8637 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8638 | |
0ff066a9 PZ |
8639 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8640 | tmp &= ~(0xF << 28); | |
8641 | tmp |= (4 << 28); | |
8642 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8643 | } |
8644 | ||
2fa86a1f PZ |
8645 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8646 | * Programming" based on the parameters passed: | |
8647 | * - Sequence to enable CLKOUT_DP | |
8648 | * - Sequence to enable CLKOUT_DP without spread | |
8649 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8650 | */ | |
8651 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8652 | bool with_fdi) | |
f31f2d55 PZ |
8653 | { |
8654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8655 | uint32_t reg, tmp; |
8656 | ||
8657 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8658 | with_spread = true; | |
c2699524 | 8659 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8660 | with_fdi = false; |
f31f2d55 | 8661 | |
a580516d | 8662 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8663 | |
8664 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8665 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8666 | tmp |= SBI_SSCCTL_PATHALT; | |
8667 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8668 | ||
8669 | udelay(24); | |
8670 | ||
2fa86a1f PZ |
8671 | if (with_spread) { |
8672 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8673 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8674 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8675 | |
2fa86a1f PZ |
8676 | if (with_fdi) { |
8677 | lpt_reset_fdi_mphy(dev_priv); | |
8678 | lpt_program_fdi_mphy(dev_priv); | |
8679 | } | |
8680 | } | |
dde86e2d | 8681 | |
c2699524 | 8682 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8683 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8684 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8685 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8686 | |
a580516d | 8687 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8688 | } |
8689 | ||
47701c3b PZ |
8690 | /* Sequence to disable CLKOUT_DP */ |
8691 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8692 | { | |
8693 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8694 | uint32_t reg, tmp; | |
8695 | ||
a580516d | 8696 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8697 | |
c2699524 | 8698 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8699 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8700 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8701 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8702 | ||
8703 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8704 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8705 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8706 | tmp |= SBI_SSCCTL_PATHALT; | |
8707 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8708 | udelay(32); | |
8709 | } | |
8710 | tmp |= SBI_SSCCTL_DISABLE; | |
8711 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8712 | } | |
8713 | ||
a580516d | 8714 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8715 | } |
8716 | ||
f7be2c21 VS |
8717 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8718 | ||
8719 | static const uint16_t sscdivintphase[] = { | |
8720 | [BEND_IDX( 50)] = 0x3B23, | |
8721 | [BEND_IDX( 45)] = 0x3B23, | |
8722 | [BEND_IDX( 40)] = 0x3C23, | |
8723 | [BEND_IDX( 35)] = 0x3C23, | |
8724 | [BEND_IDX( 30)] = 0x3D23, | |
8725 | [BEND_IDX( 25)] = 0x3D23, | |
8726 | [BEND_IDX( 20)] = 0x3E23, | |
8727 | [BEND_IDX( 15)] = 0x3E23, | |
8728 | [BEND_IDX( 10)] = 0x3F23, | |
8729 | [BEND_IDX( 5)] = 0x3F23, | |
8730 | [BEND_IDX( 0)] = 0x0025, | |
8731 | [BEND_IDX( -5)] = 0x0025, | |
8732 | [BEND_IDX(-10)] = 0x0125, | |
8733 | [BEND_IDX(-15)] = 0x0125, | |
8734 | [BEND_IDX(-20)] = 0x0225, | |
8735 | [BEND_IDX(-25)] = 0x0225, | |
8736 | [BEND_IDX(-30)] = 0x0325, | |
8737 | [BEND_IDX(-35)] = 0x0325, | |
8738 | [BEND_IDX(-40)] = 0x0425, | |
8739 | [BEND_IDX(-45)] = 0x0425, | |
8740 | [BEND_IDX(-50)] = 0x0525, | |
8741 | }; | |
8742 | ||
8743 | /* | |
8744 | * Bend CLKOUT_DP | |
8745 | * steps -50 to 50 inclusive, in steps of 5 | |
8746 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8747 | * change in clock period = -(steps / 10) * 5.787 ps | |
8748 | */ | |
8749 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8750 | { | |
8751 | uint32_t tmp; | |
8752 | int idx = BEND_IDX(steps); | |
8753 | ||
8754 | if (WARN_ON(steps % 5 != 0)) | |
8755 | return; | |
8756 | ||
8757 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8758 | return; | |
8759 | ||
8760 | mutex_lock(&dev_priv->sb_lock); | |
8761 | ||
8762 | if (steps % 10 != 0) | |
8763 | tmp = 0xAAAAAAAB; | |
8764 | else | |
8765 | tmp = 0x00000000; | |
8766 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8767 | ||
8768 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8769 | tmp &= 0xffff0000; | |
8770 | tmp |= sscdivintphase[idx]; | |
8771 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8772 | ||
8773 | mutex_unlock(&dev_priv->sb_lock); | |
8774 | } | |
8775 | ||
8776 | #undef BEND_IDX | |
8777 | ||
bf8fa3d3 PZ |
8778 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8779 | { | |
bf8fa3d3 PZ |
8780 | struct intel_encoder *encoder; |
8781 | bool has_vga = false; | |
8782 | ||
b2784e15 | 8783 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8784 | switch (encoder->type) { |
8785 | case INTEL_OUTPUT_ANALOG: | |
8786 | has_vga = true; | |
8787 | break; | |
6847d71b PZ |
8788 | default: |
8789 | break; | |
bf8fa3d3 PZ |
8790 | } |
8791 | } | |
8792 | ||
f7be2c21 VS |
8793 | if (has_vga) { |
8794 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8795 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8796 | } else { |
47701c3b | 8797 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8798 | } |
bf8fa3d3 PZ |
8799 | } |
8800 | ||
dde86e2d PZ |
8801 | /* |
8802 | * Initialize reference clocks when the driver loads | |
8803 | */ | |
8804 | void intel_init_pch_refclk(struct drm_device *dev) | |
8805 | { | |
8806 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8807 | ironlake_init_pch_refclk(dev); | |
8808 | else if (HAS_PCH_LPT(dev)) | |
8809 | lpt_init_pch_refclk(dev); | |
8810 | } | |
8811 | ||
6ff93609 | 8812 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8813 | { |
c8203565 | 8814 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8815 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8816 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8817 | uint32_t val; |
8818 | ||
78114071 | 8819 | val = 0; |
c8203565 | 8820 | |
6e3c9717 | 8821 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8822 | case 18: |
dfd07d72 | 8823 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8824 | break; |
8825 | case 24: | |
dfd07d72 | 8826 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8827 | break; |
8828 | case 30: | |
dfd07d72 | 8829 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8830 | break; |
8831 | case 36: | |
dfd07d72 | 8832 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8833 | break; |
8834 | default: | |
cc769b62 PZ |
8835 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8836 | BUG(); | |
c8203565 PZ |
8837 | } |
8838 | ||
6e3c9717 | 8839 | if (intel_crtc->config->dither) |
c8203565 PZ |
8840 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8841 | ||
6e3c9717 | 8842 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8843 | val |= PIPECONF_INTERLACED_ILK; |
8844 | else | |
8845 | val |= PIPECONF_PROGRESSIVE; | |
8846 | ||
6e3c9717 | 8847 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8848 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8849 | |
c8203565 PZ |
8850 | I915_WRITE(PIPECONF(pipe), val); |
8851 | POSTING_READ(PIPECONF(pipe)); | |
8852 | } | |
8853 | ||
6ff93609 | 8854 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8855 | { |
391bf048 | 8856 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
ee2b0b38 | 8857 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8858 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8859 | u32 val = 0; |
ee2b0b38 | 8860 | |
391bf048 | 8861 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8862 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8863 | ||
6e3c9717 | 8864 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8865 | val |= PIPECONF_INTERLACED_ILK; |
8866 | else | |
8867 | val |= PIPECONF_PROGRESSIVE; | |
8868 | ||
702e7a56 PZ |
8869 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8870 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8871 | } |
8872 | ||
391bf048 JN |
8873 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8874 | { | |
8875 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
8876 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
756f85cf | 8877 | |
391bf048 JN |
8878 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8879 | u32 val = 0; | |
756f85cf | 8880 | |
6e3c9717 | 8881 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8882 | case 18: |
8883 | val |= PIPEMISC_DITHER_6_BPC; | |
8884 | break; | |
8885 | case 24: | |
8886 | val |= PIPEMISC_DITHER_8_BPC; | |
8887 | break; | |
8888 | case 30: | |
8889 | val |= PIPEMISC_DITHER_10_BPC; | |
8890 | break; | |
8891 | case 36: | |
8892 | val |= PIPEMISC_DITHER_12_BPC; | |
8893 | break; | |
8894 | default: | |
8895 | /* Case prevented by pipe_config_set_bpp. */ | |
8896 | BUG(); | |
8897 | } | |
8898 | ||
6e3c9717 | 8899 | if (intel_crtc->config->dither) |
756f85cf PZ |
8900 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8901 | ||
391bf048 | 8902 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8903 | } |
ee2b0b38 PZ |
8904 | } |
8905 | ||
d4b1931c PZ |
8906 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8907 | { | |
8908 | /* | |
8909 | * Account for spread spectrum to avoid | |
8910 | * oversubscribing the link. Max center spread | |
8911 | * is 2.5%; use 5% for safety's sake. | |
8912 | */ | |
8913 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8914 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8915 | } |
8916 | ||
7429e9d4 | 8917 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8918 | { |
7429e9d4 | 8919 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8920 | } |
8921 | ||
b75ca6f6 ACO |
8922 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8923 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8924 | struct dpll *reduced_clock) |
79e53945 | 8925 | { |
de13a2e3 | 8926 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8927 | struct drm_device *dev = crtc->dev; |
8928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8929 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8930 | struct drm_connector *connector; |
55bb9992 ACO |
8931 | struct drm_connector_state *connector_state; |
8932 | struct intel_encoder *encoder; | |
b75ca6f6 | 8933 | u32 dpll, fp, fp2; |
ceb41007 | 8934 | int factor, i; |
09ede541 | 8935 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8936 | |
da3ced29 | 8937 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8938 | if (connector_state->crtc != crtc_state->base.crtc) |
8939 | continue; | |
8940 | ||
8941 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8942 | ||
8943 | switch (encoder->type) { | |
79e53945 JB |
8944 | case INTEL_OUTPUT_LVDS: |
8945 | is_lvds = true; | |
8946 | break; | |
8947 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8948 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8949 | is_sdvo = true; |
79e53945 | 8950 | break; |
6847d71b PZ |
8951 | default: |
8952 | break; | |
79e53945 JB |
8953 | } |
8954 | } | |
79e53945 | 8955 | |
c1858123 | 8956 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8957 | factor = 21; |
8958 | if (is_lvds) { | |
8959 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8960 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8961 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8962 | factor = 25; |
190f68c5 | 8963 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8964 | factor = 20; |
c1858123 | 8965 | |
b75ca6f6 ACO |
8966 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8967 | ||
190f68c5 | 8968 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8969 | fp |= FP_CB_TUNE; |
8970 | ||
8971 | if (reduced_clock) { | |
8972 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8973 | |
b75ca6f6 ACO |
8974 | if (reduced_clock->m < factor * reduced_clock->n) |
8975 | fp2 |= FP_CB_TUNE; | |
8976 | } else { | |
8977 | fp2 = fp; | |
8978 | } | |
9a7c7890 | 8979 | |
5eddb70b | 8980 | dpll = 0; |
2c07245f | 8981 | |
a07d6787 EA |
8982 | if (is_lvds) |
8983 | dpll |= DPLLB_MODE_LVDS; | |
8984 | else | |
8985 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8986 | |
190f68c5 | 8987 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8988 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8989 | |
8990 | if (is_sdvo) | |
4a33e48d | 8991 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8992 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8993 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8994 | |
a07d6787 | 8995 | /* compute bitmask from p1 value */ |
190f68c5 | 8996 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8997 | /* also FPA1 */ |
190f68c5 | 8998 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8999 | |
190f68c5 | 9000 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9001 | case 5: |
9002 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9003 | break; | |
9004 | case 7: | |
9005 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9006 | break; | |
9007 | case 10: | |
9008 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9009 | break; | |
9010 | case 14: | |
9011 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9012 | break; | |
79e53945 JB |
9013 | } |
9014 | ||
ceb41007 | 9015 | if (is_lvds && intel_panel_use_ssc(dev_priv)) |
43565a06 | 9016 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9017 | else |
9018 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9019 | ||
b75ca6f6 ACO |
9020 | dpll |= DPLL_VCO_ENABLE; |
9021 | ||
9022 | crtc_state->dpll_hw_state.dpll = dpll; | |
9023 | crtc_state->dpll_hw_state.fp0 = fp; | |
9024 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
9025 | } |
9026 | ||
190f68c5 ACO |
9027 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9028 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9029 | { |
997c030c ACO |
9030 | struct drm_device *dev = crtc->base.dev; |
9031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9e2c8475 | 9032 | struct dpll reduced_clock; |
7ed9f894 | 9033 | bool has_reduced_clock = false; |
e2b78267 | 9034 | struct intel_shared_dpll *pll; |
1b6f4958 | 9035 | const struct intel_limit *limit; |
997c030c | 9036 | int refclk = 120000; |
de13a2e3 | 9037 | |
dd3cd74a ACO |
9038 | memset(&crtc_state->dpll_hw_state, 0, |
9039 | sizeof(crtc_state->dpll_hw_state)); | |
9040 | ||
ded220e2 ACO |
9041 | crtc->lowfreq_avail = false; |
9042 | ||
9043 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
9044 | if (!crtc_state->has_pch_encoder) | |
9045 | return 0; | |
79e53945 | 9046 | |
997c030c ACO |
9047 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
9048 | if (intel_panel_use_ssc(dev_priv)) { | |
9049 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
9050 | dev_priv->vbt.lvds_ssc_freq); | |
9051 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
9052 | } | |
9053 | ||
9054 | if (intel_is_dual_link_lvds(dev)) { | |
9055 | if (refclk == 100000) | |
9056 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
9057 | else | |
9058 | limit = &intel_limits_ironlake_dual_lvds; | |
9059 | } else { | |
9060 | if (refclk == 100000) | |
9061 | limit = &intel_limits_ironlake_single_lvds_100m; | |
9062 | else | |
9063 | limit = &intel_limits_ironlake_single_lvds; | |
9064 | } | |
9065 | } else { | |
9066 | limit = &intel_limits_ironlake_dac; | |
9067 | } | |
9068 | ||
364ee29d | 9069 | if (!crtc_state->clock_set && |
997c030c ACO |
9070 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9071 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9072 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9073 | return -EINVAL; | |
f47709a9 | 9074 | } |
79e53945 | 9075 | |
b75ca6f6 ACO |
9076 | ironlake_compute_dpll(crtc, crtc_state, |
9077 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9078 | |
ded220e2 ACO |
9079 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9080 | if (pll == NULL) { | |
9081 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9082 | pipe_name(crtc->pipe)); | |
9083 | return -EINVAL; | |
3fb37703 | 9084 | } |
79e53945 | 9085 | |
ded220e2 ACO |
9086 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
9087 | has_reduced_clock) | |
c7653199 | 9088 | crtc->lowfreq_avail = true; |
e2b78267 | 9089 | |
c8f7a0db | 9090 | return 0; |
79e53945 JB |
9091 | } |
9092 | ||
eb14cb74 VS |
9093 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9094 | struct intel_link_m_n *m_n) | |
9095 | { | |
9096 | struct drm_device *dev = crtc->base.dev; | |
9097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9098 | enum pipe pipe = crtc->pipe; | |
9099 | ||
9100 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9101 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9102 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9103 | & ~TU_SIZE_MASK; | |
9104 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9105 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9106 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9107 | } | |
9108 | ||
9109 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9110 | enum transcoder transcoder, | |
b95af8be VK |
9111 | struct intel_link_m_n *m_n, |
9112 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9113 | { |
9114 | struct drm_device *dev = crtc->base.dev; | |
9115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9116 | enum pipe pipe = crtc->pipe; |
72419203 | 9117 | |
eb14cb74 VS |
9118 | if (INTEL_INFO(dev)->gen >= 5) { |
9119 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9120 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9121 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9122 | & ~TU_SIZE_MASK; | |
9123 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9124 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9125 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9126 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9127 | * gen < 8) and if DRRS is supported (to make sure the | |
9128 | * registers are not unnecessarily read). | |
9129 | */ | |
9130 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9131 | crtc->config->has_drrs) { |
b95af8be VK |
9132 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9133 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9134 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9135 | & ~TU_SIZE_MASK; | |
9136 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9137 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9138 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9139 | } | |
eb14cb74 VS |
9140 | } else { |
9141 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9142 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9143 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9144 | & ~TU_SIZE_MASK; | |
9145 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9146 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9147 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9148 | } | |
9149 | } | |
9150 | ||
9151 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9152 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9153 | { |
681a8504 | 9154 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9155 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9156 | else | |
9157 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9158 | &pipe_config->dp_m_n, |
9159 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9160 | } |
72419203 | 9161 | |
eb14cb74 | 9162 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9163 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9164 | { |
9165 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9166 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9167 | } |
9168 | ||
bd2e244f | 9169 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9170 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9171 | { |
9172 | struct drm_device *dev = crtc->base.dev; | |
9173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9174 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9175 | uint32_t ps_ctrl = 0; | |
9176 | int id = -1; | |
9177 | int i; | |
bd2e244f | 9178 | |
a1b2278e CK |
9179 | /* find scaler attached to this pipe */ |
9180 | for (i = 0; i < crtc->num_scalers; i++) { | |
9181 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9182 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9183 | id = i; | |
9184 | pipe_config->pch_pfit.enabled = true; | |
9185 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9186 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9187 | break; | |
9188 | } | |
9189 | } | |
bd2e244f | 9190 | |
a1b2278e CK |
9191 | scaler_state->scaler_id = id; |
9192 | if (id >= 0) { | |
9193 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9194 | } else { | |
9195 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9196 | } |
9197 | } | |
9198 | ||
5724dbd1 DL |
9199 | static void |
9200 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9201 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9202 | { |
9203 | struct drm_device *dev = crtc->base.dev; | |
9204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9205 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9206 | int pipe = crtc->pipe; |
9207 | int fourcc, pixel_format; | |
6761dd31 | 9208 | unsigned int aligned_height; |
bc8d7dff | 9209 | struct drm_framebuffer *fb; |
1b842c89 | 9210 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9211 | |
d9806c9f | 9212 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9213 | if (!intel_fb) { |
bc8d7dff DL |
9214 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9215 | return; | |
9216 | } | |
9217 | ||
1b842c89 DL |
9218 | fb = &intel_fb->base; |
9219 | ||
bc8d7dff | 9220 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9221 | if (!(val & PLANE_CTL_ENABLE)) |
9222 | goto error; | |
9223 | ||
bc8d7dff DL |
9224 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9225 | fourcc = skl_format_to_fourcc(pixel_format, | |
9226 | val & PLANE_CTL_ORDER_RGBX, | |
9227 | val & PLANE_CTL_ALPHA_MASK); | |
9228 | fb->pixel_format = fourcc; | |
9229 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9230 | ||
40f46283 DL |
9231 | tiling = val & PLANE_CTL_TILED_MASK; |
9232 | switch (tiling) { | |
9233 | case PLANE_CTL_TILED_LINEAR: | |
9234 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9235 | break; | |
9236 | case PLANE_CTL_TILED_X: | |
9237 | plane_config->tiling = I915_TILING_X; | |
9238 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9239 | break; | |
9240 | case PLANE_CTL_TILED_Y: | |
9241 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9242 | break; | |
9243 | case PLANE_CTL_TILED_YF: | |
9244 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9245 | break; | |
9246 | default: | |
9247 | MISSING_CASE(tiling); | |
9248 | goto error; | |
9249 | } | |
9250 | ||
bc8d7dff DL |
9251 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9252 | plane_config->base = base; | |
9253 | ||
9254 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9255 | ||
9256 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9257 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9258 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9259 | ||
9260 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9261 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9262 | fb->pixel_format); |
bc8d7dff DL |
9263 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9264 | ||
9265 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9266 | fb->pixel_format, |
9267 | fb->modifier[0]); | |
bc8d7dff | 9268 | |
f37b5c2b | 9269 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9270 | |
9271 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9272 | pipe_name(pipe), fb->width, fb->height, | |
9273 | fb->bits_per_pixel, base, fb->pitches[0], | |
9274 | plane_config->size); | |
9275 | ||
2d14030b | 9276 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9277 | return; |
9278 | ||
9279 | error: | |
9280 | kfree(fb); | |
9281 | } | |
9282 | ||
2fa2fe9a | 9283 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9284 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9285 | { |
9286 | struct drm_device *dev = crtc->base.dev; | |
9287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9288 | uint32_t tmp; | |
9289 | ||
9290 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9291 | ||
9292 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9293 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9294 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9295 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9296 | |
9297 | /* We currently do not free assignements of panel fitters on | |
9298 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9299 | * differentiates them) so just WARN about this case for now. */ | |
9300 | if (IS_GEN7(dev)) { | |
9301 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9302 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9303 | } | |
2fa2fe9a | 9304 | } |
79e53945 JB |
9305 | } |
9306 | ||
5724dbd1 DL |
9307 | static void |
9308 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9309 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9310 | { |
9311 | struct drm_device *dev = crtc->base.dev; | |
9312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9313 | u32 val, base, offset; | |
aeee5a49 | 9314 | int pipe = crtc->pipe; |
4c6baa59 | 9315 | int fourcc, pixel_format; |
6761dd31 | 9316 | unsigned int aligned_height; |
b113d5ee | 9317 | struct drm_framebuffer *fb; |
1b842c89 | 9318 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9319 | |
42a7b088 DL |
9320 | val = I915_READ(DSPCNTR(pipe)); |
9321 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9322 | return; | |
9323 | ||
d9806c9f | 9324 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9325 | if (!intel_fb) { |
4c6baa59 JB |
9326 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9327 | return; | |
9328 | } | |
9329 | ||
1b842c89 DL |
9330 | fb = &intel_fb->base; |
9331 | ||
18c5247e DV |
9332 | if (INTEL_INFO(dev)->gen >= 4) { |
9333 | if (val & DISPPLANE_TILED) { | |
49af449b | 9334 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9335 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9336 | } | |
9337 | } | |
4c6baa59 JB |
9338 | |
9339 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9340 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9341 | fb->pixel_format = fourcc; |
9342 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9343 | |
aeee5a49 | 9344 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9345 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9346 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9347 | } else { |
49af449b | 9348 | if (plane_config->tiling) |
aeee5a49 | 9349 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9350 | else |
aeee5a49 | 9351 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9352 | } |
9353 | plane_config->base = base; | |
9354 | ||
9355 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9356 | fb->width = ((val >> 16) & 0xfff) + 1; |
9357 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9358 | |
9359 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9360 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9361 | |
b113d5ee | 9362 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9363 | fb->pixel_format, |
9364 | fb->modifier[0]); | |
4c6baa59 | 9365 | |
f37b5c2b | 9366 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9367 | |
2844a921 DL |
9368 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9369 | pipe_name(pipe), fb->width, fb->height, | |
9370 | fb->bits_per_pixel, base, fb->pitches[0], | |
9371 | plane_config->size); | |
b113d5ee | 9372 | |
2d14030b | 9373 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9374 | } |
9375 | ||
0e8ffe1b | 9376 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9377 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9378 | { |
9379 | struct drm_device *dev = crtc->base.dev; | |
9380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9381 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9382 | uint32_t tmp; |
1729050e | 9383 | bool ret; |
0e8ffe1b | 9384 | |
1729050e ID |
9385 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9386 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9387 | return false; |
9388 | ||
e143a21c | 9389 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9390 | pipe_config->shared_dpll = NULL; |
eccb140b | 9391 | |
1729050e | 9392 | ret = false; |
0e8ffe1b DV |
9393 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9394 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9395 | goto out; |
0e8ffe1b | 9396 | |
42571aef VS |
9397 | switch (tmp & PIPECONF_BPC_MASK) { |
9398 | case PIPECONF_6BPC: | |
9399 | pipe_config->pipe_bpp = 18; | |
9400 | break; | |
9401 | case PIPECONF_8BPC: | |
9402 | pipe_config->pipe_bpp = 24; | |
9403 | break; | |
9404 | case PIPECONF_10BPC: | |
9405 | pipe_config->pipe_bpp = 30; | |
9406 | break; | |
9407 | case PIPECONF_12BPC: | |
9408 | pipe_config->pipe_bpp = 36; | |
9409 | break; | |
9410 | default: | |
9411 | break; | |
9412 | } | |
9413 | ||
b5a9fa09 DV |
9414 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9415 | pipe_config->limited_color_range = true; | |
9416 | ||
ab9412ba | 9417 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9418 | struct intel_shared_dpll *pll; |
8106ddbd | 9419 | enum intel_dpll_id pll_id; |
66e985c0 | 9420 | |
88adfff1 DV |
9421 | pipe_config->has_pch_encoder = true; |
9422 | ||
627eb5a3 DV |
9423 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9424 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9425 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9426 | |
9427 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9428 | |
2d1fe073 | 9429 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9430 | /* |
9431 | * The pipe->pch transcoder and pch transcoder->pll | |
9432 | * mapping is fixed. | |
9433 | */ | |
8106ddbd | 9434 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9435 | } else { |
9436 | tmp = I915_READ(PCH_DPLL_SEL); | |
9437 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9438 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9439 | else |
8106ddbd | 9440 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9441 | } |
66e985c0 | 9442 | |
8106ddbd ACO |
9443 | pipe_config->shared_dpll = |
9444 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9445 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9446 | |
2edd6443 ACO |
9447 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9448 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9449 | |
9450 | tmp = pipe_config->dpll_hw_state.dpll; | |
9451 | pipe_config->pixel_multiplier = | |
9452 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9453 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9454 | |
9455 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9456 | } else { |
9457 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9458 | } |
9459 | ||
1bd1bd80 | 9460 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9461 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9462 | |
2fa2fe9a DV |
9463 | ironlake_get_pfit_config(crtc, pipe_config); |
9464 | ||
1729050e ID |
9465 | ret = true; |
9466 | ||
9467 | out: | |
9468 | intel_display_power_put(dev_priv, power_domain); | |
9469 | ||
9470 | return ret; | |
0e8ffe1b DV |
9471 | } |
9472 | ||
be256dc7 PZ |
9473 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9474 | { | |
9475 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9476 | struct intel_crtc *crtc; |
be256dc7 | 9477 | |
d3fcc808 | 9478 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9479 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9480 | pipe_name(crtc->pipe)); |
9481 | ||
e2c719b7 RC |
9482 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9483 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9484 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9485 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9486 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9487 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9488 | "CPU PWM1 enabled\n"); |
c5107b87 | 9489 | if (IS_HASWELL(dev)) |
e2c719b7 | 9490 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9491 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9492 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9493 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9494 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9495 | "Utility pin enabled\n"); |
e2c719b7 | 9496 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9497 | |
9926ada1 PZ |
9498 | /* |
9499 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9500 | * interrupts remain enabled. We used to check for that, but since it's | |
9501 | * gen-specific and since we only disable LCPLL after we fully disable | |
9502 | * the interrupts, the check below should be enough. | |
9503 | */ | |
e2c719b7 | 9504 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9505 | } |
9506 | ||
9ccd5aeb PZ |
9507 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9508 | { | |
9509 | struct drm_device *dev = dev_priv->dev; | |
9510 | ||
9511 | if (IS_HASWELL(dev)) | |
9512 | return I915_READ(D_COMP_HSW); | |
9513 | else | |
9514 | return I915_READ(D_COMP_BDW); | |
9515 | } | |
9516 | ||
3c4c9b81 PZ |
9517 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9518 | { | |
9519 | struct drm_device *dev = dev_priv->dev; | |
9520 | ||
9521 | if (IS_HASWELL(dev)) { | |
9522 | mutex_lock(&dev_priv->rps.hw_lock); | |
9523 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9524 | val)) | |
f475dadf | 9525 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9526 | mutex_unlock(&dev_priv->rps.hw_lock); |
9527 | } else { | |
9ccd5aeb PZ |
9528 | I915_WRITE(D_COMP_BDW, val); |
9529 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9530 | } |
be256dc7 PZ |
9531 | } |
9532 | ||
9533 | /* | |
9534 | * This function implements pieces of two sequences from BSpec: | |
9535 | * - Sequence for display software to disable LCPLL | |
9536 | * - Sequence for display software to allow package C8+ | |
9537 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9538 | * register. Callers should take care of disabling all the display engine | |
9539 | * functions, doing the mode unset, fixing interrupts, etc. | |
9540 | */ | |
6ff58d53 PZ |
9541 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9542 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9543 | { |
9544 | uint32_t val; | |
9545 | ||
9546 | assert_can_disable_lcpll(dev_priv); | |
9547 | ||
9548 | val = I915_READ(LCPLL_CTL); | |
9549 | ||
9550 | if (switch_to_fclk) { | |
9551 | val |= LCPLL_CD_SOURCE_FCLK; | |
9552 | I915_WRITE(LCPLL_CTL, val); | |
9553 | ||
f53dd63f ID |
9554 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9555 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
9556 | DRM_ERROR("Switching to FCLK failed\n"); |
9557 | ||
9558 | val = I915_READ(LCPLL_CTL); | |
9559 | } | |
9560 | ||
9561 | val |= LCPLL_PLL_DISABLE; | |
9562 | I915_WRITE(LCPLL_CTL, val); | |
9563 | POSTING_READ(LCPLL_CTL); | |
9564 | ||
9565 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9566 | DRM_ERROR("LCPLL still locked\n"); | |
9567 | ||
9ccd5aeb | 9568 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9569 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9570 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9571 | ndelay(100); |
9572 | ||
9ccd5aeb PZ |
9573 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9574 | 1)) | |
be256dc7 PZ |
9575 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9576 | ||
9577 | if (allow_power_down) { | |
9578 | val = I915_READ(LCPLL_CTL); | |
9579 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9580 | I915_WRITE(LCPLL_CTL, val); | |
9581 | POSTING_READ(LCPLL_CTL); | |
9582 | } | |
9583 | } | |
9584 | ||
9585 | /* | |
9586 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9587 | * source. | |
9588 | */ | |
6ff58d53 | 9589 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9590 | { |
9591 | uint32_t val; | |
9592 | ||
9593 | val = I915_READ(LCPLL_CTL); | |
9594 | ||
9595 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9596 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9597 | return; | |
9598 | ||
a8a8bd54 PZ |
9599 | /* |
9600 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9601 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9602 | */ |
59bad947 | 9603 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9604 | |
be256dc7 PZ |
9605 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9606 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9607 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9608 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9609 | } |
9610 | ||
9ccd5aeb | 9611 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9612 | val |= D_COMP_COMP_FORCE; |
9613 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9614 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9615 | |
9616 | val = I915_READ(LCPLL_CTL); | |
9617 | val &= ~LCPLL_PLL_DISABLE; | |
9618 | I915_WRITE(LCPLL_CTL, val); | |
9619 | ||
9620 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9621 | DRM_ERROR("LCPLL not locked yet\n"); | |
9622 | ||
9623 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9624 | val = I915_READ(LCPLL_CTL); | |
9625 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9626 | I915_WRITE(LCPLL_CTL, val); | |
9627 | ||
f53dd63f ID |
9628 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9629 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
9630 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9631 | } | |
215733fa | 9632 | |
59bad947 | 9633 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9634 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9635 | } |
9636 | ||
765dab67 PZ |
9637 | /* |
9638 | * Package states C8 and deeper are really deep PC states that can only be | |
9639 | * reached when all the devices on the system allow it, so even if the graphics | |
9640 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9641 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9642 | * | |
9643 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9644 | * well is disabled and most interrupts are disabled, and these are also | |
9645 | * requirements for runtime PM. When these conditions are met, we manually do | |
9646 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9647 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9648 | * hang the machine. | |
9649 | * | |
9650 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9651 | * the state of some registers, so when we come back from PC8+ we need to | |
9652 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9653 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9654 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9655 | * because of the runtime PM support). | |
9656 | * | |
9657 | * For more, read "Display Sequences for Package C8" on the hardware | |
9658 | * documentation. | |
9659 | */ | |
a14cb6fc | 9660 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9661 | { |
c67a470b PZ |
9662 | struct drm_device *dev = dev_priv->dev; |
9663 | uint32_t val; | |
9664 | ||
c67a470b PZ |
9665 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9666 | ||
c2699524 | 9667 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9668 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9669 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9670 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9671 | } | |
9672 | ||
9673 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9674 | hsw_disable_lcpll(dev_priv, true, true); |
9675 | } | |
9676 | ||
a14cb6fc | 9677 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9678 | { |
9679 | struct drm_device *dev = dev_priv->dev; | |
9680 | uint32_t val; | |
9681 | ||
c67a470b PZ |
9682 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9683 | ||
9684 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9685 | lpt_init_pch_refclk(dev); |
9686 | ||
c2699524 | 9687 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9688 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9689 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9690 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9691 | } | |
c67a470b PZ |
9692 | } |
9693 | ||
324513c0 | 9694 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9695 | { |
a821fc46 | 9696 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9697 | struct intel_atomic_state *old_intel_state = |
9698 | to_intel_atomic_state(old_state); | |
9699 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9700 | |
324513c0 | 9701 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
9702 | } |
9703 | ||
b432e5cf | 9704 | /* compute the max rate for new configuration */ |
27c329ed | 9705 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9706 | { |
565602d7 ML |
9707 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9708 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9709 | struct drm_crtc *crtc; | |
9710 | struct drm_crtc_state *cstate; | |
27c329ed | 9711 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9712 | unsigned max_pixel_rate = 0, i; |
9713 | enum pipe pipe; | |
b432e5cf | 9714 | |
565602d7 ML |
9715 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9716 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9717 | |
565602d7 ML |
9718 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9719 | int pixel_rate; | |
27c329ed | 9720 | |
565602d7 ML |
9721 | crtc_state = to_intel_crtc_state(cstate); |
9722 | if (!crtc_state->base.enable) { | |
9723 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9724 | continue; |
565602d7 | 9725 | } |
b432e5cf | 9726 | |
27c329ed | 9727 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9728 | |
9729 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9730 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9731 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9732 | ||
565602d7 | 9733 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9734 | } |
9735 | ||
565602d7 ML |
9736 | for_each_pipe(dev_priv, pipe) |
9737 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9738 | ||
b432e5cf VS |
9739 | return max_pixel_rate; |
9740 | } | |
9741 | ||
9742 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9743 | { | |
9744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9745 | uint32_t val, data; | |
9746 | int ret; | |
9747 | ||
9748 | if (WARN((I915_READ(LCPLL_CTL) & | |
9749 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9750 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9751 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9752 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9753 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9754 | return; | |
9755 | ||
9756 | mutex_lock(&dev_priv->rps.hw_lock); | |
9757 | ret = sandybridge_pcode_write(dev_priv, | |
9758 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9759 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9760 | if (ret) { | |
9761 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9762 | return; | |
9763 | } | |
9764 | ||
9765 | val = I915_READ(LCPLL_CTL); | |
9766 | val |= LCPLL_CD_SOURCE_FCLK; | |
9767 | I915_WRITE(LCPLL_CTL, val); | |
9768 | ||
5ba00178 TU |
9769 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9770 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9771 | DRM_ERROR("Switching to FCLK failed\n"); |
9772 | ||
9773 | val = I915_READ(LCPLL_CTL); | |
9774 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9775 | ||
9776 | switch (cdclk) { | |
9777 | case 450000: | |
9778 | val |= LCPLL_CLK_FREQ_450; | |
9779 | data = 0; | |
9780 | break; | |
9781 | case 540000: | |
9782 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9783 | data = 1; | |
9784 | break; | |
9785 | case 337500: | |
9786 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9787 | data = 2; | |
9788 | break; | |
9789 | case 675000: | |
9790 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9791 | data = 3; | |
9792 | break; | |
9793 | default: | |
9794 | WARN(1, "invalid cdclk frequency\n"); | |
9795 | return; | |
9796 | } | |
9797 | ||
9798 | I915_WRITE(LCPLL_CTL, val); | |
9799 | ||
9800 | val = I915_READ(LCPLL_CTL); | |
9801 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9802 | I915_WRITE(LCPLL_CTL, val); | |
9803 | ||
5ba00178 TU |
9804 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9805 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9806 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9807 | ||
9808 | mutex_lock(&dev_priv->rps.hw_lock); | |
9809 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9810 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9811 | ||
7f1052a8 VS |
9812 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
9813 | ||
b432e5cf VS |
9814 | intel_update_cdclk(dev); |
9815 | ||
9816 | WARN(cdclk != dev_priv->cdclk_freq, | |
9817 | "cdclk requested %d kHz but got %d kHz\n", | |
9818 | cdclk, dev_priv->cdclk_freq); | |
9819 | } | |
9820 | ||
587c7914 VS |
9821 | static int broadwell_calc_cdclk(int max_pixclk) |
9822 | { | |
9823 | if (max_pixclk > 540000) | |
9824 | return 675000; | |
9825 | else if (max_pixclk > 450000) | |
9826 | return 540000; | |
9827 | else if (max_pixclk > 337500) | |
9828 | return 450000; | |
9829 | else | |
9830 | return 337500; | |
9831 | } | |
9832 | ||
27c329ed | 9833 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9834 | { |
27c329ed | 9835 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9836 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9837 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9838 | int cdclk; |
9839 | ||
9840 | /* | |
9841 | * FIXME should also account for plane ratio | |
9842 | * once 64bpp pixel formats are supported. | |
9843 | */ | |
587c7914 | 9844 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 9845 | |
b432e5cf | 9846 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9847 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9848 | cdclk, dev_priv->max_cdclk_freq); | |
9849 | return -EINVAL; | |
b432e5cf VS |
9850 | } |
9851 | ||
1a617b77 ML |
9852 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9853 | if (!intel_state->active_crtcs) | |
587c7914 | 9854 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
9855 | |
9856 | return 0; | |
9857 | } | |
9858 | ||
27c329ed | 9859 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9860 | { |
27c329ed | 9861 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9862 | struct intel_atomic_state *old_intel_state = |
9863 | to_intel_atomic_state(old_state); | |
9864 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9865 | |
27c329ed | 9866 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9867 | } |
9868 | ||
c89e39f3 CT |
9869 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
9870 | { | |
9871 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
9872 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9873 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 9874 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
9875 | int cdclk; |
9876 | ||
9877 | /* | |
9878 | * FIXME should also account for plane ratio | |
9879 | * once 64bpp pixel formats are supported. | |
9880 | */ | |
a8ca4934 | 9881 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
9882 | |
9883 | /* | |
9884 | * FIXME move the cdclk caclulation to | |
9885 | * compute_config() so we can fail gracegully. | |
9886 | */ | |
9887 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9888 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9889 | cdclk, dev_priv->max_cdclk_freq); | |
9890 | cdclk = dev_priv->max_cdclk_freq; | |
9891 | } | |
9892 | ||
9893 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
9894 | if (!intel_state->active_crtcs) | |
a8ca4934 | 9895 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
9896 | |
9897 | return 0; | |
9898 | } | |
9899 | ||
9900 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
9901 | { | |
1cd593e0 VS |
9902 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
9903 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
9904 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
9905 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 9906 | |
1cd593e0 | 9907 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
9908 | } |
9909 | ||
190f68c5 ACO |
9910 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9911 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9912 | { |
af3997b5 MK |
9913 | struct intel_encoder *intel_encoder = |
9914 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9915 | ||
9916 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9917 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9918 | return -EINVAL; | |
9919 | } | |
716c2e55 | 9920 | |
c7653199 | 9921 | crtc->lowfreq_avail = false; |
644cef34 | 9922 | |
c8f7a0db | 9923 | return 0; |
79e53945 JB |
9924 | } |
9925 | ||
3760b59c S |
9926 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9927 | enum port port, | |
9928 | struct intel_crtc_state *pipe_config) | |
9929 | { | |
8106ddbd ACO |
9930 | enum intel_dpll_id id; |
9931 | ||
3760b59c S |
9932 | switch (port) { |
9933 | case PORT_A: | |
9934 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 9935 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9936 | break; |
9937 | case PORT_B: | |
9938 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 9939 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9940 | break; |
9941 | case PORT_C: | |
9942 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 9943 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9944 | break; |
9945 | default: | |
9946 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9947 | return; |
3760b59c | 9948 | } |
8106ddbd ACO |
9949 | |
9950 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9951 | } |
9952 | ||
96b7dfb7 S |
9953 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9954 | enum port port, | |
5cec258b | 9955 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9956 | { |
8106ddbd | 9957 | enum intel_dpll_id id; |
a3c988ea | 9958 | u32 temp; |
96b7dfb7 S |
9959 | |
9960 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9961 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9962 | ||
9963 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 9964 | case SKL_DPLL0: |
a3c988ea ACO |
9965 | id = DPLL_ID_SKL_DPLL0; |
9966 | break; | |
96b7dfb7 | 9967 | case SKL_DPLL1: |
8106ddbd | 9968 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
9969 | break; |
9970 | case SKL_DPLL2: | |
8106ddbd | 9971 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
9972 | break; |
9973 | case SKL_DPLL3: | |
8106ddbd | 9974 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 9975 | break; |
8106ddbd ACO |
9976 | default: |
9977 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9978 | return; | |
96b7dfb7 | 9979 | } |
8106ddbd ACO |
9980 | |
9981 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9982 | } |
9983 | ||
7d2c8175 DL |
9984 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9985 | enum port port, | |
5cec258b | 9986 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9987 | { |
8106ddbd ACO |
9988 | enum intel_dpll_id id; |
9989 | ||
7d2c8175 DL |
9990 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
9991 | ||
9992 | switch (pipe_config->ddi_pll_sel) { | |
9993 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 9994 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9995 | break; |
9996 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9997 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9998 | break; |
00490c22 | 9999 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 10000 | id = DPLL_ID_SPLL; |
79bd23da | 10001 | break; |
9d16da65 ACO |
10002 | case PORT_CLK_SEL_LCPLL_810: |
10003 | id = DPLL_ID_LCPLL_810; | |
10004 | break; | |
10005 | case PORT_CLK_SEL_LCPLL_1350: | |
10006 | id = DPLL_ID_LCPLL_1350; | |
10007 | break; | |
10008 | case PORT_CLK_SEL_LCPLL_2700: | |
10009 | id = DPLL_ID_LCPLL_2700; | |
10010 | break; | |
8106ddbd ACO |
10011 | default: |
10012 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
10013 | /* fall through */ | |
10014 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 10015 | return; |
7d2c8175 | 10016 | } |
8106ddbd ACO |
10017 | |
10018 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
10019 | } |
10020 | ||
cf30429e JN |
10021 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
10022 | struct intel_crtc_state *pipe_config, | |
10023 | unsigned long *power_domain_mask) | |
10024 | { | |
10025 | struct drm_device *dev = crtc->base.dev; | |
10026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10027 | enum intel_display_power_domain power_domain; | |
10028 | u32 tmp; | |
10029 | ||
d9a7bc67 ID |
10030 | /* |
10031 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
10032 | * transcoder handled below. | |
10033 | */ | |
cf30429e JN |
10034 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
10035 | ||
10036 | /* | |
10037 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
10038 | * consistency and less surprising code; it's in always on power). | |
10039 | */ | |
10040 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
10041 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10042 | enum pipe trans_edp_pipe; | |
10043 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10044 | default: | |
10045 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10046 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10047 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10048 | trans_edp_pipe = PIPE_A; | |
10049 | break; | |
10050 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10051 | trans_edp_pipe = PIPE_B; | |
10052 | break; | |
10053 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10054 | trans_edp_pipe = PIPE_C; | |
10055 | break; | |
10056 | } | |
10057 | ||
10058 | if (trans_edp_pipe == crtc->pipe) | |
10059 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10060 | } | |
10061 | ||
10062 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
10063 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10064 | return false; | |
10065 | *power_domain_mask |= BIT(power_domain); | |
10066 | ||
10067 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
10068 | ||
10069 | return tmp & PIPECONF_ENABLE; | |
10070 | } | |
10071 | ||
4d1de975 JN |
10072 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10073 | struct intel_crtc_state *pipe_config, | |
10074 | unsigned long *power_domain_mask) | |
10075 | { | |
10076 | struct drm_device *dev = crtc->base.dev; | |
10077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10078 | enum intel_display_power_domain power_domain; | |
10079 | enum port port; | |
10080 | enum transcoder cpu_transcoder; | |
10081 | u32 tmp; | |
10082 | ||
10083 | pipe_config->has_dsi_encoder = false; | |
10084 | ||
10085 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { | |
10086 | if (port == PORT_A) | |
10087 | cpu_transcoder = TRANSCODER_DSI_A; | |
10088 | else | |
10089 | cpu_transcoder = TRANSCODER_DSI_C; | |
10090 | ||
10091 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10092 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10093 | continue; | |
10094 | *power_domain_mask |= BIT(power_domain); | |
10095 | ||
db18b6a6 ID |
10096 | /* |
10097 | * The PLL needs to be enabled with a valid divider | |
10098 | * configuration, otherwise accessing DSI registers will hang | |
10099 | * the machine. See BSpec North Display Engine | |
10100 | * registers/MIPI[BXT]. We can break out here early, since we | |
10101 | * need the same DSI PLL to be enabled for both DSI ports. | |
10102 | */ | |
10103 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10104 | break; | |
10105 | ||
4d1de975 JN |
10106 | /* XXX: this works for video mode only */ |
10107 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10108 | if (!(tmp & DPI_ENABLE)) | |
10109 | continue; | |
10110 | ||
10111 | tmp = I915_READ(MIPI_CTRL(port)); | |
10112 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10113 | continue; | |
10114 | ||
10115 | pipe_config->cpu_transcoder = cpu_transcoder; | |
10116 | pipe_config->has_dsi_encoder = true; | |
10117 | break; | |
10118 | } | |
10119 | ||
10120 | return pipe_config->has_dsi_encoder; | |
10121 | } | |
10122 | ||
26804afd | 10123 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10124 | struct intel_crtc_state *pipe_config) |
26804afd DV |
10125 | { |
10126 | struct drm_device *dev = crtc->base.dev; | |
10127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 10128 | struct intel_shared_dpll *pll; |
26804afd DV |
10129 | enum port port; |
10130 | uint32_t tmp; | |
10131 | ||
10132 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10133 | ||
10134 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10135 | ||
ef11bdb3 | 10136 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 10137 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
10138 | else if (IS_BROXTON(dev)) |
10139 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
10140 | else |
10141 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10142 | |
8106ddbd ACO |
10143 | pll = pipe_config->shared_dpll; |
10144 | if (pll) { | |
2edd6443 ACO |
10145 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10146 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10147 | } |
10148 | ||
26804afd DV |
10149 | /* |
10150 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10151 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10152 | * the PCH transcoder is on. | |
10153 | */ | |
ca370455 DL |
10154 | if (INTEL_INFO(dev)->gen < 9 && |
10155 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
10156 | pipe_config->has_pch_encoder = true; |
10157 | ||
10158 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10159 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10160 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10161 | ||
10162 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10163 | } | |
10164 | } | |
10165 | ||
0e8ffe1b | 10166 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10167 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10168 | { |
10169 | struct drm_device *dev = crtc->base.dev; | |
10170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
10171 | enum intel_display_power_domain power_domain; |
10172 | unsigned long power_domain_mask; | |
cf30429e | 10173 | bool active; |
0e8ffe1b | 10174 | |
1729050e ID |
10175 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10176 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10177 | return false; |
1729050e ID |
10178 | power_domain_mask = BIT(power_domain); |
10179 | ||
8106ddbd | 10180 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10181 | |
cf30429e | 10182 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10183 | |
4d1de975 JN |
10184 | if (IS_BROXTON(dev_priv)) { |
10185 | bxt_get_dsi_transcoder_state(crtc, pipe_config, | |
10186 | &power_domain_mask); | |
10187 | WARN_ON(active && pipe_config->has_dsi_encoder); | |
10188 | if (pipe_config->has_dsi_encoder) | |
10189 | active = true; | |
10190 | } | |
10191 | ||
cf30429e | 10192 | if (!active) |
1729050e | 10193 | goto out; |
0e8ffe1b | 10194 | |
4d1de975 JN |
10195 | if (!pipe_config->has_dsi_encoder) { |
10196 | haswell_get_ddi_port_state(crtc, pipe_config); | |
10197 | intel_get_pipe_timings(crtc, pipe_config); | |
10198 | } | |
627eb5a3 | 10199 | |
bc58be60 | 10200 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10201 | |
05dc698c LL |
10202 | pipe_config->gamma_mode = |
10203 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10204 | ||
a1b2278e CK |
10205 | if (INTEL_INFO(dev)->gen >= 9) { |
10206 | skl_init_scalers(dev, crtc, pipe_config); | |
10207 | } | |
10208 | ||
af99ceda CK |
10209 | if (INTEL_INFO(dev)->gen >= 9) { |
10210 | pipe_config->scaler_state.scaler_id = -1; | |
10211 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10212 | } | |
10213 | ||
1729050e ID |
10214 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10215 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10216 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10217 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10218 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10219 | else |
1c132b44 | 10220 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10221 | } |
88adfff1 | 10222 | |
e59150dc JB |
10223 | if (IS_HASWELL(dev)) |
10224 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10225 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10226 | |
4d1de975 JN |
10227 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10228 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10229 | pipe_config->pixel_multiplier = |
10230 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10231 | } else { | |
10232 | pipe_config->pixel_multiplier = 1; | |
10233 | } | |
6c49f241 | 10234 | |
1729050e ID |
10235 | out: |
10236 | for_each_power_domain(power_domain, power_domain_mask) | |
10237 | intel_display_power_put(dev_priv, power_domain); | |
10238 | ||
cf30429e | 10239 | return active; |
0e8ffe1b DV |
10240 | } |
10241 | ||
55a08b3f ML |
10242 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10243 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10244 | { |
10245 | struct drm_device *dev = crtc->dev; | |
10246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10248 | uint32_t cntl = 0, size = 0; |
560b85bb | 10249 | |
55a08b3f ML |
10250 | if (plane_state && plane_state->visible) { |
10251 | unsigned int width = plane_state->base.crtc_w; | |
10252 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10253 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10254 | ||
10255 | switch (stride) { | |
10256 | default: | |
10257 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10258 | width, stride); | |
10259 | stride = 256; | |
10260 | /* fallthrough */ | |
10261 | case 256: | |
10262 | case 512: | |
10263 | case 1024: | |
10264 | case 2048: | |
10265 | break; | |
4b0e333e CW |
10266 | } |
10267 | ||
dc41c154 VS |
10268 | cntl |= CURSOR_ENABLE | |
10269 | CURSOR_GAMMA_ENABLE | | |
10270 | CURSOR_FORMAT_ARGB | | |
10271 | CURSOR_STRIDE(stride); | |
10272 | ||
10273 | size = (height << 12) | width; | |
4b0e333e | 10274 | } |
560b85bb | 10275 | |
dc41c154 VS |
10276 | if (intel_crtc->cursor_cntl != 0 && |
10277 | (intel_crtc->cursor_base != base || | |
10278 | intel_crtc->cursor_size != size || | |
10279 | intel_crtc->cursor_cntl != cntl)) { | |
10280 | /* On these chipsets we can only modify the base/size/stride | |
10281 | * whilst the cursor is disabled. | |
10282 | */ | |
0b87c24e VS |
10283 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10284 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10285 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10286 | } |
560b85bb | 10287 | |
99d1f387 | 10288 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10289 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10290 | intel_crtc->cursor_base = base; |
10291 | } | |
4726e0b0 | 10292 | |
dc41c154 VS |
10293 | if (intel_crtc->cursor_size != size) { |
10294 | I915_WRITE(CURSIZE, size); | |
10295 | intel_crtc->cursor_size = size; | |
4b0e333e | 10296 | } |
560b85bb | 10297 | |
4b0e333e | 10298 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10299 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10300 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10301 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10302 | } |
560b85bb CW |
10303 | } |
10304 | ||
55a08b3f ML |
10305 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10306 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10307 | { |
10308 | struct drm_device *dev = crtc->dev; | |
10309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10311 | int pipe = intel_crtc->pipe; | |
663f3122 | 10312 | uint32_t cntl = 0; |
4b0e333e | 10313 | |
55a08b3f | 10314 | if (plane_state && plane_state->visible) { |
4b0e333e | 10315 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10316 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10317 | case 64: |
10318 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10319 | break; | |
10320 | case 128: | |
10321 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10322 | break; | |
10323 | case 256: | |
10324 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10325 | break; | |
10326 | default: | |
55a08b3f | 10327 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10328 | return; |
65a21cd6 | 10329 | } |
4b0e333e | 10330 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10331 | |
fc6f93bc | 10332 | if (HAS_DDI(dev)) |
47bf17a7 | 10333 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10334 | |
55a08b3f ML |
10335 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10336 | cntl |= CURSOR_ROTATE_180; | |
10337 | } | |
4398ad45 | 10338 | |
4b0e333e CW |
10339 | if (intel_crtc->cursor_cntl != cntl) { |
10340 | I915_WRITE(CURCNTR(pipe), cntl); | |
10341 | POSTING_READ(CURCNTR(pipe)); | |
10342 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10343 | } |
4b0e333e | 10344 | |
65a21cd6 | 10345 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10346 | I915_WRITE(CURBASE(pipe), base); |
10347 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10348 | |
10349 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10350 | } |
10351 | ||
cda4b7d3 | 10352 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10353 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10354 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10355 | { |
10356 | struct drm_device *dev = crtc->dev; | |
10357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10358 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10359 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10360 | u32 base = intel_crtc->cursor_addr; |
10361 | u32 pos = 0; | |
cda4b7d3 | 10362 | |
55a08b3f ML |
10363 | if (plane_state) { |
10364 | int x = plane_state->base.crtc_x; | |
10365 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10366 | |
55a08b3f ML |
10367 | if (x < 0) { |
10368 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10369 | x = -x; | |
10370 | } | |
10371 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10372 | |
55a08b3f ML |
10373 | if (y < 0) { |
10374 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10375 | y = -y; | |
10376 | } | |
10377 | pos |= y << CURSOR_Y_SHIFT; | |
10378 | ||
10379 | /* ILK+ do this automagically */ | |
10380 | if (HAS_GMCH_DISPLAY(dev) && | |
10381 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10382 | base += (plane_state->base.crtc_h * | |
10383 | plane_state->base.crtc_w - 1) * 4; | |
10384 | } | |
cda4b7d3 | 10385 | } |
cda4b7d3 | 10386 | |
5efb3e28 VS |
10387 | I915_WRITE(CURPOS(pipe), pos); |
10388 | ||
8ac54669 | 10389 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10390 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10391 | else |
55a08b3f | 10392 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10393 | } |
10394 | ||
dc41c154 VS |
10395 | static bool cursor_size_ok(struct drm_device *dev, |
10396 | uint32_t width, uint32_t height) | |
10397 | { | |
10398 | if (width == 0 || height == 0) | |
10399 | return false; | |
10400 | ||
10401 | /* | |
10402 | * 845g/865g are special in that they are only limited by | |
10403 | * the width of their cursors, the height is arbitrary up to | |
10404 | * the precision of the register. Everything else requires | |
10405 | * square cursors, limited to a few power-of-two sizes. | |
10406 | */ | |
10407 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10408 | if ((width & 63) != 0) | |
10409 | return false; | |
10410 | ||
10411 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10412 | return false; | |
10413 | ||
10414 | if (height > 1023) | |
10415 | return false; | |
10416 | } else { | |
10417 | switch (width | height) { | |
10418 | case 256: | |
10419 | case 128: | |
10420 | if (IS_GEN2(dev)) | |
10421 | return false; | |
10422 | case 64: | |
10423 | break; | |
10424 | default: | |
10425 | return false; | |
10426 | } | |
10427 | } | |
10428 | ||
10429 | return true; | |
10430 | } | |
10431 | ||
79e53945 JB |
10432 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10433 | static struct drm_display_mode load_detect_mode = { | |
10434 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10435 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10436 | }; | |
10437 | ||
a8bb6818 DV |
10438 | struct drm_framebuffer * |
10439 | __intel_framebuffer_create(struct drm_device *dev, | |
10440 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10441 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10442 | { |
10443 | struct intel_framebuffer *intel_fb; | |
10444 | int ret; | |
10445 | ||
10446 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10447 | if (!intel_fb) |
d2dff872 | 10448 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10449 | |
10450 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10451 | if (ret) |
10452 | goto err; | |
d2dff872 CW |
10453 | |
10454 | return &intel_fb->base; | |
dcb1394e | 10455 | |
dd4916c5 | 10456 | err: |
dd4916c5 | 10457 | kfree(intel_fb); |
dd4916c5 | 10458 | return ERR_PTR(ret); |
d2dff872 CW |
10459 | } |
10460 | ||
b5ea642a | 10461 | static struct drm_framebuffer * |
a8bb6818 DV |
10462 | intel_framebuffer_create(struct drm_device *dev, |
10463 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10464 | struct drm_i915_gem_object *obj) | |
10465 | { | |
10466 | struct drm_framebuffer *fb; | |
10467 | int ret; | |
10468 | ||
10469 | ret = i915_mutex_lock_interruptible(dev); | |
10470 | if (ret) | |
10471 | return ERR_PTR(ret); | |
10472 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10473 | mutex_unlock(&dev->struct_mutex); | |
10474 | ||
10475 | return fb; | |
10476 | } | |
10477 | ||
d2dff872 CW |
10478 | static u32 |
10479 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10480 | { | |
10481 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10482 | return ALIGN(pitch, 64); | |
10483 | } | |
10484 | ||
10485 | static u32 | |
10486 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10487 | { | |
10488 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10489 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10490 | } |
10491 | ||
10492 | static struct drm_framebuffer * | |
10493 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10494 | struct drm_display_mode *mode, | |
10495 | int depth, int bpp) | |
10496 | { | |
dcb1394e | 10497 | struct drm_framebuffer *fb; |
d2dff872 | 10498 | struct drm_i915_gem_object *obj; |
0fed39bd | 10499 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 10500 | |
d37cd8a8 | 10501 | obj = i915_gem_object_create(dev, |
d2dff872 | 10502 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
10503 | if (IS_ERR(obj)) |
10504 | return ERR_CAST(obj); | |
d2dff872 CW |
10505 | |
10506 | mode_cmd.width = mode->hdisplay; | |
10507 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10508 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10509 | bpp); | |
5ca0c34a | 10510 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10511 | |
dcb1394e LW |
10512 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10513 | if (IS_ERR(fb)) | |
10514 | drm_gem_object_unreference_unlocked(&obj->base); | |
10515 | ||
10516 | return fb; | |
d2dff872 CW |
10517 | } |
10518 | ||
10519 | static struct drm_framebuffer * | |
10520 | mode_fits_in_fbdev(struct drm_device *dev, | |
10521 | struct drm_display_mode *mode) | |
10522 | { | |
0695726e | 10523 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10524 | struct drm_i915_private *dev_priv = dev->dev_private; |
10525 | struct drm_i915_gem_object *obj; | |
10526 | struct drm_framebuffer *fb; | |
10527 | ||
4c0e5528 | 10528 | if (!dev_priv->fbdev) |
d2dff872 CW |
10529 | return NULL; |
10530 | ||
4c0e5528 | 10531 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10532 | return NULL; |
10533 | ||
4c0e5528 DV |
10534 | obj = dev_priv->fbdev->fb->obj; |
10535 | BUG_ON(!obj); | |
10536 | ||
8bcd4553 | 10537 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10538 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10539 | fb->bits_per_pixel)) | |
d2dff872 CW |
10540 | return NULL; |
10541 | ||
01f2c773 | 10542 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10543 | return NULL; |
10544 | ||
edde3617 | 10545 | drm_framebuffer_reference(fb); |
d2dff872 | 10546 | return fb; |
4520f53a DV |
10547 | #else |
10548 | return NULL; | |
10549 | #endif | |
d2dff872 CW |
10550 | } |
10551 | ||
d3a40d1b ACO |
10552 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10553 | struct drm_crtc *crtc, | |
10554 | struct drm_display_mode *mode, | |
10555 | struct drm_framebuffer *fb, | |
10556 | int x, int y) | |
10557 | { | |
10558 | struct drm_plane_state *plane_state; | |
10559 | int hdisplay, vdisplay; | |
10560 | int ret; | |
10561 | ||
10562 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10563 | if (IS_ERR(plane_state)) | |
10564 | return PTR_ERR(plane_state); | |
10565 | ||
10566 | if (mode) | |
10567 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10568 | else | |
10569 | hdisplay = vdisplay = 0; | |
10570 | ||
10571 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10572 | if (ret) | |
10573 | return ret; | |
10574 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10575 | plane_state->crtc_x = 0; | |
10576 | plane_state->crtc_y = 0; | |
10577 | plane_state->crtc_w = hdisplay; | |
10578 | plane_state->crtc_h = vdisplay; | |
10579 | plane_state->src_x = x << 16; | |
10580 | plane_state->src_y = y << 16; | |
10581 | plane_state->src_w = hdisplay << 16; | |
10582 | plane_state->src_h = vdisplay << 16; | |
10583 | ||
10584 | return 0; | |
10585 | } | |
10586 | ||
d2434ab7 | 10587 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10588 | struct drm_display_mode *mode, |
51fd371b RC |
10589 | struct intel_load_detect_pipe *old, |
10590 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10591 | { |
10592 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10593 | struct intel_encoder *intel_encoder = |
10594 | intel_attached_encoder(connector); | |
79e53945 | 10595 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10596 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10597 | struct drm_crtc *crtc = NULL; |
10598 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10599 | struct drm_framebuffer *fb; |
51fd371b | 10600 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10601 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10602 | struct drm_connector_state *connector_state; |
4be07317 | 10603 | struct intel_crtc_state *crtc_state; |
51fd371b | 10604 | int ret, i = -1; |
79e53945 | 10605 | |
d2dff872 | 10606 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10607 | connector->base.id, connector->name, |
8e329a03 | 10608 | encoder->base.id, encoder->name); |
d2dff872 | 10609 | |
edde3617 ML |
10610 | old->restore_state = NULL; |
10611 | ||
51fd371b RC |
10612 | retry: |
10613 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10614 | if (ret) | |
ad3c558f | 10615 | goto fail; |
6e9f798d | 10616 | |
79e53945 JB |
10617 | /* |
10618 | * Algorithm gets a little messy: | |
7a5e4805 | 10619 | * |
79e53945 JB |
10620 | * - if the connector already has an assigned crtc, use it (but make |
10621 | * sure it's on first) | |
7a5e4805 | 10622 | * |
79e53945 JB |
10623 | * - try to find the first unused crtc that can drive this connector, |
10624 | * and use that if we find one | |
79e53945 JB |
10625 | */ |
10626 | ||
10627 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10628 | if (connector->state->crtc) { |
10629 | crtc = connector->state->crtc; | |
8261b191 | 10630 | |
51fd371b | 10631 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10632 | if (ret) |
ad3c558f | 10633 | goto fail; |
8261b191 CW |
10634 | |
10635 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10636 | goto found; |
79e53945 JB |
10637 | } |
10638 | ||
10639 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10640 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10641 | i++; |
10642 | if (!(encoder->possible_crtcs & (1 << i))) | |
10643 | continue; | |
edde3617 ML |
10644 | |
10645 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10646 | if (ret) | |
10647 | goto fail; | |
10648 | ||
10649 | if (possible_crtc->state->enable) { | |
10650 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10651 | continue; |
edde3617 | 10652 | } |
a459249c VS |
10653 | |
10654 | crtc = possible_crtc; | |
10655 | break; | |
79e53945 JB |
10656 | } |
10657 | ||
10658 | /* | |
10659 | * If we didn't find an unused CRTC, don't use any. | |
10660 | */ | |
10661 | if (!crtc) { | |
7173188d | 10662 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10663 | goto fail; |
79e53945 JB |
10664 | } |
10665 | ||
edde3617 ML |
10666 | found: |
10667 | intel_crtc = to_intel_crtc(crtc); | |
10668 | ||
4d02e2de DV |
10669 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10670 | if (ret) | |
ad3c558f | 10671 | goto fail; |
79e53945 | 10672 | |
83a57153 | 10673 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10674 | restore_state = drm_atomic_state_alloc(dev); |
10675 | if (!state || !restore_state) { | |
10676 | ret = -ENOMEM; | |
10677 | goto fail; | |
10678 | } | |
83a57153 ACO |
10679 | |
10680 | state->acquire_ctx = ctx; | |
edde3617 | 10681 | restore_state->acquire_ctx = ctx; |
83a57153 | 10682 | |
944b0c76 ACO |
10683 | connector_state = drm_atomic_get_connector_state(state, connector); |
10684 | if (IS_ERR(connector_state)) { | |
10685 | ret = PTR_ERR(connector_state); | |
10686 | goto fail; | |
10687 | } | |
10688 | ||
edde3617 ML |
10689 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10690 | if (ret) | |
10691 | goto fail; | |
944b0c76 | 10692 | |
4be07317 ACO |
10693 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10694 | if (IS_ERR(crtc_state)) { | |
10695 | ret = PTR_ERR(crtc_state); | |
10696 | goto fail; | |
10697 | } | |
10698 | ||
49d6fa21 | 10699 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10700 | |
6492711d CW |
10701 | if (!mode) |
10702 | mode = &load_detect_mode; | |
79e53945 | 10703 | |
d2dff872 CW |
10704 | /* We need a framebuffer large enough to accommodate all accesses |
10705 | * that the plane may generate whilst we perform load detection. | |
10706 | * We can not rely on the fbcon either being present (we get called | |
10707 | * during its initialisation to detect all boot displays, or it may | |
10708 | * not even exist) or that it is large enough to satisfy the | |
10709 | * requested mode. | |
10710 | */ | |
94352cf9 DV |
10711 | fb = mode_fits_in_fbdev(dev, mode); |
10712 | if (fb == NULL) { | |
d2dff872 | 10713 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10714 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10715 | } else |
10716 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10717 | if (IS_ERR(fb)) { |
d2dff872 | 10718 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10719 | goto fail; |
79e53945 | 10720 | } |
79e53945 | 10721 | |
d3a40d1b ACO |
10722 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10723 | if (ret) | |
10724 | goto fail; | |
10725 | ||
edde3617 ML |
10726 | drm_framebuffer_unreference(fb); |
10727 | ||
10728 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10729 | if (ret) | |
10730 | goto fail; | |
10731 | ||
10732 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10733 | if (!ret) | |
10734 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10735 | if (!ret) | |
10736 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10737 | if (ret) { | |
10738 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10739 | goto fail; | |
10740 | } | |
8c7b5ccb | 10741 | |
3ba86073 ML |
10742 | ret = drm_atomic_commit(state); |
10743 | if (ret) { | |
6492711d | 10744 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10745 | goto fail; |
79e53945 | 10746 | } |
edde3617 ML |
10747 | |
10748 | old->restore_state = restore_state; | |
7173188d | 10749 | |
79e53945 | 10750 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10751 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10752 | return true; |
412b61d8 | 10753 | |
ad3c558f | 10754 | fail: |
e5d958ef | 10755 | drm_atomic_state_free(state); |
edde3617 ML |
10756 | drm_atomic_state_free(restore_state); |
10757 | restore_state = state = NULL; | |
83a57153 | 10758 | |
51fd371b RC |
10759 | if (ret == -EDEADLK) { |
10760 | drm_modeset_backoff(ctx); | |
10761 | goto retry; | |
10762 | } | |
10763 | ||
412b61d8 | 10764 | return false; |
79e53945 JB |
10765 | } |
10766 | ||
d2434ab7 | 10767 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10768 | struct intel_load_detect_pipe *old, |
10769 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10770 | { |
d2434ab7 DV |
10771 | struct intel_encoder *intel_encoder = |
10772 | intel_attached_encoder(connector); | |
4ef69c7a | 10773 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10774 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10775 | int ret; |
79e53945 | 10776 | |
d2dff872 | 10777 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10778 | connector->base.id, connector->name, |
8e329a03 | 10779 | encoder->base.id, encoder->name); |
d2dff872 | 10780 | |
edde3617 | 10781 | if (!state) |
0622a53c | 10782 | return; |
79e53945 | 10783 | |
edde3617 ML |
10784 | ret = drm_atomic_commit(state); |
10785 | if (ret) { | |
10786 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10787 | drm_atomic_state_free(state); | |
10788 | } | |
79e53945 JB |
10789 | } |
10790 | ||
da4a1efa | 10791 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10792 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10793 | { |
10794 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10795 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10796 | ||
10797 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10798 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10799 | else if (HAS_PCH_SPLIT(dev)) |
10800 | return 120000; | |
10801 | else if (!IS_GEN2(dev)) | |
10802 | return 96000; | |
10803 | else | |
10804 | return 48000; | |
10805 | } | |
10806 | ||
79e53945 | 10807 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10808 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10809 | struct intel_crtc_state *pipe_config) |
79e53945 | 10810 | { |
f1f644dc | 10811 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10812 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10813 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10814 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10815 | u32 fp; |
9e2c8475 | 10816 | struct dpll clock; |
dccbea3b | 10817 | int port_clock; |
da4a1efa | 10818 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10819 | |
10820 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10821 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10822 | else |
293623f7 | 10823 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10824 | |
10825 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10826 | if (IS_PINEVIEW(dev)) { |
10827 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10828 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10829 | } else { |
10830 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10831 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10832 | } | |
10833 | ||
a6c45cf0 | 10834 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10835 | if (IS_PINEVIEW(dev)) |
10836 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10837 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10838 | else |
10839 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10840 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10841 | ||
10842 | switch (dpll & DPLL_MODE_MASK) { | |
10843 | case DPLLB_MODE_DAC_SERIAL: | |
10844 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10845 | 5 : 10; | |
10846 | break; | |
10847 | case DPLLB_MODE_LVDS: | |
10848 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10849 | 7 : 14; | |
10850 | break; | |
10851 | default: | |
28c97730 | 10852 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10853 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10854 | return; |
79e53945 JB |
10855 | } |
10856 | ||
ac58c3f0 | 10857 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10858 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10859 | else |
dccbea3b | 10860 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10861 | } else { |
0fb58223 | 10862 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10863 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10864 | |
10865 | if (is_lvds) { | |
10866 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10867 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10868 | |
10869 | if (lvds & LVDS_CLKB_POWER_UP) | |
10870 | clock.p2 = 7; | |
10871 | else | |
10872 | clock.p2 = 14; | |
79e53945 JB |
10873 | } else { |
10874 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10875 | clock.p1 = 2; | |
10876 | else { | |
10877 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10878 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10879 | } | |
10880 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10881 | clock.p2 = 4; | |
10882 | else | |
10883 | clock.p2 = 2; | |
79e53945 | 10884 | } |
da4a1efa | 10885 | |
dccbea3b | 10886 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10887 | } |
10888 | ||
18442d08 VS |
10889 | /* |
10890 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10891 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10892 | * encoder's get_config() function. |
10893 | */ | |
dccbea3b | 10894 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10895 | } |
10896 | ||
6878da05 VS |
10897 | int intel_dotclock_calculate(int link_freq, |
10898 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10899 | { |
f1f644dc JB |
10900 | /* |
10901 | * The calculation for the data clock is: | |
1041a02f | 10902 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10903 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10904 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10905 | * |
10906 | * and the link clock is simpler: | |
1041a02f | 10907 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10908 | */ |
10909 | ||
6878da05 VS |
10910 | if (!m_n->link_n) |
10911 | return 0; | |
f1f644dc | 10912 | |
6878da05 VS |
10913 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10914 | } | |
f1f644dc | 10915 | |
18442d08 | 10916 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10917 | struct intel_crtc_state *pipe_config) |
6878da05 | 10918 | { |
e3b247da | 10919 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10920 | |
18442d08 VS |
10921 | /* read out port_clock from the DPLL */ |
10922 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10923 | |
f1f644dc | 10924 | /* |
e3b247da VS |
10925 | * In case there is an active pipe without active ports, |
10926 | * we may need some idea for the dotclock anyway. | |
10927 | * Calculate one based on the FDI configuration. | |
79e53945 | 10928 | */ |
2d112de7 | 10929 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10930 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10931 | &pipe_config->fdi_m_n); |
79e53945 JB |
10932 | } |
10933 | ||
10934 | /** Returns the currently programmed mode of the given pipe. */ | |
10935 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10936 | struct drm_crtc *crtc) | |
10937 | { | |
548f245b | 10938 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10939 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10940 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10941 | struct drm_display_mode *mode; |
3f36b937 | 10942 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10943 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10944 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10945 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10946 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10947 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10948 | |
10949 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10950 | if (!mode) | |
10951 | return NULL; | |
10952 | ||
3f36b937 TU |
10953 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10954 | if (!pipe_config) { | |
10955 | kfree(mode); | |
10956 | return NULL; | |
10957 | } | |
10958 | ||
f1f644dc JB |
10959 | /* |
10960 | * Construct a pipe_config sufficient for getting the clock info | |
10961 | * back out of crtc_clock_get. | |
10962 | * | |
10963 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10964 | * to use a real value here instead. | |
10965 | */ | |
3f36b937 TU |
10966 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10967 | pipe_config->pixel_multiplier = 1; | |
10968 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10969 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10970 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10971 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10972 | ||
10973 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10974 | mode->hdisplay = (htot & 0xffff) + 1; |
10975 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10976 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10977 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10978 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10979 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10980 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10981 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10982 | ||
10983 | drm_mode_set_name(mode); | |
79e53945 | 10984 | |
3f36b937 TU |
10985 | kfree(pipe_config); |
10986 | ||
79e53945 JB |
10987 | return mode; |
10988 | } | |
10989 | ||
7d993739 | 10990 | void intel_mark_busy(struct drm_i915_private *dev_priv) |
f047e395 | 10991 | { |
f62a0076 CW |
10992 | if (dev_priv->mm.busy) |
10993 | return; | |
10994 | ||
43694d69 | 10995 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10996 | i915_update_gfx_val(dev_priv); |
7d993739 | 10997 | if (INTEL_GEN(dev_priv) >= 6) |
43cf3bf0 | 10998 | gen6_rps_busy(dev_priv); |
f62a0076 | 10999 | dev_priv->mm.busy = true; |
f047e395 CW |
11000 | } |
11001 | ||
7d993739 | 11002 | void intel_mark_idle(struct drm_i915_private *dev_priv) |
652c393a | 11003 | { |
f62a0076 CW |
11004 | if (!dev_priv->mm.busy) |
11005 | return; | |
11006 | ||
11007 | dev_priv->mm.busy = false; | |
11008 | ||
7d993739 TU |
11009 | if (INTEL_GEN(dev_priv) >= 6) |
11010 | gen6_rps_idle(dev_priv); | |
bb4cdd53 | 11011 | |
43694d69 | 11012 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
11013 | } |
11014 | ||
79e53945 JB |
11015 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
11016 | { | |
11017 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 11018 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 11019 | struct intel_flip_work *work; |
67e77c5a | 11020 | |
5e2d7afc | 11021 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
11022 | work = intel_crtc->flip_work; |
11023 | intel_crtc->flip_work = NULL; | |
11024 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 11025 | |
5a21b665 | 11026 | if (work) { |
51cbaf01 ML |
11027 | cancel_work_sync(&work->mmio_work); |
11028 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 11029 | kfree(work); |
67e77c5a | 11030 | } |
79e53945 JB |
11031 | |
11032 | drm_crtc_cleanup(crtc); | |
67e77c5a | 11033 | |
79e53945 JB |
11034 | kfree(intel_crtc); |
11035 | } | |
11036 | ||
6b95a207 KH |
11037 | static void intel_unpin_work_fn(struct work_struct *__work) |
11038 | { | |
51cbaf01 ML |
11039 | struct intel_flip_work *work = |
11040 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
11041 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
11042 | struct drm_device *dev = crtc->base.dev; | |
11043 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 11044 | |
5a21b665 DV |
11045 | if (is_mmio_work(work)) |
11046 | flush_work(&work->mmio_work); | |
03f476e1 | 11047 | |
5a21b665 DV |
11048 | mutex_lock(&dev->struct_mutex); |
11049 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
11050 | drm_gem_object_unreference(&work->pending_flip_obj->base); | |
143f73b3 | 11051 | |
5a21b665 DV |
11052 | if (work->flip_queued_req) |
11053 | i915_gem_request_assign(&work->flip_queued_req, NULL); | |
11054 | mutex_unlock(&dev->struct_mutex); | |
143f73b3 | 11055 | |
5a21b665 DV |
11056 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
11057 | intel_fbc_post_update(crtc); | |
11058 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 11059 | |
5a21b665 DV |
11060 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11061 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 11062 | |
5a21b665 DV |
11063 | kfree(work); |
11064 | } | |
d9e86c0e | 11065 | |
5a21b665 DV |
11066 | /* Is 'a' after or equal to 'b'? */ |
11067 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11068 | { | |
11069 | return !((a - b) & 0x80000000); | |
11070 | } | |
143f73b3 | 11071 | |
5a21b665 DV |
11072 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
11073 | struct intel_flip_work *work) | |
11074 | { | |
11075 | struct drm_device *dev = crtc->base.dev; | |
11076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11077 | unsigned reset_counter; | |
143f73b3 | 11078 | |
5a21b665 DV |
11079 | reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
11080 | if (crtc->reset_counter != reset_counter) | |
11081 | return true; | |
143f73b3 | 11082 | |
5a21b665 DV |
11083 | /* |
11084 | * The relevant registers doen't exist on pre-ctg. | |
11085 | * As the flip done interrupt doesn't trigger for mmio | |
11086 | * flips on gmch platforms, a flip count check isn't | |
11087 | * really needed there. But since ctg has the registers, | |
11088 | * include it in the check anyway. | |
11089 | */ | |
11090 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11091 | return true; | |
b4a98e57 | 11092 | |
5a21b665 DV |
11093 | /* |
11094 | * BDW signals flip done immediately if the plane | |
11095 | * is disabled, even if the plane enable is already | |
11096 | * armed to occur at the next vblank :( | |
11097 | */ | |
f99d7069 | 11098 | |
5a21b665 DV |
11099 | /* |
11100 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11101 | * used the same base address. In that case the mmio flip might | |
11102 | * have completed, but the CS hasn't even executed the flip yet. | |
11103 | * | |
11104 | * A flip count check isn't enough as the CS might have updated | |
11105 | * the base address just after start of vblank, but before we | |
11106 | * managed to process the interrupt. This means we'd complete the | |
11107 | * CS flip too soon. | |
11108 | * | |
11109 | * Combining both checks should get us a good enough result. It may | |
11110 | * still happen that the CS flip has been executed, but has not | |
11111 | * yet actually completed. But in case the base address is the same | |
11112 | * anyway, we don't really care. | |
11113 | */ | |
11114 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11115 | crtc->flip_work->gtt_offset && | |
11116 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11117 | crtc->flip_work->flip_count); | |
11118 | } | |
b4a98e57 | 11119 | |
5a21b665 DV |
11120 | static bool |
11121 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11122 | struct intel_flip_work *work) | |
11123 | { | |
11124 | /* | |
11125 | * MMIO work completes when vblank is different from | |
11126 | * flip_queued_vblank. | |
11127 | * | |
11128 | * Reset counter value doesn't matter, this is handled by | |
11129 | * i915_wait_request finishing early, so no need to handle | |
11130 | * reset here. | |
11131 | */ | |
11132 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11133 | } |
11134 | ||
51cbaf01 ML |
11135 | |
11136 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11137 | struct intel_flip_work *work) | |
11138 | { | |
11139 | if (!atomic_read(&work->pending)) | |
11140 | return false; | |
11141 | ||
11142 | smp_rmb(); | |
11143 | ||
5a21b665 DV |
11144 | if (is_mmio_work(work)) |
11145 | return __pageflip_finished_mmio(crtc, work); | |
11146 | else | |
11147 | return __pageflip_finished_cs(crtc, work); | |
11148 | } | |
11149 | ||
11150 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11151 | { | |
11152 | struct drm_device *dev = dev_priv->dev; | |
11153 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11154 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11155 | struct intel_flip_work *work; | |
11156 | unsigned long flags; | |
11157 | ||
11158 | /* Ignore early vblank irqs */ | |
11159 | if (!crtc) | |
11160 | return; | |
11161 | ||
51cbaf01 | 11162 | /* |
5a21b665 DV |
11163 | * This is called both by irq handlers and the reset code (to complete |
11164 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11165 | */ |
5a21b665 DV |
11166 | spin_lock_irqsave(&dev->event_lock, flags); |
11167 | work = intel_crtc->flip_work; | |
11168 | ||
11169 | if (work != NULL && | |
11170 | !is_mmio_work(work) && | |
11171 | pageflip_finished(intel_crtc, work)) | |
11172 | page_flip_completed(intel_crtc); | |
11173 | ||
11174 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11175 | } |
11176 | ||
51cbaf01 | 11177 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11178 | { |
91d14251 | 11179 | struct drm_device *dev = dev_priv->dev; |
5251f04e ML |
11180 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11181 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
51cbaf01 | 11182 | struct intel_flip_work *work; |
6b95a207 KH |
11183 | unsigned long flags; |
11184 | ||
5251f04e ML |
11185 | /* Ignore early vblank irqs */ |
11186 | if (!crtc) | |
11187 | return; | |
f326038a DV |
11188 | |
11189 | /* | |
11190 | * This is called both by irq handlers and the reset code (to complete | |
11191 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11192 | */ |
6b95a207 | 11193 | spin_lock_irqsave(&dev->event_lock, flags); |
5a21b665 | 11194 | work = intel_crtc->flip_work; |
5251f04e | 11195 | |
5a21b665 DV |
11196 | if (work != NULL && |
11197 | is_mmio_work(work) && | |
11198 | pageflip_finished(intel_crtc, work)) | |
11199 | page_flip_completed(intel_crtc); | |
5251f04e | 11200 | |
6b95a207 KH |
11201 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11202 | } | |
11203 | ||
5a21b665 DV |
11204 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11205 | struct intel_flip_work *work) | |
84c33a64 | 11206 | { |
5a21b665 | 11207 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11208 | |
5a21b665 DV |
11209 | /* Ensure that the work item is consistent when activating it ... */ |
11210 | smp_mb__before_atomic(); | |
11211 | atomic_set(&work->pending, 1); | |
11212 | } | |
a6747b73 | 11213 | |
5a21b665 DV |
11214 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11215 | struct drm_crtc *crtc, | |
11216 | struct drm_framebuffer *fb, | |
11217 | struct drm_i915_gem_object *obj, | |
11218 | struct drm_i915_gem_request *req, | |
11219 | uint32_t flags) | |
11220 | { | |
11221 | struct intel_engine_cs *engine = req->engine; | |
11222 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11223 | u32 flip_mask; | |
11224 | int ret; | |
143f73b3 | 11225 | |
5a21b665 DV |
11226 | ret = intel_ring_begin(req, 6); |
11227 | if (ret) | |
11228 | return ret; | |
143f73b3 | 11229 | |
5a21b665 DV |
11230 | /* Can't queue multiple flips, so wait for the previous |
11231 | * one to finish before executing the next. | |
11232 | */ | |
11233 | if (intel_crtc->plane) | |
11234 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11235 | else | |
11236 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
11237 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); | |
11238 | intel_ring_emit(engine, MI_NOOP); | |
11239 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
11240 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11241 | intel_ring_emit(engine, fb->pitches[0]); | |
11242 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
11243 | intel_ring_emit(engine, 0); /* aux display base address, unused */ | |
143f73b3 | 11244 | |
5a21b665 DV |
11245 | return 0; |
11246 | } | |
84c33a64 | 11247 | |
5a21b665 DV |
11248 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11249 | struct drm_crtc *crtc, | |
11250 | struct drm_framebuffer *fb, | |
11251 | struct drm_i915_gem_object *obj, | |
11252 | struct drm_i915_gem_request *req, | |
11253 | uint32_t flags) | |
11254 | { | |
11255 | struct intel_engine_cs *engine = req->engine; | |
11256 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11257 | u32 flip_mask; | |
11258 | int ret; | |
d55dbd06 | 11259 | |
5a21b665 DV |
11260 | ret = intel_ring_begin(req, 6); |
11261 | if (ret) | |
11262 | return ret; | |
d55dbd06 | 11263 | |
5a21b665 DV |
11264 | if (intel_crtc->plane) |
11265 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11266 | else | |
11267 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
11268 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); | |
11269 | intel_ring_emit(engine, MI_NOOP); | |
11270 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | | |
11271 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11272 | intel_ring_emit(engine, fb->pitches[0]); | |
11273 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
11274 | intel_ring_emit(engine, MI_NOOP); | |
fd8e058a | 11275 | |
5a21b665 DV |
11276 | return 0; |
11277 | } | |
84c33a64 | 11278 | |
5a21b665 DV |
11279 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11280 | struct drm_crtc *crtc, | |
11281 | struct drm_framebuffer *fb, | |
11282 | struct drm_i915_gem_object *obj, | |
11283 | struct drm_i915_gem_request *req, | |
11284 | uint32_t flags) | |
11285 | { | |
11286 | struct intel_engine_cs *engine = req->engine; | |
11287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11288 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11289 | uint32_t pf, pipesrc; | |
11290 | int ret; | |
143f73b3 | 11291 | |
5a21b665 DV |
11292 | ret = intel_ring_begin(req, 4); |
11293 | if (ret) | |
11294 | return ret; | |
143f73b3 | 11295 | |
5a21b665 DV |
11296 | /* i965+ uses the linear or tiled offsets from the |
11297 | * Display Registers (which do not change across a page-flip) | |
11298 | * so we need only reprogram the base address. | |
11299 | */ | |
11300 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
11301 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11302 | intel_ring_emit(engine, fb->pitches[0]); | |
11303 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset | | |
11304 | obj->tiling_mode); | |
11305 | ||
11306 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11307 | * untested on non-native modes, so ignore it for now. | |
11308 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11309 | */ | |
11310 | pf = 0; | |
11311 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
11312 | intel_ring_emit(engine, pf | pipesrc); | |
143f73b3 | 11313 | |
5a21b665 | 11314 | return 0; |
8c9f3aaf JB |
11315 | } |
11316 | ||
5a21b665 DV |
11317 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11318 | struct drm_crtc *crtc, | |
11319 | struct drm_framebuffer *fb, | |
11320 | struct drm_i915_gem_object *obj, | |
11321 | struct drm_i915_gem_request *req, | |
11322 | uint32_t flags) | |
da20eabd | 11323 | { |
5a21b665 DV |
11324 | struct intel_engine_cs *engine = req->engine; |
11325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11326 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11327 | uint32_t pf, pipesrc; | |
11328 | int ret; | |
d21fbe87 | 11329 | |
5a21b665 DV |
11330 | ret = intel_ring_begin(req, 4); |
11331 | if (ret) | |
11332 | return ret; | |
92826fcd | 11333 | |
5a21b665 DV |
11334 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
11335 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11336 | intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); | |
11337 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
92826fcd | 11338 | |
5a21b665 DV |
11339 | /* Contrary to the suggestions in the documentation, |
11340 | * "Enable Panel Fitter" does not seem to be required when page | |
11341 | * flipping with a non-native mode, and worse causes a normal | |
11342 | * modeset to fail. | |
11343 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11344 | */ | |
11345 | pf = 0; | |
11346 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
11347 | intel_ring_emit(engine, pf | pipesrc); | |
7809e5ae | 11348 | |
5a21b665 | 11349 | return 0; |
7809e5ae MR |
11350 | } |
11351 | ||
5a21b665 DV |
11352 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11353 | struct drm_crtc *crtc, | |
11354 | struct drm_framebuffer *fb, | |
11355 | struct drm_i915_gem_object *obj, | |
11356 | struct drm_i915_gem_request *req, | |
11357 | uint32_t flags) | |
d21fbe87 | 11358 | { |
5a21b665 DV |
11359 | struct intel_engine_cs *engine = req->engine; |
11360 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11361 | uint32_t plane_bit = 0; | |
11362 | int len, ret; | |
d21fbe87 | 11363 | |
5a21b665 DV |
11364 | switch (intel_crtc->plane) { |
11365 | case PLANE_A: | |
11366 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11367 | break; | |
11368 | case PLANE_B: | |
11369 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11370 | break; | |
11371 | case PLANE_C: | |
11372 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11373 | break; | |
11374 | default: | |
11375 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11376 | return -ENODEV; | |
11377 | } | |
11378 | ||
11379 | len = 4; | |
11380 | if (engine->id == RCS) { | |
11381 | len += 6; | |
11382 | /* | |
11383 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11384 | * 48bits addresses, and we need a NOOP for the batch size to | |
11385 | * stay even. | |
11386 | */ | |
11387 | if (IS_GEN8(dev)) | |
11388 | len += 2; | |
11389 | } | |
11390 | ||
11391 | /* | |
11392 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11393 | * "The full packet must be contained within the same cache line." | |
11394 | * | |
11395 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11396 | * cacheline, if we ever start emitting more commands before | |
11397 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11398 | * then do the cacheline alignment, and finally emit the | |
11399 | * MI_DISPLAY_FLIP. | |
11400 | */ | |
11401 | ret = intel_ring_cacheline_align(req); | |
11402 | if (ret) | |
11403 | return ret; | |
11404 | ||
11405 | ret = intel_ring_begin(req, len); | |
11406 | if (ret) | |
11407 | return ret; | |
11408 | ||
11409 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11410 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11411 | * more than one flip event at any time (or ensure that one flip message | |
11412 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11413 | * Experimentation says that BCS works despite DERRMR masking all | |
11414 | * flip-done completion events and that unmasking all planes at once | |
11415 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11416 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11417 | */ | |
11418 | if (engine->id == RCS) { | |
11419 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
11420 | intel_ring_emit_reg(engine, DERRMR); | |
11421 | intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11422 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11423 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
11424 | if (IS_GEN8(dev)) | |
11425 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 | | |
11426 | MI_SRM_LRM_GLOBAL_GTT); | |
11427 | else | |
11428 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM | | |
11429 | MI_SRM_LRM_GLOBAL_GTT); | |
11430 | intel_ring_emit_reg(engine, DERRMR); | |
11431 | intel_ring_emit(engine, engine->scratch.gtt_offset + 256); | |
11432 | if (IS_GEN8(dev)) { | |
11433 | intel_ring_emit(engine, 0); | |
11434 | intel_ring_emit(engine, MI_NOOP); | |
11435 | } | |
11436 | } | |
11437 | ||
11438 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); | |
11439 | intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); | |
11440 | intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset); | |
11441 | intel_ring_emit(engine, (MI_NOOP)); | |
11442 | ||
11443 | return 0; | |
11444 | } | |
11445 | ||
11446 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11447 | struct drm_i915_gem_object *obj) | |
11448 | { | |
c37efb99 CW |
11449 | struct reservation_object *resv; |
11450 | ||
5a21b665 DV |
11451 | /* |
11452 | * This is not being used for older platforms, because | |
11453 | * non-availability of flip done interrupt forces us to use | |
11454 | * CS flips. Older platforms derive flip done using some clever | |
11455 | * tricks involving the flip_pending status bits and vblank irqs. | |
11456 | * So using MMIO flips there would disrupt this mechanism. | |
11457 | */ | |
11458 | ||
11459 | if (engine == NULL) | |
11460 | return true; | |
11461 | ||
11462 | if (INTEL_GEN(engine->i915) < 5) | |
11463 | return false; | |
11464 | ||
11465 | if (i915.use_mmio_flip < 0) | |
11466 | return false; | |
11467 | else if (i915.use_mmio_flip > 0) | |
11468 | return true; | |
11469 | else if (i915.enable_execlists) | |
11470 | return true; | |
c37efb99 CW |
11471 | |
11472 | resv = i915_gem_object_get_dmabuf_resv(obj); | |
11473 | if (resv && !reservation_object_test_signaled_rcu(resv, false)) | |
5a21b665 | 11474 | return true; |
c37efb99 CW |
11475 | |
11476 | return engine != i915_gem_request_get_engine(obj->last_write_req); | |
5a21b665 DV |
11477 | } |
11478 | ||
11479 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11480 | unsigned int rotation, | |
11481 | struct intel_flip_work *work) | |
11482 | { | |
11483 | struct drm_device *dev = intel_crtc->base.dev; | |
11484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11485 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
11486 | const enum pipe pipe = intel_crtc->pipe; | |
11487 | u32 ctl, stride, tile_height; | |
11488 | ||
11489 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11490 | ctl &= ~PLANE_CTL_TILED_MASK; | |
11491 | switch (fb->modifier[0]) { | |
11492 | case DRM_FORMAT_MOD_NONE: | |
11493 | break; | |
11494 | case I915_FORMAT_MOD_X_TILED: | |
11495 | ctl |= PLANE_CTL_TILED_X; | |
11496 | break; | |
11497 | case I915_FORMAT_MOD_Y_TILED: | |
11498 | ctl |= PLANE_CTL_TILED_Y; | |
11499 | break; | |
11500 | case I915_FORMAT_MOD_Yf_TILED: | |
11501 | ctl |= PLANE_CTL_TILED_YF; | |
11502 | break; | |
11503 | default: | |
11504 | MISSING_CASE(fb->modifier[0]); | |
11505 | } | |
11506 | ||
11507 | /* | |
11508 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11509 | * linear buffers or in number of tiles for tiled buffers. | |
11510 | */ | |
11511 | if (intel_rotation_90_or_270(rotation)) { | |
11512 | /* stride = Surface height in tiles */ | |
11513 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); | |
11514 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
11515 | } else { | |
11516 | stride = fb->pitches[0] / | |
11517 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
11518 | fb->pixel_format); | |
11519 | } | |
11520 | ||
11521 | /* | |
11522 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11523 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11524 | */ | |
11525 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11526 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11527 | ||
11528 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
11529 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11530 | } | |
11531 | ||
11532 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11533 | struct intel_flip_work *work) | |
11534 | { | |
11535 | struct drm_device *dev = intel_crtc->base.dev; | |
11536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11537 | struct intel_framebuffer *intel_fb = | |
11538 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11539 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11540 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); | |
11541 | u32 dspcntr; | |
11542 | ||
11543 | dspcntr = I915_READ(reg); | |
11544 | ||
11545 | if (obj->tiling_mode != I915_TILING_NONE) | |
11546 | dspcntr |= DISPPLANE_TILED; | |
11547 | else | |
11548 | dspcntr &= ~DISPPLANE_TILED; | |
11549 | ||
11550 | I915_WRITE(reg, dspcntr); | |
11551 | ||
11552 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
11553 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
11554 | } | |
11555 | ||
11556 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
11557 | { | |
11558 | struct intel_flip_work *work = | |
11559 | container_of(w, struct intel_flip_work, mmio_work); | |
11560 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
11561 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
11562 | struct intel_framebuffer *intel_fb = | |
11563 | to_intel_framebuffer(crtc->base.primary->fb); | |
11564 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
c37efb99 | 11565 | struct reservation_object *resv; |
5a21b665 DV |
11566 | |
11567 | if (work->flip_queued_req) | |
11568 | WARN_ON(__i915_wait_request(work->flip_queued_req, | |
11569 | false, NULL, | |
11570 | &dev_priv->rps.mmioflips)); | |
11571 | ||
11572 | /* For framebuffer backed by dmabuf, wait for fence */ | |
c37efb99 CW |
11573 | resv = i915_gem_object_get_dmabuf_resv(obj); |
11574 | if (resv) | |
11575 | WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false, | |
5a21b665 DV |
11576 | MAX_SCHEDULE_TIMEOUT) < 0); |
11577 | ||
11578 | intel_pipe_update_start(crtc); | |
11579 | ||
11580 | if (INTEL_GEN(dev_priv) >= 9) | |
11581 | skl_do_mmio_flip(crtc, work->rotation, work); | |
11582 | else | |
11583 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11584 | ilk_do_mmio_flip(crtc, work); | |
11585 | ||
11586 | intel_pipe_update_end(crtc, work); | |
11587 | } | |
11588 | ||
11589 | static int intel_default_queue_flip(struct drm_device *dev, | |
11590 | struct drm_crtc *crtc, | |
11591 | struct drm_framebuffer *fb, | |
11592 | struct drm_i915_gem_object *obj, | |
11593 | struct drm_i915_gem_request *req, | |
11594 | uint32_t flags) | |
11595 | { | |
11596 | return -ENODEV; | |
11597 | } | |
11598 | ||
11599 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
11600 | struct intel_crtc *intel_crtc, | |
11601 | struct intel_flip_work *work) | |
11602 | { | |
11603 | u32 addr, vblank; | |
11604 | ||
11605 | if (!atomic_read(&work->pending)) | |
11606 | return false; | |
11607 | ||
11608 | smp_rmb(); | |
11609 | ||
11610 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
11611 | if (work->flip_ready_vblank == 0) { | |
11612 | if (work->flip_queued_req && | |
11613 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
11614 | return false; | |
11615 | ||
11616 | work->flip_ready_vblank = vblank; | |
11617 | } | |
11618 | ||
11619 | if (vblank - work->flip_ready_vblank < 3) | |
11620 | return false; | |
11621 | ||
11622 | /* Potential stall - if we see that the flip has happened, | |
11623 | * assume a missed interrupt. */ | |
11624 | if (INTEL_GEN(dev_priv) >= 4) | |
11625 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11626 | else | |
11627 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11628 | ||
11629 | /* There is a potential issue here with a false positive after a flip | |
11630 | * to the same address. We could address this by checking for a | |
11631 | * non-incrementing frame counter. | |
11632 | */ | |
11633 | return addr == work->gtt_offset; | |
11634 | } | |
11635 | ||
11636 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
11637 | { | |
11638 | struct drm_device *dev = dev_priv->dev; | |
11639 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11640 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11641 | struct intel_flip_work *work; | |
11642 | ||
11643 | WARN_ON(!in_interrupt()); | |
11644 | ||
11645 | if (crtc == NULL) | |
11646 | return; | |
11647 | ||
11648 | spin_lock(&dev->event_lock); | |
11649 | work = intel_crtc->flip_work; | |
11650 | ||
11651 | if (work != NULL && !is_mmio_work(work) && | |
11652 | __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) { | |
11653 | WARN_ONCE(1, | |
11654 | "Kicking stuck page flip: queued at %d, now %d\n", | |
11655 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc)); | |
11656 | page_flip_completed(intel_crtc); | |
11657 | work = NULL; | |
11658 | } | |
11659 | ||
11660 | if (work != NULL && !is_mmio_work(work) && | |
11661 | intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1) | |
11662 | intel_queue_rps_boost_for_request(work->flip_queued_req); | |
11663 | spin_unlock(&dev->event_lock); | |
11664 | } | |
11665 | ||
11666 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
11667 | struct drm_framebuffer *fb, | |
11668 | struct drm_pending_vblank_event *event, | |
11669 | uint32_t page_flip_flags) | |
11670 | { | |
11671 | struct drm_device *dev = crtc->dev; | |
11672 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11673 | struct drm_framebuffer *old_fb = crtc->primary->fb; | |
11674 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11675 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11676 | struct drm_plane *primary = crtc->primary; | |
11677 | enum pipe pipe = intel_crtc->pipe; | |
11678 | struct intel_flip_work *work; | |
11679 | struct intel_engine_cs *engine; | |
11680 | bool mmio_flip; | |
11681 | struct drm_i915_gem_request *request = NULL; | |
11682 | int ret; | |
11683 | ||
11684 | /* | |
11685 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11686 | * check to be safe. In the future we may enable pageflipping from | |
11687 | * a disabled primary plane. | |
11688 | */ | |
11689 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11690 | return -EBUSY; | |
11691 | ||
11692 | /* Can't change pixel format via MI display flips. */ | |
11693 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
11694 | return -EINVAL; | |
11695 | ||
11696 | /* | |
11697 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11698 | * Note that pitch changes could also affect these register. | |
11699 | */ | |
11700 | if (INTEL_INFO(dev)->gen > 3 && | |
11701 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || | |
11702 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
11703 | return -EINVAL; | |
11704 | ||
11705 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
11706 | goto out_hang; | |
11707 | ||
11708 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
11709 | if (work == NULL) | |
11710 | return -ENOMEM; | |
11711 | ||
11712 | work->event = event; | |
11713 | work->crtc = crtc; | |
11714 | work->old_fb = old_fb; | |
11715 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
11716 | ||
11717 | ret = drm_crtc_vblank_get(crtc); | |
11718 | if (ret) | |
11719 | goto free_work; | |
11720 | ||
11721 | /* We borrow the event spin lock for protecting flip_work */ | |
11722 | spin_lock_irq(&dev->event_lock); | |
11723 | if (intel_crtc->flip_work) { | |
11724 | /* Before declaring the flip queue wedged, check if | |
11725 | * the hardware completed the operation behind our backs. | |
11726 | */ | |
11727 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
11728 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11729 | page_flip_completed(intel_crtc); | |
11730 | } else { | |
11731 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
11732 | spin_unlock_irq(&dev->event_lock); | |
11733 | ||
11734 | drm_crtc_vblank_put(crtc); | |
11735 | kfree(work); | |
11736 | return -EBUSY; | |
11737 | } | |
11738 | } | |
11739 | intel_crtc->flip_work = work; | |
11740 | spin_unlock_irq(&dev->event_lock); | |
11741 | ||
11742 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
11743 | flush_workqueue(dev_priv->wq); | |
11744 | ||
11745 | /* Reference the objects for the scheduled work. */ | |
11746 | drm_framebuffer_reference(work->old_fb); | |
11747 | drm_gem_object_reference(&obj->base); | |
11748 | ||
11749 | crtc->primary->fb = fb; | |
11750 | update_state_fb(crtc->primary); | |
faf68d92 ML |
11751 | |
11752 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
11753 | to_intel_plane_state(primary->state)); | |
5a21b665 DV |
11754 | |
11755 | work->pending_flip_obj = obj; | |
11756 | ||
11757 | ret = i915_mutex_lock_interruptible(dev); | |
11758 | if (ret) | |
11759 | goto cleanup; | |
11760 | ||
11761 | intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); | |
11762 | if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) { | |
11763 | ret = -EIO; | |
11764 | goto cleanup; | |
11765 | } | |
11766 | ||
11767 | atomic_inc(&intel_crtc->unpin_work_count); | |
11768 | ||
11769 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
11770 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; | |
11771 | ||
11772 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
11773 | engine = &dev_priv->engine[BCS]; | |
11774 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) | |
11775 | /* vlv: DISPLAY_FLIP fails to change tiling */ | |
11776 | engine = NULL; | |
11777 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { | |
11778 | engine = &dev_priv->engine[BCS]; | |
11779 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
11780 | engine = i915_gem_request_get_engine(obj->last_write_req); | |
11781 | if (engine == NULL || engine->id != RCS) | |
11782 | engine = &dev_priv->engine[BCS]; | |
11783 | } else { | |
11784 | engine = &dev_priv->engine[RCS]; | |
11785 | } | |
11786 | ||
11787 | mmio_flip = use_mmio_flip(engine, obj); | |
11788 | ||
11789 | /* When using CS flips, we want to emit semaphores between rings. | |
11790 | * However, when using mmio flips we will create a task to do the | |
11791 | * synchronisation, so all we want here is to pin the framebuffer | |
11792 | * into the display plane and skip any waits. | |
11793 | */ | |
11794 | if (!mmio_flip) { | |
11795 | ret = i915_gem_object_sync(obj, engine, &request); | |
11796 | if (!ret && !request) { | |
11797 | request = i915_gem_request_alloc(engine, NULL); | |
11798 | ret = PTR_ERR_OR_ZERO(request); | |
11799 | } | |
11800 | ||
11801 | if (ret) | |
11802 | goto cleanup_pending; | |
11803 | } | |
11804 | ||
11805 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
11806 | if (ret) | |
11807 | goto cleanup_pending; | |
11808 | ||
11809 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), | |
11810 | obj, 0); | |
11811 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
11812 | work->rotation = crtc->primary->state->rotation; | |
11813 | ||
11814 | if (mmio_flip) { | |
11815 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
11816 | ||
11817 | i915_gem_request_assign(&work->flip_queued_req, | |
11818 | obj->last_write_req); | |
11819 | ||
11820 | schedule_work(&work->mmio_work); | |
11821 | } else { | |
11822 | i915_gem_request_assign(&work->flip_queued_req, request); | |
11823 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
11824 | page_flip_flags); | |
11825 | if (ret) | |
11826 | goto cleanup_unpin; | |
11827 | ||
11828 | intel_mark_page_flip_active(intel_crtc, work); | |
11829 | ||
11830 | i915_add_request_no_flush(request); | |
11831 | } | |
11832 | ||
11833 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, | |
11834 | to_intel_plane(primary)->frontbuffer_bit); | |
11835 | mutex_unlock(&dev->struct_mutex); | |
11836 | ||
11837 | intel_frontbuffer_flip_prepare(dev, | |
11838 | to_intel_plane(primary)->frontbuffer_bit); | |
11839 | ||
11840 | trace_i915_flip_request(intel_crtc->plane, obj); | |
11841 | ||
11842 | return 0; | |
11843 | ||
11844 | cleanup_unpin: | |
11845 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
11846 | cleanup_pending: | |
11847 | if (!IS_ERR_OR_NULL(request)) | |
11848 | i915_add_request_no_flush(request); | |
11849 | atomic_dec(&intel_crtc->unpin_work_count); | |
11850 | mutex_unlock(&dev->struct_mutex); | |
11851 | cleanup: | |
11852 | crtc->primary->fb = old_fb; | |
11853 | update_state_fb(crtc->primary); | |
11854 | ||
11855 | drm_gem_object_unreference_unlocked(&obj->base); | |
11856 | drm_framebuffer_unreference(work->old_fb); | |
11857 | ||
11858 | spin_lock_irq(&dev->event_lock); | |
11859 | intel_crtc->flip_work = NULL; | |
11860 | spin_unlock_irq(&dev->event_lock); | |
11861 | ||
11862 | drm_crtc_vblank_put(crtc); | |
11863 | free_work: | |
11864 | kfree(work); | |
11865 | ||
11866 | if (ret == -EIO) { | |
11867 | struct drm_atomic_state *state; | |
11868 | struct drm_plane_state *plane_state; | |
11869 | ||
11870 | out_hang: | |
11871 | state = drm_atomic_state_alloc(dev); | |
11872 | if (!state) | |
11873 | return -ENOMEM; | |
11874 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11875 | ||
11876 | retry: | |
11877 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11878 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11879 | if (!ret) { | |
11880 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11881 | ||
11882 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11883 | if (!ret) | |
11884 | ret = drm_atomic_commit(state); | |
11885 | } | |
11886 | ||
11887 | if (ret == -EDEADLK) { | |
11888 | drm_modeset_backoff(state->acquire_ctx); | |
11889 | drm_atomic_state_clear(state); | |
11890 | goto retry; | |
11891 | } | |
11892 | ||
11893 | if (ret) | |
11894 | drm_atomic_state_free(state); | |
11895 | ||
11896 | if (ret == 0 && event) { | |
11897 | spin_lock_irq(&dev->event_lock); | |
11898 | drm_crtc_send_vblank_event(crtc, event); | |
11899 | spin_unlock_irq(&dev->event_lock); | |
11900 | } | |
11901 | } | |
11902 | return ret; | |
11903 | } | |
11904 | ||
11905 | ||
11906 | /** | |
11907 | * intel_wm_need_update - Check whether watermarks need updating | |
11908 | * @plane: drm plane | |
11909 | * @state: new plane state | |
11910 | * | |
11911 | * Check current plane state versus the new one to determine whether | |
11912 | * watermarks need to be recalculated. | |
11913 | * | |
11914 | * Returns true or false. | |
11915 | */ | |
11916 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11917 | struct drm_plane_state *state) | |
11918 | { | |
11919 | struct intel_plane_state *new = to_intel_plane_state(state); | |
11920 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11921 | ||
11922 | /* Update watermarks on tiling or size changes. */ | |
11923 | if (new->visible != cur->visible) | |
11924 | return true; | |
11925 | ||
11926 | if (!cur->base.fb || !new->base.fb) | |
11927 | return false; | |
11928 | ||
11929 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11930 | cur->base.rotation != new->base.rotation || | |
11931 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || | |
11932 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11933 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11934 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
11935 | return true; | |
11936 | ||
11937 | return false; | |
11938 | } | |
11939 | ||
11940 | static bool needs_scaling(struct intel_plane_state *state) | |
11941 | { | |
11942 | int src_w = drm_rect_width(&state->src) >> 16; | |
11943 | int src_h = drm_rect_height(&state->src) >> 16; | |
11944 | int dst_w = drm_rect_width(&state->dst); | |
11945 | int dst_h = drm_rect_height(&state->dst); | |
11946 | ||
11947 | return (src_w != dst_w || src_h != dst_h); | |
11948 | } | |
d21fbe87 | 11949 | |
da20eabd ML |
11950 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11951 | struct drm_plane_state *plane_state) | |
11952 | { | |
ab1d3a0e | 11953 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11954 | struct drm_crtc *crtc = crtc_state->crtc; |
11955 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11956 | struct drm_plane *plane = plane_state->plane; | |
11957 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11958 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11959 | struct intel_plane_state *old_plane_state = |
11960 | to_intel_plane_state(plane->state); | |
da20eabd ML |
11961 | bool mode_changed = needs_modeset(crtc_state); |
11962 | bool was_crtc_enabled = crtc->state->active; | |
11963 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11964 | bool turn_off, turn_on, visible, was_visible; |
11965 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 11966 | int ret; |
da20eabd ML |
11967 | |
11968 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11969 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11970 | ret = skl_update_scaler_plane( | |
11971 | to_intel_crtc_state(crtc_state), | |
11972 | to_intel_plane_state(plane_state)); | |
11973 | if (ret) | |
11974 | return ret; | |
11975 | } | |
11976 | ||
da20eabd ML |
11977 | was_visible = old_plane_state->visible; |
11978 | visible = to_intel_plane_state(plane_state)->visible; | |
11979 | ||
11980 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11981 | was_visible = false; | |
11982 | ||
35c08f43 ML |
11983 | /* |
11984 | * Visibility is calculated as if the crtc was on, but | |
11985 | * after scaler setup everything depends on it being off | |
11986 | * when the crtc isn't active. | |
f818ffea VS |
11987 | * |
11988 | * FIXME this is wrong for watermarks. Watermarks should also | |
11989 | * be computed as if the pipe would be active. Perhaps move | |
11990 | * per-plane wm computation to the .check_plane() hook, and | |
11991 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
11992 | */ |
11993 | if (!is_crtc_enabled) | |
11994 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11995 | |
11996 | if (!was_visible && !visible) | |
11997 | return 0; | |
11998 | ||
e8861675 ML |
11999 | if (fb != old_plane_state->base.fb) |
12000 | pipe_config->fb_changed = true; | |
12001 | ||
da20eabd ML |
12002 | turn_off = was_visible && (!visible || mode_changed); |
12003 | turn_on = visible && (!was_visible || mode_changed); | |
12004 | ||
72660ce0 | 12005 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
12006 | intel_crtc->base.base.id, |
12007 | intel_crtc->base.name, | |
72660ce0 VS |
12008 | plane->base.id, plane->name, |
12009 | fb ? fb->base.id : -1); | |
da20eabd | 12010 | |
72660ce0 VS |
12011 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
12012 | plane->base.id, plane->name, | |
12013 | was_visible, visible, | |
da20eabd ML |
12014 | turn_off, turn_on, mode_changed); |
12015 | ||
caed361d VS |
12016 | if (turn_on) { |
12017 | pipe_config->update_wm_pre = true; | |
12018 | ||
12019 | /* must disable cxsr around plane enable/disable */ | |
12020 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
12021 | pipe_config->disable_cxsr = true; | |
12022 | } else if (turn_off) { | |
12023 | pipe_config->update_wm_post = true; | |
92826fcd | 12024 | |
852eb00d | 12025 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 12026 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 12027 | pipe_config->disable_cxsr = true; |
852eb00d | 12028 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
12029 | /* FIXME bollocks */ |
12030 | pipe_config->update_wm_pre = true; | |
12031 | pipe_config->update_wm_post = true; | |
852eb00d | 12032 | } |
da20eabd | 12033 | |
ed4a6a7c | 12034 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
12035 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
12036 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
12037 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
12038 | ||
8be6ca85 | 12039 | if (visible || was_visible) |
cd202f69 | 12040 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 12041 | |
31ae71fc ML |
12042 | /* |
12043 | * WaCxSRDisabledForSpriteScaling:ivb | |
12044 | * | |
12045 | * cstate->update_wm was already set above, so this flag will | |
12046 | * take effect when we commit and program watermarks. | |
12047 | */ | |
12048 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
12049 | needs_scaling(to_intel_plane_state(plane_state)) && | |
12050 | !needs_scaling(old_plane_state)) | |
12051 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 12052 | |
da20eabd ML |
12053 | return 0; |
12054 | } | |
12055 | ||
6d3a1ce7 ML |
12056 | static bool encoders_cloneable(const struct intel_encoder *a, |
12057 | const struct intel_encoder *b) | |
12058 | { | |
12059 | /* masks could be asymmetric, so check both ways */ | |
12060 | return a == b || (a->cloneable & (1 << b->type) && | |
12061 | b->cloneable & (1 << a->type)); | |
12062 | } | |
12063 | ||
12064 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12065 | struct intel_crtc *crtc, | |
12066 | struct intel_encoder *encoder) | |
12067 | { | |
12068 | struct intel_encoder *source_encoder; | |
12069 | struct drm_connector *connector; | |
12070 | struct drm_connector_state *connector_state; | |
12071 | int i; | |
12072 | ||
12073 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12074 | if (connector_state->crtc != &crtc->base) | |
12075 | continue; | |
12076 | ||
12077 | source_encoder = | |
12078 | to_intel_encoder(connector_state->best_encoder); | |
12079 | if (!encoders_cloneable(encoder, source_encoder)) | |
12080 | return false; | |
12081 | } | |
12082 | ||
12083 | return true; | |
12084 | } | |
12085 | ||
12086 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
12087 | struct intel_crtc *crtc) | |
12088 | { | |
12089 | struct intel_encoder *encoder; | |
12090 | struct drm_connector *connector; | |
12091 | struct drm_connector_state *connector_state; | |
12092 | int i; | |
12093 | ||
12094 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12095 | if (connector_state->crtc != &crtc->base) | |
12096 | continue; | |
12097 | ||
12098 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12099 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
12100 | return false; | |
12101 | } | |
12102 | ||
12103 | return true; | |
12104 | } | |
12105 | ||
12106 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
12107 | struct drm_crtc_state *crtc_state) | |
12108 | { | |
cf5a15be | 12109 | struct drm_device *dev = crtc->dev; |
ad421372 | 12110 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 12111 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12112 | struct intel_crtc_state *pipe_config = |
12113 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12114 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12115 | int ret; |
6d3a1ce7 ML |
12116 | bool mode_changed = needs_modeset(crtc_state); |
12117 | ||
12118 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
12119 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12120 | return -EINVAL; | |
12121 | } | |
12122 | ||
852eb00d | 12123 | if (mode_changed && !crtc_state->active) |
caed361d | 12124 | pipe_config->update_wm_post = true; |
eddfcbcd | 12125 | |
ad421372 ML |
12126 | if (mode_changed && crtc_state->enable && |
12127 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 12128 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
12129 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12130 | pipe_config); | |
12131 | if (ret) | |
12132 | return ret; | |
12133 | } | |
12134 | ||
82cf435b LL |
12135 | if (crtc_state->color_mgmt_changed) { |
12136 | ret = intel_color_check(crtc, crtc_state); | |
12137 | if (ret) | |
12138 | return ret; | |
12139 | } | |
12140 | ||
e435d6e5 | 12141 | ret = 0; |
86c8bbbe | 12142 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12143 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12144 | if (ret) { |
12145 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12146 | return ret; | |
12147 | } | |
12148 | } | |
12149 | ||
12150 | if (dev_priv->display.compute_intermediate_wm && | |
12151 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12152 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12153 | return 0; | |
12154 | ||
12155 | /* | |
12156 | * Calculate 'intermediate' watermarks that satisfy both the | |
12157 | * old state and the new state. We can program these | |
12158 | * immediately. | |
12159 | */ | |
12160 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12161 | intel_crtc, | |
12162 | pipe_config); | |
12163 | if (ret) { | |
12164 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12165 | return ret; |
ed4a6a7c | 12166 | } |
e3d5457c VS |
12167 | } else if (dev_priv->display.compute_intermediate_wm) { |
12168 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12169 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12170 | } |
12171 | ||
e435d6e5 ML |
12172 | if (INTEL_INFO(dev)->gen >= 9) { |
12173 | if (mode_changed) | |
12174 | ret = skl_update_scaler_crtc(pipe_config); | |
12175 | ||
12176 | if (!ret) | |
12177 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12178 | pipe_config); | |
12179 | } | |
12180 | ||
12181 | return ret; | |
6d3a1ce7 ML |
12182 | } |
12183 | ||
65b38e0d | 12184 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12185 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12186 | .atomic_begin = intel_begin_crtc_commit, |
12187 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12188 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12189 | }; |
12190 | ||
d29b2f9d ACO |
12191 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12192 | { | |
12193 | struct intel_connector *connector; | |
12194 | ||
12195 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12196 | if (connector->base.state->crtc) |
12197 | drm_connector_unreference(&connector->base); | |
12198 | ||
d29b2f9d ACO |
12199 | if (connector->base.encoder) { |
12200 | connector->base.state->best_encoder = | |
12201 | connector->base.encoder; | |
12202 | connector->base.state->crtc = | |
12203 | connector->base.encoder->crtc; | |
8863dc7f DV |
12204 | |
12205 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12206 | } else { |
12207 | connector->base.state->best_encoder = NULL; | |
12208 | connector->base.state->crtc = NULL; | |
12209 | } | |
12210 | } | |
12211 | } | |
12212 | ||
050f7aeb | 12213 | static void |
eba905b2 | 12214 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12215 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12216 | { |
12217 | int bpp = pipe_config->pipe_bpp; | |
12218 | ||
12219 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12220 | connector->base.base.id, | |
c23cc417 | 12221 | connector->base.name); |
050f7aeb DV |
12222 | |
12223 | /* Don't use an invalid EDID bpc value */ | |
12224 | if (connector->base.display_info.bpc && | |
12225 | connector->base.display_info.bpc * 3 < bpp) { | |
12226 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12227 | bpp, connector->base.display_info.bpc*3); | |
12228 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12229 | } | |
12230 | ||
013dd9e0 JN |
12231 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12232 | if (connector->base.display_info.bpc == 0) { | |
12233 | int type = connector->base.connector_type; | |
12234 | int clamp_bpp = 24; | |
12235 | ||
12236 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12237 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12238 | type == DRM_MODE_CONNECTOR_eDP) | |
12239 | clamp_bpp = 18; | |
12240 | ||
12241 | if (bpp > clamp_bpp) { | |
12242 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12243 | bpp, clamp_bpp); | |
12244 | pipe_config->pipe_bpp = clamp_bpp; | |
12245 | } | |
050f7aeb DV |
12246 | } |
12247 | } | |
12248 | ||
4e53c2e0 | 12249 | static int |
050f7aeb | 12250 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12251 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12252 | { |
050f7aeb | 12253 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12254 | struct drm_atomic_state *state; |
da3ced29 ACO |
12255 | struct drm_connector *connector; |
12256 | struct drm_connector_state *connector_state; | |
1486017f | 12257 | int bpp, i; |
4e53c2e0 | 12258 | |
666a4537 | 12259 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12260 | bpp = 10*3; |
d328c9d7 DV |
12261 | else if (INTEL_INFO(dev)->gen >= 5) |
12262 | bpp = 12*3; | |
12263 | else | |
12264 | bpp = 8*3; | |
12265 | ||
4e53c2e0 | 12266 | |
4e53c2e0 DV |
12267 | pipe_config->pipe_bpp = bpp; |
12268 | ||
1486017f ACO |
12269 | state = pipe_config->base.state; |
12270 | ||
4e53c2e0 | 12271 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12272 | for_each_connector_in_state(state, connector, connector_state, i) { |
12273 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12274 | continue; |
12275 | ||
da3ced29 ACO |
12276 | connected_sink_compute_bpp(to_intel_connector(connector), |
12277 | pipe_config); | |
4e53c2e0 DV |
12278 | } |
12279 | ||
12280 | return bpp; | |
12281 | } | |
12282 | ||
644db711 DV |
12283 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12284 | { | |
12285 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12286 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12287 | mode->crtc_clock, |
644db711 DV |
12288 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12289 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12290 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12291 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12292 | } | |
12293 | ||
c0b03411 | 12294 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12295 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12296 | const char *context) |
12297 | { | |
6a60cd87 CK |
12298 | struct drm_device *dev = crtc->base.dev; |
12299 | struct drm_plane *plane; | |
12300 | struct intel_plane *intel_plane; | |
12301 | struct intel_plane_state *state; | |
12302 | struct drm_framebuffer *fb; | |
12303 | ||
78108b7c VS |
12304 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n", |
12305 | crtc->base.base.id, crtc->base.name, | |
6a60cd87 | 12306 | context, pipe_config, pipe_name(crtc->pipe)); |
c0b03411 | 12307 | |
da205630 | 12308 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12309 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12310 | pipe_config->pipe_bpp, pipe_config->dither); | |
12311 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12312 | pipe_config->has_pch_encoder, | |
12313 | pipe_config->fdi_lanes, | |
12314 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12315 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12316 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12317 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12318 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12319 | pipe_config->lane_count, |
eb14cb74 VS |
12320 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12321 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12322 | pipe_config->dp_m_n.tu); | |
b95af8be | 12323 | |
90a6b7b0 | 12324 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12325 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12326 | pipe_config->lane_count, |
b95af8be VK |
12327 | pipe_config->dp_m2_n2.gmch_m, |
12328 | pipe_config->dp_m2_n2.gmch_n, | |
12329 | pipe_config->dp_m2_n2.link_m, | |
12330 | pipe_config->dp_m2_n2.link_n, | |
12331 | pipe_config->dp_m2_n2.tu); | |
12332 | ||
55072d19 DV |
12333 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12334 | pipe_config->has_audio, | |
12335 | pipe_config->has_infoframe); | |
12336 | ||
c0b03411 | 12337 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12338 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12339 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12340 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12341 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12342 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12343 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12344 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12345 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12346 | crtc->num_scalers, | |
12347 | pipe_config->scaler_state.scaler_users, | |
12348 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12349 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12350 | pipe_config->gmch_pfit.control, | |
12351 | pipe_config->gmch_pfit.pgm_ratios, | |
12352 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12353 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12354 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12355 | pipe_config->pch_pfit.size, |
12356 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12357 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12358 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12359 | |
415ff0f6 | 12360 | if (IS_BROXTON(dev)) { |
05712c15 | 12361 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12362 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12363 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12364 | pipe_config->ddi_pll_sel, |
12365 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12366 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12367 | pipe_config->dpll_hw_state.pll0, |
12368 | pipe_config->dpll_hw_state.pll1, | |
12369 | pipe_config->dpll_hw_state.pll2, | |
12370 | pipe_config->dpll_hw_state.pll3, | |
12371 | pipe_config->dpll_hw_state.pll6, | |
12372 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12373 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12374 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12375 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12376 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12377 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12378 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12379 | pipe_config->ddi_pll_sel, | |
12380 | pipe_config->dpll_hw_state.ctrl1, | |
12381 | pipe_config->dpll_hw_state.cfgcr1, | |
12382 | pipe_config->dpll_hw_state.cfgcr2); | |
12383 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12384 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12385 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12386 | pipe_config->dpll_hw_state.wrpll, |
12387 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12388 | } else { |
12389 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12390 | "fp0: 0x%x, fp1: 0x%x\n", | |
12391 | pipe_config->dpll_hw_state.dpll, | |
12392 | pipe_config->dpll_hw_state.dpll_md, | |
12393 | pipe_config->dpll_hw_state.fp0, | |
12394 | pipe_config->dpll_hw_state.fp1); | |
12395 | } | |
12396 | ||
6a60cd87 CK |
12397 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12398 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12399 | intel_plane = to_intel_plane(plane); | |
12400 | if (intel_plane->pipe != crtc->pipe) | |
12401 | continue; | |
12402 | ||
12403 | state = to_intel_plane_state(plane->state); | |
12404 | fb = state->base.fb; | |
12405 | if (!fb) { | |
1d577e02 VS |
12406 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12407 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12408 | continue; |
12409 | } | |
12410 | ||
1d577e02 VS |
12411 | DRM_DEBUG_KMS("[PLANE:%d:%s] enabled", |
12412 | plane->base.id, plane->name); | |
12413 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s", | |
12414 | fb->base.id, fb->width, fb->height, | |
12415 | drm_get_format_name(fb->pixel_format)); | |
12416 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
12417 | state->scaler_id, | |
12418 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12419 | drm_rect_width(&state->src) >> 16, | |
12420 | drm_rect_height(&state->src) >> 16, | |
12421 | state->dst.x1, state->dst.y1, | |
12422 | drm_rect_width(&state->dst), | |
12423 | drm_rect_height(&state->dst)); | |
6a60cd87 | 12424 | } |
c0b03411 DV |
12425 | } |
12426 | ||
5448a00d | 12427 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12428 | { |
5448a00d | 12429 | struct drm_device *dev = state->dev; |
da3ced29 | 12430 | struct drm_connector *connector; |
00f0b378 VS |
12431 | unsigned int used_ports = 0; |
12432 | ||
12433 | /* | |
12434 | * Walk the connector list instead of the encoder | |
12435 | * list to detect the problem on ddi platforms | |
12436 | * where there's just one encoder per digital port. | |
12437 | */ | |
0bff4858 VS |
12438 | drm_for_each_connector(connector, dev) { |
12439 | struct drm_connector_state *connector_state; | |
12440 | struct intel_encoder *encoder; | |
12441 | ||
12442 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12443 | if (!connector_state) | |
12444 | connector_state = connector->state; | |
12445 | ||
5448a00d | 12446 | if (!connector_state->best_encoder) |
00f0b378 VS |
12447 | continue; |
12448 | ||
5448a00d ACO |
12449 | encoder = to_intel_encoder(connector_state->best_encoder); |
12450 | ||
12451 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12452 | |
12453 | switch (encoder->type) { | |
12454 | unsigned int port_mask; | |
12455 | case INTEL_OUTPUT_UNKNOWN: | |
12456 | if (WARN_ON(!HAS_DDI(dev))) | |
12457 | break; | |
12458 | case INTEL_OUTPUT_DISPLAYPORT: | |
12459 | case INTEL_OUTPUT_HDMI: | |
12460 | case INTEL_OUTPUT_EDP: | |
12461 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12462 | ||
12463 | /* the same port mustn't appear more than once */ | |
12464 | if (used_ports & port_mask) | |
12465 | return false; | |
12466 | ||
12467 | used_ports |= port_mask; | |
12468 | default: | |
12469 | break; | |
12470 | } | |
12471 | } | |
12472 | ||
12473 | return true; | |
12474 | } | |
12475 | ||
83a57153 ACO |
12476 | static void |
12477 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12478 | { | |
12479 | struct drm_crtc_state tmp_state; | |
663a3640 | 12480 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12481 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12482 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12483 | uint32_t ddi_pll_sel; |
c4e2d043 | 12484 | bool force_thru; |
83a57153 | 12485 | |
7546a384 ACO |
12486 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12487 | * kzalloc'd. Code that depends on any field being zero should be | |
12488 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12489 | * only fields that are know to not cause problems are preserved. */ | |
12490 | ||
83a57153 | 12491 | tmp_state = crtc_state->base; |
663a3640 | 12492 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12493 | shared_dpll = crtc_state->shared_dpll; |
12494 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12495 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12496 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12497 | |
83a57153 | 12498 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12499 | |
83a57153 | 12500 | crtc_state->base = tmp_state; |
663a3640 | 12501 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12502 | crtc_state->shared_dpll = shared_dpll; |
12503 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12504 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12505 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12506 | } |
12507 | ||
548ee15b | 12508 | static int |
b8cecdf5 | 12509 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12510 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12511 | { |
b359283a | 12512 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12513 | struct intel_encoder *encoder; |
da3ced29 | 12514 | struct drm_connector *connector; |
0b901879 | 12515 | struct drm_connector_state *connector_state; |
d328c9d7 | 12516 | int base_bpp, ret = -EINVAL; |
0b901879 | 12517 | int i; |
e29c22c0 | 12518 | bool retry = true; |
ee7b9f93 | 12519 | |
83a57153 | 12520 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12521 | |
e143a21c DV |
12522 | pipe_config->cpu_transcoder = |
12523 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12524 | |
2960bc9c ID |
12525 | /* |
12526 | * Sanitize sync polarity flags based on requested ones. If neither | |
12527 | * positive or negative polarity is requested, treat this as meaning | |
12528 | * negative polarity. | |
12529 | */ | |
2d112de7 | 12530 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12531 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12532 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12533 | |
2d112de7 | 12534 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12535 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12536 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12537 | |
d328c9d7 DV |
12538 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12539 | pipe_config); | |
12540 | if (base_bpp < 0) | |
4e53c2e0 DV |
12541 | goto fail; |
12542 | ||
e41a56be VS |
12543 | /* |
12544 | * Determine the real pipe dimensions. Note that stereo modes can | |
12545 | * increase the actual pipe size due to the frame doubling and | |
12546 | * insertion of additional space for blanks between the frame. This | |
12547 | * is stored in the crtc timings. We use the requested mode to do this | |
12548 | * computation to clearly distinguish it from the adjusted mode, which | |
12549 | * can be changed by the connectors in the below retry loop. | |
12550 | */ | |
2d112de7 | 12551 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12552 | &pipe_config->pipe_src_w, |
12553 | &pipe_config->pipe_src_h); | |
e41a56be | 12554 | |
e29c22c0 | 12555 | encoder_retry: |
ef1b460d | 12556 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12557 | pipe_config->port_clock = 0; |
ef1b460d | 12558 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12559 | |
135c81b8 | 12560 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12561 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12562 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12563 | |
7758a113 DV |
12564 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12565 | * adjust it according to limitations or connector properties, and also | |
12566 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12567 | */ |
da3ced29 | 12568 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12569 | if (connector_state->crtc != crtc) |
7758a113 | 12570 | continue; |
7ae89233 | 12571 | |
0b901879 ACO |
12572 | encoder = to_intel_encoder(connector_state->best_encoder); |
12573 | ||
efea6e8e DV |
12574 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12575 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12576 | goto fail; |
12577 | } | |
ee7b9f93 | 12578 | } |
47f1c6c9 | 12579 | |
ff9a6750 DV |
12580 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12581 | * done afterwards in case the encoder adjusts the mode. */ | |
12582 | if (!pipe_config->port_clock) | |
2d112de7 | 12583 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12584 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12585 | |
a43f6e0f | 12586 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12587 | if (ret < 0) { |
7758a113 DV |
12588 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12589 | goto fail; | |
ee7b9f93 | 12590 | } |
e29c22c0 DV |
12591 | |
12592 | if (ret == RETRY) { | |
12593 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12594 | ret = -EINVAL; | |
12595 | goto fail; | |
12596 | } | |
12597 | ||
12598 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12599 | retry = false; | |
12600 | goto encoder_retry; | |
12601 | } | |
12602 | ||
e8fa4270 DV |
12603 | /* Dithering seems to not pass-through bits correctly when it should, so |
12604 | * only enable it on 6bpc panels. */ | |
12605 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12606 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12607 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12608 | |
7758a113 | 12609 | fail: |
548ee15b | 12610 | return ret; |
ee7b9f93 | 12611 | } |
47f1c6c9 | 12612 | |
ea9d758d | 12613 | static void |
4740b0f2 | 12614 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12615 | { |
0a9ab303 ACO |
12616 | struct drm_crtc *crtc; |
12617 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12618 | int i; |
ea9d758d | 12619 | |
7668851f | 12620 | /* Double check state. */ |
8a75d157 | 12621 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12622 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12623 | |
12624 | /* Update hwmode for vblank functions */ | |
12625 | if (crtc->state->active) | |
12626 | crtc->hwmode = crtc->state->adjusted_mode; | |
12627 | else | |
12628 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12629 | |
12630 | /* | |
12631 | * Update legacy state to satisfy fbc code. This can | |
12632 | * be removed when fbc uses the atomic state. | |
12633 | */ | |
12634 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12635 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12636 | ||
12637 | crtc->primary->fb = plane_state->fb; | |
12638 | crtc->x = plane_state->src_x >> 16; | |
12639 | crtc->y = plane_state->src_y >> 16; | |
12640 | } | |
ea9d758d | 12641 | } |
ea9d758d DV |
12642 | } |
12643 | ||
3bd26263 | 12644 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12645 | { |
3bd26263 | 12646 | int diff; |
f1f644dc JB |
12647 | |
12648 | if (clock1 == clock2) | |
12649 | return true; | |
12650 | ||
12651 | if (!clock1 || !clock2) | |
12652 | return false; | |
12653 | ||
12654 | diff = abs(clock1 - clock2); | |
12655 | ||
12656 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12657 | return true; | |
12658 | ||
12659 | return false; | |
12660 | } | |
12661 | ||
25c5b266 DV |
12662 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12663 | list_for_each_entry((intel_crtc), \ | |
12664 | &(dev)->mode_config.crtc_list, \ | |
12665 | base.head) \ | |
95150bdf | 12666 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12667 | |
cfb23ed6 ML |
12668 | static bool |
12669 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12670 | unsigned int m2, unsigned int n2, | |
12671 | bool exact) | |
12672 | { | |
12673 | if (m == m2 && n == n2) | |
12674 | return true; | |
12675 | ||
12676 | if (exact || !m || !n || !m2 || !n2) | |
12677 | return false; | |
12678 | ||
12679 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12680 | ||
31d10b57 ML |
12681 | if (n > n2) { |
12682 | while (n > n2) { | |
cfb23ed6 ML |
12683 | m2 <<= 1; |
12684 | n2 <<= 1; | |
12685 | } | |
31d10b57 ML |
12686 | } else if (n < n2) { |
12687 | while (n < n2) { | |
cfb23ed6 ML |
12688 | m <<= 1; |
12689 | n <<= 1; | |
12690 | } | |
12691 | } | |
12692 | ||
31d10b57 ML |
12693 | if (n != n2) |
12694 | return false; | |
12695 | ||
12696 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12697 | } |
12698 | ||
12699 | static bool | |
12700 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12701 | struct intel_link_m_n *m2_n2, | |
12702 | bool adjust) | |
12703 | { | |
12704 | if (m_n->tu == m2_n2->tu && | |
12705 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12706 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12707 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12708 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12709 | if (adjust) | |
12710 | *m2_n2 = *m_n; | |
12711 | ||
12712 | return true; | |
12713 | } | |
12714 | ||
12715 | return false; | |
12716 | } | |
12717 | ||
0e8ffe1b | 12718 | static bool |
2fa2fe9a | 12719 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12720 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12721 | struct intel_crtc_state *pipe_config, |
12722 | bool adjust) | |
0e8ffe1b | 12723 | { |
cfb23ed6 ML |
12724 | bool ret = true; |
12725 | ||
12726 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12727 | do { \ | |
12728 | if (!adjust) \ | |
12729 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12730 | else \ | |
12731 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12732 | } while (0) | |
12733 | ||
66e985c0 DV |
12734 | #define PIPE_CONF_CHECK_X(name) \ |
12735 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12736 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12737 | "(expected 0x%08x, found 0x%08x)\n", \ |
12738 | current_config->name, \ | |
12739 | pipe_config->name); \ | |
cfb23ed6 | 12740 | ret = false; \ |
66e985c0 DV |
12741 | } |
12742 | ||
08a24034 DV |
12743 | #define PIPE_CONF_CHECK_I(name) \ |
12744 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12745 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12746 | "(expected %i, found %i)\n", \ |
12747 | current_config->name, \ | |
12748 | pipe_config->name); \ | |
cfb23ed6 ML |
12749 | ret = false; \ |
12750 | } | |
12751 | ||
8106ddbd ACO |
12752 | #define PIPE_CONF_CHECK_P(name) \ |
12753 | if (current_config->name != pipe_config->name) { \ | |
12754 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12755 | "(expected %p, found %p)\n", \ | |
12756 | current_config->name, \ | |
12757 | pipe_config->name); \ | |
12758 | ret = false; \ | |
12759 | } | |
12760 | ||
cfb23ed6 ML |
12761 | #define PIPE_CONF_CHECK_M_N(name) \ |
12762 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12763 | &pipe_config->name,\ | |
12764 | adjust)) { \ | |
12765 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12766 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12767 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12768 | current_config->name.tu, \ | |
12769 | current_config->name.gmch_m, \ | |
12770 | current_config->name.gmch_n, \ | |
12771 | current_config->name.link_m, \ | |
12772 | current_config->name.link_n, \ | |
12773 | pipe_config->name.tu, \ | |
12774 | pipe_config->name.gmch_m, \ | |
12775 | pipe_config->name.gmch_n, \ | |
12776 | pipe_config->name.link_m, \ | |
12777 | pipe_config->name.link_n); \ | |
12778 | ret = false; \ | |
12779 | } | |
12780 | ||
55c561a7 DV |
12781 | /* This is required for BDW+ where there is only one set of registers for |
12782 | * switching between high and low RR. | |
12783 | * This macro can be used whenever a comparison has to be made between one | |
12784 | * hw state and multiple sw state variables. | |
12785 | */ | |
cfb23ed6 ML |
12786 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
12787 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12788 | &pipe_config->name, adjust) && \ | |
12789 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12790 | &pipe_config->name, adjust)) { \ | |
12791 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12792 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12793 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12794 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12795 | current_config->name.tu, \ | |
12796 | current_config->name.gmch_m, \ | |
12797 | current_config->name.gmch_n, \ | |
12798 | current_config->name.link_m, \ | |
12799 | current_config->name.link_n, \ | |
12800 | current_config->alt_name.tu, \ | |
12801 | current_config->alt_name.gmch_m, \ | |
12802 | current_config->alt_name.gmch_n, \ | |
12803 | current_config->alt_name.link_m, \ | |
12804 | current_config->alt_name.link_n, \ | |
12805 | pipe_config->name.tu, \ | |
12806 | pipe_config->name.gmch_m, \ | |
12807 | pipe_config->name.gmch_n, \ | |
12808 | pipe_config->name.link_m, \ | |
12809 | pipe_config->name.link_n); \ | |
12810 | ret = false; \ | |
88adfff1 DV |
12811 | } |
12812 | ||
1bd1bd80 DV |
12813 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12814 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12815 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12816 | "(expected %i, found %i)\n", \ |
12817 | current_config->name & (mask), \ | |
12818 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12819 | ret = false; \ |
1bd1bd80 DV |
12820 | } |
12821 | ||
5e550656 VS |
12822 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12823 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12824 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12825 | "(expected %i, found %i)\n", \ |
12826 | current_config->name, \ | |
12827 | pipe_config->name); \ | |
cfb23ed6 | 12828 | ret = false; \ |
5e550656 VS |
12829 | } |
12830 | ||
bb760063 DV |
12831 | #define PIPE_CONF_QUIRK(quirk) \ |
12832 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12833 | ||
eccb140b DV |
12834 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12835 | ||
08a24034 DV |
12836 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12837 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12838 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12839 | |
eb14cb74 | 12840 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12841 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 12842 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be VK |
12843 | |
12844 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12845 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12846 | ||
cfb23ed6 ML |
12847 | if (current_config->has_drrs) |
12848 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12849 | } else | |
12850 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12851 | |
a65347ba JN |
12852 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12853 | ||
2d112de7 ACO |
12854 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12855 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12856 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12857 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12858 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12859 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12860 | |
2d112de7 ACO |
12861 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12862 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12863 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12864 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12865 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12866 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12867 | |
c93f54cf | 12868 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12869 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12870 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12871 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12872 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12873 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12874 | |
9ed109a7 DV |
12875 | PIPE_CONF_CHECK_I(has_audio); |
12876 | ||
2d112de7 | 12877 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12878 | DRM_MODE_FLAG_INTERLACE); |
12879 | ||
bb760063 | 12880 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12881 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12882 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12883 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12884 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12885 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12886 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12887 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12888 | DRM_MODE_FLAG_NVSYNC); |
12889 | } | |
045ac3b5 | 12890 | |
333b8ca8 | 12891 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12892 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12893 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 12894 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 12895 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12896 | |
bfd16b2a ML |
12897 | if (!adjust) { |
12898 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12899 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12900 | ||
12901 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12902 | if (current_config->pch_pfit.enabled) { | |
12903 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12904 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12905 | } | |
2fa2fe9a | 12906 | |
7aefe2b5 ML |
12907 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12908 | } | |
a1b2278e | 12909 | |
e59150dc JB |
12910 | /* BDW+ don't expose a synchronous way to read the state */ |
12911 | if (IS_HASWELL(dev)) | |
12912 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12913 | |
282740f7 VS |
12914 | PIPE_CONF_CHECK_I(double_wide); |
12915 | ||
26804afd DV |
12916 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12917 | ||
8106ddbd | 12918 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 12919 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12920 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12921 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12922 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12923 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12924 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12925 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12926 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12927 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12928 | |
47eacbab VS |
12929 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
12930 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
12931 | ||
42571aef VS |
12932 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12933 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12934 | ||
2d112de7 | 12935 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12936 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12937 | |
66e985c0 | 12938 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12939 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 12940 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 12941 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12942 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12943 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12944 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12945 | |
cfb23ed6 | 12946 | return ret; |
0e8ffe1b DV |
12947 | } |
12948 | ||
e3b247da VS |
12949 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12950 | const struct intel_crtc_state *pipe_config) | |
12951 | { | |
12952 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12953 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12954 | &pipe_config->fdi_m_n); |
12955 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12956 | ||
12957 | /* | |
12958 | * FDI already provided one idea for the dotclock. | |
12959 | * Yell if the encoder disagrees. | |
12960 | */ | |
12961 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12962 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12963 | fdi_dotclock, dotclock); | |
12964 | } | |
12965 | } | |
12966 | ||
c0ead703 ML |
12967 | static void verify_wm_state(struct drm_crtc *crtc, |
12968 | struct drm_crtc_state *new_state) | |
08db6652 | 12969 | { |
e7c84544 | 12970 | struct drm_device *dev = crtc->dev; |
08db6652 DL |
12971 | struct drm_i915_private *dev_priv = dev->dev_private; |
12972 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
e7c84544 ML |
12973 | struct skl_ddb_entry *hw_entry, *sw_entry; |
12974 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12975 | const enum pipe pipe = intel_crtc->pipe; | |
08db6652 DL |
12976 | int plane; |
12977 | ||
e7c84544 | 12978 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
12979 | return; |
12980 | ||
12981 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12982 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12983 | ||
e7c84544 ML |
12984 | /* planes */ |
12985 | for_each_plane(dev_priv, pipe, plane) { | |
12986 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
12987 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
08db6652 | 12988 | |
e7c84544 | 12989 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
08db6652 DL |
12990 | continue; |
12991 | ||
e7c84544 ML |
12992 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
12993 | "(expected (%u,%u), found (%u,%u))\n", | |
12994 | pipe_name(pipe), plane + 1, | |
12995 | sw_entry->start, sw_entry->end, | |
12996 | hw_entry->start, hw_entry->end); | |
12997 | } | |
08db6652 | 12998 | |
e7c84544 ML |
12999 | /* cursor */ |
13000 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
13001 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 | 13002 | |
e7c84544 | 13003 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
08db6652 DL |
13004 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
13005 | "(expected (%u,%u), found (%u,%u))\n", | |
13006 | pipe_name(pipe), | |
13007 | sw_entry->start, sw_entry->end, | |
13008 | hw_entry->start, hw_entry->end); | |
13009 | } | |
13010 | } | |
13011 | ||
91d1b4bd | 13012 | static void |
c0ead703 | 13013 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 13014 | { |
35dd3c64 | 13015 | struct drm_connector *connector; |
8af6cf88 | 13016 | |
e7c84544 | 13017 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
13018 | struct drm_encoder *encoder = connector->encoder; |
13019 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 13020 | |
e7c84544 ML |
13021 | if (state->crtc != crtc) |
13022 | continue; | |
13023 | ||
5a21b665 | 13024 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 13025 | |
ad3c558f | 13026 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 13027 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 13028 | } |
91d1b4bd DV |
13029 | } |
13030 | ||
13031 | static void | |
c0ead703 | 13032 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
13033 | { |
13034 | struct intel_encoder *encoder; | |
13035 | struct intel_connector *connector; | |
8af6cf88 | 13036 | |
b2784e15 | 13037 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13038 | bool enabled = false; |
4d20cd86 | 13039 | enum pipe pipe; |
8af6cf88 DV |
13040 | |
13041 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13042 | encoder->base.base.id, | |
8e329a03 | 13043 | encoder->base.name); |
8af6cf88 | 13044 | |
3a3371ff | 13045 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13046 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13047 | continue; |
13048 | enabled = true; | |
ad3c558f ML |
13049 | |
13050 | I915_STATE_WARN(connector->base.state->crtc != | |
13051 | encoder->base.crtc, | |
13052 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13053 | } |
0e32b39c | 13054 | |
e2c719b7 | 13055 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13056 | "encoder's enabled state mismatch " |
13057 | "(expected %i, found %i)\n", | |
13058 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13059 | |
13060 | if (!encoder->base.crtc) { | |
4d20cd86 | 13061 | bool active; |
7c60d198 | 13062 | |
4d20cd86 ML |
13063 | active = encoder->get_hw_state(encoder, &pipe); |
13064 | I915_STATE_WARN(active, | |
13065 | "encoder detached but still enabled on pipe %c.\n", | |
13066 | pipe_name(pipe)); | |
7c60d198 | 13067 | } |
8af6cf88 | 13068 | } |
91d1b4bd DV |
13069 | } |
13070 | ||
13071 | static void | |
c0ead703 ML |
13072 | verify_crtc_state(struct drm_crtc *crtc, |
13073 | struct drm_crtc_state *old_crtc_state, | |
13074 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 13075 | { |
e7c84544 | 13076 | struct drm_device *dev = crtc->dev; |
fbee40df | 13077 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 13078 | struct intel_encoder *encoder; |
e7c84544 ML |
13079 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13080 | struct intel_crtc_state *pipe_config, *sw_config; | |
13081 | struct drm_atomic_state *old_state; | |
13082 | bool active; | |
045ac3b5 | 13083 | |
e7c84544 | 13084 | old_state = old_crtc_state->state; |
ec2dc6a0 | 13085 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
13086 | pipe_config = to_intel_crtc_state(old_crtc_state); |
13087 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13088 | pipe_config->base.crtc = crtc; | |
13089 | pipe_config->base.state = old_state; | |
8af6cf88 | 13090 | |
78108b7c | 13091 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 13092 | |
e7c84544 | 13093 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 13094 | |
e7c84544 ML |
13095 | /* hw state is inconsistent with the pipe quirk */ |
13096 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
13097 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13098 | active = new_crtc_state->active; | |
6c49f241 | 13099 | |
e7c84544 ML |
13100 | I915_STATE_WARN(new_crtc_state->active != active, |
13101 | "crtc active state doesn't match with hw state " | |
13102 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 13103 | |
e7c84544 ML |
13104 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
13105 | "transitional active state does not match atomic hw state " | |
13106 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13107 | |
e7c84544 ML |
13108 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13109 | enum pipe pipe; | |
4d20cd86 | 13110 | |
e7c84544 ML |
13111 | active = encoder->get_hw_state(encoder, &pipe); |
13112 | I915_STATE_WARN(active != new_crtc_state->active, | |
13113 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13114 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13115 | |
e7c84544 ML |
13116 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13117 | "Encoder connected to wrong pipe %c\n", | |
13118 | pipe_name(pipe)); | |
4d20cd86 | 13119 | |
e7c84544 ML |
13120 | if (active) |
13121 | encoder->get_config(encoder, pipe_config); | |
13122 | } | |
53d9f4e9 | 13123 | |
e7c84544 ML |
13124 | if (!new_crtc_state->active) |
13125 | return; | |
cfb23ed6 | 13126 | |
e7c84544 | 13127 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13128 | |
e7c84544 ML |
13129 | sw_config = to_intel_crtc_state(crtc->state); |
13130 | if (!intel_pipe_config_compare(dev, sw_config, | |
13131 | pipe_config, false)) { | |
13132 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13133 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13134 | "[hw state]"); | |
13135 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13136 | "[sw state]"); | |
8af6cf88 DV |
13137 | } |
13138 | } | |
13139 | ||
91d1b4bd | 13140 | static void |
c0ead703 ML |
13141 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13142 | struct intel_shared_dpll *pll, | |
13143 | struct drm_crtc *crtc, | |
13144 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13145 | { |
91d1b4bd | 13146 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13147 | unsigned crtc_mask; |
13148 | bool active; | |
5358901f | 13149 | |
e7c84544 | 13150 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13151 | |
e7c84544 | 13152 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13153 | |
e7c84544 | 13154 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13155 | |
e7c84544 ML |
13156 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13157 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13158 | "pll in active use but not on in sw tracking\n"); | |
13159 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13160 | "pll is on but not used by any active crtc\n"); | |
13161 | I915_STATE_WARN(pll->on != active, | |
13162 | "pll on state mismatch (expected %i, found %i)\n", | |
13163 | pll->on, active); | |
13164 | } | |
5358901f | 13165 | |
e7c84544 | 13166 | if (!crtc) { |
2dd66ebd | 13167 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13168 | "more active pll users than references: %x vs %x\n", |
13169 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13170 | |
e7c84544 ML |
13171 | return; |
13172 | } | |
13173 | ||
13174 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13175 | ||
13176 | if (new_state->active) | |
13177 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13178 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13179 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13180 | else | |
13181 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13182 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13183 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13184 | |
e7c84544 ML |
13185 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13186 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13187 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13188 | |
e7c84544 ML |
13189 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13190 | &dpll_hw_state, | |
13191 | sizeof(dpll_hw_state)), | |
13192 | "pll hw state mismatch\n"); | |
13193 | } | |
13194 | ||
13195 | static void | |
c0ead703 ML |
13196 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13197 | struct drm_crtc_state *old_crtc_state, | |
13198 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 ML |
13199 | { |
13200 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13201 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); | |
13202 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13203 | ||
13204 | if (new_state->shared_dpll) | |
c0ead703 | 13205 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13206 | |
13207 | if (old_state->shared_dpll && | |
13208 | old_state->shared_dpll != new_state->shared_dpll) { | |
13209 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13210 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13211 | ||
13212 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13213 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13214 | pipe_name(drm_crtc_index(crtc))); | |
13215 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13216 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13217 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13218 | } |
8af6cf88 DV |
13219 | } |
13220 | ||
e7c84544 | 13221 | static void |
c0ead703 | 13222 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13223 | struct drm_crtc_state *old_state, |
13224 | struct drm_crtc_state *new_state) | |
13225 | { | |
5a21b665 DV |
13226 | if (!needs_modeset(new_state) && |
13227 | !to_intel_crtc_state(new_state)->update_pipe) | |
13228 | return; | |
13229 | ||
c0ead703 | 13230 | verify_wm_state(crtc, new_state); |
5a21b665 | 13231 | verify_connector_state(crtc->dev, crtc); |
c0ead703 ML |
13232 | verify_crtc_state(crtc, old_state, new_state); |
13233 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13234 | } |
13235 | ||
13236 | static void | |
c0ead703 | 13237 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 ML |
13238 | { |
13239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13240 | int i; | |
13241 | ||
13242 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13243 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13244 | } |
13245 | ||
13246 | static void | |
c0ead703 | 13247 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13248 | { |
c0ead703 ML |
13249 | verify_encoder_state(dev); |
13250 | verify_connector_state(dev, NULL); | |
13251 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13252 | } |
13253 | ||
80715b2f VS |
13254 | static void update_scanline_offset(struct intel_crtc *crtc) |
13255 | { | |
13256 | struct drm_device *dev = crtc->base.dev; | |
13257 | ||
13258 | /* | |
13259 | * The scanline counter increments at the leading edge of hsync. | |
13260 | * | |
13261 | * On most platforms it starts counting from vtotal-1 on the | |
13262 | * first active line. That means the scanline counter value is | |
13263 | * always one less than what we would expect. Ie. just after | |
13264 | * start of vblank, which also occurs at start of hsync (on the | |
13265 | * last active line), the scanline counter will read vblank_start-1. | |
13266 | * | |
13267 | * On gen2 the scanline counter starts counting from 1 instead | |
13268 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13269 | * to keep the value positive), instead of adding one. | |
13270 | * | |
13271 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13272 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13273 | * there's an extra 1 line difference. So we need to add two instead of | |
13274 | * one to the value. | |
13275 | */ | |
13276 | if (IS_GEN2(dev)) { | |
124abe07 | 13277 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13278 | int vtotal; |
13279 | ||
124abe07 VS |
13280 | vtotal = adjusted_mode->crtc_vtotal; |
13281 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13282 | vtotal /= 2; |
13283 | ||
13284 | crtc->scanline_offset = vtotal - 1; | |
13285 | } else if (HAS_DDI(dev) && | |
409ee761 | 13286 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13287 | crtc->scanline_offset = 2; |
13288 | } else | |
13289 | crtc->scanline_offset = 1; | |
13290 | } | |
13291 | ||
ad421372 | 13292 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13293 | { |
225da59b | 13294 | struct drm_device *dev = state->dev; |
ed6739ef | 13295 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13296 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13297 | struct drm_crtc *crtc; |
13298 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13299 | int i; |
ed6739ef ACO |
13300 | |
13301 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13302 | return; |
ed6739ef | 13303 | |
0a9ab303 | 13304 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13305 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13306 | struct intel_shared_dpll *old_dpll = |
13307 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13308 | |
fb1a38a9 | 13309 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13310 | continue; |
13311 | ||
8106ddbd | 13312 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13313 | |
8106ddbd | 13314 | if (!old_dpll) |
fb1a38a9 | 13315 | continue; |
0a9ab303 | 13316 | |
ad421372 ML |
13317 | if (!shared_dpll) |
13318 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13319 | |
8106ddbd | 13320 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13321 | } |
ed6739ef ACO |
13322 | } |
13323 | ||
99d736a2 ML |
13324 | /* |
13325 | * This implements the workaround described in the "notes" section of the mode | |
13326 | * set sequence documentation. When going from no pipes or single pipe to | |
13327 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13328 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13329 | */ | |
13330 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13331 | { | |
13332 | struct drm_crtc_state *crtc_state; | |
13333 | struct intel_crtc *intel_crtc; | |
13334 | struct drm_crtc *crtc; | |
13335 | struct intel_crtc_state *first_crtc_state = NULL; | |
13336 | struct intel_crtc_state *other_crtc_state = NULL; | |
13337 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13338 | int i; | |
13339 | ||
13340 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13341 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13342 | intel_crtc = to_intel_crtc(crtc); | |
13343 | ||
13344 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13345 | continue; | |
13346 | ||
13347 | if (first_crtc_state) { | |
13348 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13349 | break; | |
13350 | } else { | |
13351 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13352 | first_pipe = intel_crtc->pipe; | |
13353 | } | |
13354 | } | |
13355 | ||
13356 | /* No workaround needed? */ | |
13357 | if (!first_crtc_state) | |
13358 | return 0; | |
13359 | ||
13360 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13361 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13362 | struct intel_crtc_state *pipe_config; | |
13363 | ||
13364 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13365 | if (IS_ERR(pipe_config)) | |
13366 | return PTR_ERR(pipe_config); | |
13367 | ||
13368 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13369 | ||
13370 | if (!pipe_config->base.active || | |
13371 | needs_modeset(&pipe_config->base)) | |
13372 | continue; | |
13373 | ||
13374 | /* 2 or more enabled crtcs means no need for w/a */ | |
13375 | if (enabled_pipe != INVALID_PIPE) | |
13376 | return 0; | |
13377 | ||
13378 | enabled_pipe = intel_crtc->pipe; | |
13379 | } | |
13380 | ||
13381 | if (enabled_pipe != INVALID_PIPE) | |
13382 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13383 | else if (other_crtc_state) | |
13384 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13385 | ||
13386 | return 0; | |
13387 | } | |
13388 | ||
27c329ed ML |
13389 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13390 | { | |
13391 | struct drm_crtc *crtc; | |
13392 | struct drm_crtc_state *crtc_state; | |
13393 | int ret = 0; | |
13394 | ||
13395 | /* add all active pipes to the state */ | |
13396 | for_each_crtc(state->dev, crtc) { | |
13397 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13398 | if (IS_ERR(crtc_state)) | |
13399 | return PTR_ERR(crtc_state); | |
13400 | ||
13401 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13402 | continue; | |
13403 | ||
13404 | crtc_state->mode_changed = true; | |
13405 | ||
13406 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13407 | if (ret) | |
13408 | break; | |
13409 | ||
13410 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13411 | if (ret) | |
13412 | break; | |
13413 | } | |
13414 | ||
13415 | return ret; | |
13416 | } | |
13417 | ||
c347a676 | 13418 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13419 | { |
565602d7 ML |
13420 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13421 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13422 | struct drm_crtc *crtc; | |
13423 | struct drm_crtc_state *crtc_state; | |
13424 | int ret = 0, i; | |
054518dd | 13425 | |
b359283a ML |
13426 | if (!check_digital_port_conflicts(state)) { |
13427 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13428 | return -EINVAL; | |
13429 | } | |
13430 | ||
565602d7 ML |
13431 | intel_state->modeset = true; |
13432 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13433 | ||
13434 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13435 | if (crtc_state->active) | |
13436 | intel_state->active_crtcs |= 1 << i; | |
13437 | else | |
13438 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13439 | |
13440 | if (crtc_state->active != crtc->state->active) | |
13441 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13442 | } |
13443 | ||
054518dd ACO |
13444 | /* |
13445 | * See if the config requires any additional preparation, e.g. | |
13446 | * to adjust global state with pipes off. We need to do this | |
13447 | * here so we can get the modeset_pipe updated config for the new | |
13448 | * mode set on this crtc. For other crtcs we need to use the | |
13449 | * adjusted_mode bits in the crtc directly. | |
13450 | */ | |
27c329ed | 13451 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 13452 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 13453 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
13454 | if (!intel_state->cdclk_pll_vco) |
13455 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 13456 | |
27c329ed | 13457 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
13458 | if (ret < 0) |
13459 | return ret; | |
27c329ed | 13460 | |
c89e39f3 | 13461 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13462 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) |
27c329ed ML |
13463 | ret = intel_modeset_all_pipes(state); |
13464 | ||
13465 | if (ret < 0) | |
054518dd | 13466 | return ret; |
e8788cbc ML |
13467 | |
13468 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13469 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13470 | } else |
1a617b77 | 13471 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13472 | |
ad421372 | 13473 | intel_modeset_clear_plls(state); |
054518dd | 13474 | |
565602d7 | 13475 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13476 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13477 | |
ad421372 | 13478 | return 0; |
c347a676 ACO |
13479 | } |
13480 | ||
aa363136 MR |
13481 | /* |
13482 | * Handle calculation of various watermark data at the end of the atomic check | |
13483 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13484 | * handlers to ensure that all derived state has been updated. | |
13485 | */ | |
55994c2c | 13486 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
13487 | { |
13488 | struct drm_device *dev = state->dev; | |
98d39494 | 13489 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
13490 | |
13491 | /* Is there platform-specific watermark information to calculate? */ | |
13492 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
13493 | return dev_priv->display.compute_global_watermarks(state); |
13494 | ||
13495 | return 0; | |
aa363136 MR |
13496 | } |
13497 | ||
74c090b1 ML |
13498 | /** |
13499 | * intel_atomic_check - validate state object | |
13500 | * @dev: drm device | |
13501 | * @state: state to validate | |
13502 | */ | |
13503 | static int intel_atomic_check(struct drm_device *dev, | |
13504 | struct drm_atomic_state *state) | |
c347a676 | 13505 | { |
dd8b3bdb | 13506 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13507 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13508 | struct drm_crtc *crtc; |
13509 | struct drm_crtc_state *crtc_state; | |
13510 | int ret, i; | |
61333b60 | 13511 | bool any_ms = false; |
c347a676 | 13512 | |
74c090b1 | 13513 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13514 | if (ret) |
13515 | return ret; | |
13516 | ||
c347a676 | 13517 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13518 | struct intel_crtc_state *pipe_config = |
13519 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13520 | |
13521 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13522 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13523 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13524 | |
af4a879e | 13525 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
13526 | continue; |
13527 | ||
af4a879e DV |
13528 | if (!crtc_state->enable) { |
13529 | any_ms = true; | |
cfb23ed6 | 13530 | continue; |
af4a879e | 13531 | } |
cfb23ed6 | 13532 | |
26495481 DV |
13533 | /* FIXME: For only active_changed we shouldn't need to do any |
13534 | * state recomputation at all. */ | |
13535 | ||
1ed51de9 DV |
13536 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13537 | if (ret) | |
13538 | return ret; | |
b359283a | 13539 | |
cfb23ed6 | 13540 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
13541 | if (ret) { |
13542 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
13543 | pipe_config, "[failed]"); | |
c347a676 | 13544 | return ret; |
25aa1c39 | 13545 | } |
c347a676 | 13546 | |
73831236 | 13547 | if (i915.fastboot && |
dd8b3bdb | 13548 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13549 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13550 | pipe_config, true)) { |
26495481 | 13551 | crtc_state->mode_changed = false; |
bfd16b2a | 13552 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13553 | } |
13554 | ||
af4a879e | 13555 | if (needs_modeset(crtc_state)) |
26495481 | 13556 | any_ms = true; |
cfb23ed6 | 13557 | |
af4a879e DV |
13558 | ret = drm_atomic_add_affected_planes(state, crtc); |
13559 | if (ret) | |
13560 | return ret; | |
61333b60 | 13561 | |
26495481 DV |
13562 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13563 | needs_modeset(crtc_state) ? | |
13564 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13565 | } |
13566 | ||
61333b60 ML |
13567 | if (any_ms) { |
13568 | ret = intel_modeset_checks(state); | |
13569 | ||
13570 | if (ret) | |
13571 | return ret; | |
27c329ed | 13572 | } else |
dd8b3bdb | 13573 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13574 | |
dd8b3bdb | 13575 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13576 | if (ret) |
13577 | return ret; | |
13578 | ||
f51be2e0 | 13579 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 13580 | return calc_watermark_data(state); |
054518dd ACO |
13581 | } |
13582 | ||
5008e874 ML |
13583 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13584 | struct drm_atomic_state *state, | |
81072bfd | 13585 | bool nonblock) |
5008e874 | 13586 | { |
7580d774 ML |
13587 | struct drm_i915_private *dev_priv = dev->dev_private; |
13588 | struct drm_plane_state *plane_state; | |
5008e874 | 13589 | struct drm_crtc_state *crtc_state; |
7580d774 | 13590 | struct drm_plane *plane; |
5008e874 ML |
13591 | struct drm_crtc *crtc; |
13592 | int i, ret; | |
13593 | ||
5a21b665 DV |
13594 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13595 | if (state->legacy_cursor_update) | |
a6747b73 ML |
13596 | continue; |
13597 | ||
5a21b665 DV |
13598 | ret = intel_crtc_wait_for_pending_flips(crtc); |
13599 | if (ret) | |
13600 | return ret; | |
5008e874 | 13601 | |
5a21b665 DV |
13602 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
13603 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
13604 | } |
13605 | ||
f935675f ML |
13606 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13607 | if (ret) | |
13608 | return ret; | |
13609 | ||
5008e874 | 13610 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 13611 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 13612 | |
21daaeee | 13613 | if (!ret && !nonblock) { |
7580d774 ML |
13614 | for_each_plane_in_state(state, plane, plane_state, i) { |
13615 | struct intel_plane_state *intel_plane_state = | |
13616 | to_intel_plane_state(plane_state); | |
13617 | ||
13618 | if (!intel_plane_state->wait_req) | |
13619 | continue; | |
13620 | ||
13621 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
299259a3 | 13622 | true, NULL, NULL); |
f7e5838b | 13623 | if (ret) { |
f4457ae7 CW |
13624 | /* Any hang should be swallowed by the wait */ |
13625 | WARN_ON(ret == -EIO); | |
f7e5838b CW |
13626 | mutex_lock(&dev->struct_mutex); |
13627 | drm_atomic_helper_cleanup_planes(dev, state); | |
13628 | mutex_unlock(&dev->struct_mutex); | |
7580d774 | 13629 | break; |
f7e5838b | 13630 | } |
7580d774 | 13631 | } |
7580d774 | 13632 | } |
5008e874 ML |
13633 | |
13634 | return ret; | |
13635 | } | |
13636 | ||
a2991414 ML |
13637 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
13638 | { | |
13639 | struct drm_device *dev = crtc->base.dev; | |
13640 | ||
13641 | if (!dev->max_vblank_count) | |
13642 | return drm_accurate_vblank_count(&crtc->base); | |
13643 | ||
13644 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
13645 | } | |
13646 | ||
5a21b665 DV |
13647 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13648 | struct drm_i915_private *dev_priv, | |
13649 | unsigned crtc_mask) | |
e8861675 | 13650 | { |
5a21b665 DV |
13651 | unsigned last_vblank_count[I915_MAX_PIPES]; |
13652 | enum pipe pipe; | |
13653 | int ret; | |
e8861675 | 13654 | |
5a21b665 DV |
13655 | if (!crtc_mask) |
13656 | return; | |
e8861675 | 13657 | |
5a21b665 DV |
13658 | for_each_pipe(dev_priv, pipe) { |
13659 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
e8861675 | 13660 | |
5a21b665 | 13661 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
13662 | continue; |
13663 | ||
5a21b665 DV |
13664 | ret = drm_crtc_vblank_get(crtc); |
13665 | if (WARN_ON(ret != 0)) { | |
13666 | crtc_mask &= ~(1 << pipe); | |
13667 | continue; | |
e8861675 ML |
13668 | } |
13669 | ||
5a21b665 | 13670 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); |
e8861675 ML |
13671 | } |
13672 | ||
5a21b665 DV |
13673 | for_each_pipe(dev_priv, pipe) { |
13674 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13675 | long lret; | |
e8861675 | 13676 | |
5a21b665 DV |
13677 | if (!((1 << pipe) & crtc_mask)) |
13678 | continue; | |
d55dbd06 | 13679 | |
5a21b665 DV |
13680 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
13681 | last_vblank_count[pipe] != | |
13682 | drm_crtc_vblank_count(crtc), | |
13683 | msecs_to_jiffies(50)); | |
d55dbd06 | 13684 | |
5a21b665 | 13685 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 13686 | |
5a21b665 | 13687 | drm_crtc_vblank_put(crtc); |
d55dbd06 ML |
13688 | } |
13689 | } | |
13690 | ||
5a21b665 | 13691 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 13692 | { |
5a21b665 DV |
13693 | /* fb updated, need to unpin old fb */ |
13694 | if (crtc_state->fb_changed) | |
13695 | return true; | |
a6747b73 | 13696 | |
5a21b665 DV |
13697 | /* wm changes, need vblank before final wm's */ |
13698 | if (crtc_state->update_wm_post) | |
13699 | return true; | |
a6747b73 | 13700 | |
5a21b665 DV |
13701 | /* |
13702 | * cxsr is re-enabled after vblank. | |
13703 | * This is already handled by crtc_state->update_wm_post, | |
13704 | * but added for clarity. | |
13705 | */ | |
13706 | if (crtc_state->disable_cxsr) | |
13707 | return true; | |
a6747b73 | 13708 | |
5a21b665 | 13709 | return false; |
e8861675 ML |
13710 | } |
13711 | ||
94f05024 | 13712 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 13713 | { |
94f05024 | 13714 | struct drm_device *dev = state->dev; |
565602d7 | 13715 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13716 | struct drm_i915_private *dev_priv = dev->dev_private; |
29ceb0e6 | 13717 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13718 | struct drm_crtc *crtc; |
5a21b665 | 13719 | struct intel_crtc_state *intel_cstate; |
94f05024 DV |
13720 | struct drm_plane *plane; |
13721 | struct drm_plane_state *plane_state; | |
5a21b665 DV |
13722 | bool hw_check = intel_state->modeset; |
13723 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
13724 | unsigned crtc_vblank_mask = 0; | |
94f05024 | 13725 | int i, ret; |
a6778b3c | 13726 | |
94f05024 DV |
13727 | for_each_plane_in_state(state, plane, plane_state, i) { |
13728 | struct intel_plane_state *intel_plane_state = | |
13729 | to_intel_plane_state(plane_state); | |
ea0000f0 | 13730 | |
94f05024 DV |
13731 | if (!intel_plane_state->wait_req) |
13732 | continue; | |
d4afb8cc | 13733 | |
94f05024 DV |
13734 | ret = __i915_wait_request(intel_plane_state->wait_req, |
13735 | true, NULL, NULL); | |
13736 | /* EIO should be eaten, and we can't get interrupted in the | |
13737 | * worker, and blocking commits have waited already. */ | |
13738 | WARN_ON(ret); | |
13739 | } | |
1c5e19f8 | 13740 | |
ea0000f0 DV |
13741 | drm_atomic_helper_wait_for_dependencies(state); |
13742 | ||
565602d7 ML |
13743 | if (intel_state->modeset) { |
13744 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13745 | sizeof(intel_state->min_pixclk)); | |
13746 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13747 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
5a21b665 DV |
13748 | |
13749 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13750 | } |
13751 | ||
29ceb0e6 | 13752 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13753 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13754 | ||
5a21b665 DV |
13755 | if (needs_modeset(crtc->state) || |
13756 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13757 | hw_check = true; | |
13758 | ||
13759 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13760 | modeset_get_crtc_power_domains(crtc, | |
13761 | to_intel_crtc_state(crtc->state)); | |
13762 | } | |
13763 | ||
61333b60 ML |
13764 | if (!needs_modeset(crtc->state)) |
13765 | continue; | |
13766 | ||
29ceb0e6 | 13767 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13768 | |
29ceb0e6 VS |
13769 | if (old_crtc_state->active) { |
13770 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13771 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13772 | intel_crtc->active = false; |
58f9c0bc | 13773 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13774 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13775 | |
13776 | /* | |
13777 | * Underruns don't always raise | |
13778 | * interrupts, so check manually. | |
13779 | */ | |
13780 | intel_check_cpu_fifo_underruns(dev_priv); | |
13781 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13782 | |
13783 | if (!crtc->state->active) | |
13784 | intel_update_watermarks(crtc); | |
a539205a | 13785 | } |
b8cecdf5 | 13786 | } |
7758a113 | 13787 | |
ea9d758d DV |
13788 | /* Only after disabling all output pipelines that will be changed can we |
13789 | * update the the output configuration. */ | |
4740b0f2 | 13790 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13791 | |
565602d7 | 13792 | if (intel_state->modeset) { |
4740b0f2 | 13793 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13794 | |
13795 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 13796 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13797 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 13798 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 13799 | |
c0ead703 | 13800 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 13801 | } |
47fab737 | 13802 | |
a6778b3c | 13803 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13804 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13805 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13806 | bool modeset = needs_modeset(crtc->state); | |
5a21b665 DV |
13807 | struct intel_crtc_state *pipe_config = |
13808 | to_intel_crtc_state(crtc->state); | |
9f836f90 | 13809 | |
f6ac4b2a | 13810 | if (modeset && crtc->state->active) { |
a539205a ML |
13811 | update_scanline_offset(to_intel_crtc(crtc)); |
13812 | dev_priv->display.crtc_enable(crtc); | |
13813 | } | |
80715b2f | 13814 | |
1f7528c4 DV |
13815 | /* Complete events for now disable pipes here. */ |
13816 | if (modeset && !crtc->state->active && crtc->state->event) { | |
13817 | spin_lock_irq(&dev->event_lock); | |
13818 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
13819 | spin_unlock_irq(&dev->event_lock); | |
13820 | ||
13821 | crtc->state->event = NULL; | |
13822 | } | |
13823 | ||
f6ac4b2a | 13824 | if (!modeset) |
29ceb0e6 | 13825 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13826 | |
5a21b665 DV |
13827 | if (crtc->state->active && |
13828 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
faf68d92 | 13829 | intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state)); |
5a21b665 | 13830 | |
1f7528c4 | 13831 | if (crtc->state->active) |
5a21b665 | 13832 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
f6d1973d | 13833 | |
5a21b665 DV |
13834 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13835 | crtc_vblank_mask |= 1 << i; | |
177246a8 MR |
13836 | } |
13837 | ||
94f05024 DV |
13838 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
13839 | * already, but still need the state for the delayed optimization. To | |
13840 | * fix this: | |
13841 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
13842 | * - schedule that vblank worker _before_ calling hw_done | |
13843 | * - at the start of commit_tail, cancel it _synchrously | |
13844 | * - switch over to the vblank wait helper in the core after that since | |
13845 | * we don't need out special handling any more. | |
13846 | */ | |
5a21b665 DV |
13847 | if (!state->legacy_cursor_update) |
13848 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
13849 | ||
13850 | /* | |
13851 | * Now that the vblank has passed, we can go ahead and program the | |
13852 | * optimal watermarks on platforms that need two-step watermark | |
13853 | * programming. | |
13854 | * | |
13855 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13856 | */ | |
13857 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13858 | intel_cstate = to_intel_crtc_state(crtc->state); | |
13859 | ||
13860 | if (dev_priv->display.optimize_watermarks) | |
13861 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13862 | } | |
13863 | ||
13864 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13865 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13866 | ||
13867 | if (put_domains[i]) | |
13868 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13869 | ||
13870 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); | |
13871 | } | |
13872 | ||
94f05024 DV |
13873 | drm_atomic_helper_commit_hw_done(state); |
13874 | ||
5a21b665 DV |
13875 | if (intel_state->modeset) |
13876 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13877 | ||
13878 | mutex_lock(&dev->struct_mutex); | |
13879 | drm_atomic_helper_cleanup_planes(dev, state); | |
13880 | mutex_unlock(&dev->struct_mutex); | |
13881 | ||
ea0000f0 DV |
13882 | drm_atomic_helper_commit_cleanup_done(state); |
13883 | ||
ee165b1a | 13884 | drm_atomic_state_free(state); |
f30da187 | 13885 | |
75714940 MK |
13886 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13887 | * of triggering bugs in unclaimed access. After we finish | |
13888 | * modesetting, see if an error has been flagged, and if so | |
13889 | * enable debugging for the next modeset - and hope we catch | |
13890 | * the culprit. | |
13891 | * | |
13892 | * XXX note that we assume display power is on at this point. | |
13893 | * This might hold true now but we need to add pm helper to check | |
13894 | * unclaimed only when the hardware is on, as atomic commits | |
13895 | * can happen also when the device is completely off. | |
13896 | */ | |
13897 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
13898 | } |
13899 | ||
13900 | static void intel_atomic_commit_work(struct work_struct *work) | |
13901 | { | |
13902 | struct drm_atomic_state *state = container_of(work, | |
13903 | struct drm_atomic_state, | |
13904 | commit_work); | |
13905 | intel_atomic_commit_tail(state); | |
13906 | } | |
13907 | ||
6c9c1b38 DV |
13908 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
13909 | { | |
13910 | struct drm_plane_state *old_plane_state; | |
13911 | struct drm_plane *plane; | |
13912 | struct drm_i915_gem_object *obj, *old_obj; | |
13913 | struct intel_plane *intel_plane; | |
13914 | int i; | |
13915 | ||
13916 | mutex_lock(&state->dev->struct_mutex); | |
13917 | for_each_plane_in_state(state, plane, old_plane_state, i) { | |
13918 | obj = intel_fb_obj(plane->state->fb); | |
13919 | old_obj = intel_fb_obj(old_plane_state->fb); | |
13920 | intel_plane = to_intel_plane(plane); | |
13921 | ||
13922 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
13923 | } | |
13924 | mutex_unlock(&state->dev->struct_mutex); | |
13925 | } | |
13926 | ||
94f05024 DV |
13927 | /** |
13928 | * intel_atomic_commit - commit validated state object | |
13929 | * @dev: DRM device | |
13930 | * @state: the top-level driver state object | |
13931 | * @nonblock: nonblocking commit | |
13932 | * | |
13933 | * This function commits a top-level state object that has been validated | |
13934 | * with drm_atomic_helper_check(). | |
13935 | * | |
13936 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13937 | * nonblocking commits are only safe for pure plane updates. Everything else | |
13938 | * should work though. | |
13939 | * | |
13940 | * RETURNS | |
13941 | * Zero for success or -errno. | |
13942 | */ | |
13943 | static int intel_atomic_commit(struct drm_device *dev, | |
13944 | struct drm_atomic_state *state, | |
13945 | bool nonblock) | |
13946 | { | |
13947 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13949 | int ret = 0; | |
13950 | ||
13951 | if (intel_state->modeset && nonblock) { | |
13952 | DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n"); | |
13953 | return -EINVAL; | |
13954 | } | |
13955 | ||
13956 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
13957 | if (ret) | |
13958 | return ret; | |
13959 | ||
13960 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); | |
13961 | ||
13962 | ret = intel_atomic_prepare_commit(dev, state, nonblock); | |
13963 | if (ret) { | |
13964 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
13965 | return ret; | |
13966 | } | |
13967 | ||
13968 | drm_atomic_helper_swap_state(state, true); | |
13969 | dev_priv->wm.distrust_bios_wm = false; | |
13970 | dev_priv->wm.skl_results = intel_state->wm_results; | |
13971 | intel_shared_dpll_commit(state); | |
6c9c1b38 | 13972 | intel_atomic_track_fbs(state); |
94f05024 DV |
13973 | |
13974 | if (nonblock) | |
13975 | queue_work(system_unbound_wq, &state->commit_work); | |
13976 | else | |
13977 | intel_atomic_commit_tail(state); | |
75714940 | 13978 | |
74c090b1 | 13979 | return 0; |
7f27126e JB |
13980 | } |
13981 | ||
c0c36b94 CW |
13982 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13983 | { | |
83a57153 ACO |
13984 | struct drm_device *dev = crtc->dev; |
13985 | struct drm_atomic_state *state; | |
e694eb02 | 13986 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13987 | int ret; |
83a57153 ACO |
13988 | |
13989 | state = drm_atomic_state_alloc(dev); | |
13990 | if (!state) { | |
78108b7c VS |
13991 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
13992 | crtc->base.id, crtc->name); | |
83a57153 ACO |
13993 | return; |
13994 | } | |
13995 | ||
e694eb02 | 13996 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13997 | |
e694eb02 ML |
13998 | retry: |
13999 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
14000 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
14001 | if (!ret) { | |
14002 | if (!crtc_state->active) | |
14003 | goto out; | |
83a57153 | 14004 | |
e694eb02 | 14005 | crtc_state->mode_changed = true; |
74c090b1 | 14006 | ret = drm_atomic_commit(state); |
83a57153 ACO |
14007 | } |
14008 | ||
e694eb02 ML |
14009 | if (ret == -EDEADLK) { |
14010 | drm_atomic_state_clear(state); | |
14011 | drm_modeset_backoff(state->acquire_ctx); | |
14012 | goto retry; | |
4ed9fb37 | 14013 | } |
4be07317 | 14014 | |
2bfb4627 | 14015 | if (ret) |
e694eb02 | 14016 | out: |
2bfb4627 | 14017 | drm_atomic_state_free(state); |
c0c36b94 CW |
14018 | } |
14019 | ||
25c5b266 DV |
14020 | #undef for_each_intel_crtc_masked |
14021 | ||
f6e5b160 | 14022 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
82cf435b | 14023 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 14024 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 14025 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 14026 | .destroy = intel_crtc_destroy, |
527b6abe | 14027 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
14028 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
14029 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
14030 | }; |
14031 | ||
6beb8c23 MR |
14032 | /** |
14033 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
14034 | * @plane: drm plane to prepare for | |
14035 | * @fb: framebuffer to prepare for presentation | |
14036 | * | |
14037 | * Prepares a framebuffer for usage on a display plane. Generally this | |
14038 | * involves pinning the underlying object and updating the frontbuffer tracking | |
14039 | * bits. Some older platforms need special physical address handling for | |
14040 | * cursor planes. | |
14041 | * | |
f935675f ML |
14042 | * Must be called with struct_mutex held. |
14043 | * | |
6beb8c23 MR |
14044 | * Returns 0 on success, negative error code on failure. |
14045 | */ | |
14046 | int | |
14047 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 14048 | const struct drm_plane_state *new_state) |
465c120c MR |
14049 | { |
14050 | struct drm_device *dev = plane->dev; | |
844f9111 | 14051 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 14052 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14053 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c37efb99 | 14054 | struct reservation_object *resv; |
6beb8c23 | 14055 | int ret = 0; |
465c120c | 14056 | |
1ee49399 | 14057 | if (!obj && !old_obj) |
465c120c MR |
14058 | return 0; |
14059 | ||
5008e874 ML |
14060 | if (old_obj) { |
14061 | struct drm_crtc_state *crtc_state = | |
14062 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
14063 | ||
14064 | /* Big Hammer, we also need to ensure that any pending | |
14065 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14066 | * current scanout is retired before unpinning the old | |
14067 | * framebuffer. Note that we rely on userspace rendering | |
14068 | * into the buffer attached to the pipe they are waiting | |
14069 | * on. If not, userspace generates a GPU hang with IPEHR | |
14070 | * point to the MI_WAIT_FOR_EVENT. | |
14071 | * | |
14072 | * This should only fail upon a hung GPU, in which case we | |
14073 | * can safely continue. | |
14074 | */ | |
14075 | if (needs_modeset(crtc_state)) | |
14076 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
f4457ae7 CW |
14077 | if (ret) { |
14078 | /* GPU hangs should have been swallowed by the wait */ | |
14079 | WARN_ON(ret == -EIO); | |
f935675f | 14080 | return ret; |
f4457ae7 | 14081 | } |
5008e874 ML |
14082 | } |
14083 | ||
c37efb99 CW |
14084 | if (!obj) |
14085 | return 0; | |
14086 | ||
5a21b665 | 14087 | /* For framebuffer backed by dmabuf, wait for fence */ |
c37efb99 CW |
14088 | resv = i915_gem_object_get_dmabuf_resv(obj); |
14089 | if (resv) { | |
5a21b665 DV |
14090 | long lret; |
14091 | ||
c37efb99 | 14092 | lret = reservation_object_wait_timeout_rcu(resv, false, true, |
5a21b665 DV |
14093 | MAX_SCHEDULE_TIMEOUT); |
14094 | if (lret == -ERESTARTSYS) | |
14095 | return lret; | |
14096 | ||
14097 | WARN(lret < 0, "waiting returns %li\n", lret); | |
14098 | } | |
14099 | ||
c37efb99 | 14100 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
6beb8c23 MR |
14101 | INTEL_INFO(dev)->cursor_needs_physical) { |
14102 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
14103 | ret = i915_gem_object_attach_phys(obj, align); | |
14104 | if (ret) | |
14105 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
14106 | } else { | |
3465c580 | 14107 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 14108 | } |
465c120c | 14109 | |
c37efb99 | 14110 | if (ret == 0) { |
6c9c1b38 DV |
14111 | struct intel_plane_state *plane_state = |
14112 | to_intel_plane_state(new_state); | |
7580d774 | 14113 | |
6c9c1b38 DV |
14114 | i915_gem_request_assign(&plane_state->wait_req, |
14115 | obj->last_write_req); | |
7580d774 | 14116 | } |
fdd508a6 | 14117 | |
6beb8c23 MR |
14118 | return ret; |
14119 | } | |
14120 | ||
38f3ce3a MR |
14121 | /** |
14122 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14123 | * @plane: drm plane to clean up for | |
14124 | * @fb: old framebuffer that was on plane | |
14125 | * | |
14126 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14127 | * |
14128 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14129 | */ |
14130 | void | |
14131 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 14132 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
14133 | { |
14134 | struct drm_device *dev = plane->dev; | |
7580d774 | 14135 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
14136 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14137 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14138 | |
7580d774 ML |
14139 | old_intel_state = to_intel_plane_state(old_state); |
14140 | ||
1ee49399 | 14141 | if (!obj && !old_obj) |
38f3ce3a MR |
14142 | return; |
14143 | ||
1ee49399 ML |
14144 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
14145 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 14146 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 | 14147 | |
7580d774 | 14148 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); |
465c120c MR |
14149 | } |
14150 | ||
6156a456 CK |
14151 | int |
14152 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14153 | { | |
14154 | int max_scale; | |
14155 | struct drm_device *dev; | |
14156 | struct drm_i915_private *dev_priv; | |
14157 | int crtc_clock, cdclk; | |
14158 | ||
bf8a0af0 | 14159 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14160 | return DRM_PLANE_HELPER_NO_SCALING; |
14161 | ||
14162 | dev = intel_crtc->base.dev; | |
14163 | dev_priv = dev->dev_private; | |
14164 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 14165 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14166 | |
54bf1ce6 | 14167 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14168 | return DRM_PLANE_HELPER_NO_SCALING; |
14169 | ||
14170 | /* | |
14171 | * skl max scale is lower of: | |
14172 | * close to 3 but not 3, -1 is for that purpose | |
14173 | * or | |
14174 | * cdclk/crtc_clock | |
14175 | */ | |
14176 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14177 | ||
14178 | return max_scale; | |
14179 | } | |
14180 | ||
465c120c | 14181 | static int |
3c692a41 | 14182 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14183 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14184 | struct intel_plane_state *state) |
14185 | { | |
2b875c22 MR |
14186 | struct drm_crtc *crtc = state->base.crtc; |
14187 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 14188 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14189 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14190 | bool can_position = false; | |
465c120c | 14191 | |
693bdc28 VS |
14192 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
14193 | /* use scaler when colorkey is not required */ | |
14194 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14195 | min_scale = 1; | |
14196 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14197 | } | |
d8106366 | 14198 | can_position = true; |
6156a456 | 14199 | } |
d8106366 | 14200 | |
061e4b8d ML |
14201 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14202 | &state->dst, &state->clip, | |
9b8b013d | 14203 | state->base.rotation, |
da20eabd ML |
14204 | min_scale, max_scale, |
14205 | can_position, true, | |
14206 | &state->visible); | |
14af293f GP |
14207 | } |
14208 | ||
5a21b665 DV |
14209 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14210 | struct drm_crtc_state *old_crtc_state) | |
14211 | { | |
14212 | struct drm_device *dev = crtc->dev; | |
14213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14214 | struct intel_crtc_state *old_intel_state = | |
14215 | to_intel_crtc_state(old_crtc_state); | |
14216 | bool modeset = needs_modeset(crtc->state); | |
14217 | ||
14218 | /* Perform vblank evasion around commit operation */ | |
14219 | intel_pipe_update_start(intel_crtc); | |
14220 | ||
14221 | if (modeset) | |
14222 | return; | |
14223 | ||
14224 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14225 | intel_color_set_csc(crtc->state); | |
14226 | intel_color_load_luts(crtc->state); | |
14227 | } | |
14228 | ||
14229 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14230 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14231 | else if (INTEL_INFO(dev)->gen >= 9) | |
14232 | skl_detach_scalers(intel_crtc); | |
14233 | } | |
14234 | ||
14235 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
14236 | struct drm_crtc_state *old_crtc_state) | |
14237 | { | |
14238 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14239 | ||
14240 | intel_pipe_update_end(intel_crtc, NULL); | |
14241 | } | |
14242 | ||
cf4c7c12 | 14243 | /** |
4a3b8769 MR |
14244 | * intel_plane_destroy - destroy a plane |
14245 | * @plane: plane to destroy | |
cf4c7c12 | 14246 | * |
4a3b8769 MR |
14247 | * Common destruction function for all types of planes (primary, cursor, |
14248 | * sprite). | |
cf4c7c12 | 14249 | */ |
4a3b8769 | 14250 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 14251 | { |
69ae561f VS |
14252 | if (!plane) |
14253 | return; | |
14254 | ||
465c120c | 14255 | drm_plane_cleanup(plane); |
69ae561f | 14256 | kfree(to_intel_plane(plane)); |
465c120c MR |
14257 | } |
14258 | ||
65a3fea0 | 14259 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14260 | .update_plane = drm_atomic_helper_update_plane, |
14261 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14262 | .destroy = intel_plane_destroy, |
c196e1d6 | 14263 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14264 | .atomic_get_property = intel_plane_atomic_get_property, |
14265 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14266 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14267 | .atomic_destroy_state = intel_plane_destroy_state, | |
14268 | ||
465c120c MR |
14269 | }; |
14270 | ||
14271 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14272 | int pipe) | |
14273 | { | |
fca0ce2a VS |
14274 | struct intel_plane *primary = NULL; |
14275 | struct intel_plane_state *state = NULL; | |
465c120c | 14276 | const uint32_t *intel_primary_formats; |
45e3743a | 14277 | unsigned int num_formats; |
fca0ce2a | 14278 | int ret; |
465c120c MR |
14279 | |
14280 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
fca0ce2a VS |
14281 | if (!primary) |
14282 | goto fail; | |
465c120c | 14283 | |
8e7d688b | 14284 | state = intel_create_plane_state(&primary->base); |
fca0ce2a VS |
14285 | if (!state) |
14286 | goto fail; | |
8e7d688b | 14287 | primary->base.state = &state->base; |
ea2c67bb | 14288 | |
465c120c MR |
14289 | primary->can_scale = false; |
14290 | primary->max_downscale = 1; | |
6156a456 CK |
14291 | if (INTEL_INFO(dev)->gen >= 9) { |
14292 | primary->can_scale = true; | |
af99ceda | 14293 | state->scaler_id = -1; |
6156a456 | 14294 | } |
465c120c MR |
14295 | primary->pipe = pipe; |
14296 | primary->plane = pipe; | |
a9ff8714 | 14297 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14298 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14299 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14300 | primary->plane = !pipe; | |
14301 | ||
6c0fd451 DL |
14302 | if (INTEL_INFO(dev)->gen >= 9) { |
14303 | intel_primary_formats = skl_primary_formats; | |
14304 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14305 | |
14306 | primary->update_plane = skylake_update_primary_plane; | |
14307 | primary->disable_plane = skylake_disable_primary_plane; | |
14308 | } else if (HAS_PCH_SPLIT(dev)) { | |
14309 | intel_primary_formats = i965_primary_formats; | |
14310 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14311 | ||
14312 | primary->update_plane = ironlake_update_primary_plane; | |
14313 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14314 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14315 | intel_primary_formats = i965_primary_formats; |
14316 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14317 | |
14318 | primary->update_plane = i9xx_update_primary_plane; | |
14319 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14320 | } else { |
14321 | intel_primary_formats = i8xx_primary_formats; | |
14322 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14323 | |
14324 | primary->update_plane = i9xx_update_primary_plane; | |
14325 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14326 | } |
14327 | ||
38573dc1 VS |
14328 | if (INTEL_INFO(dev)->gen >= 9) |
14329 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14330 | &intel_plane_funcs, | |
14331 | intel_primary_formats, num_formats, | |
14332 | DRM_PLANE_TYPE_PRIMARY, | |
14333 | "plane 1%c", pipe_name(pipe)); | |
14334 | else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
14335 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14336 | &intel_plane_funcs, | |
14337 | intel_primary_formats, num_formats, | |
14338 | DRM_PLANE_TYPE_PRIMARY, | |
14339 | "primary %c", pipe_name(pipe)); | |
14340 | else | |
14341 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14342 | &intel_plane_funcs, | |
14343 | intel_primary_formats, num_formats, | |
14344 | DRM_PLANE_TYPE_PRIMARY, | |
14345 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
14346 | if (ret) |
14347 | goto fail; | |
48404c1e | 14348 | |
3b7a5119 SJ |
14349 | if (INTEL_INFO(dev)->gen >= 4) |
14350 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14351 | |
ea2c67bb MR |
14352 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14353 | ||
465c120c | 14354 | return &primary->base; |
fca0ce2a VS |
14355 | |
14356 | fail: | |
14357 | kfree(state); | |
14358 | kfree(primary); | |
14359 | ||
14360 | return NULL; | |
465c120c MR |
14361 | } |
14362 | ||
3b7a5119 SJ |
14363 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14364 | { | |
14365 | if (!dev->mode_config.rotation_property) { | |
14366 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14367 | BIT(DRM_ROTATE_180); | |
14368 | ||
14369 | if (INTEL_INFO(dev)->gen >= 9) | |
14370 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14371 | ||
14372 | dev->mode_config.rotation_property = | |
14373 | drm_mode_create_rotation_property(dev, flags); | |
14374 | } | |
14375 | if (dev->mode_config.rotation_property) | |
14376 | drm_object_attach_property(&plane->base.base, | |
14377 | dev->mode_config.rotation_property, | |
14378 | plane->base.state->rotation); | |
14379 | } | |
14380 | ||
3d7d6510 | 14381 | static int |
852e787c | 14382 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14383 | struct intel_crtc_state *crtc_state, |
852e787c | 14384 | struct intel_plane_state *state) |
3d7d6510 | 14385 | { |
061e4b8d | 14386 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14387 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14388 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14389 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14390 | unsigned stride; |
14391 | int ret; | |
3d7d6510 | 14392 | |
061e4b8d ML |
14393 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14394 | &state->dst, &state->clip, | |
9b8b013d | 14395 | state->base.rotation, |
3d7d6510 MR |
14396 | DRM_PLANE_HELPER_NO_SCALING, |
14397 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14398 | true, true, &state->visible); |
757f9a3e GP |
14399 | if (ret) |
14400 | return ret; | |
14401 | ||
757f9a3e GP |
14402 | /* if we want to turn off the cursor ignore width and height */ |
14403 | if (!obj) | |
da20eabd | 14404 | return 0; |
757f9a3e | 14405 | |
757f9a3e | 14406 | /* Check for which cursor types we support */ |
061e4b8d | 14407 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14408 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14409 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14410 | return -EINVAL; |
14411 | } | |
14412 | ||
ea2c67bb MR |
14413 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14414 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14415 | DRM_DEBUG_KMS("buffer is too small\n"); |
14416 | return -ENOMEM; | |
14417 | } | |
14418 | ||
3a656b54 | 14419 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14420 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14421 | return -EINVAL; |
32b7eeec MR |
14422 | } |
14423 | ||
b29ec92c VS |
14424 | /* |
14425 | * There's something wrong with the cursor on CHV pipe C. | |
14426 | * If it straddles the left edge of the screen then | |
14427 | * moving it away from the edge or disabling it often | |
14428 | * results in a pipe underrun, and often that can lead to | |
14429 | * dead pipe (constant underrun reported, and it scans | |
14430 | * out just a solid color). To recover from that, the | |
14431 | * display power well must be turned off and on again. | |
14432 | * Refuse the put the cursor into that compromised position. | |
14433 | */ | |
14434 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14435 | state->visible && state->base.crtc_x < 0) { | |
14436 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14437 | return -EINVAL; | |
14438 | } | |
14439 | ||
da20eabd | 14440 | return 0; |
852e787c | 14441 | } |
3d7d6510 | 14442 | |
a8ad0d8e ML |
14443 | static void |
14444 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14445 | struct drm_crtc *crtc) |
a8ad0d8e | 14446 | { |
f2858021 ML |
14447 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14448 | ||
14449 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14450 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14451 | } |
14452 | ||
f4a2cf29 | 14453 | static void |
55a08b3f ML |
14454 | intel_update_cursor_plane(struct drm_plane *plane, |
14455 | const struct intel_crtc_state *crtc_state, | |
14456 | const struct intel_plane_state *state) | |
852e787c | 14457 | { |
55a08b3f ML |
14458 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14459 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14460 | struct drm_device *dev = plane->dev; |
2b875c22 | 14461 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14462 | uint32_t addr; |
852e787c | 14463 | |
f4a2cf29 | 14464 | if (!obj) |
a912f12f | 14465 | addr = 0; |
f4a2cf29 | 14466 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14467 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14468 | else |
a912f12f | 14469 | addr = obj->phys_handle->busaddr; |
852e787c | 14470 | |
a912f12f | 14471 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14472 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14473 | } |
14474 | ||
3d7d6510 MR |
14475 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14476 | int pipe) | |
14477 | { | |
fca0ce2a VS |
14478 | struct intel_plane *cursor = NULL; |
14479 | struct intel_plane_state *state = NULL; | |
14480 | int ret; | |
3d7d6510 MR |
14481 | |
14482 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
fca0ce2a VS |
14483 | if (!cursor) |
14484 | goto fail; | |
3d7d6510 | 14485 | |
8e7d688b | 14486 | state = intel_create_plane_state(&cursor->base); |
fca0ce2a VS |
14487 | if (!state) |
14488 | goto fail; | |
8e7d688b | 14489 | cursor->base.state = &state->base; |
ea2c67bb | 14490 | |
3d7d6510 MR |
14491 | cursor->can_scale = false; |
14492 | cursor->max_downscale = 1; | |
14493 | cursor->pipe = pipe; | |
14494 | cursor->plane = pipe; | |
a9ff8714 | 14495 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14496 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14497 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14498 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 14499 | |
fca0ce2a VS |
14500 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
14501 | &intel_plane_funcs, | |
14502 | intel_cursor_formats, | |
14503 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
14504 | DRM_PLANE_TYPE_CURSOR, |
14505 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
14506 | if (ret) |
14507 | goto fail; | |
4398ad45 VS |
14508 | |
14509 | if (INTEL_INFO(dev)->gen >= 4) { | |
14510 | if (!dev->mode_config.rotation_property) | |
14511 | dev->mode_config.rotation_property = | |
14512 | drm_mode_create_rotation_property(dev, | |
14513 | BIT(DRM_ROTATE_0) | | |
14514 | BIT(DRM_ROTATE_180)); | |
14515 | if (dev->mode_config.rotation_property) | |
14516 | drm_object_attach_property(&cursor->base.base, | |
14517 | dev->mode_config.rotation_property, | |
8e7d688b | 14518 | state->base.rotation); |
4398ad45 VS |
14519 | } |
14520 | ||
af99ceda CK |
14521 | if (INTEL_INFO(dev)->gen >=9) |
14522 | state->scaler_id = -1; | |
14523 | ||
ea2c67bb MR |
14524 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14525 | ||
3d7d6510 | 14526 | return &cursor->base; |
fca0ce2a VS |
14527 | |
14528 | fail: | |
14529 | kfree(state); | |
14530 | kfree(cursor); | |
14531 | ||
14532 | return NULL; | |
3d7d6510 MR |
14533 | } |
14534 | ||
549e2bfb CK |
14535 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14536 | struct intel_crtc_state *crtc_state) | |
14537 | { | |
14538 | int i; | |
14539 | struct intel_scaler *intel_scaler; | |
14540 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14541 | ||
14542 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14543 | intel_scaler = &scaler_state->scalers[i]; | |
14544 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14545 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14546 | } | |
14547 | ||
14548 | scaler_state->scaler_id = -1; | |
14549 | } | |
14550 | ||
b358d0a6 | 14551 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14552 | { |
fbee40df | 14553 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14554 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14555 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14556 | struct drm_plane *primary = NULL; |
14557 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14558 | int ret; |
79e53945 | 14559 | |
955382f3 | 14560 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14561 | if (intel_crtc == NULL) |
14562 | return; | |
14563 | ||
f5de6e07 ACO |
14564 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14565 | if (!crtc_state) | |
14566 | goto fail; | |
550acefd ACO |
14567 | intel_crtc->config = crtc_state; |
14568 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14569 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14570 | |
549e2bfb CK |
14571 | /* initialize shared scalers */ |
14572 | if (INTEL_INFO(dev)->gen >= 9) { | |
14573 | if (pipe == PIPE_C) | |
14574 | intel_crtc->num_scalers = 1; | |
14575 | else | |
14576 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14577 | ||
14578 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14579 | } | |
14580 | ||
465c120c | 14581 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14582 | if (!primary) |
14583 | goto fail; | |
14584 | ||
14585 | cursor = intel_cursor_plane_create(dev, pipe); | |
14586 | if (!cursor) | |
14587 | goto fail; | |
14588 | ||
465c120c | 14589 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
4d5d72b7 VS |
14590 | cursor, &intel_crtc_funcs, |
14591 | "pipe %c", pipe_name(pipe)); | |
3d7d6510 MR |
14592 | if (ret) |
14593 | goto fail; | |
79e53945 | 14594 | |
1f1c2e24 VS |
14595 | /* |
14596 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14597 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14598 | */ |
80824003 JB |
14599 | intel_crtc->pipe = pipe; |
14600 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14601 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14602 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14603 | intel_crtc->plane = !pipe; |
80824003 JB |
14604 | } |
14605 | ||
4b0e333e CW |
14606 | intel_crtc->cursor_base = ~0; |
14607 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14608 | intel_crtc->cursor_size = ~0; |
8d7849db | 14609 | |
852eb00d VS |
14610 | intel_crtc->wm.cxsr_allowed = true; |
14611 | ||
22fd0fab JB |
14612 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14613 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14614 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14615 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14616 | ||
79e53945 | 14617 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14618 | |
8563b1e8 LL |
14619 | intel_color_init(&intel_crtc->base); |
14620 | ||
87b6b101 | 14621 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14622 | return; |
14623 | ||
14624 | fail: | |
69ae561f VS |
14625 | intel_plane_destroy(primary); |
14626 | intel_plane_destroy(cursor); | |
f5de6e07 | 14627 | kfree(crtc_state); |
3d7d6510 | 14628 | kfree(intel_crtc); |
79e53945 JB |
14629 | } |
14630 | ||
752aa88a JB |
14631 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14632 | { | |
14633 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14634 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14635 | |
51fd371b | 14636 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14637 | |
d3babd3f | 14638 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14639 | return INVALID_PIPE; |
14640 | ||
14641 | return to_intel_crtc(encoder->crtc)->pipe; | |
14642 | } | |
14643 | ||
08d7b3d1 | 14644 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14645 | struct drm_file *file) |
08d7b3d1 | 14646 | { |
08d7b3d1 | 14647 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14648 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14649 | struct intel_crtc *crtc; |
08d7b3d1 | 14650 | |
7707e653 | 14651 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 14652 | if (!drmmode_crtc) |
3f2c2057 | 14653 | return -ENOENT; |
08d7b3d1 | 14654 | |
7707e653 | 14655 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14656 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14657 | |
c05422d5 | 14658 | return 0; |
08d7b3d1 CW |
14659 | } |
14660 | ||
66a9278e | 14661 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14662 | { |
66a9278e DV |
14663 | struct drm_device *dev = encoder->base.dev; |
14664 | struct intel_encoder *source_encoder; | |
79e53945 | 14665 | int index_mask = 0; |
79e53945 JB |
14666 | int entry = 0; |
14667 | ||
b2784e15 | 14668 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14669 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14670 | index_mask |= (1 << entry); |
14671 | ||
79e53945 JB |
14672 | entry++; |
14673 | } | |
4ef69c7a | 14674 | |
79e53945 JB |
14675 | return index_mask; |
14676 | } | |
14677 | ||
4d302442 CW |
14678 | static bool has_edp_a(struct drm_device *dev) |
14679 | { | |
14680 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14681 | ||
14682 | if (!IS_MOBILE(dev)) | |
14683 | return false; | |
14684 | ||
14685 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14686 | return false; | |
14687 | ||
e3589908 | 14688 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14689 | return false; |
14690 | ||
14691 | return true; | |
14692 | } | |
14693 | ||
84b4e042 JB |
14694 | static bool intel_crt_present(struct drm_device *dev) |
14695 | { | |
14696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14697 | ||
884497ed DL |
14698 | if (INTEL_INFO(dev)->gen >= 9) |
14699 | return false; | |
14700 | ||
cf404ce4 | 14701 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14702 | return false; |
14703 | ||
14704 | if (IS_CHERRYVIEW(dev)) | |
14705 | return false; | |
14706 | ||
65e472e4 VS |
14707 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14708 | return false; | |
14709 | ||
70ac54d0 VS |
14710 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14711 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14712 | return false; | |
14713 | ||
e4abb733 | 14714 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14715 | return false; |
14716 | ||
14717 | return true; | |
14718 | } | |
14719 | ||
79e53945 JB |
14720 | static void intel_setup_outputs(struct drm_device *dev) |
14721 | { | |
725e30ad | 14722 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14723 | struct intel_encoder *encoder; |
cb0953d7 | 14724 | bool dpd_is_edp = false; |
79e53945 | 14725 | |
97a824e1 ID |
14726 | /* |
14727 | * intel_edp_init_connector() depends on this completing first, to | |
14728 | * prevent the registeration of both eDP and LVDS and the incorrect | |
14729 | * sharing of the PPS. | |
14730 | */ | |
c9093354 | 14731 | intel_lvds_init(dev); |
79e53945 | 14732 | |
84b4e042 | 14733 | if (intel_crt_present(dev)) |
79935fca | 14734 | intel_crt_init(dev); |
cb0953d7 | 14735 | |
c776eb2e VK |
14736 | if (IS_BROXTON(dev)) { |
14737 | /* | |
14738 | * FIXME: Broxton doesn't support port detection via the | |
14739 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14740 | * detect the ports. | |
14741 | */ | |
14742 | intel_ddi_init(dev, PORT_A); | |
14743 | intel_ddi_init(dev, PORT_B); | |
14744 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
14745 | |
14746 | intel_dsi_init(dev); | |
c776eb2e | 14747 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
14748 | int found; |
14749 | ||
de31facd JB |
14750 | /* |
14751 | * Haswell uses DDI functions to detect digital outputs. | |
14752 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14753 | * it's there. | |
14754 | */ | |
77179400 | 14755 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14756 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14757 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14758 | intel_ddi_init(dev, PORT_A); |
14759 | ||
14760 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14761 | * register */ | |
14762 | found = I915_READ(SFUSE_STRAP); | |
14763 | ||
14764 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14765 | intel_ddi_init(dev, PORT_B); | |
14766 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14767 | intel_ddi_init(dev, PORT_C); | |
14768 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14769 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14770 | /* |
14771 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14772 | */ | |
ef11bdb3 | 14773 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14774 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14775 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14776 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14777 | intel_ddi_init(dev, PORT_E); | |
14778 | ||
0e72a5b5 | 14779 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14780 | int found; |
5d8a7752 | 14781 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14782 | |
14783 | if (has_edp_a(dev)) | |
14784 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14785 | |
dc0fa718 | 14786 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14787 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14788 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14789 | if (!found) |
e2debe91 | 14790 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14791 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14792 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14793 | } |
14794 | ||
dc0fa718 | 14795 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14796 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14797 | |
dc0fa718 | 14798 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14799 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14800 | |
5eb08b69 | 14801 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14802 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14803 | |
270b3042 | 14804 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14805 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14806 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
22f35042 | 14807 | bool has_edp, has_port; |
457c52d8 | 14808 | |
e17ac6db VS |
14809 | /* |
14810 | * The DP_DETECTED bit is the latched state of the DDC | |
14811 | * SDA pin at boot. However since eDP doesn't require DDC | |
14812 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14813 | * eDP ports may have been muxed to an alternate function. | |
14814 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14815 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14816 | * detect eDP ports. | |
22f35042 VS |
14817 | * |
14818 | * Sadly the straps seem to be missing sometimes even for HDMI | |
14819 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
14820 | * and VBT for the presence of the port. Additionally we can't | |
14821 | * trust the port type the VBT declares as we've seen at least | |
14822 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 14823 | */ |
457c52d8 | 14824 | has_edp = intel_dp_is_edp(dev, PORT_B); |
22f35042 VS |
14825 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
14826 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
457c52d8 | 14827 | has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); |
22f35042 | 14828 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 14829 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
585a94b8 | 14830 | |
457c52d8 | 14831 | has_edp = intel_dp_is_edp(dev, PORT_C); |
22f35042 VS |
14832 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
14833 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
457c52d8 | 14834 | has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); |
22f35042 | 14835 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 14836 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
19c03924 | 14837 | |
9418c1f1 | 14838 | if (IS_CHERRYVIEW(dev)) { |
22f35042 VS |
14839 | /* |
14840 | * eDP not supported on port D, | |
14841 | * so no need to worry about it | |
14842 | */ | |
14843 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
14844 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
e66eb81d | 14845 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
22f35042 VS |
14846 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
14847 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
9418c1f1 VS |
14848 | } |
14849 | ||
3cfca973 | 14850 | intel_dsi_init(dev); |
09da55dc | 14851 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14852 | bool found = false; |
7d57382e | 14853 | |
e2debe91 | 14854 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14855 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14856 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14857 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14858 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14859 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14860 | } |
27185ae1 | 14861 | |
3fec3d2f | 14862 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14863 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14864 | } |
13520b05 KH |
14865 | |
14866 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14867 | |
e2debe91 | 14868 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14869 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14870 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14871 | } |
27185ae1 | 14872 | |
e2debe91 | 14873 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14874 | |
3fec3d2f | 14875 | if (IS_G4X(dev)) { |
b01f2c3a | 14876 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14877 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14878 | } |
3fec3d2f | 14879 | if (IS_G4X(dev)) |
ab9d7c30 | 14880 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14881 | } |
27185ae1 | 14882 | |
3fec3d2f | 14883 | if (IS_G4X(dev) && |
e7281eab | 14884 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14885 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14886 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14887 | intel_dvo_init(dev); |
14888 | ||
103a196f | 14889 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14890 | intel_tv_init(dev); |
14891 | ||
0bc12bcb | 14892 | intel_psr_init(dev); |
7c8f8a70 | 14893 | |
b2784e15 | 14894 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14895 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14896 | encoder->base.possible_clones = | |
66a9278e | 14897 | intel_encoder_clones(encoder); |
79e53945 | 14898 | } |
47356eb6 | 14899 | |
dde86e2d | 14900 | intel_init_pch_refclk(dev); |
270b3042 DV |
14901 | |
14902 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14903 | } |
14904 | ||
14905 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14906 | { | |
60a5ca01 | 14907 | struct drm_device *dev = fb->dev; |
79e53945 | 14908 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14909 | |
ef2d633e | 14910 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14911 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14912 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14913 | drm_gem_object_unreference(&intel_fb->obj->base); |
14914 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14915 | kfree(intel_fb); |
14916 | } | |
14917 | ||
14918 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14919 | struct drm_file *file, |
79e53945 JB |
14920 | unsigned int *handle) |
14921 | { | |
14922 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14923 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14924 | |
cc917ab4 CW |
14925 | if (obj->userptr.mm) { |
14926 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14927 | return -EINVAL; | |
14928 | } | |
14929 | ||
05394f39 | 14930 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14931 | } |
14932 | ||
86c98588 RV |
14933 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14934 | struct drm_file *file, | |
14935 | unsigned flags, unsigned color, | |
14936 | struct drm_clip_rect *clips, | |
14937 | unsigned num_clips) | |
14938 | { | |
14939 | struct drm_device *dev = fb->dev; | |
14940 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14941 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14942 | ||
14943 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14944 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14945 | mutex_unlock(&dev->struct_mutex); |
14946 | ||
14947 | return 0; | |
14948 | } | |
14949 | ||
79e53945 JB |
14950 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14951 | .destroy = intel_user_framebuffer_destroy, | |
14952 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14953 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14954 | }; |
14955 | ||
b321803d DL |
14956 | static |
14957 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14958 | uint32_t pixel_format) | |
14959 | { | |
14960 | u32 gen = INTEL_INFO(dev)->gen; | |
14961 | ||
14962 | if (gen >= 9) { | |
ac484963 VS |
14963 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14964 | ||
b321803d DL |
14965 | /* "The stride in bytes must not exceed the of the size of 8K |
14966 | * pixels and 32K bytes." | |
14967 | */ | |
ac484963 | 14968 | return min(8192 * cpp, 32768); |
666a4537 | 14969 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14970 | return 32*1024; |
14971 | } else if (gen >= 4) { | |
14972 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14973 | return 16*1024; | |
14974 | else | |
14975 | return 32*1024; | |
14976 | } else if (gen >= 3) { | |
14977 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14978 | return 8*1024; | |
14979 | else | |
14980 | return 16*1024; | |
14981 | } else { | |
14982 | /* XXX DSPC is limited to 4k tiled */ | |
14983 | return 8*1024; | |
14984 | } | |
14985 | } | |
14986 | ||
b5ea642a DV |
14987 | static int intel_framebuffer_init(struct drm_device *dev, |
14988 | struct intel_framebuffer *intel_fb, | |
14989 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14990 | struct drm_i915_gem_object *obj) | |
79e53945 | 14991 | { |
7b49f948 | 14992 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14993 | unsigned int aligned_height; |
79e53945 | 14994 | int ret; |
b321803d | 14995 | u32 pitch_limit, stride_alignment; |
79e53945 | 14996 | |
dd4916c5 DV |
14997 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14998 | ||
2a80eada DV |
14999 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
15000 | /* Enforce that fb modifier and tiling mode match, but only for | |
15001 | * X-tiled. This is needed for FBC. */ | |
15002 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
15003 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
15004 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
15005 | return -EINVAL; | |
15006 | } | |
15007 | } else { | |
15008 | if (obj->tiling_mode == I915_TILING_X) | |
15009 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
15010 | else if (obj->tiling_mode == I915_TILING_Y) { | |
15011 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
15012 | return -EINVAL; | |
15013 | } | |
15014 | } | |
15015 | ||
9a8f0a12 TU |
15016 | /* Passed in modifier sanity checking. */ |
15017 | switch (mode_cmd->modifier[0]) { | |
15018 | case I915_FORMAT_MOD_Y_TILED: | |
15019 | case I915_FORMAT_MOD_Yf_TILED: | |
15020 | if (INTEL_INFO(dev)->gen < 9) { | |
15021 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
15022 | mode_cmd->modifier[0]); | |
15023 | return -EINVAL; | |
15024 | } | |
15025 | case DRM_FORMAT_MOD_NONE: | |
15026 | case I915_FORMAT_MOD_X_TILED: | |
15027 | break; | |
15028 | default: | |
c0f40428 JB |
15029 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
15030 | mode_cmd->modifier[0]); | |
57cd6508 | 15031 | return -EINVAL; |
c16ed4be | 15032 | } |
57cd6508 | 15033 | |
7b49f948 VS |
15034 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
15035 | mode_cmd->modifier[0], | |
b321803d DL |
15036 | mode_cmd->pixel_format); |
15037 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
15038 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
15039 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 15040 | return -EINVAL; |
c16ed4be | 15041 | } |
57cd6508 | 15042 | |
b321803d DL |
15043 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
15044 | mode_cmd->pixel_format); | |
a35cdaa0 | 15045 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
15046 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
15047 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 15048 | "tiled" : "linear", |
a35cdaa0 | 15049 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 15050 | return -EINVAL; |
c16ed4be | 15051 | } |
5d7bd705 | 15052 | |
2a80eada | 15053 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
15054 | mode_cmd->pitches[0] != obj->stride) { |
15055 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
15056 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 15057 | return -EINVAL; |
c16ed4be | 15058 | } |
5d7bd705 | 15059 | |
57779d06 | 15060 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 15061 | switch (mode_cmd->pixel_format) { |
57779d06 | 15062 | case DRM_FORMAT_C8: |
04b3924d VS |
15063 | case DRM_FORMAT_RGB565: |
15064 | case DRM_FORMAT_XRGB8888: | |
15065 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
15066 | break; |
15067 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 15068 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
15069 | DRM_DEBUG("unsupported pixel format: %s\n", |
15070 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15071 | return -EINVAL; |
c16ed4be | 15072 | } |
57779d06 | 15073 | break; |
57779d06 | 15074 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
15075 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
15076 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
15077 | DRM_DEBUG("unsupported pixel format: %s\n", |
15078 | drm_get_format_name(mode_cmd->pixel_format)); | |
15079 | return -EINVAL; | |
15080 | } | |
15081 | break; | |
15082 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15083 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15084 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 15085 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
15086 | DRM_DEBUG("unsupported pixel format: %s\n", |
15087 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15088 | return -EINVAL; |
c16ed4be | 15089 | } |
b5626747 | 15090 | break; |
7531208b | 15091 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 15092 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
15093 | DRM_DEBUG("unsupported pixel format: %s\n", |
15094 | drm_get_format_name(mode_cmd->pixel_format)); | |
15095 | return -EINVAL; | |
15096 | } | |
15097 | break; | |
04b3924d VS |
15098 | case DRM_FORMAT_YUYV: |
15099 | case DRM_FORMAT_UYVY: | |
15100 | case DRM_FORMAT_YVYU: | |
15101 | case DRM_FORMAT_VYUY: | |
c16ed4be | 15102 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
15103 | DRM_DEBUG("unsupported pixel format: %s\n", |
15104 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15105 | return -EINVAL; |
c16ed4be | 15106 | } |
57cd6508 CW |
15107 | break; |
15108 | default: | |
4ee62c76 VS |
15109 | DRM_DEBUG("unsupported pixel format: %s\n", |
15110 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
15111 | return -EINVAL; |
15112 | } | |
15113 | ||
90f9a336 VS |
15114 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15115 | if (mode_cmd->offsets[0] != 0) | |
15116 | return -EINVAL; | |
15117 | ||
ec2c981e | 15118 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
15119 | mode_cmd->pixel_format, |
15120 | mode_cmd->modifier[0]); | |
53155c0a DV |
15121 | /* FIXME drm helper for size checks (especially planar formats)? */ |
15122 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
15123 | return -EINVAL; | |
15124 | ||
c7d73f6a DV |
15125 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15126 | intel_fb->obj = obj; | |
15127 | ||
2d7a215f VS |
15128 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
15129 | ||
79e53945 JB |
15130 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15131 | if (ret) { | |
15132 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15133 | return ret; | |
15134 | } | |
15135 | ||
0b05e1e0 VS |
15136 | intel_fb->obj->framebuffer_references++; |
15137 | ||
79e53945 JB |
15138 | return 0; |
15139 | } | |
15140 | ||
79e53945 JB |
15141 | static struct drm_framebuffer * |
15142 | intel_user_framebuffer_create(struct drm_device *dev, | |
15143 | struct drm_file *filp, | |
1eb83451 | 15144 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15145 | { |
dcb1394e | 15146 | struct drm_framebuffer *fb; |
05394f39 | 15147 | struct drm_i915_gem_object *obj; |
76dc3769 | 15148 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15149 | |
a8ad0bd8 | 15150 | obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0])); |
c8725226 | 15151 | if (&obj->base == NULL) |
cce13ff7 | 15152 | return ERR_PTR(-ENOENT); |
79e53945 | 15153 | |
92907cbb | 15154 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
15155 | if (IS_ERR(fb)) |
15156 | drm_gem_object_unreference_unlocked(&obj->base); | |
15157 | ||
15158 | return fb; | |
79e53945 JB |
15159 | } |
15160 | ||
0695726e | 15161 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 15162 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
15163 | { |
15164 | } | |
15165 | #endif | |
15166 | ||
79e53945 | 15167 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15168 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15169 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15170 | .atomic_check = intel_atomic_check, |
15171 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15172 | .atomic_state_alloc = intel_atomic_state_alloc, |
15173 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15174 | }; |
15175 | ||
88212941 ID |
15176 | /** |
15177 | * intel_init_display_hooks - initialize the display modesetting hooks | |
15178 | * @dev_priv: device private | |
15179 | */ | |
15180 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 15181 | { |
88212941 | 15182 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 15183 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15184 | dev_priv->display.get_initial_plane_config = |
15185 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15186 | dev_priv->display.crtc_compute_clock = |
15187 | haswell_crtc_compute_clock; | |
15188 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15189 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15190 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 15191 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15192 | dev_priv->display.get_initial_plane_config = |
15193 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15194 | dev_priv->display.crtc_compute_clock = |
15195 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15196 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15197 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15198 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 15199 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15200 | dev_priv->display.get_initial_plane_config = |
15201 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15202 | dev_priv->display.crtc_compute_clock = |
15203 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15204 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15205 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 15206 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 15207 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15208 | dev_priv->display.get_initial_plane_config = |
15209 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
15210 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
15211 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
15212 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
15213 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
15214 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15215 | dev_priv->display.get_initial_plane_config = | |
15216 | i9xx_get_initial_plane_config; | |
15217 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
15218 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15219 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
15220 | } else if (IS_G4X(dev_priv)) { |
15221 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15222 | dev_priv->display.get_initial_plane_config = | |
15223 | i9xx_get_initial_plane_config; | |
15224 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
15225 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15226 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
15227 | } else if (IS_PINEVIEW(dev_priv)) { |
15228 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15229 | dev_priv->display.get_initial_plane_config = | |
15230 | i9xx_get_initial_plane_config; | |
15231 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
15232 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15233 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 15234 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 15235 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15236 | dev_priv->display.get_initial_plane_config = |
15237 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15238 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
15239 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
15240 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
15241 | } else { |
15242 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15243 | dev_priv->display.get_initial_plane_config = | |
15244 | i9xx_get_initial_plane_config; | |
15245 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
15246 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15247 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15248 | } |
e70236a8 | 15249 | |
e70236a8 | 15250 | /* Returns the core display clock speed */ |
88212941 | 15251 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
15252 | dev_priv->display.get_display_clock_speed = |
15253 | skylake_get_display_clock_speed; | |
88212941 | 15254 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
15255 | dev_priv->display.get_display_clock_speed = |
15256 | broxton_get_display_clock_speed; | |
88212941 | 15257 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
15258 | dev_priv->display.get_display_clock_speed = |
15259 | broadwell_get_display_clock_speed; | |
88212941 | 15260 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
15261 | dev_priv->display.get_display_clock_speed = |
15262 | haswell_get_display_clock_speed; | |
88212941 | 15263 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
15264 | dev_priv->display.get_display_clock_speed = |
15265 | valleyview_get_display_clock_speed; | |
88212941 | 15266 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
15267 | dev_priv->display.get_display_clock_speed = |
15268 | ilk_get_display_clock_speed; | |
88212941 ID |
15269 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
15270 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
15271 | dev_priv->display.get_display_clock_speed = |
15272 | i945_get_display_clock_speed; | |
88212941 | 15273 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
15274 | dev_priv->display.get_display_clock_speed = |
15275 | gm45_get_display_clock_speed; | |
88212941 | 15276 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
15277 | dev_priv->display.get_display_clock_speed = |
15278 | i965gm_get_display_clock_speed; | |
88212941 | 15279 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
15280 | dev_priv->display.get_display_clock_speed = |
15281 | pnv_get_display_clock_speed; | |
88212941 | 15282 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
15283 | dev_priv->display.get_display_clock_speed = |
15284 | g33_get_display_clock_speed; | |
88212941 | 15285 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
15286 | dev_priv->display.get_display_clock_speed = |
15287 | i915_get_display_clock_speed; | |
88212941 | 15288 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
15289 | dev_priv->display.get_display_clock_speed = |
15290 | i9xx_misc_get_display_clock_speed; | |
88212941 | 15291 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
15292 | dev_priv->display.get_display_clock_speed = |
15293 | i915gm_get_display_clock_speed; | |
88212941 | 15294 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
15295 | dev_priv->display.get_display_clock_speed = |
15296 | i865_get_display_clock_speed; | |
88212941 | 15297 | else if (IS_I85X(dev_priv)) |
e70236a8 | 15298 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15299 | i85x_get_display_clock_speed; |
623e01e5 | 15300 | else { /* 830 */ |
88212941 | 15301 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
15302 | dev_priv->display.get_display_clock_speed = |
15303 | i830_get_display_clock_speed; | |
623e01e5 | 15304 | } |
e70236a8 | 15305 | |
88212941 | 15306 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 15307 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 15308 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 15309 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 15310 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
15311 | /* FIXME: detect B0+ stepping and use auto training */ |
15312 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 15313 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 15314 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
15315 | } |
15316 | ||
15317 | if (IS_BROADWELL(dev_priv)) { | |
15318 | dev_priv->display.modeset_commit_cdclk = | |
15319 | broadwell_modeset_commit_cdclk; | |
15320 | dev_priv->display.modeset_calc_cdclk = | |
15321 | broadwell_modeset_calc_cdclk; | |
88212941 | 15322 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
15323 | dev_priv->display.modeset_commit_cdclk = |
15324 | valleyview_modeset_commit_cdclk; | |
15325 | dev_priv->display.modeset_calc_cdclk = | |
15326 | valleyview_modeset_calc_cdclk; | |
88212941 | 15327 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed | 15328 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 15329 | bxt_modeset_commit_cdclk; |
27c329ed | 15330 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 15331 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
15332 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
15333 | dev_priv->display.modeset_commit_cdclk = | |
15334 | skl_modeset_commit_cdclk; | |
15335 | dev_priv->display.modeset_calc_cdclk = | |
15336 | skl_modeset_calc_cdclk; | |
e70236a8 | 15337 | } |
5a21b665 DV |
15338 | |
15339 | switch (INTEL_INFO(dev_priv)->gen) { | |
15340 | case 2: | |
15341 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15342 | break; | |
15343 | ||
15344 | case 3: | |
15345 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15346 | break; | |
15347 | ||
15348 | case 4: | |
15349 | case 5: | |
15350 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15351 | break; | |
15352 | ||
15353 | case 6: | |
15354 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15355 | break; | |
15356 | case 7: | |
15357 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
15358 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
15359 | break; | |
15360 | case 9: | |
15361 | /* Drop through - unsupported since execlist only. */ | |
15362 | default: | |
15363 | /* Default just returns -ENODEV to indicate unsupported */ | |
15364 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
15365 | } | |
e70236a8 JB |
15366 | } |
15367 | ||
b690e96c JB |
15368 | /* |
15369 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15370 | * resume, or other times. This quirk makes sure that's the case for | |
15371 | * affected systems. | |
15372 | */ | |
0206e353 | 15373 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15374 | { |
15375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15376 | ||
15377 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15378 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15379 | } |
15380 | ||
b6b5d049 VS |
15381 | static void quirk_pipeb_force(struct drm_device *dev) |
15382 | { | |
15383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15384 | ||
15385 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15386 | DRM_INFO("applying pipe b force quirk\n"); | |
15387 | } | |
15388 | ||
435793df KP |
15389 | /* |
15390 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15391 | */ | |
15392 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15393 | { | |
15394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15395 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15396 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15397 | } |
15398 | ||
4dca20ef | 15399 | /* |
5a15ab5b CE |
15400 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15401 | * brightness value | |
4dca20ef CE |
15402 | */ |
15403 | static void quirk_invert_brightness(struct drm_device *dev) | |
15404 | { | |
15405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15406 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15407 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15408 | } |
15409 | ||
9c72cc6f SD |
15410 | /* Some VBT's incorrectly indicate no backlight is present */ |
15411 | static void quirk_backlight_present(struct drm_device *dev) | |
15412 | { | |
15413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15414 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15415 | DRM_INFO("applying backlight present quirk\n"); | |
15416 | } | |
15417 | ||
b690e96c JB |
15418 | struct intel_quirk { |
15419 | int device; | |
15420 | int subsystem_vendor; | |
15421 | int subsystem_device; | |
15422 | void (*hook)(struct drm_device *dev); | |
15423 | }; | |
15424 | ||
5f85f176 EE |
15425 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15426 | struct intel_dmi_quirk { | |
15427 | void (*hook)(struct drm_device *dev); | |
15428 | const struct dmi_system_id (*dmi_id_list)[]; | |
15429 | }; | |
15430 | ||
15431 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15432 | { | |
15433 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15434 | return 1; | |
15435 | } | |
15436 | ||
15437 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15438 | { | |
15439 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15440 | { | |
15441 | .callback = intel_dmi_reverse_brightness, | |
15442 | .ident = "NCR Corporation", | |
15443 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15444 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15445 | }, | |
15446 | }, | |
15447 | { } /* terminating entry */ | |
15448 | }, | |
15449 | .hook = quirk_invert_brightness, | |
15450 | }, | |
15451 | }; | |
15452 | ||
c43b5634 | 15453 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15454 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15455 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15456 | ||
b690e96c JB |
15457 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15458 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15459 | ||
5f080c0f VS |
15460 | /* 830 needs to leave pipe A & dpll A up */ |
15461 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15462 | ||
b6b5d049 VS |
15463 | /* 830 needs to leave pipe B & dpll B up */ |
15464 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15465 | ||
435793df KP |
15466 | /* Lenovo U160 cannot use SSC on LVDS */ |
15467 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15468 | |
15469 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15470 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15471 | |
be505f64 AH |
15472 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15473 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15474 | ||
15475 | /* Acer/eMachines G725 */ | |
15476 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15477 | ||
15478 | /* Acer/eMachines e725 */ | |
15479 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15480 | ||
15481 | /* Acer/Packard Bell NCL20 */ | |
15482 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15483 | ||
15484 | /* Acer Aspire 4736Z */ | |
15485 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15486 | |
15487 | /* Acer Aspire 5336 */ | |
15488 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15489 | |
15490 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15491 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15492 | |
dfb3d47b SD |
15493 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15494 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15495 | ||
b2a9601c | 15496 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15497 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15498 | ||
1b9448b0 JN |
15499 | /* Apple Macbook 4,1 */ |
15500 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15501 | ||
d4967d8c SD |
15502 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15503 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15504 | |
15505 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15506 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15507 | |
15508 | /* Dell Chromebook 11 */ | |
15509 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15510 | |
15511 | /* Dell Chromebook 11 (2015 version) */ | |
15512 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15513 | }; |
15514 | ||
15515 | static void intel_init_quirks(struct drm_device *dev) | |
15516 | { | |
15517 | struct pci_dev *d = dev->pdev; | |
15518 | int i; | |
15519 | ||
15520 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15521 | struct intel_quirk *q = &intel_quirks[i]; | |
15522 | ||
15523 | if (d->device == q->device && | |
15524 | (d->subsystem_vendor == q->subsystem_vendor || | |
15525 | q->subsystem_vendor == PCI_ANY_ID) && | |
15526 | (d->subsystem_device == q->subsystem_device || | |
15527 | q->subsystem_device == PCI_ANY_ID)) | |
15528 | q->hook(dev); | |
15529 | } | |
5f85f176 EE |
15530 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15531 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15532 | intel_dmi_quirks[i].hook(dev); | |
15533 | } | |
b690e96c JB |
15534 | } |
15535 | ||
9cce37f4 JB |
15536 | /* Disable the VGA plane that we never use */ |
15537 | static void i915_disable_vga(struct drm_device *dev) | |
15538 | { | |
15539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15540 | u8 sr1; | |
f0f59a00 | 15541 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15542 | |
2b37c616 | 15543 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15544 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15545 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15546 | sr1 = inb(VGA_SR_DATA); |
15547 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15548 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15549 | udelay(300); | |
15550 | ||
01f5a626 | 15551 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15552 | POSTING_READ(vga_reg); |
15553 | } | |
15554 | ||
f817586c DV |
15555 | void intel_modeset_init_hw(struct drm_device *dev) |
15556 | { | |
1a617b77 ML |
15557 | struct drm_i915_private *dev_priv = dev->dev_private; |
15558 | ||
b6283055 | 15559 | intel_update_cdclk(dev); |
1a617b77 ML |
15560 | |
15561 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15562 | ||
f817586c | 15563 | intel_init_clock_gating(dev); |
dc97997a | 15564 | intel_enable_gt_powersave(dev_priv); |
f817586c DV |
15565 | } |
15566 | ||
d93c0372 MR |
15567 | /* |
15568 | * Calculate what we think the watermarks should be for the state we've read | |
15569 | * out of the hardware and then immediately program those watermarks so that | |
15570 | * we ensure the hardware settings match our internal state. | |
15571 | * | |
15572 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15573 | * current state (which was constructed during hardware readout) and running it | |
15574 | * through the atomic check code to calculate new watermark values in the | |
15575 | * state object. | |
15576 | */ | |
15577 | static void sanitize_watermarks(struct drm_device *dev) | |
15578 | { | |
15579 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15580 | struct drm_atomic_state *state; | |
15581 | struct drm_crtc *crtc; | |
15582 | struct drm_crtc_state *cstate; | |
15583 | struct drm_modeset_acquire_ctx ctx; | |
15584 | int ret; | |
15585 | int i; | |
15586 | ||
15587 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15588 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15589 | return; |
15590 | ||
15591 | /* | |
15592 | * We need to hold connection_mutex before calling duplicate_state so | |
15593 | * that the connector loop is protected. | |
15594 | */ | |
15595 | drm_modeset_acquire_init(&ctx, 0); | |
15596 | retry: | |
0cd1262d | 15597 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15598 | if (ret == -EDEADLK) { |
15599 | drm_modeset_backoff(&ctx); | |
15600 | goto retry; | |
15601 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15602 | goto fail; |
d93c0372 MR |
15603 | } |
15604 | ||
15605 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15606 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15607 | goto fail; |
d93c0372 | 15608 | |
ed4a6a7c MR |
15609 | /* |
15610 | * Hardware readout is the only time we don't want to calculate | |
15611 | * intermediate watermarks (since we don't trust the current | |
15612 | * watermarks). | |
15613 | */ | |
15614 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15615 | ||
d93c0372 MR |
15616 | ret = intel_atomic_check(dev, state); |
15617 | if (ret) { | |
15618 | /* | |
15619 | * If we fail here, it means that the hardware appears to be | |
15620 | * programmed in a way that shouldn't be possible, given our | |
15621 | * understanding of watermark requirements. This might mean a | |
15622 | * mistake in the hardware readout code or a mistake in the | |
15623 | * watermark calculations for a given platform. Raise a WARN | |
15624 | * so that this is noticeable. | |
15625 | * | |
15626 | * If this actually happens, we'll have to just leave the | |
15627 | * BIOS-programmed watermarks untouched and hope for the best. | |
15628 | */ | |
15629 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15630 | goto fail; |
d93c0372 MR |
15631 | } |
15632 | ||
15633 | /* Write calculated watermark values back */ | |
d93c0372 MR |
15634 | for_each_crtc_in_state(state, crtc, cstate, i) { |
15635 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15636 | ||
ed4a6a7c MR |
15637 | cs->wm.need_postvbl_update = true; |
15638 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15639 | } |
15640 | ||
15641 | drm_atomic_state_free(state); | |
0cd1262d | 15642 | fail: |
d93c0372 MR |
15643 | drm_modeset_drop_locks(&ctx); |
15644 | drm_modeset_acquire_fini(&ctx); | |
15645 | } | |
15646 | ||
79e53945 JB |
15647 | void intel_modeset_init(struct drm_device *dev) |
15648 | { | |
72e96d64 JL |
15649 | struct drm_i915_private *dev_priv = to_i915(dev); |
15650 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1fe47785 | 15651 | int sprite, ret; |
8cc87b75 | 15652 | enum pipe pipe; |
46f297fb | 15653 | struct intel_crtc *crtc; |
79e53945 JB |
15654 | |
15655 | drm_mode_config_init(dev); | |
15656 | ||
15657 | dev->mode_config.min_width = 0; | |
15658 | dev->mode_config.min_height = 0; | |
15659 | ||
019d96cb DA |
15660 | dev->mode_config.preferred_depth = 24; |
15661 | dev->mode_config.prefer_shadow = 1; | |
15662 | ||
25bab385 TU |
15663 | dev->mode_config.allow_fb_modifiers = true; |
15664 | ||
e6ecefaa | 15665 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15666 | |
b690e96c JB |
15667 | intel_init_quirks(dev); |
15668 | ||
1fa61106 ED |
15669 | intel_init_pm(dev); |
15670 | ||
e3c74757 BW |
15671 | if (INTEL_INFO(dev)->num_pipes == 0) |
15672 | return; | |
15673 | ||
69f92f67 LW |
15674 | /* |
15675 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15676 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15677 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15678 | * indicates as much. | |
15679 | */ | |
15680 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15681 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15682 | DREF_SSC1_ENABLE); | |
15683 | ||
15684 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15685 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15686 | bios_lvds_use_ssc ? "en" : "dis", | |
15687 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15688 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15689 | } | |
15690 | } | |
15691 | ||
a6c45cf0 CW |
15692 | if (IS_GEN2(dev)) { |
15693 | dev->mode_config.max_width = 2048; | |
15694 | dev->mode_config.max_height = 2048; | |
15695 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15696 | dev->mode_config.max_width = 4096; |
15697 | dev->mode_config.max_height = 4096; | |
79e53945 | 15698 | } else { |
a6c45cf0 CW |
15699 | dev->mode_config.max_width = 8192; |
15700 | dev->mode_config.max_height = 8192; | |
79e53945 | 15701 | } |
068be561 | 15702 | |
dc41c154 VS |
15703 | if (IS_845G(dev) || IS_I865G(dev)) { |
15704 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15705 | dev->mode_config.cursor_height = 1023; | |
15706 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15707 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15708 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15709 | } else { | |
15710 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15711 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15712 | } | |
15713 | ||
72e96d64 | 15714 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 15715 | |
28c97730 | 15716 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15717 | INTEL_INFO(dev)->num_pipes, |
15718 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15719 | |
055e393f | 15720 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15721 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15722 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15723 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15724 | if (ret) |
06da8da2 | 15725 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15726 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15727 | } |
79e53945 JB |
15728 | } |
15729 | ||
bfa7df01 VS |
15730 | intel_update_czclk(dev_priv); |
15731 | intel_update_cdclk(dev); | |
15732 | ||
e72f9fbf | 15733 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15734 | |
b2045352 VS |
15735 | if (dev_priv->max_cdclk_freq == 0) |
15736 | intel_update_max_cdclk(dev); | |
15737 | ||
9cce37f4 JB |
15738 | /* Just disable it once at startup */ |
15739 | i915_disable_vga(dev); | |
79e53945 | 15740 | intel_setup_outputs(dev); |
11be49eb | 15741 | |
6e9f798d | 15742 | drm_modeset_lock_all(dev); |
043e9bda | 15743 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15744 | drm_modeset_unlock_all(dev); |
46f297fb | 15745 | |
d3fcc808 | 15746 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15747 | struct intel_initial_plane_config plane_config = {}; |
15748 | ||
46f297fb JB |
15749 | if (!crtc->active) |
15750 | continue; | |
15751 | ||
46f297fb | 15752 | /* |
46f297fb JB |
15753 | * Note that reserving the BIOS fb up front prevents us |
15754 | * from stuffing other stolen allocations like the ring | |
15755 | * on top. This prevents some ugliness at boot time, and | |
15756 | * can even allow for smooth boot transitions if the BIOS | |
15757 | * fb is large enough for the active pipe configuration. | |
15758 | */ | |
eeebeac5 ML |
15759 | dev_priv->display.get_initial_plane_config(crtc, |
15760 | &plane_config); | |
15761 | ||
15762 | /* | |
15763 | * If the fb is shared between multiple heads, we'll | |
15764 | * just get the first one. | |
15765 | */ | |
15766 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15767 | } |
d93c0372 MR |
15768 | |
15769 | /* | |
15770 | * Make sure hardware watermarks really match the state we read out. | |
15771 | * Note that we need to do this after reconstructing the BIOS fb's | |
15772 | * since the watermark calculation done here will use pstate->fb. | |
15773 | */ | |
15774 | sanitize_watermarks(dev); | |
2c7111db CW |
15775 | } |
15776 | ||
7fad798e DV |
15777 | static void intel_enable_pipe_a(struct drm_device *dev) |
15778 | { | |
15779 | struct intel_connector *connector; | |
15780 | struct drm_connector *crt = NULL; | |
15781 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15782 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15783 | |
15784 | /* We can't just switch on the pipe A, we need to set things up with a | |
15785 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15786 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15787 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15788 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15789 | crt = &connector->base; | |
15790 | break; | |
15791 | } | |
15792 | } | |
15793 | ||
15794 | if (!crt) | |
15795 | return; | |
15796 | ||
208bf9fd | 15797 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15798 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15799 | } |
15800 | ||
fa555837 DV |
15801 | static bool |
15802 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15803 | { | |
7eb552ae BW |
15804 | struct drm_device *dev = crtc->base.dev; |
15805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15806 | u32 val; |
fa555837 | 15807 | |
7eb552ae | 15808 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15809 | return true; |
15810 | ||
649636ef | 15811 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15812 | |
15813 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15814 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15815 | return false; | |
15816 | ||
15817 | return true; | |
15818 | } | |
15819 | ||
02e93c35 VS |
15820 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15821 | { | |
15822 | struct drm_device *dev = crtc->base.dev; | |
15823 | struct intel_encoder *encoder; | |
15824 | ||
15825 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15826 | return true; | |
15827 | ||
15828 | return false; | |
15829 | } | |
15830 | ||
dd756198 VS |
15831 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15832 | { | |
15833 | struct drm_device *dev = encoder->base.dev; | |
15834 | struct intel_connector *connector; | |
15835 | ||
15836 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15837 | return true; | |
15838 | ||
15839 | return false; | |
15840 | } | |
15841 | ||
24929352 DV |
15842 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15843 | { | |
15844 | struct drm_device *dev = crtc->base.dev; | |
15845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4d1de975 | 15846 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15847 | |
24929352 | 15848 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15849 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15850 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15851 | ||
15852 | I915_WRITE(reg, | |
15853 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15854 | } | |
24929352 | 15855 | |
d3eaf884 | 15856 | /* restore vblank interrupts to correct state */ |
9625604c | 15857 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15858 | if (crtc->active) { |
f9cd7b88 VS |
15859 | struct intel_plane *plane; |
15860 | ||
9625604c | 15861 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15862 | |
15863 | /* Disable everything but the primary plane */ | |
15864 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15865 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15866 | continue; | |
15867 | ||
15868 | plane->disable_plane(&plane->base, &crtc->base); | |
15869 | } | |
9625604c | 15870 | } |
d3eaf884 | 15871 | |
24929352 | 15872 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15873 | * disable the crtc (and hence change the state) if it is wrong. Note |
15874 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15875 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15876 | bool plane; |
15877 | ||
78108b7c VS |
15878 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
15879 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
15880 | |
15881 | /* Pipe has the wrong plane attached and the plane is active. | |
15882 | * Temporarily change the plane mapping and disable everything | |
15883 | * ... */ | |
15884 | plane = crtc->plane; | |
b70709a6 | 15885 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15886 | crtc->plane = !plane; |
b17d48e2 | 15887 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15888 | crtc->plane = plane; |
24929352 | 15889 | } |
24929352 | 15890 | |
7fad798e DV |
15891 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15892 | crtc->pipe == PIPE_A && !crtc->active) { | |
15893 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15894 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15895 | * call below we restore the pipe to the right state, but leave | |
15896 | * the required bits on. */ | |
15897 | intel_enable_pipe_a(dev); | |
15898 | } | |
15899 | ||
24929352 DV |
15900 | /* Adjust the state of the output pipe according to whether we |
15901 | * have active connectors/encoders. */ | |
842e0307 | 15902 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15903 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15904 | |
a3ed6aad | 15905 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15906 | /* |
15907 | * We start out with underrun reporting disabled to avoid races. | |
15908 | * For correct bookkeeping mark this on active crtcs. | |
15909 | * | |
c5ab3bc0 DV |
15910 | * Also on gmch platforms we dont have any hardware bits to |
15911 | * disable the underrun reporting. Which means we need to start | |
15912 | * out with underrun reporting disabled also on inactive pipes, | |
15913 | * since otherwise we'll complain about the garbage we read when | |
15914 | * e.g. coming up after runtime pm. | |
15915 | * | |
4cc31489 DV |
15916 | * No protection against concurrent access is required - at |
15917 | * worst a fifo underrun happens which also sets this to false. | |
15918 | */ | |
15919 | crtc->cpu_fifo_underrun_disabled = true; | |
15920 | crtc->pch_fifo_underrun_disabled = true; | |
15921 | } | |
24929352 DV |
15922 | } |
15923 | ||
15924 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15925 | { | |
15926 | struct intel_connector *connector; | |
15927 | struct drm_device *dev = encoder->base.dev; | |
15928 | ||
15929 | /* We need to check both for a crtc link (meaning that the | |
15930 | * encoder is active and trying to read from a pipe) and the | |
15931 | * pipe itself being active. */ | |
15932 | bool has_active_crtc = encoder->base.crtc && | |
15933 | to_intel_crtc(encoder->base.crtc)->active; | |
15934 | ||
dd756198 | 15935 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15936 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15937 | encoder->base.base.id, | |
8e329a03 | 15938 | encoder->base.name); |
24929352 DV |
15939 | |
15940 | /* Connector is active, but has no active pipe. This is | |
15941 | * fallout from our resume register restoring. Disable | |
15942 | * the encoder manually again. */ | |
15943 | if (encoder->base.crtc) { | |
15944 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15945 | encoder->base.base.id, | |
8e329a03 | 15946 | encoder->base.name); |
24929352 | 15947 | encoder->disable(encoder); |
a62d1497 VS |
15948 | if (encoder->post_disable) |
15949 | encoder->post_disable(encoder); | |
24929352 | 15950 | } |
7f1950fb | 15951 | encoder->base.crtc = NULL; |
24929352 DV |
15952 | |
15953 | /* Inconsistent output/port/pipe state happens presumably due to | |
15954 | * a bug in one of the get_hw_state functions. Or someplace else | |
15955 | * in our code, like the register restore mess on resume. Clamp | |
15956 | * things to off as a safer default. */ | |
3a3371ff | 15957 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15958 | if (connector->encoder != encoder) |
15959 | continue; | |
7f1950fb EE |
15960 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15961 | connector->base.encoder = NULL; | |
24929352 DV |
15962 | } |
15963 | } | |
15964 | /* Enabled encoders without active connectors will be fixed in | |
15965 | * the crtc fixup. */ | |
15966 | } | |
15967 | ||
04098753 | 15968 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15969 | { |
15970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15971 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15972 | |
04098753 ID |
15973 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15974 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15975 | i915_disable_vga(dev); | |
15976 | } | |
15977 | } | |
15978 | ||
15979 | void i915_redisable_vga(struct drm_device *dev) | |
15980 | { | |
15981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15982 | ||
8dc8a27c PZ |
15983 | /* This function can be called both from intel_modeset_setup_hw_state or |
15984 | * at a very early point in our resume sequence, where the power well | |
15985 | * structures are not yet restored. Since this function is at a very | |
15986 | * paranoid "someone might have enabled VGA while we were not looking" | |
15987 | * level, just check if the power well is enabled instead of trying to | |
15988 | * follow the "don't touch the power well if we don't need it" policy | |
15989 | * the rest of the driver uses. */ | |
6392f847 | 15990 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15991 | return; |
15992 | ||
04098753 | 15993 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15994 | |
15995 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15996 | } |
15997 | ||
f9cd7b88 | 15998 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15999 | { |
f9cd7b88 | 16000 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 16001 | |
f9cd7b88 | 16002 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
16003 | } |
16004 | ||
f9cd7b88 VS |
16005 | /* FIXME read out full plane state for all planes */ |
16006 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 16007 | { |
b26d3ea3 | 16008 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 16009 | struct intel_plane_state *plane_state = |
b26d3ea3 | 16010 | to_intel_plane_state(primary->state); |
d032ffa0 | 16011 | |
19b8d387 | 16012 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
16013 | primary_get_hw_state(to_intel_plane(primary)); |
16014 | ||
16015 | if (plane_state->visible) | |
16016 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
16017 | } |
16018 | ||
30e984df | 16019 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
16020 | { |
16021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
16022 | enum pipe pipe; | |
24929352 DV |
16023 | struct intel_crtc *crtc; |
16024 | struct intel_encoder *encoder; | |
16025 | struct intel_connector *connector; | |
5358901f | 16026 | int i; |
24929352 | 16027 | |
565602d7 ML |
16028 | dev_priv->active_crtcs = 0; |
16029 | ||
d3fcc808 | 16030 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
16031 | struct intel_crtc_state *crtc_state = crtc->config; |
16032 | int pixclk = 0; | |
3b117c8f | 16033 | |
ec2dc6a0 | 16034 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
16035 | memset(crtc_state, 0, sizeof(*crtc_state)); |
16036 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 16037 | |
565602d7 ML |
16038 | crtc_state->base.active = crtc_state->base.enable = |
16039 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
16040 | ||
16041 | crtc->base.enabled = crtc_state->base.enable; | |
16042 | crtc->active = crtc_state->base.active; | |
16043 | ||
16044 | if (crtc_state->base.active) { | |
16045 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
16046 | ||
c89e39f3 | 16047 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 16048 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 16049 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
16050 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
16051 | else | |
16052 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
16053 | |
16054 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
16055 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
16056 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
16057 | } |
16058 | ||
16059 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 16060 | |
f9cd7b88 | 16061 | readout_plane_state(crtc); |
24929352 | 16062 | |
78108b7c VS |
16063 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
16064 | crtc->base.base.id, crtc->base.name, | |
24929352 DV |
16065 | crtc->active ? "enabled" : "disabled"); |
16066 | } | |
16067 | ||
5358901f DV |
16068 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16069 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16070 | ||
2edd6443 ACO |
16071 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16072 | &pll->config.hw_state); | |
3e369b76 | 16073 | pll->config.crtc_mask = 0; |
d3fcc808 | 16074 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16075 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16076 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16077 | } |
2dd66ebd | 16078 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16079 | |
1e6f2ddc | 16080 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16081 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16082 | } |
16083 | ||
b2784e15 | 16084 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16085 | pipe = 0; |
16086 | ||
16087 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
16088 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16089 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 16090 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16091 | } else { |
16092 | encoder->base.crtc = NULL; | |
16093 | } | |
16094 | ||
6f2bcceb | 16095 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 16096 | encoder->base.base.id, |
8e329a03 | 16097 | encoder->base.name, |
24929352 | 16098 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 16099 | pipe_name(pipe)); |
24929352 DV |
16100 | } |
16101 | ||
3a3371ff | 16102 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16103 | if (connector->get_hw_state(connector)) { |
16104 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16105 | |
16106 | encoder = connector->encoder; | |
16107 | connector->base.encoder = &encoder->base; | |
16108 | ||
16109 | if (encoder->base.crtc && | |
16110 | encoder->base.crtc->state->active) { | |
16111 | /* | |
16112 | * This has to be done during hardware readout | |
16113 | * because anything calling .crtc_disable may | |
16114 | * rely on the connector_mask being accurate. | |
16115 | */ | |
16116 | encoder->base.crtc->state->connector_mask |= | |
16117 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16118 | encoder->base.crtc->state->encoder_mask |= |
16119 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16120 | } |
16121 | ||
24929352 DV |
16122 | } else { |
16123 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16124 | connector->base.encoder = NULL; | |
16125 | } | |
16126 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
16127 | connector->base.base.id, | |
c23cc417 | 16128 | connector->base.name, |
24929352 DV |
16129 | connector->base.encoder ? "enabled" : "disabled"); |
16130 | } | |
7f4c6284 VS |
16131 | |
16132 | for_each_intel_crtc(dev, crtc) { | |
16133 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16134 | ||
16135 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16136 | if (crtc->base.state->active) { | |
16137 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16138 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16139 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16140 | ||
16141 | /* | |
16142 | * The initial mode needs to be set in order to keep | |
16143 | * the atomic core happy. It wants a valid mode if the | |
16144 | * crtc's enabled, so we do the above call. | |
16145 | * | |
16146 | * At this point some state updated by the connectors | |
16147 | * in their ->detect() callback has not run yet, so | |
16148 | * no recalculation can be done yet. | |
16149 | * | |
16150 | * Even if we could do a recalculation and modeset | |
16151 | * right now it would cause a double modeset if | |
16152 | * fbdev or userspace chooses a different initial mode. | |
16153 | * | |
16154 | * If that happens, someone indicated they wanted a | |
16155 | * mode change, which means it's safe to do a full | |
16156 | * recalculation. | |
16157 | */ | |
16158 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16159 | |
16160 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16161 | update_scanline_offset(crtc); | |
7f4c6284 | 16162 | } |
e3b247da VS |
16163 | |
16164 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16165 | } |
30e984df DV |
16166 | } |
16167 | ||
043e9bda ML |
16168 | /* Scan out the current hw modeset state, |
16169 | * and sanitizes it to the current state | |
16170 | */ | |
16171 | static void | |
16172 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
16173 | { |
16174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
16175 | enum pipe pipe; | |
30e984df DV |
16176 | struct intel_crtc *crtc; |
16177 | struct intel_encoder *encoder; | |
35c95375 | 16178 | int i; |
30e984df DV |
16179 | |
16180 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16181 | |
16182 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16183 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16184 | intel_sanitize_encoder(encoder); |
16185 | } | |
16186 | ||
055e393f | 16187 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
16188 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16189 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
16190 | intel_dump_pipe_config(crtc, crtc->config, |
16191 | "[setup_hw_state]"); | |
24929352 | 16192 | } |
9a935856 | 16193 | |
d29b2f9d ACO |
16194 | intel_modeset_update_connector_atomic_state(dev); |
16195 | ||
35c95375 DV |
16196 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16197 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16198 | ||
2dd66ebd | 16199 | if (!pll->on || pll->active_mask) |
35c95375 DV |
16200 | continue; |
16201 | ||
16202 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
16203 | ||
2edd6443 | 16204 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
16205 | pll->on = false; |
16206 | } | |
16207 | ||
666a4537 | 16208 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
16209 | vlv_wm_get_hw_state(dev); |
16210 | else if (IS_GEN9(dev)) | |
3078999f PB |
16211 | skl_wm_get_hw_state(dev); |
16212 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 16213 | ilk_wm_get_hw_state(dev); |
292b990e ML |
16214 | |
16215 | for_each_intel_crtc(dev, crtc) { | |
16216 | unsigned long put_domains; | |
16217 | ||
74bff5f9 | 16218 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
16219 | if (WARN_ON(put_domains)) |
16220 | modeset_put_power_domains(dev_priv, put_domains); | |
16221 | } | |
16222 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
16223 | |
16224 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 16225 | } |
7d0bc1ea | 16226 | |
043e9bda ML |
16227 | void intel_display_resume(struct drm_device *dev) |
16228 | { | |
e2c8b870 ML |
16229 | struct drm_i915_private *dev_priv = to_i915(dev); |
16230 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
16231 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 16232 | int ret; |
e2c8b870 | 16233 | bool setup = false; |
f30da187 | 16234 | |
e2c8b870 | 16235 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 16236 | |
ea49c9ac ML |
16237 | /* |
16238 | * This is a cludge because with real atomic modeset mode_config.mutex | |
16239 | * won't be taken. Unfortunately some probed state like | |
16240 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
16241 | * it here for now. | |
16242 | */ | |
16243 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 16244 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 16245 | |
e2c8b870 ML |
16246 | retry: |
16247 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 16248 | |
e2c8b870 ML |
16249 | if (ret == 0 && !setup) { |
16250 | setup = true; | |
043e9bda | 16251 | |
e2c8b870 ML |
16252 | intel_modeset_setup_hw_state(dev); |
16253 | i915_redisable_vga(dev); | |
45e2b5f6 | 16254 | } |
8af6cf88 | 16255 | |
e2c8b870 ML |
16256 | if (ret == 0 && state) { |
16257 | struct drm_crtc_state *crtc_state; | |
16258 | struct drm_crtc *crtc; | |
16259 | int i; | |
043e9bda | 16260 | |
e2c8b870 ML |
16261 | state->acquire_ctx = &ctx; |
16262 | ||
e3d5457c VS |
16263 | /* ignore any reset values/BIOS leftovers in the WM registers */ |
16264 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
16265 | ||
e2c8b870 ML |
16266 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
16267 | /* | |
16268 | * Force recalculation even if we restore | |
16269 | * current state. With fast modeset this may not result | |
16270 | * in a modeset when the state is compatible. | |
16271 | */ | |
16272 | crtc_state->mode_changed = true; | |
16273 | } | |
16274 | ||
16275 | ret = drm_atomic_commit(state); | |
043e9bda ML |
16276 | } |
16277 | ||
e2c8b870 ML |
16278 | if (ret == -EDEADLK) { |
16279 | drm_modeset_backoff(&ctx); | |
16280 | goto retry; | |
16281 | } | |
043e9bda | 16282 | |
e2c8b870 ML |
16283 | drm_modeset_drop_locks(&ctx); |
16284 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 16285 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 16286 | |
e2c8b870 ML |
16287 | if (ret) { |
16288 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16289 | drm_atomic_state_free(state); | |
16290 | } | |
2c7111db CW |
16291 | } |
16292 | ||
16293 | void intel_modeset_gem_init(struct drm_device *dev) | |
16294 | { | |
dc97997a | 16295 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 16296 | struct drm_crtc *c; |
2ff8fde1 | 16297 | struct drm_i915_gem_object *obj; |
e0d6149b | 16298 | int ret; |
484b41dd | 16299 | |
dc97997a | 16300 | intel_init_gt_powersave(dev_priv); |
ae48434c | 16301 | |
1833b134 | 16302 | intel_modeset_init_hw(dev); |
02e792fb | 16303 | |
1ee8da6d | 16304 | intel_setup_overlay(dev_priv); |
484b41dd JB |
16305 | |
16306 | /* | |
16307 | * Make sure any fbs we allocated at startup are properly | |
16308 | * pinned & fenced. When we do the allocation it's too early | |
16309 | * for this. | |
16310 | */ | |
70e1e0ec | 16311 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16312 | obj = intel_fb_obj(c->primary->fb); |
16313 | if (obj == NULL) | |
484b41dd JB |
16314 | continue; |
16315 | ||
e0d6149b | 16316 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
16317 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
16318 | c->primary->state->rotation); | |
e0d6149b TU |
16319 | mutex_unlock(&dev->struct_mutex); |
16320 | if (ret) { | |
484b41dd JB |
16321 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16322 | to_intel_crtc(c)->pipe); | |
66e514c1 | 16323 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 16324 | c->primary->fb = NULL; |
36750f28 | 16325 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 16326 | update_state_fb(c->primary); |
36750f28 | 16327 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16328 | } |
16329 | } | |
1ebaa0b9 CW |
16330 | } |
16331 | ||
16332 | int intel_connector_register(struct drm_connector *connector) | |
16333 | { | |
16334 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
16335 | int ret; | |
16336 | ||
16337 | ret = intel_backlight_device_register(intel_connector); | |
16338 | if (ret) | |
16339 | goto err; | |
16340 | ||
16341 | return 0; | |
0962c3c9 | 16342 | |
1ebaa0b9 CW |
16343 | err: |
16344 | return ret; | |
79e53945 JB |
16345 | } |
16346 | ||
c191eca1 | 16347 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 16348 | { |
e63d87c0 | 16349 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 16350 | |
e63d87c0 | 16351 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 16352 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
16353 | } |
16354 | ||
79e53945 JB |
16355 | void intel_modeset_cleanup(struct drm_device *dev) |
16356 | { | |
652c393a | 16357 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 16358 | |
dc97997a | 16359 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 16360 | |
fd0c0642 DV |
16361 | /* |
16362 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16363 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16364 | * experience fancy races otherwise. |
16365 | */ | |
2aeb7d3a | 16366 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16367 | |
fd0c0642 DV |
16368 | /* |
16369 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16370 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16371 | */ | |
f87ea761 | 16372 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16373 | |
723bfd70 JB |
16374 | intel_unregister_dsm_handler(); |
16375 | ||
c937ab3e | 16376 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16377 | |
1630fe75 CW |
16378 | /* flush any delayed tasks or pending work */ |
16379 | flush_scheduled_work(); | |
16380 | ||
79e53945 | 16381 | drm_mode_config_cleanup(dev); |
4d7bb011 | 16382 | |
1ee8da6d | 16383 | intel_cleanup_overlay(dev_priv); |
ae48434c | 16384 | |
dc97997a | 16385 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
16386 | |
16387 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16388 | } |
16389 | ||
df0e9248 CW |
16390 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16391 | struct intel_encoder *encoder) | |
16392 | { | |
16393 | connector->encoder = encoder; | |
16394 | drm_mode_connector_attach_encoder(&connector->base, | |
16395 | &encoder->base); | |
79e53945 | 16396 | } |
28d52043 DA |
16397 | |
16398 | /* | |
16399 | * set vga decode state - true == enable VGA decode | |
16400 | */ | |
16401 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16402 | { | |
16403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16404 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16405 | u16 gmch_ctrl; |
16406 | ||
75fa041d CW |
16407 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16408 | DRM_ERROR("failed to read control word\n"); | |
16409 | return -EIO; | |
16410 | } | |
16411 | ||
c0cc8a55 CW |
16412 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16413 | return 0; | |
16414 | ||
28d52043 DA |
16415 | if (state) |
16416 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16417 | else | |
16418 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16419 | |
16420 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16421 | DRM_ERROR("failed to write control word\n"); | |
16422 | return -EIO; | |
16423 | } | |
16424 | ||
28d52043 DA |
16425 | return 0; |
16426 | } | |
c4a1d9e4 | 16427 | |
c4a1d9e4 | 16428 | struct intel_display_error_state { |
ff57f1b0 PZ |
16429 | |
16430 | u32 power_well_driver; | |
16431 | ||
63b66e5b CW |
16432 | int num_transcoders; |
16433 | ||
c4a1d9e4 CW |
16434 | struct intel_cursor_error_state { |
16435 | u32 control; | |
16436 | u32 position; | |
16437 | u32 base; | |
16438 | u32 size; | |
52331309 | 16439 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16440 | |
16441 | struct intel_pipe_error_state { | |
ddf9c536 | 16442 | bool power_domain_on; |
c4a1d9e4 | 16443 | u32 source; |
f301b1e1 | 16444 | u32 stat; |
52331309 | 16445 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16446 | |
16447 | struct intel_plane_error_state { | |
16448 | u32 control; | |
16449 | u32 stride; | |
16450 | u32 size; | |
16451 | u32 pos; | |
16452 | u32 addr; | |
16453 | u32 surface; | |
16454 | u32 tile_offset; | |
52331309 | 16455 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16456 | |
16457 | struct intel_transcoder_error_state { | |
ddf9c536 | 16458 | bool power_domain_on; |
63b66e5b CW |
16459 | enum transcoder cpu_transcoder; |
16460 | ||
16461 | u32 conf; | |
16462 | ||
16463 | u32 htotal; | |
16464 | u32 hblank; | |
16465 | u32 hsync; | |
16466 | u32 vtotal; | |
16467 | u32 vblank; | |
16468 | u32 vsync; | |
16469 | } transcoder[4]; | |
c4a1d9e4 CW |
16470 | }; |
16471 | ||
16472 | struct intel_display_error_state * | |
c033666a | 16473 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 16474 | { |
c4a1d9e4 | 16475 | struct intel_display_error_state *error; |
63b66e5b CW |
16476 | int transcoders[] = { |
16477 | TRANSCODER_A, | |
16478 | TRANSCODER_B, | |
16479 | TRANSCODER_C, | |
16480 | TRANSCODER_EDP, | |
16481 | }; | |
c4a1d9e4 CW |
16482 | int i; |
16483 | ||
c033666a | 16484 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
16485 | return NULL; |
16486 | ||
9d1cb914 | 16487 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16488 | if (error == NULL) |
16489 | return NULL; | |
16490 | ||
c033666a | 16491 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
16492 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16493 | ||
055e393f | 16494 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16495 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16496 | __intel_display_power_is_enabled(dev_priv, |
16497 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16498 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16499 | continue; |
16500 | ||
5efb3e28 VS |
16501 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16502 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16503 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16504 | |
16505 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16506 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 16507 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 16508 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16509 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16510 | } | |
c033666a | 16511 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 16512 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 16513 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
16514 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
16515 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16516 | } | |
16517 | ||
c4a1d9e4 | 16518 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16519 | |
c033666a | 16520 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 16521 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16522 | } |
16523 | ||
4d1de975 | 16524 | /* Note: this does not include DSI transcoders. */ |
c033666a | 16525 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 16526 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
16527 | error->num_transcoders++; /* Account for eDP. */ |
16528 | ||
16529 | for (i = 0; i < error->num_transcoders; i++) { | |
16530 | enum transcoder cpu_transcoder = transcoders[i]; | |
16531 | ||
ddf9c536 | 16532 | error->transcoder[i].power_domain_on = |
f458ebbc | 16533 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16534 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16535 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16536 | continue; |
16537 | ||
63b66e5b CW |
16538 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16539 | ||
16540 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16541 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16542 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16543 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16544 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16545 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16546 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16547 | } |
16548 | ||
16549 | return error; | |
16550 | } | |
16551 | ||
edc3d884 MK |
16552 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16553 | ||
c4a1d9e4 | 16554 | void |
edc3d884 | 16555 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16556 | struct drm_device *dev, |
16557 | struct intel_display_error_state *error) | |
16558 | { | |
055e393f | 16559 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16560 | int i; |
16561 | ||
63b66e5b CW |
16562 | if (!error) |
16563 | return; | |
16564 | ||
edc3d884 | 16565 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16566 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16567 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16568 | error->power_well_driver); |
055e393f | 16569 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16570 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16571 | err_printf(m, " Power: %s\n", |
87ad3212 | 16572 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16573 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16574 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16575 | |
16576 | err_printf(m, "Plane [%d]:\n", i); | |
16577 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16578 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16579 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16580 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16581 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16582 | } |
4b71a570 | 16583 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16584 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16585 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16586 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16587 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16588 | } |
16589 | ||
edc3d884 MK |
16590 | err_printf(m, "Cursor [%d]:\n", i); |
16591 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16592 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16593 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16594 | } |
63b66e5b CW |
16595 | |
16596 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16597 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16598 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16599 | err_printf(m, " Power: %s\n", |
87ad3212 | 16600 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16601 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16602 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16603 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16604 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16605 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16606 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16607 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16608 | } | |
c4a1d9e4 | 16609 | } |