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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
db18b6a6 | 39 | #include "intel_dsi.h" |
e5510fac | 40 | #include "i915_trace.h" |
319c1d42 | 41 | #include <drm/drm_atomic.h> |
c196e1d6 | 42 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
43 | #include <drm/drm_dp_helper.h> |
44 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
45 | #include <drm/drm_plane_helper.h> |
46 | #include <drm/drm_rect.h> | |
c0f372b3 | 47 | #include <linux/dma_remapping.h> |
fd8e058a AG |
48 | #include <linux/reservation.h> |
49 | #include <linux/dma-buf.h> | |
79e53945 | 50 | |
465c120c | 51 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 52 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
53 | DRM_FORMAT_C8, |
54 | DRM_FORMAT_RGB565, | |
465c120c | 55 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 56 | DRM_FORMAT_XRGB8888, |
465c120c MR |
57 | }; |
58 | ||
59 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 60 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
61 | DRM_FORMAT_C8, |
62 | DRM_FORMAT_RGB565, | |
63 | DRM_FORMAT_XRGB8888, | |
64 | DRM_FORMAT_XBGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_XBGR2101010, | |
67 | }; | |
68 | ||
69 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
70 | DRM_FORMAT_C8, |
71 | DRM_FORMAT_RGB565, | |
72 | DRM_FORMAT_XRGB8888, | |
465c120c | 73 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 74 | DRM_FORMAT_ARGB8888, |
465c120c MR |
75 | DRM_FORMAT_ABGR8888, |
76 | DRM_FORMAT_XRGB2101010, | |
465c120c | 77 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
78 | DRM_FORMAT_YUYV, |
79 | DRM_FORMAT_YVYU, | |
80 | DRM_FORMAT_UYVY, | |
81 | DRM_FORMAT_VYUY, | |
465c120c MR |
82 | }; |
83 | ||
3d7d6510 MR |
84 | /* Cursor formats */ |
85 | static const uint32_t intel_cursor_formats[] = { | |
86 | DRM_FORMAT_ARGB8888, | |
87 | }; | |
88 | ||
f1f644dc | 89 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 90 | struct intel_crtc_state *pipe_config); |
18442d08 | 91 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 92 | struct intel_crtc_state *pipe_config); |
f1f644dc | 93 | |
eb1bfe80 JB |
94 | static int intel_framebuffer_init(struct drm_device *dev, |
95 | struct intel_framebuffer *ifb, | |
96 | struct drm_mode_fb_cmd2 *mode_cmd, | |
97 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
98 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
99 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 100 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
102 | struct intel_link_m_n *m_n, |
103 | struct intel_link_m_n *m2_n2); | |
29407aab | 104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 106 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 107 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
d288f65f | 109 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 110 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
111 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
112 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
113 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
114 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 119 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 120 | |
d4906093 | 121 | struct intel_limit { |
4c5def93 ACO |
122 | struct { |
123 | int min, max; | |
124 | } dot, vco, n, m, m1, m2, p, p1; | |
125 | ||
126 | struct { | |
127 | int dot_limit; | |
128 | int p2_slow, p2_fast; | |
129 | } p2; | |
d4906093 | 130 | }; |
79e53945 | 131 | |
bfa7df01 VS |
132 | /* returns HPLL frequency in kHz */ |
133 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
134 | { | |
135 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
136 | ||
137 | /* Obtain SKU information */ | |
138 | mutex_lock(&dev_priv->sb_lock); | |
139 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
140 | CCK_FUSE_HPLL_FREQ_MASK; | |
141 | mutex_unlock(&dev_priv->sb_lock); | |
142 | ||
143 | return vco_freq[hpll_freq] * 1000; | |
144 | } | |
145 | ||
c30fec65 VS |
146 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
147 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
148 | { |
149 | u32 val; | |
150 | int divider; | |
151 | ||
bfa7df01 VS |
152 | mutex_lock(&dev_priv->sb_lock); |
153 | val = vlv_cck_read(dev_priv, reg); | |
154 | mutex_unlock(&dev_priv->sb_lock); | |
155 | ||
156 | divider = val & CCK_FREQUENCY_VALUES; | |
157 | ||
158 | WARN((val & CCK_FREQUENCY_STATUS) != | |
159 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
160 | "%s change in progress\n", name); | |
161 | ||
c30fec65 VS |
162 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
163 | } | |
164 | ||
165 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
166 | const char *name, u32 reg) | |
167 | { | |
168 | if (dev_priv->hpll_freq == 0) | |
169 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
170 | ||
171 | return vlv_get_cck_clock(dev_priv, name, reg, | |
172 | dev_priv->hpll_freq); | |
bfa7df01 VS |
173 | } |
174 | ||
e7dc33f3 VS |
175 | static int |
176 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 177 | { |
e7dc33f3 VS |
178 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
179 | } | |
d2acd215 | 180 | |
e7dc33f3 VS |
181 | static int |
182 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
183 | { | |
19ab4ed3 | 184 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
185 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
186 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
187 | } |
188 | ||
e7dc33f3 VS |
189 | static int |
190 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 191 | { |
79e50a4f JN |
192 | uint32_t clkcfg; |
193 | ||
e7dc33f3 | 194 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
195 | clkcfg = I915_READ(CLKCFG); |
196 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
197 | case CLKCFG_FSB_400: | |
e7dc33f3 | 198 | return 100000; |
79e50a4f | 199 | case CLKCFG_FSB_533: |
e7dc33f3 | 200 | return 133333; |
79e50a4f | 201 | case CLKCFG_FSB_667: |
e7dc33f3 | 202 | return 166667; |
79e50a4f | 203 | case CLKCFG_FSB_800: |
e7dc33f3 | 204 | return 200000; |
79e50a4f | 205 | case CLKCFG_FSB_1067: |
e7dc33f3 | 206 | return 266667; |
79e50a4f | 207 | case CLKCFG_FSB_1333: |
e7dc33f3 | 208 | return 333333; |
79e50a4f JN |
209 | /* these two are just a guess; one of them might be right */ |
210 | case CLKCFG_FSB_1600: | |
211 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 212 | return 400000; |
79e50a4f | 213 | default: |
e7dc33f3 | 214 | return 133333; |
79e50a4f JN |
215 | } |
216 | } | |
217 | ||
19ab4ed3 | 218 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
219 | { |
220 | if (HAS_PCH_SPLIT(dev_priv)) | |
221 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
222 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
223 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
224 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
225 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
226 | else | |
227 | return; /* no rawclk on other platforms, or no need to know it */ | |
228 | ||
229 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
230 | } | |
231 | ||
bfa7df01 VS |
232 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
233 | { | |
666a4537 | 234 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
235 | return; |
236 | ||
237 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
238 | CCK_CZ_CLOCK_CONTROL); | |
239 | ||
240 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
241 | } | |
242 | ||
021357ac | 243 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
244 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
245 | const struct intel_crtc_state *pipe_config) | |
021357ac | 246 | { |
21a727b3 VS |
247 | if (HAS_DDI(dev_priv)) |
248 | return pipe_config->port_clock; /* SPLL */ | |
249 | else if (IS_GEN5(dev_priv)) | |
250 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 251 | else |
21a727b3 | 252 | return 270000; |
021357ac CW |
253 | } |
254 | ||
1b6f4958 | 255 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 256 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 257 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 258 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
259 | .m = { .min = 96, .max = 140 }, |
260 | .m1 = { .min = 18, .max = 26 }, | |
261 | .m2 = { .min = 6, .max = 16 }, | |
262 | .p = { .min = 4, .max = 128 }, | |
263 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
264 | .p2 = { .dot_limit = 165000, |
265 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
266 | }; |
267 | ||
1b6f4958 | 268 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 269 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 270 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 271 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
272 | .m = { .min = 96, .max = 140 }, |
273 | .m1 = { .min = 18, .max = 26 }, | |
274 | .m2 = { .min = 6, .max = 16 }, | |
275 | .p = { .min = 4, .max = 128 }, | |
276 | .p1 = { .min = 2, .max = 33 }, | |
277 | .p2 = { .dot_limit = 165000, | |
278 | .p2_slow = 4, .p2_fast = 4 }, | |
279 | }; | |
280 | ||
1b6f4958 | 281 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 282 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 283 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 284 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
285 | .m = { .min = 96, .max = 140 }, |
286 | .m1 = { .min = 18, .max = 26 }, | |
287 | .m2 = { .min = 6, .max = 16 }, | |
288 | .p = { .min = 4, .max = 128 }, | |
289 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
290 | .p2 = { .dot_limit = 165000, |
291 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 292 | }; |
273e27ca | 293 | |
1b6f4958 | 294 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
295 | .dot = { .min = 20000, .max = 400000 }, |
296 | .vco = { .min = 1400000, .max = 2800000 }, | |
297 | .n = { .min = 1, .max = 6 }, | |
298 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
299 | .m1 = { .min = 8, .max = 18 }, |
300 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
301 | .p = { .min = 5, .max = 80 }, |
302 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
303 | .p2 = { .dot_limit = 200000, |
304 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
305 | }; |
306 | ||
1b6f4958 | 307 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
308 | .dot = { .min = 20000, .max = 400000 }, |
309 | .vco = { .min = 1400000, .max = 2800000 }, | |
310 | .n = { .min = 1, .max = 6 }, | |
311 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
312 | .m1 = { .min = 8, .max = 18 }, |
313 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
314 | .p = { .min = 7, .max = 98 }, |
315 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
316 | .p2 = { .dot_limit = 112000, |
317 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
318 | }; |
319 | ||
273e27ca | 320 | |
1b6f4958 | 321 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
322 | .dot = { .min = 25000, .max = 270000 }, |
323 | .vco = { .min = 1750000, .max = 3500000}, | |
324 | .n = { .min = 1, .max = 4 }, | |
325 | .m = { .min = 104, .max = 138 }, | |
326 | .m1 = { .min = 17, .max = 23 }, | |
327 | .m2 = { .min = 5, .max = 11 }, | |
328 | .p = { .min = 10, .max = 30 }, | |
329 | .p1 = { .min = 1, .max = 3}, | |
330 | .p2 = { .dot_limit = 270000, | |
331 | .p2_slow = 10, | |
332 | .p2_fast = 10 | |
044c7c41 | 333 | }, |
e4b36699 KP |
334 | }; |
335 | ||
1b6f4958 | 336 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
337 | .dot = { .min = 22000, .max = 400000 }, |
338 | .vco = { .min = 1750000, .max = 3500000}, | |
339 | .n = { .min = 1, .max = 4 }, | |
340 | .m = { .min = 104, .max = 138 }, | |
341 | .m1 = { .min = 16, .max = 23 }, | |
342 | .m2 = { .min = 5, .max = 11 }, | |
343 | .p = { .min = 5, .max = 80 }, | |
344 | .p1 = { .min = 1, .max = 8}, | |
345 | .p2 = { .dot_limit = 165000, | |
346 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
347 | }; |
348 | ||
1b6f4958 | 349 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
350 | .dot = { .min = 20000, .max = 115000 }, |
351 | .vco = { .min = 1750000, .max = 3500000 }, | |
352 | .n = { .min = 1, .max = 3 }, | |
353 | .m = { .min = 104, .max = 138 }, | |
354 | .m1 = { .min = 17, .max = 23 }, | |
355 | .m2 = { .min = 5, .max = 11 }, | |
356 | .p = { .min = 28, .max = 112 }, | |
357 | .p1 = { .min = 2, .max = 8 }, | |
358 | .p2 = { .dot_limit = 0, | |
359 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 360 | }, |
e4b36699 KP |
361 | }; |
362 | ||
1b6f4958 | 363 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
364 | .dot = { .min = 80000, .max = 224000 }, |
365 | .vco = { .min = 1750000, .max = 3500000 }, | |
366 | .n = { .min = 1, .max = 3 }, | |
367 | .m = { .min = 104, .max = 138 }, | |
368 | .m1 = { .min = 17, .max = 23 }, | |
369 | .m2 = { .min = 5, .max = 11 }, | |
370 | .p = { .min = 14, .max = 42 }, | |
371 | .p1 = { .min = 2, .max = 6 }, | |
372 | .p2 = { .dot_limit = 0, | |
373 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 374 | }, |
e4b36699 KP |
375 | }; |
376 | ||
1b6f4958 | 377 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
378 | .dot = { .min = 20000, .max = 400000}, |
379 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 380 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
381 | .n = { .min = 3, .max = 6 }, |
382 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 383 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
384 | .m1 = { .min = 0, .max = 0 }, |
385 | .m2 = { .min = 0, .max = 254 }, | |
386 | .p = { .min = 5, .max = 80 }, | |
387 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
388 | .p2 = { .dot_limit = 200000, |
389 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
390 | }; |
391 | ||
1b6f4958 | 392 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
393 | .dot = { .min = 20000, .max = 400000 }, |
394 | .vco = { .min = 1700000, .max = 3500000 }, | |
395 | .n = { .min = 3, .max = 6 }, | |
396 | .m = { .min = 2, .max = 256 }, | |
397 | .m1 = { .min = 0, .max = 0 }, | |
398 | .m2 = { .min = 0, .max = 254 }, | |
399 | .p = { .min = 7, .max = 112 }, | |
400 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
401 | .p2 = { .dot_limit = 112000, |
402 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
403 | }; |
404 | ||
273e27ca EA |
405 | /* Ironlake / Sandybridge |
406 | * | |
407 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
408 | * the range value for them is (actual_value - 2). | |
409 | */ | |
1b6f4958 | 410 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
411 | .dot = { .min = 25000, .max = 350000 }, |
412 | .vco = { .min = 1760000, .max = 3510000 }, | |
413 | .n = { .min = 1, .max = 5 }, | |
414 | .m = { .min = 79, .max = 127 }, | |
415 | .m1 = { .min = 12, .max = 22 }, | |
416 | .m2 = { .min = 5, .max = 9 }, | |
417 | .p = { .min = 5, .max = 80 }, | |
418 | .p1 = { .min = 1, .max = 8 }, | |
419 | .p2 = { .dot_limit = 225000, | |
420 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
421 | }; |
422 | ||
1b6f4958 | 423 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
424 | .dot = { .min = 25000, .max = 350000 }, |
425 | .vco = { .min = 1760000, .max = 3510000 }, | |
426 | .n = { .min = 1, .max = 3 }, | |
427 | .m = { .min = 79, .max = 118 }, | |
428 | .m1 = { .min = 12, .max = 22 }, | |
429 | .m2 = { .min = 5, .max = 9 }, | |
430 | .p = { .min = 28, .max = 112 }, | |
431 | .p1 = { .min = 2, .max = 8 }, | |
432 | .p2 = { .dot_limit = 225000, | |
433 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
434 | }; |
435 | ||
1b6f4958 | 436 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
437 | .dot = { .min = 25000, .max = 350000 }, |
438 | .vco = { .min = 1760000, .max = 3510000 }, | |
439 | .n = { .min = 1, .max = 3 }, | |
440 | .m = { .min = 79, .max = 127 }, | |
441 | .m1 = { .min = 12, .max = 22 }, | |
442 | .m2 = { .min = 5, .max = 9 }, | |
443 | .p = { .min = 14, .max = 56 }, | |
444 | .p1 = { .min = 2, .max = 8 }, | |
445 | .p2 = { .dot_limit = 225000, | |
446 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
447 | }; |
448 | ||
273e27ca | 449 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 450 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
451 | .dot = { .min = 25000, .max = 350000 }, |
452 | .vco = { .min = 1760000, .max = 3510000 }, | |
453 | .n = { .min = 1, .max = 2 }, | |
454 | .m = { .min = 79, .max = 126 }, | |
455 | .m1 = { .min = 12, .max = 22 }, | |
456 | .m2 = { .min = 5, .max = 9 }, | |
457 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 458 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
459 | .p2 = { .dot_limit = 225000, |
460 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
461 | }; |
462 | ||
1b6f4958 | 463 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
464 | .dot = { .min = 25000, .max = 350000 }, |
465 | .vco = { .min = 1760000, .max = 3510000 }, | |
466 | .n = { .min = 1, .max = 3 }, | |
467 | .m = { .min = 79, .max = 126 }, | |
468 | .m1 = { .min = 12, .max = 22 }, | |
469 | .m2 = { .min = 5, .max = 9 }, | |
470 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 471 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
472 | .p2 = { .dot_limit = 225000, |
473 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
474 | }; |
475 | ||
1b6f4958 | 476 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
477 | /* |
478 | * These are the data rate limits (measured in fast clocks) | |
479 | * since those are the strictest limits we have. The fast | |
480 | * clock and actual rate limits are more relaxed, so checking | |
481 | * them would make no difference. | |
482 | */ | |
483 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 484 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 485 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
486 | .m1 = { .min = 2, .max = 3 }, |
487 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 488 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 489 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
490 | }; |
491 | ||
1b6f4958 | 492 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
493 | /* |
494 | * These are the data rate limits (measured in fast clocks) | |
495 | * since those are the strictest limits we have. The fast | |
496 | * clock and actual rate limits are more relaxed, so checking | |
497 | * them would make no difference. | |
498 | */ | |
499 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 500 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
501 | .n = { .min = 1, .max = 1 }, |
502 | .m1 = { .min = 2, .max = 2 }, | |
503 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
504 | .p1 = { .min = 2, .max = 4 }, | |
505 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
506 | }; | |
507 | ||
1b6f4958 | 508 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
509 | /* FIXME: find real dot limits */ |
510 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 511 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
512 | .n = { .min = 1, .max = 1 }, |
513 | .m1 = { .min = 2, .max = 2 }, | |
514 | /* FIXME: find real m2 limits */ | |
515 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
516 | .p1 = { .min = 2, .max = 4 }, | |
517 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
518 | }; | |
519 | ||
cdba954e ACO |
520 | static bool |
521 | needs_modeset(struct drm_crtc_state *state) | |
522 | { | |
fc596660 | 523 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
524 | } |
525 | ||
e0638cdf PZ |
526 | /** |
527 | * Returns whether any output on the specified pipe is of the specified type | |
528 | */ | |
4093561b | 529 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 530 | { |
409ee761 | 531 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
532 | struct intel_encoder *encoder; |
533 | ||
409ee761 | 534 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
535 | if (encoder->type == type) |
536 | return true; | |
537 | ||
538 | return false; | |
539 | } | |
540 | ||
d0737e1d ACO |
541 | /** |
542 | * Returns whether any output on the specified pipe will have the specified | |
543 | * type after a staged modeset is complete, i.e., the same as | |
544 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
545 | * encoder->crtc. | |
546 | */ | |
a93e255f ACO |
547 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
548 | int type) | |
d0737e1d | 549 | { |
a93e255f | 550 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 551 | struct drm_connector *connector; |
a93e255f | 552 | struct drm_connector_state *connector_state; |
d0737e1d | 553 | struct intel_encoder *encoder; |
a93e255f ACO |
554 | int i, num_connectors = 0; |
555 | ||
da3ced29 | 556 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
557 | if (connector_state->crtc != crtc_state->base.crtc) |
558 | continue; | |
559 | ||
560 | num_connectors++; | |
d0737e1d | 561 | |
a93e255f ACO |
562 | encoder = to_intel_encoder(connector_state->best_encoder); |
563 | if (encoder->type == type) | |
d0737e1d | 564 | return true; |
a93e255f ACO |
565 | } |
566 | ||
567 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
568 | |
569 | return false; | |
570 | } | |
571 | ||
dccbea3b ID |
572 | /* |
573 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
574 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
575 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
576 | * The helpers' return value is the rate of the clock that is fed to the | |
577 | * display engine's pipe which can be the above fast dot clock rate or a | |
578 | * divided-down version of it. | |
579 | */ | |
f2b115e6 | 580 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 581 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 582 | { |
2177832f SL |
583 | clock->m = clock->m2 + 2; |
584 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 585 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 586 | return 0; |
fb03ac01 VS |
587 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
588 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
589 | |
590 | return clock->dot; | |
2177832f SL |
591 | } |
592 | ||
7429e9d4 DV |
593 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
594 | { | |
595 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
596 | } | |
597 | ||
9e2c8475 | 598 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 599 | { |
7429e9d4 | 600 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 601 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 602 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 603 | return 0; |
fb03ac01 VS |
604 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
605 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
606 | |
607 | return clock->dot; | |
79e53945 JB |
608 | } |
609 | ||
9e2c8475 | 610 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
611 | { |
612 | clock->m = clock->m1 * clock->m2; | |
613 | clock->p = clock->p1 * clock->p2; | |
614 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 615 | return 0; |
589eca67 ID |
616 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
617 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
618 | |
619 | return clock->dot / 5; | |
589eca67 ID |
620 | } |
621 | ||
9e2c8475 | 622 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
623 | { |
624 | clock->m = clock->m1 * clock->m2; | |
625 | clock->p = clock->p1 * clock->p2; | |
626 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 627 | return 0; |
ef9348c8 CML |
628 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
629 | clock->n << 22); | |
630 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
631 | |
632 | return clock->dot / 5; | |
ef9348c8 CML |
633 | } |
634 | ||
7c04d1d9 | 635 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
636 | /** |
637 | * Returns whether the given set of divisors are valid for a given refclk with | |
638 | * the given connectors. | |
639 | */ | |
640 | ||
1b894b59 | 641 | static bool intel_PLL_is_valid(struct drm_device *dev, |
1b6f4958 | 642 | const struct intel_limit *limit, |
9e2c8475 | 643 | const struct dpll *clock) |
79e53945 | 644 | { |
f01b7962 VS |
645 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
646 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 647 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 648 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 649 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 650 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 651 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 652 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 653 | |
666a4537 WB |
654 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
655 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
656 | if (clock->m1 <= clock->m2) |
657 | INTELPllInvalid("m1 <= m2\n"); | |
658 | ||
666a4537 | 659 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
660 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
661 | INTELPllInvalid("p out of range\n"); | |
662 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
663 | INTELPllInvalid("m out of range\n"); | |
664 | } | |
665 | ||
79e53945 | 666 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 667 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
668 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
669 | * connector, etc., rather than just a single range. | |
670 | */ | |
671 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 672 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
673 | |
674 | return true; | |
675 | } | |
676 | ||
3b1429d9 | 677 | static int |
1b6f4958 | 678 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
679 | const struct intel_crtc_state *crtc_state, |
680 | int target) | |
79e53945 | 681 | { |
3b1429d9 | 682 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 683 | |
a93e255f | 684 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 685 | /* |
a210b028 DV |
686 | * For LVDS just rely on its current settings for dual-channel. |
687 | * We haven't figured out how to reliably set up different | |
688 | * single/dual channel state, if we even can. | |
79e53945 | 689 | */ |
1974cad0 | 690 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 691 | return limit->p2.p2_fast; |
79e53945 | 692 | else |
3b1429d9 | 693 | return limit->p2.p2_slow; |
79e53945 JB |
694 | } else { |
695 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 696 | return limit->p2.p2_slow; |
79e53945 | 697 | else |
3b1429d9 | 698 | return limit->p2.p2_fast; |
79e53945 | 699 | } |
3b1429d9 VS |
700 | } |
701 | ||
70e8aa21 ACO |
702 | /* |
703 | * Returns a set of divisors for the desired target clock with the given | |
704 | * refclk, or FALSE. The returned values represent the clock equation: | |
705 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
706 | * | |
707 | * Target and reference clocks are specified in kHz. | |
708 | * | |
709 | * If match_clock is provided, then best_clock P divider must match the P | |
710 | * divider from @match_clock used for LVDS downclocking. | |
711 | */ | |
3b1429d9 | 712 | static bool |
1b6f4958 | 713 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 714 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
715 | int target, int refclk, struct dpll *match_clock, |
716 | struct dpll *best_clock) | |
3b1429d9 VS |
717 | { |
718 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 719 | struct dpll clock; |
3b1429d9 | 720 | int err = target; |
79e53945 | 721 | |
0206e353 | 722 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 723 | |
3b1429d9 VS |
724 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
725 | ||
42158660 ZY |
726 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
727 | clock.m1++) { | |
728 | for (clock.m2 = limit->m2.min; | |
729 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 730 | if (clock.m2 >= clock.m1) |
42158660 ZY |
731 | break; |
732 | for (clock.n = limit->n.min; | |
733 | clock.n <= limit->n.max; clock.n++) { | |
734 | for (clock.p1 = limit->p1.min; | |
735 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
736 | int this_err; |
737 | ||
dccbea3b | 738 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
739 | if (!intel_PLL_is_valid(dev, limit, |
740 | &clock)) | |
741 | continue; | |
742 | if (match_clock && | |
743 | clock.p != match_clock->p) | |
744 | continue; | |
745 | ||
746 | this_err = abs(clock.dot - target); | |
747 | if (this_err < err) { | |
748 | *best_clock = clock; | |
749 | err = this_err; | |
750 | } | |
751 | } | |
752 | } | |
753 | } | |
754 | } | |
755 | ||
756 | return (err != target); | |
757 | } | |
758 | ||
70e8aa21 ACO |
759 | /* |
760 | * Returns a set of divisors for the desired target clock with the given | |
761 | * refclk, or FALSE. The returned values represent the clock equation: | |
762 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
763 | * | |
764 | * Target and reference clocks are specified in kHz. | |
765 | * | |
766 | * If match_clock is provided, then best_clock P divider must match the P | |
767 | * divider from @match_clock used for LVDS downclocking. | |
768 | */ | |
ac58c3f0 | 769 | static bool |
1b6f4958 | 770 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 771 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
772 | int target, int refclk, struct dpll *match_clock, |
773 | struct dpll *best_clock) | |
79e53945 | 774 | { |
3b1429d9 | 775 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 776 | struct dpll clock; |
79e53945 JB |
777 | int err = target; |
778 | ||
0206e353 | 779 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 780 | |
3b1429d9 VS |
781 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
782 | ||
42158660 ZY |
783 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
784 | clock.m1++) { | |
785 | for (clock.m2 = limit->m2.min; | |
786 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
787 | for (clock.n = limit->n.min; |
788 | clock.n <= limit->n.max; clock.n++) { | |
789 | for (clock.p1 = limit->p1.min; | |
790 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
791 | int this_err; |
792 | ||
dccbea3b | 793 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
794 | if (!intel_PLL_is_valid(dev, limit, |
795 | &clock)) | |
79e53945 | 796 | continue; |
cec2f356 SP |
797 | if (match_clock && |
798 | clock.p != match_clock->p) | |
799 | continue; | |
79e53945 JB |
800 | |
801 | this_err = abs(clock.dot - target); | |
802 | if (this_err < err) { | |
803 | *best_clock = clock; | |
804 | err = this_err; | |
805 | } | |
806 | } | |
807 | } | |
808 | } | |
809 | } | |
810 | ||
811 | return (err != target); | |
812 | } | |
813 | ||
997c030c ACO |
814 | /* |
815 | * Returns a set of divisors for the desired target clock with the given | |
816 | * refclk, or FALSE. The returned values represent the clock equation: | |
817 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
818 | * |
819 | * Target and reference clocks are specified in kHz. | |
820 | * | |
821 | * If match_clock is provided, then best_clock P divider must match the P | |
822 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 823 | */ |
d4906093 | 824 | static bool |
1b6f4958 | 825 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 826 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
827 | int target, int refclk, struct dpll *match_clock, |
828 | struct dpll *best_clock) | |
d4906093 | 829 | { |
3b1429d9 | 830 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 831 | struct dpll clock; |
d4906093 | 832 | int max_n; |
3b1429d9 | 833 | bool found = false; |
6ba770dc AJ |
834 | /* approximately equals target * 0.00585 */ |
835 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
836 | |
837 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
838 | |
839 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
840 | ||
d4906093 | 841 | max_n = limit->n.max; |
f77f13e2 | 842 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 843 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 844 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
845 | for (clock.m1 = limit->m1.max; |
846 | clock.m1 >= limit->m1.min; clock.m1--) { | |
847 | for (clock.m2 = limit->m2.max; | |
848 | clock.m2 >= limit->m2.min; clock.m2--) { | |
849 | for (clock.p1 = limit->p1.max; | |
850 | clock.p1 >= limit->p1.min; clock.p1--) { | |
851 | int this_err; | |
852 | ||
dccbea3b | 853 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
854 | if (!intel_PLL_is_valid(dev, limit, |
855 | &clock)) | |
d4906093 | 856 | continue; |
1b894b59 CW |
857 | |
858 | this_err = abs(clock.dot - target); | |
d4906093 ML |
859 | if (this_err < err_most) { |
860 | *best_clock = clock; | |
861 | err_most = this_err; | |
862 | max_n = clock.n; | |
863 | found = true; | |
864 | } | |
865 | } | |
866 | } | |
867 | } | |
868 | } | |
2c07245f ZW |
869 | return found; |
870 | } | |
871 | ||
d5dd62bd ID |
872 | /* |
873 | * Check if the calculated PLL configuration is more optimal compared to the | |
874 | * best configuration and error found so far. Return the calculated error. | |
875 | */ | |
876 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
877 | const struct dpll *calculated_clock, |
878 | const struct dpll *best_clock, | |
d5dd62bd ID |
879 | unsigned int best_error_ppm, |
880 | unsigned int *error_ppm) | |
881 | { | |
9ca3ba01 ID |
882 | /* |
883 | * For CHV ignore the error and consider only the P value. | |
884 | * Prefer a bigger P value based on HW requirements. | |
885 | */ | |
886 | if (IS_CHERRYVIEW(dev)) { | |
887 | *error_ppm = 0; | |
888 | ||
889 | return calculated_clock->p > best_clock->p; | |
890 | } | |
891 | ||
24be4e46 ID |
892 | if (WARN_ON_ONCE(!target_freq)) |
893 | return false; | |
894 | ||
d5dd62bd ID |
895 | *error_ppm = div_u64(1000000ULL * |
896 | abs(target_freq - calculated_clock->dot), | |
897 | target_freq); | |
898 | /* | |
899 | * Prefer a better P value over a better (smaller) error if the error | |
900 | * is small. Ensure this preference for future configurations too by | |
901 | * setting the error to 0. | |
902 | */ | |
903 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
904 | *error_ppm = 0; | |
905 | ||
906 | return true; | |
907 | } | |
908 | ||
909 | return *error_ppm + 10 < best_error_ppm; | |
910 | } | |
911 | ||
65b3d6a9 ACO |
912 | /* |
913 | * Returns a set of divisors for the desired target clock with the given | |
914 | * refclk, or FALSE. The returned values represent the clock equation: | |
915 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
916 | */ | |
a0c4da24 | 917 | static bool |
1b6f4958 | 918 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 919 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
920 | int target, int refclk, struct dpll *match_clock, |
921 | struct dpll *best_clock) | |
a0c4da24 | 922 | { |
a93e255f | 923 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 924 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 925 | struct dpll clock; |
69e4f900 | 926 | unsigned int bestppm = 1000000; |
27e639bf VS |
927 | /* min update 19.2 MHz */ |
928 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 929 | bool found = false; |
a0c4da24 | 930 | |
6b4bf1c4 VS |
931 | target *= 5; /* fast clock */ |
932 | ||
933 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
934 | |
935 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 936 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 937 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 938 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 939 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 940 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 941 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 942 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 943 | unsigned int ppm; |
69e4f900 | 944 | |
6b4bf1c4 VS |
945 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
946 | refclk * clock.m1); | |
947 | ||
dccbea3b | 948 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 949 | |
f01b7962 VS |
950 | if (!intel_PLL_is_valid(dev, limit, |
951 | &clock)) | |
43b0ac53 VS |
952 | continue; |
953 | ||
d5dd62bd ID |
954 | if (!vlv_PLL_is_optimal(dev, target, |
955 | &clock, | |
956 | best_clock, | |
957 | bestppm, &ppm)) | |
958 | continue; | |
6b4bf1c4 | 959 | |
d5dd62bd ID |
960 | *best_clock = clock; |
961 | bestppm = ppm; | |
962 | found = true; | |
a0c4da24 JB |
963 | } |
964 | } | |
965 | } | |
966 | } | |
a0c4da24 | 967 | |
49e497ef | 968 | return found; |
a0c4da24 | 969 | } |
a4fc5ed6 | 970 | |
65b3d6a9 ACO |
971 | /* |
972 | * Returns a set of divisors for the desired target clock with the given | |
973 | * refclk, or FALSE. The returned values represent the clock equation: | |
974 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
975 | */ | |
ef9348c8 | 976 | static bool |
1b6f4958 | 977 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 978 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
979 | int target, int refclk, struct dpll *match_clock, |
980 | struct dpll *best_clock) | |
ef9348c8 | 981 | { |
a93e255f | 982 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 983 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 984 | unsigned int best_error_ppm; |
9e2c8475 | 985 | struct dpll clock; |
ef9348c8 CML |
986 | uint64_t m2; |
987 | int found = false; | |
988 | ||
989 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 990 | best_error_ppm = 1000000; |
ef9348c8 CML |
991 | |
992 | /* | |
993 | * Based on hardware doc, the n always set to 1, and m1 always | |
994 | * set to 2. If requires to support 200Mhz refclk, we need to | |
995 | * revisit this because n may not 1 anymore. | |
996 | */ | |
997 | clock.n = 1, clock.m1 = 2; | |
998 | target *= 5; /* fast clock */ | |
999 | ||
1000 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1001 | for (clock.p2 = limit->p2.p2_fast; | |
1002 | clock.p2 >= limit->p2.p2_slow; | |
1003 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1004 | unsigned int error_ppm; |
ef9348c8 CML |
1005 | |
1006 | clock.p = clock.p1 * clock.p2; | |
1007 | ||
1008 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1009 | clock.n) << 22, refclk * clock.m1); | |
1010 | ||
1011 | if (m2 > INT_MAX/clock.m1) | |
1012 | continue; | |
1013 | ||
1014 | clock.m2 = m2; | |
1015 | ||
dccbea3b | 1016 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1017 | |
1018 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1019 | continue; | |
1020 | ||
9ca3ba01 ID |
1021 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1022 | best_error_ppm, &error_ppm)) | |
1023 | continue; | |
1024 | ||
1025 | *best_clock = clock; | |
1026 | best_error_ppm = error_ppm; | |
1027 | found = true; | |
ef9348c8 CML |
1028 | } |
1029 | } | |
1030 | ||
1031 | return found; | |
1032 | } | |
1033 | ||
5ab7b0b7 | 1034 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 1035 | struct dpll *best_clock) |
5ab7b0b7 | 1036 | { |
65b3d6a9 | 1037 | int refclk = 100000; |
1b6f4958 | 1038 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1039 | |
65b3d6a9 | 1040 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1041 | target_clock, refclk, NULL, best_clock); |
1042 | } | |
1043 | ||
20ddf665 VS |
1044 | bool intel_crtc_active(struct drm_crtc *crtc) |
1045 | { | |
1046 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1047 | ||
1048 | /* Be paranoid as we can arrive here with only partial | |
1049 | * state retrieved from the hardware during setup. | |
1050 | * | |
241bfc38 | 1051 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1052 | * as Haswell has gained clock readout/fastboot support. |
1053 | * | |
66e514c1 | 1054 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1055 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1056 | * |
1057 | * FIXME: The intel_crtc->active here should be switched to | |
1058 | * crtc->state->active once we have proper CRTC states wired up | |
1059 | * for atomic. | |
20ddf665 | 1060 | */ |
c3d1f436 | 1061 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1062 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1063 | } |
1064 | ||
a5c961d1 PZ |
1065 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1066 | enum pipe pipe) | |
1067 | { | |
1068 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1070 | ||
6e3c9717 | 1071 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1072 | } |
1073 | ||
fbf49ea2 VS |
1074 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1075 | { | |
1076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1077 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1078 | u32 line1, line2; |
1079 | u32 line_mask; | |
1080 | ||
1081 | if (IS_GEN2(dev)) | |
1082 | line_mask = DSL_LINEMASK_GEN2; | |
1083 | else | |
1084 | line_mask = DSL_LINEMASK_GEN3; | |
1085 | ||
1086 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1087 | msleep(5); |
fbf49ea2 VS |
1088 | line2 = I915_READ(reg) & line_mask; |
1089 | ||
1090 | return line1 == line2; | |
1091 | } | |
1092 | ||
ab7ad7f6 KP |
1093 | /* |
1094 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1095 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1096 | * |
1097 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1098 | * spinning on the vblank interrupt status bit, since we won't actually | |
1099 | * see an interrupt when the pipe is disabled. | |
1100 | * | |
ab7ad7f6 KP |
1101 | * On Gen4 and above: |
1102 | * wait for the pipe register state bit to turn off | |
1103 | * | |
1104 | * Otherwise: | |
1105 | * wait for the display line value to settle (it usually | |
1106 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1107 | * |
9d0498a2 | 1108 | */ |
575f7ab7 | 1109 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1110 | { |
575f7ab7 | 1111 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1112 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1113 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1114 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1115 | |
1116 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1117 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1118 | |
1119 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1120 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1121 | 100)) | |
284637d9 | 1122 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1123 | } else { |
ab7ad7f6 | 1124 | /* Wait for the display line to settle */ |
fbf49ea2 | 1125 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1126 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1127 | } |
79e53945 JB |
1128 | } |
1129 | ||
b24e7179 | 1130 | /* Only for pre-ILK configs */ |
55607e8a DV |
1131 | void assert_pll(struct drm_i915_private *dev_priv, |
1132 | enum pipe pipe, bool state) | |
b24e7179 | 1133 | { |
b24e7179 JB |
1134 | u32 val; |
1135 | bool cur_state; | |
1136 | ||
649636ef | 1137 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1138 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1139 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1140 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1141 | onoff(state), onoff(cur_state)); |
b24e7179 | 1142 | } |
b24e7179 | 1143 | |
23538ef1 | 1144 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1145 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1146 | { |
1147 | u32 val; | |
1148 | bool cur_state; | |
1149 | ||
a580516d | 1150 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1151 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1152 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1153 | |
1154 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1155 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1156 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1157 | onoff(state), onoff(cur_state)); |
23538ef1 | 1158 | } |
23538ef1 | 1159 | |
040484af JB |
1160 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1161 | enum pipe pipe, bool state) | |
1162 | { | |
040484af | 1163 | bool cur_state; |
ad80a810 PZ |
1164 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1165 | pipe); | |
040484af | 1166 | |
2d1fe073 | 1167 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1168 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1169 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1170 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1171 | } else { |
649636ef | 1172 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1173 | cur_state = !!(val & FDI_TX_ENABLE); |
1174 | } | |
e2c719b7 | 1175 | I915_STATE_WARN(cur_state != state, |
040484af | 1176 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1177 | onoff(state), onoff(cur_state)); |
040484af JB |
1178 | } |
1179 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1180 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1181 | ||
1182 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1183 | enum pipe pipe, bool state) | |
1184 | { | |
040484af JB |
1185 | u32 val; |
1186 | bool cur_state; | |
1187 | ||
649636ef | 1188 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1189 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1190 | I915_STATE_WARN(cur_state != state, |
040484af | 1191 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1192 | onoff(state), onoff(cur_state)); |
040484af JB |
1193 | } |
1194 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1195 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1196 | ||
1197 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1198 | enum pipe pipe) | |
1199 | { | |
040484af JB |
1200 | u32 val; |
1201 | ||
1202 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1203 | if (IS_GEN5(dev_priv)) |
040484af JB |
1204 | return; |
1205 | ||
bf507ef7 | 1206 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1207 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1208 | return; |
1209 | ||
649636ef | 1210 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1211 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1212 | } |
1213 | ||
55607e8a DV |
1214 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1215 | enum pipe pipe, bool state) | |
040484af | 1216 | { |
040484af | 1217 | u32 val; |
55607e8a | 1218 | bool cur_state; |
040484af | 1219 | |
649636ef | 1220 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1221 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1222 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1223 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1224 | onoff(state), onoff(cur_state)); |
040484af JB |
1225 | } |
1226 | ||
b680c37a DV |
1227 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1228 | enum pipe pipe) | |
ea0760cf | 1229 | { |
bedd4dba | 1230 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1231 | i915_reg_t pp_reg; |
ea0760cf JB |
1232 | u32 val; |
1233 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1234 | bool locked = true; |
ea0760cf | 1235 | |
bedd4dba JN |
1236 | if (WARN_ON(HAS_DDI(dev))) |
1237 | return; | |
1238 | ||
1239 | if (HAS_PCH_SPLIT(dev)) { | |
1240 | u32 port_sel; | |
1241 | ||
ea0760cf | 1242 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1243 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1244 | ||
1245 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1246 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1247 | panel_pipe = PIPE_B; | |
1248 | /* XXX: else fix for eDP */ | |
666a4537 | 1249 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1250 | /* presumably write lock depends on pipe, not port select */ |
1251 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1252 | panel_pipe = pipe; | |
ea0760cf JB |
1253 | } else { |
1254 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1255 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1256 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1257 | } |
1258 | ||
1259 | val = I915_READ(pp_reg); | |
1260 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1261 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1262 | locked = false; |
1263 | ||
e2c719b7 | 1264 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1265 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1266 | pipe_name(pipe)); |
ea0760cf JB |
1267 | } |
1268 | ||
93ce0ba6 JN |
1269 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1270 | enum pipe pipe, bool state) | |
1271 | { | |
1272 | struct drm_device *dev = dev_priv->dev; | |
1273 | bool cur_state; | |
1274 | ||
d9d82081 | 1275 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1276 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1277 | else |
5efb3e28 | 1278 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1279 | |
e2c719b7 | 1280 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1281 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1282 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1283 | } |
1284 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1285 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1286 | ||
b840d907 JB |
1287 | void assert_pipe(struct drm_i915_private *dev_priv, |
1288 | enum pipe pipe, bool state) | |
b24e7179 | 1289 | { |
63d7bbe9 | 1290 | bool cur_state; |
702e7a56 PZ |
1291 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1292 | pipe); | |
4feed0eb | 1293 | enum intel_display_power_domain power_domain; |
b24e7179 | 1294 | |
b6b5d049 VS |
1295 | /* if we need the pipe quirk it must be always on */ |
1296 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1297 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1298 | state = true; |
1299 | ||
4feed0eb ID |
1300 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1301 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1302 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1303 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1304 | |
1305 | intel_display_power_put(dev_priv, power_domain); | |
1306 | } else { | |
1307 | cur_state = false; | |
69310161 PZ |
1308 | } |
1309 | ||
e2c719b7 | 1310 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1311 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1312 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1313 | } |
1314 | ||
931872fc CW |
1315 | static void assert_plane(struct drm_i915_private *dev_priv, |
1316 | enum plane plane, bool state) | |
b24e7179 | 1317 | { |
b24e7179 | 1318 | u32 val; |
931872fc | 1319 | bool cur_state; |
b24e7179 | 1320 | |
649636ef | 1321 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1322 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1323 | I915_STATE_WARN(cur_state != state, |
931872fc | 1324 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1325 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1326 | } |
1327 | ||
931872fc CW |
1328 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1329 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1330 | ||
b24e7179 JB |
1331 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1332 | enum pipe pipe) | |
1333 | { | |
653e1026 | 1334 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1335 | int i; |
b24e7179 | 1336 | |
653e1026 VS |
1337 | /* Primary planes are fixed to pipes on gen4+ */ |
1338 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1339 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1340 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1341 | "plane %c assertion failure, should be disabled but not\n", |
1342 | plane_name(pipe)); | |
19ec1358 | 1343 | return; |
28c05794 | 1344 | } |
19ec1358 | 1345 | |
b24e7179 | 1346 | /* Need to check both planes against the pipe */ |
055e393f | 1347 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1348 | u32 val = I915_READ(DSPCNTR(i)); |
1349 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1350 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1351 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1352 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1353 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1354 | } |
1355 | } | |
1356 | ||
19332d7a JB |
1357 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1358 | enum pipe pipe) | |
1359 | { | |
20674eef | 1360 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1361 | int sprite; |
19332d7a | 1362 | |
7feb8b88 | 1363 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1364 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1365 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1366 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1367 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1368 | sprite, pipe_name(pipe)); | |
1369 | } | |
666a4537 | 1370 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1371 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1372 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1373 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1374 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1375 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1376 | } |
1377 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1378 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1379 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1380 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1381 | plane_name(pipe), pipe_name(pipe)); |
1382 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1383 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1384 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1385 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1386 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1387 | } |
1388 | } | |
1389 | ||
08c71e5e VS |
1390 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1391 | { | |
e2c719b7 | 1392 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1393 | drm_crtc_vblank_put(crtc); |
1394 | } | |
1395 | ||
7abd4b35 ACO |
1396 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1397 | enum pipe pipe) | |
92f2584a | 1398 | { |
92f2584a JB |
1399 | u32 val; |
1400 | bool enabled; | |
1401 | ||
649636ef | 1402 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1403 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1404 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1405 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1406 | pipe_name(pipe)); | |
92f2584a JB |
1407 | } |
1408 | ||
4e634389 KP |
1409 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1410 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1411 | { |
1412 | if ((val & DP_PORT_EN) == 0) | |
1413 | return false; | |
1414 | ||
2d1fe073 | 1415 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1416 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1417 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1418 | return false; | |
2d1fe073 | 1419 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1420 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1421 | return false; | |
f0575e92 KP |
1422 | } else { |
1423 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1424 | return false; | |
1425 | } | |
1426 | return true; | |
1427 | } | |
1428 | ||
1519b995 KP |
1429 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1430 | enum pipe pipe, u32 val) | |
1431 | { | |
dc0fa718 | 1432 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1433 | return false; |
1434 | ||
2d1fe073 | 1435 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1436 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1437 | return false; |
2d1fe073 | 1438 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1439 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1440 | return false; | |
1519b995 | 1441 | } else { |
dc0fa718 | 1442 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1443 | return false; |
1444 | } | |
1445 | return true; | |
1446 | } | |
1447 | ||
1448 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1449 | enum pipe pipe, u32 val) | |
1450 | { | |
1451 | if ((val & LVDS_PORT_EN) == 0) | |
1452 | return false; | |
1453 | ||
2d1fe073 | 1454 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1455 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1456 | return false; | |
1457 | } else { | |
1458 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1459 | return false; | |
1460 | } | |
1461 | return true; | |
1462 | } | |
1463 | ||
1464 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1465 | enum pipe pipe, u32 val) | |
1466 | { | |
1467 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1468 | return false; | |
2d1fe073 | 1469 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1470 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1471 | return false; | |
1472 | } else { | |
1473 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1474 | return false; | |
1475 | } | |
1476 | return true; | |
1477 | } | |
1478 | ||
291906f1 | 1479 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1480 | enum pipe pipe, i915_reg_t reg, |
1481 | u32 port_sel) | |
291906f1 | 1482 | { |
47a05eca | 1483 | u32 val = I915_READ(reg); |
e2c719b7 | 1484 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1485 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1486 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1487 | |
2d1fe073 | 1488 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1489 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1490 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1491 | } |
1492 | ||
1493 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1494 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1495 | { |
47a05eca | 1496 | u32 val = I915_READ(reg); |
e2c719b7 | 1497 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1498 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1499 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1500 | |
2d1fe073 | 1501 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1502 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1503 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1504 | } |
1505 | ||
1506 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1507 | enum pipe pipe) | |
1508 | { | |
291906f1 | 1509 | u32 val; |
291906f1 | 1510 | |
f0575e92 KP |
1511 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1512 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1513 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1514 | |
649636ef | 1515 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1516 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1517 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1518 | pipe_name(pipe)); |
291906f1 | 1519 | |
649636ef | 1520 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1521 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1522 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1523 | pipe_name(pipe)); |
291906f1 | 1524 | |
e2debe91 PZ |
1525 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1526 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1527 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1528 | } |
1529 | ||
cd2d34d9 VS |
1530 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1531 | const struct intel_crtc_state *pipe_config) | |
1532 | { | |
1533 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1534 | enum pipe pipe = crtc->pipe; | |
1535 | ||
1536 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1537 | POSTING_READ(DPLL(pipe)); | |
1538 | udelay(150); | |
1539 | ||
1540 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1541 | DRM_ERROR("DPLL %d failed to lock\n", pipe); | |
1542 | } | |
1543 | ||
d288f65f | 1544 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1545 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1546 | { |
cd2d34d9 | 1547 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1548 | enum pipe pipe = crtc->pipe; |
87442f73 | 1549 | |
8bd3f301 | 1550 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1551 | |
87442f73 | 1552 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1553 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1554 | |
cd2d34d9 VS |
1555 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1556 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1557 | |
8bd3f301 VS |
1558 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1559 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1560 | } |
1561 | ||
cd2d34d9 VS |
1562 | |
1563 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1564 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1565 | { |
cd2d34d9 | 1566 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1567 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1568 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1569 | u32 tmp; |
1570 | ||
a580516d | 1571 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1572 | |
1573 | /* Enable back the 10bit clock to display controller */ | |
1574 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1575 | tmp |= DPIO_DCLKP_EN; | |
1576 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1577 | ||
54433e91 VS |
1578 | mutex_unlock(&dev_priv->sb_lock); |
1579 | ||
9d556c99 CML |
1580 | /* |
1581 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1582 | */ | |
1583 | udelay(1); | |
1584 | ||
1585 | /* Enable PLL */ | |
d288f65f | 1586 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1587 | |
1588 | /* Check PLL is locked */ | |
a11b0703 | 1589 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 | 1590 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1591 | } |
1592 | ||
1593 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1594 | const struct intel_crtc_state *pipe_config) | |
1595 | { | |
1596 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1597 | enum pipe pipe = crtc->pipe; | |
1598 | ||
1599 | assert_pipe_disabled(dev_priv, pipe); | |
1600 | ||
1601 | /* PLL is protected by panel, make sure we can write it */ | |
1602 | assert_panel_unlocked(dev_priv, pipe); | |
1603 | ||
1604 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1605 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1606 | |
c231775c VS |
1607 | if (pipe != PIPE_A) { |
1608 | /* | |
1609 | * WaPixelRepeatModeFixForC0:chv | |
1610 | * | |
1611 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1612 | * the value from DPLLBMD to either pipe B or C. | |
1613 | */ | |
1614 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1615 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1616 | I915_WRITE(CBR4_VLV, 0); | |
1617 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1618 | ||
1619 | /* | |
1620 | * DPLLB VGA mode also seems to cause problems. | |
1621 | * We should always have it disabled. | |
1622 | */ | |
1623 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1624 | } else { | |
1625 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1626 | POSTING_READ(DPLL_MD(pipe)); | |
1627 | } | |
9d556c99 CML |
1628 | } |
1629 | ||
1c4e0274 VS |
1630 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1631 | { | |
1632 | struct intel_crtc *crtc; | |
1633 | int count = 0; | |
1634 | ||
1635 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1636 | count += crtc->base.state->active && |
409ee761 | 1637 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1638 | |
1639 | return count; | |
1640 | } | |
1641 | ||
66e3d5c0 | 1642 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1643 | { |
66e3d5c0 DV |
1644 | struct drm_device *dev = crtc->base.dev; |
1645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1646 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1647 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1648 | |
66e3d5c0 | 1649 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1650 | |
63d7bbe9 | 1651 | /* PLL is protected by panel, make sure we can write it */ |
66e3d5c0 DV |
1652 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1653 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1654 | |
1c4e0274 VS |
1655 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1656 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1657 | /* | |
1658 | * It appears to be important that we don't enable this | |
1659 | * for the current pipe before otherwise configuring the | |
1660 | * PLL. No idea how this should be handled if multiple | |
1661 | * DVO outputs are enabled simultaneosly. | |
1662 | */ | |
1663 | dpll |= DPLL_DVO_2X_MODE; | |
1664 | I915_WRITE(DPLL(!crtc->pipe), | |
1665 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1666 | } | |
66e3d5c0 | 1667 | |
c2b63374 VS |
1668 | /* |
1669 | * Apparently we need to have VGA mode enabled prior to changing | |
1670 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1671 | * dividers, even though the register value does change. | |
1672 | */ | |
1673 | I915_WRITE(reg, 0); | |
1674 | ||
8e7a65aa VS |
1675 | I915_WRITE(reg, dpll); |
1676 | ||
66e3d5c0 DV |
1677 | /* Wait for the clocks to stabilize. */ |
1678 | POSTING_READ(reg); | |
1679 | udelay(150); | |
1680 | ||
1681 | if (INTEL_INFO(dev)->gen >= 4) { | |
1682 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1683 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1684 | } else { |
1685 | /* The pixel multiplier can only be updated once the | |
1686 | * DPLL is enabled and the clocks are stable. | |
1687 | * | |
1688 | * So write it again. | |
1689 | */ | |
1690 | I915_WRITE(reg, dpll); | |
1691 | } | |
63d7bbe9 JB |
1692 | |
1693 | /* We do this three times for luck */ | |
66e3d5c0 | 1694 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1695 | POSTING_READ(reg); |
1696 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1697 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1698 | POSTING_READ(reg); |
1699 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1700 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1701 | POSTING_READ(reg); |
1702 | udelay(150); /* wait for warmup */ | |
1703 | } | |
1704 | ||
1705 | /** | |
50b44a44 | 1706 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1707 | * @dev_priv: i915 private structure |
1708 | * @pipe: pipe PLL to disable | |
1709 | * | |
1710 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1711 | * | |
1712 | * Note! This is for pre-ILK only. | |
1713 | */ | |
1c4e0274 | 1714 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1715 | { |
1c4e0274 VS |
1716 | struct drm_device *dev = crtc->base.dev; |
1717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1718 | enum pipe pipe = crtc->pipe; | |
1719 | ||
1720 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1721 | if (IS_I830(dev) && | |
409ee761 | 1722 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1723 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1724 | I915_WRITE(DPLL(PIPE_B), |
1725 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1726 | I915_WRITE(DPLL(PIPE_A), | |
1727 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1728 | } | |
1729 | ||
b6b5d049 VS |
1730 | /* Don't disable pipe or pipe PLLs if needed */ |
1731 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1732 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1733 | return; |
1734 | ||
1735 | /* Make sure the pipe isn't still relying on us */ | |
1736 | assert_pipe_disabled(dev_priv, pipe); | |
1737 | ||
b8afb911 | 1738 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1739 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1740 | } |
1741 | ||
f6071166 JB |
1742 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1743 | { | |
b8afb911 | 1744 | u32 val; |
f6071166 JB |
1745 | |
1746 | /* Make sure the pipe isn't still relying on us */ | |
1747 | assert_pipe_disabled(dev_priv, pipe); | |
1748 | ||
03ed5cbf VS |
1749 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1750 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1751 | if (pipe != PIPE_A) | |
1752 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1753 | ||
f6071166 JB |
1754 | I915_WRITE(DPLL(pipe), val); |
1755 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1756 | } |
1757 | ||
1758 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1759 | { | |
d752048d | 1760 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1761 | u32 val; |
1762 | ||
a11b0703 VS |
1763 | /* Make sure the pipe isn't still relying on us */ |
1764 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1765 | |
60bfe44f VS |
1766 | val = DPLL_SSC_REF_CLK_CHV | |
1767 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1768 | if (pipe != PIPE_A) |
1769 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1770 | |
a11b0703 VS |
1771 | I915_WRITE(DPLL(pipe), val); |
1772 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1773 | |
a580516d | 1774 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1775 | |
1776 | /* Disable 10bit clock to display controller */ | |
1777 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1778 | val &= ~DPIO_DCLKP_EN; | |
1779 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1780 | ||
a580516d | 1781 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1782 | } |
1783 | ||
e4607fcf | 1784 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1785 | struct intel_digital_port *dport, |
1786 | unsigned int expected_mask) | |
89b667f8 JB |
1787 | { |
1788 | u32 port_mask; | |
f0f59a00 | 1789 | i915_reg_t dpll_reg; |
89b667f8 | 1790 | |
e4607fcf CML |
1791 | switch (dport->port) { |
1792 | case PORT_B: | |
89b667f8 | 1793 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1794 | dpll_reg = DPLL(0); |
e4607fcf CML |
1795 | break; |
1796 | case PORT_C: | |
89b667f8 | 1797 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1798 | dpll_reg = DPLL(0); |
9b6de0a1 | 1799 | expected_mask <<= 4; |
00fc31b7 CML |
1800 | break; |
1801 | case PORT_D: | |
1802 | port_mask = DPLL_PORTD_READY_MASK; | |
1803 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1804 | break; |
1805 | default: | |
1806 | BUG(); | |
1807 | } | |
89b667f8 | 1808 | |
9b6de0a1 VS |
1809 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1810 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1811 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1812 | } |
1813 | ||
b8a4f404 PZ |
1814 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1815 | enum pipe pipe) | |
040484af | 1816 | { |
23670b32 | 1817 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1818 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1819 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1820 | i915_reg_t reg; |
1821 | uint32_t val, pipeconf_val; | |
040484af | 1822 | |
040484af | 1823 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1824 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1825 | |
1826 | /* FDI must be feeding us bits for PCH ports */ | |
1827 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1828 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1829 | ||
23670b32 DV |
1830 | if (HAS_PCH_CPT(dev)) { |
1831 | /* Workaround: Set the timing override bit before enabling the | |
1832 | * pch transcoder. */ | |
1833 | reg = TRANS_CHICKEN2(pipe); | |
1834 | val = I915_READ(reg); | |
1835 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1836 | I915_WRITE(reg, val); | |
59c859d6 | 1837 | } |
23670b32 | 1838 | |
ab9412ba | 1839 | reg = PCH_TRANSCONF(pipe); |
040484af | 1840 | val = I915_READ(reg); |
5f7f726d | 1841 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1842 | |
2d1fe073 | 1843 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1844 | /* |
c5de7c6f VS |
1845 | * Make the BPC in transcoder be consistent with |
1846 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1847 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1848 | */ |
dfd07d72 | 1849 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1850 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1851 | val |= PIPECONF_8BPC; | |
1852 | else | |
1853 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1854 | } |
5f7f726d PZ |
1855 | |
1856 | val &= ~TRANS_INTERLACE_MASK; | |
1857 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1858 | if (HAS_PCH_IBX(dev_priv) && |
409ee761 | 1859 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1860 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1861 | else | |
1862 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1863 | else |
1864 | val |= TRANS_PROGRESSIVE; | |
1865 | ||
040484af JB |
1866 | I915_WRITE(reg, val | TRANS_ENABLE); |
1867 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1868 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1869 | } |
1870 | ||
8fb033d7 | 1871 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1872 | enum transcoder cpu_transcoder) |
040484af | 1873 | { |
8fb033d7 | 1874 | u32 val, pipeconf_val; |
8fb033d7 | 1875 | |
8fb033d7 | 1876 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1877 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1878 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1879 | |
223a6fdf | 1880 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1881 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1882 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1883 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1884 | |
25f3ef11 | 1885 | val = TRANS_ENABLE; |
937bb610 | 1886 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1887 | |
9a76b1c6 PZ |
1888 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1889 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1890 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1891 | else |
1892 | val |= TRANS_PROGRESSIVE; | |
1893 | ||
ab9412ba DV |
1894 | I915_WRITE(LPT_TRANSCONF, val); |
1895 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1896 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1897 | } |
1898 | ||
b8a4f404 PZ |
1899 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1900 | enum pipe pipe) | |
040484af | 1901 | { |
23670b32 | 1902 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
1903 | i915_reg_t reg; |
1904 | uint32_t val; | |
040484af JB |
1905 | |
1906 | /* FDI relies on the transcoder */ | |
1907 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1908 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1909 | ||
291906f1 JB |
1910 | /* Ports must be off as well */ |
1911 | assert_pch_ports_disabled(dev_priv, pipe); | |
1912 | ||
ab9412ba | 1913 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1914 | val = I915_READ(reg); |
1915 | val &= ~TRANS_ENABLE; | |
1916 | I915_WRITE(reg, val); | |
1917 | /* wait for PCH transcoder off, transcoder state */ | |
1918 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1919 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1920 | |
c465613b | 1921 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1922 | /* Workaround: Clear the timing override chicken bit again. */ |
1923 | reg = TRANS_CHICKEN2(pipe); | |
1924 | val = I915_READ(reg); | |
1925 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1926 | I915_WRITE(reg, val); | |
1927 | } | |
040484af JB |
1928 | } |
1929 | ||
ab4d966c | 1930 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1931 | { |
8fb033d7 PZ |
1932 | u32 val; |
1933 | ||
ab9412ba | 1934 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1935 | val &= ~TRANS_ENABLE; |
ab9412ba | 1936 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1937 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1938 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1939 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1940 | |
1941 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1942 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1943 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1944 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1945 | } |
1946 | ||
b24e7179 | 1947 | /** |
309cfea8 | 1948 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1949 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1950 | * |
0372264a | 1951 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1952 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1953 | */ |
e1fdc473 | 1954 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1955 | { |
0372264a PZ |
1956 | struct drm_device *dev = crtc->base.dev; |
1957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1958 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 1959 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1960 | enum pipe pch_transcoder; |
f0f59a00 | 1961 | i915_reg_t reg; |
b24e7179 JB |
1962 | u32 val; |
1963 | ||
9e2ee2dd VS |
1964 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1965 | ||
58c6eaa2 | 1966 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1967 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1968 | assert_sprites_disabled(dev_priv, pipe); |
1969 | ||
2d1fe073 | 1970 | if (HAS_PCH_LPT(dev_priv)) |
cc391bbb PZ |
1971 | pch_transcoder = TRANSCODER_A; |
1972 | else | |
1973 | pch_transcoder = pipe; | |
1974 | ||
b24e7179 JB |
1975 | /* |
1976 | * A pipe without a PLL won't actually be able to drive bits from | |
1977 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1978 | * need the check. | |
1979 | */ | |
2d1fe073 | 1980 | if (HAS_GMCH_DISPLAY(dev_priv)) |
a65347ba | 1981 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
1982 | assert_dsi_pll_enabled(dev_priv); |
1983 | else | |
1984 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 1985 | else { |
6e3c9717 | 1986 | if (crtc->config->has_pch_encoder) { |
040484af | 1987 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1988 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1989 | assert_fdi_tx_pll_enabled(dev_priv, |
1990 | (enum pipe) cpu_transcoder); | |
040484af JB |
1991 | } |
1992 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1993 | } | |
b24e7179 | 1994 | |
702e7a56 | 1995 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1996 | val = I915_READ(reg); |
7ad25d48 | 1997 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1998 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1999 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2000 | return; |
7ad25d48 | 2001 | } |
00d70b15 CW |
2002 | |
2003 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2004 | POSTING_READ(reg); |
b7792d8b VS |
2005 | |
2006 | /* | |
2007 | * Until the pipe starts DSL will read as 0, which would cause | |
2008 | * an apparent vblank timestamp jump, which messes up also the | |
2009 | * frame count when it's derived from the timestamps. So let's | |
2010 | * wait for the pipe to start properly before we call | |
2011 | * drm_crtc_vblank_on() | |
2012 | */ | |
2013 | if (dev->max_vblank_count == 0 && | |
2014 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2015 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2016 | } |
2017 | ||
2018 | /** | |
309cfea8 | 2019 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2020 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2021 | * |
575f7ab7 VS |
2022 | * Disable the pipe of @crtc, making sure that various hardware |
2023 | * specific requirements are met, if applicable, e.g. plane | |
2024 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2025 | * |
2026 | * Will wait until the pipe has shut down before returning. | |
2027 | */ | |
575f7ab7 | 2028 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2029 | { |
575f7ab7 | 2030 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2031 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2032 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2033 | i915_reg_t reg; |
b24e7179 JB |
2034 | u32 val; |
2035 | ||
9e2ee2dd VS |
2036 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2037 | ||
b24e7179 JB |
2038 | /* |
2039 | * Make sure planes won't keep trying to pump pixels to us, | |
2040 | * or we might hang the display. | |
2041 | */ | |
2042 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2043 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2044 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2045 | |
702e7a56 | 2046 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2047 | val = I915_READ(reg); |
00d70b15 CW |
2048 | if ((val & PIPECONF_ENABLE) == 0) |
2049 | return; | |
2050 | ||
67adc644 VS |
2051 | /* |
2052 | * Double wide has implications for planes | |
2053 | * so best keep it disabled when not needed. | |
2054 | */ | |
6e3c9717 | 2055 | if (crtc->config->double_wide) |
67adc644 VS |
2056 | val &= ~PIPECONF_DOUBLE_WIDE; |
2057 | ||
2058 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2059 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2060 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2061 | val &= ~PIPECONF_ENABLE; |
2062 | ||
2063 | I915_WRITE(reg, val); | |
2064 | if ((val & PIPECONF_ENABLE) == 0) | |
2065 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2066 | } |
2067 | ||
693db184 CW |
2068 | static bool need_vtd_wa(struct drm_device *dev) |
2069 | { | |
2070 | #ifdef CONFIG_INTEL_IOMMU | |
2071 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2072 | return true; | |
2073 | #endif | |
2074 | return false; | |
2075 | } | |
2076 | ||
832be82f VS |
2077 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2078 | { | |
2079 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2080 | } | |
2081 | ||
27ba3910 VS |
2082 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2083 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2084 | { |
2085 | switch (fb_modifier) { | |
2086 | case DRM_FORMAT_MOD_NONE: | |
2087 | return cpp; | |
2088 | case I915_FORMAT_MOD_X_TILED: | |
2089 | if (IS_GEN2(dev_priv)) | |
2090 | return 128; | |
2091 | else | |
2092 | return 512; | |
2093 | case I915_FORMAT_MOD_Y_TILED: | |
2094 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2095 | return 128; | |
2096 | else | |
2097 | return 512; | |
2098 | case I915_FORMAT_MOD_Yf_TILED: | |
2099 | switch (cpp) { | |
2100 | case 1: | |
2101 | return 64; | |
2102 | case 2: | |
2103 | case 4: | |
2104 | return 128; | |
2105 | case 8: | |
2106 | case 16: | |
2107 | return 256; | |
2108 | default: | |
2109 | MISSING_CASE(cpp); | |
2110 | return cpp; | |
2111 | } | |
2112 | break; | |
2113 | default: | |
2114 | MISSING_CASE(fb_modifier); | |
2115 | return cpp; | |
2116 | } | |
2117 | } | |
2118 | ||
832be82f VS |
2119 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2120 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2121 | { |
832be82f VS |
2122 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2123 | return 1; | |
2124 | else | |
2125 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2126 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2127 | } |
2128 | ||
8d0deca8 VS |
2129 | /* Return the tile dimensions in pixel units */ |
2130 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2131 | unsigned int *tile_width, | |
2132 | unsigned int *tile_height, | |
2133 | uint64_t fb_modifier, | |
2134 | unsigned int cpp) | |
2135 | { | |
2136 | unsigned int tile_width_bytes = | |
2137 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2138 | ||
2139 | *tile_width = tile_width_bytes / cpp; | |
2140 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2141 | } | |
2142 | ||
6761dd31 TU |
2143 | unsigned int |
2144 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2145 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2146 | { |
832be82f VS |
2147 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2148 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2149 | ||
2150 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2151 | } |
2152 | ||
1663b9d6 VS |
2153 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2154 | { | |
2155 | unsigned int size = 0; | |
2156 | int i; | |
2157 | ||
2158 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2159 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2160 | ||
2161 | return size; | |
2162 | } | |
2163 | ||
75c82a53 | 2164 | static void |
3465c580 VS |
2165 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2166 | const struct drm_framebuffer *fb, | |
2167 | unsigned int rotation) | |
f64b98cd | 2168 | { |
2d7a215f VS |
2169 | if (intel_rotation_90_or_270(rotation)) { |
2170 | *view = i915_ggtt_view_rotated; | |
2171 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2172 | } else { | |
2173 | *view = i915_ggtt_view_normal; | |
2174 | } | |
2175 | } | |
50470bb0 | 2176 | |
2d7a215f VS |
2177 | static void |
2178 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2179 | struct drm_framebuffer *fb) | |
2180 | { | |
2181 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2182 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2183 | |
d9b3288e VS |
2184 | tile_size = intel_tile_size(dev_priv); |
2185 | ||
2186 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2187 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2188 | fb->modifier[0], cpp); | |
d9b3288e | 2189 | |
1663b9d6 VS |
2190 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2191 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2192 | |
89e3e142 | 2193 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2194 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2195 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2196 | fb->modifier[1], cpp); | |
d9b3288e | 2197 | |
2d7a215f | 2198 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2199 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2200 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2201 | } |
f64b98cd TU |
2202 | } |
2203 | ||
603525d7 | 2204 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2205 | { |
2206 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2207 | return 256 * 1024; | |
985b8bb4 | 2208 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2209 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2210 | return 128 * 1024; |
2211 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2212 | return 4 * 1024; | |
2213 | else | |
44c5905e | 2214 | return 0; |
4e9a86b6 VS |
2215 | } |
2216 | ||
603525d7 VS |
2217 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2218 | uint64_t fb_modifier) | |
2219 | { | |
2220 | switch (fb_modifier) { | |
2221 | case DRM_FORMAT_MOD_NONE: | |
2222 | return intel_linear_alignment(dev_priv); | |
2223 | case I915_FORMAT_MOD_X_TILED: | |
2224 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2225 | return 256 * 1024; | |
2226 | return 0; | |
2227 | case I915_FORMAT_MOD_Y_TILED: | |
2228 | case I915_FORMAT_MOD_Yf_TILED: | |
2229 | return 1 * 1024 * 1024; | |
2230 | default: | |
2231 | MISSING_CASE(fb_modifier); | |
2232 | return 0; | |
2233 | } | |
2234 | } | |
2235 | ||
127bd2ac | 2236 | int |
3465c580 VS |
2237 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2238 | unsigned int rotation) | |
6b95a207 | 2239 | { |
850c4cdc | 2240 | struct drm_device *dev = fb->dev; |
ce453d81 | 2241 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2242 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2243 | struct i915_ggtt_view view; |
6b95a207 KH |
2244 | u32 alignment; |
2245 | int ret; | |
2246 | ||
ebcdd39e MR |
2247 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2248 | ||
603525d7 | 2249 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2250 | |
3465c580 | 2251 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2252 | |
693db184 CW |
2253 | /* Note that the w/a also requires 64 PTE of padding following the |
2254 | * bo. We currently fill all unused PTE with the shadow page and so | |
2255 | * we should always have valid PTE following the scanout preventing | |
2256 | * the VT-d warning. | |
2257 | */ | |
2258 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2259 | alignment = 256 * 1024; | |
2260 | ||
d6dd6843 PZ |
2261 | /* |
2262 | * Global gtt pte registers are special registers which actually forward | |
2263 | * writes to a chunk of system memory. Which means that there is no risk | |
2264 | * that the register values disappear as soon as we call | |
2265 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2266 | * pin/unpin/fence and not more. | |
2267 | */ | |
2268 | intel_runtime_pm_get(dev_priv); | |
2269 | ||
7580d774 ML |
2270 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2271 | &view); | |
48b956c5 | 2272 | if (ret) |
b26a6b35 | 2273 | goto err_pm; |
6b95a207 KH |
2274 | |
2275 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2276 | * fence, whereas 965+ only requires a fence if using | |
2277 | * framebuffer compression. For simplicity, we always install | |
2278 | * a fence as the cost is not that onerous. | |
2279 | */ | |
9807216f VK |
2280 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2281 | ret = i915_gem_object_get_fence(obj); | |
2282 | if (ret == -EDEADLK) { | |
2283 | /* | |
2284 | * -EDEADLK means there are no free fences | |
2285 | * no pending flips. | |
2286 | * | |
2287 | * This is propagated to atomic, but it uses | |
2288 | * -EDEADLK to force a locking recovery, so | |
2289 | * change the returned error to -EBUSY. | |
2290 | */ | |
2291 | ret = -EBUSY; | |
2292 | goto err_unpin; | |
2293 | } else if (ret) | |
2294 | goto err_unpin; | |
1690e1eb | 2295 | |
9807216f VK |
2296 | i915_gem_object_pin_fence(obj); |
2297 | } | |
6b95a207 | 2298 | |
d6dd6843 | 2299 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2300 | return 0; |
48b956c5 CW |
2301 | |
2302 | err_unpin: | |
f64b98cd | 2303 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2304 | err_pm: |
d6dd6843 | 2305 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2306 | return ret; |
6b95a207 KH |
2307 | } |
2308 | ||
fb4b8ce1 | 2309 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2310 | { |
82bc3b2d | 2311 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2312 | struct i915_ggtt_view view; |
82bc3b2d | 2313 | |
ebcdd39e MR |
2314 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2315 | ||
3465c580 | 2316 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2317 | |
9807216f VK |
2318 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2319 | i915_gem_object_unpin_fence(obj); | |
2320 | ||
f64b98cd | 2321 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2322 | } |
2323 | ||
29cf9491 VS |
2324 | /* |
2325 | * Adjust the tile offset by moving the difference into | |
2326 | * the x/y offsets. | |
2327 | * | |
2328 | * Input tile dimensions and pitch must already be | |
2329 | * rotated to match x and y, and in pixel units. | |
2330 | */ | |
2331 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2332 | unsigned int tile_width, | |
2333 | unsigned int tile_height, | |
2334 | unsigned int tile_size, | |
2335 | unsigned int pitch_tiles, | |
2336 | u32 old_offset, | |
2337 | u32 new_offset) | |
2338 | { | |
2339 | unsigned int tiles; | |
2340 | ||
2341 | WARN_ON(old_offset & (tile_size - 1)); | |
2342 | WARN_ON(new_offset & (tile_size - 1)); | |
2343 | WARN_ON(new_offset > old_offset); | |
2344 | ||
2345 | tiles = (old_offset - new_offset) / tile_size; | |
2346 | ||
2347 | *y += tiles / pitch_tiles * tile_height; | |
2348 | *x += tiles % pitch_tiles * tile_width; | |
2349 | ||
2350 | return new_offset; | |
2351 | } | |
2352 | ||
8d0deca8 VS |
2353 | /* |
2354 | * Computes the linear offset to the base tile and adjusts | |
2355 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2356 | * | |
2357 | * In the 90/270 rotated case, x and y are assumed | |
2358 | * to be already rotated to match the rotated GTT view, and | |
2359 | * pitch is the tile_height aligned framebuffer height. | |
2360 | */ | |
4f2d9934 VS |
2361 | u32 intel_compute_tile_offset(int *x, int *y, |
2362 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2363 | unsigned int pitch, |
2364 | unsigned int rotation) | |
c2c75131 | 2365 | { |
4f2d9934 VS |
2366 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2367 | uint64_t fb_modifier = fb->modifier[plane]; | |
2368 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2369 | u32 offset, offset_aligned, alignment; |
2370 | ||
2371 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2372 | if (alignment) | |
2373 | alignment--; | |
2374 | ||
b5c65338 | 2375 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2376 | unsigned int tile_size, tile_width, tile_height; |
2377 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2378 | |
d843310d | 2379 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2380 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2381 | fb_modifier, cpp); | |
2382 | ||
2383 | if (intel_rotation_90_or_270(rotation)) { | |
2384 | pitch_tiles = pitch / tile_height; | |
2385 | swap(tile_width, tile_height); | |
2386 | } else { | |
2387 | pitch_tiles = pitch / (tile_width * cpp); | |
2388 | } | |
d843310d VS |
2389 | |
2390 | tile_rows = *y / tile_height; | |
2391 | *y %= tile_height; | |
c2c75131 | 2392 | |
8d0deca8 VS |
2393 | tiles = *x / tile_width; |
2394 | *x %= tile_width; | |
bc752862 | 2395 | |
29cf9491 VS |
2396 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2397 | offset_aligned = offset & ~alignment; | |
bc752862 | 2398 | |
29cf9491 VS |
2399 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2400 | tile_size, pitch_tiles, | |
2401 | offset, offset_aligned); | |
2402 | } else { | |
bc752862 | 2403 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2404 | offset_aligned = offset & ~alignment; |
2405 | ||
4e9a86b6 VS |
2406 | *y = (offset & alignment) / pitch; |
2407 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2408 | } |
29cf9491 VS |
2409 | |
2410 | return offset_aligned; | |
c2c75131 DV |
2411 | } |
2412 | ||
b35d63fa | 2413 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2414 | { |
2415 | switch (format) { | |
2416 | case DISPPLANE_8BPP: | |
2417 | return DRM_FORMAT_C8; | |
2418 | case DISPPLANE_BGRX555: | |
2419 | return DRM_FORMAT_XRGB1555; | |
2420 | case DISPPLANE_BGRX565: | |
2421 | return DRM_FORMAT_RGB565; | |
2422 | default: | |
2423 | case DISPPLANE_BGRX888: | |
2424 | return DRM_FORMAT_XRGB8888; | |
2425 | case DISPPLANE_RGBX888: | |
2426 | return DRM_FORMAT_XBGR8888; | |
2427 | case DISPPLANE_BGRX101010: | |
2428 | return DRM_FORMAT_XRGB2101010; | |
2429 | case DISPPLANE_RGBX101010: | |
2430 | return DRM_FORMAT_XBGR2101010; | |
2431 | } | |
2432 | } | |
2433 | ||
bc8d7dff DL |
2434 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2435 | { | |
2436 | switch (format) { | |
2437 | case PLANE_CTL_FORMAT_RGB_565: | |
2438 | return DRM_FORMAT_RGB565; | |
2439 | default: | |
2440 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2441 | if (rgb_order) { | |
2442 | if (alpha) | |
2443 | return DRM_FORMAT_ABGR8888; | |
2444 | else | |
2445 | return DRM_FORMAT_XBGR8888; | |
2446 | } else { | |
2447 | if (alpha) | |
2448 | return DRM_FORMAT_ARGB8888; | |
2449 | else | |
2450 | return DRM_FORMAT_XRGB8888; | |
2451 | } | |
2452 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2453 | if (rgb_order) | |
2454 | return DRM_FORMAT_XBGR2101010; | |
2455 | else | |
2456 | return DRM_FORMAT_XRGB2101010; | |
2457 | } | |
2458 | } | |
2459 | ||
5724dbd1 | 2460 | static bool |
f6936e29 DV |
2461 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2462 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2463 | { |
2464 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2465 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2466 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2467 | struct drm_i915_gem_object *obj = NULL; |
2468 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2469 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2470 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2471 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2472 | PAGE_SIZE); | |
2473 | ||
2474 | size_aligned -= base_aligned; | |
46f297fb | 2475 | |
ff2652ea CW |
2476 | if (plane_config->size == 0) |
2477 | return false; | |
2478 | ||
3badb49f PZ |
2479 | /* If the FB is too big, just don't use it since fbdev is not very |
2480 | * important and we should probably use that space with FBC or other | |
2481 | * features. */ | |
72e96d64 | 2482 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2483 | return false; |
2484 | ||
12c83d99 TU |
2485 | mutex_lock(&dev->struct_mutex); |
2486 | ||
f37b5c2b DV |
2487 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2488 | base_aligned, | |
2489 | base_aligned, | |
2490 | size_aligned); | |
12c83d99 TU |
2491 | if (!obj) { |
2492 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2493 | return false; |
12c83d99 | 2494 | } |
46f297fb | 2495 | |
49af449b DL |
2496 | obj->tiling_mode = plane_config->tiling; |
2497 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2498 | obj->stride = fb->pitches[0]; |
46f297fb | 2499 | |
6bf129df DL |
2500 | mode_cmd.pixel_format = fb->pixel_format; |
2501 | mode_cmd.width = fb->width; | |
2502 | mode_cmd.height = fb->height; | |
2503 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2504 | mode_cmd.modifier[0] = fb->modifier[0]; |
2505 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2506 | |
6bf129df | 2507 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2508 | &mode_cmd, obj)) { |
46f297fb JB |
2509 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2510 | goto out_unref_obj; | |
2511 | } | |
12c83d99 | 2512 | |
46f297fb | 2513 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2514 | |
f6936e29 | 2515 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2516 | return true; |
46f297fb JB |
2517 | |
2518 | out_unref_obj: | |
2519 | drm_gem_object_unreference(&obj->base); | |
2520 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2521 | return false; |
2522 | } | |
2523 | ||
afd65eb4 MR |
2524 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2525 | static void | |
2526 | update_state_fb(struct drm_plane *plane) | |
2527 | { | |
2528 | if (plane->fb == plane->state->fb) | |
2529 | return; | |
2530 | ||
2531 | if (plane->state->fb) | |
2532 | drm_framebuffer_unreference(plane->state->fb); | |
2533 | plane->state->fb = plane->fb; | |
2534 | if (plane->state->fb) | |
2535 | drm_framebuffer_reference(plane->state->fb); | |
2536 | } | |
2537 | ||
5724dbd1 | 2538 | static void |
f6936e29 DV |
2539 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2540 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2541 | { |
2542 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2543 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2544 | struct drm_crtc *c; |
2545 | struct intel_crtc *i; | |
2ff8fde1 | 2546 | struct drm_i915_gem_object *obj; |
88595ac9 | 2547 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2548 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2549 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2550 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2551 | struct intel_plane_state *intel_state = |
2552 | to_intel_plane_state(plane_state); | |
88595ac9 | 2553 | struct drm_framebuffer *fb; |
484b41dd | 2554 | |
2d14030b | 2555 | if (!plane_config->fb) |
484b41dd JB |
2556 | return; |
2557 | ||
f6936e29 | 2558 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2559 | fb = &plane_config->fb->base; |
2560 | goto valid_fb; | |
f55548b5 | 2561 | } |
484b41dd | 2562 | |
2d14030b | 2563 | kfree(plane_config->fb); |
484b41dd JB |
2564 | |
2565 | /* | |
2566 | * Failed to alloc the obj, check to see if we should share | |
2567 | * an fb with another CRTC instead | |
2568 | */ | |
70e1e0ec | 2569 | for_each_crtc(dev, c) { |
484b41dd JB |
2570 | i = to_intel_crtc(c); |
2571 | ||
2572 | if (c == &intel_crtc->base) | |
2573 | continue; | |
2574 | ||
2ff8fde1 MR |
2575 | if (!i->active) |
2576 | continue; | |
2577 | ||
88595ac9 DV |
2578 | fb = c->primary->fb; |
2579 | if (!fb) | |
484b41dd JB |
2580 | continue; |
2581 | ||
88595ac9 | 2582 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2583 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2584 | drm_framebuffer_reference(fb); |
2585 | goto valid_fb; | |
484b41dd JB |
2586 | } |
2587 | } | |
88595ac9 | 2588 | |
200757f5 MR |
2589 | /* |
2590 | * We've failed to reconstruct the BIOS FB. Current display state | |
2591 | * indicates that the primary plane is visible, but has a NULL FB, | |
2592 | * which will lead to problems later if we don't fix it up. The | |
2593 | * simplest solution is to just disable the primary plane now and | |
2594 | * pretend the BIOS never had it enabled. | |
2595 | */ | |
2596 | to_intel_plane_state(plane_state)->visible = false; | |
2597 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2598 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2599 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2600 | ||
88595ac9 DV |
2601 | return; |
2602 | ||
2603 | valid_fb: | |
f44e2659 VS |
2604 | plane_state->src_x = 0; |
2605 | plane_state->src_y = 0; | |
be5651f2 ML |
2606 | plane_state->src_w = fb->width << 16; |
2607 | plane_state->src_h = fb->height << 16; | |
2608 | ||
f44e2659 VS |
2609 | plane_state->crtc_x = 0; |
2610 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2611 | plane_state->crtc_w = fb->width; |
2612 | plane_state->crtc_h = fb->height; | |
2613 | ||
0a8d8a86 MR |
2614 | intel_state->src.x1 = plane_state->src_x; |
2615 | intel_state->src.y1 = plane_state->src_y; | |
2616 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2617 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2618 | intel_state->dst.x1 = plane_state->crtc_x; | |
2619 | intel_state->dst.y1 = plane_state->crtc_y; | |
2620 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2621 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2622 | ||
88595ac9 DV |
2623 | obj = intel_fb_obj(fb); |
2624 | if (obj->tiling_mode != I915_TILING_NONE) | |
2625 | dev_priv->preserve_bios_swizzle = true; | |
2626 | ||
be5651f2 ML |
2627 | drm_framebuffer_reference(fb); |
2628 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2629 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2630 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2631 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2632 | } |
2633 | ||
a8d201af ML |
2634 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2635 | const struct intel_crtc_state *crtc_state, | |
2636 | const struct intel_plane_state *plane_state) | |
81255565 | 2637 | { |
a8d201af | 2638 | struct drm_device *dev = primary->dev; |
81255565 | 2639 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2640 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2641 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2642 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2643 | int plane = intel_crtc->plane; |
54ea9da8 | 2644 | u32 linear_offset; |
81255565 | 2645 | u32 dspcntr; |
f0f59a00 | 2646 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2647 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2648 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2649 | int x = plane_state->src.x1 >> 16; |
2650 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2651 | |
f45651ba VS |
2652 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2653 | ||
fdd508a6 | 2654 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2655 | |
2656 | if (INTEL_INFO(dev)->gen < 4) { | |
2657 | if (intel_crtc->pipe == PIPE_B) | |
2658 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2659 | ||
2660 | /* pipesrc and dspsize control the size that is scaled from, | |
2661 | * which should always be the user's requested size. | |
2662 | */ | |
2663 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2664 | ((crtc_state->pipe_src_h - 1) << 16) | |
2665 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2666 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2667 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2668 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2669 | ((crtc_state->pipe_src_h - 1) << 16) | |
2670 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2671 | I915_WRITE(PRIMPOS(plane), 0); |
2672 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2673 | } |
81255565 | 2674 | |
57779d06 VS |
2675 | switch (fb->pixel_format) { |
2676 | case DRM_FORMAT_C8: | |
81255565 JB |
2677 | dspcntr |= DISPPLANE_8BPP; |
2678 | break; | |
57779d06 | 2679 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2680 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2681 | break; |
57779d06 VS |
2682 | case DRM_FORMAT_RGB565: |
2683 | dspcntr |= DISPPLANE_BGRX565; | |
2684 | break; | |
2685 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2686 | dspcntr |= DISPPLANE_BGRX888; |
2687 | break; | |
2688 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2689 | dspcntr |= DISPPLANE_RGBX888; |
2690 | break; | |
2691 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2692 | dspcntr |= DISPPLANE_BGRX101010; |
2693 | break; | |
2694 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2695 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2696 | break; |
2697 | default: | |
baba133a | 2698 | BUG(); |
81255565 | 2699 | } |
57779d06 | 2700 | |
f45651ba VS |
2701 | if (INTEL_INFO(dev)->gen >= 4 && |
2702 | obj->tiling_mode != I915_TILING_NONE) | |
2703 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2704 | |
de1aa629 VS |
2705 | if (IS_G4X(dev)) |
2706 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2707 | ||
ac484963 | 2708 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2709 | |
c2c75131 DV |
2710 | if (INTEL_INFO(dev)->gen >= 4) { |
2711 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2712 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2713 | fb->pitches[0], rotation); |
c2c75131 DV |
2714 | linear_offset -= intel_crtc->dspaddr_offset; |
2715 | } else { | |
e506a0c6 | 2716 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2717 | } |
e506a0c6 | 2718 | |
8d0deca8 | 2719 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2720 | dspcntr |= DISPPLANE_ROTATE_180; |
2721 | ||
a8d201af ML |
2722 | x += (crtc_state->pipe_src_w - 1); |
2723 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2724 | |
2725 | /* Finding the last pixel of the last line of the display | |
2726 | data and adding to linear_offset*/ | |
2727 | linear_offset += | |
a8d201af | 2728 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2729 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2730 | } |
2731 | ||
2db3366b PZ |
2732 | intel_crtc->adjusted_x = x; |
2733 | intel_crtc->adjusted_y = y; | |
2734 | ||
48404c1e SJ |
2735 | I915_WRITE(reg, dspcntr); |
2736 | ||
01f2c773 | 2737 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2738 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2739 | I915_WRITE(DSPSURF(plane), |
2740 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2741 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2742 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2743 | } else |
f343c5f6 | 2744 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2745 | POSTING_READ(reg); |
17638cd6 JB |
2746 | } |
2747 | ||
a8d201af ML |
2748 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2749 | struct drm_crtc *crtc) | |
17638cd6 JB |
2750 | { |
2751 | struct drm_device *dev = crtc->dev; | |
2752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2753 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2754 | int plane = intel_crtc->plane; |
f45651ba | 2755 | |
a8d201af ML |
2756 | I915_WRITE(DSPCNTR(plane), 0); |
2757 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2758 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2759 | else |
2760 | I915_WRITE(DSPADDR(plane), 0); | |
2761 | POSTING_READ(DSPCNTR(plane)); | |
2762 | } | |
c9ba6fad | 2763 | |
a8d201af ML |
2764 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2765 | const struct intel_crtc_state *crtc_state, | |
2766 | const struct intel_plane_state *plane_state) | |
2767 | { | |
2768 | struct drm_device *dev = primary->dev; | |
2769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2770 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2771 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2772 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2773 | int plane = intel_crtc->plane; | |
54ea9da8 | 2774 | u32 linear_offset; |
a8d201af ML |
2775 | u32 dspcntr; |
2776 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2777 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2778 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2779 | int x = plane_state->src.x1 >> 16; |
2780 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2781 | |
f45651ba | 2782 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2783 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2784 | |
2785 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2786 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2787 | |
57779d06 VS |
2788 | switch (fb->pixel_format) { |
2789 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2790 | dspcntr |= DISPPLANE_8BPP; |
2791 | break; | |
57779d06 VS |
2792 | case DRM_FORMAT_RGB565: |
2793 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2794 | break; |
57779d06 | 2795 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2796 | dspcntr |= DISPPLANE_BGRX888; |
2797 | break; | |
2798 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2799 | dspcntr |= DISPPLANE_RGBX888; |
2800 | break; | |
2801 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2802 | dspcntr |= DISPPLANE_BGRX101010; |
2803 | break; | |
2804 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2805 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2806 | break; |
2807 | default: | |
baba133a | 2808 | BUG(); |
17638cd6 JB |
2809 | } |
2810 | ||
2811 | if (obj->tiling_mode != I915_TILING_NONE) | |
2812 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2813 | |
f45651ba | 2814 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2815 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2816 | |
ac484963 | 2817 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2818 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2819 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2820 | fb->pitches[0], rotation); |
c2c75131 | 2821 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2822 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2823 | dspcntr |= DISPPLANE_ROTATE_180; |
2824 | ||
2825 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2826 | x += (crtc_state->pipe_src_w - 1); |
2827 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2828 | |
2829 | /* Finding the last pixel of the last line of the display | |
2830 | data and adding to linear_offset*/ | |
2831 | linear_offset += | |
a8d201af | 2832 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2833 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2834 | } |
2835 | } | |
2836 | ||
2db3366b PZ |
2837 | intel_crtc->adjusted_x = x; |
2838 | intel_crtc->adjusted_y = y; | |
2839 | ||
48404c1e | 2840 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2841 | |
01f2c773 | 2842 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2843 | I915_WRITE(DSPSURF(plane), |
2844 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2845 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2846 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2847 | } else { | |
2848 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2849 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2850 | } | |
17638cd6 | 2851 | POSTING_READ(reg); |
17638cd6 JB |
2852 | } |
2853 | ||
7b49f948 VS |
2854 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2855 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2856 | { |
7b49f948 | 2857 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2858 | return 64; |
7b49f948 VS |
2859 | } else { |
2860 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2861 | ||
27ba3910 | 2862 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2863 | } |
2864 | } | |
2865 | ||
44eb0cb9 MK |
2866 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2867 | struct drm_i915_gem_object *obj, | |
2868 | unsigned int plane) | |
121920fa | 2869 | { |
ce7f1728 | 2870 | struct i915_ggtt_view view; |
dedf278c | 2871 | struct i915_vma *vma; |
44eb0cb9 | 2872 | u64 offset; |
121920fa | 2873 | |
e7941294 | 2874 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 2875 | intel_plane->base.state->rotation); |
121920fa | 2876 | |
ce7f1728 | 2877 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2878 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2879 | view.type)) |
dedf278c TU |
2880 | return -1; |
2881 | ||
44eb0cb9 | 2882 | offset = vma->node.start; |
dedf278c TU |
2883 | |
2884 | if (plane == 1) { | |
7723f47d | 2885 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2886 | PAGE_SIZE; |
2887 | } | |
2888 | ||
44eb0cb9 MK |
2889 | WARN_ON(upper_32_bits(offset)); |
2890 | ||
2891 | return lower_32_bits(offset); | |
121920fa TU |
2892 | } |
2893 | ||
e435d6e5 ML |
2894 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2895 | { | |
2896 | struct drm_device *dev = intel_crtc->base.dev; | |
2897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2898 | ||
2899 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2900 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2901 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2902 | } |
2903 | ||
a1b2278e CK |
2904 | /* |
2905 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2906 | */ | |
0583236e | 2907 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2908 | { |
a1b2278e CK |
2909 | struct intel_crtc_scaler_state *scaler_state; |
2910 | int i; | |
2911 | ||
a1b2278e CK |
2912 | scaler_state = &intel_crtc->config->scaler_state; |
2913 | ||
2914 | /* loop through and disable scalers that aren't in use */ | |
2915 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2916 | if (!scaler_state->scalers[i].in_use) |
2917 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2918 | } |
2919 | } | |
2920 | ||
6156a456 | 2921 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2922 | { |
6156a456 | 2923 | switch (pixel_format) { |
d161cf7a | 2924 | case DRM_FORMAT_C8: |
c34ce3d1 | 2925 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2926 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2927 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2928 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2929 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2930 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2931 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2932 | /* |
2933 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2934 | * to be already pre-multiplied. We need to add a knob (or a different | |
2935 | * DRM_FORMAT) for user-space to configure that. | |
2936 | */ | |
f75fb42a | 2937 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2938 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2939 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2940 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2941 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2942 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2943 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2944 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2945 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2946 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2947 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2948 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2949 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2950 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2951 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2952 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2953 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2954 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2955 | default: |
4249eeef | 2956 | MISSING_CASE(pixel_format); |
70d21f0e | 2957 | } |
8cfcba41 | 2958 | |
c34ce3d1 | 2959 | return 0; |
6156a456 | 2960 | } |
70d21f0e | 2961 | |
6156a456 CK |
2962 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2963 | { | |
6156a456 | 2964 | switch (fb_modifier) { |
30af77c4 | 2965 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2966 | break; |
30af77c4 | 2967 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2968 | return PLANE_CTL_TILED_X; |
b321803d | 2969 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2970 | return PLANE_CTL_TILED_Y; |
b321803d | 2971 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2972 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2973 | default: |
6156a456 | 2974 | MISSING_CASE(fb_modifier); |
70d21f0e | 2975 | } |
8cfcba41 | 2976 | |
c34ce3d1 | 2977 | return 0; |
6156a456 | 2978 | } |
70d21f0e | 2979 | |
6156a456 CK |
2980 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2981 | { | |
3b7a5119 | 2982 | switch (rotation) { |
6156a456 CK |
2983 | case BIT(DRM_ROTATE_0): |
2984 | break; | |
1e8df167 SJ |
2985 | /* |
2986 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
2987 | * while i915 HW rotation is clockwise, thats why this swapping. | |
2988 | */ | |
3b7a5119 | 2989 | case BIT(DRM_ROTATE_90): |
1e8df167 | 2990 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 2991 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 2992 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 2993 | case BIT(DRM_ROTATE_270): |
1e8df167 | 2994 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
2995 | default: |
2996 | MISSING_CASE(rotation); | |
2997 | } | |
2998 | ||
c34ce3d1 | 2999 | return 0; |
6156a456 CK |
3000 | } |
3001 | ||
a8d201af ML |
3002 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3003 | const struct intel_crtc_state *crtc_state, | |
3004 | const struct intel_plane_state *plane_state) | |
6156a456 | 3005 | { |
a8d201af | 3006 | struct drm_device *dev = plane->dev; |
6156a456 | 3007 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3009 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3010 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3011 | int pipe = intel_crtc->pipe; |
3012 | u32 plane_ctl, stride_div, stride; | |
3013 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3014 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3015 | int x_offset, y_offset; |
44eb0cb9 | 3016 | u32 surf_addr; |
a8d201af ML |
3017 | int scaler_id = plane_state->scaler_id; |
3018 | int src_x = plane_state->src.x1 >> 16; | |
3019 | int src_y = plane_state->src.y1 >> 16; | |
3020 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3021 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3022 | int dst_x = plane_state->dst.x1; | |
3023 | int dst_y = plane_state->dst.y1; | |
3024 | int dst_w = drm_rect_width(&plane_state->dst); | |
3025 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3026 | |
6156a456 CK |
3027 | plane_ctl = PLANE_CTL_ENABLE | |
3028 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3029 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3030 | ||
3031 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3032 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3033 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3034 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3035 | ||
7b49f948 | 3036 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3037 | fb->pixel_format); |
dedf278c | 3038 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3039 | |
a42e5a23 PZ |
3040 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3041 | ||
3b7a5119 | 3042 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3043 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3044 | ||
3b7a5119 | 3045 | /* stride = Surface height in tiles */ |
832be82f | 3046 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3047 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3048 | x_offset = stride * tile_height - src_y - src_h; |
3049 | y_offset = src_x; | |
6156a456 | 3050 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3051 | } else { |
3052 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3053 | x_offset = src_x; |
3054 | y_offset = src_y; | |
6156a456 | 3055 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3056 | } |
3057 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3058 | |
2db3366b PZ |
3059 | intel_crtc->adjusted_x = x_offset; |
3060 | intel_crtc->adjusted_y = y_offset; | |
3061 | ||
70d21f0e | 3062 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3063 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3064 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3065 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3066 | |
3067 | if (scaler_id >= 0) { | |
3068 | uint32_t ps_ctrl = 0; | |
3069 | ||
3070 | WARN_ON(!dst_w || !dst_h); | |
3071 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3072 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3073 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3074 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3075 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3076 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3077 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3078 | } else { | |
3079 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3080 | } | |
3081 | ||
121920fa | 3082 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3083 | |
3084 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3085 | } | |
3086 | ||
a8d201af ML |
3087 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3088 | struct drm_crtc *crtc) | |
17638cd6 JB |
3089 | { |
3090 | struct drm_device *dev = crtc->dev; | |
3091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3092 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3093 | |
a8d201af ML |
3094 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3095 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3096 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3097 | } | |
29b9bde6 | 3098 | |
a8d201af ML |
3099 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3100 | static int | |
3101 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3102 | int x, int y, enum mode_set_atomic state) | |
3103 | { | |
3104 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3105 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3106 | ||
3107 | return -ENODEV; | |
81255565 JB |
3108 | } |
3109 | ||
91d14251 | 3110 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
96a02917 | 3111 | { |
96a02917 VS |
3112 | struct drm_crtc *crtc; |
3113 | ||
91d14251 | 3114 | for_each_crtc(dev_priv->dev, crtc) { |
96a02917 VS |
3115 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3116 | enum plane plane = intel_crtc->plane; | |
3117 | ||
91d14251 TU |
3118 | intel_prepare_page_flip(dev_priv, plane); |
3119 | intel_finish_page_flip_plane(dev_priv, plane); | |
96a02917 | 3120 | } |
7514747d VS |
3121 | } |
3122 | ||
3123 | static void intel_update_primary_planes(struct drm_device *dev) | |
3124 | { | |
7514747d | 3125 | struct drm_crtc *crtc; |
96a02917 | 3126 | |
70e1e0ec | 3127 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3128 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3129 | struct intel_plane_state *plane_state; | |
96a02917 | 3130 | |
11c22da6 | 3131 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3132 | plane_state = to_intel_plane_state(plane->base.state); |
3133 | ||
a8d201af ML |
3134 | if (plane_state->visible) |
3135 | plane->update_plane(&plane->base, | |
3136 | to_intel_crtc_state(crtc->state), | |
3137 | plane_state); | |
11c22da6 ML |
3138 | |
3139 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3140 | } |
3141 | } | |
3142 | ||
c033666a | 3143 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d VS |
3144 | { |
3145 | /* no reset support for gen2 */ | |
c033666a | 3146 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3147 | return; |
3148 | ||
3149 | /* reset doesn't touch the display */ | |
c033666a | 3150 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
7514747d VS |
3151 | return; |
3152 | ||
c033666a | 3153 | drm_modeset_lock_all(dev_priv->dev); |
f98ce92f VS |
3154 | /* |
3155 | * Disabling the crtcs gracefully seems nicer. Also the | |
3156 | * g33 docs say we should at least disable all the planes. | |
3157 | */ | |
c033666a | 3158 | intel_display_suspend(dev_priv->dev); |
7514747d VS |
3159 | } |
3160 | ||
c033666a | 3161 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3162 | { |
7514747d VS |
3163 | /* |
3164 | * Flips in the rings will be nuked by the reset, | |
3165 | * so complete all pending flips so that user space | |
3166 | * will get its events and not get stuck. | |
3167 | */ | |
91d14251 | 3168 | intel_complete_page_flips(dev_priv); |
7514747d VS |
3169 | |
3170 | /* no reset support for gen2 */ | |
c033666a | 3171 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3172 | return; |
3173 | ||
3174 | /* reset doesn't touch the display */ | |
c033666a | 3175 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
7514747d VS |
3176 | /* |
3177 | * Flips in the rings have been nuked by the reset, | |
3178 | * so update the base address of all primary | |
3179 | * planes to the the last fb to make sure we're | |
3180 | * showing the correct fb after a reset. | |
11c22da6 ML |
3181 | * |
3182 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3183 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d | 3184 | */ |
c033666a | 3185 | intel_update_primary_planes(dev_priv->dev); |
7514747d VS |
3186 | return; |
3187 | } | |
3188 | ||
3189 | /* | |
3190 | * The display has been reset as well, | |
3191 | * so need a full re-initialization. | |
3192 | */ | |
3193 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3194 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3195 | ||
c033666a | 3196 | intel_modeset_init_hw(dev_priv->dev); |
7514747d VS |
3197 | |
3198 | spin_lock_irq(&dev_priv->irq_lock); | |
3199 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 3200 | dev_priv->display.hpd_irq_setup(dev_priv); |
7514747d VS |
3201 | spin_unlock_irq(&dev_priv->irq_lock); |
3202 | ||
c033666a | 3203 | intel_display_resume(dev_priv->dev); |
7514747d VS |
3204 | |
3205 | intel_hpd_init(dev_priv); | |
3206 | ||
c033666a | 3207 | drm_modeset_unlock_all(dev_priv->dev); |
7514747d VS |
3208 | } |
3209 | ||
7d5e3799 CW |
3210 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3211 | { | |
3212 | struct drm_device *dev = crtc->dev; | |
7d5e3799 | 3213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
c19ae989 | 3214 | unsigned reset_counter; |
7d5e3799 CW |
3215 | bool pending; |
3216 | ||
7f1847eb CW |
3217 | reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error); |
3218 | if (intel_crtc->reset_counter != reset_counter) | |
7d5e3799 CW |
3219 | return false; |
3220 | ||
5e2d7afc | 3221 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3222 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3223 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3224 | |
3225 | return pending; | |
3226 | } | |
3227 | ||
bfd16b2a ML |
3228 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3229 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3230 | { |
3231 | struct drm_device *dev = crtc->base.dev; | |
3232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3233 | struct intel_crtc_state *pipe_config = |
3234 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3235 | |
bfd16b2a ML |
3236 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3237 | crtc->base.mode = crtc->base.state->mode; | |
3238 | ||
3239 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3240 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3241 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3242 | |
3243 | /* | |
3244 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3245 | * that in compute_mode_changes we check the native mode (not the pfit | |
3246 | * mode) to see if we can flip rather than do a full mode set. In the | |
3247 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3248 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3249 | * sized surface. | |
e30e8f75 GP |
3250 | */ |
3251 | ||
e30e8f75 | 3252 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3253 | ((pipe_config->pipe_src_w - 1) << 16) | |
3254 | (pipe_config->pipe_src_h - 1)); | |
3255 | ||
3256 | /* on skylake this is done by detaching scalers */ | |
3257 | if (INTEL_INFO(dev)->gen >= 9) { | |
3258 | skl_detach_scalers(crtc); | |
3259 | ||
3260 | if (pipe_config->pch_pfit.enabled) | |
3261 | skylake_pfit_enable(crtc); | |
3262 | } else if (HAS_PCH_SPLIT(dev)) { | |
3263 | if (pipe_config->pch_pfit.enabled) | |
3264 | ironlake_pfit_enable(crtc); | |
3265 | else if (old_crtc_state->pch_pfit.enabled) | |
3266 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3267 | } |
e30e8f75 GP |
3268 | } |
3269 | ||
5e84e1a4 ZW |
3270 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3271 | { | |
3272 | struct drm_device *dev = crtc->dev; | |
3273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3274 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3275 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3276 | i915_reg_t reg; |
3277 | u32 temp; | |
5e84e1a4 ZW |
3278 | |
3279 | /* enable normal train */ | |
3280 | reg = FDI_TX_CTL(pipe); | |
3281 | temp = I915_READ(reg); | |
61e499bf | 3282 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3283 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3284 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3285 | } else { |
3286 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3287 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3288 | } |
5e84e1a4 ZW |
3289 | I915_WRITE(reg, temp); |
3290 | ||
3291 | reg = FDI_RX_CTL(pipe); | |
3292 | temp = I915_READ(reg); | |
3293 | if (HAS_PCH_CPT(dev)) { | |
3294 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3295 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3296 | } else { | |
3297 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3298 | temp |= FDI_LINK_TRAIN_NONE; | |
3299 | } | |
3300 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3301 | ||
3302 | /* wait one idle pattern time */ | |
3303 | POSTING_READ(reg); | |
3304 | udelay(1000); | |
357555c0 JB |
3305 | |
3306 | /* IVB wants error correction enabled */ | |
3307 | if (IS_IVYBRIDGE(dev)) | |
3308 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3309 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3310 | } |
3311 | ||
8db9d77b ZW |
3312 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3313 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3314 | { | |
3315 | struct drm_device *dev = crtc->dev; | |
3316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3318 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3319 | i915_reg_t reg; |
3320 | u32 temp, tries; | |
8db9d77b | 3321 | |
1c8562f6 | 3322 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3323 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3324 | |
e1a44743 AJ |
3325 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3326 | for train result */ | |
5eddb70b CW |
3327 | reg = FDI_RX_IMR(pipe); |
3328 | temp = I915_READ(reg); | |
e1a44743 AJ |
3329 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3330 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3331 | I915_WRITE(reg, temp); |
3332 | I915_READ(reg); | |
e1a44743 AJ |
3333 | udelay(150); |
3334 | ||
8db9d77b | 3335 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3336 | reg = FDI_TX_CTL(pipe); |
3337 | temp = I915_READ(reg); | |
627eb5a3 | 3338 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3339 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3340 | temp &= ~FDI_LINK_TRAIN_NONE; |
3341 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3342 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3343 | |
5eddb70b CW |
3344 | reg = FDI_RX_CTL(pipe); |
3345 | temp = I915_READ(reg); | |
8db9d77b ZW |
3346 | temp &= ~FDI_LINK_TRAIN_NONE; |
3347 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3348 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3349 | ||
3350 | POSTING_READ(reg); | |
8db9d77b ZW |
3351 | udelay(150); |
3352 | ||
5b2adf89 | 3353 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3354 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3355 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3356 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3357 | |
5eddb70b | 3358 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3359 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3360 | temp = I915_READ(reg); |
8db9d77b ZW |
3361 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3362 | ||
3363 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3364 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3365 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3366 | break; |
3367 | } | |
8db9d77b | 3368 | } |
e1a44743 | 3369 | if (tries == 5) |
5eddb70b | 3370 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3371 | |
3372 | /* Train 2 */ | |
5eddb70b CW |
3373 | reg = FDI_TX_CTL(pipe); |
3374 | temp = I915_READ(reg); | |
8db9d77b ZW |
3375 | temp &= ~FDI_LINK_TRAIN_NONE; |
3376 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3377 | I915_WRITE(reg, temp); |
8db9d77b | 3378 | |
5eddb70b CW |
3379 | reg = FDI_RX_CTL(pipe); |
3380 | temp = I915_READ(reg); | |
8db9d77b ZW |
3381 | temp &= ~FDI_LINK_TRAIN_NONE; |
3382 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3383 | I915_WRITE(reg, temp); |
8db9d77b | 3384 | |
5eddb70b CW |
3385 | POSTING_READ(reg); |
3386 | udelay(150); | |
8db9d77b | 3387 | |
5eddb70b | 3388 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3389 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3390 | temp = I915_READ(reg); |
8db9d77b ZW |
3391 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3392 | ||
3393 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3394 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3395 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3396 | break; | |
3397 | } | |
8db9d77b | 3398 | } |
e1a44743 | 3399 | if (tries == 5) |
5eddb70b | 3400 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3401 | |
3402 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3403 | |
8db9d77b ZW |
3404 | } |
3405 | ||
0206e353 | 3406 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3407 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3408 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3409 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3410 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3411 | }; | |
3412 | ||
3413 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3414 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3415 | { | |
3416 | struct drm_device *dev = crtc->dev; | |
3417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3418 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3419 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3420 | i915_reg_t reg; |
3421 | u32 temp, i, retry; | |
8db9d77b | 3422 | |
e1a44743 AJ |
3423 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3424 | for train result */ | |
5eddb70b CW |
3425 | reg = FDI_RX_IMR(pipe); |
3426 | temp = I915_READ(reg); | |
e1a44743 AJ |
3427 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3428 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3429 | I915_WRITE(reg, temp); |
3430 | ||
3431 | POSTING_READ(reg); | |
e1a44743 AJ |
3432 | udelay(150); |
3433 | ||
8db9d77b | 3434 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3435 | reg = FDI_TX_CTL(pipe); |
3436 | temp = I915_READ(reg); | |
627eb5a3 | 3437 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3438 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3439 | temp &= ~FDI_LINK_TRAIN_NONE; |
3440 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3441 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3442 | /* SNB-B */ | |
3443 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3444 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3445 | |
d74cf324 DV |
3446 | I915_WRITE(FDI_RX_MISC(pipe), |
3447 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3448 | ||
5eddb70b CW |
3449 | reg = FDI_RX_CTL(pipe); |
3450 | temp = I915_READ(reg); | |
8db9d77b ZW |
3451 | if (HAS_PCH_CPT(dev)) { |
3452 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3453 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3454 | } else { | |
3455 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3456 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3457 | } | |
5eddb70b CW |
3458 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3459 | ||
3460 | POSTING_READ(reg); | |
8db9d77b ZW |
3461 | udelay(150); |
3462 | ||
0206e353 | 3463 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3464 | reg = FDI_TX_CTL(pipe); |
3465 | temp = I915_READ(reg); | |
8db9d77b ZW |
3466 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3467 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3468 | I915_WRITE(reg, temp); |
3469 | ||
3470 | POSTING_READ(reg); | |
8db9d77b ZW |
3471 | udelay(500); |
3472 | ||
fa37d39e SP |
3473 | for (retry = 0; retry < 5; retry++) { |
3474 | reg = FDI_RX_IIR(pipe); | |
3475 | temp = I915_READ(reg); | |
3476 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3477 | if (temp & FDI_RX_BIT_LOCK) { | |
3478 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3479 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3480 | break; | |
3481 | } | |
3482 | udelay(50); | |
8db9d77b | 3483 | } |
fa37d39e SP |
3484 | if (retry < 5) |
3485 | break; | |
8db9d77b ZW |
3486 | } |
3487 | if (i == 4) | |
5eddb70b | 3488 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3489 | |
3490 | /* Train 2 */ | |
5eddb70b CW |
3491 | reg = FDI_TX_CTL(pipe); |
3492 | temp = I915_READ(reg); | |
8db9d77b ZW |
3493 | temp &= ~FDI_LINK_TRAIN_NONE; |
3494 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3495 | if (IS_GEN6(dev)) { | |
3496 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3497 | /* SNB-B */ | |
3498 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3499 | } | |
5eddb70b | 3500 | I915_WRITE(reg, temp); |
8db9d77b | 3501 | |
5eddb70b CW |
3502 | reg = FDI_RX_CTL(pipe); |
3503 | temp = I915_READ(reg); | |
8db9d77b ZW |
3504 | if (HAS_PCH_CPT(dev)) { |
3505 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3506 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3507 | } else { | |
3508 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3509 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3510 | } | |
5eddb70b CW |
3511 | I915_WRITE(reg, temp); |
3512 | ||
3513 | POSTING_READ(reg); | |
8db9d77b ZW |
3514 | udelay(150); |
3515 | ||
0206e353 | 3516 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3517 | reg = FDI_TX_CTL(pipe); |
3518 | temp = I915_READ(reg); | |
8db9d77b ZW |
3519 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3520 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3521 | I915_WRITE(reg, temp); |
3522 | ||
3523 | POSTING_READ(reg); | |
8db9d77b ZW |
3524 | udelay(500); |
3525 | ||
fa37d39e SP |
3526 | for (retry = 0; retry < 5; retry++) { |
3527 | reg = FDI_RX_IIR(pipe); | |
3528 | temp = I915_READ(reg); | |
3529 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3530 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3531 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3532 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3533 | break; | |
3534 | } | |
3535 | udelay(50); | |
8db9d77b | 3536 | } |
fa37d39e SP |
3537 | if (retry < 5) |
3538 | break; | |
8db9d77b ZW |
3539 | } |
3540 | if (i == 4) | |
5eddb70b | 3541 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3542 | |
3543 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3544 | } | |
3545 | ||
357555c0 JB |
3546 | /* Manual link training for Ivy Bridge A0 parts */ |
3547 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3548 | { | |
3549 | struct drm_device *dev = crtc->dev; | |
3550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3551 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3552 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3553 | i915_reg_t reg; |
3554 | u32 temp, i, j; | |
357555c0 JB |
3555 | |
3556 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3557 | for train result */ | |
3558 | reg = FDI_RX_IMR(pipe); | |
3559 | temp = I915_READ(reg); | |
3560 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3561 | temp &= ~FDI_RX_BIT_LOCK; | |
3562 | I915_WRITE(reg, temp); | |
3563 | ||
3564 | POSTING_READ(reg); | |
3565 | udelay(150); | |
3566 | ||
01a415fd DV |
3567 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3568 | I915_READ(FDI_RX_IIR(pipe))); | |
3569 | ||
139ccd3f JB |
3570 | /* Try each vswing and preemphasis setting twice before moving on */ |
3571 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3572 | /* disable first in case we need to retry */ | |
3573 | reg = FDI_TX_CTL(pipe); | |
3574 | temp = I915_READ(reg); | |
3575 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3576 | temp &= ~FDI_TX_ENABLE; | |
3577 | I915_WRITE(reg, temp); | |
357555c0 | 3578 | |
139ccd3f JB |
3579 | reg = FDI_RX_CTL(pipe); |
3580 | temp = I915_READ(reg); | |
3581 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3582 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3583 | temp &= ~FDI_RX_ENABLE; | |
3584 | I915_WRITE(reg, temp); | |
357555c0 | 3585 | |
139ccd3f | 3586 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3587 | reg = FDI_TX_CTL(pipe); |
3588 | temp = I915_READ(reg); | |
139ccd3f | 3589 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3590 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3591 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3592 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3593 | temp |= snb_b_fdi_train_param[j/2]; |
3594 | temp |= FDI_COMPOSITE_SYNC; | |
3595 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3596 | |
139ccd3f JB |
3597 | I915_WRITE(FDI_RX_MISC(pipe), |
3598 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3599 | |
139ccd3f | 3600 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3601 | temp = I915_READ(reg); |
139ccd3f JB |
3602 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3603 | temp |= FDI_COMPOSITE_SYNC; | |
3604 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3605 | |
139ccd3f JB |
3606 | POSTING_READ(reg); |
3607 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3608 | |
139ccd3f JB |
3609 | for (i = 0; i < 4; i++) { |
3610 | reg = FDI_RX_IIR(pipe); | |
3611 | temp = I915_READ(reg); | |
3612 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3613 | |
139ccd3f JB |
3614 | if (temp & FDI_RX_BIT_LOCK || |
3615 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3616 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3617 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3618 | i); | |
3619 | break; | |
3620 | } | |
3621 | udelay(1); /* should be 0.5us */ | |
3622 | } | |
3623 | if (i == 4) { | |
3624 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3625 | continue; | |
3626 | } | |
357555c0 | 3627 | |
139ccd3f | 3628 | /* Train 2 */ |
357555c0 JB |
3629 | reg = FDI_TX_CTL(pipe); |
3630 | temp = I915_READ(reg); | |
139ccd3f JB |
3631 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3632 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3633 | I915_WRITE(reg, temp); | |
3634 | ||
3635 | reg = FDI_RX_CTL(pipe); | |
3636 | temp = I915_READ(reg); | |
3637 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3638 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3639 | I915_WRITE(reg, temp); |
3640 | ||
3641 | POSTING_READ(reg); | |
139ccd3f | 3642 | udelay(2); /* should be 1.5us */ |
357555c0 | 3643 | |
139ccd3f JB |
3644 | for (i = 0; i < 4; i++) { |
3645 | reg = FDI_RX_IIR(pipe); | |
3646 | temp = I915_READ(reg); | |
3647 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3648 | |
139ccd3f JB |
3649 | if (temp & FDI_RX_SYMBOL_LOCK || |
3650 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3651 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3652 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3653 | i); | |
3654 | goto train_done; | |
3655 | } | |
3656 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3657 | } |
139ccd3f JB |
3658 | if (i == 4) |
3659 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3660 | } |
357555c0 | 3661 | |
139ccd3f | 3662 | train_done: |
357555c0 JB |
3663 | DRM_DEBUG_KMS("FDI train done.\n"); |
3664 | } | |
3665 | ||
88cefb6c | 3666 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3667 | { |
88cefb6c | 3668 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3669 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3670 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3671 | i915_reg_t reg; |
3672 | u32 temp; | |
c64e311e | 3673 | |
c98e9dcf | 3674 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3675 | reg = FDI_RX_CTL(pipe); |
3676 | temp = I915_READ(reg); | |
627eb5a3 | 3677 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3678 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3679 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3680 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3681 | ||
3682 | POSTING_READ(reg); | |
c98e9dcf JB |
3683 | udelay(200); |
3684 | ||
3685 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3686 | temp = I915_READ(reg); |
3687 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3688 | ||
3689 | POSTING_READ(reg); | |
c98e9dcf JB |
3690 | udelay(200); |
3691 | ||
20749730 PZ |
3692 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3693 | reg = FDI_TX_CTL(pipe); | |
3694 | temp = I915_READ(reg); | |
3695 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3696 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3697 | |
20749730 PZ |
3698 | POSTING_READ(reg); |
3699 | udelay(100); | |
6be4a607 | 3700 | } |
0e23b99d JB |
3701 | } |
3702 | ||
88cefb6c DV |
3703 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3704 | { | |
3705 | struct drm_device *dev = intel_crtc->base.dev; | |
3706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3707 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3708 | i915_reg_t reg; |
3709 | u32 temp; | |
88cefb6c DV |
3710 | |
3711 | /* Switch from PCDclk to Rawclk */ | |
3712 | reg = FDI_RX_CTL(pipe); | |
3713 | temp = I915_READ(reg); | |
3714 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3715 | ||
3716 | /* Disable CPU FDI TX PLL */ | |
3717 | reg = FDI_TX_CTL(pipe); | |
3718 | temp = I915_READ(reg); | |
3719 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3720 | ||
3721 | POSTING_READ(reg); | |
3722 | udelay(100); | |
3723 | ||
3724 | reg = FDI_RX_CTL(pipe); | |
3725 | temp = I915_READ(reg); | |
3726 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3727 | ||
3728 | /* Wait for the clocks to turn off. */ | |
3729 | POSTING_READ(reg); | |
3730 | udelay(100); | |
3731 | } | |
3732 | ||
0fc932b8 JB |
3733 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3734 | { | |
3735 | struct drm_device *dev = crtc->dev; | |
3736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3737 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3738 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3739 | i915_reg_t reg; |
3740 | u32 temp; | |
0fc932b8 JB |
3741 | |
3742 | /* disable CPU FDI tx and PCH FDI rx */ | |
3743 | reg = FDI_TX_CTL(pipe); | |
3744 | temp = I915_READ(reg); | |
3745 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3746 | POSTING_READ(reg); | |
3747 | ||
3748 | reg = FDI_RX_CTL(pipe); | |
3749 | temp = I915_READ(reg); | |
3750 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3751 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3752 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3753 | ||
3754 | POSTING_READ(reg); | |
3755 | udelay(100); | |
3756 | ||
3757 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3758 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3759 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3760 | |
3761 | /* still set train pattern 1 */ | |
3762 | reg = FDI_TX_CTL(pipe); | |
3763 | temp = I915_READ(reg); | |
3764 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3765 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3766 | I915_WRITE(reg, temp); | |
3767 | ||
3768 | reg = FDI_RX_CTL(pipe); | |
3769 | temp = I915_READ(reg); | |
3770 | if (HAS_PCH_CPT(dev)) { | |
3771 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3772 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3773 | } else { | |
3774 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3775 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3776 | } | |
3777 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3778 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3779 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3780 | I915_WRITE(reg, temp); |
3781 | ||
3782 | POSTING_READ(reg); | |
3783 | udelay(100); | |
3784 | } | |
3785 | ||
5dce5b93 CW |
3786 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3787 | { | |
3788 | struct intel_crtc *crtc; | |
3789 | ||
3790 | /* Note that we don't need to be called with mode_config.lock here | |
3791 | * as our list of CRTC objects is static for the lifetime of the | |
3792 | * device and so cannot disappear as we iterate. Similarly, we can | |
3793 | * happily treat the predicates as racy, atomic checks as userspace | |
3794 | * cannot claim and pin a new fb without at least acquring the | |
3795 | * struct_mutex and so serialising with us. | |
3796 | */ | |
d3fcc808 | 3797 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3798 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3799 | continue; | |
3800 | ||
3801 | if (crtc->unpin_work) | |
3802 | intel_wait_for_vblank(dev, crtc->pipe); | |
3803 | ||
3804 | return true; | |
3805 | } | |
3806 | ||
3807 | return false; | |
3808 | } | |
3809 | ||
d6bbafa1 CW |
3810 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3811 | { | |
3812 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3813 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3814 | ||
3815 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3816 | smp_rmb(); | |
3817 | intel_crtc->unpin_work = NULL; | |
3818 | ||
3819 | if (work->event) | |
560ce1dc | 3820 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
3821 | |
3822 | drm_crtc_vblank_put(&intel_crtc->base); | |
3823 | ||
3824 | wake_up_all(&dev_priv->pending_flip_queue); | |
3825 | queue_work(dev_priv->wq, &work->work); | |
3826 | ||
3827 | trace_i915_flip_complete(intel_crtc->plane, | |
3828 | work->pending_flip_obj); | |
3829 | } | |
3830 | ||
5008e874 | 3831 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3832 | { |
0f91128d | 3833 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3834 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3835 | long ret; |
e6c3a2a6 | 3836 | |
2c10d571 | 3837 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3838 | |
3839 | ret = wait_event_interruptible_timeout( | |
3840 | dev_priv->pending_flip_queue, | |
3841 | !intel_crtc_has_pending_flip(crtc), | |
3842 | 60*HZ); | |
3843 | ||
3844 | if (ret < 0) | |
3845 | return ret; | |
3846 | ||
3847 | if (ret == 0) { | |
9c787942 | 3848 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3849 | |
5e2d7afc | 3850 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3851 | if (intel_crtc->unpin_work) { |
3852 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3853 | page_flip_completed(intel_crtc); | |
3854 | } | |
5e2d7afc | 3855 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3856 | } |
5bb61643 | 3857 | |
5008e874 | 3858 | return 0; |
e6c3a2a6 CW |
3859 | } |
3860 | ||
060f02d8 VS |
3861 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3862 | { | |
3863 | u32 temp; | |
3864 | ||
3865 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3866 | ||
3867 | mutex_lock(&dev_priv->sb_lock); | |
3868 | ||
3869 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3870 | temp |= SBI_SSCCTL_DISABLE; | |
3871 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3872 | ||
3873 | mutex_unlock(&dev_priv->sb_lock); | |
3874 | } | |
3875 | ||
e615efe4 ED |
3876 | /* Program iCLKIP clock to the desired frequency */ |
3877 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3878 | { | |
64b46a06 | 3879 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 3880 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3881 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3882 | u32 temp; | |
3883 | ||
060f02d8 | 3884 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 3885 | |
64b46a06 VS |
3886 | /* The iCLK virtual clock root frequency is in MHz, |
3887 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3888 | * divisors, it is necessary to divide one by another, so we | |
3889 | * convert the virtual clock precision to KHz here for higher | |
3890 | * precision. | |
3891 | */ | |
3892 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
3893 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3894 | u32 iclk_pi_range = 64; | |
64b46a06 | 3895 | u32 desired_divisor; |
e615efe4 | 3896 | |
64b46a06 VS |
3897 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
3898 | clock << auxdiv); | |
3899 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3900 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 3901 | |
64b46a06 VS |
3902 | /* |
3903 | * Near 20MHz is a corner case which is | |
3904 | * out of range for the 7-bit divisor | |
3905 | */ | |
3906 | if (divsel <= 0x7f) | |
3907 | break; | |
e615efe4 ED |
3908 | } |
3909 | ||
3910 | /* This should not happen with any sane values */ | |
3911 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3912 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3913 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3914 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3915 | ||
3916 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3917 | clock, |
e615efe4 ED |
3918 | auxdiv, |
3919 | divsel, | |
3920 | phasedir, | |
3921 | phaseinc); | |
3922 | ||
060f02d8 VS |
3923 | mutex_lock(&dev_priv->sb_lock); |
3924 | ||
e615efe4 | 3925 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 3926 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3927 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3928 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3929 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3930 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3931 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3932 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3933 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3934 | |
3935 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3936 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3937 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3938 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3939 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3940 | |
3941 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3942 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3943 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3944 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 3945 | |
060f02d8 VS |
3946 | mutex_unlock(&dev_priv->sb_lock); |
3947 | ||
e615efe4 ED |
3948 | /* Wait for initialization time */ |
3949 | udelay(24); | |
3950 | ||
3951 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3952 | } | |
3953 | ||
8802e5b6 VS |
3954 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
3955 | { | |
3956 | u32 divsel, phaseinc, auxdiv; | |
3957 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3958 | u32 iclk_pi_range = 64; | |
3959 | u32 desired_divisor; | |
3960 | u32 temp; | |
3961 | ||
3962 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
3963 | return 0; | |
3964 | ||
3965 | mutex_lock(&dev_priv->sb_lock); | |
3966 | ||
3967 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3968 | if (temp & SBI_SSCCTL_DISABLE) { | |
3969 | mutex_unlock(&dev_priv->sb_lock); | |
3970 | return 0; | |
3971 | } | |
3972 | ||
3973 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
3974 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
3975 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
3976 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
3977 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
3978 | ||
3979 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
3980 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
3981 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
3982 | ||
3983 | mutex_unlock(&dev_priv->sb_lock); | |
3984 | ||
3985 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
3986 | ||
3987 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
3988 | desired_divisor << auxdiv); | |
3989 | } | |
3990 | ||
275f01b2 DV |
3991 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3992 | enum pipe pch_transcoder) | |
3993 | { | |
3994 | struct drm_device *dev = crtc->base.dev; | |
3995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3996 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3997 | |
3998 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3999 | I915_READ(HTOTAL(cpu_transcoder))); | |
4000 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4001 | I915_READ(HBLANK(cpu_transcoder))); | |
4002 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4003 | I915_READ(HSYNC(cpu_transcoder))); | |
4004 | ||
4005 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4006 | I915_READ(VTOTAL(cpu_transcoder))); | |
4007 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4008 | I915_READ(VBLANK(cpu_transcoder))); | |
4009 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4010 | I915_READ(VSYNC(cpu_transcoder))); | |
4011 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4012 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4013 | } | |
4014 | ||
003632d9 | 4015 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4016 | { |
4017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4018 | uint32_t temp; | |
4019 | ||
4020 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4021 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4022 | return; |
4023 | ||
4024 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4025 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4026 | ||
003632d9 ACO |
4027 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4028 | if (enable) | |
4029 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4030 | ||
4031 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4032 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4033 | POSTING_READ(SOUTH_CHICKEN1); | |
4034 | } | |
4035 | ||
4036 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4037 | { | |
4038 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4039 | |
4040 | switch (intel_crtc->pipe) { | |
4041 | case PIPE_A: | |
4042 | break; | |
4043 | case PIPE_B: | |
6e3c9717 | 4044 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4045 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4046 | else |
003632d9 | 4047 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4048 | |
4049 | break; | |
4050 | case PIPE_C: | |
003632d9 | 4051 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4052 | |
4053 | break; | |
4054 | default: | |
4055 | BUG(); | |
4056 | } | |
4057 | } | |
4058 | ||
c48b5305 VS |
4059 | /* Return which DP Port should be selected for Transcoder DP control */ |
4060 | static enum port | |
4061 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4062 | { | |
4063 | struct drm_device *dev = crtc->dev; | |
4064 | struct intel_encoder *encoder; | |
4065 | ||
4066 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4067 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4068 | encoder->type == INTEL_OUTPUT_EDP) | |
4069 | return enc_to_dig_port(&encoder->base)->port; | |
4070 | } | |
4071 | ||
4072 | return -1; | |
4073 | } | |
4074 | ||
f67a559d JB |
4075 | /* |
4076 | * Enable PCH resources required for PCH ports: | |
4077 | * - PCH PLLs | |
4078 | * - FDI training & RX/TX | |
4079 | * - update transcoder timings | |
4080 | * - DP transcoding bits | |
4081 | * - transcoder | |
4082 | */ | |
4083 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4084 | { |
4085 | struct drm_device *dev = crtc->dev; | |
4086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4087 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4088 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4089 | u32 temp; |
2c07245f | 4090 | |
ab9412ba | 4091 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4092 | |
1fbc0d78 DV |
4093 | if (IS_IVYBRIDGE(dev)) |
4094 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4095 | ||
cd986abb DV |
4096 | /* Write the TU size bits before fdi link training, so that error |
4097 | * detection works. */ | |
4098 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4099 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4100 | ||
c98e9dcf | 4101 | /* For PCH output, training FDI link */ |
674cf967 | 4102 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4103 | |
3ad8a208 DV |
4104 | /* We need to program the right clock selection before writing the pixel |
4105 | * mutliplier into the DPLL. */ | |
303b81e0 | 4106 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4107 | u32 sel; |
4b645f14 | 4108 | |
c98e9dcf | 4109 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4110 | temp |= TRANS_DPLL_ENABLE(pipe); |
4111 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4112 | if (intel_crtc->config->shared_dpll == |
4113 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4114 | temp |= sel; |
4115 | else | |
4116 | temp &= ~sel; | |
c98e9dcf | 4117 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4118 | } |
5eddb70b | 4119 | |
3ad8a208 DV |
4120 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4121 | * transcoder, and we actually should do this to not upset any PCH | |
4122 | * transcoder that already use the clock when we share it. | |
4123 | * | |
4124 | * Note that enable_shared_dpll tries to do the right thing, but | |
4125 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4126 | * the right LVDS enable sequence. */ | |
85b3894f | 4127 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4128 | |
d9b6cb56 JB |
4129 | /* set transcoder timing, panel must allow it */ |
4130 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4131 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4132 | |
303b81e0 | 4133 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4134 | |
c98e9dcf | 4135 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4136 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4137 | const struct drm_display_mode *adjusted_mode = |
4138 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4139 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4140 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4141 | temp = I915_READ(reg); |
4142 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4143 | TRANS_DP_SYNC_MASK | |
4144 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4145 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4146 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4147 | |
9c4edaee | 4148 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4149 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4150 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4151 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4152 | |
4153 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4154 | case PORT_B: |
5eddb70b | 4155 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4156 | break; |
c48b5305 | 4157 | case PORT_C: |
5eddb70b | 4158 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4159 | break; |
c48b5305 | 4160 | case PORT_D: |
5eddb70b | 4161 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4162 | break; |
4163 | default: | |
e95d41e1 | 4164 | BUG(); |
32f9d658 | 4165 | } |
2c07245f | 4166 | |
5eddb70b | 4167 | I915_WRITE(reg, temp); |
6be4a607 | 4168 | } |
b52eb4dc | 4169 | |
b8a4f404 | 4170 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4171 | } |
4172 | ||
1507e5bd PZ |
4173 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4174 | { | |
4175 | struct drm_device *dev = crtc->dev; | |
4176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4177 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4178 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4179 | |
ab9412ba | 4180 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4181 | |
8c52b5e8 | 4182 | lpt_program_iclkip(crtc); |
1507e5bd | 4183 | |
0540e488 | 4184 | /* Set transcoder timing. */ |
275f01b2 | 4185 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4186 | |
937bb610 | 4187 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4188 | } |
4189 | ||
a1520318 | 4190 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4191 | { |
4192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4193 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4194 | u32 temp; |
4195 | ||
4196 | temp = I915_READ(dslreg); | |
4197 | udelay(500); | |
4198 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4199 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4200 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4201 | } |
4202 | } | |
4203 | ||
86adf9d7 ML |
4204 | static int |
4205 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4206 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4207 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4208 | { |
86adf9d7 ML |
4209 | struct intel_crtc_scaler_state *scaler_state = |
4210 | &crtc_state->scaler_state; | |
4211 | struct intel_crtc *intel_crtc = | |
4212 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4213 | int need_scaling; |
6156a456 CK |
4214 | |
4215 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4216 | (src_h != dst_w || src_w != dst_h): | |
4217 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4218 | |
4219 | /* | |
4220 | * if plane is being disabled or scaler is no more required or force detach | |
4221 | * - free scaler binded to this plane/crtc | |
4222 | * - in order to do this, update crtc->scaler_usage | |
4223 | * | |
4224 | * Here scaler state in crtc_state is set free so that | |
4225 | * scaler can be assigned to other user. Actual register | |
4226 | * update to free the scaler is done in plane/panel-fit programming. | |
4227 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4228 | */ | |
86adf9d7 | 4229 | if (force_detach || !need_scaling) { |
a1b2278e | 4230 | if (*scaler_id >= 0) { |
86adf9d7 | 4231 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4232 | scaler_state->scalers[*scaler_id].in_use = 0; |
4233 | ||
86adf9d7 ML |
4234 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4235 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4236 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4237 | scaler_state->scaler_users); |
4238 | *scaler_id = -1; | |
4239 | } | |
4240 | return 0; | |
4241 | } | |
4242 | ||
4243 | /* range checks */ | |
4244 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4245 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4246 | ||
4247 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4248 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4249 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4250 | "size is out of scaler range\n", |
86adf9d7 | 4251 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4252 | return -EINVAL; |
4253 | } | |
4254 | ||
86adf9d7 ML |
4255 | /* mark this plane as a scaler user in crtc_state */ |
4256 | scaler_state->scaler_users |= (1 << scaler_user); | |
4257 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4258 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4259 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4260 | scaler_state->scaler_users); | |
4261 | ||
4262 | return 0; | |
4263 | } | |
4264 | ||
4265 | /** | |
4266 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4267 | * | |
4268 | * @state: crtc's scaler state | |
86adf9d7 ML |
4269 | * |
4270 | * Return | |
4271 | * 0 - scaler_usage updated successfully | |
4272 | * error - requested scaling cannot be supported or other error condition | |
4273 | */ | |
e435d6e5 | 4274 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4275 | { |
4276 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4277 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4278 | |
4279 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4280 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4281 | ||
e435d6e5 | 4282 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4283 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4284 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4285 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4286 | } |
4287 | ||
4288 | /** | |
4289 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4290 | * | |
4291 | * @state: crtc's scaler state | |
86adf9d7 ML |
4292 | * @plane_state: atomic plane state to update |
4293 | * | |
4294 | * Return | |
4295 | * 0 - scaler_usage updated successfully | |
4296 | * error - requested scaling cannot be supported or other error condition | |
4297 | */ | |
da20eabd ML |
4298 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4299 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4300 | { |
4301 | ||
4302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4303 | struct intel_plane *intel_plane = |
4304 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4305 | struct drm_framebuffer *fb = plane_state->base.fb; |
4306 | int ret; | |
4307 | ||
4308 | bool force_detach = !fb || !plane_state->visible; | |
4309 | ||
4310 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4311 | intel_plane->base.base.id, intel_crtc->pipe, | |
4312 | drm_plane_index(&intel_plane->base)); | |
4313 | ||
4314 | ret = skl_update_scaler(crtc_state, force_detach, | |
4315 | drm_plane_index(&intel_plane->base), | |
4316 | &plane_state->scaler_id, | |
4317 | plane_state->base.rotation, | |
4318 | drm_rect_width(&plane_state->src) >> 16, | |
4319 | drm_rect_height(&plane_state->src) >> 16, | |
4320 | drm_rect_width(&plane_state->dst), | |
4321 | drm_rect_height(&plane_state->dst)); | |
4322 | ||
4323 | if (ret || plane_state->scaler_id < 0) | |
4324 | return ret; | |
4325 | ||
a1b2278e | 4326 | /* check colorkey */ |
818ed961 | 4327 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4328 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4329 | intel_plane->base.base.id); |
a1b2278e CK |
4330 | return -EINVAL; |
4331 | } | |
4332 | ||
4333 | /* Check src format */ | |
86adf9d7 ML |
4334 | switch (fb->pixel_format) { |
4335 | case DRM_FORMAT_RGB565: | |
4336 | case DRM_FORMAT_XBGR8888: | |
4337 | case DRM_FORMAT_XRGB8888: | |
4338 | case DRM_FORMAT_ABGR8888: | |
4339 | case DRM_FORMAT_ARGB8888: | |
4340 | case DRM_FORMAT_XRGB2101010: | |
4341 | case DRM_FORMAT_XBGR2101010: | |
4342 | case DRM_FORMAT_YUYV: | |
4343 | case DRM_FORMAT_YVYU: | |
4344 | case DRM_FORMAT_UYVY: | |
4345 | case DRM_FORMAT_VYUY: | |
4346 | break; | |
4347 | default: | |
4348 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4349 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4350 | return -EINVAL; | |
a1b2278e CK |
4351 | } |
4352 | ||
a1b2278e CK |
4353 | return 0; |
4354 | } | |
4355 | ||
e435d6e5 ML |
4356 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4357 | { | |
4358 | int i; | |
4359 | ||
4360 | for (i = 0; i < crtc->num_scalers; i++) | |
4361 | skl_detach_scaler(crtc, i); | |
4362 | } | |
4363 | ||
4364 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4365 | { |
4366 | struct drm_device *dev = crtc->base.dev; | |
4367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4368 | int pipe = crtc->pipe; | |
a1b2278e CK |
4369 | struct intel_crtc_scaler_state *scaler_state = |
4370 | &crtc->config->scaler_state; | |
4371 | ||
4372 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4373 | ||
6e3c9717 | 4374 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4375 | int id; |
4376 | ||
4377 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4378 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4379 | return; | |
4380 | } | |
4381 | ||
4382 | id = scaler_state->scaler_id; | |
4383 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4384 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4385 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4386 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4387 | ||
4388 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4389 | } |
4390 | } | |
4391 | ||
b074cec8 JB |
4392 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4393 | { | |
4394 | struct drm_device *dev = crtc->base.dev; | |
4395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4396 | int pipe = crtc->pipe; | |
4397 | ||
6e3c9717 | 4398 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4399 | /* Force use of hard-coded filter coefficients |
4400 | * as some pre-programmed values are broken, | |
4401 | * e.g. x201. | |
4402 | */ | |
4403 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4404 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4405 | PF_PIPE_SEL_IVB(pipe)); | |
4406 | else | |
4407 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4408 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4409 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4410 | } |
4411 | } | |
4412 | ||
20bc8673 | 4413 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4414 | { |
cea165c3 VS |
4415 | struct drm_device *dev = crtc->base.dev; |
4416 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4417 | |
6e3c9717 | 4418 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4419 | return; |
4420 | ||
307e4498 ML |
4421 | /* |
4422 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4423 | * This function is called from post_plane_update, which is run after | |
4424 | * a vblank wait. | |
4425 | */ | |
cea165c3 | 4426 | |
d77e4531 | 4427 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4428 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4429 | mutex_lock(&dev_priv->rps.hw_lock); |
4430 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4431 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4432 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4433 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4434 | * mailbox." Moreover, the mailbox may return a bogus state, |
4435 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4436 | */ |
4437 | } else { | |
4438 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4439 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4440 | * is essentially intel_wait_for_vblank. If we don't have this | |
4441 | * and don't wait for vblanks until the end of crtc_enable, then | |
4442 | * the HW state readout code will complain that the expected | |
4443 | * IPS_CTL value is not the one we read. */ | |
4444 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4445 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4446 | } | |
d77e4531 PZ |
4447 | } |
4448 | ||
20bc8673 | 4449 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4450 | { |
4451 | struct drm_device *dev = crtc->base.dev; | |
4452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4453 | ||
6e3c9717 | 4454 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4455 | return; |
4456 | ||
4457 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4458 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4459 | mutex_lock(&dev_priv->rps.hw_lock); |
4460 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4461 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4462 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4463 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4464 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4465 | } else { |
2a114cc1 | 4466 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4467 | POSTING_READ(IPS_CTL); |
4468 | } | |
d77e4531 PZ |
4469 | |
4470 | /* We need to wait for a vblank before we can disable the plane. */ | |
4471 | intel_wait_for_vblank(dev, crtc->pipe); | |
4472 | } | |
4473 | ||
7cac945f | 4474 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4475 | { |
7cac945f | 4476 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4477 | struct drm_device *dev = intel_crtc->base.dev; |
4478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4479 | ||
4480 | mutex_lock(&dev->struct_mutex); | |
4481 | dev_priv->mm.interruptible = false; | |
4482 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4483 | dev_priv->mm.interruptible = true; | |
4484 | mutex_unlock(&dev->struct_mutex); | |
4485 | } | |
4486 | ||
4487 | /* Let userspace switch the overlay on again. In most cases userspace | |
4488 | * has to recompute where to put it anyway. | |
4489 | */ | |
4490 | } | |
4491 | ||
87d4300a ML |
4492 | /** |
4493 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4494 | * @crtc: the CRTC whose primary plane was just enabled | |
4495 | * | |
4496 | * Performs potentially sleeping operations that must be done after the primary | |
4497 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4498 | * called due to an explicit primary plane update, or due to an implicit | |
4499 | * re-enable that is caused when a sprite plane is updated to no longer | |
4500 | * completely hide the primary plane. | |
4501 | */ | |
4502 | static void | |
4503 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4504 | { |
4505 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4506 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4507 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4508 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4509 | |
87d4300a ML |
4510 | /* |
4511 | * FIXME IPS should be fine as long as one plane is | |
4512 | * enabled, but in practice it seems to have problems | |
4513 | * when going from primary only to sprite only and vice | |
4514 | * versa. | |
4515 | */ | |
a5c4d7bc VS |
4516 | hsw_enable_ips(intel_crtc); |
4517 | ||
f99d7069 | 4518 | /* |
87d4300a ML |
4519 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4520 | * So don't enable underrun reporting before at least some planes | |
4521 | * are enabled. | |
4522 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4523 | * but leave the pipe running. | |
f99d7069 | 4524 | */ |
87d4300a ML |
4525 | if (IS_GEN2(dev)) |
4526 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4527 | ||
aca7b684 VS |
4528 | /* Underruns don't always raise interrupts, so check manually. */ |
4529 | intel_check_cpu_fifo_underruns(dev_priv); | |
4530 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4531 | } |
4532 | ||
2622a081 | 4533 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4534 | static void |
4535 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4536 | { |
4537 | struct drm_device *dev = crtc->dev; | |
4538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4539 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4540 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4541 | |
87d4300a ML |
4542 | /* |
4543 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4544 | * So diasble underrun reporting before all the planes get disabled. | |
4545 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4546 | * but leave the pipe running. | |
4547 | */ | |
4548 | if (IS_GEN2(dev)) | |
4549 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4550 | |
2622a081 VS |
4551 | /* |
4552 | * FIXME IPS should be fine as long as one plane is | |
4553 | * enabled, but in practice it seems to have problems | |
4554 | * when going from primary only to sprite only and vice | |
4555 | * versa. | |
4556 | */ | |
4557 | hsw_disable_ips(intel_crtc); | |
4558 | } | |
4559 | ||
4560 | /* FIXME get rid of this and use pre_plane_update */ | |
4561 | static void | |
4562 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4563 | { | |
4564 | struct drm_device *dev = crtc->dev; | |
4565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4566 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4567 | int pipe = intel_crtc->pipe; | |
4568 | ||
4569 | intel_pre_disable_primary(crtc); | |
4570 | ||
87d4300a ML |
4571 | /* |
4572 | * Vblank time updates from the shadow to live plane control register | |
4573 | * are blocked if the memory self-refresh mode is active at that | |
4574 | * moment. So to make sure the plane gets truly disabled, disable | |
4575 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4576 | * will be checked/applied by the HW only at the next frame start | |
4577 | * event which is after the vblank start event, so we need to have a | |
4578 | * wait-for-vblank between disabling the plane and the pipe. | |
4579 | */ | |
262cd2e1 | 4580 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4581 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4582 | dev_priv->wm.vlv.cxsr = false; |
4583 | intel_wait_for_vblank(dev, pipe); | |
4584 | } | |
87d4300a ML |
4585 | } |
4586 | ||
cd202f69 | 4587 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4588 | { |
cd202f69 ML |
4589 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
4590 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
92826fcd ML |
4591 | struct intel_crtc_state *pipe_config = |
4592 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4593 | struct drm_device *dev = crtc->base.dev; |
cd202f69 ML |
4594 | struct drm_plane *primary = crtc->base.primary; |
4595 | struct drm_plane_state *old_pri_state = | |
4596 | drm_atomic_get_existing_plane_state(old_state, primary); | |
ac21b225 | 4597 | |
cd202f69 | 4598 | intel_frontbuffer_flip(dev, pipe_config->fb_bits); |
ac21b225 | 4599 | |
ab1d3a0e | 4600 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4601 | |
caed361d | 4602 | if (pipe_config->update_wm_post && pipe_config->base.active) |
f015c551 VS |
4603 | intel_update_watermarks(&crtc->base); |
4604 | ||
cd202f69 ML |
4605 | if (old_pri_state) { |
4606 | struct intel_plane_state *primary_state = | |
4607 | to_intel_plane_state(primary->state); | |
4608 | struct intel_plane_state *old_primary_state = | |
4609 | to_intel_plane_state(old_pri_state); | |
4610 | ||
31ae71fc ML |
4611 | intel_fbc_post_update(crtc); |
4612 | ||
cd202f69 ML |
4613 | if (primary_state->visible && |
4614 | (needs_modeset(&pipe_config->base) || | |
4615 | !old_primary_state->visible)) | |
4616 | intel_post_enable_primary(&crtc->base); | |
4617 | } | |
ac21b225 ML |
4618 | } |
4619 | ||
5c74cd73 | 4620 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4621 | { |
5c74cd73 | 4622 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4623 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4624 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1d3a0e ML |
4625 | struct intel_crtc_state *pipe_config = |
4626 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4627 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4628 | struct drm_plane *primary = crtc->base.primary; | |
4629 | struct drm_plane_state *old_pri_state = | |
4630 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4631 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4632 | |
5c74cd73 ML |
4633 | if (old_pri_state) { |
4634 | struct intel_plane_state *primary_state = | |
4635 | to_intel_plane_state(primary->state); | |
4636 | struct intel_plane_state *old_primary_state = | |
4637 | to_intel_plane_state(old_pri_state); | |
4638 | ||
31ae71fc ML |
4639 | intel_fbc_pre_update(crtc); |
4640 | ||
5c74cd73 ML |
4641 | if (old_primary_state->visible && |
4642 | (modeset || !primary_state->visible)) | |
4643 | intel_pre_disable_primary(&crtc->base); | |
4644 | } | |
852eb00d | 4645 | |
ab1d3a0e | 4646 | if (pipe_config->disable_cxsr) { |
852eb00d | 4647 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4648 | |
2622a081 VS |
4649 | /* |
4650 | * Vblank time updates from the shadow to live plane control register | |
4651 | * are blocked if the memory self-refresh mode is active at that | |
4652 | * moment. So to make sure the plane gets truly disabled, disable | |
4653 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4654 | * will be checked/applied by the HW only at the next frame start | |
4655 | * event which is after the vblank start event, so we need to have a | |
4656 | * wait-for-vblank between disabling the plane and the pipe. | |
4657 | */ | |
4658 | if (old_crtc_state->base.active) { | |
2dfd178d | 4659 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4660 | dev_priv->wm.vlv.cxsr = false; |
4661 | intel_wait_for_vblank(dev, crtc->pipe); | |
4662 | } | |
852eb00d | 4663 | } |
92826fcd | 4664 | |
ed4a6a7c MR |
4665 | /* |
4666 | * IVB workaround: must disable low power watermarks for at least | |
4667 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4668 | * when scaling is disabled. | |
4669 | * | |
4670 | * WaCxSRDisabledForSpriteScaling:ivb | |
4671 | */ | |
4672 | if (pipe_config->disable_lp_wm) { | |
4673 | ilk_disable_lp_wm(dev); | |
4674 | intel_wait_for_vblank(dev, crtc->pipe); | |
4675 | } | |
4676 | ||
4677 | /* | |
4678 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4679 | * watermark programming here. | |
4680 | */ | |
4681 | if (needs_modeset(&pipe_config->base)) | |
4682 | return; | |
4683 | ||
4684 | /* | |
4685 | * For platforms that support atomic watermarks, program the | |
4686 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4687 | * will be the intermediate values that are safe for both pre- and | |
4688 | * post- vblank; when vblank happens, the 'active' values will be set | |
4689 | * to the final 'target' values and we'll do this again to get the | |
4690 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4691 | * will be the final target values which will get automatically latched | |
4692 | * at vblank time; no further programming will be necessary. | |
4693 | * | |
4694 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4695 | * we'll continue to update watermarks the old way, if flags tell | |
4696 | * us to. | |
4697 | */ | |
4698 | if (dev_priv->display.initial_watermarks != NULL) | |
4699 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4700 | else if (pipe_config->update_wm_pre) |
92826fcd | 4701 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4702 | } |
4703 | ||
d032ffa0 | 4704 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4705 | { |
4706 | struct drm_device *dev = crtc->dev; | |
4707 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4708 | struct drm_plane *p; |
87d4300a ML |
4709 | int pipe = intel_crtc->pipe; |
4710 | ||
7cac945f | 4711 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4712 | |
d032ffa0 ML |
4713 | drm_for_each_plane_mask(p, dev, plane_mask) |
4714 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4715 | |
f99d7069 DV |
4716 | /* |
4717 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4718 | * to compute the mask of flip planes precisely. For the time being | |
4719 | * consider this a flip to a NULL plane. | |
4720 | */ | |
4721 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4722 | } |
4723 | ||
f67a559d JB |
4724 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4725 | { | |
4726 | struct drm_device *dev = crtc->dev; | |
4727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4728 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4729 | struct intel_encoder *encoder; |
f67a559d | 4730 | int pipe = intel_crtc->pipe; |
b95c5321 ML |
4731 | struct intel_crtc_state *pipe_config = |
4732 | to_intel_crtc_state(crtc->state); | |
f67a559d | 4733 | |
53d9f4e9 | 4734 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4735 | return; |
4736 | ||
b2c0593a VS |
4737 | /* |
4738 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4739 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4740 | * | |
4741 | * On ILK we get an occasional spurious CPU pipe underruns | |
4742 | * between eDP port A enable and vdd enable. Also PCH port | |
4743 | * enable seems to result in the occasional CPU pipe underrun. | |
4744 | * | |
4745 | * Spurious PCH underruns also occur during PCH enabling. | |
4746 | */ | |
4747 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
4748 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
4749 | if (intel_crtc->config->has_pch_encoder) |
4750 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4751 | ||
6e3c9717 | 4752 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4753 | intel_prepare_shared_dpll(intel_crtc); |
4754 | ||
6e3c9717 | 4755 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4756 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4757 | |
4758 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4759 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4760 | |
6e3c9717 | 4761 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4762 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4763 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4764 | } |
4765 | ||
4766 | ironlake_set_pipeconf(crtc); | |
4767 | ||
f67a559d | 4768 | intel_crtc->active = true; |
8664281b | 4769 | |
f6736a1a | 4770 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4771 | if (encoder->pre_enable) |
4772 | encoder->pre_enable(encoder); | |
f67a559d | 4773 | |
6e3c9717 | 4774 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4775 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4776 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4777 | * enabling. */ | |
88cefb6c | 4778 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4779 | } else { |
4780 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4781 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4782 | } | |
f67a559d | 4783 | |
b074cec8 | 4784 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4785 | |
9c54c0dd JB |
4786 | /* |
4787 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4788 | * clocks enabled | |
4789 | */ | |
b95c5321 | 4790 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 4791 | |
1d5bf5d9 ID |
4792 | if (dev_priv->display.initial_watermarks != NULL) |
4793 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4794 | intel_enable_pipe(intel_crtc); |
f67a559d | 4795 | |
6e3c9717 | 4796 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4797 | ironlake_pch_enable(crtc); |
c98e9dcf | 4798 | |
f9b61ff6 DV |
4799 | assert_vblank_disabled(crtc); |
4800 | drm_crtc_vblank_on(crtc); | |
4801 | ||
fa5c73b1 DV |
4802 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4803 | encoder->enable(encoder); | |
61b77ddd DV |
4804 | |
4805 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4806 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4807 | |
4808 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4809 | if (intel_crtc->config->has_pch_encoder) | |
4810 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 4811 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 4812 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
4813 | } |
4814 | ||
42db64ef PZ |
4815 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4816 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4817 | { | |
f5adf94e | 4818 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4819 | } |
4820 | ||
4f771f10 PZ |
4821 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4822 | { | |
4823 | struct drm_device *dev = crtc->dev; | |
4824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4825 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4826 | struct intel_encoder *encoder; | |
99d736a2 | 4827 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 4828 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
4829 | struct intel_crtc_state *pipe_config = |
4830 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4831 | |
53d9f4e9 | 4832 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4833 | return; |
4834 | ||
81b088ca VS |
4835 | if (intel_crtc->config->has_pch_encoder) |
4836 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4837 | false); | |
4838 | ||
8106ddbd | 4839 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
4840 | intel_enable_shared_dpll(intel_crtc); |
4841 | ||
6e3c9717 | 4842 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4843 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 4844 | |
4d1de975 JN |
4845 | if (!intel_crtc->config->has_dsi_encoder) |
4846 | intel_set_pipe_timings(intel_crtc); | |
4847 | ||
bc58be60 | 4848 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 4849 | |
4d1de975 JN |
4850 | if (cpu_transcoder != TRANSCODER_EDP && |
4851 | !transcoder_is_dsi(cpu_transcoder)) { | |
4852 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 4853 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
4854 | } |
4855 | ||
6e3c9717 | 4856 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4857 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4858 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4859 | } |
4860 | ||
4d1de975 JN |
4861 | if (!intel_crtc->config->has_dsi_encoder) |
4862 | haswell_set_pipeconf(crtc); | |
4863 | ||
391bf048 | 4864 | haswell_set_pipemisc(crtc); |
229fca97 | 4865 | |
b95c5321 | 4866 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 4867 | |
4f771f10 | 4868 | intel_crtc->active = true; |
8664281b | 4869 | |
6b698516 DV |
4870 | if (intel_crtc->config->has_pch_encoder) |
4871 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4872 | else | |
4873 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4874 | ||
7d4aefd0 | 4875 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4876 | if (encoder->pre_enable) |
4877 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4878 | } |
4f771f10 | 4879 | |
d2d65408 | 4880 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4881 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4882 | |
a65347ba | 4883 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4884 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4885 | |
1c132b44 | 4886 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4887 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4888 | else |
1c132b44 | 4889 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4890 | |
4891 | /* | |
4892 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4893 | * clocks enabled | |
4894 | */ | |
b95c5321 | 4895 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 4896 | |
1f544388 | 4897 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 4898 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4899 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4900 | |
1d5bf5d9 ID |
4901 | if (dev_priv->display.initial_watermarks != NULL) |
4902 | dev_priv->display.initial_watermarks(pipe_config); | |
4903 | else | |
4904 | intel_update_watermarks(crtc); | |
4d1de975 JN |
4905 | |
4906 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
4907 | if (!intel_crtc->config->has_dsi_encoder) | |
4908 | intel_enable_pipe(intel_crtc); | |
42db64ef | 4909 | |
6e3c9717 | 4910 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4911 | lpt_pch_enable(crtc); |
4f771f10 | 4912 | |
a65347ba | 4913 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4914 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4915 | ||
f9b61ff6 DV |
4916 | assert_vblank_disabled(crtc); |
4917 | drm_crtc_vblank_on(crtc); | |
4918 | ||
8807e55b | 4919 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4920 | encoder->enable(encoder); |
8807e55b JN |
4921 | intel_opregion_notify_encoder(encoder, true); |
4922 | } | |
4f771f10 | 4923 | |
6b698516 DV |
4924 | if (intel_crtc->config->has_pch_encoder) { |
4925 | intel_wait_for_vblank(dev, pipe); | |
4926 | intel_wait_for_vblank(dev, pipe); | |
4927 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
4928 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4929 | true); | |
6b698516 | 4930 | } |
d2d65408 | 4931 | |
e4916946 PZ |
4932 | /* If we change the relative order between pipe/planes enabling, we need |
4933 | * to change the workaround. */ | |
99d736a2 ML |
4934 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4935 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4936 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4937 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4938 | } | |
4f771f10 PZ |
4939 | } |
4940 | ||
bfd16b2a | 4941 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4942 | { |
4943 | struct drm_device *dev = crtc->base.dev; | |
4944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4945 | int pipe = crtc->pipe; | |
4946 | ||
4947 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4948 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 4949 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4950 | I915_WRITE(PF_CTL(pipe), 0); |
4951 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4952 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4953 | } | |
4954 | } | |
4955 | ||
6be4a607 JB |
4956 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4957 | { | |
4958 | struct drm_device *dev = crtc->dev; | |
4959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4960 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4961 | struct intel_encoder *encoder; |
6be4a607 | 4962 | int pipe = intel_crtc->pipe; |
b52eb4dc | 4963 | |
b2c0593a VS |
4964 | /* |
4965 | * Sometimes spurious CPU pipe underruns happen when the | |
4966 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
4967 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
4968 | */ | |
4969 | if (intel_crtc->config->has_pch_encoder) { | |
4970 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 4971 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 4972 | } |
37ca8d4c | 4973 | |
ea9d758d DV |
4974 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4975 | encoder->disable(encoder); | |
4976 | ||
f9b61ff6 DV |
4977 | drm_crtc_vblank_off(crtc); |
4978 | assert_vblank_disabled(crtc); | |
4979 | ||
575f7ab7 | 4980 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4981 | |
bfd16b2a | 4982 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 4983 | |
b2c0593a | 4984 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
4985 | ironlake_fdi_disable(crtc); |
4986 | ||
bf49ec8c DV |
4987 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4988 | if (encoder->post_disable) | |
4989 | encoder->post_disable(encoder); | |
2c07245f | 4990 | |
6e3c9717 | 4991 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4992 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4993 | |
d925c59a | 4994 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
4995 | i915_reg_t reg; |
4996 | u32 temp; | |
4997 | ||
d925c59a DV |
4998 | /* disable TRANS_DP_CTL */ |
4999 | reg = TRANS_DP_CTL(pipe); | |
5000 | temp = I915_READ(reg); | |
5001 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5002 | TRANS_DP_PORT_SEL_MASK); | |
5003 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5004 | I915_WRITE(reg, temp); | |
5005 | ||
5006 | /* disable DPLL_SEL */ | |
5007 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5008 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5009 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5010 | } |
e3421a18 | 5011 | |
d925c59a DV |
5012 | ironlake_fdi_pll_disable(intel_crtc); |
5013 | } | |
81b088ca | 5014 | |
b2c0593a | 5015 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5016 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5017 | } |
1b3c7a47 | 5018 | |
4f771f10 | 5019 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5020 | { |
4f771f10 PZ |
5021 | struct drm_device *dev = crtc->dev; |
5022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5023 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5024 | struct intel_encoder *encoder; |
6e3c9717 | 5025 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5026 | |
d2d65408 VS |
5027 | if (intel_crtc->config->has_pch_encoder) |
5028 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5029 | false); | |
5030 | ||
8807e55b JN |
5031 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5032 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5033 | encoder->disable(encoder); |
8807e55b | 5034 | } |
4f771f10 | 5035 | |
f9b61ff6 DV |
5036 | drm_crtc_vblank_off(crtc); |
5037 | assert_vblank_disabled(crtc); | |
5038 | ||
4d1de975 JN |
5039 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
5040 | if (!intel_crtc->config->has_dsi_encoder) | |
5041 | intel_disable_pipe(intel_crtc); | |
4f771f10 | 5042 | |
6e3c9717 | 5043 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5044 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5045 | ||
a65347ba | 5046 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5047 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5048 | |
1c132b44 | 5049 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5050 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5051 | else |
bfd16b2a | 5052 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5053 | |
a65347ba | 5054 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5055 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5056 | |
97b040aa ID |
5057 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5058 | if (encoder->post_disable) | |
5059 | encoder->post_disable(encoder); | |
81b088ca | 5060 | |
92966a37 VS |
5061 | if (intel_crtc->config->has_pch_encoder) { |
5062 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5063 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5064 | intel_ddi_fdi_disable(crtc); |
5065 | ||
81b088ca VS |
5066 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5067 | true); | |
92966a37 | 5068 | } |
4f771f10 PZ |
5069 | } |
5070 | ||
2dd24552 JB |
5071 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5072 | { | |
5073 | struct drm_device *dev = crtc->base.dev; | |
5074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5075 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5076 | |
681a8504 | 5077 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5078 | return; |
5079 | ||
2dd24552 | 5080 | /* |
c0b03411 DV |
5081 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5082 | * according to register description and PRM. | |
2dd24552 | 5083 | */ |
c0b03411 DV |
5084 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5085 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5086 | |
b074cec8 JB |
5087 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5088 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5089 | |
5090 | /* Border color in case we don't scale up to the full screen. Black by | |
5091 | * default, change to something else for debugging. */ | |
5092 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5093 | } |
5094 | ||
d05410f9 DA |
5095 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5096 | { | |
5097 | switch (port) { | |
5098 | case PORT_A: | |
6331a704 | 5099 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5100 | case PORT_B: |
6331a704 | 5101 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5102 | case PORT_C: |
6331a704 | 5103 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5104 | case PORT_D: |
6331a704 | 5105 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5106 | case PORT_E: |
6331a704 | 5107 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5108 | default: |
b9fec167 | 5109 | MISSING_CASE(port); |
d05410f9 DA |
5110 | return POWER_DOMAIN_PORT_OTHER; |
5111 | } | |
5112 | } | |
5113 | ||
25f78f58 VS |
5114 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5115 | { | |
5116 | switch (port) { | |
5117 | case PORT_A: | |
5118 | return POWER_DOMAIN_AUX_A; | |
5119 | case PORT_B: | |
5120 | return POWER_DOMAIN_AUX_B; | |
5121 | case PORT_C: | |
5122 | return POWER_DOMAIN_AUX_C; | |
5123 | case PORT_D: | |
5124 | return POWER_DOMAIN_AUX_D; | |
5125 | case PORT_E: | |
5126 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5127 | return POWER_DOMAIN_AUX_D; | |
5128 | default: | |
b9fec167 | 5129 | MISSING_CASE(port); |
25f78f58 VS |
5130 | return POWER_DOMAIN_AUX_A; |
5131 | } | |
5132 | } | |
5133 | ||
319be8ae ID |
5134 | enum intel_display_power_domain |
5135 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5136 | { | |
5137 | struct drm_device *dev = intel_encoder->base.dev; | |
5138 | struct intel_digital_port *intel_dig_port; | |
5139 | ||
5140 | switch (intel_encoder->type) { | |
5141 | case INTEL_OUTPUT_UNKNOWN: | |
5142 | /* Only DDI platforms should ever use this output type */ | |
5143 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5144 | case INTEL_OUTPUT_DISPLAYPORT: | |
5145 | case INTEL_OUTPUT_HDMI: | |
5146 | case INTEL_OUTPUT_EDP: | |
5147 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5148 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5149 | case INTEL_OUTPUT_DP_MST: |
5150 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5151 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5152 | case INTEL_OUTPUT_ANALOG: |
5153 | return POWER_DOMAIN_PORT_CRT; | |
5154 | case INTEL_OUTPUT_DSI: | |
5155 | return POWER_DOMAIN_PORT_DSI; | |
5156 | default: | |
5157 | return POWER_DOMAIN_PORT_OTHER; | |
5158 | } | |
5159 | } | |
5160 | ||
25f78f58 VS |
5161 | enum intel_display_power_domain |
5162 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5163 | { | |
5164 | struct drm_device *dev = intel_encoder->base.dev; | |
5165 | struct intel_digital_port *intel_dig_port; | |
5166 | ||
5167 | switch (intel_encoder->type) { | |
5168 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5169 | case INTEL_OUTPUT_HDMI: |
5170 | /* | |
5171 | * Only DDI platforms should ever use these output types. | |
5172 | * We can get here after the HDMI detect code has already set | |
5173 | * the type of the shared encoder. Since we can't be sure | |
5174 | * what's the status of the given connectors, play safe and | |
5175 | * run the DP detection too. | |
5176 | */ | |
25f78f58 VS |
5177 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5178 | case INTEL_OUTPUT_DISPLAYPORT: | |
5179 | case INTEL_OUTPUT_EDP: | |
5180 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5181 | return port_to_aux_power_domain(intel_dig_port->port); | |
5182 | case INTEL_OUTPUT_DP_MST: | |
5183 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5184 | return port_to_aux_power_domain(intel_dig_port->port); | |
5185 | default: | |
b9fec167 | 5186 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5187 | return POWER_DOMAIN_AUX_A; |
5188 | } | |
5189 | } | |
5190 | ||
74bff5f9 ML |
5191 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5192 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5193 | { |
319be8ae | 5194 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5195 | struct drm_encoder *encoder; |
319be8ae ID |
5196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5197 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5198 | unsigned long mask; |
74bff5f9 | 5199 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5200 | |
74bff5f9 | 5201 | if (!crtc_state->base.active) |
292b990e ML |
5202 | return 0; |
5203 | ||
77d22dca ID |
5204 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5205 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5206 | if (crtc_state->pch_pfit.enabled || |
5207 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5208 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5209 | ||
74bff5f9 ML |
5210 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5211 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5212 | ||
319be8ae | 5213 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5214 | } |
319be8ae | 5215 | |
15e7ec29 ML |
5216 | if (crtc_state->shared_dpll) |
5217 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5218 | ||
77d22dca ID |
5219 | return mask; |
5220 | } | |
5221 | ||
74bff5f9 ML |
5222 | static unsigned long |
5223 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5224 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5225 | { |
292b990e ML |
5226 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5227 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5228 | enum intel_display_power_domain domain; | |
5229 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5230 | |
292b990e | 5231 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5232 | intel_crtc->enabled_power_domains = new_domains = |
5233 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5234 | |
292b990e ML |
5235 | domains = new_domains & ~old_domains; |
5236 | ||
5237 | for_each_power_domain(domain, domains) | |
5238 | intel_display_power_get(dev_priv, domain); | |
5239 | ||
5240 | return old_domains & ~new_domains; | |
5241 | } | |
5242 | ||
5243 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5244 | unsigned long domains) | |
5245 | { | |
5246 | enum intel_display_power_domain domain; | |
5247 | ||
5248 | for_each_power_domain(domain, domains) | |
5249 | intel_display_power_put(dev_priv, domain); | |
5250 | } | |
77d22dca | 5251 | |
adafdc6f MK |
5252 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5253 | { | |
5254 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5255 | ||
5256 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5257 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5258 | return max_cdclk_freq; | |
5259 | else if (IS_CHERRYVIEW(dev_priv)) | |
5260 | return max_cdclk_freq*95/100; | |
5261 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5262 | return 2*max_cdclk_freq*90/100; | |
5263 | else | |
5264 | return max_cdclk_freq*90/100; | |
5265 | } | |
5266 | ||
560a7ae4 DL |
5267 | static void intel_update_max_cdclk(struct drm_device *dev) |
5268 | { | |
5269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5270 | ||
ef11bdb3 | 5271 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5272 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5273 | ||
5274 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5275 | dev_priv->max_cdclk_freq = 675000; | |
5276 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5277 | dev_priv->max_cdclk_freq = 540000; | |
5278 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5279 | dev_priv->max_cdclk_freq = 450000; | |
5280 | else | |
5281 | dev_priv->max_cdclk_freq = 337500; | |
281c114f MR |
5282 | } else if (IS_BROXTON(dev)) { |
5283 | dev_priv->max_cdclk_freq = 624000; | |
560a7ae4 DL |
5284 | } else if (IS_BROADWELL(dev)) { |
5285 | /* | |
5286 | * FIXME with extra cooling we can allow | |
5287 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5288 | * How can we know if extra cooling is | |
5289 | * available? PCI ID, VTB, something else? | |
5290 | */ | |
5291 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5292 | dev_priv->max_cdclk_freq = 450000; | |
5293 | else if (IS_BDW_ULX(dev)) | |
5294 | dev_priv->max_cdclk_freq = 450000; | |
5295 | else if (IS_BDW_ULT(dev)) | |
5296 | dev_priv->max_cdclk_freq = 540000; | |
5297 | else | |
5298 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5299 | } else if (IS_CHERRYVIEW(dev)) { |
5300 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5301 | } else if (IS_VALLEYVIEW(dev)) { |
5302 | dev_priv->max_cdclk_freq = 400000; | |
5303 | } else { | |
5304 | /* otherwise assume cdclk is fixed */ | |
5305 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5306 | } | |
5307 | ||
adafdc6f MK |
5308 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5309 | ||
560a7ae4 DL |
5310 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5311 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5312 | |
5313 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5314 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5315 | } |
5316 | ||
5317 | static void intel_update_cdclk(struct drm_device *dev) | |
5318 | { | |
5319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5320 | ||
5321 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5322 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5323 | dev_priv->cdclk_freq); | |
5324 | ||
5325 | /* | |
b5d99ff9 VS |
5326 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5327 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5328 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5329 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5330 | */ |
b5d99ff9 | 5331 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5332 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5333 | |
5334 | if (dev_priv->max_cdclk_freq == 0) | |
5335 | intel_update_max_cdclk(dev); | |
5336 | } | |
5337 | ||
c6c4696f | 5338 | static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency) |
f8437dd1 | 5339 | { |
f8437dd1 VK |
5340 | uint32_t divider; |
5341 | uint32_t ratio; | |
5342 | uint32_t current_freq; | |
5343 | int ret; | |
5344 | ||
5345 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5346 | switch (frequency) { | |
5347 | case 144000: | |
5348 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5349 | ratio = BXT_DE_PLL_RATIO(60); | |
5350 | break; | |
5351 | case 288000: | |
5352 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5353 | ratio = BXT_DE_PLL_RATIO(60); | |
5354 | break; | |
5355 | case 384000: | |
5356 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5357 | ratio = BXT_DE_PLL_RATIO(60); | |
5358 | break; | |
5359 | case 576000: | |
5360 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5361 | ratio = BXT_DE_PLL_RATIO(60); | |
5362 | break; | |
5363 | case 624000: | |
5364 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5365 | ratio = BXT_DE_PLL_RATIO(65); | |
5366 | break; | |
5367 | case 19200: | |
5368 | /* | |
5369 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5370 | * to suppress GCC warning. | |
5371 | */ | |
5372 | ratio = 0; | |
5373 | divider = 0; | |
5374 | break; | |
5375 | default: | |
5376 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5377 | ||
5378 | return; | |
5379 | } | |
5380 | ||
5381 | mutex_lock(&dev_priv->rps.hw_lock); | |
5382 | /* Inform power controller of upcoming frequency change */ | |
5383 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5384 | 0x80000000); | |
5385 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5386 | ||
5387 | if (ret) { | |
5388 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5389 | ret, frequency); | |
5390 | return; | |
5391 | } | |
5392 | ||
5393 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5394 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5395 | current_freq = current_freq * 500 + 1000; | |
5396 | ||
5397 | /* | |
5398 | * DE PLL has to be disabled when | |
5399 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5400 | * - before setting to 624MHz (PLL needs toggling) | |
5401 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5402 | */ | |
5403 | if (frequency == 19200 || frequency == 624000 || | |
5404 | current_freq == 624000) { | |
5405 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5406 | /* Timeout 200us */ | |
5407 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5408 | 1)) | |
5409 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5410 | } | |
5411 | ||
5412 | if (frequency != 19200) { | |
5413 | uint32_t val; | |
5414 | ||
5415 | val = I915_READ(BXT_DE_PLL_CTL); | |
5416 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5417 | val |= ratio; | |
5418 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5419 | ||
5420 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5421 | /* Timeout 200us */ | |
5422 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5423 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5424 | ||
5425 | val = I915_READ(CDCLK_CTL); | |
5426 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5427 | val |= divider; | |
5428 | /* | |
5429 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5430 | * enable otherwise. | |
5431 | */ | |
5432 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5433 | if (frequency >= 500000) | |
5434 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5435 | ||
5436 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5437 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5438 | val |= (frequency - 1000) / 500; | |
5439 | I915_WRITE(CDCLK_CTL, val); | |
5440 | } | |
5441 | ||
5442 | mutex_lock(&dev_priv->rps.hw_lock); | |
5443 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5444 | DIV_ROUND_UP(frequency, 25000)); | |
5445 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5446 | ||
5447 | if (ret) { | |
5448 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5449 | ret, frequency); | |
5450 | return; | |
5451 | } | |
5452 | ||
c6c4696f | 5453 | intel_update_cdclk(dev_priv->dev); |
f8437dd1 VK |
5454 | } |
5455 | ||
c2e001ef ID |
5456 | static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv) |
5457 | { | |
5458 | if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE)) | |
5459 | return false; | |
5460 | ||
5461 | /* TODO: Check for a valid CDCLK rate */ | |
5462 | ||
5463 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) { | |
5464 | DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n"); | |
5465 | ||
5466 | return false; | |
5467 | } | |
5468 | ||
5469 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) { | |
5470 | DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n"); | |
5471 | ||
5472 | return false; | |
5473 | } | |
5474 | ||
5475 | return true; | |
5476 | } | |
5477 | ||
adc7f04b ID |
5478 | bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv) |
5479 | { | |
5480 | return broxton_cdclk_is_enabled(dev_priv); | |
5481 | } | |
5482 | ||
c6c4696f | 5483 | void broxton_init_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5484 | { |
f8437dd1 | 5485 | /* check if cd clock is enabled */ |
c2e001ef ID |
5486 | if (broxton_cdclk_is_enabled(dev_priv)) { |
5487 | DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n"); | |
f8437dd1 VK |
5488 | return; |
5489 | } | |
5490 | ||
c2e001ef ID |
5491 | DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n"); |
5492 | ||
f8437dd1 VK |
5493 | /* |
5494 | * FIXME: | |
5495 | * - The initial CDCLK needs to be read from VBT. | |
5496 | * Need to make this change after VBT has changes for BXT. | |
5497 | * - check if setting the max (or any) cdclk freq is really necessary | |
5498 | * here, it belongs to modeset time | |
5499 | */ | |
c6c4696f | 5500 | broxton_set_cdclk(dev_priv, 624000); |
f8437dd1 VK |
5501 | |
5502 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5503 | POSTING_READ(DBUF_CTL); |
5504 | ||
f8437dd1 VK |
5505 | udelay(10); |
5506 | ||
5507 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5508 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5509 | } | |
5510 | ||
c6c4696f | 5511 | void broxton_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5512 | { |
f8437dd1 | 5513 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); |
22e02c0b VS |
5514 | POSTING_READ(DBUF_CTL); |
5515 | ||
f8437dd1 VK |
5516 | udelay(10); |
5517 | ||
5518 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5519 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5520 | ||
5521 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
c6c4696f | 5522 | broxton_set_cdclk(dev_priv, 19200); |
f8437dd1 VK |
5523 | } |
5524 | ||
5d96d8af DL |
5525 | static const struct skl_cdclk_entry { |
5526 | unsigned int freq; | |
5527 | unsigned int vco; | |
5528 | } skl_cdclk_frequencies[] = { | |
5529 | { .freq = 308570, .vco = 8640 }, | |
5530 | { .freq = 337500, .vco = 8100 }, | |
5531 | { .freq = 432000, .vco = 8640 }, | |
5532 | { .freq = 450000, .vco = 8100 }, | |
5533 | { .freq = 540000, .vco = 8100 }, | |
5534 | { .freq = 617140, .vco = 8640 }, | |
5535 | { .freq = 675000, .vco = 8100 }, | |
5536 | }; | |
5537 | ||
5538 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5539 | { | |
5540 | return (freq - 1000) / 500; | |
5541 | } | |
5542 | ||
5543 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5544 | { | |
5545 | unsigned int i; | |
5546 | ||
5547 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5548 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5549 | ||
5550 | if (e->freq == freq) | |
5551 | return e->vco; | |
5552 | } | |
5553 | ||
5554 | return 8100; | |
5555 | } | |
5556 | ||
5557 | static void | |
5558 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5559 | { | |
5560 | unsigned int min_freq; | |
5561 | u32 val; | |
5562 | ||
5563 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5564 | val = I915_READ(CDCLK_CTL); | |
5565 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5566 | val |= CDCLK_FREQ_337_308; | |
5567 | ||
5568 | if (required_vco == 8640) | |
5569 | min_freq = 308570; | |
5570 | else | |
5571 | min_freq = 337500; | |
5572 | ||
5573 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5574 | ||
5575 | I915_WRITE(CDCLK_CTL, val); | |
5576 | POSTING_READ(CDCLK_CTL); | |
5577 | ||
5578 | /* | |
5579 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5580 | * taking into account the VCO required to operate the eDP panel at the | |
5581 | * desired frequency. The usual DP link rates operate with a VCO of | |
5582 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5583 | * The modeset code is responsible for the selection of the exact link | |
5584 | * rate later on, with the constraint of choosing a frequency that | |
5585 | * works with required_vco. | |
5586 | */ | |
5587 | val = I915_READ(DPLL_CTRL1); | |
5588 | ||
5589 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5590 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5591 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5592 | if (required_vco == 8640) | |
5593 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5594 | SKL_DPLL0); | |
5595 | else | |
5596 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5597 | SKL_DPLL0); | |
5598 | ||
5599 | I915_WRITE(DPLL_CTRL1, val); | |
5600 | POSTING_READ(DPLL_CTRL1); | |
5601 | ||
5602 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5603 | ||
5604 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5605 | DRM_ERROR("DPLL0 not locked\n"); | |
5606 | } | |
5607 | ||
5608 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5609 | { | |
5610 | int ret; | |
5611 | u32 val; | |
5612 | ||
5613 | /* inform PCU we want to change CDCLK */ | |
5614 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5615 | mutex_lock(&dev_priv->rps.hw_lock); | |
5616 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5617 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5618 | ||
5619 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5620 | } | |
5621 | ||
5622 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5623 | { | |
5624 | unsigned int i; | |
5625 | ||
5626 | for (i = 0; i < 15; i++) { | |
5627 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5628 | return true; | |
5629 | udelay(10); | |
5630 | } | |
5631 | ||
5632 | return false; | |
5633 | } | |
5634 | ||
5635 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5636 | { | |
560a7ae4 | 5637 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5638 | u32 freq_select, pcu_ack; |
5639 | ||
5640 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5641 | ||
5642 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5643 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5644 | return; | |
5645 | } | |
5646 | ||
5647 | /* set CDCLK_CTL */ | |
5648 | switch(freq) { | |
5649 | case 450000: | |
5650 | case 432000: | |
5651 | freq_select = CDCLK_FREQ_450_432; | |
5652 | pcu_ack = 1; | |
5653 | break; | |
5654 | case 540000: | |
5655 | freq_select = CDCLK_FREQ_540; | |
5656 | pcu_ack = 2; | |
5657 | break; | |
5658 | case 308570: | |
5659 | case 337500: | |
5660 | default: | |
5661 | freq_select = CDCLK_FREQ_337_308; | |
5662 | pcu_ack = 0; | |
5663 | break; | |
5664 | case 617140: | |
5665 | case 675000: | |
5666 | freq_select = CDCLK_FREQ_675_617; | |
5667 | pcu_ack = 3; | |
5668 | break; | |
5669 | } | |
5670 | ||
5671 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5672 | POSTING_READ(CDCLK_CTL); | |
5673 | ||
5674 | /* inform PCU of the change */ | |
5675 | mutex_lock(&dev_priv->rps.hw_lock); | |
5676 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5677 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5678 | |
5679 | intel_update_cdclk(dev); | |
5d96d8af DL |
5680 | } |
5681 | ||
5682 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5683 | { | |
5684 | /* disable DBUF power */ | |
5685 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5686 | POSTING_READ(DBUF_CTL); | |
5687 | ||
5688 | udelay(10); | |
5689 | ||
5690 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5691 | DRM_ERROR("DBuf power disable timeout\n"); | |
5692 | ||
ab96c1ee ID |
5693 | /* disable DPLL0 */ |
5694 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5695 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5696 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5697 | } |
5698 | ||
5699 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5700 | { | |
5d96d8af DL |
5701 | unsigned int required_vco; |
5702 | ||
39d9b85a GW |
5703 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5704 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5705 | /* enable DPLL0 */ | |
5706 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5707 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5708 | } |
5709 | ||
5d96d8af DL |
5710 | /* set CDCLK to the frequency the BIOS chose */ |
5711 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5712 | ||
5713 | /* enable DBUF power */ | |
5714 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5715 | POSTING_READ(DBUF_CTL); | |
5716 | ||
5717 | udelay(10); | |
5718 | ||
5719 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5720 | DRM_ERROR("DBuf power enable timeout\n"); | |
5721 | } | |
5722 | ||
c73666f3 SK |
5723 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5724 | { | |
5725 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5726 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5727 | int freq = dev_priv->skl_boot_cdclk; | |
5728 | ||
f1b391a5 SK |
5729 | /* |
5730 | * check if the pre-os intialized the display | |
5731 | * There is SWF18 scratchpad register defined which is set by the | |
5732 | * pre-os which can be used by the OS drivers to check the status | |
5733 | */ | |
5734 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5735 | goto sanitize; | |
5736 | ||
c73666f3 SK |
5737 | /* Is PLL enabled and locked ? */ |
5738 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5739 | goto sanitize; | |
5740 | ||
5741 | /* DPLL okay; verify the cdclock | |
5742 | * | |
5743 | * Noticed in some instances that the freq selection is correct but | |
5744 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5745 | * enable display. Verify the same as well. | |
5746 | */ | |
5747 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5748 | /* All well; nothing to sanitize */ | |
5749 | return false; | |
5750 | sanitize: | |
5751 | /* | |
5752 | * As of now initialize with max cdclk till | |
5753 | * we get dynamic cdclk support | |
5754 | * */ | |
5755 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5756 | skl_init_cdclk(dev_priv); | |
5757 | ||
5758 | /* we did have to sanitize */ | |
5759 | return true; | |
5760 | } | |
5761 | ||
30a970c6 JB |
5762 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5763 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5764 | { | |
5765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5766 | u32 val, cmd; | |
5767 | ||
164dfd28 VK |
5768 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5769 | != dev_priv->cdclk_freq); | |
d60c4473 | 5770 | |
dfcab17e | 5771 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5772 | cmd = 2; |
dfcab17e | 5773 | else if (cdclk == 266667) |
30a970c6 JB |
5774 | cmd = 1; |
5775 | else | |
5776 | cmd = 0; | |
5777 | ||
5778 | mutex_lock(&dev_priv->rps.hw_lock); | |
5779 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5780 | val &= ~DSPFREQGUAR_MASK; | |
5781 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5782 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5783 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5784 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5785 | 50)) { | |
5786 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5787 | } | |
5788 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5789 | ||
54433e91 VS |
5790 | mutex_lock(&dev_priv->sb_lock); |
5791 | ||
dfcab17e | 5792 | if (cdclk == 400000) { |
6bcda4f0 | 5793 | u32 divider; |
30a970c6 | 5794 | |
6bcda4f0 | 5795 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5796 | |
30a970c6 JB |
5797 | /* adjust cdclk divider */ |
5798 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5799 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5800 | val |= divider; |
5801 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5802 | |
5803 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5804 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5805 | 50)) |
5806 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5807 | } |
5808 | ||
30a970c6 JB |
5809 | /* adjust self-refresh exit latency value */ |
5810 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5811 | val &= ~0x7f; | |
5812 | ||
5813 | /* | |
5814 | * For high bandwidth configs, we set a higher latency in the bunit | |
5815 | * so that the core display fetch happens in time to avoid underruns. | |
5816 | */ | |
dfcab17e | 5817 | if (cdclk == 400000) |
30a970c6 JB |
5818 | val |= 4500 / 250; /* 4.5 usec */ |
5819 | else | |
5820 | val |= 3000 / 250; /* 3.0 usec */ | |
5821 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5822 | |
a580516d | 5823 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5824 | |
b6283055 | 5825 | intel_update_cdclk(dev); |
30a970c6 JB |
5826 | } |
5827 | ||
383c5a6a VS |
5828 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5829 | { | |
5830 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5831 | u32 val, cmd; | |
5832 | ||
164dfd28 VK |
5833 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5834 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5835 | |
5836 | switch (cdclk) { | |
383c5a6a VS |
5837 | case 333333: |
5838 | case 320000: | |
383c5a6a | 5839 | case 266667: |
383c5a6a | 5840 | case 200000: |
383c5a6a VS |
5841 | break; |
5842 | default: | |
5f77eeb0 | 5843 | MISSING_CASE(cdclk); |
383c5a6a VS |
5844 | return; |
5845 | } | |
5846 | ||
9d0d3fda VS |
5847 | /* |
5848 | * Specs are full of misinformation, but testing on actual | |
5849 | * hardware has shown that we just need to write the desired | |
5850 | * CCK divider into the Punit register. | |
5851 | */ | |
5852 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5853 | ||
383c5a6a VS |
5854 | mutex_lock(&dev_priv->rps.hw_lock); |
5855 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5856 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5857 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5858 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5859 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5860 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5861 | 50)) { | |
5862 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5863 | } | |
5864 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5865 | ||
b6283055 | 5866 | intel_update_cdclk(dev); |
383c5a6a VS |
5867 | } |
5868 | ||
30a970c6 JB |
5869 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5870 | int max_pixclk) | |
5871 | { | |
6bcda4f0 | 5872 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5873 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5874 | |
30a970c6 JB |
5875 | /* |
5876 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5877 | * 200MHz | |
5878 | * 267MHz | |
29dc7ef3 | 5879 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5880 | * 400MHz (VLV only) |
5881 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5882 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5883 | * |
5884 | * We seem to get an unstable or solid color picture at 200MHz. | |
5885 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5886 | * are off. | |
30a970c6 | 5887 | */ |
6cca3195 VS |
5888 | if (!IS_CHERRYVIEW(dev_priv) && |
5889 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5890 | return 400000; |
6cca3195 | 5891 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5892 | return freq_320; |
e37c67a1 | 5893 | else if (max_pixclk > 0) |
dfcab17e | 5894 | return 266667; |
e37c67a1 VS |
5895 | else |
5896 | return 200000; | |
30a970c6 JB |
5897 | } |
5898 | ||
c44deb6c | 5899 | static int broxton_calc_cdclk(int max_pixclk) |
f8437dd1 VK |
5900 | { |
5901 | /* | |
5902 | * FIXME: | |
5903 | * - remove the guardband, it's not needed on BXT | |
5904 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5905 | */ | |
5906 | if (max_pixclk > 576000*9/10) | |
5907 | return 624000; | |
5908 | else if (max_pixclk > 384000*9/10) | |
5909 | return 576000; | |
5910 | else if (max_pixclk > 288000*9/10) | |
5911 | return 384000; | |
5912 | else if (max_pixclk > 144000*9/10) | |
5913 | return 288000; | |
5914 | else | |
5915 | return 144000; | |
5916 | } | |
5917 | ||
e8788cbc | 5918 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
5919 | static int intel_mode_max_pixclk(struct drm_device *dev, |
5920 | struct drm_atomic_state *state) | |
30a970c6 | 5921 | { |
565602d7 ML |
5922 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
5923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5924 | struct drm_crtc *crtc; | |
5925 | struct drm_crtc_state *crtc_state; | |
5926 | unsigned max_pixclk = 0, i; | |
5927 | enum pipe pipe; | |
30a970c6 | 5928 | |
565602d7 ML |
5929 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
5930 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 5931 | |
565602d7 ML |
5932 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5933 | int pixclk = 0; | |
5934 | ||
5935 | if (crtc_state->enable) | |
5936 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 5937 | |
565602d7 | 5938 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
5939 | } |
5940 | ||
565602d7 ML |
5941 | for_each_pipe(dev_priv, pipe) |
5942 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
5943 | ||
30a970c6 JB |
5944 | return max_pixclk; |
5945 | } | |
5946 | ||
27c329ed | 5947 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 5948 | { |
27c329ed ML |
5949 | struct drm_device *dev = state->dev; |
5950 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5951 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
5952 | struct intel_atomic_state *intel_state = |
5953 | to_intel_atomic_state(state); | |
30a970c6 | 5954 | |
1a617b77 | 5955 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 5956 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 5957 | |
1a617b77 ML |
5958 | if (!intel_state->active_crtcs) |
5959 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
5960 | ||
27c329ed ML |
5961 | return 0; |
5962 | } | |
304603f4 | 5963 | |
27c329ed ML |
5964 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
5965 | { | |
5966 | struct drm_device *dev = state->dev; | |
27c329ed | 5967 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
5968 | struct intel_atomic_state *intel_state = |
5969 | to_intel_atomic_state(state); | |
85a96e7a | 5970 | |
1a617b77 | 5971 | intel_state->cdclk = intel_state->dev_cdclk = |
c44deb6c | 5972 | broxton_calc_cdclk(max_pixclk); |
85a96e7a | 5973 | |
1a617b77 | 5974 | if (!intel_state->active_crtcs) |
c44deb6c | 5975 | intel_state->dev_cdclk = broxton_calc_cdclk(0); |
1a617b77 | 5976 | |
27c329ed | 5977 | return 0; |
30a970c6 JB |
5978 | } |
5979 | ||
1e69cd74 VS |
5980 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5981 | { | |
5982 | unsigned int credits, default_credits; | |
5983 | ||
5984 | if (IS_CHERRYVIEW(dev_priv)) | |
5985 | default_credits = PFI_CREDIT(12); | |
5986 | else | |
5987 | default_credits = PFI_CREDIT(8); | |
5988 | ||
bfa7df01 | 5989 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
5990 | /* CHV suggested value is 31 or 63 */ |
5991 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 5992 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
5993 | else |
5994 | credits = PFI_CREDIT(15); | |
5995 | } else { | |
5996 | credits = default_credits; | |
5997 | } | |
5998 | ||
5999 | /* | |
6000 | * WA - write default credits before re-programming | |
6001 | * FIXME: should we also set the resend bit here? | |
6002 | */ | |
6003 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6004 | default_credits); | |
6005 | ||
6006 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6007 | credits | PFI_CREDIT_RESEND); | |
6008 | ||
6009 | /* | |
6010 | * FIXME is this guaranteed to clear | |
6011 | * immediately or should we poll for it? | |
6012 | */ | |
6013 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6014 | } | |
6015 | ||
27c329ed | 6016 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6017 | { |
a821fc46 | 6018 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6019 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6020 | struct intel_atomic_state *old_intel_state = |
6021 | to_intel_atomic_state(old_state); | |
6022 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6023 | |
27c329ed ML |
6024 | /* |
6025 | * FIXME: We can end up here with all power domains off, yet | |
6026 | * with a CDCLK frequency other than the minimum. To account | |
6027 | * for this take the PIPE-A power domain, which covers the HW | |
6028 | * blocks needed for the following programming. This can be | |
6029 | * removed once it's guaranteed that we get here either with | |
6030 | * the minimum CDCLK set, or the required power domains | |
6031 | * enabled. | |
6032 | */ | |
6033 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6034 | |
27c329ed ML |
6035 | if (IS_CHERRYVIEW(dev)) |
6036 | cherryview_set_cdclk(dev, req_cdclk); | |
6037 | else | |
6038 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6039 | |
27c329ed | 6040 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6041 | |
27c329ed | 6042 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6043 | } |
6044 | ||
89b667f8 JB |
6045 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6046 | { | |
6047 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6048 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6050 | struct intel_encoder *encoder; | |
b95c5321 ML |
6051 | struct intel_crtc_state *pipe_config = |
6052 | to_intel_crtc_state(crtc->state); | |
89b667f8 | 6053 | int pipe = intel_crtc->pipe; |
89b667f8 | 6054 | |
53d9f4e9 | 6055 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6056 | return; |
6057 | ||
6e3c9717 | 6058 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6059 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6060 | |
6061 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6062 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6063 | |
c14b0485 VS |
6064 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6066 | ||
6067 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6068 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6069 | } | |
6070 | ||
5b18e57c DV |
6071 | i9xx_set_pipeconf(intel_crtc); |
6072 | ||
89b667f8 | 6073 | intel_crtc->active = true; |
89b667f8 | 6074 | |
a72e4c9f | 6075 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6076 | |
89b667f8 JB |
6077 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6078 | if (encoder->pre_pll_enable) | |
6079 | encoder->pre_pll_enable(encoder); | |
6080 | ||
cd2d34d9 VS |
6081 | if (IS_CHERRYVIEW(dev)) { |
6082 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6083 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6084 | } else { | |
6085 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6086 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6087 | } |
89b667f8 JB |
6088 | |
6089 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6090 | if (encoder->pre_enable) | |
6091 | encoder->pre_enable(encoder); | |
6092 | ||
2dd24552 JB |
6093 | i9xx_pfit_enable(intel_crtc); |
6094 | ||
b95c5321 | 6095 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6096 | |
caed361d | 6097 | intel_update_watermarks(crtc); |
e1fdc473 | 6098 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6099 | |
4b3a9526 VS |
6100 | assert_vblank_disabled(crtc); |
6101 | drm_crtc_vblank_on(crtc); | |
6102 | ||
f9b61ff6 DV |
6103 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6104 | encoder->enable(encoder); | |
89b667f8 JB |
6105 | } |
6106 | ||
f13c2ef3 DV |
6107 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6108 | { | |
6109 | struct drm_device *dev = crtc->base.dev; | |
6110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6111 | ||
6e3c9717 ACO |
6112 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6113 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6114 | } |
6115 | ||
0b8765c6 | 6116 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6117 | { |
6118 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6119 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6121 | struct intel_encoder *encoder; |
b95c5321 ML |
6122 | struct intel_crtc_state *pipe_config = |
6123 | to_intel_crtc_state(crtc->state); | |
cd2d34d9 | 6124 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6125 | |
53d9f4e9 | 6126 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6127 | return; |
6128 | ||
f13c2ef3 DV |
6129 | i9xx_set_pll_dividers(intel_crtc); |
6130 | ||
6e3c9717 | 6131 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6132 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6133 | |
6134 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6135 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6136 | |
5b18e57c DV |
6137 | i9xx_set_pipeconf(intel_crtc); |
6138 | ||
f7abfe8b | 6139 | intel_crtc->active = true; |
6b383a7f | 6140 | |
4a3436e8 | 6141 | if (!IS_GEN2(dev)) |
a72e4c9f | 6142 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6143 | |
9d6d9f19 MK |
6144 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6145 | if (encoder->pre_enable) | |
6146 | encoder->pre_enable(encoder); | |
6147 | ||
f6736a1a DV |
6148 | i9xx_enable_pll(intel_crtc); |
6149 | ||
2dd24552 JB |
6150 | i9xx_pfit_enable(intel_crtc); |
6151 | ||
b95c5321 | 6152 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6153 | |
f37fcc2a | 6154 | intel_update_watermarks(crtc); |
e1fdc473 | 6155 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6156 | |
4b3a9526 VS |
6157 | assert_vblank_disabled(crtc); |
6158 | drm_crtc_vblank_on(crtc); | |
6159 | ||
f9b61ff6 DV |
6160 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6161 | encoder->enable(encoder); | |
0b8765c6 | 6162 | } |
79e53945 | 6163 | |
87476d63 DV |
6164 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6165 | { | |
6166 | struct drm_device *dev = crtc->base.dev; | |
6167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6168 | |
6e3c9717 | 6169 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6170 | return; |
87476d63 | 6171 | |
328d8e82 | 6172 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6173 | |
328d8e82 DV |
6174 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6175 | I915_READ(PFIT_CONTROL)); | |
6176 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6177 | } |
6178 | ||
0b8765c6 JB |
6179 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6180 | { | |
6181 | struct drm_device *dev = crtc->dev; | |
6182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6184 | struct intel_encoder *encoder; |
0b8765c6 | 6185 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6186 | |
6304cd91 VS |
6187 | /* |
6188 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6189 | * wait for planes to fully turn off before disabling the pipe. | |
6190 | */ | |
90e83e53 ACO |
6191 | if (IS_GEN2(dev)) |
6192 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6193 | |
4b3a9526 VS |
6194 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6195 | encoder->disable(encoder); | |
6196 | ||
f9b61ff6 DV |
6197 | drm_crtc_vblank_off(crtc); |
6198 | assert_vblank_disabled(crtc); | |
6199 | ||
575f7ab7 | 6200 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6201 | |
87476d63 | 6202 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6203 | |
89b667f8 JB |
6204 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6205 | if (encoder->post_disable) | |
6206 | encoder->post_disable(encoder); | |
6207 | ||
a65347ba | 6208 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6209 | if (IS_CHERRYVIEW(dev)) |
6210 | chv_disable_pll(dev_priv, pipe); | |
6211 | else if (IS_VALLEYVIEW(dev)) | |
6212 | vlv_disable_pll(dev_priv, pipe); | |
6213 | else | |
1c4e0274 | 6214 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6215 | } |
0b8765c6 | 6216 | |
d6db995f VS |
6217 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6218 | if (encoder->post_pll_disable) | |
6219 | encoder->post_pll_disable(encoder); | |
6220 | ||
4a3436e8 | 6221 | if (!IS_GEN2(dev)) |
a72e4c9f | 6222 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6223 | } |
6224 | ||
b17d48e2 ML |
6225 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6226 | { | |
842e0307 | 6227 | struct intel_encoder *encoder; |
b17d48e2 ML |
6228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6229 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6230 | enum intel_display_power_domain domain; | |
6231 | unsigned long domains; | |
6232 | ||
6233 | if (!intel_crtc->active) | |
6234 | return; | |
6235 | ||
a539205a | 6236 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6237 | WARN_ON(intel_crtc->unpin_work); |
6238 | ||
2622a081 | 6239 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6240 | |
6241 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6242 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6243 | } |
6244 | ||
b17d48e2 | 6245 | dev_priv->display.crtc_disable(crtc); |
842e0307 ML |
6246 | |
6247 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n", | |
6248 | crtc->base.id); | |
6249 | ||
6250 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6251 | crtc->state->active = false; | |
37d9078b | 6252 | intel_crtc->active = false; |
842e0307 ML |
6253 | crtc->enabled = false; |
6254 | crtc->state->connector_mask = 0; | |
6255 | crtc->state->encoder_mask = 0; | |
6256 | ||
6257 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6258 | encoder->base.crtc = NULL; | |
6259 | ||
58f9c0bc | 6260 | intel_fbc_disable(intel_crtc); |
37d9078b | 6261 | intel_update_watermarks(crtc); |
1f7457b1 | 6262 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6263 | |
6264 | domains = intel_crtc->enabled_power_domains; | |
6265 | for_each_power_domain(domain, domains) | |
6266 | intel_display_power_put(dev_priv, domain); | |
6267 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6268 | |
6269 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6270 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6271 | } |
6272 | ||
6b72d486 ML |
6273 | /* |
6274 | * turn all crtc's off, but do not adjust state | |
6275 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6276 | */ | |
70e0bd74 | 6277 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6278 | { |
e2c8b870 | 6279 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6280 | struct drm_atomic_state *state; |
e2c8b870 | 6281 | int ret; |
70e0bd74 | 6282 | |
e2c8b870 ML |
6283 | state = drm_atomic_helper_suspend(dev); |
6284 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6285 | if (ret) |
6286 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6287 | else |
6288 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6289 | return ret; |
ee7b9f93 JB |
6290 | } |
6291 | ||
ea5b213a | 6292 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6293 | { |
4ef69c7a | 6294 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6295 | |
ea5b213a CW |
6296 | drm_encoder_cleanup(encoder); |
6297 | kfree(intel_encoder); | |
7e7d76c3 JB |
6298 | } |
6299 | ||
0a91ca29 DV |
6300 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6301 | * internal consistency). */ | |
c0ead703 | 6302 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6303 | { |
35dd3c64 ML |
6304 | struct drm_crtc *crtc = connector->base.state->crtc; |
6305 | ||
6306 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6307 | connector->base.base.id, | |
6308 | connector->base.name); | |
6309 | ||
0a91ca29 | 6310 | if (connector->get_hw_state(connector)) { |
e85376cb | 6311 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6312 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6313 | |
35dd3c64 ML |
6314 | I915_STATE_WARN(!crtc, |
6315 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6316 | |
35dd3c64 ML |
6317 | if (!crtc) |
6318 | return; | |
6319 | ||
6320 | I915_STATE_WARN(!crtc->state->active, | |
6321 | "connector is active, but attached crtc isn't\n"); | |
6322 | ||
e85376cb | 6323 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6324 | return; |
6325 | ||
e85376cb | 6326 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6327 | "atomic encoder doesn't match attached encoder\n"); |
6328 | ||
e85376cb | 6329 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6330 | "attached encoder crtc differs from connector crtc\n"); |
6331 | } else { | |
4d688a2a ML |
6332 | I915_STATE_WARN(crtc && crtc->state->active, |
6333 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6334 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6335 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6336 | } |
79e53945 JB |
6337 | } |
6338 | ||
08d9bc92 ACO |
6339 | int intel_connector_init(struct intel_connector *connector) |
6340 | { | |
5350a031 | 6341 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6342 | |
5350a031 | 6343 | if (!connector->base.state) |
08d9bc92 ACO |
6344 | return -ENOMEM; |
6345 | ||
08d9bc92 ACO |
6346 | return 0; |
6347 | } | |
6348 | ||
6349 | struct intel_connector *intel_connector_alloc(void) | |
6350 | { | |
6351 | struct intel_connector *connector; | |
6352 | ||
6353 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6354 | if (!connector) | |
6355 | return NULL; | |
6356 | ||
6357 | if (intel_connector_init(connector) < 0) { | |
6358 | kfree(connector); | |
6359 | return NULL; | |
6360 | } | |
6361 | ||
6362 | return connector; | |
6363 | } | |
6364 | ||
f0947c37 DV |
6365 | /* Simple connector->get_hw_state implementation for encoders that support only |
6366 | * one connector and no cloning and hence the encoder state determines the state | |
6367 | * of the connector. */ | |
6368 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6369 | { |
24929352 | 6370 | enum pipe pipe = 0; |
f0947c37 | 6371 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6372 | |
f0947c37 | 6373 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6374 | } |
6375 | ||
6d293983 | 6376 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6377 | { |
6d293983 ACO |
6378 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6379 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6380 | |
6381 | return 0; | |
6382 | } | |
6383 | ||
6d293983 | 6384 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6385 | struct intel_crtc_state *pipe_config) |
1857e1da | 6386 | { |
6d293983 ACO |
6387 | struct drm_atomic_state *state = pipe_config->base.state; |
6388 | struct intel_crtc *other_crtc; | |
6389 | struct intel_crtc_state *other_crtc_state; | |
6390 | ||
1857e1da DV |
6391 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6392 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6393 | if (pipe_config->fdi_lanes > 4) { | |
6394 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6395 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6396 | return -EINVAL; |
1857e1da DV |
6397 | } |
6398 | ||
bafb6553 | 6399 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6400 | if (pipe_config->fdi_lanes > 2) { |
6401 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6402 | pipe_config->fdi_lanes); | |
6d293983 | 6403 | return -EINVAL; |
1857e1da | 6404 | } else { |
6d293983 | 6405 | return 0; |
1857e1da DV |
6406 | } |
6407 | } | |
6408 | ||
6409 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6410 | return 0; |
1857e1da DV |
6411 | |
6412 | /* Ivybridge 3 pipe is really complicated */ | |
6413 | switch (pipe) { | |
6414 | case PIPE_A: | |
6d293983 | 6415 | return 0; |
1857e1da | 6416 | case PIPE_B: |
6d293983 ACO |
6417 | if (pipe_config->fdi_lanes <= 2) |
6418 | return 0; | |
6419 | ||
6420 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6421 | other_crtc_state = | |
6422 | intel_atomic_get_crtc_state(state, other_crtc); | |
6423 | if (IS_ERR(other_crtc_state)) | |
6424 | return PTR_ERR(other_crtc_state); | |
6425 | ||
6426 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6427 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6428 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6429 | return -EINVAL; |
1857e1da | 6430 | } |
6d293983 | 6431 | return 0; |
1857e1da | 6432 | case PIPE_C: |
251cc67c VS |
6433 | if (pipe_config->fdi_lanes > 2) { |
6434 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6435 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6436 | return -EINVAL; |
251cc67c | 6437 | } |
6d293983 ACO |
6438 | |
6439 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6440 | other_crtc_state = | |
6441 | intel_atomic_get_crtc_state(state, other_crtc); | |
6442 | if (IS_ERR(other_crtc_state)) | |
6443 | return PTR_ERR(other_crtc_state); | |
6444 | ||
6445 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6446 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6447 | return -EINVAL; |
1857e1da | 6448 | } |
6d293983 | 6449 | return 0; |
1857e1da DV |
6450 | default: |
6451 | BUG(); | |
6452 | } | |
6453 | } | |
6454 | ||
e29c22c0 DV |
6455 | #define RETRY 1 |
6456 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6457 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6458 | { |
1857e1da | 6459 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6460 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6461 | int lane, link_bw, fdi_dotclock, ret; |
6462 | bool needs_recompute = false; | |
877d48d5 | 6463 | |
e29c22c0 | 6464 | retry: |
877d48d5 DV |
6465 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6466 | * each output octet as 10 bits. The actual frequency | |
6467 | * is stored as a divider into a 100MHz clock, and the | |
6468 | * mode pixel clock is stored in units of 1KHz. | |
6469 | * Hence the bw of each lane in terms of the mode signal | |
6470 | * is: | |
6471 | */ | |
21a727b3 | 6472 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6473 | |
241bfc38 | 6474 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6475 | |
2bd89a07 | 6476 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6477 | pipe_config->pipe_bpp); |
6478 | ||
6479 | pipe_config->fdi_lanes = lane; | |
6480 | ||
2bd89a07 | 6481 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6482 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6483 | |
e3b247da | 6484 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6485 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6486 | pipe_config->pipe_bpp -= 2*3; |
6487 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6488 | pipe_config->pipe_bpp); | |
6489 | needs_recompute = true; | |
6490 | pipe_config->bw_constrained = true; | |
6491 | ||
6492 | goto retry; | |
6493 | } | |
6494 | ||
6495 | if (needs_recompute) | |
6496 | return RETRY; | |
6497 | ||
6d293983 | 6498 | return ret; |
877d48d5 DV |
6499 | } |
6500 | ||
8cfb3407 VS |
6501 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6502 | struct intel_crtc_state *pipe_config) | |
6503 | { | |
6504 | if (pipe_config->pipe_bpp > 24) | |
6505 | return false; | |
6506 | ||
6507 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 6508 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
6509 | return true; |
6510 | ||
6511 | /* | |
b432e5cf VS |
6512 | * We compare against max which means we must take |
6513 | * the increased cdclk requirement into account when | |
6514 | * calculating the new cdclk. | |
6515 | * | |
6516 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6517 | */ |
6518 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6519 | dev_priv->max_cdclk_freq * 95 / 100; | |
6520 | } | |
6521 | ||
42db64ef | 6522 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6523 | struct intel_crtc_state *pipe_config) |
42db64ef | 6524 | { |
8cfb3407 VS |
6525 | struct drm_device *dev = crtc->base.dev; |
6526 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6527 | ||
d330a953 | 6528 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6529 | hsw_crtc_supports_ips(crtc) && |
6530 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6531 | } |
6532 | ||
39acb4aa VS |
6533 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6534 | { | |
6535 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6536 | ||
6537 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6538 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6539 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6540 | } | |
6541 | ||
a43f6e0f | 6542 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6543 | struct intel_crtc_state *pipe_config) |
79e53945 | 6544 | { |
a43f6e0f | 6545 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6546 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6547 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6548 | |
ad3a4479 | 6549 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6550 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6551 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6552 | |
6553 | /* | |
39acb4aa | 6554 | * Enable double wide mode when the dot clock |
cf532bb2 | 6555 | * is > 90% of the (display) core speed. |
cf532bb2 | 6556 | */ |
39acb4aa VS |
6557 | if (intel_crtc_supports_double_wide(crtc) && |
6558 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6559 | clock_limit *= 2; |
cf532bb2 | 6560 | pipe_config->double_wide = true; |
ad3a4479 VS |
6561 | } |
6562 | ||
39acb4aa VS |
6563 | if (adjusted_mode->crtc_clock > clock_limit) { |
6564 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6565 | adjusted_mode->crtc_clock, clock_limit, | |
6566 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6567 | return -EINVAL; |
39acb4aa | 6568 | } |
2c07245f | 6569 | } |
89749350 | 6570 | |
1d1d0e27 VS |
6571 | /* |
6572 | * Pipe horizontal size must be even in: | |
6573 | * - DVO ganged mode | |
6574 | * - LVDS dual channel mode | |
6575 | * - Double wide pipe | |
6576 | */ | |
a93e255f | 6577 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6578 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6579 | pipe_config->pipe_src_w &= ~1; | |
6580 | ||
8693a824 DL |
6581 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6582 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6583 | */ |
6584 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6585 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6586 | return -EINVAL; |
44f46b42 | 6587 | |
f5adf94e | 6588 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6589 | hsw_compute_ips_config(crtc, pipe_config); |
6590 | ||
877d48d5 | 6591 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6592 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6593 | |
cf5a15be | 6594 | return 0; |
79e53945 JB |
6595 | } |
6596 | ||
1652d19e VS |
6597 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6598 | { | |
6599 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6600 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6601 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6602 | uint32_t linkrate; | |
6603 | ||
414355a7 | 6604 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6605 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6606 | |
6607 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6608 | return 540000; | |
6609 | ||
6610 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6611 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6612 | |
71cd8423 DL |
6613 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6614 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6615 | /* vco 8640 */ |
6616 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6617 | case CDCLK_FREQ_450_432: | |
6618 | return 432000; | |
6619 | case CDCLK_FREQ_337_308: | |
6620 | return 308570; | |
6621 | case CDCLK_FREQ_675_617: | |
6622 | return 617140; | |
6623 | default: | |
6624 | WARN(1, "Unknown cd freq selection\n"); | |
6625 | } | |
6626 | } else { | |
6627 | /* vco 8100 */ | |
6628 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6629 | case CDCLK_FREQ_450_432: | |
6630 | return 450000; | |
6631 | case CDCLK_FREQ_337_308: | |
6632 | return 337500; | |
6633 | case CDCLK_FREQ_675_617: | |
6634 | return 675000; | |
6635 | default: | |
6636 | WARN(1, "Unknown cd freq selection\n"); | |
6637 | } | |
6638 | } | |
6639 | ||
6640 | /* error case, do as if DPLL0 isn't enabled */ | |
6641 | return 24000; | |
6642 | } | |
6643 | ||
acd3f3d3 BP |
6644 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6645 | { | |
6646 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6647 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6648 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6649 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6650 | int cdclk; | |
6651 | ||
6652 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6653 | return 19200; | |
6654 | ||
6655 | cdclk = 19200 * pll_ratio / 2; | |
6656 | ||
6657 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6658 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6659 | return cdclk; /* 576MHz or 624MHz */ | |
6660 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6661 | return cdclk * 2 / 3; /* 384MHz */ | |
6662 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6663 | return cdclk / 2; /* 288MHz */ | |
6664 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6665 | return cdclk / 4; /* 144MHz */ | |
6666 | } | |
6667 | ||
6668 | /* error case, do as if DE PLL isn't enabled */ | |
6669 | return 19200; | |
6670 | } | |
6671 | ||
1652d19e VS |
6672 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6673 | { | |
6674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6675 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6676 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6677 | ||
6678 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6679 | return 800000; | |
6680 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6681 | return 450000; | |
6682 | else if (freq == LCPLL_CLK_FREQ_450) | |
6683 | return 450000; | |
6684 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6685 | return 540000; | |
6686 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6687 | return 337500; | |
6688 | else | |
6689 | return 675000; | |
6690 | } | |
6691 | ||
6692 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6693 | { | |
6694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6695 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6696 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6697 | ||
6698 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6699 | return 800000; | |
6700 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6701 | return 450000; | |
6702 | else if (freq == LCPLL_CLK_FREQ_450) | |
6703 | return 450000; | |
6704 | else if (IS_HSW_ULT(dev)) | |
6705 | return 337500; | |
6706 | else | |
6707 | return 540000; | |
79e53945 JB |
6708 | } |
6709 | ||
25eb05fc JB |
6710 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6711 | { | |
bfa7df01 VS |
6712 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6713 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6714 | } |
6715 | ||
b37a6434 VS |
6716 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6717 | { | |
6718 | return 450000; | |
6719 | } | |
6720 | ||
e70236a8 JB |
6721 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6722 | { | |
6723 | return 400000; | |
6724 | } | |
79e53945 | 6725 | |
e70236a8 | 6726 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6727 | { |
e907f170 | 6728 | return 333333; |
e70236a8 | 6729 | } |
79e53945 | 6730 | |
e70236a8 JB |
6731 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6732 | { | |
6733 | return 200000; | |
6734 | } | |
79e53945 | 6735 | |
257a7ffc DV |
6736 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6737 | { | |
6738 | u16 gcfgc = 0; | |
6739 | ||
6740 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6741 | ||
6742 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6743 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6744 | return 266667; |
257a7ffc | 6745 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6746 | return 333333; |
257a7ffc | 6747 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6748 | return 444444; |
257a7ffc DV |
6749 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6750 | return 200000; | |
6751 | default: | |
6752 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6753 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6754 | return 133333; |
257a7ffc | 6755 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6756 | return 166667; |
257a7ffc DV |
6757 | } |
6758 | } | |
6759 | ||
e70236a8 JB |
6760 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6761 | { | |
6762 | u16 gcfgc = 0; | |
79e53945 | 6763 | |
e70236a8 JB |
6764 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6765 | ||
6766 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6767 | return 133333; |
e70236a8 JB |
6768 | else { |
6769 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6770 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6771 | return 333333; |
e70236a8 JB |
6772 | default: |
6773 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6774 | return 190000; | |
79e53945 | 6775 | } |
e70236a8 JB |
6776 | } |
6777 | } | |
6778 | ||
6779 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6780 | { | |
e907f170 | 6781 | return 266667; |
e70236a8 JB |
6782 | } |
6783 | ||
1b1d2716 | 6784 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6785 | { |
6786 | u16 hpllcc = 0; | |
1b1d2716 | 6787 | |
65cd2b3f VS |
6788 | /* |
6789 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6790 | * encoding is different :( | |
6791 | * FIXME is this the right way to detect 852GM/852GMV? | |
6792 | */ | |
6793 | if (dev->pdev->revision == 0x1) | |
6794 | return 133333; | |
6795 | ||
1b1d2716 VS |
6796 | pci_bus_read_config_word(dev->pdev->bus, |
6797 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6798 | ||
e70236a8 JB |
6799 | /* Assume that the hardware is in the high speed state. This |
6800 | * should be the default. | |
6801 | */ | |
6802 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6803 | case GC_CLOCK_133_200: | |
1b1d2716 | 6804 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6805 | case GC_CLOCK_100_200: |
6806 | return 200000; | |
6807 | case GC_CLOCK_166_250: | |
6808 | return 250000; | |
6809 | case GC_CLOCK_100_133: | |
e907f170 | 6810 | return 133333; |
1b1d2716 VS |
6811 | case GC_CLOCK_133_266: |
6812 | case GC_CLOCK_133_266_2: | |
6813 | case GC_CLOCK_166_266: | |
6814 | return 266667; | |
e70236a8 | 6815 | } |
79e53945 | 6816 | |
e70236a8 JB |
6817 | /* Shouldn't happen */ |
6818 | return 0; | |
6819 | } | |
79e53945 | 6820 | |
e70236a8 JB |
6821 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6822 | { | |
e907f170 | 6823 | return 133333; |
79e53945 JB |
6824 | } |
6825 | ||
34edce2f VS |
6826 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6827 | { | |
6828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6829 | static const unsigned int blb_vco[8] = { | |
6830 | [0] = 3200000, | |
6831 | [1] = 4000000, | |
6832 | [2] = 5333333, | |
6833 | [3] = 4800000, | |
6834 | [4] = 6400000, | |
6835 | }; | |
6836 | static const unsigned int pnv_vco[8] = { | |
6837 | [0] = 3200000, | |
6838 | [1] = 4000000, | |
6839 | [2] = 5333333, | |
6840 | [3] = 4800000, | |
6841 | [4] = 2666667, | |
6842 | }; | |
6843 | static const unsigned int cl_vco[8] = { | |
6844 | [0] = 3200000, | |
6845 | [1] = 4000000, | |
6846 | [2] = 5333333, | |
6847 | [3] = 6400000, | |
6848 | [4] = 3333333, | |
6849 | [5] = 3566667, | |
6850 | [6] = 4266667, | |
6851 | }; | |
6852 | static const unsigned int elk_vco[8] = { | |
6853 | [0] = 3200000, | |
6854 | [1] = 4000000, | |
6855 | [2] = 5333333, | |
6856 | [3] = 4800000, | |
6857 | }; | |
6858 | static const unsigned int ctg_vco[8] = { | |
6859 | [0] = 3200000, | |
6860 | [1] = 4000000, | |
6861 | [2] = 5333333, | |
6862 | [3] = 6400000, | |
6863 | [4] = 2666667, | |
6864 | [5] = 4266667, | |
6865 | }; | |
6866 | const unsigned int *vco_table; | |
6867 | unsigned int vco; | |
6868 | uint8_t tmp = 0; | |
6869 | ||
6870 | /* FIXME other chipsets? */ | |
6871 | if (IS_GM45(dev)) | |
6872 | vco_table = ctg_vco; | |
6873 | else if (IS_G4X(dev)) | |
6874 | vco_table = elk_vco; | |
6875 | else if (IS_CRESTLINE(dev)) | |
6876 | vco_table = cl_vco; | |
6877 | else if (IS_PINEVIEW(dev)) | |
6878 | vco_table = pnv_vco; | |
6879 | else if (IS_G33(dev)) | |
6880 | vco_table = blb_vco; | |
6881 | else | |
6882 | return 0; | |
6883 | ||
6884 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6885 | ||
6886 | vco = vco_table[tmp & 0x7]; | |
6887 | if (vco == 0) | |
6888 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6889 | else | |
6890 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6891 | ||
6892 | return vco; | |
6893 | } | |
6894 | ||
6895 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6896 | { | |
6897 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6898 | uint16_t tmp = 0; | |
6899 | ||
6900 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6901 | ||
6902 | cdclk_sel = (tmp >> 12) & 0x1; | |
6903 | ||
6904 | switch (vco) { | |
6905 | case 2666667: | |
6906 | case 4000000: | |
6907 | case 5333333: | |
6908 | return cdclk_sel ? 333333 : 222222; | |
6909 | case 3200000: | |
6910 | return cdclk_sel ? 320000 : 228571; | |
6911 | default: | |
6912 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6913 | return 222222; | |
6914 | } | |
6915 | } | |
6916 | ||
6917 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6918 | { | |
6919 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6920 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6921 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6922 | const uint8_t *div_table; | |
6923 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6924 | uint16_t tmp = 0; | |
6925 | ||
6926 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6927 | ||
6928 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6929 | ||
6930 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6931 | goto fail; | |
6932 | ||
6933 | switch (vco) { | |
6934 | case 3200000: | |
6935 | div_table = div_3200; | |
6936 | break; | |
6937 | case 4000000: | |
6938 | div_table = div_4000; | |
6939 | break; | |
6940 | case 5333333: | |
6941 | div_table = div_5333; | |
6942 | break; | |
6943 | default: | |
6944 | goto fail; | |
6945 | } | |
6946 | ||
6947 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6948 | ||
caf4e252 | 6949 | fail: |
34edce2f VS |
6950 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
6951 | return 200000; | |
6952 | } | |
6953 | ||
6954 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
6955 | { | |
6956 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
6957 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
6958 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
6959 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
6960 | const uint8_t *div_table; | |
6961 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6962 | uint16_t tmp = 0; | |
6963 | ||
6964 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6965 | ||
6966 | cdclk_sel = (tmp >> 4) & 0x7; | |
6967 | ||
6968 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6969 | goto fail; | |
6970 | ||
6971 | switch (vco) { | |
6972 | case 3200000: | |
6973 | div_table = div_3200; | |
6974 | break; | |
6975 | case 4000000: | |
6976 | div_table = div_4000; | |
6977 | break; | |
6978 | case 4800000: | |
6979 | div_table = div_4800; | |
6980 | break; | |
6981 | case 5333333: | |
6982 | div_table = div_5333; | |
6983 | break; | |
6984 | default: | |
6985 | goto fail; | |
6986 | } | |
6987 | ||
6988 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6989 | ||
caf4e252 | 6990 | fail: |
34edce2f VS |
6991 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
6992 | return 190476; | |
6993 | } | |
6994 | ||
2c07245f | 6995 | static void |
a65851af | 6996 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6997 | { |
a65851af VS |
6998 | while (*num > DATA_LINK_M_N_MASK || |
6999 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7000 | *num >>= 1; |
7001 | *den >>= 1; | |
7002 | } | |
7003 | } | |
7004 | ||
a65851af VS |
7005 | static void compute_m_n(unsigned int m, unsigned int n, |
7006 | uint32_t *ret_m, uint32_t *ret_n) | |
7007 | { | |
7008 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7009 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7010 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7011 | } | |
7012 | ||
e69d0bc1 DV |
7013 | void |
7014 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7015 | int pixel_clock, int link_clock, | |
7016 | struct intel_link_m_n *m_n) | |
2c07245f | 7017 | { |
e69d0bc1 | 7018 | m_n->tu = 64; |
a65851af VS |
7019 | |
7020 | compute_m_n(bits_per_pixel * pixel_clock, | |
7021 | link_clock * nlanes * 8, | |
7022 | &m_n->gmch_m, &m_n->gmch_n); | |
7023 | ||
7024 | compute_m_n(pixel_clock, link_clock, | |
7025 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7026 | } |
7027 | ||
a7615030 CW |
7028 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7029 | { | |
d330a953 JN |
7030 | if (i915.panel_use_ssc >= 0) |
7031 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7032 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7033 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7034 | } |
7035 | ||
7429e9d4 | 7036 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7037 | { |
7df00d7a | 7038 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7039 | } |
f47709a9 | 7040 | |
7429e9d4 DV |
7041 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7042 | { | |
7043 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7044 | } |
7045 | ||
f47709a9 | 7046 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7047 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7048 | struct dpll *reduced_clock) |
a7516a05 | 7049 | { |
f47709a9 | 7050 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7051 | u32 fp, fp2 = 0; |
7052 | ||
7053 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7054 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7055 | if (reduced_clock) |
7429e9d4 | 7056 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7057 | } else { |
190f68c5 | 7058 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7059 | if (reduced_clock) |
7429e9d4 | 7060 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7061 | } |
7062 | ||
190f68c5 | 7063 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7064 | |
f47709a9 | 7065 | crtc->lowfreq_avail = false; |
a93e255f | 7066 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7067 | reduced_clock) { |
190f68c5 | 7068 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7069 | crtc->lowfreq_avail = true; |
a7516a05 | 7070 | } else { |
190f68c5 | 7071 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7072 | } |
7073 | } | |
7074 | ||
5e69f97f CML |
7075 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7076 | pipe) | |
89b667f8 JB |
7077 | { |
7078 | u32 reg_val; | |
7079 | ||
7080 | /* | |
7081 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7082 | * and set it to a reasonable value instead. | |
7083 | */ | |
ab3c759a | 7084 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7085 | reg_val &= 0xffffff00; |
7086 | reg_val |= 0x00000030; | |
ab3c759a | 7087 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7088 | |
ab3c759a | 7089 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7090 | reg_val &= 0x8cffffff; |
7091 | reg_val = 0x8c000000; | |
ab3c759a | 7092 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7093 | |
ab3c759a | 7094 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7095 | reg_val &= 0xffffff00; |
ab3c759a | 7096 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7097 | |
ab3c759a | 7098 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7099 | reg_val &= 0x00ffffff; |
7100 | reg_val |= 0xb0000000; | |
ab3c759a | 7101 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7102 | } |
7103 | ||
b551842d DV |
7104 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7105 | struct intel_link_m_n *m_n) | |
7106 | { | |
7107 | struct drm_device *dev = crtc->base.dev; | |
7108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7109 | int pipe = crtc->pipe; | |
7110 | ||
e3b95f1e DV |
7111 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7112 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7113 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7114 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7115 | } |
7116 | ||
7117 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7118 | struct intel_link_m_n *m_n, |
7119 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7120 | { |
7121 | struct drm_device *dev = crtc->base.dev; | |
7122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7123 | int pipe = crtc->pipe; | |
6e3c9717 | 7124 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7125 | |
7126 | if (INTEL_INFO(dev)->gen >= 5) { | |
7127 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7128 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7129 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7130 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7131 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7132 | * for gen < 8) and if DRRS is supported (to make sure the | |
7133 | * registers are not unnecessarily accessed). | |
7134 | */ | |
44395bfe | 7135 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7136 | crtc->config->has_drrs) { |
f769cd24 VK |
7137 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7138 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7139 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7140 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7141 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7142 | } | |
b551842d | 7143 | } else { |
e3b95f1e DV |
7144 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7145 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7146 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7147 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7148 | } |
7149 | } | |
7150 | ||
fe3cd48d | 7151 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7152 | { |
fe3cd48d R |
7153 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7154 | ||
7155 | if (m_n == M1_N1) { | |
7156 | dp_m_n = &crtc->config->dp_m_n; | |
7157 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7158 | } else if (m_n == M2_N2) { | |
7159 | ||
7160 | /* | |
7161 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7162 | * needs to be programmed into M1_N1. | |
7163 | */ | |
7164 | dp_m_n = &crtc->config->dp_m2_n2; | |
7165 | } else { | |
7166 | DRM_ERROR("Unsupported divider value\n"); | |
7167 | return; | |
7168 | } | |
7169 | ||
6e3c9717 ACO |
7170 | if (crtc->config->has_pch_encoder) |
7171 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7172 | else |
fe3cd48d | 7173 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7174 | } |
7175 | ||
251ac862 DV |
7176 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7177 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7178 | { |
03ed5cbf | 7179 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7180 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7181 | if (crtc->pipe != PIPE_A) |
7182 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7183 | |
cd2d34d9 | 7184 | /* DPLL not used with DSI, but still need the rest set up */ |
187a1c07 | 7185 | if (!pipe_config->has_dsi_encoder) |
cd2d34d9 VS |
7186 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7187 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7188 | ||
03ed5cbf VS |
7189 | pipe_config->dpll_hw_state.dpll_md = |
7190 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7191 | } | |
bdd4b6a6 | 7192 | |
03ed5cbf VS |
7193 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7194 | struct intel_crtc_state *pipe_config) | |
7195 | { | |
7196 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7197 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7198 | if (crtc->pipe != PIPE_A) |
7199 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7200 | ||
cd2d34d9 | 7201 | /* DPLL not used with DSI, but still need the rest set up */ |
187a1c07 | 7202 | if (!pipe_config->has_dsi_encoder) |
cd2d34d9 VS |
7203 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7204 | ||
03ed5cbf VS |
7205 | pipe_config->dpll_hw_state.dpll_md = |
7206 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7207 | } |
7208 | ||
d288f65f | 7209 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7210 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7211 | { |
f47709a9 | 7212 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7213 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd2d34d9 | 7214 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7215 | u32 mdiv; |
a0c4da24 | 7216 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7217 | u32 coreclk, reg_val; |
a0c4da24 | 7218 | |
cd2d34d9 VS |
7219 | /* Enable Refclk */ |
7220 | I915_WRITE(DPLL(pipe), | |
7221 | pipe_config->dpll_hw_state.dpll & | |
7222 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7223 | ||
7224 | /* No need to actually set up the DPLL with DSI */ | |
7225 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7226 | return; | |
7227 | ||
a580516d | 7228 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7229 | |
d288f65f VS |
7230 | bestn = pipe_config->dpll.n; |
7231 | bestm1 = pipe_config->dpll.m1; | |
7232 | bestm2 = pipe_config->dpll.m2; | |
7233 | bestp1 = pipe_config->dpll.p1; | |
7234 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7235 | |
89b667f8 JB |
7236 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7237 | ||
7238 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7239 | if (pipe == PIPE_B) |
5e69f97f | 7240 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7241 | |
7242 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7243 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7244 | |
7245 | /* Disable target IRef on PLL */ | |
ab3c759a | 7246 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7247 | reg_val &= 0x00ffffff; |
ab3c759a | 7248 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7249 | |
7250 | /* Disable fast lock */ | |
ab3c759a | 7251 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7252 | |
7253 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7254 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7255 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7256 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7257 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7258 | |
7259 | /* | |
7260 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7261 | * but we don't support that). | |
7262 | * Note: don't use the DAC post divider as it seems unstable. | |
7263 | */ | |
7264 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7265 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7266 | |
a0c4da24 | 7267 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7268 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7269 | |
89b667f8 | 7270 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7271 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7272 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7273 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7274 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7275 | 0x009f0003); |
89b667f8 | 7276 | else |
ab3c759a | 7277 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7278 | 0x00d0000f); |
7279 | ||
681a8504 | 7280 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7281 | /* Use SSC source */ |
bdd4b6a6 | 7282 | if (pipe == PIPE_A) |
ab3c759a | 7283 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7284 | 0x0df40000); |
7285 | else | |
ab3c759a | 7286 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7287 | 0x0df70000); |
7288 | } else { /* HDMI or VGA */ | |
7289 | /* Use bend source */ | |
bdd4b6a6 | 7290 | if (pipe == PIPE_A) |
ab3c759a | 7291 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7292 | 0x0df70000); |
7293 | else | |
ab3c759a | 7294 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7295 | 0x0df40000); |
7296 | } | |
a0c4da24 | 7297 | |
ab3c759a | 7298 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7299 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7300 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7301 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7302 | coreclk |= 0x01000000; |
ab3c759a | 7303 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7304 | |
ab3c759a | 7305 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7306 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7307 | } |
7308 | ||
d288f65f | 7309 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7310 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7311 | { |
7312 | struct drm_device *dev = crtc->base.dev; | |
7313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cd2d34d9 | 7314 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7315 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7316 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7317 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7318 | u32 dpio_val; |
9cbe40c1 | 7319 | int vco; |
9d556c99 | 7320 | |
cd2d34d9 VS |
7321 | /* Enable Refclk and SSC */ |
7322 | I915_WRITE(DPLL(pipe), | |
7323 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7324 | ||
7325 | /* No need to actually set up the DPLL with DSI */ | |
7326 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7327 | return; | |
7328 | ||
d288f65f VS |
7329 | bestn = pipe_config->dpll.n; |
7330 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7331 | bestm1 = pipe_config->dpll.m1; | |
7332 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7333 | bestp1 = pipe_config->dpll.p1; | |
7334 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7335 | vco = pipe_config->dpll.vco; |
a945ce7e | 7336 | dpio_val = 0; |
9cbe40c1 | 7337 | loopfilter = 0; |
9d556c99 | 7338 | |
a580516d | 7339 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7340 | |
9d556c99 CML |
7341 | /* p1 and p2 divider */ |
7342 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7343 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7344 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7345 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7346 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7347 | ||
7348 | /* Feedback post-divider - m2 */ | |
7349 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7350 | ||
7351 | /* Feedback refclk divider - n and m1 */ | |
7352 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7353 | DPIO_CHV_M1_DIV_BY_2 | | |
7354 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7355 | ||
7356 | /* M2 fraction division */ | |
25a25dfc | 7357 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7358 | |
7359 | /* M2 fraction division enable */ | |
a945ce7e VP |
7360 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7361 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7362 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7363 | if (bestm2_frac) | |
7364 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7365 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7366 | |
de3a0fde VP |
7367 | /* Program digital lock detect threshold */ |
7368 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7369 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7370 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7371 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7372 | if (!bestm2_frac) | |
7373 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7374 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7375 | ||
9d556c99 | 7376 | /* Loop filter */ |
9cbe40c1 VP |
7377 | if (vco == 5400000) { |
7378 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7379 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7380 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7381 | tribuf_calcntr = 0x9; | |
7382 | } else if (vco <= 6200000) { | |
7383 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7384 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7385 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7386 | tribuf_calcntr = 0x9; | |
7387 | } else if (vco <= 6480000) { | |
7388 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7389 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7390 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7391 | tribuf_calcntr = 0x8; | |
7392 | } else { | |
7393 | /* Not supported. Apply the same limits as in the max case */ | |
7394 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7395 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7396 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7397 | tribuf_calcntr = 0; | |
7398 | } | |
9d556c99 CML |
7399 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7400 | ||
968040b2 | 7401 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7402 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7403 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7404 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7405 | ||
9d556c99 CML |
7406 | /* AFC Recal */ |
7407 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7408 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7409 | DPIO_AFC_RECAL); | |
7410 | ||
a580516d | 7411 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7412 | } |
7413 | ||
d288f65f VS |
7414 | /** |
7415 | * vlv_force_pll_on - forcibly enable just the PLL | |
7416 | * @dev_priv: i915 private structure | |
7417 | * @pipe: pipe PLL to enable | |
7418 | * @dpll: PLL configuration | |
7419 | * | |
7420 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7421 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7422 | * be enabled. | |
7423 | */ | |
3f36b937 TU |
7424 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7425 | const struct dpll *dpll) | |
d288f65f VS |
7426 | { |
7427 | struct intel_crtc *crtc = | |
7428 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7429 | struct intel_crtc_state *pipe_config; |
7430 | ||
7431 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7432 | if (!pipe_config) | |
7433 | return -ENOMEM; | |
7434 | ||
7435 | pipe_config->base.crtc = &crtc->base; | |
7436 | pipe_config->pixel_multiplier = 1; | |
7437 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7438 | |
7439 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7440 | chv_compute_dpll(crtc, pipe_config); |
7441 | chv_prepare_pll(crtc, pipe_config); | |
7442 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7443 | } else { |
3f36b937 TU |
7444 | vlv_compute_dpll(crtc, pipe_config); |
7445 | vlv_prepare_pll(crtc, pipe_config); | |
7446 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7447 | } |
3f36b937 TU |
7448 | |
7449 | kfree(pipe_config); | |
7450 | ||
7451 | return 0; | |
d288f65f VS |
7452 | } |
7453 | ||
7454 | /** | |
7455 | * vlv_force_pll_off - forcibly disable just the PLL | |
7456 | * @dev_priv: i915 private structure | |
7457 | * @pipe: pipe PLL to disable | |
7458 | * | |
7459 | * Disable the PLL for @pipe. To be used in cases where we need | |
7460 | * the PLL enabled even when @pipe is not going to be enabled. | |
7461 | */ | |
7462 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7463 | { | |
7464 | if (IS_CHERRYVIEW(dev)) | |
7465 | chv_disable_pll(to_i915(dev), pipe); | |
7466 | else | |
7467 | vlv_disable_pll(to_i915(dev), pipe); | |
7468 | } | |
7469 | ||
251ac862 DV |
7470 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7471 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7472 | struct dpll *reduced_clock) |
eb1cbe48 | 7473 | { |
f47709a9 | 7474 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7475 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7476 | u32 dpll; |
7477 | bool is_sdvo; | |
190f68c5 | 7478 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7479 | |
190f68c5 | 7480 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7481 | |
a93e255f ACO |
7482 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7483 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7484 | |
7485 | dpll = DPLL_VGA_MODE_DIS; | |
7486 | ||
a93e255f | 7487 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7488 | dpll |= DPLLB_MODE_LVDS; |
7489 | else | |
7490 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7491 | |
ef1b460d | 7492 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7493 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7494 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7495 | } |
198a037f DV |
7496 | |
7497 | if (is_sdvo) | |
4a33e48d | 7498 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7499 | |
190f68c5 | 7500 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7501 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7502 | |
7503 | /* compute bitmask from p1 value */ | |
7504 | if (IS_PINEVIEW(dev)) | |
7505 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7506 | else { | |
7507 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7508 | if (IS_G4X(dev) && reduced_clock) | |
7509 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7510 | } | |
7511 | switch (clock->p2) { | |
7512 | case 5: | |
7513 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7514 | break; | |
7515 | case 7: | |
7516 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7517 | break; | |
7518 | case 10: | |
7519 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7520 | break; | |
7521 | case 14: | |
7522 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7523 | break; | |
7524 | } | |
7525 | if (INTEL_INFO(dev)->gen >= 4) | |
7526 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7527 | ||
190f68c5 | 7528 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7529 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7530 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7531 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7532 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7533 | else | |
7534 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7535 | ||
7536 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7537 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7538 | |
eb1cbe48 | 7539 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7540 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7541 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7542 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7543 | } |
7544 | } | |
7545 | ||
251ac862 DV |
7546 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7547 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7548 | struct dpll *reduced_clock) |
eb1cbe48 | 7549 | { |
f47709a9 | 7550 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7551 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7552 | u32 dpll; |
190f68c5 | 7553 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7554 | |
190f68c5 | 7555 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7556 | |
eb1cbe48 DV |
7557 | dpll = DPLL_VGA_MODE_DIS; |
7558 | ||
a93e255f | 7559 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7560 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7561 | } else { | |
7562 | if (clock->p1 == 2) | |
7563 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7564 | else | |
7565 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7566 | if (clock->p2 == 4) | |
7567 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7568 | } | |
7569 | ||
a93e255f | 7570 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7571 | dpll |= DPLL_DVO_2X_MODE; |
7572 | ||
a93e255f | 7573 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7574 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7575 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7576 | else | |
7577 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7578 | ||
7579 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7580 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7581 | } |
7582 | ||
8a654f3b | 7583 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7584 | { |
7585 | struct drm_device *dev = intel_crtc->base.dev; | |
7586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7587 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7588 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7589 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7590 | uint32_t crtc_vtotal, crtc_vblank_end; |
7591 | int vsyncshift = 0; | |
4d8a62ea DV |
7592 | |
7593 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7594 | * the hw state checker will get angry at the mismatch. */ | |
7595 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7596 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7597 | |
609aeaca | 7598 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7599 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7600 | crtc_vtotal -= 1; |
7601 | crtc_vblank_end -= 1; | |
609aeaca | 7602 | |
409ee761 | 7603 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7604 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7605 | else | |
7606 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7607 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7608 | if (vsyncshift < 0) |
7609 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7610 | } |
7611 | ||
7612 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7613 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7614 | |
fe2b8f9d | 7615 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7616 | (adjusted_mode->crtc_hdisplay - 1) | |
7617 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7618 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7619 | (adjusted_mode->crtc_hblank_start - 1) | |
7620 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7621 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7622 | (adjusted_mode->crtc_hsync_start - 1) | |
7623 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7624 | ||
fe2b8f9d | 7625 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7626 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7627 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7628 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7629 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7630 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7631 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7632 | (adjusted_mode->crtc_vsync_start - 1) | |
7633 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7634 | ||
b5e508d4 PZ |
7635 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7636 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7637 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7638 | * bits. */ | |
7639 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7640 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7641 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7642 | ||
bc58be60 JN |
7643 | } |
7644 | ||
7645 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7646 | { | |
7647 | struct drm_device *dev = intel_crtc->base.dev; | |
7648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7649 | enum pipe pipe = intel_crtc->pipe; | |
7650 | ||
b0e77b9c PZ |
7651 | /* pipesrc controls the size that is scaled from, which should |
7652 | * always be the user's requested size. | |
7653 | */ | |
7654 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7655 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7656 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7657 | } |
7658 | ||
1bd1bd80 | 7659 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7660 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7661 | { |
7662 | struct drm_device *dev = crtc->base.dev; | |
7663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7664 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7665 | uint32_t tmp; | |
7666 | ||
7667 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7668 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7669 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7670 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7671 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7672 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7673 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7674 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7675 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7676 | |
7677 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7678 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7679 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7680 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7681 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7682 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7683 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7684 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7685 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7686 | |
7687 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7688 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7689 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7690 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7691 | } |
bc58be60 JN |
7692 | } |
7693 | ||
7694 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7695 | struct intel_crtc_state *pipe_config) | |
7696 | { | |
7697 | struct drm_device *dev = crtc->base.dev; | |
7698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7699 | u32 tmp; | |
1bd1bd80 DV |
7700 | |
7701 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7702 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7703 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7704 | ||
2d112de7 ACO |
7705 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7706 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7707 | } |
7708 | ||
f6a83288 | 7709 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7710 | struct intel_crtc_state *pipe_config) |
babea61d | 7711 | { |
2d112de7 ACO |
7712 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7713 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7714 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7715 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7716 | |
2d112de7 ACO |
7717 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7718 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7719 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7720 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7721 | |
2d112de7 | 7722 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7723 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7724 | |
2d112de7 ACO |
7725 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7726 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7727 | |
7728 | mode->hsync = drm_mode_hsync(mode); | |
7729 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7730 | drm_mode_set_name(mode); | |
babea61d JB |
7731 | } |
7732 | ||
84b046f3 DV |
7733 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7734 | { | |
7735 | struct drm_device *dev = intel_crtc->base.dev; | |
7736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7737 | uint32_t pipeconf; | |
7738 | ||
9f11a9e4 | 7739 | pipeconf = 0; |
84b046f3 | 7740 | |
b6b5d049 VS |
7741 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7742 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7743 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7744 | |
6e3c9717 | 7745 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7746 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7747 | |
ff9ce46e | 7748 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7749 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7750 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7751 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7752 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7753 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7754 | |
6e3c9717 | 7755 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7756 | case 18: |
7757 | pipeconf |= PIPECONF_6BPC; | |
7758 | break; | |
7759 | case 24: | |
7760 | pipeconf |= PIPECONF_8BPC; | |
7761 | break; | |
7762 | case 30: | |
7763 | pipeconf |= PIPECONF_10BPC; | |
7764 | break; | |
7765 | default: | |
7766 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7767 | BUG(); | |
84b046f3 DV |
7768 | } |
7769 | } | |
7770 | ||
7771 | if (HAS_PIPE_CXSR(dev)) { | |
7772 | if (intel_crtc->lowfreq_avail) { | |
7773 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7774 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7775 | } else { | |
7776 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7777 | } |
7778 | } | |
7779 | ||
6e3c9717 | 7780 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7781 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7782 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7783 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7784 | else | |
7785 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7786 | } else | |
84b046f3 DV |
7787 | pipeconf |= PIPECONF_PROGRESSIVE; |
7788 | ||
666a4537 WB |
7789 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7790 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7791 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7792 | |
84b046f3 DV |
7793 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7794 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7795 | } | |
7796 | ||
81c97f52 ACO |
7797 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7798 | struct intel_crtc_state *crtc_state) | |
7799 | { | |
7800 | struct drm_device *dev = crtc->base.dev; | |
7801 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 7802 | const struct intel_limit *limit; |
81c97f52 ACO |
7803 | int refclk = 48000; |
7804 | ||
7805 | memset(&crtc_state->dpll_hw_state, 0, | |
7806 | sizeof(crtc_state->dpll_hw_state)); | |
7807 | ||
7808 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7809 | if (intel_panel_use_ssc(dev_priv)) { | |
7810 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7811 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7812 | } | |
7813 | ||
7814 | limit = &intel_limits_i8xx_lvds; | |
7815 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) { | |
7816 | limit = &intel_limits_i8xx_dvo; | |
7817 | } else { | |
7818 | limit = &intel_limits_i8xx_dac; | |
7819 | } | |
7820 | ||
7821 | if (!crtc_state->clock_set && | |
7822 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7823 | refclk, NULL, &crtc_state->dpll)) { | |
7824 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7825 | return -EINVAL; | |
7826 | } | |
7827 | ||
7828 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7829 | ||
7830 | return 0; | |
7831 | } | |
7832 | ||
19ec6693 ACO |
7833 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7834 | struct intel_crtc_state *crtc_state) | |
7835 | { | |
7836 | struct drm_device *dev = crtc->base.dev; | |
7837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 7838 | const struct intel_limit *limit; |
19ec6693 ACO |
7839 | int refclk = 96000; |
7840 | ||
7841 | memset(&crtc_state->dpll_hw_state, 0, | |
7842 | sizeof(crtc_state->dpll_hw_state)); | |
7843 | ||
7844 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7845 | if (intel_panel_use_ssc(dev_priv)) { | |
7846 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7847 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7848 | } | |
7849 | ||
7850 | if (intel_is_dual_link_lvds(dev)) | |
7851 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7852 | else | |
7853 | limit = &intel_limits_g4x_single_channel_lvds; | |
7854 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || | |
7855 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
7856 | limit = &intel_limits_g4x_hdmi; | |
7857 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { | |
7858 | limit = &intel_limits_g4x_sdvo; | |
7859 | } else { | |
7860 | /* The option is for other outputs */ | |
7861 | limit = &intel_limits_i9xx_sdvo; | |
7862 | } | |
7863 | ||
7864 | if (!crtc_state->clock_set && | |
7865 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7866 | refclk, NULL, &crtc_state->dpll)) { | |
7867 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7868 | return -EINVAL; | |
7869 | } | |
7870 | ||
7871 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7872 | ||
7873 | return 0; | |
7874 | } | |
7875 | ||
70e8aa21 ACO |
7876 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7877 | struct intel_crtc_state *crtc_state) | |
7878 | { | |
7879 | struct drm_device *dev = crtc->base.dev; | |
7880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 7881 | const struct intel_limit *limit; |
70e8aa21 ACO |
7882 | int refclk = 96000; |
7883 | ||
7884 | memset(&crtc_state->dpll_hw_state, 0, | |
7885 | sizeof(crtc_state->dpll_hw_state)); | |
7886 | ||
7887 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7888 | if (intel_panel_use_ssc(dev_priv)) { | |
7889 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7890 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7891 | } | |
7892 | ||
7893 | limit = &intel_limits_pineview_lvds; | |
7894 | } else { | |
7895 | limit = &intel_limits_pineview_sdvo; | |
7896 | } | |
7897 | ||
7898 | if (!crtc_state->clock_set && | |
7899 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7900 | refclk, NULL, &crtc_state->dpll)) { | |
7901 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7902 | return -EINVAL; | |
7903 | } | |
7904 | ||
7905 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7906 | ||
7907 | return 0; | |
7908 | } | |
7909 | ||
190f68c5 ACO |
7910 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7911 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7912 | { |
c7653199 | 7913 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7914 | struct drm_i915_private *dev_priv = dev->dev_private; |
1b6f4958 | 7915 | const struct intel_limit *limit; |
81c97f52 | 7916 | int refclk = 96000; |
79e53945 | 7917 | |
dd3cd74a ACO |
7918 | memset(&crtc_state->dpll_hw_state, 0, |
7919 | sizeof(crtc_state->dpll_hw_state)); | |
7920 | ||
70e8aa21 ACO |
7921 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
7922 | if (intel_panel_use_ssc(dev_priv)) { | |
7923 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7924 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7925 | } | |
43565a06 | 7926 | |
70e8aa21 ACO |
7927 | limit = &intel_limits_i9xx_lvds; |
7928 | } else { | |
7929 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7930 | } |
79e53945 | 7931 | |
70e8aa21 ACO |
7932 | if (!crtc_state->clock_set && |
7933 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7934 | refclk, NULL, &crtc_state->dpll)) { | |
7935 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7936 | return -EINVAL; | |
f47709a9 | 7937 | } |
7026d4ac | 7938 | |
81c97f52 | 7939 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7940 | |
c8f7a0db | 7941 | return 0; |
f564048e EA |
7942 | } |
7943 | ||
65b3d6a9 ACO |
7944 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7945 | struct intel_crtc_state *crtc_state) | |
7946 | { | |
7947 | int refclk = 100000; | |
1b6f4958 | 7948 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7949 | |
7950 | memset(&crtc_state->dpll_hw_state, 0, | |
7951 | sizeof(crtc_state->dpll_hw_state)); | |
7952 | ||
65b3d6a9 ACO |
7953 | if (!crtc_state->clock_set && |
7954 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7955 | refclk, NULL, &crtc_state->dpll)) { | |
7956 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7957 | return -EINVAL; | |
7958 | } | |
7959 | ||
7960 | chv_compute_dpll(crtc, crtc_state); | |
7961 | ||
7962 | return 0; | |
7963 | } | |
7964 | ||
7965 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7966 | struct intel_crtc_state *crtc_state) | |
7967 | { | |
7968 | int refclk = 100000; | |
1b6f4958 | 7969 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7970 | |
7971 | memset(&crtc_state->dpll_hw_state, 0, | |
7972 | sizeof(crtc_state->dpll_hw_state)); | |
7973 | ||
65b3d6a9 ACO |
7974 | if (!crtc_state->clock_set && |
7975 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7976 | refclk, NULL, &crtc_state->dpll)) { | |
7977 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7978 | return -EINVAL; | |
7979 | } | |
7980 | ||
7981 | vlv_compute_dpll(crtc, crtc_state); | |
7982 | ||
7983 | return 0; | |
7984 | } | |
7985 | ||
2fa2fe9a | 7986 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7987 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7988 | { |
7989 | struct drm_device *dev = crtc->base.dev; | |
7990 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7991 | uint32_t tmp; | |
7992 | ||
dc9e7dec VS |
7993 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7994 | return; | |
7995 | ||
2fa2fe9a | 7996 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7997 | if (!(tmp & PFIT_ENABLE)) |
7998 | return; | |
2fa2fe9a | 7999 | |
06922821 | 8000 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8001 | if (INTEL_INFO(dev)->gen < 4) { |
8002 | if (crtc->pipe != PIPE_B) | |
8003 | return; | |
2fa2fe9a DV |
8004 | } else { |
8005 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8006 | return; | |
8007 | } | |
8008 | ||
06922821 | 8009 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8010 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8011 | } |
8012 | ||
acbec814 | 8013 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8014 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8015 | { |
8016 | struct drm_device *dev = crtc->base.dev; | |
8017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8018 | int pipe = pipe_config->cpu_transcoder; | |
9e2c8475 | 8019 | struct dpll clock; |
acbec814 | 8020 | u32 mdiv; |
662c6ecb | 8021 | int refclk = 100000; |
acbec814 | 8022 | |
b521973b VS |
8023 | /* In case of DSI, DPLL will not be used */ |
8024 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8025 | return; |
8026 | ||
a580516d | 8027 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8028 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8029 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8030 | |
8031 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8032 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8033 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8034 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8035 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8036 | ||
dccbea3b | 8037 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8038 | } |
8039 | ||
5724dbd1 DL |
8040 | static void |
8041 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8042 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8043 | { |
8044 | struct drm_device *dev = crtc->base.dev; | |
8045 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8046 | u32 val, base, offset; | |
8047 | int pipe = crtc->pipe, plane = crtc->plane; | |
8048 | int fourcc, pixel_format; | |
6761dd31 | 8049 | unsigned int aligned_height; |
b113d5ee | 8050 | struct drm_framebuffer *fb; |
1b842c89 | 8051 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8052 | |
42a7b088 DL |
8053 | val = I915_READ(DSPCNTR(plane)); |
8054 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8055 | return; | |
8056 | ||
d9806c9f | 8057 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8058 | if (!intel_fb) { |
1ad292b5 JB |
8059 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8060 | return; | |
8061 | } | |
8062 | ||
1b842c89 DL |
8063 | fb = &intel_fb->base; |
8064 | ||
18c5247e DV |
8065 | if (INTEL_INFO(dev)->gen >= 4) { |
8066 | if (val & DISPPLANE_TILED) { | |
49af449b | 8067 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8068 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8069 | } | |
8070 | } | |
1ad292b5 JB |
8071 | |
8072 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8073 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8074 | fb->pixel_format = fourcc; |
8075 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8076 | |
8077 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8078 | if (plane_config->tiling) |
1ad292b5 JB |
8079 | offset = I915_READ(DSPTILEOFF(plane)); |
8080 | else | |
8081 | offset = I915_READ(DSPLINOFF(plane)); | |
8082 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8083 | } else { | |
8084 | base = I915_READ(DSPADDR(plane)); | |
8085 | } | |
8086 | plane_config->base = base; | |
8087 | ||
8088 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8089 | fb->width = ((val >> 16) & 0xfff) + 1; |
8090 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8091 | |
8092 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8093 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8094 | |
b113d5ee | 8095 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8096 | fb->pixel_format, |
8097 | fb->modifier[0]); | |
1ad292b5 | 8098 | |
f37b5c2b | 8099 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8100 | |
2844a921 DL |
8101 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8102 | pipe_name(pipe), plane, fb->width, fb->height, | |
8103 | fb->bits_per_pixel, base, fb->pitches[0], | |
8104 | plane_config->size); | |
1ad292b5 | 8105 | |
2d14030b | 8106 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8107 | } |
8108 | ||
70b23a98 | 8109 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8110 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8111 | { |
8112 | struct drm_device *dev = crtc->base.dev; | |
8113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8114 | int pipe = pipe_config->cpu_transcoder; | |
8115 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8116 | struct dpll clock; |
0d7b6b11 | 8117 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8118 | int refclk = 100000; |
8119 | ||
b521973b VS |
8120 | /* In case of DSI, DPLL will not be used */ |
8121 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8122 | return; | |
8123 | ||
a580516d | 8124 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8125 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8126 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8127 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8128 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8129 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8130 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8131 | |
8132 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8133 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8134 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8135 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8136 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8137 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8138 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8139 | ||
dccbea3b | 8140 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8141 | } |
8142 | ||
0e8ffe1b | 8143 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8144 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8145 | { |
8146 | struct drm_device *dev = crtc->base.dev; | |
8147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8148 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8149 | uint32_t tmp; |
1729050e | 8150 | bool ret; |
0e8ffe1b | 8151 | |
1729050e ID |
8152 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8153 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8154 | return false; |
8155 | ||
e143a21c | 8156 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8157 | pipe_config->shared_dpll = NULL; |
eccb140b | 8158 | |
1729050e ID |
8159 | ret = false; |
8160 | ||
0e8ffe1b DV |
8161 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8162 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8163 | goto out; |
0e8ffe1b | 8164 | |
666a4537 | 8165 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8166 | switch (tmp & PIPECONF_BPC_MASK) { |
8167 | case PIPECONF_6BPC: | |
8168 | pipe_config->pipe_bpp = 18; | |
8169 | break; | |
8170 | case PIPECONF_8BPC: | |
8171 | pipe_config->pipe_bpp = 24; | |
8172 | break; | |
8173 | case PIPECONF_10BPC: | |
8174 | pipe_config->pipe_bpp = 30; | |
8175 | break; | |
8176 | default: | |
8177 | break; | |
8178 | } | |
8179 | } | |
8180 | ||
666a4537 WB |
8181 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8182 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8183 | pipe_config->limited_color_range = true; |
8184 | ||
282740f7 VS |
8185 | if (INTEL_INFO(dev)->gen < 4) |
8186 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8187 | ||
1bd1bd80 | 8188 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8189 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8190 | |
2fa2fe9a DV |
8191 | i9xx_get_pfit_config(crtc, pipe_config); |
8192 | ||
6c49f241 | 8193 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c VS |
8194 | /* No way to read it out on pipes B and C */ |
8195 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8196 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8197 | else | |
8198 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8199 | pipe_config->pixel_multiplier = |
8200 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8201 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8202 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8203 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8204 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8205 | pipe_config->pixel_multiplier = | |
8206 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8207 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8208 | } else { | |
8209 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8210 | * port and will be fixed up in the encoder->get_config | |
8211 | * function. */ | |
8212 | pipe_config->pixel_multiplier = 1; | |
8213 | } | |
8bcc2795 | 8214 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8215 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8216 | /* |
8217 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8218 | * on 830. Filter it out here so that we don't | |
8219 | * report errors due to that. | |
8220 | */ | |
8221 | if (IS_I830(dev)) | |
8222 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8223 | ||
8bcc2795 DV |
8224 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8225 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8226 | } else { |
8227 | /* Mask out read-only status bits. */ | |
8228 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8229 | DPLL_PORTC_READY_MASK | | |
8230 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8231 | } |
6c49f241 | 8232 | |
70b23a98 VS |
8233 | if (IS_CHERRYVIEW(dev)) |
8234 | chv_crtc_clock_get(crtc, pipe_config); | |
8235 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8236 | vlv_crtc_clock_get(crtc, pipe_config); |
8237 | else | |
8238 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8239 | |
0f64614d VS |
8240 | /* |
8241 | * Normally the dotclock is filled in by the encoder .get_config() | |
8242 | * but in case the pipe is enabled w/o any ports we need a sane | |
8243 | * default. | |
8244 | */ | |
8245 | pipe_config->base.adjusted_mode.crtc_clock = | |
8246 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8247 | ||
1729050e ID |
8248 | ret = true; |
8249 | ||
8250 | out: | |
8251 | intel_display_power_put(dev_priv, power_domain); | |
8252 | ||
8253 | return ret; | |
0e8ffe1b DV |
8254 | } |
8255 | ||
dde86e2d | 8256 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8257 | { |
8258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8259 | struct intel_encoder *encoder; |
74cfd7ac | 8260 | u32 val, final; |
13d83a67 | 8261 | bool has_lvds = false; |
199e5d79 | 8262 | bool has_cpu_edp = false; |
199e5d79 | 8263 | bool has_panel = false; |
99eb6a01 KP |
8264 | bool has_ck505 = false; |
8265 | bool can_ssc = false; | |
13d83a67 JB |
8266 | |
8267 | /* We need to take the global config into account */ | |
b2784e15 | 8268 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8269 | switch (encoder->type) { |
8270 | case INTEL_OUTPUT_LVDS: | |
8271 | has_panel = true; | |
8272 | has_lvds = true; | |
8273 | break; | |
8274 | case INTEL_OUTPUT_EDP: | |
8275 | has_panel = true; | |
2de6905f | 8276 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8277 | has_cpu_edp = true; |
8278 | break; | |
6847d71b PZ |
8279 | default: |
8280 | break; | |
13d83a67 JB |
8281 | } |
8282 | } | |
8283 | ||
99eb6a01 | 8284 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8285 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8286 | can_ssc = has_ck505; |
8287 | } else { | |
8288 | has_ck505 = false; | |
8289 | can_ssc = true; | |
8290 | } | |
8291 | ||
2de6905f ID |
8292 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8293 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8294 | |
8295 | /* Ironlake: try to setup display ref clock before DPLL | |
8296 | * enabling. This is only under driver's control after | |
8297 | * PCH B stepping, previous chipset stepping should be | |
8298 | * ignoring this setting. | |
8299 | */ | |
74cfd7ac CW |
8300 | val = I915_READ(PCH_DREF_CONTROL); |
8301 | ||
8302 | /* As we must carefully and slowly disable/enable each source in turn, | |
8303 | * compute the final state we want first and check if we need to | |
8304 | * make any changes at all. | |
8305 | */ | |
8306 | final = val; | |
8307 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8308 | if (has_ck505) | |
8309 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8310 | else | |
8311 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8312 | ||
8313 | final &= ~DREF_SSC_SOURCE_MASK; | |
8314 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8315 | final &= ~DREF_SSC1_ENABLE; | |
8316 | ||
8317 | if (has_panel) { | |
8318 | final |= DREF_SSC_SOURCE_ENABLE; | |
8319 | ||
8320 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8321 | final |= DREF_SSC1_ENABLE; | |
8322 | ||
8323 | if (has_cpu_edp) { | |
8324 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8325 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8326 | else | |
8327 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8328 | } else | |
8329 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8330 | } else { | |
8331 | final |= DREF_SSC_SOURCE_DISABLE; | |
8332 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8333 | } | |
8334 | ||
8335 | if (final == val) | |
8336 | return; | |
8337 | ||
13d83a67 | 8338 | /* Always enable nonspread source */ |
74cfd7ac | 8339 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8340 | |
99eb6a01 | 8341 | if (has_ck505) |
74cfd7ac | 8342 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8343 | else |
74cfd7ac | 8344 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8345 | |
199e5d79 | 8346 | if (has_panel) { |
74cfd7ac CW |
8347 | val &= ~DREF_SSC_SOURCE_MASK; |
8348 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8349 | |
199e5d79 | 8350 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8351 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8352 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8353 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8354 | } else |
74cfd7ac | 8355 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8356 | |
8357 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8358 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8359 | POSTING_READ(PCH_DREF_CONTROL); |
8360 | udelay(200); | |
8361 | ||
74cfd7ac | 8362 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8363 | |
8364 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8365 | if (has_cpu_edp) { |
99eb6a01 | 8366 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8367 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8368 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8369 | } else |
74cfd7ac | 8370 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8371 | } else |
74cfd7ac | 8372 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8373 | |
74cfd7ac | 8374 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8375 | POSTING_READ(PCH_DREF_CONTROL); |
8376 | udelay(200); | |
8377 | } else { | |
8378 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8379 | ||
74cfd7ac | 8380 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8381 | |
8382 | /* Turn off CPU output */ | |
74cfd7ac | 8383 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8384 | |
74cfd7ac | 8385 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8386 | POSTING_READ(PCH_DREF_CONTROL); |
8387 | udelay(200); | |
8388 | ||
8389 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8390 | val &= ~DREF_SSC_SOURCE_MASK; |
8391 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8392 | |
8393 | /* Turn off SSC1 */ | |
74cfd7ac | 8394 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8395 | |
74cfd7ac | 8396 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8397 | POSTING_READ(PCH_DREF_CONTROL); |
8398 | udelay(200); | |
8399 | } | |
74cfd7ac CW |
8400 | |
8401 | BUG_ON(val != final); | |
13d83a67 JB |
8402 | } |
8403 | ||
f31f2d55 | 8404 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8405 | { |
f31f2d55 | 8406 | uint32_t tmp; |
dde86e2d | 8407 | |
0ff066a9 PZ |
8408 | tmp = I915_READ(SOUTH_CHICKEN2); |
8409 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8410 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8411 | |
0ff066a9 PZ |
8412 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8413 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8414 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8415 | |
0ff066a9 PZ |
8416 | tmp = I915_READ(SOUTH_CHICKEN2); |
8417 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8418 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8419 | |
0ff066a9 PZ |
8420 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8421 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8422 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8423 | } |
8424 | ||
8425 | /* WaMPhyProgramming:hsw */ | |
8426 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8427 | { | |
8428 | uint32_t tmp; | |
dde86e2d PZ |
8429 | |
8430 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8431 | tmp &= ~(0xFF << 24); | |
8432 | tmp |= (0x12 << 24); | |
8433 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8434 | ||
dde86e2d PZ |
8435 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8436 | tmp |= (1 << 11); | |
8437 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8438 | ||
8439 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8440 | tmp |= (1 << 11); | |
8441 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8442 | ||
dde86e2d PZ |
8443 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8444 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8445 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8446 | ||
8447 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8448 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8449 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8450 | ||
0ff066a9 PZ |
8451 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8452 | tmp &= ~(7 << 13); | |
8453 | tmp |= (5 << 13); | |
8454 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8455 | |
0ff066a9 PZ |
8456 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8457 | tmp &= ~(7 << 13); | |
8458 | tmp |= (5 << 13); | |
8459 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8460 | |
8461 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8462 | tmp &= ~0xFF; | |
8463 | tmp |= 0x1C; | |
8464 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8465 | ||
8466 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8467 | tmp &= ~0xFF; | |
8468 | tmp |= 0x1C; | |
8469 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8470 | ||
8471 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8472 | tmp &= ~(0xFF << 16); | |
8473 | tmp |= (0x1C << 16); | |
8474 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8475 | ||
8476 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8477 | tmp &= ~(0xFF << 16); | |
8478 | tmp |= (0x1C << 16); | |
8479 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8480 | ||
0ff066a9 PZ |
8481 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8482 | tmp |= (1 << 27); | |
8483 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8484 | |
0ff066a9 PZ |
8485 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8486 | tmp |= (1 << 27); | |
8487 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8488 | |
0ff066a9 PZ |
8489 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8490 | tmp &= ~(0xF << 28); | |
8491 | tmp |= (4 << 28); | |
8492 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8493 | |
0ff066a9 PZ |
8494 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8495 | tmp &= ~(0xF << 28); | |
8496 | tmp |= (4 << 28); | |
8497 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8498 | } |
8499 | ||
2fa86a1f PZ |
8500 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8501 | * Programming" based on the parameters passed: | |
8502 | * - Sequence to enable CLKOUT_DP | |
8503 | * - Sequence to enable CLKOUT_DP without spread | |
8504 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8505 | */ | |
8506 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8507 | bool with_fdi) | |
f31f2d55 PZ |
8508 | { |
8509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8510 | uint32_t reg, tmp; |
8511 | ||
8512 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8513 | with_spread = true; | |
c2699524 | 8514 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8515 | with_fdi = false; |
f31f2d55 | 8516 | |
a580516d | 8517 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8518 | |
8519 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8520 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8521 | tmp |= SBI_SSCCTL_PATHALT; | |
8522 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8523 | ||
8524 | udelay(24); | |
8525 | ||
2fa86a1f PZ |
8526 | if (with_spread) { |
8527 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8528 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8529 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8530 | |
2fa86a1f PZ |
8531 | if (with_fdi) { |
8532 | lpt_reset_fdi_mphy(dev_priv); | |
8533 | lpt_program_fdi_mphy(dev_priv); | |
8534 | } | |
8535 | } | |
dde86e2d | 8536 | |
c2699524 | 8537 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8538 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8539 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8540 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8541 | |
a580516d | 8542 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8543 | } |
8544 | ||
47701c3b PZ |
8545 | /* Sequence to disable CLKOUT_DP */ |
8546 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8547 | { | |
8548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8549 | uint32_t reg, tmp; | |
8550 | ||
a580516d | 8551 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8552 | |
c2699524 | 8553 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8554 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8555 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8556 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8557 | ||
8558 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8559 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8560 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8561 | tmp |= SBI_SSCCTL_PATHALT; | |
8562 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8563 | udelay(32); | |
8564 | } | |
8565 | tmp |= SBI_SSCCTL_DISABLE; | |
8566 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8567 | } | |
8568 | ||
a580516d | 8569 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8570 | } |
8571 | ||
f7be2c21 VS |
8572 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8573 | ||
8574 | static const uint16_t sscdivintphase[] = { | |
8575 | [BEND_IDX( 50)] = 0x3B23, | |
8576 | [BEND_IDX( 45)] = 0x3B23, | |
8577 | [BEND_IDX( 40)] = 0x3C23, | |
8578 | [BEND_IDX( 35)] = 0x3C23, | |
8579 | [BEND_IDX( 30)] = 0x3D23, | |
8580 | [BEND_IDX( 25)] = 0x3D23, | |
8581 | [BEND_IDX( 20)] = 0x3E23, | |
8582 | [BEND_IDX( 15)] = 0x3E23, | |
8583 | [BEND_IDX( 10)] = 0x3F23, | |
8584 | [BEND_IDX( 5)] = 0x3F23, | |
8585 | [BEND_IDX( 0)] = 0x0025, | |
8586 | [BEND_IDX( -5)] = 0x0025, | |
8587 | [BEND_IDX(-10)] = 0x0125, | |
8588 | [BEND_IDX(-15)] = 0x0125, | |
8589 | [BEND_IDX(-20)] = 0x0225, | |
8590 | [BEND_IDX(-25)] = 0x0225, | |
8591 | [BEND_IDX(-30)] = 0x0325, | |
8592 | [BEND_IDX(-35)] = 0x0325, | |
8593 | [BEND_IDX(-40)] = 0x0425, | |
8594 | [BEND_IDX(-45)] = 0x0425, | |
8595 | [BEND_IDX(-50)] = 0x0525, | |
8596 | }; | |
8597 | ||
8598 | /* | |
8599 | * Bend CLKOUT_DP | |
8600 | * steps -50 to 50 inclusive, in steps of 5 | |
8601 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8602 | * change in clock period = -(steps / 10) * 5.787 ps | |
8603 | */ | |
8604 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8605 | { | |
8606 | uint32_t tmp; | |
8607 | int idx = BEND_IDX(steps); | |
8608 | ||
8609 | if (WARN_ON(steps % 5 != 0)) | |
8610 | return; | |
8611 | ||
8612 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8613 | return; | |
8614 | ||
8615 | mutex_lock(&dev_priv->sb_lock); | |
8616 | ||
8617 | if (steps % 10 != 0) | |
8618 | tmp = 0xAAAAAAAB; | |
8619 | else | |
8620 | tmp = 0x00000000; | |
8621 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8622 | ||
8623 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8624 | tmp &= 0xffff0000; | |
8625 | tmp |= sscdivintphase[idx]; | |
8626 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8627 | ||
8628 | mutex_unlock(&dev_priv->sb_lock); | |
8629 | } | |
8630 | ||
8631 | #undef BEND_IDX | |
8632 | ||
bf8fa3d3 PZ |
8633 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8634 | { | |
bf8fa3d3 PZ |
8635 | struct intel_encoder *encoder; |
8636 | bool has_vga = false; | |
8637 | ||
b2784e15 | 8638 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8639 | switch (encoder->type) { |
8640 | case INTEL_OUTPUT_ANALOG: | |
8641 | has_vga = true; | |
8642 | break; | |
6847d71b PZ |
8643 | default: |
8644 | break; | |
bf8fa3d3 PZ |
8645 | } |
8646 | } | |
8647 | ||
f7be2c21 VS |
8648 | if (has_vga) { |
8649 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8650 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8651 | } else { |
47701c3b | 8652 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8653 | } |
bf8fa3d3 PZ |
8654 | } |
8655 | ||
dde86e2d PZ |
8656 | /* |
8657 | * Initialize reference clocks when the driver loads | |
8658 | */ | |
8659 | void intel_init_pch_refclk(struct drm_device *dev) | |
8660 | { | |
8661 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8662 | ironlake_init_pch_refclk(dev); | |
8663 | else if (HAS_PCH_LPT(dev)) | |
8664 | lpt_init_pch_refclk(dev); | |
8665 | } | |
8666 | ||
6ff93609 | 8667 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8668 | { |
c8203565 | 8669 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8670 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8671 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8672 | uint32_t val; |
8673 | ||
78114071 | 8674 | val = 0; |
c8203565 | 8675 | |
6e3c9717 | 8676 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8677 | case 18: |
dfd07d72 | 8678 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8679 | break; |
8680 | case 24: | |
dfd07d72 | 8681 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8682 | break; |
8683 | case 30: | |
dfd07d72 | 8684 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8685 | break; |
8686 | case 36: | |
dfd07d72 | 8687 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8688 | break; |
8689 | default: | |
cc769b62 PZ |
8690 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8691 | BUG(); | |
c8203565 PZ |
8692 | } |
8693 | ||
6e3c9717 | 8694 | if (intel_crtc->config->dither) |
c8203565 PZ |
8695 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8696 | ||
6e3c9717 | 8697 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8698 | val |= PIPECONF_INTERLACED_ILK; |
8699 | else | |
8700 | val |= PIPECONF_PROGRESSIVE; | |
8701 | ||
6e3c9717 | 8702 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8703 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8704 | |
c8203565 PZ |
8705 | I915_WRITE(PIPECONF(pipe), val); |
8706 | POSTING_READ(PIPECONF(pipe)); | |
8707 | } | |
8708 | ||
6ff93609 | 8709 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8710 | { |
391bf048 | 8711 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
ee2b0b38 | 8712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8713 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8714 | u32 val = 0; |
ee2b0b38 | 8715 | |
391bf048 | 8716 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8717 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8718 | ||
6e3c9717 | 8719 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8720 | val |= PIPECONF_INTERLACED_ILK; |
8721 | else | |
8722 | val |= PIPECONF_PROGRESSIVE; | |
8723 | ||
702e7a56 PZ |
8724 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8725 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8726 | } |
8727 | ||
391bf048 JN |
8728 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8729 | { | |
8730 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
8731 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
756f85cf | 8732 | |
391bf048 JN |
8733 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8734 | u32 val = 0; | |
756f85cf | 8735 | |
6e3c9717 | 8736 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8737 | case 18: |
8738 | val |= PIPEMISC_DITHER_6_BPC; | |
8739 | break; | |
8740 | case 24: | |
8741 | val |= PIPEMISC_DITHER_8_BPC; | |
8742 | break; | |
8743 | case 30: | |
8744 | val |= PIPEMISC_DITHER_10_BPC; | |
8745 | break; | |
8746 | case 36: | |
8747 | val |= PIPEMISC_DITHER_12_BPC; | |
8748 | break; | |
8749 | default: | |
8750 | /* Case prevented by pipe_config_set_bpp. */ | |
8751 | BUG(); | |
8752 | } | |
8753 | ||
6e3c9717 | 8754 | if (intel_crtc->config->dither) |
756f85cf PZ |
8755 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8756 | ||
391bf048 | 8757 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8758 | } |
ee2b0b38 PZ |
8759 | } |
8760 | ||
d4b1931c PZ |
8761 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8762 | { | |
8763 | /* | |
8764 | * Account for spread spectrum to avoid | |
8765 | * oversubscribing the link. Max center spread | |
8766 | * is 2.5%; use 5% for safety's sake. | |
8767 | */ | |
8768 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8769 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8770 | } |
8771 | ||
7429e9d4 | 8772 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8773 | { |
7429e9d4 | 8774 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8775 | } |
8776 | ||
b75ca6f6 ACO |
8777 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8778 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8779 | struct dpll *reduced_clock) |
79e53945 | 8780 | { |
de13a2e3 | 8781 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8782 | struct drm_device *dev = crtc->dev; |
8783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8784 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8785 | struct drm_connector *connector; |
55bb9992 ACO |
8786 | struct drm_connector_state *connector_state; |
8787 | struct intel_encoder *encoder; | |
b75ca6f6 | 8788 | u32 dpll, fp, fp2; |
ceb41007 | 8789 | int factor, i; |
09ede541 | 8790 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8791 | |
da3ced29 | 8792 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8793 | if (connector_state->crtc != crtc_state->base.crtc) |
8794 | continue; | |
8795 | ||
8796 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8797 | ||
8798 | switch (encoder->type) { | |
79e53945 JB |
8799 | case INTEL_OUTPUT_LVDS: |
8800 | is_lvds = true; | |
8801 | break; | |
8802 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8803 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8804 | is_sdvo = true; |
79e53945 | 8805 | break; |
6847d71b PZ |
8806 | default: |
8807 | break; | |
79e53945 JB |
8808 | } |
8809 | } | |
79e53945 | 8810 | |
c1858123 | 8811 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8812 | factor = 21; |
8813 | if (is_lvds) { | |
8814 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8815 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8816 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8817 | factor = 25; |
190f68c5 | 8818 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8819 | factor = 20; |
c1858123 | 8820 | |
b75ca6f6 ACO |
8821 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8822 | ||
190f68c5 | 8823 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8824 | fp |= FP_CB_TUNE; |
8825 | ||
8826 | if (reduced_clock) { | |
8827 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8828 | |
b75ca6f6 ACO |
8829 | if (reduced_clock->m < factor * reduced_clock->n) |
8830 | fp2 |= FP_CB_TUNE; | |
8831 | } else { | |
8832 | fp2 = fp; | |
8833 | } | |
9a7c7890 | 8834 | |
5eddb70b | 8835 | dpll = 0; |
2c07245f | 8836 | |
a07d6787 EA |
8837 | if (is_lvds) |
8838 | dpll |= DPLLB_MODE_LVDS; | |
8839 | else | |
8840 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8841 | |
190f68c5 | 8842 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8843 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8844 | |
8845 | if (is_sdvo) | |
4a33e48d | 8846 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8847 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8848 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8849 | |
a07d6787 | 8850 | /* compute bitmask from p1 value */ |
190f68c5 | 8851 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8852 | /* also FPA1 */ |
190f68c5 | 8853 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8854 | |
190f68c5 | 8855 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8856 | case 5: |
8857 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8858 | break; | |
8859 | case 7: | |
8860 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8861 | break; | |
8862 | case 10: | |
8863 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8864 | break; | |
8865 | case 14: | |
8866 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8867 | break; | |
79e53945 JB |
8868 | } |
8869 | ||
ceb41007 | 8870 | if (is_lvds && intel_panel_use_ssc(dev_priv)) |
43565a06 | 8871 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8872 | else |
8873 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8874 | ||
b75ca6f6 ACO |
8875 | dpll |= DPLL_VCO_ENABLE; |
8876 | ||
8877 | crtc_state->dpll_hw_state.dpll = dpll; | |
8878 | crtc_state->dpll_hw_state.fp0 = fp; | |
8879 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8880 | } |
8881 | ||
190f68c5 ACO |
8882 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8883 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8884 | { |
997c030c ACO |
8885 | struct drm_device *dev = crtc->base.dev; |
8886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9e2c8475 | 8887 | struct dpll reduced_clock; |
7ed9f894 | 8888 | bool has_reduced_clock = false; |
e2b78267 | 8889 | struct intel_shared_dpll *pll; |
1b6f4958 | 8890 | const struct intel_limit *limit; |
997c030c | 8891 | int refclk = 120000; |
de13a2e3 | 8892 | |
dd3cd74a ACO |
8893 | memset(&crtc_state->dpll_hw_state, 0, |
8894 | sizeof(crtc_state->dpll_hw_state)); | |
8895 | ||
ded220e2 ACO |
8896 | crtc->lowfreq_avail = false; |
8897 | ||
8898 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8899 | if (!crtc_state->has_pch_encoder) | |
8900 | return 0; | |
79e53945 | 8901 | |
997c030c ACO |
8902 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8903 | if (intel_panel_use_ssc(dev_priv)) { | |
8904 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8905 | dev_priv->vbt.lvds_ssc_freq); | |
8906 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8907 | } | |
8908 | ||
8909 | if (intel_is_dual_link_lvds(dev)) { | |
8910 | if (refclk == 100000) | |
8911 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8912 | else | |
8913 | limit = &intel_limits_ironlake_dual_lvds; | |
8914 | } else { | |
8915 | if (refclk == 100000) | |
8916 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8917 | else | |
8918 | limit = &intel_limits_ironlake_single_lvds; | |
8919 | } | |
8920 | } else { | |
8921 | limit = &intel_limits_ironlake_dac; | |
8922 | } | |
8923 | ||
364ee29d | 8924 | if (!crtc_state->clock_set && |
997c030c ACO |
8925 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8926 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8927 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8928 | return -EINVAL; | |
f47709a9 | 8929 | } |
79e53945 | 8930 | |
b75ca6f6 ACO |
8931 | ironlake_compute_dpll(crtc, crtc_state, |
8932 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 8933 | |
ded220e2 ACO |
8934 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
8935 | if (pll == NULL) { | |
8936 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8937 | pipe_name(crtc->pipe)); | |
8938 | return -EINVAL; | |
3fb37703 | 8939 | } |
79e53945 | 8940 | |
ded220e2 ACO |
8941 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8942 | has_reduced_clock) | |
c7653199 | 8943 | crtc->lowfreq_avail = true; |
e2b78267 | 8944 | |
c8f7a0db | 8945 | return 0; |
79e53945 JB |
8946 | } |
8947 | ||
eb14cb74 VS |
8948 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8949 | struct intel_link_m_n *m_n) | |
8950 | { | |
8951 | struct drm_device *dev = crtc->base.dev; | |
8952 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8953 | enum pipe pipe = crtc->pipe; | |
8954 | ||
8955 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8956 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8957 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8958 | & ~TU_SIZE_MASK; | |
8959 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8960 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8961 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8962 | } | |
8963 | ||
8964 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8965 | enum transcoder transcoder, | |
b95af8be VK |
8966 | struct intel_link_m_n *m_n, |
8967 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8968 | { |
8969 | struct drm_device *dev = crtc->base.dev; | |
8970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8971 | enum pipe pipe = crtc->pipe; |
72419203 | 8972 | |
eb14cb74 VS |
8973 | if (INTEL_INFO(dev)->gen >= 5) { |
8974 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8975 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8976 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8977 | & ~TU_SIZE_MASK; | |
8978 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8979 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8980 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8981 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8982 | * gen < 8) and if DRRS is supported (to make sure the | |
8983 | * registers are not unnecessarily read). | |
8984 | */ | |
8985 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8986 | crtc->config->has_drrs) { |
b95af8be VK |
8987 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8988 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8989 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8990 | & ~TU_SIZE_MASK; | |
8991 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8992 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8993 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8994 | } | |
eb14cb74 VS |
8995 | } else { |
8996 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8997 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8998 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8999 | & ~TU_SIZE_MASK; | |
9000 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9001 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9002 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9003 | } | |
9004 | } | |
9005 | ||
9006 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9007 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9008 | { |
681a8504 | 9009 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9010 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9011 | else | |
9012 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9013 | &pipe_config->dp_m_n, |
9014 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9015 | } |
72419203 | 9016 | |
eb14cb74 | 9017 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9018 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9019 | { |
9020 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9021 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9022 | } |
9023 | ||
bd2e244f | 9024 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9025 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9026 | { |
9027 | struct drm_device *dev = crtc->base.dev; | |
9028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9029 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9030 | uint32_t ps_ctrl = 0; | |
9031 | int id = -1; | |
9032 | int i; | |
bd2e244f | 9033 | |
a1b2278e CK |
9034 | /* find scaler attached to this pipe */ |
9035 | for (i = 0; i < crtc->num_scalers; i++) { | |
9036 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9037 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9038 | id = i; | |
9039 | pipe_config->pch_pfit.enabled = true; | |
9040 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9041 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9042 | break; | |
9043 | } | |
9044 | } | |
bd2e244f | 9045 | |
a1b2278e CK |
9046 | scaler_state->scaler_id = id; |
9047 | if (id >= 0) { | |
9048 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9049 | } else { | |
9050 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9051 | } |
9052 | } | |
9053 | ||
5724dbd1 DL |
9054 | static void |
9055 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9056 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9057 | { |
9058 | struct drm_device *dev = crtc->base.dev; | |
9059 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9060 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9061 | int pipe = crtc->pipe; |
9062 | int fourcc, pixel_format; | |
6761dd31 | 9063 | unsigned int aligned_height; |
bc8d7dff | 9064 | struct drm_framebuffer *fb; |
1b842c89 | 9065 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9066 | |
d9806c9f | 9067 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9068 | if (!intel_fb) { |
bc8d7dff DL |
9069 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9070 | return; | |
9071 | } | |
9072 | ||
1b842c89 DL |
9073 | fb = &intel_fb->base; |
9074 | ||
bc8d7dff | 9075 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9076 | if (!(val & PLANE_CTL_ENABLE)) |
9077 | goto error; | |
9078 | ||
bc8d7dff DL |
9079 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9080 | fourcc = skl_format_to_fourcc(pixel_format, | |
9081 | val & PLANE_CTL_ORDER_RGBX, | |
9082 | val & PLANE_CTL_ALPHA_MASK); | |
9083 | fb->pixel_format = fourcc; | |
9084 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9085 | ||
40f46283 DL |
9086 | tiling = val & PLANE_CTL_TILED_MASK; |
9087 | switch (tiling) { | |
9088 | case PLANE_CTL_TILED_LINEAR: | |
9089 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9090 | break; | |
9091 | case PLANE_CTL_TILED_X: | |
9092 | plane_config->tiling = I915_TILING_X; | |
9093 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9094 | break; | |
9095 | case PLANE_CTL_TILED_Y: | |
9096 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9097 | break; | |
9098 | case PLANE_CTL_TILED_YF: | |
9099 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9100 | break; | |
9101 | default: | |
9102 | MISSING_CASE(tiling); | |
9103 | goto error; | |
9104 | } | |
9105 | ||
bc8d7dff DL |
9106 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9107 | plane_config->base = base; | |
9108 | ||
9109 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9110 | ||
9111 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9112 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9113 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9114 | ||
9115 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9116 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9117 | fb->pixel_format); |
bc8d7dff DL |
9118 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9119 | ||
9120 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9121 | fb->pixel_format, |
9122 | fb->modifier[0]); | |
bc8d7dff | 9123 | |
f37b5c2b | 9124 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9125 | |
9126 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9127 | pipe_name(pipe), fb->width, fb->height, | |
9128 | fb->bits_per_pixel, base, fb->pitches[0], | |
9129 | plane_config->size); | |
9130 | ||
2d14030b | 9131 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9132 | return; |
9133 | ||
9134 | error: | |
9135 | kfree(fb); | |
9136 | } | |
9137 | ||
2fa2fe9a | 9138 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9139 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9140 | { |
9141 | struct drm_device *dev = crtc->base.dev; | |
9142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9143 | uint32_t tmp; | |
9144 | ||
9145 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9146 | ||
9147 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9148 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9149 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9150 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9151 | |
9152 | /* We currently do not free assignements of panel fitters on | |
9153 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9154 | * differentiates them) so just WARN about this case for now. */ | |
9155 | if (IS_GEN7(dev)) { | |
9156 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9157 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9158 | } | |
2fa2fe9a | 9159 | } |
79e53945 JB |
9160 | } |
9161 | ||
5724dbd1 DL |
9162 | static void |
9163 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9164 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9165 | { |
9166 | struct drm_device *dev = crtc->base.dev; | |
9167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9168 | u32 val, base, offset; | |
aeee5a49 | 9169 | int pipe = crtc->pipe; |
4c6baa59 | 9170 | int fourcc, pixel_format; |
6761dd31 | 9171 | unsigned int aligned_height; |
b113d5ee | 9172 | struct drm_framebuffer *fb; |
1b842c89 | 9173 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9174 | |
42a7b088 DL |
9175 | val = I915_READ(DSPCNTR(pipe)); |
9176 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9177 | return; | |
9178 | ||
d9806c9f | 9179 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9180 | if (!intel_fb) { |
4c6baa59 JB |
9181 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9182 | return; | |
9183 | } | |
9184 | ||
1b842c89 DL |
9185 | fb = &intel_fb->base; |
9186 | ||
18c5247e DV |
9187 | if (INTEL_INFO(dev)->gen >= 4) { |
9188 | if (val & DISPPLANE_TILED) { | |
49af449b | 9189 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9190 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9191 | } | |
9192 | } | |
4c6baa59 JB |
9193 | |
9194 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9195 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9196 | fb->pixel_format = fourcc; |
9197 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9198 | |
aeee5a49 | 9199 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9200 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9201 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9202 | } else { |
49af449b | 9203 | if (plane_config->tiling) |
aeee5a49 | 9204 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9205 | else |
aeee5a49 | 9206 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9207 | } |
9208 | plane_config->base = base; | |
9209 | ||
9210 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9211 | fb->width = ((val >> 16) & 0xfff) + 1; |
9212 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9213 | |
9214 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9215 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9216 | |
b113d5ee | 9217 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9218 | fb->pixel_format, |
9219 | fb->modifier[0]); | |
4c6baa59 | 9220 | |
f37b5c2b | 9221 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9222 | |
2844a921 DL |
9223 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9224 | pipe_name(pipe), fb->width, fb->height, | |
9225 | fb->bits_per_pixel, base, fb->pitches[0], | |
9226 | plane_config->size); | |
b113d5ee | 9227 | |
2d14030b | 9228 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9229 | } |
9230 | ||
0e8ffe1b | 9231 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9232 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9233 | { |
9234 | struct drm_device *dev = crtc->base.dev; | |
9235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9236 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9237 | uint32_t tmp; |
1729050e | 9238 | bool ret; |
0e8ffe1b | 9239 | |
1729050e ID |
9240 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9241 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9242 | return false; |
9243 | ||
e143a21c | 9244 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9245 | pipe_config->shared_dpll = NULL; |
eccb140b | 9246 | |
1729050e | 9247 | ret = false; |
0e8ffe1b DV |
9248 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9249 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9250 | goto out; |
0e8ffe1b | 9251 | |
42571aef VS |
9252 | switch (tmp & PIPECONF_BPC_MASK) { |
9253 | case PIPECONF_6BPC: | |
9254 | pipe_config->pipe_bpp = 18; | |
9255 | break; | |
9256 | case PIPECONF_8BPC: | |
9257 | pipe_config->pipe_bpp = 24; | |
9258 | break; | |
9259 | case PIPECONF_10BPC: | |
9260 | pipe_config->pipe_bpp = 30; | |
9261 | break; | |
9262 | case PIPECONF_12BPC: | |
9263 | pipe_config->pipe_bpp = 36; | |
9264 | break; | |
9265 | default: | |
9266 | break; | |
9267 | } | |
9268 | ||
b5a9fa09 DV |
9269 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9270 | pipe_config->limited_color_range = true; | |
9271 | ||
ab9412ba | 9272 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9273 | struct intel_shared_dpll *pll; |
8106ddbd | 9274 | enum intel_dpll_id pll_id; |
66e985c0 | 9275 | |
88adfff1 DV |
9276 | pipe_config->has_pch_encoder = true; |
9277 | ||
627eb5a3 DV |
9278 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9279 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9280 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9281 | |
9282 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9283 | |
2d1fe073 | 9284 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9285 | /* |
9286 | * The pipe->pch transcoder and pch transcoder->pll | |
9287 | * mapping is fixed. | |
9288 | */ | |
8106ddbd | 9289 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9290 | } else { |
9291 | tmp = I915_READ(PCH_DPLL_SEL); | |
9292 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9293 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9294 | else |
8106ddbd | 9295 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9296 | } |
66e985c0 | 9297 | |
8106ddbd ACO |
9298 | pipe_config->shared_dpll = |
9299 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9300 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9301 | |
2edd6443 ACO |
9302 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9303 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9304 | |
9305 | tmp = pipe_config->dpll_hw_state.dpll; | |
9306 | pipe_config->pixel_multiplier = | |
9307 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9308 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9309 | |
9310 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9311 | } else { |
9312 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9313 | } |
9314 | ||
1bd1bd80 | 9315 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9316 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9317 | |
2fa2fe9a DV |
9318 | ironlake_get_pfit_config(crtc, pipe_config); |
9319 | ||
1729050e ID |
9320 | ret = true; |
9321 | ||
9322 | out: | |
9323 | intel_display_power_put(dev_priv, power_domain); | |
9324 | ||
9325 | return ret; | |
0e8ffe1b DV |
9326 | } |
9327 | ||
be256dc7 PZ |
9328 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9329 | { | |
9330 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9331 | struct intel_crtc *crtc; |
be256dc7 | 9332 | |
d3fcc808 | 9333 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9334 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9335 | pipe_name(crtc->pipe)); |
9336 | ||
e2c719b7 RC |
9337 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9338 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9339 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9340 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9341 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9342 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9343 | "CPU PWM1 enabled\n"); |
c5107b87 | 9344 | if (IS_HASWELL(dev)) |
e2c719b7 | 9345 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9346 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9347 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9348 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9349 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9350 | "Utility pin enabled\n"); |
e2c719b7 | 9351 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9352 | |
9926ada1 PZ |
9353 | /* |
9354 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9355 | * interrupts remain enabled. We used to check for that, but since it's | |
9356 | * gen-specific and since we only disable LCPLL after we fully disable | |
9357 | * the interrupts, the check below should be enough. | |
9358 | */ | |
e2c719b7 | 9359 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9360 | } |
9361 | ||
9ccd5aeb PZ |
9362 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9363 | { | |
9364 | struct drm_device *dev = dev_priv->dev; | |
9365 | ||
9366 | if (IS_HASWELL(dev)) | |
9367 | return I915_READ(D_COMP_HSW); | |
9368 | else | |
9369 | return I915_READ(D_COMP_BDW); | |
9370 | } | |
9371 | ||
3c4c9b81 PZ |
9372 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9373 | { | |
9374 | struct drm_device *dev = dev_priv->dev; | |
9375 | ||
9376 | if (IS_HASWELL(dev)) { | |
9377 | mutex_lock(&dev_priv->rps.hw_lock); | |
9378 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9379 | val)) | |
f475dadf | 9380 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9381 | mutex_unlock(&dev_priv->rps.hw_lock); |
9382 | } else { | |
9ccd5aeb PZ |
9383 | I915_WRITE(D_COMP_BDW, val); |
9384 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9385 | } |
be256dc7 PZ |
9386 | } |
9387 | ||
9388 | /* | |
9389 | * This function implements pieces of two sequences from BSpec: | |
9390 | * - Sequence for display software to disable LCPLL | |
9391 | * - Sequence for display software to allow package C8+ | |
9392 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9393 | * register. Callers should take care of disabling all the display engine | |
9394 | * functions, doing the mode unset, fixing interrupts, etc. | |
9395 | */ | |
6ff58d53 PZ |
9396 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9397 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9398 | { |
9399 | uint32_t val; | |
9400 | ||
9401 | assert_can_disable_lcpll(dev_priv); | |
9402 | ||
9403 | val = I915_READ(LCPLL_CTL); | |
9404 | ||
9405 | if (switch_to_fclk) { | |
9406 | val |= LCPLL_CD_SOURCE_FCLK; | |
9407 | I915_WRITE(LCPLL_CTL, val); | |
9408 | ||
9409 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9410 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9411 | DRM_ERROR("Switching to FCLK failed\n"); | |
9412 | ||
9413 | val = I915_READ(LCPLL_CTL); | |
9414 | } | |
9415 | ||
9416 | val |= LCPLL_PLL_DISABLE; | |
9417 | I915_WRITE(LCPLL_CTL, val); | |
9418 | POSTING_READ(LCPLL_CTL); | |
9419 | ||
9420 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9421 | DRM_ERROR("LCPLL still locked\n"); | |
9422 | ||
9ccd5aeb | 9423 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9424 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9425 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9426 | ndelay(100); |
9427 | ||
9ccd5aeb PZ |
9428 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9429 | 1)) | |
be256dc7 PZ |
9430 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9431 | ||
9432 | if (allow_power_down) { | |
9433 | val = I915_READ(LCPLL_CTL); | |
9434 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9435 | I915_WRITE(LCPLL_CTL, val); | |
9436 | POSTING_READ(LCPLL_CTL); | |
9437 | } | |
9438 | } | |
9439 | ||
9440 | /* | |
9441 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9442 | * source. | |
9443 | */ | |
6ff58d53 | 9444 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9445 | { |
9446 | uint32_t val; | |
9447 | ||
9448 | val = I915_READ(LCPLL_CTL); | |
9449 | ||
9450 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9451 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9452 | return; | |
9453 | ||
a8a8bd54 PZ |
9454 | /* |
9455 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9456 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9457 | */ |
59bad947 | 9458 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9459 | |
be256dc7 PZ |
9460 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9461 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9462 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9463 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9464 | } |
9465 | ||
9ccd5aeb | 9466 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9467 | val |= D_COMP_COMP_FORCE; |
9468 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9469 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9470 | |
9471 | val = I915_READ(LCPLL_CTL); | |
9472 | val &= ~LCPLL_PLL_DISABLE; | |
9473 | I915_WRITE(LCPLL_CTL, val); | |
9474 | ||
9475 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9476 | DRM_ERROR("LCPLL not locked yet\n"); | |
9477 | ||
9478 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9479 | val = I915_READ(LCPLL_CTL); | |
9480 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9481 | I915_WRITE(LCPLL_CTL, val); | |
9482 | ||
9483 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9484 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9485 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9486 | } | |
215733fa | 9487 | |
59bad947 | 9488 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9489 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9490 | } |
9491 | ||
765dab67 PZ |
9492 | /* |
9493 | * Package states C8 and deeper are really deep PC states that can only be | |
9494 | * reached when all the devices on the system allow it, so even if the graphics | |
9495 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9496 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9497 | * | |
9498 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9499 | * well is disabled and most interrupts are disabled, and these are also | |
9500 | * requirements for runtime PM. When these conditions are met, we manually do | |
9501 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9502 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9503 | * hang the machine. | |
9504 | * | |
9505 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9506 | * the state of some registers, so when we come back from PC8+ we need to | |
9507 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9508 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9509 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9510 | * because of the runtime PM support). | |
9511 | * | |
9512 | * For more, read "Display Sequences for Package C8" on the hardware | |
9513 | * documentation. | |
9514 | */ | |
a14cb6fc | 9515 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9516 | { |
c67a470b PZ |
9517 | struct drm_device *dev = dev_priv->dev; |
9518 | uint32_t val; | |
9519 | ||
c67a470b PZ |
9520 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9521 | ||
c2699524 | 9522 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9523 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9524 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9525 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9526 | } | |
9527 | ||
9528 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9529 | hsw_disable_lcpll(dev_priv, true, true); |
9530 | } | |
9531 | ||
a14cb6fc | 9532 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9533 | { |
9534 | struct drm_device *dev = dev_priv->dev; | |
9535 | uint32_t val; | |
9536 | ||
c67a470b PZ |
9537 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9538 | ||
9539 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9540 | lpt_init_pch_refclk(dev); |
9541 | ||
c2699524 | 9542 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9543 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9544 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9545 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9546 | } | |
c67a470b PZ |
9547 | } |
9548 | ||
27c329ed | 9549 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9550 | { |
a821fc46 | 9551 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9552 | struct intel_atomic_state *old_intel_state = |
9553 | to_intel_atomic_state(old_state); | |
9554 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9555 | |
c6c4696f | 9556 | broxton_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
9557 | } |
9558 | ||
b432e5cf | 9559 | /* compute the max rate for new configuration */ |
27c329ed | 9560 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9561 | { |
565602d7 ML |
9562 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9563 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9564 | struct drm_crtc *crtc; | |
9565 | struct drm_crtc_state *cstate; | |
27c329ed | 9566 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9567 | unsigned max_pixel_rate = 0, i; |
9568 | enum pipe pipe; | |
b432e5cf | 9569 | |
565602d7 ML |
9570 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9571 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9572 | |
565602d7 ML |
9573 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9574 | int pixel_rate; | |
27c329ed | 9575 | |
565602d7 ML |
9576 | crtc_state = to_intel_crtc_state(cstate); |
9577 | if (!crtc_state->base.enable) { | |
9578 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9579 | continue; |
565602d7 | 9580 | } |
b432e5cf | 9581 | |
27c329ed | 9582 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9583 | |
9584 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9585 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9586 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9587 | ||
565602d7 | 9588 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9589 | } |
9590 | ||
565602d7 ML |
9591 | for_each_pipe(dev_priv, pipe) |
9592 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9593 | ||
b432e5cf VS |
9594 | return max_pixel_rate; |
9595 | } | |
9596 | ||
9597 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9598 | { | |
9599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9600 | uint32_t val, data; | |
9601 | int ret; | |
9602 | ||
9603 | if (WARN((I915_READ(LCPLL_CTL) & | |
9604 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9605 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9606 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9607 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9608 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9609 | return; | |
9610 | ||
9611 | mutex_lock(&dev_priv->rps.hw_lock); | |
9612 | ret = sandybridge_pcode_write(dev_priv, | |
9613 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9614 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9615 | if (ret) { | |
9616 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9617 | return; | |
9618 | } | |
9619 | ||
9620 | val = I915_READ(LCPLL_CTL); | |
9621 | val |= LCPLL_CD_SOURCE_FCLK; | |
9622 | I915_WRITE(LCPLL_CTL, val); | |
9623 | ||
5ba00178 TU |
9624 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9625 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9626 | DRM_ERROR("Switching to FCLK failed\n"); |
9627 | ||
9628 | val = I915_READ(LCPLL_CTL); | |
9629 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9630 | ||
9631 | switch (cdclk) { | |
9632 | case 450000: | |
9633 | val |= LCPLL_CLK_FREQ_450; | |
9634 | data = 0; | |
9635 | break; | |
9636 | case 540000: | |
9637 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9638 | data = 1; | |
9639 | break; | |
9640 | case 337500: | |
9641 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9642 | data = 2; | |
9643 | break; | |
9644 | case 675000: | |
9645 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9646 | data = 3; | |
9647 | break; | |
9648 | default: | |
9649 | WARN(1, "invalid cdclk frequency\n"); | |
9650 | return; | |
9651 | } | |
9652 | ||
9653 | I915_WRITE(LCPLL_CTL, val); | |
9654 | ||
9655 | val = I915_READ(LCPLL_CTL); | |
9656 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9657 | I915_WRITE(LCPLL_CTL, val); | |
9658 | ||
5ba00178 TU |
9659 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9660 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9661 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9662 | ||
9663 | mutex_lock(&dev_priv->rps.hw_lock); | |
9664 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9665 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9666 | ||
7f1052a8 VS |
9667 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
9668 | ||
b432e5cf VS |
9669 | intel_update_cdclk(dev); |
9670 | ||
9671 | WARN(cdclk != dev_priv->cdclk_freq, | |
9672 | "cdclk requested %d kHz but got %d kHz\n", | |
9673 | cdclk, dev_priv->cdclk_freq); | |
9674 | } | |
9675 | ||
587c7914 VS |
9676 | static int broadwell_calc_cdclk(int max_pixclk) |
9677 | { | |
9678 | if (max_pixclk > 540000) | |
9679 | return 675000; | |
9680 | else if (max_pixclk > 450000) | |
9681 | return 540000; | |
9682 | else if (max_pixclk > 337500) | |
9683 | return 450000; | |
9684 | else | |
9685 | return 337500; | |
9686 | } | |
9687 | ||
27c329ed | 9688 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9689 | { |
27c329ed | 9690 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9691 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9692 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9693 | int cdclk; |
9694 | ||
9695 | /* | |
9696 | * FIXME should also account for plane ratio | |
9697 | * once 64bpp pixel formats are supported. | |
9698 | */ | |
587c7914 | 9699 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 9700 | |
b432e5cf | 9701 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9702 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9703 | cdclk, dev_priv->max_cdclk_freq); | |
9704 | return -EINVAL; | |
b432e5cf VS |
9705 | } |
9706 | ||
1a617b77 ML |
9707 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9708 | if (!intel_state->active_crtcs) | |
587c7914 | 9709 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
9710 | |
9711 | return 0; | |
9712 | } | |
9713 | ||
27c329ed | 9714 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9715 | { |
27c329ed | 9716 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9717 | struct intel_atomic_state *old_intel_state = |
9718 | to_intel_atomic_state(old_state); | |
9719 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9720 | |
27c329ed | 9721 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9722 | } |
9723 | ||
190f68c5 ACO |
9724 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9725 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9726 | { |
af3997b5 MK |
9727 | struct intel_encoder *intel_encoder = |
9728 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9729 | ||
9730 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9731 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9732 | return -EINVAL; | |
9733 | } | |
716c2e55 | 9734 | |
c7653199 | 9735 | crtc->lowfreq_avail = false; |
644cef34 | 9736 | |
c8f7a0db | 9737 | return 0; |
79e53945 JB |
9738 | } |
9739 | ||
3760b59c S |
9740 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9741 | enum port port, | |
9742 | struct intel_crtc_state *pipe_config) | |
9743 | { | |
8106ddbd ACO |
9744 | enum intel_dpll_id id; |
9745 | ||
3760b59c S |
9746 | switch (port) { |
9747 | case PORT_A: | |
9748 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 9749 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9750 | break; |
9751 | case PORT_B: | |
9752 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 9753 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9754 | break; |
9755 | case PORT_C: | |
9756 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 9757 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9758 | break; |
9759 | default: | |
9760 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9761 | return; |
3760b59c | 9762 | } |
8106ddbd ACO |
9763 | |
9764 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9765 | } |
9766 | ||
96b7dfb7 S |
9767 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9768 | enum port port, | |
5cec258b | 9769 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9770 | { |
8106ddbd | 9771 | enum intel_dpll_id id; |
a3c988ea | 9772 | u32 temp; |
96b7dfb7 S |
9773 | |
9774 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9775 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9776 | ||
9777 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 9778 | case SKL_DPLL0: |
a3c988ea ACO |
9779 | id = DPLL_ID_SKL_DPLL0; |
9780 | break; | |
96b7dfb7 | 9781 | case SKL_DPLL1: |
8106ddbd | 9782 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
9783 | break; |
9784 | case SKL_DPLL2: | |
8106ddbd | 9785 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
9786 | break; |
9787 | case SKL_DPLL3: | |
8106ddbd | 9788 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 9789 | break; |
8106ddbd ACO |
9790 | default: |
9791 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9792 | return; | |
96b7dfb7 | 9793 | } |
8106ddbd ACO |
9794 | |
9795 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9796 | } |
9797 | ||
7d2c8175 DL |
9798 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9799 | enum port port, | |
5cec258b | 9800 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9801 | { |
8106ddbd ACO |
9802 | enum intel_dpll_id id; |
9803 | ||
7d2c8175 DL |
9804 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
9805 | ||
9806 | switch (pipe_config->ddi_pll_sel) { | |
9807 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 9808 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9809 | break; |
9810 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9811 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9812 | break; |
00490c22 | 9813 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9814 | id = DPLL_ID_SPLL; |
79bd23da | 9815 | break; |
9d16da65 ACO |
9816 | case PORT_CLK_SEL_LCPLL_810: |
9817 | id = DPLL_ID_LCPLL_810; | |
9818 | break; | |
9819 | case PORT_CLK_SEL_LCPLL_1350: | |
9820 | id = DPLL_ID_LCPLL_1350; | |
9821 | break; | |
9822 | case PORT_CLK_SEL_LCPLL_2700: | |
9823 | id = DPLL_ID_LCPLL_2700; | |
9824 | break; | |
8106ddbd ACO |
9825 | default: |
9826 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9827 | /* fall through */ | |
9828 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9829 | return; |
7d2c8175 | 9830 | } |
8106ddbd ACO |
9831 | |
9832 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9833 | } |
9834 | ||
cf30429e JN |
9835 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9836 | struct intel_crtc_state *pipe_config, | |
9837 | unsigned long *power_domain_mask) | |
9838 | { | |
9839 | struct drm_device *dev = crtc->base.dev; | |
9840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9841 | enum intel_display_power_domain power_domain; | |
9842 | u32 tmp; | |
9843 | ||
d9a7bc67 ID |
9844 | /* |
9845 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
9846 | * transcoder handled below. | |
9847 | */ | |
cf30429e JN |
9848 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9849 | ||
9850 | /* | |
9851 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9852 | * consistency and less surprising code; it's in always on power). | |
9853 | */ | |
9854 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9855 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9856 | enum pipe trans_edp_pipe; | |
9857 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9858 | default: | |
9859 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9860 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9861 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9862 | trans_edp_pipe = PIPE_A; | |
9863 | break; | |
9864 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9865 | trans_edp_pipe = PIPE_B; | |
9866 | break; | |
9867 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9868 | trans_edp_pipe = PIPE_C; | |
9869 | break; | |
9870 | } | |
9871 | ||
9872 | if (trans_edp_pipe == crtc->pipe) | |
9873 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9874 | } | |
9875 | ||
9876 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9877 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9878 | return false; | |
9879 | *power_domain_mask |= BIT(power_domain); | |
9880 | ||
9881 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9882 | ||
9883 | return tmp & PIPECONF_ENABLE; | |
9884 | } | |
9885 | ||
4d1de975 JN |
9886 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9887 | struct intel_crtc_state *pipe_config, | |
9888 | unsigned long *power_domain_mask) | |
9889 | { | |
9890 | struct drm_device *dev = crtc->base.dev; | |
9891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9892 | enum intel_display_power_domain power_domain; | |
9893 | enum port port; | |
9894 | enum transcoder cpu_transcoder; | |
9895 | u32 tmp; | |
9896 | ||
9897 | pipe_config->has_dsi_encoder = false; | |
9898 | ||
9899 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { | |
9900 | if (port == PORT_A) | |
9901 | cpu_transcoder = TRANSCODER_DSI_A; | |
9902 | else | |
9903 | cpu_transcoder = TRANSCODER_DSI_C; | |
9904 | ||
9905 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9906 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9907 | continue; | |
9908 | *power_domain_mask |= BIT(power_domain); | |
9909 | ||
db18b6a6 ID |
9910 | /* |
9911 | * The PLL needs to be enabled with a valid divider | |
9912 | * configuration, otherwise accessing DSI registers will hang | |
9913 | * the machine. See BSpec North Display Engine | |
9914 | * registers/MIPI[BXT]. We can break out here early, since we | |
9915 | * need the same DSI PLL to be enabled for both DSI ports. | |
9916 | */ | |
9917 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9918 | break; | |
9919 | ||
4d1de975 JN |
9920 | /* XXX: this works for video mode only */ |
9921 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9922 | if (!(tmp & DPI_ENABLE)) | |
9923 | continue; | |
9924 | ||
9925 | tmp = I915_READ(MIPI_CTRL(port)); | |
9926 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9927 | continue; | |
9928 | ||
9929 | pipe_config->cpu_transcoder = cpu_transcoder; | |
9930 | pipe_config->has_dsi_encoder = true; | |
9931 | break; | |
9932 | } | |
9933 | ||
9934 | return pipe_config->has_dsi_encoder; | |
9935 | } | |
9936 | ||
26804afd | 9937 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9938 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9939 | { |
9940 | struct drm_device *dev = crtc->base.dev; | |
9941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9942 | struct intel_shared_dpll *pll; |
26804afd DV |
9943 | enum port port; |
9944 | uint32_t tmp; | |
9945 | ||
9946 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9947 | ||
9948 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9949 | ||
ef11bdb3 | 9950 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9951 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9952 | else if (IS_BROXTON(dev)) |
9953 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9954 | else |
9955 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9956 | |
8106ddbd ACO |
9957 | pll = pipe_config->shared_dpll; |
9958 | if (pll) { | |
2edd6443 ACO |
9959 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9960 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9961 | } |
9962 | ||
26804afd DV |
9963 | /* |
9964 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9965 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9966 | * the PCH transcoder is on. | |
9967 | */ | |
ca370455 DL |
9968 | if (INTEL_INFO(dev)->gen < 9 && |
9969 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9970 | pipe_config->has_pch_encoder = true; |
9971 | ||
9972 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9973 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9974 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9975 | ||
9976 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9977 | } | |
9978 | } | |
9979 | ||
0e8ffe1b | 9980 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9981 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9982 | { |
9983 | struct drm_device *dev = crtc->base.dev; | |
9984 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
9985 | enum intel_display_power_domain power_domain; |
9986 | unsigned long power_domain_mask; | |
cf30429e | 9987 | bool active; |
0e8ffe1b | 9988 | |
1729050e ID |
9989 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9990 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9991 | return false; |
1729050e ID |
9992 | power_domain_mask = BIT(power_domain); |
9993 | ||
8106ddbd | 9994 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9995 | |
cf30429e | 9996 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9997 | |
4d1de975 JN |
9998 | if (IS_BROXTON(dev_priv)) { |
9999 | bxt_get_dsi_transcoder_state(crtc, pipe_config, | |
10000 | &power_domain_mask); | |
10001 | WARN_ON(active && pipe_config->has_dsi_encoder); | |
10002 | if (pipe_config->has_dsi_encoder) | |
10003 | active = true; | |
10004 | } | |
10005 | ||
cf30429e | 10006 | if (!active) |
1729050e | 10007 | goto out; |
0e8ffe1b | 10008 | |
4d1de975 JN |
10009 | if (!pipe_config->has_dsi_encoder) { |
10010 | haswell_get_ddi_port_state(crtc, pipe_config); | |
10011 | intel_get_pipe_timings(crtc, pipe_config); | |
10012 | } | |
627eb5a3 | 10013 | |
bc58be60 | 10014 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10015 | |
05dc698c LL |
10016 | pipe_config->gamma_mode = |
10017 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10018 | ||
a1b2278e CK |
10019 | if (INTEL_INFO(dev)->gen >= 9) { |
10020 | skl_init_scalers(dev, crtc, pipe_config); | |
10021 | } | |
10022 | ||
af99ceda CK |
10023 | if (INTEL_INFO(dev)->gen >= 9) { |
10024 | pipe_config->scaler_state.scaler_id = -1; | |
10025 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10026 | } | |
10027 | ||
1729050e ID |
10028 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10029 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10030 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10031 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10032 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10033 | else |
1c132b44 | 10034 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10035 | } |
88adfff1 | 10036 | |
e59150dc JB |
10037 | if (IS_HASWELL(dev)) |
10038 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10039 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10040 | |
4d1de975 JN |
10041 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10042 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10043 | pipe_config->pixel_multiplier = |
10044 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10045 | } else { | |
10046 | pipe_config->pixel_multiplier = 1; | |
10047 | } | |
6c49f241 | 10048 | |
1729050e ID |
10049 | out: |
10050 | for_each_power_domain(power_domain, power_domain_mask) | |
10051 | intel_display_power_put(dev_priv, power_domain); | |
10052 | ||
cf30429e | 10053 | return active; |
0e8ffe1b DV |
10054 | } |
10055 | ||
55a08b3f ML |
10056 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10057 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10058 | { |
10059 | struct drm_device *dev = crtc->dev; | |
10060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10061 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10062 | uint32_t cntl = 0, size = 0; |
560b85bb | 10063 | |
55a08b3f ML |
10064 | if (plane_state && plane_state->visible) { |
10065 | unsigned int width = plane_state->base.crtc_w; | |
10066 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10067 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10068 | ||
10069 | switch (stride) { | |
10070 | default: | |
10071 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10072 | width, stride); | |
10073 | stride = 256; | |
10074 | /* fallthrough */ | |
10075 | case 256: | |
10076 | case 512: | |
10077 | case 1024: | |
10078 | case 2048: | |
10079 | break; | |
4b0e333e CW |
10080 | } |
10081 | ||
dc41c154 VS |
10082 | cntl |= CURSOR_ENABLE | |
10083 | CURSOR_GAMMA_ENABLE | | |
10084 | CURSOR_FORMAT_ARGB | | |
10085 | CURSOR_STRIDE(stride); | |
10086 | ||
10087 | size = (height << 12) | width; | |
4b0e333e | 10088 | } |
560b85bb | 10089 | |
dc41c154 VS |
10090 | if (intel_crtc->cursor_cntl != 0 && |
10091 | (intel_crtc->cursor_base != base || | |
10092 | intel_crtc->cursor_size != size || | |
10093 | intel_crtc->cursor_cntl != cntl)) { | |
10094 | /* On these chipsets we can only modify the base/size/stride | |
10095 | * whilst the cursor is disabled. | |
10096 | */ | |
0b87c24e VS |
10097 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10098 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10099 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10100 | } |
560b85bb | 10101 | |
99d1f387 | 10102 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10103 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10104 | intel_crtc->cursor_base = base; |
10105 | } | |
4726e0b0 | 10106 | |
dc41c154 VS |
10107 | if (intel_crtc->cursor_size != size) { |
10108 | I915_WRITE(CURSIZE, size); | |
10109 | intel_crtc->cursor_size = size; | |
4b0e333e | 10110 | } |
560b85bb | 10111 | |
4b0e333e | 10112 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10113 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10114 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10115 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10116 | } |
560b85bb CW |
10117 | } |
10118 | ||
55a08b3f ML |
10119 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10120 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10121 | { |
10122 | struct drm_device *dev = crtc->dev; | |
10123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10124 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10125 | int pipe = intel_crtc->pipe; | |
663f3122 | 10126 | uint32_t cntl = 0; |
4b0e333e | 10127 | |
55a08b3f | 10128 | if (plane_state && plane_state->visible) { |
4b0e333e | 10129 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10130 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10131 | case 64: |
10132 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10133 | break; | |
10134 | case 128: | |
10135 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10136 | break; | |
10137 | case 256: | |
10138 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10139 | break; | |
10140 | default: | |
55a08b3f | 10141 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10142 | return; |
65a21cd6 | 10143 | } |
4b0e333e | 10144 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10145 | |
fc6f93bc | 10146 | if (HAS_DDI(dev)) |
47bf17a7 | 10147 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10148 | |
55a08b3f ML |
10149 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10150 | cntl |= CURSOR_ROTATE_180; | |
10151 | } | |
4398ad45 | 10152 | |
4b0e333e CW |
10153 | if (intel_crtc->cursor_cntl != cntl) { |
10154 | I915_WRITE(CURCNTR(pipe), cntl); | |
10155 | POSTING_READ(CURCNTR(pipe)); | |
10156 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10157 | } |
4b0e333e | 10158 | |
65a21cd6 | 10159 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10160 | I915_WRITE(CURBASE(pipe), base); |
10161 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10162 | |
10163 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10164 | } |
10165 | ||
cda4b7d3 | 10166 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10167 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10168 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10169 | { |
10170 | struct drm_device *dev = crtc->dev; | |
10171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10173 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10174 | u32 base = intel_crtc->cursor_addr; |
10175 | u32 pos = 0; | |
cda4b7d3 | 10176 | |
55a08b3f ML |
10177 | if (plane_state) { |
10178 | int x = plane_state->base.crtc_x; | |
10179 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10180 | |
55a08b3f ML |
10181 | if (x < 0) { |
10182 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10183 | x = -x; | |
10184 | } | |
10185 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10186 | |
55a08b3f ML |
10187 | if (y < 0) { |
10188 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10189 | y = -y; | |
10190 | } | |
10191 | pos |= y << CURSOR_Y_SHIFT; | |
10192 | ||
10193 | /* ILK+ do this automagically */ | |
10194 | if (HAS_GMCH_DISPLAY(dev) && | |
10195 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10196 | base += (plane_state->base.crtc_h * | |
10197 | plane_state->base.crtc_w - 1) * 4; | |
10198 | } | |
cda4b7d3 | 10199 | } |
cda4b7d3 | 10200 | |
5efb3e28 VS |
10201 | I915_WRITE(CURPOS(pipe), pos); |
10202 | ||
8ac54669 | 10203 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10204 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10205 | else |
55a08b3f | 10206 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10207 | } |
10208 | ||
dc41c154 VS |
10209 | static bool cursor_size_ok(struct drm_device *dev, |
10210 | uint32_t width, uint32_t height) | |
10211 | { | |
10212 | if (width == 0 || height == 0) | |
10213 | return false; | |
10214 | ||
10215 | /* | |
10216 | * 845g/865g are special in that they are only limited by | |
10217 | * the width of their cursors, the height is arbitrary up to | |
10218 | * the precision of the register. Everything else requires | |
10219 | * square cursors, limited to a few power-of-two sizes. | |
10220 | */ | |
10221 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10222 | if ((width & 63) != 0) | |
10223 | return false; | |
10224 | ||
10225 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10226 | return false; | |
10227 | ||
10228 | if (height > 1023) | |
10229 | return false; | |
10230 | } else { | |
10231 | switch (width | height) { | |
10232 | case 256: | |
10233 | case 128: | |
10234 | if (IS_GEN2(dev)) | |
10235 | return false; | |
10236 | case 64: | |
10237 | break; | |
10238 | default: | |
10239 | return false; | |
10240 | } | |
10241 | } | |
10242 | ||
10243 | return true; | |
10244 | } | |
10245 | ||
79e53945 JB |
10246 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10247 | static struct drm_display_mode load_detect_mode = { | |
10248 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10249 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10250 | }; | |
10251 | ||
a8bb6818 DV |
10252 | struct drm_framebuffer * |
10253 | __intel_framebuffer_create(struct drm_device *dev, | |
10254 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10255 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10256 | { |
10257 | struct intel_framebuffer *intel_fb; | |
10258 | int ret; | |
10259 | ||
10260 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10261 | if (!intel_fb) |
d2dff872 | 10262 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10263 | |
10264 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10265 | if (ret) |
10266 | goto err; | |
d2dff872 CW |
10267 | |
10268 | return &intel_fb->base; | |
dcb1394e | 10269 | |
dd4916c5 | 10270 | err: |
dd4916c5 | 10271 | kfree(intel_fb); |
dd4916c5 | 10272 | return ERR_PTR(ret); |
d2dff872 CW |
10273 | } |
10274 | ||
b5ea642a | 10275 | static struct drm_framebuffer * |
a8bb6818 DV |
10276 | intel_framebuffer_create(struct drm_device *dev, |
10277 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10278 | struct drm_i915_gem_object *obj) | |
10279 | { | |
10280 | struct drm_framebuffer *fb; | |
10281 | int ret; | |
10282 | ||
10283 | ret = i915_mutex_lock_interruptible(dev); | |
10284 | if (ret) | |
10285 | return ERR_PTR(ret); | |
10286 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10287 | mutex_unlock(&dev->struct_mutex); | |
10288 | ||
10289 | return fb; | |
10290 | } | |
10291 | ||
d2dff872 CW |
10292 | static u32 |
10293 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10294 | { | |
10295 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10296 | return ALIGN(pitch, 64); | |
10297 | } | |
10298 | ||
10299 | static u32 | |
10300 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10301 | { | |
10302 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10303 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10304 | } |
10305 | ||
10306 | static struct drm_framebuffer * | |
10307 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10308 | struct drm_display_mode *mode, | |
10309 | int depth, int bpp) | |
10310 | { | |
dcb1394e | 10311 | struct drm_framebuffer *fb; |
d2dff872 | 10312 | struct drm_i915_gem_object *obj; |
0fed39bd | 10313 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 10314 | |
d37cd8a8 | 10315 | obj = i915_gem_object_create(dev, |
d2dff872 | 10316 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
10317 | if (IS_ERR(obj)) |
10318 | return ERR_CAST(obj); | |
d2dff872 CW |
10319 | |
10320 | mode_cmd.width = mode->hdisplay; | |
10321 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10322 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10323 | bpp); | |
5ca0c34a | 10324 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10325 | |
dcb1394e LW |
10326 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10327 | if (IS_ERR(fb)) | |
10328 | drm_gem_object_unreference_unlocked(&obj->base); | |
10329 | ||
10330 | return fb; | |
d2dff872 CW |
10331 | } |
10332 | ||
10333 | static struct drm_framebuffer * | |
10334 | mode_fits_in_fbdev(struct drm_device *dev, | |
10335 | struct drm_display_mode *mode) | |
10336 | { | |
0695726e | 10337 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10338 | struct drm_i915_private *dev_priv = dev->dev_private; |
10339 | struct drm_i915_gem_object *obj; | |
10340 | struct drm_framebuffer *fb; | |
10341 | ||
4c0e5528 | 10342 | if (!dev_priv->fbdev) |
d2dff872 CW |
10343 | return NULL; |
10344 | ||
4c0e5528 | 10345 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10346 | return NULL; |
10347 | ||
4c0e5528 DV |
10348 | obj = dev_priv->fbdev->fb->obj; |
10349 | BUG_ON(!obj); | |
10350 | ||
8bcd4553 | 10351 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10352 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10353 | fb->bits_per_pixel)) | |
d2dff872 CW |
10354 | return NULL; |
10355 | ||
01f2c773 | 10356 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10357 | return NULL; |
10358 | ||
edde3617 | 10359 | drm_framebuffer_reference(fb); |
d2dff872 | 10360 | return fb; |
4520f53a DV |
10361 | #else |
10362 | return NULL; | |
10363 | #endif | |
d2dff872 CW |
10364 | } |
10365 | ||
d3a40d1b ACO |
10366 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10367 | struct drm_crtc *crtc, | |
10368 | struct drm_display_mode *mode, | |
10369 | struct drm_framebuffer *fb, | |
10370 | int x, int y) | |
10371 | { | |
10372 | struct drm_plane_state *plane_state; | |
10373 | int hdisplay, vdisplay; | |
10374 | int ret; | |
10375 | ||
10376 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10377 | if (IS_ERR(plane_state)) | |
10378 | return PTR_ERR(plane_state); | |
10379 | ||
10380 | if (mode) | |
10381 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10382 | else | |
10383 | hdisplay = vdisplay = 0; | |
10384 | ||
10385 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10386 | if (ret) | |
10387 | return ret; | |
10388 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10389 | plane_state->crtc_x = 0; | |
10390 | plane_state->crtc_y = 0; | |
10391 | plane_state->crtc_w = hdisplay; | |
10392 | plane_state->crtc_h = vdisplay; | |
10393 | plane_state->src_x = x << 16; | |
10394 | plane_state->src_y = y << 16; | |
10395 | plane_state->src_w = hdisplay << 16; | |
10396 | plane_state->src_h = vdisplay << 16; | |
10397 | ||
10398 | return 0; | |
10399 | } | |
10400 | ||
d2434ab7 | 10401 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10402 | struct drm_display_mode *mode, |
51fd371b RC |
10403 | struct intel_load_detect_pipe *old, |
10404 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10405 | { |
10406 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10407 | struct intel_encoder *intel_encoder = |
10408 | intel_attached_encoder(connector); | |
79e53945 | 10409 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10410 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10411 | struct drm_crtc *crtc = NULL; |
10412 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10413 | struct drm_framebuffer *fb; |
51fd371b | 10414 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10415 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10416 | struct drm_connector_state *connector_state; |
4be07317 | 10417 | struct intel_crtc_state *crtc_state; |
51fd371b | 10418 | int ret, i = -1; |
79e53945 | 10419 | |
d2dff872 | 10420 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10421 | connector->base.id, connector->name, |
8e329a03 | 10422 | encoder->base.id, encoder->name); |
d2dff872 | 10423 | |
edde3617 ML |
10424 | old->restore_state = NULL; |
10425 | ||
51fd371b RC |
10426 | retry: |
10427 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10428 | if (ret) | |
ad3c558f | 10429 | goto fail; |
6e9f798d | 10430 | |
79e53945 JB |
10431 | /* |
10432 | * Algorithm gets a little messy: | |
7a5e4805 | 10433 | * |
79e53945 JB |
10434 | * - if the connector already has an assigned crtc, use it (but make |
10435 | * sure it's on first) | |
7a5e4805 | 10436 | * |
79e53945 JB |
10437 | * - try to find the first unused crtc that can drive this connector, |
10438 | * and use that if we find one | |
79e53945 JB |
10439 | */ |
10440 | ||
10441 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10442 | if (connector->state->crtc) { |
10443 | crtc = connector->state->crtc; | |
8261b191 | 10444 | |
51fd371b | 10445 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10446 | if (ret) |
ad3c558f | 10447 | goto fail; |
8261b191 CW |
10448 | |
10449 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10450 | goto found; |
79e53945 JB |
10451 | } |
10452 | ||
10453 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10454 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10455 | i++; |
10456 | if (!(encoder->possible_crtcs & (1 << i))) | |
10457 | continue; | |
edde3617 ML |
10458 | |
10459 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10460 | if (ret) | |
10461 | goto fail; | |
10462 | ||
10463 | if (possible_crtc->state->enable) { | |
10464 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10465 | continue; |
edde3617 | 10466 | } |
a459249c VS |
10467 | |
10468 | crtc = possible_crtc; | |
10469 | break; | |
79e53945 JB |
10470 | } |
10471 | ||
10472 | /* | |
10473 | * If we didn't find an unused CRTC, don't use any. | |
10474 | */ | |
10475 | if (!crtc) { | |
7173188d | 10476 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10477 | goto fail; |
79e53945 JB |
10478 | } |
10479 | ||
edde3617 ML |
10480 | found: |
10481 | intel_crtc = to_intel_crtc(crtc); | |
10482 | ||
4d02e2de DV |
10483 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10484 | if (ret) | |
ad3c558f | 10485 | goto fail; |
79e53945 | 10486 | |
83a57153 | 10487 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10488 | restore_state = drm_atomic_state_alloc(dev); |
10489 | if (!state || !restore_state) { | |
10490 | ret = -ENOMEM; | |
10491 | goto fail; | |
10492 | } | |
83a57153 ACO |
10493 | |
10494 | state->acquire_ctx = ctx; | |
edde3617 | 10495 | restore_state->acquire_ctx = ctx; |
83a57153 | 10496 | |
944b0c76 ACO |
10497 | connector_state = drm_atomic_get_connector_state(state, connector); |
10498 | if (IS_ERR(connector_state)) { | |
10499 | ret = PTR_ERR(connector_state); | |
10500 | goto fail; | |
10501 | } | |
10502 | ||
edde3617 ML |
10503 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10504 | if (ret) | |
10505 | goto fail; | |
944b0c76 | 10506 | |
4be07317 ACO |
10507 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10508 | if (IS_ERR(crtc_state)) { | |
10509 | ret = PTR_ERR(crtc_state); | |
10510 | goto fail; | |
10511 | } | |
10512 | ||
49d6fa21 | 10513 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10514 | |
6492711d CW |
10515 | if (!mode) |
10516 | mode = &load_detect_mode; | |
79e53945 | 10517 | |
d2dff872 CW |
10518 | /* We need a framebuffer large enough to accommodate all accesses |
10519 | * that the plane may generate whilst we perform load detection. | |
10520 | * We can not rely on the fbcon either being present (we get called | |
10521 | * during its initialisation to detect all boot displays, or it may | |
10522 | * not even exist) or that it is large enough to satisfy the | |
10523 | * requested mode. | |
10524 | */ | |
94352cf9 DV |
10525 | fb = mode_fits_in_fbdev(dev, mode); |
10526 | if (fb == NULL) { | |
d2dff872 | 10527 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10528 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10529 | } else |
10530 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10531 | if (IS_ERR(fb)) { |
d2dff872 | 10532 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10533 | goto fail; |
79e53945 | 10534 | } |
79e53945 | 10535 | |
d3a40d1b ACO |
10536 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10537 | if (ret) | |
10538 | goto fail; | |
10539 | ||
edde3617 ML |
10540 | drm_framebuffer_unreference(fb); |
10541 | ||
10542 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10543 | if (ret) | |
10544 | goto fail; | |
10545 | ||
10546 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10547 | if (!ret) | |
10548 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10549 | if (!ret) | |
10550 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10551 | if (ret) { | |
10552 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10553 | goto fail; | |
10554 | } | |
8c7b5ccb | 10555 | |
3ba86073 ML |
10556 | ret = drm_atomic_commit(state); |
10557 | if (ret) { | |
6492711d | 10558 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10559 | goto fail; |
79e53945 | 10560 | } |
edde3617 ML |
10561 | |
10562 | old->restore_state = restore_state; | |
7173188d | 10563 | |
79e53945 | 10564 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10565 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10566 | return true; |
412b61d8 | 10567 | |
ad3c558f | 10568 | fail: |
e5d958ef | 10569 | drm_atomic_state_free(state); |
edde3617 ML |
10570 | drm_atomic_state_free(restore_state); |
10571 | restore_state = state = NULL; | |
83a57153 | 10572 | |
51fd371b RC |
10573 | if (ret == -EDEADLK) { |
10574 | drm_modeset_backoff(ctx); | |
10575 | goto retry; | |
10576 | } | |
10577 | ||
412b61d8 | 10578 | return false; |
79e53945 JB |
10579 | } |
10580 | ||
d2434ab7 | 10581 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10582 | struct intel_load_detect_pipe *old, |
10583 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10584 | { |
d2434ab7 DV |
10585 | struct intel_encoder *intel_encoder = |
10586 | intel_attached_encoder(connector); | |
4ef69c7a | 10587 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10588 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10589 | int ret; |
79e53945 | 10590 | |
d2dff872 | 10591 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10592 | connector->base.id, connector->name, |
8e329a03 | 10593 | encoder->base.id, encoder->name); |
d2dff872 | 10594 | |
edde3617 | 10595 | if (!state) |
0622a53c | 10596 | return; |
79e53945 | 10597 | |
edde3617 ML |
10598 | ret = drm_atomic_commit(state); |
10599 | if (ret) { | |
10600 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10601 | drm_atomic_state_free(state); | |
10602 | } | |
79e53945 JB |
10603 | } |
10604 | ||
da4a1efa | 10605 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10606 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10607 | { |
10608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10609 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10610 | ||
10611 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10612 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10613 | else if (HAS_PCH_SPLIT(dev)) |
10614 | return 120000; | |
10615 | else if (!IS_GEN2(dev)) | |
10616 | return 96000; | |
10617 | else | |
10618 | return 48000; | |
10619 | } | |
10620 | ||
79e53945 | 10621 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10622 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10623 | struct intel_crtc_state *pipe_config) |
79e53945 | 10624 | { |
f1f644dc | 10625 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10626 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10627 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10628 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10629 | u32 fp; |
9e2c8475 | 10630 | struct dpll clock; |
dccbea3b | 10631 | int port_clock; |
da4a1efa | 10632 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10633 | |
10634 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10635 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10636 | else |
293623f7 | 10637 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10638 | |
10639 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10640 | if (IS_PINEVIEW(dev)) { |
10641 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10642 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10643 | } else { |
10644 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10645 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10646 | } | |
10647 | ||
a6c45cf0 | 10648 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10649 | if (IS_PINEVIEW(dev)) |
10650 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10651 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10652 | else |
10653 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10654 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10655 | ||
10656 | switch (dpll & DPLL_MODE_MASK) { | |
10657 | case DPLLB_MODE_DAC_SERIAL: | |
10658 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10659 | 5 : 10; | |
10660 | break; | |
10661 | case DPLLB_MODE_LVDS: | |
10662 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10663 | 7 : 14; | |
10664 | break; | |
10665 | default: | |
28c97730 | 10666 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10667 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10668 | return; |
79e53945 JB |
10669 | } |
10670 | ||
ac58c3f0 | 10671 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10672 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10673 | else |
dccbea3b | 10674 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10675 | } else { |
0fb58223 | 10676 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10677 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10678 | |
10679 | if (is_lvds) { | |
10680 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10681 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10682 | |
10683 | if (lvds & LVDS_CLKB_POWER_UP) | |
10684 | clock.p2 = 7; | |
10685 | else | |
10686 | clock.p2 = 14; | |
79e53945 JB |
10687 | } else { |
10688 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10689 | clock.p1 = 2; | |
10690 | else { | |
10691 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10692 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10693 | } | |
10694 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10695 | clock.p2 = 4; | |
10696 | else | |
10697 | clock.p2 = 2; | |
79e53945 | 10698 | } |
da4a1efa | 10699 | |
dccbea3b | 10700 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10701 | } |
10702 | ||
18442d08 VS |
10703 | /* |
10704 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10705 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10706 | * encoder's get_config() function. |
10707 | */ | |
dccbea3b | 10708 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10709 | } |
10710 | ||
6878da05 VS |
10711 | int intel_dotclock_calculate(int link_freq, |
10712 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10713 | { |
f1f644dc JB |
10714 | /* |
10715 | * The calculation for the data clock is: | |
1041a02f | 10716 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10717 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10718 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10719 | * |
10720 | * and the link clock is simpler: | |
1041a02f | 10721 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10722 | */ |
10723 | ||
6878da05 VS |
10724 | if (!m_n->link_n) |
10725 | return 0; | |
f1f644dc | 10726 | |
6878da05 VS |
10727 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10728 | } | |
f1f644dc | 10729 | |
18442d08 | 10730 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10731 | struct intel_crtc_state *pipe_config) |
6878da05 | 10732 | { |
e3b247da | 10733 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10734 | |
18442d08 VS |
10735 | /* read out port_clock from the DPLL */ |
10736 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10737 | |
f1f644dc | 10738 | /* |
e3b247da VS |
10739 | * In case there is an active pipe without active ports, |
10740 | * we may need some idea for the dotclock anyway. | |
10741 | * Calculate one based on the FDI configuration. | |
79e53945 | 10742 | */ |
2d112de7 | 10743 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10744 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10745 | &pipe_config->fdi_m_n); |
79e53945 JB |
10746 | } |
10747 | ||
10748 | /** Returns the currently programmed mode of the given pipe. */ | |
10749 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10750 | struct drm_crtc *crtc) | |
10751 | { | |
548f245b | 10752 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10753 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10754 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10755 | struct drm_display_mode *mode; |
3f36b937 | 10756 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10757 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10758 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10759 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10760 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10761 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10762 | |
10763 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10764 | if (!mode) | |
10765 | return NULL; | |
10766 | ||
3f36b937 TU |
10767 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10768 | if (!pipe_config) { | |
10769 | kfree(mode); | |
10770 | return NULL; | |
10771 | } | |
10772 | ||
f1f644dc JB |
10773 | /* |
10774 | * Construct a pipe_config sufficient for getting the clock info | |
10775 | * back out of crtc_clock_get. | |
10776 | * | |
10777 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10778 | * to use a real value here instead. | |
10779 | */ | |
3f36b937 TU |
10780 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10781 | pipe_config->pixel_multiplier = 1; | |
10782 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10783 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10784 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10785 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10786 | ||
10787 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10788 | mode->hdisplay = (htot & 0xffff) + 1; |
10789 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10790 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10791 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10792 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10793 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10794 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10795 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10796 | ||
10797 | drm_mode_set_name(mode); | |
79e53945 | 10798 | |
3f36b937 TU |
10799 | kfree(pipe_config); |
10800 | ||
79e53945 JB |
10801 | return mode; |
10802 | } | |
10803 | ||
7d993739 | 10804 | void intel_mark_busy(struct drm_i915_private *dev_priv) |
f047e395 | 10805 | { |
f62a0076 CW |
10806 | if (dev_priv->mm.busy) |
10807 | return; | |
10808 | ||
43694d69 | 10809 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10810 | i915_update_gfx_val(dev_priv); |
7d993739 | 10811 | if (INTEL_GEN(dev_priv) >= 6) |
43cf3bf0 | 10812 | gen6_rps_busy(dev_priv); |
f62a0076 | 10813 | dev_priv->mm.busy = true; |
f047e395 CW |
10814 | } |
10815 | ||
7d993739 | 10816 | void intel_mark_idle(struct drm_i915_private *dev_priv) |
652c393a | 10817 | { |
f62a0076 CW |
10818 | if (!dev_priv->mm.busy) |
10819 | return; | |
10820 | ||
10821 | dev_priv->mm.busy = false; | |
10822 | ||
7d993739 TU |
10823 | if (INTEL_GEN(dev_priv) >= 6) |
10824 | gen6_rps_idle(dev_priv); | |
bb4cdd53 | 10825 | |
43694d69 | 10826 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10827 | } |
10828 | ||
79e53945 JB |
10829 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10830 | { | |
10831 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10832 | struct drm_device *dev = crtc->dev; |
10833 | struct intel_unpin_work *work; | |
67e77c5a | 10834 | |
5e2d7afc | 10835 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10836 | work = intel_crtc->unpin_work; |
10837 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10838 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10839 | |
10840 | if (work) { | |
10841 | cancel_work_sync(&work->work); | |
10842 | kfree(work); | |
10843 | } | |
79e53945 JB |
10844 | |
10845 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10846 | |
79e53945 JB |
10847 | kfree(intel_crtc); |
10848 | } | |
10849 | ||
6b95a207 KH |
10850 | static void intel_unpin_work_fn(struct work_struct *__work) |
10851 | { | |
10852 | struct intel_unpin_work *work = | |
10853 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10854 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10855 | struct drm_device *dev = crtc->base.dev; | |
10856 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10857 | |
b4a98e57 | 10858 | mutex_lock(&dev->struct_mutex); |
3465c580 | 10859 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); |
05394f39 | 10860 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10861 | |
f06cc1b9 | 10862 | if (work->flip_queued_req) |
146d84f0 | 10863 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10864 | mutex_unlock(&dev->struct_mutex); |
10865 | ||
a9ff8714 | 10866 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 10867 | intel_fbc_post_update(crtc); |
89ed88ba | 10868 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10869 | |
a9ff8714 VS |
10870 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10871 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10872 | |
6b95a207 KH |
10873 | kfree(work); |
10874 | } | |
10875 | ||
91d14251 | 10876 | static void do_intel_finish_page_flip(struct drm_i915_private *dev_priv, |
49b14a5c | 10877 | struct drm_crtc *crtc) |
6b95a207 | 10878 | { |
91d14251 | 10879 | struct drm_device *dev = dev_priv->dev; |
6b95a207 KH |
10880 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10881 | struct intel_unpin_work *work; | |
6b95a207 KH |
10882 | unsigned long flags; |
10883 | ||
10884 | /* Ignore early vblank irqs */ | |
10885 | if (intel_crtc == NULL) | |
10886 | return; | |
10887 | ||
f326038a DV |
10888 | /* |
10889 | * This is called both by irq handlers and the reset code (to complete | |
10890 | * lost pageflips) so needs the full irqsave spinlocks. | |
10891 | */ | |
6b95a207 KH |
10892 | spin_lock_irqsave(&dev->event_lock, flags); |
10893 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10894 | |
10895 | /* Ensure we don't miss a work->pending update ... */ | |
10896 | smp_rmb(); | |
10897 | ||
10898 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10899 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10900 | return; | |
10901 | } | |
10902 | ||
d6bbafa1 | 10903 | page_flip_completed(intel_crtc); |
0af7e4df | 10904 | |
6b95a207 | 10905 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10906 | } |
10907 | ||
91d14251 | 10908 | void intel_finish_page_flip(struct drm_i915_private *dev_priv, int pipe) |
1afe3e9d | 10909 | { |
1afe3e9d JB |
10910 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10911 | ||
91d14251 | 10912 | do_intel_finish_page_flip(dev_priv, crtc); |
1afe3e9d JB |
10913 | } |
10914 | ||
91d14251 | 10915 | void intel_finish_page_flip_plane(struct drm_i915_private *dev_priv, int plane) |
1afe3e9d | 10916 | { |
1afe3e9d JB |
10917 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10918 | ||
91d14251 | 10919 | do_intel_finish_page_flip(dev_priv, crtc); |
1afe3e9d JB |
10920 | } |
10921 | ||
75f7f3ec VS |
10922 | /* Is 'a' after or equal to 'b'? */ |
10923 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10924 | { | |
10925 | return !((a - b) & 0x80000000); | |
10926 | } | |
10927 | ||
10928 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10929 | { | |
10930 | struct drm_device *dev = crtc->base.dev; | |
10931 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c19ae989 | 10932 | unsigned reset_counter; |
75f7f3ec | 10933 | |
c19ae989 | 10934 | reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
7f1847eb | 10935 | if (crtc->reset_counter != reset_counter) |
bdfa7542 VS |
10936 | return true; |
10937 | ||
75f7f3ec VS |
10938 | /* |
10939 | * The relevant registers doen't exist on pre-ctg. | |
10940 | * As the flip done interrupt doesn't trigger for mmio | |
10941 | * flips on gmch platforms, a flip count check isn't | |
10942 | * really needed there. But since ctg has the registers, | |
10943 | * include it in the check anyway. | |
10944 | */ | |
10945 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10946 | return true; | |
10947 | ||
e8861675 ML |
10948 | /* |
10949 | * BDW signals flip done immediately if the plane | |
10950 | * is disabled, even if the plane enable is already | |
10951 | * armed to occur at the next vblank :( | |
10952 | */ | |
10953 | ||
75f7f3ec VS |
10954 | /* |
10955 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10956 | * used the same base address. In that case the mmio flip might | |
10957 | * have completed, but the CS hasn't even executed the flip yet. | |
10958 | * | |
10959 | * A flip count check isn't enough as the CS might have updated | |
10960 | * the base address just after start of vblank, but before we | |
10961 | * managed to process the interrupt. This means we'd complete the | |
10962 | * CS flip too soon. | |
10963 | * | |
10964 | * Combining both checks should get us a good enough result. It may | |
10965 | * still happen that the CS flip has been executed, but has not | |
10966 | * yet actually completed. But in case the base address is the same | |
10967 | * anyway, we don't really care. | |
10968 | */ | |
10969 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10970 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10971 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
10972 | crtc->unpin_work->flip_count); |
10973 | } | |
10974 | ||
91d14251 | 10975 | void intel_prepare_page_flip(struct drm_i915_private *dev_priv, int plane) |
6b95a207 | 10976 | { |
91d14251 | 10977 | struct drm_device *dev = dev_priv->dev; |
6b95a207 KH |
10978 | struct intel_crtc *intel_crtc = |
10979 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10980 | unsigned long flags; | |
10981 | ||
f326038a DV |
10982 | |
10983 | /* | |
10984 | * This is called both by irq handlers and the reset code (to complete | |
10985 | * lost pageflips) so needs the full irqsave spinlocks. | |
10986 | * | |
10987 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10988 | * generate a page-flip completion irq, i.e. every modeset |
10989 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10990 | */ | |
6b95a207 | 10991 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10992 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10993 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10994 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10995 | } | |
10996 | ||
6042639c | 10997 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
10998 | { |
10999 | /* Ensure that the work item is consistent when activating it ... */ | |
11000 | smp_wmb(); | |
6042639c | 11001 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11002 | /* and that it is marked active as soon as the irq could fire. */ |
11003 | smp_wmb(); | |
11004 | } | |
11005 | ||
8c9f3aaf JB |
11006 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11007 | struct drm_crtc *crtc, | |
11008 | struct drm_framebuffer *fb, | |
ed8d1975 | 11009 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11010 | struct drm_i915_gem_request *req, |
ed8d1975 | 11011 | uint32_t flags) |
8c9f3aaf | 11012 | { |
4a570db5 | 11013 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 11014 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11015 | u32 flip_mask; |
11016 | int ret; | |
11017 | ||
5fb9de1a | 11018 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11019 | if (ret) |
4fa62c89 | 11020 | return ret; |
8c9f3aaf JB |
11021 | |
11022 | /* Can't queue multiple flips, so wait for the previous | |
11023 | * one to finish before executing the next. | |
11024 | */ | |
11025 | if (intel_crtc->plane) | |
11026 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11027 | else | |
11028 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
11029 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
11030 | intel_ring_emit(engine, MI_NOOP); | |
11031 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
6d90c952 | 11032 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11033 | intel_ring_emit(engine, fb->pitches[0]); |
11034 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11035 | intel_ring_emit(engine, 0); /* aux display base address, unused */ | |
e7d841ca | 11036 | |
6042639c | 11037 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11038 | return 0; |
8c9f3aaf JB |
11039 | } |
11040 | ||
11041 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11042 | struct drm_crtc *crtc, | |
11043 | struct drm_framebuffer *fb, | |
ed8d1975 | 11044 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11045 | struct drm_i915_gem_request *req, |
ed8d1975 | 11046 | uint32_t flags) |
8c9f3aaf | 11047 | { |
4a570db5 | 11048 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 11049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11050 | u32 flip_mask; |
11051 | int ret; | |
11052 | ||
5fb9de1a | 11053 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11054 | if (ret) |
4fa62c89 | 11055 | return ret; |
8c9f3aaf JB |
11056 | |
11057 | if (intel_crtc->plane) | |
11058 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11059 | else | |
11060 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
11061 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
11062 | intel_ring_emit(engine, MI_NOOP); | |
11063 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | | |
6d90c952 | 11064 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11065 | intel_ring_emit(engine, fb->pitches[0]); |
11066 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11067 | intel_ring_emit(engine, MI_NOOP); | |
6d90c952 | 11068 | |
6042639c | 11069 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11070 | return 0; |
8c9f3aaf JB |
11071 | } |
11072 | ||
11073 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11074 | struct drm_crtc *crtc, | |
11075 | struct drm_framebuffer *fb, | |
ed8d1975 | 11076 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11077 | struct drm_i915_gem_request *req, |
ed8d1975 | 11078 | uint32_t flags) |
8c9f3aaf | 11079 | { |
4a570db5 | 11080 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
11081 | struct drm_i915_private *dev_priv = dev->dev_private; |
11082 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11083 | uint32_t pf, pipesrc; | |
11084 | int ret; | |
11085 | ||
5fb9de1a | 11086 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11087 | if (ret) |
4fa62c89 | 11088 | return ret; |
8c9f3aaf JB |
11089 | |
11090 | /* i965+ uses the linear or tiled offsets from the | |
11091 | * Display Registers (which do not change across a page-flip) | |
11092 | * so we need only reprogram the base address. | |
11093 | */ | |
e2f80391 | 11094 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 11095 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11096 | intel_ring_emit(engine, fb->pitches[0]); |
11097 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset | | |
c2c75131 | 11098 | obj->tiling_mode); |
8c9f3aaf JB |
11099 | |
11100 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11101 | * untested on non-native modes, so ignore it for now. | |
11102 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11103 | */ | |
11104 | pf = 0; | |
11105 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
e2f80391 | 11106 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 11107 | |
6042639c | 11108 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11109 | return 0; |
8c9f3aaf JB |
11110 | } |
11111 | ||
11112 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11113 | struct drm_crtc *crtc, | |
11114 | struct drm_framebuffer *fb, | |
ed8d1975 | 11115 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11116 | struct drm_i915_gem_request *req, |
ed8d1975 | 11117 | uint32_t flags) |
8c9f3aaf | 11118 | { |
4a570db5 | 11119 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
11120 | struct drm_i915_private *dev_priv = dev->dev_private; |
11121 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11122 | uint32_t pf, pipesrc; | |
11123 | int ret; | |
11124 | ||
5fb9de1a | 11125 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11126 | if (ret) |
4fa62c89 | 11127 | return ret; |
8c9f3aaf | 11128 | |
e2f80391 | 11129 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 11130 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11131 | intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); |
11132 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
8c9f3aaf | 11133 | |
dc257cf1 DV |
11134 | /* Contrary to the suggestions in the documentation, |
11135 | * "Enable Panel Fitter" does not seem to be required when page | |
11136 | * flipping with a non-native mode, and worse causes a normal | |
11137 | * modeset to fail. | |
11138 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11139 | */ | |
11140 | pf = 0; | |
8c9f3aaf | 11141 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
e2f80391 | 11142 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 11143 | |
6042639c | 11144 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11145 | return 0; |
8c9f3aaf JB |
11146 | } |
11147 | ||
7c9017e5 JB |
11148 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11149 | struct drm_crtc *crtc, | |
11150 | struct drm_framebuffer *fb, | |
ed8d1975 | 11151 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11152 | struct drm_i915_gem_request *req, |
ed8d1975 | 11153 | uint32_t flags) |
7c9017e5 | 11154 | { |
4a570db5 | 11155 | struct intel_engine_cs *engine = req->engine; |
7c9017e5 | 11156 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11157 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11158 | int len, ret; |
11159 | ||
eba905b2 | 11160 | switch (intel_crtc->plane) { |
cb05d8de DV |
11161 | case PLANE_A: |
11162 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11163 | break; | |
11164 | case PLANE_B: | |
11165 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11166 | break; | |
11167 | case PLANE_C: | |
11168 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11169 | break; | |
11170 | default: | |
11171 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11172 | return -ENODEV; |
cb05d8de DV |
11173 | } |
11174 | ||
ffe74d75 | 11175 | len = 4; |
e2f80391 | 11176 | if (engine->id == RCS) { |
ffe74d75 | 11177 | len += 6; |
f476828a DL |
11178 | /* |
11179 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11180 | * 48bits addresses, and we need a NOOP for the batch size to | |
11181 | * stay even. | |
11182 | */ | |
11183 | if (IS_GEN8(dev)) | |
11184 | len += 2; | |
11185 | } | |
ffe74d75 | 11186 | |
f66fab8e VS |
11187 | /* |
11188 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11189 | * "The full packet must be contained within the same cache line." | |
11190 | * | |
11191 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11192 | * cacheline, if we ever start emitting more commands before | |
11193 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11194 | * then do the cacheline alignment, and finally emit the | |
11195 | * MI_DISPLAY_FLIP. | |
11196 | */ | |
bba09b12 | 11197 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11198 | if (ret) |
4fa62c89 | 11199 | return ret; |
f66fab8e | 11200 | |
5fb9de1a | 11201 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11202 | if (ret) |
4fa62c89 | 11203 | return ret; |
7c9017e5 | 11204 | |
ffe74d75 CW |
11205 | /* Unmask the flip-done completion message. Note that the bspec says that |
11206 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11207 | * more than one flip event at any time (or ensure that one flip message | |
11208 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11209 | * Experimentation says that BCS works despite DERRMR masking all | |
11210 | * flip-done completion events and that unmasking all planes at once | |
11211 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11212 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11213 | */ | |
e2f80391 TU |
11214 | if (engine->id == RCS) { |
11215 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
11216 | intel_ring_emit_reg(engine, DERRMR); | |
11217 | intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11218 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11219 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11220 | if (IS_GEN8(dev)) |
e2f80391 | 11221 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11222 | MI_SRM_LRM_GLOBAL_GTT); |
11223 | else | |
e2f80391 | 11224 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM | |
f476828a | 11225 | MI_SRM_LRM_GLOBAL_GTT); |
e2f80391 TU |
11226 | intel_ring_emit_reg(engine, DERRMR); |
11227 | intel_ring_emit(engine, engine->scratch.gtt_offset + 256); | |
f476828a | 11228 | if (IS_GEN8(dev)) { |
e2f80391 TU |
11229 | intel_ring_emit(engine, 0); |
11230 | intel_ring_emit(engine, MI_NOOP); | |
f476828a | 11231 | } |
ffe74d75 CW |
11232 | } |
11233 | ||
e2f80391 TU |
11234 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); |
11235 | intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); | |
11236 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11237 | intel_ring_emit(engine, (MI_NOOP)); | |
e7d841ca | 11238 | |
6042639c | 11239 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11240 | return 0; |
7c9017e5 JB |
11241 | } |
11242 | ||
0bc40be8 | 11243 | static bool use_mmio_flip(struct intel_engine_cs *engine, |
84c33a64 SG |
11244 | struct drm_i915_gem_object *obj) |
11245 | { | |
11246 | /* | |
11247 | * This is not being used for older platforms, because | |
11248 | * non-availability of flip done interrupt forces us to use | |
11249 | * CS flips. Older platforms derive flip done using some clever | |
11250 | * tricks involving the flip_pending status bits and vblank irqs. | |
11251 | * So using MMIO flips there would disrupt this mechanism. | |
11252 | */ | |
11253 | ||
0bc40be8 | 11254 | if (engine == NULL) |
8e09bf83 CW |
11255 | return true; |
11256 | ||
c033666a | 11257 | if (INTEL_GEN(engine->i915) < 5) |
84c33a64 SG |
11258 | return false; |
11259 | ||
11260 | if (i915.use_mmio_flip < 0) | |
11261 | return false; | |
11262 | else if (i915.use_mmio_flip > 0) | |
11263 | return true; | |
14bf993e OM |
11264 | else if (i915.enable_execlists) |
11265 | return true; | |
fd8e058a AG |
11266 | else if (obj->base.dma_buf && |
11267 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11268 | false)) | |
11269 | return true; | |
84c33a64 | 11270 | else |
666796da | 11271 | return engine != i915_gem_request_get_engine(obj->last_write_req); |
84c33a64 SG |
11272 | } |
11273 | ||
6042639c | 11274 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11275 | unsigned int rotation, |
6042639c | 11276 | struct intel_unpin_work *work) |
ff944564 DL |
11277 | { |
11278 | struct drm_device *dev = intel_crtc->base.dev; | |
11279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11280 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11281 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11282 | u32 ctl, stride, tile_height; |
ff944564 DL |
11283 | |
11284 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11285 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11286 | switch (fb->modifier[0]) { |
11287 | case DRM_FORMAT_MOD_NONE: | |
11288 | break; | |
11289 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11290 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11291 | break; |
11292 | case I915_FORMAT_MOD_Y_TILED: | |
11293 | ctl |= PLANE_CTL_TILED_Y; | |
11294 | break; | |
11295 | case I915_FORMAT_MOD_Yf_TILED: | |
11296 | ctl |= PLANE_CTL_TILED_YF; | |
11297 | break; | |
11298 | default: | |
11299 | MISSING_CASE(fb->modifier[0]); | |
11300 | } | |
ff944564 DL |
11301 | |
11302 | /* | |
11303 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11304 | * linear buffers or in number of tiles for tiled buffers. | |
11305 | */ | |
86efe24a TU |
11306 | if (intel_rotation_90_or_270(rotation)) { |
11307 | /* stride = Surface height in tiles */ | |
832be82f | 11308 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11309 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11310 | } else { | |
11311 | stride = fb->pitches[0] / | |
7b49f948 VS |
11312 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11313 | fb->pixel_format); | |
86efe24a | 11314 | } |
ff944564 DL |
11315 | |
11316 | /* | |
11317 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11318 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11319 | */ | |
11320 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11321 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11322 | ||
6042639c | 11323 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11324 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11325 | } | |
11326 | ||
6042639c CW |
11327 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11328 | struct intel_unpin_work *work) | |
84c33a64 SG |
11329 | { |
11330 | struct drm_device *dev = intel_crtc->base.dev; | |
11331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11332 | struct intel_framebuffer *intel_fb = | |
11333 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11334 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11335 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11336 | u32 dspcntr; |
84c33a64 | 11337 | |
84c33a64 SG |
11338 | dspcntr = I915_READ(reg); |
11339 | ||
c5d97472 DL |
11340 | if (obj->tiling_mode != I915_TILING_NONE) |
11341 | dspcntr |= DISPPLANE_TILED; | |
11342 | else | |
11343 | dspcntr &= ~DISPPLANE_TILED; | |
11344 | ||
84c33a64 SG |
11345 | I915_WRITE(reg, dspcntr); |
11346 | ||
6042639c | 11347 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11348 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11349 | } |
11350 | ||
11351 | /* | |
11352 | * XXX: This is the temporary way to update the plane registers until we get | |
11353 | * around to using the usual plane update functions for MMIO flips | |
11354 | */ | |
6042639c | 11355 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11356 | { |
6042639c CW |
11357 | struct intel_crtc *crtc = mmio_flip->crtc; |
11358 | struct intel_unpin_work *work; | |
11359 | ||
11360 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11361 | work = crtc->unpin_work; | |
11362 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11363 | if (work == NULL) | |
11364 | return; | |
ff944564 | 11365 | |
6042639c | 11366 | intel_mark_page_flip_active(work); |
ff944564 | 11367 | |
6042639c | 11368 | intel_pipe_update_start(crtc); |
ff944564 | 11369 | |
6042639c | 11370 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11371 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11372 | else |
11373 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11374 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11375 | |
6042639c | 11376 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11377 | } |
11378 | ||
9362c7c5 | 11379 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11380 | { |
b2cfe0ab CW |
11381 | struct intel_mmio_flip *mmio_flip = |
11382 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11383 | struct intel_framebuffer *intel_fb = |
11384 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11385 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11386 | |
6042639c | 11387 | if (mmio_flip->req) { |
eed29a5b | 11388 | WARN_ON(__i915_wait_request(mmio_flip->req, |
bcafc4e3 CW |
11389 | false, NULL, |
11390 | &mmio_flip->i915->rps.mmioflips)); | |
73db04cf | 11391 | i915_gem_request_unreference(mmio_flip->req); |
6042639c | 11392 | } |
84c33a64 | 11393 | |
fd8e058a AG |
11394 | /* For framebuffer backed by dmabuf, wait for fence */ |
11395 | if (obj->base.dma_buf) | |
11396 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11397 | false, false, | |
11398 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11399 | ||
6042639c | 11400 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11401 | kfree(mmio_flip); |
84c33a64 SG |
11402 | } |
11403 | ||
11404 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11405 | struct drm_crtc *crtc, | |
86efe24a | 11406 | struct drm_i915_gem_object *obj) |
84c33a64 | 11407 | { |
b2cfe0ab CW |
11408 | struct intel_mmio_flip *mmio_flip; |
11409 | ||
11410 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11411 | if (mmio_flip == NULL) | |
11412 | return -ENOMEM; | |
84c33a64 | 11413 | |
bcafc4e3 | 11414 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11415 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11416 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11417 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11418 | |
b2cfe0ab CW |
11419 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11420 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11421 | |
84c33a64 SG |
11422 | return 0; |
11423 | } | |
11424 | ||
8c9f3aaf JB |
11425 | static int intel_default_queue_flip(struct drm_device *dev, |
11426 | struct drm_crtc *crtc, | |
11427 | struct drm_framebuffer *fb, | |
ed8d1975 | 11428 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11429 | struct drm_i915_gem_request *req, |
ed8d1975 | 11430 | uint32_t flags) |
8c9f3aaf JB |
11431 | { |
11432 | return -ENODEV; | |
11433 | } | |
11434 | ||
d6bbafa1 CW |
11435 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11436 | struct drm_crtc *crtc) | |
11437 | { | |
11438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11439 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11440 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11441 | u32 addr; | |
11442 | ||
11443 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11444 | return true; | |
11445 | ||
908565c2 CW |
11446 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11447 | return false; | |
11448 | ||
d6bbafa1 CW |
11449 | if (!work->enable_stall_check) |
11450 | return false; | |
11451 | ||
11452 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11453 | if (work->flip_queued_req && |
11454 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11455 | return false; |
11456 | ||
1e3feefd | 11457 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11458 | } |
11459 | ||
1e3feefd | 11460 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11461 | return false; |
11462 | ||
11463 | /* Potential stall - if we see that the flip has happened, | |
11464 | * assume a missed interrupt. */ | |
11465 | if (INTEL_INFO(dev)->gen >= 4) | |
11466 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11467 | else | |
11468 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11469 | ||
11470 | /* There is a potential issue here with a false positive after a flip | |
11471 | * to the same address. We could address this by checking for a | |
11472 | * non-incrementing frame counter. | |
11473 | */ | |
11474 | return addr == work->gtt_offset; | |
11475 | } | |
11476 | ||
91d14251 | 11477 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) |
d6bbafa1 | 11478 | { |
91d14251 | 11479 | struct drm_device *dev = dev_priv->dev; |
d6bbafa1 CW |
11480 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11481 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11482 | struct intel_unpin_work *work; |
f326038a | 11483 | |
6c51d46f | 11484 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11485 | |
11486 | if (crtc == NULL) | |
11487 | return; | |
11488 | ||
f326038a | 11489 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11490 | work = intel_crtc->unpin_work; |
11491 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11492 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11493 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11494 | page_flip_completed(intel_crtc); |
6ad790c0 | 11495 | work = NULL; |
d6bbafa1 | 11496 | } |
6ad790c0 CW |
11497 | if (work != NULL && |
11498 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
91d14251 | 11499 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
f326038a | 11500 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11501 | } |
11502 | ||
6b95a207 KH |
11503 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11504 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11505 | struct drm_pending_vblank_event *event, |
11506 | uint32_t page_flip_flags) | |
6b95a207 KH |
11507 | { |
11508 | struct drm_device *dev = crtc->dev; | |
11509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11510 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11511 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11512 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11513 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11514 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11515 | struct intel_unpin_work *work; |
e2f80391 | 11516 | struct intel_engine_cs *engine; |
cf5d8a46 | 11517 | bool mmio_flip; |
91af127f | 11518 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11519 | int ret; |
6b95a207 | 11520 | |
2ff8fde1 MR |
11521 | /* |
11522 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11523 | * check to be safe. In the future we may enable pageflipping from | |
11524 | * a disabled primary plane. | |
11525 | */ | |
11526 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11527 | return -EBUSY; | |
11528 | ||
e6a595d2 | 11529 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11530 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11531 | return -EINVAL; |
11532 | ||
11533 | /* | |
11534 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11535 | * Note that pitch changes could also affect these register. | |
11536 | */ | |
11537 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11538 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11539 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11540 | return -EINVAL; |
11541 | ||
f900db47 CW |
11542 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11543 | goto out_hang; | |
11544 | ||
b14c5679 | 11545 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11546 | if (work == NULL) |
11547 | return -ENOMEM; | |
11548 | ||
6b95a207 | 11549 | work->event = event; |
b4a98e57 | 11550 | work->crtc = crtc; |
ab8d6675 | 11551 | work->old_fb = old_fb; |
6b95a207 KH |
11552 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11553 | ||
87b6b101 | 11554 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11555 | if (ret) |
11556 | goto free_work; | |
11557 | ||
6b95a207 | 11558 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11559 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11560 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11561 | /* Before declaring the flip queue wedged, check if |
11562 | * the hardware completed the operation behind our backs. | |
11563 | */ | |
11564 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11565 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11566 | page_flip_completed(intel_crtc); | |
11567 | } else { | |
11568 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11569 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11570 | |
d6bbafa1 CW |
11571 | drm_crtc_vblank_put(crtc); |
11572 | kfree(work); | |
11573 | return -EBUSY; | |
11574 | } | |
6b95a207 KH |
11575 | } |
11576 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11577 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11578 | |
b4a98e57 CW |
11579 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11580 | flush_workqueue(dev_priv->wq); | |
11581 | ||
75dfca80 | 11582 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11583 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11584 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11585 | |
f4510a27 | 11586 | crtc->primary->fb = fb; |
afd65eb4 | 11587 | update_state_fb(crtc->primary); |
e8216e50 | 11588 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11589 | |
e1f99ce6 | 11590 | work->pending_flip_obj = obj; |
e1f99ce6 | 11591 | |
89ed88ba CW |
11592 | ret = i915_mutex_lock_interruptible(dev); |
11593 | if (ret) | |
11594 | goto cleanup; | |
11595 | ||
c19ae989 | 11596 | intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
7f1847eb CW |
11597 | if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) { |
11598 | ret = -EIO; | |
11599 | goto cleanup; | |
11600 | } | |
11601 | ||
11602 | atomic_inc(&intel_crtc->unpin_work_count); | |
e1f99ce6 | 11603 | |
75f7f3ec | 11604 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11605 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11606 | |
666a4537 | 11607 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4a570db5 | 11608 | engine = &dev_priv->engine[BCS]; |
ab8d6675 | 11609 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 | 11610 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
e2f80391 | 11611 | engine = NULL; |
48bf5b2d | 11612 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
4a570db5 | 11613 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11614 | } else if (INTEL_INFO(dev)->gen >= 7) { |
666796da | 11615 | engine = i915_gem_request_get_engine(obj->last_write_req); |
e2f80391 | 11616 | if (engine == NULL || engine->id != RCS) |
4a570db5 | 11617 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11618 | } else { |
4a570db5 | 11619 | engine = &dev_priv->engine[RCS]; |
4fa62c89 VS |
11620 | } |
11621 | ||
e2f80391 | 11622 | mmio_flip = use_mmio_flip(engine, obj); |
cf5d8a46 CW |
11623 | |
11624 | /* When using CS flips, we want to emit semaphores between rings. | |
11625 | * However, when using mmio flips we will create a task to do the | |
11626 | * synchronisation, so all we want here is to pin the framebuffer | |
11627 | * into the display plane and skip any waits. | |
11628 | */ | |
7580d774 | 11629 | if (!mmio_flip) { |
e2f80391 | 11630 | ret = i915_gem_object_sync(obj, engine, &request); |
7580d774 ML |
11631 | if (ret) |
11632 | goto cleanup_pending; | |
11633 | } | |
11634 | ||
3465c580 | 11635 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
8c9f3aaf JB |
11636 | if (ret) |
11637 | goto cleanup_pending; | |
6b95a207 | 11638 | |
dedf278c TU |
11639 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11640 | obj, 0); | |
11641 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11642 | |
cf5d8a46 | 11643 | if (mmio_flip) { |
86efe24a | 11644 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11645 | if (ret) |
11646 | goto cleanup_unpin; | |
11647 | ||
f06cc1b9 JH |
11648 | i915_gem_request_assign(&work->flip_queued_req, |
11649 | obj->last_write_req); | |
d6bbafa1 | 11650 | } else { |
6258fbe2 | 11651 | if (!request) { |
e2f80391 | 11652 | request = i915_gem_request_alloc(engine, NULL); |
26827088 DG |
11653 | if (IS_ERR(request)) { |
11654 | ret = PTR_ERR(request); | |
6258fbe2 | 11655 | goto cleanup_unpin; |
26827088 | 11656 | } |
6258fbe2 JH |
11657 | } |
11658 | ||
11659 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11660 | page_flip_flags); |
11661 | if (ret) | |
11662 | goto cleanup_unpin; | |
11663 | ||
6258fbe2 | 11664 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11665 | } |
11666 | ||
91af127f | 11667 | if (request) |
75289874 | 11668 | i915_add_request_no_flush(request); |
91af127f | 11669 | |
1e3feefd | 11670 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11671 | work->enable_stall_check = true; |
4fa62c89 | 11672 | |
ab8d6675 | 11673 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11674 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11675 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11676 | |
a9ff8714 VS |
11677 | intel_frontbuffer_flip_prepare(dev, |
11678 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11679 | |
e5510fac JB |
11680 | trace_i915_flip_request(intel_crtc->plane, obj); |
11681 | ||
6b95a207 | 11682 | return 0; |
96b099fd | 11683 | |
4fa62c89 | 11684 | cleanup_unpin: |
3465c580 | 11685 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); |
8c9f3aaf | 11686 | cleanup_pending: |
0aa498d5 | 11687 | if (!IS_ERR_OR_NULL(request)) |
aa9b7810 | 11688 | i915_add_request_no_flush(request); |
b4a98e57 | 11689 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11690 | mutex_unlock(&dev->struct_mutex); |
11691 | cleanup: | |
f4510a27 | 11692 | crtc->primary->fb = old_fb; |
afd65eb4 | 11693 | update_state_fb(crtc->primary); |
89ed88ba CW |
11694 | |
11695 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11696 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11697 | |
5e2d7afc | 11698 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11699 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11700 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11701 | |
87b6b101 | 11702 | drm_crtc_vblank_put(crtc); |
7317c75e | 11703 | free_work: |
96b099fd CW |
11704 | kfree(work); |
11705 | ||
f900db47 | 11706 | if (ret == -EIO) { |
02e0efb5 ML |
11707 | struct drm_atomic_state *state; |
11708 | struct drm_plane_state *plane_state; | |
11709 | ||
f900db47 | 11710 | out_hang: |
02e0efb5 ML |
11711 | state = drm_atomic_state_alloc(dev); |
11712 | if (!state) | |
11713 | return -ENOMEM; | |
11714 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11715 | ||
11716 | retry: | |
11717 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11718 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11719 | if (!ret) { | |
11720 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11721 | ||
11722 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11723 | if (!ret) | |
11724 | ret = drm_atomic_commit(state); | |
11725 | } | |
11726 | ||
11727 | if (ret == -EDEADLK) { | |
11728 | drm_modeset_backoff(state->acquire_ctx); | |
11729 | drm_atomic_state_clear(state); | |
11730 | goto retry; | |
11731 | } | |
11732 | ||
11733 | if (ret) | |
11734 | drm_atomic_state_free(state); | |
11735 | ||
f0d3dad3 | 11736 | if (ret == 0 && event) { |
5e2d7afc | 11737 | spin_lock_irq(&dev->event_lock); |
560ce1dc | 11738 | drm_crtc_send_vblank_event(crtc, event); |
5e2d7afc | 11739 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11740 | } |
f900db47 | 11741 | } |
96b099fd | 11742 | return ret; |
6b95a207 KH |
11743 | } |
11744 | ||
da20eabd ML |
11745 | |
11746 | /** | |
11747 | * intel_wm_need_update - Check whether watermarks need updating | |
11748 | * @plane: drm plane | |
11749 | * @state: new plane state | |
11750 | * | |
11751 | * Check current plane state versus the new one to determine whether | |
11752 | * watermarks need to be recalculated. | |
11753 | * | |
11754 | * Returns true or false. | |
11755 | */ | |
11756 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11757 | struct drm_plane_state *state) | |
11758 | { | |
d21fbe87 MR |
11759 | struct intel_plane_state *new = to_intel_plane_state(state); |
11760 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11761 | ||
11762 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11763 | if (new->visible != cur->visible) |
11764 | return true; | |
11765 | ||
11766 | if (!cur->base.fb || !new->base.fb) | |
11767 | return false; | |
11768 | ||
11769 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11770 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11771 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11772 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11773 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11774 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11775 | return true; |
7809e5ae | 11776 | |
2791a16c | 11777 | return false; |
7809e5ae MR |
11778 | } |
11779 | ||
d21fbe87 MR |
11780 | static bool needs_scaling(struct intel_plane_state *state) |
11781 | { | |
11782 | int src_w = drm_rect_width(&state->src) >> 16; | |
11783 | int src_h = drm_rect_height(&state->src) >> 16; | |
11784 | int dst_w = drm_rect_width(&state->dst); | |
11785 | int dst_h = drm_rect_height(&state->dst); | |
11786 | ||
11787 | return (src_w != dst_w || src_h != dst_h); | |
11788 | } | |
11789 | ||
da20eabd ML |
11790 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11791 | struct drm_plane_state *plane_state) | |
11792 | { | |
ab1d3a0e | 11793 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11794 | struct drm_crtc *crtc = crtc_state->crtc; |
11795 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11796 | struct drm_plane *plane = plane_state->plane; | |
11797 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11798 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11799 | struct intel_plane_state *old_plane_state = |
11800 | to_intel_plane_state(plane->state); | |
11801 | int idx = intel_crtc->base.base.id, ret; | |
da20eabd ML |
11802 | bool mode_changed = needs_modeset(crtc_state); |
11803 | bool was_crtc_enabled = crtc->state->active; | |
11804 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11805 | bool turn_off, turn_on, visible, was_visible; |
11806 | struct drm_framebuffer *fb = plane_state->fb; | |
11807 | ||
11808 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11809 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11810 | ret = skl_update_scaler_plane( | |
11811 | to_intel_crtc_state(crtc_state), | |
11812 | to_intel_plane_state(plane_state)); | |
11813 | if (ret) | |
11814 | return ret; | |
11815 | } | |
11816 | ||
da20eabd ML |
11817 | was_visible = old_plane_state->visible; |
11818 | visible = to_intel_plane_state(plane_state)->visible; | |
11819 | ||
11820 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11821 | was_visible = false; | |
11822 | ||
35c08f43 ML |
11823 | /* |
11824 | * Visibility is calculated as if the crtc was on, but | |
11825 | * after scaler setup everything depends on it being off | |
11826 | * when the crtc isn't active. | |
f818ffea VS |
11827 | * |
11828 | * FIXME this is wrong for watermarks. Watermarks should also | |
11829 | * be computed as if the pipe would be active. Perhaps move | |
11830 | * per-plane wm computation to the .check_plane() hook, and | |
11831 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
11832 | */ |
11833 | if (!is_crtc_enabled) | |
11834 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11835 | |
11836 | if (!was_visible && !visible) | |
11837 | return 0; | |
11838 | ||
e8861675 ML |
11839 | if (fb != old_plane_state->base.fb) |
11840 | pipe_config->fb_changed = true; | |
11841 | ||
da20eabd ML |
11842 | turn_off = was_visible && (!visible || mode_changed); |
11843 | turn_on = visible && (!was_visible || mode_changed); | |
11844 | ||
11845 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11846 | plane->base.id, fb ? fb->base.id : -1); | |
11847 | ||
11848 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11849 | plane->base.id, was_visible, visible, | |
11850 | turn_off, turn_on, mode_changed); | |
11851 | ||
caed361d VS |
11852 | if (turn_on) { |
11853 | pipe_config->update_wm_pre = true; | |
11854 | ||
11855 | /* must disable cxsr around plane enable/disable */ | |
11856 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11857 | pipe_config->disable_cxsr = true; | |
11858 | } else if (turn_off) { | |
11859 | pipe_config->update_wm_post = true; | |
92826fcd | 11860 | |
852eb00d | 11861 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11862 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11863 | pipe_config->disable_cxsr = true; |
852eb00d | 11864 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
11865 | /* FIXME bollocks */ |
11866 | pipe_config->update_wm_pre = true; | |
11867 | pipe_config->update_wm_post = true; | |
852eb00d | 11868 | } |
da20eabd | 11869 | |
ed4a6a7c | 11870 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
11871 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
11872 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
11873 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
11874 | ||
8be6ca85 | 11875 | if (visible || was_visible) |
cd202f69 | 11876 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 11877 | |
31ae71fc ML |
11878 | /* |
11879 | * WaCxSRDisabledForSpriteScaling:ivb | |
11880 | * | |
11881 | * cstate->update_wm was already set above, so this flag will | |
11882 | * take effect when we commit and program watermarks. | |
11883 | */ | |
11884 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
11885 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11886 | !needs_scaling(old_plane_state)) | |
11887 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 11888 | |
da20eabd ML |
11889 | return 0; |
11890 | } | |
11891 | ||
6d3a1ce7 ML |
11892 | static bool encoders_cloneable(const struct intel_encoder *a, |
11893 | const struct intel_encoder *b) | |
11894 | { | |
11895 | /* masks could be asymmetric, so check both ways */ | |
11896 | return a == b || (a->cloneable & (1 << b->type) && | |
11897 | b->cloneable & (1 << a->type)); | |
11898 | } | |
11899 | ||
11900 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11901 | struct intel_crtc *crtc, | |
11902 | struct intel_encoder *encoder) | |
11903 | { | |
11904 | struct intel_encoder *source_encoder; | |
11905 | struct drm_connector *connector; | |
11906 | struct drm_connector_state *connector_state; | |
11907 | int i; | |
11908 | ||
11909 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11910 | if (connector_state->crtc != &crtc->base) | |
11911 | continue; | |
11912 | ||
11913 | source_encoder = | |
11914 | to_intel_encoder(connector_state->best_encoder); | |
11915 | if (!encoders_cloneable(encoder, source_encoder)) | |
11916 | return false; | |
11917 | } | |
11918 | ||
11919 | return true; | |
11920 | } | |
11921 | ||
11922 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11923 | struct intel_crtc *crtc) | |
11924 | { | |
11925 | struct intel_encoder *encoder; | |
11926 | struct drm_connector *connector; | |
11927 | struct drm_connector_state *connector_state; | |
11928 | int i; | |
11929 | ||
11930 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11931 | if (connector_state->crtc != &crtc->base) | |
11932 | continue; | |
11933 | ||
11934 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11935 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11936 | return false; | |
11937 | } | |
11938 | ||
11939 | return true; | |
11940 | } | |
11941 | ||
11942 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11943 | struct drm_crtc_state *crtc_state) | |
11944 | { | |
cf5a15be | 11945 | struct drm_device *dev = crtc->dev; |
ad421372 | 11946 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11948 | struct intel_crtc_state *pipe_config = |
11949 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11950 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11951 | int ret; |
6d3a1ce7 ML |
11952 | bool mode_changed = needs_modeset(crtc_state); |
11953 | ||
11954 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11955 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11956 | return -EINVAL; | |
11957 | } | |
11958 | ||
852eb00d | 11959 | if (mode_changed && !crtc_state->active) |
caed361d | 11960 | pipe_config->update_wm_post = true; |
eddfcbcd | 11961 | |
ad421372 ML |
11962 | if (mode_changed && crtc_state->enable && |
11963 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 11964 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
11965 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
11966 | pipe_config); | |
11967 | if (ret) | |
11968 | return ret; | |
11969 | } | |
11970 | ||
82cf435b LL |
11971 | if (crtc_state->color_mgmt_changed) { |
11972 | ret = intel_color_check(crtc, crtc_state); | |
11973 | if (ret) | |
11974 | return ret; | |
11975 | } | |
11976 | ||
e435d6e5 | 11977 | ret = 0; |
86c8bbbe | 11978 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 11979 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
11980 | if (ret) { |
11981 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
11982 | return ret; | |
11983 | } | |
11984 | } | |
11985 | ||
11986 | if (dev_priv->display.compute_intermediate_wm && | |
11987 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
11988 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
11989 | return 0; | |
11990 | ||
11991 | /* | |
11992 | * Calculate 'intermediate' watermarks that satisfy both the | |
11993 | * old state and the new state. We can program these | |
11994 | * immediately. | |
11995 | */ | |
11996 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
11997 | intel_crtc, | |
11998 | pipe_config); | |
11999 | if (ret) { | |
12000 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12001 | return ret; |
ed4a6a7c | 12002 | } |
86c8bbbe MR |
12003 | } |
12004 | ||
e435d6e5 ML |
12005 | if (INTEL_INFO(dev)->gen >= 9) { |
12006 | if (mode_changed) | |
12007 | ret = skl_update_scaler_crtc(pipe_config); | |
12008 | ||
12009 | if (!ret) | |
12010 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12011 | pipe_config); | |
12012 | } | |
12013 | ||
12014 | return ret; | |
6d3a1ce7 ML |
12015 | } |
12016 | ||
65b38e0d | 12017 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12018 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
ea2c67bb MR |
12019 | .atomic_begin = intel_begin_crtc_commit, |
12020 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12021 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12022 | }; |
12023 | ||
d29b2f9d ACO |
12024 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12025 | { | |
12026 | struct intel_connector *connector; | |
12027 | ||
12028 | for_each_intel_connector(dev, connector) { | |
12029 | if (connector->base.encoder) { | |
12030 | connector->base.state->best_encoder = | |
12031 | connector->base.encoder; | |
12032 | connector->base.state->crtc = | |
12033 | connector->base.encoder->crtc; | |
12034 | } else { | |
12035 | connector->base.state->best_encoder = NULL; | |
12036 | connector->base.state->crtc = NULL; | |
12037 | } | |
12038 | } | |
12039 | } | |
12040 | ||
050f7aeb | 12041 | static void |
eba905b2 | 12042 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12043 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12044 | { |
12045 | int bpp = pipe_config->pipe_bpp; | |
12046 | ||
12047 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12048 | connector->base.base.id, | |
c23cc417 | 12049 | connector->base.name); |
050f7aeb DV |
12050 | |
12051 | /* Don't use an invalid EDID bpc value */ | |
12052 | if (connector->base.display_info.bpc && | |
12053 | connector->base.display_info.bpc * 3 < bpp) { | |
12054 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12055 | bpp, connector->base.display_info.bpc*3); | |
12056 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12057 | } | |
12058 | ||
013dd9e0 JN |
12059 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12060 | if (connector->base.display_info.bpc == 0) { | |
12061 | int type = connector->base.connector_type; | |
12062 | int clamp_bpp = 24; | |
12063 | ||
12064 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12065 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12066 | type == DRM_MODE_CONNECTOR_eDP) | |
12067 | clamp_bpp = 18; | |
12068 | ||
12069 | if (bpp > clamp_bpp) { | |
12070 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12071 | bpp, clamp_bpp); | |
12072 | pipe_config->pipe_bpp = clamp_bpp; | |
12073 | } | |
050f7aeb DV |
12074 | } |
12075 | } | |
12076 | ||
4e53c2e0 | 12077 | static int |
050f7aeb | 12078 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12079 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12080 | { |
050f7aeb | 12081 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12082 | struct drm_atomic_state *state; |
da3ced29 ACO |
12083 | struct drm_connector *connector; |
12084 | struct drm_connector_state *connector_state; | |
1486017f | 12085 | int bpp, i; |
4e53c2e0 | 12086 | |
666a4537 | 12087 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12088 | bpp = 10*3; |
d328c9d7 DV |
12089 | else if (INTEL_INFO(dev)->gen >= 5) |
12090 | bpp = 12*3; | |
12091 | else | |
12092 | bpp = 8*3; | |
12093 | ||
4e53c2e0 | 12094 | |
4e53c2e0 DV |
12095 | pipe_config->pipe_bpp = bpp; |
12096 | ||
1486017f ACO |
12097 | state = pipe_config->base.state; |
12098 | ||
4e53c2e0 | 12099 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12100 | for_each_connector_in_state(state, connector, connector_state, i) { |
12101 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12102 | continue; |
12103 | ||
da3ced29 ACO |
12104 | connected_sink_compute_bpp(to_intel_connector(connector), |
12105 | pipe_config); | |
4e53c2e0 DV |
12106 | } |
12107 | ||
12108 | return bpp; | |
12109 | } | |
12110 | ||
644db711 DV |
12111 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12112 | { | |
12113 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12114 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12115 | mode->crtc_clock, |
644db711 DV |
12116 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12117 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12118 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12119 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12120 | } | |
12121 | ||
c0b03411 | 12122 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12123 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12124 | const char *context) |
12125 | { | |
6a60cd87 CK |
12126 | struct drm_device *dev = crtc->base.dev; |
12127 | struct drm_plane *plane; | |
12128 | struct intel_plane *intel_plane; | |
12129 | struct intel_plane_state *state; | |
12130 | struct drm_framebuffer *fb; | |
12131 | ||
12132 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12133 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 | 12134 | |
da205630 | 12135 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12136 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12137 | pipe_config->pipe_bpp, pipe_config->dither); | |
12138 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12139 | pipe_config->has_pch_encoder, | |
12140 | pipe_config->fdi_lanes, | |
12141 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12142 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12143 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12144 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12145 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12146 | pipe_config->lane_count, |
eb14cb74 VS |
12147 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12148 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12149 | pipe_config->dp_m_n.tu); | |
b95af8be | 12150 | |
90a6b7b0 | 12151 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12152 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12153 | pipe_config->lane_count, |
b95af8be VK |
12154 | pipe_config->dp_m2_n2.gmch_m, |
12155 | pipe_config->dp_m2_n2.gmch_n, | |
12156 | pipe_config->dp_m2_n2.link_m, | |
12157 | pipe_config->dp_m2_n2.link_n, | |
12158 | pipe_config->dp_m2_n2.tu); | |
12159 | ||
55072d19 DV |
12160 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12161 | pipe_config->has_audio, | |
12162 | pipe_config->has_infoframe); | |
12163 | ||
c0b03411 | 12164 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12165 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12166 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12167 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12168 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12169 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12170 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12171 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12172 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12173 | crtc->num_scalers, | |
12174 | pipe_config->scaler_state.scaler_users, | |
12175 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12176 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12177 | pipe_config->gmch_pfit.control, | |
12178 | pipe_config->gmch_pfit.pgm_ratios, | |
12179 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12180 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12181 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12182 | pipe_config->pch_pfit.size, |
12183 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12184 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12185 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12186 | |
415ff0f6 | 12187 | if (IS_BROXTON(dev)) { |
05712c15 | 12188 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12189 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12190 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12191 | pipe_config->ddi_pll_sel, |
12192 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12193 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12194 | pipe_config->dpll_hw_state.pll0, |
12195 | pipe_config->dpll_hw_state.pll1, | |
12196 | pipe_config->dpll_hw_state.pll2, | |
12197 | pipe_config->dpll_hw_state.pll3, | |
12198 | pipe_config->dpll_hw_state.pll6, | |
12199 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12200 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12201 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12202 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12203 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12204 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12205 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12206 | pipe_config->ddi_pll_sel, | |
12207 | pipe_config->dpll_hw_state.ctrl1, | |
12208 | pipe_config->dpll_hw_state.cfgcr1, | |
12209 | pipe_config->dpll_hw_state.cfgcr2); | |
12210 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12211 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12212 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12213 | pipe_config->dpll_hw_state.wrpll, |
12214 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12215 | } else { |
12216 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12217 | "fp0: 0x%x, fp1: 0x%x\n", | |
12218 | pipe_config->dpll_hw_state.dpll, | |
12219 | pipe_config->dpll_hw_state.dpll_md, | |
12220 | pipe_config->dpll_hw_state.fp0, | |
12221 | pipe_config->dpll_hw_state.fp1); | |
12222 | } | |
12223 | ||
6a60cd87 CK |
12224 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12225 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12226 | intel_plane = to_intel_plane(plane); | |
12227 | if (intel_plane->pipe != crtc->pipe) | |
12228 | continue; | |
12229 | ||
12230 | state = to_intel_plane_state(plane->state); | |
12231 | fb = state->base.fb; | |
12232 | if (!fb) { | |
12233 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12234 | "disabled, scaler_id = %d\n", | |
12235 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12236 | plane->base.id, intel_plane->pipe, | |
12237 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12238 | drm_plane_index(plane), state->scaler_id); | |
12239 | continue; | |
12240 | } | |
12241 | ||
12242 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12243 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12244 | plane->base.id, intel_plane->pipe, | |
12245 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12246 | drm_plane_index(plane)); | |
12247 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12248 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12249 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12250 | state->scaler_id, | |
12251 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12252 | drm_rect_width(&state->src) >> 16, | |
12253 | drm_rect_height(&state->src) >> 16, | |
12254 | state->dst.x1, state->dst.y1, | |
12255 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12256 | } | |
c0b03411 DV |
12257 | } |
12258 | ||
5448a00d | 12259 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12260 | { |
5448a00d | 12261 | struct drm_device *dev = state->dev; |
da3ced29 | 12262 | struct drm_connector *connector; |
00f0b378 VS |
12263 | unsigned int used_ports = 0; |
12264 | ||
12265 | /* | |
12266 | * Walk the connector list instead of the encoder | |
12267 | * list to detect the problem on ddi platforms | |
12268 | * where there's just one encoder per digital port. | |
12269 | */ | |
0bff4858 VS |
12270 | drm_for_each_connector(connector, dev) { |
12271 | struct drm_connector_state *connector_state; | |
12272 | struct intel_encoder *encoder; | |
12273 | ||
12274 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12275 | if (!connector_state) | |
12276 | connector_state = connector->state; | |
12277 | ||
5448a00d | 12278 | if (!connector_state->best_encoder) |
00f0b378 VS |
12279 | continue; |
12280 | ||
5448a00d ACO |
12281 | encoder = to_intel_encoder(connector_state->best_encoder); |
12282 | ||
12283 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12284 | |
12285 | switch (encoder->type) { | |
12286 | unsigned int port_mask; | |
12287 | case INTEL_OUTPUT_UNKNOWN: | |
12288 | if (WARN_ON(!HAS_DDI(dev))) | |
12289 | break; | |
12290 | case INTEL_OUTPUT_DISPLAYPORT: | |
12291 | case INTEL_OUTPUT_HDMI: | |
12292 | case INTEL_OUTPUT_EDP: | |
12293 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12294 | ||
12295 | /* the same port mustn't appear more than once */ | |
12296 | if (used_ports & port_mask) | |
12297 | return false; | |
12298 | ||
12299 | used_ports |= port_mask; | |
12300 | default: | |
12301 | break; | |
12302 | } | |
12303 | } | |
12304 | ||
12305 | return true; | |
12306 | } | |
12307 | ||
83a57153 ACO |
12308 | static void |
12309 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12310 | { | |
12311 | struct drm_crtc_state tmp_state; | |
663a3640 | 12312 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12313 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12314 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12315 | uint32_t ddi_pll_sel; |
c4e2d043 | 12316 | bool force_thru; |
83a57153 | 12317 | |
7546a384 ACO |
12318 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12319 | * kzalloc'd. Code that depends on any field being zero should be | |
12320 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12321 | * only fields that are know to not cause problems are preserved. */ | |
12322 | ||
83a57153 | 12323 | tmp_state = crtc_state->base; |
663a3640 | 12324 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12325 | shared_dpll = crtc_state->shared_dpll; |
12326 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12327 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12328 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12329 | |
83a57153 | 12330 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12331 | |
83a57153 | 12332 | crtc_state->base = tmp_state; |
663a3640 | 12333 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12334 | crtc_state->shared_dpll = shared_dpll; |
12335 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12336 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12337 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12338 | } |
12339 | ||
548ee15b | 12340 | static int |
b8cecdf5 | 12341 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12342 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12343 | { |
b359283a | 12344 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12345 | struct intel_encoder *encoder; |
da3ced29 | 12346 | struct drm_connector *connector; |
0b901879 | 12347 | struct drm_connector_state *connector_state; |
d328c9d7 | 12348 | int base_bpp, ret = -EINVAL; |
0b901879 | 12349 | int i; |
e29c22c0 | 12350 | bool retry = true; |
ee7b9f93 | 12351 | |
83a57153 | 12352 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12353 | |
e143a21c DV |
12354 | pipe_config->cpu_transcoder = |
12355 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12356 | |
2960bc9c ID |
12357 | /* |
12358 | * Sanitize sync polarity flags based on requested ones. If neither | |
12359 | * positive or negative polarity is requested, treat this as meaning | |
12360 | * negative polarity. | |
12361 | */ | |
2d112de7 | 12362 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12363 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12364 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12365 | |
2d112de7 | 12366 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12367 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12368 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12369 | |
d328c9d7 DV |
12370 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12371 | pipe_config); | |
12372 | if (base_bpp < 0) | |
4e53c2e0 DV |
12373 | goto fail; |
12374 | ||
e41a56be VS |
12375 | /* |
12376 | * Determine the real pipe dimensions. Note that stereo modes can | |
12377 | * increase the actual pipe size due to the frame doubling and | |
12378 | * insertion of additional space for blanks between the frame. This | |
12379 | * is stored in the crtc timings. We use the requested mode to do this | |
12380 | * computation to clearly distinguish it from the adjusted mode, which | |
12381 | * can be changed by the connectors in the below retry loop. | |
12382 | */ | |
2d112de7 | 12383 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12384 | &pipe_config->pipe_src_w, |
12385 | &pipe_config->pipe_src_h); | |
e41a56be | 12386 | |
e29c22c0 | 12387 | encoder_retry: |
ef1b460d | 12388 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12389 | pipe_config->port_clock = 0; |
ef1b460d | 12390 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12391 | |
135c81b8 | 12392 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12393 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12394 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12395 | |
7758a113 DV |
12396 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12397 | * adjust it according to limitations or connector properties, and also | |
12398 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12399 | */ |
da3ced29 | 12400 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12401 | if (connector_state->crtc != crtc) |
7758a113 | 12402 | continue; |
7ae89233 | 12403 | |
0b901879 ACO |
12404 | encoder = to_intel_encoder(connector_state->best_encoder); |
12405 | ||
efea6e8e DV |
12406 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12407 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12408 | goto fail; |
12409 | } | |
ee7b9f93 | 12410 | } |
47f1c6c9 | 12411 | |
ff9a6750 DV |
12412 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12413 | * done afterwards in case the encoder adjusts the mode. */ | |
12414 | if (!pipe_config->port_clock) | |
2d112de7 | 12415 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12416 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12417 | |
a43f6e0f | 12418 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12419 | if (ret < 0) { |
7758a113 DV |
12420 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12421 | goto fail; | |
ee7b9f93 | 12422 | } |
e29c22c0 DV |
12423 | |
12424 | if (ret == RETRY) { | |
12425 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12426 | ret = -EINVAL; | |
12427 | goto fail; | |
12428 | } | |
12429 | ||
12430 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12431 | retry = false; | |
12432 | goto encoder_retry; | |
12433 | } | |
12434 | ||
e8fa4270 DV |
12435 | /* Dithering seems to not pass-through bits correctly when it should, so |
12436 | * only enable it on 6bpc panels. */ | |
12437 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12438 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12439 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12440 | |
7758a113 | 12441 | fail: |
548ee15b | 12442 | return ret; |
ee7b9f93 | 12443 | } |
47f1c6c9 | 12444 | |
ea9d758d | 12445 | static void |
4740b0f2 | 12446 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12447 | { |
0a9ab303 ACO |
12448 | struct drm_crtc *crtc; |
12449 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12450 | int i; |
ea9d758d | 12451 | |
7668851f | 12452 | /* Double check state. */ |
8a75d157 | 12453 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12454 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12455 | |
12456 | /* Update hwmode for vblank functions */ | |
12457 | if (crtc->state->active) | |
12458 | crtc->hwmode = crtc->state->adjusted_mode; | |
12459 | else | |
12460 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12461 | |
12462 | /* | |
12463 | * Update legacy state to satisfy fbc code. This can | |
12464 | * be removed when fbc uses the atomic state. | |
12465 | */ | |
12466 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12467 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12468 | ||
12469 | crtc->primary->fb = plane_state->fb; | |
12470 | crtc->x = plane_state->src_x >> 16; | |
12471 | crtc->y = plane_state->src_y >> 16; | |
12472 | } | |
ea9d758d | 12473 | } |
ea9d758d DV |
12474 | } |
12475 | ||
3bd26263 | 12476 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12477 | { |
3bd26263 | 12478 | int diff; |
f1f644dc JB |
12479 | |
12480 | if (clock1 == clock2) | |
12481 | return true; | |
12482 | ||
12483 | if (!clock1 || !clock2) | |
12484 | return false; | |
12485 | ||
12486 | diff = abs(clock1 - clock2); | |
12487 | ||
12488 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12489 | return true; | |
12490 | ||
12491 | return false; | |
12492 | } | |
12493 | ||
25c5b266 DV |
12494 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12495 | list_for_each_entry((intel_crtc), \ | |
12496 | &(dev)->mode_config.crtc_list, \ | |
12497 | base.head) \ | |
95150bdf | 12498 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12499 | |
cfb23ed6 ML |
12500 | static bool |
12501 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12502 | unsigned int m2, unsigned int n2, | |
12503 | bool exact) | |
12504 | { | |
12505 | if (m == m2 && n == n2) | |
12506 | return true; | |
12507 | ||
12508 | if (exact || !m || !n || !m2 || !n2) | |
12509 | return false; | |
12510 | ||
12511 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12512 | ||
31d10b57 ML |
12513 | if (n > n2) { |
12514 | while (n > n2) { | |
cfb23ed6 ML |
12515 | m2 <<= 1; |
12516 | n2 <<= 1; | |
12517 | } | |
31d10b57 ML |
12518 | } else if (n < n2) { |
12519 | while (n < n2) { | |
cfb23ed6 ML |
12520 | m <<= 1; |
12521 | n <<= 1; | |
12522 | } | |
12523 | } | |
12524 | ||
31d10b57 ML |
12525 | if (n != n2) |
12526 | return false; | |
12527 | ||
12528 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12529 | } |
12530 | ||
12531 | static bool | |
12532 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12533 | struct intel_link_m_n *m2_n2, | |
12534 | bool adjust) | |
12535 | { | |
12536 | if (m_n->tu == m2_n2->tu && | |
12537 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12538 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12539 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12540 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12541 | if (adjust) | |
12542 | *m2_n2 = *m_n; | |
12543 | ||
12544 | return true; | |
12545 | } | |
12546 | ||
12547 | return false; | |
12548 | } | |
12549 | ||
0e8ffe1b | 12550 | static bool |
2fa2fe9a | 12551 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12552 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12553 | struct intel_crtc_state *pipe_config, |
12554 | bool adjust) | |
0e8ffe1b | 12555 | { |
cfb23ed6 ML |
12556 | bool ret = true; |
12557 | ||
12558 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12559 | do { \ | |
12560 | if (!adjust) \ | |
12561 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12562 | else \ | |
12563 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12564 | } while (0) | |
12565 | ||
66e985c0 DV |
12566 | #define PIPE_CONF_CHECK_X(name) \ |
12567 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12568 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12569 | "(expected 0x%08x, found 0x%08x)\n", \ |
12570 | current_config->name, \ | |
12571 | pipe_config->name); \ | |
cfb23ed6 | 12572 | ret = false; \ |
66e985c0 DV |
12573 | } |
12574 | ||
08a24034 DV |
12575 | #define PIPE_CONF_CHECK_I(name) \ |
12576 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12577 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12578 | "(expected %i, found %i)\n", \ |
12579 | current_config->name, \ | |
12580 | pipe_config->name); \ | |
cfb23ed6 ML |
12581 | ret = false; \ |
12582 | } | |
12583 | ||
8106ddbd ACO |
12584 | #define PIPE_CONF_CHECK_P(name) \ |
12585 | if (current_config->name != pipe_config->name) { \ | |
12586 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12587 | "(expected %p, found %p)\n", \ | |
12588 | current_config->name, \ | |
12589 | pipe_config->name); \ | |
12590 | ret = false; \ | |
12591 | } | |
12592 | ||
cfb23ed6 ML |
12593 | #define PIPE_CONF_CHECK_M_N(name) \ |
12594 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12595 | &pipe_config->name,\ | |
12596 | adjust)) { \ | |
12597 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12598 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12599 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12600 | current_config->name.tu, \ | |
12601 | current_config->name.gmch_m, \ | |
12602 | current_config->name.gmch_n, \ | |
12603 | current_config->name.link_m, \ | |
12604 | current_config->name.link_n, \ | |
12605 | pipe_config->name.tu, \ | |
12606 | pipe_config->name.gmch_m, \ | |
12607 | pipe_config->name.gmch_n, \ | |
12608 | pipe_config->name.link_m, \ | |
12609 | pipe_config->name.link_n); \ | |
12610 | ret = false; \ | |
12611 | } | |
12612 | ||
55c561a7 DV |
12613 | /* This is required for BDW+ where there is only one set of registers for |
12614 | * switching between high and low RR. | |
12615 | * This macro can be used whenever a comparison has to be made between one | |
12616 | * hw state and multiple sw state variables. | |
12617 | */ | |
cfb23ed6 ML |
12618 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
12619 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12620 | &pipe_config->name, adjust) && \ | |
12621 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12622 | &pipe_config->name, adjust)) { \ | |
12623 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12624 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12625 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12626 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12627 | current_config->name.tu, \ | |
12628 | current_config->name.gmch_m, \ | |
12629 | current_config->name.gmch_n, \ | |
12630 | current_config->name.link_m, \ | |
12631 | current_config->name.link_n, \ | |
12632 | current_config->alt_name.tu, \ | |
12633 | current_config->alt_name.gmch_m, \ | |
12634 | current_config->alt_name.gmch_n, \ | |
12635 | current_config->alt_name.link_m, \ | |
12636 | current_config->alt_name.link_n, \ | |
12637 | pipe_config->name.tu, \ | |
12638 | pipe_config->name.gmch_m, \ | |
12639 | pipe_config->name.gmch_n, \ | |
12640 | pipe_config->name.link_m, \ | |
12641 | pipe_config->name.link_n); \ | |
12642 | ret = false; \ | |
88adfff1 DV |
12643 | } |
12644 | ||
1bd1bd80 DV |
12645 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12646 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12647 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12648 | "(expected %i, found %i)\n", \ |
12649 | current_config->name & (mask), \ | |
12650 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12651 | ret = false; \ |
1bd1bd80 DV |
12652 | } |
12653 | ||
5e550656 VS |
12654 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12655 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12656 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12657 | "(expected %i, found %i)\n", \ |
12658 | current_config->name, \ | |
12659 | pipe_config->name); \ | |
cfb23ed6 | 12660 | ret = false; \ |
5e550656 VS |
12661 | } |
12662 | ||
bb760063 DV |
12663 | #define PIPE_CONF_QUIRK(quirk) \ |
12664 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12665 | ||
eccb140b DV |
12666 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12667 | ||
08a24034 DV |
12668 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12669 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12670 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12671 | |
eb14cb74 | 12672 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12673 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12674 | |
12675 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12676 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12677 | ||
cfb23ed6 ML |
12678 | if (current_config->has_drrs) |
12679 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12680 | } else | |
12681 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12682 | |
a65347ba JN |
12683 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12684 | ||
2d112de7 ACO |
12685 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12686 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12687 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12688 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12689 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12690 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12691 | |
2d112de7 ACO |
12692 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12693 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12694 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12695 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12696 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12697 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12698 | |
c93f54cf | 12699 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12700 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12701 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12702 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12703 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12704 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12705 | |
9ed109a7 DV |
12706 | PIPE_CONF_CHECK_I(has_audio); |
12707 | ||
2d112de7 | 12708 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12709 | DRM_MODE_FLAG_INTERLACE); |
12710 | ||
bb760063 | 12711 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12712 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12713 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12714 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12715 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12716 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12717 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12718 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12719 | DRM_MODE_FLAG_NVSYNC); |
12720 | } | |
045ac3b5 | 12721 | |
333b8ca8 | 12722 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12723 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12724 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 12725 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 12726 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12727 | |
bfd16b2a ML |
12728 | if (!adjust) { |
12729 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12730 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12731 | ||
12732 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12733 | if (current_config->pch_pfit.enabled) { | |
12734 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12735 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12736 | } | |
2fa2fe9a | 12737 | |
7aefe2b5 ML |
12738 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12739 | } | |
a1b2278e | 12740 | |
e59150dc JB |
12741 | /* BDW+ don't expose a synchronous way to read the state */ |
12742 | if (IS_HASWELL(dev)) | |
12743 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12744 | |
282740f7 VS |
12745 | PIPE_CONF_CHECK_I(double_wide); |
12746 | ||
26804afd DV |
12747 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12748 | ||
8106ddbd | 12749 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 12750 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12751 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12752 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12753 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12754 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12755 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12756 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12757 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12758 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12759 | |
47eacbab VS |
12760 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
12761 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
12762 | ||
42571aef VS |
12763 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12764 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12765 | ||
2d112de7 | 12766 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12767 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12768 | |
66e985c0 | 12769 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12770 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 12771 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 12772 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12773 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12774 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12775 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12776 | |
cfb23ed6 | 12777 | return ret; |
0e8ffe1b DV |
12778 | } |
12779 | ||
e3b247da VS |
12780 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12781 | const struct intel_crtc_state *pipe_config) | |
12782 | { | |
12783 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12784 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12785 | &pipe_config->fdi_m_n); |
12786 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12787 | ||
12788 | /* | |
12789 | * FDI already provided one idea for the dotclock. | |
12790 | * Yell if the encoder disagrees. | |
12791 | */ | |
12792 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12793 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12794 | fdi_dotclock, dotclock); | |
12795 | } | |
12796 | } | |
12797 | ||
c0ead703 ML |
12798 | static void verify_wm_state(struct drm_crtc *crtc, |
12799 | struct drm_crtc_state *new_state) | |
08db6652 | 12800 | { |
e7c84544 | 12801 | struct drm_device *dev = crtc->dev; |
08db6652 DL |
12802 | struct drm_i915_private *dev_priv = dev->dev_private; |
12803 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
e7c84544 ML |
12804 | struct skl_ddb_entry *hw_entry, *sw_entry; |
12805 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12806 | const enum pipe pipe = intel_crtc->pipe; | |
08db6652 DL |
12807 | int plane; |
12808 | ||
e7c84544 | 12809 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
12810 | return; |
12811 | ||
12812 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12813 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12814 | ||
e7c84544 ML |
12815 | /* planes */ |
12816 | for_each_plane(dev_priv, pipe, plane) { | |
12817 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
12818 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
08db6652 | 12819 | |
e7c84544 | 12820 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
08db6652 DL |
12821 | continue; |
12822 | ||
e7c84544 ML |
12823 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
12824 | "(expected (%u,%u), found (%u,%u))\n", | |
12825 | pipe_name(pipe), plane + 1, | |
12826 | sw_entry->start, sw_entry->end, | |
12827 | hw_entry->start, hw_entry->end); | |
12828 | } | |
08db6652 | 12829 | |
e7c84544 ML |
12830 | /* cursor */ |
12831 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
12832 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 | 12833 | |
e7c84544 | 12834 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
08db6652 DL |
12835 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
12836 | "(expected (%u,%u), found (%u,%u))\n", | |
12837 | pipe_name(pipe), | |
12838 | sw_entry->start, sw_entry->end, | |
12839 | hw_entry->start, hw_entry->end); | |
12840 | } | |
12841 | } | |
12842 | ||
91d1b4bd | 12843 | static void |
c0ead703 | 12844 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 12845 | { |
35dd3c64 | 12846 | struct drm_connector *connector; |
8af6cf88 | 12847 | |
e7c84544 | 12848 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
12849 | struct drm_encoder *encoder = connector->encoder; |
12850 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12851 | |
e7c84544 ML |
12852 | if (state->crtc != crtc) |
12853 | continue; | |
12854 | ||
c0ead703 | 12855 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 12856 | |
ad3c558f | 12857 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12858 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12859 | } |
91d1b4bd DV |
12860 | } |
12861 | ||
12862 | static void | |
c0ead703 | 12863 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
12864 | { |
12865 | struct intel_encoder *encoder; | |
12866 | struct intel_connector *connector; | |
8af6cf88 | 12867 | |
b2784e15 | 12868 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12869 | bool enabled = false; |
4d20cd86 | 12870 | enum pipe pipe; |
8af6cf88 DV |
12871 | |
12872 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12873 | encoder->base.base.id, | |
8e329a03 | 12874 | encoder->base.name); |
8af6cf88 | 12875 | |
3a3371ff | 12876 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12877 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12878 | continue; |
12879 | enabled = true; | |
ad3c558f ML |
12880 | |
12881 | I915_STATE_WARN(connector->base.state->crtc != | |
12882 | encoder->base.crtc, | |
12883 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12884 | } |
0e32b39c | 12885 | |
e2c719b7 | 12886 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12887 | "encoder's enabled state mismatch " |
12888 | "(expected %i, found %i)\n", | |
12889 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12890 | |
12891 | if (!encoder->base.crtc) { | |
4d20cd86 | 12892 | bool active; |
7c60d198 | 12893 | |
4d20cd86 ML |
12894 | active = encoder->get_hw_state(encoder, &pipe); |
12895 | I915_STATE_WARN(active, | |
12896 | "encoder detached but still enabled on pipe %c.\n", | |
12897 | pipe_name(pipe)); | |
7c60d198 | 12898 | } |
8af6cf88 | 12899 | } |
91d1b4bd DV |
12900 | } |
12901 | ||
12902 | static void | |
c0ead703 ML |
12903 | verify_crtc_state(struct drm_crtc *crtc, |
12904 | struct drm_crtc_state *old_crtc_state, | |
12905 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 12906 | { |
e7c84544 | 12907 | struct drm_device *dev = crtc->dev; |
fbee40df | 12908 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12909 | struct intel_encoder *encoder; |
e7c84544 ML |
12910 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12911 | struct intel_crtc_state *pipe_config, *sw_config; | |
12912 | struct drm_atomic_state *old_state; | |
12913 | bool active; | |
045ac3b5 | 12914 | |
e7c84544 ML |
12915 | old_state = old_crtc_state->state; |
12916 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); | |
12917 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12918 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12919 | pipe_config->base.crtc = crtc; | |
12920 | pipe_config->base.state = old_state; | |
8af6cf88 | 12921 | |
e7c84544 | 12922 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
8af6cf88 | 12923 | |
e7c84544 | 12924 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 12925 | |
e7c84544 ML |
12926 | /* hw state is inconsistent with the pipe quirk */ |
12927 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12928 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12929 | active = new_crtc_state->active; | |
6c49f241 | 12930 | |
e7c84544 ML |
12931 | I915_STATE_WARN(new_crtc_state->active != active, |
12932 | "crtc active state doesn't match with hw state " | |
12933 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 12934 | |
e7c84544 ML |
12935 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
12936 | "transitional active state does not match atomic hw state " | |
12937 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 12938 | |
e7c84544 ML |
12939 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
12940 | enum pipe pipe; | |
4d20cd86 | 12941 | |
e7c84544 ML |
12942 | active = encoder->get_hw_state(encoder, &pipe); |
12943 | I915_STATE_WARN(active != new_crtc_state->active, | |
12944 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12945 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 12946 | |
e7c84544 ML |
12947 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
12948 | "Encoder connected to wrong pipe %c\n", | |
12949 | pipe_name(pipe)); | |
4d20cd86 | 12950 | |
e7c84544 ML |
12951 | if (active) |
12952 | encoder->get_config(encoder, pipe_config); | |
12953 | } | |
53d9f4e9 | 12954 | |
e7c84544 ML |
12955 | if (!new_crtc_state->active) |
12956 | return; | |
cfb23ed6 | 12957 | |
e7c84544 | 12958 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 12959 | |
e7c84544 ML |
12960 | sw_config = to_intel_crtc_state(crtc->state); |
12961 | if (!intel_pipe_config_compare(dev, sw_config, | |
12962 | pipe_config, false)) { | |
12963 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
12964 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
12965 | "[hw state]"); | |
12966 | intel_dump_pipe_config(intel_crtc, sw_config, | |
12967 | "[sw state]"); | |
8af6cf88 DV |
12968 | } |
12969 | } | |
12970 | ||
91d1b4bd | 12971 | static void |
c0ead703 ML |
12972 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
12973 | struct intel_shared_dpll *pll, | |
12974 | struct drm_crtc *crtc, | |
12975 | struct drm_crtc_state *new_state) | |
91d1b4bd | 12976 | { |
91d1b4bd | 12977 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
12978 | unsigned crtc_mask; |
12979 | bool active; | |
5358901f | 12980 | |
e7c84544 | 12981 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 12982 | |
e7c84544 | 12983 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 12984 | |
e7c84544 | 12985 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12986 | |
e7c84544 ML |
12987 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
12988 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
12989 | "pll in active use but not on in sw tracking\n"); | |
12990 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12991 | "pll is on but not used by any active crtc\n"); | |
12992 | I915_STATE_WARN(pll->on != active, | |
12993 | "pll on state mismatch (expected %i, found %i)\n", | |
12994 | pll->on, active); | |
12995 | } | |
5358901f | 12996 | |
e7c84544 | 12997 | if (!crtc) { |
2dd66ebd | 12998 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
12999 | "more active pll users than references: %x vs %x\n", |
13000 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13001 | |
e7c84544 ML |
13002 | return; |
13003 | } | |
13004 | ||
13005 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13006 | ||
13007 | if (new_state->active) | |
13008 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13009 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13010 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13011 | else | |
13012 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13013 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13014 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13015 | |
e7c84544 ML |
13016 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13017 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13018 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13019 | |
e7c84544 ML |
13020 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13021 | &dpll_hw_state, | |
13022 | sizeof(dpll_hw_state)), | |
13023 | "pll hw state mismatch\n"); | |
13024 | } | |
13025 | ||
13026 | static void | |
c0ead703 ML |
13027 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13028 | struct drm_crtc_state *old_crtc_state, | |
13029 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 ML |
13030 | { |
13031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13032 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); | |
13033 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13034 | ||
13035 | if (new_state->shared_dpll) | |
c0ead703 | 13036 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13037 | |
13038 | if (old_state->shared_dpll && | |
13039 | old_state->shared_dpll != new_state->shared_dpll) { | |
13040 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13041 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13042 | ||
13043 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13044 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13045 | pipe_name(drm_crtc_index(crtc))); | |
13046 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13047 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13048 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13049 | } |
8af6cf88 DV |
13050 | } |
13051 | ||
e7c84544 | 13052 | static void |
c0ead703 | 13053 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13054 | struct drm_crtc_state *old_state, |
13055 | struct drm_crtc_state *new_state) | |
13056 | { | |
13057 | if (!needs_modeset(new_state) && | |
13058 | !to_intel_crtc_state(new_state)->update_pipe) | |
13059 | return; | |
13060 | ||
c0ead703 ML |
13061 | verify_wm_state(crtc, new_state); |
13062 | verify_connector_state(crtc->dev, crtc); | |
13063 | verify_crtc_state(crtc, old_state, new_state); | |
13064 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13065 | } |
13066 | ||
13067 | static void | |
c0ead703 | 13068 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 ML |
13069 | { |
13070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13071 | int i; | |
13072 | ||
13073 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13074 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13075 | } |
13076 | ||
13077 | static void | |
c0ead703 | 13078 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13079 | { |
c0ead703 ML |
13080 | verify_encoder_state(dev); |
13081 | verify_connector_state(dev, NULL); | |
13082 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13083 | } |
13084 | ||
80715b2f VS |
13085 | static void update_scanline_offset(struct intel_crtc *crtc) |
13086 | { | |
13087 | struct drm_device *dev = crtc->base.dev; | |
13088 | ||
13089 | /* | |
13090 | * The scanline counter increments at the leading edge of hsync. | |
13091 | * | |
13092 | * On most platforms it starts counting from vtotal-1 on the | |
13093 | * first active line. That means the scanline counter value is | |
13094 | * always one less than what we would expect. Ie. just after | |
13095 | * start of vblank, which also occurs at start of hsync (on the | |
13096 | * last active line), the scanline counter will read vblank_start-1. | |
13097 | * | |
13098 | * On gen2 the scanline counter starts counting from 1 instead | |
13099 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13100 | * to keep the value positive), instead of adding one. | |
13101 | * | |
13102 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13103 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13104 | * there's an extra 1 line difference. So we need to add two instead of | |
13105 | * one to the value. | |
13106 | */ | |
13107 | if (IS_GEN2(dev)) { | |
124abe07 | 13108 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13109 | int vtotal; |
13110 | ||
124abe07 VS |
13111 | vtotal = adjusted_mode->crtc_vtotal; |
13112 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13113 | vtotal /= 2; |
13114 | ||
13115 | crtc->scanline_offset = vtotal - 1; | |
13116 | } else if (HAS_DDI(dev) && | |
409ee761 | 13117 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13118 | crtc->scanline_offset = 2; |
13119 | } else | |
13120 | crtc->scanline_offset = 1; | |
13121 | } | |
13122 | ||
ad421372 | 13123 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13124 | { |
225da59b | 13125 | struct drm_device *dev = state->dev; |
ed6739ef | 13126 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13127 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13128 | struct drm_crtc *crtc; |
13129 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13130 | int i; |
ed6739ef ACO |
13131 | |
13132 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13133 | return; |
ed6739ef | 13134 | |
0a9ab303 | 13135 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13136 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13137 | struct intel_shared_dpll *old_dpll = |
13138 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13139 | |
fb1a38a9 | 13140 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13141 | continue; |
13142 | ||
8106ddbd | 13143 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13144 | |
8106ddbd | 13145 | if (!old_dpll) |
fb1a38a9 | 13146 | continue; |
0a9ab303 | 13147 | |
ad421372 ML |
13148 | if (!shared_dpll) |
13149 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13150 | |
8106ddbd | 13151 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13152 | } |
ed6739ef ACO |
13153 | } |
13154 | ||
99d736a2 ML |
13155 | /* |
13156 | * This implements the workaround described in the "notes" section of the mode | |
13157 | * set sequence documentation. When going from no pipes or single pipe to | |
13158 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13159 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13160 | */ | |
13161 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13162 | { | |
13163 | struct drm_crtc_state *crtc_state; | |
13164 | struct intel_crtc *intel_crtc; | |
13165 | struct drm_crtc *crtc; | |
13166 | struct intel_crtc_state *first_crtc_state = NULL; | |
13167 | struct intel_crtc_state *other_crtc_state = NULL; | |
13168 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13169 | int i; | |
13170 | ||
13171 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13172 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13173 | intel_crtc = to_intel_crtc(crtc); | |
13174 | ||
13175 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13176 | continue; | |
13177 | ||
13178 | if (first_crtc_state) { | |
13179 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13180 | break; | |
13181 | } else { | |
13182 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13183 | first_pipe = intel_crtc->pipe; | |
13184 | } | |
13185 | } | |
13186 | ||
13187 | /* No workaround needed? */ | |
13188 | if (!first_crtc_state) | |
13189 | return 0; | |
13190 | ||
13191 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13192 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13193 | struct intel_crtc_state *pipe_config; | |
13194 | ||
13195 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13196 | if (IS_ERR(pipe_config)) | |
13197 | return PTR_ERR(pipe_config); | |
13198 | ||
13199 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13200 | ||
13201 | if (!pipe_config->base.active || | |
13202 | needs_modeset(&pipe_config->base)) | |
13203 | continue; | |
13204 | ||
13205 | /* 2 or more enabled crtcs means no need for w/a */ | |
13206 | if (enabled_pipe != INVALID_PIPE) | |
13207 | return 0; | |
13208 | ||
13209 | enabled_pipe = intel_crtc->pipe; | |
13210 | } | |
13211 | ||
13212 | if (enabled_pipe != INVALID_PIPE) | |
13213 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13214 | else if (other_crtc_state) | |
13215 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13216 | ||
13217 | return 0; | |
13218 | } | |
13219 | ||
27c329ed ML |
13220 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13221 | { | |
13222 | struct drm_crtc *crtc; | |
13223 | struct drm_crtc_state *crtc_state; | |
13224 | int ret = 0; | |
13225 | ||
13226 | /* add all active pipes to the state */ | |
13227 | for_each_crtc(state->dev, crtc) { | |
13228 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13229 | if (IS_ERR(crtc_state)) | |
13230 | return PTR_ERR(crtc_state); | |
13231 | ||
13232 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13233 | continue; | |
13234 | ||
13235 | crtc_state->mode_changed = true; | |
13236 | ||
13237 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13238 | if (ret) | |
13239 | break; | |
13240 | ||
13241 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13242 | if (ret) | |
13243 | break; | |
13244 | } | |
13245 | ||
13246 | return ret; | |
13247 | } | |
13248 | ||
c347a676 | 13249 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13250 | { |
565602d7 ML |
13251 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13252 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13253 | struct drm_crtc *crtc; | |
13254 | struct drm_crtc_state *crtc_state; | |
13255 | int ret = 0, i; | |
054518dd | 13256 | |
b359283a ML |
13257 | if (!check_digital_port_conflicts(state)) { |
13258 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13259 | return -EINVAL; | |
13260 | } | |
13261 | ||
565602d7 ML |
13262 | intel_state->modeset = true; |
13263 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13264 | ||
13265 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13266 | if (crtc_state->active) | |
13267 | intel_state->active_crtcs |= 1 << i; | |
13268 | else | |
13269 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13270 | |
13271 | if (crtc_state->active != crtc->state->active) | |
13272 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13273 | } |
13274 | ||
054518dd ACO |
13275 | /* |
13276 | * See if the config requires any additional preparation, e.g. | |
13277 | * to adjust global state with pipes off. We need to do this | |
13278 | * here so we can get the modeset_pipe updated config for the new | |
13279 | * mode set on this crtc. For other crtcs we need to use the | |
13280 | * adjusted_mode bits in the crtc directly. | |
13281 | */ | |
27c329ed | 13282 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13283 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13284 | ||
1a617b77 | 13285 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13286 | ret = intel_modeset_all_pipes(state); |
13287 | ||
13288 | if (ret < 0) | |
054518dd | 13289 | return ret; |
e8788cbc ML |
13290 | |
13291 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13292 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13293 | } else |
1a617b77 | 13294 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13295 | |
ad421372 | 13296 | intel_modeset_clear_plls(state); |
054518dd | 13297 | |
565602d7 | 13298 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13299 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13300 | |
ad421372 | 13301 | return 0; |
c347a676 ACO |
13302 | } |
13303 | ||
aa363136 MR |
13304 | /* |
13305 | * Handle calculation of various watermark data at the end of the atomic check | |
13306 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13307 | * handlers to ensure that all derived state has been updated. | |
13308 | */ | |
55994c2c | 13309 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
13310 | { |
13311 | struct drm_device *dev = state->dev; | |
98d39494 | 13312 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
13313 | |
13314 | /* Is there platform-specific watermark information to calculate? */ | |
13315 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
13316 | return dev_priv->display.compute_global_watermarks(state); |
13317 | ||
13318 | return 0; | |
aa363136 MR |
13319 | } |
13320 | ||
74c090b1 ML |
13321 | /** |
13322 | * intel_atomic_check - validate state object | |
13323 | * @dev: drm device | |
13324 | * @state: state to validate | |
13325 | */ | |
13326 | static int intel_atomic_check(struct drm_device *dev, | |
13327 | struct drm_atomic_state *state) | |
c347a676 | 13328 | { |
dd8b3bdb | 13329 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13330 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13331 | struct drm_crtc *crtc; |
13332 | struct drm_crtc_state *crtc_state; | |
13333 | int ret, i; | |
61333b60 | 13334 | bool any_ms = false; |
c347a676 | 13335 | |
74c090b1 | 13336 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13337 | if (ret) |
13338 | return ret; | |
13339 | ||
c347a676 | 13340 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13341 | struct intel_crtc_state *pipe_config = |
13342 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13343 | |
13344 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13345 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13346 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13347 | |
61333b60 ML |
13348 | if (!crtc_state->enable) { |
13349 | if (needs_modeset(crtc_state)) | |
13350 | any_ms = true; | |
c347a676 | 13351 | continue; |
61333b60 | 13352 | } |
c347a676 | 13353 | |
26495481 | 13354 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13355 | continue; |
13356 | ||
26495481 DV |
13357 | /* FIXME: For only active_changed we shouldn't need to do any |
13358 | * state recomputation at all. */ | |
13359 | ||
1ed51de9 DV |
13360 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13361 | if (ret) | |
13362 | return ret; | |
b359283a | 13363 | |
cfb23ed6 | 13364 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
13365 | if (ret) { |
13366 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
13367 | pipe_config, "[failed]"); | |
c347a676 | 13368 | return ret; |
25aa1c39 | 13369 | } |
c347a676 | 13370 | |
73831236 | 13371 | if (i915.fastboot && |
dd8b3bdb | 13372 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13373 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13374 | pipe_config, true)) { |
26495481 | 13375 | crtc_state->mode_changed = false; |
bfd16b2a | 13376 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13377 | } |
13378 | ||
13379 | if (needs_modeset(crtc_state)) { | |
13380 | any_ms = true; | |
cfb23ed6 ML |
13381 | |
13382 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13383 | if (ret) | |
13384 | return ret; | |
13385 | } | |
61333b60 | 13386 | |
26495481 DV |
13387 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13388 | needs_modeset(crtc_state) ? | |
13389 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13390 | } |
13391 | ||
61333b60 ML |
13392 | if (any_ms) { |
13393 | ret = intel_modeset_checks(state); | |
13394 | ||
13395 | if (ret) | |
13396 | return ret; | |
27c329ed | 13397 | } else |
dd8b3bdb | 13398 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13399 | |
dd8b3bdb | 13400 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13401 | if (ret) |
13402 | return ret; | |
13403 | ||
f51be2e0 | 13404 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 13405 | return calc_watermark_data(state); |
054518dd ACO |
13406 | } |
13407 | ||
5008e874 ML |
13408 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13409 | struct drm_atomic_state *state, | |
13410 | bool async) | |
13411 | { | |
7580d774 ML |
13412 | struct drm_i915_private *dev_priv = dev->dev_private; |
13413 | struct drm_plane_state *plane_state; | |
5008e874 | 13414 | struct drm_crtc_state *crtc_state; |
7580d774 | 13415 | struct drm_plane *plane; |
5008e874 ML |
13416 | struct drm_crtc *crtc; |
13417 | int i, ret; | |
13418 | ||
13419 | if (async) { | |
13420 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13421 | return -EINVAL; | |
13422 | } | |
13423 | ||
13424 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
acf4e84d CW |
13425 | if (state->legacy_cursor_update) |
13426 | continue; | |
13427 | ||
5008e874 ML |
13428 | ret = intel_crtc_wait_for_pending_flips(crtc); |
13429 | if (ret) | |
13430 | return ret; | |
7580d774 ML |
13431 | |
13432 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13433 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13434 | } |
13435 | ||
f935675f ML |
13436 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13437 | if (ret) | |
13438 | return ret; | |
13439 | ||
5008e874 | 13440 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 13441 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 13442 | |
f7e5838b | 13443 | if (!ret && !async) { |
7580d774 ML |
13444 | for_each_plane_in_state(state, plane, plane_state, i) { |
13445 | struct intel_plane_state *intel_plane_state = | |
13446 | to_intel_plane_state(plane_state); | |
13447 | ||
13448 | if (!intel_plane_state->wait_req) | |
13449 | continue; | |
13450 | ||
13451 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
299259a3 | 13452 | true, NULL, NULL); |
f7e5838b | 13453 | if (ret) { |
f4457ae7 CW |
13454 | /* Any hang should be swallowed by the wait */ |
13455 | WARN_ON(ret == -EIO); | |
f7e5838b CW |
13456 | mutex_lock(&dev->struct_mutex); |
13457 | drm_atomic_helper_cleanup_planes(dev, state); | |
13458 | mutex_unlock(&dev->struct_mutex); | |
7580d774 | 13459 | break; |
f7e5838b | 13460 | } |
7580d774 | 13461 | } |
7580d774 | 13462 | } |
5008e874 ML |
13463 | |
13464 | return ret; | |
13465 | } | |
13466 | ||
e8861675 ML |
13467 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13468 | struct drm_i915_private *dev_priv, | |
13469 | unsigned crtc_mask) | |
13470 | { | |
13471 | unsigned last_vblank_count[I915_MAX_PIPES]; | |
13472 | enum pipe pipe; | |
13473 | int ret; | |
13474 | ||
13475 | if (!crtc_mask) | |
13476 | return; | |
13477 | ||
13478 | for_each_pipe(dev_priv, pipe) { | |
13479 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13480 | ||
13481 | if (!((1 << pipe) & crtc_mask)) | |
13482 | continue; | |
13483 | ||
13484 | ret = drm_crtc_vblank_get(crtc); | |
13485 | if (WARN_ON(ret != 0)) { | |
13486 | crtc_mask &= ~(1 << pipe); | |
13487 | continue; | |
13488 | } | |
13489 | ||
13490 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); | |
13491 | } | |
13492 | ||
13493 | for_each_pipe(dev_priv, pipe) { | |
13494 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13495 | long lret; | |
13496 | ||
13497 | if (!((1 << pipe) & crtc_mask)) | |
13498 | continue; | |
13499 | ||
13500 | lret = wait_event_timeout(dev->vblank[pipe].queue, | |
13501 | last_vblank_count[pipe] != | |
13502 | drm_crtc_vblank_count(crtc), | |
13503 | msecs_to_jiffies(50)); | |
13504 | ||
8a8dae26 | 13505 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
e8861675 ML |
13506 | |
13507 | drm_crtc_vblank_put(crtc); | |
13508 | } | |
13509 | } | |
13510 | ||
13511 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) | |
13512 | { | |
13513 | /* fb updated, need to unpin old fb */ | |
13514 | if (crtc_state->fb_changed) | |
13515 | return true; | |
13516 | ||
13517 | /* wm changes, need vblank before final wm's */ | |
caed361d | 13518 | if (crtc_state->update_wm_post) |
e8861675 ML |
13519 | return true; |
13520 | ||
13521 | /* | |
13522 | * cxsr is re-enabled after vblank. | |
caed361d | 13523 | * This is already handled by crtc_state->update_wm_post, |
e8861675 ML |
13524 | * but added for clarity. |
13525 | */ | |
13526 | if (crtc_state->disable_cxsr) | |
13527 | return true; | |
13528 | ||
13529 | return false; | |
13530 | } | |
13531 | ||
74c090b1 ML |
13532 | /** |
13533 | * intel_atomic_commit - commit validated state object | |
13534 | * @dev: DRM device | |
13535 | * @state: the top-level driver state object | |
13536 | * @async: asynchronous commit | |
13537 | * | |
13538 | * This function commits a top-level state object that has been validated | |
13539 | * with drm_atomic_helper_check(). | |
13540 | * | |
13541 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13542 | * we can only handle plane-related operations and do not yet support | |
13543 | * asynchronous commit. | |
13544 | * | |
13545 | * RETURNS | |
13546 | * Zero for success or -errno. | |
13547 | */ | |
13548 | static int intel_atomic_commit(struct drm_device *dev, | |
13549 | struct drm_atomic_state *state, | |
13550 | bool async) | |
a6778b3c | 13551 | { |
565602d7 | 13552 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13553 | struct drm_i915_private *dev_priv = dev->dev_private; |
29ceb0e6 | 13554 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13555 | struct drm_crtc *crtc; |
ed4a6a7c | 13556 | struct intel_crtc_state *intel_cstate; |
565602d7 ML |
13557 | int ret = 0, i; |
13558 | bool hw_check = intel_state->modeset; | |
33c8df89 | 13559 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
e8861675 | 13560 | unsigned crtc_vblank_mask = 0; |
a6778b3c | 13561 | |
5008e874 | 13562 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13563 | if (ret) { |
13564 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13565 | return ret; |
7580d774 | 13566 | } |
d4afb8cc | 13567 | |
1c5e19f8 | 13568 | drm_atomic_helper_swap_state(dev, state); |
279e99d7 | 13569 | dev_priv->wm.distrust_bios_wm = false; |
734fa01f | 13570 | dev_priv->wm.skl_results = intel_state->wm_results; |
a1475e77 | 13571 | intel_shared_dpll_commit(state); |
1c5e19f8 | 13572 | |
565602d7 ML |
13573 | if (intel_state->modeset) { |
13574 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13575 | sizeof(intel_state->min_pixclk)); | |
13576 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13577 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
33c8df89 ML |
13578 | |
13579 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13580 | } |
13581 | ||
29ceb0e6 | 13582 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13583 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13584 | ||
33c8df89 ML |
13585 | if (needs_modeset(crtc->state) || |
13586 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13587 | hw_check = true; | |
13588 | ||
13589 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13590 | modeset_get_crtc_power_domains(crtc, | |
13591 | to_intel_crtc_state(crtc->state)); | |
13592 | } | |
13593 | ||
61333b60 ML |
13594 | if (!needs_modeset(crtc->state)) |
13595 | continue; | |
13596 | ||
29ceb0e6 | 13597 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13598 | |
29ceb0e6 VS |
13599 | if (old_crtc_state->active) { |
13600 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13601 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13602 | intel_crtc->active = false; |
58f9c0bc | 13603 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13604 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13605 | |
13606 | /* | |
13607 | * Underruns don't always raise | |
13608 | * interrupts, so check manually. | |
13609 | */ | |
13610 | intel_check_cpu_fifo_underruns(dev_priv); | |
13611 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13612 | |
13613 | if (!crtc->state->active) | |
13614 | intel_update_watermarks(crtc); | |
a539205a | 13615 | } |
b8cecdf5 | 13616 | } |
7758a113 | 13617 | |
ea9d758d DV |
13618 | /* Only after disabling all output pipelines that will be changed can we |
13619 | * update the the output configuration. */ | |
4740b0f2 | 13620 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13621 | |
565602d7 | 13622 | if (intel_state->modeset) { |
4740b0f2 | 13623 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13624 | |
13625 | if (dev_priv->display.modeset_commit_cdclk && | |
13626 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13627 | dev_priv->display.modeset_commit_cdclk(state); | |
f6d1973d | 13628 | |
c0ead703 | 13629 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 13630 | } |
47fab737 | 13631 | |
a6778b3c | 13632 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13633 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13634 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13635 | bool modeset = needs_modeset(crtc->state); | |
e8861675 ML |
13636 | struct intel_crtc_state *pipe_config = |
13637 | to_intel_crtc_state(crtc->state); | |
13638 | bool update_pipe = !modeset && pipe_config->update_pipe; | |
9f836f90 | 13639 | |
f6ac4b2a | 13640 | if (modeset && crtc->state->active) { |
a539205a ML |
13641 | update_scanline_offset(to_intel_crtc(crtc)); |
13642 | dev_priv->display.crtc_enable(crtc); | |
13643 | } | |
80715b2f | 13644 | |
f6ac4b2a | 13645 | if (!modeset) |
29ceb0e6 | 13646 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13647 | |
31ae71fc ML |
13648 | if (crtc->state->active && |
13649 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
49227c4a PZ |
13650 | intel_fbc_enable(intel_crtc); |
13651 | ||
6173ee28 ML |
13652 | if (crtc->state->active && |
13653 | (crtc->state->planes_changed || update_pipe)) | |
29ceb0e6 | 13654 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
bfd16b2a | 13655 | |
e8861675 ML |
13656 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13657 | crtc_vblank_mask |= 1 << i; | |
80715b2f | 13658 | } |
a6778b3c | 13659 | |
a6778b3c | 13660 | /* FIXME: add subpixel order */ |
83a57153 | 13661 | |
e8861675 ML |
13662 | if (!state->legacy_cursor_update) |
13663 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
f935675f | 13664 | |
ed4a6a7c MR |
13665 | /* |
13666 | * Now that the vblank has passed, we can go ahead and program the | |
13667 | * optimal watermarks on platforms that need two-step watermark | |
13668 | * programming. | |
13669 | * | |
13670 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13671 | */ | |
29ceb0e6 | 13672 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
ed4a6a7c MR |
13673 | intel_cstate = to_intel_crtc_state(crtc->state); |
13674 | ||
13675 | if (dev_priv->display.optimize_watermarks) | |
13676 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13677 | } | |
13678 | ||
177246a8 MR |
13679 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
13680 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13681 | ||
13682 | if (put_domains[i]) | |
13683 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
f6d1973d | 13684 | |
c0ead703 | 13685 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); |
177246a8 MR |
13686 | } |
13687 | ||
13688 | if (intel_state->modeset) | |
13689 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13690 | ||
f935675f | 13691 | mutex_lock(&dev->struct_mutex); |
d4afb8cc | 13692 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13693 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13694 | |
ee165b1a | 13695 | drm_atomic_state_free(state); |
f30da187 | 13696 | |
75714940 MK |
13697 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13698 | * of triggering bugs in unclaimed access. After we finish | |
13699 | * modesetting, see if an error has been flagged, and if so | |
13700 | * enable debugging for the next modeset - and hope we catch | |
13701 | * the culprit. | |
13702 | * | |
13703 | * XXX note that we assume display power is on at this point. | |
13704 | * This might hold true now but we need to add pm helper to check | |
13705 | * unclaimed only when the hardware is on, as atomic commits | |
13706 | * can happen also when the device is completely off. | |
13707 | */ | |
13708 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13709 | ||
74c090b1 | 13710 | return 0; |
7f27126e JB |
13711 | } |
13712 | ||
c0c36b94 CW |
13713 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13714 | { | |
83a57153 ACO |
13715 | struct drm_device *dev = crtc->dev; |
13716 | struct drm_atomic_state *state; | |
e694eb02 | 13717 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13718 | int ret; |
83a57153 ACO |
13719 | |
13720 | state = drm_atomic_state_alloc(dev); | |
13721 | if (!state) { | |
e694eb02 | 13722 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13723 | crtc->base.id); |
13724 | return; | |
13725 | } | |
13726 | ||
e694eb02 | 13727 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13728 | |
e694eb02 ML |
13729 | retry: |
13730 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13731 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13732 | if (!ret) { | |
13733 | if (!crtc_state->active) | |
13734 | goto out; | |
83a57153 | 13735 | |
e694eb02 | 13736 | crtc_state->mode_changed = true; |
74c090b1 | 13737 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13738 | } |
13739 | ||
e694eb02 ML |
13740 | if (ret == -EDEADLK) { |
13741 | drm_atomic_state_clear(state); | |
13742 | drm_modeset_backoff(state->acquire_ctx); | |
13743 | goto retry; | |
4ed9fb37 | 13744 | } |
4be07317 | 13745 | |
2bfb4627 | 13746 | if (ret) |
e694eb02 | 13747 | out: |
2bfb4627 | 13748 | drm_atomic_state_free(state); |
c0c36b94 CW |
13749 | } |
13750 | ||
25c5b266 DV |
13751 | #undef for_each_intel_crtc_masked |
13752 | ||
f6e5b160 | 13753 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
82cf435b | 13754 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 13755 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13756 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 CW |
13757 | .destroy = intel_crtc_destroy, |
13758 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13759 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13760 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13761 | }; |
13762 | ||
6beb8c23 MR |
13763 | /** |
13764 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13765 | * @plane: drm plane to prepare for | |
13766 | * @fb: framebuffer to prepare for presentation | |
13767 | * | |
13768 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13769 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13770 | * bits. Some older platforms need special physical address handling for | |
13771 | * cursor planes. | |
13772 | * | |
f935675f ML |
13773 | * Must be called with struct_mutex held. |
13774 | * | |
6beb8c23 MR |
13775 | * Returns 0 on success, negative error code on failure. |
13776 | */ | |
13777 | int | |
13778 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13779 | const struct drm_plane_state *new_state) |
465c120c MR |
13780 | { |
13781 | struct drm_device *dev = plane->dev; | |
844f9111 | 13782 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13783 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13784 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13785 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13786 | int ret = 0; |
465c120c | 13787 | |
1ee49399 | 13788 | if (!obj && !old_obj) |
465c120c MR |
13789 | return 0; |
13790 | ||
5008e874 ML |
13791 | if (old_obj) { |
13792 | struct drm_crtc_state *crtc_state = | |
13793 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13794 | ||
13795 | /* Big Hammer, we also need to ensure that any pending | |
13796 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13797 | * current scanout is retired before unpinning the old | |
13798 | * framebuffer. Note that we rely on userspace rendering | |
13799 | * into the buffer attached to the pipe they are waiting | |
13800 | * on. If not, userspace generates a GPU hang with IPEHR | |
13801 | * point to the MI_WAIT_FOR_EVENT. | |
13802 | * | |
13803 | * This should only fail upon a hung GPU, in which case we | |
13804 | * can safely continue. | |
13805 | */ | |
13806 | if (needs_modeset(crtc_state)) | |
13807 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
f4457ae7 CW |
13808 | if (ret) { |
13809 | /* GPU hangs should have been swallowed by the wait */ | |
13810 | WARN_ON(ret == -EIO); | |
f935675f | 13811 | return ret; |
f4457ae7 | 13812 | } |
5008e874 ML |
13813 | } |
13814 | ||
3c28ff22 AG |
13815 | /* For framebuffer backed by dmabuf, wait for fence */ |
13816 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13817 | long lret; |
13818 | ||
13819 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13820 | false, true, | |
13821 | MAX_SCHEDULE_TIMEOUT); | |
13822 | if (lret == -ERESTARTSYS) | |
13823 | return lret; | |
3c28ff22 | 13824 | |
bcf8be27 | 13825 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13826 | } |
13827 | ||
1ee49399 ML |
13828 | if (!obj) { |
13829 | ret = 0; | |
13830 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13831 | INTEL_INFO(dev)->cursor_needs_physical) { |
13832 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13833 | ret = i915_gem_object_attach_phys(obj, align); | |
13834 | if (ret) | |
13835 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13836 | } else { | |
3465c580 | 13837 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 13838 | } |
465c120c | 13839 | |
7580d774 ML |
13840 | if (ret == 0) { |
13841 | if (obj) { | |
13842 | struct intel_plane_state *plane_state = | |
13843 | to_intel_plane_state(new_state); | |
13844 | ||
13845 | i915_gem_request_assign(&plane_state->wait_req, | |
13846 | obj->last_write_req); | |
13847 | } | |
13848 | ||
a9ff8714 | 13849 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13850 | } |
fdd508a6 | 13851 | |
6beb8c23 MR |
13852 | return ret; |
13853 | } | |
13854 | ||
38f3ce3a MR |
13855 | /** |
13856 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13857 | * @plane: drm plane to clean up for | |
13858 | * @fb: old framebuffer that was on plane | |
13859 | * | |
13860 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13861 | * |
13862 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13863 | */ |
13864 | void | |
13865 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13866 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13867 | { |
13868 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13869 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13870 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13871 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13872 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13873 | |
7580d774 ML |
13874 | old_intel_state = to_intel_plane_state(old_state); |
13875 | ||
1ee49399 | 13876 | if (!obj && !old_obj) |
38f3ce3a MR |
13877 | return; |
13878 | ||
1ee49399 ML |
13879 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13880 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 13881 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 ML |
13882 | |
13883 | /* prepare_fb aborted? */ | |
13884 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13885 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13886 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13887 | |
13888 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
465c120c MR |
13889 | } |
13890 | ||
6156a456 CK |
13891 | int |
13892 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13893 | { | |
13894 | int max_scale; | |
13895 | struct drm_device *dev; | |
13896 | struct drm_i915_private *dev_priv; | |
13897 | int crtc_clock, cdclk; | |
13898 | ||
bf8a0af0 | 13899 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13900 | return DRM_PLANE_HELPER_NO_SCALING; |
13901 | ||
13902 | dev = intel_crtc->base.dev; | |
13903 | dev_priv = dev->dev_private; | |
13904 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13905 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13906 | |
54bf1ce6 | 13907 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13908 | return DRM_PLANE_HELPER_NO_SCALING; |
13909 | ||
13910 | /* | |
13911 | * skl max scale is lower of: | |
13912 | * close to 3 but not 3, -1 is for that purpose | |
13913 | * or | |
13914 | * cdclk/crtc_clock | |
13915 | */ | |
13916 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13917 | ||
13918 | return max_scale; | |
13919 | } | |
13920 | ||
465c120c | 13921 | static int |
3c692a41 | 13922 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13923 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13924 | struct intel_plane_state *state) |
13925 | { | |
2b875c22 MR |
13926 | struct drm_crtc *crtc = state->base.crtc; |
13927 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13928 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13929 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13930 | bool can_position = false; | |
465c120c | 13931 | |
693bdc28 VS |
13932 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
13933 | /* use scaler when colorkey is not required */ | |
13934 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13935 | min_scale = 1; | |
13936 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13937 | } | |
d8106366 | 13938 | can_position = true; |
6156a456 | 13939 | } |
d8106366 | 13940 | |
061e4b8d ML |
13941 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13942 | &state->dst, &state->clip, | |
da20eabd ML |
13943 | min_scale, max_scale, |
13944 | can_position, true, | |
13945 | &state->visible); | |
14af293f GP |
13946 | } |
13947 | ||
613d2b27 ML |
13948 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13949 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13950 | { |
32b7eeec | 13951 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13952 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13953 | struct intel_crtc_state *old_intel_state = |
13954 | to_intel_crtc_state(old_crtc_state); | |
13955 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13956 | |
c34c9ee4 | 13957 | /* Perform vblank evasion around commit operation */ |
62852622 | 13958 | intel_pipe_update_start(intel_crtc); |
0583236e | 13959 | |
bfd16b2a ML |
13960 | if (modeset) |
13961 | return; | |
13962 | ||
20a34e78 ML |
13963 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { |
13964 | intel_color_set_csc(crtc->state); | |
13965 | intel_color_load_luts(crtc->state); | |
13966 | } | |
13967 | ||
bfd16b2a ML |
13968 | if (to_intel_crtc_state(crtc->state)->update_pipe) |
13969 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13970 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13971 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13972 | } |
13973 | ||
613d2b27 ML |
13974 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13975 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13976 | { |
32b7eeec | 13977 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13978 | |
62852622 | 13979 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13980 | } |
13981 | ||
cf4c7c12 | 13982 | /** |
4a3b8769 MR |
13983 | * intel_plane_destroy - destroy a plane |
13984 | * @plane: plane to destroy | |
cf4c7c12 | 13985 | * |
4a3b8769 MR |
13986 | * Common destruction function for all types of planes (primary, cursor, |
13987 | * sprite). | |
cf4c7c12 | 13988 | */ |
4a3b8769 | 13989 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13990 | { |
13991 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13992 | drm_plane_cleanup(plane); | |
13993 | kfree(intel_plane); | |
13994 | } | |
13995 | ||
65a3fea0 | 13996 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13997 | .update_plane = drm_atomic_helper_update_plane, |
13998 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13999 | .destroy = intel_plane_destroy, |
c196e1d6 | 14000 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14001 | .atomic_get_property = intel_plane_atomic_get_property, |
14002 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14003 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14004 | .atomic_destroy_state = intel_plane_destroy_state, | |
14005 | ||
465c120c MR |
14006 | }; |
14007 | ||
14008 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14009 | int pipe) | |
14010 | { | |
fca0ce2a VS |
14011 | struct intel_plane *primary = NULL; |
14012 | struct intel_plane_state *state = NULL; | |
465c120c | 14013 | const uint32_t *intel_primary_formats; |
45e3743a | 14014 | unsigned int num_formats; |
fca0ce2a | 14015 | int ret; |
465c120c MR |
14016 | |
14017 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
fca0ce2a VS |
14018 | if (!primary) |
14019 | goto fail; | |
465c120c | 14020 | |
8e7d688b | 14021 | state = intel_create_plane_state(&primary->base); |
fca0ce2a VS |
14022 | if (!state) |
14023 | goto fail; | |
8e7d688b | 14024 | primary->base.state = &state->base; |
ea2c67bb | 14025 | |
465c120c MR |
14026 | primary->can_scale = false; |
14027 | primary->max_downscale = 1; | |
6156a456 CK |
14028 | if (INTEL_INFO(dev)->gen >= 9) { |
14029 | primary->can_scale = true; | |
af99ceda | 14030 | state->scaler_id = -1; |
6156a456 | 14031 | } |
465c120c MR |
14032 | primary->pipe = pipe; |
14033 | primary->plane = pipe; | |
a9ff8714 | 14034 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14035 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14036 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14037 | primary->plane = !pipe; | |
14038 | ||
6c0fd451 DL |
14039 | if (INTEL_INFO(dev)->gen >= 9) { |
14040 | intel_primary_formats = skl_primary_formats; | |
14041 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14042 | |
14043 | primary->update_plane = skylake_update_primary_plane; | |
14044 | primary->disable_plane = skylake_disable_primary_plane; | |
14045 | } else if (HAS_PCH_SPLIT(dev)) { | |
14046 | intel_primary_formats = i965_primary_formats; | |
14047 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14048 | ||
14049 | primary->update_plane = ironlake_update_primary_plane; | |
14050 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14051 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14052 | intel_primary_formats = i965_primary_formats; |
14053 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14054 | |
14055 | primary->update_plane = i9xx_update_primary_plane; | |
14056 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14057 | } else { |
14058 | intel_primary_formats = i8xx_primary_formats; | |
14059 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14060 | |
14061 | primary->update_plane = i9xx_update_primary_plane; | |
14062 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14063 | } |
14064 | ||
fca0ce2a VS |
14065 | ret = drm_universal_plane_init(dev, &primary->base, 0, |
14066 | &intel_plane_funcs, | |
14067 | intel_primary_formats, num_formats, | |
14068 | DRM_PLANE_TYPE_PRIMARY, NULL); | |
14069 | if (ret) | |
14070 | goto fail; | |
48404c1e | 14071 | |
3b7a5119 SJ |
14072 | if (INTEL_INFO(dev)->gen >= 4) |
14073 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14074 | |
ea2c67bb MR |
14075 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14076 | ||
465c120c | 14077 | return &primary->base; |
fca0ce2a VS |
14078 | |
14079 | fail: | |
14080 | kfree(state); | |
14081 | kfree(primary); | |
14082 | ||
14083 | return NULL; | |
465c120c MR |
14084 | } |
14085 | ||
3b7a5119 SJ |
14086 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14087 | { | |
14088 | if (!dev->mode_config.rotation_property) { | |
14089 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14090 | BIT(DRM_ROTATE_180); | |
14091 | ||
14092 | if (INTEL_INFO(dev)->gen >= 9) | |
14093 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14094 | ||
14095 | dev->mode_config.rotation_property = | |
14096 | drm_mode_create_rotation_property(dev, flags); | |
14097 | } | |
14098 | if (dev->mode_config.rotation_property) | |
14099 | drm_object_attach_property(&plane->base.base, | |
14100 | dev->mode_config.rotation_property, | |
14101 | plane->base.state->rotation); | |
14102 | } | |
14103 | ||
3d7d6510 | 14104 | static int |
852e787c | 14105 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14106 | struct intel_crtc_state *crtc_state, |
852e787c | 14107 | struct intel_plane_state *state) |
3d7d6510 | 14108 | { |
061e4b8d | 14109 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14110 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14111 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14112 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14113 | unsigned stride; |
14114 | int ret; | |
3d7d6510 | 14115 | |
061e4b8d ML |
14116 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14117 | &state->dst, &state->clip, | |
3d7d6510 MR |
14118 | DRM_PLANE_HELPER_NO_SCALING, |
14119 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14120 | true, true, &state->visible); |
757f9a3e GP |
14121 | if (ret) |
14122 | return ret; | |
14123 | ||
757f9a3e GP |
14124 | /* if we want to turn off the cursor ignore width and height */ |
14125 | if (!obj) | |
da20eabd | 14126 | return 0; |
757f9a3e | 14127 | |
757f9a3e | 14128 | /* Check for which cursor types we support */ |
061e4b8d | 14129 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14130 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14131 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14132 | return -EINVAL; |
14133 | } | |
14134 | ||
ea2c67bb MR |
14135 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14136 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14137 | DRM_DEBUG_KMS("buffer is too small\n"); |
14138 | return -ENOMEM; | |
14139 | } | |
14140 | ||
3a656b54 | 14141 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14142 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14143 | return -EINVAL; |
32b7eeec MR |
14144 | } |
14145 | ||
b29ec92c VS |
14146 | /* |
14147 | * There's something wrong with the cursor on CHV pipe C. | |
14148 | * If it straddles the left edge of the screen then | |
14149 | * moving it away from the edge or disabling it often | |
14150 | * results in a pipe underrun, and often that can lead to | |
14151 | * dead pipe (constant underrun reported, and it scans | |
14152 | * out just a solid color). To recover from that, the | |
14153 | * display power well must be turned off and on again. | |
14154 | * Refuse the put the cursor into that compromised position. | |
14155 | */ | |
14156 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14157 | state->visible && state->base.crtc_x < 0) { | |
14158 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14159 | return -EINVAL; | |
14160 | } | |
14161 | ||
da20eabd | 14162 | return 0; |
852e787c | 14163 | } |
3d7d6510 | 14164 | |
a8ad0d8e ML |
14165 | static void |
14166 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14167 | struct drm_crtc *crtc) |
a8ad0d8e | 14168 | { |
f2858021 ML |
14169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14170 | ||
14171 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14172 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14173 | } |
14174 | ||
f4a2cf29 | 14175 | static void |
55a08b3f ML |
14176 | intel_update_cursor_plane(struct drm_plane *plane, |
14177 | const struct intel_crtc_state *crtc_state, | |
14178 | const struct intel_plane_state *state) | |
852e787c | 14179 | { |
55a08b3f ML |
14180 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14181 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14182 | struct drm_device *dev = plane->dev; |
2b875c22 | 14183 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14184 | uint32_t addr; |
852e787c | 14185 | |
f4a2cf29 | 14186 | if (!obj) |
a912f12f | 14187 | addr = 0; |
f4a2cf29 | 14188 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14189 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14190 | else |
a912f12f | 14191 | addr = obj->phys_handle->busaddr; |
852e787c | 14192 | |
a912f12f | 14193 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14194 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14195 | } |
14196 | ||
3d7d6510 MR |
14197 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14198 | int pipe) | |
14199 | { | |
fca0ce2a VS |
14200 | struct intel_plane *cursor = NULL; |
14201 | struct intel_plane_state *state = NULL; | |
14202 | int ret; | |
3d7d6510 MR |
14203 | |
14204 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
fca0ce2a VS |
14205 | if (!cursor) |
14206 | goto fail; | |
3d7d6510 | 14207 | |
8e7d688b | 14208 | state = intel_create_plane_state(&cursor->base); |
fca0ce2a VS |
14209 | if (!state) |
14210 | goto fail; | |
8e7d688b | 14211 | cursor->base.state = &state->base; |
ea2c67bb | 14212 | |
3d7d6510 MR |
14213 | cursor->can_scale = false; |
14214 | cursor->max_downscale = 1; | |
14215 | cursor->pipe = pipe; | |
14216 | cursor->plane = pipe; | |
a9ff8714 | 14217 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14218 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14219 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14220 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 14221 | |
fca0ce2a VS |
14222 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
14223 | &intel_plane_funcs, | |
14224 | intel_cursor_formats, | |
14225 | ARRAY_SIZE(intel_cursor_formats), | |
14226 | DRM_PLANE_TYPE_CURSOR, NULL); | |
14227 | if (ret) | |
14228 | goto fail; | |
4398ad45 VS |
14229 | |
14230 | if (INTEL_INFO(dev)->gen >= 4) { | |
14231 | if (!dev->mode_config.rotation_property) | |
14232 | dev->mode_config.rotation_property = | |
14233 | drm_mode_create_rotation_property(dev, | |
14234 | BIT(DRM_ROTATE_0) | | |
14235 | BIT(DRM_ROTATE_180)); | |
14236 | if (dev->mode_config.rotation_property) | |
14237 | drm_object_attach_property(&cursor->base.base, | |
14238 | dev->mode_config.rotation_property, | |
8e7d688b | 14239 | state->base.rotation); |
4398ad45 VS |
14240 | } |
14241 | ||
af99ceda CK |
14242 | if (INTEL_INFO(dev)->gen >=9) |
14243 | state->scaler_id = -1; | |
14244 | ||
ea2c67bb MR |
14245 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14246 | ||
3d7d6510 | 14247 | return &cursor->base; |
fca0ce2a VS |
14248 | |
14249 | fail: | |
14250 | kfree(state); | |
14251 | kfree(cursor); | |
14252 | ||
14253 | return NULL; | |
3d7d6510 MR |
14254 | } |
14255 | ||
549e2bfb CK |
14256 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14257 | struct intel_crtc_state *crtc_state) | |
14258 | { | |
14259 | int i; | |
14260 | struct intel_scaler *intel_scaler; | |
14261 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14262 | ||
14263 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14264 | intel_scaler = &scaler_state->scalers[i]; | |
14265 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14266 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14267 | } | |
14268 | ||
14269 | scaler_state->scaler_id = -1; | |
14270 | } | |
14271 | ||
b358d0a6 | 14272 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14273 | { |
fbee40df | 14274 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14275 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14276 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14277 | struct drm_plane *primary = NULL; |
14278 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14279 | int ret; |
79e53945 | 14280 | |
955382f3 | 14281 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14282 | if (intel_crtc == NULL) |
14283 | return; | |
14284 | ||
f5de6e07 ACO |
14285 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14286 | if (!crtc_state) | |
14287 | goto fail; | |
550acefd ACO |
14288 | intel_crtc->config = crtc_state; |
14289 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14290 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14291 | |
549e2bfb CK |
14292 | /* initialize shared scalers */ |
14293 | if (INTEL_INFO(dev)->gen >= 9) { | |
14294 | if (pipe == PIPE_C) | |
14295 | intel_crtc->num_scalers = 1; | |
14296 | else | |
14297 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14298 | ||
14299 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14300 | } | |
14301 | ||
465c120c | 14302 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14303 | if (!primary) |
14304 | goto fail; | |
14305 | ||
14306 | cursor = intel_cursor_plane_create(dev, pipe); | |
14307 | if (!cursor) | |
14308 | goto fail; | |
14309 | ||
465c120c | 14310 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14311 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14312 | if (ret) |
14313 | goto fail; | |
79e53945 | 14314 | |
1f1c2e24 VS |
14315 | /* |
14316 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14317 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14318 | */ |
80824003 JB |
14319 | intel_crtc->pipe = pipe; |
14320 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14321 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14322 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14323 | intel_crtc->plane = !pipe; |
80824003 JB |
14324 | } |
14325 | ||
4b0e333e CW |
14326 | intel_crtc->cursor_base = ~0; |
14327 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14328 | intel_crtc->cursor_size = ~0; |
8d7849db | 14329 | |
852eb00d VS |
14330 | intel_crtc->wm.cxsr_allowed = true; |
14331 | ||
22fd0fab JB |
14332 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14333 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14334 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14335 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14336 | ||
79e53945 | 14337 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14338 | |
8563b1e8 LL |
14339 | intel_color_init(&intel_crtc->base); |
14340 | ||
87b6b101 | 14341 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14342 | return; |
14343 | ||
14344 | fail: | |
14345 | if (primary) | |
14346 | drm_plane_cleanup(primary); | |
14347 | if (cursor) | |
14348 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14349 | kfree(crtc_state); |
3d7d6510 | 14350 | kfree(intel_crtc); |
79e53945 JB |
14351 | } |
14352 | ||
752aa88a JB |
14353 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14354 | { | |
14355 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14356 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14357 | |
51fd371b | 14358 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14359 | |
d3babd3f | 14360 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14361 | return INVALID_PIPE; |
14362 | ||
14363 | return to_intel_crtc(encoder->crtc)->pipe; | |
14364 | } | |
14365 | ||
08d7b3d1 | 14366 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14367 | struct drm_file *file) |
08d7b3d1 | 14368 | { |
08d7b3d1 | 14369 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14370 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14371 | struct intel_crtc *crtc; |
08d7b3d1 | 14372 | |
7707e653 | 14373 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14374 | |
7707e653 | 14375 | if (!drmmode_crtc) { |
08d7b3d1 | 14376 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14377 | return -ENOENT; |
08d7b3d1 CW |
14378 | } |
14379 | ||
7707e653 | 14380 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14381 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14382 | |
c05422d5 | 14383 | return 0; |
08d7b3d1 CW |
14384 | } |
14385 | ||
66a9278e | 14386 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14387 | { |
66a9278e DV |
14388 | struct drm_device *dev = encoder->base.dev; |
14389 | struct intel_encoder *source_encoder; | |
79e53945 | 14390 | int index_mask = 0; |
79e53945 JB |
14391 | int entry = 0; |
14392 | ||
b2784e15 | 14393 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14394 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14395 | index_mask |= (1 << entry); |
14396 | ||
79e53945 JB |
14397 | entry++; |
14398 | } | |
4ef69c7a | 14399 | |
79e53945 JB |
14400 | return index_mask; |
14401 | } | |
14402 | ||
4d302442 CW |
14403 | static bool has_edp_a(struct drm_device *dev) |
14404 | { | |
14405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14406 | ||
14407 | if (!IS_MOBILE(dev)) | |
14408 | return false; | |
14409 | ||
14410 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14411 | return false; | |
14412 | ||
e3589908 | 14413 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14414 | return false; |
14415 | ||
14416 | return true; | |
14417 | } | |
14418 | ||
84b4e042 JB |
14419 | static bool intel_crt_present(struct drm_device *dev) |
14420 | { | |
14421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14422 | ||
884497ed DL |
14423 | if (INTEL_INFO(dev)->gen >= 9) |
14424 | return false; | |
14425 | ||
cf404ce4 | 14426 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14427 | return false; |
14428 | ||
14429 | if (IS_CHERRYVIEW(dev)) | |
14430 | return false; | |
14431 | ||
65e472e4 VS |
14432 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14433 | return false; | |
14434 | ||
70ac54d0 VS |
14435 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14436 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14437 | return false; | |
14438 | ||
e4abb733 | 14439 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14440 | return false; |
14441 | ||
14442 | return true; | |
14443 | } | |
14444 | ||
79e53945 JB |
14445 | static void intel_setup_outputs(struct drm_device *dev) |
14446 | { | |
725e30ad | 14447 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14448 | struct intel_encoder *encoder; |
cb0953d7 | 14449 | bool dpd_is_edp = false; |
79e53945 | 14450 | |
c9093354 | 14451 | intel_lvds_init(dev); |
79e53945 | 14452 | |
84b4e042 | 14453 | if (intel_crt_present(dev)) |
79935fca | 14454 | intel_crt_init(dev); |
cb0953d7 | 14455 | |
c776eb2e VK |
14456 | if (IS_BROXTON(dev)) { |
14457 | /* | |
14458 | * FIXME: Broxton doesn't support port detection via the | |
14459 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14460 | * detect the ports. | |
14461 | */ | |
14462 | intel_ddi_init(dev, PORT_A); | |
14463 | intel_ddi_init(dev, PORT_B); | |
14464 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
14465 | |
14466 | intel_dsi_init(dev); | |
c776eb2e | 14467 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
14468 | int found; |
14469 | ||
de31facd JB |
14470 | /* |
14471 | * Haswell uses DDI functions to detect digital outputs. | |
14472 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14473 | * it's there. | |
14474 | */ | |
77179400 | 14475 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14476 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14477 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14478 | intel_ddi_init(dev, PORT_A); |
14479 | ||
14480 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14481 | * register */ | |
14482 | found = I915_READ(SFUSE_STRAP); | |
14483 | ||
14484 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14485 | intel_ddi_init(dev, PORT_B); | |
14486 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14487 | intel_ddi_init(dev, PORT_C); | |
14488 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14489 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14490 | /* |
14491 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14492 | */ | |
ef11bdb3 | 14493 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14494 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14495 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14496 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14497 | intel_ddi_init(dev, PORT_E); | |
14498 | ||
0e72a5b5 | 14499 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14500 | int found; |
5d8a7752 | 14501 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14502 | |
14503 | if (has_edp_a(dev)) | |
14504 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14505 | |
dc0fa718 | 14506 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14507 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14508 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14509 | if (!found) |
e2debe91 | 14510 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14511 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14512 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14513 | } |
14514 | ||
dc0fa718 | 14515 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14516 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14517 | |
dc0fa718 | 14518 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14519 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14520 | |
5eb08b69 | 14521 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14522 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14523 | |
270b3042 | 14524 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14525 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14526 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14527 | /* |
14528 | * The DP_DETECTED bit is the latched state of the DDC | |
14529 | * SDA pin at boot. However since eDP doesn't require DDC | |
14530 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14531 | * eDP ports may have been muxed to an alternate function. | |
14532 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14533 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14534 | * detect eDP ports. | |
14535 | */ | |
e66eb81d | 14536 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14537 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14538 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14539 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14540 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14541 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14542 | |
e66eb81d | 14543 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14544 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14545 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14546 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14547 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14548 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14549 | |
9418c1f1 | 14550 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14551 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14552 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14553 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14554 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14555 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14556 | } |
14557 | ||
3cfca973 | 14558 | intel_dsi_init(dev); |
09da55dc | 14559 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14560 | bool found = false; |
7d57382e | 14561 | |
e2debe91 | 14562 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14563 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14564 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14565 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14566 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14567 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14568 | } |
27185ae1 | 14569 | |
3fec3d2f | 14570 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14571 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14572 | } |
13520b05 KH |
14573 | |
14574 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14575 | |
e2debe91 | 14576 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14577 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14578 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14579 | } |
27185ae1 | 14580 | |
e2debe91 | 14581 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14582 | |
3fec3d2f | 14583 | if (IS_G4X(dev)) { |
b01f2c3a | 14584 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14585 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14586 | } |
3fec3d2f | 14587 | if (IS_G4X(dev)) |
ab9d7c30 | 14588 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14589 | } |
27185ae1 | 14590 | |
3fec3d2f | 14591 | if (IS_G4X(dev) && |
e7281eab | 14592 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14593 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14594 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14595 | intel_dvo_init(dev); |
14596 | ||
103a196f | 14597 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14598 | intel_tv_init(dev); |
14599 | ||
0bc12bcb | 14600 | intel_psr_init(dev); |
7c8f8a70 | 14601 | |
b2784e15 | 14602 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14603 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14604 | encoder->base.possible_clones = | |
66a9278e | 14605 | intel_encoder_clones(encoder); |
79e53945 | 14606 | } |
47356eb6 | 14607 | |
dde86e2d | 14608 | intel_init_pch_refclk(dev); |
270b3042 DV |
14609 | |
14610 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14611 | } |
14612 | ||
14613 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14614 | { | |
60a5ca01 | 14615 | struct drm_device *dev = fb->dev; |
79e53945 | 14616 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14617 | |
ef2d633e | 14618 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14619 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14620 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14621 | drm_gem_object_unreference(&intel_fb->obj->base); |
14622 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14623 | kfree(intel_fb); |
14624 | } | |
14625 | ||
14626 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14627 | struct drm_file *file, |
79e53945 JB |
14628 | unsigned int *handle) |
14629 | { | |
14630 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14631 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14632 | |
cc917ab4 CW |
14633 | if (obj->userptr.mm) { |
14634 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14635 | return -EINVAL; | |
14636 | } | |
14637 | ||
05394f39 | 14638 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14639 | } |
14640 | ||
86c98588 RV |
14641 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14642 | struct drm_file *file, | |
14643 | unsigned flags, unsigned color, | |
14644 | struct drm_clip_rect *clips, | |
14645 | unsigned num_clips) | |
14646 | { | |
14647 | struct drm_device *dev = fb->dev; | |
14648 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14649 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14650 | ||
14651 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14652 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14653 | mutex_unlock(&dev->struct_mutex); |
14654 | ||
14655 | return 0; | |
14656 | } | |
14657 | ||
79e53945 JB |
14658 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14659 | .destroy = intel_user_framebuffer_destroy, | |
14660 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14661 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14662 | }; |
14663 | ||
b321803d DL |
14664 | static |
14665 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14666 | uint32_t pixel_format) | |
14667 | { | |
14668 | u32 gen = INTEL_INFO(dev)->gen; | |
14669 | ||
14670 | if (gen >= 9) { | |
ac484963 VS |
14671 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14672 | ||
b321803d DL |
14673 | /* "The stride in bytes must not exceed the of the size of 8K |
14674 | * pixels and 32K bytes." | |
14675 | */ | |
ac484963 | 14676 | return min(8192 * cpp, 32768); |
666a4537 | 14677 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14678 | return 32*1024; |
14679 | } else if (gen >= 4) { | |
14680 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14681 | return 16*1024; | |
14682 | else | |
14683 | return 32*1024; | |
14684 | } else if (gen >= 3) { | |
14685 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14686 | return 8*1024; | |
14687 | else | |
14688 | return 16*1024; | |
14689 | } else { | |
14690 | /* XXX DSPC is limited to 4k tiled */ | |
14691 | return 8*1024; | |
14692 | } | |
14693 | } | |
14694 | ||
b5ea642a DV |
14695 | static int intel_framebuffer_init(struct drm_device *dev, |
14696 | struct intel_framebuffer *intel_fb, | |
14697 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14698 | struct drm_i915_gem_object *obj) | |
79e53945 | 14699 | { |
7b49f948 | 14700 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14701 | unsigned int aligned_height; |
79e53945 | 14702 | int ret; |
b321803d | 14703 | u32 pitch_limit, stride_alignment; |
79e53945 | 14704 | |
dd4916c5 DV |
14705 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14706 | ||
2a80eada DV |
14707 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14708 | /* Enforce that fb modifier and tiling mode match, but only for | |
14709 | * X-tiled. This is needed for FBC. */ | |
14710 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14711 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14712 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14713 | return -EINVAL; | |
14714 | } | |
14715 | } else { | |
14716 | if (obj->tiling_mode == I915_TILING_X) | |
14717 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14718 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14719 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14720 | return -EINVAL; | |
14721 | } | |
14722 | } | |
14723 | ||
9a8f0a12 TU |
14724 | /* Passed in modifier sanity checking. */ |
14725 | switch (mode_cmd->modifier[0]) { | |
14726 | case I915_FORMAT_MOD_Y_TILED: | |
14727 | case I915_FORMAT_MOD_Yf_TILED: | |
14728 | if (INTEL_INFO(dev)->gen < 9) { | |
14729 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14730 | mode_cmd->modifier[0]); | |
14731 | return -EINVAL; | |
14732 | } | |
14733 | case DRM_FORMAT_MOD_NONE: | |
14734 | case I915_FORMAT_MOD_X_TILED: | |
14735 | break; | |
14736 | default: | |
c0f40428 JB |
14737 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14738 | mode_cmd->modifier[0]); | |
57cd6508 | 14739 | return -EINVAL; |
c16ed4be | 14740 | } |
57cd6508 | 14741 | |
7b49f948 VS |
14742 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14743 | mode_cmd->modifier[0], | |
b321803d DL |
14744 | mode_cmd->pixel_format); |
14745 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14746 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14747 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14748 | return -EINVAL; |
c16ed4be | 14749 | } |
57cd6508 | 14750 | |
b321803d DL |
14751 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14752 | mode_cmd->pixel_format); | |
a35cdaa0 | 14753 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14754 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14755 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14756 | "tiled" : "linear", |
a35cdaa0 | 14757 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14758 | return -EINVAL; |
c16ed4be | 14759 | } |
5d7bd705 | 14760 | |
2a80eada | 14761 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14762 | mode_cmd->pitches[0] != obj->stride) { |
14763 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14764 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14765 | return -EINVAL; |
c16ed4be | 14766 | } |
5d7bd705 | 14767 | |
57779d06 | 14768 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14769 | switch (mode_cmd->pixel_format) { |
57779d06 | 14770 | case DRM_FORMAT_C8: |
04b3924d VS |
14771 | case DRM_FORMAT_RGB565: |
14772 | case DRM_FORMAT_XRGB8888: | |
14773 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14774 | break; |
14775 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14776 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14777 | DRM_DEBUG("unsupported pixel format: %s\n", |
14778 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14779 | return -EINVAL; |
c16ed4be | 14780 | } |
57779d06 | 14781 | break; |
57779d06 | 14782 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14783 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14784 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14785 | DRM_DEBUG("unsupported pixel format: %s\n", |
14786 | drm_get_format_name(mode_cmd->pixel_format)); | |
14787 | return -EINVAL; | |
14788 | } | |
14789 | break; | |
14790 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14791 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14792 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14793 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14794 | DRM_DEBUG("unsupported pixel format: %s\n", |
14795 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14796 | return -EINVAL; |
c16ed4be | 14797 | } |
b5626747 | 14798 | break; |
7531208b | 14799 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14800 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14801 | DRM_DEBUG("unsupported pixel format: %s\n", |
14802 | drm_get_format_name(mode_cmd->pixel_format)); | |
14803 | return -EINVAL; | |
14804 | } | |
14805 | break; | |
04b3924d VS |
14806 | case DRM_FORMAT_YUYV: |
14807 | case DRM_FORMAT_UYVY: | |
14808 | case DRM_FORMAT_YVYU: | |
14809 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14810 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14811 | DRM_DEBUG("unsupported pixel format: %s\n", |
14812 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14813 | return -EINVAL; |
c16ed4be | 14814 | } |
57cd6508 CW |
14815 | break; |
14816 | default: | |
4ee62c76 VS |
14817 | DRM_DEBUG("unsupported pixel format: %s\n", |
14818 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14819 | return -EINVAL; |
14820 | } | |
14821 | ||
90f9a336 VS |
14822 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14823 | if (mode_cmd->offsets[0] != 0) | |
14824 | return -EINVAL; | |
14825 | ||
ec2c981e | 14826 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14827 | mode_cmd->pixel_format, |
14828 | mode_cmd->modifier[0]); | |
53155c0a DV |
14829 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14830 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14831 | return -EINVAL; | |
14832 | ||
c7d73f6a DV |
14833 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14834 | intel_fb->obj = obj; | |
14835 | ||
2d7a215f VS |
14836 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
14837 | ||
79e53945 JB |
14838 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14839 | if (ret) { | |
14840 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14841 | return ret; | |
14842 | } | |
14843 | ||
0b05e1e0 VS |
14844 | intel_fb->obj->framebuffer_references++; |
14845 | ||
79e53945 JB |
14846 | return 0; |
14847 | } | |
14848 | ||
79e53945 JB |
14849 | static struct drm_framebuffer * |
14850 | intel_user_framebuffer_create(struct drm_device *dev, | |
14851 | struct drm_file *filp, | |
1eb83451 | 14852 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14853 | { |
dcb1394e | 14854 | struct drm_framebuffer *fb; |
05394f39 | 14855 | struct drm_i915_gem_object *obj; |
76dc3769 | 14856 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14857 | |
308e5bcb | 14858 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14859 | mode_cmd.handles[0])); |
c8725226 | 14860 | if (&obj->base == NULL) |
cce13ff7 | 14861 | return ERR_PTR(-ENOENT); |
79e53945 | 14862 | |
92907cbb | 14863 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14864 | if (IS_ERR(fb)) |
14865 | drm_gem_object_unreference_unlocked(&obj->base); | |
14866 | ||
14867 | return fb; | |
79e53945 JB |
14868 | } |
14869 | ||
0695726e | 14870 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14871 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14872 | { |
14873 | } | |
14874 | #endif | |
14875 | ||
79e53945 | 14876 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14877 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14878 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14879 | .atomic_check = intel_atomic_check, |
14880 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14881 | .atomic_state_alloc = intel_atomic_state_alloc, |
14882 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14883 | }; |
14884 | ||
88212941 ID |
14885 | /** |
14886 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14887 | * @dev_priv: device private | |
14888 | */ | |
14889 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14890 | { |
88212941 | 14891 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14892 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14893 | dev_priv->display.get_initial_plane_config = |
14894 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14895 | dev_priv->display.crtc_compute_clock = |
14896 | haswell_crtc_compute_clock; | |
14897 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14898 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14899 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14900 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14901 | dev_priv->display.get_initial_plane_config = |
14902 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14903 | dev_priv->display.crtc_compute_clock = |
14904 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14905 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14906 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14907 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14908 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14909 | dev_priv->display.get_initial_plane_config = |
14910 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14911 | dev_priv->display.crtc_compute_clock = |
14912 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14913 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14914 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14915 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14916 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14917 | dev_priv->display.get_initial_plane_config = |
14918 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14919 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14920 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14921 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14922 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14923 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14924 | dev_priv->display.get_initial_plane_config = | |
14925 | i9xx_get_initial_plane_config; | |
14926 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14927 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14928 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14929 | } else if (IS_G4X(dev_priv)) { |
14930 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14931 | dev_priv->display.get_initial_plane_config = | |
14932 | i9xx_get_initial_plane_config; | |
14933 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14934 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14935 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14936 | } else if (IS_PINEVIEW(dev_priv)) { |
14937 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14938 | dev_priv->display.get_initial_plane_config = | |
14939 | i9xx_get_initial_plane_config; | |
14940 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14941 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14942 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14943 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14944 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14945 | dev_priv->display.get_initial_plane_config = |
14946 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14947 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14948 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14949 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14950 | } else { |
14951 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14952 | dev_priv->display.get_initial_plane_config = | |
14953 | i9xx_get_initial_plane_config; | |
14954 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14955 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14956 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14957 | } |
e70236a8 | 14958 | |
e70236a8 | 14959 | /* Returns the core display clock speed */ |
88212941 | 14960 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
14961 | dev_priv->display.get_display_clock_speed = |
14962 | skylake_get_display_clock_speed; | |
88212941 | 14963 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
14964 | dev_priv->display.get_display_clock_speed = |
14965 | broxton_get_display_clock_speed; | |
88212941 | 14966 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
14967 | dev_priv->display.get_display_clock_speed = |
14968 | broadwell_get_display_clock_speed; | |
88212941 | 14969 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
14970 | dev_priv->display.get_display_clock_speed = |
14971 | haswell_get_display_clock_speed; | |
88212941 | 14972 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
14973 | dev_priv->display.get_display_clock_speed = |
14974 | valleyview_get_display_clock_speed; | |
88212941 | 14975 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
14976 | dev_priv->display.get_display_clock_speed = |
14977 | ilk_get_display_clock_speed; | |
88212941 ID |
14978 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
14979 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
14980 | dev_priv->display.get_display_clock_speed = |
14981 | i945_get_display_clock_speed; | |
88212941 | 14982 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
14983 | dev_priv->display.get_display_clock_speed = |
14984 | gm45_get_display_clock_speed; | |
88212941 | 14985 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
14986 | dev_priv->display.get_display_clock_speed = |
14987 | i965gm_get_display_clock_speed; | |
88212941 | 14988 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
14989 | dev_priv->display.get_display_clock_speed = |
14990 | pnv_get_display_clock_speed; | |
88212941 | 14991 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
14992 | dev_priv->display.get_display_clock_speed = |
14993 | g33_get_display_clock_speed; | |
88212941 | 14994 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
14995 | dev_priv->display.get_display_clock_speed = |
14996 | i915_get_display_clock_speed; | |
88212941 | 14997 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
14998 | dev_priv->display.get_display_clock_speed = |
14999 | i9xx_misc_get_display_clock_speed; | |
88212941 | 15000 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
15001 | dev_priv->display.get_display_clock_speed = |
15002 | i915gm_get_display_clock_speed; | |
88212941 | 15003 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
15004 | dev_priv->display.get_display_clock_speed = |
15005 | i865_get_display_clock_speed; | |
88212941 | 15006 | else if (IS_I85X(dev_priv)) |
e70236a8 | 15007 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15008 | i85x_get_display_clock_speed; |
623e01e5 | 15009 | else { /* 830 */ |
88212941 | 15010 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
15011 | dev_priv->display.get_display_clock_speed = |
15012 | i830_get_display_clock_speed; | |
623e01e5 | 15013 | } |
e70236a8 | 15014 | |
88212941 | 15015 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 15016 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 15017 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 15018 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 15019 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
15020 | /* FIXME: detect B0+ stepping and use auto training */ |
15021 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 15022 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 15023 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
15024 | } |
15025 | ||
15026 | if (IS_BROADWELL(dev_priv)) { | |
15027 | dev_priv->display.modeset_commit_cdclk = | |
15028 | broadwell_modeset_commit_cdclk; | |
15029 | dev_priv->display.modeset_calc_cdclk = | |
15030 | broadwell_modeset_calc_cdclk; | |
88212941 | 15031 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
15032 | dev_priv->display.modeset_commit_cdclk = |
15033 | valleyview_modeset_commit_cdclk; | |
15034 | dev_priv->display.modeset_calc_cdclk = | |
15035 | valleyview_modeset_calc_cdclk; | |
88212941 | 15036 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed ML |
15037 | dev_priv->display.modeset_commit_cdclk = |
15038 | broxton_modeset_commit_cdclk; | |
15039 | dev_priv->display.modeset_calc_cdclk = | |
15040 | broxton_modeset_calc_cdclk; | |
e70236a8 | 15041 | } |
8c9f3aaf | 15042 | |
88212941 | 15043 | switch (INTEL_INFO(dev_priv)->gen) { |
8c9f3aaf JB |
15044 | case 2: |
15045 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15046 | break; | |
15047 | ||
15048 | case 3: | |
15049 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15050 | break; | |
15051 | ||
15052 | case 4: | |
15053 | case 5: | |
15054 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15055 | break; | |
15056 | ||
15057 | case 6: | |
15058 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15059 | break; | |
7c9017e5 | 15060 | case 7: |
4e0bbc31 | 15061 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15062 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15063 | break; | |
830c81db | 15064 | case 9: |
ba343e02 TU |
15065 | /* Drop through - unsupported since execlist only. */ |
15066 | default: | |
15067 | /* Default just returns -ENODEV to indicate unsupported */ | |
15068 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15069 | } |
e70236a8 JB |
15070 | } |
15071 | ||
b690e96c JB |
15072 | /* |
15073 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15074 | * resume, or other times. This quirk makes sure that's the case for | |
15075 | * affected systems. | |
15076 | */ | |
0206e353 | 15077 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15078 | { |
15079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15080 | ||
15081 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15082 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15083 | } |
15084 | ||
b6b5d049 VS |
15085 | static void quirk_pipeb_force(struct drm_device *dev) |
15086 | { | |
15087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15088 | ||
15089 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15090 | DRM_INFO("applying pipe b force quirk\n"); | |
15091 | } | |
15092 | ||
435793df KP |
15093 | /* |
15094 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15095 | */ | |
15096 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15097 | { | |
15098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15099 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15100 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15101 | } |
15102 | ||
4dca20ef | 15103 | /* |
5a15ab5b CE |
15104 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15105 | * brightness value | |
4dca20ef CE |
15106 | */ |
15107 | static void quirk_invert_brightness(struct drm_device *dev) | |
15108 | { | |
15109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15110 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15111 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15112 | } |
15113 | ||
9c72cc6f SD |
15114 | /* Some VBT's incorrectly indicate no backlight is present */ |
15115 | static void quirk_backlight_present(struct drm_device *dev) | |
15116 | { | |
15117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15118 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15119 | DRM_INFO("applying backlight present quirk\n"); | |
15120 | } | |
15121 | ||
b690e96c JB |
15122 | struct intel_quirk { |
15123 | int device; | |
15124 | int subsystem_vendor; | |
15125 | int subsystem_device; | |
15126 | void (*hook)(struct drm_device *dev); | |
15127 | }; | |
15128 | ||
5f85f176 EE |
15129 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15130 | struct intel_dmi_quirk { | |
15131 | void (*hook)(struct drm_device *dev); | |
15132 | const struct dmi_system_id (*dmi_id_list)[]; | |
15133 | }; | |
15134 | ||
15135 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15136 | { | |
15137 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15138 | return 1; | |
15139 | } | |
15140 | ||
15141 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15142 | { | |
15143 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15144 | { | |
15145 | .callback = intel_dmi_reverse_brightness, | |
15146 | .ident = "NCR Corporation", | |
15147 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15148 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15149 | }, | |
15150 | }, | |
15151 | { } /* terminating entry */ | |
15152 | }, | |
15153 | .hook = quirk_invert_brightness, | |
15154 | }, | |
15155 | }; | |
15156 | ||
c43b5634 | 15157 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15158 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15159 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15160 | ||
b690e96c JB |
15161 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15162 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15163 | ||
5f080c0f VS |
15164 | /* 830 needs to leave pipe A & dpll A up */ |
15165 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15166 | ||
b6b5d049 VS |
15167 | /* 830 needs to leave pipe B & dpll B up */ |
15168 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15169 | ||
435793df KP |
15170 | /* Lenovo U160 cannot use SSC on LVDS */ |
15171 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15172 | |
15173 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15174 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15175 | |
be505f64 AH |
15176 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15177 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15178 | ||
15179 | /* Acer/eMachines G725 */ | |
15180 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15181 | ||
15182 | /* Acer/eMachines e725 */ | |
15183 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15184 | ||
15185 | /* Acer/Packard Bell NCL20 */ | |
15186 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15187 | ||
15188 | /* Acer Aspire 4736Z */ | |
15189 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15190 | |
15191 | /* Acer Aspire 5336 */ | |
15192 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15193 | |
15194 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15195 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15196 | |
dfb3d47b SD |
15197 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15198 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15199 | ||
b2a9601c | 15200 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15201 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15202 | ||
1b9448b0 JN |
15203 | /* Apple Macbook 4,1 */ |
15204 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15205 | ||
d4967d8c SD |
15206 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15207 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15208 | |
15209 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15210 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15211 | |
15212 | /* Dell Chromebook 11 */ | |
15213 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15214 | |
15215 | /* Dell Chromebook 11 (2015 version) */ | |
15216 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15217 | }; |
15218 | ||
15219 | static void intel_init_quirks(struct drm_device *dev) | |
15220 | { | |
15221 | struct pci_dev *d = dev->pdev; | |
15222 | int i; | |
15223 | ||
15224 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15225 | struct intel_quirk *q = &intel_quirks[i]; | |
15226 | ||
15227 | if (d->device == q->device && | |
15228 | (d->subsystem_vendor == q->subsystem_vendor || | |
15229 | q->subsystem_vendor == PCI_ANY_ID) && | |
15230 | (d->subsystem_device == q->subsystem_device || | |
15231 | q->subsystem_device == PCI_ANY_ID)) | |
15232 | q->hook(dev); | |
15233 | } | |
5f85f176 EE |
15234 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15235 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15236 | intel_dmi_quirks[i].hook(dev); | |
15237 | } | |
b690e96c JB |
15238 | } |
15239 | ||
9cce37f4 JB |
15240 | /* Disable the VGA plane that we never use */ |
15241 | static void i915_disable_vga(struct drm_device *dev) | |
15242 | { | |
15243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15244 | u8 sr1; | |
f0f59a00 | 15245 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15246 | |
2b37c616 | 15247 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15248 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15249 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15250 | sr1 = inb(VGA_SR_DATA); |
15251 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15252 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15253 | udelay(300); | |
15254 | ||
01f5a626 | 15255 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15256 | POSTING_READ(vga_reg); |
15257 | } | |
15258 | ||
f817586c DV |
15259 | void intel_modeset_init_hw(struct drm_device *dev) |
15260 | { | |
1a617b77 ML |
15261 | struct drm_i915_private *dev_priv = dev->dev_private; |
15262 | ||
b6283055 | 15263 | intel_update_cdclk(dev); |
1a617b77 ML |
15264 | |
15265 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15266 | ||
f817586c | 15267 | intel_init_clock_gating(dev); |
dc97997a | 15268 | intel_enable_gt_powersave(dev_priv); |
f817586c DV |
15269 | } |
15270 | ||
d93c0372 MR |
15271 | /* |
15272 | * Calculate what we think the watermarks should be for the state we've read | |
15273 | * out of the hardware and then immediately program those watermarks so that | |
15274 | * we ensure the hardware settings match our internal state. | |
15275 | * | |
15276 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15277 | * current state (which was constructed during hardware readout) and running it | |
15278 | * through the atomic check code to calculate new watermark values in the | |
15279 | * state object. | |
15280 | */ | |
15281 | static void sanitize_watermarks(struct drm_device *dev) | |
15282 | { | |
15283 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15284 | struct drm_atomic_state *state; | |
15285 | struct drm_crtc *crtc; | |
15286 | struct drm_crtc_state *cstate; | |
15287 | struct drm_modeset_acquire_ctx ctx; | |
15288 | int ret; | |
15289 | int i; | |
15290 | ||
15291 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15292 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15293 | return; |
15294 | ||
15295 | /* | |
15296 | * We need to hold connection_mutex before calling duplicate_state so | |
15297 | * that the connector loop is protected. | |
15298 | */ | |
15299 | drm_modeset_acquire_init(&ctx, 0); | |
15300 | retry: | |
0cd1262d | 15301 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15302 | if (ret == -EDEADLK) { |
15303 | drm_modeset_backoff(&ctx); | |
15304 | goto retry; | |
15305 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15306 | goto fail; |
d93c0372 MR |
15307 | } |
15308 | ||
15309 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15310 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15311 | goto fail; |
d93c0372 | 15312 | |
ed4a6a7c MR |
15313 | /* |
15314 | * Hardware readout is the only time we don't want to calculate | |
15315 | * intermediate watermarks (since we don't trust the current | |
15316 | * watermarks). | |
15317 | */ | |
15318 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15319 | ||
d93c0372 MR |
15320 | ret = intel_atomic_check(dev, state); |
15321 | if (ret) { | |
15322 | /* | |
15323 | * If we fail here, it means that the hardware appears to be | |
15324 | * programmed in a way that shouldn't be possible, given our | |
15325 | * understanding of watermark requirements. This might mean a | |
15326 | * mistake in the hardware readout code or a mistake in the | |
15327 | * watermark calculations for a given platform. Raise a WARN | |
15328 | * so that this is noticeable. | |
15329 | * | |
15330 | * If this actually happens, we'll have to just leave the | |
15331 | * BIOS-programmed watermarks untouched and hope for the best. | |
15332 | */ | |
15333 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15334 | goto fail; |
d93c0372 MR |
15335 | } |
15336 | ||
15337 | /* Write calculated watermark values back */ | |
d93c0372 MR |
15338 | for_each_crtc_in_state(state, crtc, cstate, i) { |
15339 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15340 | ||
ed4a6a7c MR |
15341 | cs->wm.need_postvbl_update = true; |
15342 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15343 | } |
15344 | ||
15345 | drm_atomic_state_free(state); | |
0cd1262d | 15346 | fail: |
d93c0372 MR |
15347 | drm_modeset_drop_locks(&ctx); |
15348 | drm_modeset_acquire_fini(&ctx); | |
15349 | } | |
15350 | ||
79e53945 JB |
15351 | void intel_modeset_init(struct drm_device *dev) |
15352 | { | |
72e96d64 JL |
15353 | struct drm_i915_private *dev_priv = to_i915(dev); |
15354 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1fe47785 | 15355 | int sprite, ret; |
8cc87b75 | 15356 | enum pipe pipe; |
46f297fb | 15357 | struct intel_crtc *crtc; |
79e53945 JB |
15358 | |
15359 | drm_mode_config_init(dev); | |
15360 | ||
15361 | dev->mode_config.min_width = 0; | |
15362 | dev->mode_config.min_height = 0; | |
15363 | ||
019d96cb DA |
15364 | dev->mode_config.preferred_depth = 24; |
15365 | dev->mode_config.prefer_shadow = 1; | |
15366 | ||
25bab385 TU |
15367 | dev->mode_config.allow_fb_modifiers = true; |
15368 | ||
e6ecefaa | 15369 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15370 | |
b690e96c JB |
15371 | intel_init_quirks(dev); |
15372 | ||
1fa61106 ED |
15373 | intel_init_pm(dev); |
15374 | ||
e3c74757 BW |
15375 | if (INTEL_INFO(dev)->num_pipes == 0) |
15376 | return; | |
15377 | ||
69f92f67 LW |
15378 | /* |
15379 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15380 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15381 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15382 | * indicates as much. | |
15383 | */ | |
15384 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15385 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15386 | DREF_SSC1_ENABLE); | |
15387 | ||
15388 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15389 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15390 | bios_lvds_use_ssc ? "en" : "dis", | |
15391 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15392 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15393 | } | |
15394 | } | |
15395 | ||
a6c45cf0 CW |
15396 | if (IS_GEN2(dev)) { |
15397 | dev->mode_config.max_width = 2048; | |
15398 | dev->mode_config.max_height = 2048; | |
15399 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15400 | dev->mode_config.max_width = 4096; |
15401 | dev->mode_config.max_height = 4096; | |
79e53945 | 15402 | } else { |
a6c45cf0 CW |
15403 | dev->mode_config.max_width = 8192; |
15404 | dev->mode_config.max_height = 8192; | |
79e53945 | 15405 | } |
068be561 | 15406 | |
dc41c154 VS |
15407 | if (IS_845G(dev) || IS_I865G(dev)) { |
15408 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15409 | dev->mode_config.cursor_height = 1023; | |
15410 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15411 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15412 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15413 | } else { | |
15414 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15415 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15416 | } | |
15417 | ||
72e96d64 | 15418 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 15419 | |
28c97730 | 15420 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15421 | INTEL_INFO(dev)->num_pipes, |
15422 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15423 | |
055e393f | 15424 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15425 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15426 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15427 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15428 | if (ret) |
06da8da2 | 15429 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15430 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15431 | } |
79e53945 JB |
15432 | } |
15433 | ||
bfa7df01 VS |
15434 | intel_update_czclk(dev_priv); |
15435 | intel_update_cdclk(dev); | |
15436 | ||
e72f9fbf | 15437 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15438 | |
9cce37f4 JB |
15439 | /* Just disable it once at startup */ |
15440 | i915_disable_vga(dev); | |
79e53945 | 15441 | intel_setup_outputs(dev); |
11be49eb | 15442 | |
6e9f798d | 15443 | drm_modeset_lock_all(dev); |
043e9bda | 15444 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15445 | drm_modeset_unlock_all(dev); |
46f297fb | 15446 | |
d3fcc808 | 15447 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15448 | struct intel_initial_plane_config plane_config = {}; |
15449 | ||
46f297fb JB |
15450 | if (!crtc->active) |
15451 | continue; | |
15452 | ||
46f297fb | 15453 | /* |
46f297fb JB |
15454 | * Note that reserving the BIOS fb up front prevents us |
15455 | * from stuffing other stolen allocations like the ring | |
15456 | * on top. This prevents some ugliness at boot time, and | |
15457 | * can even allow for smooth boot transitions if the BIOS | |
15458 | * fb is large enough for the active pipe configuration. | |
15459 | */ | |
eeebeac5 ML |
15460 | dev_priv->display.get_initial_plane_config(crtc, |
15461 | &plane_config); | |
15462 | ||
15463 | /* | |
15464 | * If the fb is shared between multiple heads, we'll | |
15465 | * just get the first one. | |
15466 | */ | |
15467 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15468 | } |
d93c0372 MR |
15469 | |
15470 | /* | |
15471 | * Make sure hardware watermarks really match the state we read out. | |
15472 | * Note that we need to do this after reconstructing the BIOS fb's | |
15473 | * since the watermark calculation done here will use pstate->fb. | |
15474 | */ | |
15475 | sanitize_watermarks(dev); | |
2c7111db CW |
15476 | } |
15477 | ||
7fad798e DV |
15478 | static void intel_enable_pipe_a(struct drm_device *dev) |
15479 | { | |
15480 | struct intel_connector *connector; | |
15481 | struct drm_connector *crt = NULL; | |
15482 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15483 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15484 | |
15485 | /* We can't just switch on the pipe A, we need to set things up with a | |
15486 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15487 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15488 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15489 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15490 | crt = &connector->base; | |
15491 | break; | |
15492 | } | |
15493 | } | |
15494 | ||
15495 | if (!crt) | |
15496 | return; | |
15497 | ||
208bf9fd | 15498 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15499 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15500 | } |
15501 | ||
fa555837 DV |
15502 | static bool |
15503 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15504 | { | |
7eb552ae BW |
15505 | struct drm_device *dev = crtc->base.dev; |
15506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15507 | u32 val; |
fa555837 | 15508 | |
7eb552ae | 15509 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15510 | return true; |
15511 | ||
649636ef | 15512 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15513 | |
15514 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15515 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15516 | return false; | |
15517 | ||
15518 | return true; | |
15519 | } | |
15520 | ||
02e93c35 VS |
15521 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15522 | { | |
15523 | struct drm_device *dev = crtc->base.dev; | |
15524 | struct intel_encoder *encoder; | |
15525 | ||
15526 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15527 | return true; | |
15528 | ||
15529 | return false; | |
15530 | } | |
15531 | ||
dd756198 VS |
15532 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15533 | { | |
15534 | struct drm_device *dev = encoder->base.dev; | |
15535 | struct intel_connector *connector; | |
15536 | ||
15537 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15538 | return true; | |
15539 | ||
15540 | return false; | |
15541 | } | |
15542 | ||
24929352 DV |
15543 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15544 | { | |
15545 | struct drm_device *dev = crtc->base.dev; | |
15546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4d1de975 | 15547 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15548 | |
24929352 | 15549 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15550 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15551 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15552 | ||
15553 | I915_WRITE(reg, | |
15554 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15555 | } | |
24929352 | 15556 | |
d3eaf884 | 15557 | /* restore vblank interrupts to correct state */ |
9625604c | 15558 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15559 | if (crtc->active) { |
f9cd7b88 VS |
15560 | struct intel_plane *plane; |
15561 | ||
9625604c | 15562 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15563 | |
15564 | /* Disable everything but the primary plane */ | |
15565 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15566 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15567 | continue; | |
15568 | ||
15569 | plane->disable_plane(&plane->base, &crtc->base); | |
15570 | } | |
9625604c | 15571 | } |
d3eaf884 | 15572 | |
24929352 | 15573 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15574 | * disable the crtc (and hence change the state) if it is wrong. Note |
15575 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15576 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15577 | bool plane; |
15578 | ||
24929352 DV |
15579 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15580 | crtc->base.base.id); | |
15581 | ||
15582 | /* Pipe has the wrong plane attached and the plane is active. | |
15583 | * Temporarily change the plane mapping and disable everything | |
15584 | * ... */ | |
15585 | plane = crtc->plane; | |
b70709a6 | 15586 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15587 | crtc->plane = !plane; |
b17d48e2 | 15588 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15589 | crtc->plane = plane; |
24929352 | 15590 | } |
24929352 | 15591 | |
7fad798e DV |
15592 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15593 | crtc->pipe == PIPE_A && !crtc->active) { | |
15594 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15595 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15596 | * call below we restore the pipe to the right state, but leave | |
15597 | * the required bits on. */ | |
15598 | intel_enable_pipe_a(dev); | |
15599 | } | |
15600 | ||
24929352 DV |
15601 | /* Adjust the state of the output pipe according to whether we |
15602 | * have active connectors/encoders. */ | |
842e0307 | 15603 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15604 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15605 | |
a3ed6aad | 15606 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15607 | /* |
15608 | * We start out with underrun reporting disabled to avoid races. | |
15609 | * For correct bookkeeping mark this on active crtcs. | |
15610 | * | |
c5ab3bc0 DV |
15611 | * Also on gmch platforms we dont have any hardware bits to |
15612 | * disable the underrun reporting. Which means we need to start | |
15613 | * out with underrun reporting disabled also on inactive pipes, | |
15614 | * since otherwise we'll complain about the garbage we read when | |
15615 | * e.g. coming up after runtime pm. | |
15616 | * | |
4cc31489 DV |
15617 | * No protection against concurrent access is required - at |
15618 | * worst a fifo underrun happens which also sets this to false. | |
15619 | */ | |
15620 | crtc->cpu_fifo_underrun_disabled = true; | |
15621 | crtc->pch_fifo_underrun_disabled = true; | |
15622 | } | |
24929352 DV |
15623 | } |
15624 | ||
15625 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15626 | { | |
15627 | struct intel_connector *connector; | |
15628 | struct drm_device *dev = encoder->base.dev; | |
15629 | ||
15630 | /* We need to check both for a crtc link (meaning that the | |
15631 | * encoder is active and trying to read from a pipe) and the | |
15632 | * pipe itself being active. */ | |
15633 | bool has_active_crtc = encoder->base.crtc && | |
15634 | to_intel_crtc(encoder->base.crtc)->active; | |
15635 | ||
dd756198 | 15636 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15637 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15638 | encoder->base.base.id, | |
8e329a03 | 15639 | encoder->base.name); |
24929352 DV |
15640 | |
15641 | /* Connector is active, but has no active pipe. This is | |
15642 | * fallout from our resume register restoring. Disable | |
15643 | * the encoder manually again. */ | |
15644 | if (encoder->base.crtc) { | |
15645 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15646 | encoder->base.base.id, | |
8e329a03 | 15647 | encoder->base.name); |
24929352 | 15648 | encoder->disable(encoder); |
a62d1497 VS |
15649 | if (encoder->post_disable) |
15650 | encoder->post_disable(encoder); | |
24929352 | 15651 | } |
7f1950fb | 15652 | encoder->base.crtc = NULL; |
24929352 DV |
15653 | |
15654 | /* Inconsistent output/port/pipe state happens presumably due to | |
15655 | * a bug in one of the get_hw_state functions. Or someplace else | |
15656 | * in our code, like the register restore mess on resume. Clamp | |
15657 | * things to off as a safer default. */ | |
3a3371ff | 15658 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15659 | if (connector->encoder != encoder) |
15660 | continue; | |
7f1950fb EE |
15661 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15662 | connector->base.encoder = NULL; | |
24929352 DV |
15663 | } |
15664 | } | |
15665 | /* Enabled encoders without active connectors will be fixed in | |
15666 | * the crtc fixup. */ | |
15667 | } | |
15668 | ||
04098753 | 15669 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15670 | { |
15671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15672 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15673 | |
04098753 ID |
15674 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15675 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15676 | i915_disable_vga(dev); | |
15677 | } | |
15678 | } | |
15679 | ||
15680 | void i915_redisable_vga(struct drm_device *dev) | |
15681 | { | |
15682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15683 | ||
8dc8a27c PZ |
15684 | /* This function can be called both from intel_modeset_setup_hw_state or |
15685 | * at a very early point in our resume sequence, where the power well | |
15686 | * structures are not yet restored. Since this function is at a very | |
15687 | * paranoid "someone might have enabled VGA while we were not looking" | |
15688 | * level, just check if the power well is enabled instead of trying to | |
15689 | * follow the "don't touch the power well if we don't need it" policy | |
15690 | * the rest of the driver uses. */ | |
6392f847 | 15691 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15692 | return; |
15693 | ||
04098753 | 15694 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15695 | |
15696 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15697 | } |
15698 | ||
f9cd7b88 | 15699 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15700 | { |
f9cd7b88 | 15701 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15702 | |
f9cd7b88 | 15703 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15704 | } |
15705 | ||
f9cd7b88 VS |
15706 | /* FIXME read out full plane state for all planes */ |
15707 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15708 | { |
b26d3ea3 | 15709 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15710 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15711 | to_intel_plane_state(primary->state); |
d032ffa0 | 15712 | |
19b8d387 | 15713 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15714 | primary_get_hw_state(to_intel_plane(primary)); |
15715 | ||
15716 | if (plane_state->visible) | |
15717 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15718 | } |
15719 | ||
30e984df | 15720 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15721 | { |
15722 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15723 | enum pipe pipe; | |
24929352 DV |
15724 | struct intel_crtc *crtc; |
15725 | struct intel_encoder *encoder; | |
15726 | struct intel_connector *connector; | |
5358901f | 15727 | int i; |
24929352 | 15728 | |
565602d7 ML |
15729 | dev_priv->active_crtcs = 0; |
15730 | ||
d3fcc808 | 15731 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15732 | struct intel_crtc_state *crtc_state = crtc->config; |
15733 | int pixclk = 0; | |
3b117c8f | 15734 | |
565602d7 ML |
15735 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15736 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15737 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15738 | |
565602d7 ML |
15739 | crtc_state->base.active = crtc_state->base.enable = |
15740 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15741 | ||
15742 | crtc->base.enabled = crtc_state->base.enable; | |
15743 | crtc->active = crtc_state->base.active; | |
15744 | ||
15745 | if (crtc_state->base.active) { | |
15746 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15747 | ||
15748 | if (IS_BROADWELL(dev_priv)) { | |
15749 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15750 | ||
15751 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15752 | if (crtc_state->ips_enabled) | |
15753 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15754 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15755 | IS_CHERRYVIEW(dev_priv) || | |
15756 | IS_BROXTON(dev_priv)) | |
15757 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15758 | else | |
15759 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15760 | } | |
15761 | ||
15762 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15763 | |
f9cd7b88 | 15764 | readout_plane_state(crtc); |
24929352 DV |
15765 | |
15766 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15767 | crtc->base.base.id, | |
15768 | crtc->active ? "enabled" : "disabled"); | |
15769 | } | |
15770 | ||
5358901f DV |
15771 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15772 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15773 | ||
2edd6443 ACO |
15774 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
15775 | &pll->config.hw_state); | |
3e369b76 | 15776 | pll->config.crtc_mask = 0; |
d3fcc808 | 15777 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 15778 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 15779 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15780 | } |
2dd66ebd | 15781 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 15782 | |
1e6f2ddc | 15783 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15784 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
15785 | } |
15786 | ||
b2784e15 | 15787 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15788 | pipe = 0; |
15789 | ||
15790 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15791 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15792 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15793 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15794 | } else { |
15795 | encoder->base.crtc = NULL; | |
15796 | } | |
15797 | ||
6f2bcceb | 15798 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15799 | encoder->base.base.id, |
8e329a03 | 15800 | encoder->base.name, |
24929352 | 15801 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15802 | pipe_name(pipe)); |
24929352 DV |
15803 | } |
15804 | ||
3a3371ff | 15805 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15806 | if (connector->get_hw_state(connector)) { |
15807 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15808 | |
15809 | encoder = connector->encoder; | |
15810 | connector->base.encoder = &encoder->base; | |
15811 | ||
15812 | if (encoder->base.crtc && | |
15813 | encoder->base.crtc->state->active) { | |
15814 | /* | |
15815 | * This has to be done during hardware readout | |
15816 | * because anything calling .crtc_disable may | |
15817 | * rely on the connector_mask being accurate. | |
15818 | */ | |
15819 | encoder->base.crtc->state->connector_mask |= | |
15820 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15821 | encoder->base.crtc->state->encoder_mask |= |
15822 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15823 | } |
15824 | ||
24929352 DV |
15825 | } else { |
15826 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15827 | connector->base.encoder = NULL; | |
15828 | } | |
15829 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15830 | connector->base.base.id, | |
c23cc417 | 15831 | connector->base.name, |
24929352 DV |
15832 | connector->base.encoder ? "enabled" : "disabled"); |
15833 | } | |
7f4c6284 VS |
15834 | |
15835 | for_each_intel_crtc(dev, crtc) { | |
15836 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15837 | ||
15838 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15839 | if (crtc->base.state->active) { | |
15840 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15841 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15842 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15843 | ||
15844 | /* | |
15845 | * The initial mode needs to be set in order to keep | |
15846 | * the atomic core happy. It wants a valid mode if the | |
15847 | * crtc's enabled, so we do the above call. | |
15848 | * | |
15849 | * At this point some state updated by the connectors | |
15850 | * in their ->detect() callback has not run yet, so | |
15851 | * no recalculation can be done yet. | |
15852 | * | |
15853 | * Even if we could do a recalculation and modeset | |
15854 | * right now it would cause a double modeset if | |
15855 | * fbdev or userspace chooses a different initial mode. | |
15856 | * | |
15857 | * If that happens, someone indicated they wanted a | |
15858 | * mode change, which means it's safe to do a full | |
15859 | * recalculation. | |
15860 | */ | |
15861 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15862 | |
15863 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15864 | update_scanline_offset(crtc); | |
7f4c6284 | 15865 | } |
e3b247da VS |
15866 | |
15867 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 15868 | } |
30e984df DV |
15869 | } |
15870 | ||
043e9bda ML |
15871 | /* Scan out the current hw modeset state, |
15872 | * and sanitizes it to the current state | |
15873 | */ | |
15874 | static void | |
15875 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15876 | { |
15877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15878 | enum pipe pipe; | |
30e984df DV |
15879 | struct intel_crtc *crtc; |
15880 | struct intel_encoder *encoder; | |
35c95375 | 15881 | int i; |
30e984df DV |
15882 | |
15883 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15884 | |
15885 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15886 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15887 | intel_sanitize_encoder(encoder); |
15888 | } | |
15889 | ||
055e393f | 15890 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15891 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15892 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15893 | intel_dump_pipe_config(crtc, crtc->config, |
15894 | "[setup_hw_state]"); | |
24929352 | 15895 | } |
9a935856 | 15896 | |
d29b2f9d ACO |
15897 | intel_modeset_update_connector_atomic_state(dev); |
15898 | ||
35c95375 DV |
15899 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15900 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15901 | ||
2dd66ebd | 15902 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15903 | continue; |
15904 | ||
15905 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15906 | ||
2edd6443 | 15907 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15908 | pll->on = false; |
15909 | } | |
15910 | ||
666a4537 | 15911 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15912 | vlv_wm_get_hw_state(dev); |
15913 | else if (IS_GEN9(dev)) | |
3078999f PB |
15914 | skl_wm_get_hw_state(dev); |
15915 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15916 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15917 | |
15918 | for_each_intel_crtc(dev, crtc) { | |
15919 | unsigned long put_domains; | |
15920 | ||
74bff5f9 | 15921 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15922 | if (WARN_ON(put_domains)) |
15923 | modeset_put_power_domains(dev_priv, put_domains); | |
15924 | } | |
15925 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
15926 | |
15927 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 15928 | } |
7d0bc1ea | 15929 | |
043e9bda ML |
15930 | void intel_display_resume(struct drm_device *dev) |
15931 | { | |
e2c8b870 ML |
15932 | struct drm_i915_private *dev_priv = to_i915(dev); |
15933 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15934 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15935 | int ret; |
e2c8b870 | 15936 | bool setup = false; |
f30da187 | 15937 | |
e2c8b870 | 15938 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 15939 | |
ea49c9ac ML |
15940 | /* |
15941 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15942 | * won't be taken. Unfortunately some probed state like | |
15943 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15944 | * it here for now. | |
15945 | */ | |
15946 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 15947 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15948 | |
e2c8b870 ML |
15949 | retry: |
15950 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 15951 | |
e2c8b870 ML |
15952 | if (ret == 0 && !setup) { |
15953 | setup = true; | |
043e9bda | 15954 | |
e2c8b870 ML |
15955 | intel_modeset_setup_hw_state(dev); |
15956 | i915_redisable_vga(dev); | |
45e2b5f6 | 15957 | } |
8af6cf88 | 15958 | |
e2c8b870 ML |
15959 | if (ret == 0 && state) { |
15960 | struct drm_crtc_state *crtc_state; | |
15961 | struct drm_crtc *crtc; | |
15962 | int i; | |
043e9bda | 15963 | |
e2c8b870 ML |
15964 | state->acquire_ctx = &ctx; |
15965 | ||
15966 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
15967 | /* | |
15968 | * Force recalculation even if we restore | |
15969 | * current state. With fast modeset this may not result | |
15970 | * in a modeset when the state is compatible. | |
15971 | */ | |
15972 | crtc_state->mode_changed = true; | |
15973 | } | |
15974 | ||
15975 | ret = drm_atomic_commit(state); | |
043e9bda ML |
15976 | } |
15977 | ||
e2c8b870 ML |
15978 | if (ret == -EDEADLK) { |
15979 | drm_modeset_backoff(&ctx); | |
15980 | goto retry; | |
15981 | } | |
043e9bda | 15982 | |
e2c8b870 ML |
15983 | drm_modeset_drop_locks(&ctx); |
15984 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 15985 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 15986 | |
e2c8b870 ML |
15987 | if (ret) { |
15988 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15989 | drm_atomic_state_free(state); | |
15990 | } | |
2c7111db CW |
15991 | } |
15992 | ||
15993 | void intel_modeset_gem_init(struct drm_device *dev) | |
15994 | { | |
dc97997a | 15995 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15996 | struct drm_crtc *c; |
2ff8fde1 | 15997 | struct drm_i915_gem_object *obj; |
e0d6149b | 15998 | int ret; |
484b41dd | 15999 | |
dc97997a | 16000 | intel_init_gt_powersave(dev_priv); |
ae48434c | 16001 | |
1833b134 | 16002 | intel_modeset_init_hw(dev); |
02e792fb | 16003 | |
1ee8da6d | 16004 | intel_setup_overlay(dev_priv); |
484b41dd JB |
16005 | |
16006 | /* | |
16007 | * Make sure any fbs we allocated at startup are properly | |
16008 | * pinned & fenced. When we do the allocation it's too early | |
16009 | * for this. | |
16010 | */ | |
70e1e0ec | 16011 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16012 | obj = intel_fb_obj(c->primary->fb); |
16013 | if (obj == NULL) | |
484b41dd JB |
16014 | continue; |
16015 | ||
e0d6149b | 16016 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
16017 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
16018 | c->primary->state->rotation); | |
e0d6149b TU |
16019 | mutex_unlock(&dev->struct_mutex); |
16020 | if (ret) { | |
484b41dd JB |
16021 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16022 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
16023 | drm_framebuffer_unreference(c->primary->fb); |
16024 | c->primary->fb = NULL; | |
36750f28 | 16025 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 16026 | update_state_fb(c->primary); |
36750f28 | 16027 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16028 | } |
16029 | } | |
0962c3c9 VS |
16030 | |
16031 | intel_backlight_register(dev); | |
79e53945 JB |
16032 | } |
16033 | ||
4932e2c3 ID |
16034 | void intel_connector_unregister(struct intel_connector *intel_connector) |
16035 | { | |
16036 | struct drm_connector *connector = &intel_connector->base; | |
16037 | ||
16038 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 16039 | drm_connector_unregister(connector); |
4932e2c3 ID |
16040 | } |
16041 | ||
79e53945 JB |
16042 | void intel_modeset_cleanup(struct drm_device *dev) |
16043 | { | |
652c393a | 16044 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 16045 | struct intel_connector *connector; |
652c393a | 16046 | |
dc97997a | 16047 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 16048 | |
0962c3c9 VS |
16049 | intel_backlight_unregister(dev); |
16050 | ||
fd0c0642 DV |
16051 | /* |
16052 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16053 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16054 | * experience fancy races otherwise. |
16055 | */ | |
2aeb7d3a | 16056 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16057 | |
fd0c0642 DV |
16058 | /* |
16059 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16060 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16061 | */ | |
f87ea761 | 16062 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16063 | |
723bfd70 JB |
16064 | intel_unregister_dsm_handler(); |
16065 | ||
c937ab3e | 16066 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16067 | |
1630fe75 CW |
16068 | /* flush any delayed tasks or pending work */ |
16069 | flush_scheduled_work(); | |
16070 | ||
db31af1d | 16071 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16072 | for_each_intel_connector(dev, connector) |
16073 | connector->unregister(connector); | |
d9255d57 | 16074 | |
79e53945 | 16075 | drm_mode_config_cleanup(dev); |
4d7bb011 | 16076 | |
1ee8da6d | 16077 | intel_cleanup_overlay(dev_priv); |
ae48434c | 16078 | |
dc97997a | 16079 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
16080 | |
16081 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16082 | } |
16083 | ||
f1c79df3 ZW |
16084 | /* |
16085 | * Return which encoder is currently attached for connector. | |
16086 | */ | |
df0e9248 | 16087 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16088 | { |
df0e9248 CW |
16089 | return &intel_attached_encoder(connector)->base; |
16090 | } | |
f1c79df3 | 16091 | |
df0e9248 CW |
16092 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16093 | struct intel_encoder *encoder) | |
16094 | { | |
16095 | connector->encoder = encoder; | |
16096 | drm_mode_connector_attach_encoder(&connector->base, | |
16097 | &encoder->base); | |
79e53945 | 16098 | } |
28d52043 DA |
16099 | |
16100 | /* | |
16101 | * set vga decode state - true == enable VGA decode | |
16102 | */ | |
16103 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16104 | { | |
16105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16106 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16107 | u16 gmch_ctrl; |
16108 | ||
75fa041d CW |
16109 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16110 | DRM_ERROR("failed to read control word\n"); | |
16111 | return -EIO; | |
16112 | } | |
16113 | ||
c0cc8a55 CW |
16114 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16115 | return 0; | |
16116 | ||
28d52043 DA |
16117 | if (state) |
16118 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16119 | else | |
16120 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16121 | |
16122 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16123 | DRM_ERROR("failed to write control word\n"); | |
16124 | return -EIO; | |
16125 | } | |
16126 | ||
28d52043 DA |
16127 | return 0; |
16128 | } | |
c4a1d9e4 | 16129 | |
c4a1d9e4 | 16130 | struct intel_display_error_state { |
ff57f1b0 PZ |
16131 | |
16132 | u32 power_well_driver; | |
16133 | ||
63b66e5b CW |
16134 | int num_transcoders; |
16135 | ||
c4a1d9e4 CW |
16136 | struct intel_cursor_error_state { |
16137 | u32 control; | |
16138 | u32 position; | |
16139 | u32 base; | |
16140 | u32 size; | |
52331309 | 16141 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16142 | |
16143 | struct intel_pipe_error_state { | |
ddf9c536 | 16144 | bool power_domain_on; |
c4a1d9e4 | 16145 | u32 source; |
f301b1e1 | 16146 | u32 stat; |
52331309 | 16147 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16148 | |
16149 | struct intel_plane_error_state { | |
16150 | u32 control; | |
16151 | u32 stride; | |
16152 | u32 size; | |
16153 | u32 pos; | |
16154 | u32 addr; | |
16155 | u32 surface; | |
16156 | u32 tile_offset; | |
52331309 | 16157 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16158 | |
16159 | struct intel_transcoder_error_state { | |
ddf9c536 | 16160 | bool power_domain_on; |
63b66e5b CW |
16161 | enum transcoder cpu_transcoder; |
16162 | ||
16163 | u32 conf; | |
16164 | ||
16165 | u32 htotal; | |
16166 | u32 hblank; | |
16167 | u32 hsync; | |
16168 | u32 vtotal; | |
16169 | u32 vblank; | |
16170 | u32 vsync; | |
16171 | } transcoder[4]; | |
c4a1d9e4 CW |
16172 | }; |
16173 | ||
16174 | struct intel_display_error_state * | |
c033666a | 16175 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 16176 | { |
c4a1d9e4 | 16177 | struct intel_display_error_state *error; |
63b66e5b CW |
16178 | int transcoders[] = { |
16179 | TRANSCODER_A, | |
16180 | TRANSCODER_B, | |
16181 | TRANSCODER_C, | |
16182 | TRANSCODER_EDP, | |
16183 | }; | |
c4a1d9e4 CW |
16184 | int i; |
16185 | ||
c033666a | 16186 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
16187 | return NULL; |
16188 | ||
9d1cb914 | 16189 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16190 | if (error == NULL) |
16191 | return NULL; | |
16192 | ||
c033666a | 16193 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
16194 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16195 | ||
055e393f | 16196 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16197 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16198 | __intel_display_power_is_enabled(dev_priv, |
16199 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16200 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16201 | continue; |
16202 | ||
5efb3e28 VS |
16203 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16204 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16205 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16206 | |
16207 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16208 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 16209 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 16210 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16211 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16212 | } | |
c033666a | 16213 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 16214 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 16215 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
16216 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
16217 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16218 | } | |
16219 | ||
c4a1d9e4 | 16220 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16221 | |
c033666a | 16222 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 16223 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16224 | } |
16225 | ||
4d1de975 | 16226 | /* Note: this does not include DSI transcoders. */ |
c033666a | 16227 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 16228 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
16229 | error->num_transcoders++; /* Account for eDP. */ |
16230 | ||
16231 | for (i = 0; i < error->num_transcoders; i++) { | |
16232 | enum transcoder cpu_transcoder = transcoders[i]; | |
16233 | ||
ddf9c536 | 16234 | error->transcoder[i].power_domain_on = |
f458ebbc | 16235 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16236 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16237 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16238 | continue; |
16239 | ||
63b66e5b CW |
16240 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16241 | ||
16242 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16243 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16244 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16245 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16246 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16247 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16248 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16249 | } |
16250 | ||
16251 | return error; | |
16252 | } | |
16253 | ||
edc3d884 MK |
16254 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16255 | ||
c4a1d9e4 | 16256 | void |
edc3d884 | 16257 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16258 | struct drm_device *dev, |
16259 | struct intel_display_error_state *error) | |
16260 | { | |
055e393f | 16261 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16262 | int i; |
16263 | ||
63b66e5b CW |
16264 | if (!error) |
16265 | return; | |
16266 | ||
edc3d884 | 16267 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16268 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16269 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16270 | error->power_well_driver); |
055e393f | 16271 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16272 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16273 | err_printf(m, " Power: %s\n", |
87ad3212 | 16274 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16275 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16276 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16277 | |
16278 | err_printf(m, "Plane [%d]:\n", i); | |
16279 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16280 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16281 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16282 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16283 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16284 | } |
4b71a570 | 16285 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16286 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16287 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16288 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16289 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16290 | } |
16291 | ||
edc3d884 MK |
16292 | err_printf(m, "Cursor [%d]:\n", i); |
16293 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16294 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16295 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16296 | } |
63b66e5b CW |
16297 | |
16298 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16299 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16300 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16301 | err_printf(m, " Power: %s\n", |
87ad3212 | 16302 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16303 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16304 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16305 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16306 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16307 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16308 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16309 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16310 | } | |
c4a1d9e4 | 16311 | } |