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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
57822dc6 | 40 | #include "i915_gem_clflush.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
5a21b665 DV |
52 | static bool is_mmio_work(struct intel_flip_work *work) |
53 | { | |
54 | return work->mmio_work.func; | |
55 | } | |
56 | ||
465c120c | 57 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 58 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
59 | DRM_FORMAT_C8, |
60 | DRM_FORMAT_RGB565, | |
465c120c | 61 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 62 | DRM_FORMAT_XRGB8888, |
465c120c MR |
63 | }; |
64 | ||
65 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 66 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
70 | DRM_FORMAT_XBGR8888, | |
71 | DRM_FORMAT_XRGB2101010, | |
72 | DRM_FORMAT_XBGR2101010, | |
73 | }; | |
74 | ||
75 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
76 | DRM_FORMAT_C8, |
77 | DRM_FORMAT_RGB565, | |
78 | DRM_FORMAT_XRGB8888, | |
465c120c | 79 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 80 | DRM_FORMAT_ARGB8888, |
465c120c MR |
81 | DRM_FORMAT_ABGR8888, |
82 | DRM_FORMAT_XRGB2101010, | |
465c120c | 83 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
84 | DRM_FORMAT_YUYV, |
85 | DRM_FORMAT_YVYU, | |
86 | DRM_FORMAT_UYVY, | |
87 | DRM_FORMAT_VYUY, | |
465c120c MR |
88 | }; |
89 | ||
3d7d6510 MR |
90 | /* Cursor formats */ |
91 | static const uint32_t intel_cursor_formats[] = { | |
92 | DRM_FORMAT_ARGB8888, | |
93 | }; | |
94 | ||
f1f644dc | 95 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 96 | struct intel_crtc_state *pipe_config); |
18442d08 | 97 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 98 | struct intel_crtc_state *pipe_config); |
f1f644dc | 99 | |
24dbf51a CW |
100 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
101 | struct drm_i915_gem_object *obj, | |
102 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
1c74eeaf NM |
118 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
119 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
120 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
121 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
122 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 123 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 124 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 125 | |
d4906093 | 126 | struct intel_limit { |
4c5def93 ACO |
127 | struct { |
128 | int min, max; | |
129 | } dot, vco, n, m, m1, m2, p, p1; | |
130 | ||
131 | struct { | |
132 | int dot_limit; | |
133 | int p2_slow, p2_fast; | |
134 | } p2; | |
d4906093 | 135 | }; |
79e53945 | 136 | |
bfa7df01 | 137 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 138 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
139 | { |
140 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
141 | ||
142 | /* Obtain SKU information */ | |
143 | mutex_lock(&dev_priv->sb_lock); | |
144 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
145 | CCK_FUSE_HPLL_FREQ_MASK; | |
146 | mutex_unlock(&dev_priv->sb_lock); | |
147 | ||
148 | return vco_freq[hpll_freq] * 1000; | |
149 | } | |
150 | ||
c30fec65 VS |
151 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
152 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
153 | { |
154 | u32 val; | |
155 | int divider; | |
156 | ||
bfa7df01 VS |
157 | mutex_lock(&dev_priv->sb_lock); |
158 | val = vlv_cck_read(dev_priv, reg); | |
159 | mutex_unlock(&dev_priv->sb_lock); | |
160 | ||
161 | divider = val & CCK_FREQUENCY_VALUES; | |
162 | ||
163 | WARN((val & CCK_FREQUENCY_STATUS) != | |
164 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
165 | "%s change in progress\n", name); | |
166 | ||
c30fec65 VS |
167 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
168 | } | |
169 | ||
7ff89ca2 VS |
170 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
171 | const char *name, u32 reg) | |
c30fec65 VS |
172 | { |
173 | if (dev_priv->hpll_freq == 0) | |
49cd97a3 | 174 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 VS |
175 | |
176 | return vlv_get_cck_clock(dev_priv, name, reg, | |
177 | dev_priv->hpll_freq); | |
bfa7df01 VS |
178 | } |
179 | ||
bfa7df01 VS |
180 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
181 | { | |
666a4537 | 182 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
183 | return; |
184 | ||
185 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
186 | CCK_CZ_CLOCK_CONTROL); | |
187 | ||
188 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
189 | } | |
190 | ||
021357ac | 191 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
192 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
193 | const struct intel_crtc_state *pipe_config) | |
021357ac | 194 | { |
21a727b3 VS |
195 | if (HAS_DDI(dev_priv)) |
196 | return pipe_config->port_clock; /* SPLL */ | |
197 | else if (IS_GEN5(dev_priv)) | |
198 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 199 | else |
21a727b3 | 200 | return 270000; |
021357ac CW |
201 | } |
202 | ||
1b6f4958 | 203 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 204 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 205 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 206 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
207 | .m = { .min = 96, .max = 140 }, |
208 | .m1 = { .min = 18, .max = 26 }, | |
209 | .m2 = { .min = 6, .max = 16 }, | |
210 | .p = { .min = 4, .max = 128 }, | |
211 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
212 | .p2 = { .dot_limit = 165000, |
213 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
214 | }; |
215 | ||
1b6f4958 | 216 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 217 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 218 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 219 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
220 | .m = { .min = 96, .max = 140 }, |
221 | .m1 = { .min = 18, .max = 26 }, | |
222 | .m2 = { .min = 6, .max = 16 }, | |
223 | .p = { .min = 4, .max = 128 }, | |
224 | .p1 = { .min = 2, .max = 33 }, | |
225 | .p2 = { .dot_limit = 165000, | |
226 | .p2_slow = 4, .p2_fast = 4 }, | |
227 | }; | |
228 | ||
1b6f4958 | 229 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 230 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 231 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 232 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
233 | .m = { .min = 96, .max = 140 }, |
234 | .m1 = { .min = 18, .max = 26 }, | |
235 | .m2 = { .min = 6, .max = 16 }, | |
236 | .p = { .min = 4, .max = 128 }, | |
237 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
238 | .p2 = { .dot_limit = 165000, |
239 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 240 | }; |
273e27ca | 241 | |
1b6f4958 | 242 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
243 | .dot = { .min = 20000, .max = 400000 }, |
244 | .vco = { .min = 1400000, .max = 2800000 }, | |
245 | .n = { .min = 1, .max = 6 }, | |
246 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
247 | .m1 = { .min = 8, .max = 18 }, |
248 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
249 | .p = { .min = 5, .max = 80 }, |
250 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
251 | .p2 = { .dot_limit = 200000, |
252 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
253 | }; |
254 | ||
1b6f4958 | 255 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
256 | .dot = { .min = 20000, .max = 400000 }, |
257 | .vco = { .min = 1400000, .max = 2800000 }, | |
258 | .n = { .min = 1, .max = 6 }, | |
259 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
260 | .m1 = { .min = 8, .max = 18 }, |
261 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
262 | .p = { .min = 7, .max = 98 }, |
263 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
264 | .p2 = { .dot_limit = 112000, |
265 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
266 | }; |
267 | ||
273e27ca | 268 | |
1b6f4958 | 269 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
270 | .dot = { .min = 25000, .max = 270000 }, |
271 | .vco = { .min = 1750000, .max = 3500000}, | |
272 | .n = { .min = 1, .max = 4 }, | |
273 | .m = { .min = 104, .max = 138 }, | |
274 | .m1 = { .min = 17, .max = 23 }, | |
275 | .m2 = { .min = 5, .max = 11 }, | |
276 | .p = { .min = 10, .max = 30 }, | |
277 | .p1 = { .min = 1, .max = 3}, | |
278 | .p2 = { .dot_limit = 270000, | |
279 | .p2_slow = 10, | |
280 | .p2_fast = 10 | |
044c7c41 | 281 | }, |
e4b36699 KP |
282 | }; |
283 | ||
1b6f4958 | 284 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
285 | .dot = { .min = 22000, .max = 400000 }, |
286 | .vco = { .min = 1750000, .max = 3500000}, | |
287 | .n = { .min = 1, .max = 4 }, | |
288 | .m = { .min = 104, .max = 138 }, | |
289 | .m1 = { .min = 16, .max = 23 }, | |
290 | .m2 = { .min = 5, .max = 11 }, | |
291 | .p = { .min = 5, .max = 80 }, | |
292 | .p1 = { .min = 1, .max = 8}, | |
293 | .p2 = { .dot_limit = 165000, | |
294 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
295 | }; |
296 | ||
1b6f4958 | 297 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
298 | .dot = { .min = 20000, .max = 115000 }, |
299 | .vco = { .min = 1750000, .max = 3500000 }, | |
300 | .n = { .min = 1, .max = 3 }, | |
301 | .m = { .min = 104, .max = 138 }, | |
302 | .m1 = { .min = 17, .max = 23 }, | |
303 | .m2 = { .min = 5, .max = 11 }, | |
304 | .p = { .min = 28, .max = 112 }, | |
305 | .p1 = { .min = 2, .max = 8 }, | |
306 | .p2 = { .dot_limit = 0, | |
307 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 308 | }, |
e4b36699 KP |
309 | }; |
310 | ||
1b6f4958 | 311 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
312 | .dot = { .min = 80000, .max = 224000 }, |
313 | .vco = { .min = 1750000, .max = 3500000 }, | |
314 | .n = { .min = 1, .max = 3 }, | |
315 | .m = { .min = 104, .max = 138 }, | |
316 | .m1 = { .min = 17, .max = 23 }, | |
317 | .m2 = { .min = 5, .max = 11 }, | |
318 | .p = { .min = 14, .max = 42 }, | |
319 | .p1 = { .min = 2, .max = 6 }, | |
320 | .p2 = { .dot_limit = 0, | |
321 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 322 | }, |
e4b36699 KP |
323 | }; |
324 | ||
1b6f4958 | 325 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
326 | .dot = { .min = 20000, .max = 400000}, |
327 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 328 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
329 | .n = { .min = 3, .max = 6 }, |
330 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 331 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
332 | .m1 = { .min = 0, .max = 0 }, |
333 | .m2 = { .min = 0, .max = 254 }, | |
334 | .p = { .min = 5, .max = 80 }, | |
335 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
336 | .p2 = { .dot_limit = 200000, |
337 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
338 | }; |
339 | ||
1b6f4958 | 340 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
341 | .dot = { .min = 20000, .max = 400000 }, |
342 | .vco = { .min = 1700000, .max = 3500000 }, | |
343 | .n = { .min = 3, .max = 6 }, | |
344 | .m = { .min = 2, .max = 256 }, | |
345 | .m1 = { .min = 0, .max = 0 }, | |
346 | .m2 = { .min = 0, .max = 254 }, | |
347 | .p = { .min = 7, .max = 112 }, | |
348 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
349 | .p2 = { .dot_limit = 112000, |
350 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
351 | }; |
352 | ||
273e27ca EA |
353 | /* Ironlake / Sandybridge |
354 | * | |
355 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
356 | * the range value for them is (actual_value - 2). | |
357 | */ | |
1b6f4958 | 358 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
359 | .dot = { .min = 25000, .max = 350000 }, |
360 | .vco = { .min = 1760000, .max = 3510000 }, | |
361 | .n = { .min = 1, .max = 5 }, | |
362 | .m = { .min = 79, .max = 127 }, | |
363 | .m1 = { .min = 12, .max = 22 }, | |
364 | .m2 = { .min = 5, .max = 9 }, | |
365 | .p = { .min = 5, .max = 80 }, | |
366 | .p1 = { .min = 1, .max = 8 }, | |
367 | .p2 = { .dot_limit = 225000, | |
368 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
369 | }; |
370 | ||
1b6f4958 | 371 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
372 | .dot = { .min = 25000, .max = 350000 }, |
373 | .vco = { .min = 1760000, .max = 3510000 }, | |
374 | .n = { .min = 1, .max = 3 }, | |
375 | .m = { .min = 79, .max = 118 }, | |
376 | .m1 = { .min = 12, .max = 22 }, | |
377 | .m2 = { .min = 5, .max = 9 }, | |
378 | .p = { .min = 28, .max = 112 }, | |
379 | .p1 = { .min = 2, .max = 8 }, | |
380 | .p2 = { .dot_limit = 225000, | |
381 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
382 | }; |
383 | ||
1b6f4958 | 384 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
385 | .dot = { .min = 25000, .max = 350000 }, |
386 | .vco = { .min = 1760000, .max = 3510000 }, | |
387 | .n = { .min = 1, .max = 3 }, | |
388 | .m = { .min = 79, .max = 127 }, | |
389 | .m1 = { .min = 12, .max = 22 }, | |
390 | .m2 = { .min = 5, .max = 9 }, | |
391 | .p = { .min = 14, .max = 56 }, | |
392 | .p1 = { .min = 2, .max = 8 }, | |
393 | .p2 = { .dot_limit = 225000, | |
394 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
395 | }; |
396 | ||
273e27ca | 397 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 398 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
399 | .dot = { .min = 25000, .max = 350000 }, |
400 | .vco = { .min = 1760000, .max = 3510000 }, | |
401 | .n = { .min = 1, .max = 2 }, | |
402 | .m = { .min = 79, .max = 126 }, | |
403 | .m1 = { .min = 12, .max = 22 }, | |
404 | .m2 = { .min = 5, .max = 9 }, | |
405 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 406 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
407 | .p2 = { .dot_limit = 225000, |
408 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
409 | }; |
410 | ||
1b6f4958 | 411 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
412 | .dot = { .min = 25000, .max = 350000 }, |
413 | .vco = { .min = 1760000, .max = 3510000 }, | |
414 | .n = { .min = 1, .max = 3 }, | |
415 | .m = { .min = 79, .max = 126 }, | |
416 | .m1 = { .min = 12, .max = 22 }, | |
417 | .m2 = { .min = 5, .max = 9 }, | |
418 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 419 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
420 | .p2 = { .dot_limit = 225000, |
421 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
422 | }; |
423 | ||
1b6f4958 | 424 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
425 | /* |
426 | * These are the data rate limits (measured in fast clocks) | |
427 | * since those are the strictest limits we have. The fast | |
428 | * clock and actual rate limits are more relaxed, so checking | |
429 | * them would make no difference. | |
430 | */ | |
431 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 432 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 433 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
434 | .m1 = { .min = 2, .max = 3 }, |
435 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 436 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 437 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
438 | }; |
439 | ||
1b6f4958 | 440 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
441 | /* |
442 | * These are the data rate limits (measured in fast clocks) | |
443 | * since those are the strictest limits we have. The fast | |
444 | * clock and actual rate limits are more relaxed, so checking | |
445 | * them would make no difference. | |
446 | */ | |
447 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 448 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
449 | .n = { .min = 1, .max = 1 }, |
450 | .m1 = { .min = 2, .max = 2 }, | |
451 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
452 | .p1 = { .min = 2, .max = 4 }, | |
453 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
454 | }; | |
455 | ||
1b6f4958 | 456 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
457 | /* FIXME: find real dot limits */ |
458 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 459 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
460 | .n = { .min = 1, .max = 1 }, |
461 | .m1 = { .min = 2, .max = 2 }, | |
462 | /* FIXME: find real m2 limits */ | |
463 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
464 | .p1 = { .min = 2, .max = 4 }, | |
465 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
466 | }; | |
467 | ||
cdba954e ACO |
468 | static bool |
469 | needs_modeset(struct drm_crtc_state *state) | |
470 | { | |
fc596660 | 471 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
472 | } |
473 | ||
dccbea3b ID |
474 | /* |
475 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
476 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
477 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
478 | * The helpers' return value is the rate of the clock that is fed to the | |
479 | * display engine's pipe which can be the above fast dot clock rate or a | |
480 | * divided-down version of it. | |
481 | */ | |
f2b115e6 | 482 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 483 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 484 | { |
2177832f SL |
485 | clock->m = clock->m2 + 2; |
486 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 487 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 488 | return 0; |
fb03ac01 VS |
489 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
490 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
491 | |
492 | return clock->dot; | |
2177832f SL |
493 | } |
494 | ||
7429e9d4 DV |
495 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
496 | { | |
497 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
498 | } | |
499 | ||
9e2c8475 | 500 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 501 | { |
7429e9d4 | 502 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 503 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 504 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 505 | return 0; |
fb03ac01 VS |
506 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
507 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
508 | |
509 | return clock->dot; | |
79e53945 JB |
510 | } |
511 | ||
9e2c8475 | 512 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
513 | { |
514 | clock->m = clock->m1 * clock->m2; | |
515 | clock->p = clock->p1 * clock->p2; | |
516 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 517 | return 0; |
589eca67 ID |
518 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
519 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
520 | |
521 | return clock->dot / 5; | |
589eca67 ID |
522 | } |
523 | ||
9e2c8475 | 524 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
525 | { |
526 | clock->m = clock->m1 * clock->m2; | |
527 | clock->p = clock->p1 * clock->p2; | |
528 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 529 | return 0; |
ef9348c8 CML |
530 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
531 | clock->n << 22); | |
532 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
533 | |
534 | return clock->dot / 5; | |
ef9348c8 CML |
535 | } |
536 | ||
7c04d1d9 | 537 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
538 | /** |
539 | * Returns whether the given set of divisors are valid for a given refclk with | |
540 | * the given connectors. | |
541 | */ | |
542 | ||
e2d214ae | 543 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 544 | const struct intel_limit *limit, |
9e2c8475 | 545 | const struct dpll *clock) |
79e53945 | 546 | { |
f01b7962 VS |
547 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
548 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 549 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 550 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 551 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 552 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 553 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 554 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 555 | |
e2d214ae | 556 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 557 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
558 | if (clock->m1 <= clock->m2) |
559 | INTELPllInvalid("m1 <= m2\n"); | |
560 | ||
e2d214ae | 561 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 562 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
563 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
564 | INTELPllInvalid("p out of range\n"); | |
565 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
566 | INTELPllInvalid("m out of range\n"); | |
567 | } | |
568 | ||
79e53945 | 569 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 570 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
571 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
572 | * connector, etc., rather than just a single range. | |
573 | */ | |
574 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 575 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
576 | |
577 | return true; | |
578 | } | |
579 | ||
3b1429d9 | 580 | static int |
1b6f4958 | 581 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
582 | const struct intel_crtc_state *crtc_state, |
583 | int target) | |
79e53945 | 584 | { |
3b1429d9 | 585 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 586 | |
2d84d2b3 | 587 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 588 | /* |
a210b028 DV |
589 | * For LVDS just rely on its current settings for dual-channel. |
590 | * We haven't figured out how to reliably set up different | |
591 | * single/dual channel state, if we even can. | |
79e53945 | 592 | */ |
1974cad0 | 593 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 594 | return limit->p2.p2_fast; |
79e53945 | 595 | else |
3b1429d9 | 596 | return limit->p2.p2_slow; |
79e53945 JB |
597 | } else { |
598 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 599 | return limit->p2.p2_slow; |
79e53945 | 600 | else |
3b1429d9 | 601 | return limit->p2.p2_fast; |
79e53945 | 602 | } |
3b1429d9 VS |
603 | } |
604 | ||
70e8aa21 ACO |
605 | /* |
606 | * Returns a set of divisors for the desired target clock with the given | |
607 | * refclk, or FALSE. The returned values represent the clock equation: | |
608 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
609 | * | |
610 | * Target and reference clocks are specified in kHz. | |
611 | * | |
612 | * If match_clock is provided, then best_clock P divider must match the P | |
613 | * divider from @match_clock used for LVDS downclocking. | |
614 | */ | |
3b1429d9 | 615 | static bool |
1b6f4958 | 616 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 617 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
618 | int target, int refclk, struct dpll *match_clock, |
619 | struct dpll *best_clock) | |
3b1429d9 VS |
620 | { |
621 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 622 | struct dpll clock; |
3b1429d9 | 623 | int err = target; |
79e53945 | 624 | |
0206e353 | 625 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 626 | |
3b1429d9 VS |
627 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
628 | ||
42158660 ZY |
629 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
630 | clock.m1++) { | |
631 | for (clock.m2 = limit->m2.min; | |
632 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 633 | if (clock.m2 >= clock.m1) |
42158660 ZY |
634 | break; |
635 | for (clock.n = limit->n.min; | |
636 | clock.n <= limit->n.max; clock.n++) { | |
637 | for (clock.p1 = limit->p1.min; | |
638 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
639 | int this_err; |
640 | ||
dccbea3b | 641 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
642 | if (!intel_PLL_is_valid(to_i915(dev), |
643 | limit, | |
ac58c3f0 DV |
644 | &clock)) |
645 | continue; | |
646 | if (match_clock && | |
647 | clock.p != match_clock->p) | |
648 | continue; | |
649 | ||
650 | this_err = abs(clock.dot - target); | |
651 | if (this_err < err) { | |
652 | *best_clock = clock; | |
653 | err = this_err; | |
654 | } | |
655 | } | |
656 | } | |
657 | } | |
658 | } | |
659 | ||
660 | return (err != target); | |
661 | } | |
662 | ||
70e8aa21 ACO |
663 | /* |
664 | * Returns a set of divisors for the desired target clock with the given | |
665 | * refclk, or FALSE. The returned values represent the clock equation: | |
666 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
667 | * | |
668 | * Target and reference clocks are specified in kHz. | |
669 | * | |
670 | * If match_clock is provided, then best_clock P divider must match the P | |
671 | * divider from @match_clock used for LVDS downclocking. | |
672 | */ | |
ac58c3f0 | 673 | static bool |
1b6f4958 | 674 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 675 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
676 | int target, int refclk, struct dpll *match_clock, |
677 | struct dpll *best_clock) | |
79e53945 | 678 | { |
3b1429d9 | 679 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 680 | struct dpll clock; |
79e53945 JB |
681 | int err = target; |
682 | ||
0206e353 | 683 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 684 | |
3b1429d9 VS |
685 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
686 | ||
42158660 ZY |
687 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
688 | clock.m1++) { | |
689 | for (clock.m2 = limit->m2.min; | |
690 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
691 | for (clock.n = limit->n.min; |
692 | clock.n <= limit->n.max; clock.n++) { | |
693 | for (clock.p1 = limit->p1.min; | |
694 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
695 | int this_err; |
696 | ||
dccbea3b | 697 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
698 | if (!intel_PLL_is_valid(to_i915(dev), |
699 | limit, | |
1b894b59 | 700 | &clock)) |
79e53945 | 701 | continue; |
cec2f356 SP |
702 | if (match_clock && |
703 | clock.p != match_clock->p) | |
704 | continue; | |
79e53945 JB |
705 | |
706 | this_err = abs(clock.dot - target); | |
707 | if (this_err < err) { | |
708 | *best_clock = clock; | |
709 | err = this_err; | |
710 | } | |
711 | } | |
712 | } | |
713 | } | |
714 | } | |
715 | ||
716 | return (err != target); | |
717 | } | |
718 | ||
997c030c ACO |
719 | /* |
720 | * Returns a set of divisors for the desired target clock with the given | |
721 | * refclk, or FALSE. The returned values represent the clock equation: | |
722 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
723 | * |
724 | * Target and reference clocks are specified in kHz. | |
725 | * | |
726 | * If match_clock is provided, then best_clock P divider must match the P | |
727 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 728 | */ |
d4906093 | 729 | static bool |
1b6f4958 | 730 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 731 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
732 | int target, int refclk, struct dpll *match_clock, |
733 | struct dpll *best_clock) | |
d4906093 | 734 | { |
3b1429d9 | 735 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 736 | struct dpll clock; |
d4906093 | 737 | int max_n; |
3b1429d9 | 738 | bool found = false; |
6ba770dc AJ |
739 | /* approximately equals target * 0.00585 */ |
740 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
741 | |
742 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
743 | |
744 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
745 | ||
d4906093 | 746 | max_n = limit->n.max; |
f77f13e2 | 747 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 748 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 749 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
750 | for (clock.m1 = limit->m1.max; |
751 | clock.m1 >= limit->m1.min; clock.m1--) { | |
752 | for (clock.m2 = limit->m2.max; | |
753 | clock.m2 >= limit->m2.min; clock.m2--) { | |
754 | for (clock.p1 = limit->p1.max; | |
755 | clock.p1 >= limit->p1.min; clock.p1--) { | |
756 | int this_err; | |
757 | ||
dccbea3b | 758 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
759 | if (!intel_PLL_is_valid(to_i915(dev), |
760 | limit, | |
1b894b59 | 761 | &clock)) |
d4906093 | 762 | continue; |
1b894b59 CW |
763 | |
764 | this_err = abs(clock.dot - target); | |
d4906093 ML |
765 | if (this_err < err_most) { |
766 | *best_clock = clock; | |
767 | err_most = this_err; | |
768 | max_n = clock.n; | |
769 | found = true; | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
774 | } | |
2c07245f ZW |
775 | return found; |
776 | } | |
777 | ||
d5dd62bd ID |
778 | /* |
779 | * Check if the calculated PLL configuration is more optimal compared to the | |
780 | * best configuration and error found so far. Return the calculated error. | |
781 | */ | |
782 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
783 | const struct dpll *calculated_clock, |
784 | const struct dpll *best_clock, | |
d5dd62bd ID |
785 | unsigned int best_error_ppm, |
786 | unsigned int *error_ppm) | |
787 | { | |
9ca3ba01 ID |
788 | /* |
789 | * For CHV ignore the error and consider only the P value. | |
790 | * Prefer a bigger P value based on HW requirements. | |
791 | */ | |
920a14b2 | 792 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
793 | *error_ppm = 0; |
794 | ||
795 | return calculated_clock->p > best_clock->p; | |
796 | } | |
797 | ||
24be4e46 ID |
798 | if (WARN_ON_ONCE(!target_freq)) |
799 | return false; | |
800 | ||
d5dd62bd ID |
801 | *error_ppm = div_u64(1000000ULL * |
802 | abs(target_freq - calculated_clock->dot), | |
803 | target_freq); | |
804 | /* | |
805 | * Prefer a better P value over a better (smaller) error if the error | |
806 | * is small. Ensure this preference for future configurations too by | |
807 | * setting the error to 0. | |
808 | */ | |
809 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
810 | *error_ppm = 0; | |
811 | ||
812 | return true; | |
813 | } | |
814 | ||
815 | return *error_ppm + 10 < best_error_ppm; | |
816 | } | |
817 | ||
65b3d6a9 ACO |
818 | /* |
819 | * Returns a set of divisors for the desired target clock with the given | |
820 | * refclk, or FALSE. The returned values represent the clock equation: | |
821 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
822 | */ | |
a0c4da24 | 823 | static bool |
1b6f4958 | 824 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 825 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
826 | int target, int refclk, struct dpll *match_clock, |
827 | struct dpll *best_clock) | |
a0c4da24 | 828 | { |
a93e255f | 829 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 830 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 831 | struct dpll clock; |
69e4f900 | 832 | unsigned int bestppm = 1000000; |
27e639bf VS |
833 | /* min update 19.2 MHz */ |
834 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 835 | bool found = false; |
a0c4da24 | 836 | |
6b4bf1c4 VS |
837 | target *= 5; /* fast clock */ |
838 | ||
839 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
840 | |
841 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 842 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 843 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 844 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 845 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 846 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 847 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 848 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 849 | unsigned int ppm; |
69e4f900 | 850 | |
6b4bf1c4 VS |
851 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
852 | refclk * clock.m1); | |
853 | ||
dccbea3b | 854 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 855 | |
e2d214ae TU |
856 | if (!intel_PLL_is_valid(to_i915(dev), |
857 | limit, | |
f01b7962 | 858 | &clock)) |
43b0ac53 VS |
859 | continue; |
860 | ||
d5dd62bd ID |
861 | if (!vlv_PLL_is_optimal(dev, target, |
862 | &clock, | |
863 | best_clock, | |
864 | bestppm, &ppm)) | |
865 | continue; | |
6b4bf1c4 | 866 | |
d5dd62bd ID |
867 | *best_clock = clock; |
868 | bestppm = ppm; | |
869 | found = true; | |
a0c4da24 JB |
870 | } |
871 | } | |
872 | } | |
873 | } | |
a0c4da24 | 874 | |
49e497ef | 875 | return found; |
a0c4da24 | 876 | } |
a4fc5ed6 | 877 | |
65b3d6a9 ACO |
878 | /* |
879 | * Returns a set of divisors for the desired target clock with the given | |
880 | * refclk, or FALSE. The returned values represent the clock equation: | |
881 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
882 | */ | |
ef9348c8 | 883 | static bool |
1b6f4958 | 884 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 885 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
886 | int target, int refclk, struct dpll *match_clock, |
887 | struct dpll *best_clock) | |
ef9348c8 | 888 | { |
a93e255f | 889 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 890 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 891 | unsigned int best_error_ppm; |
9e2c8475 | 892 | struct dpll clock; |
ef9348c8 CML |
893 | uint64_t m2; |
894 | int found = false; | |
895 | ||
896 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 897 | best_error_ppm = 1000000; |
ef9348c8 CML |
898 | |
899 | /* | |
900 | * Based on hardware doc, the n always set to 1, and m1 always | |
901 | * set to 2. If requires to support 200Mhz refclk, we need to | |
902 | * revisit this because n may not 1 anymore. | |
903 | */ | |
904 | clock.n = 1, clock.m1 = 2; | |
905 | target *= 5; /* fast clock */ | |
906 | ||
907 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
908 | for (clock.p2 = limit->p2.p2_fast; | |
909 | clock.p2 >= limit->p2.p2_slow; | |
910 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 911 | unsigned int error_ppm; |
ef9348c8 CML |
912 | |
913 | clock.p = clock.p1 * clock.p2; | |
914 | ||
915 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
916 | clock.n) << 22, refclk * clock.m1); | |
917 | ||
918 | if (m2 > INT_MAX/clock.m1) | |
919 | continue; | |
920 | ||
921 | clock.m2 = m2; | |
922 | ||
dccbea3b | 923 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 924 | |
e2d214ae | 925 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
926 | continue; |
927 | ||
9ca3ba01 ID |
928 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
929 | best_error_ppm, &error_ppm)) | |
930 | continue; | |
931 | ||
932 | *best_clock = clock; | |
933 | best_error_ppm = error_ppm; | |
934 | found = true; | |
ef9348c8 CML |
935 | } |
936 | } | |
937 | ||
938 | return found; | |
939 | } | |
940 | ||
5ab7b0b7 | 941 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 942 | struct dpll *best_clock) |
5ab7b0b7 | 943 | { |
65b3d6a9 | 944 | int refclk = 100000; |
1b6f4958 | 945 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 946 | |
65b3d6a9 | 947 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
948 | target_clock, refclk, NULL, best_clock); |
949 | } | |
950 | ||
525b9311 | 951 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 952 | { |
20ddf665 VS |
953 | /* Be paranoid as we can arrive here with only partial |
954 | * state retrieved from the hardware during setup. | |
955 | * | |
241bfc38 | 956 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
957 | * as Haswell has gained clock readout/fastboot support. |
958 | * | |
66e514c1 | 959 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 960 | * properly reconstruct framebuffers. |
c3d1f436 MR |
961 | * |
962 | * FIXME: The intel_crtc->active here should be switched to | |
963 | * crtc->state->active once we have proper CRTC states wired up | |
964 | * for atomic. | |
20ddf665 | 965 | */ |
525b9311 VS |
966 | return crtc->active && crtc->base.primary->state->fb && |
967 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
968 | } |
969 | ||
a5c961d1 PZ |
970 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
971 | enum pipe pipe) | |
972 | { | |
98187836 | 973 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 974 | |
e2af48c6 | 975 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
976 | } |
977 | ||
6315b5d3 | 978 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 979 | { |
f0f59a00 | 980 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
981 | u32 line1, line2; |
982 | u32 line_mask; | |
983 | ||
5db94019 | 984 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
985 | line_mask = DSL_LINEMASK_GEN2; |
986 | else | |
987 | line_mask = DSL_LINEMASK_GEN3; | |
988 | ||
989 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 990 | msleep(5); |
fbf49ea2 VS |
991 | line2 = I915_READ(reg) & line_mask; |
992 | ||
993 | return line1 == line2; | |
994 | } | |
995 | ||
ab7ad7f6 KP |
996 | /* |
997 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 998 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
999 | * |
1000 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1001 | * spinning on the vblank interrupt status bit, since we won't actually | |
1002 | * see an interrupt when the pipe is disabled. | |
1003 | * | |
ab7ad7f6 KP |
1004 | * On Gen4 and above: |
1005 | * wait for the pipe register state bit to turn off | |
1006 | * | |
1007 | * Otherwise: | |
1008 | * wait for the display line value to settle (it usually | |
1009 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1010 | * |
9d0498a2 | 1011 | */ |
575f7ab7 | 1012 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1013 | { |
6315b5d3 | 1014 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1015 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1016 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1017 | |
6315b5d3 | 1018 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1019 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1020 | |
1021 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1022 | if (intel_wait_for_register(dev_priv, |
1023 | reg, I965_PIPECONF_ACTIVE, 0, | |
1024 | 100)) | |
284637d9 | 1025 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1026 | } else { |
ab7ad7f6 | 1027 | /* Wait for the display line to settle */ |
6315b5d3 | 1028 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1029 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1030 | } |
79e53945 JB |
1031 | } |
1032 | ||
b24e7179 | 1033 | /* Only for pre-ILK configs */ |
55607e8a DV |
1034 | void assert_pll(struct drm_i915_private *dev_priv, |
1035 | enum pipe pipe, bool state) | |
b24e7179 | 1036 | { |
b24e7179 JB |
1037 | u32 val; |
1038 | bool cur_state; | |
1039 | ||
649636ef | 1040 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1041 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1042 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1043 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1044 | onoff(state), onoff(cur_state)); |
b24e7179 | 1045 | } |
b24e7179 | 1046 | |
23538ef1 | 1047 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1048 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1049 | { |
1050 | u32 val; | |
1051 | bool cur_state; | |
1052 | ||
a580516d | 1053 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1054 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1055 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1056 | |
1057 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1058 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1059 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1060 | onoff(state), onoff(cur_state)); |
23538ef1 | 1061 | } |
23538ef1 | 1062 | |
040484af JB |
1063 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1064 | enum pipe pipe, bool state) | |
1065 | { | |
040484af | 1066 | bool cur_state; |
ad80a810 PZ |
1067 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1068 | pipe); | |
040484af | 1069 | |
2d1fe073 | 1070 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1071 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1072 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1073 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1074 | } else { |
649636ef | 1075 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1076 | cur_state = !!(val & FDI_TX_ENABLE); |
1077 | } | |
e2c719b7 | 1078 | I915_STATE_WARN(cur_state != state, |
040484af | 1079 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1080 | onoff(state), onoff(cur_state)); |
040484af JB |
1081 | } |
1082 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1083 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1084 | ||
1085 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1086 | enum pipe pipe, bool state) | |
1087 | { | |
040484af JB |
1088 | u32 val; |
1089 | bool cur_state; | |
1090 | ||
649636ef | 1091 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1092 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1093 | I915_STATE_WARN(cur_state != state, |
040484af | 1094 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1095 | onoff(state), onoff(cur_state)); |
040484af JB |
1096 | } |
1097 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1098 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1099 | ||
1100 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1101 | enum pipe pipe) | |
1102 | { | |
040484af JB |
1103 | u32 val; |
1104 | ||
1105 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1106 | if (IS_GEN5(dev_priv)) |
040484af JB |
1107 | return; |
1108 | ||
bf507ef7 | 1109 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1110 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1111 | return; |
1112 | ||
649636ef | 1113 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1114 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1115 | } |
1116 | ||
55607e8a DV |
1117 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1118 | enum pipe pipe, bool state) | |
040484af | 1119 | { |
040484af | 1120 | u32 val; |
55607e8a | 1121 | bool cur_state; |
040484af | 1122 | |
649636ef | 1123 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1124 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1125 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1126 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1127 | onoff(state), onoff(cur_state)); |
040484af JB |
1128 | } |
1129 | ||
4f8036a2 | 1130 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1131 | { |
f0f59a00 | 1132 | i915_reg_t pp_reg; |
ea0760cf JB |
1133 | u32 val; |
1134 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1135 | bool locked = true; |
ea0760cf | 1136 | |
4f8036a2 | 1137 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1138 | return; |
1139 | ||
4f8036a2 | 1140 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1141 | u32 port_sel; |
1142 | ||
44cb734c ID |
1143 | pp_reg = PP_CONTROL(0); |
1144 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1145 | |
1146 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1147 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1148 | panel_pipe = PIPE_B; | |
1149 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1150 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1151 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1152 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1153 | panel_pipe = pipe; |
ea0760cf | 1154 | } else { |
44cb734c | 1155 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1156 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1157 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1158 | } |
1159 | ||
1160 | val = I915_READ(pp_reg); | |
1161 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1162 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1163 | locked = false; |
1164 | ||
e2c719b7 | 1165 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1166 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1167 | pipe_name(pipe)); |
ea0760cf JB |
1168 | } |
1169 | ||
93ce0ba6 JN |
1170 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1171 | enum pipe pipe, bool state) | |
1172 | { | |
93ce0ba6 JN |
1173 | bool cur_state; |
1174 | ||
2a307c2e | 1175 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1176 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1177 | else |
5efb3e28 | 1178 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1179 | |
e2c719b7 | 1180 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1181 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1182 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1183 | } |
1184 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1185 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1186 | ||
b840d907 JB |
1187 | void assert_pipe(struct drm_i915_private *dev_priv, |
1188 | enum pipe pipe, bool state) | |
b24e7179 | 1189 | { |
63d7bbe9 | 1190 | bool cur_state; |
702e7a56 PZ |
1191 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1192 | pipe); | |
4feed0eb | 1193 | enum intel_display_power_domain power_domain; |
b24e7179 | 1194 | |
b6b5d049 VS |
1195 | /* if we need the pipe quirk it must be always on */ |
1196 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1197 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1198 | state = true; |
1199 | ||
4feed0eb ID |
1200 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1201 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1202 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1203 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1204 | |
1205 | intel_display_power_put(dev_priv, power_domain); | |
1206 | } else { | |
1207 | cur_state = false; | |
69310161 PZ |
1208 | } |
1209 | ||
e2c719b7 | 1210 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1211 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1212 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1213 | } |
1214 | ||
931872fc CW |
1215 | static void assert_plane(struct drm_i915_private *dev_priv, |
1216 | enum plane plane, bool state) | |
b24e7179 | 1217 | { |
b24e7179 | 1218 | u32 val; |
931872fc | 1219 | bool cur_state; |
b24e7179 | 1220 | |
649636ef | 1221 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1222 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1223 | I915_STATE_WARN(cur_state != state, |
931872fc | 1224 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1225 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1226 | } |
1227 | ||
931872fc CW |
1228 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1229 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1230 | ||
b24e7179 JB |
1231 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1232 | enum pipe pipe) | |
1233 | { | |
649636ef | 1234 | int i; |
b24e7179 | 1235 | |
653e1026 | 1236 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1237 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1238 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1239 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1240 | "plane %c assertion failure, should be disabled but not\n", |
1241 | plane_name(pipe)); | |
19ec1358 | 1242 | return; |
28c05794 | 1243 | } |
19ec1358 | 1244 | |
b24e7179 | 1245 | /* Need to check both planes against the pipe */ |
055e393f | 1246 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1247 | u32 val = I915_READ(DSPCNTR(i)); |
1248 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1249 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1250 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1251 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1252 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1253 | } |
1254 | } | |
1255 | ||
19332d7a JB |
1256 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1257 | enum pipe pipe) | |
1258 | { | |
649636ef | 1259 | int sprite; |
19332d7a | 1260 | |
6315b5d3 | 1261 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1262 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1263 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1264 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1265 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1266 | sprite, pipe_name(pipe)); | |
1267 | } | |
920a14b2 | 1268 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1269 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1270 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1271 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1272 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1273 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1274 | } |
6315b5d3 | 1275 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1276 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1277 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1278 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1279 | plane_name(pipe), pipe_name(pipe)); |
ab33081a | 1280 | } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
649636ef | 1281 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1282 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1283 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1284 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1285 | } |
1286 | } | |
1287 | ||
08c71e5e VS |
1288 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1289 | { | |
e2c719b7 | 1290 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1291 | drm_crtc_vblank_put(crtc); |
1292 | } | |
1293 | ||
7abd4b35 ACO |
1294 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe) | |
92f2584a | 1296 | { |
92f2584a JB |
1297 | u32 val; |
1298 | bool enabled; | |
1299 | ||
649636ef | 1300 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1301 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1302 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1303 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1304 | pipe_name(pipe)); | |
92f2584a JB |
1305 | } |
1306 | ||
4e634389 KP |
1307 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1308 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1309 | { |
1310 | if ((val & DP_PORT_EN) == 0) | |
1311 | return false; | |
1312 | ||
2d1fe073 | 1313 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1314 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1315 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1316 | return false; | |
2d1fe073 | 1317 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1318 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1319 | return false; | |
f0575e92 KP |
1320 | } else { |
1321 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1322 | return false; | |
1323 | } | |
1324 | return true; | |
1325 | } | |
1326 | ||
1519b995 KP |
1327 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1328 | enum pipe pipe, u32 val) | |
1329 | { | |
dc0fa718 | 1330 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1331 | return false; |
1332 | ||
2d1fe073 | 1333 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1334 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1335 | return false; |
2d1fe073 | 1336 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1337 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1338 | return false; | |
1519b995 | 1339 | } else { |
dc0fa718 | 1340 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1341 | return false; |
1342 | } | |
1343 | return true; | |
1344 | } | |
1345 | ||
1346 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1347 | enum pipe pipe, u32 val) | |
1348 | { | |
1349 | if ((val & LVDS_PORT_EN) == 0) | |
1350 | return false; | |
1351 | ||
2d1fe073 | 1352 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1353 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1354 | return false; | |
1355 | } else { | |
1356 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1357 | return false; | |
1358 | } | |
1359 | return true; | |
1360 | } | |
1361 | ||
1362 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1363 | enum pipe pipe, u32 val) | |
1364 | { | |
1365 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1366 | return false; | |
2d1fe073 | 1367 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1368 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1369 | return false; | |
1370 | } else { | |
1371 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1372 | return false; | |
1373 | } | |
1374 | return true; | |
1375 | } | |
1376 | ||
291906f1 | 1377 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1378 | enum pipe pipe, i915_reg_t reg, |
1379 | u32 port_sel) | |
291906f1 | 1380 | { |
47a05eca | 1381 | u32 val = I915_READ(reg); |
e2c719b7 | 1382 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1383 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1384 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1385 | |
2d1fe073 | 1386 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1387 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1388 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1389 | } |
1390 | ||
1391 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1392 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1393 | { |
47a05eca | 1394 | u32 val = I915_READ(reg); |
e2c719b7 | 1395 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1396 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1397 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1398 | |
2d1fe073 | 1399 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1400 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1401 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1402 | } |
1403 | ||
1404 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1405 | enum pipe pipe) | |
1406 | { | |
291906f1 | 1407 | u32 val; |
291906f1 | 1408 | |
f0575e92 KP |
1409 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1410 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1411 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1412 | |
649636ef | 1413 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1414 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1415 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1416 | pipe_name(pipe)); |
291906f1 | 1417 | |
649636ef | 1418 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1419 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1420 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1421 | pipe_name(pipe)); |
291906f1 | 1422 | |
e2debe91 PZ |
1423 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1424 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1425 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1426 | } |
1427 | ||
cd2d34d9 VS |
1428 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1429 | const struct intel_crtc_state *pipe_config) | |
1430 | { | |
1431 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1432 | enum pipe pipe = crtc->pipe; | |
1433 | ||
1434 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1435 | POSTING_READ(DPLL(pipe)); | |
1436 | udelay(150); | |
1437 | ||
2c30b43b CW |
1438 | if (intel_wait_for_register(dev_priv, |
1439 | DPLL(pipe), | |
1440 | DPLL_LOCK_VLV, | |
1441 | DPLL_LOCK_VLV, | |
1442 | 1)) | |
cd2d34d9 VS |
1443 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1444 | } | |
1445 | ||
d288f65f | 1446 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1447 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1448 | { |
cd2d34d9 | 1449 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1450 | enum pipe pipe = crtc->pipe; |
87442f73 | 1451 | |
8bd3f301 | 1452 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1453 | |
87442f73 | 1454 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1455 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1456 | |
cd2d34d9 VS |
1457 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1458 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1459 | |
8bd3f301 VS |
1460 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1461 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1462 | } |
1463 | ||
cd2d34d9 VS |
1464 | |
1465 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1466 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1467 | { |
cd2d34d9 | 1468 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1469 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1470 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1471 | u32 tmp; |
1472 | ||
a580516d | 1473 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1474 | |
1475 | /* Enable back the 10bit clock to display controller */ | |
1476 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1477 | tmp |= DPIO_DCLKP_EN; | |
1478 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1479 | ||
54433e91 VS |
1480 | mutex_unlock(&dev_priv->sb_lock); |
1481 | ||
9d556c99 CML |
1482 | /* |
1483 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1484 | */ | |
1485 | udelay(1); | |
1486 | ||
1487 | /* Enable PLL */ | |
d288f65f | 1488 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1489 | |
1490 | /* Check PLL is locked */ | |
6b18826a CW |
1491 | if (intel_wait_for_register(dev_priv, |
1492 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1493 | 1)) | |
9d556c99 | 1494 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1495 | } |
1496 | ||
1497 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1498 | const struct intel_crtc_state *pipe_config) | |
1499 | { | |
1500 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1501 | enum pipe pipe = crtc->pipe; | |
1502 | ||
1503 | assert_pipe_disabled(dev_priv, pipe); | |
1504 | ||
1505 | /* PLL is protected by panel, make sure we can write it */ | |
1506 | assert_panel_unlocked(dev_priv, pipe); | |
1507 | ||
1508 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1509 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1510 | |
c231775c VS |
1511 | if (pipe != PIPE_A) { |
1512 | /* | |
1513 | * WaPixelRepeatModeFixForC0:chv | |
1514 | * | |
1515 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1516 | * the value from DPLLBMD to either pipe B or C. | |
1517 | */ | |
1518 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1519 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1520 | I915_WRITE(CBR4_VLV, 0); | |
1521 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1522 | ||
1523 | /* | |
1524 | * DPLLB VGA mode also seems to cause problems. | |
1525 | * We should always have it disabled. | |
1526 | */ | |
1527 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1528 | } else { | |
1529 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1530 | POSTING_READ(DPLL_MD(pipe)); | |
1531 | } | |
9d556c99 CML |
1532 | } |
1533 | ||
6315b5d3 | 1534 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1535 | { |
1536 | struct intel_crtc *crtc; | |
1537 | int count = 0; | |
1538 | ||
6315b5d3 | 1539 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1540 | count += crtc->base.state->active && |
2d84d2b3 VS |
1541 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1542 | } | |
1c4e0274 VS |
1543 | |
1544 | return count; | |
1545 | } | |
1546 | ||
66e3d5c0 | 1547 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1548 | { |
6315b5d3 | 1549 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1550 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1551 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1552 | |
66e3d5c0 | 1553 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1554 | |
63d7bbe9 | 1555 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1556 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1557 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1558 | |
1c4e0274 | 1559 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1560 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1561 | /* |
1562 | * It appears to be important that we don't enable this | |
1563 | * for the current pipe before otherwise configuring the | |
1564 | * PLL. No idea how this should be handled if multiple | |
1565 | * DVO outputs are enabled simultaneosly. | |
1566 | */ | |
1567 | dpll |= DPLL_DVO_2X_MODE; | |
1568 | I915_WRITE(DPLL(!crtc->pipe), | |
1569 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1570 | } | |
66e3d5c0 | 1571 | |
c2b63374 VS |
1572 | /* |
1573 | * Apparently we need to have VGA mode enabled prior to changing | |
1574 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1575 | * dividers, even though the register value does change. | |
1576 | */ | |
1577 | I915_WRITE(reg, 0); | |
1578 | ||
8e7a65aa VS |
1579 | I915_WRITE(reg, dpll); |
1580 | ||
66e3d5c0 DV |
1581 | /* Wait for the clocks to stabilize. */ |
1582 | POSTING_READ(reg); | |
1583 | udelay(150); | |
1584 | ||
6315b5d3 | 1585 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1586 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1587 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1588 | } else { |
1589 | /* The pixel multiplier can only be updated once the | |
1590 | * DPLL is enabled and the clocks are stable. | |
1591 | * | |
1592 | * So write it again. | |
1593 | */ | |
1594 | I915_WRITE(reg, dpll); | |
1595 | } | |
63d7bbe9 JB |
1596 | |
1597 | /* We do this three times for luck */ | |
66e3d5c0 | 1598 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1599 | POSTING_READ(reg); |
1600 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1601 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1602 | POSTING_READ(reg); |
1603 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1604 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1605 | POSTING_READ(reg); |
1606 | udelay(150); /* wait for warmup */ | |
1607 | } | |
1608 | ||
1609 | /** | |
50b44a44 | 1610 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1611 | * @dev_priv: i915 private structure |
1612 | * @pipe: pipe PLL to disable | |
1613 | * | |
1614 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1615 | * | |
1616 | * Note! This is for pre-ILK only. | |
1617 | */ | |
1c4e0274 | 1618 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1619 | { |
6315b5d3 | 1620 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1621 | enum pipe pipe = crtc->pipe; |
1622 | ||
1623 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1624 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1625 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1626 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1627 | I915_WRITE(DPLL(PIPE_B), |
1628 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1629 | I915_WRITE(DPLL(PIPE_A), | |
1630 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1631 | } | |
1632 | ||
b6b5d049 VS |
1633 | /* Don't disable pipe or pipe PLLs if needed */ |
1634 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1635 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1636 | return; |
1637 | ||
1638 | /* Make sure the pipe isn't still relying on us */ | |
1639 | assert_pipe_disabled(dev_priv, pipe); | |
1640 | ||
b8afb911 | 1641 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1642 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1643 | } |
1644 | ||
f6071166 JB |
1645 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1646 | { | |
b8afb911 | 1647 | u32 val; |
f6071166 JB |
1648 | |
1649 | /* Make sure the pipe isn't still relying on us */ | |
1650 | assert_pipe_disabled(dev_priv, pipe); | |
1651 | ||
03ed5cbf VS |
1652 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1653 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1654 | if (pipe != PIPE_A) | |
1655 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1656 | ||
f6071166 JB |
1657 | I915_WRITE(DPLL(pipe), val); |
1658 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1659 | } |
1660 | ||
1661 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1662 | { | |
d752048d | 1663 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1664 | u32 val; |
1665 | ||
a11b0703 VS |
1666 | /* Make sure the pipe isn't still relying on us */ |
1667 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1668 | |
60bfe44f VS |
1669 | val = DPLL_SSC_REF_CLK_CHV | |
1670 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1671 | if (pipe != PIPE_A) |
1672 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1673 | |
a11b0703 VS |
1674 | I915_WRITE(DPLL(pipe), val); |
1675 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1676 | |
a580516d | 1677 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1678 | |
1679 | /* Disable 10bit clock to display controller */ | |
1680 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1681 | val &= ~DPIO_DCLKP_EN; | |
1682 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1683 | ||
a580516d | 1684 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1685 | } |
1686 | ||
e4607fcf | 1687 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1688 | struct intel_digital_port *dport, |
1689 | unsigned int expected_mask) | |
89b667f8 JB |
1690 | { |
1691 | u32 port_mask; | |
f0f59a00 | 1692 | i915_reg_t dpll_reg; |
89b667f8 | 1693 | |
e4607fcf CML |
1694 | switch (dport->port) { |
1695 | case PORT_B: | |
89b667f8 | 1696 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1697 | dpll_reg = DPLL(0); |
e4607fcf CML |
1698 | break; |
1699 | case PORT_C: | |
89b667f8 | 1700 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1701 | dpll_reg = DPLL(0); |
9b6de0a1 | 1702 | expected_mask <<= 4; |
00fc31b7 CML |
1703 | break; |
1704 | case PORT_D: | |
1705 | port_mask = DPLL_PORTD_READY_MASK; | |
1706 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1707 | break; |
1708 | default: | |
1709 | BUG(); | |
1710 | } | |
89b667f8 | 1711 | |
370004d3 CW |
1712 | if (intel_wait_for_register(dev_priv, |
1713 | dpll_reg, port_mask, expected_mask, | |
1714 | 1000)) | |
9b6de0a1 VS |
1715 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1716 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1717 | } |
1718 | ||
b8a4f404 PZ |
1719 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1720 | enum pipe pipe) | |
040484af | 1721 | { |
98187836 VS |
1722 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1723 | pipe); | |
f0f59a00 VS |
1724 | i915_reg_t reg; |
1725 | uint32_t val, pipeconf_val; | |
040484af | 1726 | |
040484af | 1727 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1728 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1729 | |
1730 | /* FDI must be feeding us bits for PCH ports */ | |
1731 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1732 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1733 | ||
6e266956 | 1734 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1735 | /* Workaround: Set the timing override bit before enabling the |
1736 | * pch transcoder. */ | |
1737 | reg = TRANS_CHICKEN2(pipe); | |
1738 | val = I915_READ(reg); | |
1739 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1740 | I915_WRITE(reg, val); | |
59c859d6 | 1741 | } |
23670b32 | 1742 | |
ab9412ba | 1743 | reg = PCH_TRANSCONF(pipe); |
040484af | 1744 | val = I915_READ(reg); |
5f7f726d | 1745 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1746 | |
2d1fe073 | 1747 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1748 | /* |
c5de7c6f VS |
1749 | * Make the BPC in transcoder be consistent with |
1750 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1751 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1752 | */ |
dfd07d72 | 1753 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1754 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1755 | val |= PIPECONF_8BPC; |
1756 | else | |
1757 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1758 | } |
5f7f726d PZ |
1759 | |
1760 | val &= ~TRANS_INTERLACE_MASK; | |
1761 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1762 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1763 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1764 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1765 | else | |
1766 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1767 | else |
1768 | val |= TRANS_PROGRESSIVE; | |
1769 | ||
040484af | 1770 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1771 | if (intel_wait_for_register(dev_priv, |
1772 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1773 | 100)) | |
4bb6f1f3 | 1774 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1775 | } |
1776 | ||
8fb033d7 | 1777 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1778 | enum transcoder cpu_transcoder) |
040484af | 1779 | { |
8fb033d7 | 1780 | u32 val, pipeconf_val; |
8fb033d7 | 1781 | |
8fb033d7 | 1782 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1783 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1784 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1785 | |
223a6fdf | 1786 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1787 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1788 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1789 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1790 | |
25f3ef11 | 1791 | val = TRANS_ENABLE; |
937bb610 | 1792 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1793 | |
9a76b1c6 PZ |
1794 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1795 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1796 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1797 | else |
1798 | val |= TRANS_PROGRESSIVE; | |
1799 | ||
ab9412ba | 1800 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1801 | if (intel_wait_for_register(dev_priv, |
1802 | LPT_TRANSCONF, | |
1803 | TRANS_STATE_ENABLE, | |
1804 | TRANS_STATE_ENABLE, | |
1805 | 100)) | |
937bb610 | 1806 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1807 | } |
1808 | ||
b8a4f404 PZ |
1809 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1810 | enum pipe pipe) | |
040484af | 1811 | { |
f0f59a00 VS |
1812 | i915_reg_t reg; |
1813 | uint32_t val; | |
040484af JB |
1814 | |
1815 | /* FDI relies on the transcoder */ | |
1816 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1817 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1818 | ||
291906f1 JB |
1819 | /* Ports must be off as well */ |
1820 | assert_pch_ports_disabled(dev_priv, pipe); | |
1821 | ||
ab9412ba | 1822 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1823 | val = I915_READ(reg); |
1824 | val &= ~TRANS_ENABLE; | |
1825 | I915_WRITE(reg, val); | |
1826 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1827 | if (intel_wait_for_register(dev_priv, |
1828 | reg, TRANS_STATE_ENABLE, 0, | |
1829 | 50)) | |
4bb6f1f3 | 1830 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1831 | |
6e266956 | 1832 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1833 | /* Workaround: Clear the timing override chicken bit again. */ |
1834 | reg = TRANS_CHICKEN2(pipe); | |
1835 | val = I915_READ(reg); | |
1836 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1837 | I915_WRITE(reg, val); | |
1838 | } | |
040484af JB |
1839 | } |
1840 | ||
b7076546 | 1841 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1842 | { |
8fb033d7 PZ |
1843 | u32 val; |
1844 | ||
ab9412ba | 1845 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1846 | val &= ~TRANS_ENABLE; |
ab9412ba | 1847 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1848 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1849 | if (intel_wait_for_register(dev_priv, |
1850 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1851 | 50)) | |
8a52fd9f | 1852 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1853 | |
1854 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1855 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1856 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1857 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1858 | } |
1859 | ||
65f2130c VS |
1860 | enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
1861 | { | |
1862 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1863 | ||
1864 | WARN_ON(!crtc->config->has_pch_encoder); | |
1865 | ||
1866 | if (HAS_PCH_LPT(dev_priv)) | |
1867 | return TRANSCODER_A; | |
1868 | else | |
1869 | return (enum transcoder) crtc->pipe; | |
1870 | } | |
1871 | ||
b24e7179 | 1872 | /** |
309cfea8 | 1873 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1874 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1875 | * |
0372264a | 1876 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1877 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1878 | */ |
e1fdc473 | 1879 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1880 | { |
0372264a | 1881 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1882 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1883 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1884 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1885 | i915_reg_t reg; |
b24e7179 JB |
1886 | u32 val; |
1887 | ||
9e2ee2dd VS |
1888 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1889 | ||
58c6eaa2 | 1890 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1891 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1892 | assert_sprites_disabled(dev_priv, pipe); |
1893 | ||
b24e7179 JB |
1894 | /* |
1895 | * A pipe without a PLL won't actually be able to drive bits from | |
1896 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1897 | * need the check. | |
1898 | */ | |
09fa8bb9 | 1899 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1900 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1901 | assert_dsi_pll_enabled(dev_priv); |
1902 | else | |
1903 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1904 | } else { |
6e3c9717 | 1905 | if (crtc->config->has_pch_encoder) { |
040484af | 1906 | /* if driving the PCH, we need FDI enabled */ |
65f2130c VS |
1907 | assert_fdi_rx_pll_enabled(dev_priv, |
1908 | (enum pipe) intel_crtc_pch_transcoder(crtc)); | |
1a240d4d DV |
1909 | assert_fdi_tx_pll_enabled(dev_priv, |
1910 | (enum pipe) cpu_transcoder); | |
040484af JB |
1911 | } |
1912 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1913 | } | |
b24e7179 | 1914 | |
702e7a56 | 1915 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1916 | val = I915_READ(reg); |
7ad25d48 | 1917 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1918 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1919 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1920 | return; |
7ad25d48 | 1921 | } |
00d70b15 CW |
1922 | |
1923 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1924 | POSTING_READ(reg); |
b7792d8b VS |
1925 | |
1926 | /* | |
1927 | * Until the pipe starts DSL will read as 0, which would cause | |
1928 | * an apparent vblank timestamp jump, which messes up also the | |
1929 | * frame count when it's derived from the timestamps. So let's | |
1930 | * wait for the pipe to start properly before we call | |
1931 | * drm_crtc_vblank_on() | |
1932 | */ | |
1933 | if (dev->max_vblank_count == 0 && | |
1934 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1935 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1936 | } |
1937 | ||
1938 | /** | |
309cfea8 | 1939 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 1940 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 1941 | * |
575f7ab7 VS |
1942 | * Disable the pipe of @crtc, making sure that various hardware |
1943 | * specific requirements are met, if applicable, e.g. plane | |
1944 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
1945 | * |
1946 | * Will wait until the pipe has shut down before returning. | |
1947 | */ | |
575f7ab7 | 1948 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1949 | { |
fac5e23e | 1950 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1951 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1952 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1953 | i915_reg_t reg; |
b24e7179 JB |
1954 | u32 val; |
1955 | ||
9e2ee2dd VS |
1956 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
1957 | ||
b24e7179 JB |
1958 | /* |
1959 | * Make sure planes won't keep trying to pump pixels to us, | |
1960 | * or we might hang the display. | |
1961 | */ | |
1962 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1963 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1964 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 1965 | |
702e7a56 | 1966 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1967 | val = I915_READ(reg); |
00d70b15 CW |
1968 | if ((val & PIPECONF_ENABLE) == 0) |
1969 | return; | |
1970 | ||
67adc644 VS |
1971 | /* |
1972 | * Double wide has implications for planes | |
1973 | * so best keep it disabled when not needed. | |
1974 | */ | |
6e3c9717 | 1975 | if (crtc->config->double_wide) |
67adc644 VS |
1976 | val &= ~PIPECONF_DOUBLE_WIDE; |
1977 | ||
1978 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
1979 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
1980 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
1981 | val &= ~PIPECONF_ENABLE; |
1982 | ||
1983 | I915_WRITE(reg, val); | |
1984 | if ((val & PIPECONF_ENABLE) == 0) | |
1985 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
1986 | } |
1987 | ||
832be82f VS |
1988 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
1989 | { | |
1990 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
1991 | } | |
1992 | ||
d88c4afd VS |
1993 | static unsigned int |
1994 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) | |
7b49f948 | 1995 | { |
d88c4afd VS |
1996 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
1997 | unsigned int cpp = fb->format->cpp[plane]; | |
1998 | ||
1999 | switch (fb->modifier) { | |
2f075565 | 2000 | case DRM_FORMAT_MOD_LINEAR: |
7b49f948 VS |
2001 | return cpp; |
2002 | case I915_FORMAT_MOD_X_TILED: | |
2003 | if (IS_GEN2(dev_priv)) | |
2004 | return 128; | |
2005 | else | |
2006 | return 512; | |
2007 | case I915_FORMAT_MOD_Y_TILED: | |
2008 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2009 | return 128; | |
2010 | else | |
2011 | return 512; | |
2012 | case I915_FORMAT_MOD_Yf_TILED: | |
2013 | switch (cpp) { | |
2014 | case 1: | |
2015 | return 64; | |
2016 | case 2: | |
2017 | case 4: | |
2018 | return 128; | |
2019 | case 8: | |
2020 | case 16: | |
2021 | return 256; | |
2022 | default: | |
2023 | MISSING_CASE(cpp); | |
2024 | return cpp; | |
2025 | } | |
2026 | break; | |
2027 | default: | |
d88c4afd | 2028 | MISSING_CASE(fb->modifier); |
7b49f948 VS |
2029 | return cpp; |
2030 | } | |
2031 | } | |
2032 | ||
d88c4afd VS |
2033 | static unsigned int |
2034 | intel_tile_height(const struct drm_framebuffer *fb, int plane) | |
a57ce0b2 | 2035 | { |
2f075565 | 2036 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
832be82f VS |
2037 | return 1; |
2038 | else | |
d88c4afd VS |
2039 | return intel_tile_size(to_i915(fb->dev)) / |
2040 | intel_tile_width_bytes(fb, plane); | |
6761dd31 TU |
2041 | } |
2042 | ||
8d0deca8 | 2043 | /* Return the tile dimensions in pixel units */ |
d88c4afd | 2044 | static void intel_tile_dims(const struct drm_framebuffer *fb, int plane, |
8d0deca8 | 2045 | unsigned int *tile_width, |
d88c4afd | 2046 | unsigned int *tile_height) |
8d0deca8 | 2047 | { |
d88c4afd VS |
2048 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane); |
2049 | unsigned int cpp = fb->format->cpp[plane]; | |
8d0deca8 VS |
2050 | |
2051 | *tile_width = tile_width_bytes / cpp; | |
d88c4afd | 2052 | *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes; |
8d0deca8 VS |
2053 | } |
2054 | ||
6761dd31 | 2055 | unsigned int |
d88c4afd VS |
2056 | intel_fb_align_height(const struct drm_framebuffer *fb, |
2057 | int plane, unsigned int height) | |
6761dd31 | 2058 | { |
d88c4afd | 2059 | unsigned int tile_height = intel_tile_height(fb, plane); |
832be82f VS |
2060 | |
2061 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2062 | } |
2063 | ||
1663b9d6 VS |
2064 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2065 | { | |
2066 | unsigned int size = 0; | |
2067 | int i; | |
2068 | ||
2069 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2070 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2071 | ||
2072 | return size; | |
2073 | } | |
2074 | ||
75c82a53 | 2075 | static void |
3465c580 VS |
2076 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2077 | const struct drm_framebuffer *fb, | |
2078 | unsigned int rotation) | |
f64b98cd | 2079 | { |
7b92c047 | 2080 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2081 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2082 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2083 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2084 | } |
2085 | } | |
50470bb0 | 2086 | |
603525d7 | 2087 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2088 | { |
2089 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2090 | return 256 * 1024; | |
c0f86832 | 2091 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2092 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2093 | return 128 * 1024; |
2094 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2095 | return 4 * 1024; | |
2096 | else | |
44c5905e | 2097 | return 0; |
4e9a86b6 VS |
2098 | } |
2099 | ||
d88c4afd VS |
2100 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
2101 | int plane) | |
603525d7 | 2102 | { |
d88c4afd VS |
2103 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2104 | ||
b90c1ee1 VS |
2105 | /* AUX_DIST needs only 4K alignment */ |
2106 | if (fb->format->format == DRM_FORMAT_NV12 && plane == 1) | |
2107 | return 4096; | |
2108 | ||
d88c4afd | 2109 | switch (fb->modifier) { |
2f075565 | 2110 | case DRM_FORMAT_MOD_LINEAR: |
603525d7 VS |
2111 | return intel_linear_alignment(dev_priv); |
2112 | case I915_FORMAT_MOD_X_TILED: | |
d88c4afd | 2113 | if (INTEL_GEN(dev_priv) >= 9) |
603525d7 VS |
2114 | return 256 * 1024; |
2115 | return 0; | |
2116 | case I915_FORMAT_MOD_Y_TILED: | |
2117 | case I915_FORMAT_MOD_Yf_TILED: | |
2118 | return 1 * 1024 * 1024; | |
2119 | default: | |
d88c4afd | 2120 | MISSING_CASE(fb->modifier); |
603525d7 VS |
2121 | return 0; |
2122 | } | |
2123 | } | |
2124 | ||
058d88c4 CW |
2125 | struct i915_vma * |
2126 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2127 | { |
850c4cdc | 2128 | struct drm_device *dev = fb->dev; |
fac5e23e | 2129 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2130 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2131 | struct i915_ggtt_view view; |
058d88c4 | 2132 | struct i915_vma *vma; |
6b95a207 | 2133 | u32 alignment; |
6b95a207 | 2134 | |
ebcdd39e MR |
2135 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2136 | ||
d88c4afd | 2137 | alignment = intel_surf_alignment(fb, 0); |
6b95a207 | 2138 | |
3465c580 | 2139 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2140 | |
693db184 CW |
2141 | /* Note that the w/a also requires 64 PTE of padding following the |
2142 | * bo. We currently fill all unused PTE with the shadow page and so | |
2143 | * we should always have valid PTE following the scanout preventing | |
2144 | * the VT-d warning. | |
2145 | */ | |
48f112fe | 2146 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2147 | alignment = 256 * 1024; |
2148 | ||
d6dd6843 PZ |
2149 | /* |
2150 | * Global gtt pte registers are special registers which actually forward | |
2151 | * writes to a chunk of system memory. Which means that there is no risk | |
2152 | * that the register values disappear as soon as we call | |
2153 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2154 | * pin/unpin/fence and not more. | |
2155 | */ | |
2156 | intel_runtime_pm_get(dev_priv); | |
2157 | ||
058d88c4 | 2158 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2159 | if (IS_ERR(vma)) |
2160 | goto err; | |
6b95a207 | 2161 | |
05a20d09 | 2162 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2163 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2164 | * fence, whereas 965+ only requires a fence if using | |
2165 | * framebuffer compression. For simplicity, we always, when | |
2166 | * possible, install a fence as the cost is not that onerous. | |
2167 | * | |
2168 | * If we fail to fence the tiled scanout, then either the | |
2169 | * modeset will reject the change (which is highly unlikely as | |
2170 | * the affected systems, all but one, do not have unmappable | |
2171 | * space) or we will not be able to enable full powersaving | |
2172 | * techniques (also likely not to apply due to various limits | |
2173 | * FBC and the like impose on the size of the buffer, which | |
2174 | * presumably we violated anyway with this unmappable buffer). | |
2175 | * Anyway, it is presumably better to stumble onwards with | |
2176 | * something and try to run the system in a "less than optimal" | |
2177 | * mode that matches the user configuration. | |
2178 | */ | |
2179 | if (i915_vma_get_fence(vma) == 0) | |
2180 | i915_vma_pin_fence(vma); | |
9807216f | 2181 | } |
6b95a207 | 2182 | |
be1e3415 | 2183 | i915_vma_get(vma); |
49ef5294 | 2184 | err: |
d6dd6843 | 2185 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2186 | return vma; |
6b95a207 KH |
2187 | } |
2188 | ||
be1e3415 | 2189 | void intel_unpin_fb_vma(struct i915_vma *vma) |
1690e1eb | 2190 | { |
be1e3415 | 2191 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
f64b98cd | 2192 | |
49ef5294 | 2193 | i915_vma_unpin_fence(vma); |
058d88c4 | 2194 | i915_gem_object_unpin_from_display_plane(vma); |
be1e3415 | 2195 | i915_vma_put(vma); |
1690e1eb CW |
2196 | } |
2197 | ||
ef78ec94 VS |
2198 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2199 | unsigned int rotation) | |
2200 | { | |
bd2ef25d | 2201 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2202 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2203 | else | |
2204 | return fb->pitches[plane]; | |
2205 | } | |
2206 | ||
6687c906 VS |
2207 | /* |
2208 | * Convert the x/y offsets into a linear offset. | |
2209 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2210 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2211 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2212 | */ | |
2213 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2214 | const struct intel_plane_state *state, |
2215 | int plane) | |
6687c906 | 2216 | { |
2949056c | 2217 | const struct drm_framebuffer *fb = state->base.fb; |
353c8598 | 2218 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2219 | unsigned int pitch = fb->pitches[plane]; |
2220 | ||
2221 | return y * pitch + x * cpp; | |
2222 | } | |
2223 | ||
2224 | /* | |
2225 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2226 | * specified plane src x/y offsets. The resulting x/y offsets | |
2227 | * specify the start of scanout from the beginning of the gtt mapping. | |
2228 | */ | |
2229 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2230 | const struct intel_plane_state *state, |
2231 | int plane) | |
6687c906 VS |
2232 | |
2233 | { | |
2949056c VS |
2234 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2235 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2236 | |
bd2ef25d | 2237 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2238 | *x += intel_fb->rotated[plane].x; |
2239 | *y += intel_fb->rotated[plane].y; | |
2240 | } else { | |
2241 | *x += intel_fb->normal[plane].x; | |
2242 | *y += intel_fb->normal[plane].y; | |
2243 | } | |
2244 | } | |
2245 | ||
29cf9491 | 2246 | /* |
29cf9491 VS |
2247 | * Input tile dimensions and pitch must already be |
2248 | * rotated to match x and y, and in pixel units. | |
2249 | */ | |
66a2d927 VS |
2250 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2251 | unsigned int tile_width, | |
2252 | unsigned int tile_height, | |
2253 | unsigned int tile_size, | |
2254 | unsigned int pitch_tiles, | |
2255 | u32 old_offset, | |
2256 | u32 new_offset) | |
29cf9491 | 2257 | { |
b9b24038 | 2258 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2259 | unsigned int tiles; |
2260 | ||
2261 | WARN_ON(old_offset & (tile_size - 1)); | |
2262 | WARN_ON(new_offset & (tile_size - 1)); | |
2263 | WARN_ON(new_offset > old_offset); | |
2264 | ||
2265 | tiles = (old_offset - new_offset) / tile_size; | |
2266 | ||
2267 | *y += tiles / pitch_tiles * tile_height; | |
2268 | *x += tiles % pitch_tiles * tile_width; | |
2269 | ||
b9b24038 VS |
2270 | /* minimize x in case it got needlessly big */ |
2271 | *y += *x / pitch_pixels * tile_height; | |
2272 | *x %= pitch_pixels; | |
2273 | ||
29cf9491 VS |
2274 | return new_offset; |
2275 | } | |
2276 | ||
66a2d927 VS |
2277 | /* |
2278 | * Adjust the tile offset by moving the difference into | |
2279 | * the x/y offsets. | |
2280 | */ | |
2281 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2282 | const struct intel_plane_state *state, int plane, | |
2283 | u32 old_offset, u32 new_offset) | |
2284 | { | |
2285 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2286 | const struct drm_framebuffer *fb = state->base.fb; | |
353c8598 | 2287 | unsigned int cpp = fb->format->cpp[plane]; |
66a2d927 VS |
2288 | unsigned int rotation = state->base.rotation; |
2289 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2290 | ||
2291 | WARN_ON(new_offset > old_offset); | |
2292 | ||
2f075565 | 2293 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
66a2d927 VS |
2294 | unsigned int tile_size, tile_width, tile_height; |
2295 | unsigned int pitch_tiles; | |
2296 | ||
2297 | tile_size = intel_tile_size(dev_priv); | |
d88c4afd | 2298 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
66a2d927 | 2299 | |
bd2ef25d | 2300 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2301 | pitch_tiles = pitch / tile_height; |
2302 | swap(tile_width, tile_height); | |
2303 | } else { | |
2304 | pitch_tiles = pitch / (tile_width * cpp); | |
2305 | } | |
2306 | ||
2307 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2308 | tile_size, pitch_tiles, | |
2309 | old_offset, new_offset); | |
2310 | } else { | |
2311 | old_offset += *y * pitch + *x * cpp; | |
2312 | ||
2313 | *y = (old_offset - new_offset) / pitch; | |
2314 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2315 | } | |
2316 | ||
2317 | return new_offset; | |
2318 | } | |
2319 | ||
8d0deca8 VS |
2320 | /* |
2321 | * Computes the linear offset to the base tile and adjusts | |
2322 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2323 | * | |
2324 | * In the 90/270 rotated case, x and y are assumed | |
2325 | * to be already rotated to match the rotated GTT view, and | |
2326 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2327 | * |
2328 | * This function is used when computing the derived information | |
2329 | * under intel_framebuffer, so using any of that information | |
2330 | * here is not allowed. Anything under drm_framebuffer can be | |
2331 | * used. This is why the user has to pass in the pitch since it | |
2332 | * is specified in the rotated orientation. | |
8d0deca8 | 2333 | */ |
6687c906 VS |
2334 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2335 | int *x, int *y, | |
2336 | const struct drm_framebuffer *fb, int plane, | |
2337 | unsigned int pitch, | |
2338 | unsigned int rotation, | |
2339 | u32 alignment) | |
c2c75131 | 2340 | { |
bae781b2 | 2341 | uint64_t fb_modifier = fb->modifier; |
353c8598 | 2342 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 | 2343 | u32 offset, offset_aligned; |
29cf9491 | 2344 | |
29cf9491 VS |
2345 | if (alignment) |
2346 | alignment--; | |
2347 | ||
2f075565 | 2348 | if (fb_modifier != DRM_FORMAT_MOD_LINEAR) { |
8d0deca8 VS |
2349 | unsigned int tile_size, tile_width, tile_height; |
2350 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2351 | |
d843310d | 2352 | tile_size = intel_tile_size(dev_priv); |
d88c4afd | 2353 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
8d0deca8 | 2354 | |
bd2ef25d | 2355 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2356 | pitch_tiles = pitch / tile_height; |
2357 | swap(tile_width, tile_height); | |
2358 | } else { | |
2359 | pitch_tiles = pitch / (tile_width * cpp); | |
2360 | } | |
d843310d VS |
2361 | |
2362 | tile_rows = *y / tile_height; | |
2363 | *y %= tile_height; | |
c2c75131 | 2364 | |
8d0deca8 VS |
2365 | tiles = *x / tile_width; |
2366 | *x %= tile_width; | |
bc752862 | 2367 | |
29cf9491 VS |
2368 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2369 | offset_aligned = offset & ~alignment; | |
bc752862 | 2370 | |
66a2d927 VS |
2371 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2372 | tile_size, pitch_tiles, | |
2373 | offset, offset_aligned); | |
29cf9491 | 2374 | } else { |
bc752862 | 2375 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2376 | offset_aligned = offset & ~alignment; |
2377 | ||
4e9a86b6 VS |
2378 | *y = (offset & alignment) / pitch; |
2379 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2380 | } |
29cf9491 VS |
2381 | |
2382 | return offset_aligned; | |
c2c75131 DV |
2383 | } |
2384 | ||
6687c906 | 2385 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2386 | const struct intel_plane_state *state, |
2387 | int plane) | |
6687c906 | 2388 | { |
2949056c VS |
2389 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
2390 | const struct drm_framebuffer *fb = state->base.fb; | |
2391 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2392 | int pitch = intel_fb_pitch(fb, plane, rotation); |
b90c1ee1 | 2393 | u32 alignment = intel_surf_alignment(fb, plane); |
6687c906 VS |
2394 | |
2395 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2396 | rotation, alignment); | |
2397 | } | |
2398 | ||
2399 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2400 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2401 | const struct drm_framebuffer *fb, int plane) | |
2402 | { | |
353c8598 | 2403 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2404 | unsigned int pitch = fb->pitches[plane]; |
2405 | u32 linear_offset = fb->offsets[plane]; | |
2406 | ||
2407 | *y = linear_offset / pitch; | |
2408 | *x = linear_offset % pitch / cpp; | |
2409 | } | |
2410 | ||
72618ebf VS |
2411 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2412 | { | |
2413 | switch (fb_modifier) { | |
2414 | case I915_FORMAT_MOD_X_TILED: | |
2415 | return I915_TILING_X; | |
2416 | case I915_FORMAT_MOD_Y_TILED: | |
2417 | return I915_TILING_Y; | |
2418 | default: | |
2419 | return I915_TILING_NONE; | |
2420 | } | |
2421 | } | |
2422 | ||
6687c906 VS |
2423 | static int |
2424 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2425 | struct drm_framebuffer *fb) | |
2426 | { | |
2427 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2428 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2429 | u32 gtt_offset_rotated = 0; | |
2430 | unsigned int max_size = 0; | |
bcb0b461 | 2431 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
2432 | unsigned int tile_size = intel_tile_size(dev_priv); |
2433 | ||
2434 | for (i = 0; i < num_planes; i++) { | |
2435 | unsigned int width, height; | |
2436 | unsigned int cpp, size; | |
2437 | u32 offset; | |
2438 | int x, y; | |
2439 | ||
353c8598 | 2440 | cpp = fb->format->cpp[i]; |
145fcb11 VS |
2441 | width = drm_framebuffer_plane_width(fb->width, fb, i); |
2442 | height = drm_framebuffer_plane_height(fb->height, fb, i); | |
6687c906 VS |
2443 | |
2444 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2445 | ||
60d5f2a4 VS |
2446 | /* |
2447 | * The fence (if used) is aligned to the start of the object | |
2448 | * so having the framebuffer wrap around across the edge of the | |
2449 | * fenced region doesn't really work. We have no API to configure | |
2450 | * the fence start offset within the object (nor could we probably | |
2451 | * on gen2/3). So it's just easier if we just require that the | |
2452 | * fb layout agrees with the fence layout. We already check that the | |
2453 | * fb stride matches the fence stride elsewhere. | |
2454 | */ | |
2455 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2456 | (x + width) * cpp > fb->pitches[i]) { | |
144cc143 VS |
2457 | DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", |
2458 | i, fb->offsets[i]); | |
60d5f2a4 VS |
2459 | return -EINVAL; |
2460 | } | |
2461 | ||
6687c906 VS |
2462 | /* |
2463 | * First pixel of the framebuffer from | |
2464 | * the start of the normal gtt mapping. | |
2465 | */ | |
2466 | intel_fb->normal[i].x = x; | |
2467 | intel_fb->normal[i].y = y; | |
2468 | ||
2469 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
3ca46c0a | 2470 | fb, i, fb->pitches[i], |
cc926387 | 2471 | DRM_ROTATE_0, tile_size); |
6687c906 VS |
2472 | offset /= tile_size; |
2473 | ||
2f075565 | 2474 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
6687c906 VS |
2475 | unsigned int tile_width, tile_height; |
2476 | unsigned int pitch_tiles; | |
2477 | struct drm_rect r; | |
2478 | ||
d88c4afd | 2479 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
6687c906 VS |
2480 | |
2481 | rot_info->plane[i].offset = offset; | |
2482 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2483 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2484 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2485 | ||
2486 | intel_fb->rotated[i].pitch = | |
2487 | rot_info->plane[i].height * tile_height; | |
2488 | ||
2489 | /* how many tiles does this plane need */ | |
2490 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2491 | /* | |
2492 | * If the plane isn't horizontally tile aligned, | |
2493 | * we need one more tile. | |
2494 | */ | |
2495 | if (x != 0) | |
2496 | size++; | |
2497 | ||
2498 | /* rotate the x/y offsets to match the GTT view */ | |
2499 | r.x1 = x; | |
2500 | r.y1 = y; | |
2501 | r.x2 = x + width; | |
2502 | r.y2 = y + height; | |
2503 | drm_rect_rotate(&r, | |
2504 | rot_info->plane[i].width * tile_width, | |
2505 | rot_info->plane[i].height * tile_height, | |
cc926387 | 2506 | DRM_ROTATE_270); |
6687c906 VS |
2507 | x = r.x1; |
2508 | y = r.y1; | |
2509 | ||
2510 | /* rotate the tile dimensions to match the GTT view */ | |
2511 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2512 | swap(tile_width, tile_height); | |
2513 | ||
2514 | /* | |
2515 | * We only keep the x/y offsets, so push all of the | |
2516 | * gtt offset into the x/y offsets. | |
2517 | */ | |
46a1bd28 ACO |
2518 | _intel_adjust_tile_offset(&x, &y, |
2519 | tile_width, tile_height, | |
2520 | tile_size, pitch_tiles, | |
66a2d927 | 2521 | gtt_offset_rotated * tile_size, 0); |
6687c906 VS |
2522 | |
2523 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2524 | ||
2525 | /* | |
2526 | * First pixel of the framebuffer from | |
2527 | * the start of the rotated gtt mapping. | |
2528 | */ | |
2529 | intel_fb->rotated[i].x = x; | |
2530 | intel_fb->rotated[i].y = y; | |
2531 | } else { | |
2532 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2533 | x * cpp, tile_size); | |
2534 | } | |
2535 | ||
2536 | /* how many tiles in total needed in the bo */ | |
2537 | max_size = max(max_size, offset + size); | |
2538 | } | |
2539 | ||
144cc143 VS |
2540 | if (max_size * tile_size > intel_fb->obj->base.size) { |
2541 | DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2542 | max_size * tile_size, intel_fb->obj->base.size); | |
6687c906 VS |
2543 | return -EINVAL; |
2544 | } | |
2545 | ||
2546 | return 0; | |
2547 | } | |
2548 | ||
b35d63fa | 2549 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2550 | { |
2551 | switch (format) { | |
2552 | case DISPPLANE_8BPP: | |
2553 | return DRM_FORMAT_C8; | |
2554 | case DISPPLANE_BGRX555: | |
2555 | return DRM_FORMAT_XRGB1555; | |
2556 | case DISPPLANE_BGRX565: | |
2557 | return DRM_FORMAT_RGB565; | |
2558 | default: | |
2559 | case DISPPLANE_BGRX888: | |
2560 | return DRM_FORMAT_XRGB8888; | |
2561 | case DISPPLANE_RGBX888: | |
2562 | return DRM_FORMAT_XBGR8888; | |
2563 | case DISPPLANE_BGRX101010: | |
2564 | return DRM_FORMAT_XRGB2101010; | |
2565 | case DISPPLANE_RGBX101010: | |
2566 | return DRM_FORMAT_XBGR2101010; | |
2567 | } | |
2568 | } | |
2569 | ||
bc8d7dff DL |
2570 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2571 | { | |
2572 | switch (format) { | |
2573 | case PLANE_CTL_FORMAT_RGB_565: | |
2574 | return DRM_FORMAT_RGB565; | |
2575 | default: | |
2576 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2577 | if (rgb_order) { | |
2578 | if (alpha) | |
2579 | return DRM_FORMAT_ABGR8888; | |
2580 | else | |
2581 | return DRM_FORMAT_XBGR8888; | |
2582 | } else { | |
2583 | if (alpha) | |
2584 | return DRM_FORMAT_ARGB8888; | |
2585 | else | |
2586 | return DRM_FORMAT_XRGB8888; | |
2587 | } | |
2588 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2589 | if (rgb_order) | |
2590 | return DRM_FORMAT_XBGR2101010; | |
2591 | else | |
2592 | return DRM_FORMAT_XRGB2101010; | |
2593 | } | |
2594 | } | |
2595 | ||
5724dbd1 | 2596 | static bool |
f6936e29 DV |
2597 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2598 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2599 | { |
2600 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2601 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2602 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2603 | struct drm_i915_gem_object *obj = NULL; |
2604 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2605 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2606 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2607 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2608 | PAGE_SIZE); | |
2609 | ||
2610 | size_aligned -= base_aligned; | |
46f297fb | 2611 | |
ff2652ea CW |
2612 | if (plane_config->size == 0) |
2613 | return false; | |
2614 | ||
3badb49f PZ |
2615 | /* If the FB is too big, just don't use it since fbdev is not very |
2616 | * important and we should probably use that space with FBC or other | |
2617 | * features. */ | |
72e96d64 | 2618 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2619 | return false; |
2620 | ||
12c83d99 | 2621 | mutex_lock(&dev->struct_mutex); |
187685cb | 2622 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2623 | base_aligned, |
2624 | base_aligned, | |
2625 | size_aligned); | |
24dbf51a CW |
2626 | mutex_unlock(&dev->struct_mutex); |
2627 | if (!obj) | |
484b41dd | 2628 | return false; |
46f297fb | 2629 | |
3e510a8e CW |
2630 | if (plane_config->tiling == I915_TILING_X) |
2631 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2632 | |
438b74a5 | 2633 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
2634 | mode_cmd.width = fb->width; |
2635 | mode_cmd.height = fb->height; | |
2636 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2637 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2638 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2639 | |
24dbf51a | 2640 | if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { |
46f297fb JB |
2641 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2642 | goto out_unref_obj; | |
2643 | } | |
12c83d99 | 2644 | |
484b41dd | 2645 | |
f6936e29 | 2646 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2647 | return true; |
46f297fb JB |
2648 | |
2649 | out_unref_obj: | |
f8c417cd | 2650 | i915_gem_object_put(obj); |
484b41dd JB |
2651 | return false; |
2652 | } | |
2653 | ||
5a21b665 DV |
2654 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2655 | static void | |
2656 | update_state_fb(struct drm_plane *plane) | |
2657 | { | |
2658 | if (plane->fb == plane->state->fb) | |
2659 | return; | |
2660 | ||
2661 | if (plane->state->fb) | |
2662 | drm_framebuffer_unreference(plane->state->fb); | |
2663 | plane->state->fb = plane->fb; | |
2664 | if (plane->state->fb) | |
2665 | drm_framebuffer_reference(plane->state->fb); | |
2666 | } | |
2667 | ||
e9728bd8 VS |
2668 | static void |
2669 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
2670 | struct intel_plane_state *plane_state, | |
2671 | bool visible) | |
2672 | { | |
2673 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
2674 | ||
2675 | plane_state->base.visible = visible; | |
2676 | ||
2677 | /* FIXME pre-g4x don't work like this */ | |
2678 | if (visible) { | |
2679 | crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); | |
2680 | crtc_state->active_planes |= BIT(plane->id); | |
2681 | } else { | |
2682 | crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); | |
2683 | crtc_state->active_planes &= ~BIT(plane->id); | |
2684 | } | |
2685 | ||
2686 | DRM_DEBUG_KMS("%s active planes 0x%x\n", | |
2687 | crtc_state->base.crtc->name, | |
2688 | crtc_state->active_planes); | |
2689 | } | |
2690 | ||
5724dbd1 | 2691 | static void |
f6936e29 DV |
2692 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2693 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2694 | { |
2695 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2696 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 2697 | struct drm_crtc *c; |
2ff8fde1 | 2698 | struct drm_i915_gem_object *obj; |
88595ac9 | 2699 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2700 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2701 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2702 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2703 | struct intel_plane_state *intel_state = |
2704 | to_intel_plane_state(plane_state); | |
88595ac9 | 2705 | struct drm_framebuffer *fb; |
484b41dd | 2706 | |
2d14030b | 2707 | if (!plane_config->fb) |
484b41dd JB |
2708 | return; |
2709 | ||
f6936e29 | 2710 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2711 | fb = &plane_config->fb->base; |
2712 | goto valid_fb; | |
f55548b5 | 2713 | } |
484b41dd | 2714 | |
2d14030b | 2715 | kfree(plane_config->fb); |
484b41dd JB |
2716 | |
2717 | /* | |
2718 | * Failed to alloc the obj, check to see if we should share | |
2719 | * an fb with another CRTC instead | |
2720 | */ | |
70e1e0ec | 2721 | for_each_crtc(dev, c) { |
be1e3415 | 2722 | struct intel_plane_state *state; |
484b41dd JB |
2723 | |
2724 | if (c == &intel_crtc->base) | |
2725 | continue; | |
2726 | ||
be1e3415 | 2727 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
2728 | continue; |
2729 | ||
be1e3415 CW |
2730 | state = to_intel_plane_state(c->primary->state); |
2731 | if (!state->vma) | |
484b41dd JB |
2732 | continue; |
2733 | ||
be1e3415 CW |
2734 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
2735 | fb = c->primary->fb; | |
88595ac9 DV |
2736 | drm_framebuffer_reference(fb); |
2737 | goto valid_fb; | |
484b41dd JB |
2738 | } |
2739 | } | |
88595ac9 | 2740 | |
200757f5 MR |
2741 | /* |
2742 | * We've failed to reconstruct the BIOS FB. Current display state | |
2743 | * indicates that the primary plane is visible, but has a NULL FB, | |
2744 | * which will lead to problems later if we don't fix it up. The | |
2745 | * simplest solution is to just disable the primary plane now and | |
2746 | * pretend the BIOS never had it enabled. | |
2747 | */ | |
e9728bd8 VS |
2748 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), |
2749 | to_intel_plane_state(plane_state), | |
2750 | false); | |
2622a081 | 2751 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
72259536 | 2752 | trace_intel_disable_plane(primary, intel_crtc); |
200757f5 MR |
2753 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2754 | ||
88595ac9 DV |
2755 | return; |
2756 | ||
2757 | valid_fb: | |
be1e3415 CW |
2758 | mutex_lock(&dev->struct_mutex); |
2759 | intel_state->vma = | |
2760 | intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
2761 | mutex_unlock(&dev->struct_mutex); | |
2762 | if (IS_ERR(intel_state->vma)) { | |
2763 | DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", | |
2764 | intel_crtc->pipe, PTR_ERR(intel_state->vma)); | |
2765 | ||
2766 | intel_state->vma = NULL; | |
2767 | drm_framebuffer_unreference(fb); | |
2768 | return; | |
2769 | } | |
2770 | ||
f44e2659 VS |
2771 | plane_state->src_x = 0; |
2772 | plane_state->src_y = 0; | |
be5651f2 ML |
2773 | plane_state->src_w = fb->width << 16; |
2774 | plane_state->src_h = fb->height << 16; | |
2775 | ||
f44e2659 VS |
2776 | plane_state->crtc_x = 0; |
2777 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2778 | plane_state->crtc_w = fb->width; |
2779 | plane_state->crtc_h = fb->height; | |
2780 | ||
1638d30c RC |
2781 | intel_state->base.src = drm_plane_state_src(plane_state); |
2782 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2783 | |
88595ac9 | 2784 | obj = intel_fb_obj(fb); |
3e510a8e | 2785 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2786 | dev_priv->preserve_bios_swizzle = true; |
2787 | ||
be5651f2 ML |
2788 | drm_framebuffer_reference(fb); |
2789 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2790 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
e9728bd8 VS |
2791 | |
2792 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), | |
2793 | to_intel_plane_state(plane_state), | |
2794 | true); | |
2795 | ||
faf5bf0a CW |
2796 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2797 | &obj->frontbuffer_bits); | |
46f297fb JB |
2798 | } |
2799 | ||
b63a16f6 VS |
2800 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2801 | unsigned int rotation) | |
2802 | { | |
353c8598 | 2803 | int cpp = fb->format->cpp[plane]; |
b63a16f6 | 2804 | |
bae781b2 | 2805 | switch (fb->modifier) { |
2f075565 | 2806 | case DRM_FORMAT_MOD_LINEAR: |
b63a16f6 VS |
2807 | case I915_FORMAT_MOD_X_TILED: |
2808 | switch (cpp) { | |
2809 | case 8: | |
2810 | return 4096; | |
2811 | case 4: | |
2812 | case 2: | |
2813 | case 1: | |
2814 | return 8192; | |
2815 | default: | |
2816 | MISSING_CASE(cpp); | |
2817 | break; | |
2818 | } | |
2819 | break; | |
2820 | case I915_FORMAT_MOD_Y_TILED: | |
2821 | case I915_FORMAT_MOD_Yf_TILED: | |
2822 | switch (cpp) { | |
2823 | case 8: | |
2824 | return 2048; | |
2825 | case 4: | |
2826 | return 4096; | |
2827 | case 2: | |
2828 | case 1: | |
2829 | return 8192; | |
2830 | default: | |
2831 | MISSING_CASE(cpp); | |
2832 | break; | |
2833 | } | |
2834 | break; | |
2835 | default: | |
bae781b2 | 2836 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2837 | } |
2838 | ||
2839 | return 2048; | |
2840 | } | |
2841 | ||
2842 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2843 | { | |
b63a16f6 VS |
2844 | const struct drm_framebuffer *fb = plane_state->base.fb; |
2845 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2846 | int x = plane_state->base.src.x1 >> 16; |
2847 | int y = plane_state->base.src.y1 >> 16; | |
2848 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2849 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2850 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2851 | int max_height = 4096; | |
8d970654 | 2852 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2853 | |
2854 | if (w > max_width || h > max_height) { | |
2855 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2856 | w, h, max_width, max_height); | |
2857 | return -EINVAL; | |
2858 | } | |
2859 | ||
2860 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2861 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
d88c4afd | 2862 | alignment = intel_surf_alignment(fb, 0); |
b63a16f6 | 2863 | |
8d970654 VS |
2864 | /* |
2865 | * AUX surface offset is specified as the distance from the | |
2866 | * main surface offset, and it must be non-negative. Make | |
2867 | * sure that is what we will get. | |
2868 | */ | |
2869 | if (offset > aux_offset) | |
2870 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2871 | offset, aux_offset & ~(alignment - 1)); | |
2872 | ||
b63a16f6 VS |
2873 | /* |
2874 | * When using an X-tiled surface, the plane blows up | |
2875 | * if the x offset + width exceed the stride. | |
2876 | * | |
2877 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2878 | */ | |
bae781b2 | 2879 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 2880 | int cpp = fb->format->cpp[0]; |
b63a16f6 VS |
2881 | |
2882 | while ((x + w) * cpp > fb->pitches[0]) { | |
2883 | if (offset == 0) { | |
2884 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2885 | return -EINVAL; | |
2886 | } | |
2887 | ||
2888 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2889 | offset, offset - alignment); | |
2890 | } | |
2891 | } | |
2892 | ||
2893 | plane_state->main.offset = offset; | |
2894 | plane_state->main.x = x; | |
2895 | plane_state->main.y = y; | |
2896 | ||
2897 | return 0; | |
2898 | } | |
2899 | ||
8d970654 VS |
2900 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2901 | { | |
2902 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2903 | unsigned int rotation = plane_state->base.rotation; | |
2904 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2905 | int max_height = 4096; | |
cc926387 DV |
2906 | int x = plane_state->base.src.x1 >> 17; |
2907 | int y = plane_state->base.src.y1 >> 17; | |
2908 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2909 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2910 | u32 offset; |
2911 | ||
2912 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2913 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2914 | ||
2915 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2916 | if (w > max_width || h > max_height) { | |
2917 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2918 | w, h, max_width, max_height); | |
2919 | return -EINVAL; | |
2920 | } | |
2921 | ||
2922 | plane_state->aux.offset = offset; | |
2923 | plane_state->aux.x = x; | |
2924 | plane_state->aux.y = y; | |
2925 | ||
2926 | return 0; | |
2927 | } | |
2928 | ||
b63a16f6 VS |
2929 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2930 | { | |
2931 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2932 | unsigned int rotation = plane_state->base.rotation; | |
2933 | int ret; | |
2934 | ||
a5e4c7d0 VS |
2935 | if (!plane_state->base.visible) |
2936 | return 0; | |
2937 | ||
b63a16f6 | 2938 | /* Rotate src coordinates to match rotated GTT view */ |
bd2ef25d | 2939 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 2940 | drm_rect_rotate(&plane_state->base.src, |
da064b47 VS |
2941 | fb->width << 16, fb->height << 16, |
2942 | DRM_ROTATE_270); | |
b63a16f6 | 2943 | |
8d970654 VS |
2944 | /* |
2945 | * Handle the AUX surface first since | |
2946 | * the main surface setup depends on it. | |
2947 | */ | |
438b74a5 | 2948 | if (fb->format->format == DRM_FORMAT_NV12) { |
8d970654 VS |
2949 | ret = skl_check_nv12_aux_surface(plane_state); |
2950 | if (ret) | |
2951 | return ret; | |
2952 | } else { | |
2953 | plane_state->aux.offset = ~0xfff; | |
2954 | plane_state->aux.x = 0; | |
2955 | plane_state->aux.y = 0; | |
2956 | } | |
2957 | ||
b63a16f6 VS |
2958 | ret = skl_check_main_surface(plane_state); |
2959 | if (ret) | |
2960 | return ret; | |
2961 | ||
2962 | return 0; | |
2963 | } | |
2964 | ||
7145f60a VS |
2965 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
2966 | const struct intel_plane_state *plane_state) | |
81255565 | 2967 | { |
7145f60a VS |
2968 | struct drm_i915_private *dev_priv = |
2969 | to_i915(plane_state->base.plane->dev); | |
2970 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
2971 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
8d0deca8 | 2972 | unsigned int rotation = plane_state->base.rotation; |
7145f60a | 2973 | u32 dspcntr; |
c9ba6fad | 2974 | |
7145f60a | 2975 | dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; |
f45651ba | 2976 | |
6a4407a6 VS |
2977 | if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || |
2978 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
7145f60a | 2979 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
f45651ba | 2980 | |
6a4407a6 VS |
2981 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
2982 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
2983 | ||
d509e28b VS |
2984 | if (INTEL_GEN(dev_priv) < 4) |
2985 | dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); | |
81255565 | 2986 | |
438b74a5 | 2987 | switch (fb->format->format) { |
57779d06 | 2988 | case DRM_FORMAT_C8: |
81255565 JB |
2989 | dspcntr |= DISPPLANE_8BPP; |
2990 | break; | |
57779d06 | 2991 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2992 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2993 | break; |
57779d06 VS |
2994 | case DRM_FORMAT_RGB565: |
2995 | dspcntr |= DISPPLANE_BGRX565; | |
2996 | break; | |
2997 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2998 | dspcntr |= DISPPLANE_BGRX888; |
2999 | break; | |
3000 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3001 | dspcntr |= DISPPLANE_RGBX888; |
3002 | break; | |
3003 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3004 | dspcntr |= DISPPLANE_BGRX101010; |
3005 | break; | |
3006 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3007 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3008 | break; |
3009 | default: | |
7145f60a VS |
3010 | MISSING_CASE(fb->format->format); |
3011 | return 0; | |
81255565 | 3012 | } |
57779d06 | 3013 | |
72618ebf | 3014 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3015 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3016 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3017 | |
df0cd455 VS |
3018 | if (rotation & DRM_ROTATE_180) |
3019 | dspcntr |= DISPPLANE_ROTATE_180; | |
3020 | ||
4ea7be2b VS |
3021 | if (rotation & DRM_REFLECT_X) |
3022 | dspcntr |= DISPPLANE_MIRROR; | |
3023 | ||
7145f60a VS |
3024 | return dspcntr; |
3025 | } | |
3026 | ||
f9407ae1 | 3027 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
5b7fcc44 VS |
3028 | { |
3029 | struct drm_i915_private *dev_priv = | |
3030 | to_i915(plane_state->base.plane->dev); | |
3031 | int src_x = plane_state->base.src.x1 >> 16; | |
3032 | int src_y = plane_state->base.src.y1 >> 16; | |
3033 | u32 offset; | |
3034 | ||
3035 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); | |
3036 | ||
3037 | if (INTEL_GEN(dev_priv) >= 4) | |
3038 | offset = intel_compute_tile_offset(&src_x, &src_y, | |
3039 | plane_state, 0); | |
3040 | else | |
3041 | offset = 0; | |
3042 | ||
3043 | /* HSW/BDW do this automagically in hardware */ | |
3044 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { | |
3045 | unsigned int rotation = plane_state->base.rotation; | |
3046 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; | |
3047 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3048 | ||
3049 | if (rotation & DRM_ROTATE_180) { | |
3050 | src_x += src_w - 1; | |
3051 | src_y += src_h - 1; | |
3052 | } else if (rotation & DRM_REFLECT_X) { | |
3053 | src_x += src_w - 1; | |
3054 | } | |
3055 | } | |
3056 | ||
3057 | plane_state->main.offset = offset; | |
3058 | plane_state->main.x = src_x; | |
3059 | plane_state->main.y = src_y; | |
3060 | ||
3061 | return 0; | |
3062 | } | |
3063 | ||
7145f60a VS |
3064 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
3065 | const struct intel_crtc_state *crtc_state, | |
3066 | const struct intel_plane_state *plane_state) | |
3067 | { | |
3068 | struct drm_i915_private *dev_priv = to_i915(primary->dev); | |
3069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
3070 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3071 | int plane = intel_crtc->plane; | |
3072 | u32 linear_offset; | |
a0864d59 | 3073 | u32 dspcntr = plane_state->ctl; |
7145f60a | 3074 | i915_reg_t reg = DSPCNTR(plane); |
5b7fcc44 VS |
3075 | int x = plane_state->main.x; |
3076 | int y = plane_state->main.y; | |
7145f60a VS |
3077 | unsigned long irqflags; |
3078 | ||
2949056c | 3079 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3080 | |
5b7fcc44 VS |
3081 | if (INTEL_GEN(dev_priv) >= 4) |
3082 | intel_crtc->dspaddr_offset = plane_state->main.offset; | |
3083 | else | |
6687c906 VS |
3084 | intel_crtc->dspaddr_offset = linear_offset; |
3085 | ||
2db3366b PZ |
3086 | intel_crtc->adjusted_x = x; |
3087 | intel_crtc->adjusted_y = y; | |
3088 | ||
dd584fc0 VS |
3089 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3090 | ||
78587de2 VS |
3091 | if (INTEL_GEN(dev_priv) < 4) { |
3092 | /* pipesrc and dspsize control the size that is scaled from, | |
3093 | * which should always be the user's requested size. | |
3094 | */ | |
dd584fc0 VS |
3095 | I915_WRITE_FW(DSPSIZE(plane), |
3096 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3097 | (crtc_state->pipe_src_w - 1)); | |
3098 | I915_WRITE_FW(DSPPOS(plane), 0); | |
78587de2 | 3099 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
dd584fc0 VS |
3100 | I915_WRITE_FW(PRIMSIZE(plane), |
3101 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3102 | (crtc_state->pipe_src_w - 1)); | |
3103 | I915_WRITE_FW(PRIMPOS(plane), 0); | |
3104 | I915_WRITE_FW(PRIMCNSTALPHA(plane), 0); | |
78587de2 VS |
3105 | } |
3106 | ||
dd584fc0 | 3107 | I915_WRITE_FW(reg, dspcntr); |
48404c1e | 3108 | |
dd584fc0 | 3109 | I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]); |
3ba35e53 VS |
3110 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3111 | I915_WRITE_FW(DSPSURF(plane), | |
3112 | intel_plane_ggtt_offset(plane_state) + | |
3113 | intel_crtc->dspaddr_offset); | |
3114 | I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); | |
3115 | } else if (INTEL_GEN(dev_priv) >= 4) { | |
dd584fc0 VS |
3116 | I915_WRITE_FW(DSPSURF(plane), |
3117 | intel_plane_ggtt_offset(plane_state) + | |
3118 | intel_crtc->dspaddr_offset); | |
3119 | I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); | |
3120 | I915_WRITE_FW(DSPLINOFF(plane), linear_offset); | |
bfb81049 | 3121 | } else { |
dd584fc0 VS |
3122 | I915_WRITE_FW(DSPADDR(plane), |
3123 | intel_plane_ggtt_offset(plane_state) + | |
3124 | intel_crtc->dspaddr_offset); | |
bfb81049 | 3125 | } |
dd584fc0 VS |
3126 | POSTING_READ_FW(reg); |
3127 | ||
3128 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
17638cd6 JB |
3129 | } |
3130 | ||
a8d201af ML |
3131 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
3132 | struct drm_crtc *crtc) | |
17638cd6 JB |
3133 | { |
3134 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3135 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 3136 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 3137 | int plane = intel_crtc->plane; |
dd584fc0 VS |
3138 | unsigned long irqflags; |
3139 | ||
3140 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
f45651ba | 3141 | |
dd584fc0 | 3142 | I915_WRITE_FW(DSPCNTR(plane), 0); |
a8d201af | 3143 | if (INTEL_INFO(dev_priv)->gen >= 4) |
dd584fc0 | 3144 | I915_WRITE_FW(DSPSURF(plane), 0); |
a8d201af | 3145 | else |
dd584fc0 VS |
3146 | I915_WRITE_FW(DSPADDR(plane), 0); |
3147 | POSTING_READ_FW(DSPCNTR(plane)); | |
3148 | ||
3149 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3150 | } |
c9ba6fad | 3151 | |
d88c4afd VS |
3152 | static u32 |
3153 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane) | |
b321803d | 3154 | { |
2f075565 | 3155 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
b321803d | 3156 | return 64; |
d88c4afd VS |
3157 | else |
3158 | return intel_tile_width_bytes(fb, plane); | |
b321803d DL |
3159 | } |
3160 | ||
e435d6e5 ML |
3161 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3162 | { | |
3163 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3164 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3165 | |
3166 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3167 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3168 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3169 | } |
3170 | ||
a1b2278e CK |
3171 | /* |
3172 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3173 | */ | |
0583236e | 3174 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3175 | { |
a1b2278e CK |
3176 | struct intel_crtc_scaler_state *scaler_state; |
3177 | int i; | |
3178 | ||
a1b2278e CK |
3179 | scaler_state = &intel_crtc->config->scaler_state; |
3180 | ||
3181 | /* loop through and disable scalers that aren't in use */ | |
3182 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3183 | if (!scaler_state->scalers[i].in_use) |
3184 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3185 | } |
3186 | } | |
3187 | ||
d2196774 VS |
3188 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3189 | unsigned int rotation) | |
3190 | { | |
1b500535 VS |
3191 | u32 stride; |
3192 | ||
3193 | if (plane >= fb->format->num_planes) | |
3194 | return 0; | |
3195 | ||
3196 | stride = intel_fb_pitch(fb, plane, rotation); | |
d2196774 VS |
3197 | |
3198 | /* | |
3199 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3200 | * linear buffers or in number of tiles for tiled buffers. | |
3201 | */ | |
d88c4afd VS |
3202 | if (drm_rotation_90_or_270(rotation)) |
3203 | stride /= intel_tile_height(fb, plane); | |
3204 | else | |
3205 | stride /= intel_fb_stride_alignment(fb, plane); | |
d2196774 VS |
3206 | |
3207 | return stride; | |
3208 | } | |
3209 | ||
2e881264 | 3210 | static u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3211 | { |
6156a456 | 3212 | switch (pixel_format) { |
d161cf7a | 3213 | case DRM_FORMAT_C8: |
c34ce3d1 | 3214 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3215 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3216 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3217 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3218 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3219 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3220 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3221 | /* |
3222 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3223 | * to be already pre-multiplied. We need to add a knob (or a different | |
3224 | * DRM_FORMAT) for user-space to configure that. | |
3225 | */ | |
f75fb42a | 3226 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3227 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3228 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3229 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3230 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3231 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3232 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3233 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3234 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3235 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3236 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3237 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3238 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3239 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3240 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3241 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3242 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3243 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3244 | default: |
4249eeef | 3245 | MISSING_CASE(pixel_format); |
70d21f0e | 3246 | } |
8cfcba41 | 3247 | |
c34ce3d1 | 3248 | return 0; |
6156a456 | 3249 | } |
70d21f0e | 3250 | |
2e881264 | 3251 | static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
6156a456 | 3252 | { |
6156a456 | 3253 | switch (fb_modifier) { |
2f075565 | 3254 | case DRM_FORMAT_MOD_LINEAR: |
70d21f0e | 3255 | break; |
30af77c4 | 3256 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3257 | return PLANE_CTL_TILED_X; |
b321803d | 3258 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3259 | return PLANE_CTL_TILED_Y; |
b321803d | 3260 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3261 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3262 | default: |
6156a456 | 3263 | MISSING_CASE(fb_modifier); |
70d21f0e | 3264 | } |
8cfcba41 | 3265 | |
c34ce3d1 | 3266 | return 0; |
6156a456 | 3267 | } |
70d21f0e | 3268 | |
2e881264 | 3269 | static u32 skl_plane_ctl_rotation(unsigned int rotation) |
6156a456 | 3270 | { |
3b7a5119 | 3271 | switch (rotation) { |
31ad61e4 | 3272 | case DRM_ROTATE_0: |
6156a456 | 3273 | break; |
1e8df167 SJ |
3274 | /* |
3275 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3276 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3277 | */ | |
31ad61e4 | 3278 | case DRM_ROTATE_90: |
1e8df167 | 3279 | return PLANE_CTL_ROTATE_270; |
31ad61e4 | 3280 | case DRM_ROTATE_180: |
c34ce3d1 | 3281 | return PLANE_CTL_ROTATE_180; |
31ad61e4 | 3282 | case DRM_ROTATE_270: |
1e8df167 | 3283 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3284 | default: |
3285 | MISSING_CASE(rotation); | |
3286 | } | |
3287 | ||
c34ce3d1 | 3288 | return 0; |
6156a456 CK |
3289 | } |
3290 | ||
2e881264 VS |
3291 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
3292 | const struct intel_plane_state *plane_state) | |
46f788ba VS |
3293 | { |
3294 | struct drm_i915_private *dev_priv = | |
3295 | to_i915(plane_state->base.plane->dev); | |
3296 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3297 | unsigned int rotation = plane_state->base.rotation; | |
2e881264 | 3298 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
46f788ba VS |
3299 | u32 plane_ctl; |
3300 | ||
3301 | plane_ctl = PLANE_CTL_ENABLE; | |
3302 | ||
3303 | if (!IS_GEMINILAKE(dev_priv)) { | |
3304 | plane_ctl |= | |
3305 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3306 | PLANE_CTL_PIPE_CSC_ENABLE | | |
3307 | PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3308 | } | |
3309 | ||
3310 | plane_ctl |= skl_plane_ctl_format(fb->format->format); | |
3311 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); | |
3312 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3313 | ||
2e881264 VS |
3314 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
3315 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
3316 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
3317 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
3318 | ||
46f788ba VS |
3319 | return plane_ctl; |
3320 | } | |
3321 | ||
a8d201af ML |
3322 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3323 | const struct intel_crtc_state *crtc_state, | |
3324 | const struct intel_plane_state *plane_state) | |
6156a456 | 3325 | { |
a8d201af | 3326 | struct drm_device *dev = plane->dev; |
fac5e23e | 3327 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3329 | struct drm_framebuffer *fb = plane_state->base.fb; | |
8e816bb4 VS |
3330 | enum plane_id plane_id = to_intel_plane(plane)->id; |
3331 | enum pipe pipe = to_intel_plane(plane)->pipe; | |
a0864d59 | 3332 | u32 plane_ctl = plane_state->ctl; |
a8d201af | 3333 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3334 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3335 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3336 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3337 | int src_x = plane_state->main.x; |
3338 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3339 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3340 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3341 | int dst_x = plane_state->base.dst.x1; | |
3342 | int dst_y = plane_state->base.dst.y1; | |
3343 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3344 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
dd584fc0 | 3345 | unsigned long irqflags; |
70d21f0e | 3346 | |
6687c906 VS |
3347 | /* Sizes are 0 based */ |
3348 | src_w--; | |
3349 | src_h--; | |
3350 | dst_w--; | |
3351 | dst_h--; | |
3352 | ||
4c0b8a8b PZ |
3353 | intel_crtc->dspaddr_offset = surf_addr; |
3354 | ||
6687c906 VS |
3355 | intel_crtc->adjusted_x = src_x; |
3356 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3357 | |
dd584fc0 VS |
3358 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3359 | ||
78587de2 | 3360 | if (IS_GEMINILAKE(dev_priv)) { |
dd584fc0 VS |
3361 | I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), |
3362 | PLANE_COLOR_PIPE_GAMMA_ENABLE | | |
3363 | PLANE_COLOR_PIPE_CSC_ENABLE | | |
3364 | PLANE_COLOR_PLANE_GAMMA_DISABLE); | |
78587de2 VS |
3365 | } |
3366 | ||
dd584fc0 VS |
3367 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); |
3368 | I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3369 | I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); | |
3370 | I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
6156a456 CK |
3371 | |
3372 | if (scaler_id >= 0) { | |
3373 | uint32_t ps_ctrl = 0; | |
3374 | ||
3375 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3376 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 | 3377 | crtc_state->scaler_state.scalers[scaler_id].mode; |
dd584fc0 VS |
3378 | I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
3379 | I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3380 | I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3381 | I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3382 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0); | |
6156a456 | 3383 | } else { |
dd584fc0 | 3384 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3385 | } |
3386 | ||
dd584fc0 VS |
3387 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), |
3388 | intel_plane_ggtt_offset(plane_state) + surf_addr); | |
70d21f0e | 3389 | |
dd584fc0 VS |
3390 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); |
3391 | ||
3392 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
70d21f0e DL |
3393 | } |
3394 | ||
a8d201af ML |
3395 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3396 | struct drm_crtc *crtc) | |
17638cd6 JB |
3397 | { |
3398 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3399 | struct drm_i915_private *dev_priv = to_i915(dev); |
8e816bb4 VS |
3400 | enum plane_id plane_id = to_intel_plane(primary)->id; |
3401 | enum pipe pipe = to_intel_plane(primary)->pipe; | |
dd584fc0 VS |
3402 | unsigned long irqflags; |
3403 | ||
3404 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
62e0fb88 | 3405 | |
dd584fc0 VS |
3406 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); |
3407 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); | |
3408 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); | |
3409 | ||
3410 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3411 | } |
29b9bde6 | 3412 | |
5a21b665 DV |
3413 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3414 | { | |
3415 | struct intel_crtc *crtc; | |
3416 | ||
91c8a326 | 3417 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3418 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3419 | } | |
3420 | ||
7514747d VS |
3421 | static void intel_update_primary_planes(struct drm_device *dev) |
3422 | { | |
7514747d | 3423 | struct drm_crtc *crtc; |
96a02917 | 3424 | |
70e1e0ec | 3425 | for_each_crtc(dev, crtc) { |
11c22da6 | 3426 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3427 | struct intel_plane_state *plane_state = |
3428 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3429 | |
72259536 VS |
3430 | if (plane_state->base.visible) { |
3431 | trace_intel_update_plane(&plane->base, | |
3432 | to_intel_crtc(crtc)); | |
3433 | ||
a8d201af ML |
3434 | plane->update_plane(&plane->base, |
3435 | to_intel_crtc_state(crtc->state), | |
3436 | plane_state); | |
72259536 | 3437 | } |
73974893 ML |
3438 | } |
3439 | } | |
3440 | ||
3441 | static int | |
3442 | __intel_display_resume(struct drm_device *dev, | |
581e49fe ML |
3443 | struct drm_atomic_state *state, |
3444 | struct drm_modeset_acquire_ctx *ctx) | |
73974893 ML |
3445 | { |
3446 | struct drm_crtc_state *crtc_state; | |
3447 | struct drm_crtc *crtc; | |
3448 | int i, ret; | |
11c22da6 | 3449 | |
73974893 | 3450 | intel_modeset_setup_hw_state(dev); |
29b74b7f | 3451 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3452 | |
3453 | if (!state) | |
3454 | return 0; | |
3455 | ||
aa5e9b47 ML |
3456 | /* |
3457 | * We've duplicated the state, pointers to the old state are invalid. | |
3458 | * | |
3459 | * Don't attempt to use the old state until we commit the duplicated state. | |
3460 | */ | |
3461 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { | |
73974893 ML |
3462 | /* |
3463 | * Force recalculation even if we restore | |
3464 | * current state. With fast modeset this may not result | |
3465 | * in a modeset when the state is compatible. | |
3466 | */ | |
3467 | crtc_state->mode_changed = true; | |
96a02917 | 3468 | } |
73974893 ML |
3469 | |
3470 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
602ae835 VS |
3471 | if (!HAS_GMCH_DISPLAY(to_i915(dev))) |
3472 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
73974893 | 3473 | |
581e49fe | 3474 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
73974893 ML |
3475 | |
3476 | WARN_ON(ret == -EDEADLK); | |
3477 | return ret; | |
96a02917 VS |
3478 | } |
3479 | ||
4ac2ba2f VS |
3480 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3481 | { | |
ae98104b VS |
3482 | return intel_has_gpu_reset(dev_priv) && |
3483 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3484 | } |
3485 | ||
c033666a | 3486 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3487 | { |
73974893 ML |
3488 | struct drm_device *dev = &dev_priv->drm; |
3489 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3490 | struct drm_atomic_state *state; | |
3491 | int ret; | |
3492 | ||
73974893 ML |
3493 | /* |
3494 | * Need mode_config.mutex so that we don't | |
3495 | * trample ongoing ->detect() and whatnot. | |
3496 | */ | |
3497 | mutex_lock(&dev->mode_config.mutex); | |
3498 | drm_modeset_acquire_init(ctx, 0); | |
3499 | while (1) { | |
3500 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3501 | if (ret != -EDEADLK) | |
3502 | break; | |
3503 | ||
3504 | drm_modeset_backoff(ctx); | |
3505 | } | |
3506 | ||
3507 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3508 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3509 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3510 | return; |
3511 | ||
f98ce92f VS |
3512 | /* |
3513 | * Disabling the crtcs gracefully seems nicer. Also the | |
3514 | * g33 docs say we should at least disable all the planes. | |
3515 | */ | |
73974893 ML |
3516 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3517 | if (IS_ERR(state)) { | |
3518 | ret = PTR_ERR(state); | |
73974893 | 3519 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
1e5a15d6 | 3520 | return; |
73974893 ML |
3521 | } |
3522 | ||
3523 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3524 | if (ret) { | |
3525 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
1e5a15d6 ACO |
3526 | drm_atomic_state_put(state); |
3527 | return; | |
73974893 ML |
3528 | } |
3529 | ||
3530 | dev_priv->modeset_restore_state = state; | |
3531 | state->acquire_ctx = ctx; | |
7514747d VS |
3532 | } |
3533 | ||
c033666a | 3534 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3535 | { |
73974893 ML |
3536 | struct drm_device *dev = &dev_priv->drm; |
3537 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3538 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3539 | int ret; | |
3540 | ||
5a21b665 DV |
3541 | /* |
3542 | * Flips in the rings will be nuked by the reset, | |
3543 | * so complete all pending flips so that user space | |
3544 | * will get its events and not get stuck. | |
3545 | */ | |
3546 | intel_complete_page_flips(dev_priv); | |
3547 | ||
73974893 ML |
3548 | dev_priv->modeset_restore_state = NULL; |
3549 | ||
7514747d | 3550 | /* reset doesn't touch the display */ |
4ac2ba2f | 3551 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3552 | if (!state) { |
3553 | /* | |
3554 | * Flips in the rings have been nuked by the reset, | |
3555 | * so update the base address of all primary | |
3556 | * planes to the the last fb to make sure we're | |
3557 | * showing the correct fb after a reset. | |
3558 | * | |
3559 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3560 | * CS-based flips (which might get lost in gpu resets) any more. | |
3561 | */ | |
3562 | intel_update_primary_planes(dev); | |
3563 | } else { | |
581e49fe | 3564 | ret = __intel_display_resume(dev, state, ctx); |
522a63de ML |
3565 | if (ret) |
3566 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3567 | } | |
73974893 ML |
3568 | } else { |
3569 | /* | |
3570 | * The display has been reset as well, | |
3571 | * so need a full re-initialization. | |
3572 | */ | |
3573 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3574 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3575 | |
51f59205 | 3576 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3577 | intel_modeset_init_hw(dev); |
7514747d | 3578 | |
73974893 ML |
3579 | spin_lock_irq(&dev_priv->irq_lock); |
3580 | if (dev_priv->display.hpd_irq_setup) | |
3581 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3582 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3583 | |
581e49fe | 3584 | ret = __intel_display_resume(dev, state, ctx); |
73974893 ML |
3585 | if (ret) |
3586 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3587 | |
73974893 ML |
3588 | intel_hpd_init(dev_priv); |
3589 | } | |
7514747d | 3590 | |
0853695c CW |
3591 | if (state) |
3592 | drm_atomic_state_put(state); | |
73974893 ML |
3593 | drm_modeset_drop_locks(ctx); |
3594 | drm_modeset_acquire_fini(ctx); | |
3595 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3596 | } |
3597 | ||
8af29b0c CW |
3598 | static bool abort_flip_on_reset(struct intel_crtc *crtc) |
3599 | { | |
3600 | struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; | |
3601 | ||
8c185eca | 3602 | if (i915_reset_backoff(error)) |
8af29b0c CW |
3603 | return true; |
3604 | ||
3605 | if (crtc->reset_count != i915_reset_count(error)) | |
3606 | return true; | |
3607 | ||
3608 | return false; | |
3609 | } | |
3610 | ||
7d5e3799 CW |
3611 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3612 | { | |
5a21b665 DV |
3613 | struct drm_device *dev = crtc->dev; |
3614 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5a21b665 DV |
3615 | bool pending; |
3616 | ||
8af29b0c | 3617 | if (abort_flip_on_reset(intel_crtc)) |
5a21b665 DV |
3618 | return false; |
3619 | ||
3620 | spin_lock_irq(&dev->event_lock); | |
3621 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3622 | spin_unlock_irq(&dev->event_lock); | |
3623 | ||
3624 | return pending; | |
7d5e3799 CW |
3625 | } |
3626 | ||
bfd16b2a ML |
3627 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3628 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3629 | { |
6315b5d3 | 3630 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3631 | struct intel_crtc_state *pipe_config = |
3632 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3633 | |
bfd16b2a ML |
3634 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3635 | crtc->base.mode = crtc->base.state->mode; | |
3636 | ||
e30e8f75 GP |
3637 | /* |
3638 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3639 | * that in compute_mode_changes we check the native mode (not the pfit | |
3640 | * mode) to see if we can flip rather than do a full mode set. In the | |
3641 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3642 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3643 | * sized surface. | |
e30e8f75 GP |
3644 | */ |
3645 | ||
e30e8f75 | 3646 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3647 | ((pipe_config->pipe_src_w - 1) << 16) | |
3648 | (pipe_config->pipe_src_h - 1)); | |
3649 | ||
3650 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3651 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3652 | skl_detach_scalers(crtc); |
3653 | ||
3654 | if (pipe_config->pch_pfit.enabled) | |
3655 | skylake_pfit_enable(crtc); | |
6e266956 | 3656 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3657 | if (pipe_config->pch_pfit.enabled) |
3658 | ironlake_pfit_enable(crtc); | |
3659 | else if (old_crtc_state->pch_pfit.enabled) | |
3660 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3661 | } |
e30e8f75 GP |
3662 | } |
3663 | ||
4cbe4b2b | 3664 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 3665 | { |
4cbe4b2b | 3666 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3667 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3668 | int pipe = crtc->pipe; |
f0f59a00 VS |
3669 | i915_reg_t reg; |
3670 | u32 temp; | |
5e84e1a4 ZW |
3671 | |
3672 | /* enable normal train */ | |
3673 | reg = FDI_TX_CTL(pipe); | |
3674 | temp = I915_READ(reg); | |
fd6b8f43 | 3675 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3676 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3677 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3678 | } else { |
3679 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3680 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3681 | } |
5e84e1a4 ZW |
3682 | I915_WRITE(reg, temp); |
3683 | ||
3684 | reg = FDI_RX_CTL(pipe); | |
3685 | temp = I915_READ(reg); | |
6e266956 | 3686 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3687 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3688 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3689 | } else { | |
3690 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3691 | temp |= FDI_LINK_TRAIN_NONE; | |
3692 | } | |
3693 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3694 | ||
3695 | /* wait one idle pattern time */ | |
3696 | POSTING_READ(reg); | |
3697 | udelay(1000); | |
357555c0 JB |
3698 | |
3699 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3700 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3701 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3702 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3703 | } |
3704 | ||
8db9d77b | 3705 | /* The FDI link training functions for ILK/Ibexpeak. */ |
dc4a1094 ACO |
3706 | static void ironlake_fdi_link_train(struct intel_crtc *crtc, |
3707 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3708 | { |
4cbe4b2b | 3709 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3710 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3711 | int pipe = crtc->pipe; |
f0f59a00 VS |
3712 | i915_reg_t reg; |
3713 | u32 temp, tries; | |
8db9d77b | 3714 | |
1c8562f6 | 3715 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3716 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3717 | |
e1a44743 AJ |
3718 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3719 | for train result */ | |
5eddb70b CW |
3720 | reg = FDI_RX_IMR(pipe); |
3721 | temp = I915_READ(reg); | |
e1a44743 AJ |
3722 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3723 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3724 | I915_WRITE(reg, temp); |
3725 | I915_READ(reg); | |
e1a44743 AJ |
3726 | udelay(150); |
3727 | ||
8db9d77b | 3728 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3729 | reg = FDI_TX_CTL(pipe); |
3730 | temp = I915_READ(reg); | |
627eb5a3 | 3731 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3732 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3733 | temp &= ~FDI_LINK_TRAIN_NONE; |
3734 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3735 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3736 | |
5eddb70b CW |
3737 | reg = FDI_RX_CTL(pipe); |
3738 | temp = I915_READ(reg); | |
8db9d77b ZW |
3739 | temp &= ~FDI_LINK_TRAIN_NONE; |
3740 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3741 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3742 | ||
3743 | POSTING_READ(reg); | |
8db9d77b ZW |
3744 | udelay(150); |
3745 | ||
5b2adf89 | 3746 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3747 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3748 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3749 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3750 | |
5eddb70b | 3751 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3752 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3753 | temp = I915_READ(reg); |
8db9d77b ZW |
3754 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3755 | ||
3756 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3757 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3758 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3759 | break; |
3760 | } | |
8db9d77b | 3761 | } |
e1a44743 | 3762 | if (tries == 5) |
5eddb70b | 3763 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3764 | |
3765 | /* Train 2 */ | |
5eddb70b CW |
3766 | reg = FDI_TX_CTL(pipe); |
3767 | temp = I915_READ(reg); | |
8db9d77b ZW |
3768 | temp &= ~FDI_LINK_TRAIN_NONE; |
3769 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3770 | I915_WRITE(reg, temp); |
8db9d77b | 3771 | |
5eddb70b CW |
3772 | reg = FDI_RX_CTL(pipe); |
3773 | temp = I915_READ(reg); | |
8db9d77b ZW |
3774 | temp &= ~FDI_LINK_TRAIN_NONE; |
3775 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3776 | I915_WRITE(reg, temp); |
8db9d77b | 3777 | |
5eddb70b CW |
3778 | POSTING_READ(reg); |
3779 | udelay(150); | |
8db9d77b | 3780 | |
5eddb70b | 3781 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3782 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3783 | temp = I915_READ(reg); |
8db9d77b ZW |
3784 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3785 | ||
3786 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3787 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3788 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3789 | break; | |
3790 | } | |
8db9d77b | 3791 | } |
e1a44743 | 3792 | if (tries == 5) |
5eddb70b | 3793 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3794 | |
3795 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3796 | |
8db9d77b ZW |
3797 | } |
3798 | ||
0206e353 | 3799 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3800 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3801 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3802 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3803 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3804 | }; | |
3805 | ||
3806 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
3807 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
3808 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3809 | { |
4cbe4b2b | 3810 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3811 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3812 | int pipe = crtc->pipe; |
f0f59a00 VS |
3813 | i915_reg_t reg; |
3814 | u32 temp, i, retry; | |
8db9d77b | 3815 | |
e1a44743 AJ |
3816 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3817 | for train result */ | |
5eddb70b CW |
3818 | reg = FDI_RX_IMR(pipe); |
3819 | temp = I915_READ(reg); | |
e1a44743 AJ |
3820 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3821 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3822 | I915_WRITE(reg, temp); |
3823 | ||
3824 | POSTING_READ(reg); | |
e1a44743 AJ |
3825 | udelay(150); |
3826 | ||
8db9d77b | 3827 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3828 | reg = FDI_TX_CTL(pipe); |
3829 | temp = I915_READ(reg); | |
627eb5a3 | 3830 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3831 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3832 | temp &= ~FDI_LINK_TRAIN_NONE; |
3833 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3834 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3835 | /* SNB-B */ | |
3836 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3837 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3838 | |
d74cf324 DV |
3839 | I915_WRITE(FDI_RX_MISC(pipe), |
3840 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3841 | ||
5eddb70b CW |
3842 | reg = FDI_RX_CTL(pipe); |
3843 | temp = I915_READ(reg); | |
6e266956 | 3844 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3845 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3846 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3847 | } else { | |
3848 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3849 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3850 | } | |
5eddb70b CW |
3851 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3852 | ||
3853 | POSTING_READ(reg); | |
8db9d77b ZW |
3854 | udelay(150); |
3855 | ||
0206e353 | 3856 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3857 | reg = FDI_TX_CTL(pipe); |
3858 | temp = I915_READ(reg); | |
8db9d77b ZW |
3859 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3860 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3861 | I915_WRITE(reg, temp); |
3862 | ||
3863 | POSTING_READ(reg); | |
8db9d77b ZW |
3864 | udelay(500); |
3865 | ||
fa37d39e SP |
3866 | for (retry = 0; retry < 5; retry++) { |
3867 | reg = FDI_RX_IIR(pipe); | |
3868 | temp = I915_READ(reg); | |
3869 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3870 | if (temp & FDI_RX_BIT_LOCK) { | |
3871 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3872 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3873 | break; | |
3874 | } | |
3875 | udelay(50); | |
8db9d77b | 3876 | } |
fa37d39e SP |
3877 | if (retry < 5) |
3878 | break; | |
8db9d77b ZW |
3879 | } |
3880 | if (i == 4) | |
5eddb70b | 3881 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3882 | |
3883 | /* Train 2 */ | |
5eddb70b CW |
3884 | reg = FDI_TX_CTL(pipe); |
3885 | temp = I915_READ(reg); | |
8db9d77b ZW |
3886 | temp &= ~FDI_LINK_TRAIN_NONE; |
3887 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3888 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3889 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3890 | /* SNB-B */ | |
3891 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3892 | } | |
5eddb70b | 3893 | I915_WRITE(reg, temp); |
8db9d77b | 3894 | |
5eddb70b CW |
3895 | reg = FDI_RX_CTL(pipe); |
3896 | temp = I915_READ(reg); | |
6e266956 | 3897 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3898 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3899 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3900 | } else { | |
3901 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3902 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3903 | } | |
5eddb70b CW |
3904 | I915_WRITE(reg, temp); |
3905 | ||
3906 | POSTING_READ(reg); | |
8db9d77b ZW |
3907 | udelay(150); |
3908 | ||
0206e353 | 3909 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3910 | reg = FDI_TX_CTL(pipe); |
3911 | temp = I915_READ(reg); | |
8db9d77b ZW |
3912 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3913 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3914 | I915_WRITE(reg, temp); |
3915 | ||
3916 | POSTING_READ(reg); | |
8db9d77b ZW |
3917 | udelay(500); |
3918 | ||
fa37d39e SP |
3919 | for (retry = 0; retry < 5; retry++) { |
3920 | reg = FDI_RX_IIR(pipe); | |
3921 | temp = I915_READ(reg); | |
3922 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3923 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3924 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3925 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3926 | break; | |
3927 | } | |
3928 | udelay(50); | |
8db9d77b | 3929 | } |
fa37d39e SP |
3930 | if (retry < 5) |
3931 | break; | |
8db9d77b ZW |
3932 | } |
3933 | if (i == 4) | |
5eddb70b | 3934 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3935 | |
3936 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3937 | } | |
3938 | ||
357555c0 | 3939 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
3940 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
3941 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 3942 | { |
4cbe4b2b | 3943 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3944 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3945 | int pipe = crtc->pipe; |
f0f59a00 VS |
3946 | i915_reg_t reg; |
3947 | u32 temp, i, j; | |
357555c0 JB |
3948 | |
3949 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3950 | for train result */ | |
3951 | reg = FDI_RX_IMR(pipe); | |
3952 | temp = I915_READ(reg); | |
3953 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3954 | temp &= ~FDI_RX_BIT_LOCK; | |
3955 | I915_WRITE(reg, temp); | |
3956 | ||
3957 | POSTING_READ(reg); | |
3958 | udelay(150); | |
3959 | ||
01a415fd DV |
3960 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3961 | I915_READ(FDI_RX_IIR(pipe))); | |
3962 | ||
139ccd3f JB |
3963 | /* Try each vswing and preemphasis setting twice before moving on */ |
3964 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3965 | /* disable first in case we need to retry */ | |
3966 | reg = FDI_TX_CTL(pipe); | |
3967 | temp = I915_READ(reg); | |
3968 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3969 | temp &= ~FDI_TX_ENABLE; | |
3970 | I915_WRITE(reg, temp); | |
357555c0 | 3971 | |
139ccd3f JB |
3972 | reg = FDI_RX_CTL(pipe); |
3973 | temp = I915_READ(reg); | |
3974 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3975 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3976 | temp &= ~FDI_RX_ENABLE; | |
3977 | I915_WRITE(reg, temp); | |
357555c0 | 3978 | |
139ccd3f | 3979 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3980 | reg = FDI_TX_CTL(pipe); |
3981 | temp = I915_READ(reg); | |
139ccd3f | 3982 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3983 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 3984 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3985 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3986 | temp |= snb_b_fdi_train_param[j/2]; |
3987 | temp |= FDI_COMPOSITE_SYNC; | |
3988 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3989 | |
139ccd3f JB |
3990 | I915_WRITE(FDI_RX_MISC(pipe), |
3991 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3992 | |
139ccd3f | 3993 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3994 | temp = I915_READ(reg); |
139ccd3f JB |
3995 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3996 | temp |= FDI_COMPOSITE_SYNC; | |
3997 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3998 | |
139ccd3f JB |
3999 | POSTING_READ(reg); |
4000 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4001 | |
139ccd3f JB |
4002 | for (i = 0; i < 4; i++) { |
4003 | reg = FDI_RX_IIR(pipe); | |
4004 | temp = I915_READ(reg); | |
4005 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4006 | |
139ccd3f JB |
4007 | if (temp & FDI_RX_BIT_LOCK || |
4008 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4009 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4010 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4011 | i); | |
4012 | break; | |
4013 | } | |
4014 | udelay(1); /* should be 0.5us */ | |
4015 | } | |
4016 | if (i == 4) { | |
4017 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4018 | continue; | |
4019 | } | |
357555c0 | 4020 | |
139ccd3f | 4021 | /* Train 2 */ |
357555c0 JB |
4022 | reg = FDI_TX_CTL(pipe); |
4023 | temp = I915_READ(reg); | |
139ccd3f JB |
4024 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4025 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4026 | I915_WRITE(reg, temp); | |
4027 | ||
4028 | reg = FDI_RX_CTL(pipe); | |
4029 | temp = I915_READ(reg); | |
4030 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4031 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4032 | I915_WRITE(reg, temp); |
4033 | ||
4034 | POSTING_READ(reg); | |
139ccd3f | 4035 | udelay(2); /* should be 1.5us */ |
357555c0 | 4036 | |
139ccd3f JB |
4037 | for (i = 0; i < 4; i++) { |
4038 | reg = FDI_RX_IIR(pipe); | |
4039 | temp = I915_READ(reg); | |
4040 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4041 | |
139ccd3f JB |
4042 | if (temp & FDI_RX_SYMBOL_LOCK || |
4043 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4044 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4045 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4046 | i); | |
4047 | goto train_done; | |
4048 | } | |
4049 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4050 | } |
139ccd3f JB |
4051 | if (i == 4) |
4052 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4053 | } |
357555c0 | 4054 | |
139ccd3f | 4055 | train_done: |
357555c0 JB |
4056 | DRM_DEBUG_KMS("FDI train done.\n"); |
4057 | } | |
4058 | ||
88cefb6c | 4059 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4060 | { |
88cefb6c | 4061 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4062 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4063 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4064 | i915_reg_t reg; |
4065 | u32 temp; | |
c64e311e | 4066 | |
c98e9dcf | 4067 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4068 | reg = FDI_RX_CTL(pipe); |
4069 | temp = I915_READ(reg); | |
627eb5a3 | 4070 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4071 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4072 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4073 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4074 | ||
4075 | POSTING_READ(reg); | |
c98e9dcf JB |
4076 | udelay(200); |
4077 | ||
4078 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4079 | temp = I915_READ(reg); |
4080 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4081 | ||
4082 | POSTING_READ(reg); | |
c98e9dcf JB |
4083 | udelay(200); |
4084 | ||
20749730 PZ |
4085 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4086 | reg = FDI_TX_CTL(pipe); | |
4087 | temp = I915_READ(reg); | |
4088 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4089 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4090 | |
20749730 PZ |
4091 | POSTING_READ(reg); |
4092 | udelay(100); | |
6be4a607 | 4093 | } |
0e23b99d JB |
4094 | } |
4095 | ||
88cefb6c DV |
4096 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4097 | { | |
4098 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4099 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4100 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4101 | i915_reg_t reg; |
4102 | u32 temp; | |
88cefb6c DV |
4103 | |
4104 | /* Switch from PCDclk to Rawclk */ | |
4105 | reg = FDI_RX_CTL(pipe); | |
4106 | temp = I915_READ(reg); | |
4107 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4108 | ||
4109 | /* Disable CPU FDI TX PLL */ | |
4110 | reg = FDI_TX_CTL(pipe); | |
4111 | temp = I915_READ(reg); | |
4112 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4113 | ||
4114 | POSTING_READ(reg); | |
4115 | udelay(100); | |
4116 | ||
4117 | reg = FDI_RX_CTL(pipe); | |
4118 | temp = I915_READ(reg); | |
4119 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4120 | ||
4121 | /* Wait for the clocks to turn off. */ | |
4122 | POSTING_READ(reg); | |
4123 | udelay(100); | |
4124 | } | |
4125 | ||
0fc932b8 JB |
4126 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4127 | { | |
4128 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4129 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4131 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4132 | i915_reg_t reg; |
4133 | u32 temp; | |
0fc932b8 JB |
4134 | |
4135 | /* disable CPU FDI tx and PCH FDI rx */ | |
4136 | reg = FDI_TX_CTL(pipe); | |
4137 | temp = I915_READ(reg); | |
4138 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4139 | POSTING_READ(reg); | |
4140 | ||
4141 | reg = FDI_RX_CTL(pipe); | |
4142 | temp = I915_READ(reg); | |
4143 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4144 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4145 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4146 | ||
4147 | POSTING_READ(reg); | |
4148 | udelay(100); | |
4149 | ||
4150 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4151 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4152 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4153 | |
4154 | /* still set train pattern 1 */ | |
4155 | reg = FDI_TX_CTL(pipe); | |
4156 | temp = I915_READ(reg); | |
4157 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4158 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4159 | I915_WRITE(reg, temp); | |
4160 | ||
4161 | reg = FDI_RX_CTL(pipe); | |
4162 | temp = I915_READ(reg); | |
6e266956 | 4163 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4164 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4165 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4166 | } else { | |
4167 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4168 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4169 | } | |
4170 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4171 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4172 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4173 | I915_WRITE(reg, temp); |
4174 | ||
4175 | POSTING_READ(reg); | |
4176 | udelay(100); | |
4177 | } | |
4178 | ||
49d73912 | 4179 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 CW |
4180 | { |
4181 | struct intel_crtc *crtc; | |
4182 | ||
4183 | /* Note that we don't need to be called with mode_config.lock here | |
4184 | * as our list of CRTC objects is static for the lifetime of the | |
4185 | * device and so cannot disappear as we iterate. Similarly, we can | |
4186 | * happily treat the predicates as racy, atomic checks as userspace | |
4187 | * cannot claim and pin a new fb without at least acquring the | |
4188 | * struct_mutex and so serialising with us. | |
4189 | */ | |
49d73912 | 4190 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
5dce5b93 CW |
4191 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4192 | continue; | |
4193 | ||
5a21b665 | 4194 | if (crtc->flip_work) |
0f0f74bc | 4195 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
5dce5b93 CW |
4196 | |
4197 | return true; | |
4198 | } | |
4199 | ||
4200 | return false; | |
4201 | } | |
4202 | ||
5a21b665 | 4203 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4204 | { |
4205 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4206 | struct intel_flip_work *work = intel_crtc->flip_work; |
4207 | ||
4208 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4209 | |
4210 | if (work->event) | |
560ce1dc | 4211 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4212 | |
4213 | drm_crtc_vblank_put(&intel_crtc->base); | |
4214 | ||
5a21b665 | 4215 | wake_up_all(&dev_priv->pending_flip_queue); |
5a21b665 DV |
4216 | trace_i915_flip_complete(intel_crtc->plane, |
4217 | work->pending_flip_obj); | |
05c41f92 AR |
4218 | |
4219 | queue_work(dev_priv->wq, &work->unpin_work); | |
d6bbafa1 CW |
4220 | } |
4221 | ||
5008e874 | 4222 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4223 | { |
0f91128d | 4224 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4225 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4226 | long ret; |
e6c3a2a6 | 4227 | |
2c10d571 | 4228 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4229 | |
4230 | ret = wait_event_interruptible_timeout( | |
4231 | dev_priv->pending_flip_queue, | |
4232 | !intel_crtc_has_pending_flip(crtc), | |
4233 | 60*HZ); | |
4234 | ||
4235 | if (ret < 0) | |
4236 | return ret; | |
4237 | ||
5a21b665 DV |
4238 | if (ret == 0) { |
4239 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4240 | struct intel_flip_work *work; | |
4241 | ||
4242 | spin_lock_irq(&dev->event_lock); | |
4243 | work = intel_crtc->flip_work; | |
4244 | if (work && !is_mmio_work(work)) { | |
4245 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4246 | page_flip_completed(intel_crtc); | |
4247 | } | |
4248 | spin_unlock_irq(&dev->event_lock); | |
4249 | } | |
5bb61643 | 4250 | |
5008e874 | 4251 | return 0; |
e6c3a2a6 CW |
4252 | } |
4253 | ||
b7076546 | 4254 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4255 | { |
4256 | u32 temp; | |
4257 | ||
4258 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4259 | ||
4260 | mutex_lock(&dev_priv->sb_lock); | |
4261 | ||
4262 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4263 | temp |= SBI_SSCCTL_DISABLE; | |
4264 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4265 | ||
4266 | mutex_unlock(&dev_priv->sb_lock); | |
4267 | } | |
4268 | ||
e615efe4 | 4269 | /* Program iCLKIP clock to the desired frequency */ |
0dcdc382 | 4270 | static void lpt_program_iclkip(struct intel_crtc *crtc) |
e615efe4 | 4271 | { |
0dcdc382 ACO |
4272 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4273 | int clock = crtc->config->base.adjusted_mode.crtc_clock; | |
e615efe4 ED |
4274 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4275 | u32 temp; | |
4276 | ||
060f02d8 | 4277 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4278 | |
64b46a06 VS |
4279 | /* The iCLK virtual clock root frequency is in MHz, |
4280 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4281 | * divisors, it is necessary to divide one by another, so we | |
4282 | * convert the virtual clock precision to KHz here for higher | |
4283 | * precision. | |
4284 | */ | |
4285 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4286 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4287 | u32 iclk_pi_range = 64; | |
64b46a06 | 4288 | u32 desired_divisor; |
e615efe4 | 4289 | |
64b46a06 VS |
4290 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4291 | clock << auxdiv); | |
4292 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4293 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4294 | |
64b46a06 VS |
4295 | /* |
4296 | * Near 20MHz is a corner case which is | |
4297 | * out of range for the 7-bit divisor | |
4298 | */ | |
4299 | if (divsel <= 0x7f) | |
4300 | break; | |
e615efe4 ED |
4301 | } |
4302 | ||
4303 | /* This should not happen with any sane values */ | |
4304 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4305 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4306 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4307 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4308 | ||
4309 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4310 | clock, |
e615efe4 ED |
4311 | auxdiv, |
4312 | divsel, | |
4313 | phasedir, | |
4314 | phaseinc); | |
4315 | ||
060f02d8 VS |
4316 | mutex_lock(&dev_priv->sb_lock); |
4317 | ||
e615efe4 | 4318 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4319 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4320 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4321 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4322 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4323 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4324 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4325 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4326 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4327 | |
4328 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4329 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4330 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4331 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4332 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4333 | |
4334 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4335 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4336 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4337 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4338 | |
060f02d8 VS |
4339 | mutex_unlock(&dev_priv->sb_lock); |
4340 | ||
e615efe4 ED |
4341 | /* Wait for initialization time */ |
4342 | udelay(24); | |
4343 | ||
4344 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4345 | } | |
4346 | ||
8802e5b6 VS |
4347 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4348 | { | |
4349 | u32 divsel, phaseinc, auxdiv; | |
4350 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4351 | u32 iclk_pi_range = 64; | |
4352 | u32 desired_divisor; | |
4353 | u32 temp; | |
4354 | ||
4355 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4356 | return 0; | |
4357 | ||
4358 | mutex_lock(&dev_priv->sb_lock); | |
4359 | ||
4360 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4361 | if (temp & SBI_SSCCTL_DISABLE) { | |
4362 | mutex_unlock(&dev_priv->sb_lock); | |
4363 | return 0; | |
4364 | } | |
4365 | ||
4366 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4367 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4368 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4369 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4370 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4371 | ||
4372 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4373 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4374 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4375 | ||
4376 | mutex_unlock(&dev_priv->sb_lock); | |
4377 | ||
4378 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4379 | ||
4380 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4381 | desired_divisor << auxdiv); | |
4382 | } | |
4383 | ||
275f01b2 DV |
4384 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4385 | enum pipe pch_transcoder) | |
4386 | { | |
4387 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4388 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4389 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4390 | |
4391 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4392 | I915_READ(HTOTAL(cpu_transcoder))); | |
4393 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4394 | I915_READ(HBLANK(cpu_transcoder))); | |
4395 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4396 | I915_READ(HSYNC(cpu_transcoder))); | |
4397 | ||
4398 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4399 | I915_READ(VTOTAL(cpu_transcoder))); | |
4400 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4401 | I915_READ(VBLANK(cpu_transcoder))); | |
4402 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4403 | I915_READ(VSYNC(cpu_transcoder))); | |
4404 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4405 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4406 | } | |
4407 | ||
003632d9 | 4408 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4409 | { |
fac5e23e | 4410 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4411 | uint32_t temp; |
4412 | ||
4413 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4414 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4415 | return; |
4416 | ||
4417 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4418 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4419 | ||
003632d9 ACO |
4420 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4421 | if (enable) | |
4422 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4423 | ||
4424 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4425 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4426 | POSTING_READ(SOUTH_CHICKEN1); | |
4427 | } | |
4428 | ||
4429 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4430 | { | |
4431 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4432 | |
4433 | switch (intel_crtc->pipe) { | |
4434 | case PIPE_A: | |
4435 | break; | |
4436 | case PIPE_B: | |
6e3c9717 | 4437 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4438 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4439 | else |
003632d9 | 4440 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4441 | |
4442 | break; | |
4443 | case PIPE_C: | |
003632d9 | 4444 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4445 | |
4446 | break; | |
4447 | default: | |
4448 | BUG(); | |
4449 | } | |
4450 | } | |
4451 | ||
c48b5305 VS |
4452 | /* Return which DP Port should be selected for Transcoder DP control */ |
4453 | static enum port | |
4cbe4b2b | 4454 | intel_trans_dp_port_sel(struct intel_crtc *crtc) |
c48b5305 | 4455 | { |
4cbe4b2b | 4456 | struct drm_device *dev = crtc->base.dev; |
c48b5305 VS |
4457 | struct intel_encoder *encoder; |
4458 | ||
4cbe4b2b | 4459 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
cca0502b | 4460 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4461 | encoder->type == INTEL_OUTPUT_EDP) |
4462 | return enc_to_dig_port(&encoder->base)->port; | |
4463 | } | |
4464 | ||
4465 | return -1; | |
4466 | } | |
4467 | ||
f67a559d JB |
4468 | /* |
4469 | * Enable PCH resources required for PCH ports: | |
4470 | * - PCH PLLs | |
4471 | * - FDI training & RX/TX | |
4472 | * - update transcoder timings | |
4473 | * - DP transcoding bits | |
4474 | * - transcoder | |
4475 | */ | |
2ce42273 | 4476 | static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) |
0e23b99d | 4477 | { |
2ce42273 | 4478 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
4cbe4b2b | 4479 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4480 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4481 | int pipe = crtc->pipe; |
f0f59a00 | 4482 | u32 temp; |
2c07245f | 4483 | |
ab9412ba | 4484 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4485 | |
fd6b8f43 | 4486 | if (IS_IVYBRIDGE(dev_priv)) |
4cbe4b2b | 4487 | ivybridge_update_fdi_bc_bifurcation(crtc); |
1fbc0d78 | 4488 | |
cd986abb DV |
4489 | /* Write the TU size bits before fdi link training, so that error |
4490 | * detection works. */ | |
4491 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4492 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4493 | ||
c98e9dcf | 4494 | /* For PCH output, training FDI link */ |
dc4a1094 | 4495 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 4496 | |
3ad8a208 DV |
4497 | /* We need to program the right clock selection before writing the pixel |
4498 | * mutliplier into the DPLL. */ | |
6e266956 | 4499 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4500 | u32 sel; |
4b645f14 | 4501 | |
c98e9dcf | 4502 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4503 | temp |= TRANS_DPLL_ENABLE(pipe); |
4504 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 4505 | if (crtc_state->shared_dpll == |
8106ddbd | 4506 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
4507 | temp |= sel; |
4508 | else | |
4509 | temp &= ~sel; | |
c98e9dcf | 4510 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4511 | } |
5eddb70b | 4512 | |
3ad8a208 DV |
4513 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4514 | * transcoder, and we actually should do this to not upset any PCH | |
4515 | * transcoder that already use the clock when we share it. | |
4516 | * | |
4517 | * Note that enable_shared_dpll tries to do the right thing, but | |
4518 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4519 | * the right LVDS enable sequence. */ | |
4cbe4b2b | 4520 | intel_enable_shared_dpll(crtc); |
3ad8a208 | 4521 | |
d9b6cb56 JB |
4522 | /* set transcoder timing, panel must allow it */ |
4523 | assert_panel_unlocked(dev_priv, pipe); | |
4cbe4b2b | 4524 | ironlake_pch_transcoder_set_timings(crtc, pipe); |
8db9d77b | 4525 | |
303b81e0 | 4526 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4527 | |
c98e9dcf | 4528 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 4529 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 4530 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 4531 | const struct drm_display_mode *adjusted_mode = |
2ce42273 | 4532 | &crtc_state->base.adjusted_mode; |
dfd07d72 | 4533 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4534 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4535 | temp = I915_READ(reg); |
4536 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4537 | TRANS_DP_SYNC_MASK | |
4538 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4539 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4540 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4541 | |
9c4edaee | 4542 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4543 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4544 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4545 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4546 | |
4547 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4548 | case PORT_B: |
5eddb70b | 4549 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4550 | break; |
c48b5305 | 4551 | case PORT_C: |
5eddb70b | 4552 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4553 | break; |
c48b5305 | 4554 | case PORT_D: |
5eddb70b | 4555 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4556 | break; |
4557 | default: | |
e95d41e1 | 4558 | BUG(); |
32f9d658 | 4559 | } |
2c07245f | 4560 | |
5eddb70b | 4561 | I915_WRITE(reg, temp); |
6be4a607 | 4562 | } |
b52eb4dc | 4563 | |
b8a4f404 | 4564 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4565 | } |
4566 | ||
2ce42273 | 4567 | static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 4568 | { |
2ce42273 | 4569 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
0dcdc382 | 4570 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 4571 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 4572 | |
ab9412ba | 4573 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4574 | |
8c52b5e8 | 4575 | lpt_program_iclkip(crtc); |
1507e5bd | 4576 | |
0540e488 | 4577 | /* Set transcoder timing. */ |
0dcdc382 | 4578 | ironlake_pch_transcoder_set_timings(crtc, PIPE_A); |
1507e5bd | 4579 | |
937bb610 | 4580 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4581 | } |
4582 | ||
a1520318 | 4583 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4584 | { |
fac5e23e | 4585 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4586 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4587 | u32 temp; |
4588 | ||
4589 | temp = I915_READ(dslreg); | |
4590 | udelay(500); | |
4591 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4592 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4593 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4594 | } |
4595 | } | |
4596 | ||
86adf9d7 ML |
4597 | static int |
4598 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4599 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4600 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4601 | { |
86adf9d7 ML |
4602 | struct intel_crtc_scaler_state *scaler_state = |
4603 | &crtc_state->scaler_state; | |
4604 | struct intel_crtc *intel_crtc = | |
4605 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4606 | int need_scaling; |
6156a456 | 4607 | |
bd2ef25d | 4608 | need_scaling = drm_rotation_90_or_270(rotation) ? |
6156a456 CK |
4609 | (src_h != dst_w || src_w != dst_h): |
4610 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4611 | |
4612 | /* | |
4613 | * if plane is being disabled or scaler is no more required or force detach | |
4614 | * - free scaler binded to this plane/crtc | |
4615 | * - in order to do this, update crtc->scaler_usage | |
4616 | * | |
4617 | * Here scaler state in crtc_state is set free so that | |
4618 | * scaler can be assigned to other user. Actual register | |
4619 | * update to free the scaler is done in plane/panel-fit programming. | |
4620 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4621 | */ | |
86adf9d7 | 4622 | if (force_detach || !need_scaling) { |
a1b2278e | 4623 | if (*scaler_id >= 0) { |
86adf9d7 | 4624 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4625 | scaler_state->scalers[*scaler_id].in_use = 0; |
4626 | ||
86adf9d7 ML |
4627 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4628 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4629 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4630 | scaler_state->scaler_users); |
4631 | *scaler_id = -1; | |
4632 | } | |
4633 | return 0; | |
4634 | } | |
4635 | ||
4636 | /* range checks */ | |
4637 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4638 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4639 | ||
4640 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4641 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4642 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4643 | "size is out of scaler range\n", |
86adf9d7 | 4644 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4645 | return -EINVAL; |
4646 | } | |
4647 | ||
86adf9d7 ML |
4648 | /* mark this plane as a scaler user in crtc_state */ |
4649 | scaler_state->scaler_users |= (1 << scaler_user); | |
4650 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4651 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4652 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4653 | scaler_state->scaler_users); | |
4654 | ||
4655 | return 0; | |
4656 | } | |
4657 | ||
4658 | /** | |
4659 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4660 | * | |
4661 | * @state: crtc's scaler state | |
86adf9d7 ML |
4662 | * |
4663 | * Return | |
4664 | * 0 - scaler_usage updated successfully | |
4665 | * error - requested scaling cannot be supported or other error condition | |
4666 | */ | |
e435d6e5 | 4667 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4668 | { |
7c5f93b0 | 4669 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4670 | |
e435d6e5 | 4671 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
31ad61e4 | 4672 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
86adf9d7 | 4673 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4674 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4675 | } |
4676 | ||
4677 | /** | |
4678 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4679 | * | |
4680 | * @state: crtc's scaler state | |
86adf9d7 ML |
4681 | * @plane_state: atomic plane state to update |
4682 | * | |
4683 | * Return | |
4684 | * 0 - scaler_usage updated successfully | |
4685 | * error - requested scaling cannot be supported or other error condition | |
4686 | */ | |
da20eabd ML |
4687 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4688 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4689 | { |
4690 | ||
da20eabd ML |
4691 | struct intel_plane *intel_plane = |
4692 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4693 | struct drm_framebuffer *fb = plane_state->base.fb; |
4694 | int ret; | |
4695 | ||
936e71e3 | 4696 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4697 | |
86adf9d7 ML |
4698 | ret = skl_update_scaler(crtc_state, force_detach, |
4699 | drm_plane_index(&intel_plane->base), | |
4700 | &plane_state->scaler_id, | |
4701 | plane_state->base.rotation, | |
936e71e3 VS |
4702 | drm_rect_width(&plane_state->base.src) >> 16, |
4703 | drm_rect_height(&plane_state->base.src) >> 16, | |
4704 | drm_rect_width(&plane_state->base.dst), | |
4705 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4706 | |
4707 | if (ret || plane_state->scaler_id < 0) | |
4708 | return ret; | |
4709 | ||
a1b2278e | 4710 | /* check colorkey */ |
818ed961 | 4711 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4712 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4713 | intel_plane->base.base.id, | |
4714 | intel_plane->base.name); | |
a1b2278e CK |
4715 | return -EINVAL; |
4716 | } | |
4717 | ||
4718 | /* Check src format */ | |
438b74a5 | 4719 | switch (fb->format->format) { |
86adf9d7 ML |
4720 | case DRM_FORMAT_RGB565: |
4721 | case DRM_FORMAT_XBGR8888: | |
4722 | case DRM_FORMAT_XRGB8888: | |
4723 | case DRM_FORMAT_ABGR8888: | |
4724 | case DRM_FORMAT_ARGB8888: | |
4725 | case DRM_FORMAT_XRGB2101010: | |
4726 | case DRM_FORMAT_XBGR2101010: | |
4727 | case DRM_FORMAT_YUYV: | |
4728 | case DRM_FORMAT_YVYU: | |
4729 | case DRM_FORMAT_UYVY: | |
4730 | case DRM_FORMAT_VYUY: | |
4731 | break; | |
4732 | default: | |
72660ce0 VS |
4733 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4734 | intel_plane->base.base.id, intel_plane->base.name, | |
438b74a5 | 4735 | fb->base.id, fb->format->format); |
86adf9d7 | 4736 | return -EINVAL; |
a1b2278e CK |
4737 | } |
4738 | ||
a1b2278e CK |
4739 | return 0; |
4740 | } | |
4741 | ||
e435d6e5 ML |
4742 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4743 | { | |
4744 | int i; | |
4745 | ||
4746 | for (i = 0; i < crtc->num_scalers; i++) | |
4747 | skl_detach_scaler(crtc, i); | |
4748 | } | |
4749 | ||
4750 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4751 | { |
4752 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4753 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4754 | int pipe = crtc->pipe; |
a1b2278e CK |
4755 | struct intel_crtc_scaler_state *scaler_state = |
4756 | &crtc->config->scaler_state; | |
4757 | ||
6e3c9717 | 4758 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4759 | int id; |
4760 | ||
c3f8ad57 | 4761 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) |
a1b2278e | 4762 | return; |
a1b2278e CK |
4763 | |
4764 | id = scaler_state->scaler_id; | |
4765 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4766 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4767 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4768 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4769 | } |
4770 | } | |
4771 | ||
b074cec8 JB |
4772 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4773 | { | |
4774 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4775 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4776 | int pipe = crtc->pipe; |
4777 | ||
6e3c9717 | 4778 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4779 | /* Force use of hard-coded filter coefficients |
4780 | * as some pre-programmed values are broken, | |
4781 | * e.g. x201. | |
4782 | */ | |
fd6b8f43 | 4783 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4784 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4785 | PF_PIPE_SEL_IVB(pipe)); | |
4786 | else | |
4787 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4788 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4789 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4790 | } |
4791 | } | |
4792 | ||
20bc8673 | 4793 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4794 | { |
cea165c3 | 4795 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4796 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4797 | |
6e3c9717 | 4798 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4799 | return; |
4800 | ||
307e4498 ML |
4801 | /* |
4802 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4803 | * This function is called from post_plane_update, which is run after | |
4804 | * a vblank wait. | |
4805 | */ | |
cea165c3 | 4806 | |
d77e4531 | 4807 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4808 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4809 | mutex_lock(&dev_priv->rps.hw_lock); |
4810 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4811 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4812 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4813 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4814 | * mailbox." Moreover, the mailbox may return a bogus state, |
4815 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4816 | */ |
4817 | } else { | |
4818 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4819 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4820 | * is essentially intel_wait_for_vblank. If we don't have this | |
4821 | * and don't wait for vblanks until the end of crtc_enable, then | |
4822 | * the HW state readout code will complain that the expected | |
4823 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4824 | if (intel_wait_for_register(dev_priv, |
4825 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4826 | 50)) | |
2a114cc1 BW |
4827 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4828 | } | |
d77e4531 PZ |
4829 | } |
4830 | ||
20bc8673 | 4831 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4832 | { |
4833 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4834 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4835 | |
6e3c9717 | 4836 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4837 | return; |
4838 | ||
4839 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4840 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4841 | mutex_lock(&dev_priv->rps.hw_lock); |
4842 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4843 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4844 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4845 | if (intel_wait_for_register(dev_priv, |
4846 | IPS_CTL, IPS_ENABLE, 0, | |
4847 | 42)) | |
23d0b130 | 4848 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4849 | } else { |
2a114cc1 | 4850 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4851 | POSTING_READ(IPS_CTL); |
4852 | } | |
d77e4531 PZ |
4853 | |
4854 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4855 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4856 | } |
4857 | ||
7cac945f | 4858 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4859 | { |
7cac945f | 4860 | if (intel_crtc->overlay) { |
d3eedb1a | 4861 | struct drm_device *dev = intel_crtc->base.dev; |
d3eedb1a VS |
4862 | |
4863 | mutex_lock(&dev->struct_mutex); | |
d3eedb1a | 4864 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
d3eedb1a VS |
4865 | mutex_unlock(&dev->struct_mutex); |
4866 | } | |
4867 | ||
4868 | /* Let userspace switch the overlay on again. In most cases userspace | |
4869 | * has to recompute where to put it anyway. | |
4870 | */ | |
4871 | } | |
4872 | ||
87d4300a ML |
4873 | /** |
4874 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4875 | * @crtc: the CRTC whose primary plane was just enabled | |
4876 | * | |
4877 | * Performs potentially sleeping operations that must be done after the primary | |
4878 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4879 | * called due to an explicit primary plane update, or due to an implicit | |
4880 | * re-enable that is caused when a sprite plane is updated to no longer | |
4881 | * completely hide the primary plane. | |
4882 | */ | |
4883 | static void | |
4884 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4885 | { |
4886 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4887 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4888 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4889 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4890 | |
87d4300a ML |
4891 | /* |
4892 | * FIXME IPS should be fine as long as one plane is | |
4893 | * enabled, but in practice it seems to have problems | |
4894 | * when going from primary only to sprite only and vice | |
4895 | * versa. | |
4896 | */ | |
a5c4d7bc VS |
4897 | hsw_enable_ips(intel_crtc); |
4898 | ||
f99d7069 | 4899 | /* |
87d4300a ML |
4900 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4901 | * So don't enable underrun reporting before at least some planes | |
4902 | * are enabled. | |
4903 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4904 | * but leave the pipe running. | |
f99d7069 | 4905 | */ |
5db94019 | 4906 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4907 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4908 | ||
aca7b684 VS |
4909 | /* Underruns don't always raise interrupts, so check manually. */ |
4910 | intel_check_cpu_fifo_underruns(dev_priv); | |
4911 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4912 | } |
4913 | ||
2622a081 | 4914 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4915 | static void |
4916 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4917 | { |
4918 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4919 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4920 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4921 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4922 | |
87d4300a ML |
4923 | /* |
4924 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4925 | * So diasble underrun reporting before all the planes get disabled. | |
4926 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4927 | * but leave the pipe running. | |
4928 | */ | |
5db94019 | 4929 | if (IS_GEN2(dev_priv)) |
87d4300a | 4930 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 4931 | |
2622a081 VS |
4932 | /* |
4933 | * FIXME IPS should be fine as long as one plane is | |
4934 | * enabled, but in practice it seems to have problems | |
4935 | * when going from primary only to sprite only and vice | |
4936 | * versa. | |
4937 | */ | |
4938 | hsw_disable_ips(intel_crtc); | |
4939 | } | |
4940 | ||
4941 | /* FIXME get rid of this and use pre_plane_update */ | |
4942 | static void | |
4943 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4944 | { | |
4945 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4946 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4948 | int pipe = intel_crtc->pipe; | |
4949 | ||
4950 | intel_pre_disable_primary(crtc); | |
4951 | ||
87d4300a ML |
4952 | /* |
4953 | * Vblank time updates from the shadow to live plane control register | |
4954 | * are blocked if the memory self-refresh mode is active at that | |
4955 | * moment. So to make sure the plane gets truly disabled, disable | |
4956 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4957 | * will be checked/applied by the HW only at the next frame start | |
4958 | * event which is after the vblank start event, so we need to have a | |
4959 | * wait-for-vblank between disabling the plane and the pipe. | |
4960 | */ | |
11a85d6a VS |
4961 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4962 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 4963 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
4964 | } |
4965 | ||
5a21b665 DV |
4966 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4967 | { | |
4968 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4969 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4970 | struct intel_crtc_state *pipe_config = | |
4971 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
4972 | struct drm_plane *primary = crtc->base.primary; |
4973 | struct drm_plane_state *old_pri_state = | |
4974 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4975 | ||
5748b6a1 | 4976 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 | 4977 | |
5a21b665 | 4978 | if (pipe_config->update_wm_post && pipe_config->base.active) |
432081bc | 4979 | intel_update_watermarks(crtc); |
5a21b665 DV |
4980 | |
4981 | if (old_pri_state) { | |
4982 | struct intel_plane_state *primary_state = | |
4983 | to_intel_plane_state(primary->state); | |
4984 | struct intel_plane_state *old_primary_state = | |
4985 | to_intel_plane_state(old_pri_state); | |
4986 | ||
4987 | intel_fbc_post_update(crtc); | |
4988 | ||
936e71e3 | 4989 | if (primary_state->base.visible && |
5a21b665 | 4990 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 4991 | !old_primary_state->base.visible)) |
5a21b665 DV |
4992 | intel_post_enable_primary(&crtc->base); |
4993 | } | |
4994 | } | |
4995 | ||
aa5e9b47 ML |
4996 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, |
4997 | struct intel_crtc_state *pipe_config) | |
ac21b225 | 4998 | { |
5c74cd73 | 4999 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5000 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5001 | struct drm_i915_private *dev_priv = to_i915(dev); |
5c74cd73 ML |
5002 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5003 | struct drm_plane *primary = crtc->base.primary; | |
5004 | struct drm_plane_state *old_pri_state = | |
5005 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5006 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5007 | struct intel_atomic_state *old_intel_state = |
5008 | to_intel_atomic_state(old_state); | |
ac21b225 | 5009 | |
5c74cd73 ML |
5010 | if (old_pri_state) { |
5011 | struct intel_plane_state *primary_state = | |
5012 | to_intel_plane_state(primary->state); | |
5013 | struct intel_plane_state *old_primary_state = | |
5014 | to_intel_plane_state(old_pri_state); | |
5015 | ||
faf68d92 | 5016 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5017 | |
936e71e3 VS |
5018 | if (old_primary_state->base.visible && |
5019 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5020 | intel_pre_disable_primary(&crtc->base); |
5021 | } | |
852eb00d | 5022 | |
5eeb798b VS |
5023 | /* |
5024 | * Vblank time updates from the shadow to live plane control register | |
5025 | * are blocked if the memory self-refresh mode is active at that | |
5026 | * moment. So to make sure the plane gets truly disabled, disable | |
5027 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5028 | * will be checked/applied by the HW only at the next frame start | |
5029 | * event which is after the vblank start event, so we need to have a | |
5030 | * wait-for-vblank between disabling the plane and the pipe. | |
5031 | */ | |
5032 | if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active && | |
5033 | pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) | |
5034 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
92826fcd | 5035 | |
ed4a6a7c MR |
5036 | /* |
5037 | * IVB workaround: must disable low power watermarks for at least | |
5038 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5039 | * when scaling is disabled. | |
5040 | * | |
5041 | * WaCxSRDisabledForSpriteScaling:ivb | |
5042 | */ | |
ddd2b792 | 5043 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5044 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5045 | |
5046 | /* | |
5047 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5048 | * watermark programming here. | |
5049 | */ | |
5050 | if (needs_modeset(&pipe_config->base)) | |
5051 | return; | |
5052 | ||
5053 | /* | |
5054 | * For platforms that support atomic watermarks, program the | |
5055 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5056 | * will be the intermediate values that are safe for both pre- and | |
5057 | * post- vblank; when vblank happens, the 'active' values will be set | |
5058 | * to the final 'target' values and we'll do this again to get the | |
5059 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5060 | * will be the final target values which will get automatically latched | |
5061 | * at vblank time; no further programming will be necessary. | |
5062 | * | |
5063 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5064 | * we'll continue to update watermarks the old way, if flags tell | |
5065 | * us to. | |
5066 | */ | |
5067 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5068 | dev_priv->display.initial_watermarks(old_intel_state, |
5069 | pipe_config); | |
caed361d | 5070 | else if (pipe_config->update_wm_pre) |
432081bc | 5071 | intel_update_watermarks(crtc); |
ac21b225 ML |
5072 | } |
5073 | ||
d032ffa0 | 5074 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5075 | { |
5076 | struct drm_device *dev = crtc->dev; | |
5077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5078 | struct drm_plane *p; |
87d4300a ML |
5079 | int pipe = intel_crtc->pipe; |
5080 | ||
7cac945f | 5081 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5082 | |
d032ffa0 ML |
5083 | drm_for_each_plane_mask(p, dev, plane_mask) |
5084 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5085 | |
f99d7069 DV |
5086 | /* |
5087 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5088 | * to compute the mask of flip planes precisely. For the time being | |
5089 | * consider this a flip to a NULL plane. | |
5090 | */ | |
5748b6a1 | 5091 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5092 | } |
5093 | ||
fb1c98b1 | 5094 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5095 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5096 | struct drm_atomic_state *old_state) |
5097 | { | |
aa5e9b47 | 5098 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5099 | struct drm_connector *conn; |
5100 | int i; | |
5101 | ||
aa5e9b47 | 5102 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5103 | struct intel_encoder *encoder = |
5104 | to_intel_encoder(conn_state->best_encoder); | |
5105 | ||
5106 | if (conn_state->crtc != crtc) | |
5107 | continue; | |
5108 | ||
5109 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5110 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5111 | } |
5112 | } | |
5113 | ||
5114 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5115 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5116 | struct drm_atomic_state *old_state) |
5117 | { | |
aa5e9b47 | 5118 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5119 | struct drm_connector *conn; |
5120 | int i; | |
5121 | ||
aa5e9b47 | 5122 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5123 | struct intel_encoder *encoder = |
5124 | to_intel_encoder(conn_state->best_encoder); | |
5125 | ||
5126 | if (conn_state->crtc != crtc) | |
5127 | continue; | |
5128 | ||
5129 | if (encoder->pre_enable) | |
fd6bbda9 | 5130 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5131 | } |
5132 | } | |
5133 | ||
5134 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5135 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5136 | struct drm_atomic_state *old_state) |
5137 | { | |
aa5e9b47 | 5138 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5139 | struct drm_connector *conn; |
5140 | int i; | |
5141 | ||
aa5e9b47 | 5142 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5143 | struct intel_encoder *encoder = |
5144 | to_intel_encoder(conn_state->best_encoder); | |
5145 | ||
5146 | if (conn_state->crtc != crtc) | |
5147 | continue; | |
5148 | ||
fd6bbda9 | 5149 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5150 | intel_opregion_notify_encoder(encoder, true); |
5151 | } | |
5152 | } | |
5153 | ||
5154 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5155 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5156 | struct drm_atomic_state *old_state) |
5157 | { | |
5158 | struct drm_connector_state *old_conn_state; | |
5159 | struct drm_connector *conn; | |
5160 | int i; | |
5161 | ||
aa5e9b47 | 5162 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5163 | struct intel_encoder *encoder = |
5164 | to_intel_encoder(old_conn_state->best_encoder); | |
5165 | ||
5166 | if (old_conn_state->crtc != crtc) | |
5167 | continue; | |
5168 | ||
5169 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5170 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5171 | } |
5172 | } | |
5173 | ||
5174 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5175 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5176 | struct drm_atomic_state *old_state) |
5177 | { | |
5178 | struct drm_connector_state *old_conn_state; | |
5179 | struct drm_connector *conn; | |
5180 | int i; | |
5181 | ||
aa5e9b47 | 5182 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5183 | struct intel_encoder *encoder = |
5184 | to_intel_encoder(old_conn_state->best_encoder); | |
5185 | ||
5186 | if (old_conn_state->crtc != crtc) | |
5187 | continue; | |
5188 | ||
5189 | if (encoder->post_disable) | |
fd6bbda9 | 5190 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5191 | } |
5192 | } | |
5193 | ||
5194 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5195 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5196 | struct drm_atomic_state *old_state) |
5197 | { | |
5198 | struct drm_connector_state *old_conn_state; | |
5199 | struct drm_connector *conn; | |
5200 | int i; | |
5201 | ||
aa5e9b47 | 5202 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5203 | struct intel_encoder *encoder = |
5204 | to_intel_encoder(old_conn_state->best_encoder); | |
5205 | ||
5206 | if (old_conn_state->crtc != crtc) | |
5207 | continue; | |
5208 | ||
5209 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5210 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5211 | } |
5212 | } | |
5213 | ||
4a806558 ML |
5214 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5215 | struct drm_atomic_state *old_state) | |
f67a559d | 5216 | { |
4a806558 | 5217 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5218 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5219 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5220 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5221 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5222 | struct intel_atomic_state *old_intel_state = |
5223 | to_intel_atomic_state(old_state); | |
f67a559d | 5224 | |
53d9f4e9 | 5225 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5226 | return; |
5227 | ||
b2c0593a VS |
5228 | /* |
5229 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5230 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5231 | * | |
5232 | * On ILK we get an occasional spurious CPU pipe underruns | |
5233 | * between eDP port A enable and vdd enable. Also PCH port | |
5234 | * enable seems to result in the occasional CPU pipe underrun. | |
5235 | * | |
5236 | * Spurious PCH underruns also occur during PCH enabling. | |
5237 | */ | |
5238 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5239 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5240 | if (intel_crtc->config->has_pch_encoder) |
5241 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5242 | ||
6e3c9717 | 5243 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5244 | intel_prepare_shared_dpll(intel_crtc); |
5245 | ||
37a5650b | 5246 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5247 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5248 | |
5249 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5250 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5251 | |
6e3c9717 | 5252 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5253 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5254 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5255 | } |
5256 | ||
5257 | ironlake_set_pipeconf(crtc); | |
5258 | ||
f67a559d | 5259 | intel_crtc->active = true; |
8664281b | 5260 | |
fd6bbda9 | 5261 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5262 | |
6e3c9717 | 5263 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5264 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5265 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5266 | * enabling. */ | |
88cefb6c | 5267 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5268 | } else { |
5269 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5270 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5271 | } | |
f67a559d | 5272 | |
b074cec8 | 5273 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5274 | |
9c54c0dd JB |
5275 | /* |
5276 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5277 | * clocks enabled | |
5278 | */ | |
b95c5321 | 5279 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5280 | |
1d5bf5d9 | 5281 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5282 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5283 | intel_enable_pipe(intel_crtc); |
f67a559d | 5284 | |
6e3c9717 | 5285 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5286 | ironlake_pch_enable(pipe_config); |
c98e9dcf | 5287 | |
f9b61ff6 DV |
5288 | assert_vblank_disabled(crtc); |
5289 | drm_crtc_vblank_on(crtc); | |
5290 | ||
fd6bbda9 | 5291 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5292 | |
6e266956 | 5293 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5294 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5295 | |
5296 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5297 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5298 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5299 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5300 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5301 | } |
5302 | ||
42db64ef PZ |
5303 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5304 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5305 | { | |
50a0bc90 | 5306 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5307 | } |
5308 | ||
4a806558 ML |
5309 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5310 | struct drm_atomic_state *old_state) | |
4f771f10 | 5311 | { |
4a806558 | 5312 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5313 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5314 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5315 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5316 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5317 | struct intel_atomic_state *old_intel_state = |
5318 | to_intel_atomic_state(old_state); | |
4f771f10 | 5319 | |
53d9f4e9 | 5320 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5321 | return; |
5322 | ||
81b088ca VS |
5323 | if (intel_crtc->config->has_pch_encoder) |
5324 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5325 | false); | |
5326 | ||
fd6bbda9 | 5327 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5328 | |
8106ddbd | 5329 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5330 | intel_enable_shared_dpll(intel_crtc); |
5331 | ||
37a5650b | 5332 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5333 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5334 | |
d7edc4e5 | 5335 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5336 | intel_set_pipe_timings(intel_crtc); |
5337 | ||
bc58be60 | 5338 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5339 | |
4d1de975 JN |
5340 | if (cpu_transcoder != TRANSCODER_EDP && |
5341 | !transcoder_is_dsi(cpu_transcoder)) { | |
5342 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5343 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5344 | } |
5345 | ||
6e3c9717 | 5346 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5347 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5348 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5349 | } |
5350 | ||
d7edc4e5 | 5351 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5352 | haswell_set_pipeconf(crtc); |
5353 | ||
391bf048 | 5354 | haswell_set_pipemisc(crtc); |
229fca97 | 5355 | |
b95c5321 | 5356 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5357 | |
4f771f10 | 5358 | intel_crtc->active = true; |
8664281b | 5359 | |
6b698516 DV |
5360 | if (intel_crtc->config->has_pch_encoder) |
5361 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5362 | else | |
5363 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5364 | ||
fd6bbda9 | 5365 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5366 | |
d2d65408 | 5367 | if (intel_crtc->config->has_pch_encoder) |
dc4a1094 | 5368 | dev_priv->display.fdi_link_train(intel_crtc, pipe_config); |
4fe9467d | 5369 | |
d7edc4e5 | 5370 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5371 | intel_ddi_enable_pipe_clock(pipe_config); |
4f771f10 | 5372 | |
6315b5d3 | 5373 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5374 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5375 | else |
1c132b44 | 5376 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5377 | |
5378 | /* | |
5379 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5380 | * clocks enabled | |
5381 | */ | |
b95c5321 | 5382 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5383 | |
3dc38eea | 5384 | intel_ddi_set_pipe_settings(pipe_config); |
d7edc4e5 | 5385 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5386 | intel_ddi_enable_transcoder_func(pipe_config); |
4f771f10 | 5387 | |
1d5bf5d9 | 5388 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5389 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5390 | |
5391 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5392 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5393 | intel_enable_pipe(intel_crtc); |
42db64ef | 5394 | |
6e3c9717 | 5395 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5396 | lpt_pch_enable(pipe_config); |
4f771f10 | 5397 | |
0037071d | 5398 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5399 | intel_ddi_set_vc_payload_alloc(pipe_config, true); |
0e32b39c | 5400 | |
f9b61ff6 DV |
5401 | assert_vblank_disabled(crtc); |
5402 | drm_crtc_vblank_on(crtc); | |
5403 | ||
fd6bbda9 | 5404 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5405 | |
6b698516 | 5406 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5407 | intel_wait_for_vblank(dev_priv, pipe); |
5408 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5409 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
d2d65408 VS |
5410 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5411 | true); | |
6b698516 | 5412 | } |
d2d65408 | 5413 | |
e4916946 PZ |
5414 | /* If we change the relative order between pipe/planes enabling, we need |
5415 | * to change the workaround. */ | |
99d736a2 | 5416 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5417 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5418 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5419 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5420 | } |
4f771f10 PZ |
5421 | } |
5422 | ||
bfd16b2a | 5423 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5424 | { |
5425 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5426 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5427 | int pipe = crtc->pipe; |
5428 | ||
5429 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5430 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5431 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5432 | I915_WRITE(PF_CTL(pipe), 0); |
5433 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5434 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5435 | } | |
5436 | } | |
5437 | ||
4a806558 ML |
5438 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5439 | struct drm_atomic_state *old_state) | |
6be4a607 | 5440 | { |
4a806558 | 5441 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5442 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5443 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5444 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5445 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5446 | |
b2c0593a VS |
5447 | /* |
5448 | * Sometimes spurious CPU pipe underruns happen when the | |
5449 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5450 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5451 | */ | |
5452 | if (intel_crtc->config->has_pch_encoder) { | |
5453 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5454 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5455 | } |
37ca8d4c | 5456 | |
fd6bbda9 | 5457 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5458 | |
f9b61ff6 DV |
5459 | drm_crtc_vblank_off(crtc); |
5460 | assert_vblank_disabled(crtc); | |
5461 | ||
575f7ab7 | 5462 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5463 | |
bfd16b2a | 5464 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5465 | |
b2c0593a | 5466 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5467 | ironlake_fdi_disable(crtc); |
5468 | ||
fd6bbda9 | 5469 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5470 | |
6e3c9717 | 5471 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5472 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5473 | |
6e266956 | 5474 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5475 | i915_reg_t reg; |
5476 | u32 temp; | |
5477 | ||
d925c59a DV |
5478 | /* disable TRANS_DP_CTL */ |
5479 | reg = TRANS_DP_CTL(pipe); | |
5480 | temp = I915_READ(reg); | |
5481 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5482 | TRANS_DP_PORT_SEL_MASK); | |
5483 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5484 | I915_WRITE(reg, temp); | |
5485 | ||
5486 | /* disable DPLL_SEL */ | |
5487 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5488 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5489 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5490 | } |
e3421a18 | 5491 | |
d925c59a DV |
5492 | ironlake_fdi_pll_disable(intel_crtc); |
5493 | } | |
81b088ca | 5494 | |
b2c0593a | 5495 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5496 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5497 | } |
1b3c7a47 | 5498 | |
4a806558 ML |
5499 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5500 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5501 | { |
4a806558 | 5502 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5503 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5505 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5506 | |
d2d65408 VS |
5507 | if (intel_crtc->config->has_pch_encoder) |
5508 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5509 | false); | |
5510 | ||
fd6bbda9 | 5511 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5512 | |
f9b61ff6 DV |
5513 | drm_crtc_vblank_off(crtc); |
5514 | assert_vblank_disabled(crtc); | |
5515 | ||
4d1de975 | 5516 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5517 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5518 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5519 | |
0037071d | 5520 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5521 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); |
a4bf214f | 5522 | |
d7edc4e5 | 5523 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5524 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5525 | |
6315b5d3 | 5526 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5527 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5528 | else |
bfd16b2a | 5529 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5530 | |
d7edc4e5 | 5531 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5532 | intel_ddi_disable_pipe_clock(intel_crtc->config); |
4f771f10 | 5533 | |
fd6bbda9 | 5534 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5535 | |
b7076546 | 5536 | if (old_crtc_state->has_pch_encoder) |
81b088ca VS |
5537 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5538 | true); | |
4f771f10 PZ |
5539 | } |
5540 | ||
2dd24552 JB |
5541 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5542 | { | |
5543 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5544 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5545 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5546 | |
681a8504 | 5547 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5548 | return; |
5549 | ||
2dd24552 | 5550 | /* |
c0b03411 DV |
5551 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5552 | * according to register description and PRM. | |
2dd24552 | 5553 | */ |
c0b03411 DV |
5554 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5555 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5556 | |
b074cec8 JB |
5557 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5558 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5559 | |
5560 | /* Border color in case we don't scale up to the full screen. Black by | |
5561 | * default, change to something else for debugging. */ | |
5562 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5563 | } |
5564 | ||
79f255a0 | 5565 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
5566 | { |
5567 | switch (port) { | |
5568 | case PORT_A: | |
6331a704 | 5569 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5570 | case PORT_B: |
6331a704 | 5571 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5572 | case PORT_C: |
6331a704 | 5573 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5574 | case PORT_D: |
6331a704 | 5575 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5576 | case PORT_E: |
6331a704 | 5577 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5578 | default: |
b9fec167 | 5579 | MISSING_CASE(port); |
d05410f9 DA |
5580 | return POWER_DOMAIN_PORT_OTHER; |
5581 | } | |
5582 | } | |
5583 | ||
d8fc70b7 ACO |
5584 | static u64 get_crtc_power_domains(struct drm_crtc *crtc, |
5585 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5586 | { |
319be8ae | 5587 | struct drm_device *dev = crtc->dev; |
37255d8d | 5588 | struct drm_i915_private *dev_priv = to_i915(dev); |
74bff5f9 | 5589 | struct drm_encoder *encoder; |
319be8ae ID |
5590 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5591 | enum pipe pipe = intel_crtc->pipe; | |
d8fc70b7 | 5592 | u64 mask; |
74bff5f9 | 5593 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5594 | |
74bff5f9 | 5595 | if (!crtc_state->base.active) |
292b990e ML |
5596 | return 0; |
5597 | ||
77d22dca ID |
5598 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5599 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5600 | if (crtc_state->pch_pfit.enabled || |
5601 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 5602 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 5603 | |
74bff5f9 ML |
5604 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5605 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5606 | ||
79f255a0 | 5607 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 5608 | } |
319be8ae | 5609 | |
37255d8d ML |
5610 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
5611 | mask |= BIT(POWER_DOMAIN_AUDIO); | |
5612 | ||
15e7ec29 | 5613 | if (crtc_state->shared_dpll) |
d8fc70b7 | 5614 | mask |= BIT_ULL(POWER_DOMAIN_PLLS); |
15e7ec29 | 5615 | |
77d22dca ID |
5616 | return mask; |
5617 | } | |
5618 | ||
d2d15016 | 5619 | static u64 |
74bff5f9 ML |
5620 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
5621 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5622 | { |
fac5e23e | 5623 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5624 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5625 | enum intel_display_power_domain domain; | |
d8fc70b7 | 5626 | u64 domains, new_domains, old_domains; |
77d22dca | 5627 | |
292b990e | 5628 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5629 | intel_crtc->enabled_power_domains = new_domains = |
5630 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5631 | |
5a21b665 | 5632 | domains = new_domains & ~old_domains; |
292b990e ML |
5633 | |
5634 | for_each_power_domain(domain, domains) | |
5635 | intel_display_power_get(dev_priv, domain); | |
5636 | ||
5a21b665 | 5637 | return old_domains & ~new_domains; |
292b990e ML |
5638 | } |
5639 | ||
5640 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 5641 | u64 domains) |
292b990e ML |
5642 | { |
5643 | enum intel_display_power_domain domain; | |
5644 | ||
5645 | for_each_power_domain(domain, domains) | |
5646 | intel_display_power_put(dev_priv, domain); | |
5647 | } | |
77d22dca | 5648 | |
7ff89ca2 VS |
5649 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
5650 | struct drm_atomic_state *old_state) | |
adafdc6f | 5651 | { |
ff32c54e VS |
5652 | struct intel_atomic_state *old_intel_state = |
5653 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5654 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5655 | struct drm_device *dev = crtc->dev; | |
5656 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5657 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5658 | int pipe = intel_crtc->pipe; | |
adafdc6f | 5659 | |
7ff89ca2 VS |
5660 | if (WARN_ON(intel_crtc->active)) |
5661 | return; | |
adafdc6f | 5662 | |
7ff89ca2 VS |
5663 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5664 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
b2045352 | 5665 | |
7ff89ca2 VS |
5666 | intel_set_pipe_timings(intel_crtc); |
5667 | intel_set_pipe_src_size(intel_crtc); | |
b2045352 | 5668 | |
7ff89ca2 VS |
5669 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
5670 | struct drm_i915_private *dev_priv = to_i915(dev); | |
560a7ae4 | 5671 | |
7ff89ca2 VS |
5672 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
5673 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
5674 | } |
5675 | ||
7ff89ca2 | 5676 | i9xx_set_pipeconf(intel_crtc); |
560a7ae4 | 5677 | |
7ff89ca2 | 5678 | intel_crtc->active = true; |
92891e45 | 5679 | |
7ff89ca2 | 5680 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 5681 | |
7ff89ca2 | 5682 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
5f199dfa | 5683 | |
7ff89ca2 VS |
5684 | if (IS_CHERRYVIEW(dev_priv)) { |
5685 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
5686 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
5687 | } else { | |
5688 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
5689 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
5f199dfa VS |
5690 | } |
5691 | ||
7ff89ca2 | 5692 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
5f199dfa | 5693 | |
7ff89ca2 | 5694 | i9xx_pfit_enable(intel_crtc); |
89b3c3c7 | 5695 | |
7ff89ca2 | 5696 | intel_color_load_luts(&pipe_config->base); |
89b3c3c7 | 5697 | |
ff32c54e VS |
5698 | dev_priv->display.initial_watermarks(old_intel_state, |
5699 | pipe_config); | |
7ff89ca2 VS |
5700 | intel_enable_pipe(intel_crtc); |
5701 | ||
5702 | assert_vblank_disabled(crtc); | |
5703 | drm_crtc_vblank_on(crtc); | |
89b3c3c7 | 5704 | |
7ff89ca2 | 5705 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b3c3c7 ACO |
5706 | } |
5707 | ||
7ff89ca2 | 5708 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
2b73001e | 5709 | { |
7ff89ca2 VS |
5710 | struct drm_device *dev = crtc->base.dev; |
5711 | struct drm_i915_private *dev_priv = to_i915(dev); | |
83d7c81f | 5712 | |
7ff89ca2 VS |
5713 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5714 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
2b73001e VS |
5715 | } |
5716 | ||
7ff89ca2 VS |
5717 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
5718 | struct drm_atomic_state *old_state) | |
2b73001e | 5719 | { |
04548cba VS |
5720 | struct intel_atomic_state *old_intel_state = |
5721 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5722 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5723 | struct drm_device *dev = crtc->dev; | |
5724 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5726 | enum pipe pipe = intel_crtc->pipe; | |
2b73001e | 5727 | |
7ff89ca2 VS |
5728 | if (WARN_ON(intel_crtc->active)) |
5729 | return; | |
2b73001e | 5730 | |
7ff89ca2 | 5731 | i9xx_set_pll_dividers(intel_crtc); |
2b73001e | 5732 | |
7ff89ca2 VS |
5733 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5734 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
83d7c81f | 5735 | |
7ff89ca2 VS |
5736 | intel_set_pipe_timings(intel_crtc); |
5737 | intel_set_pipe_src_size(intel_crtc); | |
2b73001e | 5738 | |
7ff89ca2 | 5739 | i9xx_set_pipeconf(intel_crtc); |
f8437dd1 | 5740 | |
7ff89ca2 | 5741 | intel_crtc->active = true; |
5f199dfa | 5742 | |
7ff89ca2 VS |
5743 | if (!IS_GEN2(dev_priv)) |
5744 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5f199dfa | 5745 | |
7ff89ca2 | 5746 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f8437dd1 | 5747 | |
7ff89ca2 | 5748 | i9xx_enable_pll(intel_crtc); |
f8437dd1 | 5749 | |
7ff89ca2 | 5750 | i9xx_pfit_enable(intel_crtc); |
f8437dd1 | 5751 | |
7ff89ca2 | 5752 | intel_color_load_luts(&pipe_config->base); |
f8437dd1 | 5753 | |
04548cba VS |
5754 | if (dev_priv->display.initial_watermarks != NULL) |
5755 | dev_priv->display.initial_watermarks(old_intel_state, | |
5756 | intel_crtc->config); | |
5757 | else | |
5758 | intel_update_watermarks(intel_crtc); | |
7ff89ca2 | 5759 | intel_enable_pipe(intel_crtc); |
f8437dd1 | 5760 | |
7ff89ca2 VS |
5761 | assert_vblank_disabled(crtc); |
5762 | drm_crtc_vblank_on(crtc); | |
f8437dd1 | 5763 | |
7ff89ca2 VS |
5764 | intel_encoders_enable(crtc, pipe_config, old_state); |
5765 | } | |
f8437dd1 | 5766 | |
7ff89ca2 VS |
5767 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5768 | { | |
5769 | struct drm_device *dev = crtc->base.dev; | |
5770 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f8437dd1 | 5771 | |
7ff89ca2 | 5772 | if (!crtc->config->gmch_pfit.control) |
f8437dd1 | 5773 | return; |
f8437dd1 | 5774 | |
7ff89ca2 VS |
5775 | assert_pipe_disabled(dev_priv, crtc->pipe); |
5776 | ||
5777 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
5778 | I915_READ(PFIT_CONTROL)); | |
5779 | I915_WRITE(PFIT_CONTROL, 0); | |
f8437dd1 VK |
5780 | } |
5781 | ||
7ff89ca2 VS |
5782 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5783 | struct drm_atomic_state *old_state) | |
f8437dd1 | 5784 | { |
7ff89ca2 VS |
5785 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
5786 | struct drm_device *dev = crtc->dev; | |
5787 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5788 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5789 | int pipe = intel_crtc->pipe; | |
d66a2194 | 5790 | |
d66a2194 | 5791 | /* |
7ff89ca2 VS |
5792 | * On gen2 planes are double buffered but the pipe isn't, so we must |
5793 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 5794 | */ |
7ff89ca2 VS |
5795 | if (IS_GEN2(dev_priv)) |
5796 | intel_wait_for_vblank(dev_priv, pipe); | |
d66a2194 | 5797 | |
7ff89ca2 | 5798 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5799 | |
7ff89ca2 VS |
5800 | drm_crtc_vblank_off(crtc); |
5801 | assert_vblank_disabled(crtc); | |
d66a2194 | 5802 | |
7ff89ca2 | 5803 | intel_disable_pipe(intel_crtc); |
d66a2194 | 5804 | |
7ff89ca2 | 5805 | i9xx_pfit_disable(intel_crtc); |
89b3c3c7 | 5806 | |
7ff89ca2 | 5807 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5808 | |
7ff89ca2 VS |
5809 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
5810 | if (IS_CHERRYVIEW(dev_priv)) | |
5811 | chv_disable_pll(dev_priv, pipe); | |
5812 | else if (IS_VALLEYVIEW(dev_priv)) | |
5813 | vlv_disable_pll(dev_priv, pipe); | |
5814 | else | |
5815 | i9xx_disable_pll(intel_crtc); | |
5816 | } | |
c2e001ef | 5817 | |
7ff89ca2 | 5818 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
89b3c3c7 | 5819 | |
7ff89ca2 VS |
5820 | if (!IS_GEN2(dev_priv)) |
5821 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
ff32c54e VS |
5822 | |
5823 | if (!dev_priv->display.initial_watermarks) | |
5824 | intel_update_watermarks(intel_crtc); | |
f8437dd1 VK |
5825 | } |
5826 | ||
7ff89ca2 | 5827 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
f8437dd1 | 5828 | { |
7ff89ca2 VS |
5829 | struct intel_encoder *encoder; |
5830 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5831 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
5832 | enum intel_display_power_domain domain; | |
d2d15016 | 5833 | u64 domains; |
7ff89ca2 VS |
5834 | struct drm_atomic_state *state; |
5835 | struct intel_crtc_state *crtc_state; | |
5836 | int ret; | |
f8437dd1 | 5837 | |
7ff89ca2 VS |
5838 | if (!intel_crtc->active) |
5839 | return; | |
a8ca4934 | 5840 | |
7ff89ca2 VS |
5841 | if (crtc->primary->state->visible) { |
5842 | WARN_ON(intel_crtc->flip_work); | |
5d96d8af | 5843 | |
7ff89ca2 | 5844 | intel_pre_disable_primary_noatomic(crtc); |
709e05c3 | 5845 | |
7ff89ca2 VS |
5846 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
5847 | crtc->primary->state->visible = false; | |
5848 | } | |
5d96d8af | 5849 | |
7ff89ca2 VS |
5850 | state = drm_atomic_state_alloc(crtc->dev); |
5851 | if (!state) { | |
5852 | DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", | |
5853 | crtc->base.id, crtc->name); | |
1c3f7700 | 5854 | return; |
7ff89ca2 | 5855 | } |
9f7eb31a | 5856 | |
7ff89ca2 | 5857 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; |
ea61791e | 5858 | |
7ff89ca2 VS |
5859 | /* Everything's already locked, -EDEADLK can't happen. */ |
5860 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
5861 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
9f7eb31a | 5862 | |
7ff89ca2 | 5863 | WARN_ON(IS_ERR(crtc_state) || ret); |
5d96d8af | 5864 | |
7ff89ca2 | 5865 | dev_priv->display.crtc_disable(crtc_state, state); |
4a806558 | 5866 | |
0853695c | 5867 | drm_atomic_state_put(state); |
842e0307 | 5868 | |
78108b7c VS |
5869 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
5870 | crtc->base.id, crtc->name); | |
842e0307 ML |
5871 | |
5872 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
5873 | crtc->state->active = false; | |
37d9078b | 5874 | intel_crtc->active = false; |
842e0307 ML |
5875 | crtc->enabled = false; |
5876 | crtc->state->connector_mask = 0; | |
5877 | crtc->state->encoder_mask = 0; | |
5878 | ||
5879 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
5880 | encoder->base.crtc = NULL; | |
5881 | ||
58f9c0bc | 5882 | intel_fbc_disable(intel_crtc); |
432081bc | 5883 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 5884 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
5885 | |
5886 | domains = intel_crtc->enabled_power_domains; | |
5887 | for_each_power_domain(domain, domains) | |
5888 | intel_display_power_put(dev_priv, domain); | |
5889 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
5890 | |
5891 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
5892 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
5893 | } |
5894 | ||
6b72d486 ML |
5895 | /* |
5896 | * turn all crtc's off, but do not adjust state | |
5897 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
5898 | */ | |
70e0bd74 | 5899 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 5900 | { |
e2c8b870 | 5901 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 5902 | struct drm_atomic_state *state; |
e2c8b870 | 5903 | int ret; |
70e0bd74 | 5904 | |
e2c8b870 ML |
5905 | state = drm_atomic_helper_suspend(dev); |
5906 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
5907 | if (ret) |
5908 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
5909 | else |
5910 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 5911 | return ret; |
ee7b9f93 JB |
5912 | } |
5913 | ||
ea5b213a | 5914 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5915 | { |
4ef69c7a | 5916 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5917 | |
ea5b213a CW |
5918 | drm_encoder_cleanup(encoder); |
5919 | kfree(intel_encoder); | |
7e7d76c3 JB |
5920 | } |
5921 | ||
0a91ca29 DV |
5922 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5923 | * internal consistency). */ | |
5a21b665 | 5924 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 5925 | { |
5a21b665 | 5926 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
5927 | |
5928 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5929 | connector->base.base.id, | |
5930 | connector->base.name); | |
5931 | ||
0a91ca29 | 5932 | if (connector->get_hw_state(connector)) { |
e85376cb | 5933 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 5934 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 5935 | |
35dd3c64 ML |
5936 | I915_STATE_WARN(!crtc, |
5937 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 5938 | |
35dd3c64 ML |
5939 | if (!crtc) |
5940 | return; | |
5941 | ||
5942 | I915_STATE_WARN(!crtc->state->active, | |
5943 | "connector is active, but attached crtc isn't\n"); | |
5944 | ||
e85376cb | 5945 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
5946 | return; |
5947 | ||
e85376cb | 5948 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
5949 | "atomic encoder doesn't match attached encoder\n"); |
5950 | ||
e85376cb | 5951 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
5952 | "attached encoder crtc differs from connector crtc\n"); |
5953 | } else { | |
4d688a2a ML |
5954 | I915_STATE_WARN(crtc && crtc->state->active, |
5955 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 5956 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 5957 | "best encoder set without crtc!\n"); |
0a91ca29 | 5958 | } |
79e53945 JB |
5959 | } |
5960 | ||
08d9bc92 ACO |
5961 | int intel_connector_init(struct intel_connector *connector) |
5962 | { | |
5350a031 | 5963 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 5964 | |
5350a031 | 5965 | if (!connector->base.state) |
08d9bc92 ACO |
5966 | return -ENOMEM; |
5967 | ||
08d9bc92 ACO |
5968 | return 0; |
5969 | } | |
5970 | ||
5971 | struct intel_connector *intel_connector_alloc(void) | |
5972 | { | |
5973 | struct intel_connector *connector; | |
5974 | ||
5975 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
5976 | if (!connector) | |
5977 | return NULL; | |
5978 | ||
5979 | if (intel_connector_init(connector) < 0) { | |
5980 | kfree(connector); | |
5981 | return NULL; | |
5982 | } | |
5983 | ||
5984 | return connector; | |
5985 | } | |
5986 | ||
f0947c37 DV |
5987 | /* Simple connector->get_hw_state implementation for encoders that support only |
5988 | * one connector and no cloning and hence the encoder state determines the state | |
5989 | * of the connector. */ | |
5990 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5991 | { |
24929352 | 5992 | enum pipe pipe = 0; |
f0947c37 | 5993 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5994 | |
f0947c37 | 5995 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5996 | } |
5997 | ||
6d293983 | 5998 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 5999 | { |
6d293983 ACO |
6000 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6001 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6002 | |
6003 | return 0; | |
6004 | } | |
6005 | ||
6d293983 | 6006 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6007 | struct intel_crtc_state *pipe_config) |
1857e1da | 6008 | { |
8652744b | 6009 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
6010 | struct drm_atomic_state *state = pipe_config->base.state; |
6011 | struct intel_crtc *other_crtc; | |
6012 | struct intel_crtc_state *other_crtc_state; | |
6013 | ||
1857e1da DV |
6014 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6015 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6016 | if (pipe_config->fdi_lanes > 4) { | |
6017 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6018 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6019 | return -EINVAL; |
1857e1da DV |
6020 | } |
6021 | ||
8652744b | 6022 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
6023 | if (pipe_config->fdi_lanes > 2) { |
6024 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6025 | pipe_config->fdi_lanes); | |
6d293983 | 6026 | return -EINVAL; |
1857e1da | 6027 | } else { |
6d293983 | 6028 | return 0; |
1857e1da DV |
6029 | } |
6030 | } | |
6031 | ||
b7f05d4a | 6032 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 6033 | return 0; |
1857e1da DV |
6034 | |
6035 | /* Ivybridge 3 pipe is really complicated */ | |
6036 | switch (pipe) { | |
6037 | case PIPE_A: | |
6d293983 | 6038 | return 0; |
1857e1da | 6039 | case PIPE_B: |
6d293983 ACO |
6040 | if (pipe_config->fdi_lanes <= 2) |
6041 | return 0; | |
6042 | ||
b91eb5cc | 6043 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
6044 | other_crtc_state = |
6045 | intel_atomic_get_crtc_state(state, other_crtc); | |
6046 | if (IS_ERR(other_crtc_state)) | |
6047 | return PTR_ERR(other_crtc_state); | |
6048 | ||
6049 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6050 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6051 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6052 | return -EINVAL; |
1857e1da | 6053 | } |
6d293983 | 6054 | return 0; |
1857e1da | 6055 | case PIPE_C: |
251cc67c VS |
6056 | if (pipe_config->fdi_lanes > 2) { |
6057 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6058 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6059 | return -EINVAL; |
251cc67c | 6060 | } |
6d293983 | 6061 | |
b91eb5cc | 6062 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
6063 | other_crtc_state = |
6064 | intel_atomic_get_crtc_state(state, other_crtc); | |
6065 | if (IS_ERR(other_crtc_state)) | |
6066 | return PTR_ERR(other_crtc_state); | |
6067 | ||
6068 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6069 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6070 | return -EINVAL; |
1857e1da | 6071 | } |
6d293983 | 6072 | return 0; |
1857e1da DV |
6073 | default: |
6074 | BUG(); | |
6075 | } | |
6076 | } | |
6077 | ||
e29c22c0 DV |
6078 | #define RETRY 1 |
6079 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6080 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6081 | { |
1857e1da | 6082 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6083 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6084 | int lane, link_bw, fdi_dotclock, ret; |
6085 | bool needs_recompute = false; | |
877d48d5 | 6086 | |
e29c22c0 | 6087 | retry: |
877d48d5 DV |
6088 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6089 | * each output octet as 10 bits. The actual frequency | |
6090 | * is stored as a divider into a 100MHz clock, and the | |
6091 | * mode pixel clock is stored in units of 1KHz. | |
6092 | * Hence the bw of each lane in terms of the mode signal | |
6093 | * is: | |
6094 | */ | |
21a727b3 | 6095 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6096 | |
241bfc38 | 6097 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6098 | |
2bd89a07 | 6099 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6100 | pipe_config->pipe_bpp); |
6101 | ||
6102 | pipe_config->fdi_lanes = lane; | |
6103 | ||
2bd89a07 | 6104 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6105 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6106 | |
e3b247da | 6107 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6108 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 6109 | pipe_config->pipe_bpp -= 2*3; |
7ff89ca2 VS |
6110 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
6111 | pipe_config->pipe_bpp); | |
6112 | needs_recompute = true; | |
6113 | pipe_config->bw_constrained = true; | |
257a7ffc | 6114 | |
7ff89ca2 | 6115 | goto retry; |
257a7ffc | 6116 | } |
79e53945 | 6117 | |
7ff89ca2 VS |
6118 | if (needs_recompute) |
6119 | return RETRY; | |
e70236a8 | 6120 | |
7ff89ca2 | 6121 | return ret; |
e70236a8 JB |
6122 | } |
6123 | ||
7ff89ca2 VS |
6124 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6125 | struct intel_crtc_state *pipe_config) | |
e70236a8 | 6126 | { |
7ff89ca2 VS |
6127 | if (pipe_config->pipe_bpp > 24) |
6128 | return false; | |
e70236a8 | 6129 | |
7ff89ca2 VS |
6130 | /* HSW can handle pixel rate up to cdclk? */ |
6131 | if (IS_HASWELL(dev_priv)) | |
6132 | return true; | |
1b1d2716 | 6133 | |
65cd2b3f | 6134 | /* |
7ff89ca2 VS |
6135 | * We compare against max which means we must take |
6136 | * the increased cdclk requirement into account when | |
6137 | * calculating the new cdclk. | |
6138 | * | |
6139 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 6140 | */ |
7ff89ca2 VS |
6141 | return pipe_config->pixel_rate <= |
6142 | dev_priv->max_cdclk_freq * 95 / 100; | |
e70236a8 | 6143 | } |
79e53945 | 6144 | |
7ff89ca2 VS |
6145 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
6146 | struct intel_crtc_state *pipe_config) | |
6147 | { | |
6148 | struct drm_device *dev = crtc->base.dev; | |
6149 | struct drm_i915_private *dev_priv = to_i915(dev); | |
34edce2f | 6150 | |
7ff89ca2 VS |
6151 | pipe_config->ips_enabled = i915.enable_ips && |
6152 | hsw_crtc_supports_ips(crtc) && | |
6153 | pipe_config_supports_ips(dev_priv, pipe_config); | |
34edce2f VS |
6154 | } |
6155 | ||
7ff89ca2 | 6156 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 6157 | { |
7ff89ca2 | 6158 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 6159 | |
7ff89ca2 VS |
6160 | /* GDG double wide on either pipe, otherwise pipe A only */ |
6161 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6162 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
34edce2f VS |
6163 | } |
6164 | ||
ceb99320 VS |
6165 | static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
6166 | { | |
6167 | uint32_t pixel_rate; | |
6168 | ||
6169 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; | |
6170 | ||
6171 | /* | |
6172 | * We only use IF-ID interlacing. If we ever use | |
6173 | * PF-ID we'll need to adjust the pixel_rate here. | |
6174 | */ | |
6175 | ||
6176 | if (pipe_config->pch_pfit.enabled) { | |
6177 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
6178 | uint32_t pfit_size = pipe_config->pch_pfit.size; | |
6179 | ||
6180 | pipe_w = pipe_config->pipe_src_w; | |
6181 | pipe_h = pipe_config->pipe_src_h; | |
6182 | ||
6183 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
6184 | pfit_h = pfit_size & 0xFFFF; | |
6185 | if (pipe_w < pfit_w) | |
6186 | pipe_w = pfit_w; | |
6187 | if (pipe_h < pfit_h) | |
6188 | pipe_h = pfit_h; | |
6189 | ||
6190 | if (WARN_ON(!pfit_w || !pfit_h)) | |
6191 | return pixel_rate; | |
6192 | ||
6193 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
6194 | pfit_w * pfit_h); | |
6195 | } | |
6196 | ||
6197 | return pixel_rate; | |
6198 | } | |
6199 | ||
7ff89ca2 | 6200 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 6201 | { |
7ff89ca2 | 6202 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
34edce2f | 6203 | |
7ff89ca2 VS |
6204 | if (HAS_GMCH_DISPLAY(dev_priv)) |
6205 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ | |
6206 | crtc_state->pixel_rate = | |
6207 | crtc_state->base.adjusted_mode.crtc_clock; | |
6208 | else | |
6209 | crtc_state->pixel_rate = | |
6210 | ilk_pipe_pixel_rate(crtc_state); | |
6211 | } | |
34edce2f | 6212 | |
7ff89ca2 VS |
6213 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6214 | struct intel_crtc_state *pipe_config) | |
6215 | { | |
6216 | struct drm_device *dev = crtc->base.dev; | |
6217 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6218 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6219 | int clock_limit = dev_priv->max_dotclk_freq; | |
34edce2f | 6220 | |
7ff89ca2 VS |
6221 | if (INTEL_GEN(dev_priv) < 4) { |
6222 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 6223 | |
7ff89ca2 VS |
6224 | /* |
6225 | * Enable double wide mode when the dot clock | |
6226 | * is > 90% of the (display) core speed. | |
6227 | */ | |
6228 | if (intel_crtc_supports_double_wide(crtc) && | |
6229 | adjusted_mode->crtc_clock > clock_limit) { | |
6230 | clock_limit = dev_priv->max_dotclk_freq; | |
6231 | pipe_config->double_wide = true; | |
6232 | } | |
34edce2f VS |
6233 | } |
6234 | ||
7ff89ca2 VS |
6235 | if (adjusted_mode->crtc_clock > clock_limit) { |
6236 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6237 | adjusted_mode->crtc_clock, clock_limit, | |
6238 | yesno(pipe_config->double_wide)); | |
6239 | return -EINVAL; | |
6240 | } | |
34edce2f | 6241 | |
7ff89ca2 VS |
6242 | /* |
6243 | * Pipe horizontal size must be even in: | |
6244 | * - DVO ganged mode | |
6245 | * - LVDS dual channel mode | |
6246 | * - Double wide pipe | |
6247 | */ | |
6248 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6249 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6250 | pipe_config->pipe_src_w &= ~1; | |
34edce2f | 6251 | |
7ff89ca2 VS |
6252 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6253 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6254 | */ | |
6255 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
6256 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6257 | return -EINVAL; | |
34edce2f | 6258 | |
7ff89ca2 | 6259 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 6260 | |
7ff89ca2 VS |
6261 | if (HAS_IPS(dev_priv)) |
6262 | hsw_compute_ips_config(crtc, pipe_config); | |
34edce2f | 6263 | |
7ff89ca2 VS |
6264 | if (pipe_config->has_pch_encoder) |
6265 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
34edce2f | 6266 | |
7ff89ca2 | 6267 | return 0; |
34edce2f VS |
6268 | } |
6269 | ||
2c07245f | 6270 | static void |
a65851af | 6271 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6272 | { |
a65851af VS |
6273 | while (*num > DATA_LINK_M_N_MASK || |
6274 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6275 | *num >>= 1; |
6276 | *den >>= 1; | |
6277 | } | |
6278 | } | |
6279 | ||
a65851af VS |
6280 | static void compute_m_n(unsigned int m, unsigned int n, |
6281 | uint32_t *ret_m, uint32_t *ret_n) | |
6282 | { | |
9a86cda0 JN |
6283 | /* |
6284 | * Reduce M/N as much as possible without loss in precision. Several DP | |
6285 | * dongles in particular seem to be fussy about too large *link* M/N | |
6286 | * values. The passed in values are more likely to have the least | |
6287 | * significant bits zero than M after rounding below, so do this first. | |
6288 | */ | |
6289 | while ((m & 1) == 0 && (n & 1) == 0) { | |
6290 | m >>= 1; | |
6291 | n >>= 1; | |
6292 | } | |
6293 | ||
a65851af VS |
6294 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
6295 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6296 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6297 | } | |
6298 | ||
e69d0bc1 DV |
6299 | void |
6300 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6301 | int pixel_clock, int link_clock, | |
6302 | struct intel_link_m_n *m_n) | |
2c07245f | 6303 | { |
e69d0bc1 | 6304 | m_n->tu = 64; |
a65851af VS |
6305 | |
6306 | compute_m_n(bits_per_pixel * pixel_clock, | |
6307 | link_clock * nlanes * 8, | |
6308 | &m_n->gmch_m, &m_n->gmch_n); | |
6309 | ||
6310 | compute_m_n(pixel_clock, link_clock, | |
6311 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6312 | } |
6313 | ||
a7615030 CW |
6314 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6315 | { | |
d330a953 JN |
6316 | if (i915.panel_use_ssc >= 0) |
6317 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6318 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6319 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6320 | } |
6321 | ||
7429e9d4 | 6322 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6323 | { |
7df00d7a | 6324 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6325 | } |
f47709a9 | 6326 | |
7429e9d4 DV |
6327 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6328 | { | |
6329 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6330 | } |
6331 | ||
f47709a9 | 6332 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6333 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 6334 | struct dpll *reduced_clock) |
a7516a05 | 6335 | { |
9b1e14f4 | 6336 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
6337 | u32 fp, fp2 = 0; |
6338 | ||
9b1e14f4 | 6339 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 6340 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6341 | if (reduced_clock) |
7429e9d4 | 6342 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6343 | } else { |
190f68c5 | 6344 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6345 | if (reduced_clock) |
7429e9d4 | 6346 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6347 | } |
6348 | ||
190f68c5 | 6349 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6350 | |
f47709a9 | 6351 | crtc->lowfreq_avail = false; |
2d84d2b3 | 6352 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6353 | reduced_clock) { |
190f68c5 | 6354 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6355 | crtc->lowfreq_avail = true; |
a7516a05 | 6356 | } else { |
190f68c5 | 6357 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6358 | } |
6359 | } | |
6360 | ||
5e69f97f CML |
6361 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6362 | pipe) | |
89b667f8 JB |
6363 | { |
6364 | u32 reg_val; | |
6365 | ||
6366 | /* | |
6367 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6368 | * and set it to a reasonable value instead. | |
6369 | */ | |
ab3c759a | 6370 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6371 | reg_val &= 0xffffff00; |
6372 | reg_val |= 0x00000030; | |
ab3c759a | 6373 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6374 | |
ab3c759a | 6375 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
ed58570f ID |
6376 | reg_val &= 0x00ffffff; |
6377 | reg_val |= 0x8c000000; | |
ab3c759a | 6378 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6379 | |
ab3c759a | 6380 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6381 | reg_val &= 0xffffff00; |
ab3c759a | 6382 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6383 | |
ab3c759a | 6384 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6385 | reg_val &= 0x00ffffff; |
6386 | reg_val |= 0xb0000000; | |
ab3c759a | 6387 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6388 | } |
6389 | ||
b551842d DV |
6390 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6391 | struct intel_link_m_n *m_n) | |
6392 | { | |
6393 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6394 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
6395 | int pipe = crtc->pipe; |
6396 | ||
e3b95f1e DV |
6397 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6398 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6399 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6400 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6401 | } |
6402 | ||
6403 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6404 | struct intel_link_m_n *m_n, |
6405 | struct intel_link_m_n *m2_n2) | |
b551842d | 6406 | { |
6315b5d3 | 6407 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 6408 | int pipe = crtc->pipe; |
6e3c9717 | 6409 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 6410 | |
6315b5d3 | 6411 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
6412 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6413 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6414 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6415 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6416 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6417 | * for gen < 8) and if DRRS is supported (to make sure the | |
6418 | * registers are not unnecessarily accessed). | |
6419 | */ | |
920a14b2 TU |
6420 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
6421 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
6422 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6423 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6424 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6425 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6426 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6427 | } | |
b551842d | 6428 | } else { |
e3b95f1e DV |
6429 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6430 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6431 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6432 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6433 | } |
6434 | } | |
6435 | ||
fe3cd48d | 6436 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6437 | { |
fe3cd48d R |
6438 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6439 | ||
6440 | if (m_n == M1_N1) { | |
6441 | dp_m_n = &crtc->config->dp_m_n; | |
6442 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6443 | } else if (m_n == M2_N2) { | |
6444 | ||
6445 | /* | |
6446 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6447 | * needs to be programmed into M1_N1. | |
6448 | */ | |
6449 | dp_m_n = &crtc->config->dp_m2_n2; | |
6450 | } else { | |
6451 | DRM_ERROR("Unsupported divider value\n"); | |
6452 | return; | |
6453 | } | |
6454 | ||
6e3c9717 ACO |
6455 | if (crtc->config->has_pch_encoder) |
6456 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6457 | else |
fe3cd48d | 6458 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6459 | } |
6460 | ||
251ac862 DV |
6461 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
6462 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 6463 | { |
03ed5cbf | 6464 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 6465 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6466 | if (crtc->pipe != PIPE_A) |
6467 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 6468 | |
cd2d34d9 | 6469 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6470 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6471 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
6472 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
6473 | ||
03ed5cbf VS |
6474 | pipe_config->dpll_hw_state.dpll_md = |
6475 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6476 | } | |
bdd4b6a6 | 6477 | |
03ed5cbf VS |
6478 | static void chv_compute_dpll(struct intel_crtc *crtc, |
6479 | struct intel_crtc_state *pipe_config) | |
6480 | { | |
6481 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 6482 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6483 | if (crtc->pipe != PIPE_A) |
6484 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6485 | ||
cd2d34d9 | 6486 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6487 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6488 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
6489 | ||
03ed5cbf VS |
6490 | pipe_config->dpll_hw_state.dpll_md = |
6491 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
6492 | } |
6493 | ||
d288f65f | 6494 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6495 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6496 | { |
f47709a9 | 6497 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6498 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6499 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 6500 | u32 mdiv; |
a0c4da24 | 6501 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6502 | u32 coreclk, reg_val; |
a0c4da24 | 6503 | |
cd2d34d9 VS |
6504 | /* Enable Refclk */ |
6505 | I915_WRITE(DPLL(pipe), | |
6506 | pipe_config->dpll_hw_state.dpll & | |
6507 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
6508 | ||
6509 | /* No need to actually set up the DPLL with DSI */ | |
6510 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6511 | return; | |
6512 | ||
a580516d | 6513 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 6514 | |
d288f65f VS |
6515 | bestn = pipe_config->dpll.n; |
6516 | bestm1 = pipe_config->dpll.m1; | |
6517 | bestm2 = pipe_config->dpll.m2; | |
6518 | bestp1 = pipe_config->dpll.p1; | |
6519 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6520 | |
89b667f8 JB |
6521 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6522 | ||
6523 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6524 | if (pipe == PIPE_B) |
5e69f97f | 6525 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6526 | |
6527 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6528 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6529 | |
6530 | /* Disable target IRef on PLL */ | |
ab3c759a | 6531 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6532 | reg_val &= 0x00ffffff; |
ab3c759a | 6533 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6534 | |
6535 | /* Disable fast lock */ | |
ab3c759a | 6536 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6537 | |
6538 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6539 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6540 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6541 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6542 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6543 | |
6544 | /* | |
6545 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6546 | * but we don't support that). | |
6547 | * Note: don't use the DAC post divider as it seems unstable. | |
6548 | */ | |
6549 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6550 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6551 | |
a0c4da24 | 6552 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6553 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6554 | |
89b667f8 | 6555 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6556 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
6557 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
6558 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6559 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6560 | 0x009f0003); |
89b667f8 | 6561 | else |
ab3c759a | 6562 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6563 | 0x00d0000f); |
6564 | ||
37a5650b | 6565 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 6566 | /* Use SSC source */ |
bdd4b6a6 | 6567 | if (pipe == PIPE_A) |
ab3c759a | 6568 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6569 | 0x0df40000); |
6570 | else | |
ab3c759a | 6571 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6572 | 0x0df70000); |
6573 | } else { /* HDMI or VGA */ | |
6574 | /* Use bend source */ | |
bdd4b6a6 | 6575 | if (pipe == PIPE_A) |
ab3c759a | 6576 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6577 | 0x0df70000); |
6578 | else | |
ab3c759a | 6579 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6580 | 0x0df40000); |
6581 | } | |
a0c4da24 | 6582 | |
ab3c759a | 6583 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6584 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 6585 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 6586 | coreclk |= 0x01000000; |
ab3c759a | 6587 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6588 | |
ab3c759a | 6589 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 6590 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
6591 | } |
6592 | ||
d288f65f | 6593 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6594 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6595 | { |
6596 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6597 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6598 | enum pipe pipe = crtc->pipe; |
9d556c99 | 6599 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 6600 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6601 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6602 | u32 dpio_val; |
9cbe40c1 | 6603 | int vco; |
9d556c99 | 6604 | |
cd2d34d9 VS |
6605 | /* Enable Refclk and SSC */ |
6606 | I915_WRITE(DPLL(pipe), | |
6607 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
6608 | ||
6609 | /* No need to actually set up the DPLL with DSI */ | |
6610 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6611 | return; | |
6612 | ||
d288f65f VS |
6613 | bestn = pipe_config->dpll.n; |
6614 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6615 | bestm1 = pipe_config->dpll.m1; | |
6616 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6617 | bestp1 = pipe_config->dpll.p1; | |
6618 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6619 | vco = pipe_config->dpll.vco; |
a945ce7e | 6620 | dpio_val = 0; |
9cbe40c1 | 6621 | loopfilter = 0; |
9d556c99 | 6622 | |
a580516d | 6623 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 6624 | |
9d556c99 CML |
6625 | /* p1 and p2 divider */ |
6626 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6627 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6628 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6629 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6630 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6631 | ||
6632 | /* Feedback post-divider - m2 */ | |
6633 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6634 | ||
6635 | /* Feedback refclk divider - n and m1 */ | |
6636 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6637 | DPIO_CHV_M1_DIV_BY_2 | | |
6638 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6639 | ||
6640 | /* M2 fraction division */ | |
25a25dfc | 6641 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
6642 | |
6643 | /* M2 fraction division enable */ | |
a945ce7e VP |
6644 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6645 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6646 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6647 | if (bestm2_frac) | |
6648 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6649 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6650 | |
de3a0fde VP |
6651 | /* Program digital lock detect threshold */ |
6652 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6653 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6654 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6655 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6656 | if (!bestm2_frac) | |
6657 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6658 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6659 | ||
9d556c99 | 6660 | /* Loop filter */ |
9cbe40c1 VP |
6661 | if (vco == 5400000) { |
6662 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6663 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6664 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6665 | tribuf_calcntr = 0x9; | |
6666 | } else if (vco <= 6200000) { | |
6667 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6668 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6669 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6670 | tribuf_calcntr = 0x9; | |
6671 | } else if (vco <= 6480000) { | |
6672 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6673 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6674 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6675 | tribuf_calcntr = 0x8; | |
6676 | } else { | |
6677 | /* Not supported. Apply the same limits as in the max case */ | |
6678 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6679 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6680 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6681 | tribuf_calcntr = 0; | |
6682 | } | |
9d556c99 CML |
6683 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6684 | ||
968040b2 | 6685 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6686 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6687 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6688 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6689 | ||
9d556c99 CML |
6690 | /* AFC Recal */ |
6691 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6692 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6693 | DPIO_AFC_RECAL); | |
6694 | ||
a580516d | 6695 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
6696 | } |
6697 | ||
d288f65f VS |
6698 | /** |
6699 | * vlv_force_pll_on - forcibly enable just the PLL | |
6700 | * @dev_priv: i915 private structure | |
6701 | * @pipe: pipe PLL to enable | |
6702 | * @dpll: PLL configuration | |
6703 | * | |
6704 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6705 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6706 | * be enabled. | |
6707 | */ | |
30ad9814 | 6708 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 6709 | const struct dpll *dpll) |
d288f65f | 6710 | { |
b91eb5cc | 6711 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
6712 | struct intel_crtc_state *pipe_config; |
6713 | ||
6714 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
6715 | if (!pipe_config) | |
6716 | return -ENOMEM; | |
6717 | ||
6718 | pipe_config->base.crtc = &crtc->base; | |
6719 | pipe_config->pixel_multiplier = 1; | |
6720 | pipe_config->dpll = *dpll; | |
d288f65f | 6721 | |
30ad9814 | 6722 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
6723 | chv_compute_dpll(crtc, pipe_config); |
6724 | chv_prepare_pll(crtc, pipe_config); | |
6725 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 6726 | } else { |
3f36b937 TU |
6727 | vlv_compute_dpll(crtc, pipe_config); |
6728 | vlv_prepare_pll(crtc, pipe_config); | |
6729 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 6730 | } |
3f36b937 TU |
6731 | |
6732 | kfree(pipe_config); | |
6733 | ||
6734 | return 0; | |
d288f65f VS |
6735 | } |
6736 | ||
6737 | /** | |
6738 | * vlv_force_pll_off - forcibly disable just the PLL | |
6739 | * @dev_priv: i915 private structure | |
6740 | * @pipe: pipe PLL to disable | |
6741 | * | |
6742 | * Disable the PLL for @pipe. To be used in cases where we need | |
6743 | * the PLL enabled even when @pipe is not going to be enabled. | |
6744 | */ | |
30ad9814 | 6745 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 6746 | { |
30ad9814 VS |
6747 | if (IS_CHERRYVIEW(dev_priv)) |
6748 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 6749 | else |
30ad9814 | 6750 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
6751 | } |
6752 | ||
251ac862 DV |
6753 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
6754 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6755 | struct dpll *reduced_clock) |
eb1cbe48 | 6756 | { |
9b1e14f4 | 6757 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 6758 | u32 dpll; |
190f68c5 | 6759 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6760 | |
190f68c5 | 6761 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6762 | |
eb1cbe48 DV |
6763 | dpll = DPLL_VGA_MODE_DIS; |
6764 | ||
2d84d2b3 | 6765 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6766 | dpll |= DPLLB_MODE_LVDS; |
6767 | else | |
6768 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6769 | |
73f67aa8 JN |
6770 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
6771 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 6772 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6773 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6774 | } |
198a037f | 6775 | |
3d6e9ee0 VS |
6776 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6777 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 6778 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6779 | |
37a5650b | 6780 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 6781 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6782 | |
6783 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 6784 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
6785 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
6786 | else { | |
6787 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 6788 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
6789 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6790 | } | |
6791 | switch (clock->p2) { | |
6792 | case 5: | |
6793 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6794 | break; | |
6795 | case 7: | |
6796 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6797 | break; | |
6798 | case 10: | |
6799 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6800 | break; | |
6801 | case 14: | |
6802 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6803 | break; | |
6804 | } | |
9b1e14f4 | 6805 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
6806 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
6807 | ||
190f68c5 | 6808 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6809 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 6810 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6811 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6812 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6813 | else | |
6814 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6815 | ||
6816 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6817 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6818 | |
9b1e14f4 | 6819 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 6820 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6821 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6822 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6823 | } |
6824 | } | |
6825 | ||
251ac862 DV |
6826 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
6827 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6828 | struct dpll *reduced_clock) |
eb1cbe48 | 6829 | { |
f47709a9 | 6830 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6831 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 6832 | u32 dpll; |
190f68c5 | 6833 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6834 | |
190f68c5 | 6835 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6836 | |
eb1cbe48 DV |
6837 | dpll = DPLL_VGA_MODE_DIS; |
6838 | ||
2d84d2b3 | 6839 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6840 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6841 | } else { | |
6842 | if (clock->p1 == 2) | |
6843 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6844 | else | |
6845 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6846 | if (clock->p2 == 4) | |
6847 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6848 | } | |
6849 | ||
50a0bc90 TU |
6850 | if (!IS_I830(dev_priv) && |
6851 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
6852 | dpll |= DPLL_DVO_2X_MODE; |
6853 | ||
2d84d2b3 | 6854 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6855 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6856 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6857 | else | |
6858 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6859 | ||
6860 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6861 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6862 | } |
6863 | ||
8a654f3b | 6864 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 6865 | { |
6315b5d3 | 6866 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 6867 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 6868 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 6869 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6870 | uint32_t crtc_vtotal, crtc_vblank_end; |
6871 | int vsyncshift = 0; | |
4d8a62ea DV |
6872 | |
6873 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6874 | * the hw state checker will get angry at the mismatch. */ | |
6875 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6876 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6877 | |
609aeaca | 6878 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6879 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6880 | crtc_vtotal -= 1; |
6881 | crtc_vblank_end -= 1; | |
609aeaca | 6882 | |
2d84d2b3 | 6883 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6884 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6885 | else | |
6886 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6887 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6888 | if (vsyncshift < 0) |
6889 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6890 | } |
6891 | ||
6315b5d3 | 6892 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 6893 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6894 | |
fe2b8f9d | 6895 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6896 | (adjusted_mode->crtc_hdisplay - 1) | |
6897 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6898 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6899 | (adjusted_mode->crtc_hblank_start - 1) | |
6900 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6901 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6902 | (adjusted_mode->crtc_hsync_start - 1) | |
6903 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6904 | ||
fe2b8f9d | 6905 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6906 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6907 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6908 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6909 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6910 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6911 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6912 | (adjusted_mode->crtc_vsync_start - 1) | |
6913 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6914 | ||
b5e508d4 PZ |
6915 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6916 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6917 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6918 | * bits. */ | |
772c2a51 | 6919 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
6920 | (pipe == PIPE_B || pipe == PIPE_C)) |
6921 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6922 | ||
bc58be60 JN |
6923 | } |
6924 | ||
6925 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
6926 | { | |
6927 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 6928 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
6929 | enum pipe pipe = intel_crtc->pipe; |
6930 | ||
b0e77b9c PZ |
6931 | /* pipesrc controls the size that is scaled from, which should |
6932 | * always be the user's requested size. | |
6933 | */ | |
6934 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6935 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6936 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6937 | } |
6938 | ||
1bd1bd80 | 6939 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6940 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6941 | { |
6942 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6943 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
6944 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
6945 | uint32_t tmp; | |
6946 | ||
6947 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6948 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6949 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6950 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6951 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6952 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6953 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6954 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6955 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6956 | |
6957 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6958 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6959 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6960 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6961 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6962 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6963 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6964 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6965 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6966 | |
6967 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6968 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6969 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6970 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 6971 | } |
bc58be60 JN |
6972 | } |
6973 | ||
6974 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
6975 | struct intel_crtc_state *pipe_config) | |
6976 | { | |
6977 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6978 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 6979 | u32 tmp; |
1bd1bd80 DV |
6980 | |
6981 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6982 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6983 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6984 | ||
2d112de7 ACO |
6985 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
6986 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6987 | } |
6988 | ||
f6a83288 | 6989 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 6990 | struct intel_crtc_state *pipe_config) |
babea61d | 6991 | { |
2d112de7 ACO |
6992 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
6993 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
6994 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
6995 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 6996 | |
2d112de7 ACO |
6997 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
6998 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
6999 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7000 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7001 | |
2d112de7 | 7002 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7003 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7004 | |
2d112de7 | 7005 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
cd13f5ab ML |
7006 | |
7007 | mode->hsync = drm_mode_hsync(mode); | |
7008 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7009 | drm_mode_set_name(mode); | |
babea61d JB |
7010 | } |
7011 | ||
84b046f3 DV |
7012 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7013 | { | |
6315b5d3 | 7014 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
7015 | uint32_t pipeconf; |
7016 | ||
9f11a9e4 | 7017 | pipeconf = 0; |
84b046f3 | 7018 | |
b6b5d049 VS |
7019 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7020 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7021 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7022 | |
6e3c9717 | 7023 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7024 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7025 | |
ff9ce46e | 7026 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
7027 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7028 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 7029 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7030 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7031 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7032 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7033 | |
6e3c9717 | 7034 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7035 | case 18: |
7036 | pipeconf |= PIPECONF_6BPC; | |
7037 | break; | |
7038 | case 24: | |
7039 | pipeconf |= PIPECONF_8BPC; | |
7040 | break; | |
7041 | case 30: | |
7042 | pipeconf |= PIPECONF_10BPC; | |
7043 | break; | |
7044 | default: | |
7045 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7046 | BUG(); | |
84b046f3 DV |
7047 | } |
7048 | } | |
7049 | ||
56b857a5 | 7050 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
7051 | if (intel_crtc->lowfreq_avail) { |
7052 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7053 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7054 | } else { | |
7055 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7056 | } |
7057 | } | |
7058 | ||
6e3c9717 | 7059 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 7060 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 7061 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7062 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7063 | else | |
7064 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7065 | } else | |
84b046f3 DV |
7066 | pipeconf |= PIPECONF_PROGRESSIVE; |
7067 | ||
920a14b2 | 7068 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7069 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 7070 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7071 | |
84b046f3 DV |
7072 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7073 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7074 | } | |
7075 | ||
81c97f52 ACO |
7076 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7077 | struct intel_crtc_state *crtc_state) | |
7078 | { | |
7079 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7080 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7081 | const struct intel_limit *limit; |
81c97f52 ACO |
7082 | int refclk = 48000; |
7083 | ||
7084 | memset(&crtc_state->dpll_hw_state, 0, | |
7085 | sizeof(crtc_state->dpll_hw_state)); | |
7086 | ||
2d84d2b3 | 7087 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7088 | if (intel_panel_use_ssc(dev_priv)) { |
7089 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7090 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7091 | } | |
7092 | ||
7093 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7094 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7095 | limit = &intel_limits_i8xx_dvo; |
7096 | } else { | |
7097 | limit = &intel_limits_i8xx_dac; | |
7098 | } | |
7099 | ||
7100 | if (!crtc_state->clock_set && | |
7101 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7102 | refclk, NULL, &crtc_state->dpll)) { | |
7103 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7104 | return -EINVAL; | |
7105 | } | |
7106 | ||
7107 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7108 | ||
7109 | return 0; | |
7110 | } | |
7111 | ||
19ec6693 ACO |
7112 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7113 | struct intel_crtc_state *crtc_state) | |
7114 | { | |
7115 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7116 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7117 | const struct intel_limit *limit; |
19ec6693 ACO |
7118 | int refclk = 96000; |
7119 | ||
7120 | memset(&crtc_state->dpll_hw_state, 0, | |
7121 | sizeof(crtc_state->dpll_hw_state)); | |
7122 | ||
2d84d2b3 | 7123 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7124 | if (intel_panel_use_ssc(dev_priv)) { |
7125 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7126 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7127 | } | |
7128 | ||
7129 | if (intel_is_dual_link_lvds(dev)) | |
7130 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7131 | else | |
7132 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7133 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7134 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7135 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7136 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7137 | limit = &intel_limits_g4x_sdvo; |
7138 | } else { | |
7139 | /* The option is for other outputs */ | |
7140 | limit = &intel_limits_i9xx_sdvo; | |
7141 | } | |
7142 | ||
7143 | if (!crtc_state->clock_set && | |
7144 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7145 | refclk, NULL, &crtc_state->dpll)) { | |
7146 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7147 | return -EINVAL; | |
7148 | } | |
7149 | ||
7150 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7151 | ||
7152 | return 0; | |
7153 | } | |
7154 | ||
70e8aa21 ACO |
7155 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7156 | struct intel_crtc_state *crtc_state) | |
7157 | { | |
7158 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7159 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7160 | const struct intel_limit *limit; |
70e8aa21 ACO |
7161 | int refclk = 96000; |
7162 | ||
7163 | memset(&crtc_state->dpll_hw_state, 0, | |
7164 | sizeof(crtc_state->dpll_hw_state)); | |
7165 | ||
2d84d2b3 | 7166 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7167 | if (intel_panel_use_ssc(dev_priv)) { |
7168 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7169 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7170 | } | |
7171 | ||
7172 | limit = &intel_limits_pineview_lvds; | |
7173 | } else { | |
7174 | limit = &intel_limits_pineview_sdvo; | |
7175 | } | |
7176 | ||
7177 | if (!crtc_state->clock_set && | |
7178 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7179 | refclk, NULL, &crtc_state->dpll)) { | |
7180 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7181 | return -EINVAL; | |
7182 | } | |
7183 | ||
7184 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7185 | ||
7186 | return 0; | |
7187 | } | |
7188 | ||
190f68c5 ACO |
7189 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7190 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7191 | { |
c7653199 | 7192 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7193 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7194 | const struct intel_limit *limit; |
81c97f52 | 7195 | int refclk = 96000; |
79e53945 | 7196 | |
dd3cd74a ACO |
7197 | memset(&crtc_state->dpll_hw_state, 0, |
7198 | sizeof(crtc_state->dpll_hw_state)); | |
7199 | ||
2d84d2b3 | 7200 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7201 | if (intel_panel_use_ssc(dev_priv)) { |
7202 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7203 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7204 | } | |
43565a06 | 7205 | |
70e8aa21 ACO |
7206 | limit = &intel_limits_i9xx_lvds; |
7207 | } else { | |
7208 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7209 | } |
79e53945 | 7210 | |
70e8aa21 ACO |
7211 | if (!crtc_state->clock_set && |
7212 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7213 | refclk, NULL, &crtc_state->dpll)) { | |
7214 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7215 | return -EINVAL; | |
f47709a9 | 7216 | } |
7026d4ac | 7217 | |
81c97f52 | 7218 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7219 | |
c8f7a0db | 7220 | return 0; |
f564048e EA |
7221 | } |
7222 | ||
65b3d6a9 ACO |
7223 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7224 | struct intel_crtc_state *crtc_state) | |
7225 | { | |
7226 | int refclk = 100000; | |
1b6f4958 | 7227 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7228 | |
7229 | memset(&crtc_state->dpll_hw_state, 0, | |
7230 | sizeof(crtc_state->dpll_hw_state)); | |
7231 | ||
65b3d6a9 ACO |
7232 | if (!crtc_state->clock_set && |
7233 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7234 | refclk, NULL, &crtc_state->dpll)) { | |
7235 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7236 | return -EINVAL; | |
7237 | } | |
7238 | ||
7239 | chv_compute_dpll(crtc, crtc_state); | |
7240 | ||
7241 | return 0; | |
7242 | } | |
7243 | ||
7244 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7245 | struct intel_crtc_state *crtc_state) | |
7246 | { | |
7247 | int refclk = 100000; | |
1b6f4958 | 7248 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7249 | |
7250 | memset(&crtc_state->dpll_hw_state, 0, | |
7251 | sizeof(crtc_state->dpll_hw_state)); | |
7252 | ||
65b3d6a9 ACO |
7253 | if (!crtc_state->clock_set && |
7254 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7255 | refclk, NULL, &crtc_state->dpll)) { | |
7256 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7257 | return -EINVAL; | |
7258 | } | |
7259 | ||
7260 | vlv_compute_dpll(crtc, crtc_state); | |
7261 | ||
7262 | return 0; | |
7263 | } | |
7264 | ||
2fa2fe9a | 7265 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7266 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 7267 | { |
6315b5d3 | 7268 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
7269 | uint32_t tmp; |
7270 | ||
50a0bc90 TU |
7271 | if (INTEL_GEN(dev_priv) <= 3 && |
7272 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
7273 | return; |
7274 | ||
2fa2fe9a | 7275 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7276 | if (!(tmp & PFIT_ENABLE)) |
7277 | return; | |
2fa2fe9a | 7278 | |
06922821 | 7279 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 7280 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
7281 | if (crtc->pipe != PIPE_B) |
7282 | return; | |
2fa2fe9a DV |
7283 | } else { |
7284 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7285 | return; | |
7286 | } | |
7287 | ||
06922821 | 7288 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7289 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7290 | } |
7291 | ||
acbec814 | 7292 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7293 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7294 | { |
7295 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7296 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 7297 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 7298 | struct dpll clock; |
acbec814 | 7299 | u32 mdiv; |
662c6ecb | 7300 | int refclk = 100000; |
acbec814 | 7301 | |
b521973b VS |
7302 | /* In case of DSI, DPLL will not be used */ |
7303 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
7304 | return; |
7305 | ||
a580516d | 7306 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7307 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7308 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7309 | |
7310 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7311 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7312 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7313 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7314 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7315 | ||
dccbea3b | 7316 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7317 | } |
7318 | ||
5724dbd1 DL |
7319 | static void |
7320 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7321 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7322 | { |
7323 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7324 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
7325 | u32 val, base, offset; |
7326 | int pipe = crtc->pipe, plane = crtc->plane; | |
7327 | int fourcc, pixel_format; | |
6761dd31 | 7328 | unsigned int aligned_height; |
b113d5ee | 7329 | struct drm_framebuffer *fb; |
1b842c89 | 7330 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7331 | |
42a7b088 DL |
7332 | val = I915_READ(DSPCNTR(plane)); |
7333 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7334 | return; | |
7335 | ||
d9806c9f | 7336 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7337 | if (!intel_fb) { |
1ad292b5 JB |
7338 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7339 | return; | |
7340 | } | |
7341 | ||
1b842c89 DL |
7342 | fb = &intel_fb->base; |
7343 | ||
d2e9f5fc VS |
7344 | fb->dev = dev; |
7345 | ||
6315b5d3 | 7346 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 7347 | if (val & DISPPLANE_TILED) { |
49af449b | 7348 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 7349 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
7350 | } |
7351 | } | |
1ad292b5 JB |
7352 | |
7353 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7354 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 7355 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 7356 | |
6315b5d3 | 7357 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 7358 | if (plane_config->tiling) |
1ad292b5 JB |
7359 | offset = I915_READ(DSPTILEOFF(plane)); |
7360 | else | |
7361 | offset = I915_READ(DSPLINOFF(plane)); | |
7362 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7363 | } else { | |
7364 | base = I915_READ(DSPADDR(plane)); | |
7365 | } | |
7366 | plane_config->base = base; | |
7367 | ||
7368 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7369 | fb->width = ((val >> 16) & 0xfff) + 1; |
7370 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7371 | |
7372 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7373 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7374 | |
d88c4afd | 7375 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1ad292b5 | 7376 | |
f37b5c2b | 7377 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7378 | |
2844a921 DL |
7379 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7380 | pipe_name(pipe), plane, fb->width, fb->height, | |
272725c7 | 7381 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 7382 | plane_config->size); |
1ad292b5 | 7383 | |
2d14030b | 7384 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7385 | } |
7386 | ||
70b23a98 | 7387 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7388 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7389 | { |
7390 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7391 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
7392 | int pipe = pipe_config->cpu_transcoder; |
7393 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 7394 | struct dpll clock; |
0d7b6b11 | 7395 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
7396 | int refclk = 100000; |
7397 | ||
b521973b VS |
7398 | /* In case of DSI, DPLL will not be used */ |
7399 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7400 | return; | |
7401 | ||
a580516d | 7402 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7403 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7404 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7405 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7406 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 7407 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 7408 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7409 | |
7410 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
7411 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7412 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
7413 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
7414 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7415 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7416 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7417 | ||
dccbea3b | 7418 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
7419 | } |
7420 | ||
0e8ffe1b | 7421 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7422 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 7423 | { |
6315b5d3 | 7424 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 7425 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 7426 | uint32_t tmp; |
1729050e | 7427 | bool ret; |
0e8ffe1b | 7428 | |
1729050e ID |
7429 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
7430 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
7431 | return false; |
7432 | ||
e143a21c | 7433 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 7434 | pipe_config->shared_dpll = NULL; |
eccb140b | 7435 | |
1729050e ID |
7436 | ret = false; |
7437 | ||
0e8ffe1b DV |
7438 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7439 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 7440 | goto out; |
0e8ffe1b | 7441 | |
9beb5fea TU |
7442 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7443 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
7444 | switch (tmp & PIPECONF_BPC_MASK) { |
7445 | case PIPECONF_6BPC: | |
7446 | pipe_config->pipe_bpp = 18; | |
7447 | break; | |
7448 | case PIPECONF_8BPC: | |
7449 | pipe_config->pipe_bpp = 24; | |
7450 | break; | |
7451 | case PIPECONF_10BPC: | |
7452 | pipe_config->pipe_bpp = 30; | |
7453 | break; | |
7454 | default: | |
7455 | break; | |
7456 | } | |
7457 | } | |
7458 | ||
920a14b2 | 7459 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7460 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
7461 | pipe_config->limited_color_range = true; |
7462 | ||
6315b5d3 | 7463 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
7464 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
7465 | ||
1bd1bd80 | 7466 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 7467 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 7468 | |
2fa2fe9a DV |
7469 | i9xx_get_pfit_config(crtc, pipe_config); |
7470 | ||
6315b5d3 | 7471 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 7472 | /* No way to read it out on pipes B and C */ |
920a14b2 | 7473 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
7474 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
7475 | else | |
7476 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
7477 | pipe_config->pixel_multiplier = |
7478 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7479 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7480 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 7481 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 7482 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
7483 | tmp = I915_READ(DPLL(crtc->pipe)); |
7484 | pipe_config->pixel_multiplier = | |
7485 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7486 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7487 | } else { | |
7488 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7489 | * port and will be fixed up in the encoder->get_config | |
7490 | * function. */ | |
7491 | pipe_config->pixel_multiplier = 1; | |
7492 | } | |
8bcc2795 | 7493 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 7494 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
7495 | /* |
7496 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7497 | * on 830. Filter it out here so that we don't | |
7498 | * report errors due to that. | |
7499 | */ | |
50a0bc90 | 7500 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
7501 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
7502 | ||
8bcc2795 DV |
7503 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7504 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7505 | } else { |
7506 | /* Mask out read-only status bits. */ | |
7507 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7508 | DPLL_PORTC_READY_MASK | | |
7509 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7510 | } |
6c49f241 | 7511 | |
920a14b2 | 7512 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 7513 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 7514 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
7515 | vlv_crtc_clock_get(crtc, pipe_config); |
7516 | else | |
7517 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7518 | |
0f64614d VS |
7519 | /* |
7520 | * Normally the dotclock is filled in by the encoder .get_config() | |
7521 | * but in case the pipe is enabled w/o any ports we need a sane | |
7522 | * default. | |
7523 | */ | |
7524 | pipe_config->base.adjusted_mode.crtc_clock = | |
7525 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
7526 | ||
1729050e ID |
7527 | ret = true; |
7528 | ||
7529 | out: | |
7530 | intel_display_power_put(dev_priv, power_domain); | |
7531 | ||
7532 | return ret; | |
0e8ffe1b DV |
7533 | } |
7534 | ||
c39055b0 | 7535 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 7536 | { |
13d83a67 | 7537 | struct intel_encoder *encoder; |
1c1a24d2 | 7538 | int i; |
74cfd7ac | 7539 | u32 val, final; |
13d83a67 | 7540 | bool has_lvds = false; |
199e5d79 | 7541 | bool has_cpu_edp = false; |
199e5d79 | 7542 | bool has_panel = false; |
99eb6a01 KP |
7543 | bool has_ck505 = false; |
7544 | bool can_ssc = false; | |
1c1a24d2 | 7545 | bool using_ssc_source = false; |
13d83a67 JB |
7546 | |
7547 | /* We need to take the global config into account */ | |
c39055b0 | 7548 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
7549 | switch (encoder->type) { |
7550 | case INTEL_OUTPUT_LVDS: | |
7551 | has_panel = true; | |
7552 | has_lvds = true; | |
7553 | break; | |
7554 | case INTEL_OUTPUT_EDP: | |
7555 | has_panel = true; | |
2de6905f | 7556 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7557 | has_cpu_edp = true; |
7558 | break; | |
6847d71b PZ |
7559 | default: |
7560 | break; | |
13d83a67 JB |
7561 | } |
7562 | } | |
7563 | ||
6e266956 | 7564 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 7565 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7566 | can_ssc = has_ck505; |
7567 | } else { | |
7568 | has_ck505 = false; | |
7569 | can_ssc = true; | |
7570 | } | |
7571 | ||
1c1a24d2 L |
7572 | /* Check if any DPLLs are using the SSC source */ |
7573 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
7574 | u32 temp = I915_READ(PCH_DPLL(i)); | |
7575 | ||
7576 | if (!(temp & DPLL_VCO_ENABLE)) | |
7577 | continue; | |
7578 | ||
7579 | if ((temp & PLL_REF_INPUT_MASK) == | |
7580 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7581 | using_ssc_source = true; | |
7582 | break; | |
7583 | } | |
7584 | } | |
7585 | ||
7586 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
7587 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
7588 | |
7589 | /* Ironlake: try to setup display ref clock before DPLL | |
7590 | * enabling. This is only under driver's control after | |
7591 | * PCH B stepping, previous chipset stepping should be | |
7592 | * ignoring this setting. | |
7593 | */ | |
74cfd7ac CW |
7594 | val = I915_READ(PCH_DREF_CONTROL); |
7595 | ||
7596 | /* As we must carefully and slowly disable/enable each source in turn, | |
7597 | * compute the final state we want first and check if we need to | |
7598 | * make any changes at all. | |
7599 | */ | |
7600 | final = val; | |
7601 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7602 | if (has_ck505) | |
7603 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7604 | else | |
7605 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7606 | ||
8c07eb68 | 7607 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 7608 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 7609 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
7610 | |
7611 | if (has_panel) { | |
7612 | final |= DREF_SSC_SOURCE_ENABLE; | |
7613 | ||
7614 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7615 | final |= DREF_SSC1_ENABLE; | |
7616 | ||
7617 | if (has_cpu_edp) { | |
7618 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7619 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7620 | else | |
7621 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7622 | } else | |
7623 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
7624 | } else if (using_ssc_source) { |
7625 | final |= DREF_SSC_SOURCE_ENABLE; | |
7626 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
7627 | } |
7628 | ||
7629 | if (final == val) | |
7630 | return; | |
7631 | ||
13d83a67 | 7632 | /* Always enable nonspread source */ |
74cfd7ac | 7633 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7634 | |
99eb6a01 | 7635 | if (has_ck505) |
74cfd7ac | 7636 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7637 | else |
74cfd7ac | 7638 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7639 | |
199e5d79 | 7640 | if (has_panel) { |
74cfd7ac CW |
7641 | val &= ~DREF_SSC_SOURCE_MASK; |
7642 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7643 | |
199e5d79 | 7644 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7645 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7646 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7647 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7648 | } else |
74cfd7ac | 7649 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7650 | |
7651 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7652 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7653 | POSTING_READ(PCH_DREF_CONTROL); |
7654 | udelay(200); | |
7655 | ||
74cfd7ac | 7656 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7657 | |
7658 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7659 | if (has_cpu_edp) { |
99eb6a01 | 7660 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7661 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7662 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7663 | } else |
74cfd7ac | 7664 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7665 | } else |
74cfd7ac | 7666 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7667 | |
74cfd7ac | 7668 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7669 | POSTING_READ(PCH_DREF_CONTROL); |
7670 | udelay(200); | |
7671 | } else { | |
1c1a24d2 | 7672 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 7673 | |
74cfd7ac | 7674 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7675 | |
7676 | /* Turn off CPU output */ | |
74cfd7ac | 7677 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7678 | |
74cfd7ac | 7679 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7680 | POSTING_READ(PCH_DREF_CONTROL); |
7681 | udelay(200); | |
7682 | ||
1c1a24d2 L |
7683 | if (!using_ssc_source) { |
7684 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 7685 | |
1c1a24d2 L |
7686 | /* Turn off the SSC source */ |
7687 | val &= ~DREF_SSC_SOURCE_MASK; | |
7688 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 7689 | |
1c1a24d2 L |
7690 | /* Turn off SSC1 */ |
7691 | val &= ~DREF_SSC1_ENABLE; | |
7692 | ||
7693 | I915_WRITE(PCH_DREF_CONTROL, val); | |
7694 | POSTING_READ(PCH_DREF_CONTROL); | |
7695 | udelay(200); | |
7696 | } | |
13d83a67 | 7697 | } |
74cfd7ac CW |
7698 | |
7699 | BUG_ON(val != final); | |
13d83a67 JB |
7700 | } |
7701 | ||
f31f2d55 | 7702 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7703 | { |
f31f2d55 | 7704 | uint32_t tmp; |
dde86e2d | 7705 | |
0ff066a9 PZ |
7706 | tmp = I915_READ(SOUTH_CHICKEN2); |
7707 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7708 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7709 | |
cf3598c2 ID |
7710 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
7711 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 7712 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 7713 | |
0ff066a9 PZ |
7714 | tmp = I915_READ(SOUTH_CHICKEN2); |
7715 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7716 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7717 | |
cf3598c2 ID |
7718 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
7719 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 7720 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
7721 | } |
7722 | ||
7723 | /* WaMPhyProgramming:hsw */ | |
7724 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7725 | { | |
7726 | uint32_t tmp; | |
dde86e2d PZ |
7727 | |
7728 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7729 | tmp &= ~(0xFF << 24); | |
7730 | tmp |= (0x12 << 24); | |
7731 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7732 | ||
dde86e2d PZ |
7733 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7734 | tmp |= (1 << 11); | |
7735 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7736 | ||
7737 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7738 | tmp |= (1 << 11); | |
7739 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7740 | ||
dde86e2d PZ |
7741 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7742 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7743 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7744 | ||
7745 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7746 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7747 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7748 | ||
0ff066a9 PZ |
7749 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7750 | tmp &= ~(7 << 13); | |
7751 | tmp |= (5 << 13); | |
7752 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7753 | |
0ff066a9 PZ |
7754 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7755 | tmp &= ~(7 << 13); | |
7756 | tmp |= (5 << 13); | |
7757 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7758 | |
7759 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7760 | tmp &= ~0xFF; | |
7761 | tmp |= 0x1C; | |
7762 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7763 | ||
7764 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7765 | tmp &= ~0xFF; | |
7766 | tmp |= 0x1C; | |
7767 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7768 | ||
7769 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7770 | tmp &= ~(0xFF << 16); | |
7771 | tmp |= (0x1C << 16); | |
7772 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7773 | ||
7774 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7775 | tmp &= ~(0xFF << 16); | |
7776 | tmp |= (0x1C << 16); | |
7777 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7778 | ||
0ff066a9 PZ |
7779 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7780 | tmp |= (1 << 27); | |
7781 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7782 | |
0ff066a9 PZ |
7783 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7784 | tmp |= (1 << 27); | |
7785 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7786 | |
0ff066a9 PZ |
7787 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7788 | tmp &= ~(0xF << 28); | |
7789 | tmp |= (4 << 28); | |
7790 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7791 | |
0ff066a9 PZ |
7792 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7793 | tmp &= ~(0xF << 28); | |
7794 | tmp |= (4 << 28); | |
7795 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7796 | } |
7797 | ||
2fa86a1f PZ |
7798 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7799 | * Programming" based on the parameters passed: | |
7800 | * - Sequence to enable CLKOUT_DP | |
7801 | * - Sequence to enable CLKOUT_DP without spread | |
7802 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7803 | */ | |
c39055b0 ACO |
7804 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
7805 | bool with_spread, bool with_fdi) | |
f31f2d55 | 7806 | { |
2fa86a1f PZ |
7807 | uint32_t reg, tmp; |
7808 | ||
7809 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7810 | with_spread = true; | |
4f8036a2 TU |
7811 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
7812 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 7813 | with_fdi = false; |
f31f2d55 | 7814 | |
a580516d | 7815 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
7816 | |
7817 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7818 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7819 | tmp |= SBI_SSCCTL_PATHALT; | |
7820 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7821 | ||
7822 | udelay(24); | |
7823 | ||
2fa86a1f PZ |
7824 | if (with_spread) { |
7825 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7826 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7827 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7828 | |
2fa86a1f PZ |
7829 | if (with_fdi) { |
7830 | lpt_reset_fdi_mphy(dev_priv); | |
7831 | lpt_program_fdi_mphy(dev_priv); | |
7832 | } | |
7833 | } | |
dde86e2d | 7834 | |
4f8036a2 | 7835 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
7836 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7837 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7838 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 7839 | |
a580516d | 7840 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
7841 | } |
7842 | ||
47701c3b | 7843 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 7844 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 7845 | { |
47701c3b PZ |
7846 | uint32_t reg, tmp; |
7847 | ||
a580516d | 7848 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 7849 | |
4f8036a2 | 7850 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
7851 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7852 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7853 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7854 | ||
7855 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7856 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7857 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7858 | tmp |= SBI_SSCCTL_PATHALT; | |
7859 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7860 | udelay(32); | |
7861 | } | |
7862 | tmp |= SBI_SSCCTL_DISABLE; | |
7863 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7864 | } | |
7865 | ||
a580516d | 7866 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
7867 | } |
7868 | ||
f7be2c21 VS |
7869 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
7870 | ||
7871 | static const uint16_t sscdivintphase[] = { | |
7872 | [BEND_IDX( 50)] = 0x3B23, | |
7873 | [BEND_IDX( 45)] = 0x3B23, | |
7874 | [BEND_IDX( 40)] = 0x3C23, | |
7875 | [BEND_IDX( 35)] = 0x3C23, | |
7876 | [BEND_IDX( 30)] = 0x3D23, | |
7877 | [BEND_IDX( 25)] = 0x3D23, | |
7878 | [BEND_IDX( 20)] = 0x3E23, | |
7879 | [BEND_IDX( 15)] = 0x3E23, | |
7880 | [BEND_IDX( 10)] = 0x3F23, | |
7881 | [BEND_IDX( 5)] = 0x3F23, | |
7882 | [BEND_IDX( 0)] = 0x0025, | |
7883 | [BEND_IDX( -5)] = 0x0025, | |
7884 | [BEND_IDX(-10)] = 0x0125, | |
7885 | [BEND_IDX(-15)] = 0x0125, | |
7886 | [BEND_IDX(-20)] = 0x0225, | |
7887 | [BEND_IDX(-25)] = 0x0225, | |
7888 | [BEND_IDX(-30)] = 0x0325, | |
7889 | [BEND_IDX(-35)] = 0x0325, | |
7890 | [BEND_IDX(-40)] = 0x0425, | |
7891 | [BEND_IDX(-45)] = 0x0425, | |
7892 | [BEND_IDX(-50)] = 0x0525, | |
7893 | }; | |
7894 | ||
7895 | /* | |
7896 | * Bend CLKOUT_DP | |
7897 | * steps -50 to 50 inclusive, in steps of 5 | |
7898 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
7899 | * change in clock period = -(steps / 10) * 5.787 ps | |
7900 | */ | |
7901 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
7902 | { | |
7903 | uint32_t tmp; | |
7904 | int idx = BEND_IDX(steps); | |
7905 | ||
7906 | if (WARN_ON(steps % 5 != 0)) | |
7907 | return; | |
7908 | ||
7909 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
7910 | return; | |
7911 | ||
7912 | mutex_lock(&dev_priv->sb_lock); | |
7913 | ||
7914 | if (steps % 10 != 0) | |
7915 | tmp = 0xAAAAAAAB; | |
7916 | else | |
7917 | tmp = 0x00000000; | |
7918 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
7919 | ||
7920 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
7921 | tmp &= 0xffff0000; | |
7922 | tmp |= sscdivintphase[idx]; | |
7923 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
7924 | ||
7925 | mutex_unlock(&dev_priv->sb_lock); | |
7926 | } | |
7927 | ||
7928 | #undef BEND_IDX | |
7929 | ||
c39055b0 | 7930 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 7931 | { |
bf8fa3d3 PZ |
7932 | struct intel_encoder *encoder; |
7933 | bool has_vga = false; | |
7934 | ||
c39055b0 | 7935 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
7936 | switch (encoder->type) { |
7937 | case INTEL_OUTPUT_ANALOG: | |
7938 | has_vga = true; | |
7939 | break; | |
6847d71b PZ |
7940 | default: |
7941 | break; | |
bf8fa3d3 PZ |
7942 | } |
7943 | } | |
7944 | ||
f7be2c21 | 7945 | if (has_vga) { |
c39055b0 ACO |
7946 | lpt_bend_clkout_dp(dev_priv, 0); |
7947 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 7948 | } else { |
c39055b0 | 7949 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 7950 | } |
bf8fa3d3 PZ |
7951 | } |
7952 | ||
dde86e2d PZ |
7953 | /* |
7954 | * Initialize reference clocks when the driver loads | |
7955 | */ | |
c39055b0 | 7956 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 7957 | { |
6e266956 | 7958 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 7959 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 7960 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 7961 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
7962 | } |
7963 | ||
6ff93609 | 7964 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7965 | { |
fac5e23e | 7966 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
7967 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7968 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7969 | uint32_t val; |
7970 | ||
78114071 | 7971 | val = 0; |
c8203565 | 7972 | |
6e3c9717 | 7973 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7974 | case 18: |
dfd07d72 | 7975 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7976 | break; |
7977 | case 24: | |
dfd07d72 | 7978 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7979 | break; |
7980 | case 30: | |
dfd07d72 | 7981 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7982 | break; |
7983 | case 36: | |
dfd07d72 | 7984 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7985 | break; |
7986 | default: | |
cc769b62 PZ |
7987 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7988 | BUG(); | |
c8203565 PZ |
7989 | } |
7990 | ||
6e3c9717 | 7991 | if (intel_crtc->config->dither) |
c8203565 PZ |
7992 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7993 | ||
6e3c9717 | 7994 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7995 | val |= PIPECONF_INTERLACED_ILK; |
7996 | else | |
7997 | val |= PIPECONF_PROGRESSIVE; | |
7998 | ||
6e3c9717 | 7999 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8000 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8001 | |
c8203565 PZ |
8002 | I915_WRITE(PIPECONF(pipe), val); |
8003 | POSTING_READ(PIPECONF(pipe)); | |
8004 | } | |
8005 | ||
6ff93609 | 8006 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8007 | { |
fac5e23e | 8008 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8009 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8010 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8011 | u32 val = 0; |
ee2b0b38 | 8012 | |
391bf048 | 8013 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8014 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8015 | ||
6e3c9717 | 8016 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8017 | val |= PIPECONF_INTERLACED_ILK; |
8018 | else | |
8019 | val |= PIPECONF_PROGRESSIVE; | |
8020 | ||
702e7a56 PZ |
8021 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8022 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8023 | } |
8024 | ||
391bf048 JN |
8025 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8026 | { | |
fac5e23e | 8027 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8028 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8029 | |
391bf048 JN |
8030 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8031 | u32 val = 0; | |
756f85cf | 8032 | |
6e3c9717 | 8033 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8034 | case 18: |
8035 | val |= PIPEMISC_DITHER_6_BPC; | |
8036 | break; | |
8037 | case 24: | |
8038 | val |= PIPEMISC_DITHER_8_BPC; | |
8039 | break; | |
8040 | case 30: | |
8041 | val |= PIPEMISC_DITHER_10_BPC; | |
8042 | break; | |
8043 | case 36: | |
8044 | val |= PIPEMISC_DITHER_12_BPC; | |
8045 | break; | |
8046 | default: | |
8047 | /* Case prevented by pipe_config_set_bpp. */ | |
8048 | BUG(); | |
8049 | } | |
8050 | ||
6e3c9717 | 8051 | if (intel_crtc->config->dither) |
756f85cf PZ |
8052 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8053 | ||
391bf048 | 8054 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8055 | } |
ee2b0b38 PZ |
8056 | } |
8057 | ||
d4b1931c PZ |
8058 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8059 | { | |
8060 | /* | |
8061 | * Account for spread spectrum to avoid | |
8062 | * oversubscribing the link. Max center spread | |
8063 | * is 2.5%; use 5% for safety's sake. | |
8064 | */ | |
8065 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8066 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8067 | } |
8068 | ||
7429e9d4 | 8069 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8070 | { |
7429e9d4 | 8071 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8072 | } |
8073 | ||
b75ca6f6 ACO |
8074 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8075 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8076 | struct dpll *reduced_clock) |
79e53945 | 8077 | { |
de13a2e3 | 8078 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8079 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8080 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8081 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8082 | int factor; |
79e53945 | 8083 | |
c1858123 | 8084 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8085 | factor = 21; |
3d6e9ee0 | 8086 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8087 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8088 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 8089 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8090 | factor = 25; |
190f68c5 | 8091 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8092 | factor = 20; |
c1858123 | 8093 | |
b75ca6f6 ACO |
8094 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8095 | ||
190f68c5 | 8096 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8097 | fp |= FP_CB_TUNE; |
8098 | ||
8099 | if (reduced_clock) { | |
8100 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8101 | |
b75ca6f6 ACO |
8102 | if (reduced_clock->m < factor * reduced_clock->n) |
8103 | fp2 |= FP_CB_TUNE; | |
8104 | } else { | |
8105 | fp2 = fp; | |
8106 | } | |
9a7c7890 | 8107 | |
5eddb70b | 8108 | dpll = 0; |
2c07245f | 8109 | |
3d6e9ee0 | 8110 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8111 | dpll |= DPLLB_MODE_LVDS; |
8112 | else | |
8113 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8114 | |
190f68c5 | 8115 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8116 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8117 | |
3d6e9ee0 VS |
8118 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8119 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8120 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8121 | |
37a5650b | 8122 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8123 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8124 | |
7d7f8633 VS |
8125 | /* |
8126 | * The high speed IO clock is only really required for | |
8127 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
8128 | * possible to share the DPLL between CRT and HDMI. Enabling | |
8129 | * the clock needlessly does no real harm, except use up a | |
8130 | * bit of power potentially. | |
8131 | * | |
8132 | * We'll limit this to IVB with 3 pipes, since it has only two | |
8133 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
8134 | * driving PCH ports at the same time. On SNB we could do this, | |
8135 | * and potentially avoid enabling the second DPLL, but it's not | |
8136 | * clear if it''s a win or loss power wise. No point in doing | |
8137 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
8138 | */ | |
8139 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
8140 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
8141 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8142 | ||
a07d6787 | 8143 | /* compute bitmask from p1 value */ |
190f68c5 | 8144 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8145 | /* also FPA1 */ |
190f68c5 | 8146 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8147 | |
190f68c5 | 8148 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8149 | case 5: |
8150 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8151 | break; | |
8152 | case 7: | |
8153 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8154 | break; | |
8155 | case 10: | |
8156 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8157 | break; | |
8158 | case 14: | |
8159 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8160 | break; | |
79e53945 JB |
8161 | } |
8162 | ||
3d6e9ee0 VS |
8163 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8164 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8165 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8166 | else |
8167 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8168 | ||
b75ca6f6 ACO |
8169 | dpll |= DPLL_VCO_ENABLE; |
8170 | ||
8171 | crtc_state->dpll_hw_state.dpll = dpll; | |
8172 | crtc_state->dpll_hw_state.fp0 = fp; | |
8173 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8174 | } |
8175 | ||
190f68c5 ACO |
8176 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8177 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8178 | { |
997c030c | 8179 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8180 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 8181 | struct dpll reduced_clock; |
7ed9f894 | 8182 | bool has_reduced_clock = false; |
e2b78267 | 8183 | struct intel_shared_dpll *pll; |
1b6f4958 | 8184 | const struct intel_limit *limit; |
997c030c | 8185 | int refclk = 120000; |
de13a2e3 | 8186 | |
dd3cd74a ACO |
8187 | memset(&crtc_state->dpll_hw_state, 0, |
8188 | sizeof(crtc_state->dpll_hw_state)); | |
8189 | ||
ded220e2 ACO |
8190 | crtc->lowfreq_avail = false; |
8191 | ||
8192 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8193 | if (!crtc_state->has_pch_encoder) | |
8194 | return 0; | |
79e53945 | 8195 | |
2d84d2b3 | 8196 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8197 | if (intel_panel_use_ssc(dev_priv)) { |
8198 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8199 | dev_priv->vbt.lvds_ssc_freq); | |
8200 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8201 | } | |
8202 | ||
8203 | if (intel_is_dual_link_lvds(dev)) { | |
8204 | if (refclk == 100000) | |
8205 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8206 | else | |
8207 | limit = &intel_limits_ironlake_dual_lvds; | |
8208 | } else { | |
8209 | if (refclk == 100000) | |
8210 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8211 | else | |
8212 | limit = &intel_limits_ironlake_single_lvds; | |
8213 | } | |
8214 | } else { | |
8215 | limit = &intel_limits_ironlake_dac; | |
8216 | } | |
8217 | ||
364ee29d | 8218 | if (!crtc_state->clock_set && |
997c030c ACO |
8219 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8220 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8221 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8222 | return -EINVAL; | |
f47709a9 | 8223 | } |
79e53945 | 8224 | |
b75ca6f6 ACO |
8225 | ironlake_compute_dpll(crtc, crtc_state, |
8226 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 8227 | |
ded220e2 ACO |
8228 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
8229 | if (pll == NULL) { | |
8230 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8231 | pipe_name(crtc->pipe)); | |
8232 | return -EINVAL; | |
3fb37703 | 8233 | } |
79e53945 | 8234 | |
2d84d2b3 | 8235 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 8236 | has_reduced_clock) |
c7653199 | 8237 | crtc->lowfreq_avail = true; |
e2b78267 | 8238 | |
c8f7a0db | 8239 | return 0; |
79e53945 JB |
8240 | } |
8241 | ||
eb14cb74 VS |
8242 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8243 | struct intel_link_m_n *m_n) | |
8244 | { | |
8245 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8246 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
8247 | enum pipe pipe = crtc->pipe; |
8248 | ||
8249 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8250 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8251 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8252 | & ~TU_SIZE_MASK; | |
8253 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8254 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8255 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8256 | } | |
8257 | ||
8258 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8259 | enum transcoder transcoder, | |
b95af8be VK |
8260 | struct intel_link_m_n *m_n, |
8261 | struct intel_link_m_n *m2_n2) | |
72419203 | 8262 | { |
6315b5d3 | 8263 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 8264 | enum pipe pipe = crtc->pipe; |
72419203 | 8265 | |
6315b5d3 | 8266 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
8267 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
8268 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8269 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8270 | & ~TU_SIZE_MASK; | |
8271 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8272 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8273 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8274 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8275 | * gen < 8) and if DRRS is supported (to make sure the | |
8276 | * registers are not unnecessarily read). | |
8277 | */ | |
6315b5d3 | 8278 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 8279 | crtc->config->has_drrs) { |
b95af8be VK |
8280 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8281 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8282 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8283 | & ~TU_SIZE_MASK; | |
8284 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8285 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8286 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8287 | } | |
eb14cb74 VS |
8288 | } else { |
8289 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8290 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8291 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8292 | & ~TU_SIZE_MASK; | |
8293 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8294 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8295 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8296 | } | |
8297 | } | |
8298 | ||
8299 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8300 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8301 | { |
681a8504 | 8302 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8303 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8304 | else | |
8305 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8306 | &pipe_config->dp_m_n, |
8307 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8308 | } |
72419203 | 8309 | |
eb14cb74 | 8310 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8311 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8312 | { |
8313 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8314 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8315 | } |
8316 | ||
bd2e244f | 8317 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8318 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8319 | { |
8320 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8321 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
8322 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8323 | uint32_t ps_ctrl = 0; | |
8324 | int id = -1; | |
8325 | int i; | |
bd2e244f | 8326 | |
a1b2278e CK |
8327 | /* find scaler attached to this pipe */ |
8328 | for (i = 0; i < crtc->num_scalers; i++) { | |
8329 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8330 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8331 | id = i; | |
8332 | pipe_config->pch_pfit.enabled = true; | |
8333 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8334 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8335 | break; | |
8336 | } | |
8337 | } | |
bd2e244f | 8338 | |
a1b2278e CK |
8339 | scaler_state->scaler_id = id; |
8340 | if (id >= 0) { | |
8341 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8342 | } else { | |
8343 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8344 | } |
8345 | } | |
8346 | ||
5724dbd1 DL |
8347 | static void |
8348 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8349 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8350 | { |
8351 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8352 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 8353 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8354 | int pipe = crtc->pipe; |
8355 | int fourcc, pixel_format; | |
6761dd31 | 8356 | unsigned int aligned_height; |
bc8d7dff | 8357 | struct drm_framebuffer *fb; |
1b842c89 | 8358 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8359 | |
d9806c9f | 8360 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8361 | if (!intel_fb) { |
bc8d7dff DL |
8362 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8363 | return; | |
8364 | } | |
8365 | ||
1b842c89 DL |
8366 | fb = &intel_fb->base; |
8367 | ||
d2e9f5fc VS |
8368 | fb->dev = dev; |
8369 | ||
bc8d7dff | 8370 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8371 | if (!(val & PLANE_CTL_ENABLE)) |
8372 | goto error; | |
8373 | ||
bc8d7dff DL |
8374 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8375 | fourcc = skl_format_to_fourcc(pixel_format, | |
8376 | val & PLANE_CTL_ORDER_RGBX, | |
8377 | val & PLANE_CTL_ALPHA_MASK); | |
2f3f4763 | 8378 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 8379 | |
40f46283 DL |
8380 | tiling = val & PLANE_CTL_TILED_MASK; |
8381 | switch (tiling) { | |
8382 | case PLANE_CTL_TILED_LINEAR: | |
2f075565 | 8383 | fb->modifier = DRM_FORMAT_MOD_LINEAR; |
40f46283 DL |
8384 | break; |
8385 | case PLANE_CTL_TILED_X: | |
8386 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 8387 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
8388 | break; |
8389 | case PLANE_CTL_TILED_Y: | |
bae781b2 | 8390 | fb->modifier = I915_FORMAT_MOD_Y_TILED; |
40f46283 DL |
8391 | break; |
8392 | case PLANE_CTL_TILED_YF: | |
bae781b2 | 8393 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; |
40f46283 DL |
8394 | break; |
8395 | default: | |
8396 | MISSING_CASE(tiling); | |
8397 | goto error; | |
8398 | } | |
8399 | ||
bc8d7dff DL |
8400 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8401 | plane_config->base = base; | |
8402 | ||
8403 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8404 | ||
8405 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8406 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8407 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8408 | ||
8409 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
d88c4afd | 8410 | stride_mult = intel_fb_stride_alignment(fb, 0); |
bc8d7dff DL |
8411 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8412 | ||
d88c4afd | 8413 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
bc8d7dff | 8414 | |
f37b5c2b | 8415 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8416 | |
8417 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8418 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8419 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
bc8d7dff DL |
8420 | plane_config->size); |
8421 | ||
2d14030b | 8422 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8423 | return; |
8424 | ||
8425 | error: | |
d1a3a036 | 8426 | kfree(intel_fb); |
bc8d7dff DL |
8427 | } |
8428 | ||
2fa2fe9a | 8429 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8430 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8431 | { |
8432 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8433 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8434 | uint32_t tmp; |
8435 | ||
8436 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8437 | ||
8438 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8439 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8440 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8441 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8442 | |
8443 | /* We currently do not free assignements of panel fitters on | |
8444 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8445 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 8446 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
8447 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
8448 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8449 | } | |
2fa2fe9a | 8450 | } |
79e53945 JB |
8451 | } |
8452 | ||
5724dbd1 DL |
8453 | static void |
8454 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8455 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8456 | { |
8457 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8458 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 8459 | u32 val, base, offset; |
aeee5a49 | 8460 | int pipe = crtc->pipe; |
4c6baa59 | 8461 | int fourcc, pixel_format; |
6761dd31 | 8462 | unsigned int aligned_height; |
b113d5ee | 8463 | struct drm_framebuffer *fb; |
1b842c89 | 8464 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8465 | |
42a7b088 DL |
8466 | val = I915_READ(DSPCNTR(pipe)); |
8467 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8468 | return; | |
8469 | ||
d9806c9f | 8470 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8471 | if (!intel_fb) { |
4c6baa59 JB |
8472 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8473 | return; | |
8474 | } | |
8475 | ||
1b842c89 DL |
8476 | fb = &intel_fb->base; |
8477 | ||
d2e9f5fc VS |
8478 | fb->dev = dev; |
8479 | ||
6315b5d3 | 8480 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8481 | if (val & DISPPLANE_TILED) { |
49af449b | 8482 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8483 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8484 | } |
8485 | } | |
4c6baa59 JB |
8486 | |
8487 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8488 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 8489 | fb->format = drm_format_info(fourcc); |
4c6baa59 | 8490 | |
aeee5a49 | 8491 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 8492 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 8493 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8494 | } else { |
49af449b | 8495 | if (plane_config->tiling) |
aeee5a49 | 8496 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8497 | else |
aeee5a49 | 8498 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8499 | } |
8500 | plane_config->base = base; | |
8501 | ||
8502 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8503 | fb->width = ((val >> 16) & 0xfff) + 1; |
8504 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8505 | |
8506 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8507 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8508 | |
d88c4afd | 8509 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
4c6baa59 | 8510 | |
f37b5c2b | 8511 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8512 | |
2844a921 DL |
8513 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8514 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8515 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 8516 | plane_config->size); |
b113d5ee | 8517 | |
2d14030b | 8518 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8519 | } |
8520 | ||
0e8ffe1b | 8521 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8522 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8523 | { |
8524 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8525 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8526 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8527 | uint32_t tmp; |
1729050e | 8528 | bool ret; |
0e8ffe1b | 8529 | |
1729050e ID |
8530 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8531 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
8532 | return false; |
8533 | ||
e143a21c | 8534 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8535 | pipe_config->shared_dpll = NULL; |
eccb140b | 8536 | |
1729050e | 8537 | ret = false; |
0e8ffe1b DV |
8538 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8539 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8540 | goto out; |
0e8ffe1b | 8541 | |
42571aef VS |
8542 | switch (tmp & PIPECONF_BPC_MASK) { |
8543 | case PIPECONF_6BPC: | |
8544 | pipe_config->pipe_bpp = 18; | |
8545 | break; | |
8546 | case PIPECONF_8BPC: | |
8547 | pipe_config->pipe_bpp = 24; | |
8548 | break; | |
8549 | case PIPECONF_10BPC: | |
8550 | pipe_config->pipe_bpp = 30; | |
8551 | break; | |
8552 | case PIPECONF_12BPC: | |
8553 | pipe_config->pipe_bpp = 36; | |
8554 | break; | |
8555 | default: | |
8556 | break; | |
8557 | } | |
8558 | ||
b5a9fa09 DV |
8559 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8560 | pipe_config->limited_color_range = true; | |
8561 | ||
ab9412ba | 8562 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 8563 | struct intel_shared_dpll *pll; |
8106ddbd | 8564 | enum intel_dpll_id pll_id; |
66e985c0 | 8565 | |
88adfff1 DV |
8566 | pipe_config->has_pch_encoder = true; |
8567 | ||
627eb5a3 DV |
8568 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8569 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8570 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8571 | |
8572 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8573 | |
2d1fe073 | 8574 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
8575 | /* |
8576 | * The pipe->pch transcoder and pch transcoder->pll | |
8577 | * mapping is fixed. | |
8578 | */ | |
8106ddbd | 8579 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
8580 | } else { |
8581 | tmp = I915_READ(PCH_DPLL_SEL); | |
8582 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 8583 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 8584 | else |
8106ddbd | 8585 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 8586 | } |
66e985c0 | 8587 | |
8106ddbd ACO |
8588 | pipe_config->shared_dpll = |
8589 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
8590 | pll = pipe_config->shared_dpll; | |
66e985c0 | 8591 | |
2edd6443 ACO |
8592 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8593 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8594 | |
8595 | tmp = pipe_config->dpll_hw_state.dpll; | |
8596 | pipe_config->pixel_multiplier = | |
8597 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8598 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8599 | |
8600 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8601 | } else { |
8602 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8603 | } |
8604 | ||
1bd1bd80 | 8605 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8606 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8607 | |
2fa2fe9a DV |
8608 | ironlake_get_pfit_config(crtc, pipe_config); |
8609 | ||
1729050e ID |
8610 | ret = true; |
8611 | ||
8612 | out: | |
8613 | intel_display_power_put(dev_priv, power_domain); | |
8614 | ||
8615 | return ret; | |
0e8ffe1b DV |
8616 | } |
8617 | ||
be256dc7 PZ |
8618 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8619 | { | |
91c8a326 | 8620 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 8621 | struct intel_crtc *crtc; |
be256dc7 | 8622 | |
d3fcc808 | 8623 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8624 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8625 | pipe_name(crtc->pipe)); |
8626 | ||
e2c719b7 RC |
8627 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8628 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
8629 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
8630 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 8631 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 8632 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 8633 | "CPU PWM1 enabled\n"); |
772c2a51 | 8634 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 8635 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8636 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8637 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8638 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8639 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8640 | "Utility pin enabled\n"); |
e2c719b7 | 8641 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8642 | |
9926ada1 PZ |
8643 | /* |
8644 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8645 | * interrupts remain enabled. We used to check for that, but since it's | |
8646 | * gen-specific and since we only disable LCPLL after we fully disable | |
8647 | * the interrupts, the check below should be enough. | |
8648 | */ | |
e2c719b7 | 8649 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8650 | } |
8651 | ||
9ccd5aeb PZ |
8652 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8653 | { | |
772c2a51 | 8654 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
8655 | return I915_READ(D_COMP_HSW); |
8656 | else | |
8657 | return I915_READ(D_COMP_BDW); | |
8658 | } | |
8659 | ||
3c4c9b81 PZ |
8660 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8661 | { | |
772c2a51 | 8662 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
8663 | mutex_lock(&dev_priv->rps.hw_lock); |
8664 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8665 | val)) | |
79cf219a | 8666 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8667 | mutex_unlock(&dev_priv->rps.hw_lock); |
8668 | } else { | |
9ccd5aeb PZ |
8669 | I915_WRITE(D_COMP_BDW, val); |
8670 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8671 | } |
be256dc7 PZ |
8672 | } |
8673 | ||
8674 | /* | |
8675 | * This function implements pieces of two sequences from BSpec: | |
8676 | * - Sequence for display software to disable LCPLL | |
8677 | * - Sequence for display software to allow package C8+ | |
8678 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8679 | * register. Callers should take care of disabling all the display engine | |
8680 | * functions, doing the mode unset, fixing interrupts, etc. | |
8681 | */ | |
6ff58d53 PZ |
8682 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8683 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8684 | { |
8685 | uint32_t val; | |
8686 | ||
8687 | assert_can_disable_lcpll(dev_priv); | |
8688 | ||
8689 | val = I915_READ(LCPLL_CTL); | |
8690 | ||
8691 | if (switch_to_fclk) { | |
8692 | val |= LCPLL_CD_SOURCE_FCLK; | |
8693 | I915_WRITE(LCPLL_CTL, val); | |
8694 | ||
f53dd63f ID |
8695 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
8696 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
8697 | DRM_ERROR("Switching to FCLK failed\n"); |
8698 | ||
8699 | val = I915_READ(LCPLL_CTL); | |
8700 | } | |
8701 | ||
8702 | val |= LCPLL_PLL_DISABLE; | |
8703 | I915_WRITE(LCPLL_CTL, val); | |
8704 | POSTING_READ(LCPLL_CTL); | |
8705 | ||
24d8441d | 8706 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
8707 | DRM_ERROR("LCPLL still locked\n"); |
8708 | ||
9ccd5aeb | 8709 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8710 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8711 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8712 | ndelay(100); |
8713 | ||
9ccd5aeb PZ |
8714 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8715 | 1)) | |
be256dc7 PZ |
8716 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8717 | ||
8718 | if (allow_power_down) { | |
8719 | val = I915_READ(LCPLL_CTL); | |
8720 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8721 | I915_WRITE(LCPLL_CTL, val); | |
8722 | POSTING_READ(LCPLL_CTL); | |
8723 | } | |
8724 | } | |
8725 | ||
8726 | /* | |
8727 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8728 | * source. | |
8729 | */ | |
6ff58d53 | 8730 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8731 | { |
8732 | uint32_t val; | |
8733 | ||
8734 | val = I915_READ(LCPLL_CTL); | |
8735 | ||
8736 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8737 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8738 | return; | |
8739 | ||
a8a8bd54 PZ |
8740 | /* |
8741 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8742 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8743 | */ |
59bad947 | 8744 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8745 | |
be256dc7 PZ |
8746 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8747 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8748 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8749 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8750 | } |
8751 | ||
9ccd5aeb | 8752 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8753 | val |= D_COMP_COMP_FORCE; |
8754 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8755 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8756 | |
8757 | val = I915_READ(LCPLL_CTL); | |
8758 | val &= ~LCPLL_PLL_DISABLE; | |
8759 | I915_WRITE(LCPLL_CTL, val); | |
8760 | ||
93220c08 CW |
8761 | if (intel_wait_for_register(dev_priv, |
8762 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
8763 | 5)) | |
be256dc7 PZ |
8764 | DRM_ERROR("LCPLL not locked yet\n"); |
8765 | ||
8766 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8767 | val = I915_READ(LCPLL_CTL); | |
8768 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8769 | I915_WRITE(LCPLL_CTL, val); | |
8770 | ||
f53dd63f ID |
8771 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
8772 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
8773 | DRM_ERROR("Switching back to LCPLL failed\n"); |
8774 | } | |
215733fa | 8775 | |
59bad947 | 8776 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 8777 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
8778 | } |
8779 | ||
765dab67 PZ |
8780 | /* |
8781 | * Package states C8 and deeper are really deep PC states that can only be | |
8782 | * reached when all the devices on the system allow it, so even if the graphics | |
8783 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8784 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8785 | * | |
8786 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8787 | * well is disabled and most interrupts are disabled, and these are also | |
8788 | * requirements for runtime PM. When these conditions are met, we manually do | |
8789 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8790 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8791 | * hang the machine. | |
8792 | * | |
8793 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8794 | * the state of some registers, so when we come back from PC8+ we need to | |
8795 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8796 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8797 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8798 | * because of the runtime PM support). | |
8799 | * | |
8800 | * For more, read "Display Sequences for Package C8" on the hardware | |
8801 | * documentation. | |
8802 | */ | |
a14cb6fc | 8803 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8804 | { |
c67a470b PZ |
8805 | uint32_t val; |
8806 | ||
c67a470b PZ |
8807 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8808 | ||
4f8036a2 | 8809 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8810 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8811 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8812 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8813 | } | |
8814 | ||
c39055b0 | 8815 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
8816 | hsw_disable_lcpll(dev_priv, true, true); |
8817 | } | |
8818 | ||
a14cb6fc | 8819 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8820 | { |
c67a470b PZ |
8821 | uint32_t val; |
8822 | ||
c67a470b PZ |
8823 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8824 | ||
8825 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 8826 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 8827 | |
4f8036a2 | 8828 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8829 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8830 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8831 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8832 | } | |
c67a470b PZ |
8833 | } |
8834 | ||
190f68c5 ACO |
8835 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8836 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8837 | { |
d7edc4e5 | 8838 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
44a126ba PZ |
8839 | struct intel_encoder *encoder = |
8840 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
8841 | ||
8842 | if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) { | |
8843 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8844 | pipe_name(crtc->pipe)); | |
af3997b5 | 8845 | return -EINVAL; |
44a126ba | 8846 | } |
af3997b5 | 8847 | } |
716c2e55 | 8848 | |
c7653199 | 8849 | crtc->lowfreq_avail = false; |
644cef34 | 8850 | |
c8f7a0db | 8851 | return 0; |
79e53945 JB |
8852 | } |
8853 | ||
3760b59c S |
8854 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
8855 | enum port port, | |
8856 | struct intel_crtc_state *pipe_config) | |
8857 | { | |
8106ddbd ACO |
8858 | enum intel_dpll_id id; |
8859 | ||
3760b59c S |
8860 | switch (port) { |
8861 | case PORT_A: | |
08250c4b | 8862 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
8863 | break; |
8864 | case PORT_B: | |
08250c4b | 8865 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
8866 | break; |
8867 | case PORT_C: | |
08250c4b | 8868 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
8869 | break; |
8870 | default: | |
8871 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 8872 | return; |
3760b59c | 8873 | } |
8106ddbd ACO |
8874 | |
8875 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
8876 | } |
8877 | ||
96b7dfb7 S |
8878 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8879 | enum port port, | |
5cec258b | 8880 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8881 | { |
8106ddbd | 8882 | enum intel_dpll_id id; |
a3c988ea | 8883 | u32 temp; |
96b7dfb7 S |
8884 | |
8885 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 8886 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 8887 | |
c856052a | 8888 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 8889 | return; |
8106ddbd ACO |
8890 | |
8891 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
8892 | } |
8893 | ||
7d2c8175 DL |
8894 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8895 | enum port port, | |
5cec258b | 8896 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 8897 | { |
8106ddbd | 8898 | enum intel_dpll_id id; |
c856052a | 8899 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 8900 | |
c856052a | 8901 | switch (ddi_pll_sel) { |
7d2c8175 | 8902 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 8903 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
8904 | break; |
8905 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 8906 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 8907 | break; |
00490c22 | 8908 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 8909 | id = DPLL_ID_SPLL; |
79bd23da | 8910 | break; |
9d16da65 ACO |
8911 | case PORT_CLK_SEL_LCPLL_810: |
8912 | id = DPLL_ID_LCPLL_810; | |
8913 | break; | |
8914 | case PORT_CLK_SEL_LCPLL_1350: | |
8915 | id = DPLL_ID_LCPLL_1350; | |
8916 | break; | |
8917 | case PORT_CLK_SEL_LCPLL_2700: | |
8918 | id = DPLL_ID_LCPLL_2700; | |
8919 | break; | |
8106ddbd | 8920 | default: |
c856052a | 8921 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
8922 | /* fall through */ |
8923 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 8924 | return; |
7d2c8175 | 8925 | } |
8106ddbd ACO |
8926 | |
8927 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
8928 | } |
8929 | ||
cf30429e JN |
8930 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
8931 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8932 | u64 *power_domain_mask) |
cf30429e JN |
8933 | { |
8934 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8935 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
8936 | enum intel_display_power_domain power_domain; |
8937 | u32 tmp; | |
8938 | ||
d9a7bc67 ID |
8939 | /* |
8940 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
8941 | * transcoder handled below. | |
8942 | */ | |
cf30429e JN |
8943 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8944 | ||
8945 | /* | |
8946 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
8947 | * consistency and less surprising code; it's in always on power). | |
8948 | */ | |
8949 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
8950 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8951 | enum pipe trans_edp_pipe; | |
8952 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8953 | default: | |
8954 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8955 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8956 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8957 | trans_edp_pipe = PIPE_A; | |
8958 | break; | |
8959 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8960 | trans_edp_pipe = PIPE_B; | |
8961 | break; | |
8962 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8963 | trans_edp_pipe = PIPE_C; | |
8964 | break; | |
8965 | } | |
8966 | ||
8967 | if (trans_edp_pipe == crtc->pipe) | |
8968 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8969 | } | |
8970 | ||
8971 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
8972 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
8973 | return false; | |
d8fc70b7 | 8974 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e JN |
8975 | |
8976 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
8977 | ||
8978 | return tmp & PIPECONF_ENABLE; | |
8979 | } | |
8980 | ||
4d1de975 JN |
8981 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
8982 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8983 | u64 *power_domain_mask) |
4d1de975 JN |
8984 | { |
8985 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8986 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
8987 | enum intel_display_power_domain power_domain; |
8988 | enum port port; | |
8989 | enum transcoder cpu_transcoder; | |
8990 | u32 tmp; | |
8991 | ||
4d1de975 JN |
8992 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
8993 | if (port == PORT_A) | |
8994 | cpu_transcoder = TRANSCODER_DSI_A; | |
8995 | else | |
8996 | cpu_transcoder = TRANSCODER_DSI_C; | |
8997 | ||
8998 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
8999 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9000 | continue; | |
d8fc70b7 | 9001 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 9002 | |
db18b6a6 ID |
9003 | /* |
9004 | * The PLL needs to be enabled with a valid divider | |
9005 | * configuration, otherwise accessing DSI registers will hang | |
9006 | * the machine. See BSpec North Display Engine | |
9007 | * registers/MIPI[BXT]. We can break out here early, since we | |
9008 | * need the same DSI PLL to be enabled for both DSI ports. | |
9009 | */ | |
9010 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9011 | break; | |
9012 | ||
4d1de975 JN |
9013 | /* XXX: this works for video mode only */ |
9014 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9015 | if (!(tmp & DPI_ENABLE)) | |
9016 | continue; | |
9017 | ||
9018 | tmp = I915_READ(MIPI_CTRL(port)); | |
9019 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9020 | continue; | |
9021 | ||
9022 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
9023 | break; |
9024 | } | |
9025 | ||
d7edc4e5 | 9026 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
9027 | } |
9028 | ||
26804afd | 9029 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9030 | struct intel_crtc_state *pipe_config) |
26804afd | 9031 | { |
6315b5d3 | 9032 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 9033 | struct intel_shared_dpll *pll; |
26804afd DV |
9034 | enum port port; |
9035 | uint32_t tmp; | |
9036 | ||
9037 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9038 | ||
9039 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9040 | ||
b976dc53 | 9041 | if (IS_GEN9_BC(dev_priv)) |
96b7dfb7 | 9042 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 9043 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 9044 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
9045 | else |
9046 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9047 | |
8106ddbd ACO |
9048 | pll = pipe_config->shared_dpll; |
9049 | if (pll) { | |
2edd6443 ACO |
9050 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9051 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9052 | } |
9053 | ||
26804afd DV |
9054 | /* |
9055 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9056 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9057 | * the PCH transcoder is on. | |
9058 | */ | |
6315b5d3 | 9059 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 9060 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
9061 | pipe_config->has_pch_encoder = true; |
9062 | ||
9063 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9064 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9065 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9066 | ||
9067 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9068 | } | |
9069 | } | |
9070 | ||
0e8ffe1b | 9071 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9072 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9073 | { |
6315b5d3 | 9074 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9075 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 9076 | u64 power_domain_mask; |
cf30429e | 9077 | bool active; |
0e8ffe1b | 9078 | |
1729050e ID |
9079 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9080 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9081 | return false; |
d8fc70b7 | 9082 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 9083 | |
8106ddbd | 9084 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9085 | |
cf30429e | 9086 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9087 | |
cc3f90f0 | 9088 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
9089 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
9090 | WARN_ON(active); | |
9091 | active = true; | |
4d1de975 JN |
9092 | } |
9093 | ||
cf30429e | 9094 | if (!active) |
1729050e | 9095 | goto out; |
0e8ffe1b | 9096 | |
d7edc4e5 | 9097 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
9098 | haswell_get_ddi_port_state(crtc, pipe_config); |
9099 | intel_get_pipe_timings(crtc, pipe_config); | |
9100 | } | |
627eb5a3 | 9101 | |
bc58be60 | 9102 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9103 | |
05dc698c LL |
9104 | pipe_config->gamma_mode = |
9105 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9106 | ||
6315b5d3 | 9107 | if (INTEL_GEN(dev_priv) >= 9) { |
1c74eeaf | 9108 | intel_crtc_init_scalers(crtc, pipe_config); |
a1b2278e | 9109 | |
af99ceda CK |
9110 | pipe_config->scaler_state.scaler_id = -1; |
9111 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9112 | } | |
9113 | ||
1729050e ID |
9114 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9115 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
d8fc70b7 | 9116 | power_domain_mask |= BIT_ULL(power_domain); |
6315b5d3 | 9117 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 9118 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9119 | else |
1c132b44 | 9120 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9121 | } |
88adfff1 | 9122 | |
772c2a51 | 9123 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
9124 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
9125 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9126 | |
4d1de975 JN |
9127 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9128 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9129 | pipe_config->pixel_multiplier = |
9130 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9131 | } else { | |
9132 | pipe_config->pixel_multiplier = 1; | |
9133 | } | |
6c49f241 | 9134 | |
1729050e ID |
9135 | out: |
9136 | for_each_power_domain(power_domain, power_domain_mask) | |
9137 | intel_display_power_put(dev_priv, power_domain); | |
9138 | ||
cf30429e | 9139 | return active; |
0e8ffe1b DV |
9140 | } |
9141 | ||
292889e1 VS |
9142 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9143 | const struct intel_plane_state *plane_state) | |
9144 | { | |
9145 | unsigned int width = plane_state->base.crtc_w; | |
9146 | unsigned int stride = roundup_pow_of_two(width) * 4; | |
9147 | ||
9148 | switch (stride) { | |
9149 | default: | |
9150 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9151 | width, stride); | |
9152 | stride = 256; | |
9153 | /* fallthrough */ | |
9154 | case 256: | |
9155 | case 512: | |
9156 | case 1024: | |
9157 | case 2048: | |
9158 | break; | |
9159 | } | |
9160 | ||
9161 | return CURSOR_ENABLE | | |
9162 | CURSOR_GAMMA_ENABLE | | |
9163 | CURSOR_FORMAT_ARGB | | |
9164 | CURSOR_STRIDE(stride); | |
9165 | } | |
9166 | ||
55a08b3f ML |
9167 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
9168 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
9169 | { |
9170 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9171 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 9172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 9173 | uint32_t cntl = 0, size = 0; |
560b85bb | 9174 | |
936e71e3 | 9175 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
9176 | unsigned int width = plane_state->base.crtc_w; |
9177 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 | 9178 | |
a0864d59 | 9179 | cntl = plane_state->ctl; |
dc41c154 | 9180 | size = (height << 12) | width; |
4b0e333e | 9181 | } |
560b85bb | 9182 | |
dc41c154 VS |
9183 | if (intel_crtc->cursor_cntl != 0 && |
9184 | (intel_crtc->cursor_base != base || | |
9185 | intel_crtc->cursor_size != size || | |
9186 | intel_crtc->cursor_cntl != cntl)) { | |
9187 | /* On these chipsets we can only modify the base/size/stride | |
9188 | * whilst the cursor is disabled. | |
9189 | */ | |
dd584fc0 VS |
9190 | I915_WRITE_FW(CURCNTR(PIPE_A), 0); |
9191 | POSTING_READ_FW(CURCNTR(PIPE_A)); | |
dc41c154 | 9192 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9193 | } |
560b85bb | 9194 | |
99d1f387 | 9195 | if (intel_crtc->cursor_base != base) { |
dd584fc0 | 9196 | I915_WRITE_FW(CURBASE(PIPE_A), base); |
99d1f387 VS |
9197 | intel_crtc->cursor_base = base; |
9198 | } | |
4726e0b0 | 9199 | |
dc41c154 | 9200 | if (intel_crtc->cursor_size != size) { |
dd584fc0 | 9201 | I915_WRITE_FW(CURSIZE, size); |
dc41c154 | 9202 | intel_crtc->cursor_size = size; |
4b0e333e | 9203 | } |
560b85bb | 9204 | |
4b0e333e | 9205 | if (intel_crtc->cursor_cntl != cntl) { |
dd584fc0 VS |
9206 | I915_WRITE_FW(CURCNTR(PIPE_A), cntl); |
9207 | POSTING_READ_FW(CURCNTR(PIPE_A)); | |
4b0e333e | 9208 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9209 | } |
560b85bb CW |
9210 | } |
9211 | ||
292889e1 VS |
9212 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9213 | const struct intel_plane_state *plane_state) | |
9214 | { | |
9215 | struct drm_i915_private *dev_priv = | |
9216 | to_i915(plane_state->base.plane->dev); | |
9217 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
292889e1 VS |
9218 | u32 cntl; |
9219 | ||
9220 | cntl = MCURSOR_GAMMA_ENABLE; | |
9221 | ||
9222 | if (HAS_DDI(dev_priv)) | |
9223 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
9224 | ||
d509e28b | 9225 | cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); |
292889e1 VS |
9226 | |
9227 | switch (plane_state->base.crtc_w) { | |
9228 | case 64: | |
9229 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9230 | break; | |
9231 | case 128: | |
9232 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9233 | break; | |
9234 | case 256: | |
9235 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9236 | break; | |
9237 | default: | |
9238 | MISSING_CASE(plane_state->base.crtc_w); | |
9239 | return 0; | |
9240 | } | |
9241 | ||
9242 | if (plane_state->base.rotation & DRM_ROTATE_180) | |
9243 | cntl |= CURSOR_ROTATE_180; | |
9244 | ||
9245 | return cntl; | |
9246 | } | |
9247 | ||
55a08b3f ML |
9248 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
9249 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
9250 | { |
9251 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9252 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
9253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9254 | int pipe = intel_crtc->pipe; | |
663f3122 | 9255 | uint32_t cntl = 0; |
4b0e333e | 9256 | |
292889e1 | 9257 | if (plane_state && plane_state->base.visible) |
a0864d59 | 9258 | cntl = plane_state->ctl; |
4398ad45 | 9259 | |
4b0e333e | 9260 | if (intel_crtc->cursor_cntl != cntl) { |
dd584fc0 VS |
9261 | I915_WRITE_FW(CURCNTR(pipe), cntl); |
9262 | POSTING_READ_FW(CURCNTR(pipe)); | |
4b0e333e | 9263 | intel_crtc->cursor_cntl = cntl; |
65a21cd6 | 9264 | } |
4b0e333e | 9265 | |
65a21cd6 | 9266 | /* and commit changes on next vblank */ |
dd584fc0 VS |
9267 | I915_WRITE_FW(CURBASE(pipe), base); |
9268 | POSTING_READ_FW(CURBASE(pipe)); | |
99d1f387 VS |
9269 | |
9270 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9271 | } |
9272 | ||
cda4b7d3 | 9273 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 9274 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 9275 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
9276 | { |
9277 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9278 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
9279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9280 | int pipe = intel_crtc->pipe; | |
55a08b3f | 9281 | u32 base = intel_crtc->cursor_addr; |
dd584fc0 | 9282 | unsigned long irqflags; |
55a08b3f | 9283 | u32 pos = 0; |
cda4b7d3 | 9284 | |
55a08b3f ML |
9285 | if (plane_state) { |
9286 | int x = plane_state->base.crtc_x; | |
9287 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 9288 | |
55a08b3f ML |
9289 | if (x < 0) { |
9290 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9291 | x = -x; | |
9292 | } | |
9293 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 9294 | |
55a08b3f ML |
9295 | if (y < 0) { |
9296 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9297 | y = -y; | |
9298 | } | |
9299 | pos |= y << CURSOR_Y_SHIFT; | |
9300 | ||
9301 | /* ILK+ do this automagically */ | |
49cff963 | 9302 | if (HAS_GMCH_DISPLAY(dev_priv) && |
f22aa143 | 9303 | plane_state->base.rotation & DRM_ROTATE_180) { |
55a08b3f ML |
9304 | base += (plane_state->base.crtc_h * |
9305 | plane_state->base.crtc_w - 1) * 4; | |
9306 | } | |
cda4b7d3 | 9307 | } |
cda4b7d3 | 9308 | |
dd584fc0 VS |
9309 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
9310 | ||
9311 | I915_WRITE_FW(CURPOS(pipe), pos); | |
5efb3e28 | 9312 | |
2a307c2e | 9313 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
a0864d59 | 9314 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 9315 | else |
a0864d59 | 9316 | i9xx_update_cursor(crtc, base, plane_state); |
dd584fc0 VS |
9317 | |
9318 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
cda4b7d3 CW |
9319 | } |
9320 | ||
50a0bc90 | 9321 | static bool cursor_size_ok(struct drm_i915_private *dev_priv, |
dc41c154 VS |
9322 | uint32_t width, uint32_t height) |
9323 | { | |
9324 | if (width == 0 || height == 0) | |
9325 | return false; | |
9326 | ||
9327 | /* | |
9328 | * 845g/865g are special in that they are only limited by | |
9329 | * the width of their cursors, the height is arbitrary up to | |
9330 | * the precision of the register. Everything else requires | |
9331 | * square cursors, limited to a few power-of-two sizes. | |
9332 | */ | |
2a307c2e | 9333 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
dc41c154 VS |
9334 | if ((width & 63) != 0) |
9335 | return false; | |
9336 | ||
2a307c2e | 9337 | if (width > (IS_I845G(dev_priv) ? 64 : 512)) |
dc41c154 VS |
9338 | return false; |
9339 | ||
9340 | if (height > 1023) | |
9341 | return false; | |
9342 | } else { | |
9343 | switch (width | height) { | |
9344 | case 256: | |
9345 | case 128: | |
50a0bc90 | 9346 | if (IS_GEN2(dev_priv)) |
dc41c154 VS |
9347 | return false; |
9348 | case 64: | |
9349 | break; | |
9350 | default: | |
9351 | return false; | |
9352 | } | |
9353 | } | |
9354 | ||
9355 | return true; | |
9356 | } | |
9357 | ||
79e53945 JB |
9358 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9359 | static struct drm_display_mode load_detect_mode = { | |
9360 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9361 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9362 | }; | |
9363 | ||
a8bb6818 | 9364 | struct drm_framebuffer * |
24dbf51a CW |
9365 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
9366 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
9367 | { |
9368 | struct intel_framebuffer *intel_fb; | |
9369 | int ret; | |
9370 | ||
9371 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 9372 | if (!intel_fb) |
d2dff872 | 9373 | return ERR_PTR(-ENOMEM); |
d2dff872 | 9374 | |
24dbf51a | 9375 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
9376 | if (ret) |
9377 | goto err; | |
d2dff872 CW |
9378 | |
9379 | return &intel_fb->base; | |
dcb1394e | 9380 | |
dd4916c5 | 9381 | err: |
dd4916c5 | 9382 | kfree(intel_fb); |
dd4916c5 | 9383 | return ERR_PTR(ret); |
d2dff872 CW |
9384 | } |
9385 | ||
9386 | static u32 | |
9387 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9388 | { | |
9389 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9390 | return ALIGN(pitch, 64); | |
9391 | } | |
9392 | ||
9393 | static u32 | |
9394 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9395 | { | |
9396 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9397 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9398 | } |
9399 | ||
9400 | static struct drm_framebuffer * | |
9401 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9402 | struct drm_display_mode *mode, | |
9403 | int depth, int bpp) | |
9404 | { | |
dcb1394e | 9405 | struct drm_framebuffer *fb; |
d2dff872 | 9406 | struct drm_i915_gem_object *obj; |
0fed39bd | 9407 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 9408 | |
12d79d78 | 9409 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 9410 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
9411 | if (IS_ERR(obj)) |
9412 | return ERR_CAST(obj); | |
d2dff872 CW |
9413 | |
9414 | mode_cmd.width = mode->hdisplay; | |
9415 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9416 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9417 | bpp); | |
5ca0c34a | 9418 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 9419 | |
24dbf51a | 9420 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 9421 | if (IS_ERR(fb)) |
f0cd5182 | 9422 | i915_gem_object_put(obj); |
dcb1394e LW |
9423 | |
9424 | return fb; | |
d2dff872 CW |
9425 | } |
9426 | ||
9427 | static struct drm_framebuffer * | |
9428 | mode_fits_in_fbdev(struct drm_device *dev, | |
9429 | struct drm_display_mode *mode) | |
9430 | { | |
0695726e | 9431 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 9432 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
9433 | struct drm_i915_gem_object *obj; |
9434 | struct drm_framebuffer *fb; | |
9435 | ||
4c0e5528 | 9436 | if (!dev_priv->fbdev) |
d2dff872 CW |
9437 | return NULL; |
9438 | ||
4c0e5528 | 9439 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9440 | return NULL; |
9441 | ||
4c0e5528 DV |
9442 | obj = dev_priv->fbdev->fb->obj; |
9443 | BUG_ON(!obj); | |
9444 | ||
8bcd4553 | 9445 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 | 9446 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
272725c7 | 9447 | fb->format->cpp[0] * 8)) |
d2dff872 CW |
9448 | return NULL; |
9449 | ||
01f2c773 | 9450 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9451 | return NULL; |
9452 | ||
edde3617 | 9453 | drm_framebuffer_reference(fb); |
d2dff872 | 9454 | return fb; |
4520f53a DV |
9455 | #else |
9456 | return NULL; | |
9457 | #endif | |
d2dff872 CW |
9458 | } |
9459 | ||
d3a40d1b ACO |
9460 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9461 | struct drm_crtc *crtc, | |
9462 | struct drm_display_mode *mode, | |
9463 | struct drm_framebuffer *fb, | |
9464 | int x, int y) | |
9465 | { | |
9466 | struct drm_plane_state *plane_state; | |
9467 | int hdisplay, vdisplay; | |
9468 | int ret; | |
9469 | ||
9470 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9471 | if (IS_ERR(plane_state)) | |
9472 | return PTR_ERR(plane_state); | |
9473 | ||
9474 | if (mode) | |
196cd5d3 | 9475 | drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay); |
d3a40d1b ACO |
9476 | else |
9477 | hdisplay = vdisplay = 0; | |
9478 | ||
9479 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9480 | if (ret) | |
9481 | return ret; | |
9482 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9483 | plane_state->crtc_x = 0; | |
9484 | plane_state->crtc_y = 0; | |
9485 | plane_state->crtc_w = hdisplay; | |
9486 | plane_state->crtc_h = vdisplay; | |
9487 | plane_state->src_x = x << 16; | |
9488 | plane_state->src_y = y << 16; | |
9489 | plane_state->src_w = hdisplay << 16; | |
9490 | plane_state->src_h = vdisplay << 16; | |
9491 | ||
9492 | return 0; | |
9493 | } | |
9494 | ||
6c5ed5ae ML |
9495 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
9496 | struct drm_display_mode *mode, | |
9497 | struct intel_load_detect_pipe *old, | |
9498 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9499 | { |
9500 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9501 | struct intel_encoder *intel_encoder = |
9502 | intel_attached_encoder(connector); | |
79e53945 | 9503 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9504 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9505 | struct drm_crtc *crtc = NULL; |
9506 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 9507 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 9508 | struct drm_framebuffer *fb; |
51fd371b | 9509 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 9510 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 9511 | struct drm_connector_state *connector_state; |
4be07317 | 9512 | struct intel_crtc_state *crtc_state; |
51fd371b | 9513 | int ret, i = -1; |
79e53945 | 9514 | |
d2dff872 | 9515 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9516 | connector->base.id, connector->name, |
8e329a03 | 9517 | encoder->base.id, encoder->name); |
d2dff872 | 9518 | |
edde3617 ML |
9519 | old->restore_state = NULL; |
9520 | ||
6c5ed5ae | 9521 | WARN_ON(!drm_modeset_is_locked(&config->connection_mutex)); |
6e9f798d | 9522 | |
79e53945 JB |
9523 | /* |
9524 | * Algorithm gets a little messy: | |
7a5e4805 | 9525 | * |
79e53945 JB |
9526 | * - if the connector already has an assigned crtc, use it (but make |
9527 | * sure it's on first) | |
7a5e4805 | 9528 | * |
79e53945 JB |
9529 | * - try to find the first unused crtc that can drive this connector, |
9530 | * and use that if we find one | |
79e53945 JB |
9531 | */ |
9532 | ||
9533 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
9534 | if (connector->state->crtc) { |
9535 | crtc = connector->state->crtc; | |
8261b191 | 9536 | |
51fd371b | 9537 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 9538 | if (ret) |
ad3c558f | 9539 | goto fail; |
8261b191 CW |
9540 | |
9541 | /* Make sure the crtc and connector are running */ | |
edde3617 | 9542 | goto found; |
79e53945 JB |
9543 | } |
9544 | ||
9545 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9546 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9547 | i++; |
9548 | if (!(encoder->possible_crtcs & (1 << i))) | |
9549 | continue; | |
edde3617 ML |
9550 | |
9551 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
9552 | if (ret) | |
9553 | goto fail; | |
9554 | ||
9555 | if (possible_crtc->state->enable) { | |
9556 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 9557 | continue; |
edde3617 | 9558 | } |
a459249c VS |
9559 | |
9560 | crtc = possible_crtc; | |
9561 | break; | |
79e53945 JB |
9562 | } |
9563 | ||
9564 | /* | |
9565 | * If we didn't find an unused CRTC, don't use any. | |
9566 | */ | |
9567 | if (!crtc) { | |
7173188d | 9568 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
f4bf77b4 | 9569 | ret = -ENODEV; |
ad3c558f | 9570 | goto fail; |
79e53945 JB |
9571 | } |
9572 | ||
edde3617 ML |
9573 | found: |
9574 | intel_crtc = to_intel_crtc(crtc); | |
9575 | ||
4d02e2de DV |
9576 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
9577 | if (ret) | |
ad3c558f | 9578 | goto fail; |
79e53945 | 9579 | |
83a57153 | 9580 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
9581 | restore_state = drm_atomic_state_alloc(dev); |
9582 | if (!state || !restore_state) { | |
9583 | ret = -ENOMEM; | |
9584 | goto fail; | |
9585 | } | |
83a57153 ACO |
9586 | |
9587 | state->acquire_ctx = ctx; | |
edde3617 | 9588 | restore_state->acquire_ctx = ctx; |
83a57153 | 9589 | |
944b0c76 ACO |
9590 | connector_state = drm_atomic_get_connector_state(state, connector); |
9591 | if (IS_ERR(connector_state)) { | |
9592 | ret = PTR_ERR(connector_state); | |
9593 | goto fail; | |
9594 | } | |
9595 | ||
edde3617 ML |
9596 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
9597 | if (ret) | |
9598 | goto fail; | |
944b0c76 | 9599 | |
4be07317 ACO |
9600 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9601 | if (IS_ERR(crtc_state)) { | |
9602 | ret = PTR_ERR(crtc_state); | |
9603 | goto fail; | |
9604 | } | |
9605 | ||
49d6fa21 | 9606 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 9607 | |
6492711d CW |
9608 | if (!mode) |
9609 | mode = &load_detect_mode; | |
79e53945 | 9610 | |
d2dff872 CW |
9611 | /* We need a framebuffer large enough to accommodate all accesses |
9612 | * that the plane may generate whilst we perform load detection. | |
9613 | * We can not rely on the fbcon either being present (we get called | |
9614 | * during its initialisation to detect all boot displays, or it may | |
9615 | * not even exist) or that it is large enough to satisfy the | |
9616 | * requested mode. | |
9617 | */ | |
94352cf9 DV |
9618 | fb = mode_fits_in_fbdev(dev, mode); |
9619 | if (fb == NULL) { | |
d2dff872 | 9620 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 9621 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
9622 | } else |
9623 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9624 | if (IS_ERR(fb)) { |
d2dff872 | 9625 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
f4bf77b4 | 9626 | ret = PTR_ERR(fb); |
412b61d8 | 9627 | goto fail; |
79e53945 | 9628 | } |
79e53945 | 9629 | |
d3a40d1b ACO |
9630 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
9631 | if (ret) | |
9632 | goto fail; | |
9633 | ||
edde3617 ML |
9634 | drm_framebuffer_unreference(fb); |
9635 | ||
9636 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
9637 | if (ret) | |
9638 | goto fail; | |
9639 | ||
9640 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
9641 | if (!ret) | |
9642 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
9643 | if (!ret) | |
9644 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
9645 | if (ret) { | |
9646 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
9647 | goto fail; | |
9648 | } | |
8c7b5ccb | 9649 | |
3ba86073 ML |
9650 | ret = drm_atomic_commit(state); |
9651 | if (ret) { | |
6492711d | 9652 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 9653 | goto fail; |
79e53945 | 9654 | } |
edde3617 ML |
9655 | |
9656 | old->restore_state = restore_state; | |
7abbd11f | 9657 | drm_atomic_state_put(state); |
7173188d | 9658 | |
79e53945 | 9659 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 9660 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 9661 | return true; |
412b61d8 | 9662 | |
ad3c558f | 9663 | fail: |
7fb71c8f CW |
9664 | if (state) { |
9665 | drm_atomic_state_put(state); | |
9666 | state = NULL; | |
9667 | } | |
9668 | if (restore_state) { | |
9669 | drm_atomic_state_put(restore_state); | |
9670 | restore_state = NULL; | |
9671 | } | |
83a57153 | 9672 | |
6c5ed5ae ML |
9673 | if (ret == -EDEADLK) |
9674 | return ret; | |
51fd371b | 9675 | |
412b61d8 | 9676 | return false; |
79e53945 JB |
9677 | } |
9678 | ||
d2434ab7 | 9679 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9680 | struct intel_load_detect_pipe *old, |
9681 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9682 | { |
d2434ab7 DV |
9683 | struct intel_encoder *intel_encoder = |
9684 | intel_attached_encoder(connector); | |
4ef69c7a | 9685 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 9686 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 9687 | int ret; |
79e53945 | 9688 | |
d2dff872 | 9689 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9690 | connector->base.id, connector->name, |
8e329a03 | 9691 | encoder->base.id, encoder->name); |
d2dff872 | 9692 | |
edde3617 | 9693 | if (!state) |
0622a53c | 9694 | return; |
79e53945 | 9695 | |
581e49fe | 9696 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
0853695c | 9697 | if (ret) |
edde3617 | 9698 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 9699 | drm_atomic_state_put(state); |
79e53945 JB |
9700 | } |
9701 | ||
da4a1efa | 9702 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9703 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 9704 | { |
fac5e23e | 9705 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
9706 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
9707 | ||
9708 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9709 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 9710 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 9711 | return 120000; |
5db94019 | 9712 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
9713 | return 96000; |
9714 | else | |
9715 | return 48000; | |
9716 | } | |
9717 | ||
79e53945 | 9718 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9719 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9720 | struct intel_crtc_state *pipe_config) |
79e53945 | 9721 | { |
f1f644dc | 9722 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9723 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 9724 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9725 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 9726 | u32 fp; |
9e2c8475 | 9727 | struct dpll clock; |
dccbea3b | 9728 | int port_clock; |
da4a1efa | 9729 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9730 | |
9731 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9732 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9733 | else |
293623f7 | 9734 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9735 | |
9736 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 9737 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
9738 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
9739 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9740 | } else { |
9741 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9742 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9743 | } | |
9744 | ||
5db94019 | 9745 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 9746 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
9747 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
9748 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9749 | else |
9750 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9751 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9752 | ||
9753 | switch (dpll & DPLL_MODE_MASK) { | |
9754 | case DPLLB_MODE_DAC_SERIAL: | |
9755 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9756 | 5 : 10; | |
9757 | break; | |
9758 | case DPLLB_MODE_LVDS: | |
9759 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9760 | 7 : 14; | |
9761 | break; | |
9762 | default: | |
28c97730 | 9763 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9764 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9765 | return; |
79e53945 JB |
9766 | } |
9767 | ||
9b1e14f4 | 9768 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 9769 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 9770 | else |
dccbea3b | 9771 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 9772 | } else { |
50a0bc90 | 9773 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9774 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9775 | |
9776 | if (is_lvds) { | |
9777 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9778 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9779 | |
9780 | if (lvds & LVDS_CLKB_POWER_UP) | |
9781 | clock.p2 = 7; | |
9782 | else | |
9783 | clock.p2 = 14; | |
79e53945 JB |
9784 | } else { |
9785 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9786 | clock.p1 = 2; | |
9787 | else { | |
9788 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9789 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9790 | } | |
9791 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9792 | clock.p2 = 4; | |
9793 | else | |
9794 | clock.p2 = 2; | |
79e53945 | 9795 | } |
da4a1efa | 9796 | |
dccbea3b | 9797 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
9798 | } |
9799 | ||
18442d08 VS |
9800 | /* |
9801 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9802 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9803 | * encoder's get_config() function. |
9804 | */ | |
dccbea3b | 9805 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
9806 | } |
9807 | ||
6878da05 VS |
9808 | int intel_dotclock_calculate(int link_freq, |
9809 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9810 | { |
f1f644dc JB |
9811 | /* |
9812 | * The calculation for the data clock is: | |
1041a02f | 9813 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9814 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9815 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9816 | * |
9817 | * and the link clock is simpler: | |
1041a02f | 9818 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9819 | */ |
9820 | ||
6878da05 VS |
9821 | if (!m_n->link_n) |
9822 | return 0; | |
f1f644dc | 9823 | |
6878da05 VS |
9824 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9825 | } | |
f1f644dc | 9826 | |
18442d08 | 9827 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9828 | struct intel_crtc_state *pipe_config) |
6878da05 | 9829 | { |
e3b247da | 9830 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 9831 | |
18442d08 VS |
9832 | /* read out port_clock from the DPLL */ |
9833 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9834 | |
f1f644dc | 9835 | /* |
e3b247da VS |
9836 | * In case there is an active pipe without active ports, |
9837 | * we may need some idea for the dotclock anyway. | |
9838 | * Calculate one based on the FDI configuration. | |
79e53945 | 9839 | */ |
2d112de7 | 9840 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 9841 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 9842 | &pipe_config->fdi_m_n); |
79e53945 JB |
9843 | } |
9844 | ||
9845 | /** Returns the currently programmed mode of the given pipe. */ | |
9846 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9847 | struct drm_crtc *crtc) | |
9848 | { | |
fac5e23e | 9849 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 9850 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9851 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9852 | struct drm_display_mode *mode; |
3f36b937 | 9853 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
9854 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9855 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9856 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9857 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9858 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9859 | |
9860 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9861 | if (!mode) | |
9862 | return NULL; | |
9863 | ||
3f36b937 TU |
9864 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9865 | if (!pipe_config) { | |
9866 | kfree(mode); | |
9867 | return NULL; | |
9868 | } | |
9869 | ||
f1f644dc JB |
9870 | /* |
9871 | * Construct a pipe_config sufficient for getting the clock info | |
9872 | * back out of crtc_clock_get. | |
9873 | * | |
9874 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9875 | * to use a real value here instead. | |
9876 | */ | |
3f36b937 TU |
9877 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
9878 | pipe_config->pixel_multiplier = 1; | |
9879 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
9880 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9881 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
9882 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
9883 | ||
9884 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
9885 | mode->hdisplay = (htot & 0xffff) + 1; |
9886 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9887 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9888 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9889 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9890 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9891 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9892 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9893 | ||
9894 | drm_mode_set_name(mode); | |
79e53945 | 9895 | |
3f36b937 TU |
9896 | kfree(pipe_config); |
9897 | ||
79e53945 JB |
9898 | return mode; |
9899 | } | |
9900 | ||
9901 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
9902 | { | |
9903 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 9904 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 9905 | struct intel_flip_work *work; |
67e77c5a | 9906 | |
5e2d7afc | 9907 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
9908 | work = intel_crtc->flip_work; |
9909 | intel_crtc->flip_work = NULL; | |
9910 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 9911 | |
5a21b665 | 9912 | if (work) { |
51cbaf01 ML |
9913 | cancel_work_sync(&work->mmio_work); |
9914 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 9915 | kfree(work); |
67e77c5a | 9916 | } |
79e53945 JB |
9917 | |
9918 | drm_crtc_cleanup(crtc); | |
67e77c5a | 9919 | |
79e53945 JB |
9920 | kfree(intel_crtc); |
9921 | } | |
9922 | ||
6b95a207 KH |
9923 | static void intel_unpin_work_fn(struct work_struct *__work) |
9924 | { | |
51cbaf01 ML |
9925 | struct intel_flip_work *work = |
9926 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
9927 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
9928 | struct drm_device *dev = crtc->base.dev; | |
9929 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 9930 | |
5a21b665 DV |
9931 | if (is_mmio_work(work)) |
9932 | flush_work(&work->mmio_work); | |
03f476e1 | 9933 | |
5a21b665 | 9934 | mutex_lock(&dev->struct_mutex); |
be1e3415 | 9935 | intel_unpin_fb_vma(work->old_vma); |
f8c417cd | 9936 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 9937 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 9938 | |
e8a261ea CW |
9939 | i915_gem_request_put(work->flip_queued_req); |
9940 | ||
5748b6a1 CW |
9941 | intel_frontbuffer_flip_complete(to_i915(dev), |
9942 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
9943 | intel_fbc_post_update(crtc); |
9944 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 9945 | |
5a21b665 DV |
9946 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
9947 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 9948 | |
5a21b665 DV |
9949 | kfree(work); |
9950 | } | |
d9e86c0e | 9951 | |
5a21b665 DV |
9952 | /* Is 'a' after or equal to 'b'? */ |
9953 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9954 | { | |
9955 | return !((a - b) & 0x80000000); | |
9956 | } | |
143f73b3 | 9957 | |
5a21b665 DV |
9958 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
9959 | struct intel_flip_work *work) | |
9960 | { | |
9961 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9962 | struct drm_i915_private *dev_priv = to_i915(dev); |
143f73b3 | 9963 | |
8af29b0c | 9964 | if (abort_flip_on_reset(crtc)) |
5a21b665 | 9965 | return true; |
143f73b3 | 9966 | |
5a21b665 DV |
9967 | /* |
9968 | * The relevant registers doen't exist on pre-ctg. | |
9969 | * As the flip done interrupt doesn't trigger for mmio | |
9970 | * flips on gmch platforms, a flip count check isn't | |
9971 | * really needed there. But since ctg has the registers, | |
9972 | * include it in the check anyway. | |
9973 | */ | |
9beb5fea | 9974 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
5a21b665 | 9975 | return true; |
b4a98e57 | 9976 | |
5a21b665 DV |
9977 | /* |
9978 | * BDW signals flip done immediately if the plane | |
9979 | * is disabled, even if the plane enable is already | |
9980 | * armed to occur at the next vblank :( | |
9981 | */ | |
f99d7069 | 9982 | |
5a21b665 DV |
9983 | /* |
9984 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9985 | * used the same base address. In that case the mmio flip might | |
9986 | * have completed, but the CS hasn't even executed the flip yet. | |
9987 | * | |
9988 | * A flip count check isn't enough as the CS might have updated | |
9989 | * the base address just after start of vblank, but before we | |
9990 | * managed to process the interrupt. This means we'd complete the | |
9991 | * CS flip too soon. | |
9992 | * | |
9993 | * Combining both checks should get us a good enough result. It may | |
9994 | * still happen that the CS flip has been executed, but has not | |
9995 | * yet actually completed. But in case the base address is the same | |
9996 | * anyway, we don't really care. | |
9997 | */ | |
9998 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9999 | crtc->flip_work->gtt_offset && | |
10000 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
10001 | crtc->flip_work->flip_count); | |
10002 | } | |
b4a98e57 | 10003 | |
5a21b665 DV |
10004 | static bool |
10005 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
10006 | struct intel_flip_work *work) | |
10007 | { | |
10008 | /* | |
10009 | * MMIO work completes when vblank is different from | |
10010 | * flip_queued_vblank. | |
10011 | * | |
10012 | * Reset counter value doesn't matter, this is handled by | |
10013 | * i915_wait_request finishing early, so no need to handle | |
10014 | * reset here. | |
10015 | */ | |
10016 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
10017 | } |
10018 | ||
51cbaf01 ML |
10019 | |
10020 | static bool pageflip_finished(struct intel_crtc *crtc, | |
10021 | struct intel_flip_work *work) | |
10022 | { | |
10023 | if (!atomic_read(&work->pending)) | |
10024 | return false; | |
10025 | ||
10026 | smp_rmb(); | |
10027 | ||
5a21b665 DV |
10028 | if (is_mmio_work(work)) |
10029 | return __pageflip_finished_mmio(crtc, work); | |
10030 | else | |
10031 | return __pageflip_finished_cs(crtc, work); | |
10032 | } | |
10033 | ||
10034 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
10035 | { | |
91c8a326 | 10036 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10037 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
10038 | struct intel_flip_work *work; |
10039 | unsigned long flags; | |
10040 | ||
10041 | /* Ignore early vblank irqs */ | |
10042 | if (!crtc) | |
10043 | return; | |
10044 | ||
51cbaf01 | 10045 | /* |
5a21b665 DV |
10046 | * This is called both by irq handlers and the reset code (to complete |
10047 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 10048 | */ |
5a21b665 | 10049 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 10050 | work = crtc->flip_work; |
5a21b665 DV |
10051 | |
10052 | if (work != NULL && | |
10053 | !is_mmio_work(work) && | |
e2af48c6 VS |
10054 | pageflip_finished(crtc, work)) |
10055 | page_flip_completed(crtc); | |
5a21b665 DV |
10056 | |
10057 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
10058 | } |
10059 | ||
51cbaf01 | 10060 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 10061 | { |
91c8a326 | 10062 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10063 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
51cbaf01 | 10064 | struct intel_flip_work *work; |
6b95a207 KH |
10065 | unsigned long flags; |
10066 | ||
5251f04e ML |
10067 | /* Ignore early vblank irqs */ |
10068 | if (!crtc) | |
10069 | return; | |
f326038a DV |
10070 | |
10071 | /* | |
10072 | * This is called both by irq handlers and the reset code (to complete | |
10073 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 10074 | */ |
6b95a207 | 10075 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 10076 | work = crtc->flip_work; |
5251f04e | 10077 | |
5a21b665 DV |
10078 | if (work != NULL && |
10079 | is_mmio_work(work) && | |
e2af48c6 VS |
10080 | pageflip_finished(crtc, work)) |
10081 | page_flip_completed(crtc); | |
5251f04e | 10082 | |
6b95a207 KH |
10083 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10084 | } | |
10085 | ||
5a21b665 DV |
10086 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
10087 | struct intel_flip_work *work) | |
84c33a64 | 10088 | { |
5a21b665 | 10089 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 10090 | |
5a21b665 DV |
10091 | /* Ensure that the work item is consistent when activating it ... */ |
10092 | smp_mb__before_atomic(); | |
10093 | atomic_set(&work->pending, 1); | |
10094 | } | |
a6747b73 | 10095 | |
5a21b665 DV |
10096 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10097 | struct drm_crtc *crtc, | |
10098 | struct drm_framebuffer *fb, | |
10099 | struct drm_i915_gem_object *obj, | |
10100 | struct drm_i915_gem_request *req, | |
10101 | uint32_t flags) | |
10102 | { | |
5a21b665 | 10103 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10104 | u32 flip_mask, *cs; |
143f73b3 | 10105 | |
73dec95e TU |
10106 | cs = intel_ring_begin(req, 6); |
10107 | if (IS_ERR(cs)) | |
10108 | return PTR_ERR(cs); | |
143f73b3 | 10109 | |
5a21b665 DV |
10110 | /* Can't queue multiple flips, so wait for the previous |
10111 | * one to finish before executing the next. | |
10112 | */ | |
10113 | if (intel_crtc->plane) | |
10114 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10115 | else | |
10116 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
73dec95e TU |
10117 | *cs++ = MI_WAIT_FOR_EVENT | flip_mask; |
10118 | *cs++ = MI_NOOP; | |
10119 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); | |
10120 | *cs++ = fb->pitches[0]; | |
10121 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10122 | *cs++ = 0; /* aux display base address, unused */ | |
143f73b3 | 10123 | |
5a21b665 DV |
10124 | return 0; |
10125 | } | |
84c33a64 | 10126 | |
5a21b665 DV |
10127 | static int intel_gen3_queue_flip(struct drm_device *dev, |
10128 | struct drm_crtc *crtc, | |
10129 | struct drm_framebuffer *fb, | |
10130 | struct drm_i915_gem_object *obj, | |
10131 | struct drm_i915_gem_request *req, | |
10132 | uint32_t flags) | |
10133 | { | |
5a21b665 | 10134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10135 | u32 flip_mask, *cs; |
d55dbd06 | 10136 | |
73dec95e TU |
10137 | cs = intel_ring_begin(req, 6); |
10138 | if (IS_ERR(cs)) | |
10139 | return PTR_ERR(cs); | |
d55dbd06 | 10140 | |
5a21b665 DV |
10141 | if (intel_crtc->plane) |
10142 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10143 | else | |
10144 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
73dec95e TU |
10145 | *cs++ = MI_WAIT_FOR_EVENT | flip_mask; |
10146 | *cs++ = MI_NOOP; | |
10147 | *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); | |
10148 | *cs++ = fb->pitches[0]; | |
10149 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10150 | *cs++ = MI_NOOP; | |
fd8e058a | 10151 | |
5a21b665 DV |
10152 | return 0; |
10153 | } | |
84c33a64 | 10154 | |
5a21b665 DV |
10155 | static int intel_gen4_queue_flip(struct drm_device *dev, |
10156 | struct drm_crtc *crtc, | |
10157 | struct drm_framebuffer *fb, | |
10158 | struct drm_i915_gem_object *obj, | |
10159 | struct drm_i915_gem_request *req, | |
10160 | uint32_t flags) | |
10161 | { | |
fac5e23e | 10162 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10164 | u32 pf, pipesrc, *cs; |
143f73b3 | 10165 | |
73dec95e TU |
10166 | cs = intel_ring_begin(req, 4); |
10167 | if (IS_ERR(cs)) | |
10168 | return PTR_ERR(cs); | |
143f73b3 | 10169 | |
5a21b665 DV |
10170 | /* i965+ uses the linear or tiled offsets from the |
10171 | * Display Registers (which do not change across a page-flip) | |
10172 | * so we need only reprogram the base address. | |
10173 | */ | |
73dec95e TU |
10174 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); |
10175 | *cs++ = fb->pitches[0]; | |
10176 | *cs++ = intel_crtc->flip_work->gtt_offset | | |
10177 | intel_fb_modifier_to_tiling(fb->modifier); | |
5a21b665 DV |
10178 | |
10179 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10180 | * untested on non-native modes, so ignore it for now. | |
10181 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10182 | */ | |
10183 | pf = 0; | |
10184 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
73dec95e | 10185 | *cs++ = pf | pipesrc; |
143f73b3 | 10186 | |
5a21b665 | 10187 | return 0; |
8c9f3aaf JB |
10188 | } |
10189 | ||
5a21b665 DV |
10190 | static int intel_gen6_queue_flip(struct drm_device *dev, |
10191 | struct drm_crtc *crtc, | |
10192 | struct drm_framebuffer *fb, | |
10193 | struct drm_i915_gem_object *obj, | |
10194 | struct drm_i915_gem_request *req, | |
10195 | uint32_t flags) | |
da20eabd | 10196 | { |
fac5e23e | 10197 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10198 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10199 | u32 pf, pipesrc, *cs; |
d21fbe87 | 10200 | |
73dec95e TU |
10201 | cs = intel_ring_begin(req, 4); |
10202 | if (IS_ERR(cs)) | |
10203 | return PTR_ERR(cs); | |
92826fcd | 10204 | |
73dec95e TU |
10205 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); |
10206 | *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); | |
10207 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
92826fcd | 10208 | |
5a21b665 DV |
10209 | /* Contrary to the suggestions in the documentation, |
10210 | * "Enable Panel Fitter" does not seem to be required when page | |
10211 | * flipping with a non-native mode, and worse causes a normal | |
10212 | * modeset to fail. | |
10213 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10214 | */ | |
10215 | pf = 0; | |
10216 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
73dec95e | 10217 | *cs++ = pf | pipesrc; |
7809e5ae | 10218 | |
5a21b665 | 10219 | return 0; |
7809e5ae MR |
10220 | } |
10221 | ||
5a21b665 DV |
10222 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10223 | struct drm_crtc *crtc, | |
10224 | struct drm_framebuffer *fb, | |
10225 | struct drm_i915_gem_object *obj, | |
10226 | struct drm_i915_gem_request *req, | |
10227 | uint32_t flags) | |
d21fbe87 | 10228 | { |
5db94019 | 10229 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10230 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10231 | u32 *cs, plane_bit = 0; |
5a21b665 | 10232 | int len, ret; |
d21fbe87 | 10233 | |
5a21b665 DV |
10234 | switch (intel_crtc->plane) { |
10235 | case PLANE_A: | |
10236 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10237 | break; | |
10238 | case PLANE_B: | |
10239 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10240 | break; | |
10241 | case PLANE_C: | |
10242 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10243 | break; | |
10244 | default: | |
10245 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
10246 | return -ENODEV; | |
10247 | } | |
10248 | ||
10249 | len = 4; | |
b5321f30 | 10250 | if (req->engine->id == RCS) { |
5a21b665 DV |
10251 | len += 6; |
10252 | /* | |
10253 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10254 | * 48bits addresses, and we need a NOOP for the batch size to | |
10255 | * stay even. | |
10256 | */ | |
5db94019 | 10257 | if (IS_GEN8(dev_priv)) |
5a21b665 DV |
10258 | len += 2; |
10259 | } | |
10260 | ||
10261 | /* | |
10262 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10263 | * "The full packet must be contained within the same cache line." | |
10264 | * | |
10265 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10266 | * cacheline, if we ever start emitting more commands before | |
10267 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10268 | * then do the cacheline alignment, and finally emit the | |
10269 | * MI_DISPLAY_FLIP. | |
10270 | */ | |
10271 | ret = intel_ring_cacheline_align(req); | |
10272 | if (ret) | |
10273 | return ret; | |
10274 | ||
73dec95e TU |
10275 | cs = intel_ring_begin(req, len); |
10276 | if (IS_ERR(cs)) | |
10277 | return PTR_ERR(cs); | |
5a21b665 DV |
10278 | |
10279 | /* Unmask the flip-done completion message. Note that the bspec says that | |
10280 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10281 | * more than one flip event at any time (or ensure that one flip message | |
10282 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10283 | * Experimentation says that BCS works despite DERRMR masking all | |
10284 | * flip-done completion events and that unmasking all planes at once | |
10285 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10286 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10287 | */ | |
b5321f30 | 10288 | if (req->engine->id == RCS) { |
73dec95e TU |
10289 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
10290 | *cs++ = i915_mmio_reg_offset(DERRMR); | |
10291 | *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10292 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10293 | DERRMR_PIPEC_PRI_FLIP_DONE); | |
5db94019 | 10294 | if (IS_GEN8(dev_priv)) |
73dec95e TU |
10295 | *cs++ = MI_STORE_REGISTER_MEM_GEN8 | |
10296 | MI_SRM_LRM_GLOBAL_GTT; | |
5a21b665 | 10297 | else |
73dec95e TU |
10298 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; |
10299 | *cs++ = i915_mmio_reg_offset(DERRMR); | |
10300 | *cs++ = i915_ggtt_offset(req->engine->scratch) + 256; | |
5db94019 | 10301 | if (IS_GEN8(dev_priv)) { |
73dec95e TU |
10302 | *cs++ = 0; |
10303 | *cs++ = MI_NOOP; | |
5a21b665 DV |
10304 | } |
10305 | } | |
10306 | ||
73dec95e TU |
10307 | *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit; |
10308 | *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); | |
10309 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10310 | *cs++ = MI_NOOP; | |
5a21b665 DV |
10311 | |
10312 | return 0; | |
10313 | } | |
10314 | ||
10315 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
10316 | struct drm_i915_gem_object *obj) | |
10317 | { | |
10318 | /* | |
10319 | * This is not being used for older platforms, because | |
10320 | * non-availability of flip done interrupt forces us to use | |
10321 | * CS flips. Older platforms derive flip done using some clever | |
10322 | * tricks involving the flip_pending status bits and vblank irqs. | |
10323 | * So using MMIO flips there would disrupt this mechanism. | |
10324 | */ | |
10325 | ||
10326 | if (engine == NULL) | |
10327 | return true; | |
10328 | ||
10329 | if (INTEL_GEN(engine->i915) < 5) | |
10330 | return false; | |
10331 | ||
10332 | if (i915.use_mmio_flip < 0) | |
10333 | return false; | |
10334 | else if (i915.use_mmio_flip > 0) | |
10335 | return true; | |
10336 | else if (i915.enable_execlists) | |
10337 | return true; | |
c37efb99 | 10338 | |
d07f0e59 | 10339 | return engine != i915_gem_object_last_write_engine(obj); |
5a21b665 DV |
10340 | } |
10341 | ||
10342 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
10343 | unsigned int rotation, | |
10344 | struct intel_flip_work *work) | |
10345 | { | |
10346 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 10347 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
10348 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
10349 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 10350 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
10351 | |
10352 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10353 | ctl &= ~PLANE_CTL_TILED_MASK; | |
bae781b2 | 10354 | switch (fb->modifier) { |
2f075565 | 10355 | case DRM_FORMAT_MOD_LINEAR: |
5a21b665 DV |
10356 | break; |
10357 | case I915_FORMAT_MOD_X_TILED: | |
10358 | ctl |= PLANE_CTL_TILED_X; | |
10359 | break; | |
10360 | case I915_FORMAT_MOD_Y_TILED: | |
10361 | ctl |= PLANE_CTL_TILED_Y; | |
10362 | break; | |
10363 | case I915_FORMAT_MOD_Yf_TILED: | |
10364 | ctl |= PLANE_CTL_TILED_YF; | |
10365 | break; | |
10366 | default: | |
bae781b2 | 10367 | MISSING_CASE(fb->modifier); |
5a21b665 DV |
10368 | } |
10369 | ||
5a21b665 DV |
10370 | /* |
10371 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10372 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10373 | */ | |
10374 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10375 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10376 | ||
10377 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
10378 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10379 | } | |
10380 | ||
10381 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
10382 | struct intel_flip_work *work) | |
10383 | { | |
10384 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 10385 | struct drm_i915_private *dev_priv = to_i915(dev); |
72618ebf | 10386 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
5a21b665 DV |
10387 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
10388 | u32 dspcntr; | |
10389 | ||
10390 | dspcntr = I915_READ(reg); | |
10391 | ||
bae781b2 | 10392 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
5a21b665 DV |
10393 | dspcntr |= DISPPLANE_TILED; |
10394 | else | |
10395 | dspcntr &= ~DISPPLANE_TILED; | |
10396 | ||
10397 | I915_WRITE(reg, dspcntr); | |
10398 | ||
10399 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
10400 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
10401 | } | |
10402 | ||
10403 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
10404 | { | |
10405 | struct intel_flip_work *work = | |
10406 | container_of(w, struct intel_flip_work, mmio_work); | |
10407 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
10408 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
10409 | struct intel_framebuffer *intel_fb = | |
10410 | to_intel_framebuffer(crtc->base.primary->fb); | |
10411 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10412 | ||
d07f0e59 | 10413 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); |
5a21b665 DV |
10414 | |
10415 | intel_pipe_update_start(crtc); | |
10416 | ||
10417 | if (INTEL_GEN(dev_priv) >= 9) | |
10418 | skl_do_mmio_flip(crtc, work->rotation, work); | |
10419 | else | |
10420 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10421 | ilk_do_mmio_flip(crtc, work); | |
10422 | ||
10423 | intel_pipe_update_end(crtc, work); | |
10424 | } | |
10425 | ||
10426 | static int intel_default_queue_flip(struct drm_device *dev, | |
10427 | struct drm_crtc *crtc, | |
10428 | struct drm_framebuffer *fb, | |
10429 | struct drm_i915_gem_object *obj, | |
10430 | struct drm_i915_gem_request *req, | |
10431 | uint32_t flags) | |
10432 | { | |
10433 | return -ENODEV; | |
10434 | } | |
10435 | ||
10436 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
10437 | struct intel_crtc *intel_crtc, | |
10438 | struct intel_flip_work *work) | |
10439 | { | |
10440 | u32 addr, vblank; | |
10441 | ||
10442 | if (!atomic_read(&work->pending)) | |
10443 | return false; | |
10444 | ||
10445 | smp_rmb(); | |
10446 | ||
10447 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
10448 | if (work->flip_ready_vblank == 0) { | |
10449 | if (work->flip_queued_req && | |
f69a02c9 | 10450 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
10451 | return false; |
10452 | ||
10453 | work->flip_ready_vblank = vblank; | |
10454 | } | |
10455 | ||
10456 | if (vblank - work->flip_ready_vblank < 3) | |
10457 | return false; | |
10458 | ||
10459 | /* Potential stall - if we see that the flip has happened, | |
10460 | * assume a missed interrupt. */ | |
10461 | if (INTEL_GEN(dev_priv) >= 4) | |
10462 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10463 | else | |
10464 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10465 | ||
10466 | /* There is a potential issue here with a false positive after a flip | |
10467 | * to the same address. We could address this by checking for a | |
10468 | * non-incrementing frame counter. | |
10469 | */ | |
10470 | return addr == work->gtt_offset; | |
10471 | } | |
10472 | ||
10473 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
10474 | { | |
91c8a326 | 10475 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10476 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
10477 | struct intel_flip_work *work; |
10478 | ||
10479 | WARN_ON(!in_interrupt()); | |
10480 | ||
10481 | if (crtc == NULL) | |
10482 | return; | |
10483 | ||
10484 | spin_lock(&dev->event_lock); | |
e2af48c6 | 10485 | work = crtc->flip_work; |
5a21b665 DV |
10486 | |
10487 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 10488 | __pageflip_stall_check_cs(dev_priv, crtc, work)) { |
5a21b665 DV |
10489 | WARN_ONCE(1, |
10490 | "Kicking stuck page flip: queued at %d, now %d\n", | |
e2af48c6 VS |
10491 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); |
10492 | page_flip_completed(crtc); | |
5a21b665 DV |
10493 | work = NULL; |
10494 | } | |
10495 | ||
10496 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 10497 | intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) |
5a21b665 DV |
10498 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
10499 | spin_unlock(&dev->event_lock); | |
10500 | } | |
10501 | ||
4c01ded5 | 10502 | __maybe_unused |
5a21b665 DV |
10503 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10504 | struct drm_framebuffer *fb, | |
10505 | struct drm_pending_vblank_event *event, | |
10506 | uint32_t page_flip_flags) | |
10507 | { | |
10508 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10509 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
10510 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
10511 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
10512 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10513 | struct drm_plane *primary = crtc->primary; | |
10514 | enum pipe pipe = intel_crtc->pipe; | |
10515 | struct intel_flip_work *work; | |
10516 | struct intel_engine_cs *engine; | |
10517 | bool mmio_flip; | |
8e637178 | 10518 | struct drm_i915_gem_request *request; |
058d88c4 | 10519 | struct i915_vma *vma; |
5a21b665 DV |
10520 | int ret; |
10521 | ||
10522 | /* | |
10523 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10524 | * check to be safe. In the future we may enable pageflipping from | |
10525 | * a disabled primary plane. | |
10526 | */ | |
10527 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10528 | return -EBUSY; | |
10529 | ||
10530 | /* Can't change pixel format via MI display flips. */ | |
dbd4d576 | 10531 | if (fb->format != crtc->primary->fb->format) |
5a21b665 DV |
10532 | return -EINVAL; |
10533 | ||
10534 | /* | |
10535 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10536 | * Note that pitch changes could also affect these register. | |
10537 | */ | |
6315b5d3 | 10538 | if (INTEL_GEN(dev_priv) > 3 && |
5a21b665 DV |
10539 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10540 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
10541 | return -EINVAL; | |
10542 | ||
10543 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
10544 | goto out_hang; | |
10545 | ||
10546 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
10547 | if (work == NULL) | |
10548 | return -ENOMEM; | |
10549 | ||
10550 | work->event = event; | |
10551 | work->crtc = crtc; | |
10552 | work->old_fb = old_fb; | |
10553 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
10554 | ||
10555 | ret = drm_crtc_vblank_get(crtc); | |
10556 | if (ret) | |
10557 | goto free_work; | |
10558 | ||
10559 | /* We borrow the event spin lock for protecting flip_work */ | |
10560 | spin_lock_irq(&dev->event_lock); | |
10561 | if (intel_crtc->flip_work) { | |
10562 | /* Before declaring the flip queue wedged, check if | |
10563 | * the hardware completed the operation behind our backs. | |
10564 | */ | |
10565 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
10566 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10567 | page_flip_completed(intel_crtc); | |
10568 | } else { | |
10569 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
10570 | spin_unlock_irq(&dev->event_lock); | |
10571 | ||
10572 | drm_crtc_vblank_put(crtc); | |
10573 | kfree(work); | |
10574 | return -EBUSY; | |
10575 | } | |
10576 | } | |
10577 | intel_crtc->flip_work = work; | |
10578 | spin_unlock_irq(&dev->event_lock); | |
10579 | ||
10580 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
10581 | flush_workqueue(dev_priv->wq); | |
10582 | ||
10583 | /* Reference the objects for the scheduled work. */ | |
10584 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
10585 | |
10586 | crtc->primary->fb = fb; | |
10587 | update_state_fb(crtc->primary); | |
faf68d92 | 10588 | |
25dc556a | 10589 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
10590 | |
10591 | ret = i915_mutex_lock_interruptible(dev); | |
10592 | if (ret) | |
10593 | goto cleanup; | |
10594 | ||
8af29b0c | 10595 | intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); |
8c185eca | 10596 | if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) { |
5a21b665 | 10597 | ret = -EIO; |
ddbb271a | 10598 | goto unlock; |
5a21b665 DV |
10599 | } |
10600 | ||
10601 | atomic_inc(&intel_crtc->unpin_work_count); | |
10602 | ||
9beb5fea | 10603 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
5a21b665 DV |
10604 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
10605 | ||
920a14b2 | 10606 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3b3f1650 | 10607 | engine = dev_priv->engine[BCS]; |
bae781b2 | 10608 | if (fb->modifier != old_fb->modifier) |
5a21b665 DV |
10609 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10610 | engine = NULL; | |
fd6b8f43 | 10611 | } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { |
3b3f1650 | 10612 | engine = dev_priv->engine[BCS]; |
6315b5d3 | 10613 | } else if (INTEL_GEN(dev_priv) >= 7) { |
d07f0e59 | 10614 | engine = i915_gem_object_last_write_engine(obj); |
5a21b665 | 10615 | if (engine == NULL || engine->id != RCS) |
3b3f1650 | 10616 | engine = dev_priv->engine[BCS]; |
5a21b665 | 10617 | } else { |
3b3f1650 | 10618 | engine = dev_priv->engine[RCS]; |
5a21b665 DV |
10619 | } |
10620 | ||
10621 | mmio_flip = use_mmio_flip(engine, obj); | |
10622 | ||
058d88c4 CW |
10623 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
10624 | if (IS_ERR(vma)) { | |
10625 | ret = PTR_ERR(vma); | |
5a21b665 | 10626 | goto cleanup_pending; |
058d88c4 | 10627 | } |
5a21b665 | 10628 | |
be1e3415 CW |
10629 | work->old_vma = to_intel_plane_state(primary->state)->vma; |
10630 | to_intel_plane_state(primary->state)->vma = vma; | |
10631 | ||
10632 | work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset; | |
5a21b665 DV |
10633 | work->rotation = crtc->primary->state->rotation; |
10634 | ||
1f061316 PZ |
10635 | /* |
10636 | * There's the potential that the next frame will not be compatible with | |
10637 | * FBC, so we want to call pre_update() before the actual page flip. | |
10638 | * The problem is that pre_update() caches some information about the fb | |
10639 | * object, so we want to do this only after the object is pinned. Let's | |
10640 | * be on the safe side and do this immediately before scheduling the | |
10641 | * flip. | |
10642 | */ | |
10643 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
10644 | to_intel_plane_state(primary->state)); | |
10645 | ||
5a21b665 DV |
10646 | if (mmio_flip) { |
10647 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
6277c8d0 | 10648 | queue_work(system_unbound_wq, &work->mmio_work); |
5a21b665 | 10649 | } else { |
e8a9c58f CW |
10650 | request = i915_gem_request_alloc(engine, |
10651 | dev_priv->kernel_context); | |
8e637178 CW |
10652 | if (IS_ERR(request)) { |
10653 | ret = PTR_ERR(request); | |
10654 | goto cleanup_unpin; | |
10655 | } | |
10656 | ||
a2bc4695 | 10657 | ret = i915_gem_request_await_object(request, obj, false); |
8e637178 CW |
10658 | if (ret) |
10659 | goto cleanup_request; | |
10660 | ||
5a21b665 DV |
10661 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
10662 | page_flip_flags); | |
10663 | if (ret) | |
8e637178 | 10664 | goto cleanup_request; |
5a21b665 DV |
10665 | |
10666 | intel_mark_page_flip_active(intel_crtc, work); | |
10667 | ||
8e637178 | 10668 | work->flip_queued_req = i915_gem_request_get(request); |
e642c85b | 10669 | i915_add_request(request); |
5a21b665 DV |
10670 | } |
10671 | ||
92117f0b | 10672 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); |
5a21b665 DV |
10673 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, |
10674 | to_intel_plane(primary)->frontbuffer_bit); | |
10675 | mutex_unlock(&dev->struct_mutex); | |
10676 | ||
5748b6a1 | 10677 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
10678 | to_intel_plane(primary)->frontbuffer_bit); |
10679 | ||
10680 | trace_i915_flip_request(intel_crtc->plane, obj); | |
10681 | ||
10682 | return 0; | |
10683 | ||
8e637178 | 10684 | cleanup_request: |
e642c85b | 10685 | i915_add_request(request); |
5a21b665 | 10686 | cleanup_unpin: |
be1e3415 CW |
10687 | to_intel_plane_state(primary->state)->vma = work->old_vma; |
10688 | intel_unpin_fb_vma(vma); | |
5a21b665 | 10689 | cleanup_pending: |
5a21b665 | 10690 | atomic_dec(&intel_crtc->unpin_work_count); |
ddbb271a | 10691 | unlock: |
5a21b665 DV |
10692 | mutex_unlock(&dev->struct_mutex); |
10693 | cleanup: | |
10694 | crtc->primary->fb = old_fb; | |
10695 | update_state_fb(crtc->primary); | |
10696 | ||
f0cd5182 | 10697 | i915_gem_object_put(obj); |
5a21b665 DV |
10698 | drm_framebuffer_unreference(work->old_fb); |
10699 | ||
10700 | spin_lock_irq(&dev->event_lock); | |
10701 | intel_crtc->flip_work = NULL; | |
10702 | spin_unlock_irq(&dev->event_lock); | |
10703 | ||
10704 | drm_crtc_vblank_put(crtc); | |
10705 | free_work: | |
10706 | kfree(work); | |
10707 | ||
10708 | if (ret == -EIO) { | |
10709 | struct drm_atomic_state *state; | |
10710 | struct drm_plane_state *plane_state; | |
10711 | ||
10712 | out_hang: | |
10713 | state = drm_atomic_state_alloc(dev); | |
10714 | if (!state) | |
10715 | return -ENOMEM; | |
b260ac3e | 10716 | state->acquire_ctx = dev->mode_config.acquire_ctx; |
5a21b665 DV |
10717 | |
10718 | retry: | |
10719 | plane_state = drm_atomic_get_plane_state(state, primary); | |
10720 | ret = PTR_ERR_OR_ZERO(plane_state); | |
10721 | if (!ret) { | |
10722 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10723 | ||
10724 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
10725 | if (!ret) | |
10726 | ret = drm_atomic_commit(state); | |
10727 | } | |
10728 | ||
10729 | if (ret == -EDEADLK) { | |
10730 | drm_modeset_backoff(state->acquire_ctx); | |
10731 | drm_atomic_state_clear(state); | |
10732 | goto retry; | |
10733 | } | |
10734 | ||
0853695c | 10735 | drm_atomic_state_put(state); |
5a21b665 DV |
10736 | |
10737 | if (ret == 0 && event) { | |
10738 | spin_lock_irq(&dev->event_lock); | |
10739 | drm_crtc_send_vblank_event(crtc, event); | |
10740 | spin_unlock_irq(&dev->event_lock); | |
10741 | } | |
10742 | } | |
10743 | return ret; | |
10744 | } | |
10745 | ||
10746 | ||
10747 | /** | |
10748 | * intel_wm_need_update - Check whether watermarks need updating | |
10749 | * @plane: drm plane | |
10750 | * @state: new plane state | |
10751 | * | |
10752 | * Check current plane state versus the new one to determine whether | |
10753 | * watermarks need to be recalculated. | |
10754 | * | |
10755 | * Returns true or false. | |
10756 | */ | |
10757 | static bool intel_wm_need_update(struct drm_plane *plane, | |
10758 | struct drm_plane_state *state) | |
10759 | { | |
10760 | struct intel_plane_state *new = to_intel_plane_state(state); | |
10761 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
10762 | ||
10763 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 10764 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
10765 | return true; |
10766 | ||
10767 | if (!cur->base.fb || !new->base.fb) | |
10768 | return false; | |
10769 | ||
bae781b2 | 10770 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 10771 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
10772 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
10773 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
10774 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
10775 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
10776 | return true; |
10777 | ||
10778 | return false; | |
10779 | } | |
10780 | ||
10781 | static bool needs_scaling(struct intel_plane_state *state) | |
10782 | { | |
936e71e3 VS |
10783 | int src_w = drm_rect_width(&state->base.src) >> 16; |
10784 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
10785 | int dst_w = drm_rect_width(&state->base.dst); | |
10786 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
10787 | |
10788 | return (src_w != dst_w || src_h != dst_h); | |
10789 | } | |
d21fbe87 | 10790 | |
da20eabd ML |
10791 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
10792 | struct drm_plane_state *plane_state) | |
10793 | { | |
ab1d3a0e | 10794 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
10795 | struct drm_crtc *crtc = crtc_state->crtc; |
10796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e9728bd8 | 10797 | struct intel_plane *plane = to_intel_plane(plane_state->plane); |
da20eabd | 10798 | struct drm_device *dev = crtc->dev; |
ed4a6a7c | 10799 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd | 10800 | struct intel_plane_state *old_plane_state = |
e9728bd8 | 10801 | to_intel_plane_state(plane->base.state); |
da20eabd ML |
10802 | bool mode_changed = needs_modeset(crtc_state); |
10803 | bool was_crtc_enabled = crtc->state->active; | |
10804 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
10805 | bool turn_off, turn_on, visible, was_visible; |
10806 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 10807 | int ret; |
da20eabd | 10808 | |
e9728bd8 | 10809 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
da20eabd ML |
10810 | ret = skl_update_scaler_plane( |
10811 | to_intel_crtc_state(crtc_state), | |
10812 | to_intel_plane_state(plane_state)); | |
10813 | if (ret) | |
10814 | return ret; | |
10815 | } | |
10816 | ||
936e71e3 | 10817 | was_visible = old_plane_state->base.visible; |
1d4258db | 10818 | visible = plane_state->visible; |
da20eabd ML |
10819 | |
10820 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
10821 | was_visible = false; | |
10822 | ||
35c08f43 ML |
10823 | /* |
10824 | * Visibility is calculated as if the crtc was on, but | |
10825 | * after scaler setup everything depends on it being off | |
10826 | * when the crtc isn't active. | |
f818ffea VS |
10827 | * |
10828 | * FIXME this is wrong for watermarks. Watermarks should also | |
10829 | * be computed as if the pipe would be active. Perhaps move | |
10830 | * per-plane wm computation to the .check_plane() hook, and | |
10831 | * only combine the results from all planes in the current place? | |
35c08f43 | 10832 | */ |
e9728bd8 | 10833 | if (!is_crtc_enabled) { |
1d4258db | 10834 | plane_state->visible = visible = false; |
e9728bd8 VS |
10835 | to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); |
10836 | } | |
da20eabd ML |
10837 | |
10838 | if (!was_visible && !visible) | |
10839 | return 0; | |
10840 | ||
e8861675 ML |
10841 | if (fb != old_plane_state->base.fb) |
10842 | pipe_config->fb_changed = true; | |
10843 | ||
da20eabd ML |
10844 | turn_off = was_visible && (!visible || mode_changed); |
10845 | turn_on = visible && (!was_visible || mode_changed); | |
10846 | ||
72660ce0 | 10847 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
e9728bd8 VS |
10848 | intel_crtc->base.base.id, intel_crtc->base.name, |
10849 | plane->base.base.id, plane->base.name, | |
72660ce0 | 10850 | fb ? fb->base.id : -1); |
da20eabd | 10851 | |
72660ce0 | 10852 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
e9728bd8 | 10853 | plane->base.base.id, plane->base.name, |
72660ce0 | 10854 | was_visible, visible, |
da20eabd ML |
10855 | turn_off, turn_on, mode_changed); |
10856 | ||
caed361d | 10857 | if (turn_on) { |
04548cba | 10858 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10859 | pipe_config->update_wm_pre = true; |
caed361d VS |
10860 | |
10861 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 10862 | if (plane->id != PLANE_CURSOR) |
caed361d VS |
10863 | pipe_config->disable_cxsr = true; |
10864 | } else if (turn_off) { | |
04548cba | 10865 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10866 | pipe_config->update_wm_post = true; |
92826fcd | 10867 | |
852eb00d | 10868 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 10869 | if (plane->id != PLANE_CURSOR) |
ab1d3a0e | 10870 | pipe_config->disable_cxsr = true; |
e9728bd8 | 10871 | } else if (intel_wm_need_update(&plane->base, plane_state)) { |
04548cba | 10872 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
b4ede6df VS |
10873 | /* FIXME bollocks */ |
10874 | pipe_config->update_wm_pre = true; | |
10875 | pipe_config->update_wm_post = true; | |
10876 | } | |
852eb00d | 10877 | } |
da20eabd | 10878 | |
8be6ca85 | 10879 | if (visible || was_visible) |
e9728bd8 | 10880 | pipe_config->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 10881 | |
31ae71fc ML |
10882 | /* |
10883 | * WaCxSRDisabledForSpriteScaling:ivb | |
10884 | * | |
10885 | * cstate->update_wm was already set above, so this flag will | |
10886 | * take effect when we commit and program watermarks. | |
10887 | */ | |
e9728bd8 | 10888 | if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
10889 | needs_scaling(to_intel_plane_state(plane_state)) && |
10890 | !needs_scaling(old_plane_state)) | |
10891 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 10892 | |
da20eabd ML |
10893 | return 0; |
10894 | } | |
10895 | ||
6d3a1ce7 ML |
10896 | static bool encoders_cloneable(const struct intel_encoder *a, |
10897 | const struct intel_encoder *b) | |
10898 | { | |
10899 | /* masks could be asymmetric, so check both ways */ | |
10900 | return a == b || (a->cloneable & (1 << b->type) && | |
10901 | b->cloneable & (1 << a->type)); | |
10902 | } | |
10903 | ||
10904 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
10905 | struct intel_crtc *crtc, | |
10906 | struct intel_encoder *encoder) | |
10907 | { | |
10908 | struct intel_encoder *source_encoder; | |
10909 | struct drm_connector *connector; | |
10910 | struct drm_connector_state *connector_state; | |
10911 | int i; | |
10912 | ||
aa5e9b47 | 10913 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
6d3a1ce7 ML |
10914 | if (connector_state->crtc != &crtc->base) |
10915 | continue; | |
10916 | ||
10917 | source_encoder = | |
10918 | to_intel_encoder(connector_state->best_encoder); | |
10919 | if (!encoders_cloneable(encoder, source_encoder)) | |
10920 | return false; | |
10921 | } | |
10922 | ||
10923 | return true; | |
10924 | } | |
10925 | ||
6d3a1ce7 ML |
10926 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
10927 | struct drm_crtc_state *crtc_state) | |
10928 | { | |
cf5a15be | 10929 | struct drm_device *dev = crtc->dev; |
fac5e23e | 10930 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 10931 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
10932 | struct intel_crtc_state *pipe_config = |
10933 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 10934 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 10935 | int ret; |
6d3a1ce7 ML |
10936 | bool mode_changed = needs_modeset(crtc_state); |
10937 | ||
852eb00d | 10938 | if (mode_changed && !crtc_state->active) |
caed361d | 10939 | pipe_config->update_wm_post = true; |
eddfcbcd | 10940 | |
ad421372 ML |
10941 | if (mode_changed && crtc_state->enable && |
10942 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 10943 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
10944 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
10945 | pipe_config); | |
10946 | if (ret) | |
10947 | return ret; | |
10948 | } | |
10949 | ||
82cf435b LL |
10950 | if (crtc_state->color_mgmt_changed) { |
10951 | ret = intel_color_check(crtc, crtc_state); | |
10952 | if (ret) | |
10953 | return ret; | |
e7852a4b LL |
10954 | |
10955 | /* | |
10956 | * Changing color management on Intel hardware is | |
10957 | * handled as part of planes update. | |
10958 | */ | |
10959 | crtc_state->planes_changed = true; | |
82cf435b LL |
10960 | } |
10961 | ||
e435d6e5 | 10962 | ret = 0; |
86c8bbbe | 10963 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 10964 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
10965 | if (ret) { |
10966 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
10967 | return ret; | |
10968 | } | |
10969 | } | |
10970 | ||
10971 | if (dev_priv->display.compute_intermediate_wm && | |
10972 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
10973 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
10974 | return 0; | |
10975 | ||
10976 | /* | |
10977 | * Calculate 'intermediate' watermarks that satisfy both the | |
10978 | * old state and the new state. We can program these | |
10979 | * immediately. | |
10980 | */ | |
6315b5d3 | 10981 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
10982 | intel_crtc, |
10983 | pipe_config); | |
10984 | if (ret) { | |
10985 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 10986 | return ret; |
ed4a6a7c | 10987 | } |
e3d5457c VS |
10988 | } else if (dev_priv->display.compute_intermediate_wm) { |
10989 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
10990 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
10991 | } |
10992 | ||
6315b5d3 | 10993 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
10994 | if (mode_changed) |
10995 | ret = skl_update_scaler_crtc(pipe_config); | |
10996 | ||
10997 | if (!ret) | |
6ebc6923 | 10998 | ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, |
e435d6e5 ML |
10999 | pipe_config); |
11000 | } | |
11001 | ||
11002 | return ret; | |
6d3a1ce7 ML |
11003 | } |
11004 | ||
65b38e0d | 11005 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
5a21b665 DV |
11006 | .atomic_begin = intel_begin_crtc_commit, |
11007 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11008 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11009 | }; |
11010 | ||
d29b2f9d ACO |
11011 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11012 | { | |
11013 | struct intel_connector *connector; | |
f9e905ca | 11014 | struct drm_connector_list_iter conn_iter; |
d29b2f9d | 11015 | |
f9e905ca DV |
11016 | drm_connector_list_iter_begin(dev, &conn_iter); |
11017 | for_each_intel_connector_iter(connector, &conn_iter) { | |
8863dc7f DV |
11018 | if (connector->base.state->crtc) |
11019 | drm_connector_unreference(&connector->base); | |
11020 | ||
d29b2f9d ACO |
11021 | if (connector->base.encoder) { |
11022 | connector->base.state->best_encoder = | |
11023 | connector->base.encoder; | |
11024 | connector->base.state->crtc = | |
11025 | connector->base.encoder->crtc; | |
8863dc7f DV |
11026 | |
11027 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
11028 | } else { |
11029 | connector->base.state->best_encoder = NULL; | |
11030 | connector->base.state->crtc = NULL; | |
11031 | } | |
11032 | } | |
f9e905ca | 11033 | drm_connector_list_iter_end(&conn_iter); |
d29b2f9d ACO |
11034 | } |
11035 | ||
050f7aeb | 11036 | static void |
eba905b2 | 11037 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11038 | struct intel_crtc_state *pipe_config) |
050f7aeb | 11039 | { |
6a2a5c5d | 11040 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
11041 | int bpp = pipe_config->pipe_bpp; |
11042 | ||
11043 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
11044 | connector->base.base.id, |
11045 | connector->base.name); | |
050f7aeb DV |
11046 | |
11047 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 11048 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 11049 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
11050 | bpp, info->bpc * 3); |
11051 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
11052 | } |
11053 | ||
196f954e | 11054 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 11055 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
11056 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
11057 | bpp); | |
11058 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
11059 | } |
11060 | } | |
11061 | ||
4e53c2e0 | 11062 | static int |
050f7aeb | 11063 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11064 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11065 | { |
9beb5fea | 11066 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 11067 | struct drm_atomic_state *state; |
da3ced29 ACO |
11068 | struct drm_connector *connector; |
11069 | struct drm_connector_state *connector_state; | |
1486017f | 11070 | int bpp, i; |
4e53c2e0 | 11071 | |
9beb5fea TU |
11072 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
11073 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 11074 | bpp = 10*3; |
9beb5fea | 11075 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
11076 | bpp = 12*3; |
11077 | else | |
11078 | bpp = 8*3; | |
11079 | ||
4e53c2e0 | 11080 | |
4e53c2e0 DV |
11081 | pipe_config->pipe_bpp = bpp; |
11082 | ||
1486017f ACO |
11083 | state = pipe_config->base.state; |
11084 | ||
4e53c2e0 | 11085 | /* Clamp display bpp to EDID value */ |
aa5e9b47 | 11086 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
da3ced29 | 11087 | if (connector_state->crtc != &crtc->base) |
4e53c2e0 DV |
11088 | continue; |
11089 | ||
da3ced29 ACO |
11090 | connected_sink_compute_bpp(to_intel_connector(connector), |
11091 | pipe_config); | |
4e53c2e0 DV |
11092 | } |
11093 | ||
11094 | return bpp; | |
11095 | } | |
11096 | ||
644db711 DV |
11097 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11098 | { | |
11099 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11100 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11101 | mode->crtc_clock, |
644db711 DV |
11102 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11103 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11104 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11105 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11106 | } | |
11107 | ||
f6982332 TU |
11108 | static inline void |
11109 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 11110 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 11111 | { |
a4309657 TU |
11112 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11113 | id, lane_count, | |
f6982332 TU |
11114 | m_n->gmch_m, m_n->gmch_n, |
11115 | m_n->link_m, m_n->link_n, m_n->tu); | |
11116 | } | |
11117 | ||
c0b03411 | 11118 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11119 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11120 | const char *context) |
11121 | { | |
6a60cd87 | 11122 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 11123 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
11124 | struct drm_plane *plane; |
11125 | struct intel_plane *intel_plane; | |
11126 | struct intel_plane_state *state; | |
11127 | struct drm_framebuffer *fb; | |
11128 | ||
66766e4f TU |
11129 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
11130 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 11131 | |
2c89429e TU |
11132 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
11133 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 11134 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
11135 | |
11136 | if (pipe_config->has_pch_encoder) | |
11137 | intel_dump_m_n_config(pipe_config, "fdi", | |
11138 | pipe_config->fdi_lanes, | |
11139 | &pipe_config->fdi_m_n); | |
f6982332 TU |
11140 | |
11141 | if (intel_crtc_has_dp_encoder(pipe_config)) { | |
a4309657 TU |
11142 | intel_dump_m_n_config(pipe_config, "dp m_n", |
11143 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
11144 | if (pipe_config->has_drrs) |
11145 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
11146 | pipe_config->lane_count, | |
11147 | &pipe_config->dp_m2_n2); | |
f6982332 | 11148 | } |
b95af8be | 11149 | |
55072d19 | 11150 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 11151 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 11152 | |
c0b03411 | 11153 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11154 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11155 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11156 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11157 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
a7d1b3f4 | 11158 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", |
2c89429e | 11159 | pipe_config->port_clock, |
a7d1b3f4 VS |
11160 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
11161 | pipe_config->pixel_rate); | |
dd2f616d TU |
11162 | |
11163 | if (INTEL_GEN(dev_priv) >= 9) | |
11164 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
11165 | crtc->num_scalers, | |
11166 | pipe_config->scaler_state.scaler_users, | |
11167 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
11168 | |
11169 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
11170 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
11171 | pipe_config->gmch_pfit.control, | |
11172 | pipe_config->gmch_pfit.pgm_ratios, | |
11173 | pipe_config->gmch_pfit.lvds_border_bits); | |
11174 | else | |
11175 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
11176 | pipe_config->pch_pfit.pos, | |
11177 | pipe_config->pch_pfit.size, | |
08c4d7fc | 11178 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 11179 | |
2c89429e TU |
11180 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
11181 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 11182 | |
f50b79f0 | 11183 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 11184 | |
6a60cd87 CK |
11185 | DRM_DEBUG_KMS("planes on this crtc\n"); |
11186 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 11187 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
11188 | intel_plane = to_intel_plane(plane); |
11189 | if (intel_plane->pipe != crtc->pipe) | |
11190 | continue; | |
11191 | ||
11192 | state = to_intel_plane_state(plane->state); | |
11193 | fb = state->base.fb; | |
11194 | if (!fb) { | |
1d577e02 VS |
11195 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
11196 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
11197 | continue; |
11198 | } | |
11199 | ||
dd2f616d TU |
11200 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
11201 | plane->base.id, plane->name, | |
b3c11ac2 | 11202 | fb->base.id, fb->width, fb->height, |
438b74a5 | 11203 | drm_get_format_name(fb->format->format, &format_name)); |
dd2f616d TU |
11204 | if (INTEL_GEN(dev_priv) >= 9) |
11205 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
11206 | state->scaler_id, | |
11207 | state->base.src.x1 >> 16, | |
11208 | state->base.src.y1 >> 16, | |
11209 | drm_rect_width(&state->base.src) >> 16, | |
11210 | drm_rect_height(&state->base.src) >> 16, | |
11211 | state->base.dst.x1, state->base.dst.y1, | |
11212 | drm_rect_width(&state->base.dst), | |
11213 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 11214 | } |
c0b03411 DV |
11215 | } |
11216 | ||
5448a00d | 11217 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11218 | { |
5448a00d | 11219 | struct drm_device *dev = state->dev; |
da3ced29 | 11220 | struct drm_connector *connector; |
00f0b378 | 11221 | unsigned int used_ports = 0; |
477321e0 | 11222 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
11223 | |
11224 | /* | |
11225 | * Walk the connector list instead of the encoder | |
11226 | * list to detect the problem on ddi platforms | |
11227 | * where there's just one encoder per digital port. | |
11228 | */ | |
0bff4858 VS |
11229 | drm_for_each_connector(connector, dev) { |
11230 | struct drm_connector_state *connector_state; | |
11231 | struct intel_encoder *encoder; | |
11232 | ||
11233 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
11234 | if (!connector_state) | |
11235 | connector_state = connector->state; | |
11236 | ||
5448a00d | 11237 | if (!connector_state->best_encoder) |
00f0b378 VS |
11238 | continue; |
11239 | ||
5448a00d ACO |
11240 | encoder = to_intel_encoder(connector_state->best_encoder); |
11241 | ||
11242 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11243 | |
11244 | switch (encoder->type) { | |
11245 | unsigned int port_mask; | |
11246 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 11247 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 11248 | break; |
cca0502b | 11249 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
11250 | case INTEL_OUTPUT_HDMI: |
11251 | case INTEL_OUTPUT_EDP: | |
11252 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11253 | ||
11254 | /* the same port mustn't appear more than once */ | |
11255 | if (used_ports & port_mask) | |
11256 | return false; | |
11257 | ||
11258 | used_ports |= port_mask; | |
477321e0 VS |
11259 | break; |
11260 | case INTEL_OUTPUT_DP_MST: | |
11261 | used_mst_ports |= | |
11262 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
11263 | break; | |
00f0b378 VS |
11264 | default: |
11265 | break; | |
11266 | } | |
11267 | } | |
11268 | ||
477321e0 VS |
11269 | /* can't mix MST and SST/HDMI on the same port */ |
11270 | if (used_ports & used_mst_ports) | |
11271 | return false; | |
11272 | ||
00f0b378 VS |
11273 | return true; |
11274 | } | |
11275 | ||
83a57153 ACO |
11276 | static void |
11277 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11278 | { | |
ff32c54e VS |
11279 | struct drm_i915_private *dev_priv = |
11280 | to_i915(crtc_state->base.crtc->dev); | |
663a3640 | 11281 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 11282 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 11283 | struct intel_shared_dpll *shared_dpll; |
ff32c54e | 11284 | struct intel_crtc_wm_state wm_state; |
c4e2d043 | 11285 | bool force_thru; |
83a57153 | 11286 | |
7546a384 ACO |
11287 | /* FIXME: before the switch to atomic started, a new pipe_config was |
11288 | * kzalloc'd. Code that depends on any field being zero should be | |
11289 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
11290 | * only fields that are know to not cause problems are preserved. */ | |
11291 | ||
663a3640 | 11292 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
11293 | shared_dpll = crtc_state->shared_dpll; |
11294 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 11295 | force_thru = crtc_state->pch_pfit.force_thru; |
04548cba VS |
11296 | if (IS_G4X(dev_priv) || |
11297 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 11298 | wm_state = crtc_state->wm; |
4978cc93 | 11299 | |
d2fa80a5 CW |
11300 | /* Keep base drm_crtc_state intact, only clear our extended struct */ |
11301 | BUILD_BUG_ON(offsetof(struct intel_crtc_state, base)); | |
11302 | memset(&crtc_state->base + 1, 0, | |
11303 | sizeof(*crtc_state) - sizeof(crtc_state->base)); | |
4978cc93 | 11304 | |
663a3640 | 11305 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
11306 | crtc_state->shared_dpll = shared_dpll; |
11307 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 11308 | crtc_state->pch_pfit.force_thru = force_thru; |
04548cba VS |
11309 | if (IS_G4X(dev_priv) || |
11310 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 11311 | crtc_state->wm = wm_state; |
83a57153 ACO |
11312 | } |
11313 | ||
548ee15b | 11314 | static int |
b8cecdf5 | 11315 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 11316 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 11317 | { |
b359283a | 11318 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 11319 | struct intel_encoder *encoder; |
da3ced29 | 11320 | struct drm_connector *connector; |
0b901879 | 11321 | struct drm_connector_state *connector_state; |
d328c9d7 | 11322 | int base_bpp, ret = -EINVAL; |
0b901879 | 11323 | int i; |
e29c22c0 | 11324 | bool retry = true; |
ee7b9f93 | 11325 | |
83a57153 | 11326 | clear_intel_crtc_state(pipe_config); |
7758a113 | 11327 | |
e143a21c DV |
11328 | pipe_config->cpu_transcoder = |
11329 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 11330 | |
2960bc9c ID |
11331 | /* |
11332 | * Sanitize sync polarity flags based on requested ones. If neither | |
11333 | * positive or negative polarity is requested, treat this as meaning | |
11334 | * negative polarity. | |
11335 | */ | |
2d112de7 | 11336 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11337 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11338 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11339 | |
2d112de7 | 11340 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11341 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11342 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11343 | |
d328c9d7 DV |
11344 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11345 | pipe_config); | |
11346 | if (base_bpp < 0) | |
4e53c2e0 DV |
11347 | goto fail; |
11348 | ||
e41a56be VS |
11349 | /* |
11350 | * Determine the real pipe dimensions. Note that stereo modes can | |
11351 | * increase the actual pipe size due to the frame doubling and | |
11352 | * insertion of additional space for blanks between the frame. This | |
11353 | * is stored in the crtc timings. We use the requested mode to do this | |
11354 | * computation to clearly distinguish it from the adjusted mode, which | |
11355 | * can be changed by the connectors in the below retry loop. | |
11356 | */ | |
196cd5d3 | 11357 | drm_mode_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11358 | &pipe_config->pipe_src_w, |
11359 | &pipe_config->pipe_src_h); | |
e41a56be | 11360 | |
aa5e9b47 | 11361 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
253c84c8 VS |
11362 | if (connector_state->crtc != crtc) |
11363 | continue; | |
11364 | ||
11365 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11366 | ||
e25148d0 VS |
11367 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
11368 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11369 | goto fail; | |
11370 | } | |
11371 | ||
253c84c8 VS |
11372 | /* |
11373 | * Determine output_types before calling the .compute_config() | |
11374 | * hooks so that the hooks can use this information safely. | |
11375 | */ | |
11376 | pipe_config->output_types |= 1 << encoder->type; | |
11377 | } | |
11378 | ||
e29c22c0 | 11379 | encoder_retry: |
ef1b460d | 11380 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11381 | pipe_config->port_clock = 0; |
ef1b460d | 11382 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11383 | |
135c81b8 | 11384 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11385 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11386 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11387 | |
7758a113 DV |
11388 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11389 | * adjust it according to limitations or connector properties, and also | |
11390 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11391 | */ |
aa5e9b47 | 11392 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 11393 | if (connector_state->crtc != crtc) |
7758a113 | 11394 | continue; |
7ae89233 | 11395 | |
0b901879 ACO |
11396 | encoder = to_intel_encoder(connector_state->best_encoder); |
11397 | ||
0a478c27 | 11398 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 11399 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
11400 | goto fail; |
11401 | } | |
ee7b9f93 | 11402 | } |
47f1c6c9 | 11403 | |
ff9a6750 DV |
11404 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11405 | * done afterwards in case the encoder adjusts the mode. */ | |
11406 | if (!pipe_config->port_clock) | |
2d112de7 | 11407 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11408 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11409 | |
a43f6e0f | 11410 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11411 | if (ret < 0) { |
7758a113 DV |
11412 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11413 | goto fail; | |
ee7b9f93 | 11414 | } |
e29c22c0 DV |
11415 | |
11416 | if (ret == RETRY) { | |
11417 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11418 | ret = -EINVAL; | |
11419 | goto fail; | |
11420 | } | |
11421 | ||
11422 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11423 | retry = false; | |
11424 | goto encoder_retry; | |
11425 | } | |
11426 | ||
e8fa4270 | 11427 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
11428 | * only enable it on 6bpc panels and when its not a compliance |
11429 | * test requesting 6bpc video pattern. | |
11430 | */ | |
11431 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
11432 | !pipe_config->dither_force_disable; | |
62f0ace5 | 11433 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11434 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11435 | |
7758a113 | 11436 | fail: |
548ee15b | 11437 | return ret; |
ee7b9f93 | 11438 | } |
47f1c6c9 | 11439 | |
ea9d758d | 11440 | static void |
4740b0f2 | 11441 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 11442 | { |
0a9ab303 | 11443 | struct drm_crtc *crtc; |
aa5e9b47 | 11444 | struct drm_crtc_state *new_crtc_state; |
8a75d157 | 11445 | int i; |
ea9d758d | 11446 | |
7668851f | 11447 | /* Double check state. */ |
aa5e9b47 ML |
11448 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
11449 | to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state); | |
fc467a22 ML |
11450 | |
11451 | /* Update hwmode for vblank functions */ | |
aa5e9b47 ML |
11452 | if (new_crtc_state->active) |
11453 | crtc->hwmode = new_crtc_state->adjusted_mode; | |
fc467a22 ML |
11454 | else |
11455 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
11456 | |
11457 | /* | |
11458 | * Update legacy state to satisfy fbc code. This can | |
11459 | * be removed when fbc uses the atomic state. | |
11460 | */ | |
11461 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
11462 | struct drm_plane_state *plane_state = crtc->primary->state; | |
11463 | ||
11464 | crtc->primary->fb = plane_state->fb; | |
11465 | crtc->x = plane_state->src_x >> 16; | |
11466 | crtc->y = plane_state->src_y >> 16; | |
11467 | } | |
ea9d758d | 11468 | } |
ea9d758d DV |
11469 | } |
11470 | ||
3bd26263 | 11471 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11472 | { |
3bd26263 | 11473 | int diff; |
f1f644dc JB |
11474 | |
11475 | if (clock1 == clock2) | |
11476 | return true; | |
11477 | ||
11478 | if (!clock1 || !clock2) | |
11479 | return false; | |
11480 | ||
11481 | diff = abs(clock1 - clock2); | |
11482 | ||
11483 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11484 | return true; | |
11485 | ||
11486 | return false; | |
11487 | } | |
11488 | ||
cfb23ed6 ML |
11489 | static bool |
11490 | intel_compare_m_n(unsigned int m, unsigned int n, | |
11491 | unsigned int m2, unsigned int n2, | |
11492 | bool exact) | |
11493 | { | |
11494 | if (m == m2 && n == n2) | |
11495 | return true; | |
11496 | ||
11497 | if (exact || !m || !n || !m2 || !n2) | |
11498 | return false; | |
11499 | ||
11500 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
11501 | ||
31d10b57 ML |
11502 | if (n > n2) { |
11503 | while (n > n2) { | |
cfb23ed6 ML |
11504 | m2 <<= 1; |
11505 | n2 <<= 1; | |
11506 | } | |
31d10b57 ML |
11507 | } else if (n < n2) { |
11508 | while (n < n2) { | |
cfb23ed6 ML |
11509 | m <<= 1; |
11510 | n <<= 1; | |
11511 | } | |
11512 | } | |
11513 | ||
31d10b57 ML |
11514 | if (n != n2) |
11515 | return false; | |
11516 | ||
11517 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
11518 | } |
11519 | ||
11520 | static bool | |
11521 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
11522 | struct intel_link_m_n *m2_n2, | |
11523 | bool adjust) | |
11524 | { | |
11525 | if (m_n->tu == m2_n2->tu && | |
11526 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
11527 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
11528 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
11529 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
11530 | if (adjust) | |
11531 | *m2_n2 = *m_n; | |
11532 | ||
11533 | return true; | |
11534 | } | |
11535 | ||
11536 | return false; | |
11537 | } | |
11538 | ||
4e8048f8 TU |
11539 | static void __printf(3, 4) |
11540 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
11541 | { | |
11542 | char *level; | |
11543 | unsigned int category; | |
11544 | struct va_format vaf; | |
11545 | va_list args; | |
11546 | ||
11547 | if (adjust) { | |
11548 | level = KERN_DEBUG; | |
11549 | category = DRM_UT_KMS; | |
11550 | } else { | |
11551 | level = KERN_ERR; | |
11552 | category = DRM_UT_NONE; | |
11553 | } | |
11554 | ||
11555 | va_start(args, format); | |
11556 | vaf.fmt = format; | |
11557 | vaf.va = &args; | |
11558 | ||
11559 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
11560 | ||
11561 | va_end(args); | |
11562 | } | |
11563 | ||
0e8ffe1b | 11564 | static bool |
6315b5d3 | 11565 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 11566 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
11567 | struct intel_crtc_state *pipe_config, |
11568 | bool adjust) | |
0e8ffe1b | 11569 | { |
cfb23ed6 ML |
11570 | bool ret = true; |
11571 | ||
66e985c0 DV |
11572 | #define PIPE_CONF_CHECK_X(name) \ |
11573 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11574 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
11575 | "(expected 0x%08x, found 0x%08x)\n", \ |
11576 | current_config->name, \ | |
11577 | pipe_config->name); \ | |
cfb23ed6 | 11578 | ret = false; \ |
66e985c0 DV |
11579 | } |
11580 | ||
08a24034 DV |
11581 | #define PIPE_CONF_CHECK_I(name) \ |
11582 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11583 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
11584 | "(expected %i, found %i)\n", \ |
11585 | current_config->name, \ | |
11586 | pipe_config->name); \ | |
cfb23ed6 ML |
11587 | ret = false; \ |
11588 | } | |
11589 | ||
8106ddbd ACO |
11590 | #define PIPE_CONF_CHECK_P(name) \ |
11591 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11592 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
11593 | "(expected %p, found %p)\n", \ |
11594 | current_config->name, \ | |
11595 | pipe_config->name); \ | |
11596 | ret = false; \ | |
11597 | } | |
11598 | ||
cfb23ed6 ML |
11599 | #define PIPE_CONF_CHECK_M_N(name) \ |
11600 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11601 | &pipe_config->name,\ | |
11602 | adjust)) { \ | |
4e8048f8 | 11603 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11604 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11605 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11606 | current_config->name.tu, \ | |
11607 | current_config->name.gmch_m, \ | |
11608 | current_config->name.gmch_n, \ | |
11609 | current_config->name.link_m, \ | |
11610 | current_config->name.link_n, \ | |
11611 | pipe_config->name.tu, \ | |
11612 | pipe_config->name.gmch_m, \ | |
11613 | pipe_config->name.gmch_n, \ | |
11614 | pipe_config->name.link_m, \ | |
11615 | pipe_config->name.link_n); \ | |
11616 | ret = false; \ | |
11617 | } | |
11618 | ||
55c561a7 DV |
11619 | /* This is required for BDW+ where there is only one set of registers for |
11620 | * switching between high and low RR. | |
11621 | * This macro can be used whenever a comparison has to be made between one | |
11622 | * hw state and multiple sw state variables. | |
11623 | */ | |
cfb23ed6 ML |
11624 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
11625 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11626 | &pipe_config->name, adjust) && \ | |
11627 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
11628 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 11629 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11630 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11631 | "or tu %i gmch %i/%i link %i/%i, " \ | |
11632 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11633 | current_config->name.tu, \ | |
11634 | current_config->name.gmch_m, \ | |
11635 | current_config->name.gmch_n, \ | |
11636 | current_config->name.link_m, \ | |
11637 | current_config->name.link_n, \ | |
11638 | current_config->alt_name.tu, \ | |
11639 | current_config->alt_name.gmch_m, \ | |
11640 | current_config->alt_name.gmch_n, \ | |
11641 | current_config->alt_name.link_m, \ | |
11642 | current_config->alt_name.link_n, \ | |
11643 | pipe_config->name.tu, \ | |
11644 | pipe_config->name.gmch_m, \ | |
11645 | pipe_config->name.gmch_n, \ | |
11646 | pipe_config->name.link_m, \ | |
11647 | pipe_config->name.link_n); \ | |
11648 | ret = false; \ | |
88adfff1 DV |
11649 | } |
11650 | ||
1bd1bd80 DV |
11651 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11652 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
11653 | pipe_config_err(adjust, __stringify(name), \ |
11654 | "(%x) (expected %i, found %i)\n", \ | |
11655 | (mask), \ | |
1bd1bd80 DV |
11656 | current_config->name & (mask), \ |
11657 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 11658 | ret = false; \ |
1bd1bd80 DV |
11659 | } |
11660 | ||
5e550656 VS |
11661 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11662 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 11663 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
11664 | "(expected %i, found %i)\n", \ |
11665 | current_config->name, \ | |
11666 | pipe_config->name); \ | |
cfb23ed6 | 11667 | ret = false; \ |
5e550656 VS |
11668 | } |
11669 | ||
bb760063 DV |
11670 | #define PIPE_CONF_QUIRK(quirk) \ |
11671 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11672 | ||
eccb140b DV |
11673 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11674 | ||
08a24034 DV |
11675 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11676 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 11677 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 11678 | |
90a6b7b0 | 11679 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 11680 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 11681 | |
6315b5d3 | 11682 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
11683 | PIPE_CONF_CHECK_M_N(dp_m_n); |
11684 | ||
cfb23ed6 ML |
11685 | if (current_config->has_drrs) |
11686 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
11687 | } else | |
11688 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 11689 | |
253c84c8 | 11690 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 11691 | |
2d112de7 ACO |
11692 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11693 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11694 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11695 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11696 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11697 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11698 | |
2d112de7 ACO |
11699 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11700 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11701 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11702 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11703 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11704 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11705 | |
c93f54cf | 11706 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11707 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 11708 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 11709 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 11710 | PIPE_CONF_CHECK_I(limited_color_range); |
15953637 SS |
11711 | |
11712 | PIPE_CONF_CHECK_I(hdmi_scrambling); | |
11713 | PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio); | |
e43823ec | 11714 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11715 | |
9ed109a7 DV |
11716 | PIPE_CONF_CHECK_I(has_audio); |
11717 | ||
2d112de7 | 11718 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11719 | DRM_MODE_FLAG_INTERLACE); |
11720 | ||
bb760063 | 11721 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11722 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11723 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11724 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11725 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11726 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11727 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11728 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11729 | DRM_MODE_FLAG_NVSYNC); |
11730 | } | |
045ac3b5 | 11731 | |
333b8ca8 | 11732 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 11733 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 11734 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 11735 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 11736 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 11737 | |
bfd16b2a ML |
11738 | if (!adjust) { |
11739 | PIPE_CONF_CHECK_I(pipe_src_w); | |
11740 | PIPE_CONF_CHECK_I(pipe_src_h); | |
11741 | ||
11742 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
11743 | if (current_config->pch_pfit.enabled) { | |
11744 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
11745 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
11746 | } | |
2fa2fe9a | 11747 | |
7aefe2b5 | 11748 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 11749 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
7aefe2b5 | 11750 | } |
a1b2278e | 11751 | |
e59150dc | 11752 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 11753 | if (IS_HASWELL(dev_priv)) |
e59150dc | 11754 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 11755 | |
282740f7 VS |
11756 | PIPE_CONF_CHECK_I(double_wide); |
11757 | ||
8106ddbd | 11758 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 11759 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11760 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11761 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11762 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11763 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 11764 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
11765 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11766 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11767 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11768 | |
47eacbab VS |
11769 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
11770 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
11771 | ||
9beb5fea | 11772 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
11773 | PIPE_CONF_CHECK_I(pipe_bpp); |
11774 | ||
2d112de7 | 11775 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11776 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11777 | |
66e985c0 | 11778 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11779 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 11780 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 11781 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11782 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11783 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11784 | |
cfb23ed6 | 11785 | return ret; |
0e8ffe1b DV |
11786 | } |
11787 | ||
e3b247da VS |
11788 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
11789 | const struct intel_crtc_state *pipe_config) | |
11790 | { | |
11791 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 11792 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
11793 | &pipe_config->fdi_m_n); |
11794 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
11795 | ||
11796 | /* | |
11797 | * FDI already provided one idea for the dotclock. | |
11798 | * Yell if the encoder disagrees. | |
11799 | */ | |
11800 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
11801 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
11802 | fdi_dotclock, dotclock); | |
11803 | } | |
11804 | } | |
11805 | ||
c0ead703 ML |
11806 | static void verify_wm_state(struct drm_crtc *crtc, |
11807 | struct drm_crtc_state *new_state) | |
08db6652 | 11808 | { |
6315b5d3 | 11809 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 11810 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 11811 | struct skl_pipe_wm hw_wm, *sw_wm; |
11812 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
11813 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
11814 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11815 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 11816 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 11817 | |
6315b5d3 | 11818 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
11819 | return; |
11820 | ||
3de8a14c | 11821 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 11822 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 11823 | |
08db6652 DL |
11824 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
11825 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11826 | ||
e7c84544 | 11827 | /* planes */ |
8b364b41 | 11828 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 11829 | hw_plane_wm = &hw_wm.planes[plane]; |
11830 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 11831 | |
3de8a14c | 11832 | /* Watermarks */ |
11833 | for (level = 0; level <= max_level; level++) { | |
11834 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11835 | &sw_plane_wm->wm[level])) | |
11836 | continue; | |
11837 | ||
11838 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11839 | pipe_name(pipe), plane + 1, level, | |
11840 | sw_plane_wm->wm[level].plane_en, | |
11841 | sw_plane_wm->wm[level].plane_res_b, | |
11842 | sw_plane_wm->wm[level].plane_res_l, | |
11843 | hw_plane_wm->wm[level].plane_en, | |
11844 | hw_plane_wm->wm[level].plane_res_b, | |
11845 | hw_plane_wm->wm[level].plane_res_l); | |
11846 | } | |
08db6652 | 11847 | |
3de8a14c | 11848 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
11849 | &sw_plane_wm->trans_wm)) { | |
11850 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11851 | pipe_name(pipe), plane + 1, | |
11852 | sw_plane_wm->trans_wm.plane_en, | |
11853 | sw_plane_wm->trans_wm.plane_res_b, | |
11854 | sw_plane_wm->trans_wm.plane_res_l, | |
11855 | hw_plane_wm->trans_wm.plane_en, | |
11856 | hw_plane_wm->trans_wm.plane_res_b, | |
11857 | hw_plane_wm->trans_wm.plane_res_l); | |
11858 | } | |
11859 | ||
11860 | /* DDB */ | |
11861 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
11862 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
11863 | ||
11864 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 11865 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 11866 | pipe_name(pipe), plane + 1, |
11867 | sw_ddb_entry->start, sw_ddb_entry->end, | |
11868 | hw_ddb_entry->start, hw_ddb_entry->end); | |
11869 | } | |
e7c84544 | 11870 | } |
08db6652 | 11871 | |
27082493 L |
11872 | /* |
11873 | * cursor | |
11874 | * If the cursor plane isn't active, we may not have updated it's ddb | |
11875 | * allocation. In that case since the ddb allocation will be updated | |
11876 | * once the plane becomes visible, we can skip this check | |
11877 | */ | |
11878 | if (intel_crtc->cursor_addr) { | |
3de8a14c | 11879 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
11880 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
11881 | ||
11882 | /* Watermarks */ | |
11883 | for (level = 0; level <= max_level; level++) { | |
11884 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11885 | &sw_plane_wm->wm[level])) | |
11886 | continue; | |
11887 | ||
11888 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11889 | pipe_name(pipe), level, | |
11890 | sw_plane_wm->wm[level].plane_en, | |
11891 | sw_plane_wm->wm[level].plane_res_b, | |
11892 | sw_plane_wm->wm[level].plane_res_l, | |
11893 | hw_plane_wm->wm[level].plane_en, | |
11894 | hw_plane_wm->wm[level].plane_res_b, | |
11895 | hw_plane_wm->wm[level].plane_res_l); | |
11896 | } | |
11897 | ||
11898 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
11899 | &sw_plane_wm->trans_wm)) { | |
11900 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11901 | pipe_name(pipe), | |
11902 | sw_plane_wm->trans_wm.plane_en, | |
11903 | sw_plane_wm->trans_wm.plane_res_b, | |
11904 | sw_plane_wm->trans_wm.plane_res_l, | |
11905 | hw_plane_wm->trans_wm.plane_en, | |
11906 | hw_plane_wm->trans_wm.plane_res_b, | |
11907 | hw_plane_wm->trans_wm.plane_res_l); | |
11908 | } | |
11909 | ||
11910 | /* DDB */ | |
11911 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
11912 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 11913 | |
3de8a14c | 11914 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 11915 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 11916 | pipe_name(pipe), |
3de8a14c | 11917 | sw_ddb_entry->start, sw_ddb_entry->end, |
11918 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 11919 | } |
08db6652 DL |
11920 | } |
11921 | } | |
11922 | ||
91d1b4bd | 11923 | static void |
677100ce ML |
11924 | verify_connector_state(struct drm_device *dev, |
11925 | struct drm_atomic_state *state, | |
11926 | struct drm_crtc *crtc) | |
8af6cf88 | 11927 | { |
35dd3c64 | 11928 | struct drm_connector *connector; |
aa5e9b47 | 11929 | struct drm_connector_state *new_conn_state; |
677100ce | 11930 | int i; |
8af6cf88 | 11931 | |
aa5e9b47 | 11932 | for_each_new_connector_in_state(state, connector, new_conn_state, i) { |
35dd3c64 | 11933 | struct drm_encoder *encoder = connector->encoder; |
ad3c558f | 11934 | |
aa5e9b47 | 11935 | if (new_conn_state->crtc != crtc) |
e7c84544 ML |
11936 | continue; |
11937 | ||
5a21b665 | 11938 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 11939 | |
aa5e9b47 | 11940 | I915_STATE_WARN(new_conn_state->best_encoder != encoder, |
35dd3c64 | 11941 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 11942 | } |
91d1b4bd DV |
11943 | } |
11944 | ||
11945 | static void | |
86b04268 | 11946 | verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state) |
91d1b4bd DV |
11947 | { |
11948 | struct intel_encoder *encoder; | |
86b04268 DV |
11949 | struct drm_connector *connector; |
11950 | struct drm_connector_state *old_conn_state, *new_conn_state; | |
11951 | int i; | |
8af6cf88 | 11952 | |
b2784e15 | 11953 | for_each_intel_encoder(dev, encoder) { |
86b04268 | 11954 | bool enabled = false, found = false; |
4d20cd86 | 11955 | enum pipe pipe; |
8af6cf88 DV |
11956 | |
11957 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11958 | encoder->base.base.id, | |
8e329a03 | 11959 | encoder->base.name); |
8af6cf88 | 11960 | |
86b04268 DV |
11961 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, |
11962 | new_conn_state, i) { | |
11963 | if (old_conn_state->best_encoder == &encoder->base) | |
11964 | found = true; | |
11965 | ||
11966 | if (new_conn_state->best_encoder != &encoder->base) | |
8af6cf88 | 11967 | continue; |
86b04268 | 11968 | found = enabled = true; |
ad3c558f | 11969 | |
86b04268 | 11970 | I915_STATE_WARN(new_conn_state->crtc != |
ad3c558f ML |
11971 | encoder->base.crtc, |
11972 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 11973 | } |
86b04268 DV |
11974 | |
11975 | if (!found) | |
11976 | continue; | |
0e32b39c | 11977 | |
e2c719b7 | 11978 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11979 | "encoder's enabled state mismatch " |
11980 | "(expected %i, found %i)\n", | |
11981 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
11982 | |
11983 | if (!encoder->base.crtc) { | |
4d20cd86 | 11984 | bool active; |
7c60d198 | 11985 | |
4d20cd86 ML |
11986 | active = encoder->get_hw_state(encoder, &pipe); |
11987 | I915_STATE_WARN(active, | |
11988 | "encoder detached but still enabled on pipe %c.\n", | |
11989 | pipe_name(pipe)); | |
7c60d198 | 11990 | } |
8af6cf88 | 11991 | } |
91d1b4bd DV |
11992 | } |
11993 | ||
11994 | static void | |
c0ead703 ML |
11995 | verify_crtc_state(struct drm_crtc *crtc, |
11996 | struct drm_crtc_state *old_crtc_state, | |
11997 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 11998 | { |
e7c84544 | 11999 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12000 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 12001 | struct intel_encoder *encoder; |
e7c84544 ML |
12002 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12003 | struct intel_crtc_state *pipe_config, *sw_config; | |
12004 | struct drm_atomic_state *old_state; | |
12005 | bool active; | |
045ac3b5 | 12006 | |
e7c84544 | 12007 | old_state = old_crtc_state->state; |
ec2dc6a0 | 12008 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
12009 | pipe_config = to_intel_crtc_state(old_crtc_state); |
12010 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12011 | pipe_config->base.crtc = crtc; | |
12012 | pipe_config->base.state = old_state; | |
8af6cf88 | 12013 | |
78108b7c | 12014 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 12015 | |
e7c84544 | 12016 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 12017 | |
e7c84544 ML |
12018 | /* hw state is inconsistent with the pipe quirk */ |
12019 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12020 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12021 | active = new_crtc_state->active; | |
6c49f241 | 12022 | |
e7c84544 ML |
12023 | I915_STATE_WARN(new_crtc_state->active != active, |
12024 | "crtc active state doesn't match with hw state " | |
12025 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 12026 | |
e7c84544 ML |
12027 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
12028 | "transitional active state does not match atomic hw state " | |
12029 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 12030 | |
e7c84544 ML |
12031 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
12032 | enum pipe pipe; | |
4d20cd86 | 12033 | |
e7c84544 ML |
12034 | active = encoder->get_hw_state(encoder, &pipe); |
12035 | I915_STATE_WARN(active != new_crtc_state->active, | |
12036 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12037 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 12038 | |
e7c84544 ML |
12039 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
12040 | "Encoder connected to wrong pipe %c\n", | |
12041 | pipe_name(pipe)); | |
4d20cd86 | 12042 | |
253c84c8 VS |
12043 | if (active) { |
12044 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 12045 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 12046 | } |
e7c84544 | 12047 | } |
53d9f4e9 | 12048 | |
a7d1b3f4 VS |
12049 | intel_crtc_compute_pixel_rate(pipe_config); |
12050 | ||
e7c84544 ML |
12051 | if (!new_crtc_state->active) |
12052 | return; | |
cfb23ed6 | 12053 | |
e7c84544 | 12054 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 12055 | |
e7c84544 | 12056 | sw_config = to_intel_crtc_state(crtc->state); |
6315b5d3 | 12057 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
12058 | pipe_config, false)) { |
12059 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
12060 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
12061 | "[hw state]"); | |
12062 | intel_dump_pipe_config(intel_crtc, sw_config, | |
12063 | "[sw state]"); | |
8af6cf88 DV |
12064 | } |
12065 | } | |
12066 | ||
91d1b4bd | 12067 | static void |
c0ead703 ML |
12068 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
12069 | struct intel_shared_dpll *pll, | |
12070 | struct drm_crtc *crtc, | |
12071 | struct drm_crtc_state *new_state) | |
91d1b4bd | 12072 | { |
91d1b4bd | 12073 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
12074 | unsigned crtc_mask; |
12075 | bool active; | |
5358901f | 12076 | |
e7c84544 | 12077 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 12078 | |
e7c84544 | 12079 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 12080 | |
e7c84544 | 12081 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12082 | |
e7c84544 ML |
12083 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
12084 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
12085 | "pll in active use but not on in sw tracking\n"); | |
12086 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12087 | "pll is on but not used by any active crtc\n"); | |
12088 | I915_STATE_WARN(pll->on != active, | |
12089 | "pll on state mismatch (expected %i, found %i)\n", | |
12090 | pll->on, active); | |
12091 | } | |
5358901f | 12092 | |
e7c84544 | 12093 | if (!crtc) { |
2c42e535 | 12094 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 12095 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 12096 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 12097 | |
e7c84544 ML |
12098 | return; |
12099 | } | |
12100 | ||
12101 | crtc_mask = 1 << drm_crtc_index(crtc); | |
12102 | ||
12103 | if (new_state->active) | |
12104 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
12105 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
12106 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
12107 | else | |
12108 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12109 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
12110 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 12111 | |
2c42e535 | 12112 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 12113 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 12114 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 12115 | |
2c42e535 | 12116 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
12117 | &dpll_hw_state, |
12118 | sizeof(dpll_hw_state)), | |
12119 | "pll hw state mismatch\n"); | |
12120 | } | |
12121 | ||
12122 | static void | |
c0ead703 ML |
12123 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
12124 | struct drm_crtc_state *old_crtc_state, | |
12125 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 12126 | { |
fac5e23e | 12127 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
12128 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
12129 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
12130 | ||
12131 | if (new_state->shared_dpll) | |
c0ead703 | 12132 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
12133 | |
12134 | if (old_state->shared_dpll && | |
12135 | old_state->shared_dpll != new_state->shared_dpll) { | |
12136 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
12137 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
12138 | ||
12139 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12140 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
12141 | pipe_name(drm_crtc_index(crtc))); | |
2c42e535 | 12142 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 ML |
12143 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
12144 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 12145 | } |
8af6cf88 DV |
12146 | } |
12147 | ||
e7c84544 | 12148 | static void |
c0ead703 | 12149 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
12150 | struct drm_atomic_state *state, |
12151 | struct drm_crtc_state *old_state, | |
12152 | struct drm_crtc_state *new_state) | |
e7c84544 | 12153 | { |
5a21b665 DV |
12154 | if (!needs_modeset(new_state) && |
12155 | !to_intel_crtc_state(new_state)->update_pipe) | |
12156 | return; | |
12157 | ||
c0ead703 | 12158 | verify_wm_state(crtc, new_state); |
677100ce | 12159 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
12160 | verify_crtc_state(crtc, old_state, new_state); |
12161 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
12162 | } |
12163 | ||
12164 | static void | |
c0ead703 | 12165 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 12166 | { |
fac5e23e | 12167 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
12168 | int i; |
12169 | ||
12170 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 12171 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
12172 | } |
12173 | ||
12174 | static void | |
677100ce ML |
12175 | intel_modeset_verify_disabled(struct drm_device *dev, |
12176 | struct drm_atomic_state *state) | |
e7c84544 | 12177 | { |
86b04268 | 12178 | verify_encoder_state(dev, state); |
677100ce | 12179 | verify_connector_state(dev, state, NULL); |
c0ead703 | 12180 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
12181 | } |
12182 | ||
80715b2f VS |
12183 | static void update_scanline_offset(struct intel_crtc *crtc) |
12184 | { | |
4f8036a2 | 12185 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
12186 | |
12187 | /* | |
12188 | * The scanline counter increments at the leading edge of hsync. | |
12189 | * | |
12190 | * On most platforms it starts counting from vtotal-1 on the | |
12191 | * first active line. That means the scanline counter value is | |
12192 | * always one less than what we would expect. Ie. just after | |
12193 | * start of vblank, which also occurs at start of hsync (on the | |
12194 | * last active line), the scanline counter will read vblank_start-1. | |
12195 | * | |
12196 | * On gen2 the scanline counter starts counting from 1 instead | |
12197 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12198 | * to keep the value positive), instead of adding one. | |
12199 | * | |
12200 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12201 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12202 | * there's an extra 1 line difference. So we need to add two instead of | |
12203 | * one to the value. | |
12204 | */ | |
4f8036a2 | 12205 | if (IS_GEN2(dev_priv)) { |
124abe07 | 12206 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12207 | int vtotal; |
12208 | ||
124abe07 VS |
12209 | vtotal = adjusted_mode->crtc_vtotal; |
12210 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
12211 | vtotal /= 2; |
12212 | ||
12213 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 12214 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 12215 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12216 | crtc->scanline_offset = 2; |
12217 | } else | |
12218 | crtc->scanline_offset = 1; | |
12219 | } | |
12220 | ||
ad421372 | 12221 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12222 | { |
225da59b | 12223 | struct drm_device *dev = state->dev; |
ed6739ef | 12224 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 12225 | struct drm_crtc *crtc; |
aa5e9b47 | 12226 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
0a9ab303 | 12227 | int i; |
ed6739ef ACO |
12228 | |
12229 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12230 | return; |
ed6739ef | 12231 | |
aa5e9b47 | 12232 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
fb1a38a9 | 12233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd | 12234 | struct intel_shared_dpll *old_dpll = |
aa5e9b47 | 12235 | to_intel_crtc_state(old_crtc_state)->shared_dpll; |
0a9ab303 | 12236 | |
aa5e9b47 | 12237 | if (!needs_modeset(new_crtc_state)) |
225da59b ACO |
12238 | continue; |
12239 | ||
aa5e9b47 | 12240 | to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 12241 | |
8106ddbd | 12242 | if (!old_dpll) |
fb1a38a9 | 12243 | continue; |
0a9ab303 | 12244 | |
a1c414ee | 12245 | intel_release_shared_dpll(old_dpll, intel_crtc, state); |
ad421372 | 12246 | } |
ed6739ef ACO |
12247 | } |
12248 | ||
99d736a2 ML |
12249 | /* |
12250 | * This implements the workaround described in the "notes" section of the mode | |
12251 | * set sequence documentation. When going from no pipes or single pipe to | |
12252 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12253 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12254 | */ | |
12255 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12256 | { | |
12257 | struct drm_crtc_state *crtc_state; | |
12258 | struct intel_crtc *intel_crtc; | |
12259 | struct drm_crtc *crtc; | |
12260 | struct intel_crtc_state *first_crtc_state = NULL; | |
12261 | struct intel_crtc_state *other_crtc_state = NULL; | |
12262 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12263 | int i; | |
12264 | ||
12265 | /* look at all crtc's that are going to be enabled in during modeset */ | |
aa5e9b47 | 12266 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
99d736a2 ML |
12267 | intel_crtc = to_intel_crtc(crtc); |
12268 | ||
12269 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12270 | continue; | |
12271 | ||
12272 | if (first_crtc_state) { | |
12273 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
12274 | break; | |
12275 | } else { | |
12276 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
12277 | first_pipe = intel_crtc->pipe; | |
12278 | } | |
12279 | } | |
12280 | ||
12281 | /* No workaround needed? */ | |
12282 | if (!first_crtc_state) | |
12283 | return 0; | |
12284 | ||
12285 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
12286 | for_each_intel_crtc(state->dev, intel_crtc) { | |
12287 | struct intel_crtc_state *pipe_config; | |
12288 | ||
12289 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12290 | if (IS_ERR(pipe_config)) | |
12291 | return PTR_ERR(pipe_config); | |
12292 | ||
12293 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
12294 | ||
12295 | if (!pipe_config->base.active || | |
12296 | needs_modeset(&pipe_config->base)) | |
12297 | continue; | |
12298 | ||
12299 | /* 2 or more enabled crtcs means no need for w/a */ | |
12300 | if (enabled_pipe != INVALID_PIPE) | |
12301 | return 0; | |
12302 | ||
12303 | enabled_pipe = intel_crtc->pipe; | |
12304 | } | |
12305 | ||
12306 | if (enabled_pipe != INVALID_PIPE) | |
12307 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
12308 | else if (other_crtc_state) | |
12309 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
12310 | ||
12311 | return 0; | |
12312 | } | |
12313 | ||
8d96561a VS |
12314 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
12315 | { | |
12316 | struct drm_crtc *crtc; | |
12317 | ||
12318 | /* Add all pipes to the state */ | |
12319 | for_each_crtc(state->dev, crtc) { | |
12320 | struct drm_crtc_state *crtc_state; | |
12321 | ||
12322 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
12323 | if (IS_ERR(crtc_state)) | |
12324 | return PTR_ERR(crtc_state); | |
12325 | } | |
12326 | ||
12327 | return 0; | |
12328 | } | |
12329 | ||
27c329ed ML |
12330 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
12331 | { | |
12332 | struct drm_crtc *crtc; | |
27c329ed | 12333 | |
8d96561a VS |
12334 | /* |
12335 | * Add all pipes to the state, and force | |
12336 | * a modeset on all the active ones. | |
12337 | */ | |
27c329ed | 12338 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
12339 | struct drm_crtc_state *crtc_state; |
12340 | int ret; | |
12341 | ||
27c329ed ML |
12342 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
12343 | if (IS_ERR(crtc_state)) | |
12344 | return PTR_ERR(crtc_state); | |
12345 | ||
12346 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
12347 | continue; | |
12348 | ||
12349 | crtc_state->mode_changed = true; | |
12350 | ||
12351 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12352 | if (ret) | |
9780aad5 | 12353 | return ret; |
27c329ed ML |
12354 | |
12355 | ret = drm_atomic_add_affected_planes(state, crtc); | |
12356 | if (ret) | |
9780aad5 | 12357 | return ret; |
27c329ed ML |
12358 | } |
12359 | ||
9780aad5 | 12360 | return 0; |
27c329ed ML |
12361 | } |
12362 | ||
c347a676 | 12363 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 12364 | { |
565602d7 | 12365 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12366 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 | 12367 | struct drm_crtc *crtc; |
aa5e9b47 | 12368 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
565602d7 | 12369 | int ret = 0, i; |
054518dd | 12370 | |
b359283a ML |
12371 | if (!check_digital_port_conflicts(state)) { |
12372 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
12373 | return -EINVAL; | |
12374 | } | |
12375 | ||
565602d7 ML |
12376 | intel_state->modeset = true; |
12377 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
bb0f4aab VS |
12378 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
12379 | intel_state->cdclk.actual = dev_priv->cdclk.actual; | |
565602d7 | 12380 | |
aa5e9b47 ML |
12381 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
12382 | if (new_crtc_state->active) | |
565602d7 ML |
12383 | intel_state->active_crtcs |= 1 << i; |
12384 | else | |
12385 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 | 12386 | |
aa5e9b47 | 12387 | if (old_crtc_state->active != new_crtc_state->active) |
8b4a7d05 | 12388 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); |
565602d7 ML |
12389 | } |
12390 | ||
054518dd ACO |
12391 | /* |
12392 | * See if the config requires any additional preparation, e.g. | |
12393 | * to adjust global state with pipes off. We need to do this | |
12394 | * here so we can get the modeset_pipe updated config for the new | |
12395 | * mode set on this crtc. For other crtcs we need to use the | |
12396 | * adjusted_mode bits in the crtc directly. | |
12397 | */ | |
27c329ed | 12398 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed | 12399 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
12400 | if (ret < 0) |
12401 | return ret; | |
27c329ed | 12402 | |
8d96561a | 12403 | /* |
bb0f4aab | 12404 | * Writes to dev_priv->cdclk.logical must protected by |
8d96561a VS |
12405 | * holding all the crtc locks, even if we don't end up |
12406 | * touching the hardware | |
12407 | */ | |
bb0f4aab VS |
12408 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical, |
12409 | &intel_state->cdclk.logical)) { | |
8d96561a VS |
12410 | ret = intel_lock_all_pipes(state); |
12411 | if (ret < 0) | |
12412 | return ret; | |
12413 | } | |
12414 | ||
12415 | /* All pipes must be switched off while we change the cdclk. */ | |
bb0f4aab VS |
12416 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual, |
12417 | &intel_state->cdclk.actual)) { | |
27c329ed | 12418 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
12419 | if (ret < 0) |
12420 | return ret; | |
12421 | } | |
e8788cbc | 12422 | |
bb0f4aab VS |
12423 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", |
12424 | intel_state->cdclk.logical.cdclk, | |
12425 | intel_state->cdclk.actual.cdclk); | |
e0ca7a6b | 12426 | } else { |
bb0f4aab | 12427 | to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12428 | } |
054518dd | 12429 | |
ad421372 | 12430 | intel_modeset_clear_plls(state); |
054518dd | 12431 | |
565602d7 | 12432 | if (IS_HASWELL(dev_priv)) |
ad421372 | 12433 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 12434 | |
ad421372 | 12435 | return 0; |
c347a676 ACO |
12436 | } |
12437 | ||
aa363136 MR |
12438 | /* |
12439 | * Handle calculation of various watermark data at the end of the atomic check | |
12440 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
12441 | * handlers to ensure that all derived state has been updated. | |
12442 | */ | |
55994c2c | 12443 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
12444 | { |
12445 | struct drm_device *dev = state->dev; | |
98d39494 | 12446 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
12447 | |
12448 | /* Is there platform-specific watermark information to calculate? */ | |
12449 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
12450 | return dev_priv->display.compute_global_watermarks(state); |
12451 | ||
12452 | return 0; | |
aa363136 MR |
12453 | } |
12454 | ||
74c090b1 ML |
12455 | /** |
12456 | * intel_atomic_check - validate state object | |
12457 | * @dev: drm device | |
12458 | * @state: state to validate | |
12459 | */ | |
12460 | static int intel_atomic_check(struct drm_device *dev, | |
12461 | struct drm_atomic_state *state) | |
c347a676 | 12462 | { |
dd8b3bdb | 12463 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 12464 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 | 12465 | struct drm_crtc *crtc; |
aa5e9b47 | 12466 | struct drm_crtc_state *old_crtc_state, *crtc_state; |
c347a676 | 12467 | int ret, i; |
61333b60 | 12468 | bool any_ms = false; |
c347a676 | 12469 | |
74c090b1 | 12470 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
12471 | if (ret) |
12472 | return ret; | |
12473 | ||
aa5e9b47 | 12474 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) { |
cfb23ed6 ML |
12475 | struct intel_crtc_state *pipe_config = |
12476 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
12477 | |
12478 | /* Catch I915_MODE_FLAG_INHERITED */ | |
aa5e9b47 | 12479 | if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags) |
1ed51de9 | 12480 | crtc_state->mode_changed = true; |
cfb23ed6 | 12481 | |
af4a879e | 12482 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
12483 | continue; |
12484 | ||
af4a879e DV |
12485 | if (!crtc_state->enable) { |
12486 | any_ms = true; | |
cfb23ed6 | 12487 | continue; |
af4a879e | 12488 | } |
cfb23ed6 | 12489 | |
26495481 DV |
12490 | /* FIXME: For only active_changed we shouldn't need to do any |
12491 | * state recomputation at all. */ | |
12492 | ||
1ed51de9 DV |
12493 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12494 | if (ret) | |
12495 | return ret; | |
b359283a | 12496 | |
cfb23ed6 | 12497 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
12498 | if (ret) { |
12499 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12500 | pipe_config, "[failed]"); | |
c347a676 | 12501 | return ret; |
25aa1c39 | 12502 | } |
c347a676 | 12503 | |
73831236 | 12504 | if (i915.fastboot && |
6315b5d3 | 12505 | intel_pipe_config_compare(dev_priv, |
aa5e9b47 | 12506 | to_intel_crtc_state(old_crtc_state), |
1ed51de9 | 12507 | pipe_config, true)) { |
26495481 | 12508 | crtc_state->mode_changed = false; |
aa5e9b47 | 12509 | pipe_config->update_pipe = true; |
26495481 DV |
12510 | } |
12511 | ||
af4a879e | 12512 | if (needs_modeset(crtc_state)) |
26495481 | 12513 | any_ms = true; |
cfb23ed6 | 12514 | |
af4a879e DV |
12515 | ret = drm_atomic_add_affected_planes(state, crtc); |
12516 | if (ret) | |
12517 | return ret; | |
61333b60 | 12518 | |
26495481 DV |
12519 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12520 | needs_modeset(crtc_state) ? | |
12521 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
12522 | } |
12523 | ||
61333b60 ML |
12524 | if (any_ms) { |
12525 | ret = intel_modeset_checks(state); | |
12526 | ||
12527 | if (ret) | |
12528 | return ret; | |
e0ca7a6b | 12529 | } else { |
bb0f4aab | 12530 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12531 | } |
76305b1a | 12532 | |
dd8b3bdb | 12533 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
12534 | if (ret) |
12535 | return ret; | |
12536 | ||
f51be2e0 | 12537 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 12538 | return calc_watermark_data(state); |
054518dd ACO |
12539 | } |
12540 | ||
5008e874 | 12541 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 12542 | struct drm_atomic_state *state) |
5008e874 | 12543 | { |
fac5e23e | 12544 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 ML |
12545 | struct drm_crtc_state *crtc_state; |
12546 | struct drm_crtc *crtc; | |
12547 | int i, ret; | |
12548 | ||
aa5e9b47 | 12549 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
5a21b665 | 12550 | if (state->legacy_cursor_update) |
a6747b73 ML |
12551 | continue; |
12552 | ||
5a21b665 DV |
12553 | ret = intel_crtc_wait_for_pending_flips(crtc); |
12554 | if (ret) | |
12555 | return ret; | |
5008e874 | 12556 | |
5a21b665 DV |
12557 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
12558 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
12559 | } |
12560 | ||
f935675f ML |
12561 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
12562 | if (ret) | |
12563 | return ret; | |
12564 | ||
5008e874 | 12565 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 12566 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 12567 | |
5008e874 ML |
12568 | return ret; |
12569 | } | |
12570 | ||
a2991414 ML |
12571 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
12572 | { | |
12573 | struct drm_device *dev = crtc->base.dev; | |
12574 | ||
12575 | if (!dev->max_vblank_count) | |
12576 | return drm_accurate_vblank_count(&crtc->base); | |
12577 | ||
12578 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
12579 | } | |
12580 | ||
5a21b665 DV |
12581 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
12582 | struct drm_i915_private *dev_priv, | |
12583 | unsigned crtc_mask) | |
e8861675 | 12584 | { |
5a21b665 DV |
12585 | unsigned last_vblank_count[I915_MAX_PIPES]; |
12586 | enum pipe pipe; | |
12587 | int ret; | |
e8861675 | 12588 | |
5a21b665 DV |
12589 | if (!crtc_mask) |
12590 | return; | |
e8861675 | 12591 | |
5a21b665 | 12592 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12593 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12594 | pipe); | |
e8861675 | 12595 | |
5a21b665 | 12596 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
12597 | continue; |
12598 | ||
e2af48c6 | 12599 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
12600 | if (WARN_ON(ret != 0)) { |
12601 | crtc_mask &= ~(1 << pipe); | |
12602 | continue; | |
e8861675 ML |
12603 | } |
12604 | ||
e2af48c6 | 12605 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
12606 | } |
12607 | ||
5a21b665 | 12608 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12609 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12610 | pipe); | |
5a21b665 | 12611 | long lret; |
e8861675 | 12612 | |
5a21b665 DV |
12613 | if (!((1 << pipe) & crtc_mask)) |
12614 | continue; | |
d55dbd06 | 12615 | |
5a21b665 DV |
12616 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
12617 | last_vblank_count[pipe] != | |
e2af48c6 | 12618 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 12619 | msecs_to_jiffies(50)); |
d55dbd06 | 12620 | |
5a21b665 | 12621 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 12622 | |
e2af48c6 | 12623 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
12624 | } |
12625 | } | |
12626 | ||
5a21b665 | 12627 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 12628 | { |
5a21b665 DV |
12629 | /* fb updated, need to unpin old fb */ |
12630 | if (crtc_state->fb_changed) | |
12631 | return true; | |
a6747b73 | 12632 | |
5a21b665 DV |
12633 | /* wm changes, need vblank before final wm's */ |
12634 | if (crtc_state->update_wm_post) | |
12635 | return true; | |
a6747b73 | 12636 | |
5eeb798b | 12637 | if (crtc_state->wm.need_postvbl_update) |
5a21b665 | 12638 | return true; |
a6747b73 | 12639 | |
5a21b665 | 12640 | return false; |
e8861675 ML |
12641 | } |
12642 | ||
896e5bb0 L |
12643 | static void intel_update_crtc(struct drm_crtc *crtc, |
12644 | struct drm_atomic_state *state, | |
12645 | struct drm_crtc_state *old_crtc_state, | |
aa5e9b47 | 12646 | struct drm_crtc_state *new_crtc_state, |
896e5bb0 L |
12647 | unsigned int *crtc_vblank_mask) |
12648 | { | |
12649 | struct drm_device *dev = crtc->dev; | |
12650 | struct drm_i915_private *dev_priv = to_i915(dev); | |
12651 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
aa5e9b47 ML |
12652 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); |
12653 | bool modeset = needs_modeset(new_crtc_state); | |
896e5bb0 L |
12654 | |
12655 | if (modeset) { | |
12656 | update_scanline_offset(intel_crtc); | |
12657 | dev_priv->display.crtc_enable(pipe_config, state); | |
12658 | } else { | |
aa5e9b47 ML |
12659 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12660 | pipe_config); | |
896e5bb0 L |
12661 | } |
12662 | ||
12663 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12664 | intel_fbc_enable( | |
12665 | intel_crtc, pipe_config, | |
12666 | to_intel_plane_state(crtc->primary->state)); | |
12667 | } | |
12668 | ||
12669 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
12670 | ||
12671 | if (needs_vblank_wait(pipe_config)) | |
12672 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
12673 | } | |
12674 | ||
12675 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
12676 | unsigned int *crtc_vblank_mask) | |
12677 | { | |
12678 | struct drm_crtc *crtc; | |
aa5e9b47 | 12679 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
896e5bb0 L |
12680 | int i; |
12681 | ||
aa5e9b47 ML |
12682 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
12683 | if (!new_crtc_state->active) | |
896e5bb0 L |
12684 | continue; |
12685 | ||
12686 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 12687 | new_crtc_state, crtc_vblank_mask); |
896e5bb0 L |
12688 | } |
12689 | } | |
12690 | ||
27082493 L |
12691 | static void skl_update_crtcs(struct drm_atomic_state *state, |
12692 | unsigned int *crtc_vblank_mask) | |
12693 | { | |
0f0f74bc | 12694 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
12695 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
12696 | struct drm_crtc *crtc; | |
ce0ba283 | 12697 | struct intel_crtc *intel_crtc; |
aa5e9b47 | 12698 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
ce0ba283 | 12699 | struct intel_crtc_state *cstate; |
27082493 L |
12700 | unsigned int updated = 0; |
12701 | bool progress; | |
12702 | enum pipe pipe; | |
5eff503b ML |
12703 | int i; |
12704 | ||
12705 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
12706 | ||
aa5e9b47 | 12707 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) |
5eff503b | 12708 | /* ignore allocations for crtc's that have been turned off. */ |
aa5e9b47 | 12709 | if (new_crtc_state->active) |
5eff503b | 12710 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; |
27082493 L |
12711 | |
12712 | /* | |
12713 | * Whenever the number of active pipes changes, we need to make sure we | |
12714 | * update the pipes in the right order so that their ddb allocations | |
12715 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
12716 | * cause pipe underruns and other bad stuff. | |
12717 | */ | |
12718 | do { | |
27082493 L |
12719 | progress = false; |
12720 | ||
aa5e9b47 | 12721 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
27082493 L |
12722 | bool vbl_wait = false; |
12723 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
12724 | |
12725 | intel_crtc = to_intel_crtc(crtc); | |
12726 | cstate = to_intel_crtc_state(crtc->state); | |
12727 | pipe = intel_crtc->pipe; | |
27082493 | 12728 | |
5eff503b | 12729 | if (updated & cmask || !cstate->base.active) |
27082493 | 12730 | continue; |
5eff503b ML |
12731 | |
12732 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
12733 | continue; |
12734 | ||
12735 | updated |= cmask; | |
5eff503b | 12736 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
12737 | |
12738 | /* | |
12739 | * If this is an already active pipe, it's DDB changed, | |
12740 | * and this isn't the last pipe that needs updating | |
12741 | * then we need to wait for a vblank to pass for the | |
12742 | * new ddb allocation to take effect. | |
12743 | */ | |
ce0ba283 | 12744 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 12745 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
aa5e9b47 | 12746 | !new_crtc_state->active_changed && |
27082493 L |
12747 | intel_state->wm_results.dirty_pipes != updated) |
12748 | vbl_wait = true; | |
12749 | ||
12750 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 12751 | new_crtc_state, crtc_vblank_mask); |
27082493 L |
12752 | |
12753 | if (vbl_wait) | |
0f0f74bc | 12754 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
12755 | |
12756 | progress = true; | |
12757 | } | |
12758 | } while (progress); | |
12759 | } | |
12760 | ||
ba318c61 CW |
12761 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
12762 | { | |
12763 | struct intel_atomic_state *state, *next; | |
12764 | struct llist_node *freed; | |
12765 | ||
12766 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
12767 | llist_for_each_entry_safe(state, next, freed, freed) | |
12768 | drm_atomic_state_put(&state->base); | |
12769 | } | |
12770 | ||
12771 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
12772 | { | |
12773 | struct drm_i915_private *dev_priv = | |
12774 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
12775 | ||
12776 | intel_atomic_helper_free_state(dev_priv); | |
12777 | } | |
12778 | ||
94f05024 | 12779 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 12780 | { |
94f05024 | 12781 | struct drm_device *dev = state->dev; |
565602d7 | 12782 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12783 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa5e9b47 | 12784 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
7580d774 | 12785 | struct drm_crtc *crtc; |
5a21b665 | 12786 | struct intel_crtc_state *intel_cstate; |
5a21b665 | 12787 | bool hw_check = intel_state->modeset; |
d8fc70b7 | 12788 | u64 put_domains[I915_MAX_PIPES] = {}; |
5a21b665 | 12789 | unsigned crtc_vblank_mask = 0; |
e95433c7 | 12790 | int i; |
a6778b3c | 12791 | |
ea0000f0 DV |
12792 | drm_atomic_helper_wait_for_dependencies(state); |
12793 | ||
c3b32658 | 12794 | if (intel_state->modeset) |
5a21b665 | 12795 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 12796 | |
aa5e9b47 | 12797 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
a539205a ML |
12798 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12799 | ||
aa5e9b47 ML |
12800 | if (needs_modeset(new_crtc_state) || |
12801 | to_intel_crtc_state(new_crtc_state)->update_pipe) { | |
5a21b665 DV |
12802 | hw_check = true; |
12803 | ||
12804 | put_domains[to_intel_crtc(crtc)->pipe] = | |
12805 | modeset_get_crtc_power_domains(crtc, | |
aa5e9b47 | 12806 | to_intel_crtc_state(new_crtc_state)); |
5a21b665 DV |
12807 | } |
12808 | ||
aa5e9b47 | 12809 | if (!needs_modeset(new_crtc_state)) |
61333b60 ML |
12810 | continue; |
12811 | ||
aa5e9b47 ML |
12812 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12813 | to_intel_crtc_state(new_crtc_state)); | |
460da916 | 12814 | |
29ceb0e6 VS |
12815 | if (old_crtc_state->active) { |
12816 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 12817 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 12818 | intel_crtc->active = false; |
58f9c0bc | 12819 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 12820 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
12821 | |
12822 | /* | |
12823 | * Underruns don't always raise | |
12824 | * interrupts, so check manually. | |
12825 | */ | |
12826 | intel_check_cpu_fifo_underruns(dev_priv); | |
12827 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 12828 | |
e62929b3 ML |
12829 | if (!crtc->state->active) { |
12830 | /* | |
12831 | * Make sure we don't call initial_watermarks | |
12832 | * for ILK-style watermark updates. | |
ff32c54e VS |
12833 | * |
12834 | * No clue what this is supposed to achieve. | |
e62929b3 | 12835 | */ |
ff32c54e | 12836 | if (INTEL_GEN(dev_priv) >= 9) |
e62929b3 ML |
12837 | dev_priv->display.initial_watermarks(intel_state, |
12838 | to_intel_crtc_state(crtc->state)); | |
e62929b3 | 12839 | } |
a539205a | 12840 | } |
b8cecdf5 | 12841 | } |
7758a113 | 12842 | |
ea9d758d DV |
12843 | /* Only after disabling all output pipelines that will be changed can we |
12844 | * update the the output configuration. */ | |
4740b0f2 | 12845 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 12846 | |
565602d7 | 12847 | if (intel_state->modeset) { |
4740b0f2 | 12848 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 | 12849 | |
b0587e4d | 12850 | intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
f6d1973d | 12851 | |
656d1b89 L |
12852 | /* |
12853 | * SKL workaround: bspec recommends we disable the SAGV when we | |
12854 | * have more then one pipe enabled | |
12855 | */ | |
56feca91 | 12856 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 12857 | intel_disable_sagv(dev_priv); |
656d1b89 | 12858 | |
677100ce | 12859 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 12860 | } |
47fab737 | 12861 | |
896e5bb0 | 12862 | /* Complete the events for pipes that have now been disabled */ |
aa5e9b47 ML |
12863 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12864 | bool modeset = needs_modeset(new_crtc_state); | |
80715b2f | 12865 | |
1f7528c4 | 12866 | /* Complete events for now disable pipes here. */ |
aa5e9b47 | 12867 | if (modeset && !new_crtc_state->active && new_crtc_state->event) { |
1f7528c4 | 12868 | spin_lock_irq(&dev->event_lock); |
aa5e9b47 | 12869 | drm_crtc_send_vblank_event(crtc, new_crtc_state->event); |
1f7528c4 DV |
12870 | spin_unlock_irq(&dev->event_lock); |
12871 | ||
aa5e9b47 | 12872 | new_crtc_state->event = NULL; |
1f7528c4 | 12873 | } |
177246a8 MR |
12874 | } |
12875 | ||
896e5bb0 L |
12876 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
12877 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
12878 | ||
94f05024 DV |
12879 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
12880 | * already, but still need the state for the delayed optimization. To | |
12881 | * fix this: | |
12882 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
12883 | * - schedule that vblank worker _before_ calling hw_done | |
12884 | * - at the start of commit_tail, cancel it _synchrously | |
12885 | * - switch over to the vblank wait helper in the core after that since | |
12886 | * we don't need out special handling any more. | |
12887 | */ | |
5a21b665 DV |
12888 | if (!state->legacy_cursor_update) |
12889 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
12890 | ||
12891 | /* | |
12892 | * Now that the vblank has passed, we can go ahead and program the | |
12893 | * optimal watermarks on platforms that need two-step watermark | |
12894 | * programming. | |
12895 | * | |
12896 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
12897 | */ | |
aa5e9b47 ML |
12898 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12899 | intel_cstate = to_intel_crtc_state(new_crtc_state); | |
5a21b665 DV |
12900 | |
12901 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
12902 | dev_priv->display.optimize_watermarks(intel_state, |
12903 | intel_cstate); | |
5a21b665 DV |
12904 | } |
12905 | ||
aa5e9b47 | 12906 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
5a21b665 DV |
12907 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); |
12908 | ||
12909 | if (put_domains[i]) | |
12910 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
12911 | ||
aa5e9b47 | 12912 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); |
5a21b665 DV |
12913 | } |
12914 | ||
56feca91 | 12915 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 12916 | intel_enable_sagv(dev_priv); |
656d1b89 | 12917 | |
94f05024 DV |
12918 | drm_atomic_helper_commit_hw_done(state); |
12919 | ||
5a21b665 DV |
12920 | if (intel_state->modeset) |
12921 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
12922 | ||
12923 | mutex_lock(&dev->struct_mutex); | |
12924 | drm_atomic_helper_cleanup_planes(dev, state); | |
12925 | mutex_unlock(&dev->struct_mutex); | |
12926 | ||
ea0000f0 DV |
12927 | drm_atomic_helper_commit_cleanup_done(state); |
12928 | ||
0853695c | 12929 | drm_atomic_state_put(state); |
f30da187 | 12930 | |
75714940 MK |
12931 | /* As one of the primary mmio accessors, KMS has a high likelihood |
12932 | * of triggering bugs in unclaimed access. After we finish | |
12933 | * modesetting, see if an error has been flagged, and if so | |
12934 | * enable debugging for the next modeset - and hope we catch | |
12935 | * the culprit. | |
12936 | * | |
12937 | * XXX note that we assume display power is on at this point. | |
12938 | * This might hold true now but we need to add pm helper to check | |
12939 | * unclaimed only when the hardware is on, as atomic commits | |
12940 | * can happen also when the device is completely off. | |
12941 | */ | |
12942 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
ba318c61 CW |
12943 | |
12944 | intel_atomic_helper_free_state(dev_priv); | |
94f05024 DV |
12945 | } |
12946 | ||
12947 | static void intel_atomic_commit_work(struct work_struct *work) | |
12948 | { | |
c004a90b CW |
12949 | struct drm_atomic_state *state = |
12950 | container_of(work, struct drm_atomic_state, commit_work); | |
12951 | ||
94f05024 DV |
12952 | intel_atomic_commit_tail(state); |
12953 | } | |
12954 | ||
c004a90b CW |
12955 | static int __i915_sw_fence_call |
12956 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
12957 | enum i915_sw_fence_notify notify) | |
12958 | { | |
12959 | struct intel_atomic_state *state = | |
12960 | container_of(fence, struct intel_atomic_state, commit_ready); | |
12961 | ||
12962 | switch (notify) { | |
12963 | case FENCE_COMPLETE: | |
12964 | if (state->base.commit_work.func) | |
12965 | queue_work(system_unbound_wq, &state->base.commit_work); | |
12966 | break; | |
12967 | ||
12968 | case FENCE_FREE: | |
eb955eee CW |
12969 | { |
12970 | struct intel_atomic_helper *helper = | |
12971 | &to_i915(state->base.dev)->atomic_helper; | |
12972 | ||
12973 | if (llist_add(&state->freed, &helper->free_list)) | |
12974 | schedule_work(&helper->free_work); | |
12975 | break; | |
12976 | } | |
c004a90b CW |
12977 | } |
12978 | ||
12979 | return NOTIFY_DONE; | |
12980 | } | |
12981 | ||
6c9c1b38 DV |
12982 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
12983 | { | |
aa5e9b47 | 12984 | struct drm_plane_state *old_plane_state, *new_plane_state; |
6c9c1b38 | 12985 | struct drm_plane *plane; |
6c9c1b38 DV |
12986 | int i; |
12987 | ||
aa5e9b47 | 12988 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) |
faf5bf0a | 12989 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), |
aa5e9b47 | 12990 | intel_fb_obj(new_plane_state->fb), |
faf5bf0a | 12991 | to_intel_plane(plane)->frontbuffer_bit); |
6c9c1b38 DV |
12992 | } |
12993 | ||
94f05024 DV |
12994 | /** |
12995 | * intel_atomic_commit - commit validated state object | |
12996 | * @dev: DRM device | |
12997 | * @state: the top-level driver state object | |
12998 | * @nonblock: nonblocking commit | |
12999 | * | |
13000 | * This function commits a top-level state object that has been validated | |
13001 | * with drm_atomic_helper_check(). | |
13002 | * | |
94f05024 DV |
13003 | * RETURNS |
13004 | * Zero for success or -errno. | |
13005 | */ | |
13006 | static int intel_atomic_commit(struct drm_device *dev, | |
13007 | struct drm_atomic_state *state, | |
13008 | bool nonblock) | |
13009 | { | |
13010 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 13011 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
13012 | int ret = 0; |
13013 | ||
94f05024 DV |
13014 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
13015 | if (ret) | |
13016 | return ret; | |
13017 | ||
c004a90b CW |
13018 | drm_atomic_state_get(state); |
13019 | i915_sw_fence_init(&intel_state->commit_ready, | |
13020 | intel_atomic_commit_ready); | |
94f05024 | 13021 | |
d07f0e59 | 13022 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
13023 | if (ret) { |
13024 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 13025 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
13026 | return ret; |
13027 | } | |
13028 | ||
89520304 VS |
13029 | /* |
13030 | * The intel_legacy_cursor_update() fast path takes care | |
13031 | * of avoiding the vblank waits for simple cursor | |
13032 | * movement and flips. For cursor on/off and size changes, | |
13033 | * we want to perform the vblank waits so that watermark | |
13034 | * updates happen during the correct frames. Gen9+ have | |
13035 | * double buffered watermarks and so shouldn't need this. | |
13036 | * | |
13037 | * Do this after drm_atomic_helper_setup_commit() and | |
13038 | * intel_atomic_prepare_commit() because we still want | |
13039 | * to skip the flip and fb cleanup waits. Although that | |
13040 | * does risk yanking the mapping from under the display | |
13041 | * engine. | |
13042 | * | |
13043 | * FIXME doing watermarks and fb cleanup from a vblank worker | |
13044 | * (assuming we had any) would solve these problems. | |
13045 | */ | |
13046 | if (INTEL_GEN(dev_priv) < 9) | |
13047 | state->legacy_cursor_update = false; | |
13048 | ||
94f05024 DV |
13049 | drm_atomic_helper_swap_state(state, true); |
13050 | dev_priv->wm.distrust_bios_wm = false; | |
3c0fb588 | 13051 | intel_shared_dpll_swap_state(state); |
6c9c1b38 | 13052 | intel_atomic_track_fbs(state); |
94f05024 | 13053 | |
c3b32658 ML |
13054 | if (intel_state->modeset) { |
13055 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13056 | sizeof(intel_state->min_pixclk)); | |
13057 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
bb0f4aab VS |
13058 | dev_priv->cdclk.logical = intel_state->cdclk.logical; |
13059 | dev_priv->cdclk.actual = intel_state->cdclk.actual; | |
c3b32658 ML |
13060 | } |
13061 | ||
0853695c | 13062 | drm_atomic_state_get(state); |
c004a90b CW |
13063 | INIT_WORK(&state->commit_work, |
13064 | nonblock ? intel_atomic_commit_work : NULL); | |
13065 | ||
13066 | i915_sw_fence_commit(&intel_state->commit_ready); | |
13067 | if (!nonblock) { | |
13068 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 13069 | intel_atomic_commit_tail(state); |
c004a90b | 13070 | } |
75714940 | 13071 | |
74c090b1 | 13072 | return 0; |
7f27126e JB |
13073 | } |
13074 | ||
c0c36b94 CW |
13075 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13076 | { | |
83a57153 ACO |
13077 | struct drm_device *dev = crtc->dev; |
13078 | struct drm_atomic_state *state; | |
e694eb02 | 13079 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13080 | int ret; |
83a57153 ACO |
13081 | |
13082 | state = drm_atomic_state_alloc(dev); | |
13083 | if (!state) { | |
78108b7c VS |
13084 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
13085 | crtc->base.id, crtc->name); | |
83a57153 ACO |
13086 | return; |
13087 | } | |
13088 | ||
b260ac3e | 13089 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; |
83a57153 | 13090 | |
e694eb02 ML |
13091 | retry: |
13092 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13093 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13094 | if (!ret) { | |
13095 | if (!crtc_state->active) | |
13096 | goto out; | |
83a57153 | 13097 | |
e694eb02 | 13098 | crtc_state->mode_changed = true; |
74c090b1 | 13099 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13100 | } |
13101 | ||
e694eb02 ML |
13102 | if (ret == -EDEADLK) { |
13103 | drm_atomic_state_clear(state); | |
13104 | drm_modeset_backoff(state->acquire_ctx); | |
13105 | goto retry; | |
4ed9fb37 | 13106 | } |
4be07317 | 13107 | |
e694eb02 | 13108 | out: |
0853695c | 13109 | drm_atomic_state_put(state); |
c0c36b94 CW |
13110 | } |
13111 | ||
f6e5b160 | 13112 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
3fab2f09 | 13113 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 13114 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13115 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 13116 | .destroy = intel_crtc_destroy, |
4c01ded5 | 13117 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
13118 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13119 | .atomic_destroy_state = intel_crtc_destroy_state, | |
8c6b709d | 13120 | .set_crc_source = intel_crtc_set_crc_source, |
f6e5b160 CW |
13121 | }; |
13122 | ||
6beb8c23 MR |
13123 | /** |
13124 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13125 | * @plane: drm plane to prepare for | |
13126 | * @fb: framebuffer to prepare for presentation | |
13127 | * | |
13128 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13129 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13130 | * bits. Some older platforms need special physical address handling for | |
13131 | * cursor planes. | |
13132 | * | |
f935675f ML |
13133 | * Must be called with struct_mutex held. |
13134 | * | |
6beb8c23 MR |
13135 | * Returns 0 on success, negative error code on failure. |
13136 | */ | |
13137 | int | |
13138 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 13139 | struct drm_plane_state *new_state) |
465c120c | 13140 | { |
c004a90b CW |
13141 | struct intel_atomic_state *intel_state = |
13142 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 13143 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 13144 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13145 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13146 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 13147 | int ret; |
465c120c | 13148 | |
57822dc6 CW |
13149 | if (obj) { |
13150 | if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
13151 | INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
13152 | const int align = IS_I830(dev_priv) ? 16 * 1024 : 256; | |
13153 | ||
13154 | ret = i915_gem_object_attach_phys(obj, align); | |
13155 | if (ret) { | |
13156 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13157 | return ret; | |
13158 | } | |
13159 | } else { | |
13160 | struct i915_vma *vma; | |
13161 | ||
13162 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
13163 | if (IS_ERR(vma)) { | |
13164 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13165 | return PTR_ERR(vma); | |
13166 | } | |
13167 | ||
13168 | to_intel_plane_state(new_state)->vma = vma; | |
13169 | } | |
13170 | } | |
13171 | ||
1ee49399 | 13172 | if (!obj && !old_obj) |
465c120c MR |
13173 | return 0; |
13174 | ||
5008e874 ML |
13175 | if (old_obj) { |
13176 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
13177 | drm_atomic_get_existing_crtc_state(new_state->state, |
13178 | plane->state->crtc); | |
5008e874 ML |
13179 | |
13180 | /* Big Hammer, we also need to ensure that any pending | |
13181 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13182 | * current scanout is retired before unpinning the old | |
13183 | * framebuffer. Note that we rely on userspace rendering | |
13184 | * into the buffer attached to the pipe they are waiting | |
13185 | * on. If not, userspace generates a GPU hang with IPEHR | |
13186 | * point to the MI_WAIT_FOR_EVENT. | |
13187 | * | |
13188 | * This should only fail upon a hung GPU, in which case we | |
13189 | * can safely continue. | |
13190 | */ | |
c004a90b CW |
13191 | if (needs_modeset(crtc_state)) { |
13192 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
13193 | old_obj->resv, NULL, | |
13194 | false, 0, | |
13195 | GFP_KERNEL); | |
13196 | if (ret < 0) | |
13197 | return ret; | |
f4457ae7 | 13198 | } |
5008e874 ML |
13199 | } |
13200 | ||
c004a90b CW |
13201 | if (new_state->fence) { /* explicit fencing */ |
13202 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
13203 | new_state->fence, | |
13204 | I915_FENCE_TIMEOUT, | |
13205 | GFP_KERNEL); | |
13206 | if (ret < 0) | |
13207 | return ret; | |
13208 | } | |
13209 | ||
c37efb99 CW |
13210 | if (!obj) |
13211 | return 0; | |
13212 | ||
c004a90b CW |
13213 | if (!new_state->fence) { /* implicit fencing */ |
13214 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
13215 | obj->resv, NULL, | |
13216 | false, I915_FENCE_TIMEOUT, | |
13217 | GFP_KERNEL); | |
13218 | if (ret < 0) | |
13219 | return ret; | |
6b5e90f5 CW |
13220 | |
13221 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
c004a90b | 13222 | } |
5a21b665 | 13223 | |
d07f0e59 | 13224 | return 0; |
6beb8c23 MR |
13225 | } |
13226 | ||
38f3ce3a MR |
13227 | /** |
13228 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13229 | * @plane: drm plane to clean up for | |
13230 | * @fb: old framebuffer that was on plane | |
13231 | * | |
13232 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13233 | * |
13234 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13235 | */ |
13236 | void | |
13237 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 13238 | struct drm_plane_state *old_state) |
38f3ce3a | 13239 | { |
be1e3415 | 13240 | struct i915_vma *vma; |
38f3ce3a | 13241 | |
be1e3415 CW |
13242 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
13243 | vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); | |
13244 | if (vma) | |
13245 | intel_unpin_fb_vma(vma); | |
465c120c MR |
13246 | } |
13247 | ||
6156a456 CK |
13248 | int |
13249 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13250 | { | |
5b7280f0 | 13251 | struct drm_i915_private *dev_priv; |
6156a456 | 13252 | int max_scale; |
5b7280f0 | 13253 | int crtc_clock, max_dotclk; |
6156a456 | 13254 | |
bf8a0af0 | 13255 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13256 | return DRM_PLANE_HELPER_NO_SCALING; |
13257 | ||
5b7280f0 ACO |
13258 | dev_priv = to_i915(intel_crtc->base.dev); |
13259 | ||
6156a456 | 13260 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
5b7280f0 ACO |
13261 | max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; |
13262 | ||
13263 | if (IS_GEMINILAKE(dev_priv)) | |
13264 | max_dotclk *= 2; | |
6156a456 | 13265 | |
5b7280f0 | 13266 | if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) |
6156a456 CK |
13267 | return DRM_PLANE_HELPER_NO_SCALING; |
13268 | ||
13269 | /* | |
13270 | * skl max scale is lower of: | |
13271 | * close to 3 but not 3, -1 is for that purpose | |
13272 | * or | |
13273 | * cdclk/crtc_clock | |
13274 | */ | |
5b7280f0 ACO |
13275 | max_scale = min((1 << 16) * 3 - 1, |
13276 | (1 << 8) * ((max_dotclk << 8) / crtc_clock)); | |
6156a456 CK |
13277 | |
13278 | return max_scale; | |
13279 | } | |
13280 | ||
465c120c | 13281 | static int |
3c692a41 | 13282 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13283 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13284 | struct intel_plane_state *state) |
13285 | { | |
b63a16f6 | 13286 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 13287 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 13288 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13289 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13290 | bool can_position = false; | |
b63a16f6 | 13291 | int ret; |
465c120c | 13292 | |
b63a16f6 | 13293 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
13294 | /* use scaler when colorkey is not required */ |
13295 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13296 | min_scale = 1; | |
13297 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13298 | } | |
d8106366 | 13299 | can_position = true; |
6156a456 | 13300 | } |
d8106366 | 13301 | |
cc926387 DV |
13302 | ret = drm_plane_helper_check_state(&state->base, |
13303 | &state->clip, | |
13304 | min_scale, max_scale, | |
13305 | can_position, true); | |
b63a16f6 VS |
13306 | if (ret) |
13307 | return ret; | |
13308 | ||
cc926387 | 13309 | if (!state->base.fb) |
b63a16f6 VS |
13310 | return 0; |
13311 | ||
13312 | if (INTEL_GEN(dev_priv) >= 9) { | |
13313 | ret = skl_check_plane_surface(state); | |
13314 | if (ret) | |
13315 | return ret; | |
a0864d59 VS |
13316 | |
13317 | state->ctl = skl_plane_ctl(crtc_state, state); | |
13318 | } else { | |
5b7fcc44 VS |
13319 | ret = i9xx_check_plane_surface(state); |
13320 | if (ret) | |
13321 | return ret; | |
13322 | ||
a0864d59 | 13323 | state->ctl = i9xx_plane_ctl(crtc_state, state); |
b63a16f6 VS |
13324 | } |
13325 | ||
13326 | return 0; | |
14af293f GP |
13327 | } |
13328 | ||
5a21b665 DV |
13329 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13330 | struct drm_crtc_state *old_crtc_state) | |
13331 | { | |
13332 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 13333 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 13334 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
13335 | struct intel_crtc_state *intel_cstate = |
13336 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 13337 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 13338 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
13339 | struct intel_atomic_state *old_intel_state = |
13340 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
13341 | bool modeset = needs_modeset(crtc->state); |
13342 | ||
567f0792 ML |
13343 | if (!modeset && |
13344 | (intel_cstate->base.color_mgmt_changed || | |
13345 | intel_cstate->update_pipe)) { | |
13346 | intel_color_set_csc(crtc->state); | |
13347 | intel_color_load_luts(crtc->state); | |
13348 | } | |
13349 | ||
5a21b665 DV |
13350 | /* Perform vblank evasion around commit operation */ |
13351 | intel_pipe_update_start(intel_crtc); | |
13352 | ||
13353 | if (modeset) | |
e62929b3 | 13354 | goto out; |
5a21b665 | 13355 | |
ccf010fb ML |
13356 | if (intel_cstate->update_pipe) |
13357 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
13358 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 13359 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 13360 | |
e62929b3 | 13361 | out: |
ccf010fb ML |
13362 | if (dev_priv->display.atomic_update_watermarks) |
13363 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
13364 | intel_cstate); | |
5a21b665 DV |
13365 | } |
13366 | ||
13367 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
13368 | struct drm_crtc_state *old_crtc_state) | |
13369 | { | |
13370 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13371 | ||
13372 | intel_pipe_update_end(intel_crtc, NULL); | |
13373 | } | |
13374 | ||
cf4c7c12 | 13375 | /** |
4a3b8769 MR |
13376 | * intel_plane_destroy - destroy a plane |
13377 | * @plane: plane to destroy | |
cf4c7c12 | 13378 | * |
4a3b8769 MR |
13379 | * Common destruction function for all types of planes (primary, cursor, |
13380 | * sprite). | |
cf4c7c12 | 13381 | */ |
4a3b8769 | 13382 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 13383 | { |
465c120c | 13384 | drm_plane_cleanup(plane); |
69ae561f | 13385 | kfree(to_intel_plane(plane)); |
465c120c MR |
13386 | } |
13387 | ||
65a3fea0 | 13388 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13389 | .update_plane = drm_atomic_helper_update_plane, |
13390 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13391 | .destroy = intel_plane_destroy, |
c196e1d6 | 13392 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13393 | .atomic_get_property = intel_plane_atomic_get_property, |
13394 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13395 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13396 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
13397 | }; |
13398 | ||
f79f2692 ML |
13399 | static int |
13400 | intel_legacy_cursor_update(struct drm_plane *plane, | |
13401 | struct drm_crtc *crtc, | |
13402 | struct drm_framebuffer *fb, | |
13403 | int crtc_x, int crtc_y, | |
13404 | unsigned int crtc_w, unsigned int crtc_h, | |
13405 | uint32_t src_x, uint32_t src_y, | |
34a2ab5e DV |
13406 | uint32_t src_w, uint32_t src_h, |
13407 | struct drm_modeset_acquire_ctx *ctx) | |
f79f2692 ML |
13408 | { |
13409 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
13410 | int ret; | |
13411 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
13412 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13413 | struct drm_framebuffer *old_fb; | |
13414 | struct drm_crtc_state *crtc_state = crtc->state; | |
be1e3415 | 13415 | struct i915_vma *old_vma; |
f79f2692 ML |
13416 | |
13417 | /* | |
13418 | * When crtc is inactive or there is a modeset pending, | |
13419 | * wait for it to complete in the slowpath | |
13420 | */ | |
13421 | if (!crtc_state->active || needs_modeset(crtc_state) || | |
13422 | to_intel_crtc_state(crtc_state)->update_pipe) | |
13423 | goto slow; | |
13424 | ||
13425 | old_plane_state = plane->state; | |
13426 | ||
13427 | /* | |
13428 | * If any parameters change that may affect watermarks, | |
13429 | * take the slowpath. Only changing fb or position should be | |
13430 | * in the fastpath. | |
13431 | */ | |
13432 | if (old_plane_state->crtc != crtc || | |
13433 | old_plane_state->src_w != src_w || | |
13434 | old_plane_state->src_h != src_h || | |
13435 | old_plane_state->crtc_w != crtc_w || | |
13436 | old_plane_state->crtc_h != crtc_h || | |
a5509abd | 13437 | !old_plane_state->fb != !fb) |
f79f2692 ML |
13438 | goto slow; |
13439 | ||
13440 | new_plane_state = intel_plane_duplicate_state(plane); | |
13441 | if (!new_plane_state) | |
13442 | return -ENOMEM; | |
13443 | ||
13444 | drm_atomic_set_fb_for_plane(new_plane_state, fb); | |
13445 | ||
13446 | new_plane_state->src_x = src_x; | |
13447 | new_plane_state->src_y = src_y; | |
13448 | new_plane_state->src_w = src_w; | |
13449 | new_plane_state->src_h = src_h; | |
13450 | new_plane_state->crtc_x = crtc_x; | |
13451 | new_plane_state->crtc_y = crtc_y; | |
13452 | new_plane_state->crtc_w = crtc_w; | |
13453 | new_plane_state->crtc_h = crtc_h; | |
13454 | ||
13455 | ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), | |
13456 | to_intel_plane_state(new_plane_state)); | |
13457 | if (ret) | |
13458 | goto out_free; | |
13459 | ||
f79f2692 ML |
13460 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
13461 | if (ret) | |
13462 | goto out_free; | |
13463 | ||
13464 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
13465 | int align = IS_I830(dev_priv) ? 16 * 1024 : 256; | |
13466 | ||
13467 | ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align); | |
13468 | if (ret) { | |
13469 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13470 | goto out_unlock; | |
13471 | } | |
13472 | } else { | |
13473 | struct i915_vma *vma; | |
13474 | ||
13475 | vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); | |
13476 | if (IS_ERR(vma)) { | |
13477 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13478 | ||
13479 | ret = PTR_ERR(vma); | |
13480 | goto out_unlock; | |
13481 | } | |
be1e3415 CW |
13482 | |
13483 | to_intel_plane_state(new_plane_state)->vma = vma; | |
f79f2692 ML |
13484 | } |
13485 | ||
13486 | old_fb = old_plane_state->fb; | |
be1e3415 | 13487 | old_vma = to_intel_plane_state(old_plane_state)->vma; |
f79f2692 ML |
13488 | |
13489 | i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), | |
13490 | intel_plane->frontbuffer_bit); | |
13491 | ||
13492 | /* Swap plane state */ | |
13493 | new_plane_state->fence = old_plane_state->fence; | |
13494 | *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state); | |
13495 | new_plane_state->fence = NULL; | |
13496 | new_plane_state->fb = old_fb; | |
be1e3415 | 13497 | to_intel_plane_state(new_plane_state)->vma = old_vma; |
f79f2692 | 13498 | |
72259536 VS |
13499 | if (plane->state->visible) { |
13500 | trace_intel_update_plane(plane, to_intel_crtc(crtc)); | |
a5509abd VS |
13501 | intel_plane->update_plane(plane, |
13502 | to_intel_crtc_state(crtc->state), | |
13503 | to_intel_plane_state(plane->state)); | |
72259536 VS |
13504 | } else { |
13505 | trace_intel_disable_plane(plane, to_intel_crtc(crtc)); | |
a5509abd | 13506 | intel_plane->disable_plane(plane, crtc); |
72259536 | 13507 | } |
f79f2692 ML |
13508 | |
13509 | intel_cleanup_plane_fb(plane, new_plane_state); | |
13510 | ||
13511 | out_unlock: | |
13512 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
13513 | out_free: | |
13514 | intel_plane_destroy_state(plane, new_plane_state); | |
13515 | return ret; | |
13516 | ||
f79f2692 ML |
13517 | slow: |
13518 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
13519 | crtc_x, crtc_y, crtc_w, crtc_h, | |
34a2ab5e | 13520 | src_x, src_y, src_w, src_h, ctx); |
f79f2692 ML |
13521 | } |
13522 | ||
13523 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
13524 | .update_plane = intel_legacy_cursor_update, | |
13525 | .disable_plane = drm_atomic_helper_disable_plane, | |
13526 | .destroy = intel_plane_destroy, | |
13527 | .set_property = drm_atomic_helper_plane_set_property, | |
13528 | .atomic_get_property = intel_plane_atomic_get_property, | |
13529 | .atomic_set_property = intel_plane_atomic_set_property, | |
13530 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
13531 | .atomic_destroy_state = intel_plane_destroy_state, | |
13532 | }; | |
13533 | ||
b079bd17 | 13534 | static struct intel_plane * |
580503c7 | 13535 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 13536 | { |
fca0ce2a VS |
13537 | struct intel_plane *primary = NULL; |
13538 | struct intel_plane_state *state = NULL; | |
465c120c | 13539 | const uint32_t *intel_primary_formats; |
93ca7e00 | 13540 | unsigned int supported_rotations; |
45e3743a | 13541 | unsigned int num_formats; |
fca0ce2a | 13542 | int ret; |
465c120c MR |
13543 | |
13544 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
13545 | if (!primary) { |
13546 | ret = -ENOMEM; | |
fca0ce2a | 13547 | goto fail; |
b079bd17 | 13548 | } |
465c120c | 13549 | |
8e7d688b | 13550 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
13551 | if (!state) { |
13552 | ret = -ENOMEM; | |
fca0ce2a | 13553 | goto fail; |
b079bd17 VS |
13554 | } |
13555 | ||
8e7d688b | 13556 | primary->base.state = &state->base; |
ea2c67bb | 13557 | |
465c120c MR |
13558 | primary->can_scale = false; |
13559 | primary->max_downscale = 1; | |
580503c7 | 13560 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 13561 | primary->can_scale = true; |
af99ceda | 13562 | state->scaler_id = -1; |
6156a456 | 13563 | } |
465c120c | 13564 | primary->pipe = pipe; |
e3c566df VS |
13565 | /* |
13566 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
13567 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
13568 | */ | |
13569 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
13570 | primary->plane = (enum plane) !pipe; | |
13571 | else | |
13572 | primary->plane = (enum plane) pipe; | |
b14e5848 | 13573 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 13574 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13575 | primary->check_plane = intel_check_primary_plane; |
465c120c | 13576 | |
580503c7 | 13577 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
13578 | intel_primary_formats = skl_primary_formats; |
13579 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
13580 | |
13581 | primary->update_plane = skylake_update_primary_plane; | |
13582 | primary->disable_plane = skylake_disable_primary_plane; | |
580503c7 | 13583 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
13584 | intel_primary_formats = i965_primary_formats; |
13585 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
13586 | |
13587 | primary->update_plane = i9xx_update_primary_plane; | |
13588 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13589 | } else { |
13590 | intel_primary_formats = i8xx_primary_formats; | |
13591 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
13592 | |
13593 | primary->update_plane = i9xx_update_primary_plane; | |
13594 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13595 | } |
13596 | ||
580503c7 VS |
13597 | if (INTEL_GEN(dev_priv) >= 9) |
13598 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
13599 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13600 | intel_primary_formats, num_formats, |
13601 | DRM_PLANE_TYPE_PRIMARY, | |
13602 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 13603 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
13604 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13605 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13606 | intel_primary_formats, num_formats, |
13607 | DRM_PLANE_TYPE_PRIMARY, | |
13608 | "primary %c", pipe_name(pipe)); | |
13609 | else | |
580503c7 VS |
13610 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13611 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13612 | intel_primary_formats, num_formats, |
13613 | DRM_PLANE_TYPE_PRIMARY, | |
13614 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
13615 | if (ret) |
13616 | goto fail; | |
48404c1e | 13617 | |
5481e27f | 13618 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 VS |
13619 | supported_rotations = |
13620 | DRM_ROTATE_0 | DRM_ROTATE_90 | | |
13621 | DRM_ROTATE_180 | DRM_ROTATE_270; | |
4ea7be2b VS |
13622 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
13623 | supported_rotations = | |
13624 | DRM_ROTATE_0 | DRM_ROTATE_180 | | |
13625 | DRM_REFLECT_X; | |
5481e27f | 13626 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 VS |
13627 | supported_rotations = |
13628 | DRM_ROTATE_0 | DRM_ROTATE_180; | |
13629 | } else { | |
13630 | supported_rotations = DRM_ROTATE_0; | |
13631 | } | |
13632 | ||
5481e27f | 13633 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
13634 | drm_plane_create_rotation_property(&primary->base, |
13635 | DRM_ROTATE_0, | |
13636 | supported_rotations); | |
48404c1e | 13637 | |
ea2c67bb MR |
13638 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13639 | ||
b079bd17 | 13640 | return primary; |
fca0ce2a VS |
13641 | |
13642 | fail: | |
13643 | kfree(state); | |
13644 | kfree(primary); | |
13645 | ||
b079bd17 | 13646 | return ERR_PTR(ret); |
465c120c MR |
13647 | } |
13648 | ||
3d7d6510 | 13649 | static int |
852e787c | 13650 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13651 | struct intel_crtc_state *crtc_state, |
852e787c | 13652 | struct intel_plane_state *state) |
3d7d6510 | 13653 | { |
a0864d59 | 13654 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 13655 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13656 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 13657 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
13658 | unsigned stride; |
13659 | int ret; | |
3d7d6510 | 13660 | |
f8856a44 VS |
13661 | ret = drm_plane_helper_check_state(&state->base, |
13662 | &state->clip, | |
13663 | DRM_PLANE_HELPER_NO_SCALING, | |
13664 | DRM_PLANE_HELPER_NO_SCALING, | |
13665 | true, true); | |
757f9a3e GP |
13666 | if (ret) |
13667 | return ret; | |
13668 | ||
757f9a3e GP |
13669 | /* if we want to turn off the cursor ignore width and height */ |
13670 | if (!obj) | |
da20eabd | 13671 | return 0; |
757f9a3e | 13672 | |
757f9a3e | 13673 | /* Check for which cursor types we support */ |
a0864d59 | 13674 | if (!cursor_size_ok(dev_priv, state->base.crtc_w, |
50a0bc90 | 13675 | state->base.crtc_h)) { |
ea2c67bb MR |
13676 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
13677 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13678 | return -EINVAL; |
13679 | } | |
13680 | ||
ea2c67bb MR |
13681 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13682 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13683 | DRM_DEBUG_KMS("buffer is too small\n"); |
13684 | return -ENOMEM; | |
13685 | } | |
13686 | ||
2f075565 | 13687 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
757f9a3e | 13688 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 13689 | return -EINVAL; |
32b7eeec MR |
13690 | } |
13691 | ||
b29ec92c VS |
13692 | /* |
13693 | * There's something wrong with the cursor on CHV pipe C. | |
13694 | * If it straddles the left edge of the screen then | |
13695 | * moving it away from the edge or disabling it often | |
13696 | * results in a pipe underrun, and often that can lead to | |
13697 | * dead pipe (constant underrun reported, and it scans | |
13698 | * out just a solid color). To recover from that, the | |
13699 | * display power well must be turned off and on again. | |
13700 | * Refuse the put the cursor into that compromised position. | |
13701 | */ | |
a0864d59 | 13702 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && |
936e71e3 | 13703 | state->base.visible && state->base.crtc_x < 0) { |
b29ec92c VS |
13704 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
13705 | return -EINVAL; | |
13706 | } | |
13707 | ||
a0864d59 VS |
13708 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
13709 | state->ctl = i845_cursor_ctl(crtc_state, state); | |
13710 | else | |
13711 | state->ctl = i9xx_cursor_ctl(crtc_state, state); | |
13712 | ||
da20eabd | 13713 | return 0; |
852e787c | 13714 | } |
3d7d6510 | 13715 | |
a8ad0d8e ML |
13716 | static void |
13717 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 13718 | struct drm_crtc *crtc) |
a8ad0d8e | 13719 | { |
f2858021 ML |
13720 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13721 | ||
13722 | intel_crtc->cursor_addr = 0; | |
a0864d59 | 13723 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
13724 | } |
13725 | ||
f4a2cf29 | 13726 | static void |
55a08b3f ML |
13727 | intel_update_cursor_plane(struct drm_plane *plane, |
13728 | const struct intel_crtc_state *crtc_state, | |
13729 | const struct intel_plane_state *state) | |
852e787c | 13730 | { |
55a08b3f ML |
13731 | struct drm_crtc *crtc = crtc_state->base.crtc; |
13732 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b7f05d4a | 13733 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 13734 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13735 | uint32_t addr; |
852e787c | 13736 | |
f4a2cf29 | 13737 | if (!obj) |
a912f12f | 13738 | addr = 0; |
b7f05d4a | 13739 | else if (!INTEL_INFO(dev_priv)->cursor_needs_physical) |
be1e3415 | 13740 | addr = intel_plane_ggtt_offset(state); |
f4a2cf29 | 13741 | else |
a912f12f | 13742 | addr = obj->phys_handle->busaddr; |
852e787c | 13743 | |
a912f12f | 13744 | intel_crtc->cursor_addr = addr; |
a0864d59 | 13745 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
13746 | } |
13747 | ||
b079bd17 | 13748 | static struct intel_plane * |
580503c7 | 13749 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
3d7d6510 | 13750 | { |
fca0ce2a VS |
13751 | struct intel_plane *cursor = NULL; |
13752 | struct intel_plane_state *state = NULL; | |
13753 | int ret; | |
3d7d6510 MR |
13754 | |
13755 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
13756 | if (!cursor) { |
13757 | ret = -ENOMEM; | |
fca0ce2a | 13758 | goto fail; |
b079bd17 | 13759 | } |
3d7d6510 | 13760 | |
8e7d688b | 13761 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
13762 | if (!state) { |
13763 | ret = -ENOMEM; | |
fca0ce2a | 13764 | goto fail; |
b079bd17 VS |
13765 | } |
13766 | ||
8e7d688b | 13767 | cursor->base.state = &state->base; |
ea2c67bb | 13768 | |
3d7d6510 MR |
13769 | cursor->can_scale = false; |
13770 | cursor->max_downscale = 1; | |
13771 | cursor->pipe = pipe; | |
13772 | cursor->plane = pipe; | |
b14e5848 | 13773 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 13774 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 13775 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 13776 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 13777 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 13778 | |
580503c7 | 13779 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
f79f2692 | 13780 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
13781 | intel_cursor_formats, |
13782 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
13783 | DRM_PLANE_TYPE_CURSOR, |
13784 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
13785 | if (ret) |
13786 | goto fail; | |
4398ad45 | 13787 | |
5481e27f | 13788 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
13789 | drm_plane_create_rotation_property(&cursor->base, |
13790 | DRM_ROTATE_0, | |
13791 | DRM_ROTATE_0 | | |
13792 | DRM_ROTATE_180); | |
4398ad45 | 13793 | |
580503c7 | 13794 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
13795 | state->scaler_id = -1; |
13796 | ||
ea2c67bb MR |
13797 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13798 | ||
b079bd17 | 13799 | return cursor; |
fca0ce2a VS |
13800 | |
13801 | fail: | |
13802 | kfree(state); | |
13803 | kfree(cursor); | |
13804 | ||
b079bd17 | 13805 | return ERR_PTR(ret); |
3d7d6510 MR |
13806 | } |
13807 | ||
1c74eeaf NM |
13808 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
13809 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 13810 | { |
65edccce VS |
13811 | struct intel_crtc_scaler_state *scaler_state = |
13812 | &crtc_state->scaler_state; | |
1c74eeaf | 13813 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
549e2bfb | 13814 | int i; |
549e2bfb | 13815 | |
1c74eeaf NM |
13816 | crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; |
13817 | if (!crtc->num_scalers) | |
13818 | return; | |
13819 | ||
65edccce VS |
13820 | for (i = 0; i < crtc->num_scalers; i++) { |
13821 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
13822 | ||
13823 | scaler->in_use = 0; | |
13824 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
13825 | } |
13826 | ||
13827 | scaler_state->scaler_id = -1; | |
13828 | } | |
13829 | ||
5ab0d85b | 13830 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
13831 | { |
13832 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 13833 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
13834 | struct intel_plane *primary = NULL; |
13835 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 13836 | int sprite, ret; |
79e53945 | 13837 | |
955382f3 | 13838 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
13839 | if (!intel_crtc) |
13840 | return -ENOMEM; | |
79e53945 | 13841 | |
f5de6e07 | 13842 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
13843 | if (!crtc_state) { |
13844 | ret = -ENOMEM; | |
f5de6e07 | 13845 | goto fail; |
b079bd17 | 13846 | } |
550acefd ACO |
13847 | intel_crtc->config = crtc_state; |
13848 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13849 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13850 | |
580503c7 | 13851 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
13852 | if (IS_ERR(primary)) { |
13853 | ret = PTR_ERR(primary); | |
3d7d6510 | 13854 | goto fail; |
b079bd17 | 13855 | } |
d97d7b48 | 13856 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 13857 | |
a81d6fa0 | 13858 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
13859 | struct intel_plane *plane; |
13860 | ||
580503c7 | 13861 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 13862 | if (IS_ERR(plane)) { |
b079bd17 VS |
13863 | ret = PTR_ERR(plane); |
13864 | goto fail; | |
13865 | } | |
d97d7b48 | 13866 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
13867 | } |
13868 | ||
580503c7 | 13869 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 13870 | if (IS_ERR(cursor)) { |
b079bd17 | 13871 | ret = PTR_ERR(cursor); |
3d7d6510 | 13872 | goto fail; |
b079bd17 | 13873 | } |
d97d7b48 | 13874 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 13875 | |
5ab0d85b | 13876 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
13877 | &primary->base, &cursor->base, |
13878 | &intel_crtc_funcs, | |
4d5d72b7 | 13879 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
13880 | if (ret) |
13881 | goto fail; | |
79e53945 | 13882 | |
80824003 | 13883 | intel_crtc->pipe = pipe; |
e3c566df | 13884 | intel_crtc->plane = primary->plane; |
80824003 | 13885 | |
4b0e333e CW |
13886 | intel_crtc->cursor_base = ~0; |
13887 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13888 | intel_crtc->cursor_size = ~0; |
8d7849db | 13889 | |
1c74eeaf NM |
13890 | /* initialize shared scalers */ |
13891 | intel_crtc_init_scalers(intel_crtc, crtc_state); | |
13892 | ||
22fd0fab JB |
13893 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13894 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
13895 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
13896 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 13897 | |
79e53945 | 13898 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13899 | |
8563b1e8 LL |
13900 | intel_color_init(&intel_crtc->base); |
13901 | ||
87b6b101 | 13902 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
13903 | |
13904 | return 0; | |
3d7d6510 MR |
13905 | |
13906 | fail: | |
b079bd17 VS |
13907 | /* |
13908 | * drm_mode_config_cleanup() will free up any | |
13909 | * crtcs/planes already initialized. | |
13910 | */ | |
f5de6e07 | 13911 | kfree(crtc_state); |
3d7d6510 | 13912 | kfree(intel_crtc); |
b079bd17 VS |
13913 | |
13914 | return ret; | |
79e53945 JB |
13915 | } |
13916 | ||
752aa88a JB |
13917 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13918 | { | |
6e9f798d | 13919 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13920 | |
51fd371b | 13921 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13922 | |
51ec53da | 13923 | if (!connector->base.state->crtc) |
752aa88a JB |
13924 | return INVALID_PIPE; |
13925 | ||
51ec53da | 13926 | return to_intel_crtc(connector->base.state->crtc)->pipe; |
752aa88a JB |
13927 | } |
13928 | ||
08d7b3d1 | 13929 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13930 | struct drm_file *file) |
08d7b3d1 | 13931 | { |
08d7b3d1 | 13932 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13933 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13934 | struct intel_crtc *crtc; |
08d7b3d1 | 13935 | |
7707e653 | 13936 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 13937 | if (!drmmode_crtc) |
3f2c2057 | 13938 | return -ENOENT; |
08d7b3d1 | 13939 | |
7707e653 | 13940 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13941 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13942 | |
c05422d5 | 13943 | return 0; |
08d7b3d1 CW |
13944 | } |
13945 | ||
66a9278e | 13946 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13947 | { |
66a9278e DV |
13948 | struct drm_device *dev = encoder->base.dev; |
13949 | struct intel_encoder *source_encoder; | |
79e53945 | 13950 | int index_mask = 0; |
79e53945 JB |
13951 | int entry = 0; |
13952 | ||
b2784e15 | 13953 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13954 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13955 | index_mask |= (1 << entry); |
13956 | ||
79e53945 JB |
13957 | entry++; |
13958 | } | |
4ef69c7a | 13959 | |
79e53945 JB |
13960 | return index_mask; |
13961 | } | |
13962 | ||
646d5772 | 13963 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 13964 | { |
646d5772 | 13965 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
13966 | return false; |
13967 | ||
13968 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13969 | return false; | |
13970 | ||
5db94019 | 13971 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13972 | return false; |
13973 | ||
13974 | return true; | |
13975 | } | |
13976 | ||
6315b5d3 | 13977 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 13978 | { |
6315b5d3 | 13979 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
13980 | return false; |
13981 | ||
50a0bc90 | 13982 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
13983 | return false; |
13984 | ||
920a14b2 | 13985 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
13986 | return false; |
13987 | ||
4f8036a2 TU |
13988 | if (HAS_PCH_LPT_H(dev_priv) && |
13989 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
13990 | return false; |
13991 | ||
70ac54d0 | 13992 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 13993 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
13994 | return false; |
13995 | ||
e4abb733 | 13996 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
13997 | return false; |
13998 | ||
13999 | return true; | |
14000 | } | |
14001 | ||
8090ba8c ID |
14002 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
14003 | { | |
14004 | int pps_num; | |
14005 | int pps_idx; | |
14006 | ||
14007 | if (HAS_DDI(dev_priv)) | |
14008 | return; | |
14009 | /* | |
14010 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
14011 | * everywhere where registers can be write protected. | |
14012 | */ | |
14013 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14014 | pps_num = 2; | |
14015 | else | |
14016 | pps_num = 1; | |
14017 | ||
14018 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
14019 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
14020 | ||
14021 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
14022 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
14023 | } | |
14024 | } | |
14025 | ||
44cb734c ID |
14026 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
14027 | { | |
cc3f90f0 | 14028 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
14029 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
14030 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14031 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
14032 | else | |
14033 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
14034 | |
14035 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
14036 | } |
14037 | ||
c39055b0 | 14038 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 14039 | { |
4ef69c7a | 14040 | struct intel_encoder *encoder; |
cb0953d7 | 14041 | bool dpd_is_edp = false; |
79e53945 | 14042 | |
44cb734c ID |
14043 | intel_pps_init(dev_priv); |
14044 | ||
97a824e1 ID |
14045 | /* |
14046 | * intel_edp_init_connector() depends on this completing first, to | |
14047 | * prevent the registeration of both eDP and LVDS and the incorrect | |
14048 | * sharing of the PPS. | |
14049 | */ | |
c39055b0 | 14050 | intel_lvds_init(dev_priv); |
79e53945 | 14051 | |
6315b5d3 | 14052 | if (intel_crt_present(dev_priv)) |
c39055b0 | 14053 | intel_crt_init(dev_priv); |
cb0953d7 | 14054 | |
cc3f90f0 | 14055 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
14056 | /* |
14057 | * FIXME: Broxton doesn't support port detection via the | |
14058 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14059 | * detect the ports. | |
14060 | */ | |
c39055b0 ACO |
14061 | intel_ddi_init(dev_priv, PORT_A); |
14062 | intel_ddi_init(dev_priv, PORT_B); | |
14063 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 14064 | |
c39055b0 | 14065 | intel_dsi_init(dev_priv); |
4f8036a2 | 14066 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
14067 | int found; |
14068 | ||
de31facd JB |
14069 | /* |
14070 | * Haswell uses DDI functions to detect digital outputs. | |
14071 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14072 | * it's there. | |
14073 | */ | |
77179400 | 14074 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14075 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 14076 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 14077 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
14078 | |
14079 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14080 | * register */ | |
14081 | found = I915_READ(SFUSE_STRAP); | |
14082 | ||
14083 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 14084 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 14085 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 14086 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 14087 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 14088 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
14089 | /* |
14090 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14091 | */ | |
b976dc53 | 14092 | if (IS_GEN9_BC(dev_priv) && |
2800e4c2 RV |
14093 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14094 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14095 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 14096 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 14097 | |
6e266956 | 14098 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 14099 | int found; |
dd11bc10 | 14100 | dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); |
270b3042 | 14101 | |
646d5772 | 14102 | if (has_edp_a(dev_priv)) |
c39055b0 | 14103 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 14104 | |
dc0fa718 | 14105 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14106 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 14107 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 14108 | if (!found) |
c39055b0 | 14109 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 14110 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 14111 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14112 | } |
14113 | ||
dc0fa718 | 14114 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 14115 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 14116 | |
dc0fa718 | 14117 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 14118 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 14119 | |
5eb08b69 | 14120 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 14121 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 14122 | |
270b3042 | 14123 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 14124 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 14125 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 14126 | bool has_edp, has_port; |
457c52d8 | 14127 | |
e17ac6db VS |
14128 | /* |
14129 | * The DP_DETECTED bit is the latched state of the DDC | |
14130 | * SDA pin at boot. However since eDP doesn't require DDC | |
14131 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14132 | * eDP ports may have been muxed to an alternate function. | |
14133 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14134 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14135 | * detect eDP ports. | |
22f35042 VS |
14136 | * |
14137 | * Sadly the straps seem to be missing sometimes even for HDMI | |
14138 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
14139 | * and VBT for the presence of the port. Additionally we can't | |
14140 | * trust the port type the VBT declares as we've seen at least | |
14141 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 14142 | */ |
dd11bc10 | 14143 | has_edp = intel_dp_is_edp(dev_priv, PORT_B); |
22f35042 VS |
14144 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
14145 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 14146 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 14147 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 14148 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 14149 | |
dd11bc10 | 14150 | has_edp = intel_dp_is_edp(dev_priv, PORT_C); |
22f35042 VS |
14151 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
14152 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 14153 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 14154 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 14155 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 14156 | |
920a14b2 | 14157 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
14158 | /* |
14159 | * eDP not supported on port D, | |
14160 | * so no need to worry about it | |
14161 | */ | |
14162 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
14163 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 14164 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 14165 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 14166 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
14167 | } |
14168 | ||
c39055b0 | 14169 | intel_dsi_init(dev_priv); |
5db94019 | 14170 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 14171 | bool found = false; |
7d57382e | 14172 | |
e2debe91 | 14173 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14174 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 14175 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 14176 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 14177 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 14178 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14179 | } |
27185ae1 | 14180 | |
9beb5fea | 14181 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 14182 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 14183 | } |
13520b05 KH |
14184 | |
14185 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14186 | |
e2debe91 | 14187 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14188 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 14189 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14190 | } |
27185ae1 | 14191 | |
e2debe91 | 14192 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14193 | |
9beb5fea | 14194 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 14195 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 14196 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14197 | } |
9beb5fea | 14198 | if (IS_G4X(dev_priv)) |
c39055b0 | 14199 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 14200 | } |
27185ae1 | 14201 | |
9beb5fea | 14202 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 14203 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 14204 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 14205 | intel_dvo_init(dev_priv); |
79e53945 | 14206 | |
56b857a5 | 14207 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 14208 | intel_tv_init(dev_priv); |
79e53945 | 14209 | |
c39055b0 | 14210 | intel_psr_init(dev_priv); |
7c8f8a70 | 14211 | |
c39055b0 | 14212 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
14213 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14214 | encoder->base.possible_clones = | |
66a9278e | 14215 | intel_encoder_clones(encoder); |
79e53945 | 14216 | } |
47356eb6 | 14217 | |
c39055b0 | 14218 | intel_init_pch_refclk(dev_priv); |
270b3042 | 14219 | |
c39055b0 | 14220 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
14221 | } |
14222 | ||
14223 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14224 | { | |
14225 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 14226 | |
ef2d633e | 14227 | drm_framebuffer_cleanup(fb); |
70001cd2 | 14228 | |
dd689287 CW |
14229 | i915_gem_object_lock(intel_fb->obj); |
14230 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
14231 | i915_gem_object_unlock(intel_fb->obj); | |
14232 | ||
f8c417cd | 14233 | i915_gem_object_put(intel_fb->obj); |
70001cd2 | 14234 | |
79e53945 JB |
14235 | kfree(intel_fb); |
14236 | } | |
14237 | ||
14238 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14239 | struct drm_file *file, |
79e53945 JB |
14240 | unsigned int *handle) |
14241 | { | |
14242 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14243 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14244 | |
cc917ab4 CW |
14245 | if (obj->userptr.mm) { |
14246 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14247 | return -EINVAL; | |
14248 | } | |
14249 | ||
05394f39 | 14250 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14251 | } |
14252 | ||
86c98588 RV |
14253 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14254 | struct drm_file *file, | |
14255 | unsigned flags, unsigned color, | |
14256 | struct drm_clip_rect *clips, | |
14257 | unsigned num_clips) | |
14258 | { | |
5a97bcc6 | 14259 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 14260 | |
5a97bcc6 | 14261 | i915_gem_object_flush_if_display(obj); |
d59b21ec | 14262 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
86c98588 RV |
14263 | |
14264 | return 0; | |
14265 | } | |
14266 | ||
79e53945 JB |
14267 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14268 | .destroy = intel_user_framebuffer_destroy, | |
14269 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14270 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14271 | }; |
14272 | ||
b321803d | 14273 | static |
920a14b2 TU |
14274 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
14275 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 14276 | { |
24dbf51a | 14277 | u32 gen = INTEL_GEN(dev_priv); |
b321803d DL |
14278 | |
14279 | if (gen >= 9) { | |
ac484963 VS |
14280 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14281 | ||
b321803d DL |
14282 | /* "The stride in bytes must not exceed the of the size of 8K |
14283 | * pixels and 32K bytes." | |
14284 | */ | |
ac484963 | 14285 | return min(8192 * cpp, 32768); |
6401c37d | 14286 | } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) { |
b321803d DL |
14287 | return 32*1024; |
14288 | } else if (gen >= 4) { | |
14289 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14290 | return 16*1024; | |
14291 | else | |
14292 | return 32*1024; | |
14293 | } else if (gen >= 3) { | |
14294 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14295 | return 8*1024; | |
14296 | else | |
14297 | return 16*1024; | |
14298 | } else { | |
14299 | /* XXX DSPC is limited to 4k tiled */ | |
14300 | return 8*1024; | |
14301 | } | |
14302 | } | |
14303 | ||
24dbf51a CW |
14304 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
14305 | struct drm_i915_gem_object *obj, | |
14306 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 14307 | { |
24dbf51a | 14308 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
b3c11ac2 | 14309 | struct drm_format_name_buf format_name; |
dd689287 CW |
14310 | u32 pitch_limit, stride_alignment; |
14311 | unsigned int tiling, stride; | |
24dbf51a | 14312 | int ret = -EINVAL; |
79e53945 | 14313 | |
dd689287 CW |
14314 | i915_gem_object_lock(obj); |
14315 | obj->framebuffer_references++; | |
14316 | tiling = i915_gem_object_get_tiling(obj); | |
14317 | stride = i915_gem_object_get_stride(obj); | |
14318 | i915_gem_object_unlock(obj); | |
dd4916c5 | 14319 | |
2a80eada | 14320 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
14321 | /* |
14322 | * If there's a fence, enforce that | |
14323 | * the fb modifier and tiling mode match. | |
14324 | */ | |
14325 | if (tiling != I915_TILING_NONE && | |
14326 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 14327 | DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n"); |
24dbf51a | 14328 | goto err; |
2a80eada DV |
14329 | } |
14330 | } else { | |
c2ff7370 | 14331 | if (tiling == I915_TILING_X) { |
2a80eada | 14332 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 14333 | } else if (tiling == I915_TILING_Y) { |
144cc143 | 14334 | DRM_DEBUG_KMS("No Y tiling for legacy addfb\n"); |
24dbf51a | 14335 | goto err; |
2a80eada DV |
14336 | } |
14337 | } | |
14338 | ||
9a8f0a12 TU |
14339 | /* Passed in modifier sanity checking. */ |
14340 | switch (mode_cmd->modifier[0]) { | |
14341 | case I915_FORMAT_MOD_Y_TILED: | |
14342 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 14343 | if (INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
14344 | DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", |
14345 | mode_cmd->modifier[0]); | |
24dbf51a | 14346 | goto err; |
9a8f0a12 | 14347 | } |
2f075565 | 14348 | case DRM_FORMAT_MOD_LINEAR: |
9a8f0a12 TU |
14349 | case I915_FORMAT_MOD_X_TILED: |
14350 | break; | |
14351 | default: | |
144cc143 VS |
14352 | DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n", |
14353 | mode_cmd->modifier[0]); | |
24dbf51a | 14354 | goto err; |
c16ed4be | 14355 | } |
57cd6508 | 14356 | |
c2ff7370 VS |
14357 | /* |
14358 | * gen2/3 display engine uses the fence if present, | |
14359 | * so the tiling mode must match the fb modifier exactly. | |
14360 | */ | |
14361 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
14362 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 14363 | DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); |
9aceb5c1 | 14364 | goto err; |
c2ff7370 VS |
14365 | } |
14366 | ||
920a14b2 | 14367 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 14368 | mode_cmd->pixel_format); |
a35cdaa0 | 14369 | if (mode_cmd->pitches[0] > pitch_limit) { |
144cc143 | 14370 | DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n", |
2f075565 | 14371 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? |
144cc143 VS |
14372 | "tiled" : "linear", |
14373 | mode_cmd->pitches[0], pitch_limit); | |
24dbf51a | 14374 | goto err; |
c16ed4be | 14375 | } |
5d7bd705 | 14376 | |
c2ff7370 VS |
14377 | /* |
14378 | * If there's a fence, enforce that | |
14379 | * the fb pitch and fence stride match. | |
14380 | */ | |
144cc143 VS |
14381 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
14382 | DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n", | |
14383 | mode_cmd->pitches[0], stride); | |
24dbf51a | 14384 | goto err; |
c16ed4be | 14385 | } |
5d7bd705 | 14386 | |
57779d06 | 14387 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14388 | switch (mode_cmd->pixel_format) { |
57779d06 | 14389 | case DRM_FORMAT_C8: |
04b3924d VS |
14390 | case DRM_FORMAT_RGB565: |
14391 | case DRM_FORMAT_XRGB8888: | |
14392 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14393 | break; |
14394 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 14395 | if (INTEL_GEN(dev_priv) > 3) { |
144cc143 VS |
14396 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14397 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14398 | goto err; |
c16ed4be | 14399 | } |
57779d06 | 14400 | break; |
57779d06 | 14401 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 14402 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 14403 | INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
14404 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14405 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14406 | goto err; |
6c0fd451 DL |
14407 | } |
14408 | break; | |
14409 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14410 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14411 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 14412 | if (INTEL_GEN(dev_priv) < 4) { |
144cc143 VS |
14413 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14414 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14415 | goto err; |
c16ed4be | 14416 | } |
b5626747 | 14417 | break; |
7531208b | 14418 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 14419 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
144cc143 VS |
14420 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14421 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14422 | goto err; |
7531208b DL |
14423 | } |
14424 | break; | |
04b3924d VS |
14425 | case DRM_FORMAT_YUYV: |
14426 | case DRM_FORMAT_UYVY: | |
14427 | case DRM_FORMAT_YVYU: | |
14428 | case DRM_FORMAT_VYUY: | |
ab33081a | 14429 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
144cc143 VS |
14430 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14431 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14432 | goto err; |
c16ed4be | 14433 | } |
57cd6508 CW |
14434 | break; |
14435 | default: | |
144cc143 VS |
14436 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14437 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14438 | goto err; |
57cd6508 CW |
14439 | } |
14440 | ||
90f9a336 VS |
14441 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14442 | if (mode_cmd->offsets[0] != 0) | |
24dbf51a | 14443 | goto err; |
90f9a336 | 14444 | |
24dbf51a CW |
14445 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, |
14446 | &intel_fb->base, mode_cmd); | |
d88c4afd VS |
14447 | |
14448 | stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0); | |
14449 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
144cc143 VS |
14450 | DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n", |
14451 | mode_cmd->pitches[0], stride_alignment); | |
d88c4afd VS |
14452 | goto err; |
14453 | } | |
14454 | ||
c7d73f6a DV |
14455 | intel_fb->obj = obj; |
14456 | ||
6687c906 VS |
14457 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
14458 | if (ret) | |
9aceb5c1 | 14459 | goto err; |
2d7a215f | 14460 | |
24dbf51a CW |
14461 | ret = drm_framebuffer_init(obj->base.dev, |
14462 | &intel_fb->base, | |
14463 | &intel_fb_funcs); | |
79e53945 JB |
14464 | if (ret) { |
14465 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
24dbf51a | 14466 | goto err; |
79e53945 JB |
14467 | } |
14468 | ||
79e53945 | 14469 | return 0; |
24dbf51a CW |
14470 | |
14471 | err: | |
dd689287 CW |
14472 | i915_gem_object_lock(obj); |
14473 | obj->framebuffer_references--; | |
14474 | i915_gem_object_unlock(obj); | |
24dbf51a | 14475 | return ret; |
79e53945 JB |
14476 | } |
14477 | ||
79e53945 JB |
14478 | static struct drm_framebuffer * |
14479 | intel_user_framebuffer_create(struct drm_device *dev, | |
14480 | struct drm_file *filp, | |
1eb83451 | 14481 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14482 | { |
dcb1394e | 14483 | struct drm_framebuffer *fb; |
05394f39 | 14484 | struct drm_i915_gem_object *obj; |
76dc3769 | 14485 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14486 | |
03ac0642 CW |
14487 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
14488 | if (!obj) | |
cce13ff7 | 14489 | return ERR_PTR(-ENOENT); |
79e53945 | 14490 | |
24dbf51a | 14491 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 14492 | if (IS_ERR(fb)) |
f0cd5182 | 14493 | i915_gem_object_put(obj); |
dcb1394e LW |
14494 | |
14495 | return fb; | |
79e53945 JB |
14496 | } |
14497 | ||
778e23a9 CW |
14498 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
14499 | { | |
14500 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
14501 | ||
14502 | drm_atomic_state_default_release(state); | |
14503 | ||
14504 | i915_sw_fence_fini(&intel_state->commit_ready); | |
14505 | ||
14506 | kfree(state); | |
14507 | } | |
14508 | ||
79e53945 | 14509 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14510 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14511 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14512 | .atomic_check = intel_atomic_check, |
14513 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14514 | .atomic_state_alloc = intel_atomic_state_alloc, |
14515 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 14516 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
14517 | }; |
14518 | ||
88212941 ID |
14519 | /** |
14520 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14521 | * @dev_priv: device private | |
14522 | */ | |
14523 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14524 | { |
7ff89ca2 VS |
14525 | intel_init_cdclk_hooks(dev_priv); |
14526 | ||
88212941 | 14527 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14528 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14529 | dev_priv->display.get_initial_plane_config = |
14530 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14531 | dev_priv->display.crtc_compute_clock = |
14532 | haswell_crtc_compute_clock; | |
14533 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14534 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14535 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14536 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14537 | dev_priv->display.get_initial_plane_config = |
14538 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14539 | dev_priv->display.crtc_compute_clock = |
14540 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14541 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14542 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14543 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14544 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14545 | dev_priv->display.get_initial_plane_config = |
14546 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14547 | dev_priv->display.crtc_compute_clock = |
14548 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14549 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14550 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14551 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14552 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14553 | dev_priv->display.get_initial_plane_config = |
14554 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14555 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14556 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14557 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14558 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14559 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14560 | dev_priv->display.get_initial_plane_config = | |
14561 | i9xx_get_initial_plane_config; | |
14562 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14563 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14564 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14565 | } else if (IS_G4X(dev_priv)) { |
14566 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14567 | dev_priv->display.get_initial_plane_config = | |
14568 | i9xx_get_initial_plane_config; | |
14569 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14570 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14571 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14572 | } else if (IS_PINEVIEW(dev_priv)) { |
14573 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14574 | dev_priv->display.get_initial_plane_config = | |
14575 | i9xx_get_initial_plane_config; | |
14576 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14577 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14578 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14579 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14580 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14581 | dev_priv->display.get_initial_plane_config = |
14582 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14583 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14584 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14585 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14586 | } else { |
14587 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14588 | dev_priv->display.get_initial_plane_config = | |
14589 | i9xx_get_initial_plane_config; | |
14590 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14591 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14592 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14593 | } |
e70236a8 | 14594 | |
88212941 | 14595 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14596 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14597 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14598 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14599 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14600 | /* FIXME: detect B0+ stepping and use auto training */ |
14601 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14602 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14603 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14604 | } |
14605 | ||
27082493 L |
14606 | if (dev_priv->info.gen >= 9) |
14607 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
14608 | else | |
14609 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
14610 | ||
5a21b665 DV |
14611 | switch (INTEL_INFO(dev_priv)->gen) { |
14612 | case 2: | |
14613 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14614 | break; | |
14615 | ||
14616 | case 3: | |
14617 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14618 | break; | |
14619 | ||
14620 | case 4: | |
14621 | case 5: | |
14622 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14623 | break; | |
14624 | ||
14625 | case 6: | |
14626 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14627 | break; | |
14628 | case 7: | |
14629 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
14630 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
14631 | break; | |
14632 | case 9: | |
14633 | /* Drop through - unsupported since execlist only. */ | |
14634 | default: | |
14635 | /* Default just returns -ENODEV to indicate unsupported */ | |
14636 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
14637 | } | |
e70236a8 JB |
14638 | } |
14639 | ||
b690e96c JB |
14640 | /* |
14641 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14642 | * resume, or other times. This quirk makes sure that's the case for | |
14643 | * affected systems. | |
14644 | */ | |
0206e353 | 14645 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 14646 | { |
fac5e23e | 14647 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
14648 | |
14649 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14650 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14651 | } |
14652 | ||
b6b5d049 VS |
14653 | static void quirk_pipeb_force(struct drm_device *dev) |
14654 | { | |
fac5e23e | 14655 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
14656 | |
14657 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14658 | DRM_INFO("applying pipe b force quirk\n"); | |
14659 | } | |
14660 | ||
435793df KP |
14661 | /* |
14662 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14663 | */ | |
14664 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14665 | { | |
fac5e23e | 14666 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 14667 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 14668 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14669 | } |
14670 | ||
4dca20ef | 14671 | /* |
5a15ab5b CE |
14672 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14673 | * brightness value | |
4dca20ef CE |
14674 | */ |
14675 | static void quirk_invert_brightness(struct drm_device *dev) | |
14676 | { | |
fac5e23e | 14677 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 14678 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 14679 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14680 | } |
14681 | ||
9c72cc6f SD |
14682 | /* Some VBT's incorrectly indicate no backlight is present */ |
14683 | static void quirk_backlight_present(struct drm_device *dev) | |
14684 | { | |
fac5e23e | 14685 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
14686 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
14687 | DRM_INFO("applying backlight present quirk\n"); | |
14688 | } | |
14689 | ||
b690e96c JB |
14690 | struct intel_quirk { |
14691 | int device; | |
14692 | int subsystem_vendor; | |
14693 | int subsystem_device; | |
14694 | void (*hook)(struct drm_device *dev); | |
14695 | }; | |
14696 | ||
5f85f176 EE |
14697 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14698 | struct intel_dmi_quirk { | |
14699 | void (*hook)(struct drm_device *dev); | |
14700 | const struct dmi_system_id (*dmi_id_list)[]; | |
14701 | }; | |
14702 | ||
14703 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14704 | { | |
14705 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14706 | return 1; | |
14707 | } | |
14708 | ||
14709 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14710 | { | |
14711 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14712 | { | |
14713 | .callback = intel_dmi_reverse_brightness, | |
14714 | .ident = "NCR Corporation", | |
14715 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14716 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14717 | }, | |
14718 | }, | |
14719 | { } /* terminating entry */ | |
14720 | }, | |
14721 | .hook = quirk_invert_brightness, | |
14722 | }, | |
14723 | }; | |
14724 | ||
c43b5634 | 14725 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14726 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14727 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14728 | ||
b690e96c JB |
14729 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14730 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14731 | ||
5f080c0f VS |
14732 | /* 830 needs to leave pipe A & dpll A up */ |
14733 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14734 | ||
b6b5d049 VS |
14735 | /* 830 needs to leave pipe B & dpll B up */ |
14736 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14737 | ||
435793df KP |
14738 | /* Lenovo U160 cannot use SSC on LVDS */ |
14739 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14740 | |
14741 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14742 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14743 | |
be505f64 AH |
14744 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14745 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14746 | ||
14747 | /* Acer/eMachines G725 */ | |
14748 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14749 | ||
14750 | /* Acer/eMachines e725 */ | |
14751 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14752 | ||
14753 | /* Acer/Packard Bell NCL20 */ | |
14754 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14755 | ||
14756 | /* Acer Aspire 4736Z */ | |
14757 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14758 | |
14759 | /* Acer Aspire 5336 */ | |
14760 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14761 | |
14762 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14763 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14764 | |
dfb3d47b SD |
14765 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14766 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14767 | ||
b2a9601c | 14768 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14769 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14770 | ||
1b9448b0 JN |
14771 | /* Apple Macbook 4,1 */ |
14772 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
14773 | ||
d4967d8c SD |
14774 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14775 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14776 | |
14777 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14778 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14779 | |
14780 | /* Dell Chromebook 11 */ | |
14781 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
14782 | |
14783 | /* Dell Chromebook 11 (2015 version) */ | |
14784 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14785 | }; |
14786 | ||
14787 | static void intel_init_quirks(struct drm_device *dev) | |
14788 | { | |
14789 | struct pci_dev *d = dev->pdev; | |
14790 | int i; | |
14791 | ||
14792 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14793 | struct intel_quirk *q = &intel_quirks[i]; | |
14794 | ||
14795 | if (d->device == q->device && | |
14796 | (d->subsystem_vendor == q->subsystem_vendor || | |
14797 | q->subsystem_vendor == PCI_ANY_ID) && | |
14798 | (d->subsystem_device == q->subsystem_device || | |
14799 | q->subsystem_device == PCI_ANY_ID)) | |
14800 | q->hook(dev); | |
14801 | } | |
5f85f176 EE |
14802 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14803 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14804 | intel_dmi_quirks[i].hook(dev); | |
14805 | } | |
b690e96c JB |
14806 | } |
14807 | ||
9cce37f4 | 14808 | /* Disable the VGA plane that we never use */ |
29b74b7f | 14809 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 14810 | { |
52a05c30 | 14811 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 14812 | u8 sr1; |
920a14b2 | 14813 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 14814 | |
2b37c616 | 14815 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 14816 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14817 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14818 | sr1 = inb(VGA_SR_DATA); |
14819 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 14820 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
14821 | udelay(300); |
14822 | ||
01f5a626 | 14823 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14824 | POSTING_READ(vga_reg); |
14825 | } | |
14826 | ||
f817586c DV |
14827 | void intel_modeset_init_hw(struct drm_device *dev) |
14828 | { | |
fac5e23e | 14829 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 14830 | |
4c75b940 | 14831 | intel_update_cdclk(dev_priv); |
bb0f4aab | 14832 | dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; |
1a617b77 | 14833 | |
46f16e63 | 14834 | intel_init_clock_gating(dev_priv); |
f817586c DV |
14835 | } |
14836 | ||
d93c0372 MR |
14837 | /* |
14838 | * Calculate what we think the watermarks should be for the state we've read | |
14839 | * out of the hardware and then immediately program those watermarks so that | |
14840 | * we ensure the hardware settings match our internal state. | |
14841 | * | |
14842 | * We can calculate what we think WM's should be by creating a duplicate of the | |
14843 | * current state (which was constructed during hardware readout) and running it | |
14844 | * through the atomic check code to calculate new watermark values in the | |
14845 | * state object. | |
14846 | */ | |
14847 | static void sanitize_watermarks(struct drm_device *dev) | |
14848 | { | |
14849 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14850 | struct drm_atomic_state *state; | |
ccf010fb | 14851 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
14852 | struct drm_crtc *crtc; |
14853 | struct drm_crtc_state *cstate; | |
14854 | struct drm_modeset_acquire_ctx ctx; | |
14855 | int ret; | |
14856 | int i; | |
14857 | ||
14858 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 14859 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
14860 | return; |
14861 | ||
14862 | /* | |
14863 | * We need to hold connection_mutex before calling duplicate_state so | |
14864 | * that the connector loop is protected. | |
14865 | */ | |
14866 | drm_modeset_acquire_init(&ctx, 0); | |
14867 | retry: | |
0cd1262d | 14868 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
14869 | if (ret == -EDEADLK) { |
14870 | drm_modeset_backoff(&ctx); | |
14871 | goto retry; | |
14872 | } else if (WARN_ON(ret)) { | |
0cd1262d | 14873 | goto fail; |
d93c0372 MR |
14874 | } |
14875 | ||
14876 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
14877 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 14878 | goto fail; |
d93c0372 | 14879 | |
ccf010fb ML |
14880 | intel_state = to_intel_atomic_state(state); |
14881 | ||
ed4a6a7c MR |
14882 | /* |
14883 | * Hardware readout is the only time we don't want to calculate | |
14884 | * intermediate watermarks (since we don't trust the current | |
14885 | * watermarks). | |
14886 | */ | |
602ae835 VS |
14887 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14888 | intel_state->skip_intermediate_wm = true; | |
ed4a6a7c | 14889 | |
d93c0372 MR |
14890 | ret = intel_atomic_check(dev, state); |
14891 | if (ret) { | |
14892 | /* | |
14893 | * If we fail here, it means that the hardware appears to be | |
14894 | * programmed in a way that shouldn't be possible, given our | |
14895 | * understanding of watermark requirements. This might mean a | |
14896 | * mistake in the hardware readout code or a mistake in the | |
14897 | * watermark calculations for a given platform. Raise a WARN | |
14898 | * so that this is noticeable. | |
14899 | * | |
14900 | * If this actually happens, we'll have to just leave the | |
14901 | * BIOS-programmed watermarks untouched and hope for the best. | |
14902 | */ | |
14903 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 14904 | goto put_state; |
d93c0372 MR |
14905 | } |
14906 | ||
14907 | /* Write calculated watermark values back */ | |
aa5e9b47 | 14908 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
d93c0372 MR |
14909 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); |
14910 | ||
ed4a6a7c | 14911 | cs->wm.need_postvbl_update = true; |
ccf010fb | 14912 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
14913 | } |
14914 | ||
b9a1b717 | 14915 | put_state: |
0853695c | 14916 | drm_atomic_state_put(state); |
0cd1262d | 14917 | fail: |
d93c0372 MR |
14918 | drm_modeset_drop_locks(&ctx); |
14919 | drm_modeset_acquire_fini(&ctx); | |
14920 | } | |
14921 | ||
b079bd17 | 14922 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 14923 | { |
72e96d64 JL |
14924 | struct drm_i915_private *dev_priv = to_i915(dev); |
14925 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 14926 | enum pipe pipe; |
46f297fb | 14927 | struct intel_crtc *crtc; |
79e53945 JB |
14928 | |
14929 | drm_mode_config_init(dev); | |
14930 | ||
14931 | dev->mode_config.min_width = 0; | |
14932 | dev->mode_config.min_height = 0; | |
14933 | ||
019d96cb DA |
14934 | dev->mode_config.preferred_depth = 24; |
14935 | dev->mode_config.prefer_shadow = 1; | |
14936 | ||
25bab385 TU |
14937 | dev->mode_config.allow_fb_modifiers = true; |
14938 | ||
e6ecefaa | 14939 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14940 | |
400c19d9 | 14941 | init_llist_head(&dev_priv->atomic_helper.free_list); |
eb955eee | 14942 | INIT_WORK(&dev_priv->atomic_helper.free_work, |
ba318c61 | 14943 | intel_atomic_helper_free_state_worker); |
eb955eee | 14944 | |
b690e96c JB |
14945 | intel_init_quirks(dev); |
14946 | ||
62d75df7 | 14947 | intel_init_pm(dev_priv); |
1fa61106 | 14948 | |
b7f05d4a | 14949 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 14950 | return 0; |
e3c74757 | 14951 | |
69f92f67 LW |
14952 | /* |
14953 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14954 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14955 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14956 | * indicates as much. | |
14957 | */ | |
6e266956 | 14958 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
14959 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
14960 | DREF_SSC1_ENABLE); | |
14961 | ||
14962 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14963 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14964 | bios_lvds_use_ssc ? "en" : "dis", | |
14965 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14966 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14967 | } | |
14968 | } | |
14969 | ||
5db94019 | 14970 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
14971 | dev->mode_config.max_width = 2048; |
14972 | dev->mode_config.max_height = 2048; | |
5db94019 | 14973 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
14974 | dev->mode_config.max_width = 4096; |
14975 | dev->mode_config.max_height = 4096; | |
79e53945 | 14976 | } else { |
a6c45cf0 CW |
14977 | dev->mode_config.max_width = 8192; |
14978 | dev->mode_config.max_height = 8192; | |
79e53945 | 14979 | } |
068be561 | 14980 | |
2a307c2e JN |
14981 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
14982 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 14983 | dev->mode_config.cursor_height = 1023; |
5db94019 | 14984 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
14985 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14986 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14987 | } else { | |
14988 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14989 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14990 | } | |
14991 | ||
72e96d64 | 14992 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 14993 | |
28c97730 | 14994 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
14995 | INTEL_INFO(dev_priv)->num_pipes, |
14996 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14997 | |
055e393f | 14998 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
14999 | int ret; |
15000 | ||
5ab0d85b | 15001 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
15002 | if (ret) { |
15003 | drm_mode_config_cleanup(dev); | |
15004 | return ret; | |
15005 | } | |
79e53945 JB |
15006 | } |
15007 | ||
e72f9fbf | 15008 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15009 | |
5be6e334 VS |
15010 | intel_update_czclk(dev_priv); |
15011 | intel_modeset_init_hw(dev); | |
15012 | ||
b2045352 | 15013 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 15014 | intel_update_max_cdclk(dev_priv); |
b2045352 | 15015 | |
9cce37f4 | 15016 | /* Just disable it once at startup */ |
29b74b7f | 15017 | i915_disable_vga(dev_priv); |
c39055b0 | 15018 | intel_setup_outputs(dev_priv); |
11be49eb | 15019 | |
6e9f798d | 15020 | drm_modeset_lock_all(dev); |
043e9bda | 15021 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15022 | drm_modeset_unlock_all(dev); |
46f297fb | 15023 | |
d3fcc808 | 15024 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15025 | struct intel_initial_plane_config plane_config = {}; |
15026 | ||
46f297fb JB |
15027 | if (!crtc->active) |
15028 | continue; | |
15029 | ||
46f297fb | 15030 | /* |
46f297fb JB |
15031 | * Note that reserving the BIOS fb up front prevents us |
15032 | * from stuffing other stolen allocations like the ring | |
15033 | * on top. This prevents some ugliness at boot time, and | |
15034 | * can even allow for smooth boot transitions if the BIOS | |
15035 | * fb is large enough for the active pipe configuration. | |
15036 | */ | |
eeebeac5 ML |
15037 | dev_priv->display.get_initial_plane_config(crtc, |
15038 | &plane_config); | |
15039 | ||
15040 | /* | |
15041 | * If the fb is shared between multiple heads, we'll | |
15042 | * just get the first one. | |
15043 | */ | |
15044 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15045 | } |
d93c0372 MR |
15046 | |
15047 | /* | |
15048 | * Make sure hardware watermarks really match the state we read out. | |
15049 | * Note that we need to do this after reconstructing the BIOS fb's | |
15050 | * since the watermark calculation done here will use pstate->fb. | |
15051 | */ | |
602ae835 VS |
15052 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
15053 | sanitize_watermarks(dev); | |
b079bd17 VS |
15054 | |
15055 | return 0; | |
2c7111db CW |
15056 | } |
15057 | ||
7fad798e DV |
15058 | static void intel_enable_pipe_a(struct drm_device *dev) |
15059 | { | |
15060 | struct intel_connector *connector; | |
f9e905ca | 15061 | struct drm_connector_list_iter conn_iter; |
7fad798e DV |
15062 | struct drm_connector *crt = NULL; |
15063 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15064 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
6c5ed5ae | 15065 | int ret; |
7fad798e DV |
15066 | |
15067 | /* We can't just switch on the pipe A, we need to set things up with a | |
15068 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15069 | * by enabling the load detect pipe once. */ | |
f9e905ca DV |
15070 | drm_connector_list_iter_begin(dev, &conn_iter); |
15071 | for_each_intel_connector_iter(connector, &conn_iter) { | |
7fad798e DV |
15072 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15073 | crt = &connector->base; | |
15074 | break; | |
15075 | } | |
15076 | } | |
f9e905ca | 15077 | drm_connector_list_iter_end(&conn_iter); |
7fad798e DV |
15078 | |
15079 | if (!crt) | |
15080 | return; | |
15081 | ||
6c5ed5ae ML |
15082 | ret = intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx); |
15083 | WARN(ret < 0, "All modeset mutexes are locked, but intel_get_load_detect_pipe failed\n"); | |
15084 | ||
15085 | if (ret > 0) | |
49172fee | 15086 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15087 | } |
15088 | ||
fa555837 DV |
15089 | static bool |
15090 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15091 | { | |
b7f05d4a | 15092 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 15093 | u32 val; |
fa555837 | 15094 | |
b7f05d4a | 15095 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
15096 | return true; |
15097 | ||
649636ef | 15098 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15099 | |
15100 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15101 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15102 | return false; | |
15103 | ||
15104 | return true; | |
15105 | } | |
15106 | ||
02e93c35 VS |
15107 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15108 | { | |
15109 | struct drm_device *dev = crtc->base.dev; | |
15110 | struct intel_encoder *encoder; | |
15111 | ||
15112 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15113 | return true; | |
15114 | ||
15115 | return false; | |
15116 | } | |
15117 | ||
496b0fc3 ML |
15118 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
15119 | { | |
15120 | struct drm_device *dev = encoder->base.dev; | |
15121 | struct intel_connector *connector; | |
15122 | ||
15123 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15124 | return connector; | |
15125 | ||
15126 | return NULL; | |
15127 | } | |
15128 | ||
a168f5b3 VS |
15129 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
15130 | enum transcoder pch_transcoder) | |
15131 | { | |
15132 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
15133 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
15134 | } | |
15135 | ||
24929352 DV |
15136 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15137 | { | |
15138 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 15139 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 15140 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15141 | |
24929352 | 15142 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15143 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15144 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15145 | ||
15146 | I915_WRITE(reg, | |
15147 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15148 | } | |
24929352 | 15149 | |
d3eaf884 | 15150 | /* restore vblank interrupts to correct state */ |
9625604c | 15151 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15152 | if (crtc->active) { |
f9cd7b88 VS |
15153 | struct intel_plane *plane; |
15154 | ||
9625604c | 15155 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15156 | |
15157 | /* Disable everything but the primary plane */ | |
15158 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15159 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15160 | continue; | |
15161 | ||
72259536 | 15162 | trace_intel_disable_plane(&plane->base, crtc); |
f9cd7b88 VS |
15163 | plane->disable_plane(&plane->base, &crtc->base); |
15164 | } | |
9625604c | 15165 | } |
d3eaf884 | 15166 | |
24929352 | 15167 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15168 | * disable the crtc (and hence change the state) if it is wrong. Note |
15169 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 15170 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
15171 | bool plane; |
15172 | ||
78108b7c VS |
15173 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
15174 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
15175 | |
15176 | /* Pipe has the wrong plane attached and the plane is active. | |
15177 | * Temporarily change the plane mapping and disable everything | |
15178 | * ... */ | |
15179 | plane = crtc->plane; | |
1d4258db | 15180 | crtc->base.primary->state->visible = true; |
24929352 | 15181 | crtc->plane = !plane; |
b17d48e2 | 15182 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15183 | crtc->plane = plane; |
24929352 | 15184 | } |
24929352 | 15185 | |
7fad798e DV |
15186 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15187 | crtc->pipe == PIPE_A && !crtc->active) { | |
15188 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15189 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15190 | * call below we restore the pipe to the right state, but leave | |
15191 | * the required bits on. */ | |
15192 | intel_enable_pipe_a(dev); | |
15193 | } | |
15194 | ||
24929352 DV |
15195 | /* Adjust the state of the output pipe according to whether we |
15196 | * have active connectors/encoders. */ | |
842e0307 | 15197 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15198 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15199 | |
49cff963 | 15200 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
15201 | /* |
15202 | * We start out with underrun reporting disabled to avoid races. | |
15203 | * For correct bookkeeping mark this on active crtcs. | |
15204 | * | |
c5ab3bc0 DV |
15205 | * Also on gmch platforms we dont have any hardware bits to |
15206 | * disable the underrun reporting. Which means we need to start | |
15207 | * out with underrun reporting disabled also on inactive pipes, | |
15208 | * since otherwise we'll complain about the garbage we read when | |
15209 | * e.g. coming up after runtime pm. | |
15210 | * | |
4cc31489 DV |
15211 | * No protection against concurrent access is required - at |
15212 | * worst a fifo underrun happens which also sets this to false. | |
15213 | */ | |
15214 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
15215 | /* |
15216 | * We track the PCH trancoder underrun reporting state | |
15217 | * within the crtc. With crtc for pipe A housing the underrun | |
15218 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
15219 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
15220 | * and marking underrun reporting as disabled for the non-existing | |
15221 | * PCH transcoders B and C would prevent enabling the south | |
15222 | * error interrupt (see cpt_can_enable_serr_int()). | |
15223 | */ | |
15224 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
15225 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 15226 | } |
24929352 DV |
15227 | } |
15228 | ||
15229 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15230 | { | |
15231 | struct intel_connector *connector; | |
24929352 DV |
15232 | |
15233 | /* We need to check both for a crtc link (meaning that the | |
15234 | * encoder is active and trying to read from a pipe) and the | |
15235 | * pipe itself being active. */ | |
15236 | bool has_active_crtc = encoder->base.crtc && | |
15237 | to_intel_crtc(encoder->base.crtc)->active; | |
15238 | ||
496b0fc3 ML |
15239 | connector = intel_encoder_find_connector(encoder); |
15240 | if (connector && !has_active_crtc) { | |
24929352 DV |
15241 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15242 | encoder->base.base.id, | |
8e329a03 | 15243 | encoder->base.name); |
24929352 DV |
15244 | |
15245 | /* Connector is active, but has no active pipe. This is | |
15246 | * fallout from our resume register restoring. Disable | |
15247 | * the encoder manually again. */ | |
15248 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
15249 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
15250 | ||
24929352 DV |
15251 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
15252 | encoder->base.base.id, | |
8e329a03 | 15253 | encoder->base.name); |
fd6bbda9 | 15254 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 15255 | if (encoder->post_disable) |
fd6bbda9 | 15256 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 15257 | } |
7f1950fb | 15258 | encoder->base.crtc = NULL; |
24929352 DV |
15259 | |
15260 | /* Inconsistent output/port/pipe state happens presumably due to | |
15261 | * a bug in one of the get_hw_state functions. Or someplace else | |
15262 | * in our code, like the register restore mess on resume. Clamp | |
15263 | * things to off as a safer default. */ | |
fd6bbda9 ML |
15264 | |
15265 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15266 | connector->base.encoder = NULL; | |
24929352 DV |
15267 | } |
15268 | /* Enabled encoders without active connectors will be fixed in | |
15269 | * the crtc fixup. */ | |
15270 | } | |
15271 | ||
29b74b7f | 15272 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 15273 | { |
920a14b2 | 15274 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 15275 | |
04098753 ID |
15276 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15277 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 15278 | i915_disable_vga(dev_priv); |
04098753 ID |
15279 | } |
15280 | } | |
15281 | ||
29b74b7f | 15282 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 15283 | { |
8dc8a27c PZ |
15284 | /* This function can be called both from intel_modeset_setup_hw_state or |
15285 | * at a very early point in our resume sequence, where the power well | |
15286 | * structures are not yet restored. Since this function is at a very | |
15287 | * paranoid "someone might have enabled VGA while we were not looking" | |
15288 | * level, just check if the power well is enabled instead of trying to | |
15289 | * follow the "don't touch the power well if we don't need it" policy | |
15290 | * the rest of the driver uses. */ | |
6392f847 | 15291 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15292 | return; |
15293 | ||
29b74b7f | 15294 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
15295 | |
15296 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15297 | } |
15298 | ||
f9cd7b88 | 15299 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15300 | { |
f9cd7b88 | 15301 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15302 | |
f9cd7b88 | 15303 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15304 | } |
15305 | ||
f9cd7b88 VS |
15306 | /* FIXME read out full plane state for all planes */ |
15307 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15308 | { |
e9728bd8 VS |
15309 | struct intel_plane *primary = to_intel_plane(crtc->base.primary); |
15310 | bool visible; | |
d032ffa0 | 15311 | |
e9728bd8 | 15312 | visible = crtc->active && primary_get_hw_state(primary); |
b26d3ea3 | 15313 | |
e9728bd8 VS |
15314 | intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), |
15315 | to_intel_plane_state(primary->base.state), | |
15316 | visible); | |
98ec7739 VS |
15317 | } |
15318 | ||
30e984df | 15319 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 15320 | { |
fac5e23e | 15321 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 15322 | enum pipe pipe; |
24929352 DV |
15323 | struct intel_crtc *crtc; |
15324 | struct intel_encoder *encoder; | |
15325 | struct intel_connector *connector; | |
f9e905ca | 15326 | struct drm_connector_list_iter conn_iter; |
5358901f | 15327 | int i; |
24929352 | 15328 | |
565602d7 ML |
15329 | dev_priv->active_crtcs = 0; |
15330 | ||
d3fcc808 | 15331 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
15332 | struct intel_crtc_state *crtc_state = |
15333 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 15334 | |
ec2dc6a0 | 15335 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
15336 | memset(crtc_state, 0, sizeof(*crtc_state)); |
15337 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15338 | |
565602d7 ML |
15339 | crtc_state->base.active = crtc_state->base.enable = |
15340 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15341 | ||
15342 | crtc->base.enabled = crtc_state->base.enable; | |
15343 | crtc->active = crtc_state->base.active; | |
15344 | ||
aca1ebf4 | 15345 | if (crtc_state->base.active) |
565602d7 ML |
15346 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
15347 | ||
f9cd7b88 | 15348 | readout_plane_state(crtc); |
24929352 | 15349 | |
78108b7c VS |
15350 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
15351 | crtc->base.base.id, crtc->base.name, | |
a8cd6da0 | 15352 | enableddisabled(crtc_state->base.active)); |
24929352 DV |
15353 | } |
15354 | ||
5358901f DV |
15355 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15356 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15357 | ||
2edd6443 | 15358 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
2c42e535 ACO |
15359 | &pll->state.hw_state); |
15360 | pll->state.crtc_mask = 0; | |
d3fcc808 | 15361 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
15362 | struct intel_crtc_state *crtc_state = |
15363 | to_intel_crtc_state(crtc->base.state); | |
15364 | ||
15365 | if (crtc_state->base.active && | |
15366 | crtc_state->shared_dpll == pll) | |
2c42e535 | 15367 | pll->state.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15368 | } |
2c42e535 | 15369 | pll->active_mask = pll->state.crtc_mask; |
5358901f | 15370 | |
1e6f2ddc | 15371 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
2c42e535 | 15372 | pll->name, pll->state.crtc_mask, pll->on); |
5358901f DV |
15373 | } |
15374 | ||
b2784e15 | 15375 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15376 | pipe = 0; |
15377 | ||
15378 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
15379 | struct intel_crtc_state *crtc_state; |
15380 | ||
98187836 | 15381 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 15382 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 15383 | |
045ac3b5 | 15384 | encoder->base.crtc = &crtc->base; |
a8cd6da0 VS |
15385 | crtc_state->output_types |= 1 << encoder->type; |
15386 | encoder->get_config(encoder, crtc_state); | |
24929352 DV |
15387 | } else { |
15388 | encoder->base.crtc = NULL; | |
15389 | } | |
15390 | ||
6f2bcceb | 15391 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
15392 | encoder->base.base.id, encoder->base.name, |
15393 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 15394 | pipe_name(pipe)); |
24929352 DV |
15395 | } |
15396 | ||
f9e905ca DV |
15397 | drm_connector_list_iter_begin(dev, &conn_iter); |
15398 | for_each_intel_connector_iter(connector, &conn_iter) { | |
24929352 DV |
15399 | if (connector->get_hw_state(connector)) { |
15400 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15401 | |
15402 | encoder = connector->encoder; | |
15403 | connector->base.encoder = &encoder->base; | |
15404 | ||
15405 | if (encoder->base.crtc && | |
15406 | encoder->base.crtc->state->active) { | |
15407 | /* | |
15408 | * This has to be done during hardware readout | |
15409 | * because anything calling .crtc_disable may | |
15410 | * rely on the connector_mask being accurate. | |
15411 | */ | |
15412 | encoder->base.crtc->state->connector_mask |= | |
15413 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15414 | encoder->base.crtc->state->encoder_mask |= |
15415 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15416 | } |
15417 | ||
24929352 DV |
15418 | } else { |
15419 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15420 | connector->base.encoder = NULL; | |
15421 | } | |
15422 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
15423 | connector->base.base.id, connector->base.name, |
15424 | enableddisabled(connector->base.encoder)); | |
24929352 | 15425 | } |
f9e905ca | 15426 | drm_connector_list_iter_end(&conn_iter); |
7f4c6284 VS |
15427 | |
15428 | for_each_intel_crtc(dev, crtc) { | |
a8cd6da0 VS |
15429 | struct intel_crtc_state *crtc_state = |
15430 | to_intel_crtc_state(crtc->base.state); | |
aca1ebf4 VS |
15431 | int pixclk = 0; |
15432 | ||
a8cd6da0 | 15433 | crtc->base.hwmode = crtc_state->base.adjusted_mode; |
7f4c6284 VS |
15434 | |
15435 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
a8cd6da0 VS |
15436 | if (crtc_state->base.active) { |
15437 | intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); | |
15438 | intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); | |
7f4c6284 VS |
15439 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
15440 | ||
15441 | /* | |
15442 | * The initial mode needs to be set in order to keep | |
15443 | * the atomic core happy. It wants a valid mode if the | |
15444 | * crtc's enabled, so we do the above call. | |
15445 | * | |
7800fb69 DV |
15446 | * But we don't set all the derived state fully, hence |
15447 | * set a flag to indicate that a full recalculation is | |
15448 | * needed on the next commit. | |
7f4c6284 | 15449 | */ |
a8cd6da0 | 15450 | crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; |
9eca6832 | 15451 | |
a7d1b3f4 VS |
15452 | intel_crtc_compute_pixel_rate(crtc_state); |
15453 | ||
15454 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || | |
15455 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15456 | pixclk = crtc_state->pixel_rate; | |
aca1ebf4 VS |
15457 | else |
15458 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15459 | ||
15460 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
a8cd6da0 | 15461 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
aca1ebf4 VS |
15462 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
15463 | ||
9eca6832 VS |
15464 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); |
15465 | update_scanline_offset(crtc); | |
7f4c6284 | 15466 | } |
e3b247da | 15467 | |
aca1ebf4 VS |
15468 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
15469 | ||
a8cd6da0 | 15470 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 15471 | } |
30e984df DV |
15472 | } |
15473 | ||
62b69566 ACO |
15474 | static void |
15475 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
15476 | { | |
15477 | struct intel_encoder *encoder; | |
15478 | ||
15479 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
15480 | u64 get_domains; | |
15481 | enum intel_display_power_domain domain; | |
15482 | ||
15483 | if (!encoder->get_power_domains) | |
15484 | continue; | |
15485 | ||
15486 | get_domains = encoder->get_power_domains(encoder); | |
15487 | for_each_power_domain(domain, get_domains) | |
15488 | intel_display_power_get(dev_priv, domain); | |
15489 | } | |
15490 | } | |
15491 | ||
043e9bda ML |
15492 | /* Scan out the current hw modeset state, |
15493 | * and sanitizes it to the current state | |
15494 | */ | |
15495 | static void | |
15496 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 15497 | { |
fac5e23e | 15498 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 15499 | enum pipe pipe; |
30e984df DV |
15500 | struct intel_crtc *crtc; |
15501 | struct intel_encoder *encoder; | |
35c95375 | 15502 | int i; |
30e984df DV |
15503 | |
15504 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15505 | |
15506 | /* HW state is read out, now we need to sanitize this mess. */ | |
62b69566 ACO |
15507 | get_encoder_power_domains(dev_priv); |
15508 | ||
b2784e15 | 15509 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15510 | intel_sanitize_encoder(encoder); |
15511 | } | |
15512 | ||
055e393f | 15513 | for_each_pipe(dev_priv, pipe) { |
98187836 | 15514 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 15515 | |
24929352 | 15516 | intel_sanitize_crtc(crtc); |
6e3c9717 ACO |
15517 | intel_dump_pipe_config(crtc, crtc->config, |
15518 | "[setup_hw_state]"); | |
24929352 | 15519 | } |
9a935856 | 15520 | |
d29b2f9d ACO |
15521 | intel_modeset_update_connector_atomic_state(dev); |
15522 | ||
35c95375 DV |
15523 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15524 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15525 | ||
2dd66ebd | 15526 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15527 | continue; |
15528 | ||
15529 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15530 | ||
2edd6443 | 15531 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15532 | pll->on = false; |
15533 | } | |
15534 | ||
04548cba VS |
15535 | if (IS_G4X(dev_priv)) { |
15536 | g4x_wm_get_hw_state(dev); | |
15537 | g4x_wm_sanitize(dev_priv); | |
15538 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
6eb1a681 | 15539 | vlv_wm_get_hw_state(dev); |
602ae835 VS |
15540 | vlv_wm_sanitize(dev_priv); |
15541 | } else if (IS_GEN9(dev_priv)) { | |
3078999f | 15542 | skl_wm_get_hw_state(dev); |
602ae835 | 15543 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
243e6a44 | 15544 | ilk_wm_get_hw_state(dev); |
602ae835 | 15545 | } |
292b990e ML |
15546 | |
15547 | for_each_intel_crtc(dev, crtc) { | |
d8fc70b7 | 15548 | u64 put_domains; |
292b990e | 15549 | |
74bff5f9 | 15550 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15551 | if (WARN_ON(put_domains)) |
15552 | modeset_put_power_domains(dev_priv, put_domains); | |
15553 | } | |
15554 | intel_display_set_init_power(dev_priv, false); | |
010cf73d | 15555 | |
8d8c386c ID |
15556 | intel_power_domains_verify_state(dev_priv); |
15557 | ||
010cf73d | 15558 | intel_fbc_init_pipe_state(dev_priv); |
043e9bda | 15559 | } |
7d0bc1ea | 15560 | |
043e9bda ML |
15561 | void intel_display_resume(struct drm_device *dev) |
15562 | { | |
e2c8b870 ML |
15563 | struct drm_i915_private *dev_priv = to_i915(dev); |
15564 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15565 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15566 | int ret; |
f30da187 | 15567 | |
e2c8b870 | 15568 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
15569 | if (state) |
15570 | state->acquire_ctx = &ctx; | |
043e9bda | 15571 | |
e2c8b870 | 15572 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15573 | |
73974893 ML |
15574 | while (1) { |
15575 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
15576 | if (ret != -EDEADLK) | |
15577 | break; | |
043e9bda | 15578 | |
e2c8b870 | 15579 | drm_modeset_backoff(&ctx); |
e2c8b870 | 15580 | } |
043e9bda | 15581 | |
73974893 | 15582 | if (!ret) |
581e49fe | 15583 | ret = __intel_display_resume(dev, state, &ctx); |
73974893 | 15584 | |
e2c8b870 ML |
15585 | drm_modeset_drop_locks(&ctx); |
15586 | drm_modeset_acquire_fini(&ctx); | |
043e9bda | 15587 | |
0853695c | 15588 | if (ret) |
e2c8b870 | 15589 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
3c5e37f1 CW |
15590 | if (state) |
15591 | drm_atomic_state_put(state); | |
2c7111db CW |
15592 | } |
15593 | ||
15594 | void intel_modeset_gem_init(struct drm_device *dev) | |
15595 | { | |
dc97997a | 15596 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15597 | |
dc97997a | 15598 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15599 | |
1ee8da6d | 15600 | intel_setup_overlay(dev_priv); |
1ebaa0b9 CW |
15601 | } |
15602 | ||
15603 | int intel_connector_register(struct drm_connector *connector) | |
15604 | { | |
15605 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
15606 | int ret; | |
15607 | ||
15608 | ret = intel_backlight_device_register(intel_connector); | |
15609 | if (ret) | |
15610 | goto err; | |
15611 | ||
15612 | return 0; | |
0962c3c9 | 15613 | |
1ebaa0b9 CW |
15614 | err: |
15615 | return ret; | |
79e53945 JB |
15616 | } |
15617 | ||
c191eca1 | 15618 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 15619 | { |
e63d87c0 | 15620 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 15621 | |
e63d87c0 | 15622 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 15623 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
15624 | } |
15625 | ||
79e53945 JB |
15626 | void intel_modeset_cleanup(struct drm_device *dev) |
15627 | { | |
fac5e23e | 15628 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 15629 | |
eb955eee CW |
15630 | flush_work(&dev_priv->atomic_helper.free_work); |
15631 | WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); | |
15632 | ||
dc97997a | 15633 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 15634 | |
fd0c0642 DV |
15635 | /* |
15636 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15637 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15638 | * experience fancy races otherwise. |
15639 | */ | |
2aeb7d3a | 15640 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15641 | |
fd0c0642 DV |
15642 | /* |
15643 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15644 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15645 | */ | |
f87ea761 | 15646 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15647 | |
723bfd70 JB |
15648 | intel_unregister_dsm_handler(); |
15649 | ||
c937ab3e | 15650 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15651 | |
1630fe75 CW |
15652 | /* flush any delayed tasks or pending work */ |
15653 | flush_scheduled_work(); | |
15654 | ||
79e53945 | 15655 | drm_mode_config_cleanup(dev); |
4d7bb011 | 15656 | |
1ee8da6d | 15657 | intel_cleanup_overlay(dev_priv); |
ae48434c | 15658 | |
dc97997a | 15659 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 15660 | |
40196446 | 15661 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
15662 | } |
15663 | ||
df0e9248 CW |
15664 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15665 | struct intel_encoder *encoder) | |
15666 | { | |
15667 | connector->encoder = encoder; | |
15668 | drm_mode_connector_attach_encoder(&connector->base, | |
15669 | &encoder->base); | |
79e53945 | 15670 | } |
28d52043 DA |
15671 | |
15672 | /* | |
15673 | * set vga decode state - true == enable VGA decode | |
15674 | */ | |
6315b5d3 | 15675 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 15676 | { |
6315b5d3 | 15677 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15678 | u16 gmch_ctrl; |
15679 | ||
75fa041d CW |
15680 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15681 | DRM_ERROR("failed to read control word\n"); | |
15682 | return -EIO; | |
15683 | } | |
15684 | ||
c0cc8a55 CW |
15685 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15686 | return 0; | |
15687 | ||
28d52043 DA |
15688 | if (state) |
15689 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15690 | else | |
15691 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15692 | |
15693 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15694 | DRM_ERROR("failed to write control word\n"); | |
15695 | return -EIO; | |
15696 | } | |
15697 | ||
28d52043 DA |
15698 | return 0; |
15699 | } | |
c4a1d9e4 | 15700 | |
98a2f411 CW |
15701 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
15702 | ||
c4a1d9e4 | 15703 | struct intel_display_error_state { |
ff57f1b0 PZ |
15704 | |
15705 | u32 power_well_driver; | |
15706 | ||
63b66e5b CW |
15707 | int num_transcoders; |
15708 | ||
c4a1d9e4 CW |
15709 | struct intel_cursor_error_state { |
15710 | u32 control; | |
15711 | u32 position; | |
15712 | u32 base; | |
15713 | u32 size; | |
52331309 | 15714 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15715 | |
15716 | struct intel_pipe_error_state { | |
ddf9c536 | 15717 | bool power_domain_on; |
c4a1d9e4 | 15718 | u32 source; |
f301b1e1 | 15719 | u32 stat; |
52331309 | 15720 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15721 | |
15722 | struct intel_plane_error_state { | |
15723 | u32 control; | |
15724 | u32 stride; | |
15725 | u32 size; | |
15726 | u32 pos; | |
15727 | u32 addr; | |
15728 | u32 surface; | |
15729 | u32 tile_offset; | |
52331309 | 15730 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15731 | |
15732 | struct intel_transcoder_error_state { | |
ddf9c536 | 15733 | bool power_domain_on; |
63b66e5b CW |
15734 | enum transcoder cpu_transcoder; |
15735 | ||
15736 | u32 conf; | |
15737 | ||
15738 | u32 htotal; | |
15739 | u32 hblank; | |
15740 | u32 hsync; | |
15741 | u32 vtotal; | |
15742 | u32 vblank; | |
15743 | u32 vsync; | |
15744 | } transcoder[4]; | |
c4a1d9e4 CW |
15745 | }; |
15746 | ||
15747 | struct intel_display_error_state * | |
c033666a | 15748 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 15749 | { |
c4a1d9e4 | 15750 | struct intel_display_error_state *error; |
63b66e5b CW |
15751 | int transcoders[] = { |
15752 | TRANSCODER_A, | |
15753 | TRANSCODER_B, | |
15754 | TRANSCODER_C, | |
15755 | TRANSCODER_EDP, | |
15756 | }; | |
c4a1d9e4 CW |
15757 | int i; |
15758 | ||
c033666a | 15759 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
15760 | return NULL; |
15761 | ||
9d1cb914 | 15762 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15763 | if (error == NULL) |
15764 | return NULL; | |
15765 | ||
c033666a | 15766 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
15767 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15768 | ||
055e393f | 15769 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15770 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15771 | __intel_display_power_is_enabled(dev_priv, |
15772 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15773 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15774 | continue; |
15775 | ||
5efb3e28 VS |
15776 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15777 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15778 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15779 | |
15780 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15781 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 15782 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 15783 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15784 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15785 | } | |
c033666a | 15786 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 15787 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 15788 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
15789 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
15790 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15791 | } | |
15792 | ||
c4a1d9e4 | 15793 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15794 | |
c033666a | 15795 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 15796 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15797 | } |
15798 | ||
4d1de975 | 15799 | /* Note: this does not include DSI transcoders. */ |
c033666a | 15800 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 15801 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
15802 | error->num_transcoders++; /* Account for eDP. */ |
15803 | ||
15804 | for (i = 0; i < error->num_transcoders; i++) { | |
15805 | enum transcoder cpu_transcoder = transcoders[i]; | |
15806 | ||
ddf9c536 | 15807 | error->transcoder[i].power_domain_on = |
f458ebbc | 15808 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15809 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15810 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15811 | continue; |
15812 | ||
63b66e5b CW |
15813 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15814 | ||
15815 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15816 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15817 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15818 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15819 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15820 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15821 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15822 | } |
15823 | ||
15824 | return error; | |
15825 | } | |
15826 | ||
edc3d884 MK |
15827 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15828 | ||
c4a1d9e4 | 15829 | void |
edc3d884 | 15830 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15831 | struct intel_display_error_state *error) |
15832 | { | |
5a4c6f1b | 15833 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
15834 | int i; |
15835 | ||
63b66e5b CW |
15836 | if (!error) |
15837 | return; | |
15838 | ||
b7f05d4a | 15839 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 15840 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 15841 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15842 | error->power_well_driver); |
055e393f | 15843 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15844 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 15845 | err_printf(m, " Power: %s\n", |
87ad3212 | 15846 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 15847 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15848 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15849 | |
15850 | err_printf(m, "Plane [%d]:\n", i); | |
15851 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15852 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 15853 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
15854 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15855 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15856 | } |
772c2a51 | 15857 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 15858 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 15859 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
15860 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15861 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15862 | } |
15863 | ||
edc3d884 MK |
15864 | err_printf(m, "Cursor [%d]:\n", i); |
15865 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15866 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15867 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15868 | } |
63b66e5b CW |
15869 | |
15870 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15871 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15872 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15873 | err_printf(m, " Power: %s\n", |
87ad3212 | 15874 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15875 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15876 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15877 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15878 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15879 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15880 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15881 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15882 | } | |
c4a1d9e4 | 15883 | } |
98a2f411 CW |
15884 | |
15885 | #endif |