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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
c37efb99 | 40 | #include "i915_gem_dmabuf.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
5a21b665 DV |
52 | static bool is_mmio_work(struct intel_flip_work *work) |
53 | { | |
54 | return work->mmio_work.func; | |
55 | } | |
56 | ||
465c120c | 57 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 58 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
59 | DRM_FORMAT_C8, |
60 | DRM_FORMAT_RGB565, | |
465c120c | 61 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 62 | DRM_FORMAT_XRGB8888, |
465c120c MR |
63 | }; |
64 | ||
65 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 66 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
70 | DRM_FORMAT_XBGR8888, | |
71 | DRM_FORMAT_XRGB2101010, | |
72 | DRM_FORMAT_XBGR2101010, | |
73 | }; | |
74 | ||
75 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
76 | DRM_FORMAT_C8, |
77 | DRM_FORMAT_RGB565, | |
78 | DRM_FORMAT_XRGB8888, | |
465c120c | 79 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 80 | DRM_FORMAT_ARGB8888, |
465c120c MR |
81 | DRM_FORMAT_ABGR8888, |
82 | DRM_FORMAT_XRGB2101010, | |
465c120c | 83 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
84 | DRM_FORMAT_YUYV, |
85 | DRM_FORMAT_YVYU, | |
86 | DRM_FORMAT_UYVY, | |
87 | DRM_FORMAT_VYUY, | |
465c120c MR |
88 | }; |
89 | ||
3d7d6510 MR |
90 | /* Cursor formats */ |
91 | static const uint32_t intel_cursor_formats[] = { | |
92 | DRM_FORMAT_ARGB8888, | |
93 | }; | |
94 | ||
f1f644dc | 95 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 96 | struct intel_crtc_state *pipe_config); |
18442d08 | 97 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 98 | struct intel_crtc_state *pipe_config); |
f1f644dc | 99 | |
eb1bfe80 JB |
100 | static int intel_framebuffer_init(struct drm_device *dev, |
101 | struct intel_framebuffer *ifb, | |
102 | struct drm_mode_fb_cmd2 *mode_cmd, | |
103 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
104 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
105 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 106 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 107 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
108 | struct intel_link_m_n *m_n, |
109 | struct intel_link_m_n *m2_n2); | |
29407aab | 110 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 111 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 112 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 113 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 114 | const struct intel_crtc_state *pipe_config); |
d288f65f | 115 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 116 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
117 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
118 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
119 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
120 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
121 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
122 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
123 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 124 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 125 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 126 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
324513c0 | 127 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 128 | |
d4906093 | 129 | struct intel_limit { |
4c5def93 ACO |
130 | struct { |
131 | int min, max; | |
132 | } dot, vco, n, m, m1, m2, p, p1; | |
133 | ||
134 | struct { | |
135 | int dot_limit; | |
136 | int p2_slow, p2_fast; | |
137 | } p2; | |
d4906093 | 138 | }; |
79e53945 | 139 | |
bfa7df01 VS |
140 | /* returns HPLL frequency in kHz */ |
141 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
142 | { | |
143 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
144 | ||
145 | /* Obtain SKU information */ | |
146 | mutex_lock(&dev_priv->sb_lock); | |
147 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
148 | CCK_FUSE_HPLL_FREQ_MASK; | |
149 | mutex_unlock(&dev_priv->sb_lock); | |
150 | ||
151 | return vco_freq[hpll_freq] * 1000; | |
152 | } | |
153 | ||
c30fec65 VS |
154 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
155 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
156 | { |
157 | u32 val; | |
158 | int divider; | |
159 | ||
bfa7df01 VS |
160 | mutex_lock(&dev_priv->sb_lock); |
161 | val = vlv_cck_read(dev_priv, reg); | |
162 | mutex_unlock(&dev_priv->sb_lock); | |
163 | ||
164 | divider = val & CCK_FREQUENCY_VALUES; | |
165 | ||
166 | WARN((val & CCK_FREQUENCY_STATUS) != | |
167 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
168 | "%s change in progress\n", name); | |
169 | ||
c30fec65 VS |
170 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
171 | } | |
172 | ||
173 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
174 | const char *name, u32 reg) | |
175 | { | |
176 | if (dev_priv->hpll_freq == 0) | |
177 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
178 | ||
179 | return vlv_get_cck_clock(dev_priv, name, reg, | |
180 | dev_priv->hpll_freq); | |
bfa7df01 VS |
181 | } |
182 | ||
e7dc33f3 VS |
183 | static int |
184 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 185 | { |
e7dc33f3 VS |
186 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
187 | } | |
d2acd215 | 188 | |
e7dc33f3 VS |
189 | static int |
190 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
191 | { | |
19ab4ed3 | 192 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
193 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
194 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
195 | } |
196 | ||
e7dc33f3 VS |
197 | static int |
198 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 199 | { |
79e50a4f JN |
200 | uint32_t clkcfg; |
201 | ||
e7dc33f3 | 202 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
203 | clkcfg = I915_READ(CLKCFG); |
204 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
205 | case CLKCFG_FSB_400: | |
e7dc33f3 | 206 | return 100000; |
79e50a4f | 207 | case CLKCFG_FSB_533: |
e7dc33f3 | 208 | return 133333; |
79e50a4f | 209 | case CLKCFG_FSB_667: |
e7dc33f3 | 210 | return 166667; |
79e50a4f | 211 | case CLKCFG_FSB_800: |
e7dc33f3 | 212 | return 200000; |
79e50a4f | 213 | case CLKCFG_FSB_1067: |
e7dc33f3 | 214 | return 266667; |
79e50a4f | 215 | case CLKCFG_FSB_1333: |
e7dc33f3 | 216 | return 333333; |
79e50a4f JN |
217 | /* these two are just a guess; one of them might be right */ |
218 | case CLKCFG_FSB_1600: | |
219 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 220 | return 400000; |
79e50a4f | 221 | default: |
e7dc33f3 | 222 | return 133333; |
79e50a4f JN |
223 | } |
224 | } | |
225 | ||
19ab4ed3 | 226 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
227 | { |
228 | if (HAS_PCH_SPLIT(dev_priv)) | |
229 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
230 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
231 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
232 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
233 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
234 | else | |
235 | return; /* no rawclk on other platforms, or no need to know it */ | |
236 | ||
237 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
238 | } | |
239 | ||
bfa7df01 VS |
240 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
241 | { | |
666a4537 | 242 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
243 | return; |
244 | ||
245 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
246 | CCK_CZ_CLOCK_CONTROL); | |
247 | ||
248 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
249 | } | |
250 | ||
021357ac | 251 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
252 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
253 | const struct intel_crtc_state *pipe_config) | |
021357ac | 254 | { |
21a727b3 VS |
255 | if (HAS_DDI(dev_priv)) |
256 | return pipe_config->port_clock; /* SPLL */ | |
257 | else if (IS_GEN5(dev_priv)) | |
258 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 259 | else |
21a727b3 | 260 | return 270000; |
021357ac CW |
261 | } |
262 | ||
1b6f4958 | 263 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 264 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 265 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 266 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
267 | .m = { .min = 96, .max = 140 }, |
268 | .m1 = { .min = 18, .max = 26 }, | |
269 | .m2 = { .min = 6, .max = 16 }, | |
270 | .p = { .min = 4, .max = 128 }, | |
271 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
272 | .p2 = { .dot_limit = 165000, |
273 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
274 | }; |
275 | ||
1b6f4958 | 276 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 277 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 278 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 279 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
280 | .m = { .min = 96, .max = 140 }, |
281 | .m1 = { .min = 18, .max = 26 }, | |
282 | .m2 = { .min = 6, .max = 16 }, | |
283 | .p = { .min = 4, .max = 128 }, | |
284 | .p1 = { .min = 2, .max = 33 }, | |
285 | .p2 = { .dot_limit = 165000, | |
286 | .p2_slow = 4, .p2_fast = 4 }, | |
287 | }; | |
288 | ||
1b6f4958 | 289 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 290 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 291 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 292 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
293 | .m = { .min = 96, .max = 140 }, |
294 | .m1 = { .min = 18, .max = 26 }, | |
295 | .m2 = { .min = 6, .max = 16 }, | |
296 | .p = { .min = 4, .max = 128 }, | |
297 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
298 | .p2 = { .dot_limit = 165000, |
299 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 300 | }; |
273e27ca | 301 | |
1b6f4958 | 302 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
303 | .dot = { .min = 20000, .max = 400000 }, |
304 | .vco = { .min = 1400000, .max = 2800000 }, | |
305 | .n = { .min = 1, .max = 6 }, | |
306 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
307 | .m1 = { .min = 8, .max = 18 }, |
308 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
309 | .p = { .min = 5, .max = 80 }, |
310 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
311 | .p2 = { .dot_limit = 200000, |
312 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
313 | }; |
314 | ||
1b6f4958 | 315 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
316 | .dot = { .min = 20000, .max = 400000 }, |
317 | .vco = { .min = 1400000, .max = 2800000 }, | |
318 | .n = { .min = 1, .max = 6 }, | |
319 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
320 | .m1 = { .min = 8, .max = 18 }, |
321 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
322 | .p = { .min = 7, .max = 98 }, |
323 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
324 | .p2 = { .dot_limit = 112000, |
325 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
326 | }; |
327 | ||
273e27ca | 328 | |
1b6f4958 | 329 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
330 | .dot = { .min = 25000, .max = 270000 }, |
331 | .vco = { .min = 1750000, .max = 3500000}, | |
332 | .n = { .min = 1, .max = 4 }, | |
333 | .m = { .min = 104, .max = 138 }, | |
334 | .m1 = { .min = 17, .max = 23 }, | |
335 | .m2 = { .min = 5, .max = 11 }, | |
336 | .p = { .min = 10, .max = 30 }, | |
337 | .p1 = { .min = 1, .max = 3}, | |
338 | .p2 = { .dot_limit = 270000, | |
339 | .p2_slow = 10, | |
340 | .p2_fast = 10 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
1b6f4958 | 344 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
345 | .dot = { .min = 22000, .max = 400000 }, |
346 | .vco = { .min = 1750000, .max = 3500000}, | |
347 | .n = { .min = 1, .max = 4 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 16, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 5, .max = 80 }, | |
352 | .p1 = { .min = 1, .max = 8}, | |
353 | .p2 = { .dot_limit = 165000, | |
354 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
355 | }; |
356 | ||
1b6f4958 | 357 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
358 | .dot = { .min = 20000, .max = 115000 }, |
359 | .vco = { .min = 1750000, .max = 3500000 }, | |
360 | .n = { .min = 1, .max = 3 }, | |
361 | .m = { .min = 104, .max = 138 }, | |
362 | .m1 = { .min = 17, .max = 23 }, | |
363 | .m2 = { .min = 5, .max = 11 }, | |
364 | .p = { .min = 28, .max = 112 }, | |
365 | .p1 = { .min = 2, .max = 8 }, | |
366 | .p2 = { .dot_limit = 0, | |
367 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 368 | }, |
e4b36699 KP |
369 | }; |
370 | ||
1b6f4958 | 371 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
372 | .dot = { .min = 80000, .max = 224000 }, |
373 | .vco = { .min = 1750000, .max = 3500000 }, | |
374 | .n = { .min = 1, .max = 3 }, | |
375 | .m = { .min = 104, .max = 138 }, | |
376 | .m1 = { .min = 17, .max = 23 }, | |
377 | .m2 = { .min = 5, .max = 11 }, | |
378 | .p = { .min = 14, .max = 42 }, | |
379 | .p1 = { .min = 2, .max = 6 }, | |
380 | .p2 = { .dot_limit = 0, | |
381 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 382 | }, |
e4b36699 KP |
383 | }; |
384 | ||
1b6f4958 | 385 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
386 | .dot = { .min = 20000, .max = 400000}, |
387 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 388 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
389 | .n = { .min = 3, .max = 6 }, |
390 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 391 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
392 | .m1 = { .min = 0, .max = 0 }, |
393 | .m2 = { .min = 0, .max = 254 }, | |
394 | .p = { .min = 5, .max = 80 }, | |
395 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
396 | .p2 = { .dot_limit = 200000, |
397 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
398 | }; |
399 | ||
1b6f4958 | 400 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
401 | .dot = { .min = 20000, .max = 400000 }, |
402 | .vco = { .min = 1700000, .max = 3500000 }, | |
403 | .n = { .min = 3, .max = 6 }, | |
404 | .m = { .min = 2, .max = 256 }, | |
405 | .m1 = { .min = 0, .max = 0 }, | |
406 | .m2 = { .min = 0, .max = 254 }, | |
407 | .p = { .min = 7, .max = 112 }, | |
408 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
409 | .p2 = { .dot_limit = 112000, |
410 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
411 | }; |
412 | ||
273e27ca EA |
413 | /* Ironlake / Sandybridge |
414 | * | |
415 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
416 | * the range value for them is (actual_value - 2). | |
417 | */ | |
1b6f4958 | 418 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
419 | .dot = { .min = 25000, .max = 350000 }, |
420 | .vco = { .min = 1760000, .max = 3510000 }, | |
421 | .n = { .min = 1, .max = 5 }, | |
422 | .m = { .min = 79, .max = 127 }, | |
423 | .m1 = { .min = 12, .max = 22 }, | |
424 | .m2 = { .min = 5, .max = 9 }, | |
425 | .p = { .min = 5, .max = 80 }, | |
426 | .p1 = { .min = 1, .max = 8 }, | |
427 | .p2 = { .dot_limit = 225000, | |
428 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
429 | }; |
430 | ||
1b6f4958 | 431 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 3 }, | |
435 | .m = { .min = 79, .max = 118 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
439 | .p1 = { .min = 2, .max = 8 }, | |
440 | .p2 = { .dot_limit = 225000, | |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
1b6f4958 | 444 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 127 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 56 }, | |
452 | .p1 = { .min = 2, .max = 8 }, | |
453 | .p2 = { .dot_limit = 225000, | |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
455 | }; |
456 | ||
273e27ca | 457 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 458 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
459 | .dot = { .min = 25000, .max = 350000 }, |
460 | .vco = { .min = 1760000, .max = 3510000 }, | |
461 | .n = { .min = 1, .max = 2 }, | |
462 | .m = { .min = 79, .max = 126 }, | |
463 | .m1 = { .min = 12, .max = 22 }, | |
464 | .m2 = { .min = 5, .max = 9 }, | |
465 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 466 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
467 | .p2 = { .dot_limit = 225000, |
468 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
469 | }; |
470 | ||
1b6f4958 | 471 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
472 | .dot = { .min = 25000, .max = 350000 }, |
473 | .vco = { .min = 1760000, .max = 3510000 }, | |
474 | .n = { .min = 1, .max = 3 }, | |
475 | .m = { .min = 79, .max = 126 }, | |
476 | .m1 = { .min = 12, .max = 22 }, | |
477 | .m2 = { .min = 5, .max = 9 }, | |
478 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 479 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
480 | .p2 = { .dot_limit = 225000, |
481 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
482 | }; |
483 | ||
1b6f4958 | 484 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
485 | /* |
486 | * These are the data rate limits (measured in fast clocks) | |
487 | * since those are the strictest limits we have. The fast | |
488 | * clock and actual rate limits are more relaxed, so checking | |
489 | * them would make no difference. | |
490 | */ | |
491 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 492 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 493 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
494 | .m1 = { .min = 2, .max = 3 }, |
495 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 496 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 497 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
498 | }; |
499 | ||
1b6f4958 | 500 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
501 | /* |
502 | * These are the data rate limits (measured in fast clocks) | |
503 | * since those are the strictest limits we have. The fast | |
504 | * clock and actual rate limits are more relaxed, so checking | |
505 | * them would make no difference. | |
506 | */ | |
507 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 508 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
509 | .n = { .min = 1, .max = 1 }, |
510 | .m1 = { .min = 2, .max = 2 }, | |
511 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
512 | .p1 = { .min = 2, .max = 4 }, | |
513 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
514 | }; | |
515 | ||
1b6f4958 | 516 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
517 | /* FIXME: find real dot limits */ |
518 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 519 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
520 | .n = { .min = 1, .max = 1 }, |
521 | .m1 = { .min = 2, .max = 2 }, | |
522 | /* FIXME: find real m2 limits */ | |
523 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
524 | .p1 = { .min = 2, .max = 4 }, | |
525 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
526 | }; | |
527 | ||
cdba954e ACO |
528 | static bool |
529 | needs_modeset(struct drm_crtc_state *state) | |
530 | { | |
fc596660 | 531 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
532 | } |
533 | ||
dccbea3b ID |
534 | /* |
535 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
536 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
537 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
538 | * The helpers' return value is the rate of the clock that is fed to the | |
539 | * display engine's pipe which can be the above fast dot clock rate or a | |
540 | * divided-down version of it. | |
541 | */ | |
f2b115e6 | 542 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 543 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 544 | { |
2177832f SL |
545 | clock->m = clock->m2 + 2; |
546 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 547 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 548 | return 0; |
fb03ac01 VS |
549 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
550 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
551 | |
552 | return clock->dot; | |
2177832f SL |
553 | } |
554 | ||
7429e9d4 DV |
555 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
556 | { | |
557 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
558 | } | |
559 | ||
9e2c8475 | 560 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 561 | { |
7429e9d4 | 562 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 563 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 564 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 565 | return 0; |
fb03ac01 VS |
566 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
567 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
568 | |
569 | return clock->dot; | |
79e53945 JB |
570 | } |
571 | ||
9e2c8475 | 572 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
573 | { |
574 | clock->m = clock->m1 * clock->m2; | |
575 | clock->p = clock->p1 * clock->p2; | |
576 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 577 | return 0; |
589eca67 ID |
578 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
579 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
580 | |
581 | return clock->dot / 5; | |
589eca67 ID |
582 | } |
583 | ||
9e2c8475 | 584 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
585 | { |
586 | clock->m = clock->m1 * clock->m2; | |
587 | clock->p = clock->p1 * clock->p2; | |
588 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 589 | return 0; |
ef9348c8 CML |
590 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
591 | clock->n << 22); | |
592 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
593 | |
594 | return clock->dot / 5; | |
ef9348c8 CML |
595 | } |
596 | ||
7c04d1d9 | 597 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
598 | /** |
599 | * Returns whether the given set of divisors are valid for a given refclk with | |
600 | * the given connectors. | |
601 | */ | |
602 | ||
1b894b59 | 603 | static bool intel_PLL_is_valid(struct drm_device *dev, |
1b6f4958 | 604 | const struct intel_limit *limit, |
9e2c8475 | 605 | const struct dpll *clock) |
79e53945 | 606 | { |
f01b7962 VS |
607 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
608 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 609 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 610 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 611 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 612 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 613 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 614 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 615 | |
666a4537 WB |
616 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
617 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
618 | if (clock->m1 <= clock->m2) |
619 | INTELPllInvalid("m1 <= m2\n"); | |
620 | ||
666a4537 | 621 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
622 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
623 | INTELPllInvalid("p out of range\n"); | |
624 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
625 | INTELPllInvalid("m out of range\n"); | |
626 | } | |
627 | ||
79e53945 | 628 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 629 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
630 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
631 | * connector, etc., rather than just a single range. | |
632 | */ | |
633 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 634 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
635 | |
636 | return true; | |
637 | } | |
638 | ||
3b1429d9 | 639 | static int |
1b6f4958 | 640 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
641 | const struct intel_crtc_state *crtc_state, |
642 | int target) | |
79e53945 | 643 | { |
3b1429d9 | 644 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 645 | |
2d84d2b3 | 646 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 647 | /* |
a210b028 DV |
648 | * For LVDS just rely on its current settings for dual-channel. |
649 | * We haven't figured out how to reliably set up different | |
650 | * single/dual channel state, if we even can. | |
79e53945 | 651 | */ |
1974cad0 | 652 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 653 | return limit->p2.p2_fast; |
79e53945 | 654 | else |
3b1429d9 | 655 | return limit->p2.p2_slow; |
79e53945 JB |
656 | } else { |
657 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 658 | return limit->p2.p2_slow; |
79e53945 | 659 | else |
3b1429d9 | 660 | return limit->p2.p2_fast; |
79e53945 | 661 | } |
3b1429d9 VS |
662 | } |
663 | ||
70e8aa21 ACO |
664 | /* |
665 | * Returns a set of divisors for the desired target clock with the given | |
666 | * refclk, or FALSE. The returned values represent the clock equation: | |
667 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
668 | * | |
669 | * Target and reference clocks are specified in kHz. | |
670 | * | |
671 | * If match_clock is provided, then best_clock P divider must match the P | |
672 | * divider from @match_clock used for LVDS downclocking. | |
673 | */ | |
3b1429d9 | 674 | static bool |
1b6f4958 | 675 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 676 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
677 | int target, int refclk, struct dpll *match_clock, |
678 | struct dpll *best_clock) | |
3b1429d9 VS |
679 | { |
680 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 681 | struct dpll clock; |
3b1429d9 | 682 | int err = target; |
79e53945 | 683 | |
0206e353 | 684 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 685 | |
3b1429d9 VS |
686 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
687 | ||
42158660 ZY |
688 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
689 | clock.m1++) { | |
690 | for (clock.m2 = limit->m2.min; | |
691 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 692 | if (clock.m2 >= clock.m1) |
42158660 ZY |
693 | break; |
694 | for (clock.n = limit->n.min; | |
695 | clock.n <= limit->n.max; clock.n++) { | |
696 | for (clock.p1 = limit->p1.min; | |
697 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
698 | int this_err; |
699 | ||
dccbea3b | 700 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
701 | if (!intel_PLL_is_valid(dev, limit, |
702 | &clock)) | |
703 | continue; | |
704 | if (match_clock && | |
705 | clock.p != match_clock->p) | |
706 | continue; | |
707 | ||
708 | this_err = abs(clock.dot - target); | |
709 | if (this_err < err) { | |
710 | *best_clock = clock; | |
711 | err = this_err; | |
712 | } | |
713 | } | |
714 | } | |
715 | } | |
716 | } | |
717 | ||
718 | return (err != target); | |
719 | } | |
720 | ||
70e8aa21 ACO |
721 | /* |
722 | * Returns a set of divisors for the desired target clock with the given | |
723 | * refclk, or FALSE. The returned values represent the clock equation: | |
724 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
725 | * | |
726 | * Target and reference clocks are specified in kHz. | |
727 | * | |
728 | * If match_clock is provided, then best_clock P divider must match the P | |
729 | * divider from @match_clock used for LVDS downclocking. | |
730 | */ | |
ac58c3f0 | 731 | static bool |
1b6f4958 | 732 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 733 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
734 | int target, int refclk, struct dpll *match_clock, |
735 | struct dpll *best_clock) | |
79e53945 | 736 | { |
3b1429d9 | 737 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 738 | struct dpll clock; |
79e53945 JB |
739 | int err = target; |
740 | ||
0206e353 | 741 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 742 | |
3b1429d9 VS |
743 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
744 | ||
42158660 ZY |
745 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
746 | clock.m1++) { | |
747 | for (clock.m2 = limit->m2.min; | |
748 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
749 | for (clock.n = limit->n.min; |
750 | clock.n <= limit->n.max; clock.n++) { | |
751 | for (clock.p1 = limit->p1.min; | |
752 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
753 | int this_err; |
754 | ||
dccbea3b | 755 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
756 | if (!intel_PLL_is_valid(dev, limit, |
757 | &clock)) | |
79e53945 | 758 | continue; |
cec2f356 SP |
759 | if (match_clock && |
760 | clock.p != match_clock->p) | |
761 | continue; | |
79e53945 JB |
762 | |
763 | this_err = abs(clock.dot - target); | |
764 | if (this_err < err) { | |
765 | *best_clock = clock; | |
766 | err = this_err; | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
771 | } | |
772 | ||
773 | return (err != target); | |
774 | } | |
775 | ||
997c030c ACO |
776 | /* |
777 | * Returns a set of divisors for the desired target clock with the given | |
778 | * refclk, or FALSE. The returned values represent the clock equation: | |
779 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
780 | * |
781 | * Target and reference clocks are specified in kHz. | |
782 | * | |
783 | * If match_clock is provided, then best_clock P divider must match the P | |
784 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 785 | */ |
d4906093 | 786 | static bool |
1b6f4958 | 787 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 788 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
789 | int target, int refclk, struct dpll *match_clock, |
790 | struct dpll *best_clock) | |
d4906093 | 791 | { |
3b1429d9 | 792 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 793 | struct dpll clock; |
d4906093 | 794 | int max_n; |
3b1429d9 | 795 | bool found = false; |
6ba770dc AJ |
796 | /* approximately equals target * 0.00585 */ |
797 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
798 | |
799 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
800 | |
801 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
802 | ||
d4906093 | 803 | max_n = limit->n.max; |
f77f13e2 | 804 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 805 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 806 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
807 | for (clock.m1 = limit->m1.max; |
808 | clock.m1 >= limit->m1.min; clock.m1--) { | |
809 | for (clock.m2 = limit->m2.max; | |
810 | clock.m2 >= limit->m2.min; clock.m2--) { | |
811 | for (clock.p1 = limit->p1.max; | |
812 | clock.p1 >= limit->p1.min; clock.p1--) { | |
813 | int this_err; | |
814 | ||
dccbea3b | 815 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
816 | if (!intel_PLL_is_valid(dev, limit, |
817 | &clock)) | |
d4906093 | 818 | continue; |
1b894b59 CW |
819 | |
820 | this_err = abs(clock.dot - target); | |
d4906093 ML |
821 | if (this_err < err_most) { |
822 | *best_clock = clock; | |
823 | err_most = this_err; | |
824 | max_n = clock.n; | |
825 | found = true; | |
826 | } | |
827 | } | |
828 | } | |
829 | } | |
830 | } | |
2c07245f ZW |
831 | return found; |
832 | } | |
833 | ||
d5dd62bd ID |
834 | /* |
835 | * Check if the calculated PLL configuration is more optimal compared to the | |
836 | * best configuration and error found so far. Return the calculated error. | |
837 | */ | |
838 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
839 | const struct dpll *calculated_clock, |
840 | const struct dpll *best_clock, | |
d5dd62bd ID |
841 | unsigned int best_error_ppm, |
842 | unsigned int *error_ppm) | |
843 | { | |
9ca3ba01 ID |
844 | /* |
845 | * For CHV ignore the error and consider only the P value. | |
846 | * Prefer a bigger P value based on HW requirements. | |
847 | */ | |
848 | if (IS_CHERRYVIEW(dev)) { | |
849 | *error_ppm = 0; | |
850 | ||
851 | return calculated_clock->p > best_clock->p; | |
852 | } | |
853 | ||
24be4e46 ID |
854 | if (WARN_ON_ONCE(!target_freq)) |
855 | return false; | |
856 | ||
d5dd62bd ID |
857 | *error_ppm = div_u64(1000000ULL * |
858 | abs(target_freq - calculated_clock->dot), | |
859 | target_freq); | |
860 | /* | |
861 | * Prefer a better P value over a better (smaller) error if the error | |
862 | * is small. Ensure this preference for future configurations too by | |
863 | * setting the error to 0. | |
864 | */ | |
865 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
866 | *error_ppm = 0; | |
867 | ||
868 | return true; | |
869 | } | |
870 | ||
871 | return *error_ppm + 10 < best_error_ppm; | |
872 | } | |
873 | ||
65b3d6a9 ACO |
874 | /* |
875 | * Returns a set of divisors for the desired target clock with the given | |
876 | * refclk, or FALSE. The returned values represent the clock equation: | |
877 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
878 | */ | |
a0c4da24 | 879 | static bool |
1b6f4958 | 880 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 881 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
882 | int target, int refclk, struct dpll *match_clock, |
883 | struct dpll *best_clock) | |
a0c4da24 | 884 | { |
a93e255f | 885 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 886 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 887 | struct dpll clock; |
69e4f900 | 888 | unsigned int bestppm = 1000000; |
27e639bf VS |
889 | /* min update 19.2 MHz */ |
890 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 891 | bool found = false; |
a0c4da24 | 892 | |
6b4bf1c4 VS |
893 | target *= 5; /* fast clock */ |
894 | ||
895 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
896 | |
897 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 898 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 899 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 900 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 901 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 902 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 903 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 904 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 905 | unsigned int ppm; |
69e4f900 | 906 | |
6b4bf1c4 VS |
907 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
908 | refclk * clock.m1); | |
909 | ||
dccbea3b | 910 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 911 | |
f01b7962 VS |
912 | if (!intel_PLL_is_valid(dev, limit, |
913 | &clock)) | |
43b0ac53 VS |
914 | continue; |
915 | ||
d5dd62bd ID |
916 | if (!vlv_PLL_is_optimal(dev, target, |
917 | &clock, | |
918 | best_clock, | |
919 | bestppm, &ppm)) | |
920 | continue; | |
6b4bf1c4 | 921 | |
d5dd62bd ID |
922 | *best_clock = clock; |
923 | bestppm = ppm; | |
924 | found = true; | |
a0c4da24 JB |
925 | } |
926 | } | |
927 | } | |
928 | } | |
a0c4da24 | 929 | |
49e497ef | 930 | return found; |
a0c4da24 | 931 | } |
a4fc5ed6 | 932 | |
65b3d6a9 ACO |
933 | /* |
934 | * Returns a set of divisors for the desired target clock with the given | |
935 | * refclk, or FALSE. The returned values represent the clock equation: | |
936 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
937 | */ | |
ef9348c8 | 938 | static bool |
1b6f4958 | 939 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 940 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
941 | int target, int refclk, struct dpll *match_clock, |
942 | struct dpll *best_clock) | |
ef9348c8 | 943 | { |
a93e255f | 944 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 945 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 946 | unsigned int best_error_ppm; |
9e2c8475 | 947 | struct dpll clock; |
ef9348c8 CML |
948 | uint64_t m2; |
949 | int found = false; | |
950 | ||
951 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 952 | best_error_ppm = 1000000; |
ef9348c8 CML |
953 | |
954 | /* | |
955 | * Based on hardware doc, the n always set to 1, and m1 always | |
956 | * set to 2. If requires to support 200Mhz refclk, we need to | |
957 | * revisit this because n may not 1 anymore. | |
958 | */ | |
959 | clock.n = 1, clock.m1 = 2; | |
960 | target *= 5; /* fast clock */ | |
961 | ||
962 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
963 | for (clock.p2 = limit->p2.p2_fast; | |
964 | clock.p2 >= limit->p2.p2_slow; | |
965 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 966 | unsigned int error_ppm; |
ef9348c8 CML |
967 | |
968 | clock.p = clock.p1 * clock.p2; | |
969 | ||
970 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
971 | clock.n) << 22, refclk * clock.m1); | |
972 | ||
973 | if (m2 > INT_MAX/clock.m1) | |
974 | continue; | |
975 | ||
976 | clock.m2 = m2; | |
977 | ||
dccbea3b | 978 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
979 | |
980 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
981 | continue; | |
982 | ||
9ca3ba01 ID |
983 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
984 | best_error_ppm, &error_ppm)) | |
985 | continue; | |
986 | ||
987 | *best_clock = clock; | |
988 | best_error_ppm = error_ppm; | |
989 | found = true; | |
ef9348c8 CML |
990 | } |
991 | } | |
992 | ||
993 | return found; | |
994 | } | |
995 | ||
5ab7b0b7 | 996 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 997 | struct dpll *best_clock) |
5ab7b0b7 | 998 | { |
65b3d6a9 | 999 | int refclk = 100000; |
1b6f4958 | 1000 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1001 | |
65b3d6a9 | 1002 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1003 | target_clock, refclk, NULL, best_clock); |
1004 | } | |
1005 | ||
20ddf665 VS |
1006 | bool intel_crtc_active(struct drm_crtc *crtc) |
1007 | { | |
1008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1009 | ||
1010 | /* Be paranoid as we can arrive here with only partial | |
1011 | * state retrieved from the hardware during setup. | |
1012 | * | |
241bfc38 | 1013 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1014 | * as Haswell has gained clock readout/fastboot support. |
1015 | * | |
66e514c1 | 1016 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1017 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1018 | * |
1019 | * FIXME: The intel_crtc->active here should be switched to | |
1020 | * crtc->state->active once we have proper CRTC states wired up | |
1021 | * for atomic. | |
20ddf665 | 1022 | */ |
c3d1f436 | 1023 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1024 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1025 | } |
1026 | ||
a5c961d1 PZ |
1027 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1028 | enum pipe pipe) | |
1029 | { | |
1030 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1032 | ||
6e3c9717 | 1033 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1034 | } |
1035 | ||
fbf49ea2 VS |
1036 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1037 | { | |
fac5e23e | 1038 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1039 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1040 | u32 line1, line2; |
1041 | u32 line_mask; | |
1042 | ||
1043 | if (IS_GEN2(dev)) | |
1044 | line_mask = DSL_LINEMASK_GEN2; | |
1045 | else | |
1046 | line_mask = DSL_LINEMASK_GEN3; | |
1047 | ||
1048 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1049 | msleep(5); |
fbf49ea2 VS |
1050 | line2 = I915_READ(reg) & line_mask; |
1051 | ||
1052 | return line1 == line2; | |
1053 | } | |
1054 | ||
ab7ad7f6 KP |
1055 | /* |
1056 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1057 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1058 | * |
1059 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1060 | * spinning on the vblank interrupt status bit, since we won't actually | |
1061 | * see an interrupt when the pipe is disabled. | |
1062 | * | |
ab7ad7f6 KP |
1063 | * On Gen4 and above: |
1064 | * wait for the pipe register state bit to turn off | |
1065 | * | |
1066 | * Otherwise: | |
1067 | * wait for the display line value to settle (it usually | |
1068 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1069 | * |
9d0498a2 | 1070 | */ |
575f7ab7 | 1071 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1072 | { |
575f7ab7 | 1073 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1074 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 1075 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1076 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1077 | |
1078 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1079 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1080 | |
1081 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1082 | if (intel_wait_for_register(dev_priv, |
1083 | reg, I965_PIPECONF_ACTIVE, 0, | |
1084 | 100)) | |
284637d9 | 1085 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1086 | } else { |
ab7ad7f6 | 1087 | /* Wait for the display line to settle */ |
fbf49ea2 | 1088 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1089 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1090 | } |
79e53945 JB |
1091 | } |
1092 | ||
b24e7179 | 1093 | /* Only for pre-ILK configs */ |
55607e8a DV |
1094 | void assert_pll(struct drm_i915_private *dev_priv, |
1095 | enum pipe pipe, bool state) | |
b24e7179 | 1096 | { |
b24e7179 JB |
1097 | u32 val; |
1098 | bool cur_state; | |
1099 | ||
649636ef | 1100 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1101 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1102 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1103 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1104 | onoff(state), onoff(cur_state)); |
b24e7179 | 1105 | } |
b24e7179 | 1106 | |
23538ef1 | 1107 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1108 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1109 | { |
1110 | u32 val; | |
1111 | bool cur_state; | |
1112 | ||
a580516d | 1113 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1114 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1115 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1116 | |
1117 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1118 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1119 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1120 | onoff(state), onoff(cur_state)); |
23538ef1 | 1121 | } |
23538ef1 | 1122 | |
040484af JB |
1123 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1124 | enum pipe pipe, bool state) | |
1125 | { | |
040484af | 1126 | bool cur_state; |
ad80a810 PZ |
1127 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1128 | pipe); | |
040484af | 1129 | |
2d1fe073 | 1130 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1131 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1132 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1133 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1134 | } else { |
649636ef | 1135 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1136 | cur_state = !!(val & FDI_TX_ENABLE); |
1137 | } | |
e2c719b7 | 1138 | I915_STATE_WARN(cur_state != state, |
040484af | 1139 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1140 | onoff(state), onoff(cur_state)); |
040484af JB |
1141 | } |
1142 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1143 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1144 | ||
1145 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1146 | enum pipe pipe, bool state) | |
1147 | { | |
040484af JB |
1148 | u32 val; |
1149 | bool cur_state; | |
1150 | ||
649636ef | 1151 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1152 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1153 | I915_STATE_WARN(cur_state != state, |
040484af | 1154 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1155 | onoff(state), onoff(cur_state)); |
040484af JB |
1156 | } |
1157 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1158 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1159 | ||
1160 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1161 | enum pipe pipe) | |
1162 | { | |
040484af JB |
1163 | u32 val; |
1164 | ||
1165 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1166 | if (IS_GEN5(dev_priv)) |
040484af JB |
1167 | return; |
1168 | ||
bf507ef7 | 1169 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1170 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1171 | return; |
1172 | ||
649636ef | 1173 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1174 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1175 | } |
1176 | ||
55607e8a DV |
1177 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1178 | enum pipe pipe, bool state) | |
040484af | 1179 | { |
040484af | 1180 | u32 val; |
55607e8a | 1181 | bool cur_state; |
040484af | 1182 | |
649636ef | 1183 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1184 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1185 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1186 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1187 | onoff(state), onoff(cur_state)); |
040484af JB |
1188 | } |
1189 | ||
b680c37a DV |
1190 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1191 | enum pipe pipe) | |
ea0760cf | 1192 | { |
91c8a326 | 1193 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 | 1194 | i915_reg_t pp_reg; |
ea0760cf JB |
1195 | u32 val; |
1196 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1197 | bool locked = true; |
ea0760cf | 1198 | |
bedd4dba JN |
1199 | if (WARN_ON(HAS_DDI(dev))) |
1200 | return; | |
1201 | ||
1202 | if (HAS_PCH_SPLIT(dev)) { | |
1203 | u32 port_sel; | |
1204 | ||
44cb734c ID |
1205 | pp_reg = PP_CONTROL(0); |
1206 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1207 | |
1208 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1209 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1210 | panel_pipe = PIPE_B; | |
1211 | /* XXX: else fix for eDP */ | |
666a4537 | 1212 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba | 1213 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1214 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1215 | panel_pipe = pipe; |
ea0760cf | 1216 | } else { |
44cb734c | 1217 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1218 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1219 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1220 | } |
1221 | ||
1222 | val = I915_READ(pp_reg); | |
1223 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1224 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1225 | locked = false; |
1226 | ||
e2c719b7 | 1227 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1228 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1229 | pipe_name(pipe)); |
ea0760cf JB |
1230 | } |
1231 | ||
93ce0ba6 JN |
1232 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1233 | enum pipe pipe, bool state) | |
1234 | { | |
91c8a326 | 1235 | struct drm_device *dev = &dev_priv->drm; |
93ce0ba6 JN |
1236 | bool cur_state; |
1237 | ||
d9d82081 | 1238 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1239 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1240 | else |
5efb3e28 | 1241 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1242 | |
e2c719b7 | 1243 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1244 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1245 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1246 | } |
1247 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1248 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1249 | ||
b840d907 JB |
1250 | void assert_pipe(struct drm_i915_private *dev_priv, |
1251 | enum pipe pipe, bool state) | |
b24e7179 | 1252 | { |
63d7bbe9 | 1253 | bool cur_state; |
702e7a56 PZ |
1254 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1255 | pipe); | |
4feed0eb | 1256 | enum intel_display_power_domain power_domain; |
b24e7179 | 1257 | |
b6b5d049 VS |
1258 | /* if we need the pipe quirk it must be always on */ |
1259 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1260 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1261 | state = true; |
1262 | ||
4feed0eb ID |
1263 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1264 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1265 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1266 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1267 | |
1268 | intel_display_power_put(dev_priv, power_domain); | |
1269 | } else { | |
1270 | cur_state = false; | |
69310161 PZ |
1271 | } |
1272 | ||
e2c719b7 | 1273 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1274 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1275 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1276 | } |
1277 | ||
931872fc CW |
1278 | static void assert_plane(struct drm_i915_private *dev_priv, |
1279 | enum plane plane, bool state) | |
b24e7179 | 1280 | { |
b24e7179 | 1281 | u32 val; |
931872fc | 1282 | bool cur_state; |
b24e7179 | 1283 | |
649636ef | 1284 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1285 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1286 | I915_STATE_WARN(cur_state != state, |
931872fc | 1287 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1288 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1289 | } |
1290 | ||
931872fc CW |
1291 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1292 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1293 | ||
b24e7179 JB |
1294 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe) | |
1296 | { | |
91c8a326 | 1297 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1298 | int i; |
b24e7179 | 1299 | |
653e1026 VS |
1300 | /* Primary planes are fixed to pipes on gen4+ */ |
1301 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1302 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1303 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1304 | "plane %c assertion failure, should be disabled but not\n", |
1305 | plane_name(pipe)); | |
19ec1358 | 1306 | return; |
28c05794 | 1307 | } |
19ec1358 | 1308 | |
b24e7179 | 1309 | /* Need to check both planes against the pipe */ |
055e393f | 1310 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1311 | u32 val = I915_READ(DSPCNTR(i)); |
1312 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1313 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1314 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1315 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1316 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1317 | } |
1318 | } | |
1319 | ||
19332d7a JB |
1320 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1321 | enum pipe pipe) | |
1322 | { | |
91c8a326 | 1323 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1324 | int sprite; |
19332d7a | 1325 | |
7feb8b88 | 1326 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1327 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1328 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1329 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1330 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1331 | sprite, pipe_name(pipe)); | |
1332 | } | |
666a4537 | 1333 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1334 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1335 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1336 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1337 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1338 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1339 | } |
1340 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1341 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1342 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1343 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1344 | plane_name(pipe), pipe_name(pipe)); |
1345 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1346 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1347 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1348 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1349 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1350 | } |
1351 | } | |
1352 | ||
08c71e5e VS |
1353 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1354 | { | |
e2c719b7 | 1355 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1356 | drm_crtc_vblank_put(crtc); |
1357 | } | |
1358 | ||
7abd4b35 ACO |
1359 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1360 | enum pipe pipe) | |
92f2584a | 1361 | { |
92f2584a JB |
1362 | u32 val; |
1363 | bool enabled; | |
1364 | ||
649636ef | 1365 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1366 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1367 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1368 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1369 | pipe_name(pipe)); | |
92f2584a JB |
1370 | } |
1371 | ||
4e634389 KP |
1372 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1373 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1374 | { |
1375 | if ((val & DP_PORT_EN) == 0) | |
1376 | return false; | |
1377 | ||
2d1fe073 | 1378 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1379 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1380 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1381 | return false; | |
2d1fe073 | 1382 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1383 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1384 | return false; | |
f0575e92 KP |
1385 | } else { |
1386 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1387 | return false; | |
1388 | } | |
1389 | return true; | |
1390 | } | |
1391 | ||
1519b995 KP |
1392 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1393 | enum pipe pipe, u32 val) | |
1394 | { | |
dc0fa718 | 1395 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1396 | return false; |
1397 | ||
2d1fe073 | 1398 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1399 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1400 | return false; |
2d1fe073 | 1401 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1402 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1403 | return false; | |
1519b995 | 1404 | } else { |
dc0fa718 | 1405 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1406 | return false; |
1407 | } | |
1408 | return true; | |
1409 | } | |
1410 | ||
1411 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1412 | enum pipe pipe, u32 val) | |
1413 | { | |
1414 | if ((val & LVDS_PORT_EN) == 0) | |
1415 | return false; | |
1416 | ||
2d1fe073 | 1417 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1418 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1419 | return false; | |
1420 | } else { | |
1421 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1422 | return false; | |
1423 | } | |
1424 | return true; | |
1425 | } | |
1426 | ||
1427 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1428 | enum pipe pipe, u32 val) | |
1429 | { | |
1430 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1431 | return false; | |
2d1fe073 | 1432 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1433 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1434 | return false; | |
1435 | } else { | |
1436 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1437 | return false; | |
1438 | } | |
1439 | return true; | |
1440 | } | |
1441 | ||
291906f1 | 1442 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1443 | enum pipe pipe, i915_reg_t reg, |
1444 | u32 port_sel) | |
291906f1 | 1445 | { |
47a05eca | 1446 | u32 val = I915_READ(reg); |
e2c719b7 | 1447 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1448 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1449 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1450 | |
2d1fe073 | 1451 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1452 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1453 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1454 | } |
1455 | ||
1456 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1457 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1458 | { |
47a05eca | 1459 | u32 val = I915_READ(reg); |
e2c719b7 | 1460 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1461 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1462 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1463 | |
2d1fe073 | 1464 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1465 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1466 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1467 | } |
1468 | ||
1469 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1470 | enum pipe pipe) | |
1471 | { | |
291906f1 | 1472 | u32 val; |
291906f1 | 1473 | |
f0575e92 KP |
1474 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1475 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1476 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1477 | |
649636ef | 1478 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1479 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1480 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1481 | pipe_name(pipe)); |
291906f1 | 1482 | |
649636ef | 1483 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1484 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1485 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1486 | pipe_name(pipe)); |
291906f1 | 1487 | |
e2debe91 PZ |
1488 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1490 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1491 | } |
1492 | ||
cd2d34d9 VS |
1493 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1494 | const struct intel_crtc_state *pipe_config) | |
1495 | { | |
1496 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1497 | enum pipe pipe = crtc->pipe; | |
1498 | ||
1499 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1500 | POSTING_READ(DPLL(pipe)); | |
1501 | udelay(150); | |
1502 | ||
2c30b43b CW |
1503 | if (intel_wait_for_register(dev_priv, |
1504 | DPLL(pipe), | |
1505 | DPLL_LOCK_VLV, | |
1506 | DPLL_LOCK_VLV, | |
1507 | 1)) | |
cd2d34d9 VS |
1508 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1509 | } | |
1510 | ||
d288f65f | 1511 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1512 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1513 | { |
cd2d34d9 | 1514 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1515 | enum pipe pipe = crtc->pipe; |
87442f73 | 1516 | |
8bd3f301 | 1517 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1518 | |
87442f73 | 1519 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1520 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1521 | |
cd2d34d9 VS |
1522 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1523 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1524 | |
8bd3f301 VS |
1525 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1526 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1527 | } |
1528 | ||
cd2d34d9 VS |
1529 | |
1530 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1531 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1532 | { |
cd2d34d9 | 1533 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1534 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1535 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1536 | u32 tmp; |
1537 | ||
a580516d | 1538 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1539 | |
1540 | /* Enable back the 10bit clock to display controller */ | |
1541 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1542 | tmp |= DPIO_DCLKP_EN; | |
1543 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1544 | ||
54433e91 VS |
1545 | mutex_unlock(&dev_priv->sb_lock); |
1546 | ||
9d556c99 CML |
1547 | /* |
1548 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1549 | */ | |
1550 | udelay(1); | |
1551 | ||
1552 | /* Enable PLL */ | |
d288f65f | 1553 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1554 | |
1555 | /* Check PLL is locked */ | |
6b18826a CW |
1556 | if (intel_wait_for_register(dev_priv, |
1557 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1558 | 1)) | |
9d556c99 | 1559 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1560 | } |
1561 | ||
1562 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1563 | const struct intel_crtc_state *pipe_config) | |
1564 | { | |
1565 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1566 | enum pipe pipe = crtc->pipe; | |
1567 | ||
1568 | assert_pipe_disabled(dev_priv, pipe); | |
1569 | ||
1570 | /* PLL is protected by panel, make sure we can write it */ | |
1571 | assert_panel_unlocked(dev_priv, pipe); | |
1572 | ||
1573 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1574 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1575 | |
c231775c VS |
1576 | if (pipe != PIPE_A) { |
1577 | /* | |
1578 | * WaPixelRepeatModeFixForC0:chv | |
1579 | * | |
1580 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1581 | * the value from DPLLBMD to either pipe B or C. | |
1582 | */ | |
1583 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1584 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1585 | I915_WRITE(CBR4_VLV, 0); | |
1586 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1587 | ||
1588 | /* | |
1589 | * DPLLB VGA mode also seems to cause problems. | |
1590 | * We should always have it disabled. | |
1591 | */ | |
1592 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1593 | } else { | |
1594 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1595 | POSTING_READ(DPLL_MD(pipe)); | |
1596 | } | |
9d556c99 CML |
1597 | } |
1598 | ||
1c4e0274 VS |
1599 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1600 | { | |
1601 | struct intel_crtc *crtc; | |
1602 | int count = 0; | |
1603 | ||
2d84d2b3 | 1604 | for_each_intel_crtc(dev, crtc) { |
3538b9df | 1605 | count += crtc->base.state->active && |
2d84d2b3 VS |
1606 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1607 | } | |
1c4e0274 VS |
1608 | |
1609 | return count; | |
1610 | } | |
1611 | ||
66e3d5c0 | 1612 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1613 | { |
66e3d5c0 | 1614 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1615 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1616 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1617 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1618 | |
66e3d5c0 | 1619 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1620 | |
63d7bbe9 | 1621 | /* PLL is protected by panel, make sure we can write it */ |
66e3d5c0 DV |
1622 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1623 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1624 | |
1c4e0274 VS |
1625 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1626 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1627 | /* | |
1628 | * It appears to be important that we don't enable this | |
1629 | * for the current pipe before otherwise configuring the | |
1630 | * PLL. No idea how this should be handled if multiple | |
1631 | * DVO outputs are enabled simultaneosly. | |
1632 | */ | |
1633 | dpll |= DPLL_DVO_2X_MODE; | |
1634 | I915_WRITE(DPLL(!crtc->pipe), | |
1635 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1636 | } | |
66e3d5c0 | 1637 | |
c2b63374 VS |
1638 | /* |
1639 | * Apparently we need to have VGA mode enabled prior to changing | |
1640 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1641 | * dividers, even though the register value does change. | |
1642 | */ | |
1643 | I915_WRITE(reg, 0); | |
1644 | ||
8e7a65aa VS |
1645 | I915_WRITE(reg, dpll); |
1646 | ||
66e3d5c0 DV |
1647 | /* Wait for the clocks to stabilize. */ |
1648 | POSTING_READ(reg); | |
1649 | udelay(150); | |
1650 | ||
1651 | if (INTEL_INFO(dev)->gen >= 4) { | |
1652 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1653 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1654 | } else { |
1655 | /* The pixel multiplier can only be updated once the | |
1656 | * DPLL is enabled and the clocks are stable. | |
1657 | * | |
1658 | * So write it again. | |
1659 | */ | |
1660 | I915_WRITE(reg, dpll); | |
1661 | } | |
63d7bbe9 JB |
1662 | |
1663 | /* We do this three times for luck */ | |
66e3d5c0 | 1664 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1665 | POSTING_READ(reg); |
1666 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1667 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1668 | POSTING_READ(reg); |
1669 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1670 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1671 | POSTING_READ(reg); |
1672 | udelay(150); /* wait for warmup */ | |
1673 | } | |
1674 | ||
1675 | /** | |
50b44a44 | 1676 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1677 | * @dev_priv: i915 private structure |
1678 | * @pipe: pipe PLL to disable | |
1679 | * | |
1680 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1681 | * | |
1682 | * Note! This is for pre-ILK only. | |
1683 | */ | |
1c4e0274 | 1684 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1685 | { |
1c4e0274 | 1686 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1687 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c4e0274 VS |
1688 | enum pipe pipe = crtc->pipe; |
1689 | ||
1690 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1691 | if (IS_I830(dev) && | |
2d84d2b3 | 1692 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
3538b9df | 1693 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1694 | I915_WRITE(DPLL(PIPE_B), |
1695 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1696 | I915_WRITE(DPLL(PIPE_A), | |
1697 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1698 | } | |
1699 | ||
b6b5d049 VS |
1700 | /* Don't disable pipe or pipe PLLs if needed */ |
1701 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1702 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1703 | return; |
1704 | ||
1705 | /* Make sure the pipe isn't still relying on us */ | |
1706 | assert_pipe_disabled(dev_priv, pipe); | |
1707 | ||
b8afb911 | 1708 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1709 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1710 | } |
1711 | ||
f6071166 JB |
1712 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1713 | { | |
b8afb911 | 1714 | u32 val; |
f6071166 JB |
1715 | |
1716 | /* Make sure the pipe isn't still relying on us */ | |
1717 | assert_pipe_disabled(dev_priv, pipe); | |
1718 | ||
03ed5cbf VS |
1719 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1720 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1721 | if (pipe != PIPE_A) | |
1722 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1723 | ||
f6071166 JB |
1724 | I915_WRITE(DPLL(pipe), val); |
1725 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1726 | } |
1727 | ||
1728 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1729 | { | |
d752048d | 1730 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1731 | u32 val; |
1732 | ||
a11b0703 VS |
1733 | /* Make sure the pipe isn't still relying on us */ |
1734 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1735 | |
60bfe44f VS |
1736 | val = DPLL_SSC_REF_CLK_CHV | |
1737 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1738 | if (pipe != PIPE_A) |
1739 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1740 | |
a11b0703 VS |
1741 | I915_WRITE(DPLL(pipe), val); |
1742 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1743 | |
a580516d | 1744 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1745 | |
1746 | /* Disable 10bit clock to display controller */ | |
1747 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1748 | val &= ~DPIO_DCLKP_EN; | |
1749 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1750 | ||
a580516d | 1751 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1752 | } |
1753 | ||
e4607fcf | 1754 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1755 | struct intel_digital_port *dport, |
1756 | unsigned int expected_mask) | |
89b667f8 JB |
1757 | { |
1758 | u32 port_mask; | |
f0f59a00 | 1759 | i915_reg_t dpll_reg; |
89b667f8 | 1760 | |
e4607fcf CML |
1761 | switch (dport->port) { |
1762 | case PORT_B: | |
89b667f8 | 1763 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1764 | dpll_reg = DPLL(0); |
e4607fcf CML |
1765 | break; |
1766 | case PORT_C: | |
89b667f8 | 1767 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1768 | dpll_reg = DPLL(0); |
9b6de0a1 | 1769 | expected_mask <<= 4; |
00fc31b7 CML |
1770 | break; |
1771 | case PORT_D: | |
1772 | port_mask = DPLL_PORTD_READY_MASK; | |
1773 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1774 | break; |
1775 | default: | |
1776 | BUG(); | |
1777 | } | |
89b667f8 | 1778 | |
370004d3 CW |
1779 | if (intel_wait_for_register(dev_priv, |
1780 | dpll_reg, port_mask, expected_mask, | |
1781 | 1000)) | |
9b6de0a1 VS |
1782 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1783 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1784 | } |
1785 | ||
b8a4f404 PZ |
1786 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1787 | enum pipe pipe) | |
040484af | 1788 | { |
91c8a326 | 1789 | struct drm_device *dev = &dev_priv->drm; |
7c26e5c6 | 1790 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1792 | i915_reg_t reg; |
1793 | uint32_t val, pipeconf_val; | |
040484af | 1794 | |
040484af | 1795 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1796 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1797 | |
1798 | /* FDI must be feeding us bits for PCH ports */ | |
1799 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1800 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1801 | ||
23670b32 DV |
1802 | if (HAS_PCH_CPT(dev)) { |
1803 | /* Workaround: Set the timing override bit before enabling the | |
1804 | * pch transcoder. */ | |
1805 | reg = TRANS_CHICKEN2(pipe); | |
1806 | val = I915_READ(reg); | |
1807 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1808 | I915_WRITE(reg, val); | |
59c859d6 | 1809 | } |
23670b32 | 1810 | |
ab9412ba | 1811 | reg = PCH_TRANSCONF(pipe); |
040484af | 1812 | val = I915_READ(reg); |
5f7f726d | 1813 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1814 | |
2d1fe073 | 1815 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1816 | /* |
c5de7c6f VS |
1817 | * Make the BPC in transcoder be consistent with |
1818 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1819 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1820 | */ |
dfd07d72 | 1821 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1822 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1823 | val |= PIPECONF_8BPC; |
1824 | else | |
1825 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1826 | } |
5f7f726d PZ |
1827 | |
1828 | val &= ~TRANS_INTERLACE_MASK; | |
1829 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1830 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1831 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1832 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1833 | else | |
1834 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1835 | else |
1836 | val |= TRANS_PROGRESSIVE; | |
1837 | ||
040484af | 1838 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1839 | if (intel_wait_for_register(dev_priv, |
1840 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1841 | 100)) | |
4bb6f1f3 | 1842 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1843 | } |
1844 | ||
8fb033d7 | 1845 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1846 | enum transcoder cpu_transcoder) |
040484af | 1847 | { |
8fb033d7 | 1848 | u32 val, pipeconf_val; |
8fb033d7 | 1849 | |
8fb033d7 | 1850 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1851 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1852 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1853 | |
223a6fdf | 1854 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1855 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1856 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1857 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1858 | |
25f3ef11 | 1859 | val = TRANS_ENABLE; |
937bb610 | 1860 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1861 | |
9a76b1c6 PZ |
1862 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1863 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1864 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1865 | else |
1866 | val |= TRANS_PROGRESSIVE; | |
1867 | ||
ab9412ba | 1868 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1869 | if (intel_wait_for_register(dev_priv, |
1870 | LPT_TRANSCONF, | |
1871 | TRANS_STATE_ENABLE, | |
1872 | TRANS_STATE_ENABLE, | |
1873 | 100)) | |
937bb610 | 1874 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1875 | } |
1876 | ||
b8a4f404 PZ |
1877 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1878 | enum pipe pipe) | |
040484af | 1879 | { |
91c8a326 | 1880 | struct drm_device *dev = &dev_priv->drm; |
f0f59a00 VS |
1881 | i915_reg_t reg; |
1882 | uint32_t val; | |
040484af JB |
1883 | |
1884 | /* FDI relies on the transcoder */ | |
1885 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1886 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1887 | ||
291906f1 JB |
1888 | /* Ports must be off as well */ |
1889 | assert_pch_ports_disabled(dev_priv, pipe); | |
1890 | ||
ab9412ba | 1891 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1892 | val = I915_READ(reg); |
1893 | val &= ~TRANS_ENABLE; | |
1894 | I915_WRITE(reg, val); | |
1895 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1896 | if (intel_wait_for_register(dev_priv, |
1897 | reg, TRANS_STATE_ENABLE, 0, | |
1898 | 50)) | |
4bb6f1f3 | 1899 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1900 | |
c465613b | 1901 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1902 | /* Workaround: Clear the timing override chicken bit again. */ |
1903 | reg = TRANS_CHICKEN2(pipe); | |
1904 | val = I915_READ(reg); | |
1905 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1906 | I915_WRITE(reg, val); | |
1907 | } | |
040484af JB |
1908 | } |
1909 | ||
ab4d966c | 1910 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1911 | { |
8fb033d7 PZ |
1912 | u32 val; |
1913 | ||
ab9412ba | 1914 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1915 | val &= ~TRANS_ENABLE; |
ab9412ba | 1916 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1917 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1918 | if (intel_wait_for_register(dev_priv, |
1919 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1920 | 50)) | |
8a52fd9f | 1921 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1922 | |
1923 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1924 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1925 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1926 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1927 | } |
1928 | ||
b24e7179 | 1929 | /** |
309cfea8 | 1930 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1931 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1932 | * |
0372264a | 1933 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1934 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1935 | */ |
e1fdc473 | 1936 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1937 | { |
0372264a | 1938 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1939 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1940 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1941 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1942 | enum pipe pch_transcoder; |
f0f59a00 | 1943 | i915_reg_t reg; |
b24e7179 JB |
1944 | u32 val; |
1945 | ||
9e2ee2dd VS |
1946 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1947 | ||
58c6eaa2 | 1948 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1949 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1950 | assert_sprites_disabled(dev_priv, pipe); |
1951 | ||
2d1fe073 | 1952 | if (HAS_PCH_LPT(dev_priv)) |
cc391bbb PZ |
1953 | pch_transcoder = TRANSCODER_A; |
1954 | else | |
1955 | pch_transcoder = pipe; | |
1956 | ||
b24e7179 JB |
1957 | /* |
1958 | * A pipe without a PLL won't actually be able to drive bits from | |
1959 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1960 | * need the check. | |
1961 | */ | |
09fa8bb9 | 1962 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1963 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1964 | assert_dsi_pll_enabled(dev_priv); |
1965 | else | |
1966 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1967 | } else { |
6e3c9717 | 1968 | if (crtc->config->has_pch_encoder) { |
040484af | 1969 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1970 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1971 | assert_fdi_tx_pll_enabled(dev_priv, |
1972 | (enum pipe) cpu_transcoder); | |
040484af JB |
1973 | } |
1974 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1975 | } | |
b24e7179 | 1976 | |
702e7a56 | 1977 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1978 | val = I915_READ(reg); |
7ad25d48 | 1979 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1980 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1981 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1982 | return; |
7ad25d48 | 1983 | } |
00d70b15 CW |
1984 | |
1985 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1986 | POSTING_READ(reg); |
b7792d8b VS |
1987 | |
1988 | /* | |
1989 | * Until the pipe starts DSL will read as 0, which would cause | |
1990 | * an apparent vblank timestamp jump, which messes up also the | |
1991 | * frame count when it's derived from the timestamps. So let's | |
1992 | * wait for the pipe to start properly before we call | |
1993 | * drm_crtc_vblank_on() | |
1994 | */ | |
1995 | if (dev->max_vblank_count == 0 && | |
1996 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1997 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1998 | } |
1999 | ||
2000 | /** | |
309cfea8 | 2001 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2002 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2003 | * |
575f7ab7 VS |
2004 | * Disable the pipe of @crtc, making sure that various hardware |
2005 | * specific requirements are met, if applicable, e.g. plane | |
2006 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2007 | * |
2008 | * Will wait until the pipe has shut down before returning. | |
2009 | */ | |
575f7ab7 | 2010 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2011 | { |
fac5e23e | 2012 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 2013 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2014 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2015 | i915_reg_t reg; |
b24e7179 JB |
2016 | u32 val; |
2017 | ||
9e2ee2dd VS |
2018 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2019 | ||
b24e7179 JB |
2020 | /* |
2021 | * Make sure planes won't keep trying to pump pixels to us, | |
2022 | * or we might hang the display. | |
2023 | */ | |
2024 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2025 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2026 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2027 | |
702e7a56 | 2028 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2029 | val = I915_READ(reg); |
00d70b15 CW |
2030 | if ((val & PIPECONF_ENABLE) == 0) |
2031 | return; | |
2032 | ||
67adc644 VS |
2033 | /* |
2034 | * Double wide has implications for planes | |
2035 | * so best keep it disabled when not needed. | |
2036 | */ | |
6e3c9717 | 2037 | if (crtc->config->double_wide) |
67adc644 VS |
2038 | val &= ~PIPECONF_DOUBLE_WIDE; |
2039 | ||
2040 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2041 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2042 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2043 | val &= ~PIPECONF_ENABLE; |
2044 | ||
2045 | I915_WRITE(reg, val); | |
2046 | if ((val & PIPECONF_ENABLE) == 0) | |
2047 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2048 | } |
2049 | ||
832be82f VS |
2050 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2051 | { | |
2052 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2053 | } | |
2054 | ||
27ba3910 VS |
2055 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2056 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2057 | { |
2058 | switch (fb_modifier) { | |
2059 | case DRM_FORMAT_MOD_NONE: | |
2060 | return cpp; | |
2061 | case I915_FORMAT_MOD_X_TILED: | |
2062 | if (IS_GEN2(dev_priv)) | |
2063 | return 128; | |
2064 | else | |
2065 | return 512; | |
2066 | case I915_FORMAT_MOD_Y_TILED: | |
2067 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2068 | return 128; | |
2069 | else | |
2070 | return 512; | |
2071 | case I915_FORMAT_MOD_Yf_TILED: | |
2072 | switch (cpp) { | |
2073 | case 1: | |
2074 | return 64; | |
2075 | case 2: | |
2076 | case 4: | |
2077 | return 128; | |
2078 | case 8: | |
2079 | case 16: | |
2080 | return 256; | |
2081 | default: | |
2082 | MISSING_CASE(cpp); | |
2083 | return cpp; | |
2084 | } | |
2085 | break; | |
2086 | default: | |
2087 | MISSING_CASE(fb_modifier); | |
2088 | return cpp; | |
2089 | } | |
2090 | } | |
2091 | ||
832be82f VS |
2092 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2093 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2094 | { |
832be82f VS |
2095 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2096 | return 1; | |
2097 | else | |
2098 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2099 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2100 | } |
2101 | ||
8d0deca8 VS |
2102 | /* Return the tile dimensions in pixel units */ |
2103 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2104 | unsigned int *tile_width, | |
2105 | unsigned int *tile_height, | |
2106 | uint64_t fb_modifier, | |
2107 | unsigned int cpp) | |
2108 | { | |
2109 | unsigned int tile_width_bytes = | |
2110 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2111 | ||
2112 | *tile_width = tile_width_bytes / cpp; | |
2113 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2114 | } | |
2115 | ||
6761dd31 TU |
2116 | unsigned int |
2117 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2118 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2119 | { |
832be82f VS |
2120 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2121 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2122 | ||
2123 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2124 | } |
2125 | ||
1663b9d6 VS |
2126 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2127 | { | |
2128 | unsigned int size = 0; | |
2129 | int i; | |
2130 | ||
2131 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2132 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2133 | ||
2134 | return size; | |
2135 | } | |
2136 | ||
75c82a53 | 2137 | static void |
3465c580 VS |
2138 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2139 | const struct drm_framebuffer *fb, | |
2140 | unsigned int rotation) | |
f64b98cd | 2141 | { |
2d7a215f VS |
2142 | if (intel_rotation_90_or_270(rotation)) { |
2143 | *view = i915_ggtt_view_rotated; | |
2144 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2145 | } else { | |
2146 | *view = i915_ggtt_view_normal; | |
2147 | } | |
2148 | } | |
50470bb0 | 2149 | |
2d7a215f VS |
2150 | static void |
2151 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2152 | struct drm_framebuffer *fb) | |
2153 | { | |
2154 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2155 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2156 | |
d9b3288e VS |
2157 | tile_size = intel_tile_size(dev_priv); |
2158 | ||
2159 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2160 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2161 | fb->modifier[0], cpp); | |
d9b3288e | 2162 | |
1663b9d6 VS |
2163 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2164 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2165 | |
89e3e142 | 2166 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2167 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2168 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2169 | fb->modifier[1], cpp); | |
d9b3288e | 2170 | |
2d7a215f | 2171 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2172 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2173 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2174 | } |
f64b98cd TU |
2175 | } |
2176 | ||
603525d7 | 2177 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2178 | { |
2179 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2180 | return 256 * 1024; | |
985b8bb4 | 2181 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2182 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2183 | return 128 * 1024; |
2184 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2185 | return 4 * 1024; | |
2186 | else | |
44c5905e | 2187 | return 0; |
4e9a86b6 VS |
2188 | } |
2189 | ||
603525d7 VS |
2190 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2191 | uint64_t fb_modifier) | |
2192 | { | |
2193 | switch (fb_modifier) { | |
2194 | case DRM_FORMAT_MOD_NONE: | |
2195 | return intel_linear_alignment(dev_priv); | |
2196 | case I915_FORMAT_MOD_X_TILED: | |
2197 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2198 | return 256 * 1024; | |
2199 | return 0; | |
2200 | case I915_FORMAT_MOD_Y_TILED: | |
2201 | case I915_FORMAT_MOD_Yf_TILED: | |
2202 | return 1 * 1024 * 1024; | |
2203 | default: | |
2204 | MISSING_CASE(fb_modifier); | |
2205 | return 0; | |
2206 | } | |
2207 | } | |
2208 | ||
127bd2ac | 2209 | int |
3465c580 VS |
2210 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2211 | unsigned int rotation) | |
6b95a207 | 2212 | { |
850c4cdc | 2213 | struct drm_device *dev = fb->dev; |
fac5e23e | 2214 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2215 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2216 | struct i915_ggtt_view view; |
6b95a207 KH |
2217 | u32 alignment; |
2218 | int ret; | |
2219 | ||
ebcdd39e MR |
2220 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2221 | ||
603525d7 | 2222 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2223 | |
3465c580 | 2224 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2225 | |
693db184 CW |
2226 | /* Note that the w/a also requires 64 PTE of padding following the |
2227 | * bo. We currently fill all unused PTE with the shadow page and so | |
2228 | * we should always have valid PTE following the scanout preventing | |
2229 | * the VT-d warning. | |
2230 | */ | |
48f112fe | 2231 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2232 | alignment = 256 * 1024; |
2233 | ||
d6dd6843 PZ |
2234 | /* |
2235 | * Global gtt pte registers are special registers which actually forward | |
2236 | * writes to a chunk of system memory. Which means that there is no risk | |
2237 | * that the register values disappear as soon as we call | |
2238 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2239 | * pin/unpin/fence and not more. | |
2240 | */ | |
2241 | intel_runtime_pm_get(dev_priv); | |
2242 | ||
7580d774 ML |
2243 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2244 | &view); | |
48b956c5 | 2245 | if (ret) |
b26a6b35 | 2246 | goto err_pm; |
6b95a207 KH |
2247 | |
2248 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2249 | * fence, whereas 965+ only requires a fence if using | |
2250 | * framebuffer compression. For simplicity, we always install | |
2251 | * a fence as the cost is not that onerous. | |
2252 | */ | |
9807216f VK |
2253 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2254 | ret = i915_gem_object_get_fence(obj); | |
2255 | if (ret == -EDEADLK) { | |
2256 | /* | |
2257 | * -EDEADLK means there are no free fences | |
2258 | * no pending flips. | |
2259 | * | |
2260 | * This is propagated to atomic, but it uses | |
2261 | * -EDEADLK to force a locking recovery, so | |
2262 | * change the returned error to -EBUSY. | |
2263 | */ | |
2264 | ret = -EBUSY; | |
2265 | goto err_unpin; | |
2266 | } else if (ret) | |
2267 | goto err_unpin; | |
1690e1eb | 2268 | |
9807216f VK |
2269 | i915_gem_object_pin_fence(obj); |
2270 | } | |
6b95a207 | 2271 | |
d6dd6843 | 2272 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2273 | return 0; |
48b956c5 CW |
2274 | |
2275 | err_unpin: | |
f64b98cd | 2276 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2277 | err_pm: |
d6dd6843 | 2278 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2279 | return ret; |
6b95a207 KH |
2280 | } |
2281 | ||
fb4b8ce1 | 2282 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2283 | { |
82bc3b2d | 2284 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2285 | struct i915_ggtt_view view; |
82bc3b2d | 2286 | |
ebcdd39e MR |
2287 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2288 | ||
3465c580 | 2289 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2290 | |
9807216f VK |
2291 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2292 | i915_gem_object_unpin_fence(obj); | |
2293 | ||
f64b98cd | 2294 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2295 | } |
2296 | ||
29cf9491 VS |
2297 | /* |
2298 | * Adjust the tile offset by moving the difference into | |
2299 | * the x/y offsets. | |
2300 | * | |
2301 | * Input tile dimensions and pitch must already be | |
2302 | * rotated to match x and y, and in pixel units. | |
2303 | */ | |
2304 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2305 | unsigned int tile_width, | |
2306 | unsigned int tile_height, | |
2307 | unsigned int tile_size, | |
2308 | unsigned int pitch_tiles, | |
2309 | u32 old_offset, | |
2310 | u32 new_offset) | |
2311 | { | |
2312 | unsigned int tiles; | |
2313 | ||
2314 | WARN_ON(old_offset & (tile_size - 1)); | |
2315 | WARN_ON(new_offset & (tile_size - 1)); | |
2316 | WARN_ON(new_offset > old_offset); | |
2317 | ||
2318 | tiles = (old_offset - new_offset) / tile_size; | |
2319 | ||
2320 | *y += tiles / pitch_tiles * tile_height; | |
2321 | *x += tiles % pitch_tiles * tile_width; | |
2322 | ||
2323 | return new_offset; | |
2324 | } | |
2325 | ||
8d0deca8 VS |
2326 | /* |
2327 | * Computes the linear offset to the base tile and adjusts | |
2328 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2329 | * | |
2330 | * In the 90/270 rotated case, x and y are assumed | |
2331 | * to be already rotated to match the rotated GTT view, and | |
2332 | * pitch is the tile_height aligned framebuffer height. | |
2333 | */ | |
4f2d9934 VS |
2334 | u32 intel_compute_tile_offset(int *x, int *y, |
2335 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2336 | unsigned int pitch, |
2337 | unsigned int rotation) | |
c2c75131 | 2338 | { |
4f2d9934 VS |
2339 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2340 | uint64_t fb_modifier = fb->modifier[plane]; | |
2341 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2342 | u32 offset, offset_aligned, alignment; |
2343 | ||
2344 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2345 | if (alignment) | |
2346 | alignment--; | |
2347 | ||
b5c65338 | 2348 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2349 | unsigned int tile_size, tile_width, tile_height; |
2350 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2351 | |
d843310d | 2352 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2353 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2354 | fb_modifier, cpp); | |
2355 | ||
2356 | if (intel_rotation_90_or_270(rotation)) { | |
2357 | pitch_tiles = pitch / tile_height; | |
2358 | swap(tile_width, tile_height); | |
2359 | } else { | |
2360 | pitch_tiles = pitch / (tile_width * cpp); | |
2361 | } | |
d843310d VS |
2362 | |
2363 | tile_rows = *y / tile_height; | |
2364 | *y %= tile_height; | |
c2c75131 | 2365 | |
8d0deca8 VS |
2366 | tiles = *x / tile_width; |
2367 | *x %= tile_width; | |
bc752862 | 2368 | |
29cf9491 VS |
2369 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2370 | offset_aligned = offset & ~alignment; | |
bc752862 | 2371 | |
29cf9491 VS |
2372 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2373 | tile_size, pitch_tiles, | |
2374 | offset, offset_aligned); | |
2375 | } else { | |
bc752862 | 2376 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2377 | offset_aligned = offset & ~alignment; |
2378 | ||
4e9a86b6 VS |
2379 | *y = (offset & alignment) / pitch; |
2380 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2381 | } |
29cf9491 VS |
2382 | |
2383 | return offset_aligned; | |
c2c75131 DV |
2384 | } |
2385 | ||
b35d63fa | 2386 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2387 | { |
2388 | switch (format) { | |
2389 | case DISPPLANE_8BPP: | |
2390 | return DRM_FORMAT_C8; | |
2391 | case DISPPLANE_BGRX555: | |
2392 | return DRM_FORMAT_XRGB1555; | |
2393 | case DISPPLANE_BGRX565: | |
2394 | return DRM_FORMAT_RGB565; | |
2395 | default: | |
2396 | case DISPPLANE_BGRX888: | |
2397 | return DRM_FORMAT_XRGB8888; | |
2398 | case DISPPLANE_RGBX888: | |
2399 | return DRM_FORMAT_XBGR8888; | |
2400 | case DISPPLANE_BGRX101010: | |
2401 | return DRM_FORMAT_XRGB2101010; | |
2402 | case DISPPLANE_RGBX101010: | |
2403 | return DRM_FORMAT_XBGR2101010; | |
2404 | } | |
2405 | } | |
2406 | ||
bc8d7dff DL |
2407 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2408 | { | |
2409 | switch (format) { | |
2410 | case PLANE_CTL_FORMAT_RGB_565: | |
2411 | return DRM_FORMAT_RGB565; | |
2412 | default: | |
2413 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2414 | if (rgb_order) { | |
2415 | if (alpha) | |
2416 | return DRM_FORMAT_ABGR8888; | |
2417 | else | |
2418 | return DRM_FORMAT_XBGR8888; | |
2419 | } else { | |
2420 | if (alpha) | |
2421 | return DRM_FORMAT_ARGB8888; | |
2422 | else | |
2423 | return DRM_FORMAT_XRGB8888; | |
2424 | } | |
2425 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2426 | if (rgb_order) | |
2427 | return DRM_FORMAT_XBGR2101010; | |
2428 | else | |
2429 | return DRM_FORMAT_XRGB2101010; | |
2430 | } | |
2431 | } | |
2432 | ||
5724dbd1 | 2433 | static bool |
f6936e29 DV |
2434 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2435 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2436 | { |
2437 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2438 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2439 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2440 | struct drm_i915_gem_object *obj = NULL; |
2441 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2442 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2443 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2444 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2445 | PAGE_SIZE); | |
2446 | ||
2447 | size_aligned -= base_aligned; | |
46f297fb | 2448 | |
ff2652ea CW |
2449 | if (plane_config->size == 0) |
2450 | return false; | |
2451 | ||
3badb49f PZ |
2452 | /* If the FB is too big, just don't use it since fbdev is not very |
2453 | * important and we should probably use that space with FBC or other | |
2454 | * features. */ | |
72e96d64 | 2455 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2456 | return false; |
2457 | ||
12c83d99 TU |
2458 | mutex_lock(&dev->struct_mutex); |
2459 | ||
f37b5c2b DV |
2460 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2461 | base_aligned, | |
2462 | base_aligned, | |
2463 | size_aligned); | |
12c83d99 TU |
2464 | if (!obj) { |
2465 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2466 | return false; |
12c83d99 | 2467 | } |
46f297fb | 2468 | |
3e510a8e CW |
2469 | if (plane_config->tiling == I915_TILING_X) |
2470 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2471 | |
6bf129df DL |
2472 | mode_cmd.pixel_format = fb->pixel_format; |
2473 | mode_cmd.width = fb->width; | |
2474 | mode_cmd.height = fb->height; | |
2475 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2476 | mode_cmd.modifier[0] = fb->modifier[0]; |
2477 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2478 | |
6bf129df | 2479 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2480 | &mode_cmd, obj)) { |
46f297fb JB |
2481 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2482 | goto out_unref_obj; | |
2483 | } | |
12c83d99 | 2484 | |
46f297fb | 2485 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2486 | |
f6936e29 | 2487 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2488 | return true; |
46f297fb JB |
2489 | |
2490 | out_unref_obj: | |
f8c417cd | 2491 | i915_gem_object_put(obj); |
46f297fb | 2492 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2493 | return false; |
2494 | } | |
2495 | ||
5a21b665 DV |
2496 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2497 | static void | |
2498 | update_state_fb(struct drm_plane *plane) | |
2499 | { | |
2500 | if (plane->fb == plane->state->fb) | |
2501 | return; | |
2502 | ||
2503 | if (plane->state->fb) | |
2504 | drm_framebuffer_unreference(plane->state->fb); | |
2505 | plane->state->fb = plane->fb; | |
2506 | if (plane->state->fb) | |
2507 | drm_framebuffer_reference(plane->state->fb); | |
2508 | } | |
2509 | ||
5724dbd1 | 2510 | static void |
f6936e29 DV |
2511 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2512 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2513 | { |
2514 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2515 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd JB |
2516 | struct drm_crtc *c; |
2517 | struct intel_crtc *i; | |
2ff8fde1 | 2518 | struct drm_i915_gem_object *obj; |
88595ac9 | 2519 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2520 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2521 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2522 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2523 | struct intel_plane_state *intel_state = |
2524 | to_intel_plane_state(plane_state); | |
88595ac9 | 2525 | struct drm_framebuffer *fb; |
484b41dd | 2526 | |
2d14030b | 2527 | if (!plane_config->fb) |
484b41dd JB |
2528 | return; |
2529 | ||
f6936e29 | 2530 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2531 | fb = &plane_config->fb->base; |
2532 | goto valid_fb; | |
f55548b5 | 2533 | } |
484b41dd | 2534 | |
2d14030b | 2535 | kfree(plane_config->fb); |
484b41dd JB |
2536 | |
2537 | /* | |
2538 | * Failed to alloc the obj, check to see if we should share | |
2539 | * an fb with another CRTC instead | |
2540 | */ | |
70e1e0ec | 2541 | for_each_crtc(dev, c) { |
484b41dd JB |
2542 | i = to_intel_crtc(c); |
2543 | ||
2544 | if (c == &intel_crtc->base) | |
2545 | continue; | |
2546 | ||
2ff8fde1 MR |
2547 | if (!i->active) |
2548 | continue; | |
2549 | ||
88595ac9 DV |
2550 | fb = c->primary->fb; |
2551 | if (!fb) | |
484b41dd JB |
2552 | continue; |
2553 | ||
88595ac9 | 2554 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2555 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2556 | drm_framebuffer_reference(fb); |
2557 | goto valid_fb; | |
484b41dd JB |
2558 | } |
2559 | } | |
88595ac9 | 2560 | |
200757f5 MR |
2561 | /* |
2562 | * We've failed to reconstruct the BIOS FB. Current display state | |
2563 | * indicates that the primary plane is visible, but has a NULL FB, | |
2564 | * which will lead to problems later if we don't fix it up. The | |
2565 | * simplest solution is to just disable the primary plane now and | |
2566 | * pretend the BIOS never had it enabled. | |
2567 | */ | |
2568 | to_intel_plane_state(plane_state)->visible = false; | |
2569 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2570 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2571 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2572 | ||
88595ac9 DV |
2573 | return; |
2574 | ||
2575 | valid_fb: | |
f44e2659 VS |
2576 | plane_state->src_x = 0; |
2577 | plane_state->src_y = 0; | |
be5651f2 ML |
2578 | plane_state->src_w = fb->width << 16; |
2579 | plane_state->src_h = fb->height << 16; | |
2580 | ||
f44e2659 VS |
2581 | plane_state->crtc_x = 0; |
2582 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2583 | plane_state->crtc_w = fb->width; |
2584 | plane_state->crtc_h = fb->height; | |
2585 | ||
0a8d8a86 MR |
2586 | intel_state->src.x1 = plane_state->src_x; |
2587 | intel_state->src.y1 = plane_state->src_y; | |
2588 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2589 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2590 | intel_state->dst.x1 = plane_state->crtc_x; | |
2591 | intel_state->dst.y1 = plane_state->crtc_y; | |
2592 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2593 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2594 | ||
88595ac9 | 2595 | obj = intel_fb_obj(fb); |
3e510a8e | 2596 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2597 | dev_priv->preserve_bios_swizzle = true; |
2598 | ||
be5651f2 ML |
2599 | drm_framebuffer_reference(fb); |
2600 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2601 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2602 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
faf5bf0a CW |
2603 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2604 | &obj->frontbuffer_bits); | |
46f297fb JB |
2605 | } |
2606 | ||
a8d201af ML |
2607 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2608 | const struct intel_crtc_state *crtc_state, | |
2609 | const struct intel_plane_state *plane_state) | |
81255565 | 2610 | { |
a8d201af | 2611 | struct drm_device *dev = primary->dev; |
fac5e23e | 2612 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2613 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2614 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2615 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2616 | int plane = intel_crtc->plane; |
54ea9da8 | 2617 | u32 linear_offset; |
81255565 | 2618 | u32 dspcntr; |
f0f59a00 | 2619 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2620 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2621 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2622 | int x = plane_state->src.x1 >> 16; |
2623 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2624 | |
f45651ba VS |
2625 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2626 | ||
fdd508a6 | 2627 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2628 | |
2629 | if (INTEL_INFO(dev)->gen < 4) { | |
2630 | if (intel_crtc->pipe == PIPE_B) | |
2631 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2632 | ||
2633 | /* pipesrc and dspsize control the size that is scaled from, | |
2634 | * which should always be the user's requested size. | |
2635 | */ | |
2636 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2637 | ((crtc_state->pipe_src_h - 1) << 16) | |
2638 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2639 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2640 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2641 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2642 | ((crtc_state->pipe_src_h - 1) << 16) | |
2643 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2644 | I915_WRITE(PRIMPOS(plane), 0); |
2645 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2646 | } |
81255565 | 2647 | |
57779d06 VS |
2648 | switch (fb->pixel_format) { |
2649 | case DRM_FORMAT_C8: | |
81255565 JB |
2650 | dspcntr |= DISPPLANE_8BPP; |
2651 | break; | |
57779d06 | 2652 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2653 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2654 | break; |
57779d06 VS |
2655 | case DRM_FORMAT_RGB565: |
2656 | dspcntr |= DISPPLANE_BGRX565; | |
2657 | break; | |
2658 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2659 | dspcntr |= DISPPLANE_BGRX888; |
2660 | break; | |
2661 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2662 | dspcntr |= DISPPLANE_RGBX888; |
2663 | break; | |
2664 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2665 | dspcntr |= DISPPLANE_BGRX101010; |
2666 | break; | |
2667 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2668 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2669 | break; |
2670 | default: | |
baba133a | 2671 | BUG(); |
81255565 | 2672 | } |
57779d06 | 2673 | |
3e510a8e | 2674 | if (INTEL_INFO(dev)->gen >= 4 && i915_gem_object_is_tiled(obj)) |
f45651ba | 2675 | dspcntr |= DISPPLANE_TILED; |
81255565 | 2676 | |
de1aa629 VS |
2677 | if (IS_G4X(dev)) |
2678 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2679 | ||
ac484963 | 2680 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2681 | |
c2c75131 DV |
2682 | if (INTEL_INFO(dev)->gen >= 4) { |
2683 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2684 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2685 | fb->pitches[0], rotation); |
c2c75131 DV |
2686 | linear_offset -= intel_crtc->dspaddr_offset; |
2687 | } else { | |
e506a0c6 | 2688 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2689 | } |
e506a0c6 | 2690 | |
8d0deca8 | 2691 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2692 | dspcntr |= DISPPLANE_ROTATE_180; |
2693 | ||
a8d201af ML |
2694 | x += (crtc_state->pipe_src_w - 1); |
2695 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2696 | |
2697 | /* Finding the last pixel of the last line of the display | |
2698 | data and adding to linear_offset*/ | |
2699 | linear_offset += | |
a8d201af | 2700 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2701 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2702 | } |
2703 | ||
2db3366b PZ |
2704 | intel_crtc->adjusted_x = x; |
2705 | intel_crtc->adjusted_y = y; | |
2706 | ||
48404c1e SJ |
2707 | I915_WRITE(reg, dspcntr); |
2708 | ||
01f2c773 | 2709 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2710 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2711 | I915_WRITE(DSPSURF(plane), |
2712 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2713 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2714 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2715 | } else |
f343c5f6 | 2716 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2717 | POSTING_READ(reg); |
17638cd6 JB |
2718 | } |
2719 | ||
a8d201af ML |
2720 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2721 | struct drm_crtc *crtc) | |
17638cd6 JB |
2722 | { |
2723 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 2724 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 2725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 2726 | int plane = intel_crtc->plane; |
f45651ba | 2727 | |
a8d201af ML |
2728 | I915_WRITE(DSPCNTR(plane), 0); |
2729 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2730 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2731 | else |
2732 | I915_WRITE(DSPADDR(plane), 0); | |
2733 | POSTING_READ(DSPCNTR(plane)); | |
2734 | } | |
c9ba6fad | 2735 | |
a8d201af ML |
2736 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2737 | const struct intel_crtc_state *crtc_state, | |
2738 | const struct intel_plane_state *plane_state) | |
2739 | { | |
2740 | struct drm_device *dev = primary->dev; | |
fac5e23e | 2741 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2743 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2744 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2745 | int plane = intel_crtc->plane; | |
54ea9da8 | 2746 | u32 linear_offset; |
a8d201af ML |
2747 | u32 dspcntr; |
2748 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2749 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2750 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2751 | int x = plane_state->src.x1 >> 16; |
2752 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2753 | |
f45651ba | 2754 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2755 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2756 | |
2757 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2758 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2759 | |
57779d06 VS |
2760 | switch (fb->pixel_format) { |
2761 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2762 | dspcntr |= DISPPLANE_8BPP; |
2763 | break; | |
57779d06 VS |
2764 | case DRM_FORMAT_RGB565: |
2765 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2766 | break; |
57779d06 | 2767 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2768 | dspcntr |= DISPPLANE_BGRX888; |
2769 | break; | |
2770 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2771 | dspcntr |= DISPPLANE_RGBX888; |
2772 | break; | |
2773 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2774 | dspcntr |= DISPPLANE_BGRX101010; |
2775 | break; | |
2776 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2777 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2778 | break; |
2779 | default: | |
baba133a | 2780 | BUG(); |
17638cd6 JB |
2781 | } |
2782 | ||
3e510a8e | 2783 | if (i915_gem_object_is_tiled(obj)) |
17638cd6 | 2784 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 2785 | |
f45651ba | 2786 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2787 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2788 | |
ac484963 | 2789 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2790 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2791 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2792 | fb->pitches[0], rotation); |
c2c75131 | 2793 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2794 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2795 | dspcntr |= DISPPLANE_ROTATE_180; |
2796 | ||
2797 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2798 | x += (crtc_state->pipe_src_w - 1); |
2799 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2800 | |
2801 | /* Finding the last pixel of the last line of the display | |
2802 | data and adding to linear_offset*/ | |
2803 | linear_offset += | |
a8d201af | 2804 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2805 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2806 | } |
2807 | } | |
2808 | ||
2db3366b PZ |
2809 | intel_crtc->adjusted_x = x; |
2810 | intel_crtc->adjusted_y = y; | |
2811 | ||
48404c1e | 2812 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2813 | |
01f2c773 | 2814 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2815 | I915_WRITE(DSPSURF(plane), |
2816 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2817 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2818 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2819 | } else { | |
2820 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2821 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2822 | } | |
17638cd6 | 2823 | POSTING_READ(reg); |
17638cd6 JB |
2824 | } |
2825 | ||
7b49f948 VS |
2826 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2827 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2828 | { |
7b49f948 | 2829 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2830 | return 64; |
7b49f948 VS |
2831 | } else { |
2832 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2833 | ||
27ba3910 | 2834 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2835 | } |
2836 | } | |
2837 | ||
44eb0cb9 MK |
2838 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2839 | struct drm_i915_gem_object *obj, | |
2840 | unsigned int plane) | |
121920fa | 2841 | { |
ce7f1728 | 2842 | struct i915_ggtt_view view; |
dedf278c | 2843 | struct i915_vma *vma; |
44eb0cb9 | 2844 | u64 offset; |
121920fa | 2845 | |
e7941294 | 2846 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 2847 | intel_plane->base.state->rotation); |
121920fa | 2848 | |
ce7f1728 | 2849 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2850 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2851 | view.type)) |
dedf278c TU |
2852 | return -1; |
2853 | ||
44eb0cb9 | 2854 | offset = vma->node.start; |
dedf278c TU |
2855 | |
2856 | if (plane == 1) { | |
7723f47d | 2857 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2858 | PAGE_SIZE; |
2859 | } | |
2860 | ||
44eb0cb9 MK |
2861 | WARN_ON(upper_32_bits(offset)); |
2862 | ||
2863 | return lower_32_bits(offset); | |
121920fa TU |
2864 | } |
2865 | ||
e435d6e5 ML |
2866 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2867 | { | |
2868 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2869 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
2870 | |
2871 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2872 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2873 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2874 | } |
2875 | ||
a1b2278e CK |
2876 | /* |
2877 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2878 | */ | |
0583236e | 2879 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2880 | { |
a1b2278e CK |
2881 | struct intel_crtc_scaler_state *scaler_state; |
2882 | int i; | |
2883 | ||
a1b2278e CK |
2884 | scaler_state = &intel_crtc->config->scaler_state; |
2885 | ||
2886 | /* loop through and disable scalers that aren't in use */ | |
2887 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2888 | if (!scaler_state->scalers[i].in_use) |
2889 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2890 | } |
2891 | } | |
2892 | ||
6156a456 | 2893 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2894 | { |
6156a456 | 2895 | switch (pixel_format) { |
d161cf7a | 2896 | case DRM_FORMAT_C8: |
c34ce3d1 | 2897 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2898 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2899 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2900 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2901 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2902 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2903 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2904 | /* |
2905 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2906 | * to be already pre-multiplied. We need to add a knob (or a different | |
2907 | * DRM_FORMAT) for user-space to configure that. | |
2908 | */ | |
f75fb42a | 2909 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2910 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2911 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2912 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2913 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2914 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2915 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2916 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2917 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2918 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2919 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2920 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2921 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2922 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2923 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2924 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2925 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2926 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2927 | default: |
4249eeef | 2928 | MISSING_CASE(pixel_format); |
70d21f0e | 2929 | } |
8cfcba41 | 2930 | |
c34ce3d1 | 2931 | return 0; |
6156a456 | 2932 | } |
70d21f0e | 2933 | |
6156a456 CK |
2934 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2935 | { | |
6156a456 | 2936 | switch (fb_modifier) { |
30af77c4 | 2937 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2938 | break; |
30af77c4 | 2939 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2940 | return PLANE_CTL_TILED_X; |
b321803d | 2941 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2942 | return PLANE_CTL_TILED_Y; |
b321803d | 2943 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2944 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2945 | default: |
6156a456 | 2946 | MISSING_CASE(fb_modifier); |
70d21f0e | 2947 | } |
8cfcba41 | 2948 | |
c34ce3d1 | 2949 | return 0; |
6156a456 | 2950 | } |
70d21f0e | 2951 | |
6156a456 CK |
2952 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2953 | { | |
3b7a5119 | 2954 | switch (rotation) { |
6156a456 CK |
2955 | case BIT(DRM_ROTATE_0): |
2956 | break; | |
1e8df167 SJ |
2957 | /* |
2958 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
2959 | * while i915 HW rotation is clockwise, thats why this swapping. | |
2960 | */ | |
3b7a5119 | 2961 | case BIT(DRM_ROTATE_90): |
1e8df167 | 2962 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 2963 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 2964 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 2965 | case BIT(DRM_ROTATE_270): |
1e8df167 | 2966 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
2967 | default: |
2968 | MISSING_CASE(rotation); | |
2969 | } | |
2970 | ||
c34ce3d1 | 2971 | return 0; |
6156a456 CK |
2972 | } |
2973 | ||
a8d201af ML |
2974 | static void skylake_update_primary_plane(struct drm_plane *plane, |
2975 | const struct intel_crtc_state *crtc_state, | |
2976 | const struct intel_plane_state *plane_state) | |
6156a456 | 2977 | { |
a8d201af | 2978 | struct drm_device *dev = plane->dev; |
fac5e23e | 2979 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
2980 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2981 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2982 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
2983 | int pipe = intel_crtc->pipe; |
2984 | u32 plane_ctl, stride_div, stride; | |
2985 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 2986 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 2987 | int x_offset, y_offset; |
44eb0cb9 | 2988 | u32 surf_addr; |
a8d201af ML |
2989 | int scaler_id = plane_state->scaler_id; |
2990 | int src_x = plane_state->src.x1 >> 16; | |
2991 | int src_y = plane_state->src.y1 >> 16; | |
2992 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
2993 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
2994 | int dst_x = plane_state->dst.x1; | |
2995 | int dst_y = plane_state->dst.y1; | |
2996 | int dst_w = drm_rect_width(&plane_state->dst); | |
2997 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 2998 | |
6156a456 CK |
2999 | plane_ctl = PLANE_CTL_ENABLE | |
3000 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3001 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3002 | ||
3003 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3004 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3005 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3006 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3007 | ||
7b49f948 | 3008 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3009 | fb->pixel_format); |
dedf278c | 3010 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3011 | |
a42e5a23 PZ |
3012 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3013 | ||
3b7a5119 | 3014 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3015 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3016 | ||
3b7a5119 | 3017 | /* stride = Surface height in tiles */ |
832be82f | 3018 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3019 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3020 | x_offset = stride * tile_height - src_y - src_h; |
3021 | y_offset = src_x; | |
6156a456 | 3022 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3023 | } else { |
3024 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3025 | x_offset = src_x; |
3026 | y_offset = src_y; | |
6156a456 | 3027 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3028 | } |
3029 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3030 | |
2db3366b PZ |
3031 | intel_crtc->adjusted_x = x_offset; |
3032 | intel_crtc->adjusted_y = y_offset; | |
3033 | ||
70d21f0e | 3034 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3035 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3036 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3037 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3038 | |
3039 | if (scaler_id >= 0) { | |
3040 | uint32_t ps_ctrl = 0; | |
3041 | ||
3042 | WARN_ON(!dst_w || !dst_h); | |
3043 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3044 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3045 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3046 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3047 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3048 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3049 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3050 | } else { | |
3051 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3052 | } | |
3053 | ||
121920fa | 3054 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3055 | |
3056 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3057 | } | |
3058 | ||
a8d201af ML |
3059 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3060 | struct drm_crtc *crtc) | |
17638cd6 JB |
3061 | { |
3062 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3063 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af | 3064 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3065 | |
a8d201af ML |
3066 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3067 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3068 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3069 | } | |
29b9bde6 | 3070 | |
a8d201af ML |
3071 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3072 | static int | |
3073 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3074 | int x, int y, enum mode_set_atomic state) | |
3075 | { | |
3076 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3077 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3078 | ||
3079 | return -ENODEV; | |
81255565 JB |
3080 | } |
3081 | ||
5a21b665 DV |
3082 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3083 | { | |
3084 | struct intel_crtc *crtc; | |
3085 | ||
91c8a326 | 3086 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3087 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3088 | } | |
3089 | ||
7514747d VS |
3090 | static void intel_update_primary_planes(struct drm_device *dev) |
3091 | { | |
7514747d | 3092 | struct drm_crtc *crtc; |
96a02917 | 3093 | |
70e1e0ec | 3094 | for_each_crtc(dev, crtc) { |
11c22da6 | 3095 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3096 | struct intel_plane_state *plane_state = |
3097 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3098 | |
a8d201af ML |
3099 | if (plane_state->visible) |
3100 | plane->update_plane(&plane->base, | |
3101 | to_intel_crtc_state(crtc->state), | |
3102 | plane_state); | |
73974893 ML |
3103 | } |
3104 | } | |
3105 | ||
3106 | static int | |
3107 | __intel_display_resume(struct drm_device *dev, | |
3108 | struct drm_atomic_state *state) | |
3109 | { | |
3110 | struct drm_crtc_state *crtc_state; | |
3111 | struct drm_crtc *crtc; | |
3112 | int i, ret; | |
11c22da6 | 3113 | |
73974893 ML |
3114 | intel_modeset_setup_hw_state(dev); |
3115 | i915_redisable_vga(dev); | |
3116 | ||
3117 | if (!state) | |
3118 | return 0; | |
3119 | ||
3120 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3121 | /* | |
3122 | * Force recalculation even if we restore | |
3123 | * current state. With fast modeset this may not result | |
3124 | * in a modeset when the state is compatible. | |
3125 | */ | |
3126 | crtc_state->mode_changed = true; | |
96a02917 | 3127 | } |
73974893 ML |
3128 | |
3129 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
3130 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
3131 | ||
3132 | ret = drm_atomic_commit(state); | |
3133 | ||
3134 | WARN_ON(ret == -EDEADLK); | |
3135 | return ret; | |
96a02917 VS |
3136 | } |
3137 | ||
4ac2ba2f VS |
3138 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3139 | { | |
ae98104b VS |
3140 | return intel_has_gpu_reset(dev_priv) && |
3141 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3142 | } |
3143 | ||
c033666a | 3144 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3145 | { |
73974893 ML |
3146 | struct drm_device *dev = &dev_priv->drm; |
3147 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3148 | struct drm_atomic_state *state; | |
3149 | int ret; | |
3150 | ||
73974893 ML |
3151 | /* |
3152 | * Need mode_config.mutex so that we don't | |
3153 | * trample ongoing ->detect() and whatnot. | |
3154 | */ | |
3155 | mutex_lock(&dev->mode_config.mutex); | |
3156 | drm_modeset_acquire_init(ctx, 0); | |
3157 | while (1) { | |
3158 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3159 | if (ret != -EDEADLK) | |
3160 | break; | |
3161 | ||
3162 | drm_modeset_backoff(ctx); | |
3163 | } | |
3164 | ||
3165 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3166 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3167 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3168 | return; |
3169 | ||
f98ce92f VS |
3170 | /* |
3171 | * Disabling the crtcs gracefully seems nicer. Also the | |
3172 | * g33 docs say we should at least disable all the planes. | |
3173 | */ | |
73974893 ML |
3174 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3175 | if (IS_ERR(state)) { | |
3176 | ret = PTR_ERR(state); | |
3177 | state = NULL; | |
3178 | DRM_ERROR("Duplicating state failed with %i\n", ret); | |
3179 | goto err; | |
3180 | } | |
3181 | ||
3182 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3183 | if (ret) { | |
3184 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
3185 | goto err; | |
3186 | } | |
3187 | ||
3188 | dev_priv->modeset_restore_state = state; | |
3189 | state->acquire_ctx = ctx; | |
3190 | return; | |
3191 | ||
3192 | err: | |
3193 | drm_atomic_state_free(state); | |
7514747d VS |
3194 | } |
3195 | ||
c033666a | 3196 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3197 | { |
73974893 ML |
3198 | struct drm_device *dev = &dev_priv->drm; |
3199 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3200 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3201 | int ret; | |
3202 | ||
5a21b665 DV |
3203 | /* |
3204 | * Flips in the rings will be nuked by the reset, | |
3205 | * so complete all pending flips so that user space | |
3206 | * will get its events and not get stuck. | |
3207 | */ | |
3208 | intel_complete_page_flips(dev_priv); | |
3209 | ||
73974893 ML |
3210 | dev_priv->modeset_restore_state = NULL; |
3211 | ||
7514747d | 3212 | /* reset doesn't touch the display */ |
4ac2ba2f | 3213 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3214 | if (!state) { |
3215 | /* | |
3216 | * Flips in the rings have been nuked by the reset, | |
3217 | * so update the base address of all primary | |
3218 | * planes to the the last fb to make sure we're | |
3219 | * showing the correct fb after a reset. | |
3220 | * | |
3221 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3222 | * CS-based flips (which might get lost in gpu resets) any more. | |
3223 | */ | |
3224 | intel_update_primary_planes(dev); | |
3225 | } else { | |
3226 | ret = __intel_display_resume(dev, state); | |
3227 | if (ret) | |
3228 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3229 | } | |
73974893 ML |
3230 | } else { |
3231 | /* | |
3232 | * The display has been reset as well, | |
3233 | * so need a full re-initialization. | |
3234 | */ | |
3235 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3236 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3237 | |
73974893 | 3238 | intel_modeset_init_hw(dev); |
7514747d | 3239 | |
73974893 ML |
3240 | spin_lock_irq(&dev_priv->irq_lock); |
3241 | if (dev_priv->display.hpd_irq_setup) | |
3242 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3243 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3244 | |
73974893 ML |
3245 | ret = __intel_display_resume(dev, state); |
3246 | if (ret) | |
3247 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3248 | |
73974893 ML |
3249 | intel_hpd_init(dev_priv); |
3250 | } | |
7514747d | 3251 | |
73974893 ML |
3252 | drm_modeset_drop_locks(ctx); |
3253 | drm_modeset_acquire_fini(ctx); | |
3254 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3255 | } |
3256 | ||
7d5e3799 CW |
3257 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3258 | { | |
5a21b665 DV |
3259 | struct drm_device *dev = crtc->dev; |
3260 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3261 | unsigned reset_counter; | |
3262 | bool pending; | |
3263 | ||
3264 | reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error); | |
3265 | if (intel_crtc->reset_counter != reset_counter) | |
3266 | return false; | |
3267 | ||
3268 | spin_lock_irq(&dev->event_lock); | |
3269 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3270 | spin_unlock_irq(&dev->event_lock); | |
3271 | ||
3272 | return pending; | |
7d5e3799 CW |
3273 | } |
3274 | ||
bfd16b2a ML |
3275 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3276 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3277 | { |
3278 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 3279 | struct drm_i915_private *dev_priv = to_i915(dev); |
bfd16b2a ML |
3280 | struct intel_crtc_state *pipe_config = |
3281 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3282 | |
bfd16b2a ML |
3283 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3284 | crtc->base.mode = crtc->base.state->mode; | |
3285 | ||
3286 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3287 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3288 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3289 | |
3290 | /* | |
3291 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3292 | * that in compute_mode_changes we check the native mode (not the pfit | |
3293 | * mode) to see if we can flip rather than do a full mode set. In the | |
3294 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3295 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3296 | * sized surface. | |
e30e8f75 GP |
3297 | */ |
3298 | ||
e30e8f75 | 3299 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3300 | ((pipe_config->pipe_src_w - 1) << 16) | |
3301 | (pipe_config->pipe_src_h - 1)); | |
3302 | ||
3303 | /* on skylake this is done by detaching scalers */ | |
3304 | if (INTEL_INFO(dev)->gen >= 9) { | |
3305 | skl_detach_scalers(crtc); | |
3306 | ||
3307 | if (pipe_config->pch_pfit.enabled) | |
3308 | skylake_pfit_enable(crtc); | |
3309 | } else if (HAS_PCH_SPLIT(dev)) { | |
3310 | if (pipe_config->pch_pfit.enabled) | |
3311 | ironlake_pfit_enable(crtc); | |
3312 | else if (old_crtc_state->pch_pfit.enabled) | |
3313 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3314 | } |
e30e8f75 GP |
3315 | } |
3316 | ||
5e84e1a4 ZW |
3317 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3318 | { | |
3319 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3320 | struct drm_i915_private *dev_priv = to_i915(dev); |
5e84e1a4 ZW |
3321 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3322 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3323 | i915_reg_t reg; |
3324 | u32 temp; | |
5e84e1a4 ZW |
3325 | |
3326 | /* enable normal train */ | |
3327 | reg = FDI_TX_CTL(pipe); | |
3328 | temp = I915_READ(reg); | |
61e499bf | 3329 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3330 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3331 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3332 | } else { |
3333 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3334 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3335 | } |
5e84e1a4 ZW |
3336 | I915_WRITE(reg, temp); |
3337 | ||
3338 | reg = FDI_RX_CTL(pipe); | |
3339 | temp = I915_READ(reg); | |
3340 | if (HAS_PCH_CPT(dev)) { | |
3341 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3342 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3343 | } else { | |
3344 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3345 | temp |= FDI_LINK_TRAIN_NONE; | |
3346 | } | |
3347 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3348 | ||
3349 | /* wait one idle pattern time */ | |
3350 | POSTING_READ(reg); | |
3351 | udelay(1000); | |
357555c0 JB |
3352 | |
3353 | /* IVB wants error correction enabled */ | |
3354 | if (IS_IVYBRIDGE(dev)) | |
3355 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3356 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3357 | } |
3358 | ||
8db9d77b ZW |
3359 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3360 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3361 | { | |
3362 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3363 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3364 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3365 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3366 | i915_reg_t reg; |
3367 | u32 temp, tries; | |
8db9d77b | 3368 | |
1c8562f6 | 3369 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3370 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3371 | |
e1a44743 AJ |
3372 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3373 | for train result */ | |
5eddb70b CW |
3374 | reg = FDI_RX_IMR(pipe); |
3375 | temp = I915_READ(reg); | |
e1a44743 AJ |
3376 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3377 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3378 | I915_WRITE(reg, temp); |
3379 | I915_READ(reg); | |
e1a44743 AJ |
3380 | udelay(150); |
3381 | ||
8db9d77b | 3382 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3383 | reg = FDI_TX_CTL(pipe); |
3384 | temp = I915_READ(reg); | |
627eb5a3 | 3385 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3386 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3387 | temp &= ~FDI_LINK_TRAIN_NONE; |
3388 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3389 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3390 | |
5eddb70b CW |
3391 | reg = FDI_RX_CTL(pipe); |
3392 | temp = I915_READ(reg); | |
8db9d77b ZW |
3393 | temp &= ~FDI_LINK_TRAIN_NONE; |
3394 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3395 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3396 | ||
3397 | POSTING_READ(reg); | |
8db9d77b ZW |
3398 | udelay(150); |
3399 | ||
5b2adf89 | 3400 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3401 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3402 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3403 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3404 | |
5eddb70b | 3405 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3406 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3407 | temp = I915_READ(reg); |
8db9d77b ZW |
3408 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3409 | ||
3410 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3411 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3412 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3413 | break; |
3414 | } | |
8db9d77b | 3415 | } |
e1a44743 | 3416 | if (tries == 5) |
5eddb70b | 3417 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3418 | |
3419 | /* Train 2 */ | |
5eddb70b CW |
3420 | reg = FDI_TX_CTL(pipe); |
3421 | temp = I915_READ(reg); | |
8db9d77b ZW |
3422 | temp &= ~FDI_LINK_TRAIN_NONE; |
3423 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3424 | I915_WRITE(reg, temp); |
8db9d77b | 3425 | |
5eddb70b CW |
3426 | reg = FDI_RX_CTL(pipe); |
3427 | temp = I915_READ(reg); | |
8db9d77b ZW |
3428 | temp &= ~FDI_LINK_TRAIN_NONE; |
3429 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3430 | I915_WRITE(reg, temp); |
8db9d77b | 3431 | |
5eddb70b CW |
3432 | POSTING_READ(reg); |
3433 | udelay(150); | |
8db9d77b | 3434 | |
5eddb70b | 3435 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3436 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3437 | temp = I915_READ(reg); |
8db9d77b ZW |
3438 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3439 | ||
3440 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3441 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3442 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3443 | break; | |
3444 | } | |
8db9d77b | 3445 | } |
e1a44743 | 3446 | if (tries == 5) |
5eddb70b | 3447 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3448 | |
3449 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3450 | |
8db9d77b ZW |
3451 | } |
3452 | ||
0206e353 | 3453 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3454 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3455 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3456 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3457 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3458 | }; | |
3459 | ||
3460 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3461 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3462 | { | |
3463 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3464 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3465 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3466 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3467 | i915_reg_t reg; |
3468 | u32 temp, i, retry; | |
8db9d77b | 3469 | |
e1a44743 AJ |
3470 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3471 | for train result */ | |
5eddb70b CW |
3472 | reg = FDI_RX_IMR(pipe); |
3473 | temp = I915_READ(reg); | |
e1a44743 AJ |
3474 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3475 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3476 | I915_WRITE(reg, temp); |
3477 | ||
3478 | POSTING_READ(reg); | |
e1a44743 AJ |
3479 | udelay(150); |
3480 | ||
8db9d77b | 3481 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3482 | reg = FDI_TX_CTL(pipe); |
3483 | temp = I915_READ(reg); | |
627eb5a3 | 3484 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3485 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3486 | temp &= ~FDI_LINK_TRAIN_NONE; |
3487 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3488 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3489 | /* SNB-B */ | |
3490 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3491 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3492 | |
d74cf324 DV |
3493 | I915_WRITE(FDI_RX_MISC(pipe), |
3494 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3495 | ||
5eddb70b CW |
3496 | reg = FDI_RX_CTL(pipe); |
3497 | temp = I915_READ(reg); | |
8db9d77b ZW |
3498 | if (HAS_PCH_CPT(dev)) { |
3499 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3500 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3501 | } else { | |
3502 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3503 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3504 | } | |
5eddb70b CW |
3505 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3506 | ||
3507 | POSTING_READ(reg); | |
8db9d77b ZW |
3508 | udelay(150); |
3509 | ||
0206e353 | 3510 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3511 | reg = FDI_TX_CTL(pipe); |
3512 | temp = I915_READ(reg); | |
8db9d77b ZW |
3513 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3514 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3515 | I915_WRITE(reg, temp); |
3516 | ||
3517 | POSTING_READ(reg); | |
8db9d77b ZW |
3518 | udelay(500); |
3519 | ||
fa37d39e SP |
3520 | for (retry = 0; retry < 5; retry++) { |
3521 | reg = FDI_RX_IIR(pipe); | |
3522 | temp = I915_READ(reg); | |
3523 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3524 | if (temp & FDI_RX_BIT_LOCK) { | |
3525 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3526 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3527 | break; | |
3528 | } | |
3529 | udelay(50); | |
8db9d77b | 3530 | } |
fa37d39e SP |
3531 | if (retry < 5) |
3532 | break; | |
8db9d77b ZW |
3533 | } |
3534 | if (i == 4) | |
5eddb70b | 3535 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3536 | |
3537 | /* Train 2 */ | |
5eddb70b CW |
3538 | reg = FDI_TX_CTL(pipe); |
3539 | temp = I915_READ(reg); | |
8db9d77b ZW |
3540 | temp &= ~FDI_LINK_TRAIN_NONE; |
3541 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3542 | if (IS_GEN6(dev)) { | |
3543 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3544 | /* SNB-B */ | |
3545 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3546 | } | |
5eddb70b | 3547 | I915_WRITE(reg, temp); |
8db9d77b | 3548 | |
5eddb70b CW |
3549 | reg = FDI_RX_CTL(pipe); |
3550 | temp = I915_READ(reg); | |
8db9d77b ZW |
3551 | if (HAS_PCH_CPT(dev)) { |
3552 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3553 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3554 | } else { | |
3555 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3556 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3557 | } | |
5eddb70b CW |
3558 | I915_WRITE(reg, temp); |
3559 | ||
3560 | POSTING_READ(reg); | |
8db9d77b ZW |
3561 | udelay(150); |
3562 | ||
0206e353 | 3563 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3564 | reg = FDI_TX_CTL(pipe); |
3565 | temp = I915_READ(reg); | |
8db9d77b ZW |
3566 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3567 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3568 | I915_WRITE(reg, temp); |
3569 | ||
3570 | POSTING_READ(reg); | |
8db9d77b ZW |
3571 | udelay(500); |
3572 | ||
fa37d39e SP |
3573 | for (retry = 0; retry < 5; retry++) { |
3574 | reg = FDI_RX_IIR(pipe); | |
3575 | temp = I915_READ(reg); | |
3576 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3577 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3578 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3579 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3580 | break; | |
3581 | } | |
3582 | udelay(50); | |
8db9d77b | 3583 | } |
fa37d39e SP |
3584 | if (retry < 5) |
3585 | break; | |
8db9d77b ZW |
3586 | } |
3587 | if (i == 4) | |
5eddb70b | 3588 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3589 | |
3590 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3591 | } | |
3592 | ||
357555c0 JB |
3593 | /* Manual link training for Ivy Bridge A0 parts */ |
3594 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3595 | { | |
3596 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3597 | struct drm_i915_private *dev_priv = to_i915(dev); |
357555c0 JB |
3598 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3599 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3600 | i915_reg_t reg; |
3601 | u32 temp, i, j; | |
357555c0 JB |
3602 | |
3603 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3604 | for train result */ | |
3605 | reg = FDI_RX_IMR(pipe); | |
3606 | temp = I915_READ(reg); | |
3607 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3608 | temp &= ~FDI_RX_BIT_LOCK; | |
3609 | I915_WRITE(reg, temp); | |
3610 | ||
3611 | POSTING_READ(reg); | |
3612 | udelay(150); | |
3613 | ||
01a415fd DV |
3614 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3615 | I915_READ(FDI_RX_IIR(pipe))); | |
3616 | ||
139ccd3f JB |
3617 | /* Try each vswing and preemphasis setting twice before moving on */ |
3618 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3619 | /* disable first in case we need to retry */ | |
3620 | reg = FDI_TX_CTL(pipe); | |
3621 | temp = I915_READ(reg); | |
3622 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3623 | temp &= ~FDI_TX_ENABLE; | |
3624 | I915_WRITE(reg, temp); | |
357555c0 | 3625 | |
139ccd3f JB |
3626 | reg = FDI_RX_CTL(pipe); |
3627 | temp = I915_READ(reg); | |
3628 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3629 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3630 | temp &= ~FDI_RX_ENABLE; | |
3631 | I915_WRITE(reg, temp); | |
357555c0 | 3632 | |
139ccd3f | 3633 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3634 | reg = FDI_TX_CTL(pipe); |
3635 | temp = I915_READ(reg); | |
139ccd3f | 3636 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3637 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3638 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3639 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3640 | temp |= snb_b_fdi_train_param[j/2]; |
3641 | temp |= FDI_COMPOSITE_SYNC; | |
3642 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3643 | |
139ccd3f JB |
3644 | I915_WRITE(FDI_RX_MISC(pipe), |
3645 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3646 | |
139ccd3f | 3647 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3648 | temp = I915_READ(reg); |
139ccd3f JB |
3649 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3650 | temp |= FDI_COMPOSITE_SYNC; | |
3651 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3652 | |
139ccd3f JB |
3653 | POSTING_READ(reg); |
3654 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3655 | |
139ccd3f JB |
3656 | for (i = 0; i < 4; i++) { |
3657 | reg = FDI_RX_IIR(pipe); | |
3658 | temp = I915_READ(reg); | |
3659 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3660 | |
139ccd3f JB |
3661 | if (temp & FDI_RX_BIT_LOCK || |
3662 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3663 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3664 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3665 | i); | |
3666 | break; | |
3667 | } | |
3668 | udelay(1); /* should be 0.5us */ | |
3669 | } | |
3670 | if (i == 4) { | |
3671 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3672 | continue; | |
3673 | } | |
357555c0 | 3674 | |
139ccd3f | 3675 | /* Train 2 */ |
357555c0 JB |
3676 | reg = FDI_TX_CTL(pipe); |
3677 | temp = I915_READ(reg); | |
139ccd3f JB |
3678 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3679 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3680 | I915_WRITE(reg, temp); | |
3681 | ||
3682 | reg = FDI_RX_CTL(pipe); | |
3683 | temp = I915_READ(reg); | |
3684 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3685 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3686 | I915_WRITE(reg, temp); |
3687 | ||
3688 | POSTING_READ(reg); | |
139ccd3f | 3689 | udelay(2); /* should be 1.5us */ |
357555c0 | 3690 | |
139ccd3f JB |
3691 | for (i = 0; i < 4; i++) { |
3692 | reg = FDI_RX_IIR(pipe); | |
3693 | temp = I915_READ(reg); | |
3694 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3695 | |
139ccd3f JB |
3696 | if (temp & FDI_RX_SYMBOL_LOCK || |
3697 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3698 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3699 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3700 | i); | |
3701 | goto train_done; | |
3702 | } | |
3703 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3704 | } |
139ccd3f JB |
3705 | if (i == 4) |
3706 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3707 | } |
357555c0 | 3708 | |
139ccd3f | 3709 | train_done: |
357555c0 JB |
3710 | DRM_DEBUG_KMS("FDI train done.\n"); |
3711 | } | |
3712 | ||
88cefb6c | 3713 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3714 | { |
88cefb6c | 3715 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 3716 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 3717 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3718 | i915_reg_t reg; |
3719 | u32 temp; | |
c64e311e | 3720 | |
c98e9dcf | 3721 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3722 | reg = FDI_RX_CTL(pipe); |
3723 | temp = I915_READ(reg); | |
627eb5a3 | 3724 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3725 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3726 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3727 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3728 | ||
3729 | POSTING_READ(reg); | |
c98e9dcf JB |
3730 | udelay(200); |
3731 | ||
3732 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3733 | temp = I915_READ(reg); |
3734 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3735 | ||
3736 | POSTING_READ(reg); | |
c98e9dcf JB |
3737 | udelay(200); |
3738 | ||
20749730 PZ |
3739 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3740 | reg = FDI_TX_CTL(pipe); | |
3741 | temp = I915_READ(reg); | |
3742 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3743 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3744 | |
20749730 PZ |
3745 | POSTING_READ(reg); |
3746 | udelay(100); | |
6be4a607 | 3747 | } |
0e23b99d JB |
3748 | } |
3749 | ||
88cefb6c DV |
3750 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3751 | { | |
3752 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3753 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 3754 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3755 | i915_reg_t reg; |
3756 | u32 temp; | |
88cefb6c DV |
3757 | |
3758 | /* Switch from PCDclk to Rawclk */ | |
3759 | reg = FDI_RX_CTL(pipe); | |
3760 | temp = I915_READ(reg); | |
3761 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3762 | ||
3763 | /* Disable CPU FDI TX PLL */ | |
3764 | reg = FDI_TX_CTL(pipe); | |
3765 | temp = I915_READ(reg); | |
3766 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3767 | ||
3768 | POSTING_READ(reg); | |
3769 | udelay(100); | |
3770 | ||
3771 | reg = FDI_RX_CTL(pipe); | |
3772 | temp = I915_READ(reg); | |
3773 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3774 | ||
3775 | /* Wait for the clocks to turn off. */ | |
3776 | POSTING_READ(reg); | |
3777 | udelay(100); | |
3778 | } | |
3779 | ||
0fc932b8 JB |
3780 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3781 | { | |
3782 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3783 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
3784 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3785 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3786 | i915_reg_t reg; |
3787 | u32 temp; | |
0fc932b8 JB |
3788 | |
3789 | /* disable CPU FDI tx and PCH FDI rx */ | |
3790 | reg = FDI_TX_CTL(pipe); | |
3791 | temp = I915_READ(reg); | |
3792 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3793 | POSTING_READ(reg); | |
3794 | ||
3795 | reg = FDI_RX_CTL(pipe); | |
3796 | temp = I915_READ(reg); | |
3797 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3798 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3799 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3800 | ||
3801 | POSTING_READ(reg); | |
3802 | udelay(100); | |
3803 | ||
3804 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3805 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3806 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3807 | |
3808 | /* still set train pattern 1 */ | |
3809 | reg = FDI_TX_CTL(pipe); | |
3810 | temp = I915_READ(reg); | |
3811 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3812 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3813 | I915_WRITE(reg, temp); | |
3814 | ||
3815 | reg = FDI_RX_CTL(pipe); | |
3816 | temp = I915_READ(reg); | |
3817 | if (HAS_PCH_CPT(dev)) { | |
3818 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3819 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3820 | } else { | |
3821 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3822 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3823 | } | |
3824 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3825 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3826 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3827 | I915_WRITE(reg, temp); |
3828 | ||
3829 | POSTING_READ(reg); | |
3830 | udelay(100); | |
3831 | } | |
3832 | ||
5dce5b93 CW |
3833 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3834 | { | |
3835 | struct intel_crtc *crtc; | |
3836 | ||
3837 | /* Note that we don't need to be called with mode_config.lock here | |
3838 | * as our list of CRTC objects is static for the lifetime of the | |
3839 | * device and so cannot disappear as we iterate. Similarly, we can | |
3840 | * happily treat the predicates as racy, atomic checks as userspace | |
3841 | * cannot claim and pin a new fb without at least acquring the | |
3842 | * struct_mutex and so serialising with us. | |
3843 | */ | |
d3fcc808 | 3844 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3845 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3846 | continue; | |
3847 | ||
5a21b665 | 3848 | if (crtc->flip_work) |
5dce5b93 CW |
3849 | intel_wait_for_vblank(dev, crtc->pipe); |
3850 | ||
3851 | return true; | |
3852 | } | |
3853 | ||
3854 | return false; | |
3855 | } | |
3856 | ||
5a21b665 | 3857 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
3858 | { |
3859 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
3860 | struct intel_flip_work *work = intel_crtc->flip_work; |
3861 | ||
3862 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
3863 | |
3864 | if (work->event) | |
560ce1dc | 3865 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
3866 | |
3867 | drm_crtc_vblank_put(&intel_crtc->base); | |
3868 | ||
5a21b665 | 3869 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 3870 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
3871 | |
3872 | trace_i915_flip_complete(intel_crtc->plane, | |
3873 | work->pending_flip_obj); | |
d6bbafa1 CW |
3874 | } |
3875 | ||
5008e874 | 3876 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3877 | { |
0f91128d | 3878 | struct drm_device *dev = crtc->dev; |
fac5e23e | 3879 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 3880 | long ret; |
e6c3a2a6 | 3881 | |
2c10d571 | 3882 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3883 | |
3884 | ret = wait_event_interruptible_timeout( | |
3885 | dev_priv->pending_flip_queue, | |
3886 | !intel_crtc_has_pending_flip(crtc), | |
3887 | 60*HZ); | |
3888 | ||
3889 | if (ret < 0) | |
3890 | return ret; | |
3891 | ||
5a21b665 DV |
3892 | if (ret == 0) { |
3893 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3894 | struct intel_flip_work *work; | |
3895 | ||
3896 | spin_lock_irq(&dev->event_lock); | |
3897 | work = intel_crtc->flip_work; | |
3898 | if (work && !is_mmio_work(work)) { | |
3899 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3900 | page_flip_completed(intel_crtc); | |
3901 | } | |
3902 | spin_unlock_irq(&dev->event_lock); | |
3903 | } | |
5bb61643 | 3904 | |
5008e874 | 3905 | return 0; |
e6c3a2a6 CW |
3906 | } |
3907 | ||
060f02d8 VS |
3908 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3909 | { | |
3910 | u32 temp; | |
3911 | ||
3912 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3913 | ||
3914 | mutex_lock(&dev_priv->sb_lock); | |
3915 | ||
3916 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3917 | temp |= SBI_SSCCTL_DISABLE; | |
3918 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3919 | ||
3920 | mutex_unlock(&dev_priv->sb_lock); | |
3921 | } | |
3922 | ||
e615efe4 ED |
3923 | /* Program iCLKIP clock to the desired frequency */ |
3924 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3925 | { | |
64b46a06 | 3926 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 3927 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3928 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3929 | u32 temp; | |
3930 | ||
060f02d8 | 3931 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 3932 | |
64b46a06 VS |
3933 | /* The iCLK virtual clock root frequency is in MHz, |
3934 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3935 | * divisors, it is necessary to divide one by another, so we | |
3936 | * convert the virtual clock precision to KHz here for higher | |
3937 | * precision. | |
3938 | */ | |
3939 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
3940 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3941 | u32 iclk_pi_range = 64; | |
64b46a06 | 3942 | u32 desired_divisor; |
e615efe4 | 3943 | |
64b46a06 VS |
3944 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
3945 | clock << auxdiv); | |
3946 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3947 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 3948 | |
64b46a06 VS |
3949 | /* |
3950 | * Near 20MHz is a corner case which is | |
3951 | * out of range for the 7-bit divisor | |
3952 | */ | |
3953 | if (divsel <= 0x7f) | |
3954 | break; | |
e615efe4 ED |
3955 | } |
3956 | ||
3957 | /* This should not happen with any sane values */ | |
3958 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3959 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3960 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3961 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3962 | ||
3963 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3964 | clock, |
e615efe4 ED |
3965 | auxdiv, |
3966 | divsel, | |
3967 | phasedir, | |
3968 | phaseinc); | |
3969 | ||
060f02d8 VS |
3970 | mutex_lock(&dev_priv->sb_lock); |
3971 | ||
e615efe4 | 3972 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 3973 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3974 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3975 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3976 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3977 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3978 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3979 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3980 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3981 | |
3982 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3983 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3984 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3985 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3986 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3987 | |
3988 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3989 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3990 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3991 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 3992 | |
060f02d8 VS |
3993 | mutex_unlock(&dev_priv->sb_lock); |
3994 | ||
e615efe4 ED |
3995 | /* Wait for initialization time */ |
3996 | udelay(24); | |
3997 | ||
3998 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3999 | } | |
4000 | ||
8802e5b6 VS |
4001 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4002 | { | |
4003 | u32 divsel, phaseinc, auxdiv; | |
4004 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4005 | u32 iclk_pi_range = 64; | |
4006 | u32 desired_divisor; | |
4007 | u32 temp; | |
4008 | ||
4009 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4010 | return 0; | |
4011 | ||
4012 | mutex_lock(&dev_priv->sb_lock); | |
4013 | ||
4014 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4015 | if (temp & SBI_SSCCTL_DISABLE) { | |
4016 | mutex_unlock(&dev_priv->sb_lock); | |
4017 | return 0; | |
4018 | } | |
4019 | ||
4020 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4021 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4022 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4023 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4024 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4025 | ||
4026 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4027 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4028 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4029 | ||
4030 | mutex_unlock(&dev_priv->sb_lock); | |
4031 | ||
4032 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4033 | ||
4034 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4035 | desired_divisor << auxdiv); | |
4036 | } | |
4037 | ||
275f01b2 DV |
4038 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4039 | enum pipe pch_transcoder) | |
4040 | { | |
4041 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4042 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4043 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4044 | |
4045 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4046 | I915_READ(HTOTAL(cpu_transcoder))); | |
4047 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4048 | I915_READ(HBLANK(cpu_transcoder))); | |
4049 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4050 | I915_READ(HSYNC(cpu_transcoder))); | |
4051 | ||
4052 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4053 | I915_READ(VTOTAL(cpu_transcoder))); | |
4054 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4055 | I915_READ(VBLANK(cpu_transcoder))); | |
4056 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4057 | I915_READ(VSYNC(cpu_transcoder))); | |
4058 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4059 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4060 | } | |
4061 | ||
003632d9 | 4062 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4063 | { |
fac5e23e | 4064 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4065 | uint32_t temp; |
4066 | ||
4067 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4068 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4069 | return; |
4070 | ||
4071 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4072 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4073 | ||
003632d9 ACO |
4074 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4075 | if (enable) | |
4076 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4077 | ||
4078 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4079 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4080 | POSTING_READ(SOUTH_CHICKEN1); | |
4081 | } | |
4082 | ||
4083 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4084 | { | |
4085 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4086 | |
4087 | switch (intel_crtc->pipe) { | |
4088 | case PIPE_A: | |
4089 | break; | |
4090 | case PIPE_B: | |
6e3c9717 | 4091 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4092 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4093 | else |
003632d9 | 4094 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4095 | |
4096 | break; | |
4097 | case PIPE_C: | |
003632d9 | 4098 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4099 | |
4100 | break; | |
4101 | default: | |
4102 | BUG(); | |
4103 | } | |
4104 | } | |
4105 | ||
c48b5305 VS |
4106 | /* Return which DP Port should be selected for Transcoder DP control */ |
4107 | static enum port | |
4108 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4109 | { | |
4110 | struct drm_device *dev = crtc->dev; | |
4111 | struct intel_encoder *encoder; | |
4112 | ||
4113 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
cca0502b | 4114 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4115 | encoder->type == INTEL_OUTPUT_EDP) |
4116 | return enc_to_dig_port(&encoder->base)->port; | |
4117 | } | |
4118 | ||
4119 | return -1; | |
4120 | } | |
4121 | ||
f67a559d JB |
4122 | /* |
4123 | * Enable PCH resources required for PCH ports: | |
4124 | * - PCH PLLs | |
4125 | * - FDI training & RX/TX | |
4126 | * - update transcoder timings | |
4127 | * - DP transcoding bits | |
4128 | * - transcoder | |
4129 | */ | |
4130 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4131 | { |
4132 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4133 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e23b99d JB |
4134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4135 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4136 | u32 temp; |
2c07245f | 4137 | |
ab9412ba | 4138 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4139 | |
1fbc0d78 DV |
4140 | if (IS_IVYBRIDGE(dev)) |
4141 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4142 | ||
cd986abb DV |
4143 | /* Write the TU size bits before fdi link training, so that error |
4144 | * detection works. */ | |
4145 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4146 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4147 | ||
c98e9dcf | 4148 | /* For PCH output, training FDI link */ |
674cf967 | 4149 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4150 | |
3ad8a208 DV |
4151 | /* We need to program the right clock selection before writing the pixel |
4152 | * mutliplier into the DPLL. */ | |
303b81e0 | 4153 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4154 | u32 sel; |
4b645f14 | 4155 | |
c98e9dcf | 4156 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4157 | temp |= TRANS_DPLL_ENABLE(pipe); |
4158 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4159 | if (intel_crtc->config->shared_dpll == |
4160 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4161 | temp |= sel; |
4162 | else | |
4163 | temp &= ~sel; | |
c98e9dcf | 4164 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4165 | } |
5eddb70b | 4166 | |
3ad8a208 DV |
4167 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4168 | * transcoder, and we actually should do this to not upset any PCH | |
4169 | * transcoder that already use the clock when we share it. | |
4170 | * | |
4171 | * Note that enable_shared_dpll tries to do the right thing, but | |
4172 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4173 | * the right LVDS enable sequence. */ | |
85b3894f | 4174 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4175 | |
d9b6cb56 JB |
4176 | /* set transcoder timing, panel must allow it */ |
4177 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4178 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4179 | |
303b81e0 | 4180 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4181 | |
c98e9dcf | 4182 | /* For PCH DP, enable TRANS_DP_CTL */ |
37a5650b | 4183 | if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) { |
9c4edaee VS |
4184 | const struct drm_display_mode *adjusted_mode = |
4185 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4186 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4187 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4188 | temp = I915_READ(reg); |
4189 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4190 | TRANS_DP_SYNC_MASK | |
4191 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4192 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4193 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4194 | |
9c4edaee | 4195 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4196 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4197 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4198 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4199 | |
4200 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4201 | case PORT_B: |
5eddb70b | 4202 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4203 | break; |
c48b5305 | 4204 | case PORT_C: |
5eddb70b | 4205 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4206 | break; |
c48b5305 | 4207 | case PORT_D: |
5eddb70b | 4208 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4209 | break; |
4210 | default: | |
e95d41e1 | 4211 | BUG(); |
32f9d658 | 4212 | } |
2c07245f | 4213 | |
5eddb70b | 4214 | I915_WRITE(reg, temp); |
6be4a607 | 4215 | } |
b52eb4dc | 4216 | |
b8a4f404 | 4217 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4218 | } |
4219 | ||
1507e5bd PZ |
4220 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4221 | { | |
4222 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4223 | struct drm_i915_private *dev_priv = to_i915(dev); |
1507e5bd | 4224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 4225 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4226 | |
ab9412ba | 4227 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4228 | |
8c52b5e8 | 4229 | lpt_program_iclkip(crtc); |
1507e5bd | 4230 | |
0540e488 | 4231 | /* Set transcoder timing. */ |
275f01b2 | 4232 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4233 | |
937bb610 | 4234 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4235 | } |
4236 | ||
a1520318 | 4237 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4238 | { |
fac5e23e | 4239 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4240 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4241 | u32 temp; |
4242 | ||
4243 | temp = I915_READ(dslreg); | |
4244 | udelay(500); | |
4245 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4246 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4247 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4248 | } |
4249 | } | |
4250 | ||
86adf9d7 ML |
4251 | static int |
4252 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4253 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4254 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4255 | { |
86adf9d7 ML |
4256 | struct intel_crtc_scaler_state *scaler_state = |
4257 | &crtc_state->scaler_state; | |
4258 | struct intel_crtc *intel_crtc = | |
4259 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4260 | int need_scaling; |
6156a456 CK |
4261 | |
4262 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4263 | (src_h != dst_w || src_w != dst_h): | |
4264 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4265 | |
4266 | /* | |
4267 | * if plane is being disabled or scaler is no more required or force detach | |
4268 | * - free scaler binded to this plane/crtc | |
4269 | * - in order to do this, update crtc->scaler_usage | |
4270 | * | |
4271 | * Here scaler state in crtc_state is set free so that | |
4272 | * scaler can be assigned to other user. Actual register | |
4273 | * update to free the scaler is done in plane/panel-fit programming. | |
4274 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4275 | */ | |
86adf9d7 | 4276 | if (force_detach || !need_scaling) { |
a1b2278e | 4277 | if (*scaler_id >= 0) { |
86adf9d7 | 4278 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4279 | scaler_state->scalers[*scaler_id].in_use = 0; |
4280 | ||
86adf9d7 ML |
4281 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4282 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4283 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4284 | scaler_state->scaler_users); |
4285 | *scaler_id = -1; | |
4286 | } | |
4287 | return 0; | |
4288 | } | |
4289 | ||
4290 | /* range checks */ | |
4291 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4292 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4293 | ||
4294 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4295 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4296 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4297 | "size is out of scaler range\n", |
86adf9d7 | 4298 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4299 | return -EINVAL; |
4300 | } | |
4301 | ||
86adf9d7 ML |
4302 | /* mark this plane as a scaler user in crtc_state */ |
4303 | scaler_state->scaler_users |= (1 << scaler_user); | |
4304 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4305 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4306 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4307 | scaler_state->scaler_users); | |
4308 | ||
4309 | return 0; | |
4310 | } | |
4311 | ||
4312 | /** | |
4313 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4314 | * | |
4315 | * @state: crtc's scaler state | |
86adf9d7 ML |
4316 | * |
4317 | * Return | |
4318 | * 0 - scaler_usage updated successfully | |
4319 | * error - requested scaling cannot be supported or other error condition | |
4320 | */ | |
e435d6e5 | 4321 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4322 | { |
4323 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4324 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4325 | |
78108b7c VS |
4326 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n", |
4327 | intel_crtc->base.base.id, intel_crtc->base.name, | |
4328 | intel_crtc->pipe, SKL_CRTC_INDEX); | |
86adf9d7 | 4329 | |
e435d6e5 | 4330 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4331 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4332 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4333 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4334 | } |
4335 | ||
4336 | /** | |
4337 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4338 | * | |
4339 | * @state: crtc's scaler state | |
86adf9d7 ML |
4340 | * @plane_state: atomic plane state to update |
4341 | * | |
4342 | * Return | |
4343 | * 0 - scaler_usage updated successfully | |
4344 | * error - requested scaling cannot be supported or other error condition | |
4345 | */ | |
da20eabd ML |
4346 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4347 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4348 | { |
4349 | ||
4350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4351 | struct intel_plane *intel_plane = |
4352 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4353 | struct drm_framebuffer *fb = plane_state->base.fb; |
4354 | int ret; | |
4355 | ||
4356 | bool force_detach = !fb || !plane_state->visible; | |
4357 | ||
72660ce0 VS |
4358 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n", |
4359 | intel_plane->base.base.id, intel_plane->base.name, | |
4360 | intel_crtc->pipe, drm_plane_index(&intel_plane->base)); | |
86adf9d7 ML |
4361 | |
4362 | ret = skl_update_scaler(crtc_state, force_detach, | |
4363 | drm_plane_index(&intel_plane->base), | |
4364 | &plane_state->scaler_id, | |
4365 | plane_state->base.rotation, | |
4366 | drm_rect_width(&plane_state->src) >> 16, | |
4367 | drm_rect_height(&plane_state->src) >> 16, | |
4368 | drm_rect_width(&plane_state->dst), | |
4369 | drm_rect_height(&plane_state->dst)); | |
4370 | ||
4371 | if (ret || plane_state->scaler_id < 0) | |
4372 | return ret; | |
4373 | ||
a1b2278e | 4374 | /* check colorkey */ |
818ed961 | 4375 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4376 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4377 | intel_plane->base.base.id, | |
4378 | intel_plane->base.name); | |
a1b2278e CK |
4379 | return -EINVAL; |
4380 | } | |
4381 | ||
4382 | /* Check src format */ | |
86adf9d7 ML |
4383 | switch (fb->pixel_format) { |
4384 | case DRM_FORMAT_RGB565: | |
4385 | case DRM_FORMAT_XBGR8888: | |
4386 | case DRM_FORMAT_XRGB8888: | |
4387 | case DRM_FORMAT_ABGR8888: | |
4388 | case DRM_FORMAT_ARGB8888: | |
4389 | case DRM_FORMAT_XRGB2101010: | |
4390 | case DRM_FORMAT_XBGR2101010: | |
4391 | case DRM_FORMAT_YUYV: | |
4392 | case DRM_FORMAT_YVYU: | |
4393 | case DRM_FORMAT_UYVY: | |
4394 | case DRM_FORMAT_VYUY: | |
4395 | break; | |
4396 | default: | |
72660ce0 VS |
4397 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4398 | intel_plane->base.base.id, intel_plane->base.name, | |
4399 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4400 | return -EINVAL; |
a1b2278e CK |
4401 | } |
4402 | ||
a1b2278e CK |
4403 | return 0; |
4404 | } | |
4405 | ||
e435d6e5 ML |
4406 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4407 | { | |
4408 | int i; | |
4409 | ||
4410 | for (i = 0; i < crtc->num_scalers; i++) | |
4411 | skl_detach_scaler(crtc, i); | |
4412 | } | |
4413 | ||
4414 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4415 | { |
4416 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4417 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4418 | int pipe = crtc->pipe; |
a1b2278e CK |
4419 | struct intel_crtc_scaler_state *scaler_state = |
4420 | &crtc->config->scaler_state; | |
4421 | ||
4422 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4423 | ||
6e3c9717 | 4424 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4425 | int id; |
4426 | ||
4427 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4428 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4429 | return; | |
4430 | } | |
4431 | ||
4432 | id = scaler_state->scaler_id; | |
4433 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4434 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4435 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4436 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4437 | ||
4438 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4439 | } |
4440 | } | |
4441 | ||
b074cec8 JB |
4442 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4443 | { | |
4444 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4445 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4446 | int pipe = crtc->pipe; |
4447 | ||
6e3c9717 | 4448 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4449 | /* Force use of hard-coded filter coefficients |
4450 | * as some pre-programmed values are broken, | |
4451 | * e.g. x201. | |
4452 | */ | |
4453 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4454 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4455 | PF_PIPE_SEL_IVB(pipe)); | |
4456 | else | |
4457 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4458 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4459 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4460 | } |
4461 | } | |
4462 | ||
20bc8673 | 4463 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4464 | { |
cea165c3 | 4465 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4466 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4467 | |
6e3c9717 | 4468 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4469 | return; |
4470 | ||
307e4498 ML |
4471 | /* |
4472 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4473 | * This function is called from post_plane_update, which is run after | |
4474 | * a vblank wait. | |
4475 | */ | |
cea165c3 | 4476 | |
d77e4531 | 4477 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4478 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4479 | mutex_lock(&dev_priv->rps.hw_lock); |
4480 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4481 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4482 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4483 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4484 | * mailbox." Moreover, the mailbox may return a bogus state, |
4485 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4486 | */ |
4487 | } else { | |
4488 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4489 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4490 | * is essentially intel_wait_for_vblank. If we don't have this | |
4491 | * and don't wait for vblanks until the end of crtc_enable, then | |
4492 | * the HW state readout code will complain that the expected | |
4493 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4494 | if (intel_wait_for_register(dev_priv, |
4495 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4496 | 50)) | |
2a114cc1 BW |
4497 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4498 | } | |
d77e4531 PZ |
4499 | } |
4500 | ||
20bc8673 | 4501 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4502 | { |
4503 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4504 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4505 | |
6e3c9717 | 4506 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4507 | return; |
4508 | ||
4509 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4510 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4511 | mutex_lock(&dev_priv->rps.hw_lock); |
4512 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4513 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4514 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4515 | if (intel_wait_for_register(dev_priv, |
4516 | IPS_CTL, IPS_ENABLE, 0, | |
4517 | 42)) | |
23d0b130 | 4518 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4519 | } else { |
2a114cc1 | 4520 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4521 | POSTING_READ(IPS_CTL); |
4522 | } | |
d77e4531 PZ |
4523 | |
4524 | /* We need to wait for a vblank before we can disable the plane. */ | |
4525 | intel_wait_for_vblank(dev, crtc->pipe); | |
4526 | } | |
4527 | ||
7cac945f | 4528 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4529 | { |
7cac945f | 4530 | if (intel_crtc->overlay) { |
d3eedb1a | 4531 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4532 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4533 | |
4534 | mutex_lock(&dev->struct_mutex); | |
4535 | dev_priv->mm.interruptible = false; | |
4536 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4537 | dev_priv->mm.interruptible = true; | |
4538 | mutex_unlock(&dev->struct_mutex); | |
4539 | } | |
4540 | ||
4541 | /* Let userspace switch the overlay on again. In most cases userspace | |
4542 | * has to recompute where to put it anyway. | |
4543 | */ | |
4544 | } | |
4545 | ||
87d4300a ML |
4546 | /** |
4547 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4548 | * @crtc: the CRTC whose primary plane was just enabled | |
4549 | * | |
4550 | * Performs potentially sleeping operations that must be done after the primary | |
4551 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4552 | * called due to an explicit primary plane update, or due to an implicit | |
4553 | * re-enable that is caused when a sprite plane is updated to no longer | |
4554 | * completely hide the primary plane. | |
4555 | */ | |
4556 | static void | |
4557 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4558 | { |
4559 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4560 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4561 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4562 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4563 | |
87d4300a ML |
4564 | /* |
4565 | * FIXME IPS should be fine as long as one plane is | |
4566 | * enabled, but in practice it seems to have problems | |
4567 | * when going from primary only to sprite only and vice | |
4568 | * versa. | |
4569 | */ | |
a5c4d7bc VS |
4570 | hsw_enable_ips(intel_crtc); |
4571 | ||
f99d7069 | 4572 | /* |
87d4300a ML |
4573 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4574 | * So don't enable underrun reporting before at least some planes | |
4575 | * are enabled. | |
4576 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4577 | * but leave the pipe running. | |
f99d7069 | 4578 | */ |
87d4300a ML |
4579 | if (IS_GEN2(dev)) |
4580 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4581 | ||
aca7b684 VS |
4582 | /* Underruns don't always raise interrupts, so check manually. */ |
4583 | intel_check_cpu_fifo_underruns(dev_priv); | |
4584 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4585 | } |
4586 | ||
2622a081 | 4587 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4588 | static void |
4589 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4590 | { |
4591 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4592 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4593 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4594 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4595 | |
87d4300a ML |
4596 | /* |
4597 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4598 | * So diasble underrun reporting before all the planes get disabled. | |
4599 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4600 | * but leave the pipe running. | |
4601 | */ | |
4602 | if (IS_GEN2(dev)) | |
4603 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4604 | |
2622a081 VS |
4605 | /* |
4606 | * FIXME IPS should be fine as long as one plane is | |
4607 | * enabled, but in practice it seems to have problems | |
4608 | * when going from primary only to sprite only and vice | |
4609 | * versa. | |
4610 | */ | |
4611 | hsw_disable_ips(intel_crtc); | |
4612 | } | |
4613 | ||
4614 | /* FIXME get rid of this and use pre_plane_update */ | |
4615 | static void | |
4616 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4617 | { | |
4618 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4619 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4620 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4621 | int pipe = intel_crtc->pipe; | |
4622 | ||
4623 | intel_pre_disable_primary(crtc); | |
4624 | ||
87d4300a ML |
4625 | /* |
4626 | * Vblank time updates from the shadow to live plane control register | |
4627 | * are blocked if the memory self-refresh mode is active at that | |
4628 | * moment. So to make sure the plane gets truly disabled, disable | |
4629 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4630 | * will be checked/applied by the HW only at the next frame start | |
4631 | * event which is after the vblank start event, so we need to have a | |
4632 | * wait-for-vblank between disabling the plane and the pipe. | |
4633 | */ | |
262cd2e1 | 4634 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4635 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4636 | dev_priv->wm.vlv.cxsr = false; |
4637 | intel_wait_for_vblank(dev, pipe); | |
4638 | } | |
87d4300a ML |
4639 | } |
4640 | ||
5a21b665 DV |
4641 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4642 | { | |
4643 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4644 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4645 | struct intel_crtc_state *pipe_config = | |
4646 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
4647 | struct drm_plane *primary = crtc->base.primary; |
4648 | struct drm_plane_state *old_pri_state = | |
4649 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4650 | ||
5748b6a1 | 4651 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 DV |
4652 | |
4653 | crtc->wm.cxsr_allowed = true; | |
4654 | ||
4655 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
4656 | intel_update_watermarks(&crtc->base); | |
4657 | ||
4658 | if (old_pri_state) { | |
4659 | struct intel_plane_state *primary_state = | |
4660 | to_intel_plane_state(primary->state); | |
4661 | struct intel_plane_state *old_primary_state = | |
4662 | to_intel_plane_state(old_pri_state); | |
4663 | ||
4664 | intel_fbc_post_update(crtc); | |
4665 | ||
4666 | if (primary_state->visible && | |
4667 | (needs_modeset(&pipe_config->base) || | |
4668 | !old_primary_state->visible)) | |
4669 | intel_post_enable_primary(&crtc->base); | |
4670 | } | |
4671 | } | |
4672 | ||
5c74cd73 | 4673 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4674 | { |
5c74cd73 | 4675 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4676 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4677 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
4678 | struct intel_crtc_state *pipe_config = |
4679 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4680 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4681 | struct drm_plane *primary = crtc->base.primary; | |
4682 | struct drm_plane_state *old_pri_state = | |
4683 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4684 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4685 | |
5c74cd73 ML |
4686 | if (old_pri_state) { |
4687 | struct intel_plane_state *primary_state = | |
4688 | to_intel_plane_state(primary->state); | |
4689 | struct intel_plane_state *old_primary_state = | |
4690 | to_intel_plane_state(old_pri_state); | |
4691 | ||
faf68d92 | 4692 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 4693 | |
5c74cd73 ML |
4694 | if (old_primary_state->visible && |
4695 | (modeset || !primary_state->visible)) | |
4696 | intel_pre_disable_primary(&crtc->base); | |
4697 | } | |
852eb00d | 4698 | |
a4015f9a | 4699 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) { |
852eb00d | 4700 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4701 | |
2622a081 VS |
4702 | /* |
4703 | * Vblank time updates from the shadow to live plane control register | |
4704 | * are blocked if the memory self-refresh mode is active at that | |
4705 | * moment. So to make sure the plane gets truly disabled, disable | |
4706 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4707 | * will be checked/applied by the HW only at the next frame start | |
4708 | * event which is after the vblank start event, so we need to have a | |
4709 | * wait-for-vblank between disabling the plane and the pipe. | |
4710 | */ | |
4711 | if (old_crtc_state->base.active) { | |
2dfd178d | 4712 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4713 | dev_priv->wm.vlv.cxsr = false; |
4714 | intel_wait_for_vblank(dev, crtc->pipe); | |
4715 | } | |
852eb00d | 4716 | } |
92826fcd | 4717 | |
ed4a6a7c MR |
4718 | /* |
4719 | * IVB workaround: must disable low power watermarks for at least | |
4720 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4721 | * when scaling is disabled. | |
4722 | * | |
4723 | * WaCxSRDisabledForSpriteScaling:ivb | |
4724 | */ | |
4725 | if (pipe_config->disable_lp_wm) { | |
4726 | ilk_disable_lp_wm(dev); | |
4727 | intel_wait_for_vblank(dev, crtc->pipe); | |
4728 | } | |
4729 | ||
4730 | /* | |
4731 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4732 | * watermark programming here. | |
4733 | */ | |
4734 | if (needs_modeset(&pipe_config->base)) | |
4735 | return; | |
4736 | ||
4737 | /* | |
4738 | * For platforms that support atomic watermarks, program the | |
4739 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4740 | * will be the intermediate values that are safe for both pre- and | |
4741 | * post- vblank; when vblank happens, the 'active' values will be set | |
4742 | * to the final 'target' values and we'll do this again to get the | |
4743 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4744 | * will be the final target values which will get automatically latched | |
4745 | * at vblank time; no further programming will be necessary. | |
4746 | * | |
4747 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4748 | * we'll continue to update watermarks the old way, if flags tell | |
4749 | * us to. | |
4750 | */ | |
4751 | if (dev_priv->display.initial_watermarks != NULL) | |
4752 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4753 | else if (pipe_config->update_wm_pre) |
92826fcd | 4754 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4755 | } |
4756 | ||
d032ffa0 | 4757 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4758 | { |
4759 | struct drm_device *dev = crtc->dev; | |
4760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4761 | struct drm_plane *p; |
87d4300a ML |
4762 | int pipe = intel_crtc->pipe; |
4763 | ||
7cac945f | 4764 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4765 | |
d032ffa0 ML |
4766 | drm_for_each_plane_mask(p, dev, plane_mask) |
4767 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4768 | |
f99d7069 DV |
4769 | /* |
4770 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4771 | * to compute the mask of flip planes precisely. For the time being | |
4772 | * consider this a flip to a NULL plane. | |
4773 | */ | |
5748b6a1 | 4774 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
4775 | } |
4776 | ||
f67a559d JB |
4777 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4778 | { | |
4779 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4780 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d | 4781 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4782 | struct intel_encoder *encoder; |
f67a559d | 4783 | int pipe = intel_crtc->pipe; |
b95c5321 ML |
4784 | struct intel_crtc_state *pipe_config = |
4785 | to_intel_crtc_state(crtc->state); | |
f67a559d | 4786 | |
53d9f4e9 | 4787 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4788 | return; |
4789 | ||
b2c0593a VS |
4790 | /* |
4791 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4792 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4793 | * | |
4794 | * On ILK we get an occasional spurious CPU pipe underruns | |
4795 | * between eDP port A enable and vdd enable. Also PCH port | |
4796 | * enable seems to result in the occasional CPU pipe underrun. | |
4797 | * | |
4798 | * Spurious PCH underruns also occur during PCH enabling. | |
4799 | */ | |
4800 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
4801 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
4802 | if (intel_crtc->config->has_pch_encoder) |
4803 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4804 | ||
6e3c9717 | 4805 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4806 | intel_prepare_shared_dpll(intel_crtc); |
4807 | ||
37a5650b | 4808 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 4809 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4810 | |
4811 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4812 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4813 | |
6e3c9717 | 4814 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4815 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4816 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4817 | } |
4818 | ||
4819 | ironlake_set_pipeconf(crtc); | |
4820 | ||
f67a559d | 4821 | intel_crtc->active = true; |
8664281b | 4822 | |
f6736a1a | 4823 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4824 | if (encoder->pre_enable) |
4825 | encoder->pre_enable(encoder); | |
f67a559d | 4826 | |
6e3c9717 | 4827 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4828 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4829 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4830 | * enabling. */ | |
88cefb6c | 4831 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4832 | } else { |
4833 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4834 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4835 | } | |
f67a559d | 4836 | |
b074cec8 | 4837 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4838 | |
9c54c0dd JB |
4839 | /* |
4840 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4841 | * clocks enabled | |
4842 | */ | |
b95c5321 | 4843 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 4844 | |
1d5bf5d9 ID |
4845 | if (dev_priv->display.initial_watermarks != NULL) |
4846 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4847 | intel_enable_pipe(intel_crtc); |
f67a559d | 4848 | |
6e3c9717 | 4849 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4850 | ironlake_pch_enable(crtc); |
c98e9dcf | 4851 | |
f9b61ff6 DV |
4852 | assert_vblank_disabled(crtc); |
4853 | drm_crtc_vblank_on(crtc); | |
4854 | ||
fa5c73b1 DV |
4855 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4856 | encoder->enable(encoder); | |
61b77ddd DV |
4857 | |
4858 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4859 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4860 | |
4861 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4862 | if (intel_crtc->config->has_pch_encoder) | |
4863 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 4864 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 4865 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
4866 | } |
4867 | ||
42db64ef PZ |
4868 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4869 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4870 | { | |
f5adf94e | 4871 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4872 | } |
4873 | ||
4f771f10 PZ |
4874 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4875 | { | |
4876 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4877 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f771f10 PZ |
4878 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4879 | struct intel_encoder *encoder; | |
99d736a2 | 4880 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 4881 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
4882 | struct intel_crtc_state *pipe_config = |
4883 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4884 | |
53d9f4e9 | 4885 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4886 | return; |
4887 | ||
81b088ca VS |
4888 | if (intel_crtc->config->has_pch_encoder) |
4889 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4890 | false); | |
4891 | ||
95a7a2ae ID |
4892 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4893 | if (encoder->pre_pll_enable) | |
4894 | encoder->pre_pll_enable(encoder); | |
4895 | ||
8106ddbd | 4896 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
4897 | intel_enable_shared_dpll(intel_crtc); |
4898 | ||
37a5650b | 4899 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 4900 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 4901 | |
d7edc4e5 | 4902 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
4903 | intel_set_pipe_timings(intel_crtc); |
4904 | ||
bc58be60 | 4905 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 4906 | |
4d1de975 JN |
4907 | if (cpu_transcoder != TRANSCODER_EDP && |
4908 | !transcoder_is_dsi(cpu_transcoder)) { | |
4909 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 4910 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
4911 | } |
4912 | ||
6e3c9717 | 4913 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4914 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4915 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4916 | } |
4917 | ||
d7edc4e5 | 4918 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
4919 | haswell_set_pipeconf(crtc); |
4920 | ||
391bf048 | 4921 | haswell_set_pipemisc(crtc); |
229fca97 | 4922 | |
b95c5321 | 4923 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 4924 | |
4f771f10 | 4925 | intel_crtc->active = true; |
8664281b | 4926 | |
6b698516 DV |
4927 | if (intel_crtc->config->has_pch_encoder) |
4928 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4929 | else | |
4930 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4931 | ||
7d4aefd0 | 4932 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4933 | if (encoder->pre_enable) |
4934 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4935 | } |
4f771f10 | 4936 | |
d2d65408 | 4937 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4938 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4939 | |
d7edc4e5 | 4940 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 4941 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4942 | |
1c132b44 | 4943 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4944 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4945 | else |
1c132b44 | 4946 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4947 | |
4948 | /* | |
4949 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4950 | * clocks enabled | |
4951 | */ | |
b95c5321 | 4952 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 4953 | |
1f544388 | 4954 | intel_ddi_set_pipe_settings(crtc); |
d7edc4e5 | 4955 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 4956 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4957 | |
1d5bf5d9 ID |
4958 | if (dev_priv->display.initial_watermarks != NULL) |
4959 | dev_priv->display.initial_watermarks(pipe_config); | |
4960 | else | |
4961 | intel_update_watermarks(crtc); | |
4d1de975 JN |
4962 | |
4963 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 4964 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 4965 | intel_enable_pipe(intel_crtc); |
42db64ef | 4966 | |
6e3c9717 | 4967 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4968 | lpt_pch_enable(crtc); |
4f771f10 | 4969 | |
a65347ba | 4970 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4971 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4972 | ||
f9b61ff6 DV |
4973 | assert_vblank_disabled(crtc); |
4974 | drm_crtc_vblank_on(crtc); | |
4975 | ||
8807e55b | 4976 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4977 | encoder->enable(encoder); |
8807e55b JN |
4978 | intel_opregion_notify_encoder(encoder, true); |
4979 | } | |
4f771f10 | 4980 | |
6b698516 DV |
4981 | if (intel_crtc->config->has_pch_encoder) { |
4982 | intel_wait_for_vblank(dev, pipe); | |
4983 | intel_wait_for_vblank(dev, pipe); | |
4984 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
4985 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4986 | true); | |
6b698516 | 4987 | } |
d2d65408 | 4988 | |
e4916946 PZ |
4989 | /* If we change the relative order between pipe/planes enabling, we need |
4990 | * to change the workaround. */ | |
99d736a2 ML |
4991 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4992 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4993 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4994 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4995 | } | |
4f771f10 PZ |
4996 | } |
4997 | ||
bfd16b2a | 4998 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4999 | { |
5000 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5001 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5002 | int pipe = crtc->pipe; |
5003 | ||
5004 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5005 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5006 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5007 | I915_WRITE(PF_CTL(pipe), 0); |
5008 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5009 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5010 | } | |
5011 | } | |
5012 | ||
6be4a607 JB |
5013 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5014 | { | |
5015 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5016 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 | 5017 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5018 | struct intel_encoder *encoder; |
6be4a607 | 5019 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5020 | |
b2c0593a VS |
5021 | /* |
5022 | * Sometimes spurious CPU pipe underruns happen when the | |
5023 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5024 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5025 | */ | |
5026 | if (intel_crtc->config->has_pch_encoder) { | |
5027 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5028 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5029 | } |
37ca8d4c | 5030 | |
ea9d758d DV |
5031 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5032 | encoder->disable(encoder); | |
5033 | ||
f9b61ff6 DV |
5034 | drm_crtc_vblank_off(crtc); |
5035 | assert_vblank_disabled(crtc); | |
5036 | ||
575f7ab7 | 5037 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5038 | |
bfd16b2a | 5039 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5040 | |
b2c0593a | 5041 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5042 | ironlake_fdi_disable(crtc); |
5043 | ||
bf49ec8c DV |
5044 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5045 | if (encoder->post_disable) | |
5046 | encoder->post_disable(encoder); | |
2c07245f | 5047 | |
6e3c9717 | 5048 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5049 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5050 | |
d925c59a | 5051 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5052 | i915_reg_t reg; |
5053 | u32 temp; | |
5054 | ||
d925c59a DV |
5055 | /* disable TRANS_DP_CTL */ |
5056 | reg = TRANS_DP_CTL(pipe); | |
5057 | temp = I915_READ(reg); | |
5058 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5059 | TRANS_DP_PORT_SEL_MASK); | |
5060 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5061 | I915_WRITE(reg, temp); | |
5062 | ||
5063 | /* disable DPLL_SEL */ | |
5064 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5065 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5066 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5067 | } |
e3421a18 | 5068 | |
d925c59a DV |
5069 | ironlake_fdi_pll_disable(intel_crtc); |
5070 | } | |
81b088ca | 5071 | |
b2c0593a | 5072 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5073 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5074 | } |
1b3c7a47 | 5075 | |
4f771f10 | 5076 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5077 | { |
4f771f10 | 5078 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5079 | struct drm_i915_private *dev_priv = to_i915(dev); |
ee7b9f93 | 5080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5081 | struct intel_encoder *encoder; |
6e3c9717 | 5082 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5083 | |
d2d65408 VS |
5084 | if (intel_crtc->config->has_pch_encoder) |
5085 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5086 | false); | |
5087 | ||
8807e55b JN |
5088 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5089 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5090 | encoder->disable(encoder); |
8807e55b | 5091 | } |
4f771f10 | 5092 | |
f9b61ff6 DV |
5093 | drm_crtc_vblank_off(crtc); |
5094 | assert_vblank_disabled(crtc); | |
5095 | ||
4d1de975 | 5096 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5097 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5098 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5099 | |
6e3c9717 | 5100 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5101 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5102 | ||
d7edc4e5 | 5103 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5104 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5105 | |
1c132b44 | 5106 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5107 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5108 | else |
bfd16b2a | 5109 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5110 | |
d7edc4e5 | 5111 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5112 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5113 | |
97b040aa ID |
5114 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5115 | if (encoder->post_disable) | |
5116 | encoder->post_disable(encoder); | |
81b088ca | 5117 | |
92966a37 VS |
5118 | if (intel_crtc->config->has_pch_encoder) { |
5119 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5120 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5121 | intel_ddi_fdi_disable(crtc); |
5122 | ||
81b088ca VS |
5123 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5124 | true); | |
92966a37 | 5125 | } |
4f771f10 PZ |
5126 | } |
5127 | ||
2dd24552 JB |
5128 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5129 | { | |
5130 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5131 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5132 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5133 | |
681a8504 | 5134 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5135 | return; |
5136 | ||
2dd24552 | 5137 | /* |
c0b03411 DV |
5138 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5139 | * according to register description and PRM. | |
2dd24552 | 5140 | */ |
c0b03411 DV |
5141 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5142 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5143 | |
b074cec8 JB |
5144 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5145 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5146 | |
5147 | /* Border color in case we don't scale up to the full screen. Black by | |
5148 | * default, change to something else for debugging. */ | |
5149 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5150 | } |
5151 | ||
d05410f9 DA |
5152 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5153 | { | |
5154 | switch (port) { | |
5155 | case PORT_A: | |
6331a704 | 5156 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5157 | case PORT_B: |
6331a704 | 5158 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5159 | case PORT_C: |
6331a704 | 5160 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5161 | case PORT_D: |
6331a704 | 5162 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5163 | case PORT_E: |
6331a704 | 5164 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5165 | default: |
b9fec167 | 5166 | MISSING_CASE(port); |
d05410f9 DA |
5167 | return POWER_DOMAIN_PORT_OTHER; |
5168 | } | |
5169 | } | |
5170 | ||
25f78f58 VS |
5171 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5172 | { | |
5173 | switch (port) { | |
5174 | case PORT_A: | |
5175 | return POWER_DOMAIN_AUX_A; | |
5176 | case PORT_B: | |
5177 | return POWER_DOMAIN_AUX_B; | |
5178 | case PORT_C: | |
5179 | return POWER_DOMAIN_AUX_C; | |
5180 | case PORT_D: | |
5181 | return POWER_DOMAIN_AUX_D; | |
5182 | case PORT_E: | |
5183 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5184 | return POWER_DOMAIN_AUX_D; | |
5185 | default: | |
b9fec167 | 5186 | MISSING_CASE(port); |
25f78f58 VS |
5187 | return POWER_DOMAIN_AUX_A; |
5188 | } | |
5189 | } | |
5190 | ||
319be8ae ID |
5191 | enum intel_display_power_domain |
5192 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5193 | { | |
5194 | struct drm_device *dev = intel_encoder->base.dev; | |
5195 | struct intel_digital_port *intel_dig_port; | |
5196 | ||
5197 | switch (intel_encoder->type) { | |
5198 | case INTEL_OUTPUT_UNKNOWN: | |
5199 | /* Only DDI platforms should ever use this output type */ | |
5200 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
cca0502b | 5201 | case INTEL_OUTPUT_DP: |
319be8ae ID |
5202 | case INTEL_OUTPUT_HDMI: |
5203 | case INTEL_OUTPUT_EDP: | |
5204 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5205 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5206 | case INTEL_OUTPUT_DP_MST: |
5207 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5208 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5209 | case INTEL_OUTPUT_ANALOG: |
5210 | return POWER_DOMAIN_PORT_CRT; | |
5211 | case INTEL_OUTPUT_DSI: | |
5212 | return POWER_DOMAIN_PORT_DSI; | |
5213 | default: | |
5214 | return POWER_DOMAIN_PORT_OTHER; | |
5215 | } | |
5216 | } | |
5217 | ||
25f78f58 VS |
5218 | enum intel_display_power_domain |
5219 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5220 | { | |
5221 | struct drm_device *dev = intel_encoder->base.dev; | |
5222 | struct intel_digital_port *intel_dig_port; | |
5223 | ||
5224 | switch (intel_encoder->type) { | |
5225 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5226 | case INTEL_OUTPUT_HDMI: |
5227 | /* | |
5228 | * Only DDI platforms should ever use these output types. | |
5229 | * We can get here after the HDMI detect code has already set | |
5230 | * the type of the shared encoder. Since we can't be sure | |
5231 | * what's the status of the given connectors, play safe and | |
5232 | * run the DP detection too. | |
5233 | */ | |
25f78f58 | 5234 | WARN_ON_ONCE(!HAS_DDI(dev)); |
cca0502b | 5235 | case INTEL_OUTPUT_DP: |
25f78f58 VS |
5236 | case INTEL_OUTPUT_EDP: |
5237 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5238 | return port_to_aux_power_domain(intel_dig_port->port); | |
5239 | case INTEL_OUTPUT_DP_MST: | |
5240 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5241 | return port_to_aux_power_domain(intel_dig_port->port); | |
5242 | default: | |
b9fec167 | 5243 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5244 | return POWER_DOMAIN_AUX_A; |
5245 | } | |
5246 | } | |
5247 | ||
74bff5f9 ML |
5248 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5249 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5250 | { |
319be8ae | 5251 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5252 | struct drm_encoder *encoder; |
319be8ae ID |
5253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5254 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5255 | unsigned long mask; |
74bff5f9 | 5256 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5257 | |
74bff5f9 | 5258 | if (!crtc_state->base.active) |
292b990e ML |
5259 | return 0; |
5260 | ||
77d22dca ID |
5261 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5262 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5263 | if (crtc_state->pch_pfit.enabled || |
5264 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5265 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5266 | ||
74bff5f9 ML |
5267 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5268 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5269 | ||
319be8ae | 5270 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5271 | } |
319be8ae | 5272 | |
15e7ec29 ML |
5273 | if (crtc_state->shared_dpll) |
5274 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5275 | ||
77d22dca ID |
5276 | return mask; |
5277 | } | |
5278 | ||
74bff5f9 ML |
5279 | static unsigned long |
5280 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5281 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5282 | { |
fac5e23e | 5283 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5284 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5285 | enum intel_display_power_domain domain; | |
5a21b665 | 5286 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5287 | |
292b990e | 5288 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5289 | intel_crtc->enabled_power_domains = new_domains = |
5290 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5291 | |
5a21b665 | 5292 | domains = new_domains & ~old_domains; |
292b990e ML |
5293 | |
5294 | for_each_power_domain(domain, domains) | |
5295 | intel_display_power_get(dev_priv, domain); | |
5296 | ||
5a21b665 | 5297 | return old_domains & ~new_domains; |
292b990e ML |
5298 | } |
5299 | ||
5300 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5301 | unsigned long domains) | |
5302 | { | |
5303 | enum intel_display_power_domain domain; | |
5304 | ||
5305 | for_each_power_domain(domain, domains) | |
5306 | intel_display_power_put(dev_priv, domain); | |
5307 | } | |
77d22dca | 5308 | |
adafdc6f MK |
5309 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5310 | { | |
5311 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5312 | ||
5313 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5314 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5315 | return max_cdclk_freq; | |
5316 | else if (IS_CHERRYVIEW(dev_priv)) | |
5317 | return max_cdclk_freq*95/100; | |
5318 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5319 | return 2*max_cdclk_freq*90/100; | |
5320 | else | |
5321 | return max_cdclk_freq*90/100; | |
5322 | } | |
5323 | ||
b2045352 VS |
5324 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5325 | ||
560a7ae4 DL |
5326 | static void intel_update_max_cdclk(struct drm_device *dev) |
5327 | { | |
fac5e23e | 5328 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 | 5329 | |
ef11bdb3 | 5330 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 | 5331 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5332 | int max_cdclk, vco; |
5333 | ||
5334 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5335 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5336 | |
b2045352 VS |
5337 | /* |
5338 | * Use the lower (vco 8640) cdclk values as a | |
5339 | * first guess. skl_calc_cdclk() will correct it | |
5340 | * if the preferred vco is 8100 instead. | |
5341 | */ | |
560a7ae4 | 5342 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5343 | max_cdclk = 617143; |
560a7ae4 | 5344 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5345 | max_cdclk = 540000; |
560a7ae4 | 5346 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5347 | max_cdclk = 432000; |
560a7ae4 | 5348 | else |
487ed2e4 | 5349 | max_cdclk = 308571; |
b2045352 VS |
5350 | |
5351 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
281c114f MR |
5352 | } else if (IS_BROXTON(dev)) { |
5353 | dev_priv->max_cdclk_freq = 624000; | |
560a7ae4 DL |
5354 | } else if (IS_BROADWELL(dev)) { |
5355 | /* | |
5356 | * FIXME with extra cooling we can allow | |
5357 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5358 | * How can we know if extra cooling is | |
5359 | * available? PCI ID, VTB, something else? | |
5360 | */ | |
5361 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5362 | dev_priv->max_cdclk_freq = 450000; | |
5363 | else if (IS_BDW_ULX(dev)) | |
5364 | dev_priv->max_cdclk_freq = 450000; | |
5365 | else if (IS_BDW_ULT(dev)) | |
5366 | dev_priv->max_cdclk_freq = 540000; | |
5367 | else | |
5368 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5369 | } else if (IS_CHERRYVIEW(dev)) { |
5370 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5371 | } else if (IS_VALLEYVIEW(dev)) { |
5372 | dev_priv->max_cdclk_freq = 400000; | |
5373 | } else { | |
5374 | /* otherwise assume cdclk is fixed */ | |
5375 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5376 | } | |
5377 | ||
adafdc6f MK |
5378 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5379 | ||
560a7ae4 DL |
5380 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5381 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5382 | |
5383 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5384 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5385 | } |
5386 | ||
5387 | static void intel_update_cdclk(struct drm_device *dev) | |
5388 | { | |
fac5e23e | 5389 | struct drm_i915_private *dev_priv = to_i915(dev); |
560a7ae4 DL |
5390 | |
5391 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
2f2a121a | 5392 | |
83d7c81f | 5393 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5394 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5395 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5396 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5397 | else |
5398 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5399 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5400 | |
5401 | /* | |
b5d99ff9 VS |
5402 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5403 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5404 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5405 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5406 | */ |
b5d99ff9 | 5407 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5408 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5409 | } |
5410 | ||
92891e45 VS |
5411 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5412 | static int skl_cdclk_decimal(int cdclk) | |
5413 | { | |
5414 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5415 | } | |
5416 | ||
5f199dfa VS |
5417 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5418 | { | |
5419 | int ratio; | |
5420 | ||
5421 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5422 | return 0; | |
5423 | ||
5424 | switch (cdclk) { | |
5425 | default: | |
5426 | MISSING_CASE(cdclk); | |
5427 | case 144000: | |
5428 | case 288000: | |
5429 | case 384000: | |
5430 | case 576000: | |
5431 | ratio = 60; | |
5432 | break; | |
5433 | case 624000: | |
5434 | ratio = 65; | |
5435 | break; | |
5436 | } | |
5437 | ||
5438 | return dev_priv->cdclk_pll.ref * ratio; | |
5439 | } | |
5440 | ||
2b73001e VS |
5441 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5442 | { | |
5443 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5444 | ||
5445 | /* Timeout 200us */ | |
95cac283 CW |
5446 | if (intel_wait_for_register(dev_priv, |
5447 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
5448 | 1)) | |
2b73001e | 5449 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
83d7c81f VS |
5450 | |
5451 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5452 | } |
5453 | ||
5f199dfa | 5454 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5455 | { |
5f199dfa | 5456 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5457 | u32 val; |
5458 | ||
5459 | val = I915_READ(BXT_DE_PLL_CTL); | |
5460 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5461 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5462 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5463 | ||
5464 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5465 | ||
5466 | /* Timeout 200us */ | |
e084e1b9 CW |
5467 | if (intel_wait_for_register(dev_priv, |
5468 | BXT_DE_PLL_ENABLE, | |
5469 | BXT_DE_PLL_LOCK, | |
5470 | BXT_DE_PLL_LOCK, | |
5471 | 1)) | |
2b73001e | 5472 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
83d7c81f | 5473 | |
5f199dfa | 5474 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5475 | } |
5476 | ||
324513c0 | 5477 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5478 | { |
5f199dfa VS |
5479 | u32 val, divider; |
5480 | int vco, ret; | |
f8437dd1 | 5481 | |
5f199dfa VS |
5482 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
5483 | ||
5484 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5485 | ||
5486 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5487 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5488 | case 8: | |
f8437dd1 | 5489 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5490 | break; |
5f199dfa | 5491 | case 4: |
f8437dd1 | 5492 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 5493 | break; |
5f199dfa | 5494 | case 3: |
f8437dd1 | 5495 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 5496 | break; |
5f199dfa | 5497 | case 2: |
f8437dd1 | 5498 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
5499 | break; |
5500 | default: | |
5f199dfa VS |
5501 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
5502 | WARN_ON(vco != 0); | |
f8437dd1 | 5503 | |
5f199dfa VS |
5504 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
5505 | break; | |
f8437dd1 VK |
5506 | } |
5507 | ||
f8437dd1 | 5508 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 5509 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
5510 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
5511 | 0x80000000); | |
5512 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5513 | ||
5514 | if (ret) { | |
5515 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 5516 | ret, cdclk); |
f8437dd1 VK |
5517 | return; |
5518 | } | |
5519 | ||
5f199dfa VS |
5520 | if (dev_priv->cdclk_pll.vco != 0 && |
5521 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 5522 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 5523 | |
5f199dfa VS |
5524 | if (dev_priv->cdclk_pll.vco != vco) |
5525 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 5526 | |
5f199dfa VS |
5527 | val = divider | skl_cdclk_decimal(cdclk); |
5528 | /* | |
5529 | * FIXME if only the cd2x divider needs changing, it could be done | |
5530 | * without shutting off the pipe (if only one pipe is active). | |
5531 | */ | |
5532 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
5533 | /* | |
5534 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5535 | * enable otherwise. | |
5536 | */ | |
5537 | if (cdclk >= 500000) | |
5538 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5539 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
5540 | |
5541 | mutex_lock(&dev_priv->rps.hw_lock); | |
5542 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 5543 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
5544 | mutex_unlock(&dev_priv->rps.hw_lock); |
5545 | ||
5546 | if (ret) { | |
5547 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 5548 | ret, cdclk); |
f8437dd1 VK |
5549 | return; |
5550 | } | |
5551 | ||
91c8a326 | 5552 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 VK |
5553 | } |
5554 | ||
d66a2194 | 5555 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5556 | { |
d66a2194 ID |
5557 | u32 cdctl, expected; |
5558 | ||
91c8a326 | 5559 | intel_update_cdclk(&dev_priv->drm); |
f8437dd1 | 5560 | |
d66a2194 ID |
5561 | if (dev_priv->cdclk_pll.vco == 0 || |
5562 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
5563 | goto sanitize; | |
5564 | ||
5565 | /* DPLL okay; verify the cdclock | |
5566 | * | |
5567 | * Some BIOS versions leave an incorrect decimal frequency value and | |
5568 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
5569 | * so sanitize this register. | |
5570 | */ | |
5571 | cdctl = I915_READ(CDCLK_CTL); | |
5572 | /* | |
5573 | * Let's ignore the pipe field, since BIOS could have configured the | |
5574 | * dividers both synching to an active pipe, or asynchronously | |
5575 | * (PIPE_NONE). | |
5576 | */ | |
5577 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
5578 | ||
5579 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
5580 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5581 | /* | |
5582 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5583 | * enable otherwise. | |
5584 | */ | |
5585 | if (dev_priv->cdclk_freq >= 500000) | |
5586 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5587 | ||
5588 | if (cdctl == expected) | |
5589 | /* All well; nothing to sanitize */ | |
5590 | return; | |
5591 | ||
5592 | sanitize: | |
5593 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
5594 | ||
5595 | /* force cdclk programming */ | |
5596 | dev_priv->cdclk_freq = 0; | |
5597 | ||
5598 | /* force full PLL disable + enable */ | |
5599 | dev_priv->cdclk_pll.vco = -1; | |
5600 | } | |
5601 | ||
324513c0 | 5602 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 ID |
5603 | { |
5604 | bxt_sanitize_cdclk(dev_priv); | |
5605 | ||
5606 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 5607 | return; |
c2e001ef | 5608 | |
f8437dd1 VK |
5609 | /* |
5610 | * FIXME: | |
5611 | * - The initial CDCLK needs to be read from VBT. | |
5612 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 5613 | */ |
324513c0 | 5614 | bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); |
f8437dd1 VK |
5615 | } |
5616 | ||
324513c0 | 5617 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5618 | { |
324513c0 | 5619 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
5620 | } |
5621 | ||
a8ca4934 VS |
5622 | static int skl_calc_cdclk(int max_pixclk, int vco) |
5623 | { | |
63911d72 | 5624 | if (vco == 8640000) { |
a8ca4934 | 5625 | if (max_pixclk > 540000) |
487ed2e4 | 5626 | return 617143; |
a8ca4934 VS |
5627 | else if (max_pixclk > 432000) |
5628 | return 540000; | |
487ed2e4 | 5629 | else if (max_pixclk > 308571) |
a8ca4934 VS |
5630 | return 432000; |
5631 | else | |
487ed2e4 | 5632 | return 308571; |
a8ca4934 | 5633 | } else { |
a8ca4934 VS |
5634 | if (max_pixclk > 540000) |
5635 | return 675000; | |
5636 | else if (max_pixclk > 450000) | |
5637 | return 540000; | |
5638 | else if (max_pixclk > 337500) | |
5639 | return 450000; | |
5640 | else | |
5641 | return 337500; | |
5642 | } | |
5643 | } | |
5644 | ||
ea61791e VS |
5645 | static void |
5646 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 5647 | { |
ea61791e | 5648 | u32 val; |
5d96d8af | 5649 | |
709e05c3 | 5650 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 5651 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 5652 | |
ea61791e | 5653 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 5654 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 5655 | return; |
5d96d8af | 5656 | |
1c3f7700 ID |
5657 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
5658 | return; | |
9f7eb31a | 5659 | |
ea61791e VS |
5660 | val = I915_READ(DPLL_CTRL1); |
5661 | ||
1c3f7700 ID |
5662 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
5663 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5664 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
5665 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
5666 | return; | |
9f7eb31a | 5667 | |
ea61791e VS |
5668 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
5669 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
5670 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
5671 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
5672 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 5673 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
5674 | break; |
5675 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
5676 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 5677 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
5678 | break; |
5679 | default: | |
5680 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
5681 | break; |
5682 | } | |
5d96d8af DL |
5683 | } |
5684 | ||
b2045352 VS |
5685 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
5686 | { | |
5687 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
5688 | ||
5689 | dev_priv->skl_preferred_vco_freq = vco; | |
5690 | ||
5691 | if (changed) | |
91c8a326 | 5692 | intel_update_max_cdclk(&dev_priv->drm); |
b2045352 VS |
5693 | } |
5694 | ||
5d96d8af | 5695 | static void |
3861fc60 | 5696 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 5697 | { |
a8ca4934 | 5698 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
5699 | u32 val; |
5700 | ||
63911d72 | 5701 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 5702 | |
5d96d8af | 5703 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 5704 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
5705 | I915_WRITE(CDCLK_CTL, val); |
5706 | POSTING_READ(CDCLK_CTL); | |
5707 | ||
5708 | /* | |
5709 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5710 | * taking into account the VCO required to operate the eDP panel at the | |
5711 | * desired frequency. The usual DP link rates operate with a VCO of | |
5712 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5713 | * The modeset code is responsible for the selection of the exact link | |
5714 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 5715 | * works with vco. |
5d96d8af DL |
5716 | */ |
5717 | val = I915_READ(DPLL_CTRL1); | |
5718 | ||
5719 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5720 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5721 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 5722 | if (vco == 8640000) |
5d96d8af DL |
5723 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
5724 | SKL_DPLL0); | |
5725 | else | |
5726 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5727 | SKL_DPLL0); | |
5728 | ||
5729 | I915_WRITE(DPLL_CTRL1, val); | |
5730 | POSTING_READ(DPLL_CTRL1); | |
5731 | ||
5732 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5733 | ||
e24ca054 CW |
5734 | if (intel_wait_for_register(dev_priv, |
5735 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
5736 | 5)) | |
5d96d8af | 5737 | DRM_ERROR("DPLL0 not locked\n"); |
1cd593e0 | 5738 | |
63911d72 | 5739 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
5740 | |
5741 | /* We'll want to keep using the current vco from now on. */ | |
5742 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
5743 | } |
5744 | ||
430e05de VS |
5745 | static void |
5746 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
5747 | { | |
5748 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
8ad32a05 CW |
5749 | if (intel_wait_for_register(dev_priv, |
5750 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
5751 | 1)) | |
430e05de | 5752 | DRM_ERROR("Couldn't disable DPLL0\n"); |
1cd593e0 | 5753 | |
63911d72 | 5754 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
5755 | } |
5756 | ||
5d96d8af DL |
5757 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
5758 | { | |
5759 | int ret; | |
5760 | u32 val; | |
5761 | ||
5762 | /* inform PCU we want to change CDCLK */ | |
5763 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5764 | mutex_lock(&dev_priv->rps.hw_lock); | |
5765 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5766 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5767 | ||
5768 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5769 | } | |
5770 | ||
5771 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5772 | { | |
848496e5 | 5773 | return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0; |
5d96d8af DL |
5774 | } |
5775 | ||
1cd593e0 | 5776 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af | 5777 | { |
91c8a326 | 5778 | struct drm_device *dev = &dev_priv->drm; |
5d96d8af DL |
5779 | u32 freq_select, pcu_ack; |
5780 | ||
1cd593e0 VS |
5781 | WARN_ON((cdclk == 24000) != (vco == 0)); |
5782 | ||
63911d72 | 5783 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
5784 | |
5785 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5786 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5787 | return; | |
5788 | } | |
5789 | ||
5790 | /* set CDCLK_CTL */ | |
9ef56154 | 5791 | switch (cdclk) { |
5d96d8af DL |
5792 | case 450000: |
5793 | case 432000: | |
5794 | freq_select = CDCLK_FREQ_450_432; | |
5795 | pcu_ack = 1; | |
5796 | break; | |
5797 | case 540000: | |
5798 | freq_select = CDCLK_FREQ_540; | |
5799 | pcu_ack = 2; | |
5800 | break; | |
487ed2e4 | 5801 | case 308571: |
5d96d8af DL |
5802 | case 337500: |
5803 | default: | |
5804 | freq_select = CDCLK_FREQ_337_308; | |
5805 | pcu_ack = 0; | |
5806 | break; | |
487ed2e4 | 5807 | case 617143: |
5d96d8af DL |
5808 | case 675000: |
5809 | freq_select = CDCLK_FREQ_675_617; | |
5810 | pcu_ack = 3; | |
5811 | break; | |
5812 | } | |
5813 | ||
63911d72 VS |
5814 | if (dev_priv->cdclk_pll.vco != 0 && |
5815 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
5816 | skl_dpll0_disable(dev_priv); |
5817 | ||
63911d72 | 5818 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
5819 | skl_dpll0_enable(dev_priv, vco); |
5820 | ||
9ef56154 | 5821 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
5822 | POSTING_READ(CDCLK_CTL); |
5823 | ||
5824 | /* inform PCU of the change */ | |
5825 | mutex_lock(&dev_priv->rps.hw_lock); | |
5826 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5827 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5828 | |
5829 | intel_update_cdclk(dev); | |
5d96d8af DL |
5830 | } |
5831 | ||
9f7eb31a VS |
5832 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
5833 | ||
5d96d8af DL |
5834 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
5835 | { | |
709e05c3 | 5836 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
5837 | } |
5838 | ||
5839 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5840 | { | |
9f7eb31a VS |
5841 | int cdclk, vco; |
5842 | ||
5843 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 5844 | |
63911d72 | 5845 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
5846 | /* |
5847 | * Use the current vco as our initial | |
5848 | * guess as to what the preferred vco is. | |
5849 | */ | |
5850 | if (dev_priv->skl_preferred_vco_freq == 0) | |
5851 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 5852 | dev_priv->cdclk_pll.vco); |
70c2c184 | 5853 | return; |
1cd593e0 | 5854 | } |
5d96d8af | 5855 | |
70c2c184 VS |
5856 | vco = dev_priv->skl_preferred_vco_freq; |
5857 | if (vco == 0) | |
63911d72 | 5858 | vco = 8100000; |
70c2c184 | 5859 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 5860 | |
70c2c184 | 5861 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
5862 | } |
5863 | ||
9f7eb31a | 5864 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 5865 | { |
09492498 | 5866 | uint32_t cdctl, expected; |
c73666f3 | 5867 | |
f1b391a5 SK |
5868 | /* |
5869 | * check if the pre-os intialized the display | |
5870 | * There is SWF18 scratchpad register defined which is set by the | |
5871 | * pre-os which can be used by the OS drivers to check the status | |
5872 | */ | |
5873 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5874 | goto sanitize; | |
5875 | ||
91c8a326 | 5876 | intel_update_cdclk(&dev_priv->drm); |
c73666f3 | 5877 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
5878 | if (dev_priv->cdclk_pll.vco == 0 || |
5879 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
5880 | goto sanitize; |
5881 | ||
5882 | /* DPLL okay; verify the cdclock | |
5883 | * | |
5884 | * Noticed in some instances that the freq selection is correct but | |
5885 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5886 | * enable display. Verify the same as well. | |
5887 | */ | |
09492498 VS |
5888 | cdctl = I915_READ(CDCLK_CTL); |
5889 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
5890 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
5891 | if (cdctl == expected) | |
c73666f3 | 5892 | /* All well; nothing to sanitize */ |
9f7eb31a | 5893 | return; |
c89e39f3 | 5894 | |
9f7eb31a VS |
5895 | sanitize: |
5896 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 5897 | |
9f7eb31a VS |
5898 | /* force cdclk programming */ |
5899 | dev_priv->cdclk_freq = 0; | |
5900 | /* force full PLL disable + enable */ | |
63911d72 | 5901 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
5902 | } |
5903 | ||
30a970c6 JB |
5904 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5905 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5906 | { | |
fac5e23e | 5907 | struct drm_i915_private *dev_priv = to_i915(dev); |
30a970c6 JB |
5908 | u32 val, cmd; |
5909 | ||
164dfd28 VK |
5910 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5911 | != dev_priv->cdclk_freq); | |
d60c4473 | 5912 | |
dfcab17e | 5913 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5914 | cmd = 2; |
dfcab17e | 5915 | else if (cdclk == 266667) |
30a970c6 JB |
5916 | cmd = 1; |
5917 | else | |
5918 | cmd = 0; | |
5919 | ||
5920 | mutex_lock(&dev_priv->rps.hw_lock); | |
5921 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5922 | val &= ~DSPFREQGUAR_MASK; | |
5923 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5924 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5925 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5926 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5927 | 50)) { | |
5928 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5929 | } | |
5930 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5931 | ||
54433e91 VS |
5932 | mutex_lock(&dev_priv->sb_lock); |
5933 | ||
dfcab17e | 5934 | if (cdclk == 400000) { |
6bcda4f0 | 5935 | u32 divider; |
30a970c6 | 5936 | |
6bcda4f0 | 5937 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5938 | |
30a970c6 JB |
5939 | /* adjust cdclk divider */ |
5940 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5941 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5942 | val |= divider; |
5943 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5944 | |
5945 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5946 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5947 | 50)) |
5948 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5949 | } |
5950 | ||
30a970c6 JB |
5951 | /* adjust self-refresh exit latency value */ |
5952 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5953 | val &= ~0x7f; | |
5954 | ||
5955 | /* | |
5956 | * For high bandwidth configs, we set a higher latency in the bunit | |
5957 | * so that the core display fetch happens in time to avoid underruns. | |
5958 | */ | |
dfcab17e | 5959 | if (cdclk == 400000) |
30a970c6 JB |
5960 | val |= 4500 / 250; /* 4.5 usec */ |
5961 | else | |
5962 | val |= 3000 / 250; /* 3.0 usec */ | |
5963 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5964 | |
a580516d | 5965 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5966 | |
b6283055 | 5967 | intel_update_cdclk(dev); |
30a970c6 JB |
5968 | } |
5969 | ||
383c5a6a VS |
5970 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5971 | { | |
fac5e23e | 5972 | struct drm_i915_private *dev_priv = to_i915(dev); |
383c5a6a VS |
5973 | u32 val, cmd; |
5974 | ||
164dfd28 VK |
5975 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5976 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5977 | |
5978 | switch (cdclk) { | |
383c5a6a VS |
5979 | case 333333: |
5980 | case 320000: | |
383c5a6a | 5981 | case 266667: |
383c5a6a | 5982 | case 200000: |
383c5a6a VS |
5983 | break; |
5984 | default: | |
5f77eeb0 | 5985 | MISSING_CASE(cdclk); |
383c5a6a VS |
5986 | return; |
5987 | } | |
5988 | ||
9d0d3fda VS |
5989 | /* |
5990 | * Specs are full of misinformation, but testing on actual | |
5991 | * hardware has shown that we just need to write the desired | |
5992 | * CCK divider into the Punit register. | |
5993 | */ | |
5994 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5995 | ||
383c5a6a VS |
5996 | mutex_lock(&dev_priv->rps.hw_lock); |
5997 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5998 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5999 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6000 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6001 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6002 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6003 | 50)) { | |
6004 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6005 | } | |
6006 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6007 | ||
b6283055 | 6008 | intel_update_cdclk(dev); |
383c5a6a VS |
6009 | } |
6010 | ||
30a970c6 JB |
6011 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6012 | int max_pixclk) | |
6013 | { | |
6bcda4f0 | 6014 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6015 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6016 | |
30a970c6 JB |
6017 | /* |
6018 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6019 | * 200MHz | |
6020 | * 267MHz | |
29dc7ef3 | 6021 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6022 | * 400MHz (VLV only) |
6023 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6024 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6025 | * |
6026 | * We seem to get an unstable or solid color picture at 200MHz. | |
6027 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6028 | * are off. | |
30a970c6 | 6029 | */ |
6cca3195 VS |
6030 | if (!IS_CHERRYVIEW(dev_priv) && |
6031 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6032 | return 400000; |
6cca3195 | 6033 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6034 | return freq_320; |
e37c67a1 | 6035 | else if (max_pixclk > 0) |
dfcab17e | 6036 | return 266667; |
e37c67a1 VS |
6037 | else |
6038 | return 200000; | |
30a970c6 JB |
6039 | } |
6040 | ||
324513c0 | 6041 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 6042 | { |
760e1477 | 6043 | if (max_pixclk > 576000) |
f8437dd1 | 6044 | return 624000; |
760e1477 | 6045 | else if (max_pixclk > 384000) |
f8437dd1 | 6046 | return 576000; |
760e1477 | 6047 | else if (max_pixclk > 288000) |
f8437dd1 | 6048 | return 384000; |
760e1477 | 6049 | else if (max_pixclk > 144000) |
f8437dd1 VK |
6050 | return 288000; |
6051 | else | |
6052 | return 144000; | |
6053 | } | |
6054 | ||
e8788cbc | 6055 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6056 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6057 | struct drm_atomic_state *state) | |
30a970c6 | 6058 | { |
565602d7 | 6059 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 6060 | struct drm_i915_private *dev_priv = to_i915(dev); |
565602d7 ML |
6061 | struct drm_crtc *crtc; |
6062 | struct drm_crtc_state *crtc_state; | |
6063 | unsigned max_pixclk = 0, i; | |
6064 | enum pipe pipe; | |
30a970c6 | 6065 | |
565602d7 ML |
6066 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6067 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6068 | |
565602d7 ML |
6069 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6070 | int pixclk = 0; | |
6071 | ||
6072 | if (crtc_state->enable) | |
6073 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6074 | |
565602d7 | 6075 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6076 | } |
6077 | ||
565602d7 ML |
6078 | for_each_pipe(dev_priv, pipe) |
6079 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6080 | ||
30a970c6 JB |
6081 | return max_pixclk; |
6082 | } | |
6083 | ||
27c329ed | 6084 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6085 | { |
27c329ed | 6086 | struct drm_device *dev = state->dev; |
fac5e23e | 6087 | struct drm_i915_private *dev_priv = to_i915(dev); |
27c329ed | 6088 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
6089 | struct intel_atomic_state *intel_state = |
6090 | to_intel_atomic_state(state); | |
30a970c6 | 6091 | |
1a617b77 | 6092 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6093 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6094 | |
1a617b77 ML |
6095 | if (!intel_state->active_crtcs) |
6096 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6097 | ||
27c329ed ML |
6098 | return 0; |
6099 | } | |
304603f4 | 6100 | |
324513c0 | 6101 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6102 | { |
4e5ca60f | 6103 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6104 | struct intel_atomic_state *intel_state = |
6105 | to_intel_atomic_state(state); | |
85a96e7a | 6106 | |
1a617b77 | 6107 | intel_state->cdclk = intel_state->dev_cdclk = |
324513c0 | 6108 | bxt_calc_cdclk(max_pixclk); |
85a96e7a | 6109 | |
1a617b77 | 6110 | if (!intel_state->active_crtcs) |
324513c0 | 6111 | intel_state->dev_cdclk = bxt_calc_cdclk(0); |
1a617b77 | 6112 | |
27c329ed | 6113 | return 0; |
30a970c6 JB |
6114 | } |
6115 | ||
1e69cd74 VS |
6116 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6117 | { | |
6118 | unsigned int credits, default_credits; | |
6119 | ||
6120 | if (IS_CHERRYVIEW(dev_priv)) | |
6121 | default_credits = PFI_CREDIT(12); | |
6122 | else | |
6123 | default_credits = PFI_CREDIT(8); | |
6124 | ||
bfa7df01 | 6125 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6126 | /* CHV suggested value is 31 or 63 */ |
6127 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6128 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6129 | else |
6130 | credits = PFI_CREDIT(15); | |
6131 | } else { | |
6132 | credits = default_credits; | |
6133 | } | |
6134 | ||
6135 | /* | |
6136 | * WA - write default credits before re-programming | |
6137 | * FIXME: should we also set the resend bit here? | |
6138 | */ | |
6139 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6140 | default_credits); | |
6141 | ||
6142 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6143 | credits | PFI_CREDIT_RESEND); | |
6144 | ||
6145 | /* | |
6146 | * FIXME is this guaranteed to clear | |
6147 | * immediately or should we poll for it? | |
6148 | */ | |
6149 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6150 | } | |
6151 | ||
27c329ed | 6152 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6153 | { |
a821fc46 | 6154 | struct drm_device *dev = old_state->dev; |
fac5e23e | 6155 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 ML |
6156 | struct intel_atomic_state *old_intel_state = |
6157 | to_intel_atomic_state(old_state); | |
6158 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6159 | |
27c329ed ML |
6160 | /* |
6161 | * FIXME: We can end up here with all power domains off, yet | |
6162 | * with a CDCLK frequency other than the minimum. To account | |
6163 | * for this take the PIPE-A power domain, which covers the HW | |
6164 | * blocks needed for the following programming. This can be | |
6165 | * removed once it's guaranteed that we get here either with | |
6166 | * the minimum CDCLK set, or the required power domains | |
6167 | * enabled. | |
6168 | */ | |
6169 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6170 | |
27c329ed ML |
6171 | if (IS_CHERRYVIEW(dev)) |
6172 | cherryview_set_cdclk(dev, req_cdclk); | |
6173 | else | |
6174 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6175 | |
27c329ed | 6176 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6177 | |
27c329ed | 6178 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6179 | } |
6180 | ||
89b667f8 JB |
6181 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6182 | { | |
6183 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6184 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6185 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6186 | struct intel_encoder *encoder; | |
b95c5321 ML |
6187 | struct intel_crtc_state *pipe_config = |
6188 | to_intel_crtc_state(crtc->state); | |
89b667f8 | 6189 | int pipe = intel_crtc->pipe; |
89b667f8 | 6190 | |
53d9f4e9 | 6191 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6192 | return; |
6193 | ||
37a5650b | 6194 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6195 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6196 | |
6197 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6198 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6199 | |
c14b0485 | 6200 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
fac5e23e | 6201 | struct drm_i915_private *dev_priv = to_i915(dev); |
c14b0485 VS |
6202 | |
6203 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6204 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6205 | } | |
6206 | ||
5b18e57c DV |
6207 | i9xx_set_pipeconf(intel_crtc); |
6208 | ||
89b667f8 | 6209 | intel_crtc->active = true; |
89b667f8 | 6210 | |
a72e4c9f | 6211 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6212 | |
89b667f8 JB |
6213 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6214 | if (encoder->pre_pll_enable) | |
6215 | encoder->pre_pll_enable(encoder); | |
6216 | ||
cd2d34d9 VS |
6217 | if (IS_CHERRYVIEW(dev)) { |
6218 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6219 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6220 | } else { | |
6221 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6222 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6223 | } |
89b667f8 JB |
6224 | |
6225 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6226 | if (encoder->pre_enable) | |
6227 | encoder->pre_enable(encoder); | |
6228 | ||
2dd24552 JB |
6229 | i9xx_pfit_enable(intel_crtc); |
6230 | ||
b95c5321 | 6231 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6232 | |
caed361d | 6233 | intel_update_watermarks(crtc); |
e1fdc473 | 6234 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6235 | |
4b3a9526 VS |
6236 | assert_vblank_disabled(crtc); |
6237 | drm_crtc_vblank_on(crtc); | |
6238 | ||
f9b61ff6 DV |
6239 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6240 | encoder->enable(encoder); | |
89b667f8 JB |
6241 | } |
6242 | ||
f13c2ef3 DV |
6243 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6244 | { | |
6245 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6246 | struct drm_i915_private *dev_priv = to_i915(dev); |
f13c2ef3 | 6247 | |
6e3c9717 ACO |
6248 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6249 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6250 | } |
6251 | ||
0b8765c6 | 6252 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6253 | { |
6254 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6255 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6256 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6257 | struct intel_encoder *encoder; |
b95c5321 ML |
6258 | struct intel_crtc_state *pipe_config = |
6259 | to_intel_crtc_state(crtc->state); | |
cd2d34d9 | 6260 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6261 | |
53d9f4e9 | 6262 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6263 | return; |
6264 | ||
f13c2ef3 DV |
6265 | i9xx_set_pll_dividers(intel_crtc); |
6266 | ||
37a5650b | 6267 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6268 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6269 | |
6270 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6271 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6272 | |
5b18e57c DV |
6273 | i9xx_set_pipeconf(intel_crtc); |
6274 | ||
f7abfe8b | 6275 | intel_crtc->active = true; |
6b383a7f | 6276 | |
4a3436e8 | 6277 | if (!IS_GEN2(dev)) |
a72e4c9f | 6278 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6279 | |
9d6d9f19 MK |
6280 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6281 | if (encoder->pre_enable) | |
6282 | encoder->pre_enable(encoder); | |
6283 | ||
f6736a1a DV |
6284 | i9xx_enable_pll(intel_crtc); |
6285 | ||
2dd24552 JB |
6286 | i9xx_pfit_enable(intel_crtc); |
6287 | ||
b95c5321 | 6288 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6289 | |
f37fcc2a | 6290 | intel_update_watermarks(crtc); |
e1fdc473 | 6291 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6292 | |
4b3a9526 VS |
6293 | assert_vblank_disabled(crtc); |
6294 | drm_crtc_vblank_on(crtc); | |
6295 | ||
f9b61ff6 DV |
6296 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6297 | encoder->enable(encoder); | |
0b8765c6 | 6298 | } |
79e53945 | 6299 | |
87476d63 DV |
6300 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6301 | { | |
6302 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6303 | struct drm_i915_private *dev_priv = to_i915(dev); |
87476d63 | 6304 | |
6e3c9717 | 6305 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6306 | return; |
87476d63 | 6307 | |
328d8e82 | 6308 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6309 | |
328d8e82 DV |
6310 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6311 | I915_READ(PFIT_CONTROL)); | |
6312 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6313 | } |
6314 | ||
0b8765c6 JB |
6315 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6316 | { | |
6317 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 6318 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b8765c6 | 6319 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6320 | struct intel_encoder *encoder; |
0b8765c6 | 6321 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6322 | |
6304cd91 VS |
6323 | /* |
6324 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6325 | * wait for planes to fully turn off before disabling the pipe. | |
6326 | */ | |
90e83e53 ACO |
6327 | if (IS_GEN2(dev)) |
6328 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6329 | |
4b3a9526 VS |
6330 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6331 | encoder->disable(encoder); | |
6332 | ||
f9b61ff6 DV |
6333 | drm_crtc_vblank_off(crtc); |
6334 | assert_vblank_disabled(crtc); | |
6335 | ||
575f7ab7 | 6336 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6337 | |
87476d63 | 6338 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6339 | |
89b667f8 JB |
6340 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6341 | if (encoder->post_disable) | |
6342 | encoder->post_disable(encoder); | |
6343 | ||
d7edc4e5 | 6344 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6345 | if (IS_CHERRYVIEW(dev)) |
6346 | chv_disable_pll(dev_priv, pipe); | |
6347 | else if (IS_VALLEYVIEW(dev)) | |
6348 | vlv_disable_pll(dev_priv, pipe); | |
6349 | else | |
1c4e0274 | 6350 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6351 | } |
0b8765c6 | 6352 | |
d6db995f VS |
6353 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6354 | if (encoder->post_pll_disable) | |
6355 | encoder->post_pll_disable(encoder); | |
6356 | ||
4a3436e8 | 6357 | if (!IS_GEN2(dev)) |
a72e4c9f | 6358 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6359 | } |
6360 | ||
b17d48e2 ML |
6361 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6362 | { | |
842e0307 | 6363 | struct intel_encoder *encoder; |
b17d48e2 ML |
6364 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6365 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6366 | enum intel_display_power_domain domain; | |
6367 | unsigned long domains; | |
6368 | ||
6369 | if (!intel_crtc->active) | |
6370 | return; | |
6371 | ||
a539205a | 6372 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
5a21b665 | 6373 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6374 | |
2622a081 | 6375 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6376 | |
6377 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6378 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6379 | } |
6380 | ||
b17d48e2 | 6381 | dev_priv->display.crtc_disable(crtc); |
842e0307 | 6382 | |
78108b7c VS |
6383 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6384 | crtc->base.id, crtc->name); | |
842e0307 ML |
6385 | |
6386 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6387 | crtc->state->active = false; | |
37d9078b | 6388 | intel_crtc->active = false; |
842e0307 ML |
6389 | crtc->enabled = false; |
6390 | crtc->state->connector_mask = 0; | |
6391 | crtc->state->encoder_mask = 0; | |
6392 | ||
6393 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6394 | encoder->base.crtc = NULL; | |
6395 | ||
58f9c0bc | 6396 | intel_fbc_disable(intel_crtc); |
37d9078b | 6397 | intel_update_watermarks(crtc); |
1f7457b1 | 6398 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6399 | |
6400 | domains = intel_crtc->enabled_power_domains; | |
6401 | for_each_power_domain(domain, domains) | |
6402 | intel_display_power_put(dev_priv, domain); | |
6403 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6404 | |
6405 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6406 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6407 | } |
6408 | ||
6b72d486 ML |
6409 | /* |
6410 | * turn all crtc's off, but do not adjust state | |
6411 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6412 | */ | |
70e0bd74 | 6413 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6414 | { |
e2c8b870 | 6415 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6416 | struct drm_atomic_state *state; |
e2c8b870 | 6417 | int ret; |
70e0bd74 | 6418 | |
e2c8b870 ML |
6419 | state = drm_atomic_helper_suspend(dev); |
6420 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6421 | if (ret) |
6422 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6423 | else |
6424 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6425 | return ret; |
ee7b9f93 JB |
6426 | } |
6427 | ||
ea5b213a | 6428 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6429 | { |
4ef69c7a | 6430 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6431 | |
ea5b213a CW |
6432 | drm_encoder_cleanup(encoder); |
6433 | kfree(intel_encoder); | |
7e7d76c3 JB |
6434 | } |
6435 | ||
0a91ca29 DV |
6436 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6437 | * internal consistency). */ | |
5a21b665 | 6438 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6439 | { |
5a21b665 | 6440 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6441 | |
6442 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6443 | connector->base.base.id, | |
6444 | connector->base.name); | |
6445 | ||
0a91ca29 | 6446 | if (connector->get_hw_state(connector)) { |
e85376cb | 6447 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6448 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6449 | |
35dd3c64 ML |
6450 | I915_STATE_WARN(!crtc, |
6451 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6452 | |
35dd3c64 ML |
6453 | if (!crtc) |
6454 | return; | |
6455 | ||
6456 | I915_STATE_WARN(!crtc->state->active, | |
6457 | "connector is active, but attached crtc isn't\n"); | |
6458 | ||
e85376cb | 6459 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6460 | return; |
6461 | ||
e85376cb | 6462 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6463 | "atomic encoder doesn't match attached encoder\n"); |
6464 | ||
e85376cb | 6465 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6466 | "attached encoder crtc differs from connector crtc\n"); |
6467 | } else { | |
4d688a2a ML |
6468 | I915_STATE_WARN(crtc && crtc->state->active, |
6469 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 6470 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 6471 | "best encoder set without crtc!\n"); |
0a91ca29 | 6472 | } |
79e53945 JB |
6473 | } |
6474 | ||
08d9bc92 ACO |
6475 | int intel_connector_init(struct intel_connector *connector) |
6476 | { | |
5350a031 | 6477 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6478 | |
5350a031 | 6479 | if (!connector->base.state) |
08d9bc92 ACO |
6480 | return -ENOMEM; |
6481 | ||
08d9bc92 ACO |
6482 | return 0; |
6483 | } | |
6484 | ||
6485 | struct intel_connector *intel_connector_alloc(void) | |
6486 | { | |
6487 | struct intel_connector *connector; | |
6488 | ||
6489 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6490 | if (!connector) | |
6491 | return NULL; | |
6492 | ||
6493 | if (intel_connector_init(connector) < 0) { | |
6494 | kfree(connector); | |
6495 | return NULL; | |
6496 | } | |
6497 | ||
6498 | return connector; | |
6499 | } | |
6500 | ||
f0947c37 DV |
6501 | /* Simple connector->get_hw_state implementation for encoders that support only |
6502 | * one connector and no cloning and hence the encoder state determines the state | |
6503 | * of the connector. */ | |
6504 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6505 | { |
24929352 | 6506 | enum pipe pipe = 0; |
f0947c37 | 6507 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6508 | |
f0947c37 | 6509 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6510 | } |
6511 | ||
6d293983 | 6512 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6513 | { |
6d293983 ACO |
6514 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6515 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6516 | |
6517 | return 0; | |
6518 | } | |
6519 | ||
6d293983 | 6520 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6521 | struct intel_crtc_state *pipe_config) |
1857e1da | 6522 | { |
6d293983 ACO |
6523 | struct drm_atomic_state *state = pipe_config->base.state; |
6524 | struct intel_crtc *other_crtc; | |
6525 | struct intel_crtc_state *other_crtc_state; | |
6526 | ||
1857e1da DV |
6527 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6528 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6529 | if (pipe_config->fdi_lanes > 4) { | |
6530 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6531 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6532 | return -EINVAL; |
1857e1da DV |
6533 | } |
6534 | ||
bafb6553 | 6535 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6536 | if (pipe_config->fdi_lanes > 2) { |
6537 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6538 | pipe_config->fdi_lanes); | |
6d293983 | 6539 | return -EINVAL; |
1857e1da | 6540 | } else { |
6d293983 | 6541 | return 0; |
1857e1da DV |
6542 | } |
6543 | } | |
6544 | ||
6545 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6546 | return 0; |
1857e1da DV |
6547 | |
6548 | /* Ivybridge 3 pipe is really complicated */ | |
6549 | switch (pipe) { | |
6550 | case PIPE_A: | |
6d293983 | 6551 | return 0; |
1857e1da | 6552 | case PIPE_B: |
6d293983 ACO |
6553 | if (pipe_config->fdi_lanes <= 2) |
6554 | return 0; | |
6555 | ||
6556 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6557 | other_crtc_state = | |
6558 | intel_atomic_get_crtc_state(state, other_crtc); | |
6559 | if (IS_ERR(other_crtc_state)) | |
6560 | return PTR_ERR(other_crtc_state); | |
6561 | ||
6562 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6563 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6564 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6565 | return -EINVAL; |
1857e1da | 6566 | } |
6d293983 | 6567 | return 0; |
1857e1da | 6568 | case PIPE_C: |
251cc67c VS |
6569 | if (pipe_config->fdi_lanes > 2) { |
6570 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6571 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6572 | return -EINVAL; |
251cc67c | 6573 | } |
6d293983 ACO |
6574 | |
6575 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6576 | other_crtc_state = | |
6577 | intel_atomic_get_crtc_state(state, other_crtc); | |
6578 | if (IS_ERR(other_crtc_state)) | |
6579 | return PTR_ERR(other_crtc_state); | |
6580 | ||
6581 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6582 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6583 | return -EINVAL; |
1857e1da | 6584 | } |
6d293983 | 6585 | return 0; |
1857e1da DV |
6586 | default: |
6587 | BUG(); | |
6588 | } | |
6589 | } | |
6590 | ||
e29c22c0 DV |
6591 | #define RETRY 1 |
6592 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6593 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6594 | { |
1857e1da | 6595 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6596 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6597 | int lane, link_bw, fdi_dotclock, ret; |
6598 | bool needs_recompute = false; | |
877d48d5 | 6599 | |
e29c22c0 | 6600 | retry: |
877d48d5 DV |
6601 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6602 | * each output octet as 10 bits. The actual frequency | |
6603 | * is stored as a divider into a 100MHz clock, and the | |
6604 | * mode pixel clock is stored in units of 1KHz. | |
6605 | * Hence the bw of each lane in terms of the mode signal | |
6606 | * is: | |
6607 | */ | |
21a727b3 | 6608 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6609 | |
241bfc38 | 6610 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6611 | |
2bd89a07 | 6612 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6613 | pipe_config->pipe_bpp); |
6614 | ||
6615 | pipe_config->fdi_lanes = lane; | |
6616 | ||
2bd89a07 | 6617 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6618 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6619 | |
e3b247da | 6620 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6621 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6622 | pipe_config->pipe_bpp -= 2*3; |
6623 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6624 | pipe_config->pipe_bpp); | |
6625 | needs_recompute = true; | |
6626 | pipe_config->bw_constrained = true; | |
6627 | ||
6628 | goto retry; | |
6629 | } | |
6630 | ||
6631 | if (needs_recompute) | |
6632 | return RETRY; | |
6633 | ||
6d293983 | 6634 | return ret; |
877d48d5 DV |
6635 | } |
6636 | ||
8cfb3407 VS |
6637 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6638 | struct intel_crtc_state *pipe_config) | |
6639 | { | |
6640 | if (pipe_config->pipe_bpp > 24) | |
6641 | return false; | |
6642 | ||
6643 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 6644 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
6645 | return true; |
6646 | ||
6647 | /* | |
b432e5cf VS |
6648 | * We compare against max which means we must take |
6649 | * the increased cdclk requirement into account when | |
6650 | * calculating the new cdclk. | |
6651 | * | |
6652 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6653 | */ |
6654 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6655 | dev_priv->max_cdclk_freq * 95 / 100; | |
6656 | } | |
6657 | ||
42db64ef | 6658 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6659 | struct intel_crtc_state *pipe_config) |
42db64ef | 6660 | { |
8cfb3407 | 6661 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6662 | struct drm_i915_private *dev_priv = to_i915(dev); |
8cfb3407 | 6663 | |
d330a953 | 6664 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6665 | hsw_crtc_supports_ips(crtc) && |
6666 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6667 | } |
6668 | ||
39acb4aa VS |
6669 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6670 | { | |
6671 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6672 | ||
6673 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6674 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6675 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6676 | } | |
6677 | ||
a43f6e0f | 6678 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6679 | struct intel_crtc_state *pipe_config) |
79e53945 | 6680 | { |
a43f6e0f | 6681 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6682 | struct drm_i915_private *dev_priv = to_i915(dev); |
7c5f93b0 | 6683 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 6684 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 6685 | |
cf532bb2 | 6686 | if (INTEL_INFO(dev)->gen < 4) { |
f3261156 | 6687 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6688 | |
6689 | /* | |
39acb4aa | 6690 | * Enable double wide mode when the dot clock |
cf532bb2 | 6691 | * is > 90% of the (display) core speed. |
cf532bb2 | 6692 | */ |
39acb4aa VS |
6693 | if (intel_crtc_supports_double_wide(crtc) && |
6694 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 6695 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 6696 | pipe_config->double_wide = true; |
ad3a4479 | 6697 | } |
f3261156 | 6698 | } |
ad3a4479 | 6699 | |
f3261156 VS |
6700 | if (adjusted_mode->crtc_clock > clock_limit) { |
6701 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6702 | adjusted_mode->crtc_clock, clock_limit, | |
6703 | yesno(pipe_config->double_wide)); | |
6704 | return -EINVAL; | |
2c07245f | 6705 | } |
89749350 | 6706 | |
1d1d0e27 VS |
6707 | /* |
6708 | * Pipe horizontal size must be even in: | |
6709 | * - DVO ganged mode | |
6710 | * - LVDS dual channel mode | |
6711 | * - Double wide pipe | |
6712 | */ | |
2d84d2b3 | 6713 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6714 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6715 | pipe_config->pipe_src_w &= ~1; | |
6716 | ||
8693a824 DL |
6717 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6718 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6719 | */ |
6720 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6721 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6722 | return -EINVAL; |
44f46b42 | 6723 | |
f5adf94e | 6724 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6725 | hsw_compute_ips_config(crtc, pipe_config); |
6726 | ||
877d48d5 | 6727 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6728 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6729 | |
cf5a15be | 6730 | return 0; |
79e53945 JB |
6731 | } |
6732 | ||
1652d19e VS |
6733 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6734 | { | |
6735 | struct drm_i915_private *dev_priv = to_i915(dev); | |
ea61791e | 6736 | uint32_t cdctl; |
1652d19e | 6737 | |
ea61791e | 6738 | skl_dpll0_update(dev_priv); |
1652d19e | 6739 | |
63911d72 | 6740 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 6741 | return dev_priv->cdclk_pll.ref; |
1652d19e | 6742 | |
ea61791e | 6743 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 6744 | |
63911d72 | 6745 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
6746 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6747 | case CDCLK_FREQ_450_432: | |
6748 | return 432000; | |
6749 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 6750 | return 308571; |
ea61791e VS |
6751 | case CDCLK_FREQ_540: |
6752 | return 540000; | |
1652d19e | 6753 | case CDCLK_FREQ_675_617: |
487ed2e4 | 6754 | return 617143; |
1652d19e | 6755 | default: |
ea61791e | 6756 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6757 | } |
6758 | } else { | |
1652d19e VS |
6759 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
6760 | case CDCLK_FREQ_450_432: | |
6761 | return 450000; | |
6762 | case CDCLK_FREQ_337_308: | |
6763 | return 337500; | |
ea61791e VS |
6764 | case CDCLK_FREQ_540: |
6765 | return 540000; | |
1652d19e VS |
6766 | case CDCLK_FREQ_675_617: |
6767 | return 675000; | |
6768 | default: | |
ea61791e | 6769 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
6770 | } |
6771 | } | |
6772 | ||
709e05c3 | 6773 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
6774 | } |
6775 | ||
83d7c81f VS |
6776 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
6777 | { | |
6778 | u32 val; | |
6779 | ||
6780 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 6781 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
6782 | |
6783 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 6784 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 6785 | return; |
83d7c81f | 6786 | |
1c3f7700 ID |
6787 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
6788 | return; | |
83d7c81f VS |
6789 | |
6790 | val = I915_READ(BXT_DE_PLL_CTL); | |
6791 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
6792 | dev_priv->cdclk_pll.ref; | |
6793 | } | |
6794 | ||
acd3f3d3 BP |
6795 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6796 | { | |
6797 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f5986242 VS |
6798 | u32 divider; |
6799 | int div, vco; | |
acd3f3d3 | 6800 | |
83d7c81f VS |
6801 | bxt_de_pll_update(dev_priv); |
6802 | ||
f5986242 VS |
6803 | vco = dev_priv->cdclk_pll.vco; |
6804 | if (vco == 0) | |
6805 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 6806 | |
f5986242 | 6807 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 6808 | |
f5986242 | 6809 | switch (divider) { |
acd3f3d3 | 6810 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
6811 | div = 2; |
6812 | break; | |
acd3f3d3 | 6813 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
f5986242 VS |
6814 | div = 3; |
6815 | break; | |
acd3f3d3 | 6816 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
6817 | div = 4; |
6818 | break; | |
acd3f3d3 | 6819 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
6820 | div = 8; |
6821 | break; | |
6822 | default: | |
6823 | MISSING_CASE(divider); | |
6824 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
6825 | } |
6826 | ||
f5986242 | 6827 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
6828 | } |
6829 | ||
1652d19e VS |
6830 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6831 | { | |
fac5e23e | 6832 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
6833 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
6834 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6835 | ||
6836 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6837 | return 800000; | |
6838 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6839 | return 450000; | |
6840 | else if (freq == LCPLL_CLK_FREQ_450) | |
6841 | return 450000; | |
6842 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6843 | return 540000; | |
6844 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6845 | return 337500; | |
6846 | else | |
6847 | return 675000; | |
6848 | } | |
6849 | ||
6850 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6851 | { | |
fac5e23e | 6852 | struct drm_i915_private *dev_priv = to_i915(dev); |
1652d19e VS |
6853 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
6854 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6855 | ||
6856 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6857 | return 800000; | |
6858 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6859 | return 450000; | |
6860 | else if (freq == LCPLL_CLK_FREQ_450) | |
6861 | return 450000; | |
6862 | else if (IS_HSW_ULT(dev)) | |
6863 | return 337500; | |
6864 | else | |
6865 | return 540000; | |
79e53945 JB |
6866 | } |
6867 | ||
25eb05fc JB |
6868 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6869 | { | |
bfa7df01 VS |
6870 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6871 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6872 | } |
6873 | ||
b37a6434 VS |
6874 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6875 | { | |
6876 | return 450000; | |
6877 | } | |
6878 | ||
e70236a8 JB |
6879 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6880 | { | |
6881 | return 400000; | |
6882 | } | |
79e53945 | 6883 | |
e70236a8 | 6884 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6885 | { |
e907f170 | 6886 | return 333333; |
e70236a8 | 6887 | } |
79e53945 | 6888 | |
e70236a8 JB |
6889 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6890 | { | |
6891 | return 200000; | |
6892 | } | |
79e53945 | 6893 | |
257a7ffc DV |
6894 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6895 | { | |
6896 | u16 gcfgc = 0; | |
6897 | ||
6898 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6899 | ||
6900 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6901 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6902 | return 266667; |
257a7ffc | 6903 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6904 | return 333333; |
257a7ffc | 6905 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6906 | return 444444; |
257a7ffc DV |
6907 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6908 | return 200000; | |
6909 | default: | |
6910 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6911 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6912 | return 133333; |
257a7ffc | 6913 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6914 | return 166667; |
257a7ffc DV |
6915 | } |
6916 | } | |
6917 | ||
e70236a8 JB |
6918 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6919 | { | |
6920 | u16 gcfgc = 0; | |
79e53945 | 6921 | |
e70236a8 JB |
6922 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6923 | ||
6924 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6925 | return 133333; |
e70236a8 JB |
6926 | else { |
6927 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6928 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6929 | return 333333; |
e70236a8 JB |
6930 | default: |
6931 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6932 | return 190000; | |
79e53945 | 6933 | } |
e70236a8 JB |
6934 | } |
6935 | } | |
6936 | ||
6937 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6938 | { | |
e907f170 | 6939 | return 266667; |
e70236a8 JB |
6940 | } |
6941 | ||
1b1d2716 | 6942 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6943 | { |
6944 | u16 hpllcc = 0; | |
1b1d2716 | 6945 | |
65cd2b3f VS |
6946 | /* |
6947 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6948 | * encoding is different :( | |
6949 | * FIXME is this the right way to detect 852GM/852GMV? | |
6950 | */ | |
6951 | if (dev->pdev->revision == 0x1) | |
6952 | return 133333; | |
6953 | ||
1b1d2716 VS |
6954 | pci_bus_read_config_word(dev->pdev->bus, |
6955 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6956 | ||
e70236a8 JB |
6957 | /* Assume that the hardware is in the high speed state. This |
6958 | * should be the default. | |
6959 | */ | |
6960 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6961 | case GC_CLOCK_133_200: | |
1b1d2716 | 6962 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6963 | case GC_CLOCK_100_200: |
6964 | return 200000; | |
6965 | case GC_CLOCK_166_250: | |
6966 | return 250000; | |
6967 | case GC_CLOCK_100_133: | |
e907f170 | 6968 | return 133333; |
1b1d2716 VS |
6969 | case GC_CLOCK_133_266: |
6970 | case GC_CLOCK_133_266_2: | |
6971 | case GC_CLOCK_166_266: | |
6972 | return 266667; | |
e70236a8 | 6973 | } |
79e53945 | 6974 | |
e70236a8 JB |
6975 | /* Shouldn't happen */ |
6976 | return 0; | |
6977 | } | |
79e53945 | 6978 | |
e70236a8 JB |
6979 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6980 | { | |
e907f170 | 6981 | return 133333; |
79e53945 JB |
6982 | } |
6983 | ||
34edce2f VS |
6984 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6985 | { | |
fac5e23e | 6986 | struct drm_i915_private *dev_priv = to_i915(dev); |
34edce2f VS |
6987 | static const unsigned int blb_vco[8] = { |
6988 | [0] = 3200000, | |
6989 | [1] = 4000000, | |
6990 | [2] = 5333333, | |
6991 | [3] = 4800000, | |
6992 | [4] = 6400000, | |
6993 | }; | |
6994 | static const unsigned int pnv_vco[8] = { | |
6995 | [0] = 3200000, | |
6996 | [1] = 4000000, | |
6997 | [2] = 5333333, | |
6998 | [3] = 4800000, | |
6999 | [4] = 2666667, | |
7000 | }; | |
7001 | static const unsigned int cl_vco[8] = { | |
7002 | [0] = 3200000, | |
7003 | [1] = 4000000, | |
7004 | [2] = 5333333, | |
7005 | [3] = 6400000, | |
7006 | [4] = 3333333, | |
7007 | [5] = 3566667, | |
7008 | [6] = 4266667, | |
7009 | }; | |
7010 | static const unsigned int elk_vco[8] = { | |
7011 | [0] = 3200000, | |
7012 | [1] = 4000000, | |
7013 | [2] = 5333333, | |
7014 | [3] = 4800000, | |
7015 | }; | |
7016 | static const unsigned int ctg_vco[8] = { | |
7017 | [0] = 3200000, | |
7018 | [1] = 4000000, | |
7019 | [2] = 5333333, | |
7020 | [3] = 6400000, | |
7021 | [4] = 2666667, | |
7022 | [5] = 4266667, | |
7023 | }; | |
7024 | const unsigned int *vco_table; | |
7025 | unsigned int vco; | |
7026 | uint8_t tmp = 0; | |
7027 | ||
7028 | /* FIXME other chipsets? */ | |
7029 | if (IS_GM45(dev)) | |
7030 | vco_table = ctg_vco; | |
7031 | else if (IS_G4X(dev)) | |
7032 | vco_table = elk_vco; | |
7033 | else if (IS_CRESTLINE(dev)) | |
7034 | vco_table = cl_vco; | |
7035 | else if (IS_PINEVIEW(dev)) | |
7036 | vco_table = pnv_vco; | |
7037 | else if (IS_G33(dev)) | |
7038 | vco_table = blb_vco; | |
7039 | else | |
7040 | return 0; | |
7041 | ||
7042 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7043 | ||
7044 | vco = vco_table[tmp & 0x7]; | |
7045 | if (vco == 0) | |
7046 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7047 | else | |
7048 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7049 | ||
7050 | return vco; | |
7051 | } | |
7052 | ||
7053 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7054 | { | |
7055 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7056 | uint16_t tmp = 0; | |
7057 | ||
7058 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7059 | ||
7060 | cdclk_sel = (tmp >> 12) & 0x1; | |
7061 | ||
7062 | switch (vco) { | |
7063 | case 2666667: | |
7064 | case 4000000: | |
7065 | case 5333333: | |
7066 | return cdclk_sel ? 333333 : 222222; | |
7067 | case 3200000: | |
7068 | return cdclk_sel ? 320000 : 228571; | |
7069 | default: | |
7070 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7071 | return 222222; | |
7072 | } | |
7073 | } | |
7074 | ||
7075 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7076 | { | |
7077 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7078 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7079 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7080 | const uint8_t *div_table; | |
7081 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7082 | uint16_t tmp = 0; | |
7083 | ||
7084 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7085 | ||
7086 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7087 | ||
7088 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7089 | goto fail; | |
7090 | ||
7091 | switch (vco) { | |
7092 | case 3200000: | |
7093 | div_table = div_3200; | |
7094 | break; | |
7095 | case 4000000: | |
7096 | div_table = div_4000; | |
7097 | break; | |
7098 | case 5333333: | |
7099 | div_table = div_5333; | |
7100 | break; | |
7101 | default: | |
7102 | goto fail; | |
7103 | } | |
7104 | ||
7105 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7106 | ||
caf4e252 | 7107 | fail: |
34edce2f VS |
7108 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7109 | return 200000; | |
7110 | } | |
7111 | ||
7112 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7113 | { | |
7114 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7115 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7116 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7117 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7118 | const uint8_t *div_table; | |
7119 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7120 | uint16_t tmp = 0; | |
7121 | ||
7122 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7123 | ||
7124 | cdclk_sel = (tmp >> 4) & 0x7; | |
7125 | ||
7126 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7127 | goto fail; | |
7128 | ||
7129 | switch (vco) { | |
7130 | case 3200000: | |
7131 | div_table = div_3200; | |
7132 | break; | |
7133 | case 4000000: | |
7134 | div_table = div_4000; | |
7135 | break; | |
7136 | case 4800000: | |
7137 | div_table = div_4800; | |
7138 | break; | |
7139 | case 5333333: | |
7140 | div_table = div_5333; | |
7141 | break; | |
7142 | default: | |
7143 | goto fail; | |
7144 | } | |
7145 | ||
7146 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7147 | ||
caf4e252 | 7148 | fail: |
34edce2f VS |
7149 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7150 | return 190476; | |
7151 | } | |
7152 | ||
2c07245f | 7153 | static void |
a65851af | 7154 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7155 | { |
a65851af VS |
7156 | while (*num > DATA_LINK_M_N_MASK || |
7157 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7158 | *num >>= 1; |
7159 | *den >>= 1; | |
7160 | } | |
7161 | } | |
7162 | ||
a65851af VS |
7163 | static void compute_m_n(unsigned int m, unsigned int n, |
7164 | uint32_t *ret_m, uint32_t *ret_n) | |
7165 | { | |
7166 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7167 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7168 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7169 | } | |
7170 | ||
e69d0bc1 DV |
7171 | void |
7172 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7173 | int pixel_clock, int link_clock, | |
7174 | struct intel_link_m_n *m_n) | |
2c07245f | 7175 | { |
e69d0bc1 | 7176 | m_n->tu = 64; |
a65851af VS |
7177 | |
7178 | compute_m_n(bits_per_pixel * pixel_clock, | |
7179 | link_clock * nlanes * 8, | |
7180 | &m_n->gmch_m, &m_n->gmch_n); | |
7181 | ||
7182 | compute_m_n(pixel_clock, link_clock, | |
7183 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7184 | } |
7185 | ||
a7615030 CW |
7186 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7187 | { | |
d330a953 JN |
7188 | if (i915.panel_use_ssc >= 0) |
7189 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7190 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7191 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7192 | } |
7193 | ||
7429e9d4 | 7194 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7195 | { |
7df00d7a | 7196 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7197 | } |
f47709a9 | 7198 | |
7429e9d4 DV |
7199 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7200 | { | |
7201 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7202 | } |
7203 | ||
f47709a9 | 7204 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7205 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7206 | struct dpll *reduced_clock) |
a7516a05 | 7207 | { |
f47709a9 | 7208 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7209 | u32 fp, fp2 = 0; |
7210 | ||
7211 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7212 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7213 | if (reduced_clock) |
7429e9d4 | 7214 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7215 | } else { |
190f68c5 | 7216 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7217 | if (reduced_clock) |
7429e9d4 | 7218 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7219 | } |
7220 | ||
190f68c5 | 7221 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7222 | |
f47709a9 | 7223 | crtc->lowfreq_avail = false; |
2d84d2b3 | 7224 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7225 | reduced_clock) { |
190f68c5 | 7226 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7227 | crtc->lowfreq_avail = true; |
a7516a05 | 7228 | } else { |
190f68c5 | 7229 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7230 | } |
7231 | } | |
7232 | ||
5e69f97f CML |
7233 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7234 | pipe) | |
89b667f8 JB |
7235 | { |
7236 | u32 reg_val; | |
7237 | ||
7238 | /* | |
7239 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7240 | * and set it to a reasonable value instead. | |
7241 | */ | |
ab3c759a | 7242 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7243 | reg_val &= 0xffffff00; |
7244 | reg_val |= 0x00000030; | |
ab3c759a | 7245 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7246 | |
ab3c759a | 7247 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7248 | reg_val &= 0x8cffffff; |
7249 | reg_val = 0x8c000000; | |
ab3c759a | 7250 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7251 | |
ab3c759a | 7252 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7253 | reg_val &= 0xffffff00; |
ab3c759a | 7254 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7255 | |
ab3c759a | 7256 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7257 | reg_val &= 0x00ffffff; |
7258 | reg_val |= 0xb0000000; | |
ab3c759a | 7259 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7260 | } |
7261 | ||
b551842d DV |
7262 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7263 | struct intel_link_m_n *m_n) | |
7264 | { | |
7265 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7266 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
7267 | int pipe = crtc->pipe; |
7268 | ||
e3b95f1e DV |
7269 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7270 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7271 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7272 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7273 | } |
7274 | ||
7275 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7276 | struct intel_link_m_n *m_n, |
7277 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7278 | { |
7279 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7280 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d | 7281 | int pipe = crtc->pipe; |
6e3c9717 | 7282 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7283 | |
7284 | if (INTEL_INFO(dev)->gen >= 5) { | |
7285 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7286 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7287 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7288 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7289 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7290 | * for gen < 8) and if DRRS is supported (to make sure the | |
7291 | * registers are not unnecessarily accessed). | |
7292 | */ | |
44395bfe | 7293 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7294 | crtc->config->has_drrs) { |
f769cd24 VK |
7295 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7296 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7297 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7298 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7299 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7300 | } | |
b551842d | 7301 | } else { |
e3b95f1e DV |
7302 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7303 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7304 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7305 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7306 | } |
7307 | } | |
7308 | ||
fe3cd48d | 7309 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7310 | { |
fe3cd48d R |
7311 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7312 | ||
7313 | if (m_n == M1_N1) { | |
7314 | dp_m_n = &crtc->config->dp_m_n; | |
7315 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7316 | } else if (m_n == M2_N2) { | |
7317 | ||
7318 | /* | |
7319 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7320 | * needs to be programmed into M1_N1. | |
7321 | */ | |
7322 | dp_m_n = &crtc->config->dp_m2_n2; | |
7323 | } else { | |
7324 | DRM_ERROR("Unsupported divider value\n"); | |
7325 | return; | |
7326 | } | |
7327 | ||
6e3c9717 ACO |
7328 | if (crtc->config->has_pch_encoder) |
7329 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7330 | else |
fe3cd48d | 7331 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7332 | } |
7333 | ||
251ac862 DV |
7334 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7335 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7336 | { |
03ed5cbf | 7337 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7338 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7339 | if (crtc->pipe != PIPE_A) |
7340 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7341 | |
cd2d34d9 | 7342 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7343 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7344 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7345 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7346 | ||
03ed5cbf VS |
7347 | pipe_config->dpll_hw_state.dpll_md = |
7348 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7349 | } | |
bdd4b6a6 | 7350 | |
03ed5cbf VS |
7351 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7352 | struct intel_crtc_state *pipe_config) | |
7353 | { | |
7354 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7355 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7356 | if (crtc->pipe != PIPE_A) |
7357 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7358 | ||
cd2d34d9 | 7359 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7360 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7361 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7362 | ||
03ed5cbf VS |
7363 | pipe_config->dpll_hw_state.dpll_md = |
7364 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7365 | } |
7366 | ||
d288f65f | 7367 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7368 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7369 | { |
f47709a9 | 7370 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7371 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7372 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7373 | u32 mdiv; |
a0c4da24 | 7374 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7375 | u32 coreclk, reg_val; |
a0c4da24 | 7376 | |
cd2d34d9 VS |
7377 | /* Enable Refclk */ |
7378 | I915_WRITE(DPLL(pipe), | |
7379 | pipe_config->dpll_hw_state.dpll & | |
7380 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7381 | ||
7382 | /* No need to actually set up the DPLL with DSI */ | |
7383 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7384 | return; | |
7385 | ||
a580516d | 7386 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7387 | |
d288f65f VS |
7388 | bestn = pipe_config->dpll.n; |
7389 | bestm1 = pipe_config->dpll.m1; | |
7390 | bestm2 = pipe_config->dpll.m2; | |
7391 | bestp1 = pipe_config->dpll.p1; | |
7392 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7393 | |
89b667f8 JB |
7394 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7395 | ||
7396 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7397 | if (pipe == PIPE_B) |
5e69f97f | 7398 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7399 | |
7400 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7401 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7402 | |
7403 | /* Disable target IRef on PLL */ | |
ab3c759a | 7404 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7405 | reg_val &= 0x00ffffff; |
ab3c759a | 7406 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7407 | |
7408 | /* Disable fast lock */ | |
ab3c759a | 7409 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7410 | |
7411 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7412 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7413 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7414 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7415 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7416 | |
7417 | /* | |
7418 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7419 | * but we don't support that). | |
7420 | * Note: don't use the DAC post divider as it seems unstable. | |
7421 | */ | |
7422 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7423 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7424 | |
a0c4da24 | 7425 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7426 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7427 | |
89b667f8 | 7428 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7429 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
7430 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
7431 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7432 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7433 | 0x009f0003); |
89b667f8 | 7434 | else |
ab3c759a | 7435 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7436 | 0x00d0000f); |
7437 | ||
37a5650b | 7438 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 7439 | /* Use SSC source */ |
bdd4b6a6 | 7440 | if (pipe == PIPE_A) |
ab3c759a | 7441 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7442 | 0x0df40000); |
7443 | else | |
ab3c759a | 7444 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7445 | 0x0df70000); |
7446 | } else { /* HDMI or VGA */ | |
7447 | /* Use bend source */ | |
bdd4b6a6 | 7448 | if (pipe == PIPE_A) |
ab3c759a | 7449 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7450 | 0x0df70000); |
7451 | else | |
ab3c759a | 7452 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7453 | 0x0df40000); |
7454 | } | |
a0c4da24 | 7455 | |
ab3c759a | 7456 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7457 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 7458 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 7459 | coreclk |= 0x01000000; |
ab3c759a | 7460 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7461 | |
ab3c759a | 7462 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7463 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7464 | } |
7465 | ||
d288f65f | 7466 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7467 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7468 | { |
7469 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7470 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7471 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7472 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7473 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7474 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7475 | u32 dpio_val; |
9cbe40c1 | 7476 | int vco; |
9d556c99 | 7477 | |
cd2d34d9 VS |
7478 | /* Enable Refclk and SSC */ |
7479 | I915_WRITE(DPLL(pipe), | |
7480 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7481 | ||
7482 | /* No need to actually set up the DPLL with DSI */ | |
7483 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7484 | return; | |
7485 | ||
d288f65f VS |
7486 | bestn = pipe_config->dpll.n; |
7487 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7488 | bestm1 = pipe_config->dpll.m1; | |
7489 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7490 | bestp1 = pipe_config->dpll.p1; | |
7491 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7492 | vco = pipe_config->dpll.vco; |
a945ce7e | 7493 | dpio_val = 0; |
9cbe40c1 | 7494 | loopfilter = 0; |
9d556c99 | 7495 | |
a580516d | 7496 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7497 | |
9d556c99 CML |
7498 | /* p1 and p2 divider */ |
7499 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7500 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7501 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7502 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7503 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7504 | ||
7505 | /* Feedback post-divider - m2 */ | |
7506 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7507 | ||
7508 | /* Feedback refclk divider - n and m1 */ | |
7509 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7510 | DPIO_CHV_M1_DIV_BY_2 | | |
7511 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7512 | ||
7513 | /* M2 fraction division */ | |
25a25dfc | 7514 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7515 | |
7516 | /* M2 fraction division enable */ | |
a945ce7e VP |
7517 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7518 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7519 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7520 | if (bestm2_frac) | |
7521 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7522 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7523 | |
de3a0fde VP |
7524 | /* Program digital lock detect threshold */ |
7525 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7526 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7527 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7528 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7529 | if (!bestm2_frac) | |
7530 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7531 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7532 | ||
9d556c99 | 7533 | /* Loop filter */ |
9cbe40c1 VP |
7534 | if (vco == 5400000) { |
7535 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7536 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7537 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7538 | tribuf_calcntr = 0x9; | |
7539 | } else if (vco <= 6200000) { | |
7540 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7541 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7542 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7543 | tribuf_calcntr = 0x9; | |
7544 | } else if (vco <= 6480000) { | |
7545 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7546 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7547 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7548 | tribuf_calcntr = 0x8; | |
7549 | } else { | |
7550 | /* Not supported. Apply the same limits as in the max case */ | |
7551 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7552 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7553 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7554 | tribuf_calcntr = 0; | |
7555 | } | |
9d556c99 CML |
7556 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7557 | ||
968040b2 | 7558 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7559 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7560 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7561 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7562 | ||
9d556c99 CML |
7563 | /* AFC Recal */ |
7564 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7565 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7566 | DPIO_AFC_RECAL); | |
7567 | ||
a580516d | 7568 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7569 | } |
7570 | ||
d288f65f VS |
7571 | /** |
7572 | * vlv_force_pll_on - forcibly enable just the PLL | |
7573 | * @dev_priv: i915 private structure | |
7574 | * @pipe: pipe PLL to enable | |
7575 | * @dpll: PLL configuration | |
7576 | * | |
7577 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7578 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7579 | * be enabled. | |
7580 | */ | |
3f36b937 TU |
7581 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7582 | const struct dpll *dpll) | |
d288f65f VS |
7583 | { |
7584 | struct intel_crtc *crtc = | |
7585 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7586 | struct intel_crtc_state *pipe_config; |
7587 | ||
7588 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7589 | if (!pipe_config) | |
7590 | return -ENOMEM; | |
7591 | ||
7592 | pipe_config->base.crtc = &crtc->base; | |
7593 | pipe_config->pixel_multiplier = 1; | |
7594 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7595 | |
7596 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7597 | chv_compute_dpll(crtc, pipe_config); |
7598 | chv_prepare_pll(crtc, pipe_config); | |
7599 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7600 | } else { |
3f36b937 TU |
7601 | vlv_compute_dpll(crtc, pipe_config); |
7602 | vlv_prepare_pll(crtc, pipe_config); | |
7603 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7604 | } |
3f36b937 TU |
7605 | |
7606 | kfree(pipe_config); | |
7607 | ||
7608 | return 0; | |
d288f65f VS |
7609 | } |
7610 | ||
7611 | /** | |
7612 | * vlv_force_pll_off - forcibly disable just the PLL | |
7613 | * @dev_priv: i915 private structure | |
7614 | * @pipe: pipe PLL to disable | |
7615 | * | |
7616 | * Disable the PLL for @pipe. To be used in cases where we need | |
7617 | * the PLL enabled even when @pipe is not going to be enabled. | |
7618 | */ | |
7619 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7620 | { | |
7621 | if (IS_CHERRYVIEW(dev)) | |
7622 | chv_disable_pll(to_i915(dev), pipe); | |
7623 | else | |
7624 | vlv_disable_pll(to_i915(dev), pipe); | |
7625 | } | |
7626 | ||
251ac862 DV |
7627 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7628 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7629 | struct dpll *reduced_clock) |
eb1cbe48 | 7630 | { |
f47709a9 | 7631 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7632 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 7633 | u32 dpll; |
190f68c5 | 7634 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7635 | |
190f68c5 | 7636 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7637 | |
eb1cbe48 DV |
7638 | dpll = DPLL_VGA_MODE_DIS; |
7639 | ||
2d84d2b3 | 7640 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7641 | dpll |= DPLLB_MODE_LVDS; |
7642 | else | |
7643 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7644 | |
ef1b460d | 7645 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7646 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7647 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7648 | } |
198a037f | 7649 | |
3d6e9ee0 VS |
7650 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7651 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 7652 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7653 | |
37a5650b | 7654 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 7655 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7656 | |
7657 | /* compute bitmask from p1 value */ | |
7658 | if (IS_PINEVIEW(dev)) | |
7659 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7660 | else { | |
7661 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7662 | if (IS_G4X(dev) && reduced_clock) | |
7663 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7664 | } | |
7665 | switch (clock->p2) { | |
7666 | case 5: | |
7667 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7668 | break; | |
7669 | case 7: | |
7670 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7671 | break; | |
7672 | case 10: | |
7673 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7674 | break; | |
7675 | case 14: | |
7676 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7677 | break; | |
7678 | } | |
7679 | if (INTEL_INFO(dev)->gen >= 4) | |
7680 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7681 | ||
190f68c5 | 7682 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7683 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 7684 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7685 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7686 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7687 | else | |
7688 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7689 | ||
7690 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7691 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7692 | |
eb1cbe48 | 7693 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7694 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7695 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7696 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7697 | } |
7698 | } | |
7699 | ||
251ac862 DV |
7700 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7701 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7702 | struct dpll *reduced_clock) |
eb1cbe48 | 7703 | { |
f47709a9 | 7704 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7705 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 7706 | u32 dpll; |
190f68c5 | 7707 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7708 | |
190f68c5 | 7709 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7710 | |
eb1cbe48 DV |
7711 | dpll = DPLL_VGA_MODE_DIS; |
7712 | ||
2d84d2b3 | 7713 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7714 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7715 | } else { | |
7716 | if (clock->p1 == 2) | |
7717 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7718 | else | |
7719 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7720 | if (clock->p2 == 4) | |
7721 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7722 | } | |
7723 | ||
2d84d2b3 | 7724 | if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7725 | dpll |= DPLL_DVO_2X_MODE; |
7726 | ||
2d84d2b3 | 7727 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7728 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7729 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7730 | else | |
7731 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7732 | ||
7733 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7734 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7735 | } |
7736 | ||
8a654f3b | 7737 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7738 | { |
7739 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7740 | struct drm_i915_private *dev_priv = to_i915(dev); |
b0e77b9c | 7741 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7742 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7743 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7744 | uint32_t crtc_vtotal, crtc_vblank_end; |
7745 | int vsyncshift = 0; | |
4d8a62ea DV |
7746 | |
7747 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7748 | * the hw state checker will get angry at the mismatch. */ | |
7749 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7750 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7751 | |
609aeaca | 7752 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7753 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7754 | crtc_vtotal -= 1; |
7755 | crtc_vblank_end -= 1; | |
609aeaca | 7756 | |
2d84d2b3 | 7757 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7758 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7759 | else | |
7760 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7761 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7762 | if (vsyncshift < 0) |
7763 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7764 | } |
7765 | ||
7766 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7767 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7768 | |
fe2b8f9d | 7769 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7770 | (adjusted_mode->crtc_hdisplay - 1) | |
7771 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7772 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7773 | (adjusted_mode->crtc_hblank_start - 1) | |
7774 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7775 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7776 | (adjusted_mode->crtc_hsync_start - 1) | |
7777 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7778 | ||
fe2b8f9d | 7779 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7780 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7781 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7782 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7783 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7784 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7785 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7786 | (adjusted_mode->crtc_vsync_start - 1) | |
7787 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7788 | ||
b5e508d4 PZ |
7789 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7790 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7791 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7792 | * bits. */ | |
7793 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7794 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7795 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7796 | ||
bc58be60 JN |
7797 | } |
7798 | ||
7799 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7800 | { | |
7801 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7802 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
7803 | enum pipe pipe = intel_crtc->pipe; |
7804 | ||
b0e77b9c PZ |
7805 | /* pipesrc controls the size that is scaled from, which should |
7806 | * always be the user's requested size. | |
7807 | */ | |
7808 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7809 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7810 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7811 | } |
7812 | ||
1bd1bd80 | 7813 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7814 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7815 | { |
7816 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7817 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
7818 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7819 | uint32_t tmp; | |
7820 | ||
7821 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7822 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7823 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7824 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7825 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7826 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7827 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7828 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7829 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7830 | |
7831 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7832 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7833 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7834 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7835 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7836 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7837 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7838 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7839 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7840 | |
7841 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7842 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7843 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7844 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7845 | } |
bc58be60 JN |
7846 | } |
7847 | ||
7848 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7849 | struct intel_crtc_state *pipe_config) | |
7850 | { | |
7851 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7852 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 7853 | u32 tmp; |
1bd1bd80 DV |
7854 | |
7855 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7856 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7857 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7858 | ||
2d112de7 ACO |
7859 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7860 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7861 | } |
7862 | ||
f6a83288 | 7863 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7864 | struct intel_crtc_state *pipe_config) |
babea61d | 7865 | { |
2d112de7 ACO |
7866 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7867 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7868 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7869 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7870 | |
2d112de7 ACO |
7871 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7872 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7873 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7874 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7875 | |
2d112de7 | 7876 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7877 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7878 | |
2d112de7 ACO |
7879 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7880 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7881 | |
7882 | mode->hsync = drm_mode_hsync(mode); | |
7883 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7884 | drm_mode_set_name(mode); | |
babea61d JB |
7885 | } |
7886 | ||
84b046f3 DV |
7887 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7888 | { | |
7889 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7890 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b046f3 DV |
7891 | uint32_t pipeconf; |
7892 | ||
9f11a9e4 | 7893 | pipeconf = 0; |
84b046f3 | 7894 | |
b6b5d049 VS |
7895 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7896 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7897 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7898 | |
6e3c9717 | 7899 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7900 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7901 | |
ff9ce46e | 7902 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7903 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7904 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7905 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7906 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7907 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7908 | |
6e3c9717 | 7909 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7910 | case 18: |
7911 | pipeconf |= PIPECONF_6BPC; | |
7912 | break; | |
7913 | case 24: | |
7914 | pipeconf |= PIPECONF_8BPC; | |
7915 | break; | |
7916 | case 30: | |
7917 | pipeconf |= PIPECONF_10BPC; | |
7918 | break; | |
7919 | default: | |
7920 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7921 | BUG(); | |
84b046f3 DV |
7922 | } |
7923 | } | |
7924 | ||
7925 | if (HAS_PIPE_CXSR(dev)) { | |
7926 | if (intel_crtc->lowfreq_avail) { | |
7927 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7928 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7929 | } else { | |
7930 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7931 | } |
7932 | } | |
7933 | ||
6e3c9717 | 7934 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7935 | if (INTEL_INFO(dev)->gen < 4 || |
2d84d2b3 | 7936 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7937 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7938 | else | |
7939 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7940 | } else | |
84b046f3 DV |
7941 | pipeconf |= PIPECONF_PROGRESSIVE; |
7942 | ||
666a4537 WB |
7943 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7944 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7945 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7946 | |
84b046f3 DV |
7947 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7948 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7949 | } | |
7950 | ||
81c97f52 ACO |
7951 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7952 | struct intel_crtc_state *crtc_state) | |
7953 | { | |
7954 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7955 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7956 | const struct intel_limit *limit; |
81c97f52 ACO |
7957 | int refclk = 48000; |
7958 | ||
7959 | memset(&crtc_state->dpll_hw_state, 0, | |
7960 | sizeof(crtc_state->dpll_hw_state)); | |
7961 | ||
2d84d2b3 | 7962 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7963 | if (intel_panel_use_ssc(dev_priv)) { |
7964 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7965 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7966 | } | |
7967 | ||
7968 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7969 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7970 | limit = &intel_limits_i8xx_dvo; |
7971 | } else { | |
7972 | limit = &intel_limits_i8xx_dac; | |
7973 | } | |
7974 | ||
7975 | if (!crtc_state->clock_set && | |
7976 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7977 | refclk, NULL, &crtc_state->dpll)) { | |
7978 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7979 | return -EINVAL; | |
7980 | } | |
7981 | ||
7982 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7983 | ||
7984 | return 0; | |
7985 | } | |
7986 | ||
19ec6693 ACO |
7987 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7988 | struct intel_crtc_state *crtc_state) | |
7989 | { | |
7990 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7991 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7992 | const struct intel_limit *limit; |
19ec6693 ACO |
7993 | int refclk = 96000; |
7994 | ||
7995 | memset(&crtc_state->dpll_hw_state, 0, | |
7996 | sizeof(crtc_state->dpll_hw_state)); | |
7997 | ||
2d84d2b3 | 7998 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7999 | if (intel_panel_use_ssc(dev_priv)) { |
8000 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8001 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8002 | } | |
8003 | ||
8004 | if (intel_is_dual_link_lvds(dev)) | |
8005 | limit = &intel_limits_g4x_dual_channel_lvds; | |
8006 | else | |
8007 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
8008 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
8009 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 8010 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 8011 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
8012 | limit = &intel_limits_g4x_sdvo; |
8013 | } else { | |
8014 | /* The option is for other outputs */ | |
8015 | limit = &intel_limits_i9xx_sdvo; | |
8016 | } | |
8017 | ||
8018 | if (!crtc_state->clock_set && | |
8019 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8020 | refclk, NULL, &crtc_state->dpll)) { | |
8021 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8022 | return -EINVAL; | |
8023 | } | |
8024 | ||
8025 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8026 | ||
8027 | return 0; | |
8028 | } | |
8029 | ||
70e8aa21 ACO |
8030 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
8031 | struct intel_crtc_state *crtc_state) | |
8032 | { | |
8033 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8034 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8035 | const struct intel_limit *limit; |
70e8aa21 ACO |
8036 | int refclk = 96000; |
8037 | ||
8038 | memset(&crtc_state->dpll_hw_state, 0, | |
8039 | sizeof(crtc_state->dpll_hw_state)); | |
8040 | ||
2d84d2b3 | 8041 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8042 | if (intel_panel_use_ssc(dev_priv)) { |
8043 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8044 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8045 | } | |
8046 | ||
8047 | limit = &intel_limits_pineview_lvds; | |
8048 | } else { | |
8049 | limit = &intel_limits_pineview_sdvo; | |
8050 | } | |
8051 | ||
8052 | if (!crtc_state->clock_set && | |
8053 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8054 | refclk, NULL, &crtc_state->dpll)) { | |
8055 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8056 | return -EINVAL; | |
8057 | } | |
8058 | ||
8059 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8060 | ||
8061 | return 0; | |
8062 | } | |
8063 | ||
190f68c5 ACO |
8064 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8065 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8066 | { |
c7653199 | 8067 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8068 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8069 | const struct intel_limit *limit; |
81c97f52 | 8070 | int refclk = 96000; |
79e53945 | 8071 | |
dd3cd74a ACO |
8072 | memset(&crtc_state->dpll_hw_state, 0, |
8073 | sizeof(crtc_state->dpll_hw_state)); | |
8074 | ||
2d84d2b3 | 8075 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8076 | if (intel_panel_use_ssc(dev_priv)) { |
8077 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8078 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8079 | } | |
43565a06 | 8080 | |
70e8aa21 ACO |
8081 | limit = &intel_limits_i9xx_lvds; |
8082 | } else { | |
8083 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8084 | } |
79e53945 | 8085 | |
70e8aa21 ACO |
8086 | if (!crtc_state->clock_set && |
8087 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8088 | refclk, NULL, &crtc_state->dpll)) { | |
8089 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8090 | return -EINVAL; | |
f47709a9 | 8091 | } |
7026d4ac | 8092 | |
81c97f52 | 8093 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8094 | |
c8f7a0db | 8095 | return 0; |
f564048e EA |
8096 | } |
8097 | ||
65b3d6a9 ACO |
8098 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8099 | struct intel_crtc_state *crtc_state) | |
8100 | { | |
8101 | int refclk = 100000; | |
1b6f4958 | 8102 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8103 | |
8104 | memset(&crtc_state->dpll_hw_state, 0, | |
8105 | sizeof(crtc_state->dpll_hw_state)); | |
8106 | ||
65b3d6a9 ACO |
8107 | if (!crtc_state->clock_set && |
8108 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8109 | refclk, NULL, &crtc_state->dpll)) { | |
8110 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8111 | return -EINVAL; | |
8112 | } | |
8113 | ||
8114 | chv_compute_dpll(crtc, crtc_state); | |
8115 | ||
8116 | return 0; | |
8117 | } | |
8118 | ||
8119 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8120 | struct intel_crtc_state *crtc_state) | |
8121 | { | |
8122 | int refclk = 100000; | |
1b6f4958 | 8123 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8124 | |
8125 | memset(&crtc_state->dpll_hw_state, 0, | |
8126 | sizeof(crtc_state->dpll_hw_state)); | |
8127 | ||
65b3d6a9 ACO |
8128 | if (!crtc_state->clock_set && |
8129 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8130 | refclk, NULL, &crtc_state->dpll)) { | |
8131 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8132 | return -EINVAL; | |
8133 | } | |
8134 | ||
8135 | vlv_compute_dpll(crtc, crtc_state); | |
8136 | ||
8137 | return 0; | |
8138 | } | |
8139 | ||
2fa2fe9a | 8140 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8141 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8142 | { |
8143 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8144 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8145 | uint32_t tmp; |
8146 | ||
dc9e7dec VS |
8147 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8148 | return; | |
8149 | ||
2fa2fe9a | 8150 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8151 | if (!(tmp & PFIT_ENABLE)) |
8152 | return; | |
2fa2fe9a | 8153 | |
06922821 | 8154 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8155 | if (INTEL_INFO(dev)->gen < 4) { |
8156 | if (crtc->pipe != PIPE_B) | |
8157 | return; | |
2fa2fe9a DV |
8158 | } else { |
8159 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8160 | return; | |
8161 | } | |
8162 | ||
06922821 | 8163 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8164 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8165 | } |
8166 | ||
acbec814 | 8167 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8168 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8169 | { |
8170 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8171 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 8172 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 8173 | struct dpll clock; |
acbec814 | 8174 | u32 mdiv; |
662c6ecb | 8175 | int refclk = 100000; |
acbec814 | 8176 | |
b521973b VS |
8177 | /* In case of DSI, DPLL will not be used */ |
8178 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8179 | return; |
8180 | ||
a580516d | 8181 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8182 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8183 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8184 | |
8185 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8186 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8187 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8188 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8189 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8190 | ||
dccbea3b | 8191 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8192 | } |
8193 | ||
5724dbd1 DL |
8194 | static void |
8195 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8196 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8197 | { |
8198 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8199 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
8200 | u32 val, base, offset; |
8201 | int pipe = crtc->pipe, plane = crtc->plane; | |
8202 | int fourcc, pixel_format; | |
6761dd31 | 8203 | unsigned int aligned_height; |
b113d5ee | 8204 | struct drm_framebuffer *fb; |
1b842c89 | 8205 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8206 | |
42a7b088 DL |
8207 | val = I915_READ(DSPCNTR(plane)); |
8208 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8209 | return; | |
8210 | ||
d9806c9f | 8211 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8212 | if (!intel_fb) { |
1ad292b5 JB |
8213 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8214 | return; | |
8215 | } | |
8216 | ||
1b842c89 DL |
8217 | fb = &intel_fb->base; |
8218 | ||
18c5247e DV |
8219 | if (INTEL_INFO(dev)->gen >= 4) { |
8220 | if (val & DISPPLANE_TILED) { | |
49af449b | 8221 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8222 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8223 | } | |
8224 | } | |
1ad292b5 JB |
8225 | |
8226 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8227 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8228 | fb->pixel_format = fourcc; |
8229 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8230 | |
8231 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8232 | if (plane_config->tiling) |
1ad292b5 JB |
8233 | offset = I915_READ(DSPTILEOFF(plane)); |
8234 | else | |
8235 | offset = I915_READ(DSPLINOFF(plane)); | |
8236 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8237 | } else { | |
8238 | base = I915_READ(DSPADDR(plane)); | |
8239 | } | |
8240 | plane_config->base = base; | |
8241 | ||
8242 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8243 | fb->width = ((val >> 16) & 0xfff) + 1; |
8244 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8245 | |
8246 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8247 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8248 | |
b113d5ee | 8249 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8250 | fb->pixel_format, |
8251 | fb->modifier[0]); | |
1ad292b5 | 8252 | |
f37b5c2b | 8253 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8254 | |
2844a921 DL |
8255 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8256 | pipe_name(pipe), plane, fb->width, fb->height, | |
8257 | fb->bits_per_pixel, base, fb->pitches[0], | |
8258 | plane_config->size); | |
1ad292b5 | 8259 | |
2d14030b | 8260 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8261 | } |
8262 | ||
70b23a98 | 8263 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8264 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8265 | { |
8266 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8267 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
8268 | int pipe = pipe_config->cpu_transcoder; |
8269 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8270 | struct dpll clock; |
0d7b6b11 | 8271 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8272 | int refclk = 100000; |
8273 | ||
b521973b VS |
8274 | /* In case of DSI, DPLL will not be used */ |
8275 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8276 | return; | |
8277 | ||
a580516d | 8278 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8279 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8280 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8281 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8282 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8283 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8284 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8285 | |
8286 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8287 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8288 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8289 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8290 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8291 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8292 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8293 | ||
dccbea3b | 8294 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8295 | } |
8296 | ||
0e8ffe1b | 8297 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8298 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8299 | { |
8300 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8301 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8302 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8303 | uint32_t tmp; |
1729050e | 8304 | bool ret; |
0e8ffe1b | 8305 | |
1729050e ID |
8306 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8307 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8308 | return false; |
8309 | ||
e143a21c | 8310 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8311 | pipe_config->shared_dpll = NULL; |
eccb140b | 8312 | |
1729050e ID |
8313 | ret = false; |
8314 | ||
0e8ffe1b DV |
8315 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8316 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8317 | goto out; |
0e8ffe1b | 8318 | |
666a4537 | 8319 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8320 | switch (tmp & PIPECONF_BPC_MASK) { |
8321 | case PIPECONF_6BPC: | |
8322 | pipe_config->pipe_bpp = 18; | |
8323 | break; | |
8324 | case PIPECONF_8BPC: | |
8325 | pipe_config->pipe_bpp = 24; | |
8326 | break; | |
8327 | case PIPECONF_10BPC: | |
8328 | pipe_config->pipe_bpp = 30; | |
8329 | break; | |
8330 | default: | |
8331 | break; | |
8332 | } | |
8333 | } | |
8334 | ||
666a4537 WB |
8335 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8336 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8337 | pipe_config->limited_color_range = true; |
8338 | ||
282740f7 VS |
8339 | if (INTEL_INFO(dev)->gen < 4) |
8340 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8341 | ||
1bd1bd80 | 8342 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8343 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8344 | |
2fa2fe9a DV |
8345 | i9xx_get_pfit_config(crtc, pipe_config); |
8346 | ||
6c49f241 | 8347 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c VS |
8348 | /* No way to read it out on pipes B and C */ |
8349 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8350 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8351 | else | |
8352 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8353 | pipe_config->pixel_multiplier = |
8354 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8355 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8356 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8357 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8358 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8359 | pipe_config->pixel_multiplier = | |
8360 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8361 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8362 | } else { | |
8363 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8364 | * port and will be fixed up in the encoder->get_config | |
8365 | * function. */ | |
8366 | pipe_config->pixel_multiplier = 1; | |
8367 | } | |
8bcc2795 | 8368 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8369 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8370 | /* |
8371 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8372 | * on 830. Filter it out here so that we don't | |
8373 | * report errors due to that. | |
8374 | */ | |
8375 | if (IS_I830(dev)) | |
8376 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8377 | ||
8bcc2795 DV |
8378 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8379 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8380 | } else { |
8381 | /* Mask out read-only status bits. */ | |
8382 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8383 | DPLL_PORTC_READY_MASK | | |
8384 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8385 | } |
6c49f241 | 8386 | |
70b23a98 VS |
8387 | if (IS_CHERRYVIEW(dev)) |
8388 | chv_crtc_clock_get(crtc, pipe_config); | |
8389 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8390 | vlv_crtc_clock_get(crtc, pipe_config); |
8391 | else | |
8392 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8393 | |
0f64614d VS |
8394 | /* |
8395 | * Normally the dotclock is filled in by the encoder .get_config() | |
8396 | * but in case the pipe is enabled w/o any ports we need a sane | |
8397 | * default. | |
8398 | */ | |
8399 | pipe_config->base.adjusted_mode.crtc_clock = | |
8400 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8401 | ||
1729050e ID |
8402 | ret = true; |
8403 | ||
8404 | out: | |
8405 | intel_display_power_put(dev_priv, power_domain); | |
8406 | ||
8407 | return ret; | |
0e8ffe1b DV |
8408 | } |
8409 | ||
dde86e2d | 8410 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 | 8411 | { |
fac5e23e | 8412 | struct drm_i915_private *dev_priv = to_i915(dev); |
13d83a67 | 8413 | struct intel_encoder *encoder; |
1c1a24d2 | 8414 | int i; |
74cfd7ac | 8415 | u32 val, final; |
13d83a67 | 8416 | bool has_lvds = false; |
199e5d79 | 8417 | bool has_cpu_edp = false; |
199e5d79 | 8418 | bool has_panel = false; |
99eb6a01 KP |
8419 | bool has_ck505 = false; |
8420 | bool can_ssc = false; | |
1c1a24d2 | 8421 | bool using_ssc_source = false; |
13d83a67 JB |
8422 | |
8423 | /* We need to take the global config into account */ | |
b2784e15 | 8424 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8425 | switch (encoder->type) { |
8426 | case INTEL_OUTPUT_LVDS: | |
8427 | has_panel = true; | |
8428 | has_lvds = true; | |
8429 | break; | |
8430 | case INTEL_OUTPUT_EDP: | |
8431 | has_panel = true; | |
2de6905f | 8432 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8433 | has_cpu_edp = true; |
8434 | break; | |
6847d71b PZ |
8435 | default: |
8436 | break; | |
13d83a67 JB |
8437 | } |
8438 | } | |
8439 | ||
99eb6a01 | 8440 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8441 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8442 | can_ssc = has_ck505; |
8443 | } else { | |
8444 | has_ck505 = false; | |
8445 | can_ssc = true; | |
8446 | } | |
8447 | ||
1c1a24d2 L |
8448 | /* Check if any DPLLs are using the SSC source */ |
8449 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8450 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8451 | ||
8452 | if (!(temp & DPLL_VCO_ENABLE)) | |
8453 | continue; | |
8454 | ||
8455 | if ((temp & PLL_REF_INPUT_MASK) == | |
8456 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8457 | using_ssc_source = true; | |
8458 | break; | |
8459 | } | |
8460 | } | |
8461 | ||
8462 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
8463 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
8464 | |
8465 | /* Ironlake: try to setup display ref clock before DPLL | |
8466 | * enabling. This is only under driver's control after | |
8467 | * PCH B stepping, previous chipset stepping should be | |
8468 | * ignoring this setting. | |
8469 | */ | |
74cfd7ac CW |
8470 | val = I915_READ(PCH_DREF_CONTROL); |
8471 | ||
8472 | /* As we must carefully and slowly disable/enable each source in turn, | |
8473 | * compute the final state we want first and check if we need to | |
8474 | * make any changes at all. | |
8475 | */ | |
8476 | final = val; | |
8477 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8478 | if (has_ck505) | |
8479 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8480 | else | |
8481 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8482 | ||
8c07eb68 | 8483 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 8484 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 8485 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
8486 | |
8487 | if (has_panel) { | |
8488 | final |= DREF_SSC_SOURCE_ENABLE; | |
8489 | ||
8490 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8491 | final |= DREF_SSC1_ENABLE; | |
8492 | ||
8493 | if (has_cpu_edp) { | |
8494 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8495 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8496 | else | |
8497 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8498 | } else | |
8499 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
8500 | } else if (using_ssc_source) { |
8501 | final |= DREF_SSC_SOURCE_ENABLE; | |
8502 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
8503 | } |
8504 | ||
8505 | if (final == val) | |
8506 | return; | |
8507 | ||
13d83a67 | 8508 | /* Always enable nonspread source */ |
74cfd7ac | 8509 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8510 | |
99eb6a01 | 8511 | if (has_ck505) |
74cfd7ac | 8512 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8513 | else |
74cfd7ac | 8514 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8515 | |
199e5d79 | 8516 | if (has_panel) { |
74cfd7ac CW |
8517 | val &= ~DREF_SSC_SOURCE_MASK; |
8518 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8519 | |
199e5d79 | 8520 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8521 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8522 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8523 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8524 | } else |
74cfd7ac | 8525 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8526 | |
8527 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8528 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8529 | POSTING_READ(PCH_DREF_CONTROL); |
8530 | udelay(200); | |
8531 | ||
74cfd7ac | 8532 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8533 | |
8534 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8535 | if (has_cpu_edp) { |
99eb6a01 | 8536 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8537 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8538 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8539 | } else |
74cfd7ac | 8540 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8541 | } else |
74cfd7ac | 8542 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8543 | |
74cfd7ac | 8544 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8545 | POSTING_READ(PCH_DREF_CONTROL); |
8546 | udelay(200); | |
8547 | } else { | |
1c1a24d2 | 8548 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 8549 | |
74cfd7ac | 8550 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8551 | |
8552 | /* Turn off CPU output */ | |
74cfd7ac | 8553 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8554 | |
74cfd7ac | 8555 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8556 | POSTING_READ(PCH_DREF_CONTROL); |
8557 | udelay(200); | |
8558 | ||
1c1a24d2 L |
8559 | if (!using_ssc_source) { |
8560 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 8561 | |
1c1a24d2 L |
8562 | /* Turn off the SSC source */ |
8563 | val &= ~DREF_SSC_SOURCE_MASK; | |
8564 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 8565 | |
1c1a24d2 L |
8566 | /* Turn off SSC1 */ |
8567 | val &= ~DREF_SSC1_ENABLE; | |
8568 | ||
8569 | I915_WRITE(PCH_DREF_CONTROL, val); | |
8570 | POSTING_READ(PCH_DREF_CONTROL); | |
8571 | udelay(200); | |
8572 | } | |
13d83a67 | 8573 | } |
74cfd7ac CW |
8574 | |
8575 | BUG_ON(val != final); | |
13d83a67 JB |
8576 | } |
8577 | ||
f31f2d55 | 8578 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8579 | { |
f31f2d55 | 8580 | uint32_t tmp; |
dde86e2d | 8581 | |
0ff066a9 PZ |
8582 | tmp = I915_READ(SOUTH_CHICKEN2); |
8583 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8584 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8585 | |
cf3598c2 ID |
8586 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
8587 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 8588 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 8589 | |
0ff066a9 PZ |
8590 | tmp = I915_READ(SOUTH_CHICKEN2); |
8591 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8592 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8593 | |
cf3598c2 ID |
8594 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
8595 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 8596 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
8597 | } |
8598 | ||
8599 | /* WaMPhyProgramming:hsw */ | |
8600 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8601 | { | |
8602 | uint32_t tmp; | |
dde86e2d PZ |
8603 | |
8604 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8605 | tmp &= ~(0xFF << 24); | |
8606 | tmp |= (0x12 << 24); | |
8607 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8608 | ||
dde86e2d PZ |
8609 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8610 | tmp |= (1 << 11); | |
8611 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8612 | ||
8613 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8614 | tmp |= (1 << 11); | |
8615 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8616 | ||
dde86e2d PZ |
8617 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8618 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8619 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8620 | ||
8621 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8622 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8623 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8624 | ||
0ff066a9 PZ |
8625 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8626 | tmp &= ~(7 << 13); | |
8627 | tmp |= (5 << 13); | |
8628 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8629 | |
0ff066a9 PZ |
8630 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8631 | tmp &= ~(7 << 13); | |
8632 | tmp |= (5 << 13); | |
8633 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8634 | |
8635 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8636 | tmp &= ~0xFF; | |
8637 | tmp |= 0x1C; | |
8638 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8639 | ||
8640 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8641 | tmp &= ~0xFF; | |
8642 | tmp |= 0x1C; | |
8643 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8644 | ||
8645 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8646 | tmp &= ~(0xFF << 16); | |
8647 | tmp |= (0x1C << 16); | |
8648 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8649 | ||
8650 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8651 | tmp &= ~(0xFF << 16); | |
8652 | tmp |= (0x1C << 16); | |
8653 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8654 | ||
0ff066a9 PZ |
8655 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8656 | tmp |= (1 << 27); | |
8657 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8658 | |
0ff066a9 PZ |
8659 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8660 | tmp |= (1 << 27); | |
8661 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8662 | |
0ff066a9 PZ |
8663 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8664 | tmp &= ~(0xF << 28); | |
8665 | tmp |= (4 << 28); | |
8666 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8667 | |
0ff066a9 PZ |
8668 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8669 | tmp &= ~(0xF << 28); | |
8670 | tmp |= (4 << 28); | |
8671 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8672 | } |
8673 | ||
2fa86a1f PZ |
8674 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8675 | * Programming" based on the parameters passed: | |
8676 | * - Sequence to enable CLKOUT_DP | |
8677 | * - Sequence to enable CLKOUT_DP without spread | |
8678 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8679 | */ | |
8680 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8681 | bool with_fdi) | |
f31f2d55 | 8682 | { |
fac5e23e | 8683 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa86a1f PZ |
8684 | uint32_t reg, tmp; |
8685 | ||
8686 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8687 | with_spread = true; | |
c2699524 | 8688 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8689 | with_fdi = false; |
f31f2d55 | 8690 | |
a580516d | 8691 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8692 | |
8693 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8694 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8695 | tmp |= SBI_SSCCTL_PATHALT; | |
8696 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8697 | ||
8698 | udelay(24); | |
8699 | ||
2fa86a1f PZ |
8700 | if (with_spread) { |
8701 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8702 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8703 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8704 | |
2fa86a1f PZ |
8705 | if (with_fdi) { |
8706 | lpt_reset_fdi_mphy(dev_priv); | |
8707 | lpt_program_fdi_mphy(dev_priv); | |
8708 | } | |
8709 | } | |
dde86e2d | 8710 | |
c2699524 | 8711 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8712 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8713 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8714 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8715 | |
a580516d | 8716 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8717 | } |
8718 | ||
47701c3b PZ |
8719 | /* Sequence to disable CLKOUT_DP */ |
8720 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8721 | { | |
fac5e23e | 8722 | struct drm_i915_private *dev_priv = to_i915(dev); |
47701c3b PZ |
8723 | uint32_t reg, tmp; |
8724 | ||
a580516d | 8725 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8726 | |
c2699524 | 8727 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8728 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8729 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8730 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8731 | ||
8732 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8733 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8734 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8735 | tmp |= SBI_SSCCTL_PATHALT; | |
8736 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8737 | udelay(32); | |
8738 | } | |
8739 | tmp |= SBI_SSCCTL_DISABLE; | |
8740 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8741 | } | |
8742 | ||
a580516d | 8743 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8744 | } |
8745 | ||
f7be2c21 VS |
8746 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8747 | ||
8748 | static const uint16_t sscdivintphase[] = { | |
8749 | [BEND_IDX( 50)] = 0x3B23, | |
8750 | [BEND_IDX( 45)] = 0x3B23, | |
8751 | [BEND_IDX( 40)] = 0x3C23, | |
8752 | [BEND_IDX( 35)] = 0x3C23, | |
8753 | [BEND_IDX( 30)] = 0x3D23, | |
8754 | [BEND_IDX( 25)] = 0x3D23, | |
8755 | [BEND_IDX( 20)] = 0x3E23, | |
8756 | [BEND_IDX( 15)] = 0x3E23, | |
8757 | [BEND_IDX( 10)] = 0x3F23, | |
8758 | [BEND_IDX( 5)] = 0x3F23, | |
8759 | [BEND_IDX( 0)] = 0x0025, | |
8760 | [BEND_IDX( -5)] = 0x0025, | |
8761 | [BEND_IDX(-10)] = 0x0125, | |
8762 | [BEND_IDX(-15)] = 0x0125, | |
8763 | [BEND_IDX(-20)] = 0x0225, | |
8764 | [BEND_IDX(-25)] = 0x0225, | |
8765 | [BEND_IDX(-30)] = 0x0325, | |
8766 | [BEND_IDX(-35)] = 0x0325, | |
8767 | [BEND_IDX(-40)] = 0x0425, | |
8768 | [BEND_IDX(-45)] = 0x0425, | |
8769 | [BEND_IDX(-50)] = 0x0525, | |
8770 | }; | |
8771 | ||
8772 | /* | |
8773 | * Bend CLKOUT_DP | |
8774 | * steps -50 to 50 inclusive, in steps of 5 | |
8775 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8776 | * change in clock period = -(steps / 10) * 5.787 ps | |
8777 | */ | |
8778 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8779 | { | |
8780 | uint32_t tmp; | |
8781 | int idx = BEND_IDX(steps); | |
8782 | ||
8783 | if (WARN_ON(steps % 5 != 0)) | |
8784 | return; | |
8785 | ||
8786 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8787 | return; | |
8788 | ||
8789 | mutex_lock(&dev_priv->sb_lock); | |
8790 | ||
8791 | if (steps % 10 != 0) | |
8792 | tmp = 0xAAAAAAAB; | |
8793 | else | |
8794 | tmp = 0x00000000; | |
8795 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8796 | ||
8797 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8798 | tmp &= 0xffff0000; | |
8799 | tmp |= sscdivintphase[idx]; | |
8800 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8801 | ||
8802 | mutex_unlock(&dev_priv->sb_lock); | |
8803 | } | |
8804 | ||
8805 | #undef BEND_IDX | |
8806 | ||
bf8fa3d3 PZ |
8807 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8808 | { | |
bf8fa3d3 PZ |
8809 | struct intel_encoder *encoder; |
8810 | bool has_vga = false; | |
8811 | ||
b2784e15 | 8812 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8813 | switch (encoder->type) { |
8814 | case INTEL_OUTPUT_ANALOG: | |
8815 | has_vga = true; | |
8816 | break; | |
6847d71b PZ |
8817 | default: |
8818 | break; | |
bf8fa3d3 PZ |
8819 | } |
8820 | } | |
8821 | ||
f7be2c21 VS |
8822 | if (has_vga) { |
8823 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8824 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8825 | } else { |
47701c3b | 8826 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8827 | } |
bf8fa3d3 PZ |
8828 | } |
8829 | ||
dde86e2d PZ |
8830 | /* |
8831 | * Initialize reference clocks when the driver loads | |
8832 | */ | |
8833 | void intel_init_pch_refclk(struct drm_device *dev) | |
8834 | { | |
8835 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8836 | ironlake_init_pch_refclk(dev); | |
8837 | else if (HAS_PCH_LPT(dev)) | |
8838 | lpt_init_pch_refclk(dev); | |
8839 | } | |
8840 | ||
6ff93609 | 8841 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8842 | { |
fac5e23e | 8843 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
8844 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8845 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8846 | uint32_t val; |
8847 | ||
78114071 | 8848 | val = 0; |
c8203565 | 8849 | |
6e3c9717 | 8850 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8851 | case 18: |
dfd07d72 | 8852 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8853 | break; |
8854 | case 24: | |
dfd07d72 | 8855 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8856 | break; |
8857 | case 30: | |
dfd07d72 | 8858 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8859 | break; |
8860 | case 36: | |
dfd07d72 | 8861 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8862 | break; |
8863 | default: | |
cc769b62 PZ |
8864 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8865 | BUG(); | |
c8203565 PZ |
8866 | } |
8867 | ||
6e3c9717 | 8868 | if (intel_crtc->config->dither) |
c8203565 PZ |
8869 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8870 | ||
6e3c9717 | 8871 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8872 | val |= PIPECONF_INTERLACED_ILK; |
8873 | else | |
8874 | val |= PIPECONF_PROGRESSIVE; | |
8875 | ||
6e3c9717 | 8876 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8877 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8878 | |
c8203565 PZ |
8879 | I915_WRITE(PIPECONF(pipe), val); |
8880 | POSTING_READ(PIPECONF(pipe)); | |
8881 | } | |
8882 | ||
6ff93609 | 8883 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8884 | { |
fac5e23e | 8885 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8887 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8888 | u32 val = 0; |
ee2b0b38 | 8889 | |
391bf048 | 8890 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8891 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8892 | ||
6e3c9717 | 8893 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8894 | val |= PIPECONF_INTERLACED_ILK; |
8895 | else | |
8896 | val |= PIPECONF_PROGRESSIVE; | |
8897 | ||
702e7a56 PZ |
8898 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8899 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8900 | } |
8901 | ||
391bf048 JN |
8902 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8903 | { | |
fac5e23e | 8904 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8905 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8906 | |
391bf048 JN |
8907 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8908 | u32 val = 0; | |
756f85cf | 8909 | |
6e3c9717 | 8910 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8911 | case 18: |
8912 | val |= PIPEMISC_DITHER_6_BPC; | |
8913 | break; | |
8914 | case 24: | |
8915 | val |= PIPEMISC_DITHER_8_BPC; | |
8916 | break; | |
8917 | case 30: | |
8918 | val |= PIPEMISC_DITHER_10_BPC; | |
8919 | break; | |
8920 | case 36: | |
8921 | val |= PIPEMISC_DITHER_12_BPC; | |
8922 | break; | |
8923 | default: | |
8924 | /* Case prevented by pipe_config_set_bpp. */ | |
8925 | BUG(); | |
8926 | } | |
8927 | ||
6e3c9717 | 8928 | if (intel_crtc->config->dither) |
756f85cf PZ |
8929 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8930 | ||
391bf048 | 8931 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8932 | } |
ee2b0b38 PZ |
8933 | } |
8934 | ||
d4b1931c PZ |
8935 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8936 | { | |
8937 | /* | |
8938 | * Account for spread spectrum to avoid | |
8939 | * oversubscribing the link. Max center spread | |
8940 | * is 2.5%; use 5% for safety's sake. | |
8941 | */ | |
8942 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8943 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8944 | } |
8945 | ||
7429e9d4 | 8946 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8947 | { |
7429e9d4 | 8948 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8949 | } |
8950 | ||
b75ca6f6 ACO |
8951 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8952 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8953 | struct dpll *reduced_clock) |
79e53945 | 8954 | { |
de13a2e3 | 8955 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8956 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8957 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8958 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8959 | int factor; |
79e53945 | 8960 | |
c1858123 | 8961 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8962 | factor = 21; |
3d6e9ee0 | 8963 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8964 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8965 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8966 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8967 | factor = 25; |
190f68c5 | 8968 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8969 | factor = 20; |
c1858123 | 8970 | |
b75ca6f6 ACO |
8971 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8972 | ||
190f68c5 | 8973 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8974 | fp |= FP_CB_TUNE; |
8975 | ||
8976 | if (reduced_clock) { | |
8977 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8978 | |
b75ca6f6 ACO |
8979 | if (reduced_clock->m < factor * reduced_clock->n) |
8980 | fp2 |= FP_CB_TUNE; | |
8981 | } else { | |
8982 | fp2 = fp; | |
8983 | } | |
9a7c7890 | 8984 | |
5eddb70b | 8985 | dpll = 0; |
2c07245f | 8986 | |
3d6e9ee0 | 8987 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8988 | dpll |= DPLLB_MODE_LVDS; |
8989 | else | |
8990 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8991 | |
190f68c5 | 8992 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8993 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8994 | |
3d6e9ee0 VS |
8995 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8996 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8997 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8998 | |
37a5650b | 8999 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 9000 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9001 | |
a07d6787 | 9002 | /* compute bitmask from p1 value */ |
190f68c5 | 9003 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9004 | /* also FPA1 */ |
190f68c5 | 9005 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9006 | |
190f68c5 | 9007 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9008 | case 5: |
9009 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9010 | break; | |
9011 | case 7: | |
9012 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9013 | break; | |
9014 | case 10: | |
9015 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9016 | break; | |
9017 | case 14: | |
9018 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9019 | break; | |
79e53945 JB |
9020 | } |
9021 | ||
3d6e9ee0 VS |
9022 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
9023 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 9024 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9025 | else |
9026 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9027 | ||
b75ca6f6 ACO |
9028 | dpll |= DPLL_VCO_ENABLE; |
9029 | ||
9030 | crtc_state->dpll_hw_state.dpll = dpll; | |
9031 | crtc_state->dpll_hw_state.fp0 = fp; | |
9032 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
9033 | } |
9034 | ||
190f68c5 ACO |
9035 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9036 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9037 | { |
997c030c | 9038 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9039 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 9040 | struct dpll reduced_clock; |
7ed9f894 | 9041 | bool has_reduced_clock = false; |
e2b78267 | 9042 | struct intel_shared_dpll *pll; |
1b6f4958 | 9043 | const struct intel_limit *limit; |
997c030c | 9044 | int refclk = 120000; |
de13a2e3 | 9045 | |
dd3cd74a ACO |
9046 | memset(&crtc_state->dpll_hw_state, 0, |
9047 | sizeof(crtc_state->dpll_hw_state)); | |
9048 | ||
ded220e2 ACO |
9049 | crtc->lowfreq_avail = false; |
9050 | ||
9051 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
9052 | if (!crtc_state->has_pch_encoder) | |
9053 | return 0; | |
79e53945 | 9054 | |
2d84d2b3 | 9055 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
9056 | if (intel_panel_use_ssc(dev_priv)) { |
9057 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
9058 | dev_priv->vbt.lvds_ssc_freq); | |
9059 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
9060 | } | |
9061 | ||
9062 | if (intel_is_dual_link_lvds(dev)) { | |
9063 | if (refclk == 100000) | |
9064 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
9065 | else | |
9066 | limit = &intel_limits_ironlake_dual_lvds; | |
9067 | } else { | |
9068 | if (refclk == 100000) | |
9069 | limit = &intel_limits_ironlake_single_lvds_100m; | |
9070 | else | |
9071 | limit = &intel_limits_ironlake_single_lvds; | |
9072 | } | |
9073 | } else { | |
9074 | limit = &intel_limits_ironlake_dac; | |
9075 | } | |
9076 | ||
364ee29d | 9077 | if (!crtc_state->clock_set && |
997c030c ACO |
9078 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9079 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9080 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9081 | return -EINVAL; | |
f47709a9 | 9082 | } |
79e53945 | 9083 | |
b75ca6f6 ACO |
9084 | ironlake_compute_dpll(crtc, crtc_state, |
9085 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9086 | |
ded220e2 ACO |
9087 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9088 | if (pll == NULL) { | |
9089 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9090 | pipe_name(crtc->pipe)); | |
9091 | return -EINVAL; | |
3fb37703 | 9092 | } |
79e53945 | 9093 | |
2d84d2b3 | 9094 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 9095 | has_reduced_clock) |
c7653199 | 9096 | crtc->lowfreq_avail = true; |
e2b78267 | 9097 | |
c8f7a0db | 9098 | return 0; |
79e53945 JB |
9099 | } |
9100 | ||
eb14cb74 VS |
9101 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9102 | struct intel_link_m_n *m_n) | |
9103 | { | |
9104 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9105 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
9106 | enum pipe pipe = crtc->pipe; |
9107 | ||
9108 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9109 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9110 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9111 | & ~TU_SIZE_MASK; | |
9112 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9113 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9114 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9115 | } | |
9116 | ||
9117 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9118 | enum transcoder transcoder, | |
b95af8be VK |
9119 | struct intel_link_m_n *m_n, |
9120 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9121 | { |
9122 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9123 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 | 9124 | enum pipe pipe = crtc->pipe; |
72419203 | 9125 | |
eb14cb74 VS |
9126 | if (INTEL_INFO(dev)->gen >= 5) { |
9127 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9128 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9129 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9130 | & ~TU_SIZE_MASK; | |
9131 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9132 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9133 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9134 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9135 | * gen < 8) and if DRRS is supported (to make sure the | |
9136 | * registers are not unnecessarily read). | |
9137 | */ | |
9138 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9139 | crtc->config->has_drrs) { |
b95af8be VK |
9140 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9141 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9142 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9143 | & ~TU_SIZE_MASK; | |
9144 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9145 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9146 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9147 | } | |
eb14cb74 VS |
9148 | } else { |
9149 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9150 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9151 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9152 | & ~TU_SIZE_MASK; | |
9153 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9154 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9155 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9156 | } | |
9157 | } | |
9158 | ||
9159 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9160 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9161 | { |
681a8504 | 9162 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9163 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9164 | else | |
9165 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9166 | &pipe_config->dp_m_n, |
9167 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9168 | } |
72419203 | 9169 | |
eb14cb74 | 9170 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9171 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9172 | { |
9173 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9174 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9175 | } |
9176 | ||
bd2e244f | 9177 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9178 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9179 | { |
9180 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9181 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
9182 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9183 | uint32_t ps_ctrl = 0; | |
9184 | int id = -1; | |
9185 | int i; | |
bd2e244f | 9186 | |
a1b2278e CK |
9187 | /* find scaler attached to this pipe */ |
9188 | for (i = 0; i < crtc->num_scalers; i++) { | |
9189 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9190 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9191 | id = i; | |
9192 | pipe_config->pch_pfit.enabled = true; | |
9193 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9194 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9195 | break; | |
9196 | } | |
9197 | } | |
bd2e244f | 9198 | |
a1b2278e CK |
9199 | scaler_state->scaler_id = id; |
9200 | if (id >= 0) { | |
9201 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9202 | } else { | |
9203 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9204 | } |
9205 | } | |
9206 | ||
5724dbd1 DL |
9207 | static void |
9208 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9209 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9210 | { |
9211 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9212 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 9213 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9214 | int pipe = crtc->pipe; |
9215 | int fourcc, pixel_format; | |
6761dd31 | 9216 | unsigned int aligned_height; |
bc8d7dff | 9217 | struct drm_framebuffer *fb; |
1b842c89 | 9218 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9219 | |
d9806c9f | 9220 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9221 | if (!intel_fb) { |
bc8d7dff DL |
9222 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9223 | return; | |
9224 | } | |
9225 | ||
1b842c89 DL |
9226 | fb = &intel_fb->base; |
9227 | ||
bc8d7dff | 9228 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9229 | if (!(val & PLANE_CTL_ENABLE)) |
9230 | goto error; | |
9231 | ||
bc8d7dff DL |
9232 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9233 | fourcc = skl_format_to_fourcc(pixel_format, | |
9234 | val & PLANE_CTL_ORDER_RGBX, | |
9235 | val & PLANE_CTL_ALPHA_MASK); | |
9236 | fb->pixel_format = fourcc; | |
9237 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9238 | ||
40f46283 DL |
9239 | tiling = val & PLANE_CTL_TILED_MASK; |
9240 | switch (tiling) { | |
9241 | case PLANE_CTL_TILED_LINEAR: | |
9242 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9243 | break; | |
9244 | case PLANE_CTL_TILED_X: | |
9245 | plane_config->tiling = I915_TILING_X; | |
9246 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9247 | break; | |
9248 | case PLANE_CTL_TILED_Y: | |
9249 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9250 | break; | |
9251 | case PLANE_CTL_TILED_YF: | |
9252 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9253 | break; | |
9254 | default: | |
9255 | MISSING_CASE(tiling); | |
9256 | goto error; | |
9257 | } | |
9258 | ||
bc8d7dff DL |
9259 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9260 | plane_config->base = base; | |
9261 | ||
9262 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9263 | ||
9264 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9265 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9266 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9267 | ||
9268 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9269 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9270 | fb->pixel_format); |
bc8d7dff DL |
9271 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9272 | ||
9273 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9274 | fb->pixel_format, |
9275 | fb->modifier[0]); | |
bc8d7dff | 9276 | |
f37b5c2b | 9277 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9278 | |
9279 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9280 | pipe_name(pipe), fb->width, fb->height, | |
9281 | fb->bits_per_pixel, base, fb->pitches[0], | |
9282 | plane_config->size); | |
9283 | ||
2d14030b | 9284 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9285 | return; |
9286 | ||
9287 | error: | |
9288 | kfree(fb); | |
9289 | } | |
9290 | ||
2fa2fe9a | 9291 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9292 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9293 | { |
9294 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9295 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
9296 | uint32_t tmp; |
9297 | ||
9298 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9299 | ||
9300 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9301 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9302 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9303 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9304 | |
9305 | /* We currently do not free assignements of panel fitters on | |
9306 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9307 | * differentiates them) so just WARN about this case for now. */ | |
9308 | if (IS_GEN7(dev)) { | |
9309 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9310 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9311 | } | |
2fa2fe9a | 9312 | } |
79e53945 JB |
9313 | } |
9314 | ||
5724dbd1 DL |
9315 | static void |
9316 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9317 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9318 | { |
9319 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9320 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 9321 | u32 val, base, offset; |
aeee5a49 | 9322 | int pipe = crtc->pipe; |
4c6baa59 | 9323 | int fourcc, pixel_format; |
6761dd31 | 9324 | unsigned int aligned_height; |
b113d5ee | 9325 | struct drm_framebuffer *fb; |
1b842c89 | 9326 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9327 | |
42a7b088 DL |
9328 | val = I915_READ(DSPCNTR(pipe)); |
9329 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9330 | return; | |
9331 | ||
d9806c9f | 9332 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9333 | if (!intel_fb) { |
4c6baa59 JB |
9334 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9335 | return; | |
9336 | } | |
9337 | ||
1b842c89 DL |
9338 | fb = &intel_fb->base; |
9339 | ||
18c5247e DV |
9340 | if (INTEL_INFO(dev)->gen >= 4) { |
9341 | if (val & DISPPLANE_TILED) { | |
49af449b | 9342 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9343 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9344 | } | |
9345 | } | |
4c6baa59 JB |
9346 | |
9347 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9348 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9349 | fb->pixel_format = fourcc; |
9350 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9351 | |
aeee5a49 | 9352 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9353 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9354 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9355 | } else { |
49af449b | 9356 | if (plane_config->tiling) |
aeee5a49 | 9357 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9358 | else |
aeee5a49 | 9359 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9360 | } |
9361 | plane_config->base = base; | |
9362 | ||
9363 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9364 | fb->width = ((val >> 16) & 0xfff) + 1; |
9365 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9366 | |
9367 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9368 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9369 | |
b113d5ee | 9370 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9371 | fb->pixel_format, |
9372 | fb->modifier[0]); | |
4c6baa59 | 9373 | |
f37b5c2b | 9374 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9375 | |
2844a921 DL |
9376 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9377 | pipe_name(pipe), fb->width, fb->height, | |
9378 | fb->bits_per_pixel, base, fb->pitches[0], | |
9379 | plane_config->size); | |
b113d5ee | 9380 | |
2d14030b | 9381 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9382 | } |
9383 | ||
0e8ffe1b | 9384 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9385 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9386 | { |
9387 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9388 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 9389 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9390 | uint32_t tmp; |
1729050e | 9391 | bool ret; |
0e8ffe1b | 9392 | |
1729050e ID |
9393 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9394 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9395 | return false; |
9396 | ||
e143a21c | 9397 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9398 | pipe_config->shared_dpll = NULL; |
eccb140b | 9399 | |
1729050e | 9400 | ret = false; |
0e8ffe1b DV |
9401 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9402 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9403 | goto out; |
0e8ffe1b | 9404 | |
42571aef VS |
9405 | switch (tmp & PIPECONF_BPC_MASK) { |
9406 | case PIPECONF_6BPC: | |
9407 | pipe_config->pipe_bpp = 18; | |
9408 | break; | |
9409 | case PIPECONF_8BPC: | |
9410 | pipe_config->pipe_bpp = 24; | |
9411 | break; | |
9412 | case PIPECONF_10BPC: | |
9413 | pipe_config->pipe_bpp = 30; | |
9414 | break; | |
9415 | case PIPECONF_12BPC: | |
9416 | pipe_config->pipe_bpp = 36; | |
9417 | break; | |
9418 | default: | |
9419 | break; | |
9420 | } | |
9421 | ||
b5a9fa09 DV |
9422 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9423 | pipe_config->limited_color_range = true; | |
9424 | ||
ab9412ba | 9425 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9426 | struct intel_shared_dpll *pll; |
8106ddbd | 9427 | enum intel_dpll_id pll_id; |
66e985c0 | 9428 | |
88adfff1 DV |
9429 | pipe_config->has_pch_encoder = true; |
9430 | ||
627eb5a3 DV |
9431 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9432 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9433 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9434 | |
9435 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9436 | |
2d1fe073 | 9437 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9438 | /* |
9439 | * The pipe->pch transcoder and pch transcoder->pll | |
9440 | * mapping is fixed. | |
9441 | */ | |
8106ddbd | 9442 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9443 | } else { |
9444 | tmp = I915_READ(PCH_DPLL_SEL); | |
9445 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9446 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9447 | else |
8106ddbd | 9448 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9449 | } |
66e985c0 | 9450 | |
8106ddbd ACO |
9451 | pipe_config->shared_dpll = |
9452 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9453 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9454 | |
2edd6443 ACO |
9455 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9456 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9457 | |
9458 | tmp = pipe_config->dpll_hw_state.dpll; | |
9459 | pipe_config->pixel_multiplier = | |
9460 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9461 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9462 | |
9463 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9464 | } else { |
9465 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9466 | } |
9467 | ||
1bd1bd80 | 9468 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9469 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9470 | |
2fa2fe9a DV |
9471 | ironlake_get_pfit_config(crtc, pipe_config); |
9472 | ||
1729050e ID |
9473 | ret = true; |
9474 | ||
9475 | out: | |
9476 | intel_display_power_put(dev_priv, power_domain); | |
9477 | ||
9478 | return ret; | |
0e8ffe1b DV |
9479 | } |
9480 | ||
be256dc7 PZ |
9481 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9482 | { | |
91c8a326 | 9483 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 9484 | struct intel_crtc *crtc; |
be256dc7 | 9485 | |
d3fcc808 | 9486 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9487 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9488 | pipe_name(crtc->pipe)); |
9489 | ||
e2c719b7 RC |
9490 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9491 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9492 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9493 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 9494 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 9495 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 9496 | "CPU PWM1 enabled\n"); |
c5107b87 | 9497 | if (IS_HASWELL(dev)) |
e2c719b7 | 9498 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9499 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9500 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9501 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9502 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9503 | "Utility pin enabled\n"); |
e2c719b7 | 9504 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9505 | |
9926ada1 PZ |
9506 | /* |
9507 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9508 | * interrupts remain enabled. We used to check for that, but since it's | |
9509 | * gen-specific and since we only disable LCPLL after we fully disable | |
9510 | * the interrupts, the check below should be enough. | |
9511 | */ | |
e2c719b7 | 9512 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9513 | } |
9514 | ||
9ccd5aeb PZ |
9515 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9516 | { | |
91c8a326 | 9517 | struct drm_device *dev = &dev_priv->drm; |
9ccd5aeb PZ |
9518 | |
9519 | if (IS_HASWELL(dev)) | |
9520 | return I915_READ(D_COMP_HSW); | |
9521 | else | |
9522 | return I915_READ(D_COMP_BDW); | |
9523 | } | |
9524 | ||
3c4c9b81 PZ |
9525 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9526 | { | |
91c8a326 | 9527 | struct drm_device *dev = &dev_priv->drm; |
3c4c9b81 PZ |
9528 | |
9529 | if (IS_HASWELL(dev)) { | |
9530 | mutex_lock(&dev_priv->rps.hw_lock); | |
9531 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9532 | val)) | |
f475dadf | 9533 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9534 | mutex_unlock(&dev_priv->rps.hw_lock); |
9535 | } else { | |
9ccd5aeb PZ |
9536 | I915_WRITE(D_COMP_BDW, val); |
9537 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9538 | } |
be256dc7 PZ |
9539 | } |
9540 | ||
9541 | /* | |
9542 | * This function implements pieces of two sequences from BSpec: | |
9543 | * - Sequence for display software to disable LCPLL | |
9544 | * - Sequence for display software to allow package C8+ | |
9545 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9546 | * register. Callers should take care of disabling all the display engine | |
9547 | * functions, doing the mode unset, fixing interrupts, etc. | |
9548 | */ | |
6ff58d53 PZ |
9549 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9550 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9551 | { |
9552 | uint32_t val; | |
9553 | ||
9554 | assert_can_disable_lcpll(dev_priv); | |
9555 | ||
9556 | val = I915_READ(LCPLL_CTL); | |
9557 | ||
9558 | if (switch_to_fclk) { | |
9559 | val |= LCPLL_CD_SOURCE_FCLK; | |
9560 | I915_WRITE(LCPLL_CTL, val); | |
9561 | ||
f53dd63f ID |
9562 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9563 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
9564 | DRM_ERROR("Switching to FCLK failed\n"); |
9565 | ||
9566 | val = I915_READ(LCPLL_CTL); | |
9567 | } | |
9568 | ||
9569 | val |= LCPLL_PLL_DISABLE; | |
9570 | I915_WRITE(LCPLL_CTL, val); | |
9571 | POSTING_READ(LCPLL_CTL); | |
9572 | ||
24d8441d | 9573 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
9574 | DRM_ERROR("LCPLL still locked\n"); |
9575 | ||
9ccd5aeb | 9576 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9577 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9578 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9579 | ndelay(100); |
9580 | ||
9ccd5aeb PZ |
9581 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9582 | 1)) | |
be256dc7 PZ |
9583 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9584 | ||
9585 | if (allow_power_down) { | |
9586 | val = I915_READ(LCPLL_CTL); | |
9587 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9588 | I915_WRITE(LCPLL_CTL, val); | |
9589 | POSTING_READ(LCPLL_CTL); | |
9590 | } | |
9591 | } | |
9592 | ||
9593 | /* | |
9594 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9595 | * source. | |
9596 | */ | |
6ff58d53 | 9597 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9598 | { |
9599 | uint32_t val; | |
9600 | ||
9601 | val = I915_READ(LCPLL_CTL); | |
9602 | ||
9603 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9604 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9605 | return; | |
9606 | ||
a8a8bd54 PZ |
9607 | /* |
9608 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9609 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9610 | */ |
59bad947 | 9611 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9612 | |
be256dc7 PZ |
9613 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9614 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9615 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9616 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9617 | } |
9618 | ||
9ccd5aeb | 9619 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9620 | val |= D_COMP_COMP_FORCE; |
9621 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9622 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9623 | |
9624 | val = I915_READ(LCPLL_CTL); | |
9625 | val &= ~LCPLL_PLL_DISABLE; | |
9626 | I915_WRITE(LCPLL_CTL, val); | |
9627 | ||
93220c08 CW |
9628 | if (intel_wait_for_register(dev_priv, |
9629 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
9630 | 5)) | |
be256dc7 PZ |
9631 | DRM_ERROR("LCPLL not locked yet\n"); |
9632 | ||
9633 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9634 | val = I915_READ(LCPLL_CTL); | |
9635 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9636 | I915_WRITE(LCPLL_CTL, val); | |
9637 | ||
f53dd63f ID |
9638 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9639 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
9640 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9641 | } | |
215733fa | 9642 | |
59bad947 | 9643 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
91c8a326 | 9644 | intel_update_cdclk(&dev_priv->drm); |
be256dc7 PZ |
9645 | } |
9646 | ||
765dab67 PZ |
9647 | /* |
9648 | * Package states C8 and deeper are really deep PC states that can only be | |
9649 | * reached when all the devices on the system allow it, so even if the graphics | |
9650 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9651 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9652 | * | |
9653 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9654 | * well is disabled and most interrupts are disabled, and these are also | |
9655 | * requirements for runtime PM. When these conditions are met, we manually do | |
9656 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9657 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9658 | * hang the machine. | |
9659 | * | |
9660 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9661 | * the state of some registers, so when we come back from PC8+ we need to | |
9662 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9663 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9664 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9665 | * because of the runtime PM support). | |
9666 | * | |
9667 | * For more, read "Display Sequences for Package C8" on the hardware | |
9668 | * documentation. | |
9669 | */ | |
a14cb6fc | 9670 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9671 | { |
91c8a326 | 9672 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
9673 | uint32_t val; |
9674 | ||
c67a470b PZ |
9675 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9676 | ||
c2699524 | 9677 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9678 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9679 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9680 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9681 | } | |
9682 | ||
9683 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9684 | hsw_disable_lcpll(dev_priv, true, true); |
9685 | } | |
9686 | ||
a14cb6fc | 9687 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9688 | { |
91c8a326 | 9689 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
9690 | uint32_t val; |
9691 | ||
c67a470b PZ |
9692 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9693 | ||
9694 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9695 | lpt_init_pch_refclk(dev); |
9696 | ||
c2699524 | 9697 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9698 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9699 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9700 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9701 | } | |
c67a470b PZ |
9702 | } |
9703 | ||
324513c0 | 9704 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9705 | { |
a821fc46 | 9706 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9707 | struct intel_atomic_state *old_intel_state = |
9708 | to_intel_atomic_state(old_state); | |
9709 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9710 | |
324513c0 | 9711 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
9712 | } |
9713 | ||
b432e5cf | 9714 | /* compute the max rate for new configuration */ |
27c329ed | 9715 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9716 | { |
565602d7 | 9717 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 9718 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
9719 | struct drm_crtc *crtc; |
9720 | struct drm_crtc_state *cstate; | |
27c329ed | 9721 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9722 | unsigned max_pixel_rate = 0, i; |
9723 | enum pipe pipe; | |
b432e5cf | 9724 | |
565602d7 ML |
9725 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9726 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9727 | |
565602d7 ML |
9728 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9729 | int pixel_rate; | |
27c329ed | 9730 | |
565602d7 ML |
9731 | crtc_state = to_intel_crtc_state(cstate); |
9732 | if (!crtc_state->base.enable) { | |
9733 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9734 | continue; |
565602d7 | 9735 | } |
b432e5cf | 9736 | |
27c329ed | 9737 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9738 | |
9739 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9740 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9741 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9742 | ||
565602d7 | 9743 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9744 | } |
9745 | ||
565602d7 ML |
9746 | for_each_pipe(dev_priv, pipe) |
9747 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9748 | ||
b432e5cf VS |
9749 | return max_pixel_rate; |
9750 | } | |
9751 | ||
9752 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9753 | { | |
fac5e23e | 9754 | struct drm_i915_private *dev_priv = to_i915(dev); |
b432e5cf VS |
9755 | uint32_t val, data; |
9756 | int ret; | |
9757 | ||
9758 | if (WARN((I915_READ(LCPLL_CTL) & | |
9759 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9760 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9761 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9762 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9763 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9764 | return; | |
9765 | ||
9766 | mutex_lock(&dev_priv->rps.hw_lock); | |
9767 | ret = sandybridge_pcode_write(dev_priv, | |
9768 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9769 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9770 | if (ret) { | |
9771 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9772 | return; | |
9773 | } | |
9774 | ||
9775 | val = I915_READ(LCPLL_CTL); | |
9776 | val |= LCPLL_CD_SOURCE_FCLK; | |
9777 | I915_WRITE(LCPLL_CTL, val); | |
9778 | ||
5ba00178 TU |
9779 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9780 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9781 | DRM_ERROR("Switching to FCLK failed\n"); |
9782 | ||
9783 | val = I915_READ(LCPLL_CTL); | |
9784 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9785 | ||
9786 | switch (cdclk) { | |
9787 | case 450000: | |
9788 | val |= LCPLL_CLK_FREQ_450; | |
9789 | data = 0; | |
9790 | break; | |
9791 | case 540000: | |
9792 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9793 | data = 1; | |
9794 | break; | |
9795 | case 337500: | |
9796 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9797 | data = 2; | |
9798 | break; | |
9799 | case 675000: | |
9800 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9801 | data = 3; | |
9802 | break; | |
9803 | default: | |
9804 | WARN(1, "invalid cdclk frequency\n"); | |
9805 | return; | |
9806 | } | |
9807 | ||
9808 | I915_WRITE(LCPLL_CTL, val); | |
9809 | ||
9810 | val = I915_READ(LCPLL_CTL); | |
9811 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9812 | I915_WRITE(LCPLL_CTL, val); | |
9813 | ||
5ba00178 TU |
9814 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9815 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9816 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9817 | ||
9818 | mutex_lock(&dev_priv->rps.hw_lock); | |
9819 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9820 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9821 | ||
7f1052a8 VS |
9822 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
9823 | ||
b432e5cf VS |
9824 | intel_update_cdclk(dev); |
9825 | ||
9826 | WARN(cdclk != dev_priv->cdclk_freq, | |
9827 | "cdclk requested %d kHz but got %d kHz\n", | |
9828 | cdclk, dev_priv->cdclk_freq); | |
9829 | } | |
9830 | ||
587c7914 VS |
9831 | static int broadwell_calc_cdclk(int max_pixclk) |
9832 | { | |
9833 | if (max_pixclk > 540000) | |
9834 | return 675000; | |
9835 | else if (max_pixclk > 450000) | |
9836 | return 540000; | |
9837 | else if (max_pixclk > 337500) | |
9838 | return 450000; | |
9839 | else | |
9840 | return 337500; | |
9841 | } | |
9842 | ||
27c329ed | 9843 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9844 | { |
27c329ed | 9845 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9846 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9847 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9848 | int cdclk; |
9849 | ||
9850 | /* | |
9851 | * FIXME should also account for plane ratio | |
9852 | * once 64bpp pixel formats are supported. | |
9853 | */ | |
587c7914 | 9854 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 9855 | |
b432e5cf | 9856 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9857 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9858 | cdclk, dev_priv->max_cdclk_freq); | |
9859 | return -EINVAL; | |
b432e5cf VS |
9860 | } |
9861 | ||
1a617b77 ML |
9862 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9863 | if (!intel_state->active_crtcs) | |
587c7914 | 9864 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
9865 | |
9866 | return 0; | |
9867 | } | |
9868 | ||
27c329ed | 9869 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9870 | { |
27c329ed | 9871 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9872 | struct intel_atomic_state *old_intel_state = |
9873 | to_intel_atomic_state(old_state); | |
9874 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9875 | |
27c329ed | 9876 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9877 | } |
9878 | ||
c89e39f3 CT |
9879 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
9880 | { | |
9881 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
9882 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
9883 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 9884 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
9885 | int cdclk; |
9886 | ||
9887 | /* | |
9888 | * FIXME should also account for plane ratio | |
9889 | * once 64bpp pixel formats are supported. | |
9890 | */ | |
a8ca4934 | 9891 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
9892 | |
9893 | /* | |
9894 | * FIXME move the cdclk caclulation to | |
9895 | * compute_config() so we can fail gracegully. | |
9896 | */ | |
9897 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9898 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9899 | cdclk, dev_priv->max_cdclk_freq); | |
9900 | cdclk = dev_priv->max_cdclk_freq; | |
9901 | } | |
9902 | ||
9903 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
9904 | if (!intel_state->active_crtcs) | |
a8ca4934 | 9905 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
9906 | |
9907 | return 0; | |
9908 | } | |
9909 | ||
9910 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
9911 | { | |
1cd593e0 VS |
9912 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
9913 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
9914 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
9915 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 9916 | |
1cd593e0 | 9917 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
9918 | } |
9919 | ||
190f68c5 ACO |
9920 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9921 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9922 | { |
d7edc4e5 | 9923 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
9924 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
9925 | return -EINVAL; | |
9926 | } | |
716c2e55 | 9927 | |
c7653199 | 9928 | crtc->lowfreq_avail = false; |
644cef34 | 9929 | |
c8f7a0db | 9930 | return 0; |
79e53945 JB |
9931 | } |
9932 | ||
3760b59c S |
9933 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9934 | enum port port, | |
9935 | struct intel_crtc_state *pipe_config) | |
9936 | { | |
8106ddbd ACO |
9937 | enum intel_dpll_id id; |
9938 | ||
3760b59c S |
9939 | switch (port) { |
9940 | case PORT_A: | |
9941 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 9942 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9943 | break; |
9944 | case PORT_B: | |
9945 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 9946 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9947 | break; |
9948 | case PORT_C: | |
9949 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 9950 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9951 | break; |
9952 | default: | |
9953 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9954 | return; |
3760b59c | 9955 | } |
8106ddbd ACO |
9956 | |
9957 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9958 | } |
9959 | ||
96b7dfb7 S |
9960 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9961 | enum port port, | |
5cec258b | 9962 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9963 | { |
8106ddbd | 9964 | enum intel_dpll_id id; |
a3c988ea | 9965 | u32 temp; |
96b7dfb7 S |
9966 | |
9967 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9968 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9969 | ||
9970 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 9971 | case SKL_DPLL0: |
a3c988ea ACO |
9972 | id = DPLL_ID_SKL_DPLL0; |
9973 | break; | |
96b7dfb7 | 9974 | case SKL_DPLL1: |
8106ddbd | 9975 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
9976 | break; |
9977 | case SKL_DPLL2: | |
8106ddbd | 9978 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
9979 | break; |
9980 | case SKL_DPLL3: | |
8106ddbd | 9981 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 9982 | break; |
8106ddbd ACO |
9983 | default: |
9984 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9985 | return; | |
96b7dfb7 | 9986 | } |
8106ddbd ACO |
9987 | |
9988 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9989 | } |
9990 | ||
7d2c8175 DL |
9991 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9992 | enum port port, | |
5cec258b | 9993 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9994 | { |
8106ddbd ACO |
9995 | enum intel_dpll_id id; |
9996 | ||
7d2c8175 DL |
9997 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
9998 | ||
9999 | switch (pipe_config->ddi_pll_sel) { | |
10000 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 10001 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
10002 | break; |
10003 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 10004 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 10005 | break; |
00490c22 | 10006 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 10007 | id = DPLL_ID_SPLL; |
79bd23da | 10008 | break; |
9d16da65 ACO |
10009 | case PORT_CLK_SEL_LCPLL_810: |
10010 | id = DPLL_ID_LCPLL_810; | |
10011 | break; | |
10012 | case PORT_CLK_SEL_LCPLL_1350: | |
10013 | id = DPLL_ID_LCPLL_1350; | |
10014 | break; | |
10015 | case PORT_CLK_SEL_LCPLL_2700: | |
10016 | id = DPLL_ID_LCPLL_2700; | |
10017 | break; | |
8106ddbd ACO |
10018 | default: |
10019 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
10020 | /* fall through */ | |
10021 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 10022 | return; |
7d2c8175 | 10023 | } |
8106ddbd ACO |
10024 | |
10025 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
10026 | } |
10027 | ||
cf30429e JN |
10028 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
10029 | struct intel_crtc_state *pipe_config, | |
10030 | unsigned long *power_domain_mask) | |
10031 | { | |
10032 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10033 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
10034 | enum intel_display_power_domain power_domain; |
10035 | u32 tmp; | |
10036 | ||
d9a7bc67 ID |
10037 | /* |
10038 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
10039 | * transcoder handled below. | |
10040 | */ | |
cf30429e JN |
10041 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
10042 | ||
10043 | /* | |
10044 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
10045 | * consistency and less surprising code; it's in always on power). | |
10046 | */ | |
10047 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
10048 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10049 | enum pipe trans_edp_pipe; | |
10050 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10051 | default: | |
10052 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10053 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10054 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10055 | trans_edp_pipe = PIPE_A; | |
10056 | break; | |
10057 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10058 | trans_edp_pipe = PIPE_B; | |
10059 | break; | |
10060 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10061 | trans_edp_pipe = PIPE_C; | |
10062 | break; | |
10063 | } | |
10064 | ||
10065 | if (trans_edp_pipe == crtc->pipe) | |
10066 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10067 | } | |
10068 | ||
10069 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
10070 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10071 | return false; | |
10072 | *power_domain_mask |= BIT(power_domain); | |
10073 | ||
10074 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
10075 | ||
10076 | return tmp & PIPECONF_ENABLE; | |
10077 | } | |
10078 | ||
4d1de975 JN |
10079 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10080 | struct intel_crtc_state *pipe_config, | |
10081 | unsigned long *power_domain_mask) | |
10082 | { | |
10083 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10084 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
10085 | enum intel_display_power_domain power_domain; |
10086 | enum port port; | |
10087 | enum transcoder cpu_transcoder; | |
10088 | u32 tmp; | |
10089 | ||
4d1de975 JN |
10090 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
10091 | if (port == PORT_A) | |
10092 | cpu_transcoder = TRANSCODER_DSI_A; | |
10093 | else | |
10094 | cpu_transcoder = TRANSCODER_DSI_C; | |
10095 | ||
10096 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10097 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10098 | continue; | |
10099 | *power_domain_mask |= BIT(power_domain); | |
10100 | ||
db18b6a6 ID |
10101 | /* |
10102 | * The PLL needs to be enabled with a valid divider | |
10103 | * configuration, otherwise accessing DSI registers will hang | |
10104 | * the machine. See BSpec North Display Engine | |
10105 | * registers/MIPI[BXT]. We can break out here early, since we | |
10106 | * need the same DSI PLL to be enabled for both DSI ports. | |
10107 | */ | |
10108 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10109 | break; | |
10110 | ||
4d1de975 JN |
10111 | /* XXX: this works for video mode only */ |
10112 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10113 | if (!(tmp & DPI_ENABLE)) | |
10114 | continue; | |
10115 | ||
10116 | tmp = I915_READ(MIPI_CTRL(port)); | |
10117 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10118 | continue; | |
10119 | ||
10120 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
10121 | break; |
10122 | } | |
10123 | ||
d7edc4e5 | 10124 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
10125 | } |
10126 | ||
26804afd | 10127 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10128 | struct intel_crtc_state *pipe_config) |
26804afd DV |
10129 | { |
10130 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10131 | struct drm_i915_private *dev_priv = to_i915(dev); |
d452c5b6 | 10132 | struct intel_shared_dpll *pll; |
26804afd DV |
10133 | enum port port; |
10134 | uint32_t tmp; | |
10135 | ||
10136 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10137 | ||
10138 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10139 | ||
ef11bdb3 | 10140 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 10141 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
10142 | else if (IS_BROXTON(dev)) |
10143 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
10144 | else |
10145 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10146 | |
8106ddbd ACO |
10147 | pll = pipe_config->shared_dpll; |
10148 | if (pll) { | |
2edd6443 ACO |
10149 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10150 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10151 | } |
10152 | ||
26804afd DV |
10153 | /* |
10154 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10155 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10156 | * the PCH transcoder is on. | |
10157 | */ | |
ca370455 DL |
10158 | if (INTEL_INFO(dev)->gen < 9 && |
10159 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
10160 | pipe_config->has_pch_encoder = true; |
10161 | ||
10162 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10163 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10164 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10165 | ||
10166 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10167 | } | |
10168 | } | |
10169 | ||
0e8ffe1b | 10170 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10171 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10172 | { |
10173 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10174 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e ID |
10175 | enum intel_display_power_domain power_domain; |
10176 | unsigned long power_domain_mask; | |
cf30429e | 10177 | bool active; |
0e8ffe1b | 10178 | |
1729050e ID |
10179 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10180 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10181 | return false; |
1729050e ID |
10182 | power_domain_mask = BIT(power_domain); |
10183 | ||
8106ddbd | 10184 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10185 | |
cf30429e | 10186 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10187 | |
d7edc4e5 VS |
10188 | if (IS_BROXTON(dev_priv) && |
10189 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { | |
10190 | WARN_ON(active); | |
10191 | active = true; | |
4d1de975 JN |
10192 | } |
10193 | ||
cf30429e | 10194 | if (!active) |
1729050e | 10195 | goto out; |
0e8ffe1b | 10196 | |
d7edc4e5 | 10197 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
10198 | haswell_get_ddi_port_state(crtc, pipe_config); |
10199 | intel_get_pipe_timings(crtc, pipe_config); | |
10200 | } | |
627eb5a3 | 10201 | |
bc58be60 | 10202 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10203 | |
05dc698c LL |
10204 | pipe_config->gamma_mode = |
10205 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10206 | ||
a1b2278e CK |
10207 | if (INTEL_INFO(dev)->gen >= 9) { |
10208 | skl_init_scalers(dev, crtc, pipe_config); | |
10209 | } | |
10210 | ||
af99ceda CK |
10211 | if (INTEL_INFO(dev)->gen >= 9) { |
10212 | pipe_config->scaler_state.scaler_id = -1; | |
10213 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10214 | } | |
10215 | ||
1729050e ID |
10216 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10217 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10218 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10219 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10220 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10221 | else |
1c132b44 | 10222 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10223 | } |
88adfff1 | 10224 | |
e59150dc JB |
10225 | if (IS_HASWELL(dev)) |
10226 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10227 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10228 | |
4d1de975 JN |
10229 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10230 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10231 | pipe_config->pixel_multiplier = |
10232 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10233 | } else { | |
10234 | pipe_config->pixel_multiplier = 1; | |
10235 | } | |
6c49f241 | 10236 | |
1729050e ID |
10237 | out: |
10238 | for_each_power_domain(power_domain, power_domain_mask) | |
10239 | intel_display_power_put(dev_priv, power_domain); | |
10240 | ||
cf30429e | 10241 | return active; |
0e8ffe1b DV |
10242 | } |
10243 | ||
55a08b3f ML |
10244 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10245 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10246 | { |
10247 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10248 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 10249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 10250 | uint32_t cntl = 0, size = 0; |
560b85bb | 10251 | |
55a08b3f ML |
10252 | if (plane_state && plane_state->visible) { |
10253 | unsigned int width = plane_state->base.crtc_w; | |
10254 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10255 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10256 | ||
10257 | switch (stride) { | |
10258 | default: | |
10259 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10260 | width, stride); | |
10261 | stride = 256; | |
10262 | /* fallthrough */ | |
10263 | case 256: | |
10264 | case 512: | |
10265 | case 1024: | |
10266 | case 2048: | |
10267 | break; | |
4b0e333e CW |
10268 | } |
10269 | ||
dc41c154 VS |
10270 | cntl |= CURSOR_ENABLE | |
10271 | CURSOR_GAMMA_ENABLE | | |
10272 | CURSOR_FORMAT_ARGB | | |
10273 | CURSOR_STRIDE(stride); | |
10274 | ||
10275 | size = (height << 12) | width; | |
4b0e333e | 10276 | } |
560b85bb | 10277 | |
dc41c154 VS |
10278 | if (intel_crtc->cursor_cntl != 0 && |
10279 | (intel_crtc->cursor_base != base || | |
10280 | intel_crtc->cursor_size != size || | |
10281 | intel_crtc->cursor_cntl != cntl)) { | |
10282 | /* On these chipsets we can only modify the base/size/stride | |
10283 | * whilst the cursor is disabled. | |
10284 | */ | |
0b87c24e VS |
10285 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10286 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10287 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10288 | } |
560b85bb | 10289 | |
99d1f387 | 10290 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10291 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10292 | intel_crtc->cursor_base = base; |
10293 | } | |
4726e0b0 | 10294 | |
dc41c154 VS |
10295 | if (intel_crtc->cursor_size != size) { |
10296 | I915_WRITE(CURSIZE, size); | |
10297 | intel_crtc->cursor_size = size; | |
4b0e333e | 10298 | } |
560b85bb | 10299 | |
4b0e333e | 10300 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10301 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10302 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10303 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10304 | } |
560b85bb CW |
10305 | } |
10306 | ||
55a08b3f ML |
10307 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10308 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10309 | { |
10310 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10311 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
10312 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10313 | int pipe = intel_crtc->pipe; | |
663f3122 | 10314 | uint32_t cntl = 0; |
4b0e333e | 10315 | |
55a08b3f | 10316 | if (plane_state && plane_state->visible) { |
4b0e333e | 10317 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10318 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10319 | case 64: |
10320 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10321 | break; | |
10322 | case 128: | |
10323 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10324 | break; | |
10325 | case 256: | |
10326 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10327 | break; | |
10328 | default: | |
55a08b3f | 10329 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10330 | return; |
65a21cd6 | 10331 | } |
4b0e333e | 10332 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10333 | |
fc6f93bc | 10334 | if (HAS_DDI(dev)) |
47bf17a7 | 10335 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10336 | |
55a08b3f ML |
10337 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10338 | cntl |= CURSOR_ROTATE_180; | |
10339 | } | |
4398ad45 | 10340 | |
4b0e333e CW |
10341 | if (intel_crtc->cursor_cntl != cntl) { |
10342 | I915_WRITE(CURCNTR(pipe), cntl); | |
10343 | POSTING_READ(CURCNTR(pipe)); | |
10344 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10345 | } |
4b0e333e | 10346 | |
65a21cd6 | 10347 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10348 | I915_WRITE(CURBASE(pipe), base); |
10349 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10350 | |
10351 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10352 | } |
10353 | ||
cda4b7d3 | 10354 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10355 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10356 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10357 | { |
10358 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10359 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
10360 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10361 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10362 | u32 base = intel_crtc->cursor_addr; |
10363 | u32 pos = 0; | |
cda4b7d3 | 10364 | |
55a08b3f ML |
10365 | if (plane_state) { |
10366 | int x = plane_state->base.crtc_x; | |
10367 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10368 | |
55a08b3f ML |
10369 | if (x < 0) { |
10370 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10371 | x = -x; | |
10372 | } | |
10373 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10374 | |
55a08b3f ML |
10375 | if (y < 0) { |
10376 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10377 | y = -y; | |
10378 | } | |
10379 | pos |= y << CURSOR_Y_SHIFT; | |
10380 | ||
10381 | /* ILK+ do this automagically */ | |
10382 | if (HAS_GMCH_DISPLAY(dev) && | |
10383 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10384 | base += (plane_state->base.crtc_h * | |
10385 | plane_state->base.crtc_w - 1) * 4; | |
10386 | } | |
cda4b7d3 | 10387 | } |
cda4b7d3 | 10388 | |
5efb3e28 VS |
10389 | I915_WRITE(CURPOS(pipe), pos); |
10390 | ||
8ac54669 | 10391 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10392 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10393 | else |
55a08b3f | 10394 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10395 | } |
10396 | ||
dc41c154 VS |
10397 | static bool cursor_size_ok(struct drm_device *dev, |
10398 | uint32_t width, uint32_t height) | |
10399 | { | |
10400 | if (width == 0 || height == 0) | |
10401 | return false; | |
10402 | ||
10403 | /* | |
10404 | * 845g/865g are special in that they are only limited by | |
10405 | * the width of their cursors, the height is arbitrary up to | |
10406 | * the precision of the register. Everything else requires | |
10407 | * square cursors, limited to a few power-of-two sizes. | |
10408 | */ | |
10409 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10410 | if ((width & 63) != 0) | |
10411 | return false; | |
10412 | ||
10413 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10414 | return false; | |
10415 | ||
10416 | if (height > 1023) | |
10417 | return false; | |
10418 | } else { | |
10419 | switch (width | height) { | |
10420 | case 256: | |
10421 | case 128: | |
10422 | if (IS_GEN2(dev)) | |
10423 | return false; | |
10424 | case 64: | |
10425 | break; | |
10426 | default: | |
10427 | return false; | |
10428 | } | |
10429 | } | |
10430 | ||
10431 | return true; | |
10432 | } | |
10433 | ||
79e53945 JB |
10434 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10435 | static struct drm_display_mode load_detect_mode = { | |
10436 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10437 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10438 | }; | |
10439 | ||
a8bb6818 DV |
10440 | struct drm_framebuffer * |
10441 | __intel_framebuffer_create(struct drm_device *dev, | |
10442 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10443 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10444 | { |
10445 | struct intel_framebuffer *intel_fb; | |
10446 | int ret; | |
10447 | ||
10448 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10449 | if (!intel_fb) |
d2dff872 | 10450 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10451 | |
10452 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10453 | if (ret) |
10454 | goto err; | |
d2dff872 CW |
10455 | |
10456 | return &intel_fb->base; | |
dcb1394e | 10457 | |
dd4916c5 | 10458 | err: |
dd4916c5 | 10459 | kfree(intel_fb); |
dd4916c5 | 10460 | return ERR_PTR(ret); |
d2dff872 CW |
10461 | } |
10462 | ||
b5ea642a | 10463 | static struct drm_framebuffer * |
a8bb6818 DV |
10464 | intel_framebuffer_create(struct drm_device *dev, |
10465 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10466 | struct drm_i915_gem_object *obj) | |
10467 | { | |
10468 | struct drm_framebuffer *fb; | |
10469 | int ret; | |
10470 | ||
10471 | ret = i915_mutex_lock_interruptible(dev); | |
10472 | if (ret) | |
10473 | return ERR_PTR(ret); | |
10474 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10475 | mutex_unlock(&dev->struct_mutex); | |
10476 | ||
10477 | return fb; | |
10478 | } | |
10479 | ||
d2dff872 CW |
10480 | static u32 |
10481 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10482 | { | |
10483 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10484 | return ALIGN(pitch, 64); | |
10485 | } | |
10486 | ||
10487 | static u32 | |
10488 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10489 | { | |
10490 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10491 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10492 | } |
10493 | ||
10494 | static struct drm_framebuffer * | |
10495 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10496 | struct drm_display_mode *mode, | |
10497 | int depth, int bpp) | |
10498 | { | |
dcb1394e | 10499 | struct drm_framebuffer *fb; |
d2dff872 | 10500 | struct drm_i915_gem_object *obj; |
0fed39bd | 10501 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 10502 | |
d37cd8a8 | 10503 | obj = i915_gem_object_create(dev, |
d2dff872 | 10504 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
10505 | if (IS_ERR(obj)) |
10506 | return ERR_CAST(obj); | |
d2dff872 CW |
10507 | |
10508 | mode_cmd.width = mode->hdisplay; | |
10509 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10510 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10511 | bpp); | |
5ca0c34a | 10512 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10513 | |
dcb1394e LW |
10514 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10515 | if (IS_ERR(fb)) | |
34911fd3 | 10516 | i915_gem_object_put_unlocked(obj); |
dcb1394e LW |
10517 | |
10518 | return fb; | |
d2dff872 CW |
10519 | } |
10520 | ||
10521 | static struct drm_framebuffer * | |
10522 | mode_fits_in_fbdev(struct drm_device *dev, | |
10523 | struct drm_display_mode *mode) | |
10524 | { | |
0695726e | 10525 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 10526 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
10527 | struct drm_i915_gem_object *obj; |
10528 | struct drm_framebuffer *fb; | |
10529 | ||
4c0e5528 | 10530 | if (!dev_priv->fbdev) |
d2dff872 CW |
10531 | return NULL; |
10532 | ||
4c0e5528 | 10533 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10534 | return NULL; |
10535 | ||
4c0e5528 DV |
10536 | obj = dev_priv->fbdev->fb->obj; |
10537 | BUG_ON(!obj); | |
10538 | ||
8bcd4553 | 10539 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10540 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10541 | fb->bits_per_pixel)) | |
d2dff872 CW |
10542 | return NULL; |
10543 | ||
01f2c773 | 10544 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10545 | return NULL; |
10546 | ||
edde3617 | 10547 | drm_framebuffer_reference(fb); |
d2dff872 | 10548 | return fb; |
4520f53a DV |
10549 | #else |
10550 | return NULL; | |
10551 | #endif | |
d2dff872 CW |
10552 | } |
10553 | ||
d3a40d1b ACO |
10554 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10555 | struct drm_crtc *crtc, | |
10556 | struct drm_display_mode *mode, | |
10557 | struct drm_framebuffer *fb, | |
10558 | int x, int y) | |
10559 | { | |
10560 | struct drm_plane_state *plane_state; | |
10561 | int hdisplay, vdisplay; | |
10562 | int ret; | |
10563 | ||
10564 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10565 | if (IS_ERR(plane_state)) | |
10566 | return PTR_ERR(plane_state); | |
10567 | ||
10568 | if (mode) | |
10569 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10570 | else | |
10571 | hdisplay = vdisplay = 0; | |
10572 | ||
10573 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10574 | if (ret) | |
10575 | return ret; | |
10576 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10577 | plane_state->crtc_x = 0; | |
10578 | plane_state->crtc_y = 0; | |
10579 | plane_state->crtc_w = hdisplay; | |
10580 | plane_state->crtc_h = vdisplay; | |
10581 | plane_state->src_x = x << 16; | |
10582 | plane_state->src_y = y << 16; | |
10583 | plane_state->src_w = hdisplay << 16; | |
10584 | plane_state->src_h = vdisplay << 16; | |
10585 | ||
10586 | return 0; | |
10587 | } | |
10588 | ||
d2434ab7 | 10589 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10590 | struct drm_display_mode *mode, |
51fd371b RC |
10591 | struct intel_load_detect_pipe *old, |
10592 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10593 | { |
10594 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10595 | struct intel_encoder *intel_encoder = |
10596 | intel_attached_encoder(connector); | |
79e53945 | 10597 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10598 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10599 | struct drm_crtc *crtc = NULL; |
10600 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10601 | struct drm_framebuffer *fb; |
51fd371b | 10602 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10603 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10604 | struct drm_connector_state *connector_state; |
4be07317 | 10605 | struct intel_crtc_state *crtc_state; |
51fd371b | 10606 | int ret, i = -1; |
79e53945 | 10607 | |
d2dff872 | 10608 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10609 | connector->base.id, connector->name, |
8e329a03 | 10610 | encoder->base.id, encoder->name); |
d2dff872 | 10611 | |
edde3617 ML |
10612 | old->restore_state = NULL; |
10613 | ||
51fd371b RC |
10614 | retry: |
10615 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10616 | if (ret) | |
ad3c558f | 10617 | goto fail; |
6e9f798d | 10618 | |
79e53945 JB |
10619 | /* |
10620 | * Algorithm gets a little messy: | |
7a5e4805 | 10621 | * |
79e53945 JB |
10622 | * - if the connector already has an assigned crtc, use it (but make |
10623 | * sure it's on first) | |
7a5e4805 | 10624 | * |
79e53945 JB |
10625 | * - try to find the first unused crtc that can drive this connector, |
10626 | * and use that if we find one | |
79e53945 JB |
10627 | */ |
10628 | ||
10629 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10630 | if (connector->state->crtc) { |
10631 | crtc = connector->state->crtc; | |
8261b191 | 10632 | |
51fd371b | 10633 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10634 | if (ret) |
ad3c558f | 10635 | goto fail; |
8261b191 CW |
10636 | |
10637 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10638 | goto found; |
79e53945 JB |
10639 | } |
10640 | ||
10641 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10642 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10643 | i++; |
10644 | if (!(encoder->possible_crtcs & (1 << i))) | |
10645 | continue; | |
edde3617 ML |
10646 | |
10647 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10648 | if (ret) | |
10649 | goto fail; | |
10650 | ||
10651 | if (possible_crtc->state->enable) { | |
10652 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10653 | continue; |
edde3617 | 10654 | } |
a459249c VS |
10655 | |
10656 | crtc = possible_crtc; | |
10657 | break; | |
79e53945 JB |
10658 | } |
10659 | ||
10660 | /* | |
10661 | * If we didn't find an unused CRTC, don't use any. | |
10662 | */ | |
10663 | if (!crtc) { | |
7173188d | 10664 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10665 | goto fail; |
79e53945 JB |
10666 | } |
10667 | ||
edde3617 ML |
10668 | found: |
10669 | intel_crtc = to_intel_crtc(crtc); | |
10670 | ||
4d02e2de DV |
10671 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10672 | if (ret) | |
ad3c558f | 10673 | goto fail; |
79e53945 | 10674 | |
83a57153 | 10675 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10676 | restore_state = drm_atomic_state_alloc(dev); |
10677 | if (!state || !restore_state) { | |
10678 | ret = -ENOMEM; | |
10679 | goto fail; | |
10680 | } | |
83a57153 ACO |
10681 | |
10682 | state->acquire_ctx = ctx; | |
edde3617 | 10683 | restore_state->acquire_ctx = ctx; |
83a57153 | 10684 | |
944b0c76 ACO |
10685 | connector_state = drm_atomic_get_connector_state(state, connector); |
10686 | if (IS_ERR(connector_state)) { | |
10687 | ret = PTR_ERR(connector_state); | |
10688 | goto fail; | |
10689 | } | |
10690 | ||
edde3617 ML |
10691 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10692 | if (ret) | |
10693 | goto fail; | |
944b0c76 | 10694 | |
4be07317 ACO |
10695 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10696 | if (IS_ERR(crtc_state)) { | |
10697 | ret = PTR_ERR(crtc_state); | |
10698 | goto fail; | |
10699 | } | |
10700 | ||
49d6fa21 | 10701 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10702 | |
6492711d CW |
10703 | if (!mode) |
10704 | mode = &load_detect_mode; | |
79e53945 | 10705 | |
d2dff872 CW |
10706 | /* We need a framebuffer large enough to accommodate all accesses |
10707 | * that the plane may generate whilst we perform load detection. | |
10708 | * We can not rely on the fbcon either being present (we get called | |
10709 | * during its initialisation to detect all boot displays, or it may | |
10710 | * not even exist) or that it is large enough to satisfy the | |
10711 | * requested mode. | |
10712 | */ | |
94352cf9 DV |
10713 | fb = mode_fits_in_fbdev(dev, mode); |
10714 | if (fb == NULL) { | |
d2dff872 | 10715 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10716 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10717 | } else |
10718 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10719 | if (IS_ERR(fb)) { |
d2dff872 | 10720 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10721 | goto fail; |
79e53945 | 10722 | } |
79e53945 | 10723 | |
d3a40d1b ACO |
10724 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10725 | if (ret) | |
10726 | goto fail; | |
10727 | ||
edde3617 ML |
10728 | drm_framebuffer_unreference(fb); |
10729 | ||
10730 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10731 | if (ret) | |
10732 | goto fail; | |
10733 | ||
10734 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10735 | if (!ret) | |
10736 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10737 | if (!ret) | |
10738 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10739 | if (ret) { | |
10740 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10741 | goto fail; | |
10742 | } | |
8c7b5ccb | 10743 | |
3ba86073 ML |
10744 | ret = drm_atomic_commit(state); |
10745 | if (ret) { | |
6492711d | 10746 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10747 | goto fail; |
79e53945 | 10748 | } |
edde3617 ML |
10749 | |
10750 | old->restore_state = restore_state; | |
7173188d | 10751 | |
79e53945 | 10752 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10753 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10754 | return true; |
412b61d8 | 10755 | |
ad3c558f | 10756 | fail: |
e5d958ef | 10757 | drm_atomic_state_free(state); |
edde3617 ML |
10758 | drm_atomic_state_free(restore_state); |
10759 | restore_state = state = NULL; | |
83a57153 | 10760 | |
51fd371b RC |
10761 | if (ret == -EDEADLK) { |
10762 | drm_modeset_backoff(ctx); | |
10763 | goto retry; | |
10764 | } | |
10765 | ||
412b61d8 | 10766 | return false; |
79e53945 JB |
10767 | } |
10768 | ||
d2434ab7 | 10769 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10770 | struct intel_load_detect_pipe *old, |
10771 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10772 | { |
d2434ab7 DV |
10773 | struct intel_encoder *intel_encoder = |
10774 | intel_attached_encoder(connector); | |
4ef69c7a | 10775 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10776 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10777 | int ret; |
79e53945 | 10778 | |
d2dff872 | 10779 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10780 | connector->base.id, connector->name, |
8e329a03 | 10781 | encoder->base.id, encoder->name); |
d2dff872 | 10782 | |
edde3617 | 10783 | if (!state) |
0622a53c | 10784 | return; |
79e53945 | 10785 | |
edde3617 ML |
10786 | ret = drm_atomic_commit(state); |
10787 | if (ret) { | |
10788 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10789 | drm_atomic_state_free(state); | |
10790 | } | |
79e53945 JB |
10791 | } |
10792 | ||
da4a1efa | 10793 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10794 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 10795 | { |
fac5e23e | 10796 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
10797 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
10798 | ||
10799 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10800 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10801 | else if (HAS_PCH_SPLIT(dev)) |
10802 | return 120000; | |
10803 | else if (!IS_GEN2(dev)) | |
10804 | return 96000; | |
10805 | else | |
10806 | return 48000; | |
10807 | } | |
10808 | ||
79e53945 | 10809 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10810 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10811 | struct intel_crtc_state *pipe_config) |
79e53945 | 10812 | { |
f1f644dc | 10813 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 10814 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 10815 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10816 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10817 | u32 fp; |
9e2c8475 | 10818 | struct dpll clock; |
dccbea3b | 10819 | int port_clock; |
da4a1efa | 10820 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10821 | |
10822 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10823 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10824 | else |
293623f7 | 10825 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10826 | |
10827 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10828 | if (IS_PINEVIEW(dev)) { |
10829 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10830 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10831 | } else { |
10832 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10833 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10834 | } | |
10835 | ||
a6c45cf0 | 10836 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10837 | if (IS_PINEVIEW(dev)) |
10838 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10839 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10840 | else |
10841 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10842 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10843 | ||
10844 | switch (dpll & DPLL_MODE_MASK) { | |
10845 | case DPLLB_MODE_DAC_SERIAL: | |
10846 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10847 | 5 : 10; | |
10848 | break; | |
10849 | case DPLLB_MODE_LVDS: | |
10850 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10851 | 7 : 14; | |
10852 | break; | |
10853 | default: | |
28c97730 | 10854 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10855 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10856 | return; |
79e53945 JB |
10857 | } |
10858 | ||
ac58c3f0 | 10859 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10860 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10861 | else |
dccbea3b | 10862 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10863 | } else { |
0fb58223 | 10864 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10865 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10866 | |
10867 | if (is_lvds) { | |
10868 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10869 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10870 | |
10871 | if (lvds & LVDS_CLKB_POWER_UP) | |
10872 | clock.p2 = 7; | |
10873 | else | |
10874 | clock.p2 = 14; | |
79e53945 JB |
10875 | } else { |
10876 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10877 | clock.p1 = 2; | |
10878 | else { | |
10879 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10880 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10881 | } | |
10882 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10883 | clock.p2 = 4; | |
10884 | else | |
10885 | clock.p2 = 2; | |
79e53945 | 10886 | } |
da4a1efa | 10887 | |
dccbea3b | 10888 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10889 | } |
10890 | ||
18442d08 VS |
10891 | /* |
10892 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10893 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10894 | * encoder's get_config() function. |
10895 | */ | |
dccbea3b | 10896 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10897 | } |
10898 | ||
6878da05 VS |
10899 | int intel_dotclock_calculate(int link_freq, |
10900 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10901 | { |
f1f644dc JB |
10902 | /* |
10903 | * The calculation for the data clock is: | |
1041a02f | 10904 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10905 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10906 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10907 | * |
10908 | * and the link clock is simpler: | |
1041a02f | 10909 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10910 | */ |
10911 | ||
6878da05 VS |
10912 | if (!m_n->link_n) |
10913 | return 0; | |
f1f644dc | 10914 | |
6878da05 VS |
10915 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10916 | } | |
f1f644dc | 10917 | |
18442d08 | 10918 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10919 | struct intel_crtc_state *pipe_config) |
6878da05 | 10920 | { |
e3b247da | 10921 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10922 | |
18442d08 VS |
10923 | /* read out port_clock from the DPLL */ |
10924 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10925 | |
f1f644dc | 10926 | /* |
e3b247da VS |
10927 | * In case there is an active pipe without active ports, |
10928 | * we may need some idea for the dotclock anyway. | |
10929 | * Calculate one based on the FDI configuration. | |
79e53945 | 10930 | */ |
2d112de7 | 10931 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10932 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10933 | &pipe_config->fdi_m_n); |
79e53945 JB |
10934 | } |
10935 | ||
10936 | /** Returns the currently programmed mode of the given pipe. */ | |
10937 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10938 | struct drm_crtc *crtc) | |
10939 | { | |
fac5e23e | 10940 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 10941 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10942 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10943 | struct drm_display_mode *mode; |
3f36b937 | 10944 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10945 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10946 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10947 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10948 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10949 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10950 | |
10951 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10952 | if (!mode) | |
10953 | return NULL; | |
10954 | ||
3f36b937 TU |
10955 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10956 | if (!pipe_config) { | |
10957 | kfree(mode); | |
10958 | return NULL; | |
10959 | } | |
10960 | ||
f1f644dc JB |
10961 | /* |
10962 | * Construct a pipe_config sufficient for getting the clock info | |
10963 | * back out of crtc_clock_get. | |
10964 | * | |
10965 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10966 | * to use a real value here instead. | |
10967 | */ | |
3f36b937 TU |
10968 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10969 | pipe_config->pixel_multiplier = 1; | |
10970 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10971 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10972 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10973 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10974 | ||
10975 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10976 | mode->hdisplay = (htot & 0xffff) + 1; |
10977 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10978 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10979 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10980 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10981 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10982 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10983 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10984 | ||
10985 | drm_mode_set_name(mode); | |
79e53945 | 10986 | |
3f36b937 TU |
10987 | kfree(pipe_config); |
10988 | ||
79e53945 JB |
10989 | return mode; |
10990 | } | |
10991 | ||
10992 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
10993 | { | |
10994 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 10995 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 10996 | struct intel_flip_work *work; |
67e77c5a | 10997 | |
5e2d7afc | 10998 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
10999 | work = intel_crtc->flip_work; |
11000 | intel_crtc->flip_work = NULL; | |
11001 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 11002 | |
5a21b665 | 11003 | if (work) { |
51cbaf01 ML |
11004 | cancel_work_sync(&work->mmio_work); |
11005 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 11006 | kfree(work); |
67e77c5a | 11007 | } |
79e53945 JB |
11008 | |
11009 | drm_crtc_cleanup(crtc); | |
67e77c5a | 11010 | |
79e53945 JB |
11011 | kfree(intel_crtc); |
11012 | } | |
11013 | ||
6b95a207 KH |
11014 | static void intel_unpin_work_fn(struct work_struct *__work) |
11015 | { | |
51cbaf01 ML |
11016 | struct intel_flip_work *work = |
11017 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
11018 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
11019 | struct drm_device *dev = crtc->base.dev; | |
11020 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 11021 | |
5a21b665 DV |
11022 | if (is_mmio_work(work)) |
11023 | flush_work(&work->mmio_work); | |
03f476e1 | 11024 | |
5a21b665 DV |
11025 | mutex_lock(&dev->struct_mutex); |
11026 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
f8c417cd | 11027 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 11028 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 11029 | |
e8a261ea CW |
11030 | i915_gem_request_put(work->flip_queued_req); |
11031 | ||
5748b6a1 CW |
11032 | intel_frontbuffer_flip_complete(to_i915(dev), |
11033 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
11034 | intel_fbc_post_update(crtc); |
11035 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 11036 | |
5a21b665 DV |
11037 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11038 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 11039 | |
5a21b665 DV |
11040 | kfree(work); |
11041 | } | |
d9e86c0e | 11042 | |
5a21b665 DV |
11043 | /* Is 'a' after or equal to 'b'? */ |
11044 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11045 | { | |
11046 | return !((a - b) & 0x80000000); | |
11047 | } | |
143f73b3 | 11048 | |
5a21b665 DV |
11049 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
11050 | struct intel_flip_work *work) | |
11051 | { | |
11052 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11053 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 11054 | unsigned reset_counter; |
143f73b3 | 11055 | |
5a21b665 DV |
11056 | reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
11057 | if (crtc->reset_counter != reset_counter) | |
11058 | return true; | |
143f73b3 | 11059 | |
5a21b665 DV |
11060 | /* |
11061 | * The relevant registers doen't exist on pre-ctg. | |
11062 | * As the flip done interrupt doesn't trigger for mmio | |
11063 | * flips on gmch platforms, a flip count check isn't | |
11064 | * really needed there. But since ctg has the registers, | |
11065 | * include it in the check anyway. | |
11066 | */ | |
11067 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11068 | return true; | |
b4a98e57 | 11069 | |
5a21b665 DV |
11070 | /* |
11071 | * BDW signals flip done immediately if the plane | |
11072 | * is disabled, even if the plane enable is already | |
11073 | * armed to occur at the next vblank :( | |
11074 | */ | |
f99d7069 | 11075 | |
5a21b665 DV |
11076 | /* |
11077 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11078 | * used the same base address. In that case the mmio flip might | |
11079 | * have completed, but the CS hasn't even executed the flip yet. | |
11080 | * | |
11081 | * A flip count check isn't enough as the CS might have updated | |
11082 | * the base address just after start of vblank, but before we | |
11083 | * managed to process the interrupt. This means we'd complete the | |
11084 | * CS flip too soon. | |
11085 | * | |
11086 | * Combining both checks should get us a good enough result. It may | |
11087 | * still happen that the CS flip has been executed, but has not | |
11088 | * yet actually completed. But in case the base address is the same | |
11089 | * anyway, we don't really care. | |
11090 | */ | |
11091 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11092 | crtc->flip_work->gtt_offset && | |
11093 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11094 | crtc->flip_work->flip_count); | |
11095 | } | |
b4a98e57 | 11096 | |
5a21b665 DV |
11097 | static bool |
11098 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11099 | struct intel_flip_work *work) | |
11100 | { | |
11101 | /* | |
11102 | * MMIO work completes when vblank is different from | |
11103 | * flip_queued_vblank. | |
11104 | * | |
11105 | * Reset counter value doesn't matter, this is handled by | |
11106 | * i915_wait_request finishing early, so no need to handle | |
11107 | * reset here. | |
11108 | */ | |
11109 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11110 | } |
11111 | ||
51cbaf01 ML |
11112 | |
11113 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11114 | struct intel_flip_work *work) | |
11115 | { | |
11116 | if (!atomic_read(&work->pending)) | |
11117 | return false; | |
11118 | ||
11119 | smp_rmb(); | |
11120 | ||
5a21b665 DV |
11121 | if (is_mmio_work(work)) |
11122 | return __pageflip_finished_mmio(crtc, work); | |
11123 | else | |
11124 | return __pageflip_finished_cs(crtc, work); | |
11125 | } | |
11126 | ||
11127 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11128 | { | |
91c8a326 | 11129 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11130 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11131 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11132 | struct intel_flip_work *work; | |
11133 | unsigned long flags; | |
11134 | ||
11135 | /* Ignore early vblank irqs */ | |
11136 | if (!crtc) | |
11137 | return; | |
11138 | ||
51cbaf01 | 11139 | /* |
5a21b665 DV |
11140 | * This is called both by irq handlers and the reset code (to complete |
11141 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11142 | */ |
5a21b665 DV |
11143 | spin_lock_irqsave(&dev->event_lock, flags); |
11144 | work = intel_crtc->flip_work; | |
11145 | ||
11146 | if (work != NULL && | |
11147 | !is_mmio_work(work) && | |
11148 | pageflip_finished(intel_crtc, work)) | |
11149 | page_flip_completed(intel_crtc); | |
11150 | ||
11151 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11152 | } |
11153 | ||
51cbaf01 | 11154 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11155 | { |
91c8a326 | 11156 | struct drm_device *dev = &dev_priv->drm; |
5251f04e ML |
11157 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
51cbaf01 | 11159 | struct intel_flip_work *work; |
6b95a207 KH |
11160 | unsigned long flags; |
11161 | ||
5251f04e ML |
11162 | /* Ignore early vblank irqs */ |
11163 | if (!crtc) | |
11164 | return; | |
f326038a DV |
11165 | |
11166 | /* | |
11167 | * This is called both by irq handlers and the reset code (to complete | |
11168 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11169 | */ |
6b95a207 | 11170 | spin_lock_irqsave(&dev->event_lock, flags); |
5a21b665 | 11171 | work = intel_crtc->flip_work; |
5251f04e | 11172 | |
5a21b665 DV |
11173 | if (work != NULL && |
11174 | is_mmio_work(work) && | |
11175 | pageflip_finished(intel_crtc, work)) | |
11176 | page_flip_completed(intel_crtc); | |
5251f04e | 11177 | |
6b95a207 KH |
11178 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11179 | } | |
11180 | ||
5a21b665 DV |
11181 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11182 | struct intel_flip_work *work) | |
84c33a64 | 11183 | { |
5a21b665 | 11184 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11185 | |
5a21b665 DV |
11186 | /* Ensure that the work item is consistent when activating it ... */ |
11187 | smp_mb__before_atomic(); | |
11188 | atomic_set(&work->pending, 1); | |
11189 | } | |
a6747b73 | 11190 | |
5a21b665 DV |
11191 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11192 | struct drm_crtc *crtc, | |
11193 | struct drm_framebuffer *fb, | |
11194 | struct drm_i915_gem_object *obj, | |
11195 | struct drm_i915_gem_request *req, | |
11196 | uint32_t flags) | |
11197 | { | |
7e37f889 | 11198 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11200 | u32 flip_mask; | |
11201 | int ret; | |
143f73b3 | 11202 | |
5a21b665 DV |
11203 | ret = intel_ring_begin(req, 6); |
11204 | if (ret) | |
11205 | return ret; | |
143f73b3 | 11206 | |
5a21b665 DV |
11207 | /* Can't queue multiple flips, so wait for the previous |
11208 | * one to finish before executing the next. | |
11209 | */ | |
11210 | if (intel_crtc->plane) | |
11211 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11212 | else | |
11213 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11214 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11215 | intel_ring_emit(ring, MI_NOOP); | |
11216 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
5a21b665 | 11217 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11218 | intel_ring_emit(ring, fb->pitches[0]); |
11219 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11220 | intel_ring_emit(ring, 0); /* aux display base address, unused */ | |
143f73b3 | 11221 | |
5a21b665 DV |
11222 | return 0; |
11223 | } | |
84c33a64 | 11224 | |
5a21b665 DV |
11225 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11226 | struct drm_crtc *crtc, | |
11227 | struct drm_framebuffer *fb, | |
11228 | struct drm_i915_gem_object *obj, | |
11229 | struct drm_i915_gem_request *req, | |
11230 | uint32_t flags) | |
11231 | { | |
7e37f889 | 11232 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11234 | u32 flip_mask; | |
11235 | int ret; | |
d55dbd06 | 11236 | |
5a21b665 DV |
11237 | ret = intel_ring_begin(req, 6); |
11238 | if (ret) | |
11239 | return ret; | |
d55dbd06 | 11240 | |
5a21b665 DV |
11241 | if (intel_crtc->plane) |
11242 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11243 | else | |
11244 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11245 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11246 | intel_ring_emit(ring, MI_NOOP); | |
11247 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
5a21b665 | 11248 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11249 | intel_ring_emit(ring, fb->pitches[0]); |
11250 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11251 | intel_ring_emit(ring, MI_NOOP); | |
fd8e058a | 11252 | |
5a21b665 DV |
11253 | return 0; |
11254 | } | |
84c33a64 | 11255 | |
5a21b665 DV |
11256 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11257 | struct drm_crtc *crtc, | |
11258 | struct drm_framebuffer *fb, | |
11259 | struct drm_i915_gem_object *obj, | |
11260 | struct drm_i915_gem_request *req, | |
11261 | uint32_t flags) | |
11262 | { | |
7e37f889 | 11263 | struct intel_ring *ring = req->ring; |
fac5e23e | 11264 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11265 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11266 | uint32_t pf, pipesrc; | |
11267 | int ret; | |
143f73b3 | 11268 | |
5a21b665 DV |
11269 | ret = intel_ring_begin(req, 4); |
11270 | if (ret) | |
11271 | return ret; | |
143f73b3 | 11272 | |
5a21b665 DV |
11273 | /* i965+ uses the linear or tiled offsets from the |
11274 | * Display Registers (which do not change across a page-flip) | |
11275 | * so we need only reprogram the base address. | |
11276 | */ | |
b5321f30 | 11277 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11278 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11279 | intel_ring_emit(ring, fb->pitches[0]); |
11280 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset | | |
3e510a8e | 11281 | i915_gem_object_get_tiling(obj)); |
5a21b665 DV |
11282 | |
11283 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11284 | * untested on non-native modes, so ignore it for now. | |
11285 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11286 | */ | |
11287 | pf = 0; | |
11288 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11289 | intel_ring_emit(ring, pf | pipesrc); |
143f73b3 | 11290 | |
5a21b665 | 11291 | return 0; |
8c9f3aaf JB |
11292 | } |
11293 | ||
5a21b665 DV |
11294 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11295 | struct drm_crtc *crtc, | |
11296 | struct drm_framebuffer *fb, | |
11297 | struct drm_i915_gem_object *obj, | |
11298 | struct drm_i915_gem_request *req, | |
11299 | uint32_t flags) | |
da20eabd | 11300 | { |
7e37f889 | 11301 | struct intel_ring *ring = req->ring; |
fac5e23e | 11302 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11303 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11304 | uint32_t pf, pipesrc; | |
11305 | int ret; | |
d21fbe87 | 11306 | |
5a21b665 DV |
11307 | ret = intel_ring_begin(req, 4); |
11308 | if (ret) | |
11309 | return ret; | |
92826fcd | 11310 | |
b5321f30 | 11311 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11312 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
3e510a8e | 11313 | intel_ring_emit(ring, fb->pitches[0] | i915_gem_object_get_tiling(obj)); |
b5321f30 | 11314 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
92826fcd | 11315 | |
5a21b665 DV |
11316 | /* Contrary to the suggestions in the documentation, |
11317 | * "Enable Panel Fitter" does not seem to be required when page | |
11318 | * flipping with a non-native mode, and worse causes a normal | |
11319 | * modeset to fail. | |
11320 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11321 | */ | |
11322 | pf = 0; | |
11323 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11324 | intel_ring_emit(ring, pf | pipesrc); |
7809e5ae | 11325 | |
5a21b665 | 11326 | return 0; |
7809e5ae MR |
11327 | } |
11328 | ||
5a21b665 DV |
11329 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11330 | struct drm_crtc *crtc, | |
11331 | struct drm_framebuffer *fb, | |
11332 | struct drm_i915_gem_object *obj, | |
11333 | struct drm_i915_gem_request *req, | |
11334 | uint32_t flags) | |
d21fbe87 | 11335 | { |
7e37f889 | 11336 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11337 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11338 | uint32_t plane_bit = 0; | |
11339 | int len, ret; | |
d21fbe87 | 11340 | |
5a21b665 DV |
11341 | switch (intel_crtc->plane) { |
11342 | case PLANE_A: | |
11343 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11344 | break; | |
11345 | case PLANE_B: | |
11346 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11347 | break; | |
11348 | case PLANE_C: | |
11349 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11350 | break; | |
11351 | default: | |
11352 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11353 | return -ENODEV; | |
11354 | } | |
11355 | ||
11356 | len = 4; | |
b5321f30 | 11357 | if (req->engine->id == RCS) { |
5a21b665 DV |
11358 | len += 6; |
11359 | /* | |
11360 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11361 | * 48bits addresses, and we need a NOOP for the batch size to | |
11362 | * stay even. | |
11363 | */ | |
11364 | if (IS_GEN8(dev)) | |
11365 | len += 2; | |
11366 | } | |
11367 | ||
11368 | /* | |
11369 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11370 | * "The full packet must be contained within the same cache line." | |
11371 | * | |
11372 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11373 | * cacheline, if we ever start emitting more commands before | |
11374 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11375 | * then do the cacheline alignment, and finally emit the | |
11376 | * MI_DISPLAY_FLIP. | |
11377 | */ | |
11378 | ret = intel_ring_cacheline_align(req); | |
11379 | if (ret) | |
11380 | return ret; | |
11381 | ||
11382 | ret = intel_ring_begin(req, len); | |
11383 | if (ret) | |
11384 | return ret; | |
11385 | ||
11386 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11387 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11388 | * more than one flip event at any time (or ensure that one flip message | |
11389 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11390 | * Experimentation says that BCS works despite DERRMR masking all | |
11391 | * flip-done completion events and that unmasking all planes at once | |
11392 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11393 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11394 | */ | |
b5321f30 CW |
11395 | if (req->engine->id == RCS) { |
11396 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11397 | intel_ring_emit_reg(ring, DERRMR); | |
11398 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
5a21b665 DV |
11399 | DERRMR_PIPEB_PRI_FLIP_DONE | |
11400 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
11401 | if (IS_GEN8(dev)) | |
b5321f30 | 11402 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
5a21b665 DV |
11403 | MI_SRM_LRM_GLOBAL_GTT); |
11404 | else | |
b5321f30 | 11405 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
5a21b665 | 11406 | MI_SRM_LRM_GLOBAL_GTT); |
b5321f30 CW |
11407 | intel_ring_emit_reg(ring, DERRMR); |
11408 | intel_ring_emit(ring, req->engine->scratch.gtt_offset + 256); | |
5a21b665 | 11409 | if (IS_GEN8(dev)) { |
b5321f30 CW |
11410 | intel_ring_emit(ring, 0); |
11411 | intel_ring_emit(ring, MI_NOOP); | |
5a21b665 DV |
11412 | } |
11413 | } | |
11414 | ||
b5321f30 | 11415 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
3e510a8e | 11416 | intel_ring_emit(ring, fb->pitches[0] | i915_gem_object_get_tiling(obj)); |
b5321f30 CW |
11417 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
11418 | intel_ring_emit(ring, (MI_NOOP)); | |
5a21b665 DV |
11419 | |
11420 | return 0; | |
11421 | } | |
11422 | ||
11423 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11424 | struct drm_i915_gem_object *obj) | |
11425 | { | |
c37efb99 CW |
11426 | struct reservation_object *resv; |
11427 | ||
5a21b665 DV |
11428 | /* |
11429 | * This is not being used for older platforms, because | |
11430 | * non-availability of flip done interrupt forces us to use | |
11431 | * CS flips. Older platforms derive flip done using some clever | |
11432 | * tricks involving the flip_pending status bits and vblank irqs. | |
11433 | * So using MMIO flips there would disrupt this mechanism. | |
11434 | */ | |
11435 | ||
11436 | if (engine == NULL) | |
11437 | return true; | |
11438 | ||
11439 | if (INTEL_GEN(engine->i915) < 5) | |
11440 | return false; | |
11441 | ||
11442 | if (i915.use_mmio_flip < 0) | |
11443 | return false; | |
11444 | else if (i915.use_mmio_flip > 0) | |
11445 | return true; | |
11446 | else if (i915.enable_execlists) | |
11447 | return true; | |
c37efb99 CW |
11448 | |
11449 | resv = i915_gem_object_get_dmabuf_resv(obj); | |
11450 | if (resv && !reservation_object_test_signaled_rcu(resv, false)) | |
5a21b665 | 11451 | return true; |
c37efb99 | 11452 | |
d72d908b CW |
11453 | return engine != i915_gem_active_get_engine(&obj->last_write, |
11454 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
11455 | } |
11456 | ||
11457 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11458 | unsigned int rotation, | |
11459 | struct intel_flip_work *work) | |
11460 | { | |
11461 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11462 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11463 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
11464 | const enum pipe pipe = intel_crtc->pipe; | |
11465 | u32 ctl, stride, tile_height; | |
11466 | ||
11467 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11468 | ctl &= ~PLANE_CTL_TILED_MASK; | |
11469 | switch (fb->modifier[0]) { | |
11470 | case DRM_FORMAT_MOD_NONE: | |
11471 | break; | |
11472 | case I915_FORMAT_MOD_X_TILED: | |
11473 | ctl |= PLANE_CTL_TILED_X; | |
11474 | break; | |
11475 | case I915_FORMAT_MOD_Y_TILED: | |
11476 | ctl |= PLANE_CTL_TILED_Y; | |
11477 | break; | |
11478 | case I915_FORMAT_MOD_Yf_TILED: | |
11479 | ctl |= PLANE_CTL_TILED_YF; | |
11480 | break; | |
11481 | default: | |
11482 | MISSING_CASE(fb->modifier[0]); | |
11483 | } | |
11484 | ||
11485 | /* | |
11486 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11487 | * linear buffers or in number of tiles for tiled buffers. | |
11488 | */ | |
11489 | if (intel_rotation_90_or_270(rotation)) { | |
11490 | /* stride = Surface height in tiles */ | |
11491 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); | |
11492 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
11493 | } else { | |
11494 | stride = fb->pitches[0] / | |
11495 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
11496 | fb->pixel_format); | |
11497 | } | |
11498 | ||
11499 | /* | |
11500 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11501 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11502 | */ | |
11503 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11504 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11505 | ||
11506 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
11507 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11508 | } | |
11509 | ||
11510 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11511 | struct intel_flip_work *work) | |
11512 | { | |
11513 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11514 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11515 | struct intel_framebuffer *intel_fb = |
11516 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11517 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11518 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); | |
11519 | u32 dspcntr; | |
11520 | ||
11521 | dspcntr = I915_READ(reg); | |
11522 | ||
3e510a8e | 11523 | if (i915_gem_object_is_tiled(obj)) |
5a21b665 DV |
11524 | dspcntr |= DISPPLANE_TILED; |
11525 | else | |
11526 | dspcntr &= ~DISPPLANE_TILED; | |
11527 | ||
11528 | I915_WRITE(reg, dspcntr); | |
11529 | ||
11530 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
11531 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
11532 | } | |
11533 | ||
11534 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
11535 | { | |
11536 | struct intel_flip_work *work = | |
11537 | container_of(w, struct intel_flip_work, mmio_work); | |
11538 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
11539 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
11540 | struct intel_framebuffer *intel_fb = | |
11541 | to_intel_framebuffer(crtc->base.primary->fb); | |
11542 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
c37efb99 | 11543 | struct reservation_object *resv; |
5a21b665 DV |
11544 | |
11545 | if (work->flip_queued_req) | |
776f3236 CW |
11546 | WARN_ON(i915_wait_request(work->flip_queued_req, |
11547 | false, NULL, | |
11548 | NO_WAITBOOST)); | |
5a21b665 DV |
11549 | |
11550 | /* For framebuffer backed by dmabuf, wait for fence */ | |
c37efb99 CW |
11551 | resv = i915_gem_object_get_dmabuf_resv(obj); |
11552 | if (resv) | |
11553 | WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false, | |
5a21b665 DV |
11554 | MAX_SCHEDULE_TIMEOUT) < 0); |
11555 | ||
11556 | intel_pipe_update_start(crtc); | |
11557 | ||
11558 | if (INTEL_GEN(dev_priv) >= 9) | |
11559 | skl_do_mmio_flip(crtc, work->rotation, work); | |
11560 | else | |
11561 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11562 | ilk_do_mmio_flip(crtc, work); | |
11563 | ||
11564 | intel_pipe_update_end(crtc, work); | |
11565 | } | |
11566 | ||
11567 | static int intel_default_queue_flip(struct drm_device *dev, | |
11568 | struct drm_crtc *crtc, | |
11569 | struct drm_framebuffer *fb, | |
11570 | struct drm_i915_gem_object *obj, | |
11571 | struct drm_i915_gem_request *req, | |
11572 | uint32_t flags) | |
11573 | { | |
11574 | return -ENODEV; | |
11575 | } | |
11576 | ||
11577 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
11578 | struct intel_crtc *intel_crtc, | |
11579 | struct intel_flip_work *work) | |
11580 | { | |
11581 | u32 addr, vblank; | |
11582 | ||
11583 | if (!atomic_read(&work->pending)) | |
11584 | return false; | |
11585 | ||
11586 | smp_rmb(); | |
11587 | ||
11588 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
11589 | if (work->flip_ready_vblank == 0) { | |
11590 | if (work->flip_queued_req && | |
f69a02c9 | 11591 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
11592 | return false; |
11593 | ||
11594 | work->flip_ready_vblank = vblank; | |
11595 | } | |
11596 | ||
11597 | if (vblank - work->flip_ready_vblank < 3) | |
11598 | return false; | |
11599 | ||
11600 | /* Potential stall - if we see that the flip has happened, | |
11601 | * assume a missed interrupt. */ | |
11602 | if (INTEL_GEN(dev_priv) >= 4) | |
11603 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11604 | else | |
11605 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11606 | ||
11607 | /* There is a potential issue here with a false positive after a flip | |
11608 | * to the same address. We could address this by checking for a | |
11609 | * non-incrementing frame counter. | |
11610 | */ | |
11611 | return addr == work->gtt_offset; | |
11612 | } | |
11613 | ||
11614 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
11615 | { | |
91c8a326 | 11616 | struct drm_device *dev = &dev_priv->drm; |
5a21b665 DV |
11617 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11618 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11619 | struct intel_flip_work *work; | |
11620 | ||
11621 | WARN_ON(!in_interrupt()); | |
11622 | ||
11623 | if (crtc == NULL) | |
11624 | return; | |
11625 | ||
11626 | spin_lock(&dev->event_lock); | |
11627 | work = intel_crtc->flip_work; | |
11628 | ||
11629 | if (work != NULL && !is_mmio_work(work) && | |
11630 | __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) { | |
11631 | WARN_ONCE(1, | |
11632 | "Kicking stuck page flip: queued at %d, now %d\n", | |
11633 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc)); | |
11634 | page_flip_completed(intel_crtc); | |
11635 | work = NULL; | |
11636 | } | |
11637 | ||
11638 | if (work != NULL && !is_mmio_work(work) && | |
11639 | intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1) | |
11640 | intel_queue_rps_boost_for_request(work->flip_queued_req); | |
11641 | spin_unlock(&dev->event_lock); | |
11642 | } | |
11643 | ||
11644 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
11645 | struct drm_framebuffer *fb, | |
11646 | struct drm_pending_vblank_event *event, | |
11647 | uint32_t page_flip_flags) | |
11648 | { | |
11649 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 11650 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11651 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
11652 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11653 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11654 | struct drm_plane *primary = crtc->primary; | |
11655 | enum pipe pipe = intel_crtc->pipe; | |
11656 | struct intel_flip_work *work; | |
11657 | struct intel_engine_cs *engine; | |
11658 | bool mmio_flip; | |
8e637178 | 11659 | struct drm_i915_gem_request *request; |
5a21b665 DV |
11660 | int ret; |
11661 | ||
11662 | /* | |
11663 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11664 | * check to be safe. In the future we may enable pageflipping from | |
11665 | * a disabled primary plane. | |
11666 | */ | |
11667 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11668 | return -EBUSY; | |
11669 | ||
11670 | /* Can't change pixel format via MI display flips. */ | |
11671 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
11672 | return -EINVAL; | |
11673 | ||
11674 | /* | |
11675 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11676 | * Note that pitch changes could also affect these register. | |
11677 | */ | |
11678 | if (INTEL_INFO(dev)->gen > 3 && | |
11679 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || | |
11680 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
11681 | return -EINVAL; | |
11682 | ||
11683 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
11684 | goto out_hang; | |
11685 | ||
11686 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
11687 | if (work == NULL) | |
11688 | return -ENOMEM; | |
11689 | ||
11690 | work->event = event; | |
11691 | work->crtc = crtc; | |
11692 | work->old_fb = old_fb; | |
11693 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
11694 | ||
11695 | ret = drm_crtc_vblank_get(crtc); | |
11696 | if (ret) | |
11697 | goto free_work; | |
11698 | ||
11699 | /* We borrow the event spin lock for protecting flip_work */ | |
11700 | spin_lock_irq(&dev->event_lock); | |
11701 | if (intel_crtc->flip_work) { | |
11702 | /* Before declaring the flip queue wedged, check if | |
11703 | * the hardware completed the operation behind our backs. | |
11704 | */ | |
11705 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
11706 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11707 | page_flip_completed(intel_crtc); | |
11708 | } else { | |
11709 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
11710 | spin_unlock_irq(&dev->event_lock); | |
11711 | ||
11712 | drm_crtc_vblank_put(crtc); | |
11713 | kfree(work); | |
11714 | return -EBUSY; | |
11715 | } | |
11716 | } | |
11717 | intel_crtc->flip_work = work; | |
11718 | spin_unlock_irq(&dev->event_lock); | |
11719 | ||
11720 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
11721 | flush_workqueue(dev_priv->wq); | |
11722 | ||
11723 | /* Reference the objects for the scheduled work. */ | |
11724 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
11725 | |
11726 | crtc->primary->fb = fb; | |
11727 | update_state_fb(crtc->primary); | |
faf68d92 ML |
11728 | |
11729 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
11730 | to_intel_plane_state(primary->state)); | |
5a21b665 | 11731 | |
25dc556a | 11732 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
11733 | |
11734 | ret = i915_mutex_lock_interruptible(dev); | |
11735 | if (ret) | |
11736 | goto cleanup; | |
11737 | ||
11738 | intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); | |
11739 | if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) { | |
11740 | ret = -EIO; | |
11741 | goto cleanup; | |
11742 | } | |
11743 | ||
11744 | atomic_inc(&intel_crtc->unpin_work_count); | |
11745 | ||
11746 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
11747 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; | |
11748 | ||
11749 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
11750 | engine = &dev_priv->engine[BCS]; | |
3e510a8e CW |
11751 | if (i915_gem_object_get_tiling(obj) != |
11752 | i915_gem_object_get_tiling(intel_fb_obj(work->old_fb))) | |
5a21b665 DV |
11753 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11754 | engine = NULL; | |
11755 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { | |
11756 | engine = &dev_priv->engine[BCS]; | |
11757 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
d72d908b CW |
11758 | engine = i915_gem_active_get_engine(&obj->last_write, |
11759 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
11760 | if (engine == NULL || engine->id != RCS) |
11761 | engine = &dev_priv->engine[BCS]; | |
11762 | } else { | |
11763 | engine = &dev_priv->engine[RCS]; | |
11764 | } | |
11765 | ||
11766 | mmio_flip = use_mmio_flip(engine, obj); | |
11767 | ||
5a21b665 DV |
11768 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
11769 | if (ret) | |
11770 | goto cleanup_pending; | |
11771 | ||
11772 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), | |
11773 | obj, 0); | |
11774 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
11775 | work->rotation = crtc->primary->state->rotation; | |
11776 | ||
11777 | if (mmio_flip) { | |
11778 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
11779 | ||
d72d908b CW |
11780 | work->flip_queued_req = i915_gem_active_get(&obj->last_write, |
11781 | &obj->base.dev->struct_mutex); | |
5a21b665 DV |
11782 | schedule_work(&work->mmio_work); |
11783 | } else { | |
8e637178 CW |
11784 | request = i915_gem_request_alloc(engine, engine->last_context); |
11785 | if (IS_ERR(request)) { | |
11786 | ret = PTR_ERR(request); | |
11787 | goto cleanup_unpin; | |
11788 | } | |
11789 | ||
11790 | ret = i915_gem_object_sync(obj, request); | |
11791 | if (ret) | |
11792 | goto cleanup_request; | |
11793 | ||
5a21b665 DV |
11794 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
11795 | page_flip_flags); | |
11796 | if (ret) | |
8e637178 | 11797 | goto cleanup_request; |
5a21b665 DV |
11798 | |
11799 | intel_mark_page_flip_active(intel_crtc, work); | |
11800 | ||
8e637178 | 11801 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
11802 | i915_add_request_no_flush(request); |
11803 | } | |
11804 | ||
11805 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, | |
11806 | to_intel_plane(primary)->frontbuffer_bit); | |
11807 | mutex_unlock(&dev->struct_mutex); | |
11808 | ||
5748b6a1 | 11809 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
11810 | to_intel_plane(primary)->frontbuffer_bit); |
11811 | ||
11812 | trace_i915_flip_request(intel_crtc->plane, obj); | |
11813 | ||
11814 | return 0; | |
11815 | ||
8e637178 CW |
11816 | cleanup_request: |
11817 | i915_add_request_no_flush(request); | |
5a21b665 DV |
11818 | cleanup_unpin: |
11819 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
11820 | cleanup_pending: | |
5a21b665 DV |
11821 | atomic_dec(&intel_crtc->unpin_work_count); |
11822 | mutex_unlock(&dev->struct_mutex); | |
11823 | cleanup: | |
11824 | crtc->primary->fb = old_fb; | |
11825 | update_state_fb(crtc->primary); | |
11826 | ||
34911fd3 | 11827 | i915_gem_object_put_unlocked(obj); |
5a21b665 DV |
11828 | drm_framebuffer_unreference(work->old_fb); |
11829 | ||
11830 | spin_lock_irq(&dev->event_lock); | |
11831 | intel_crtc->flip_work = NULL; | |
11832 | spin_unlock_irq(&dev->event_lock); | |
11833 | ||
11834 | drm_crtc_vblank_put(crtc); | |
11835 | free_work: | |
11836 | kfree(work); | |
11837 | ||
11838 | if (ret == -EIO) { | |
11839 | struct drm_atomic_state *state; | |
11840 | struct drm_plane_state *plane_state; | |
11841 | ||
11842 | out_hang: | |
11843 | state = drm_atomic_state_alloc(dev); | |
11844 | if (!state) | |
11845 | return -ENOMEM; | |
11846 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11847 | ||
11848 | retry: | |
11849 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11850 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11851 | if (!ret) { | |
11852 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11853 | ||
11854 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11855 | if (!ret) | |
11856 | ret = drm_atomic_commit(state); | |
11857 | } | |
11858 | ||
11859 | if (ret == -EDEADLK) { | |
11860 | drm_modeset_backoff(state->acquire_ctx); | |
11861 | drm_atomic_state_clear(state); | |
11862 | goto retry; | |
11863 | } | |
11864 | ||
11865 | if (ret) | |
11866 | drm_atomic_state_free(state); | |
11867 | ||
11868 | if (ret == 0 && event) { | |
11869 | spin_lock_irq(&dev->event_lock); | |
11870 | drm_crtc_send_vblank_event(crtc, event); | |
11871 | spin_unlock_irq(&dev->event_lock); | |
11872 | } | |
11873 | } | |
11874 | return ret; | |
11875 | } | |
11876 | ||
11877 | ||
11878 | /** | |
11879 | * intel_wm_need_update - Check whether watermarks need updating | |
11880 | * @plane: drm plane | |
11881 | * @state: new plane state | |
11882 | * | |
11883 | * Check current plane state versus the new one to determine whether | |
11884 | * watermarks need to be recalculated. | |
11885 | * | |
11886 | * Returns true or false. | |
11887 | */ | |
11888 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11889 | struct drm_plane_state *state) | |
11890 | { | |
11891 | struct intel_plane_state *new = to_intel_plane_state(state); | |
11892 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11893 | ||
11894 | /* Update watermarks on tiling or size changes. */ | |
11895 | if (new->visible != cur->visible) | |
11896 | return true; | |
11897 | ||
11898 | if (!cur->base.fb || !new->base.fb) | |
11899 | return false; | |
11900 | ||
11901 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11902 | cur->base.rotation != new->base.rotation || | |
11903 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || | |
11904 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11905 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11906 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
11907 | return true; | |
11908 | ||
11909 | return false; | |
11910 | } | |
11911 | ||
11912 | static bool needs_scaling(struct intel_plane_state *state) | |
11913 | { | |
11914 | int src_w = drm_rect_width(&state->src) >> 16; | |
11915 | int src_h = drm_rect_height(&state->src) >> 16; | |
11916 | int dst_w = drm_rect_width(&state->dst); | |
11917 | int dst_h = drm_rect_height(&state->dst); | |
11918 | ||
11919 | return (src_w != dst_w || src_h != dst_h); | |
11920 | } | |
d21fbe87 | 11921 | |
da20eabd ML |
11922 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11923 | struct drm_plane_state *plane_state) | |
11924 | { | |
ab1d3a0e | 11925 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11926 | struct drm_crtc *crtc = crtc_state->crtc; |
11927 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11928 | struct drm_plane *plane = plane_state->plane; | |
11929 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11930 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11931 | struct intel_plane_state *old_plane_state = |
11932 | to_intel_plane_state(plane->state); | |
da20eabd ML |
11933 | bool mode_changed = needs_modeset(crtc_state); |
11934 | bool was_crtc_enabled = crtc->state->active; | |
11935 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11936 | bool turn_off, turn_on, visible, was_visible; |
11937 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 11938 | int ret; |
da20eabd | 11939 | |
84114990 | 11940 | if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
11941 | ret = skl_update_scaler_plane( |
11942 | to_intel_crtc_state(crtc_state), | |
11943 | to_intel_plane_state(plane_state)); | |
11944 | if (ret) | |
11945 | return ret; | |
11946 | } | |
11947 | ||
da20eabd ML |
11948 | was_visible = old_plane_state->visible; |
11949 | visible = to_intel_plane_state(plane_state)->visible; | |
11950 | ||
11951 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11952 | was_visible = false; | |
11953 | ||
35c08f43 ML |
11954 | /* |
11955 | * Visibility is calculated as if the crtc was on, but | |
11956 | * after scaler setup everything depends on it being off | |
11957 | * when the crtc isn't active. | |
f818ffea VS |
11958 | * |
11959 | * FIXME this is wrong for watermarks. Watermarks should also | |
11960 | * be computed as if the pipe would be active. Perhaps move | |
11961 | * per-plane wm computation to the .check_plane() hook, and | |
11962 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
11963 | */ |
11964 | if (!is_crtc_enabled) | |
11965 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11966 | |
11967 | if (!was_visible && !visible) | |
11968 | return 0; | |
11969 | ||
e8861675 ML |
11970 | if (fb != old_plane_state->base.fb) |
11971 | pipe_config->fb_changed = true; | |
11972 | ||
da20eabd ML |
11973 | turn_off = was_visible && (!visible || mode_changed); |
11974 | turn_on = visible && (!was_visible || mode_changed); | |
11975 | ||
72660ce0 | 11976 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
11977 | intel_crtc->base.base.id, |
11978 | intel_crtc->base.name, | |
72660ce0 VS |
11979 | plane->base.id, plane->name, |
11980 | fb ? fb->base.id : -1); | |
da20eabd | 11981 | |
72660ce0 VS |
11982 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
11983 | plane->base.id, plane->name, | |
11984 | was_visible, visible, | |
da20eabd ML |
11985 | turn_off, turn_on, mode_changed); |
11986 | ||
caed361d VS |
11987 | if (turn_on) { |
11988 | pipe_config->update_wm_pre = true; | |
11989 | ||
11990 | /* must disable cxsr around plane enable/disable */ | |
11991 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11992 | pipe_config->disable_cxsr = true; | |
11993 | } else if (turn_off) { | |
11994 | pipe_config->update_wm_post = true; | |
92826fcd | 11995 | |
852eb00d | 11996 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11997 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11998 | pipe_config->disable_cxsr = true; |
852eb00d | 11999 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
12000 | /* FIXME bollocks */ |
12001 | pipe_config->update_wm_pre = true; | |
12002 | pipe_config->update_wm_post = true; | |
852eb00d | 12003 | } |
da20eabd | 12004 | |
ed4a6a7c | 12005 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
12006 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
12007 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
12008 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
12009 | ||
8be6ca85 | 12010 | if (visible || was_visible) |
cd202f69 | 12011 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 12012 | |
31ae71fc ML |
12013 | /* |
12014 | * WaCxSRDisabledForSpriteScaling:ivb | |
12015 | * | |
12016 | * cstate->update_wm was already set above, so this flag will | |
12017 | * take effect when we commit and program watermarks. | |
12018 | */ | |
12019 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
12020 | needs_scaling(to_intel_plane_state(plane_state)) && | |
12021 | !needs_scaling(old_plane_state)) | |
12022 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 12023 | |
da20eabd ML |
12024 | return 0; |
12025 | } | |
12026 | ||
6d3a1ce7 ML |
12027 | static bool encoders_cloneable(const struct intel_encoder *a, |
12028 | const struct intel_encoder *b) | |
12029 | { | |
12030 | /* masks could be asymmetric, so check both ways */ | |
12031 | return a == b || (a->cloneable & (1 << b->type) && | |
12032 | b->cloneable & (1 << a->type)); | |
12033 | } | |
12034 | ||
12035 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12036 | struct intel_crtc *crtc, | |
12037 | struct intel_encoder *encoder) | |
12038 | { | |
12039 | struct intel_encoder *source_encoder; | |
12040 | struct drm_connector *connector; | |
12041 | struct drm_connector_state *connector_state; | |
12042 | int i; | |
12043 | ||
12044 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12045 | if (connector_state->crtc != &crtc->base) | |
12046 | continue; | |
12047 | ||
12048 | source_encoder = | |
12049 | to_intel_encoder(connector_state->best_encoder); | |
12050 | if (!encoders_cloneable(encoder, source_encoder)) | |
12051 | return false; | |
12052 | } | |
12053 | ||
12054 | return true; | |
12055 | } | |
12056 | ||
6d3a1ce7 ML |
12057 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
12058 | struct drm_crtc_state *crtc_state) | |
12059 | { | |
cf5a15be | 12060 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12061 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 12062 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12063 | struct intel_crtc_state *pipe_config = |
12064 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12065 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12066 | int ret; |
6d3a1ce7 ML |
12067 | bool mode_changed = needs_modeset(crtc_state); |
12068 | ||
852eb00d | 12069 | if (mode_changed && !crtc_state->active) |
caed361d | 12070 | pipe_config->update_wm_post = true; |
eddfcbcd | 12071 | |
ad421372 ML |
12072 | if (mode_changed && crtc_state->enable && |
12073 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 12074 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
12075 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12076 | pipe_config); | |
12077 | if (ret) | |
12078 | return ret; | |
12079 | } | |
12080 | ||
82cf435b LL |
12081 | if (crtc_state->color_mgmt_changed) { |
12082 | ret = intel_color_check(crtc, crtc_state); | |
12083 | if (ret) | |
12084 | return ret; | |
e7852a4b LL |
12085 | |
12086 | /* | |
12087 | * Changing color management on Intel hardware is | |
12088 | * handled as part of planes update. | |
12089 | */ | |
12090 | crtc_state->planes_changed = true; | |
82cf435b LL |
12091 | } |
12092 | ||
e435d6e5 | 12093 | ret = 0; |
86c8bbbe | 12094 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12095 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12096 | if (ret) { |
12097 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12098 | return ret; | |
12099 | } | |
12100 | } | |
12101 | ||
12102 | if (dev_priv->display.compute_intermediate_wm && | |
12103 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12104 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12105 | return 0; | |
12106 | ||
12107 | /* | |
12108 | * Calculate 'intermediate' watermarks that satisfy both the | |
12109 | * old state and the new state. We can program these | |
12110 | * immediately. | |
12111 | */ | |
12112 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12113 | intel_crtc, | |
12114 | pipe_config); | |
12115 | if (ret) { | |
12116 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12117 | return ret; |
ed4a6a7c | 12118 | } |
e3d5457c VS |
12119 | } else if (dev_priv->display.compute_intermediate_wm) { |
12120 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12121 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12122 | } |
12123 | ||
e435d6e5 ML |
12124 | if (INTEL_INFO(dev)->gen >= 9) { |
12125 | if (mode_changed) | |
12126 | ret = skl_update_scaler_crtc(pipe_config); | |
12127 | ||
12128 | if (!ret) | |
12129 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12130 | pipe_config); | |
12131 | } | |
12132 | ||
12133 | return ret; | |
6d3a1ce7 ML |
12134 | } |
12135 | ||
65b38e0d | 12136 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12137 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12138 | .atomic_begin = intel_begin_crtc_commit, |
12139 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12140 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12141 | }; |
12142 | ||
d29b2f9d ACO |
12143 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12144 | { | |
12145 | struct intel_connector *connector; | |
12146 | ||
12147 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12148 | if (connector->base.state->crtc) |
12149 | drm_connector_unreference(&connector->base); | |
12150 | ||
d29b2f9d ACO |
12151 | if (connector->base.encoder) { |
12152 | connector->base.state->best_encoder = | |
12153 | connector->base.encoder; | |
12154 | connector->base.state->crtc = | |
12155 | connector->base.encoder->crtc; | |
8863dc7f DV |
12156 | |
12157 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12158 | } else { |
12159 | connector->base.state->best_encoder = NULL; | |
12160 | connector->base.state->crtc = NULL; | |
12161 | } | |
12162 | } | |
12163 | } | |
12164 | ||
050f7aeb | 12165 | static void |
eba905b2 | 12166 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12167 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12168 | { |
12169 | int bpp = pipe_config->pipe_bpp; | |
12170 | ||
12171 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12172 | connector->base.base.id, | |
c23cc417 | 12173 | connector->base.name); |
050f7aeb DV |
12174 | |
12175 | /* Don't use an invalid EDID bpc value */ | |
12176 | if (connector->base.display_info.bpc && | |
12177 | connector->base.display_info.bpc * 3 < bpp) { | |
12178 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12179 | bpp, connector->base.display_info.bpc*3); | |
12180 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12181 | } | |
12182 | ||
013dd9e0 JN |
12183 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12184 | if (connector->base.display_info.bpc == 0) { | |
12185 | int type = connector->base.connector_type; | |
12186 | int clamp_bpp = 24; | |
12187 | ||
12188 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12189 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12190 | type == DRM_MODE_CONNECTOR_eDP) | |
12191 | clamp_bpp = 18; | |
12192 | ||
12193 | if (bpp > clamp_bpp) { | |
12194 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12195 | bpp, clamp_bpp); | |
12196 | pipe_config->pipe_bpp = clamp_bpp; | |
12197 | } | |
050f7aeb DV |
12198 | } |
12199 | } | |
12200 | ||
4e53c2e0 | 12201 | static int |
050f7aeb | 12202 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12203 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12204 | { |
050f7aeb | 12205 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12206 | struct drm_atomic_state *state; |
da3ced29 ACO |
12207 | struct drm_connector *connector; |
12208 | struct drm_connector_state *connector_state; | |
1486017f | 12209 | int bpp, i; |
4e53c2e0 | 12210 | |
666a4537 | 12211 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12212 | bpp = 10*3; |
d328c9d7 DV |
12213 | else if (INTEL_INFO(dev)->gen >= 5) |
12214 | bpp = 12*3; | |
12215 | else | |
12216 | bpp = 8*3; | |
12217 | ||
4e53c2e0 | 12218 | |
4e53c2e0 DV |
12219 | pipe_config->pipe_bpp = bpp; |
12220 | ||
1486017f ACO |
12221 | state = pipe_config->base.state; |
12222 | ||
4e53c2e0 | 12223 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12224 | for_each_connector_in_state(state, connector, connector_state, i) { |
12225 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12226 | continue; |
12227 | ||
da3ced29 ACO |
12228 | connected_sink_compute_bpp(to_intel_connector(connector), |
12229 | pipe_config); | |
4e53c2e0 DV |
12230 | } |
12231 | ||
12232 | return bpp; | |
12233 | } | |
12234 | ||
644db711 DV |
12235 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12236 | { | |
12237 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12238 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12239 | mode->crtc_clock, |
644db711 DV |
12240 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12241 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12242 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12243 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12244 | } | |
12245 | ||
c0b03411 | 12246 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12247 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12248 | const char *context) |
12249 | { | |
6a60cd87 CK |
12250 | struct drm_device *dev = crtc->base.dev; |
12251 | struct drm_plane *plane; | |
12252 | struct intel_plane *intel_plane; | |
12253 | struct intel_plane_state *state; | |
12254 | struct drm_framebuffer *fb; | |
12255 | ||
78108b7c VS |
12256 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n", |
12257 | crtc->base.base.id, crtc->base.name, | |
6a60cd87 | 12258 | context, pipe_config, pipe_name(crtc->pipe)); |
c0b03411 | 12259 | |
da205630 | 12260 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12261 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12262 | pipe_config->pipe_bpp, pipe_config->dither); | |
12263 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12264 | pipe_config->has_pch_encoder, | |
12265 | pipe_config->fdi_lanes, | |
12266 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12267 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12268 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12269 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
37a5650b | 12270 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12271 | pipe_config->lane_count, |
eb14cb74 VS |
12272 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12273 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12274 | pipe_config->dp_m_n.tu); | |
b95af8be | 12275 | |
90a6b7b0 | 12276 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
37a5650b | 12277 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12278 | pipe_config->lane_count, |
b95af8be VK |
12279 | pipe_config->dp_m2_n2.gmch_m, |
12280 | pipe_config->dp_m2_n2.gmch_n, | |
12281 | pipe_config->dp_m2_n2.link_m, | |
12282 | pipe_config->dp_m2_n2.link_n, | |
12283 | pipe_config->dp_m2_n2.tu); | |
12284 | ||
55072d19 DV |
12285 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12286 | pipe_config->has_audio, | |
12287 | pipe_config->has_infoframe); | |
12288 | ||
c0b03411 | 12289 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12290 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12291 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12292 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12293 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12294 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12295 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12296 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12297 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12298 | crtc->num_scalers, | |
12299 | pipe_config->scaler_state.scaler_users, | |
12300 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12301 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12302 | pipe_config->gmch_pfit.control, | |
12303 | pipe_config->gmch_pfit.pgm_ratios, | |
12304 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12305 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12306 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12307 | pipe_config->pch_pfit.size, |
12308 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12309 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12310 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12311 | |
415ff0f6 | 12312 | if (IS_BROXTON(dev)) { |
05712c15 | 12313 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12314 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12315 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12316 | pipe_config->ddi_pll_sel, |
12317 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12318 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12319 | pipe_config->dpll_hw_state.pll0, |
12320 | pipe_config->dpll_hw_state.pll1, | |
12321 | pipe_config->dpll_hw_state.pll2, | |
12322 | pipe_config->dpll_hw_state.pll3, | |
12323 | pipe_config->dpll_hw_state.pll6, | |
12324 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12325 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12326 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12327 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12328 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12329 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12330 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12331 | pipe_config->ddi_pll_sel, | |
12332 | pipe_config->dpll_hw_state.ctrl1, | |
12333 | pipe_config->dpll_hw_state.cfgcr1, | |
12334 | pipe_config->dpll_hw_state.cfgcr2); | |
12335 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12336 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12337 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12338 | pipe_config->dpll_hw_state.wrpll, |
12339 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12340 | } else { |
12341 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12342 | "fp0: 0x%x, fp1: 0x%x\n", | |
12343 | pipe_config->dpll_hw_state.dpll, | |
12344 | pipe_config->dpll_hw_state.dpll_md, | |
12345 | pipe_config->dpll_hw_state.fp0, | |
12346 | pipe_config->dpll_hw_state.fp1); | |
12347 | } | |
12348 | ||
6a60cd87 CK |
12349 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12350 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12351 | intel_plane = to_intel_plane(plane); | |
12352 | if (intel_plane->pipe != crtc->pipe) | |
12353 | continue; | |
12354 | ||
12355 | state = to_intel_plane_state(plane->state); | |
12356 | fb = state->base.fb; | |
12357 | if (!fb) { | |
1d577e02 VS |
12358 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12359 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12360 | continue; |
12361 | } | |
12362 | ||
1d577e02 VS |
12363 | DRM_DEBUG_KMS("[PLANE:%d:%s] enabled", |
12364 | plane->base.id, plane->name); | |
12365 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s", | |
12366 | fb->base.id, fb->width, fb->height, | |
12367 | drm_get_format_name(fb->pixel_format)); | |
12368 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
12369 | state->scaler_id, | |
12370 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12371 | drm_rect_width(&state->src) >> 16, | |
12372 | drm_rect_height(&state->src) >> 16, | |
12373 | state->dst.x1, state->dst.y1, | |
12374 | drm_rect_width(&state->dst), | |
12375 | drm_rect_height(&state->dst)); | |
6a60cd87 | 12376 | } |
c0b03411 DV |
12377 | } |
12378 | ||
5448a00d | 12379 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12380 | { |
5448a00d | 12381 | struct drm_device *dev = state->dev; |
da3ced29 | 12382 | struct drm_connector *connector; |
00f0b378 | 12383 | unsigned int used_ports = 0; |
477321e0 | 12384 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
12385 | |
12386 | /* | |
12387 | * Walk the connector list instead of the encoder | |
12388 | * list to detect the problem on ddi platforms | |
12389 | * where there's just one encoder per digital port. | |
12390 | */ | |
0bff4858 VS |
12391 | drm_for_each_connector(connector, dev) { |
12392 | struct drm_connector_state *connector_state; | |
12393 | struct intel_encoder *encoder; | |
12394 | ||
12395 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12396 | if (!connector_state) | |
12397 | connector_state = connector->state; | |
12398 | ||
5448a00d | 12399 | if (!connector_state->best_encoder) |
00f0b378 VS |
12400 | continue; |
12401 | ||
5448a00d ACO |
12402 | encoder = to_intel_encoder(connector_state->best_encoder); |
12403 | ||
12404 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12405 | |
12406 | switch (encoder->type) { | |
12407 | unsigned int port_mask; | |
12408 | case INTEL_OUTPUT_UNKNOWN: | |
12409 | if (WARN_ON(!HAS_DDI(dev))) | |
12410 | break; | |
cca0502b | 12411 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
12412 | case INTEL_OUTPUT_HDMI: |
12413 | case INTEL_OUTPUT_EDP: | |
12414 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12415 | ||
12416 | /* the same port mustn't appear more than once */ | |
12417 | if (used_ports & port_mask) | |
12418 | return false; | |
12419 | ||
12420 | used_ports |= port_mask; | |
477321e0 VS |
12421 | break; |
12422 | case INTEL_OUTPUT_DP_MST: | |
12423 | used_mst_ports |= | |
12424 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
12425 | break; | |
00f0b378 VS |
12426 | default: |
12427 | break; | |
12428 | } | |
12429 | } | |
12430 | ||
477321e0 VS |
12431 | /* can't mix MST and SST/HDMI on the same port */ |
12432 | if (used_ports & used_mst_ports) | |
12433 | return false; | |
12434 | ||
00f0b378 VS |
12435 | return true; |
12436 | } | |
12437 | ||
83a57153 ACO |
12438 | static void |
12439 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12440 | { | |
12441 | struct drm_crtc_state tmp_state; | |
663a3640 | 12442 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12443 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12444 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12445 | uint32_t ddi_pll_sel; |
c4e2d043 | 12446 | bool force_thru; |
83a57153 | 12447 | |
7546a384 ACO |
12448 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12449 | * kzalloc'd. Code that depends on any field being zero should be | |
12450 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12451 | * only fields that are know to not cause problems are preserved. */ | |
12452 | ||
83a57153 | 12453 | tmp_state = crtc_state->base; |
663a3640 | 12454 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12455 | shared_dpll = crtc_state->shared_dpll; |
12456 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12457 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12458 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12459 | |
83a57153 | 12460 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12461 | |
83a57153 | 12462 | crtc_state->base = tmp_state; |
663a3640 | 12463 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12464 | crtc_state->shared_dpll = shared_dpll; |
12465 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12466 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12467 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12468 | } |
12469 | ||
548ee15b | 12470 | static int |
b8cecdf5 | 12471 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12472 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12473 | { |
b359283a | 12474 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12475 | struct intel_encoder *encoder; |
da3ced29 | 12476 | struct drm_connector *connector; |
0b901879 | 12477 | struct drm_connector_state *connector_state; |
d328c9d7 | 12478 | int base_bpp, ret = -EINVAL; |
0b901879 | 12479 | int i; |
e29c22c0 | 12480 | bool retry = true; |
ee7b9f93 | 12481 | |
83a57153 | 12482 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12483 | |
e143a21c DV |
12484 | pipe_config->cpu_transcoder = |
12485 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12486 | |
2960bc9c ID |
12487 | /* |
12488 | * Sanitize sync polarity flags based on requested ones. If neither | |
12489 | * positive or negative polarity is requested, treat this as meaning | |
12490 | * negative polarity. | |
12491 | */ | |
2d112de7 | 12492 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12493 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12494 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12495 | |
2d112de7 | 12496 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12497 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12498 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12499 | |
d328c9d7 DV |
12500 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12501 | pipe_config); | |
12502 | if (base_bpp < 0) | |
4e53c2e0 DV |
12503 | goto fail; |
12504 | ||
e41a56be VS |
12505 | /* |
12506 | * Determine the real pipe dimensions. Note that stereo modes can | |
12507 | * increase the actual pipe size due to the frame doubling and | |
12508 | * insertion of additional space for blanks between the frame. This | |
12509 | * is stored in the crtc timings. We use the requested mode to do this | |
12510 | * computation to clearly distinguish it from the adjusted mode, which | |
12511 | * can be changed by the connectors in the below retry loop. | |
12512 | */ | |
2d112de7 | 12513 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12514 | &pipe_config->pipe_src_w, |
12515 | &pipe_config->pipe_src_h); | |
e41a56be | 12516 | |
253c84c8 VS |
12517 | for_each_connector_in_state(state, connector, connector_state, i) { |
12518 | if (connector_state->crtc != crtc) | |
12519 | continue; | |
12520 | ||
12521 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12522 | ||
e25148d0 VS |
12523 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
12524 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12525 | goto fail; | |
12526 | } | |
12527 | ||
253c84c8 VS |
12528 | /* |
12529 | * Determine output_types before calling the .compute_config() | |
12530 | * hooks so that the hooks can use this information safely. | |
12531 | */ | |
12532 | pipe_config->output_types |= 1 << encoder->type; | |
12533 | } | |
12534 | ||
e29c22c0 | 12535 | encoder_retry: |
ef1b460d | 12536 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12537 | pipe_config->port_clock = 0; |
ef1b460d | 12538 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12539 | |
135c81b8 | 12540 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12541 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12542 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12543 | |
7758a113 DV |
12544 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12545 | * adjust it according to limitations or connector properties, and also | |
12546 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12547 | */ |
da3ced29 | 12548 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12549 | if (connector_state->crtc != crtc) |
7758a113 | 12550 | continue; |
7ae89233 | 12551 | |
0b901879 ACO |
12552 | encoder = to_intel_encoder(connector_state->best_encoder); |
12553 | ||
efea6e8e DV |
12554 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12555 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12556 | goto fail; |
12557 | } | |
ee7b9f93 | 12558 | } |
47f1c6c9 | 12559 | |
ff9a6750 DV |
12560 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12561 | * done afterwards in case the encoder adjusts the mode. */ | |
12562 | if (!pipe_config->port_clock) | |
2d112de7 | 12563 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12564 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12565 | |
a43f6e0f | 12566 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12567 | if (ret < 0) { |
7758a113 DV |
12568 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12569 | goto fail; | |
ee7b9f93 | 12570 | } |
e29c22c0 DV |
12571 | |
12572 | if (ret == RETRY) { | |
12573 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12574 | ret = -EINVAL; | |
12575 | goto fail; | |
12576 | } | |
12577 | ||
12578 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12579 | retry = false; | |
12580 | goto encoder_retry; | |
12581 | } | |
12582 | ||
e8fa4270 DV |
12583 | /* Dithering seems to not pass-through bits correctly when it should, so |
12584 | * only enable it on 6bpc panels. */ | |
12585 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12586 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12587 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12588 | |
7758a113 | 12589 | fail: |
548ee15b | 12590 | return ret; |
ee7b9f93 | 12591 | } |
47f1c6c9 | 12592 | |
ea9d758d | 12593 | static void |
4740b0f2 | 12594 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12595 | { |
0a9ab303 ACO |
12596 | struct drm_crtc *crtc; |
12597 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12598 | int i; |
ea9d758d | 12599 | |
7668851f | 12600 | /* Double check state. */ |
8a75d157 | 12601 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12602 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12603 | |
12604 | /* Update hwmode for vblank functions */ | |
12605 | if (crtc->state->active) | |
12606 | crtc->hwmode = crtc->state->adjusted_mode; | |
12607 | else | |
12608 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12609 | |
12610 | /* | |
12611 | * Update legacy state to satisfy fbc code. This can | |
12612 | * be removed when fbc uses the atomic state. | |
12613 | */ | |
12614 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12615 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12616 | ||
12617 | crtc->primary->fb = plane_state->fb; | |
12618 | crtc->x = plane_state->src_x >> 16; | |
12619 | crtc->y = plane_state->src_y >> 16; | |
12620 | } | |
ea9d758d | 12621 | } |
ea9d758d DV |
12622 | } |
12623 | ||
3bd26263 | 12624 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12625 | { |
3bd26263 | 12626 | int diff; |
f1f644dc JB |
12627 | |
12628 | if (clock1 == clock2) | |
12629 | return true; | |
12630 | ||
12631 | if (!clock1 || !clock2) | |
12632 | return false; | |
12633 | ||
12634 | diff = abs(clock1 - clock2); | |
12635 | ||
12636 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12637 | return true; | |
12638 | ||
12639 | return false; | |
12640 | } | |
12641 | ||
25c5b266 DV |
12642 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12643 | list_for_each_entry((intel_crtc), \ | |
12644 | &(dev)->mode_config.crtc_list, \ | |
12645 | base.head) \ | |
95150bdf | 12646 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12647 | |
cfb23ed6 ML |
12648 | static bool |
12649 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12650 | unsigned int m2, unsigned int n2, | |
12651 | bool exact) | |
12652 | { | |
12653 | if (m == m2 && n == n2) | |
12654 | return true; | |
12655 | ||
12656 | if (exact || !m || !n || !m2 || !n2) | |
12657 | return false; | |
12658 | ||
12659 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12660 | ||
31d10b57 ML |
12661 | if (n > n2) { |
12662 | while (n > n2) { | |
cfb23ed6 ML |
12663 | m2 <<= 1; |
12664 | n2 <<= 1; | |
12665 | } | |
31d10b57 ML |
12666 | } else if (n < n2) { |
12667 | while (n < n2) { | |
cfb23ed6 ML |
12668 | m <<= 1; |
12669 | n <<= 1; | |
12670 | } | |
12671 | } | |
12672 | ||
31d10b57 ML |
12673 | if (n != n2) |
12674 | return false; | |
12675 | ||
12676 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12677 | } |
12678 | ||
12679 | static bool | |
12680 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12681 | struct intel_link_m_n *m2_n2, | |
12682 | bool adjust) | |
12683 | { | |
12684 | if (m_n->tu == m2_n2->tu && | |
12685 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12686 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12687 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12688 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12689 | if (adjust) | |
12690 | *m2_n2 = *m_n; | |
12691 | ||
12692 | return true; | |
12693 | } | |
12694 | ||
12695 | return false; | |
12696 | } | |
12697 | ||
0e8ffe1b | 12698 | static bool |
2fa2fe9a | 12699 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12700 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12701 | struct intel_crtc_state *pipe_config, |
12702 | bool adjust) | |
0e8ffe1b | 12703 | { |
cfb23ed6 ML |
12704 | bool ret = true; |
12705 | ||
12706 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12707 | do { \ | |
12708 | if (!adjust) \ | |
12709 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12710 | else \ | |
12711 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12712 | } while (0) | |
12713 | ||
66e985c0 DV |
12714 | #define PIPE_CONF_CHECK_X(name) \ |
12715 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12716 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12717 | "(expected 0x%08x, found 0x%08x)\n", \ |
12718 | current_config->name, \ | |
12719 | pipe_config->name); \ | |
cfb23ed6 | 12720 | ret = false; \ |
66e985c0 DV |
12721 | } |
12722 | ||
08a24034 DV |
12723 | #define PIPE_CONF_CHECK_I(name) \ |
12724 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12725 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12726 | "(expected %i, found %i)\n", \ |
12727 | current_config->name, \ | |
12728 | pipe_config->name); \ | |
cfb23ed6 ML |
12729 | ret = false; \ |
12730 | } | |
12731 | ||
8106ddbd ACO |
12732 | #define PIPE_CONF_CHECK_P(name) \ |
12733 | if (current_config->name != pipe_config->name) { \ | |
12734 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12735 | "(expected %p, found %p)\n", \ | |
12736 | current_config->name, \ | |
12737 | pipe_config->name); \ | |
12738 | ret = false; \ | |
12739 | } | |
12740 | ||
cfb23ed6 ML |
12741 | #define PIPE_CONF_CHECK_M_N(name) \ |
12742 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12743 | &pipe_config->name,\ | |
12744 | adjust)) { \ | |
12745 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12746 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12747 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12748 | current_config->name.tu, \ | |
12749 | current_config->name.gmch_m, \ | |
12750 | current_config->name.gmch_n, \ | |
12751 | current_config->name.link_m, \ | |
12752 | current_config->name.link_n, \ | |
12753 | pipe_config->name.tu, \ | |
12754 | pipe_config->name.gmch_m, \ | |
12755 | pipe_config->name.gmch_n, \ | |
12756 | pipe_config->name.link_m, \ | |
12757 | pipe_config->name.link_n); \ | |
12758 | ret = false; \ | |
12759 | } | |
12760 | ||
55c561a7 DV |
12761 | /* This is required for BDW+ where there is only one set of registers for |
12762 | * switching between high and low RR. | |
12763 | * This macro can be used whenever a comparison has to be made between one | |
12764 | * hw state and multiple sw state variables. | |
12765 | */ | |
cfb23ed6 ML |
12766 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
12767 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12768 | &pipe_config->name, adjust) && \ | |
12769 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12770 | &pipe_config->name, adjust)) { \ | |
12771 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12772 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12773 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12774 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12775 | current_config->name.tu, \ | |
12776 | current_config->name.gmch_m, \ | |
12777 | current_config->name.gmch_n, \ | |
12778 | current_config->name.link_m, \ | |
12779 | current_config->name.link_n, \ | |
12780 | current_config->alt_name.tu, \ | |
12781 | current_config->alt_name.gmch_m, \ | |
12782 | current_config->alt_name.gmch_n, \ | |
12783 | current_config->alt_name.link_m, \ | |
12784 | current_config->alt_name.link_n, \ | |
12785 | pipe_config->name.tu, \ | |
12786 | pipe_config->name.gmch_m, \ | |
12787 | pipe_config->name.gmch_n, \ | |
12788 | pipe_config->name.link_m, \ | |
12789 | pipe_config->name.link_n); \ | |
12790 | ret = false; \ | |
88adfff1 DV |
12791 | } |
12792 | ||
1bd1bd80 DV |
12793 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12794 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12795 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12796 | "(expected %i, found %i)\n", \ |
12797 | current_config->name & (mask), \ | |
12798 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12799 | ret = false; \ |
1bd1bd80 DV |
12800 | } |
12801 | ||
5e550656 VS |
12802 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12803 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12804 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12805 | "(expected %i, found %i)\n", \ |
12806 | current_config->name, \ | |
12807 | pipe_config->name); \ | |
cfb23ed6 | 12808 | ret = false; \ |
5e550656 VS |
12809 | } |
12810 | ||
bb760063 DV |
12811 | #define PIPE_CONF_QUIRK(quirk) \ |
12812 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12813 | ||
eccb140b DV |
12814 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12815 | ||
08a24034 DV |
12816 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12817 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12818 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12819 | |
90a6b7b0 | 12820 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 12821 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be VK |
12822 | |
12823 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12824 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12825 | ||
cfb23ed6 ML |
12826 | if (current_config->has_drrs) |
12827 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12828 | } else | |
12829 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12830 | |
253c84c8 | 12831 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 12832 | |
2d112de7 ACO |
12833 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12834 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12835 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12836 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12837 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12838 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12839 | |
2d112de7 ACO |
12840 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12841 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12842 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12843 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12844 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12845 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12846 | |
c93f54cf | 12847 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12848 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12849 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12850 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12851 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12852 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12853 | |
9ed109a7 DV |
12854 | PIPE_CONF_CHECK_I(has_audio); |
12855 | ||
2d112de7 | 12856 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12857 | DRM_MODE_FLAG_INTERLACE); |
12858 | ||
bb760063 | 12859 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12860 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12861 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12862 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12863 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12864 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12865 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12866 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12867 | DRM_MODE_FLAG_NVSYNC); |
12868 | } | |
045ac3b5 | 12869 | |
333b8ca8 | 12870 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12871 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12872 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 12873 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 12874 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12875 | |
bfd16b2a ML |
12876 | if (!adjust) { |
12877 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12878 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12879 | ||
12880 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12881 | if (current_config->pch_pfit.enabled) { | |
12882 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12883 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12884 | } | |
2fa2fe9a | 12885 | |
7aefe2b5 ML |
12886 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12887 | } | |
a1b2278e | 12888 | |
e59150dc JB |
12889 | /* BDW+ don't expose a synchronous way to read the state */ |
12890 | if (IS_HASWELL(dev)) | |
12891 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12892 | |
282740f7 VS |
12893 | PIPE_CONF_CHECK_I(double_wide); |
12894 | ||
26804afd DV |
12895 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12896 | ||
8106ddbd | 12897 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 12898 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12899 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12900 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12901 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12902 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12903 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12904 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12905 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12906 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12907 | |
47eacbab VS |
12908 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
12909 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
12910 | ||
42571aef VS |
12911 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12912 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12913 | ||
2d112de7 | 12914 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12915 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12916 | |
66e985c0 | 12917 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12918 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 12919 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 12920 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12921 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12922 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12923 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12924 | |
cfb23ed6 | 12925 | return ret; |
0e8ffe1b DV |
12926 | } |
12927 | ||
e3b247da VS |
12928 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12929 | const struct intel_crtc_state *pipe_config) | |
12930 | { | |
12931 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12932 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12933 | &pipe_config->fdi_m_n); |
12934 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12935 | ||
12936 | /* | |
12937 | * FDI already provided one idea for the dotclock. | |
12938 | * Yell if the encoder disagrees. | |
12939 | */ | |
12940 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12941 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12942 | fdi_dotclock, dotclock); | |
12943 | } | |
12944 | } | |
12945 | ||
c0ead703 ML |
12946 | static void verify_wm_state(struct drm_crtc *crtc, |
12947 | struct drm_crtc_state *new_state) | |
08db6652 | 12948 | { |
e7c84544 | 12949 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12950 | struct drm_i915_private *dev_priv = to_i915(dev); |
08db6652 | 12951 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
e7c84544 ML |
12952 | struct skl_ddb_entry *hw_entry, *sw_entry; |
12953 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12954 | const enum pipe pipe = intel_crtc->pipe; | |
08db6652 DL |
12955 | int plane; |
12956 | ||
e7c84544 | 12957 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
12958 | return; |
12959 | ||
12960 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12961 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12962 | ||
e7c84544 ML |
12963 | /* planes */ |
12964 | for_each_plane(dev_priv, pipe, plane) { | |
12965 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
12966 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
08db6652 | 12967 | |
e7c84544 | 12968 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
08db6652 DL |
12969 | continue; |
12970 | ||
e7c84544 ML |
12971 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
12972 | "(expected (%u,%u), found (%u,%u))\n", | |
12973 | pipe_name(pipe), plane + 1, | |
12974 | sw_entry->start, sw_entry->end, | |
12975 | hw_entry->start, hw_entry->end); | |
12976 | } | |
08db6652 | 12977 | |
e7c84544 ML |
12978 | /* cursor */ |
12979 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
12980 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 | 12981 | |
e7c84544 | 12982 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
08db6652 DL |
12983 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
12984 | "(expected (%u,%u), found (%u,%u))\n", | |
12985 | pipe_name(pipe), | |
12986 | sw_entry->start, sw_entry->end, | |
12987 | hw_entry->start, hw_entry->end); | |
12988 | } | |
12989 | } | |
12990 | ||
91d1b4bd | 12991 | static void |
c0ead703 | 12992 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 12993 | { |
35dd3c64 | 12994 | struct drm_connector *connector; |
8af6cf88 | 12995 | |
e7c84544 | 12996 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
12997 | struct drm_encoder *encoder = connector->encoder; |
12998 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12999 | |
e7c84544 ML |
13000 | if (state->crtc != crtc) |
13001 | continue; | |
13002 | ||
5a21b665 | 13003 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 13004 | |
ad3c558f | 13005 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 13006 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 13007 | } |
91d1b4bd DV |
13008 | } |
13009 | ||
13010 | static void | |
c0ead703 | 13011 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
13012 | { |
13013 | struct intel_encoder *encoder; | |
13014 | struct intel_connector *connector; | |
8af6cf88 | 13015 | |
b2784e15 | 13016 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13017 | bool enabled = false; |
4d20cd86 | 13018 | enum pipe pipe; |
8af6cf88 DV |
13019 | |
13020 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13021 | encoder->base.base.id, | |
8e329a03 | 13022 | encoder->base.name); |
8af6cf88 | 13023 | |
3a3371ff | 13024 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13025 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13026 | continue; |
13027 | enabled = true; | |
ad3c558f ML |
13028 | |
13029 | I915_STATE_WARN(connector->base.state->crtc != | |
13030 | encoder->base.crtc, | |
13031 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13032 | } |
0e32b39c | 13033 | |
e2c719b7 | 13034 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13035 | "encoder's enabled state mismatch " |
13036 | "(expected %i, found %i)\n", | |
13037 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13038 | |
13039 | if (!encoder->base.crtc) { | |
4d20cd86 | 13040 | bool active; |
7c60d198 | 13041 | |
4d20cd86 ML |
13042 | active = encoder->get_hw_state(encoder, &pipe); |
13043 | I915_STATE_WARN(active, | |
13044 | "encoder detached but still enabled on pipe %c.\n", | |
13045 | pipe_name(pipe)); | |
7c60d198 | 13046 | } |
8af6cf88 | 13047 | } |
91d1b4bd DV |
13048 | } |
13049 | ||
13050 | static void | |
c0ead703 ML |
13051 | verify_crtc_state(struct drm_crtc *crtc, |
13052 | struct drm_crtc_state *old_crtc_state, | |
13053 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 13054 | { |
e7c84544 | 13055 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13056 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 13057 | struct intel_encoder *encoder; |
e7c84544 ML |
13058 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13059 | struct intel_crtc_state *pipe_config, *sw_config; | |
13060 | struct drm_atomic_state *old_state; | |
13061 | bool active; | |
045ac3b5 | 13062 | |
e7c84544 | 13063 | old_state = old_crtc_state->state; |
ec2dc6a0 | 13064 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
13065 | pipe_config = to_intel_crtc_state(old_crtc_state); |
13066 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13067 | pipe_config->base.crtc = crtc; | |
13068 | pipe_config->base.state = old_state; | |
8af6cf88 | 13069 | |
78108b7c | 13070 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 13071 | |
e7c84544 | 13072 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 13073 | |
e7c84544 ML |
13074 | /* hw state is inconsistent with the pipe quirk */ |
13075 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
13076 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13077 | active = new_crtc_state->active; | |
6c49f241 | 13078 | |
e7c84544 ML |
13079 | I915_STATE_WARN(new_crtc_state->active != active, |
13080 | "crtc active state doesn't match with hw state " | |
13081 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 13082 | |
e7c84544 ML |
13083 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
13084 | "transitional active state does not match atomic hw state " | |
13085 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13086 | |
e7c84544 ML |
13087 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13088 | enum pipe pipe; | |
4d20cd86 | 13089 | |
e7c84544 ML |
13090 | active = encoder->get_hw_state(encoder, &pipe); |
13091 | I915_STATE_WARN(active != new_crtc_state->active, | |
13092 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13093 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13094 | |
e7c84544 ML |
13095 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13096 | "Encoder connected to wrong pipe %c\n", | |
13097 | pipe_name(pipe)); | |
4d20cd86 | 13098 | |
253c84c8 VS |
13099 | if (active) { |
13100 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 13101 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 13102 | } |
e7c84544 | 13103 | } |
53d9f4e9 | 13104 | |
e7c84544 ML |
13105 | if (!new_crtc_state->active) |
13106 | return; | |
cfb23ed6 | 13107 | |
e7c84544 | 13108 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13109 | |
e7c84544 ML |
13110 | sw_config = to_intel_crtc_state(crtc->state); |
13111 | if (!intel_pipe_config_compare(dev, sw_config, | |
13112 | pipe_config, false)) { | |
13113 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13114 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13115 | "[hw state]"); | |
13116 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13117 | "[sw state]"); | |
8af6cf88 DV |
13118 | } |
13119 | } | |
13120 | ||
91d1b4bd | 13121 | static void |
c0ead703 ML |
13122 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13123 | struct intel_shared_dpll *pll, | |
13124 | struct drm_crtc *crtc, | |
13125 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13126 | { |
91d1b4bd | 13127 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13128 | unsigned crtc_mask; |
13129 | bool active; | |
5358901f | 13130 | |
e7c84544 | 13131 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13132 | |
e7c84544 | 13133 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13134 | |
e7c84544 | 13135 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13136 | |
e7c84544 ML |
13137 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13138 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13139 | "pll in active use but not on in sw tracking\n"); | |
13140 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13141 | "pll is on but not used by any active crtc\n"); | |
13142 | I915_STATE_WARN(pll->on != active, | |
13143 | "pll on state mismatch (expected %i, found %i)\n", | |
13144 | pll->on, active); | |
13145 | } | |
5358901f | 13146 | |
e7c84544 | 13147 | if (!crtc) { |
2dd66ebd | 13148 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13149 | "more active pll users than references: %x vs %x\n", |
13150 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13151 | |
e7c84544 ML |
13152 | return; |
13153 | } | |
13154 | ||
13155 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13156 | ||
13157 | if (new_state->active) | |
13158 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13159 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13160 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13161 | else | |
13162 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13163 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13164 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13165 | |
e7c84544 ML |
13166 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13167 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13168 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13169 | |
e7c84544 ML |
13170 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13171 | &dpll_hw_state, | |
13172 | sizeof(dpll_hw_state)), | |
13173 | "pll hw state mismatch\n"); | |
13174 | } | |
13175 | ||
13176 | static void | |
c0ead703 ML |
13177 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13178 | struct drm_crtc_state *old_crtc_state, | |
13179 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 13180 | { |
fac5e23e | 13181 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13182 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
13183 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13184 | ||
13185 | if (new_state->shared_dpll) | |
c0ead703 | 13186 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13187 | |
13188 | if (old_state->shared_dpll && | |
13189 | old_state->shared_dpll != new_state->shared_dpll) { | |
13190 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13191 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13192 | ||
13193 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13194 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13195 | pipe_name(drm_crtc_index(crtc))); | |
13196 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13197 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13198 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13199 | } |
8af6cf88 DV |
13200 | } |
13201 | ||
e7c84544 | 13202 | static void |
c0ead703 | 13203 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13204 | struct drm_crtc_state *old_state, |
13205 | struct drm_crtc_state *new_state) | |
13206 | { | |
5a21b665 DV |
13207 | if (!needs_modeset(new_state) && |
13208 | !to_intel_crtc_state(new_state)->update_pipe) | |
13209 | return; | |
13210 | ||
c0ead703 | 13211 | verify_wm_state(crtc, new_state); |
5a21b665 | 13212 | verify_connector_state(crtc->dev, crtc); |
c0ead703 ML |
13213 | verify_crtc_state(crtc, old_state, new_state); |
13214 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13215 | } |
13216 | ||
13217 | static void | |
c0ead703 | 13218 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 13219 | { |
fac5e23e | 13220 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13221 | int i; |
13222 | ||
13223 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13224 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13225 | } |
13226 | ||
13227 | static void | |
c0ead703 | 13228 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13229 | { |
c0ead703 ML |
13230 | verify_encoder_state(dev); |
13231 | verify_connector_state(dev, NULL); | |
13232 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13233 | } |
13234 | ||
80715b2f VS |
13235 | static void update_scanline_offset(struct intel_crtc *crtc) |
13236 | { | |
13237 | struct drm_device *dev = crtc->base.dev; | |
13238 | ||
13239 | /* | |
13240 | * The scanline counter increments at the leading edge of hsync. | |
13241 | * | |
13242 | * On most platforms it starts counting from vtotal-1 on the | |
13243 | * first active line. That means the scanline counter value is | |
13244 | * always one less than what we would expect. Ie. just after | |
13245 | * start of vblank, which also occurs at start of hsync (on the | |
13246 | * last active line), the scanline counter will read vblank_start-1. | |
13247 | * | |
13248 | * On gen2 the scanline counter starts counting from 1 instead | |
13249 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13250 | * to keep the value positive), instead of adding one. | |
13251 | * | |
13252 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13253 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13254 | * there's an extra 1 line difference. So we need to add two instead of | |
13255 | * one to the value. | |
13256 | */ | |
13257 | if (IS_GEN2(dev)) { | |
124abe07 | 13258 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13259 | int vtotal; |
13260 | ||
124abe07 VS |
13261 | vtotal = adjusted_mode->crtc_vtotal; |
13262 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13263 | vtotal /= 2; |
13264 | ||
13265 | crtc->scanline_offset = vtotal - 1; | |
13266 | } else if (HAS_DDI(dev) && | |
2d84d2b3 | 13267 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13268 | crtc->scanline_offset = 2; |
13269 | } else | |
13270 | crtc->scanline_offset = 1; | |
13271 | } | |
13272 | ||
ad421372 | 13273 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13274 | { |
225da59b | 13275 | struct drm_device *dev = state->dev; |
ed6739ef | 13276 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13277 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13278 | struct drm_crtc *crtc; |
13279 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13280 | int i; |
ed6739ef ACO |
13281 | |
13282 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13283 | return; |
ed6739ef | 13284 | |
0a9ab303 | 13285 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13286 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13287 | struct intel_shared_dpll *old_dpll = |
13288 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13289 | |
fb1a38a9 | 13290 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13291 | continue; |
13292 | ||
8106ddbd | 13293 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13294 | |
8106ddbd | 13295 | if (!old_dpll) |
fb1a38a9 | 13296 | continue; |
0a9ab303 | 13297 | |
ad421372 ML |
13298 | if (!shared_dpll) |
13299 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13300 | |
8106ddbd | 13301 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13302 | } |
ed6739ef ACO |
13303 | } |
13304 | ||
99d736a2 ML |
13305 | /* |
13306 | * This implements the workaround described in the "notes" section of the mode | |
13307 | * set sequence documentation. When going from no pipes or single pipe to | |
13308 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13309 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13310 | */ | |
13311 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13312 | { | |
13313 | struct drm_crtc_state *crtc_state; | |
13314 | struct intel_crtc *intel_crtc; | |
13315 | struct drm_crtc *crtc; | |
13316 | struct intel_crtc_state *first_crtc_state = NULL; | |
13317 | struct intel_crtc_state *other_crtc_state = NULL; | |
13318 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13319 | int i; | |
13320 | ||
13321 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13322 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13323 | intel_crtc = to_intel_crtc(crtc); | |
13324 | ||
13325 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13326 | continue; | |
13327 | ||
13328 | if (first_crtc_state) { | |
13329 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13330 | break; | |
13331 | } else { | |
13332 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13333 | first_pipe = intel_crtc->pipe; | |
13334 | } | |
13335 | } | |
13336 | ||
13337 | /* No workaround needed? */ | |
13338 | if (!first_crtc_state) | |
13339 | return 0; | |
13340 | ||
13341 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13342 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13343 | struct intel_crtc_state *pipe_config; | |
13344 | ||
13345 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13346 | if (IS_ERR(pipe_config)) | |
13347 | return PTR_ERR(pipe_config); | |
13348 | ||
13349 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13350 | ||
13351 | if (!pipe_config->base.active || | |
13352 | needs_modeset(&pipe_config->base)) | |
13353 | continue; | |
13354 | ||
13355 | /* 2 or more enabled crtcs means no need for w/a */ | |
13356 | if (enabled_pipe != INVALID_PIPE) | |
13357 | return 0; | |
13358 | ||
13359 | enabled_pipe = intel_crtc->pipe; | |
13360 | } | |
13361 | ||
13362 | if (enabled_pipe != INVALID_PIPE) | |
13363 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13364 | else if (other_crtc_state) | |
13365 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13366 | ||
13367 | return 0; | |
13368 | } | |
13369 | ||
27c329ed ML |
13370 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13371 | { | |
13372 | struct drm_crtc *crtc; | |
13373 | struct drm_crtc_state *crtc_state; | |
13374 | int ret = 0; | |
13375 | ||
13376 | /* add all active pipes to the state */ | |
13377 | for_each_crtc(state->dev, crtc) { | |
13378 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13379 | if (IS_ERR(crtc_state)) | |
13380 | return PTR_ERR(crtc_state); | |
13381 | ||
13382 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13383 | continue; | |
13384 | ||
13385 | crtc_state->mode_changed = true; | |
13386 | ||
13387 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13388 | if (ret) | |
13389 | break; | |
13390 | ||
13391 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13392 | if (ret) | |
13393 | break; | |
13394 | } | |
13395 | ||
13396 | return ret; | |
13397 | } | |
13398 | ||
c347a676 | 13399 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13400 | { |
565602d7 | 13401 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13402 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
13403 | struct drm_crtc *crtc; |
13404 | struct drm_crtc_state *crtc_state; | |
13405 | int ret = 0, i; | |
054518dd | 13406 | |
b359283a ML |
13407 | if (!check_digital_port_conflicts(state)) { |
13408 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13409 | return -EINVAL; | |
13410 | } | |
13411 | ||
565602d7 ML |
13412 | intel_state->modeset = true; |
13413 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13414 | ||
13415 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13416 | if (crtc_state->active) | |
13417 | intel_state->active_crtcs |= 1 << i; | |
13418 | else | |
13419 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13420 | |
13421 | if (crtc_state->active != crtc->state->active) | |
13422 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13423 | } |
13424 | ||
054518dd ACO |
13425 | /* |
13426 | * See if the config requires any additional preparation, e.g. | |
13427 | * to adjust global state with pipes off. We need to do this | |
13428 | * here so we can get the modeset_pipe updated config for the new | |
13429 | * mode set on this crtc. For other crtcs we need to use the | |
13430 | * adjusted_mode bits in the crtc directly. | |
13431 | */ | |
27c329ed | 13432 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 13433 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 13434 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
13435 | if (!intel_state->cdclk_pll_vco) |
13436 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 13437 | |
27c329ed | 13438 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
13439 | if (ret < 0) |
13440 | return ret; | |
27c329ed | 13441 | |
c89e39f3 | 13442 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13443 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) |
27c329ed ML |
13444 | ret = intel_modeset_all_pipes(state); |
13445 | ||
13446 | if (ret < 0) | |
054518dd | 13447 | return ret; |
e8788cbc ML |
13448 | |
13449 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13450 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13451 | } else |
1a617b77 | 13452 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13453 | |
ad421372 | 13454 | intel_modeset_clear_plls(state); |
054518dd | 13455 | |
565602d7 | 13456 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13457 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13458 | |
ad421372 | 13459 | return 0; |
c347a676 ACO |
13460 | } |
13461 | ||
aa363136 MR |
13462 | /* |
13463 | * Handle calculation of various watermark data at the end of the atomic check | |
13464 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13465 | * handlers to ensure that all derived state has been updated. | |
13466 | */ | |
55994c2c | 13467 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
13468 | { |
13469 | struct drm_device *dev = state->dev; | |
98d39494 | 13470 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
13471 | |
13472 | /* Is there platform-specific watermark information to calculate? */ | |
13473 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
13474 | return dev_priv->display.compute_global_watermarks(state); |
13475 | ||
13476 | return 0; | |
aa363136 MR |
13477 | } |
13478 | ||
74c090b1 ML |
13479 | /** |
13480 | * intel_atomic_check - validate state object | |
13481 | * @dev: drm device | |
13482 | * @state: state to validate | |
13483 | */ | |
13484 | static int intel_atomic_check(struct drm_device *dev, | |
13485 | struct drm_atomic_state *state) | |
c347a676 | 13486 | { |
dd8b3bdb | 13487 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13488 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13489 | struct drm_crtc *crtc; |
13490 | struct drm_crtc_state *crtc_state; | |
13491 | int ret, i; | |
61333b60 | 13492 | bool any_ms = false; |
c347a676 | 13493 | |
74c090b1 | 13494 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13495 | if (ret) |
13496 | return ret; | |
13497 | ||
c347a676 | 13498 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13499 | struct intel_crtc_state *pipe_config = |
13500 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13501 | |
13502 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13503 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13504 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13505 | |
af4a879e | 13506 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
13507 | continue; |
13508 | ||
af4a879e DV |
13509 | if (!crtc_state->enable) { |
13510 | any_ms = true; | |
cfb23ed6 | 13511 | continue; |
af4a879e | 13512 | } |
cfb23ed6 | 13513 | |
26495481 DV |
13514 | /* FIXME: For only active_changed we shouldn't need to do any |
13515 | * state recomputation at all. */ | |
13516 | ||
1ed51de9 DV |
13517 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13518 | if (ret) | |
13519 | return ret; | |
b359283a | 13520 | |
cfb23ed6 | 13521 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
13522 | if (ret) { |
13523 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
13524 | pipe_config, "[failed]"); | |
c347a676 | 13525 | return ret; |
25aa1c39 | 13526 | } |
c347a676 | 13527 | |
73831236 | 13528 | if (i915.fastboot && |
dd8b3bdb | 13529 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13530 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13531 | pipe_config, true)) { |
26495481 | 13532 | crtc_state->mode_changed = false; |
bfd16b2a | 13533 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13534 | } |
13535 | ||
af4a879e | 13536 | if (needs_modeset(crtc_state)) |
26495481 | 13537 | any_ms = true; |
cfb23ed6 | 13538 | |
af4a879e DV |
13539 | ret = drm_atomic_add_affected_planes(state, crtc); |
13540 | if (ret) | |
13541 | return ret; | |
61333b60 | 13542 | |
26495481 DV |
13543 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13544 | needs_modeset(crtc_state) ? | |
13545 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13546 | } |
13547 | ||
61333b60 ML |
13548 | if (any_ms) { |
13549 | ret = intel_modeset_checks(state); | |
13550 | ||
13551 | if (ret) | |
13552 | return ret; | |
27c329ed | 13553 | } else |
dd8b3bdb | 13554 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13555 | |
dd8b3bdb | 13556 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13557 | if (ret) |
13558 | return ret; | |
13559 | ||
f51be2e0 | 13560 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 13561 | return calc_watermark_data(state); |
054518dd ACO |
13562 | } |
13563 | ||
5008e874 ML |
13564 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13565 | struct drm_atomic_state *state, | |
81072bfd | 13566 | bool nonblock) |
5008e874 | 13567 | { |
fac5e23e | 13568 | struct drm_i915_private *dev_priv = to_i915(dev); |
7580d774 | 13569 | struct drm_plane_state *plane_state; |
5008e874 | 13570 | struct drm_crtc_state *crtc_state; |
7580d774 | 13571 | struct drm_plane *plane; |
5008e874 ML |
13572 | struct drm_crtc *crtc; |
13573 | int i, ret; | |
13574 | ||
5a21b665 DV |
13575 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
13576 | if (state->legacy_cursor_update) | |
a6747b73 ML |
13577 | continue; |
13578 | ||
5a21b665 DV |
13579 | ret = intel_crtc_wait_for_pending_flips(crtc); |
13580 | if (ret) | |
13581 | return ret; | |
5008e874 | 13582 | |
5a21b665 DV |
13583 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
13584 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
13585 | } |
13586 | ||
f935675f ML |
13587 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13588 | if (ret) | |
13589 | return ret; | |
13590 | ||
5008e874 | 13591 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 13592 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 13593 | |
21daaeee | 13594 | if (!ret && !nonblock) { |
7580d774 ML |
13595 | for_each_plane_in_state(state, plane, plane_state, i) { |
13596 | struct intel_plane_state *intel_plane_state = | |
13597 | to_intel_plane_state(plane_state); | |
13598 | ||
13599 | if (!intel_plane_state->wait_req) | |
13600 | continue; | |
13601 | ||
776f3236 CW |
13602 | ret = i915_wait_request(intel_plane_state->wait_req, |
13603 | true, NULL, NULL); | |
f7e5838b | 13604 | if (ret) { |
f4457ae7 CW |
13605 | /* Any hang should be swallowed by the wait */ |
13606 | WARN_ON(ret == -EIO); | |
f7e5838b CW |
13607 | mutex_lock(&dev->struct_mutex); |
13608 | drm_atomic_helper_cleanup_planes(dev, state); | |
13609 | mutex_unlock(&dev->struct_mutex); | |
7580d774 | 13610 | break; |
f7e5838b | 13611 | } |
7580d774 | 13612 | } |
7580d774 | 13613 | } |
5008e874 ML |
13614 | |
13615 | return ret; | |
13616 | } | |
13617 | ||
a2991414 ML |
13618 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
13619 | { | |
13620 | struct drm_device *dev = crtc->base.dev; | |
13621 | ||
13622 | if (!dev->max_vblank_count) | |
13623 | return drm_accurate_vblank_count(&crtc->base); | |
13624 | ||
13625 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
13626 | } | |
13627 | ||
5a21b665 DV |
13628 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13629 | struct drm_i915_private *dev_priv, | |
13630 | unsigned crtc_mask) | |
e8861675 | 13631 | { |
5a21b665 DV |
13632 | unsigned last_vblank_count[I915_MAX_PIPES]; |
13633 | enum pipe pipe; | |
13634 | int ret; | |
e8861675 | 13635 | |
5a21b665 DV |
13636 | if (!crtc_mask) |
13637 | return; | |
e8861675 | 13638 | |
5a21b665 DV |
13639 | for_each_pipe(dev_priv, pipe) { |
13640 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
e8861675 | 13641 | |
5a21b665 | 13642 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
13643 | continue; |
13644 | ||
5a21b665 DV |
13645 | ret = drm_crtc_vblank_get(crtc); |
13646 | if (WARN_ON(ret != 0)) { | |
13647 | crtc_mask &= ~(1 << pipe); | |
13648 | continue; | |
e8861675 ML |
13649 | } |
13650 | ||
5a21b665 | 13651 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); |
e8861675 ML |
13652 | } |
13653 | ||
5a21b665 DV |
13654 | for_each_pipe(dev_priv, pipe) { |
13655 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13656 | long lret; | |
e8861675 | 13657 | |
5a21b665 DV |
13658 | if (!((1 << pipe) & crtc_mask)) |
13659 | continue; | |
d55dbd06 | 13660 | |
5a21b665 DV |
13661 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
13662 | last_vblank_count[pipe] != | |
13663 | drm_crtc_vblank_count(crtc), | |
13664 | msecs_to_jiffies(50)); | |
d55dbd06 | 13665 | |
5a21b665 | 13666 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 13667 | |
5a21b665 | 13668 | drm_crtc_vblank_put(crtc); |
d55dbd06 ML |
13669 | } |
13670 | } | |
13671 | ||
5a21b665 | 13672 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 13673 | { |
5a21b665 DV |
13674 | /* fb updated, need to unpin old fb */ |
13675 | if (crtc_state->fb_changed) | |
13676 | return true; | |
a6747b73 | 13677 | |
5a21b665 DV |
13678 | /* wm changes, need vblank before final wm's */ |
13679 | if (crtc_state->update_wm_post) | |
13680 | return true; | |
a6747b73 | 13681 | |
5a21b665 DV |
13682 | /* |
13683 | * cxsr is re-enabled after vblank. | |
13684 | * This is already handled by crtc_state->update_wm_post, | |
13685 | * but added for clarity. | |
13686 | */ | |
13687 | if (crtc_state->disable_cxsr) | |
13688 | return true; | |
a6747b73 | 13689 | |
5a21b665 | 13690 | return false; |
e8861675 ML |
13691 | } |
13692 | ||
94f05024 | 13693 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 13694 | { |
94f05024 | 13695 | struct drm_device *dev = state->dev; |
565602d7 | 13696 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13697 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 13698 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13699 | struct drm_crtc *crtc; |
5a21b665 | 13700 | struct intel_crtc_state *intel_cstate; |
94f05024 DV |
13701 | struct drm_plane *plane; |
13702 | struct drm_plane_state *plane_state; | |
5a21b665 DV |
13703 | bool hw_check = intel_state->modeset; |
13704 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
13705 | unsigned crtc_vblank_mask = 0; | |
94f05024 | 13706 | int i, ret; |
a6778b3c | 13707 | |
94f05024 DV |
13708 | for_each_plane_in_state(state, plane, plane_state, i) { |
13709 | struct intel_plane_state *intel_plane_state = | |
13710 | to_intel_plane_state(plane_state); | |
ea0000f0 | 13711 | |
94f05024 DV |
13712 | if (!intel_plane_state->wait_req) |
13713 | continue; | |
d4afb8cc | 13714 | |
776f3236 CW |
13715 | ret = i915_wait_request(intel_plane_state->wait_req, |
13716 | true, NULL, NULL); | |
94f05024 DV |
13717 | /* EIO should be eaten, and we can't get interrupted in the |
13718 | * worker, and blocking commits have waited already. */ | |
13719 | WARN_ON(ret); | |
13720 | } | |
1c5e19f8 | 13721 | |
ea0000f0 DV |
13722 | drm_atomic_helper_wait_for_dependencies(state); |
13723 | ||
565602d7 ML |
13724 | if (intel_state->modeset) { |
13725 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13726 | sizeof(intel_state->min_pixclk)); | |
13727 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13728 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
5a21b665 DV |
13729 | |
13730 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13731 | } |
13732 | ||
29ceb0e6 | 13733 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13734 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13735 | ||
5a21b665 DV |
13736 | if (needs_modeset(crtc->state) || |
13737 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13738 | hw_check = true; | |
13739 | ||
13740 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13741 | modeset_get_crtc_power_domains(crtc, | |
13742 | to_intel_crtc_state(crtc->state)); | |
13743 | } | |
13744 | ||
61333b60 ML |
13745 | if (!needs_modeset(crtc->state)) |
13746 | continue; | |
13747 | ||
29ceb0e6 | 13748 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13749 | |
29ceb0e6 VS |
13750 | if (old_crtc_state->active) { |
13751 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13752 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13753 | intel_crtc->active = false; |
58f9c0bc | 13754 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13755 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13756 | |
13757 | /* | |
13758 | * Underruns don't always raise | |
13759 | * interrupts, so check manually. | |
13760 | */ | |
13761 | intel_check_cpu_fifo_underruns(dev_priv); | |
13762 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13763 | |
13764 | if (!crtc->state->active) | |
13765 | intel_update_watermarks(crtc); | |
a539205a | 13766 | } |
b8cecdf5 | 13767 | } |
7758a113 | 13768 | |
ea9d758d DV |
13769 | /* Only after disabling all output pipelines that will be changed can we |
13770 | * update the the output configuration. */ | |
4740b0f2 | 13771 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13772 | |
565602d7 | 13773 | if (intel_state->modeset) { |
4740b0f2 | 13774 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13775 | |
13776 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 13777 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 13778 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 13779 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 13780 | |
c0ead703 | 13781 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 13782 | } |
47fab737 | 13783 | |
a6778b3c | 13784 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13785 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13786 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13787 | bool modeset = needs_modeset(crtc->state); | |
5a21b665 DV |
13788 | struct intel_crtc_state *pipe_config = |
13789 | to_intel_crtc_state(crtc->state); | |
9f836f90 | 13790 | |
f6ac4b2a | 13791 | if (modeset && crtc->state->active) { |
a539205a ML |
13792 | update_scanline_offset(to_intel_crtc(crtc)); |
13793 | dev_priv->display.crtc_enable(crtc); | |
13794 | } | |
80715b2f | 13795 | |
1f7528c4 DV |
13796 | /* Complete events for now disable pipes here. */ |
13797 | if (modeset && !crtc->state->active && crtc->state->event) { | |
13798 | spin_lock_irq(&dev->event_lock); | |
13799 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
13800 | spin_unlock_irq(&dev->event_lock); | |
13801 | ||
13802 | crtc->state->event = NULL; | |
13803 | } | |
13804 | ||
f6ac4b2a | 13805 | if (!modeset) |
29ceb0e6 | 13806 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13807 | |
5a21b665 DV |
13808 | if (crtc->state->active && |
13809 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
faf68d92 | 13810 | intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state)); |
5a21b665 | 13811 | |
1f7528c4 | 13812 | if (crtc->state->active) |
5a21b665 | 13813 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
f6d1973d | 13814 | |
5a21b665 DV |
13815 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13816 | crtc_vblank_mask |= 1 << i; | |
177246a8 MR |
13817 | } |
13818 | ||
94f05024 DV |
13819 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
13820 | * already, but still need the state for the delayed optimization. To | |
13821 | * fix this: | |
13822 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
13823 | * - schedule that vblank worker _before_ calling hw_done | |
13824 | * - at the start of commit_tail, cancel it _synchrously | |
13825 | * - switch over to the vblank wait helper in the core after that since | |
13826 | * we don't need out special handling any more. | |
13827 | */ | |
5a21b665 DV |
13828 | if (!state->legacy_cursor_update) |
13829 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
13830 | ||
13831 | /* | |
13832 | * Now that the vblank has passed, we can go ahead and program the | |
13833 | * optimal watermarks on platforms that need two-step watermark | |
13834 | * programming. | |
13835 | * | |
13836 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13837 | */ | |
13838 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13839 | intel_cstate = to_intel_crtc_state(crtc->state); | |
13840 | ||
13841 | if (dev_priv->display.optimize_watermarks) | |
13842 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13843 | } | |
13844 | ||
13845 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
13846 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13847 | ||
13848 | if (put_domains[i]) | |
13849 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13850 | ||
13851 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); | |
13852 | } | |
13853 | ||
94f05024 DV |
13854 | drm_atomic_helper_commit_hw_done(state); |
13855 | ||
5a21b665 DV |
13856 | if (intel_state->modeset) |
13857 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13858 | ||
13859 | mutex_lock(&dev->struct_mutex); | |
13860 | drm_atomic_helper_cleanup_planes(dev, state); | |
13861 | mutex_unlock(&dev->struct_mutex); | |
13862 | ||
ea0000f0 DV |
13863 | drm_atomic_helper_commit_cleanup_done(state); |
13864 | ||
ee165b1a | 13865 | drm_atomic_state_free(state); |
f30da187 | 13866 | |
75714940 MK |
13867 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13868 | * of triggering bugs in unclaimed access. After we finish | |
13869 | * modesetting, see if an error has been flagged, and if so | |
13870 | * enable debugging for the next modeset - and hope we catch | |
13871 | * the culprit. | |
13872 | * | |
13873 | * XXX note that we assume display power is on at this point. | |
13874 | * This might hold true now but we need to add pm helper to check | |
13875 | * unclaimed only when the hardware is on, as atomic commits | |
13876 | * can happen also when the device is completely off. | |
13877 | */ | |
13878 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
13879 | } |
13880 | ||
13881 | static void intel_atomic_commit_work(struct work_struct *work) | |
13882 | { | |
13883 | struct drm_atomic_state *state = container_of(work, | |
13884 | struct drm_atomic_state, | |
13885 | commit_work); | |
13886 | intel_atomic_commit_tail(state); | |
13887 | } | |
13888 | ||
6c9c1b38 DV |
13889 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
13890 | { | |
13891 | struct drm_plane_state *old_plane_state; | |
13892 | struct drm_plane *plane; | |
6c9c1b38 DV |
13893 | int i; |
13894 | ||
faf5bf0a CW |
13895 | for_each_plane_in_state(state, plane, old_plane_state, i) |
13896 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
13897 | intel_fb_obj(plane->state->fb), | |
13898 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
13899 | } |
13900 | ||
94f05024 DV |
13901 | /** |
13902 | * intel_atomic_commit - commit validated state object | |
13903 | * @dev: DRM device | |
13904 | * @state: the top-level driver state object | |
13905 | * @nonblock: nonblocking commit | |
13906 | * | |
13907 | * This function commits a top-level state object that has been validated | |
13908 | * with drm_atomic_helper_check(). | |
13909 | * | |
13910 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13911 | * nonblocking commits are only safe for pure plane updates. Everything else | |
13912 | * should work though. | |
13913 | * | |
13914 | * RETURNS | |
13915 | * Zero for success or -errno. | |
13916 | */ | |
13917 | static int intel_atomic_commit(struct drm_device *dev, | |
13918 | struct drm_atomic_state *state, | |
13919 | bool nonblock) | |
13920 | { | |
13921 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 13922 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
13923 | int ret = 0; |
13924 | ||
13925 | if (intel_state->modeset && nonblock) { | |
13926 | DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n"); | |
13927 | return -EINVAL; | |
13928 | } | |
13929 | ||
13930 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
13931 | if (ret) | |
13932 | return ret; | |
13933 | ||
13934 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); | |
13935 | ||
13936 | ret = intel_atomic_prepare_commit(dev, state, nonblock); | |
13937 | if (ret) { | |
13938 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
13939 | return ret; | |
13940 | } | |
13941 | ||
13942 | drm_atomic_helper_swap_state(state, true); | |
13943 | dev_priv->wm.distrust_bios_wm = false; | |
13944 | dev_priv->wm.skl_results = intel_state->wm_results; | |
13945 | intel_shared_dpll_commit(state); | |
6c9c1b38 | 13946 | intel_atomic_track_fbs(state); |
94f05024 DV |
13947 | |
13948 | if (nonblock) | |
13949 | queue_work(system_unbound_wq, &state->commit_work); | |
13950 | else | |
13951 | intel_atomic_commit_tail(state); | |
75714940 | 13952 | |
74c090b1 | 13953 | return 0; |
7f27126e JB |
13954 | } |
13955 | ||
c0c36b94 CW |
13956 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13957 | { | |
83a57153 ACO |
13958 | struct drm_device *dev = crtc->dev; |
13959 | struct drm_atomic_state *state; | |
e694eb02 | 13960 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13961 | int ret; |
83a57153 ACO |
13962 | |
13963 | state = drm_atomic_state_alloc(dev); | |
13964 | if (!state) { | |
78108b7c VS |
13965 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
13966 | crtc->base.id, crtc->name); | |
83a57153 ACO |
13967 | return; |
13968 | } | |
13969 | ||
e694eb02 | 13970 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13971 | |
e694eb02 ML |
13972 | retry: |
13973 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13974 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13975 | if (!ret) { | |
13976 | if (!crtc_state->active) | |
13977 | goto out; | |
83a57153 | 13978 | |
e694eb02 | 13979 | crtc_state->mode_changed = true; |
74c090b1 | 13980 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13981 | } |
13982 | ||
e694eb02 ML |
13983 | if (ret == -EDEADLK) { |
13984 | drm_atomic_state_clear(state); | |
13985 | drm_modeset_backoff(state->acquire_ctx); | |
13986 | goto retry; | |
4ed9fb37 | 13987 | } |
4be07317 | 13988 | |
2bfb4627 | 13989 | if (ret) |
e694eb02 | 13990 | out: |
2bfb4627 | 13991 | drm_atomic_state_free(state); |
c0c36b94 CW |
13992 | } |
13993 | ||
25c5b266 DV |
13994 | #undef for_each_intel_crtc_masked |
13995 | ||
a8784875 BP |
13996 | /* |
13997 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
13998 | * drm_atomic_helper_legacy_gamma_set() directly. | |
13999 | */ | |
14000 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
14001 | u16 *red, u16 *green, u16 *blue, | |
14002 | uint32_t size) | |
14003 | { | |
14004 | struct drm_device *dev = crtc->dev; | |
14005 | struct drm_mode_config *config = &dev->mode_config; | |
14006 | struct drm_crtc_state *state; | |
14007 | int ret; | |
14008 | ||
14009 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
14010 | if (ret) | |
14011 | return ret; | |
14012 | ||
14013 | /* | |
14014 | * Make sure we update the legacy properties so this works when | |
14015 | * atomic is not enabled. | |
14016 | */ | |
14017 | ||
14018 | state = crtc->state; | |
14019 | ||
14020 | drm_object_property_set_value(&crtc->base, | |
14021 | config->degamma_lut_property, | |
14022 | (state->degamma_lut) ? | |
14023 | state->degamma_lut->base.id : 0); | |
14024 | ||
14025 | drm_object_property_set_value(&crtc->base, | |
14026 | config->ctm_property, | |
14027 | (state->ctm) ? | |
14028 | state->ctm->base.id : 0); | |
14029 | ||
14030 | drm_object_property_set_value(&crtc->base, | |
14031 | config->gamma_lut_property, | |
14032 | (state->gamma_lut) ? | |
14033 | state->gamma_lut->base.id : 0); | |
14034 | ||
14035 | return 0; | |
14036 | } | |
14037 | ||
f6e5b160 | 14038 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 14039 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 14040 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 14041 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 14042 | .destroy = intel_crtc_destroy, |
527b6abe | 14043 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
14044 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
14045 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
14046 | }; |
14047 | ||
6beb8c23 MR |
14048 | /** |
14049 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
14050 | * @plane: drm plane to prepare for | |
14051 | * @fb: framebuffer to prepare for presentation | |
14052 | * | |
14053 | * Prepares a framebuffer for usage on a display plane. Generally this | |
14054 | * involves pinning the underlying object and updating the frontbuffer tracking | |
14055 | * bits. Some older platforms need special physical address handling for | |
14056 | * cursor planes. | |
14057 | * | |
f935675f ML |
14058 | * Must be called with struct_mutex held. |
14059 | * | |
6beb8c23 MR |
14060 | * Returns 0 on success, negative error code on failure. |
14061 | */ | |
14062 | int | |
14063 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 14064 | const struct drm_plane_state *new_state) |
465c120c MR |
14065 | { |
14066 | struct drm_device *dev = plane->dev; | |
844f9111 | 14067 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 14068 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14069 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c37efb99 | 14070 | struct reservation_object *resv; |
6beb8c23 | 14071 | int ret = 0; |
465c120c | 14072 | |
1ee49399 | 14073 | if (!obj && !old_obj) |
465c120c MR |
14074 | return 0; |
14075 | ||
5008e874 ML |
14076 | if (old_obj) { |
14077 | struct drm_crtc_state *crtc_state = | |
14078 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
14079 | ||
14080 | /* Big Hammer, we also need to ensure that any pending | |
14081 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14082 | * current scanout is retired before unpinning the old | |
14083 | * framebuffer. Note that we rely on userspace rendering | |
14084 | * into the buffer attached to the pipe they are waiting | |
14085 | * on. If not, userspace generates a GPU hang with IPEHR | |
14086 | * point to the MI_WAIT_FOR_EVENT. | |
14087 | * | |
14088 | * This should only fail upon a hung GPU, in which case we | |
14089 | * can safely continue. | |
14090 | */ | |
14091 | if (needs_modeset(crtc_state)) | |
14092 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
f4457ae7 CW |
14093 | if (ret) { |
14094 | /* GPU hangs should have been swallowed by the wait */ | |
14095 | WARN_ON(ret == -EIO); | |
f935675f | 14096 | return ret; |
f4457ae7 | 14097 | } |
5008e874 ML |
14098 | } |
14099 | ||
c37efb99 CW |
14100 | if (!obj) |
14101 | return 0; | |
14102 | ||
5a21b665 | 14103 | /* For framebuffer backed by dmabuf, wait for fence */ |
c37efb99 CW |
14104 | resv = i915_gem_object_get_dmabuf_resv(obj); |
14105 | if (resv) { | |
5a21b665 DV |
14106 | long lret; |
14107 | ||
c37efb99 | 14108 | lret = reservation_object_wait_timeout_rcu(resv, false, true, |
5a21b665 DV |
14109 | MAX_SCHEDULE_TIMEOUT); |
14110 | if (lret == -ERESTARTSYS) | |
14111 | return lret; | |
14112 | ||
14113 | WARN(lret < 0, "waiting returns %li\n", lret); | |
14114 | } | |
14115 | ||
c37efb99 | 14116 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
6beb8c23 MR |
14117 | INTEL_INFO(dev)->cursor_needs_physical) { |
14118 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
14119 | ret = i915_gem_object_attach_phys(obj, align); | |
14120 | if (ret) | |
14121 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
14122 | } else { | |
3465c580 | 14123 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 14124 | } |
465c120c | 14125 | |
c37efb99 | 14126 | if (ret == 0) { |
27c01aae | 14127 | to_intel_plane_state(new_state)->wait_req = |
d72d908b CW |
14128 | i915_gem_active_get(&obj->last_write, |
14129 | &obj->base.dev->struct_mutex); | |
7580d774 | 14130 | } |
fdd508a6 | 14131 | |
6beb8c23 MR |
14132 | return ret; |
14133 | } | |
14134 | ||
38f3ce3a MR |
14135 | /** |
14136 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14137 | * @plane: drm plane to clean up for | |
14138 | * @fb: old framebuffer that was on plane | |
14139 | * | |
14140 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14141 | * |
14142 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14143 | */ |
14144 | void | |
14145 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 14146 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
14147 | { |
14148 | struct drm_device *dev = plane->dev; | |
7580d774 | 14149 | struct intel_plane_state *old_intel_state; |
84978257 | 14150 | struct intel_plane_state *intel_state = to_intel_plane_state(plane->state); |
1ee49399 ML |
14151 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14152 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14153 | |
7580d774 ML |
14154 | old_intel_state = to_intel_plane_state(old_state); |
14155 | ||
1ee49399 | 14156 | if (!obj && !old_obj) |
38f3ce3a MR |
14157 | return; |
14158 | ||
1ee49399 ML |
14159 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
14160 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 14161 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 | 14162 | |
84978257 | 14163 | i915_gem_request_assign(&intel_state->wait_req, NULL); |
7580d774 | 14164 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); |
465c120c MR |
14165 | } |
14166 | ||
6156a456 CK |
14167 | int |
14168 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14169 | { | |
14170 | int max_scale; | |
6156a456 CK |
14171 | int crtc_clock, cdclk; |
14172 | ||
bf8a0af0 | 14173 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14174 | return DRM_PLANE_HELPER_NO_SCALING; |
14175 | ||
6156a456 | 14176 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
27c329ed | 14177 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14178 | |
54bf1ce6 | 14179 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14180 | return DRM_PLANE_HELPER_NO_SCALING; |
14181 | ||
14182 | /* | |
14183 | * skl max scale is lower of: | |
14184 | * close to 3 but not 3, -1 is for that purpose | |
14185 | * or | |
14186 | * cdclk/crtc_clock | |
14187 | */ | |
14188 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14189 | ||
14190 | return max_scale; | |
14191 | } | |
14192 | ||
465c120c | 14193 | static int |
3c692a41 | 14194 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14195 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14196 | struct intel_plane_state *state) |
14197 | { | |
2b875c22 MR |
14198 | struct drm_crtc *crtc = state->base.crtc; |
14199 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 14200 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14201 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14202 | bool can_position = false; | |
465c120c | 14203 | |
693bdc28 VS |
14204 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
14205 | /* use scaler when colorkey is not required */ | |
14206 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14207 | min_scale = 1; | |
14208 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14209 | } | |
d8106366 | 14210 | can_position = true; |
6156a456 | 14211 | } |
d8106366 | 14212 | |
061e4b8d ML |
14213 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14214 | &state->dst, &state->clip, | |
9b8b013d | 14215 | state->base.rotation, |
da20eabd ML |
14216 | min_scale, max_scale, |
14217 | can_position, true, | |
14218 | &state->visible); | |
14af293f GP |
14219 | } |
14220 | ||
5a21b665 DV |
14221 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14222 | struct drm_crtc_state *old_crtc_state) | |
14223 | { | |
14224 | struct drm_device *dev = crtc->dev; | |
14225 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14226 | struct intel_crtc_state *old_intel_state = | |
14227 | to_intel_crtc_state(old_crtc_state); | |
14228 | bool modeset = needs_modeset(crtc->state); | |
14229 | ||
14230 | /* Perform vblank evasion around commit operation */ | |
14231 | intel_pipe_update_start(intel_crtc); | |
14232 | ||
14233 | if (modeset) | |
14234 | return; | |
14235 | ||
14236 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14237 | intel_color_set_csc(crtc->state); | |
14238 | intel_color_load_luts(crtc->state); | |
14239 | } | |
14240 | ||
14241 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14242 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14243 | else if (INTEL_INFO(dev)->gen >= 9) | |
14244 | skl_detach_scalers(intel_crtc); | |
14245 | } | |
14246 | ||
14247 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
14248 | struct drm_crtc_state *old_crtc_state) | |
14249 | { | |
14250 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14251 | ||
14252 | intel_pipe_update_end(intel_crtc, NULL); | |
14253 | } | |
14254 | ||
cf4c7c12 | 14255 | /** |
4a3b8769 MR |
14256 | * intel_plane_destroy - destroy a plane |
14257 | * @plane: plane to destroy | |
cf4c7c12 | 14258 | * |
4a3b8769 MR |
14259 | * Common destruction function for all types of planes (primary, cursor, |
14260 | * sprite). | |
cf4c7c12 | 14261 | */ |
4a3b8769 | 14262 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 14263 | { |
69ae561f VS |
14264 | if (!plane) |
14265 | return; | |
14266 | ||
465c120c | 14267 | drm_plane_cleanup(plane); |
69ae561f | 14268 | kfree(to_intel_plane(plane)); |
465c120c MR |
14269 | } |
14270 | ||
65a3fea0 | 14271 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14272 | .update_plane = drm_atomic_helper_update_plane, |
14273 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14274 | .destroy = intel_plane_destroy, |
c196e1d6 | 14275 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14276 | .atomic_get_property = intel_plane_atomic_get_property, |
14277 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14278 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14279 | .atomic_destroy_state = intel_plane_destroy_state, | |
14280 | ||
465c120c MR |
14281 | }; |
14282 | ||
14283 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14284 | int pipe) | |
14285 | { | |
fca0ce2a VS |
14286 | struct intel_plane *primary = NULL; |
14287 | struct intel_plane_state *state = NULL; | |
465c120c | 14288 | const uint32_t *intel_primary_formats; |
45e3743a | 14289 | unsigned int num_formats; |
fca0ce2a | 14290 | int ret; |
465c120c MR |
14291 | |
14292 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
fca0ce2a VS |
14293 | if (!primary) |
14294 | goto fail; | |
465c120c | 14295 | |
8e7d688b | 14296 | state = intel_create_plane_state(&primary->base); |
fca0ce2a VS |
14297 | if (!state) |
14298 | goto fail; | |
8e7d688b | 14299 | primary->base.state = &state->base; |
ea2c67bb | 14300 | |
465c120c MR |
14301 | primary->can_scale = false; |
14302 | primary->max_downscale = 1; | |
6156a456 CK |
14303 | if (INTEL_INFO(dev)->gen >= 9) { |
14304 | primary->can_scale = true; | |
af99ceda | 14305 | state->scaler_id = -1; |
6156a456 | 14306 | } |
465c120c MR |
14307 | primary->pipe = pipe; |
14308 | primary->plane = pipe; | |
a9ff8714 | 14309 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14310 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14311 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14312 | primary->plane = !pipe; | |
14313 | ||
6c0fd451 DL |
14314 | if (INTEL_INFO(dev)->gen >= 9) { |
14315 | intel_primary_formats = skl_primary_formats; | |
14316 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14317 | |
14318 | primary->update_plane = skylake_update_primary_plane; | |
14319 | primary->disable_plane = skylake_disable_primary_plane; | |
14320 | } else if (HAS_PCH_SPLIT(dev)) { | |
14321 | intel_primary_formats = i965_primary_formats; | |
14322 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14323 | ||
14324 | primary->update_plane = ironlake_update_primary_plane; | |
14325 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14326 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14327 | intel_primary_formats = i965_primary_formats; |
14328 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14329 | |
14330 | primary->update_plane = i9xx_update_primary_plane; | |
14331 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14332 | } else { |
14333 | intel_primary_formats = i8xx_primary_formats; | |
14334 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14335 | |
14336 | primary->update_plane = i9xx_update_primary_plane; | |
14337 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14338 | } |
14339 | ||
38573dc1 VS |
14340 | if (INTEL_INFO(dev)->gen >= 9) |
14341 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14342 | &intel_plane_funcs, | |
14343 | intel_primary_formats, num_formats, | |
14344 | DRM_PLANE_TYPE_PRIMARY, | |
14345 | "plane 1%c", pipe_name(pipe)); | |
14346 | else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
14347 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14348 | &intel_plane_funcs, | |
14349 | intel_primary_formats, num_formats, | |
14350 | DRM_PLANE_TYPE_PRIMARY, | |
14351 | "primary %c", pipe_name(pipe)); | |
14352 | else | |
14353 | ret = drm_universal_plane_init(dev, &primary->base, 0, | |
14354 | &intel_plane_funcs, | |
14355 | intel_primary_formats, num_formats, | |
14356 | DRM_PLANE_TYPE_PRIMARY, | |
14357 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
14358 | if (ret) |
14359 | goto fail; | |
48404c1e | 14360 | |
3b7a5119 SJ |
14361 | if (INTEL_INFO(dev)->gen >= 4) |
14362 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14363 | |
ea2c67bb MR |
14364 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14365 | ||
465c120c | 14366 | return &primary->base; |
fca0ce2a VS |
14367 | |
14368 | fail: | |
14369 | kfree(state); | |
14370 | kfree(primary); | |
14371 | ||
14372 | return NULL; | |
465c120c MR |
14373 | } |
14374 | ||
3b7a5119 SJ |
14375 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14376 | { | |
14377 | if (!dev->mode_config.rotation_property) { | |
14378 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14379 | BIT(DRM_ROTATE_180); | |
14380 | ||
14381 | if (INTEL_INFO(dev)->gen >= 9) | |
14382 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14383 | ||
14384 | dev->mode_config.rotation_property = | |
14385 | drm_mode_create_rotation_property(dev, flags); | |
14386 | } | |
14387 | if (dev->mode_config.rotation_property) | |
14388 | drm_object_attach_property(&plane->base.base, | |
14389 | dev->mode_config.rotation_property, | |
14390 | plane->base.state->rotation); | |
14391 | } | |
14392 | ||
3d7d6510 | 14393 | static int |
852e787c | 14394 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14395 | struct intel_crtc_state *crtc_state, |
852e787c | 14396 | struct intel_plane_state *state) |
3d7d6510 | 14397 | { |
061e4b8d | 14398 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14399 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14400 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14401 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14402 | unsigned stride; |
14403 | int ret; | |
3d7d6510 | 14404 | |
061e4b8d ML |
14405 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14406 | &state->dst, &state->clip, | |
9b8b013d | 14407 | state->base.rotation, |
3d7d6510 MR |
14408 | DRM_PLANE_HELPER_NO_SCALING, |
14409 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14410 | true, true, &state->visible); |
757f9a3e GP |
14411 | if (ret) |
14412 | return ret; | |
14413 | ||
757f9a3e GP |
14414 | /* if we want to turn off the cursor ignore width and height */ |
14415 | if (!obj) | |
da20eabd | 14416 | return 0; |
757f9a3e | 14417 | |
757f9a3e | 14418 | /* Check for which cursor types we support */ |
061e4b8d | 14419 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14420 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14421 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14422 | return -EINVAL; |
14423 | } | |
14424 | ||
ea2c67bb MR |
14425 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14426 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14427 | DRM_DEBUG_KMS("buffer is too small\n"); |
14428 | return -ENOMEM; | |
14429 | } | |
14430 | ||
3a656b54 | 14431 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14432 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14433 | return -EINVAL; |
32b7eeec MR |
14434 | } |
14435 | ||
b29ec92c VS |
14436 | /* |
14437 | * There's something wrong with the cursor on CHV pipe C. | |
14438 | * If it straddles the left edge of the screen then | |
14439 | * moving it away from the edge or disabling it often | |
14440 | * results in a pipe underrun, and often that can lead to | |
14441 | * dead pipe (constant underrun reported, and it scans | |
14442 | * out just a solid color). To recover from that, the | |
14443 | * display power well must be turned off and on again. | |
14444 | * Refuse the put the cursor into that compromised position. | |
14445 | */ | |
14446 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14447 | state->visible && state->base.crtc_x < 0) { | |
14448 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14449 | return -EINVAL; | |
14450 | } | |
14451 | ||
da20eabd | 14452 | return 0; |
852e787c | 14453 | } |
3d7d6510 | 14454 | |
a8ad0d8e ML |
14455 | static void |
14456 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14457 | struct drm_crtc *crtc) |
a8ad0d8e | 14458 | { |
f2858021 ML |
14459 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14460 | ||
14461 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14462 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14463 | } |
14464 | ||
f4a2cf29 | 14465 | static void |
55a08b3f ML |
14466 | intel_update_cursor_plane(struct drm_plane *plane, |
14467 | const struct intel_crtc_state *crtc_state, | |
14468 | const struct intel_plane_state *state) | |
852e787c | 14469 | { |
55a08b3f ML |
14470 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14471 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14472 | struct drm_device *dev = plane->dev; |
2b875c22 | 14473 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14474 | uint32_t addr; |
852e787c | 14475 | |
f4a2cf29 | 14476 | if (!obj) |
a912f12f | 14477 | addr = 0; |
f4a2cf29 | 14478 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14479 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14480 | else |
a912f12f | 14481 | addr = obj->phys_handle->busaddr; |
852e787c | 14482 | |
a912f12f | 14483 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14484 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14485 | } |
14486 | ||
3d7d6510 MR |
14487 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14488 | int pipe) | |
14489 | { | |
fca0ce2a VS |
14490 | struct intel_plane *cursor = NULL; |
14491 | struct intel_plane_state *state = NULL; | |
14492 | int ret; | |
3d7d6510 MR |
14493 | |
14494 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
fca0ce2a VS |
14495 | if (!cursor) |
14496 | goto fail; | |
3d7d6510 | 14497 | |
8e7d688b | 14498 | state = intel_create_plane_state(&cursor->base); |
fca0ce2a VS |
14499 | if (!state) |
14500 | goto fail; | |
8e7d688b | 14501 | cursor->base.state = &state->base; |
ea2c67bb | 14502 | |
3d7d6510 MR |
14503 | cursor->can_scale = false; |
14504 | cursor->max_downscale = 1; | |
14505 | cursor->pipe = pipe; | |
14506 | cursor->plane = pipe; | |
a9ff8714 | 14507 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14508 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14509 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14510 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 14511 | |
fca0ce2a VS |
14512 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
14513 | &intel_plane_funcs, | |
14514 | intel_cursor_formats, | |
14515 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
14516 | DRM_PLANE_TYPE_CURSOR, |
14517 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
14518 | if (ret) |
14519 | goto fail; | |
4398ad45 VS |
14520 | |
14521 | if (INTEL_INFO(dev)->gen >= 4) { | |
14522 | if (!dev->mode_config.rotation_property) | |
14523 | dev->mode_config.rotation_property = | |
14524 | drm_mode_create_rotation_property(dev, | |
14525 | BIT(DRM_ROTATE_0) | | |
14526 | BIT(DRM_ROTATE_180)); | |
14527 | if (dev->mode_config.rotation_property) | |
14528 | drm_object_attach_property(&cursor->base.base, | |
14529 | dev->mode_config.rotation_property, | |
8e7d688b | 14530 | state->base.rotation); |
4398ad45 VS |
14531 | } |
14532 | ||
af99ceda CK |
14533 | if (INTEL_INFO(dev)->gen >=9) |
14534 | state->scaler_id = -1; | |
14535 | ||
ea2c67bb MR |
14536 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14537 | ||
3d7d6510 | 14538 | return &cursor->base; |
fca0ce2a VS |
14539 | |
14540 | fail: | |
14541 | kfree(state); | |
14542 | kfree(cursor); | |
14543 | ||
14544 | return NULL; | |
3d7d6510 MR |
14545 | } |
14546 | ||
549e2bfb CK |
14547 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14548 | struct intel_crtc_state *crtc_state) | |
14549 | { | |
14550 | int i; | |
14551 | struct intel_scaler *intel_scaler; | |
14552 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14553 | ||
14554 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14555 | intel_scaler = &scaler_state->scalers[i]; | |
14556 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14557 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14558 | } | |
14559 | ||
14560 | scaler_state->scaler_id = -1; | |
14561 | } | |
14562 | ||
b358d0a6 | 14563 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14564 | { |
fac5e23e | 14565 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 14566 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14567 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14568 | struct drm_plane *primary = NULL; |
14569 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14570 | int ret; |
79e53945 | 14571 | |
955382f3 | 14572 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14573 | if (intel_crtc == NULL) |
14574 | return; | |
14575 | ||
f5de6e07 ACO |
14576 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14577 | if (!crtc_state) | |
14578 | goto fail; | |
550acefd ACO |
14579 | intel_crtc->config = crtc_state; |
14580 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14581 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14582 | |
549e2bfb CK |
14583 | /* initialize shared scalers */ |
14584 | if (INTEL_INFO(dev)->gen >= 9) { | |
14585 | if (pipe == PIPE_C) | |
14586 | intel_crtc->num_scalers = 1; | |
14587 | else | |
14588 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14589 | ||
14590 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14591 | } | |
14592 | ||
465c120c | 14593 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14594 | if (!primary) |
14595 | goto fail; | |
14596 | ||
14597 | cursor = intel_cursor_plane_create(dev, pipe); | |
14598 | if (!cursor) | |
14599 | goto fail; | |
14600 | ||
465c120c | 14601 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
4d5d72b7 VS |
14602 | cursor, &intel_crtc_funcs, |
14603 | "pipe %c", pipe_name(pipe)); | |
3d7d6510 MR |
14604 | if (ret) |
14605 | goto fail; | |
79e53945 | 14606 | |
1f1c2e24 VS |
14607 | /* |
14608 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14609 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14610 | */ |
80824003 JB |
14611 | intel_crtc->pipe = pipe; |
14612 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14613 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14614 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14615 | intel_crtc->plane = !pipe; |
80824003 JB |
14616 | } |
14617 | ||
4b0e333e CW |
14618 | intel_crtc->cursor_base = ~0; |
14619 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14620 | intel_crtc->cursor_size = ~0; |
8d7849db | 14621 | |
852eb00d VS |
14622 | intel_crtc->wm.cxsr_allowed = true; |
14623 | ||
22fd0fab JB |
14624 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14625 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14626 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14627 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14628 | ||
79e53945 | 14629 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14630 | |
8563b1e8 LL |
14631 | intel_color_init(&intel_crtc->base); |
14632 | ||
87b6b101 | 14633 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14634 | return; |
14635 | ||
14636 | fail: | |
69ae561f VS |
14637 | intel_plane_destroy(primary); |
14638 | intel_plane_destroy(cursor); | |
f5de6e07 | 14639 | kfree(crtc_state); |
3d7d6510 | 14640 | kfree(intel_crtc); |
79e53945 JB |
14641 | } |
14642 | ||
752aa88a JB |
14643 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14644 | { | |
14645 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14646 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14647 | |
51fd371b | 14648 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14649 | |
d3babd3f | 14650 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14651 | return INVALID_PIPE; |
14652 | ||
14653 | return to_intel_crtc(encoder->crtc)->pipe; | |
14654 | } | |
14655 | ||
08d7b3d1 | 14656 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14657 | struct drm_file *file) |
08d7b3d1 | 14658 | { |
08d7b3d1 | 14659 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14660 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14661 | struct intel_crtc *crtc; |
08d7b3d1 | 14662 | |
7707e653 | 14663 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 14664 | if (!drmmode_crtc) |
3f2c2057 | 14665 | return -ENOENT; |
08d7b3d1 | 14666 | |
7707e653 | 14667 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14668 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14669 | |
c05422d5 | 14670 | return 0; |
08d7b3d1 CW |
14671 | } |
14672 | ||
66a9278e | 14673 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14674 | { |
66a9278e DV |
14675 | struct drm_device *dev = encoder->base.dev; |
14676 | struct intel_encoder *source_encoder; | |
79e53945 | 14677 | int index_mask = 0; |
79e53945 JB |
14678 | int entry = 0; |
14679 | ||
b2784e15 | 14680 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14681 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14682 | index_mask |= (1 << entry); |
14683 | ||
79e53945 JB |
14684 | entry++; |
14685 | } | |
4ef69c7a | 14686 | |
79e53945 JB |
14687 | return index_mask; |
14688 | } | |
14689 | ||
4d302442 CW |
14690 | static bool has_edp_a(struct drm_device *dev) |
14691 | { | |
fac5e23e | 14692 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d302442 CW |
14693 | |
14694 | if (!IS_MOBILE(dev)) | |
14695 | return false; | |
14696 | ||
14697 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14698 | return false; | |
14699 | ||
e3589908 | 14700 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14701 | return false; |
14702 | ||
14703 | return true; | |
14704 | } | |
14705 | ||
84b4e042 JB |
14706 | static bool intel_crt_present(struct drm_device *dev) |
14707 | { | |
fac5e23e | 14708 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b4e042 | 14709 | |
884497ed DL |
14710 | if (INTEL_INFO(dev)->gen >= 9) |
14711 | return false; | |
14712 | ||
cf404ce4 | 14713 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14714 | return false; |
14715 | ||
14716 | if (IS_CHERRYVIEW(dev)) | |
14717 | return false; | |
14718 | ||
65e472e4 VS |
14719 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14720 | return false; | |
14721 | ||
70ac54d0 VS |
14722 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14723 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14724 | return false; | |
14725 | ||
e4abb733 | 14726 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14727 | return false; |
14728 | ||
14729 | return true; | |
14730 | } | |
14731 | ||
8090ba8c ID |
14732 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
14733 | { | |
14734 | int pps_num; | |
14735 | int pps_idx; | |
14736 | ||
14737 | if (HAS_DDI(dev_priv)) | |
14738 | return; | |
14739 | /* | |
14740 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
14741 | * everywhere where registers can be write protected. | |
14742 | */ | |
14743 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14744 | pps_num = 2; | |
14745 | else | |
14746 | pps_num = 1; | |
14747 | ||
14748 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
14749 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
14750 | ||
14751 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
14752 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
14753 | } | |
14754 | } | |
14755 | ||
44cb734c ID |
14756 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
14757 | { | |
14758 | if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv)) | |
14759 | dev_priv->pps_mmio_base = PCH_PPS_BASE; | |
14760 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14761 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
14762 | else | |
14763 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
14764 | |
14765 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
14766 | } |
14767 | ||
79e53945 JB |
14768 | static void intel_setup_outputs(struct drm_device *dev) |
14769 | { | |
fac5e23e | 14770 | struct drm_i915_private *dev_priv = to_i915(dev); |
4ef69c7a | 14771 | struct intel_encoder *encoder; |
cb0953d7 | 14772 | bool dpd_is_edp = false; |
79e53945 | 14773 | |
44cb734c ID |
14774 | intel_pps_init(dev_priv); |
14775 | ||
97a824e1 ID |
14776 | /* |
14777 | * intel_edp_init_connector() depends on this completing first, to | |
14778 | * prevent the registeration of both eDP and LVDS and the incorrect | |
14779 | * sharing of the PPS. | |
14780 | */ | |
c9093354 | 14781 | intel_lvds_init(dev); |
79e53945 | 14782 | |
84b4e042 | 14783 | if (intel_crt_present(dev)) |
79935fca | 14784 | intel_crt_init(dev); |
cb0953d7 | 14785 | |
c776eb2e VK |
14786 | if (IS_BROXTON(dev)) { |
14787 | /* | |
14788 | * FIXME: Broxton doesn't support port detection via the | |
14789 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14790 | * detect the ports. | |
14791 | */ | |
14792 | intel_ddi_init(dev, PORT_A); | |
14793 | intel_ddi_init(dev, PORT_B); | |
14794 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
14795 | |
14796 | intel_dsi_init(dev); | |
c776eb2e | 14797 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
14798 | int found; |
14799 | ||
de31facd JB |
14800 | /* |
14801 | * Haswell uses DDI functions to detect digital outputs. | |
14802 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14803 | * it's there. | |
14804 | */ | |
77179400 | 14805 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14806 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14807 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14808 | intel_ddi_init(dev, PORT_A); |
14809 | ||
14810 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14811 | * register */ | |
14812 | found = I915_READ(SFUSE_STRAP); | |
14813 | ||
14814 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14815 | intel_ddi_init(dev, PORT_B); | |
14816 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14817 | intel_ddi_init(dev, PORT_C); | |
14818 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14819 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14820 | /* |
14821 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14822 | */ | |
ef11bdb3 | 14823 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14824 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14825 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14826 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14827 | intel_ddi_init(dev, PORT_E); | |
14828 | ||
0e72a5b5 | 14829 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14830 | int found; |
5d8a7752 | 14831 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14832 | |
14833 | if (has_edp_a(dev)) | |
14834 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14835 | |
dc0fa718 | 14836 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14837 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14838 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14839 | if (!found) |
e2debe91 | 14840 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14841 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14842 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14843 | } |
14844 | ||
dc0fa718 | 14845 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14846 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14847 | |
dc0fa718 | 14848 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14849 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14850 | |
5eb08b69 | 14851 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14852 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14853 | |
270b3042 | 14854 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14855 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14856 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
22f35042 | 14857 | bool has_edp, has_port; |
457c52d8 | 14858 | |
e17ac6db VS |
14859 | /* |
14860 | * The DP_DETECTED bit is the latched state of the DDC | |
14861 | * SDA pin at boot. However since eDP doesn't require DDC | |
14862 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14863 | * eDP ports may have been muxed to an alternate function. | |
14864 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14865 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14866 | * detect eDP ports. | |
22f35042 VS |
14867 | * |
14868 | * Sadly the straps seem to be missing sometimes even for HDMI | |
14869 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
14870 | * and VBT for the presence of the port. Additionally we can't | |
14871 | * trust the port type the VBT declares as we've seen at least | |
14872 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 14873 | */ |
457c52d8 | 14874 | has_edp = intel_dp_is_edp(dev, PORT_B); |
22f35042 VS |
14875 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
14876 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
457c52d8 | 14877 | has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); |
22f35042 | 14878 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 14879 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
585a94b8 | 14880 | |
457c52d8 | 14881 | has_edp = intel_dp_is_edp(dev, PORT_C); |
22f35042 VS |
14882 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
14883 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
457c52d8 | 14884 | has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); |
22f35042 | 14885 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 14886 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
19c03924 | 14887 | |
9418c1f1 | 14888 | if (IS_CHERRYVIEW(dev)) { |
22f35042 VS |
14889 | /* |
14890 | * eDP not supported on port D, | |
14891 | * so no need to worry about it | |
14892 | */ | |
14893 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
14894 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
e66eb81d | 14895 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
22f35042 VS |
14896 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
14897 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
9418c1f1 VS |
14898 | } |
14899 | ||
3cfca973 | 14900 | intel_dsi_init(dev); |
09da55dc | 14901 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14902 | bool found = false; |
7d57382e | 14903 | |
e2debe91 | 14904 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14905 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14906 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14907 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14908 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14909 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14910 | } |
27185ae1 | 14911 | |
3fec3d2f | 14912 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14913 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14914 | } |
13520b05 KH |
14915 | |
14916 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14917 | |
e2debe91 | 14918 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14919 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14920 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14921 | } |
27185ae1 | 14922 | |
e2debe91 | 14923 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14924 | |
3fec3d2f | 14925 | if (IS_G4X(dev)) { |
b01f2c3a | 14926 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14927 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14928 | } |
3fec3d2f | 14929 | if (IS_G4X(dev)) |
ab9d7c30 | 14930 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14931 | } |
27185ae1 | 14932 | |
3fec3d2f | 14933 | if (IS_G4X(dev) && |
e7281eab | 14934 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14935 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14936 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14937 | intel_dvo_init(dev); |
14938 | ||
103a196f | 14939 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14940 | intel_tv_init(dev); |
14941 | ||
0bc12bcb | 14942 | intel_psr_init(dev); |
7c8f8a70 | 14943 | |
b2784e15 | 14944 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14945 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14946 | encoder->base.possible_clones = | |
66a9278e | 14947 | intel_encoder_clones(encoder); |
79e53945 | 14948 | } |
47356eb6 | 14949 | |
dde86e2d | 14950 | intel_init_pch_refclk(dev); |
270b3042 DV |
14951 | |
14952 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14953 | } |
14954 | ||
14955 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14956 | { | |
60a5ca01 | 14957 | struct drm_device *dev = fb->dev; |
79e53945 | 14958 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14959 | |
ef2d633e | 14960 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14961 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14962 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
f8c417cd | 14963 | i915_gem_object_put(intel_fb->obj); |
60a5ca01 | 14964 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
14965 | kfree(intel_fb); |
14966 | } | |
14967 | ||
14968 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14969 | struct drm_file *file, |
79e53945 JB |
14970 | unsigned int *handle) |
14971 | { | |
14972 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14973 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14974 | |
cc917ab4 CW |
14975 | if (obj->userptr.mm) { |
14976 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14977 | return -EINVAL; | |
14978 | } | |
14979 | ||
05394f39 | 14980 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14981 | } |
14982 | ||
86c98588 RV |
14983 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14984 | struct drm_file *file, | |
14985 | unsigned flags, unsigned color, | |
14986 | struct drm_clip_rect *clips, | |
14987 | unsigned num_clips) | |
14988 | { | |
14989 | struct drm_device *dev = fb->dev; | |
14990 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14991 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14992 | ||
14993 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14994 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14995 | mutex_unlock(&dev->struct_mutex); |
14996 | ||
14997 | return 0; | |
14998 | } | |
14999 | ||
79e53945 JB |
15000 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
15001 | .destroy = intel_user_framebuffer_destroy, | |
15002 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 15003 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
15004 | }; |
15005 | ||
b321803d DL |
15006 | static |
15007 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
15008 | uint32_t pixel_format) | |
15009 | { | |
15010 | u32 gen = INTEL_INFO(dev)->gen; | |
15011 | ||
15012 | if (gen >= 9) { | |
ac484963 VS |
15013 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
15014 | ||
b321803d DL |
15015 | /* "The stride in bytes must not exceed the of the size of 8K |
15016 | * pixels and 32K bytes." | |
15017 | */ | |
ac484963 | 15018 | return min(8192 * cpp, 32768); |
666a4537 | 15019 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
15020 | return 32*1024; |
15021 | } else if (gen >= 4) { | |
15022 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15023 | return 16*1024; | |
15024 | else | |
15025 | return 32*1024; | |
15026 | } else if (gen >= 3) { | |
15027 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15028 | return 8*1024; | |
15029 | else | |
15030 | return 16*1024; | |
15031 | } else { | |
15032 | /* XXX DSPC is limited to 4k tiled */ | |
15033 | return 8*1024; | |
15034 | } | |
15035 | } | |
15036 | ||
b5ea642a DV |
15037 | static int intel_framebuffer_init(struct drm_device *dev, |
15038 | struct intel_framebuffer *intel_fb, | |
15039 | struct drm_mode_fb_cmd2 *mode_cmd, | |
15040 | struct drm_i915_gem_object *obj) | |
79e53945 | 15041 | { |
7b49f948 | 15042 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 15043 | unsigned int aligned_height; |
79e53945 | 15044 | int ret; |
b321803d | 15045 | u32 pitch_limit, stride_alignment; |
79e53945 | 15046 | |
dd4916c5 DV |
15047 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
15048 | ||
2a80eada DV |
15049 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
15050 | /* Enforce that fb modifier and tiling mode match, but only for | |
15051 | * X-tiled. This is needed for FBC. */ | |
3e510a8e | 15052 | if (!!(i915_gem_object_get_tiling(obj) == I915_TILING_X) != |
2a80eada DV |
15053 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { |
15054 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
15055 | return -EINVAL; | |
15056 | } | |
15057 | } else { | |
3e510a8e | 15058 | if (i915_gem_object_get_tiling(obj) == I915_TILING_X) |
2a80eada | 15059 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
3e510a8e | 15060 | else if (i915_gem_object_get_tiling(obj) == I915_TILING_Y) { |
2a80eada DV |
15061 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
15062 | return -EINVAL; | |
15063 | } | |
15064 | } | |
15065 | ||
9a8f0a12 TU |
15066 | /* Passed in modifier sanity checking. */ |
15067 | switch (mode_cmd->modifier[0]) { | |
15068 | case I915_FORMAT_MOD_Y_TILED: | |
15069 | case I915_FORMAT_MOD_Yf_TILED: | |
15070 | if (INTEL_INFO(dev)->gen < 9) { | |
15071 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
15072 | mode_cmd->modifier[0]); | |
15073 | return -EINVAL; | |
15074 | } | |
15075 | case DRM_FORMAT_MOD_NONE: | |
15076 | case I915_FORMAT_MOD_X_TILED: | |
15077 | break; | |
15078 | default: | |
c0f40428 JB |
15079 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
15080 | mode_cmd->modifier[0]); | |
57cd6508 | 15081 | return -EINVAL; |
c16ed4be | 15082 | } |
57cd6508 | 15083 | |
7b49f948 VS |
15084 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
15085 | mode_cmd->modifier[0], | |
b321803d DL |
15086 | mode_cmd->pixel_format); |
15087 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
15088 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
15089 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 15090 | return -EINVAL; |
c16ed4be | 15091 | } |
57cd6508 | 15092 | |
b321803d DL |
15093 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
15094 | mode_cmd->pixel_format); | |
a35cdaa0 | 15095 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
15096 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
15097 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 15098 | "tiled" : "linear", |
a35cdaa0 | 15099 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 15100 | return -EINVAL; |
c16ed4be | 15101 | } |
5d7bd705 | 15102 | |
2a80eada | 15103 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
3e510a8e | 15104 | mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) { |
c16ed4be | 15105 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
3e510a8e CW |
15106 | mode_cmd->pitches[0], |
15107 | i915_gem_object_get_stride(obj)); | |
5d7bd705 | 15108 | return -EINVAL; |
c16ed4be | 15109 | } |
5d7bd705 | 15110 | |
57779d06 | 15111 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 15112 | switch (mode_cmd->pixel_format) { |
57779d06 | 15113 | case DRM_FORMAT_C8: |
04b3924d VS |
15114 | case DRM_FORMAT_RGB565: |
15115 | case DRM_FORMAT_XRGB8888: | |
15116 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
15117 | break; |
15118 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 15119 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
15120 | DRM_DEBUG("unsupported pixel format: %s\n", |
15121 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15122 | return -EINVAL; |
c16ed4be | 15123 | } |
57779d06 | 15124 | break; |
57779d06 | 15125 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
15126 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
15127 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
15128 | DRM_DEBUG("unsupported pixel format: %s\n", |
15129 | drm_get_format_name(mode_cmd->pixel_format)); | |
15130 | return -EINVAL; | |
15131 | } | |
15132 | break; | |
15133 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15134 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15135 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 15136 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
15137 | DRM_DEBUG("unsupported pixel format: %s\n", |
15138 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15139 | return -EINVAL; |
c16ed4be | 15140 | } |
b5626747 | 15141 | break; |
7531208b | 15142 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 15143 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
15144 | DRM_DEBUG("unsupported pixel format: %s\n", |
15145 | drm_get_format_name(mode_cmd->pixel_format)); | |
15146 | return -EINVAL; | |
15147 | } | |
15148 | break; | |
04b3924d VS |
15149 | case DRM_FORMAT_YUYV: |
15150 | case DRM_FORMAT_UYVY: | |
15151 | case DRM_FORMAT_YVYU: | |
15152 | case DRM_FORMAT_VYUY: | |
c16ed4be | 15153 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
15154 | DRM_DEBUG("unsupported pixel format: %s\n", |
15155 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15156 | return -EINVAL; |
c16ed4be | 15157 | } |
57cd6508 CW |
15158 | break; |
15159 | default: | |
4ee62c76 VS |
15160 | DRM_DEBUG("unsupported pixel format: %s\n", |
15161 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
15162 | return -EINVAL; |
15163 | } | |
15164 | ||
90f9a336 VS |
15165 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15166 | if (mode_cmd->offsets[0] != 0) | |
15167 | return -EINVAL; | |
15168 | ||
ec2c981e | 15169 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
15170 | mode_cmd->pixel_format, |
15171 | mode_cmd->modifier[0]); | |
53155c0a DV |
15172 | /* FIXME drm helper for size checks (especially planar formats)? */ |
15173 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
15174 | return -EINVAL; | |
15175 | ||
c7d73f6a DV |
15176 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15177 | intel_fb->obj = obj; | |
15178 | ||
2d7a215f VS |
15179 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
15180 | ||
79e53945 JB |
15181 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15182 | if (ret) { | |
15183 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15184 | return ret; | |
15185 | } | |
15186 | ||
0b05e1e0 VS |
15187 | intel_fb->obj->framebuffer_references++; |
15188 | ||
79e53945 JB |
15189 | return 0; |
15190 | } | |
15191 | ||
79e53945 JB |
15192 | static struct drm_framebuffer * |
15193 | intel_user_framebuffer_create(struct drm_device *dev, | |
15194 | struct drm_file *filp, | |
1eb83451 | 15195 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15196 | { |
dcb1394e | 15197 | struct drm_framebuffer *fb; |
05394f39 | 15198 | struct drm_i915_gem_object *obj; |
76dc3769 | 15199 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15200 | |
03ac0642 CW |
15201 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
15202 | if (!obj) | |
cce13ff7 | 15203 | return ERR_PTR(-ENOENT); |
79e53945 | 15204 | |
92907cbb | 15205 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e | 15206 | if (IS_ERR(fb)) |
34911fd3 | 15207 | i915_gem_object_put_unlocked(obj); |
dcb1394e LW |
15208 | |
15209 | return fb; | |
79e53945 JB |
15210 | } |
15211 | ||
0695726e | 15212 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 15213 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
15214 | { |
15215 | } | |
15216 | #endif | |
15217 | ||
79e53945 | 15218 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15219 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15220 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15221 | .atomic_check = intel_atomic_check, |
15222 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15223 | .atomic_state_alloc = intel_atomic_state_alloc, |
15224 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15225 | }; |
15226 | ||
88212941 ID |
15227 | /** |
15228 | * intel_init_display_hooks - initialize the display modesetting hooks | |
15229 | * @dev_priv: device private | |
15230 | */ | |
15231 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 15232 | { |
88212941 | 15233 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 15234 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15235 | dev_priv->display.get_initial_plane_config = |
15236 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15237 | dev_priv->display.crtc_compute_clock = |
15238 | haswell_crtc_compute_clock; | |
15239 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15240 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15241 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 15242 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15243 | dev_priv->display.get_initial_plane_config = |
15244 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15245 | dev_priv->display.crtc_compute_clock = |
15246 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15247 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15248 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15249 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 15250 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15251 | dev_priv->display.get_initial_plane_config = |
15252 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15253 | dev_priv->display.crtc_compute_clock = |
15254 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15255 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15256 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 15257 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 15258 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15259 | dev_priv->display.get_initial_plane_config = |
15260 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
15261 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
15262 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
15263 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
15264 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
15265 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15266 | dev_priv->display.get_initial_plane_config = | |
15267 | i9xx_get_initial_plane_config; | |
15268 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
15269 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15270 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
15271 | } else if (IS_G4X(dev_priv)) { |
15272 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15273 | dev_priv->display.get_initial_plane_config = | |
15274 | i9xx_get_initial_plane_config; | |
15275 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
15276 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15277 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
15278 | } else if (IS_PINEVIEW(dev_priv)) { |
15279 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15280 | dev_priv->display.get_initial_plane_config = | |
15281 | i9xx_get_initial_plane_config; | |
15282 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
15283 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15284 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 15285 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 15286 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15287 | dev_priv->display.get_initial_plane_config = |
15288 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15289 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
15290 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
15291 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
15292 | } else { |
15293 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15294 | dev_priv->display.get_initial_plane_config = | |
15295 | i9xx_get_initial_plane_config; | |
15296 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
15297 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15298 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15299 | } |
e70236a8 | 15300 | |
e70236a8 | 15301 | /* Returns the core display clock speed */ |
88212941 | 15302 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
15303 | dev_priv->display.get_display_clock_speed = |
15304 | skylake_get_display_clock_speed; | |
88212941 | 15305 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
15306 | dev_priv->display.get_display_clock_speed = |
15307 | broxton_get_display_clock_speed; | |
88212941 | 15308 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
15309 | dev_priv->display.get_display_clock_speed = |
15310 | broadwell_get_display_clock_speed; | |
88212941 | 15311 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
15312 | dev_priv->display.get_display_clock_speed = |
15313 | haswell_get_display_clock_speed; | |
88212941 | 15314 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
15315 | dev_priv->display.get_display_clock_speed = |
15316 | valleyview_get_display_clock_speed; | |
88212941 | 15317 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
15318 | dev_priv->display.get_display_clock_speed = |
15319 | ilk_get_display_clock_speed; | |
88212941 ID |
15320 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
15321 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
15322 | dev_priv->display.get_display_clock_speed = |
15323 | i945_get_display_clock_speed; | |
88212941 | 15324 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
15325 | dev_priv->display.get_display_clock_speed = |
15326 | gm45_get_display_clock_speed; | |
88212941 | 15327 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
15328 | dev_priv->display.get_display_clock_speed = |
15329 | i965gm_get_display_clock_speed; | |
88212941 | 15330 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
15331 | dev_priv->display.get_display_clock_speed = |
15332 | pnv_get_display_clock_speed; | |
88212941 | 15333 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
15334 | dev_priv->display.get_display_clock_speed = |
15335 | g33_get_display_clock_speed; | |
88212941 | 15336 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
15337 | dev_priv->display.get_display_clock_speed = |
15338 | i915_get_display_clock_speed; | |
88212941 | 15339 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
15340 | dev_priv->display.get_display_clock_speed = |
15341 | i9xx_misc_get_display_clock_speed; | |
88212941 | 15342 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
15343 | dev_priv->display.get_display_clock_speed = |
15344 | i915gm_get_display_clock_speed; | |
88212941 | 15345 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
15346 | dev_priv->display.get_display_clock_speed = |
15347 | i865_get_display_clock_speed; | |
88212941 | 15348 | else if (IS_I85X(dev_priv)) |
e70236a8 | 15349 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15350 | i85x_get_display_clock_speed; |
623e01e5 | 15351 | else { /* 830 */ |
88212941 | 15352 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
15353 | dev_priv->display.get_display_clock_speed = |
15354 | i830_get_display_clock_speed; | |
623e01e5 | 15355 | } |
e70236a8 | 15356 | |
88212941 | 15357 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 15358 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 15359 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 15360 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 15361 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
15362 | /* FIXME: detect B0+ stepping and use auto training */ |
15363 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 15364 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 15365 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
15366 | } |
15367 | ||
15368 | if (IS_BROADWELL(dev_priv)) { | |
15369 | dev_priv->display.modeset_commit_cdclk = | |
15370 | broadwell_modeset_commit_cdclk; | |
15371 | dev_priv->display.modeset_calc_cdclk = | |
15372 | broadwell_modeset_calc_cdclk; | |
88212941 | 15373 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
15374 | dev_priv->display.modeset_commit_cdclk = |
15375 | valleyview_modeset_commit_cdclk; | |
15376 | dev_priv->display.modeset_calc_cdclk = | |
15377 | valleyview_modeset_calc_cdclk; | |
88212941 | 15378 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed | 15379 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 15380 | bxt_modeset_commit_cdclk; |
27c329ed | 15381 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 15382 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
15383 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
15384 | dev_priv->display.modeset_commit_cdclk = | |
15385 | skl_modeset_commit_cdclk; | |
15386 | dev_priv->display.modeset_calc_cdclk = | |
15387 | skl_modeset_calc_cdclk; | |
e70236a8 | 15388 | } |
5a21b665 DV |
15389 | |
15390 | switch (INTEL_INFO(dev_priv)->gen) { | |
15391 | case 2: | |
15392 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15393 | break; | |
15394 | ||
15395 | case 3: | |
15396 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15397 | break; | |
15398 | ||
15399 | case 4: | |
15400 | case 5: | |
15401 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15402 | break; | |
15403 | ||
15404 | case 6: | |
15405 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15406 | break; | |
15407 | case 7: | |
15408 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
15409 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
15410 | break; | |
15411 | case 9: | |
15412 | /* Drop through - unsupported since execlist only. */ | |
15413 | default: | |
15414 | /* Default just returns -ENODEV to indicate unsupported */ | |
15415 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
15416 | } | |
e70236a8 JB |
15417 | } |
15418 | ||
b690e96c JB |
15419 | /* |
15420 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15421 | * resume, or other times. This quirk makes sure that's the case for | |
15422 | * affected systems. | |
15423 | */ | |
0206e353 | 15424 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 15425 | { |
fac5e23e | 15426 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
15427 | |
15428 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15429 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15430 | } |
15431 | ||
b6b5d049 VS |
15432 | static void quirk_pipeb_force(struct drm_device *dev) |
15433 | { | |
fac5e23e | 15434 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
15435 | |
15436 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15437 | DRM_INFO("applying pipe b force quirk\n"); | |
15438 | } | |
15439 | ||
435793df KP |
15440 | /* |
15441 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15442 | */ | |
15443 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15444 | { | |
fac5e23e | 15445 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 15446 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 15447 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15448 | } |
15449 | ||
4dca20ef | 15450 | /* |
5a15ab5b CE |
15451 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15452 | * brightness value | |
4dca20ef CE |
15453 | */ |
15454 | static void quirk_invert_brightness(struct drm_device *dev) | |
15455 | { | |
fac5e23e | 15456 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 15457 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 15458 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15459 | } |
15460 | ||
9c72cc6f SD |
15461 | /* Some VBT's incorrectly indicate no backlight is present */ |
15462 | static void quirk_backlight_present(struct drm_device *dev) | |
15463 | { | |
fac5e23e | 15464 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
15465 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
15466 | DRM_INFO("applying backlight present quirk\n"); | |
15467 | } | |
15468 | ||
b690e96c JB |
15469 | struct intel_quirk { |
15470 | int device; | |
15471 | int subsystem_vendor; | |
15472 | int subsystem_device; | |
15473 | void (*hook)(struct drm_device *dev); | |
15474 | }; | |
15475 | ||
5f85f176 EE |
15476 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15477 | struct intel_dmi_quirk { | |
15478 | void (*hook)(struct drm_device *dev); | |
15479 | const struct dmi_system_id (*dmi_id_list)[]; | |
15480 | }; | |
15481 | ||
15482 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15483 | { | |
15484 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15485 | return 1; | |
15486 | } | |
15487 | ||
15488 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15489 | { | |
15490 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15491 | { | |
15492 | .callback = intel_dmi_reverse_brightness, | |
15493 | .ident = "NCR Corporation", | |
15494 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15495 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15496 | }, | |
15497 | }, | |
15498 | { } /* terminating entry */ | |
15499 | }, | |
15500 | .hook = quirk_invert_brightness, | |
15501 | }, | |
15502 | }; | |
15503 | ||
c43b5634 | 15504 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15505 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15506 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15507 | ||
b690e96c JB |
15508 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15509 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15510 | ||
5f080c0f VS |
15511 | /* 830 needs to leave pipe A & dpll A up */ |
15512 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15513 | ||
b6b5d049 VS |
15514 | /* 830 needs to leave pipe B & dpll B up */ |
15515 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15516 | ||
435793df KP |
15517 | /* Lenovo U160 cannot use SSC on LVDS */ |
15518 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15519 | |
15520 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15521 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15522 | |
be505f64 AH |
15523 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15524 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15525 | ||
15526 | /* Acer/eMachines G725 */ | |
15527 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15528 | ||
15529 | /* Acer/eMachines e725 */ | |
15530 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15531 | ||
15532 | /* Acer/Packard Bell NCL20 */ | |
15533 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15534 | ||
15535 | /* Acer Aspire 4736Z */ | |
15536 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15537 | |
15538 | /* Acer Aspire 5336 */ | |
15539 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15540 | |
15541 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15542 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15543 | |
dfb3d47b SD |
15544 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15545 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15546 | ||
b2a9601c | 15547 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15548 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15549 | ||
1b9448b0 JN |
15550 | /* Apple Macbook 4,1 */ |
15551 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15552 | ||
d4967d8c SD |
15553 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15554 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15555 | |
15556 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15557 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15558 | |
15559 | /* Dell Chromebook 11 */ | |
15560 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15561 | |
15562 | /* Dell Chromebook 11 (2015 version) */ | |
15563 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15564 | }; |
15565 | ||
15566 | static void intel_init_quirks(struct drm_device *dev) | |
15567 | { | |
15568 | struct pci_dev *d = dev->pdev; | |
15569 | int i; | |
15570 | ||
15571 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15572 | struct intel_quirk *q = &intel_quirks[i]; | |
15573 | ||
15574 | if (d->device == q->device && | |
15575 | (d->subsystem_vendor == q->subsystem_vendor || | |
15576 | q->subsystem_vendor == PCI_ANY_ID) && | |
15577 | (d->subsystem_device == q->subsystem_device || | |
15578 | q->subsystem_device == PCI_ANY_ID)) | |
15579 | q->hook(dev); | |
15580 | } | |
5f85f176 EE |
15581 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15582 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15583 | intel_dmi_quirks[i].hook(dev); | |
15584 | } | |
b690e96c JB |
15585 | } |
15586 | ||
9cce37f4 JB |
15587 | /* Disable the VGA plane that we never use */ |
15588 | static void i915_disable_vga(struct drm_device *dev) | |
15589 | { | |
fac5e23e | 15590 | struct drm_i915_private *dev_priv = to_i915(dev); |
9cce37f4 | 15591 | u8 sr1; |
f0f59a00 | 15592 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15593 | |
2b37c616 | 15594 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15595 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15596 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15597 | sr1 = inb(VGA_SR_DATA); |
15598 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15599 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15600 | udelay(300); | |
15601 | ||
01f5a626 | 15602 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15603 | POSTING_READ(vga_reg); |
15604 | } | |
15605 | ||
f817586c DV |
15606 | void intel_modeset_init_hw(struct drm_device *dev) |
15607 | { | |
fac5e23e | 15608 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 15609 | |
b6283055 | 15610 | intel_update_cdclk(dev); |
1a617b77 ML |
15611 | |
15612 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15613 | ||
f817586c | 15614 | intel_init_clock_gating(dev); |
f817586c DV |
15615 | } |
15616 | ||
d93c0372 MR |
15617 | /* |
15618 | * Calculate what we think the watermarks should be for the state we've read | |
15619 | * out of the hardware and then immediately program those watermarks so that | |
15620 | * we ensure the hardware settings match our internal state. | |
15621 | * | |
15622 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15623 | * current state (which was constructed during hardware readout) and running it | |
15624 | * through the atomic check code to calculate new watermark values in the | |
15625 | * state object. | |
15626 | */ | |
15627 | static void sanitize_watermarks(struct drm_device *dev) | |
15628 | { | |
15629 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15630 | struct drm_atomic_state *state; | |
15631 | struct drm_crtc *crtc; | |
15632 | struct drm_crtc_state *cstate; | |
15633 | struct drm_modeset_acquire_ctx ctx; | |
15634 | int ret; | |
15635 | int i; | |
15636 | ||
15637 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15638 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15639 | return; |
15640 | ||
15641 | /* | |
15642 | * We need to hold connection_mutex before calling duplicate_state so | |
15643 | * that the connector loop is protected. | |
15644 | */ | |
15645 | drm_modeset_acquire_init(&ctx, 0); | |
15646 | retry: | |
0cd1262d | 15647 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15648 | if (ret == -EDEADLK) { |
15649 | drm_modeset_backoff(&ctx); | |
15650 | goto retry; | |
15651 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15652 | goto fail; |
d93c0372 MR |
15653 | } |
15654 | ||
15655 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15656 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15657 | goto fail; |
d93c0372 | 15658 | |
ed4a6a7c MR |
15659 | /* |
15660 | * Hardware readout is the only time we don't want to calculate | |
15661 | * intermediate watermarks (since we don't trust the current | |
15662 | * watermarks). | |
15663 | */ | |
15664 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15665 | ||
d93c0372 MR |
15666 | ret = intel_atomic_check(dev, state); |
15667 | if (ret) { | |
15668 | /* | |
15669 | * If we fail here, it means that the hardware appears to be | |
15670 | * programmed in a way that shouldn't be possible, given our | |
15671 | * understanding of watermark requirements. This might mean a | |
15672 | * mistake in the hardware readout code or a mistake in the | |
15673 | * watermark calculations for a given platform. Raise a WARN | |
15674 | * so that this is noticeable. | |
15675 | * | |
15676 | * If this actually happens, we'll have to just leave the | |
15677 | * BIOS-programmed watermarks untouched and hope for the best. | |
15678 | */ | |
15679 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15680 | goto fail; |
d93c0372 MR |
15681 | } |
15682 | ||
15683 | /* Write calculated watermark values back */ | |
d93c0372 MR |
15684 | for_each_crtc_in_state(state, crtc, cstate, i) { |
15685 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15686 | ||
ed4a6a7c MR |
15687 | cs->wm.need_postvbl_update = true; |
15688 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15689 | } |
15690 | ||
15691 | drm_atomic_state_free(state); | |
0cd1262d | 15692 | fail: |
d93c0372 MR |
15693 | drm_modeset_drop_locks(&ctx); |
15694 | drm_modeset_acquire_fini(&ctx); | |
15695 | } | |
15696 | ||
79e53945 JB |
15697 | void intel_modeset_init(struct drm_device *dev) |
15698 | { | |
72e96d64 JL |
15699 | struct drm_i915_private *dev_priv = to_i915(dev); |
15700 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1fe47785 | 15701 | int sprite, ret; |
8cc87b75 | 15702 | enum pipe pipe; |
46f297fb | 15703 | struct intel_crtc *crtc; |
79e53945 JB |
15704 | |
15705 | drm_mode_config_init(dev); | |
15706 | ||
15707 | dev->mode_config.min_width = 0; | |
15708 | dev->mode_config.min_height = 0; | |
15709 | ||
019d96cb DA |
15710 | dev->mode_config.preferred_depth = 24; |
15711 | dev->mode_config.prefer_shadow = 1; | |
15712 | ||
25bab385 TU |
15713 | dev->mode_config.allow_fb_modifiers = true; |
15714 | ||
e6ecefaa | 15715 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15716 | |
b690e96c JB |
15717 | intel_init_quirks(dev); |
15718 | ||
1fa61106 ED |
15719 | intel_init_pm(dev); |
15720 | ||
e3c74757 BW |
15721 | if (INTEL_INFO(dev)->num_pipes == 0) |
15722 | return; | |
15723 | ||
69f92f67 LW |
15724 | /* |
15725 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15726 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15727 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15728 | * indicates as much. | |
15729 | */ | |
15730 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15731 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15732 | DREF_SSC1_ENABLE); | |
15733 | ||
15734 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15735 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15736 | bios_lvds_use_ssc ? "en" : "dis", | |
15737 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15738 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15739 | } | |
15740 | } | |
15741 | ||
a6c45cf0 CW |
15742 | if (IS_GEN2(dev)) { |
15743 | dev->mode_config.max_width = 2048; | |
15744 | dev->mode_config.max_height = 2048; | |
15745 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15746 | dev->mode_config.max_width = 4096; |
15747 | dev->mode_config.max_height = 4096; | |
79e53945 | 15748 | } else { |
a6c45cf0 CW |
15749 | dev->mode_config.max_width = 8192; |
15750 | dev->mode_config.max_height = 8192; | |
79e53945 | 15751 | } |
068be561 | 15752 | |
dc41c154 VS |
15753 | if (IS_845G(dev) || IS_I865G(dev)) { |
15754 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15755 | dev->mode_config.cursor_height = 1023; | |
15756 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15757 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15758 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15759 | } else { | |
15760 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15761 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15762 | } | |
15763 | ||
72e96d64 | 15764 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 15765 | |
28c97730 | 15766 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15767 | INTEL_INFO(dev)->num_pipes, |
15768 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15769 | |
055e393f | 15770 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15771 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15772 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15773 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15774 | if (ret) |
06da8da2 | 15775 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15776 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15777 | } |
79e53945 JB |
15778 | } |
15779 | ||
bfa7df01 VS |
15780 | intel_update_czclk(dev_priv); |
15781 | intel_update_cdclk(dev); | |
15782 | ||
e72f9fbf | 15783 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15784 | |
b2045352 VS |
15785 | if (dev_priv->max_cdclk_freq == 0) |
15786 | intel_update_max_cdclk(dev); | |
15787 | ||
9cce37f4 JB |
15788 | /* Just disable it once at startup */ |
15789 | i915_disable_vga(dev); | |
79e53945 | 15790 | intel_setup_outputs(dev); |
11be49eb | 15791 | |
6e9f798d | 15792 | drm_modeset_lock_all(dev); |
043e9bda | 15793 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15794 | drm_modeset_unlock_all(dev); |
46f297fb | 15795 | |
d3fcc808 | 15796 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15797 | struct intel_initial_plane_config plane_config = {}; |
15798 | ||
46f297fb JB |
15799 | if (!crtc->active) |
15800 | continue; | |
15801 | ||
46f297fb | 15802 | /* |
46f297fb JB |
15803 | * Note that reserving the BIOS fb up front prevents us |
15804 | * from stuffing other stolen allocations like the ring | |
15805 | * on top. This prevents some ugliness at boot time, and | |
15806 | * can even allow for smooth boot transitions if the BIOS | |
15807 | * fb is large enough for the active pipe configuration. | |
15808 | */ | |
eeebeac5 ML |
15809 | dev_priv->display.get_initial_plane_config(crtc, |
15810 | &plane_config); | |
15811 | ||
15812 | /* | |
15813 | * If the fb is shared between multiple heads, we'll | |
15814 | * just get the first one. | |
15815 | */ | |
15816 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15817 | } |
d93c0372 MR |
15818 | |
15819 | /* | |
15820 | * Make sure hardware watermarks really match the state we read out. | |
15821 | * Note that we need to do this after reconstructing the BIOS fb's | |
15822 | * since the watermark calculation done here will use pstate->fb. | |
15823 | */ | |
15824 | sanitize_watermarks(dev); | |
2c7111db CW |
15825 | } |
15826 | ||
7fad798e DV |
15827 | static void intel_enable_pipe_a(struct drm_device *dev) |
15828 | { | |
15829 | struct intel_connector *connector; | |
15830 | struct drm_connector *crt = NULL; | |
15831 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15832 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15833 | |
15834 | /* We can't just switch on the pipe A, we need to set things up with a | |
15835 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15836 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15837 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15838 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15839 | crt = &connector->base; | |
15840 | break; | |
15841 | } | |
15842 | } | |
15843 | ||
15844 | if (!crt) | |
15845 | return; | |
15846 | ||
208bf9fd | 15847 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15848 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15849 | } |
15850 | ||
fa555837 DV |
15851 | static bool |
15852 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15853 | { | |
7eb552ae | 15854 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 15855 | struct drm_i915_private *dev_priv = to_i915(dev); |
649636ef | 15856 | u32 val; |
fa555837 | 15857 | |
7eb552ae | 15858 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15859 | return true; |
15860 | ||
649636ef | 15861 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15862 | |
15863 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15864 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15865 | return false; | |
15866 | ||
15867 | return true; | |
15868 | } | |
15869 | ||
02e93c35 VS |
15870 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15871 | { | |
15872 | struct drm_device *dev = crtc->base.dev; | |
15873 | struct intel_encoder *encoder; | |
15874 | ||
15875 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15876 | return true; | |
15877 | ||
15878 | return false; | |
15879 | } | |
15880 | ||
dd756198 VS |
15881 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15882 | { | |
15883 | struct drm_device *dev = encoder->base.dev; | |
15884 | struct intel_connector *connector; | |
15885 | ||
15886 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15887 | return true; | |
15888 | ||
15889 | return false; | |
15890 | } | |
15891 | ||
a168f5b3 VS |
15892 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
15893 | enum transcoder pch_transcoder) | |
15894 | { | |
15895 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
15896 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
15897 | } | |
15898 | ||
24929352 DV |
15899 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15900 | { | |
15901 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 15902 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 15903 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15904 | |
24929352 | 15905 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15906 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15907 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15908 | ||
15909 | I915_WRITE(reg, | |
15910 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15911 | } | |
24929352 | 15912 | |
d3eaf884 | 15913 | /* restore vblank interrupts to correct state */ |
9625604c | 15914 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15915 | if (crtc->active) { |
f9cd7b88 VS |
15916 | struct intel_plane *plane; |
15917 | ||
9625604c | 15918 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15919 | |
15920 | /* Disable everything but the primary plane */ | |
15921 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15922 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15923 | continue; | |
15924 | ||
15925 | plane->disable_plane(&plane->base, &crtc->base); | |
15926 | } | |
9625604c | 15927 | } |
d3eaf884 | 15928 | |
24929352 | 15929 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15930 | * disable the crtc (and hence change the state) if it is wrong. Note |
15931 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15932 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15933 | bool plane; |
15934 | ||
78108b7c VS |
15935 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
15936 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
15937 | |
15938 | /* Pipe has the wrong plane attached and the plane is active. | |
15939 | * Temporarily change the plane mapping and disable everything | |
15940 | * ... */ | |
15941 | plane = crtc->plane; | |
b70709a6 | 15942 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15943 | crtc->plane = !plane; |
b17d48e2 | 15944 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15945 | crtc->plane = plane; |
24929352 | 15946 | } |
24929352 | 15947 | |
7fad798e DV |
15948 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15949 | crtc->pipe == PIPE_A && !crtc->active) { | |
15950 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15951 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15952 | * call below we restore the pipe to the right state, but leave | |
15953 | * the required bits on. */ | |
15954 | intel_enable_pipe_a(dev); | |
15955 | } | |
15956 | ||
24929352 DV |
15957 | /* Adjust the state of the output pipe according to whether we |
15958 | * have active connectors/encoders. */ | |
842e0307 | 15959 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15960 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15961 | |
a3ed6aad | 15962 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15963 | /* |
15964 | * We start out with underrun reporting disabled to avoid races. | |
15965 | * For correct bookkeeping mark this on active crtcs. | |
15966 | * | |
c5ab3bc0 DV |
15967 | * Also on gmch platforms we dont have any hardware bits to |
15968 | * disable the underrun reporting. Which means we need to start | |
15969 | * out with underrun reporting disabled also on inactive pipes, | |
15970 | * since otherwise we'll complain about the garbage we read when | |
15971 | * e.g. coming up after runtime pm. | |
15972 | * | |
4cc31489 DV |
15973 | * No protection against concurrent access is required - at |
15974 | * worst a fifo underrun happens which also sets this to false. | |
15975 | */ | |
15976 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
15977 | /* |
15978 | * We track the PCH trancoder underrun reporting state | |
15979 | * within the crtc. With crtc for pipe A housing the underrun | |
15980 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
15981 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
15982 | * and marking underrun reporting as disabled for the non-existing | |
15983 | * PCH transcoders B and C would prevent enabling the south | |
15984 | * error interrupt (see cpt_can_enable_serr_int()). | |
15985 | */ | |
15986 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
15987 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 15988 | } |
24929352 DV |
15989 | } |
15990 | ||
15991 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15992 | { | |
15993 | struct intel_connector *connector; | |
15994 | struct drm_device *dev = encoder->base.dev; | |
15995 | ||
15996 | /* We need to check both for a crtc link (meaning that the | |
15997 | * encoder is active and trying to read from a pipe) and the | |
15998 | * pipe itself being active. */ | |
15999 | bool has_active_crtc = encoder->base.crtc && | |
16000 | to_intel_crtc(encoder->base.crtc)->active; | |
16001 | ||
dd756198 | 16002 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
16003 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
16004 | encoder->base.base.id, | |
8e329a03 | 16005 | encoder->base.name); |
24929352 DV |
16006 | |
16007 | /* Connector is active, but has no active pipe. This is | |
16008 | * fallout from our resume register restoring. Disable | |
16009 | * the encoder manually again. */ | |
16010 | if (encoder->base.crtc) { | |
16011 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
16012 | encoder->base.base.id, | |
8e329a03 | 16013 | encoder->base.name); |
24929352 | 16014 | encoder->disable(encoder); |
a62d1497 VS |
16015 | if (encoder->post_disable) |
16016 | encoder->post_disable(encoder); | |
24929352 | 16017 | } |
7f1950fb | 16018 | encoder->base.crtc = NULL; |
24929352 DV |
16019 | |
16020 | /* Inconsistent output/port/pipe state happens presumably due to | |
16021 | * a bug in one of the get_hw_state functions. Or someplace else | |
16022 | * in our code, like the register restore mess on resume. Clamp | |
16023 | * things to off as a safer default. */ | |
3a3371ff | 16024 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16025 | if (connector->encoder != encoder) |
16026 | continue; | |
7f1950fb EE |
16027 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
16028 | connector->base.encoder = NULL; | |
24929352 DV |
16029 | } |
16030 | } | |
16031 | /* Enabled encoders without active connectors will be fixed in | |
16032 | * the crtc fixup. */ | |
16033 | } | |
16034 | ||
04098753 | 16035 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f | 16036 | { |
fac5e23e | 16037 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 16038 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 16039 | |
04098753 ID |
16040 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
16041 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
16042 | i915_disable_vga(dev); | |
16043 | } | |
16044 | } | |
16045 | ||
16046 | void i915_redisable_vga(struct drm_device *dev) | |
16047 | { | |
fac5e23e | 16048 | struct drm_i915_private *dev_priv = to_i915(dev); |
04098753 | 16049 | |
8dc8a27c PZ |
16050 | /* This function can be called both from intel_modeset_setup_hw_state or |
16051 | * at a very early point in our resume sequence, where the power well | |
16052 | * structures are not yet restored. Since this function is at a very | |
16053 | * paranoid "someone might have enabled VGA while we were not looking" | |
16054 | * level, just check if the power well is enabled instead of trying to | |
16055 | * follow the "don't touch the power well if we don't need it" policy | |
16056 | * the rest of the driver uses. */ | |
6392f847 | 16057 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
16058 | return; |
16059 | ||
04098753 | 16060 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
16061 | |
16062 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
16063 | } |
16064 | ||
f9cd7b88 | 16065 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 16066 | { |
f9cd7b88 | 16067 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 16068 | |
f9cd7b88 | 16069 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
16070 | } |
16071 | ||
f9cd7b88 VS |
16072 | /* FIXME read out full plane state for all planes */ |
16073 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 16074 | { |
b26d3ea3 | 16075 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 16076 | struct intel_plane_state *plane_state = |
b26d3ea3 | 16077 | to_intel_plane_state(primary->state); |
d032ffa0 | 16078 | |
19b8d387 | 16079 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
16080 | primary_get_hw_state(to_intel_plane(primary)); |
16081 | ||
16082 | if (plane_state->visible) | |
16083 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
16084 | } |
16085 | ||
30e984df | 16086 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 16087 | { |
fac5e23e | 16088 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 16089 | enum pipe pipe; |
24929352 DV |
16090 | struct intel_crtc *crtc; |
16091 | struct intel_encoder *encoder; | |
16092 | struct intel_connector *connector; | |
5358901f | 16093 | int i; |
24929352 | 16094 | |
565602d7 ML |
16095 | dev_priv->active_crtcs = 0; |
16096 | ||
d3fcc808 | 16097 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
16098 | struct intel_crtc_state *crtc_state = crtc->config; |
16099 | int pixclk = 0; | |
3b117c8f | 16100 | |
ec2dc6a0 | 16101 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
16102 | memset(crtc_state, 0, sizeof(*crtc_state)); |
16103 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 16104 | |
565602d7 ML |
16105 | crtc_state->base.active = crtc_state->base.enable = |
16106 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
16107 | ||
16108 | crtc->base.enabled = crtc_state->base.enable; | |
16109 | crtc->active = crtc_state->base.active; | |
16110 | ||
16111 | if (crtc_state->base.active) { | |
16112 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
16113 | ||
c89e39f3 | 16114 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 16115 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 16116 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
16117 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
16118 | else | |
16119 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
16120 | |
16121 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
16122 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
16123 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
16124 | } |
16125 | ||
16126 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 16127 | |
f9cd7b88 | 16128 | readout_plane_state(crtc); |
24929352 | 16129 | |
78108b7c VS |
16130 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
16131 | crtc->base.base.id, crtc->base.name, | |
24929352 DV |
16132 | crtc->active ? "enabled" : "disabled"); |
16133 | } | |
16134 | ||
5358901f DV |
16135 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16136 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16137 | ||
2edd6443 ACO |
16138 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16139 | &pll->config.hw_state); | |
3e369b76 | 16140 | pll->config.crtc_mask = 0; |
d3fcc808 | 16141 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16142 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16143 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16144 | } |
2dd66ebd | 16145 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16146 | |
1e6f2ddc | 16147 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16148 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16149 | } |
16150 | ||
b2784e15 | 16151 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16152 | pipe = 0; |
16153 | ||
16154 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
16155 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16156 | encoder->base.crtc = &crtc->base; | |
253c84c8 | 16157 | crtc->config->output_types |= 1 << encoder->type; |
6e3c9717 | 16158 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16159 | } else { |
16160 | encoder->base.crtc = NULL; | |
16161 | } | |
16162 | ||
6f2bcceb | 16163 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 16164 | encoder->base.base.id, |
8e329a03 | 16165 | encoder->base.name, |
24929352 | 16166 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 16167 | pipe_name(pipe)); |
24929352 DV |
16168 | } |
16169 | ||
3a3371ff | 16170 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16171 | if (connector->get_hw_state(connector)) { |
16172 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16173 | |
16174 | encoder = connector->encoder; | |
16175 | connector->base.encoder = &encoder->base; | |
16176 | ||
16177 | if (encoder->base.crtc && | |
16178 | encoder->base.crtc->state->active) { | |
16179 | /* | |
16180 | * This has to be done during hardware readout | |
16181 | * because anything calling .crtc_disable may | |
16182 | * rely on the connector_mask being accurate. | |
16183 | */ | |
16184 | encoder->base.crtc->state->connector_mask |= | |
16185 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16186 | encoder->base.crtc->state->encoder_mask |= |
16187 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16188 | } |
16189 | ||
24929352 DV |
16190 | } else { |
16191 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16192 | connector->base.encoder = NULL; | |
16193 | } | |
16194 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
16195 | connector->base.base.id, | |
c23cc417 | 16196 | connector->base.name, |
24929352 DV |
16197 | connector->base.encoder ? "enabled" : "disabled"); |
16198 | } | |
7f4c6284 VS |
16199 | |
16200 | for_each_intel_crtc(dev, crtc) { | |
16201 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16202 | ||
16203 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16204 | if (crtc->base.state->active) { | |
16205 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16206 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16207 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16208 | ||
16209 | /* | |
16210 | * The initial mode needs to be set in order to keep | |
16211 | * the atomic core happy. It wants a valid mode if the | |
16212 | * crtc's enabled, so we do the above call. | |
16213 | * | |
16214 | * At this point some state updated by the connectors | |
16215 | * in their ->detect() callback has not run yet, so | |
16216 | * no recalculation can be done yet. | |
16217 | * | |
16218 | * Even if we could do a recalculation and modeset | |
16219 | * right now it would cause a double modeset if | |
16220 | * fbdev or userspace chooses a different initial mode. | |
16221 | * | |
16222 | * If that happens, someone indicated they wanted a | |
16223 | * mode change, which means it's safe to do a full | |
16224 | * recalculation. | |
16225 | */ | |
16226 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16227 | |
16228 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16229 | update_scanline_offset(crtc); | |
7f4c6284 | 16230 | } |
e3b247da VS |
16231 | |
16232 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16233 | } |
30e984df DV |
16234 | } |
16235 | ||
043e9bda ML |
16236 | /* Scan out the current hw modeset state, |
16237 | * and sanitizes it to the current state | |
16238 | */ | |
16239 | static void | |
16240 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 16241 | { |
fac5e23e | 16242 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 16243 | enum pipe pipe; |
30e984df DV |
16244 | struct intel_crtc *crtc; |
16245 | struct intel_encoder *encoder; | |
35c95375 | 16246 | int i; |
30e984df DV |
16247 | |
16248 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16249 | |
16250 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16251 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16252 | intel_sanitize_encoder(encoder); |
16253 | } | |
16254 | ||
055e393f | 16255 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
16256 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16257 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
16258 | intel_dump_pipe_config(crtc, crtc->config, |
16259 | "[setup_hw_state]"); | |
24929352 | 16260 | } |
9a935856 | 16261 | |
d29b2f9d ACO |
16262 | intel_modeset_update_connector_atomic_state(dev); |
16263 | ||
35c95375 DV |
16264 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16265 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16266 | ||
2dd66ebd | 16267 | if (!pll->on || pll->active_mask) |
35c95375 DV |
16268 | continue; |
16269 | ||
16270 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
16271 | ||
2edd6443 | 16272 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
16273 | pll->on = false; |
16274 | } | |
16275 | ||
666a4537 | 16276 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
16277 | vlv_wm_get_hw_state(dev); |
16278 | else if (IS_GEN9(dev)) | |
3078999f PB |
16279 | skl_wm_get_hw_state(dev); |
16280 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 16281 | ilk_wm_get_hw_state(dev); |
292b990e ML |
16282 | |
16283 | for_each_intel_crtc(dev, crtc) { | |
16284 | unsigned long put_domains; | |
16285 | ||
74bff5f9 | 16286 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
16287 | if (WARN_ON(put_domains)) |
16288 | modeset_put_power_domains(dev_priv, put_domains); | |
16289 | } | |
16290 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
16291 | |
16292 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 16293 | } |
7d0bc1ea | 16294 | |
043e9bda ML |
16295 | void intel_display_resume(struct drm_device *dev) |
16296 | { | |
e2c8b870 ML |
16297 | struct drm_i915_private *dev_priv = to_i915(dev); |
16298 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
16299 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 16300 | int ret; |
f30da187 | 16301 | |
e2c8b870 | 16302 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
16303 | if (state) |
16304 | state->acquire_ctx = &ctx; | |
043e9bda | 16305 | |
ea49c9ac ML |
16306 | /* |
16307 | * This is a cludge because with real atomic modeset mode_config.mutex | |
16308 | * won't be taken. Unfortunately some probed state like | |
16309 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
16310 | * it here for now. | |
16311 | */ | |
16312 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 16313 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 16314 | |
73974893 ML |
16315 | while (1) { |
16316 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
16317 | if (ret != -EDEADLK) | |
16318 | break; | |
043e9bda | 16319 | |
e2c8b870 | 16320 | drm_modeset_backoff(&ctx); |
e2c8b870 | 16321 | } |
043e9bda | 16322 | |
73974893 ML |
16323 | if (!ret) |
16324 | ret = __intel_display_resume(dev, state); | |
16325 | ||
e2c8b870 ML |
16326 | drm_modeset_drop_locks(&ctx); |
16327 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 16328 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 16329 | |
e2c8b870 ML |
16330 | if (ret) { |
16331 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16332 | drm_atomic_state_free(state); | |
16333 | } | |
2c7111db CW |
16334 | } |
16335 | ||
16336 | void intel_modeset_gem_init(struct drm_device *dev) | |
16337 | { | |
dc97997a | 16338 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 16339 | struct drm_crtc *c; |
2ff8fde1 | 16340 | struct drm_i915_gem_object *obj; |
e0d6149b | 16341 | int ret; |
484b41dd | 16342 | |
dc97997a | 16343 | intel_init_gt_powersave(dev_priv); |
ae48434c | 16344 | |
1833b134 | 16345 | intel_modeset_init_hw(dev); |
02e792fb | 16346 | |
1ee8da6d | 16347 | intel_setup_overlay(dev_priv); |
484b41dd JB |
16348 | |
16349 | /* | |
16350 | * Make sure any fbs we allocated at startup are properly | |
16351 | * pinned & fenced. When we do the allocation it's too early | |
16352 | * for this. | |
16353 | */ | |
70e1e0ec | 16354 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16355 | obj = intel_fb_obj(c->primary->fb); |
16356 | if (obj == NULL) | |
484b41dd JB |
16357 | continue; |
16358 | ||
e0d6149b | 16359 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
16360 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
16361 | c->primary->state->rotation); | |
e0d6149b TU |
16362 | mutex_unlock(&dev->struct_mutex); |
16363 | if (ret) { | |
484b41dd JB |
16364 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16365 | to_intel_crtc(c)->pipe); | |
66e514c1 | 16366 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 16367 | c->primary->fb = NULL; |
36750f28 | 16368 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 16369 | update_state_fb(c->primary); |
36750f28 | 16370 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16371 | } |
16372 | } | |
1ebaa0b9 CW |
16373 | } |
16374 | ||
16375 | int intel_connector_register(struct drm_connector *connector) | |
16376 | { | |
16377 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
16378 | int ret; | |
16379 | ||
16380 | ret = intel_backlight_device_register(intel_connector); | |
16381 | if (ret) | |
16382 | goto err; | |
16383 | ||
16384 | return 0; | |
0962c3c9 | 16385 | |
1ebaa0b9 CW |
16386 | err: |
16387 | return ret; | |
79e53945 JB |
16388 | } |
16389 | ||
c191eca1 | 16390 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 16391 | { |
e63d87c0 | 16392 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 16393 | |
e63d87c0 | 16394 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 16395 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
16396 | } |
16397 | ||
79e53945 JB |
16398 | void intel_modeset_cleanup(struct drm_device *dev) |
16399 | { | |
fac5e23e | 16400 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 16401 | |
dc97997a | 16402 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 16403 | |
fd0c0642 DV |
16404 | /* |
16405 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16406 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16407 | * experience fancy races otherwise. |
16408 | */ | |
2aeb7d3a | 16409 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16410 | |
fd0c0642 DV |
16411 | /* |
16412 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16413 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16414 | */ | |
f87ea761 | 16415 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16416 | |
723bfd70 JB |
16417 | intel_unregister_dsm_handler(); |
16418 | ||
c937ab3e | 16419 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16420 | |
1630fe75 CW |
16421 | /* flush any delayed tasks or pending work */ |
16422 | flush_scheduled_work(); | |
16423 | ||
79e53945 | 16424 | drm_mode_config_cleanup(dev); |
4d7bb011 | 16425 | |
1ee8da6d | 16426 | intel_cleanup_overlay(dev_priv); |
ae48434c | 16427 | |
dc97997a | 16428 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
16429 | |
16430 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16431 | } |
16432 | ||
df0e9248 CW |
16433 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16434 | struct intel_encoder *encoder) | |
16435 | { | |
16436 | connector->encoder = encoder; | |
16437 | drm_mode_connector_attach_encoder(&connector->base, | |
16438 | &encoder->base); | |
79e53945 | 16439 | } |
28d52043 DA |
16440 | |
16441 | /* | |
16442 | * set vga decode state - true == enable VGA decode | |
16443 | */ | |
16444 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16445 | { | |
fac5e23e | 16446 | struct drm_i915_private *dev_priv = to_i915(dev); |
a885b3cc | 16447 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16448 | u16 gmch_ctrl; |
16449 | ||
75fa041d CW |
16450 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16451 | DRM_ERROR("failed to read control word\n"); | |
16452 | return -EIO; | |
16453 | } | |
16454 | ||
c0cc8a55 CW |
16455 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16456 | return 0; | |
16457 | ||
28d52043 DA |
16458 | if (state) |
16459 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16460 | else | |
16461 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16462 | |
16463 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16464 | DRM_ERROR("failed to write control word\n"); | |
16465 | return -EIO; | |
16466 | } | |
16467 | ||
28d52043 DA |
16468 | return 0; |
16469 | } | |
c4a1d9e4 | 16470 | |
c4a1d9e4 | 16471 | struct intel_display_error_state { |
ff57f1b0 PZ |
16472 | |
16473 | u32 power_well_driver; | |
16474 | ||
63b66e5b CW |
16475 | int num_transcoders; |
16476 | ||
c4a1d9e4 CW |
16477 | struct intel_cursor_error_state { |
16478 | u32 control; | |
16479 | u32 position; | |
16480 | u32 base; | |
16481 | u32 size; | |
52331309 | 16482 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16483 | |
16484 | struct intel_pipe_error_state { | |
ddf9c536 | 16485 | bool power_domain_on; |
c4a1d9e4 | 16486 | u32 source; |
f301b1e1 | 16487 | u32 stat; |
52331309 | 16488 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16489 | |
16490 | struct intel_plane_error_state { | |
16491 | u32 control; | |
16492 | u32 stride; | |
16493 | u32 size; | |
16494 | u32 pos; | |
16495 | u32 addr; | |
16496 | u32 surface; | |
16497 | u32 tile_offset; | |
52331309 | 16498 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16499 | |
16500 | struct intel_transcoder_error_state { | |
ddf9c536 | 16501 | bool power_domain_on; |
63b66e5b CW |
16502 | enum transcoder cpu_transcoder; |
16503 | ||
16504 | u32 conf; | |
16505 | ||
16506 | u32 htotal; | |
16507 | u32 hblank; | |
16508 | u32 hsync; | |
16509 | u32 vtotal; | |
16510 | u32 vblank; | |
16511 | u32 vsync; | |
16512 | } transcoder[4]; | |
c4a1d9e4 CW |
16513 | }; |
16514 | ||
16515 | struct intel_display_error_state * | |
c033666a | 16516 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 16517 | { |
c4a1d9e4 | 16518 | struct intel_display_error_state *error; |
63b66e5b CW |
16519 | int transcoders[] = { |
16520 | TRANSCODER_A, | |
16521 | TRANSCODER_B, | |
16522 | TRANSCODER_C, | |
16523 | TRANSCODER_EDP, | |
16524 | }; | |
c4a1d9e4 CW |
16525 | int i; |
16526 | ||
c033666a | 16527 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
16528 | return NULL; |
16529 | ||
9d1cb914 | 16530 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16531 | if (error == NULL) |
16532 | return NULL; | |
16533 | ||
c033666a | 16534 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
16535 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16536 | ||
055e393f | 16537 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16538 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16539 | __intel_display_power_is_enabled(dev_priv, |
16540 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16541 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16542 | continue; |
16543 | ||
5efb3e28 VS |
16544 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16545 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16546 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16547 | |
16548 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16549 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 16550 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 16551 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16552 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16553 | } | |
c033666a | 16554 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 16555 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 16556 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
16557 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
16558 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16559 | } | |
16560 | ||
c4a1d9e4 | 16561 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16562 | |
c033666a | 16563 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 16564 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16565 | } |
16566 | ||
4d1de975 | 16567 | /* Note: this does not include DSI transcoders. */ |
c033666a | 16568 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 16569 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
16570 | error->num_transcoders++; /* Account for eDP. */ |
16571 | ||
16572 | for (i = 0; i < error->num_transcoders; i++) { | |
16573 | enum transcoder cpu_transcoder = transcoders[i]; | |
16574 | ||
ddf9c536 | 16575 | error->transcoder[i].power_domain_on = |
f458ebbc | 16576 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16577 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16578 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16579 | continue; |
16580 | ||
63b66e5b CW |
16581 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16582 | ||
16583 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16584 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16585 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16586 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16587 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16588 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16589 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16590 | } |
16591 | ||
16592 | return error; | |
16593 | } | |
16594 | ||
edc3d884 MK |
16595 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16596 | ||
c4a1d9e4 | 16597 | void |
edc3d884 | 16598 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16599 | struct drm_device *dev, |
16600 | struct intel_display_error_state *error) | |
16601 | { | |
fac5e23e | 16602 | struct drm_i915_private *dev_priv = to_i915(dev); |
c4a1d9e4 CW |
16603 | int i; |
16604 | ||
63b66e5b CW |
16605 | if (!error) |
16606 | return; | |
16607 | ||
edc3d884 | 16608 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16609 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16610 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16611 | error->power_well_driver); |
055e393f | 16612 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16613 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16614 | err_printf(m, " Power: %s\n", |
87ad3212 | 16615 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16616 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16617 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16618 | |
16619 | err_printf(m, "Plane [%d]:\n", i); | |
16620 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16621 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16622 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16623 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16624 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16625 | } |
4b71a570 | 16626 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16627 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16628 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16629 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16630 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16631 | } |
16632 | ||
edc3d884 MK |
16633 | err_printf(m, "Cursor [%d]:\n", i); |
16634 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16635 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16636 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16637 | } |
63b66e5b CW |
16638 | |
16639 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16640 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16641 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16642 | err_printf(m, " Power: %s\n", |
87ad3212 | 16643 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16644 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16645 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16646 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16647 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16648 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16649 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16650 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16651 | } | |
c4a1d9e4 | 16652 | } |